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nickg/nvc | lib/ieee.08/std_logic_1164-body.vhdl | 1 | 59,404 | -- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Standard multivalue logic package
-- : (STD_LOGIC_1164 package body)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE model standards group (PAR 1164),
-- : Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines a standard for designers
-- : to use in describing the interconnection data types
-- : used in vhdl modeling.
-- :
-- Limitation: The logic system defined in this package may
-- : be insufficient for modeling switched transistors,
-- : since such a requirement is out of the scope of this
-- : effort. Furthermore, mathematics, primitives,
-- : timing standards, etc. are considered orthogonal
-- : issues as it relates to this package and are therefore
-- : beyond the scope of this effort.
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
package body std_logic_1164 is
-------------------------------------------------------------------
-- local types
-------------------------------------------------------------------
type stdlogic_1d is array (STD_ULOGIC) of STD_ULOGIC;
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
constant resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | X |
('U', 'X', '0', 'X', '0', '0', '0', '0', 'X'), -- | 0 |
('U', 'X', 'X', '1', '1', '1', '1', '1', 'X'), -- | 1 |
('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X'), -- | Z |
('U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X'), -- | W |
('U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X'), -- | L |
('U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X'), -- | H |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X') -- | - |
);
function resolved (s : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := 'Z'; -- weakest state default
begin
-- the test for a single driver is essential otherwise the
-- loop would return 'X' for a single driver of '-' and that
-- would conflict with the value of a single driver unresolved
-- signal.
if (s'length = 1) then return s(s'low);
else
for i in s'range loop
result := resolution_table(result, s(i));
end loop;
end if;
return result;
end function resolved;
-------------------------------------------------------------------
-- tables for logical operations
-------------------------------------------------------------------
-- truth table for "and" function
constant and_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
('U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U'), -- | U |
('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X'), -- | X |
('0', '0', '0', '0', '0', '0', '0', '0', '0'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | 1 |
('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X'), -- | Z |
('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X'), -- | W |
('0', '0', '0', '0', '0', '0', '0', '0', '0'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | H |
('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X') -- | - |
);
-- truth table for "or" function
constant or_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
('U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U'), -- | U |
('U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | 0 |
('1', '1', '1', '1', '1', '1', '1', '1', '1'), -- | 1 |
('U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X'), -- | Z |
('U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | L |
('1', '1', '1', '1', '1', '1', '1', '1', '1'), -- | H |
('U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X') -- | - |
);
-- truth table for "xor" function
constant xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | 0 |
('U', 'X', '1', '0', 'X', 'X', '1', '0', 'X'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | L |
('U', 'X', '1', '0', 'X', 'X', '1', '0', 'X'), -- | H |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X') -- | - |
);
-- truth table for "not" function
constant not_table : stdlogic_1d :=
-- -------------------------------------------------
-- | U X 0 1 Z W L H - |
-- -------------------------------------------------
('U', 'X', '1', '0', 'X', 'X', '1', '0', 'X');
-------------------------------------------------------------------
-- overloaded logical operators ( with optimizing hints )
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is
begin
return (and_table(l, r));
end function "and";
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is
begin
return (not_table (and_table(l, r)));
end function "nand";
function "or" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is
begin
return (or_table(l, r));
end function "or";
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is
begin
return (not_table (or_table(l, r)));
end function "nor";
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is
begin
return (xor_table(l, r));
end function "xor";
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is
begin
return not_table(xor_table(l, r));
end function "xnor";
function "not" (l : STD_ULOGIC) return UX01 is
begin
return (not_table(l));
end function "not";
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function "and" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""and"": "
& "arguments of overloaded 'and' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := and_table (lv(i), rv(i));
end loop;
end if;
return result;
end function "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function "nand" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""nand"": "
& "arguments of overloaded 'nand' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := not_table(and_table (lv(i), rv(i)));
end loop;
end if;
return result;
end function "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function "or" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""or"": "
& "arguments of overloaded 'or' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := or_table (lv(i), rv(i));
end loop;
end if;
return result;
end function "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function "nor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""nor"": "
& "arguments of overloaded 'nor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := not_table(or_table (lv(i), rv(i)));
end loop;
end if;
return result;
end function "nor";
---------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function "xor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""xor"": "
& "arguments of overloaded 'xor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := xor_table (lv(i), rv(i));
end loop;
end if;
return result;
end function "xor";
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function "xnor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""xnor"": "
& "arguments of overloaded 'xnor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := not_table(xor_table (lv(i), rv(i)));
end loop;
end if;
return result;
end function "xnor";
-------------------------------------------------------------------
-- not
-------------------------------------------------------------------
function "not" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => 'X');
begin
for i in result'range loop
result(i) := not_table(lv(i));
end loop;
return result;
end function "not";
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := and_table (lv(i), r);
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR
is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := and_table (l, rv(i));
end loop;
return result;
end function "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := not_table(and_table (lv(i), r));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR
is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := not_table(and_table (l, rv(i)));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := or_table (lv(i), r);
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR
is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := or_table (l, rv(i));
end loop;
return result;
end function "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := not_table(or_table (lv(i), r));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR
is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := not_table(or_table (l, rv(i)));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := xor_table (lv(i), r);
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR
is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := xor_table (l, rv(i));
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := not_table(xor_table (lv(i), r));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR
is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := not_table(xor_table (l, rv(i)));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '1';
begin
for i in l'reverse_range loop
result := and_table (l(i), result);
end loop;
return result;
end function "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '1';
begin
for i in l'reverse_range loop
result := and_table (l(i), result);
end loop;
return not_table(result);
end function "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := or_table (l(i), result);
end loop;
return result;
end function "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := or_table (l(i), result);
end loop;
return not_table(result);
end function "nor";
-------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := xor_table (l(i), result);
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := xor_table (l(i), result);
end loop;
return not_table(result);
end function "xnor";
-------------------------------------------------------------------
-- shift operators
-------------------------------------------------------------------
-------------------------------------------------------------------
-- sll
-------------------------------------------------------------------
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
-------------------------------------------------------------------
-- srl
-------------------------------------------------------------------
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
-------------------------------------------------------------------
-- rol
-------------------------------------------------------------------
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
-------------------------------------------------------------------
-- ror
-------------------------------------------------------------------
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-------------------------------------------------------------------
-- conversion tables
-------------------------------------------------------------------
type logic_x01_table is array (STD_ULOGIC'low to STD_ULOGIC'high) of X01;
type logic_x01z_table is array (STD_ULOGIC'low to STD_ULOGIC'high) of X01Z;
type logic_ux01_table is array (STD_ULOGIC'low to STD_ULOGIC'high) of UX01;
----------------------------------------------------------
-- table name : cvt_to_x01
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : x01 -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_x01 (input_signal) = '1' ) then ...
--
----------------------------------------------------------
constant cvt_to_x01 : logic_x01_table := (
'X', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'X', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
----------------------------------------------------------
-- table name : cvt_to_x01z
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : x01z -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_x01z (input_signal) = '1' ) then ...
--
----------------------------------------------------------
constant cvt_to_x01z : logic_x01z_table := (
'X', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'Z', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
----------------------------------------------------------
-- table name : cvt_to_ux01
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : ux01 -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_ux01 (input_signal) = '1' ) then ...
--
----------------------------------------------------------
constant cvt_to_ux01 : logic_ux01_table := (
'U', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'X', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
-------------------------------------------------------------------
-- conversion functions
-------------------------------------------------------------------
function To_bit (s : STD_ULOGIC; xmap : BIT := '0') return BIT is
begin
case s is
when '0' | 'L' => return ('0');
when '1' | 'H' => return ('1');
when others => return xmap;
end case;
end function To_bit;
--------------------------------------------------------------------
function To_bitvector (s : STD_ULOGIC_VECTOR; xmap : BIT := '0')
return BIT_VECTOR
is
alias sv : STD_ULOGIC_VECTOR (s'length-1 downto 0) is s;
variable result : BIT_VECTOR (s'length-1 downto 0);
begin
for i in result'range loop
case sv(i) is
when '0' | 'L' => result(i) := '0';
when '1' | 'H' => result(i) := '1';
when others => result(i) := xmap;
end case;
end loop;
return result;
end function To_bitvector;
--------------------------------------------------------------------
function To_StdULogic (b : BIT) return STD_ULOGIC is
begin
case b is
when '0' => return '0';
when '1' => return '1';
end case;
end function To_StdULogic;
--------------------------------------------------------------------
function To_StdLogicVector (b : BIT_VECTOR)
return STD_LOGIC_VECTOR
is
alias bv : BIT_VECTOR (b'length-1 downto 0) is b;
variable result : STD_LOGIC_VECTOR (b'length-1 downto 0);
begin
for i in result'range loop
case bv(i) is
when '0' => result(i) := '0';
when '1' => result(i) := '1';
end case;
end loop;
return result;
end function To_StdLogicVector;
--------------------------------------------------------------------
function To_StdLogicVector (s : STD_ULOGIC_VECTOR)
return STD_LOGIC_VECTOR
is
alias sv : STD_ULOGIC_VECTOR (s'length-1 downto 0) is s;
variable result : STD_LOGIC_VECTOR (s'length-1 downto 0);
begin
for i in result'range loop
result(i) := sv(i);
end loop;
return result;
end function To_StdLogicVector;
--------------------------------------------------------------------
function To_StdULogicVector (b : BIT_VECTOR)
return STD_ULOGIC_VECTOR
is
alias bv : BIT_VECTOR (b'length-1 downto 0) is b;
variable result : STD_ULOGIC_VECTOR (b'length-1 downto 0);
begin
for i in result'range loop
case bv(i) is
when '0' => result(i) := '0';
when '1' => result(i) := '1';
end case;
end loop;
return result;
end function To_StdULogicVector;
--------------------------------------------------------------------
function To_StdULogicVector (s : STD_LOGIC_VECTOR)
return STD_ULOGIC_VECTOR
is
alias sv : STD_LOGIC_VECTOR (s'length-1 downto 0) is s;
variable result : STD_ULOGIC_VECTOR (s'length-1 downto 0);
begin
for i in result'range loop
result(i) := sv(i);
end loop;
return result;
end function To_StdULogicVector;
-------------------------------------------------------------------
-- strength strippers and type convertors
-------------------------------------------------------------------
-- to_01
-------------------------------------------------------------------
function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR
is
variable RESULT : STD_ULOGIC_VECTOR(s'length-1 downto 0);
variable BAD_ELEMENT : BOOLEAN := false;
alias XS : STD_ULOGIC_VECTOR(s'length-1 downto 0) is s;
begin
for I in RESULT'range loop
case XS(I) is
when '0' | 'L' => RESULT(I) := '0';
when '1' | 'H' => RESULT(I) := '1';
when others => BAD_ELEMENT := true;
end case;
end loop;
if BAD_ELEMENT then
for I in RESULT'range loop
RESULT(I) := xmap; -- standard fixup
end loop;
end if;
return RESULT;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0') return STD_ULOGIC is
begin
case s is
when '0' | 'L' => RETURN '0';
when '1' | 'H' => RETURN '1';
when others => return xmap;
end case;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR
is
variable RESULT : STD_ULOGIC_VECTOR(s'length-1 downto 0);
alias XS : BIT_VECTOR(s'length-1 downto 0) is s;
begin
for I in RESULT'range loop
case XS(I) is
when '0' => RESULT(I) := '0';
when '1' => RESULT(I) := '1';
end case;
end loop;
return RESULT;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : BIT; xmap : STD_ULOGIC := '0') return STD_ULOGIC is
begin
case s is
when '0' => RETURN '0';
when '1' => RETURN '1';
end case;
end function TO_01;
-------------------------------------------------------------------
-- to_x01
-------------------------------------------------------------------
function To_X01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias sv : STD_ULOGIC_VECTOR (1 to s'length) is s;
variable result : STD_ULOGIC_VECTOR (1 to s'length);
begin
for i in result'range loop
result(i) := cvt_to_x01 (sv(i));
end loop;
return result;
end function To_X01;
--------------------------------------------------------------------
function To_X01 (s : STD_ULOGIC) return X01 is
begin
return (cvt_to_x01(s));
end function To_X01;
--------------------------------------------------------------------
function To_X01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR is
alias bv : BIT_VECTOR (1 to b'length) is b;
variable result : STD_ULOGIC_VECTOR (1 to b'length);
begin
for i in result'range loop
case bv(i) is
when '0' => result(i) := '0';
when '1' => result(i) := '1';
end case;
end loop;
return result;
end function To_X01;
--------------------------------------------------------------------
function To_X01 (b : BIT) return X01 is
begin
case b is
when '0' => return('0');
when '1' => return('1');
end case;
end function To_X01;
--------------------------------------------------------------------
-- to_x01z
-------------------------------------------------------------------
function To_X01Z (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias sv : STD_ULOGIC_VECTOR (1 to s'length) is s;
variable result : STD_ULOGIC_VECTOR (1 to s'length);
begin
for i in result'range loop
result(i) := cvt_to_x01z (sv(i));
end loop;
return result;
end function To_X01Z;
--------------------------------------------------------------------
function To_X01Z (s : STD_ULOGIC) return X01Z is
begin
return (cvt_to_x01z(s));
end function To_X01Z;
--------------------------------------------------------------------
function To_X01Z (b : BIT_VECTOR) return STD_ULOGIC_VECTOR is
alias bv : BIT_VECTOR (1 to b'length) is b;
variable result : STD_ULOGIC_VECTOR (1 to b'length);
begin
for i in result'range loop
case bv(i) is
when '0' => result(i) := '0';
when '1' => result(i) := '1';
end case;
end loop;
return result;
end function To_X01Z;
--------------------------------------------------------------------
function To_X01Z (b : BIT) return X01Z is
begin
case b is
when '0' => return('0');
when '1' => return('1');
end case;
end function To_X01Z;
--------------------------------------------------------------------
-- to_ux01
-------------------------------------------------------------------
function To_UX01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias sv : STD_ULOGIC_VECTOR (1 to s'length) is s;
variable result : STD_ULOGIC_VECTOR (1 to s'length);
begin
for i in result'range loop
result(i) := cvt_to_ux01 (sv(i));
end loop;
return result;
end function To_UX01;
--------------------------------------------------------------------
function To_UX01 (s : STD_ULOGIC) return UX01 is
begin
return (cvt_to_ux01(s));
end function To_UX01;
--------------------------------------------------------------------
function To_UX01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR is
alias bv : BIT_VECTOR (1 to b'length) is b;
variable result : STD_ULOGIC_VECTOR (1 to b'length);
begin
for i in result'range loop
case bv(i) is
when '0' => result(i) := '0';
when '1' => result(i) := '1';
end case;
end loop;
return result;
end function To_UX01;
--------------------------------------------------------------------
function To_UX01 (b : BIT) return UX01 is
begin
case b is
when '0' => return('0');
when '1' => return('1');
end case;
end function To_UX01;
function "??" (l : STD_ULOGIC) return BOOLEAN is
begin
return l = '1' or l = 'H';
end function "??";
-------------------------------------------------------------------
-- edge detection
-------------------------------------------------------------------
function rising_edge (signal s : STD_ULOGIC) return BOOLEAN is
begin
return (s'event and (To_X01(s) = '1') and
(To_X01(s'last_value) = '0'));
end function rising_edge;
function falling_edge (signal s : STD_ULOGIC) return BOOLEAN is
begin
return (s'event and (To_X01(s) = '0') and
(To_X01(s'last_value) = '1'));
end function falling_edge;
-------------------------------------------------------------------
-- object contains an unknown
-------------------------------------------------------------------
function Is_X (s : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
for i in s'range loop
case s(i) is
when 'U' | 'X' | 'Z' | 'W' | '-' => return true;
when others => null;
end case;
end loop;
return false;
end function Is_X;
--------------------------------------------------------------------
function Is_X (s : STD_ULOGIC) return BOOLEAN is
begin
case s is
when 'U' | 'X' | 'Z' | 'W' | '-' => return true;
when others => null;
end case;
return false;
end function Is_X;
-------------------------------------------------------------------
-- string conversion and write operations
-------------------------------------------------------------------
function TO_OSTRING (value : STD_ULOGIC_VECTOR) return STRING is
constant result_length : NATURAL := (value'length+2)/3;
variable pad : STD_ULOGIC_VECTOR(1 to result_length*3 - value'length);
variable padded_value : STD_ULOGIC_VECTOR(1 to result_length*3);
variable result : STRING(1 to result_length);
variable tri : STD_ULOGIC_VECTOR(1 to 3);
begin
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
padded_value := pad & value;
for i in 1 to result_length loop
tri := To_X01Z(padded_value(3*i-2 to 3*i));
case tri is
when o"0" => result(i) := '0';
when o"1" => result(i) := '1';
when o"2" => result(i) := '2';
when o"3" => result(i) := '3';
when o"4" => result(i) := '4';
when o"5" => result(i) := '5';
when o"6" => result(i) := '6';
when o"7" => result(i) := '7';
when "ZZZ" => result(i) := 'Z';
when others => result(i) := 'X';
end case;
end loop;
return result;
end function TO_OSTRING;
function TO_HSTRING (value : STD_ULOGIC_VECTOR) return STRING is
constant result_length : NATURAL := (value'length+3)/4;
variable pad : STD_ULOGIC_VECTOR(1 to result_length*4 - value'length);
variable padded_value : STD_ULOGIC_VECTOR(1 to result_length*4);
variable result : STRING(1 to result_length);
variable quad : STD_ULOGIC_VECTOR(1 to 4);
begin
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
padded_value := pad & value;
for i in 1 to result_length loop
quad := To_X01Z(padded_value(4*i-3 to 4*i));
case quad is
when x"0" => result(i) := '0';
when x"1" => result(i) := '1';
when x"2" => result(i) := '2';
when x"3" => result(i) := '3';
when x"4" => result(i) := '4';
when x"5" => result(i) := '5';
when x"6" => result(i) := '6';
when x"7" => result(i) := '7';
when x"8" => result(i) := '8';
when x"9" => result(i) := '9';
when x"A" => result(i) := 'A';
when x"B" => result(i) := 'B';
when x"C" => result(i) := 'C';
when x"D" => result(i) := 'D';
when x"E" => result(i) := 'E';
when x"F" => result(i) := 'F';
when "ZZZZ" => result(i) := 'Z';
when others => result(i) := 'X';
end case;
end loop;
return result;
end function TO_HSTRING;
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable c : CHARACTER;
variable left : positive;
begin
while L /= null and L.all'length /= 0 loop
left := L.all'left;
c := L.all(left);
if (c = ' ' or c = NBSP or c = HT) then
read (L, c);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC;
GOOD : out BOOLEAN) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
begin
VALUE := 'U'; -- initialize to a "U"
skip_whitespace (L);
read (L, c, readOk);
if not readOk then
GOOD := false;
else
if char_to_MVL9plus(c) = error then
GOOD := false;
else
VALUE := char_to_MVL9(c);
GOOD := true;
end if;
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable c : CHARACTER;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable readOk : BOOLEAN;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
skip_whitespace (L);
if VALUE'length > 0 then
read (L, c, readOk);
i := 0;
GOOD := true;
while i < VALUE'length loop
if not readOk then -- Bail out if there was a bad read
GOOD := false;
return;
elsif c = '_' then
if i = 0 then
GOOD := false; -- Begins with an "_"
return;
elsif lastu then
GOOD := false; -- "__" detected
return;
else
lastu := true;
end if;
elsif (char_to_MVL9plus(c) = error) then
GOOD := false; -- Illegal character
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then -- reading done
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
else
GOOD := true; -- read into a null array
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
begin
VALUE := 'U'; -- initialize to a "U"
skip_whitespace (L);
read (L, c, readOk);
if not readOk then
report "STD_LOGIC_1164.READ(STD_ULOGIC) "
& "End of string encountered"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report
"STD_LOGIC_1164.READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
else
VALUE := char_to_MVL9(c);
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (L, c, readOk);
i := 0;
while i < VALUE'length loop
if readOk = false then -- Bail out if there was a bad read
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif char_to_MVL9plus(c) = error then
report
"STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write(L, MVL9_to_char(VALUE), JUSTIFIED, FIELD);
end procedure WRITE;
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable s : STRING(1 to VALUE'length);
alias m : STD_ULOGIC_VECTOR(1 to VALUE'length) is VALUE;
begin
for i in 1 to VALUE'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(L, s, JUSTIFIED, FIELD);
end procedure WRITE;
procedure Char2TriBits (C : in CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case C is
when '0' => RESULT := o"0"; GOOD := true;
when '1' => RESULT := o"1"; GOOD := true;
when '2' => RESULT := o"2"; GOOD := true;
when '3' => RESULT := o"3"; GOOD := true;
when '4' => RESULT := o"4"; GOOD := true;
when '5' => RESULT := o"5"; GOOD := true;
when '6' => RESULT := o"6"; GOOD := true;
when '7' => RESULT := o"7"; GOOD := true;
when 'Z' => RESULT := "ZZZ"; GOOD := true;
when 'X' => RESULT := "XXX"; GOOD := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.OREAD Error: Read a '" & C &
"', expected an Octal character (0-7)."
severity error;
GOOD := false;
end case;
end procedure Char2TriBits;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
skip_whitespace (L);
if VALUE'length > 0 then
read (L, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
GOOD := false;
return;
elsif c = '_' then
if i = 0 then
GOOD := false; -- Begins with an "_"
return;
elsif lastu then
GOOD := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, false);
if not ok then
GOOD := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or (sv (0 to pad-1)) = '1' then
GOOD := false; -- vector was truncated.
else
GOOD := true;
VALUE := sv (pad to sv'high);
end if;
else
GOOD := true; -- read into a null array
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable c : CHARACTER;
variable ok : BOOLEAN;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
skip_whitespace (L);
if VALUE'length > 0 then
read (L, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.OREAD "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.OREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.OREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or (sv (0 to pad-1)) = '1' then
report "STD_LOGIC_1164.OREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure OREAD;
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case C is
when '0' => RESULT := x"0"; GOOD := true;
when '1' => RESULT := x"1"; GOOD := true;
when '2' => RESULT := x"2"; GOOD := true;
when '3' => RESULT := x"3"; GOOD := true;
when '4' => RESULT := x"4"; GOOD := true;
when '5' => RESULT := x"5"; GOOD := true;
when '6' => RESULT := x"6"; GOOD := true;
when '7' => RESULT := x"7"; GOOD := true;
when '8' => RESULT := x"8"; GOOD := true;
when '9' => RESULT := x"9"; GOOD := true;
when 'A' | 'a' => RESULT := x"A"; GOOD := true;
when 'B' | 'b' => RESULT := x"B"; GOOD := true;
when 'C' | 'c' => RESULT := x"C"; GOOD := true;
when 'D' | 'd' => RESULT := x"D"; GOOD := true;
when 'E' | 'e' => RESULT := x"E"; GOOD := true;
when 'F' | 'f' => RESULT := x"F"; GOOD := true;
when 'Z' => RESULT := "ZZZZ"; GOOD := true;
when 'X' => RESULT := "XXXX"; GOOD := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.HREAD Error: Read a '" & C &
"', expected a Hex character (0-F)."
severity error;
GOOD := false;
end case;
end procedure Char2QuadBits;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
skip_whitespace (L);
if VALUE'length > 0 then
read (L, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
GOOD := false;
return;
elsif c = '_' then
if i = 0 then
GOOD := false; -- Begins with an "_"
return;
elsif lastu then
GOOD := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, false);
if not ok then
GOOD := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or (sv (0 to pad-1)) = '1' then
GOOD := false; -- vector was truncated.
else
GOOD := true;
VALUE := sv (pad to sv'high);
end if;
else
GOOD := true; -- Null input string, skips whitespace
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (L, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.HREAD "
& "End of string encountered"
severity error;
return;
end if;
if c = '_' then
if i = 0 then
report "STD_LOGIC_1164.HREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.HREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or (sv (0 to pad-1)) = '1' then
report "STD_LOGIC_1164.HREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure HREAD;
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, TO_OSTRING(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, TO_HSTRING (VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
-----------------------------------------------------------------------------
-- BEGIN NVC ADDITIONS
-----------------------------------------------------------------------------
-- The standard specifies the matching relational operators on
-- STD_ULOGIC are predefined but they are implemented here in VHDL for
-- convenience. These functions are not exported from the package and
-- cannot be called directly by user code. Instead the compiler emits
-- calls to these functions when lowering the predefined operators.
type match_table_t is array (std_ulogic, std_ulogic) of std_ulogic;
constant match_eq_table : match_table_t := (
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1' ),
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1' ),
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', '1' ),
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', '1' ),
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1' ),
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1' ),
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', '1' ),
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', '1' ),
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ) );
function nvc_rel_match_eq (l, r : std_ulogic) return std_ulogic is
begin
return match_eq_table(l, r);
end function;
constant match_lt_table : match_table_t := (
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'X' ),
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ),
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ),
( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ),
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ),
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ),
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ),
( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ),
( 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) );
function nvc_rel_match_lt (l, r : std_ulogic) return std_ulogic is
begin
assert l /= '-' and r /= '-'
report "STD_LOGIC_1164: '-' operand for matching ordering operator"
severity ERROR;
return match_lt_table(l, r);
end function;
function nvc_rel_match_leq (l, r : std_ulogic) return std_ulogic is
begin
assert l /= '-' and r /= '-'
report "STD_LOGIC_1164: '-' operand for matching ordering operator"
severity ERROR;
return match_lt_table(l, r) or match_eq_table(l, r);
end function;
end package body std_logic_1164;
| gpl-3.0 | 107a1413f195d34de9344b686fabe068 | 0.438152 | 3.888205 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3157.vhd | 4 | 2,897 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3157.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s03b00x00p16n01i03157ent IS
-- Define resolution function for SIG:
function RESFUNC( S : BIT_VECTOR ) return BIT is
begin
for I in S'RANGE loop
if (S(I) = '1') then
return '1';
end if;
end loop;
return '0';
end RESFUNC;
-- Define the signal.
subtype RBIT is RESFUNC BIT;
signal SIG : RBIT bus;
-- Use the implicit disconnect specification here.
-- Define the GUARD signal.
signal GUARD : BOOLEAN := FALSE;
begin
END c05s03b00x00p16n01i03157ent;
ARCHITECTURE c05s03b00x00p16n01i03157arch OF c05s03b00x00p16n01i03157ent IS
BEGIN
-- Define the guarded signal assignment.
L1: block
begin
SIG <= guarded '1';
end block L1;
TESTING: PROCESS
variable ShouldBeTime : TIME;
BEGIN
-- 1. Turn on the GUARD, verify that SIG gets toggled.
GUARD <= TRUE;
ShouldBeTime := NOW;
wait on SIG;
assert( SIG = '1' ) severity FAILURE;
assert( ShouldBeTime = NOW ) severity FAILURE;
-- 2. Turn off the GUARD, verify that SIG gets turned OFF.
GUARD <= FALSE;
ShouldBeTime := NOW;
wait on SIG;
assert( SIG = '0' ) severity FAILURE;
assert( ShouldBeTime = NOW ) severity FAILURE;
assert NOT( SIG = '0' and ShouldBeTime = NOW )
report "***PASSED TEST: c05s03b00x00p16n01i03157"
severity NOTE;
assert ( SIG = '0' and ShouldBeTime = NOW )
report "***FAILED TEST: c05s03b00x00p16n01i03157 - Default disconnect specification test failed."
severity ERROR;
-- Define a second driver for SIG, just for kicks.
-- Should never get invoked. Not have an effect on the value.
SIG <= '0' after 10 ns;
wait;
END PROCESS TESTING;
END c05s03b00x00p16n01i03157arch;
| gpl-2.0 | b144f67a1fcc4f0635b677840adab7e3 | 0.65447 | 3.832011 | false | true | false | false |
tgingold/ghdl | testsuite/synth/func01/tb_func04.vhdl | 1 | 457 | entity tb_func04 is
end tb_func04;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_func04 is
signal a, b, r : std_logic_vector(7 downto 0);
begin
dut: entity work.func04
port map (a, b, r);
process
begin
a <= x"5d";
b <= x"78";
wait for 1 ns;
assert r = x"79" severity failure;
a <= x"0f";
b <= x"f0";
wait for 1 ns;
assert r = x"f3" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 8400c2b976f5db68104c893f6180648d | 0.599562 | 2.85625 | false | false | false | false |
tgingold/ghdl | testsuite/synth/dispout01/tb_rec09.vhdl | 1 | 453 | entity tb_rec09 is
end tb_rec09;
library ieee;
use ieee.std_logic_1164.all;
use work.rec09_pkg.all;
architecture behav of tb_rec09 is
signal inp : std_logic;
signal r : myrec;
begin
dut: entity work.rec09
port map (inp => inp, o => r);
process
begin
inp <= '1';
wait for 1 ns;
assert r.b = '0' severity failure;
inp <= '0';
wait for 1 ns;
assert r.b = '1' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | cc2e2b39eb865a27892d84449a08ea4b | 0.620309 | 3 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug051/tb2.vhdl | 2 | 305 | entity tb2 is
end tb2;
architecture behav of tb2 is
signal s : bit;
signal clk : bit;
begin
-- psl default clock is (clk'event and clk = '1');
postponed assert always {s = '0'; s = '1'} severity failure;
process
begin
s <= '1';
wait for 0 ns;
s <= '0';
wait;
end process;
end behav;
| gpl-2.0 | f69197dbed31eb9e2f79ae6afadc2f43 | 0.616393 | 3.05 | false | false | false | false |
tgingold/ghdl | testsuite/synth/func01/tb_func02.vhdl | 1 | 494 | entity tb_func02 is
end tb_func02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_func02 is
signal a, b : std_logic_vector(7 downto 0);
begin
dut: entity work.func02
port map (a, b);
process
begin
a <= x"5d";
wait for 1 ns;
assert b = x"01" severity failure;
a <= x"ff";
wait for 1 ns;
assert b = x"01" severity failure;
a <= x"fe";
wait for 1 ns;
assert b = x"00" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 101ebb4fdd20f932f49b2af0170b9d02 | 0.61336 | 3.030675 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug040/p_jinfo_ac_dhuff_tbl_maxcode.vhd | 2 | 1,460 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity p_jinfo_ac_dhuff_tbl_maxcode is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end p_jinfo_ac_dhuff_tbl_maxcode;
architecture augh of p_jinfo_ac_dhuff_tbl_maxcode is
-- Embedded RAM
type ram_type is array (0 to 127) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 | ce4db21a1975a4d7499643ae8377ec2d | 0.676712 | 2.874016 | false | false | false | false |
nickg/nvc | test/regress/assert6.vhd | 1 | 864 | entity assert6 is
end entity;
architecture test of assert6 is
signal x : integer;
signal y : real;
begin
main: process is
type int_ptr is access integer;
variable p : int_ptr;
begin
x <= 0;
y <= 3.142;
p := new integer'(5);
wait for 1 ns;
assert x = 5 severity warning;
assert x < -1 severity warning;
assert character'val(x) /= NUL severity warning;
x <= 512;
wait for 1 ns;
assert x > 1000 severity warning;
assert x <= 2 severity warning;
assert x >= 2000 severity warning;
assert y = 4.56 severity warning;
-- This can't print a hint because "and" short-circuits
assert (x < 0) and (x / 0 < 0) severity warning;
assert p = null severity warning;
wait;
end process;
end architecture;
| gpl-3.0 | 2baf21de93e6ad00cf3e176991d4ccea | 0.56713 | 4.114286 | false | false | false | false |
tgingold/ghdl | testsuite/synth/dff03/tb_dff02.vhdl | 1 | 894 | entity tb_dff02 is
end tb_dff02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff02 is
signal clk : std_logic;
signal en1 : std_logic;
signal en2 : std_logic;
signal din : std_logic;
signal dout : std_logic;
begin
dut: entity work.dff02
port map (
q => dout,
d => din,
en1 => en1,
en2 => en2,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
en1 <= '1';
en2 <= '1';
din <= '0';
pulse;
assert dout = '0' severity failure;
din <= '1';
pulse;
assert dout = '1' severity failure;
en1 <= '0';
din <= '0';
pulse;
assert dout = '1' severity failure;
en1 <= '1';
din <= '0';
pulse;
assert dout = '0' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | fe12e81b7521a5ffd8a752881ce9322c | 0.532438 | 3.204301 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/counter.vhd | 4 | 3,849 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
package counter_types is
-- code in book (in text)
subtype digit is bit_vector(3 downto 0);
-- end code in book (in text)
end package counter_types;
entity add_1 is
port ( d0, d1, d2, d3 : in bit;
y0, y1, y2, y3 : out bit );
end entity add_1;
architecture boolean_eqn of add_1 is
begin
y0 <= not d0 after 4 ns;
y1 <= (not d1 and d0)
or (d1 and not d0) after 4 ns;
y2 <= (not d2 and d1 and d0)
or (d2 and not (d1 and d0)) after 4 ns;
y3 <= (not d3 and d2 and d1 and d0)
or (d3 and not (d2 and d1 and d0)) after 4 ns;
end architecture boolean_eqn;
entity buf4 is
port ( a0, a1, a2, a3 : in bit;
y0, y1, y2, y3 : out bit );
end entity buf4;
architecture basic of buf4 is
begin
y0 <= a0 after 2 ns;
y1 <= a1 after 2 ns;
y2 <= a2 after 2 ns;
y3 <= a3 after 2 ns;
end architecture basic;
use work.counter_types.all;
-- end not in book
entity counter is
port ( clk, clr : in bit;
q0, q1 : out digit );
end entity counter;
--------------------------------------------------
architecture registered of counter is
signal current_val0, current_val1, next_val0, next_val1 : digit;
begin
val0_reg : entity work.reg4(struct)
port map ( d0 => next_val0(0), d1 => next_val0(1),
d2 => next_val0(2), d3 => next_val0(3),
q0 => current_val0(0), q1 => current_val0(1),
q2 => current_val0(2), q3 => current_val0(3),
clk => clk, clr => clr );
val1_reg : entity work.reg4(struct)
port map ( d0 => next_val1(0), d1 => next_val1(1),
d2 => next_val1(2), d3 => next_val1(3),
q0 => current_val1(0), q1 => current_val1(1),
q2 => current_val1(2), q3 => current_val1(3),
clk => clk, clr => clr );
incr0 : entity work.add_1(boolean_eqn) -- . . .;
-- not in book
port map ( d0 => current_val0(0), d1 => current_val0(1),
d2 => current_val0(2), d3 => current_val0(3),
y0 => next_val0(0), y1 => next_val0(1),
y2 => next_val0(2), y3 => next_val0(3) );
-- end not in book
incr1 : entity work.add_1(boolean_eqn) -- . . .;
-- not in book
port map ( d0 => current_val1(0), d1 => current_val1(1),
d2 => current_val1(2), d3 => current_val1(3),
y0 => next_val1(0), y1 => next_val1(1),
y2 => next_val1(2), y3 => next_val1(3) );
-- end not in book
buf0 : entity work.buf4(basic) -- . . .;
-- not in book
port map ( a0 => current_val0(0), a1 => current_val0(1),
a2 => current_val0(2), a3 => current_val0(3),
y0 => q0(0), y1 => q0(1),
y2 => q0(2), y3 => q0(3) );
-- end not in book
buf1 : entity work.buf4(basic) -- . . .;
-- not in book
port map ( a0 => current_val1(0), a1 => current_val1(1),
a2 => current_val1(2), a3 => current_val1(3),
y0 => q1(0), y1 => q1(1),
y2 => q1(2), y3 => q1(3) );
-- end not in book
end architecture registered;
| gpl-2.0 | 28a85249f4f6fec10e280f2b47b40309 | 0.56742 | 3.00234 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado_HLS/image_contrast_adj/solution1/impl/ip/tmp.srcs/sources_1/ip/doHistStretch_ap_fdiv_14_no_dsp_32/synth/doHistStretch_ap_fdiv_14_no_dsp_32.vhd | 3 | 12,808 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_2;
USE floating_point_v7_1_2.floating_point_v7_1_2;
ENTITY doHistStretch_ap_fdiv_14_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END doHistStretch_ap_fdiv_14_no_dsp_32;
ARCHITECTURE doHistStretch_ap_fdiv_14_no_dsp_32_arch OF doHistStretch_ap_fdiv_14_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF doHistStretch_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_2 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF doHistStretch_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_2,Vivado 2016.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF doHistStretch_ap_fdiv_14_no_dsp_32_arch : ARCHITECTURE IS "doHistStretch_ap_fdiv_14_no_dsp_32,floating_point_v7_1_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF doHistStretch_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "doHistStretch_ap_fdiv_14_no_dsp_32,floating_point_v7_1_2,{x_ipProduct=Vivado 2016.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=1,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS" &
"=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=14,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0," &
"C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_2
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 1,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 14,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END doHistStretch_ap_fdiv_14_no_dsp_32_arch;
| gpl-3.0 | 3c076fec3da8a311add4b63cd66982af | 0.652014 | 3.02575 | false | false | false | false |
tgingold/ghdl | testsuite/synth/memmux01/memmux02.vhdl | 1 | 726 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memmux02 is
port (
wen : std_logic;
addr : std_logic_vector (3 downto 0);
rdat : out std_logic;
wdat : std_logic_vector (15 downto 0);
clk : std_logic;
rst : std_logic);
end memmux02;
architecture rtl of memmux02 is
begin
process (clk)
is
variable mem : std_logic_vector (15 downto 0);
variable ad : natural range 0 to 15;
begin
if rising_edge(clk) then
if rst = '1' then
mem := (others => '0');
else
ad := to_integer(unsigned(addr));
rdat <= mem (ad);
if wen = '1' then
mem := wdat;
end if;
end if;
end if;
end process;
end rtl;
| gpl-2.0 | b3ba5f77c5660744286a7cd6107509b2 | 0.575758 | 3.345622 | false | false | false | false |
nickg/nvc | test/regress/record9.vhd | 1 | 932 | entity sub is
end entity;
architecture test of sub is
type rec is record
x : integer;
end record;
constant c : rec := (x => 2);
signal ss : rec := c;
function add1(x : integer) return integer is
begin
return x + 1;
end function;
begin
process is
variable r : rec := c;
begin
r.x := add1(ss.x);
assert r.x = 3;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity record9 is
end entity;
architecture test of record9 is
type rec is record
x : bit_vector(1 to 3);
end record;
constant c : rec := (x => "101");
signal s : rec := c;
begin
uut: entity work.sub;
s.x <= "111";
process is
begin
assert s = c;
wait for 1 ns;
assert s = (x => "111");
wait;
end process;
end architecture;
| gpl-3.0 | 8ff113f9841c572845db2dfcdf5f9bd1 | 0.486052 | 3.899582 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue263/mac.vhdl | 2 | 3,289 | library ieee;
use ieee.std_logic_1164.all, ieee.fixed_pkg.all;
use ieee.math_complex.all;
entity mac is
port( clk, reset : in std_ulogic;
x_real : in u_sfixed(0 downto -15);-- real and imaginary part of the two input data sequences
x_imag : in u_sfixed(0 downto -15);
y_real : in u_sfixed(0 downto -15);
y_imag : in u_sfixed(0 downto -15);
s_real : out u_sfixed(0 downto -15); --real and imaginary parts of accumulated sum
s_imag : out u_sfixed(0 downto -15);
ovf : out std_ulogic); --overflow flag
end entity mac;
-- Behavioral model of MAC algorithm allows for focus on the algorithm without being distracted
-- by other details at this erly design stage.
architecture behavioral of mac is
signal x_complex, y_complex, s_complex : complex;
begin
x_complex <= ( to_real(x_real), to_real(x_imag) );
y_complex <= ( to_real(y_real), to_real(y_imag) );
behavior : process (clk) is
variable input_x, input_y : complex := (0.0, 0.0);
variable real_part_product_1, real_part_product_2,
imag_part_product_1, imag_part_product_2 : real := 0.0;
variable product, sum : complex := (0.0, 0.0);
variable real_accumulator_ovf,
imag_accumulator_ovf : boolean := false;
begin
if rising_edge(clk) then
-- Work from the end of the pipeline back to the start,
-- so as not to overwrite previosu results from the pipeline
-- registers before they are even used.
-- Update accumulator and generate outputs.
if reset then
sum := (0.0, 0.0);
real_accumulator_ovf := false;
imag_accumulator_ovf := false;
else
sum := product + sum;
real_accumulator_ovf := real_accumulator_ovf
or sum.re < -16.0
or sum.re >= +16.0;
imag_accumulator_ovf := imag_accumulator_ovf
or sum.im < -16.0
or sum.im >= +16.0;
end if;
s_complex <= sum;
ovf <= '1';
-- ovf <= '1' when (real_accumulator_ovf or imag_accumulator_ovf
-- or sum.re < -1.0 or sum.re >= +1.0
-- or sum.im < -1.0 or sum.im >= +1.0 ) else '0';
-- Update product registers
product.re := real_part_product_1 - real_part_product_2;
product.im := imag_part_product_1 + imag_part_product_2;
-- Update partial product registers
-- (actually with the full product).
real_part_product_1 := input_x.re * input_y.re;
real_part_product_2 := input_x.im * input_y.im;
imag_part_product_1 := input_x.re * input_y.re;
imag_part_product_2 := input_x.im * input_y.im;
-- Update input registers using MAC inputs
input_x := x_complex;
input_y := y_complex;
end if;
end process behavior;
s_real <= to_sfixed(s_complex.re, s_real);
s_imag <= to_sfixed(s_complex.im, s_imag);
end architecture behavioral;
| gpl-2.0 | 801ea73de19a2f233b30f9686ca7c9da | 0.533597 | 3.833333 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue301/src/axi4s_buffer.vhd | 7 | 3,625 | --!
--! Copyright (C) 2012 - 2014 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief AXI4-Stream buffer that allows to buffer the accept-signal.
--! @author Matthias Alles
--! @date 2012/04/18
--!
--! @details
--! One problem when concatenating multiple AXI4-Stream builind blocks is that
--! the accept signal has to pass from the very last component to the input
--! of the very first component. Only then it is possible to have an interruption
--! free data processing within the whole chain. The drawback of this approach is
--! that the accept signal has a long path and high fanouts.
--! This entity allows to use registers on the accept signals by introducing buffers
--! for storing the input values. It should improve timing of bigger building blocks.
--!
library ieee;
use ieee.std_logic_1164.all;
entity axi4s_buffer is
generic (
DATA_WIDTH : natural := 1
);
port (
clk : in std_logic;
rst : in std_logic;
-- Input data handling
----------------------
input : in std_logic_vector(DATA_WIDTH - 1 downto 0);
input_valid : in std_logic;
input_last : in std_logic;
input_accept : out std_logic;
-- Output data handling
-----------------------
output : out std_logic_vector(DATA_WIDTH - 1 downto 0);
output_valid : out std_logic;
output_last : out std_logic;
output_accept : in std_logic
);
end entity axi4s_buffer;
architecture rtl of axi4s_buffer is
signal input_accept_int : std_logic;
signal output_reg : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal output_last_reg : std_logic;
signal output_valid_reg : std_logic;
signal buffer_full : std_logic;
signal buffer_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal buffer_last : std_logic;
begin
input_accept <= input_accept_int;
output <= output_reg;
output_last <= output_last_reg;
output_valid <= output_valid_reg;
--
-- This process registers all signals.
-- No combinatorial logic is bypassed from input to output and vice versa.
--
pr_reg: process(clk) is
begin
if rising_edge(clk) then
if rst = '1' then
output_reg <= (others => '0');
output_last_reg <= '0';
output_valid_reg <= '0';
input_accept_int <= '1';
buffer_full <= '0';
buffer_data <= (others => '0');
buffer_last <= '0';
else
--
-- Data is coming, buf output data can't be sent => Store input data in buffer
-- and remove input_accept signal!
--
if input_valid = '1' and input_accept_int = '1' and output_valid_reg = '1' and output_accept = '0' then
buffer_data <= input;
buffer_last <= input_last;
buffer_full <= '1';
input_accept_int <= '0';
end if;
--
-- Output data is being read but there is data in the buffer waiting for being sent
-- => Use the buffer data!
--
if output_accept = '1' and output_valid_reg = '1' and buffer_full = '1' then
output_reg <= buffer_data;
output_last_reg <= buffer_last;
output_valid_reg <= '1';
buffer_full <= '0';
input_accept_int <= '1';
--
-- Data is being read and buffer is empty => Use input data directly!
-- Output register is empty => Use input data directly!
--
elsif (output_accept = '1' and output_valid_reg = '1') or output_valid_reg = '0' then
output_reg <= input;
output_last_reg <= input_last;
output_valid_reg <= input_valid;
end if;
end if;
end if;
end process pr_reg;
end architecture rtl;
| gpl-2.0 | a7c0d922c43e929b56c4f5b5facd247c | 0.635862 | 3.283514 | false | false | false | false |
nickg/nvc | test/regress/vests41.vhd | 1 | 6,006 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc744.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p05n02i00744pkg is
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a: boolean;
b: bit;
c: character;
d: severity_level;
e: integer;
f: real;
g: time;
h: natural;
i: positive;
j: string(1 to 7);
k: bit_vector(0 to 3);
end record;
type array_rec_std is array (integer range <>) of record_std_package;
end c01s01b01x01p05n02i00744pkg;
use work.c01s01b01x01p05n02i00744pkg.all;
ENTITY vests41 IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
C1 : boolean := true;
C2 : bit := '1';
C3 : character := 's';
C4 : severity_level:= note;
C5 : integer := 3;
C6 : real := 3.0;
C7 : time := 3 ns;
C8 : natural := 1;
C9 : positive := 1;
C10 : string := "shishir";
C11 : bit_vector := B"0011"
);
port(
S1 : inout boolean_vector (zero to fifteen);
S2 : inout severity_level_vector (zero to fifteen);
S3 : inout integer_vector (zero to fifteen);
S4 : inout real_vector (zero to fifteen);
S5 : inout time_vector (zero to fifteen);
S6 : inout natural_vector (zero to fifteen);
S7 : inout positive_vector (zero to fifteen);
S48: inout array_rec_std (zero to seven)
);
END vests41;
ARCHITECTURE c01s01b01x01p05n02i00744arch OF vests41 IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
for i in S1'range loop
S1(i) <= C1;
end loop;
for i in S2'range loop
S2(i) <= C4;
end loop;
for i in S3'range loop
S3(i) <= C5;
end loop;
for i in S4'range loop
S4(i) <= C6;
end loop;
for i in S5'range loop
S5(i) <= C7;
end loop;
for i in S6'range loop
S6(i) <= C8;
end loop;
for i in S7'range loop
S7(i) <= C9;
end loop;
for i in S48'range loop
S48(i) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
end loop;
wait for 10 ns;
for i in zero to 7 loop
if (S1(i) /= true) then
k := 1;
end if;
assert S1(i) = true report " boolean_vector(zero to fifteen) error in the left generic value" severity error;
if (S2(i) /= note) then
k := 1;
end if;
assert S2(i) = note report " severity_level_vector(zero to fifteen) error in the left generic value" severity error;
if (S3(i) /= 3) then
k := 1;
end if;
assert S3(i) = 3 report " integer_vector(zero to fifteen) error in the left generic value" severity error;
if (S4(i) /= 3.0) then
k := 1;
end if;
assert S4(i) = 3.0 report " real_vector(zero to fifteen) error in the left generic value" severity error;
if (S5(i) /= 3 ns) then
k := 1;
end if;
assert S5(i) = 3 ns report " time_vector (zero to fifteen) error in the left generic value" severity error;
if (S6(i) /= 1) then
k := 1;
end if;
assert S6(i) = 1 report " natural_vector(zero to fifteen) error in the left generic value" severity error;
if (S7(i) /= 1) then
k := 1;
end if;
assert S7(i) = 1 report " positive_vector(zero to fifteen) error in the left generic value" severity error;
if (S48(i) /= (true,'1','s',note,3,3.0,3 ns,1,1,"shishir","0011")) then
k := 1;
end if;
assert S48(i) = (true,'1','s',note,3,3.0,3 ns,1,1,"shishir","0011") report " array_rec_std(zero to seven) error in the left generic value" severity error;
end loop;
assert NOT( k=0 )
report "***PASSED TEST: c01s01b01x01p05n02i00744"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c01s01b01x01p05n02i00744 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00744arch;
| gpl-3.0 | eb6d308cf94016847198347315e6df8f | 0.561772 | 3.520516 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/quad_opamp_wa.vhd | 4 | 1,600 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity quad_opamp_wa is
port (terminal n1, n2, output : electrical_vector(1 to 4));
end entity quad_opamp_wa ;
----------------------------------------------------------------
architecture slew_limited of quad_opamp_wa is
quantity vin across n1 to n2;
quantity vout across iout through output;
quantity vamp1 : real;
quantity vamp2 : real;
quantity vamp3 : real;
quantity vamp4 : real;
constant gain : real := 50.0;
begin
vamp1 == gain*vin(1);
vamp2 == gain*vin(2);
vamp3 == gain*vin(3);
vamp4 == gain*vin(4);
vout(1) == vamp1'slew(1.0e6,-1.0e6);
vout(2) == vamp2'slew(1.0e6,-1.0e6);
vout(3) == vamp3'slew(1.0e6,-1.0e6);
vout(4) == vamp4'slew(1.0e6,-1.0e6);
end architecture slew_limited ;
| gpl-2.0 | 73e9368376196950b43e22921345f7b2 | 0.675 | 3.411514 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug040/fsm_224.vhd | 2 | 124,170 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity fsm_224 is
port (
clock : in std_logic;
reset : in std_logic;
out40 : out std_logic;
in2 : in std_logic;
in11 : in std_logic;
out146 : out std_logic;
out148 : out std_logic;
out150 : out std_logic;
out152 : out std_logic;
in12 : in std_logic;
out153 : out std_logic;
out154 : out std_logic;
in13 : in std_logic;
out156 : out std_logic;
out157 : out std_logic;
out160 : out std_logic;
out162 : out std_logic;
out165 : out std_logic;
out170 : out std_logic;
out171 : out std_logic;
out173 : out std_logic;
out175 : out std_logic;
out177 : out std_logic;
out180 : out std_logic;
out184 : out std_logic;
in14 : in std_logic;
out186 : out std_logic;
out189 : out std_logic;
out191 : out std_logic;
out192 : out std_logic;
out193 : out std_logic;
out197 : out std_logic;
out199 : out std_logic;
out201 : out std_logic;
out202 : out std_logic;
out205 : out std_logic;
out207 : out std_logic;
out208 : out std_logic;
out209 : out std_logic;
out210 : out std_logic;
out212 : out std_logic;
out213 : out std_logic;
in15 : in std_logic;
out221 : out std_logic;
out222 : out std_logic;
out224 : out std_logic;
out225 : out std_logic;
out228 : out std_logic;
out229 : out std_logic;
out230 : out std_logic;
out231 : out std_logic;
out99 : out std_logic;
in6 : in std_logic;
out92 : out std_logic;
out232 : out std_logic;
in16 : in std_logic;
out234 : out std_logic;
out236 : out std_logic;
out239 : out std_logic;
out240 : out std_logic;
out241 : out std_logic;
out245 : out std_logic;
out246 : out std_logic;
out247 : out std_logic;
out251 : out std_logic;
out252 : out std_logic;
out253 : out std_logic;
out255 : out std_logic;
out256 : out std_logic;
out258 : out std_logic;
out259 : out std_logic;
in17 : in std_logic;
out263 : out std_logic;
out264 : out std_logic;
out266 : out std_logic;
in18 : in std_logic;
out267 : out std_logic;
out268 : out std_logic;
out270 : out std_logic;
out273 : out std_logic;
out275 : out std_logic;
out276 : out std_logic;
in19 : in std_logic;
out279 : out std_logic;
in20 : in std_logic;
out281 : out std_logic;
out282 : out std_logic;
in21 : in std_logic;
out283 : out std_logic;
out286 : out std_logic;
out289 : out std_logic;
out296 : out std_logic;
out297 : out std_logic;
out299 : out std_logic;
out300 : out std_logic;
out304 : out std_logic;
out305 : out std_logic;
in22 : in std_logic;
out306 : out std_logic;
out310 : out std_logic;
out311 : out std_logic;
out313 : out std_logic;
out314 : out std_logic;
in23 : in std_logic;
out316 : out std_logic;
out317 : out std_logic;
out320 : out std_logic;
out322 : out std_logic;
out324 : out std_logic;
out325 : out std_logic;
out326 : out std_logic;
out328 : out std_logic;
out332 : out std_logic;
out333 : out std_logic;
out334 : out std_logic;
out335 : out std_logic;
out338 : out std_logic;
out339 : out std_logic;
out341 : out std_logic;
out342 : out std_logic;
out344 : out std_logic;
out93 : out std_logic;
out98 : out std_logic;
out85 : out std_logic;
out87 : out std_logic;
out88 : out std_logic;
out80 : out std_logic;
out82 : out std_logic;
out83 : out std_logic;
out84 : out std_logic;
in5 : in std_logic;
out77 : out std_logic;
out78 : out std_logic;
out71 : out std_logic;
out72 : out std_logic;
in4 : in std_logic;
out65 : out std_logic;
out67 : out std_logic;
out60 : out std_logic;
out64 : out std_logic;
in3 : in std_logic;
out59 : out std_logic;
out53 : out std_logic;
out55 : out std_logic;
out49 : out std_logic;
out44 : out std_logic;
out104 : out std_logic;
out107 : out std_logic;
out111 : out std_logic;
out112 : out std_logic;
out114 : out std_logic;
in7 : in std_logic;
out117 : out std_logic;
out119 : out std_logic;
out122 : out std_logic;
in8 : in std_logic;
out128 : out std_logic;
in9 : in std_logic;
out129 : out std_logic;
out130 : out std_logic;
out133 : out std_logic;
out134 : out std_logic;
out136 : out std_logic;
out137 : out std_logic;
in10 : in std_logic;
out139 : out std_logic;
out143 : out std_logic;
out144 : out std_logic;
out32 : out std_logic;
out35 : out std_logic;
out27 : out std_logic;
out25 : out std_logic;
out26 : out std_logic;
in1 : in std_logic;
out15 : out std_logic;
out16 : out std_logic;
out11 : out std_logic;
out13 : out std_logic;
out14 : out std_logic;
out7 : out std_logic;
out1 : out std_logic;
out2 : out std_logic;
out3 : out std_logic;
out4 : out std_logic;
in0 : in std_logic;
in24 : in std_logic;
out346 : out std_logic;
out347 : out std_logic;
out348 : out std_logic;
out349 : out std_logic;
in25 : in std_logic;
out350 : out std_logic;
out351 : out std_logic;
out355 : out std_logic;
out356 : out std_logic;
out357 : out std_logic;
out358 : out std_logic;
out360 : out std_logic;
out362 : out std_logic;
out363 : out std_logic;
out364 : out std_logic;
out365 : out std_logic;
out366 : out std_logic;
out370 : out std_logic;
out371 : out std_logic;
out372 : out std_logic;
out373 : out std_logic;
out375 : out std_logic;
in26 : in std_logic;
out376 : out std_logic;
out378 : out std_logic;
out379 : out std_logic;
out381 : out std_logic;
out382 : out std_logic;
in27 : in std_logic;
out384 : out std_logic;
in28 : in std_logic;
out391 : out std_logic;
out395 : out std_logic;
out396 : out std_logic;
out401 : out std_logic;
out402 : out std_logic;
out403 : out std_logic;
out404 : out std_logic;
out405 : out std_logic;
out407 : out std_logic;
out408 : out std_logic;
out409 : out std_logic;
out410 : out std_logic;
in29 : in std_logic;
out412 : out std_logic;
out414 : out std_logic;
out415 : out std_logic;
out417 : out std_logic;
out418 : out std_logic;
out419 : out std_logic;
out420 : out std_logic;
out422 : out std_logic;
out424 : out std_logic;
out425 : out std_logic;
out426 : out std_logic;
in30 : in std_logic;
out428 : out std_logic;
out429 : out std_logic;
out432 : out std_logic;
out433 : out std_logic;
out434 : out std_logic;
out437 : out std_logic;
out440 : out std_logic;
out441 : out std_logic;
in31 : in std_logic;
out443 : out std_logic;
in32 : in std_logic;
out445 : out std_logic;
out447 : out std_logic;
out448 : out std_logic;
out450 : out std_logic;
in33 : in std_logic;
out453 : out std_logic;
out455 : out std_logic;
out458 : out std_logic;
in34 : in std_logic;
out462 : out std_logic;
out464 : out std_logic;
out467 : out std_logic;
out468 : out std_logic;
out472 : out std_logic;
in35 : in std_logic;
out478 : out std_logic;
out479 : out std_logic;
out480 : out std_logic;
out487 : out std_logic;
out488 : out std_logic;
in36 : in std_logic;
out491 : out std_logic;
out496 : out std_logic;
out497 : out std_logic;
out498 : out std_logic;
out500 : out std_logic;
out504 : out std_logic;
out505 : out std_logic;
in37 : in std_logic;
out506 : out std_logic;
out508 : out std_logic;
in38 : in std_logic;
out510 : out std_logic;
out513 : out std_logic;
out514 : out std_logic;
out515 : out std_logic;
out517 : out std_logic;
out519 : out std_logic;
in39 : in std_logic;
out523 : out std_logic;
out526 : out std_logic;
out527 : out std_logic;
out528 : out std_logic;
out530 : out std_logic;
out531 : out std_logic;
out533 : out std_logic;
out534 : out std_logic;
out537 : out std_logic;
out538 : out std_logic;
out549 : out std_logic;
out558 : out std_logic;
out559 : out std_logic;
out561 : out std_logic;
in40 : in std_logic;
out566 : out std_logic;
out567 : out std_logic;
out568 : out std_logic;
out569 : out std_logic;
out570 : out std_logic;
out572 : out std_logic;
out574 : out std_logic;
out575 : out std_logic;
out577 : out std_logic;
in41 : in std_logic;
out578 : out std_logic;
out581 : out std_logic;
out589 : out std_logic;
out590 : out std_logic;
out595 : out std_logic;
out597 : out std_logic;
out599 : out std_logic;
out601 : out std_logic;
out602 : out std_logic;
out607 : out std_logic;
out610 : out std_logic;
out612 : out std_logic;
in42 : in std_logic;
out614 : out std_logic;
out621 : out std_logic;
out628 : out std_logic;
out635 : out std_logic;
out636 : out std_logic;
out638 : out std_logic;
out640 : out std_logic;
out643 : out std_logic;
out646 : out std_logic;
out649 : out std_logic;
out651 : out std_logic;
out656 : out std_logic;
in43 : in std_logic;
out658 : out std_logic;
out659 : out std_logic;
out661 : out std_logic;
out663 : out std_logic;
out664 : out std_logic;
in44 : in std_logic;
out667 : out std_logic;
out668 : out std_logic;
out670 : out std_logic;
out672 : out std_logic;
out674 : out std_logic;
in45 : in std_logic;
out679 : out std_logic;
out681 : out std_logic;
out683 : out std_logic;
out686 : out std_logic;
out688 : out std_logic;
out690 : out std_logic;
out692 : out std_logic;
out694 : out std_logic;
out696 : out std_logic;
out697 : out std_logic;
out698 : out std_logic;
out699 : out std_logic;
out700 : out std_logic;
out703 : out std_logic;
out704 : out std_logic;
out706 : out std_logic;
out708 : out std_logic;
out710 : out std_logic;
out712 : out std_logic;
out715 : out std_logic;
out718 : out std_logic;
in46 : in std_logic;
out722 : out std_logic;
out724 : out std_logic;
out726 : out std_logic;
out728 : out std_logic;
out731 : out std_logic;
out733 : out std_logic;
out734 : out std_logic;
out737 : out std_logic;
out739 : out std_logic;
out740 : out std_logic;
out743 : out std_logic;
out745 : out std_logic;
out746 : out std_logic;
in47 : in std_logic;
out749 : out std_logic;
out753 : out std_logic;
out755 : out std_logic;
out759 : out std_logic;
in48 : in std_logic;
out762 : out std_logic;
out764 : out std_logic;
out765 : out std_logic;
out767 : out std_logic;
out768 : out std_logic;
in49 : in std_logic;
out772 : out std_logic;
in50 : in std_logic;
out775 : out std_logic;
out776 : out std_logic;
out778 : out std_logic;
out783 : out std_logic;
out784 : out std_logic;
out787 : out std_logic;
out791 : out std_logic;
in51 : in std_logic;
out794 : out std_logic;
out795 : out std_logic;
in52 : in std_logic;
out799 : out std_logic;
out802 : out std_logic;
out806 : out std_logic;
out809 : out std_logic;
out812 : out std_logic;
out815 : out std_logic;
out826 : out std_logic;
out828 : out std_logic;
in53 : in std_logic;
in54 : in std_logic;
out843 : out std_logic;
out848 : out std_logic;
out852 : out std_logic;
in55 : in std_logic;
out855 : out std_logic;
out858 : out std_logic;
in56 : in std_logic;
out860 : out std_logic;
out861 : out std_logic;
out863 : out std_logic;
out866 : out std_logic;
out872 : out std_logic;
in57 : in std_logic;
out874 : out std_logic;
out876 : out std_logic;
out879 : out std_logic;
out882 : out std_logic;
out886 : out std_logic;
out887 : out std_logic;
in58 : in std_logic;
out888 : out std_logic;
out892 : out std_logic;
out894 : out std_logic;
out895 : out std_logic;
out896 : out std_logic;
out901 : out std_logic;
out902 : out std_logic;
out903 : out std_logic;
out905 : out std_logic;
out907 : out std_logic;
out918 : out std_logic;
out920 : out std_logic;
out921 : out std_logic;
out923 : out std_logic;
out925 : out std_logic;
out928 : out std_logic;
out929 : out std_logic;
out931 : out std_logic;
out933 : out std_logic;
out936 : out std_logic;
out937 : out std_logic;
out938 : out std_logic;
out939 : out std_logic;
out942 : out std_logic;
out943 : out std_logic;
out944 : out std_logic;
out947 : out std_logic;
out948 : out std_logic;
out949 : out std_logic;
out951 : out std_logic;
in59 : in std_logic;
out952 : out std_logic;
out953 : out std_logic;
out955 : out std_logic;
out956 : out std_logic;
out957 : out std_logic;
out958 : out std_logic;
in60 : in std_logic;
in61 : in std_logic;
out962 : out std_logic;
out963 : out std_logic;
out972 : out std_logic;
out973 : out std_logic;
out974 : out std_logic;
in62 : in std_logic;
out978 : out std_logic;
out979 : out std_logic;
out981 : out std_logic;
out982 : out std_logic;
out985 : out std_logic;
out986 : out std_logic;
out989 : out std_logic;
in63 : in std_logic;
in64 : in std_logic;
in65 : in std_logic;
in66 : in std_logic;
in67 : in std_logic;
in68 : in std_logic;
in69 : in std_logic;
in70 : in std_logic;
in71 : in std_logic;
in72 : in std_logic;
in73 : in std_logic;
in74 : in std_logic;
in75 : in std_logic;
in76 : in std_logic;
in77 : in std_logic;
in78 : in std_logic;
out990 : out std_logic;
out991 : out std_logic;
out993 : out std_logic;
out994 : out std_logic;
out996 : out std_logic;
out997 : out std_logic;
out998 : out std_logic;
out999 : out std_logic;
out1000 : out std_logic;
out1002 : out std_logic;
out1003 : out std_logic;
out1005 : out std_logic;
out1006 : out std_logic;
out1007 : out std_logic;
out1009 : out std_logic;
out1011 : out std_logic;
out1012 : out std_logic;
out1013 : out std_logic;
out1014 : out std_logic;
out1015 : out std_logic;
out1016 : out std_logic;
out1018 : out std_logic;
out1019 : out std_logic;
out1021 : out std_logic;
out1022 : out std_logic;
out1024 : out std_logic;
out1026 : out std_logic;
out1027 : out std_logic;
out1029 : out std_logic;
out1030 : out std_logic;
out1032 : out std_logic;
out1033 : out std_logic;
out1035 : out std_logic;
out1036 : out std_logic;
out1037 : out std_logic;
out1057 : out std_logic;
out1068 : out std_logic;
out1069 : out std_logic;
out1070 : out std_logic;
out1072 : out std_logic;
out1073 : out std_logic;
out1075 : out std_logic;
out1078 : out std_logic;
out1080 : out std_logic;
out1082 : out std_logic;
out1083 : out std_logic;
out1084 : out std_logic;
out1085 : out std_logic;
out1088 : out std_logic;
out1089 : out std_logic;
out1091 : out std_logic;
out1092 : out std_logic;
out1094 : out std_logic;
out1096 : out std_logic;
out1098 : out std_logic;
out1101 : out std_logic;
out1104 : out std_logic;
out1107 : out std_logic;
out1109 : out std_logic;
out1111 : out std_logic;
out1114 : out std_logic;
out1119 : out std_logic;
out1121 : out std_logic;
out1125 : out std_logic;
out1126 : out std_logic;
out1128 : out std_logic;
out1131 : out std_logic;
out1134 : out std_logic;
out1137 : out std_logic;
out1139 : out std_logic;
out1141 : out std_logic;
out1145 : out std_logic;
out1146 : out std_logic;
out1147 : out std_logic;
out1150 : out std_logic;
out1151 : out std_logic;
out1152 : out std_logic;
out1155 : out std_logic;
out1158 : out std_logic;
out1160 : out std_logic;
out1164 : out std_logic;
out1166 : out std_logic;
out1169 : out std_logic;
out1171 : out std_logic;
out1174 : out std_logic;
out1175 : out std_logic;
out1176 : out std_logic;
out1180 : out std_logic;
out1181 : out std_logic;
out1182 : out std_logic;
out1185 : out std_logic;
out1186 : out std_logic;
out1187 : out std_logic;
out1190 : out std_logic;
out1213 : out std_logic;
out1215 : out std_logic;
out1217 : out std_logic;
out1220 : out std_logic;
out1221 : out std_logic;
out1223 : out std_logic;
out1228 : out std_logic;
out1229 : out std_logic;
out1231 : out std_logic;
out1235 : out std_logic;
out1236 : out std_logic;
out1240 : out std_logic;
out1243 : out std_logic;
out1250 : out std_logic;
out1252 : out std_logic;
out1253 : out std_logic;
out1258 : out std_logic;
out1262 : out std_logic;
out1266 : out std_logic;
out1269 : out std_logic;
out1275 : out std_logic;
out1278 : out std_logic;
out1279 : out std_logic;
out1284 : out std_logic;
out1286 : out std_logic;
out1287 : out std_logic;
out1289 : out std_logic;
out1290 : out std_logic;
out1292 : out std_logic;
out1293 : out std_logic;
out1295 : out std_logic;
out1298 : out std_logic;
out1301 : out std_logic;
out1302 : out std_logic;
out1303 : out std_logic;
out1308 : out std_logic;
out1309 : out std_logic;
out1311 : out std_logic;
out1318 : out std_logic;
out1319 : out std_logic;
out1320 : out std_logic;
out1323 : out std_logic;
out1324 : out std_logic;
out1326 : out std_logic;
out1327 : out std_logic;
out1329 : out std_logic;
out1337 : out std_logic;
out1339 : out std_logic;
out1340 : out std_logic;
out1341 : out std_logic;
out1344 : out std_logic;
out1346 : out std_logic;
out1349 : out std_logic;
out1353 : out std_logic;
out1356 : out std_logic;
out1362 : out std_logic;
out1363 : out std_logic;
out1364 : out std_logic;
out1365 : out std_logic;
out1366 : out std_logic;
out1368 : out std_logic;
out1370 : out std_logic;
out1375 : out std_logic;
out1378 : out std_logic;
out1381 : out std_logic;
out1383 : out std_logic;
out1387 : out std_logic
);
end fsm_224;
architecture augh of fsm_224 is
signal state_cur : std_logic_vector(0 to 473) := (457 => '1', others => '0');
signal state_next : std_logic_vector(0 to 473) := (457 => '1', others => '0');
-- Buffers for outputs
signal out1057_buf : std_logic := '0';
signal out1057_bufn : std_logic;
signal out59_buf : std_logic := '0';
signal out59_bufn : std_logic;
signal out447_buf : std_logic := '0';
signal out447_bufn : std_logic;
signal out157_buf : std_logic := '0';
signal out157_bufn : std_logic;
signal out450_buf : std_logic := '0';
signal out450_bufn : std_logic;
signal out1012_buf : std_logic := '0';
signal out1012_bufn : std_logic;
signal out1072_buf : std_logic := '0';
signal out1072_bufn : std_logic;
signal out999_buf : std_logic := '0';
signal out999_bufn : std_logic;
signal out437_buf : std_logic := '0';
signal out437_bufn : std_logic;
signal out415_buf : std_logic := '0';
signal out415_bufn : std_logic;
signal out426_buf : std_logic := '0';
signal out426_bufn : std_logic;
signal out375_buf : std_logic := '0';
signal out375_bufn : std_logic;
signal out704_buf : std_logic := '0';
signal out704_bufn : std_logic;
signal out973_buf : std_logic := '0';
signal out973_bufn : std_logic;
signal out11_buf : std_logic := '0';
signal out11_bufn : std_logic;
signal out549_buf : std_logic := '0';
signal out549_bufn : std_logic;
signal out453_buf : std_logic := '0';
signal out453_bufn : std_logic;
signal out1231_buf : std_logic := '0';
signal out1231_bufn : std_logic;
signal out87_buf : std_logic := '0';
signal out87_bufn : std_logic;
signal out401_buf : std_logic := '0';
signal out401_bufn : std_logic;
signal out990_buf : std_logic := '0';
signal out990_bufn : std_logic;
signal out378_buf : std_logic := '0';
signal out378_bufn : std_logic;
signal out1302_buf : std_logic := '0';
signal out1302_bufn : std_logic;
signal out27_buf : std_logic := '0';
signal out27_bufn : std_logic;
signal out569_buf : std_logic := '0';
signal out569_bufn : std_logic;
signal out1030_buf : std_logic := '0';
signal out1030_bufn : std_logic;
signal out537_buf : std_logic := '0';
signal out537_bufn : std_logic;
signal out77_buf : std_logic := '0';
signal out77_bufn : std_logic;
signal out1318_buf : std_logic := '0';
signal out1318_bufn : std_logic;
signal out533_buf : std_logic := '0';
signal out533_bufn : std_logic;
signal out32_buf : std_logic := '0';
signal out32_bufn : std_logic;
signal out1027_buf : std_logic := '0';
signal out1027_bufn : std_logic;
signal out599_buf : std_logic := '0';
signal out599_bufn : std_logic;
signal out668_buf : std_logic := '0';
signal out668_bufn : std_logic;
signal out568_buf : std_logic := '0';
signal out568_bufn : std_logic;
signal out225_buf : std_logic := '0';
signal out225_bufn : std_logic;
signal out700_buf : std_logic := '0';
signal out700_bufn : std_logic;
signal out638_buf : std_logic := '0';
signal out638_bufn : std_logic;
signal out670_buf : std_logic := '0';
signal out670_bufn : std_logic;
signal out433_buf : std_logic := '0';
signal out433_bufn : std_logic;
signal out896_buf : std_logic := '0';
signal out896_bufn : std_logic;
signal out575_buf : std_logic := '0';
signal out575_bufn : std_logic;
signal out428_buf : std_logic := '0';
signal out428_bufn : std_logic;
signal out72_buf : std_logic := '0';
signal out72_bufn : std_logic;
signal out404_buf : std_logic := '0';
signal out404_bufn : std_logic;
signal out98_buf : std_logic := '0';
signal out98_bufn : std_logic;
signal out67_buf : std_logic := '0';
signal out67_bufn : std_logic;
signal out635_buf : std_logic := '0';
signal out635_bufn : std_logic;
signal out381_buf : std_logic := '0';
signal out381_bufn : std_logic;
signal out222_buf : std_logic := '0';
signal out222_bufn : std_logic;
signal out339_buf : std_logic := '0';
signal out339_bufn : std_logic;
signal out268_buf : std_logic := '0';
signal out268_bufn : std_logic;
signal out419_buf : std_logic := '0';
signal out419_bufn : std_logic;
signal out559_buf : std_logic := '0';
signal out559_bufn : std_logic;
signal out1002_buf : std_logic := '0';
signal out1002_bufn : std_logic;
signal out1006_buf : std_logic := '0';
signal out1006_bufn : std_logic;
signal out276_buf : std_logic := '0';
signal out276_bufn : std_logic;
signal out205_buf : std_logic := '0';
signal out205_bufn : std_logic;
signal out943_buf : std_logic := '0';
signal out943_bufn : std_logic;
signal out1080_buf : std_logic := '0';
signal out1080_bufn : std_logic;
signal out408_buf : std_logic := '0';
signal out408_bufn : std_logic;
signal out252_buf : std_logic := '0';
signal out252_bufn : std_logic;
signal out71_buf : std_logic := '0';
signal out71_bufn : std_logic;
signal out672_buf : std_logic := '0';
signal out672_bufn : std_logic;
signal out357_buf : std_logic := '0';
signal out357_bufn : std_logic;
signal out441_buf : std_logic := '0';
signal out441_bufn : std_logic;
signal out1084_buf : std_logic := '0';
signal out1084_bufn : std_logic;
signal out144_buf : std_logic := '0';
signal out144_bufn : std_logic;
signal out574_buf : std_logic := '0';
signal out574_bufn : std_logic;
signal out210_buf : std_logic := '0';
signal out210_bufn : std_logic;
signal out128_buf : std_logic := '0';
signal out128_bufn : std_logic;
signal out360_buf : std_logic := '0';
signal out360_bufn : std_logic;
signal out948_buf : std_logic := '0';
signal out948_bufn : std_logic;
signal out506_buf : std_logic := '0';
signal out506_bufn : std_logic;
signal out207_buf : std_logic := '0';
signal out207_bufn : std_logic;
signal out1083_buf : std_logic := '0';
signal out1083_bufn : std_logic;
signal out491_buf : std_logic := '0';
signal out491_bufn : std_logic;
signal out4_buf : std_logic := '0';
signal out4_bufn : std_logic;
signal out784_buf : std_logic := '0';
signal out784_bufn : std_logic;
signal out3_buf : std_logic := '0';
signal out3_bufn : std_logic;
signal out746_buf : std_logic := '0';
signal out746_bufn : std_logic;
signal out528_buf : std_logic := '0';
signal out528_bufn : std_logic;
signal out372_buf : std_logic := '0';
signal out372_bufn : std_logic;
signal out418_buf : std_logic := '0';
signal out418_bufn : std_logic;
signal out708_buf : std_logic := '0';
signal out708_bufn : std_logic;
signal out706_buf : std_logic := '0';
signal out706_bufn : std_logic;
signal out445_buf : std_logic := '0';
signal out445_bufn : std_logic;
signal out1021_buf : std_logic := '0';
signal out1021_bufn : std_logic;
signal out405_buf : std_logic := '0';
signal out405_bufn : std_logic;
signal out764_buf : std_logic := '0';
signal out764_bufn : std_logic;
signal out581_buf : std_logic := '0';
signal out581_bufn : std_logic;
signal out776_buf : std_logic := '0';
signal out776_bufn : std_logic;
signal out213_buf : std_logic := '0';
signal out213_bufn : std_logic;
signal out674_buf : std_logic := '0';
signal out674_bufn : std_logic;
signal out1326_buf : std_logic := '0';
signal out1326_bufn : std_logic;
signal out334_buf : std_logic := '0';
signal out334_bufn : std_logic;
signal out843_buf : std_logic := '0';
signal out843_bufn : std_logic;
signal out175_buf : std_logic := '0';
signal out175_bufn : std_logic;
signal out1036_buf : std_logic := '0';
signal out1036_bufn : std_logic;
signal out1015_buf : std_logic := '0';
signal out1015_bufn : std_logic;
signal out236_buf : std_logic := '0';
signal out236_bufn : std_logic;
signal out395_buf : std_logic := '0';
signal out395_bufn : std_logic;
signal out1340_buf : std_logic := '0';
signal out1340_bufn : std_logic;
signal out993_buf : std_logic := '0';
signal out993_bufn : std_logic;
signal out356_buf : std_logic := '0';
signal out356_bufn : std_logic;
signal out273_buf : std_logic := '0';
signal out273_bufn : std_logic;
signal out403_buf : std_logic := '0';
signal out403_bufn : std_logic;
signal out286_buf : std_logic := '0';
signal out286_bufn : std_logic;
signal out364_buf : std_logic := '0';
signal out364_bufn : std_logic;
signal out697_buf : std_logic := '0';
signal out697_bufn : std_logic;
signal out283_buf : std_logic := '0';
signal out283_bufn : std_logic;
signal out282_buf : std_logic := '0';
signal out282_bufn : std_logic;
signal out1319_buf : std_logic := '0';
signal out1319_bufn : std_logic;
signal out409_buf : std_logic := '0';
signal out409_bufn : std_logic;
signal out1092_buf : std_logic := '0';
signal out1092_bufn : std_logic;
signal out1075_buf : std_logic := '0';
signal out1075_bufn : std_logic;
signal out925_buf : std_logic := '0';
signal out925_bufn : std_logic;
signal out78_buf : std_logic := '0';
signal out78_bufn : std_logic;
signal out1089_buf : std_logic := '0';
signal out1089_bufn : std_logic;
signal out362_buf : std_logic := '0';
signal out362_bufn : std_logic;
signal out982_buf : std_logic := '0';
signal out982_bufn : std_logic;
signal out979_buf : std_logic := '0';
signal out979_bufn : std_logic;
signal out952_buf : std_logic := '0';
signal out952_bufn : std_logic;
signal out1109_buf : std_logic := '0';
signal out1109_bufn : std_logic;
signal out16_buf : std_logic := '0';
signal out16_bufn : std_logic;
signal out703_buf : std_logic := '0';
signal out703_bufn : std_logic;
signal out371_buf : std_logic := '0';
signal out371_bufn : std_logic;
signal out956_buf : std_logic := '0';
signal out956_bufn : std_logic;
signal out1107_buf : std_logic := '0';
signal out1107_bufn : std_logic;
signal out1033_buf : std_logic := '0';
signal out1033_bufn : std_logic;
signal out148_buf : std_logic := '0';
signal out148_bufn : std_logic;
signal out351_buf : std_logic := '0';
signal out351_bufn : std_logic;
signal out740_buf : std_logic := '0';
signal out740_bufn : std_logic;
signal out391_buf : std_logic := '0';
signal out391_bufn : std_logic;
signal out129_buf : std_logic := '0';
signal out129_bufn : std_logic;
signal out338_buf : std_logic := '0';
signal out338_bufn : std_logic;
signal out425_buf : std_logic := '0';
signal out425_bufn : std_logic;
signal out1078_buf : std_logic := '0';
signal out1078_bufn : std_logic;
signal out349_buf : std_logic := '0';
signal out349_bufn : std_logic;
signal out590_buf : std_logic := '0';
signal out590_bufn : std_logic;
signal out325_buf : std_logic := '0';
signal out325_bufn : std_logic;
signal out112_buf : std_logic := '0';
signal out112_bufn : std_logic;
signal out224_buf : std_logic := '0';
signal out224_bufn : std_logic;
signal out1220_buf : std_logic := '0';
signal out1220_bufn : std_logic;
signal out1250_buf : std_logic := '0';
signal out1250_bufn : std_logic;
signal out365_buf : std_logic := '0';
signal out365_bufn : std_logic;
signal out699_buf : std_logic := '0';
signal out699_bufn : std_logic;
signal out488_buf : std_logic := '0';
signal out488_bufn : std_logic;
signal out1069_buf : std_logic := '0';
signal out1069_bufn : std_logic;
signal out530_buf : std_logic := '0';
signal out530_bufn : std_logic;
signal out326_buf : std_logic := '0';
signal out326_bufn : std_logic;
signal out602_buf : std_logic := '0';
signal out602_bufn : std_logic;
signal out83_buf : std_logic := '0';
signal out83_bufn : std_logic;
signal out311_buf : std_logic := '0';
signal out311_bufn : std_logic;
signal out253_buf : std_logic := '0';
signal out253_bufn : std_logic;
signal out209_buf : std_logic := '0';
signal out209_bufn : std_logic;
signal out1240_buf : std_logic := '0';
signal out1240_bufn : std_logic;
signal out1018_buf : std_logic := '0';
signal out1018_bufn : std_logic;
signal out1152_buf : std_logic := '0';
signal out1152_bufn : std_logic;
signal out1236_buf : std_logic := '0';
signal out1236_bufn : std_logic;
signal out130_buf : std_logic := '0';
signal out130_bufn : std_logic;
signal out567_buf : std_logic := '0';
signal out567_bufn : std_logic;
signal out646_buf : std_logic := '0';
signal out646_bufn : std_logic;
-- Function calls: return IDs
signal funccall0 : natural range 0 to 18 := 0;
signal funccall0_next : natural range 0 to 18 := 0;
signal funccall1 : natural range 0 to 6 := 0;
signal funccall1_next : natural range 0 to 6 := 0;
signal funccall2 : natural range 0 to 2 := 0;
signal funccall2_next : natural range 0 to 2 := 0;
signal funccall3 : natural range 0 to 3 := 0;
signal funccall3_next : natural range 0 to 3 := 0;
signal funccall4 : natural range 0 to 1 := 0;
signal funccall4_next : natural range 0 to 1 := 0;
signal funccall5 : natural range 0 to 1 := 0;
signal funccall5_next : natural range 0 to 1 := 0;
signal funccall6 : natural range 0 to 1 := 0;
signal funccall6_next : natural range 0 to 1 := 0;
signal funccall7 : natural range 0 to 4 := 0;
signal funccall7_next : natural range 0 to 4 := 0;
signal funccall8 : natural range 0 to 1 := 0;
signal funccall8_next : natural range 0 to 1 := 0;
signal funccall9 : natural range 0 to 3 := 0;
signal funccall9_next : natural range 0 to 3 := 0;
-- A utility function to convert bool to std_logic
function to_stdl (b: boolean) return std_logic is
begin
if b = true then
return '1';
end if;
return '0';
end function;
begin
-- Sequential process
-- Set the current state
process (clock)
begin
if rising_edge(clock) then
-- Next state
state_cur <= state_next;
-- Buffers for outputs
out1057_buf <= out1057_bufn;
out59_buf <= out59_bufn;
out447_buf <= out447_bufn;
out157_buf <= out157_bufn;
out450_buf <= out450_bufn;
out1012_buf <= out1012_bufn;
out1072_buf <= out1072_bufn;
out999_buf <= out999_bufn;
out437_buf <= out437_bufn;
out415_buf <= out415_bufn;
out426_buf <= out426_bufn;
out375_buf <= out375_bufn;
out704_buf <= out704_bufn;
out973_buf <= out973_bufn;
out11_buf <= out11_bufn;
out549_buf <= out549_bufn;
out453_buf <= out453_bufn;
out1231_buf <= out1231_bufn;
out87_buf <= out87_bufn;
out401_buf <= out401_bufn;
out990_buf <= out990_bufn;
out378_buf <= out378_bufn;
out1302_buf <= out1302_bufn;
out27_buf <= out27_bufn;
out569_buf <= out569_bufn;
out1030_buf <= out1030_bufn;
out537_buf <= out537_bufn;
out77_buf <= out77_bufn;
out1318_buf <= out1318_bufn;
out533_buf <= out533_bufn;
out32_buf <= out32_bufn;
out1027_buf <= out1027_bufn;
out599_buf <= out599_bufn;
out668_buf <= out668_bufn;
out568_buf <= out568_bufn;
out225_buf <= out225_bufn;
out700_buf <= out700_bufn;
out638_buf <= out638_bufn;
out670_buf <= out670_bufn;
out433_buf <= out433_bufn;
out896_buf <= out896_bufn;
out575_buf <= out575_bufn;
out428_buf <= out428_bufn;
out72_buf <= out72_bufn;
out404_buf <= out404_bufn;
out98_buf <= out98_bufn;
out67_buf <= out67_bufn;
out635_buf <= out635_bufn;
out381_buf <= out381_bufn;
out222_buf <= out222_bufn;
out339_buf <= out339_bufn;
out268_buf <= out268_bufn;
out419_buf <= out419_bufn;
out559_buf <= out559_bufn;
out1002_buf <= out1002_bufn;
out1006_buf <= out1006_bufn;
out276_buf <= out276_bufn;
out205_buf <= out205_bufn;
out943_buf <= out943_bufn;
out1080_buf <= out1080_bufn;
out408_buf <= out408_bufn;
out252_buf <= out252_bufn;
out71_buf <= out71_bufn;
out672_buf <= out672_bufn;
out357_buf <= out357_bufn;
out441_buf <= out441_bufn;
out1084_buf <= out1084_bufn;
out144_buf <= out144_bufn;
out574_buf <= out574_bufn;
out210_buf <= out210_bufn;
out128_buf <= out128_bufn;
out360_buf <= out360_bufn;
out948_buf <= out948_bufn;
out506_buf <= out506_bufn;
out207_buf <= out207_bufn;
out1083_buf <= out1083_bufn;
out491_buf <= out491_bufn;
out4_buf <= out4_bufn;
out784_buf <= out784_bufn;
out3_buf <= out3_bufn;
out746_buf <= out746_bufn;
out528_buf <= out528_bufn;
out372_buf <= out372_bufn;
out418_buf <= out418_bufn;
out708_buf <= out708_bufn;
out706_buf <= out706_bufn;
out445_buf <= out445_bufn;
out1021_buf <= out1021_bufn;
out405_buf <= out405_bufn;
out764_buf <= out764_bufn;
out581_buf <= out581_bufn;
out776_buf <= out776_bufn;
out213_buf <= out213_bufn;
out674_buf <= out674_bufn;
out1326_buf <= out1326_bufn;
out334_buf <= out334_bufn;
out843_buf <= out843_bufn;
out175_buf <= out175_bufn;
out1036_buf <= out1036_bufn;
out1015_buf <= out1015_bufn;
out236_buf <= out236_bufn;
out395_buf <= out395_bufn;
out1340_buf <= out1340_bufn;
out993_buf <= out993_bufn;
out356_buf <= out356_bufn;
out273_buf <= out273_bufn;
out403_buf <= out403_bufn;
out286_buf <= out286_bufn;
out364_buf <= out364_bufn;
out697_buf <= out697_bufn;
out283_buf <= out283_bufn;
out282_buf <= out282_bufn;
out1319_buf <= out1319_bufn;
out409_buf <= out409_bufn;
out1092_buf <= out1092_bufn;
out1075_buf <= out1075_bufn;
out925_buf <= out925_bufn;
out78_buf <= out78_bufn;
out1089_buf <= out1089_bufn;
out362_buf <= out362_bufn;
out982_buf <= out982_bufn;
out979_buf <= out979_bufn;
out952_buf <= out952_bufn;
out1109_buf <= out1109_bufn;
out16_buf <= out16_bufn;
out703_buf <= out703_bufn;
out371_buf <= out371_bufn;
out956_buf <= out956_bufn;
out1107_buf <= out1107_bufn;
out1033_buf <= out1033_bufn;
out148_buf <= out148_bufn;
out351_buf <= out351_bufn;
out740_buf <= out740_bufn;
out391_buf <= out391_bufn;
out129_buf <= out129_bufn;
out338_buf <= out338_bufn;
out425_buf <= out425_bufn;
out1078_buf <= out1078_bufn;
out349_buf <= out349_bufn;
out590_buf <= out590_bufn;
out325_buf <= out325_bufn;
out112_buf <= out112_bufn;
out224_buf <= out224_bufn;
out1220_buf <= out1220_bufn;
out1250_buf <= out1250_bufn;
out365_buf <= out365_bufn;
out699_buf <= out699_bufn;
out488_buf <= out488_bufn;
out1069_buf <= out1069_bufn;
out530_buf <= out530_bufn;
out326_buf <= out326_bufn;
out602_buf <= out602_bufn;
out83_buf <= out83_bufn;
out311_buf <= out311_bufn;
out253_buf <= out253_bufn;
out209_buf <= out209_bufn;
out1240_buf <= out1240_bufn;
out1018_buf <= out1018_bufn;
out1152_buf <= out1152_bufn;
out1236_buf <= out1236_bufn;
out130_buf <= out130_bufn;
out567_buf <= out567_bufn;
out646_buf <= out646_bufn;
-- Function calls: return IDs
funccall0 <= funccall0_next;
funccall1 <= funccall1_next;
funccall2 <= funccall2_next;
funccall3 <= funccall3_next;
funccall4 <= funccall4_next;
funccall5 <= funccall5_next;
funccall6 <= funccall6_next;
funccall7 <= funccall7_next;
funccall8 <= funccall8_next;
funccall9 <= funccall9_next;
end if;
end process;
-- Function calls: The call IDs
-- Function 'read_byte'
funccall0_next <=
0 when ( state_cur(130) and in33 ) = '1' else
2 when ( state_cur(130) and not ( in33 ) ) = '1' else
18 when ( state_cur(137) and not ( in34 ) ) = '1' else
17 when ( state_cur(148) and in36 ) = '1' else
16 when ( state_cur(160) and in38 ) = '1' else
15 when ( state_cur(170) and in39 ) = '1' else
14 when ( state_cur(179) and in40 ) = '1' else
10 when ( state_cur(207) and to_stdl(funccall1 = 3) ) = '1' else
5 when ( state_cur(207) and to_stdl(funccall1 = 0) ) = '1' else
12 when state_cur(211) = '1' else
11 when ( state_cur(212) and in43 ) = '1' else
9 when state_cur(237) = '1' else
8 when state_cur(238) = '1' else
7 when state_cur(242) = '1' else
6 when state_cur(243) = '1' else
2 when ( state_cur(246) and not ( in46 ) ) = '1' else
3 when ( state_cur(249) and in47 ) = '1' else
4 when ( state_cur(249) and not ( in47 ) ) = '1' else
4 when ( state_cur(251) and in48 ) = '1' else
13 when ( state_cur(338) and in52 ) = '1' else
1 when ( state_cur(396) and to_stdl(funccall0 = 0) ) = '1' else
funccall0;
-- Function 'read_word'
funccall1_next <=
5 when ( state_cur(126) and not ( in32 ) and in31 ) = '1' else
4 when ( state_cur(126) and not ( in32 ) and not ( in31 ) and in30 ) = '1' else
3 when ( state_cur(126) and not ( in32 ) and not ( in31 ) and not ( in30 ) and in29 ) = '1' else
0 when ( state_cur(126) and not ( in32 ) and not ( in31 ) and not ( in30 ) and not ( in29 ) and in28 ) = '1' else
6 when ( state_cur(137) and in34 ) = '1' else
2 when state_cur(244) = '1' else
1 when ( state_cur(396) and to_stdl(funccall0 = 5) ) = '1' else
funccall1;
-- Function 'pgetc'
funccall2_next <=
1 when state_cur(72) = '1' else
2 when ( state_cur(73) and not ( in20 ) ) = '1' else
0 when ( state_cur(78) and in23 ) = '1' else
funccall2;
-- Function 'buf_getb'
funccall3_next <=
0 when state_cur(15) = '1' else
3 when ( state_cur(25) and in6 ) = '1' else
1 when ( state_cur(30) and in8 ) = '1' else
2 when state_cur(270) = '1' else
funccall3;
-- Function 'buf_getv'
funccall4_next <=
0 when state_cur(254) = '1' else
1 when state_cur(256) = '1' else
funccall4;
-- Function 'huff_make_dhuff_tb_ac'
funccall5_next <=
0 when state_cur(259) = '1' else
1 when state_cur(260) = '1' else
funccall5;
-- Function 'huff_make_dhuff_tb_dc'
funccall6_next <=
1 when state_cur(258) = '1' else
0 when state_cur(333) = '1' else
funccall6;
-- Function 'WriteOneBlock'
funccall7_next <=
1 when state_cur(257) = '1' else
2 when state_cur(445) = '1' else
3 when state_cur(461) = '1' else
4 when state_cur(462) = '1' else
0 when state_cur(469) = '1' else
funccall7;
-- Function 'YuvToRgb'
funccall8_next <=
0 when state_cur(468) = '1' else
1 when state_cur(472) = '1' else
funccall8;
-- Function 'decode_block'
funccall9_next <=
0 when state_cur(418) = '1' else
1 when state_cur(458) = '1' else
2 when state_cur(470) = '1' else
3 when state_cur(471) = '1' else
funccall9;
-- Next state bits
state_next(0) <= (not reset) and ( ( state_cur(422) and in65 ) );
state_next(1) <= (not reset) and ( state_cur(385) );
state_next(2) <= (not reset) and ( state_cur(8) or state_cur(3) );
state_next(3) <= (not reset) and ( ( state_cur(2) and in0 ) );
state_next(4) <= (not reset) and ( state_cur(377) );
state_next(5) <= (not reset) and ( ( state_cur(6) and in1 ) );
state_next(6) <= (not reset) and ( ( state_cur(424) and not ( in67 ) ) );
state_next(7) <= (not reset) and ( ( state_cur(252) and not ( in49 ) ) or state_cur(202) );
state_next(8) <= (not reset) and ( ( state_cur(460) and in78 ) or ( state_cur(13) and not ( in2 ) ) or ( state_cur(6) and not ( in1 ) ) );
state_next(9) <= (not reset) and ( state_cur(327) );
state_next(10) <= (not reset) and ( state_cur(140) );
state_next(11) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 16) ) );
state_next(12) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 15) ) );
state_next(13) <= (not reset) and ( state_cur(14) or state_cur(7) or state_cur(5) );
state_next(14) <= (not reset) and ( ( state_cur(17) and not ( in3 ) ) );
state_next(15) <= (not reset) and ( ( state_cur(13) and in2 ) );
state_next(16) <= (not reset) and ( ( state_cur(82) and in24 ) );
state_next(17) <= (not reset) and ( state_cur(19) or state_cur(18) );
state_next(18) <= (not reset) and ( state_cur(466) or ( state_cur(23) and not ( in4 ) ) );
state_next(19) <= (not reset) and ( ( state_cur(17) and in3 ) );
state_next(20) <= (not reset) and ( ( state_cur(454) and in76 ) );
state_next(21) <= (not reset) and ( ( state_cur(121) and in26 ) );
state_next(22) <= (not reset) and ( ( state_cur(24) and not ( in5 ) ) );
state_next(23) <= (not reset) and ( state_cur(159) or state_cur(22) );
state_next(24) <= (not reset) and ( ( state_cur(25) and not ( in6 ) ) );
state_next(25) <= (not reset) and ( state_cur(28) or state_cur(26) );
state_next(26) <= (not reset) and ( ( state_cur(77) and to_stdl(funccall3 = 3) ) or ( state_cur(75) and to_stdl(funccall3 = 3) ) );
state_next(27) <= (not reset) and ( ( state_cur(29) and not ( in7 ) ) );
state_next(28) <= (not reset) and ( ( state_cur(77) and to_stdl(funccall3 = 2) ) or ( state_cur(75) and to_stdl(funccall3 = 2) ) );
state_next(29) <= (not reset) and ( ( state_cur(30) and not ( in8 ) ) );
state_next(30) <= (not reset) and ( state_cur(32) or state_cur(31) );
state_next(31) <= (not reset) and ( ( state_cur(77) and to_stdl(funccall3 = 1) ) or ( state_cur(75) and to_stdl(funccall3 = 1) ) );
state_next(32) <= (not reset) and ( ( state_cur(77) and to_stdl(funccall3 = 0) ) or ( state_cur(75) and to_stdl(funccall3 = 0) ) );
state_next(33) <= (not reset) and ( state_cur(369) );
state_next(34) <= (not reset) and ( state_cur(188) or state_cur(38) );
state_next(35) <= (not reset) and ( ( state_cur(40) and not ( in10 ) ) );
state_next(36) <= (not reset) and ( state_cur(444) );
state_next(37) <= (not reset) and ( state_cur(328) );
state_next(38) <= (not reset) and ( ( state_cur(39) and in9 ) );
state_next(39) <= (not reset) and ( ( state_cur(40) and in10 ) );
state_next(40) <= (not reset) and ( state_cur(42) or state_cur(34) );
state_next(41) <= (not reset) and ( ( state_cur(53) and not ( in14 ) ) );
state_next(42) <= (not reset) and ( ( state_cur(43) and in11 ) );
state_next(43) <= (not reset) and ( ( state_cur(427) and not ( in68 ) ) );
state_next(44) <= (not reset) and ( ( state_cur(45) and not ( in12 ) ) );
state_next(45) <= (not reset) and ( state_cur(48) or state_cur(46) );
state_next(46) <= (not reset) and ( ( state_cur(47) and in13 ) );
state_next(47) <= (not reset) and ( state_cur(49) or state_cur(44) );
state_next(48) <= (not reset) and ( ( state_cur(45) and in12 ) );
state_next(49) <= (not reset) and ( ( state_cur(333) ) or ( state_cur(258) ) );
state_next(50) <= (not reset) and ( state_cur(430) or state_cur(52) );
state_next(51) <= (not reset) and ( ( state_cur(54) and not ( in15 ) ) );
state_next(52) <= (not reset) and ( ( state_cur(53) and in14 ) );
state_next(53) <= (not reset) and ( ( state_cur(54) and in15 ) );
state_next(54) <= (not reset) and ( state_cur(57) or state_cur(50) );
state_next(55) <= (not reset) and ( state_cur(372) );
state_next(56) <= (not reset) and ( state_cur(266) );
state_next(57) <= (not reset) and ( ( state_cur(59) and in16 ) );
state_next(58) <= (not reset) and ( state_cur(56) );
state_next(59) <= (not reset) and ( ( state_cur(366) and not ( in53 ) ) );
state_next(60) <= (not reset) and ( state_cur(350) );
state_next(61) <= (not reset) and ( ( state_cur(471) ) or ( state_cur(470) ) or ( state_cur(458) ) or ( state_cur(418) ) );
state_next(62) <= (not reset) and ( state_cur(208) );
state_next(63) <= (not reset) and ( ( state_cur(64) and not ( in17 ) ) );
state_next(64) <= (not reset) and ( state_cur(67) or state_cur(65) );
state_next(65) <= (not reset) and ( ( state_cur(66) and in18 ) );
state_next(66) <= (not reset) and ( state_cur(68) or state_cur(63) );
state_next(67) <= (not reset) and ( ( state_cur(64) and in17 ) );
state_next(68) <= (not reset) and ( ( state_cur(260) ) or ( state_cur(259) ) );
state_next(69) <= (not reset) and ( ( state_cur(74) and not ( in21 ) ) );
state_next(70) <= (not reset) and ( ( state_cur(69) and in19 ) );
state_next(71) <= (not reset) and ( ( state_cur(80) and to_stdl(funccall2 = 2) ) or ( state_cur(79) and to_stdl(funccall2 = 2) ) );
state_next(72) <= (not reset) and ( ( state_cur(73) and in20 ) );
state_next(73) <= (not reset) and ( ( state_cur(74) and in21 ) );
state_next(74) <= (not reset) and ( state_cur(432) or state_cur(71) );
state_next(75) <= (not reset) and ( ( state_cur(76) and not ( in22 ) ) );
state_next(76) <= (not reset) and ( state_cur(81) or ( state_cur(78) and not ( in23 ) ) );
state_next(77) <= (not reset) and ( ( state_cur(76) and in22 ) );
state_next(78) <= (not reset) and ( ( state_cur(270) ) or ( state_cur(30) and in8 ) or ( state_cur(25) and in6 ) or ( state_cur(15) ) );
state_next(79) <= (not reset) and ( ( state_cur(454) and not ( in76 ) ) or ( state_cur(240) and in44 ) );
state_next(80) <= (not reset) and ( ( state_cur(240) and not ( in44 ) ) );
state_next(81) <= (not reset) and ( ( state_cur(80) and to_stdl(funccall2 = 0) ) or ( state_cur(79) and to_stdl(funccall2 = 0) ) );
state_next(82) <= (not reset) and ( state_cur(83) or state_cur(16) );
state_next(83) <= (not reset) and ( ( state_cur(105) and not ( in25 ) ) );
state_next(84) <= (not reset) and ( state_cur(302) );
state_next(85) <= (not reset) and ( state_cur(282) );
state_next(86) <= (not reset) and ( state_cur(388) );
state_next(87) <= (not reset) and ( state_cur(122) );
state_next(88) <= (not reset) and ( state_cur(112) );
state_next(89) <= (not reset) and ( state_cur(283) );
state_next(90) <= (not reset) and ( state_cur(89) );
state_next(91) <= (not reset) and ( state_cur(315) );
state_next(92) <= (not reset) and ( state_cur(292) );
state_next(93) <= (not reset) and ( state_cur(99) );
state_next(94) <= (not reset) and ( state_cur(93) );
state_next(95) <= (not reset) and ( state_cur(306) );
state_next(96) <= (not reset) and ( state_cur(317) );
state_next(97) <= (not reset) and ( state_cur(295) );
state_next(98) <= (not reset) and ( state_cur(296) );
state_next(99) <= (not reset) and ( state_cur(290) );
state_next(100) <= (not reset) and ( state_cur(98) );
state_next(101) <= (not reset) and ( state_cur(299) );
state_next(102) <= (not reset) and ( state_cur(106) );
state_next(103) <= (not reset) and ( state_cur(102) );
state_next(104) <= (not reset) and ( state_cur(300) );
state_next(105) <= (not reset) and ( state_cur(224) or state_cur(107) );
state_next(106) <= (not reset) and ( state_cur(104) );
state_next(107) <= (not reset) and ( ( state_cur(121) and not ( in26 ) ) );
state_next(108) <= (not reset) and ( state_cur(307) );
state_next(109) <= (not reset) and ( state_cur(436) );
state_next(110) <= (not reset) and ( state_cur(172) );
state_next(111) <= (not reset) and ( state_cur(314) );
state_next(112) <= (not reset) and ( state_cur(199) );
state_next(113) <= (not reset) and ( state_cur(303) );
state_next(114) <= (not reset) and ( state_cur(111) );
state_next(115) <= (not reset) and ( state_cur(96) );
state_next(116) <= (not reset) and ( state_cur(380) );
state_next(117) <= (not reset) and ( state_cur(345) );
state_next(118) <= (not reset) and ( state_cur(347) );
state_next(119) <= (not reset) and ( state_cur(337) );
state_next(120) <= (not reset) and ( state_cur(180) );
state_next(121) <= (not reset) and ( state_cur(321) or state_cur(223) );
state_next(122) <= (not reset) and ( state_cur(183) );
state_next(123) <= (not reset) and ( ( state_cur(80) and to_stdl(funccall2 = 1) ) or ( state_cur(79) and to_stdl(funccall2 = 1) ) );
state_next(124) <= (not reset) and ( state_cur(354) );
state_next(125) <= (not reset) and ( ( state_cur(126) and not ( in32 ) and not ( in31 ) and not ( in30 ) and not ( in29 ) and not ( in28 ) and in27 ) );
state_next(126) <= (not reset) and ( state_cur(129) or state_cur(128) );
state_next(127) <= (not reset) and ( state_cur(171) );
state_next(128) <= (not reset) and ( state_cur(245) );
state_next(129) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 1) ) );
state_next(130) <= (not reset) and ( state_cur(234) or ( state_cur(179) and not ( in40 ) ) or ( state_cur(148) and not ( in36 ) ) or state_cur(134) or ( state_cur(126) and not ( in32 ) and not ( in31 ) and not ( in30 ) and not ( in29 ) and not ( in28 ) and not ( in27 ) ) or state_cur(125) );
state_next(131) <= (not reset) and ( state_cur(273) );
state_next(132) <= (not reset) and ( ( state_cur(157) and in37 ) );
state_next(133) <= (not reset) and ( ( state_cur(453) and to_stdl(funccall4 = 0) ) or ( state_cur(131) and to_stdl(funccall4 = 0) ) or ( state_cur(70) and to_stdl(funccall4 = 0) ) );
state_next(134) <= (not reset) and ( ( state_cur(423) and not ( in66 ) ) );
state_next(135) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 18) ) );
state_next(136) <= (not reset) and ( ( state_cur(207) and to_stdl(funccall1 = 6) ) );
state_next(137) <= (not reset) and ( ( state_cur(138) and in35 ) );
state_next(138) <= (not reset) and ( state_cur(161) or state_cur(139) );
state_next(139) <= (not reset) and ( state_cur(136) or state_cur(135) );
state_next(140) <= (not reset) and ( state_cur(21) );
state_next(141) <= (not reset) and ( state_cur(331) );
state_next(142) <= (not reset) and ( state_cur(332) );
state_next(143) <= (not reset) and ( state_cur(463) );
state_next(144) <= (not reset) and ( state_cur(9) );
state_next(145) <= (not reset) and ( state_cur(110) );
state_next(146) <= (not reset) and ( state_cur(465) );
state_next(147) <= (not reset) and ( state_cur(10) );
state_next(148) <= (not reset) and ( state_cur(214) or state_cur(152) );
state_next(149) <= (not reset) and ( state_cur(319) );
state_next(150) <= (not reset) and ( state_cur(119) );
state_next(151) <= (not reset) and ( state_cur(166) );
state_next(152) <= (not reset) and ( ( state_cur(207) and to_stdl(funccall1 = 5) ) );
state_next(153) <= (not reset) and ( state_cur(151) );
state_next(154) <= (not reset) and ( ( state_cur(160) and not ( in38 ) ) );
state_next(155) <= (not reset) and ( state_cur(341) );
state_next(156) <= (not reset) and ( state_cur(335) );
state_next(157) <= (not reset) and ( state_cur(133) );
state_next(158) <= (not reset) and ( state_cur(186) or ( state_cur(126) and in32 ) );
state_next(159) <= (not reset) and ( state_cur(167) );
state_next(160) <= (not reset) and ( state_cur(163) or state_cur(11) );
state_next(161) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 17) ) );
state_next(162) <= (not reset) and ( state_cur(156) );
state_next(163) <= (not reset) and ( ( state_cur(170) and not ( in39 ) ) );
state_next(164) <= (not reset) and ( ( state_cur(439) and in71 ) );
state_next(165) <= (not reset) and ( ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 0) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 0) ) );
state_next(166) <= (not reset) and ( state_cur(361) );
state_next(167) <= (not reset) and ( ( state_cur(24) and in5 ) );
state_next(168) <= (not reset) and ( ( state_cur(29) and in7 ) );
state_next(169) <= (not reset) and ( state_cur(190) or state_cur(187) );
state_next(170) <= (not reset) and ( state_cur(255) or state_cur(12) );
state_next(171) <= (not reset) and ( state_cur(87) );
state_next(172) <= (not reset) and ( state_cur(322) );
state_next(173) <= (not reset) and ( state_cur(168) );
state_next(174) <= (not reset) and ( ( state_cur(433) and in70 ) or ( state_cur(59) and not ( in16 ) ) );
state_next(175) <= (not reset) and ( state_cur(456) );
state_next(176) <= (not reset) and ( state_cur(348) );
state_next(177) <= (not reset) and ( state_cur(192) );
state_next(178) <= (not reset) and ( state_cur(384) );
state_next(179) <= (not reset) and ( state_cur(184) or state_cur(154) );
state_next(180) <= (not reset) and ( state_cur(88) );
state_next(181) <= (not reset) and ( state_cur(455) );
state_next(182) <= (not reset) and ( state_cur(336) );
state_next(183) <= (not reset) and ( state_cur(124) );
state_next(184) <= (not reset) and ( ( state_cur(207) and to_stdl(funccall1 = 4) ) );
state_next(185) <= (not reset) and ( state_cur(194) );
state_next(186) <= (not reset) and ( ( state_cur(338) and not ( in52 ) ) );
state_next(187) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 13) ) );
state_next(188) <= (not reset) and ( state_cur(426) );
state_next(189) <= (not reset) and ( state_cur(343) );
state_next(190) <= (not reset) and ( ( state_cur(212) and not ( in43 ) ) );
state_next(191) <= (not reset) and ( ( state_cur(252) and in49 ) );
state_next(192) <= (not reset) and ( state_cur(473) );
state_next(193) <= (not reset) and ( state_cur(362) );
state_next(194) <= (not reset) and ( state_cur(176) );
state_next(195) <= (not reset) and ( state_cur(360) );
state_next(196) <= (not reset) and ( state_cur(86) );
state_next(197) <= (not reset) and ( state_cur(55) );
state_next(198) <= (not reset) and ( state_cur(371) );
state_next(199) <= (not reset) and ( state_cur(118) );
state_next(200) <= (not reset) and ( state_cur(376) );
state_next(201) <= (not reset) and ( state_cur(204) );
state_next(202) <= (not reset) and ( state_cur(191) );
state_next(203) <= (not reset) and ( state_cur(359) );
state_next(204) <= (not reset) and ( state_cur(182) );
state_next(205) <= (not reset) and ( ( state_cur(210) and not ( in42 ) ) );
state_next(206) <= (not reset) and ( ( state_cur(210) and in42 ) or ( state_cur(209) and not ( in41 ) ) );
state_next(207) <= (not reset) and ( state_cur(365) );
state_next(208) <= (not reset) and ( state_cur(344) );
state_next(209) <= (not reset) and ( state_cur(213) or state_cur(205) );
state_next(210) <= (not reset) and ( ( state_cur(209) and in41 ) );
state_next(211) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 11) ) );
state_next(212) <= (not reset) and ( state_cur(229) or state_cur(206) );
state_next(213) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 12) ) );
state_next(214) <= (not reset) and ( state_cur(353) );
state_next(215) <= (not reset) and ( state_cur(62) );
state_next(216) <= (not reset) and ( state_cur(178) );
state_next(217) <= (not reset) and ( state_cur(389) );
state_next(218) <= (not reset) and ( state_cur(373) );
state_next(219) <= (not reset) and ( state_cur(340) );
state_next(220) <= (not reset) and ( state_cur(374) );
state_next(221) <= (not reset) and ( state_cur(346) );
state_next(222) <= (not reset) and ( state_cur(370) );
state_next(223) <= (not reset) and ( state_cur(367) );
state_next(224) <= (not reset) and ( state_cur(185) );
state_next(225) <= (not reset) and ( state_cur(226) );
state_next(226) <= (not reset) and ( state_cur(227) );
state_next(227) <= (not reset) and ( state_cur(218) );
state_next(228) <= (not reset) and ( state_cur(230) );
state_next(229) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 10) ) );
state_next(230) <= (not reset) and ( state_cur(225) );
state_next(231) <= (not reset) and ( state_cur(233) );
state_next(232) <= (not reset) and ( state_cur(280) );
state_next(233) <= (not reset) and ( state_cur(232) );
state_next(234) <= (not reset) and ( ( state_cur(241) and not ( in45 ) ) );
state_next(235) <= (not reset) and ( state_cur(164) );
state_next(236) <= (not reset) and ( state_cur(165) );
state_next(237) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 8) ) );
state_next(238) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 7) ) );
state_next(239) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 9) ) );
state_next(240) <= (not reset) and ( state_cur(20) );
state_next(241) <= (not reset) and ( state_cur(247) or state_cur(239) );
state_next(242) <= (not reset) and ( ( state_cur(241) and in45 ) );
state_next(243) <= (not reset) and ( ( state_cur(207) and to_stdl(funccall1 = 2) ) );
state_next(244) <= (not reset) and ( ( state_cur(207) and to_stdl(funccall1 = 1) ) );
state_next(245) <= (not reset) and ( ( state_cur(246) and in46 ) );
state_next(246) <= (not reset) and ( ( state_cur(251) and not ( in48 ) ) );
state_next(247) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 6) ) );
state_next(248) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 3) ) );
state_next(249) <= (not reset) and ( state_cur(250) or state_cur(248) );
state_next(250) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 2) ) );
state_next(251) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 4) ) );
state_next(252) <= (not reset) and ( state_cur(253) );
state_next(253) <= (not reset) and ( ( state_cur(453) and to_stdl(funccall4 = 1) ) or ( state_cur(131) and to_stdl(funccall4 = 1) ) or ( state_cur(70) and to_stdl(funccall4 = 1) ) );
state_next(254) <= (not reset) and ( ( state_cur(23) and in4 ) );
state_next(255) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 14) ) );
state_next(256) <= (not reset) and ( ( state_cur(460) and not ( in78 ) ) );
state_next(257) <= (not reset) and ( ( state_cur(399) and in56 ) );
state_next(258) <= (not reset) and ( ( state_cur(35) and to_stdl(funccall6 = 0) ) );
state_next(259) <= (not reset) and ( ( state_cur(35) and to_stdl(funccall6 = 1) ) );
state_next(260) <= (not reset) and ( ( state_cur(51) and to_stdl(funccall5 = 0) ) );
state_next(261) <= (not reset) and ( ( state_cur(51) and to_stdl(funccall5 = 1) ) );
state_next(262) <= (not reset) and ( state_cur(391) or ( state_cur(262) and not (in50) ) );
state_next(263) <= (not reset) and ( ( state_cur(392) and not ( in55 ) ) or ( state_cur(263) and not (in50) ) );
state_next(264) <= (not reset) and ( state_cur(386) or ( state_cur(264) and not (in50) ) );
state_next(265) <= (not reset) and ( ( state_cur(423) and in66 ) or state_cur(397) or ( state_cur(265) and not (in51) ) );
state_next(266) <= (not reset) and ( state_cur(85) );
state_next(267) <= (not reset) and ( state_cur(58) );
state_next(268) <= (not reset) and ( state_cur(267) );
state_next(269) <= (not reset) and ( state_cur(268) );
state_next(270) <= (not reset) and ( state_cur(61) );
state_next(271) <= (not reset) and ( ( state_cur(256) ) or ( state_cur(254) ) );
state_next(272) <= (not reset) and ( state_cur(198) );
state_next(273) <= (not reset) and ( ( state_cur(69) and not ( in19 ) ) );
state_next(274) <= (not reset) and ( state_cur(272) );
state_next(275) <= (not reset) and ( ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 4) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 4) ) );
state_next(276) <= (not reset) and ( state_cur(275) );
state_next(277) <= (not reset) and ( state_cur(269) );
state_next(278) <= (not reset) and ( state_cur(277) );
state_next(279) <= (not reset) and ( state_cur(274) );
state_next(280) <= (not reset) and ( state_cur(279) );
state_next(281) <= (not reset) and ( state_cur(84) );
state_next(282) <= (not reset) and ( state_cur(281) );
state_next(283) <= (not reset) and ( state_cur(92) );
state_next(284) <= (not reset) and ( state_cur(90) );
state_next(285) <= (not reset) and ( state_cur(284) );
state_next(286) <= (not reset) and ( state_cur(285) );
state_next(287) <= (not reset) and ( state_cur(286) );
state_next(288) <= (not reset) and ( state_cur(287) );
state_next(289) <= (not reset) and ( state_cur(288) );
state_next(290) <= (not reset) and ( state_cur(289) );
state_next(291) <= (not reset) and ( state_cur(91) );
state_next(292) <= (not reset) and ( state_cur(291) );
state_next(293) <= (not reset) and ( state_cur(94) );
state_next(294) <= (not reset) and ( state_cur(293) );
state_next(295) <= (not reset) and ( state_cur(294) );
state_next(296) <= (not reset) and ( state_cur(97) );
state_next(297) <= (not reset) and ( state_cur(100) );
state_next(298) <= (not reset) and ( state_cur(297) );
state_next(299) <= (not reset) and ( state_cur(298) );
state_next(300) <= (not reset) and ( state_cur(101) );
state_next(301) <= (not reset) and ( state_cur(103) );
state_next(302) <= (not reset) and ( state_cur(301) );
state_next(303) <= (not reset) and ( state_cur(357) );
state_next(304) <= (not reset) and ( state_cur(434) );
state_next(305) <= (not reset) and ( state_cur(425) );
state_next(306) <= (not reset) and ( state_cur(305) );
state_next(307) <= (not reset) and ( state_cur(304) );
state_next(308) <= (not reset) and ( state_cur(108) );
state_next(309) <= (not reset) and ( state_cur(308) );
state_next(310) <= (not reset) and ( state_cur(95) );
state_next(311) <= (not reset) and ( state_cur(310) );
state_next(312) <= (not reset) and ( state_cur(311) );
state_next(313) <= (not reset) and ( state_cur(309) );
state_next(314) <= (not reset) and ( state_cur(313) );
state_next(315) <= (not reset) and ( state_cur(114) );
state_next(316) <= (not reset) and ( state_cur(318) );
state_next(317) <= (not reset) and ( state_cur(312) );
state_next(318) <= (not reset) and ( state_cur(329) );
state_next(319) <= (not reset) and ( state_cur(316) );
state_next(320) <= (not reset) and ( state_cur(326) );
state_next(321) <= (not reset) and ( state_cur(115) );
state_next(322) <= (not reset) and ( state_cur(320) );
state_next(323) <= (not reset) and ( state_cur(330) );
state_next(324) <= (not reset) and ( ( state_cur(78) and in23 ) or ( state_cur(73) and not ( in20 ) ) or ( state_cur(72) ) );
state_next(325) <= (not reset) and ( state_cur(323) );
state_next(326) <= (not reset) and ( state_cur(325) );
state_next(327) <= (not reset) and ( state_cur(155) );
state_next(328) <= (not reset) and ( state_cur(145) );
state_next(329) <= (not reset) and ( state_cur(141) );
state_next(330) <= (not reset) and ( state_cur(142) );
state_next(331) <= (not reset) and ( state_cur(113) );
state_next(332) <= (not reset) and ( state_cur(438) );
state_next(333) <= (not reset) and ( state_cur(158) );
state_next(334) <= (not reset) and ( state_cur(197) );
state_next(335) <= (not reset) and ( state_cur(189) );
state_next(336) <= (not reset) and ( state_cur(203) );
state_next(337) <= (not reset) and ( state_cur(358) );
state_next(338) <= (not reset) and ( state_cur(169) );
state_next(339) <= (not reset) and ( state_cur(349) );
state_next(340) <= (not reset) and ( state_cur(177) );
state_next(341) <= (not reset) and ( state_cur(339) );
state_next(342) <= (not reset) and ( state_cur(382) );
state_next(343) <= (not reset) and ( state_cur(150) );
state_next(344) <= (not reset) and ( state_cur(442) );
state_next(345) <= (not reset) and ( state_cur(400) );
state_next(346) <= (not reset) and ( state_cur(200) );
state_next(347) <= (not reset) and ( state_cur(162) );
state_next(348) <= (not reset) and ( state_cur(193) );
state_next(349) <= (not reset) and ( state_cur(219) );
state_next(350) <= (not reset) and ( state_cur(37) );
state_next(351) <= (not reset) and ( state_cur(404) );
state_next(352) <= (not reset) and ( state_cur(1) );
state_next(353) <= (not reset) and ( ( state_cur(138) and not ( in35 ) ) );
state_next(354) <= (not reset) and ( ( state_cur(105) and in25 ) );
state_next(355) <= (not reset) and ( state_cur(175) );
state_next(356) <= (not reset) and ( state_cur(4) );
state_next(357) <= (not reset) and ( ( state_cur(82) and not ( in24 ) ) );
state_next(358) <= (not reset) and ( state_cur(117) );
state_next(359) <= (not reset) and ( state_cur(352) );
state_next(360) <= (not reset) and ( state_cur(368) );
state_next(361) <= (not reset) and ( state_cur(33) );
state_next(362) <= (not reset) and ( state_cur(356) );
state_next(363) <= (not reset) and ( ( state_cur(451) and in74 ) );
state_next(364) <= (not reset) and ( state_cur(228) );
state_next(365) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 5) ) or ( state_cur(244) ) or ( state_cur(137) and in34 ) or ( state_cur(126) and not ( in32 ) and not ( in31 ) and not ( in30 ) and not ( in29 ) and in28 ) or ( state_cur(126) and not ( in32 ) and not ( in31 ) and not ( in30 ) and in29 ) or ( state_cur(126) and not ( in32 ) and not ( in31 ) and in30 ) or ( state_cur(126) and not ( in32 ) and in31 ) );
state_next(366) <= (not reset) and ( state_cur(441) );
state_next(367) <= (not reset) and ( state_cur(201) );
state_next(368) <= (not reset) and ( state_cur(221) );
state_next(369) <= (not reset) and ( state_cur(231) );
state_next(370) <= (not reset) and ( state_cur(394) );
state_next(371) <= (not reset) and ( ( state_cur(2) and not ( in0 ) ) );
state_next(372) <= (not reset) and ( state_cur(375) );
state_next(373) <= (not reset) and ( state_cur(215) );
state_next(374) <= (not reset) and ( state_cur(217) );
state_next(375) <= (not reset) and ( state_cur(355) );
state_next(376) <= (not reset) and ( state_cur(381) );
state_next(377) <= (not reset) and ( state_cur(127) );
state_next(378) <= (not reset) and ( ( state_cur(428) and in69 ) or ( state_cur(43) and not ( in11 ) ) );
state_next(379) <= (not reset) and ( ( state_cur(47) and not ( in13 ) ) );
state_next(380) <= (not reset) and ( state_cur(351) );
state_next(381) <= (not reset) and ( state_cur(216) );
state_next(382) <= (not reset) and ( state_cur(195) );
state_next(383) <= (not reset) and ( ( state_cur(469) ) or ( state_cur(462) ) or ( state_cur(461) ) or ( state_cur(445) ) or ( state_cur(257) ) );
state_next(384) <= (not reset) and ( state_cur(196) );
state_next(385) <= (not reset) and ( state_cur(120) );
state_next(386) <= (not reset) and ( ( state_cur(263) and not ( not (in50) ) ) );
state_next(387) <= (not reset) and ( state_cur(342) );
state_next(388) <= (not reset) and ( state_cur(60) );
state_next(389) <= (not reset) and ( state_cur(235) );
state_next(390) <= (not reset) and ( ( state_cur(262) and not ( not (in50) ) ) );
state_next(391) <= (not reset) and ( state_cur(393) or ( state_cur(390) and in54 ) );
state_next(392) <= (not reset) and ( ( state_cur(390) and not ( in54 ) ) );
state_next(393) <= (not reset) and ( state_cur(395) or ( state_cur(392) and in55 ) );
state_next(394) <= (not reset) and ( state_cur(364) );
state_next(395) <= (not reset) and ( ( state_cur(416) and not ( in62 ) ) or ( state_cur(409) and not ( in59 ) ) );
state_next(396) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 0) ) or ( state_cur(338) and in52 ) or ( state_cur(251) and in48 ) or ( state_cur(249) and not ( in47 ) ) or ( state_cur(249) and in47 ) or ( state_cur(246) and not ( in46 ) ) or ( state_cur(243) ) or ( state_cur(242) ) or ( state_cur(238) ) or ( state_cur(237) ) or ( state_cur(212) and in43 ) or ( state_cur(211) ) or ( state_cur(207) and to_stdl(funccall1 = 0) ) or ( state_cur(207) and to_stdl(funccall1 = 3) ) or ( state_cur(179) and in40 ) or ( state_cur(170) and in39 ) or ( state_cur(160) and in38 ) or ( state_cur(148) and in36 ) or ( state_cur(137) and not ( in34 ) ) or ( state_cur(130) and not ( in33 ) ) or ( state_cur(130) and in33 ) );
state_next(397) <= (not reset) and ( ( state_cur(457) and not ( not (in77) ) ) or ( state_cur(264) and not ( not (in50) ) ) );
state_next(398) <= (not reset) and ( ( state_cur(399) and not ( in56 ) ) );
state_next(399) <= (not reset) and ( state_cur(401) or state_cur(276) );
state_next(400) <= (not reset) and ( state_cur(109) );
state_next(401) <= (not reset) and ( ( state_cur(403) and not ( in57 ) ) );
state_next(402) <= (not reset) and ( ( state_cur(439) and not ( in71 ) and to_stdl(funccall8 = 1) ) );
state_next(403) <= (not reset) and ( state_cur(405) or state_cur(402) );
state_next(404) <= (not reset) and ( state_cur(387) );
state_next(405) <= (not reset) and ( ( state_cur(278) and to_stdl(funccall9 = 3) ) );
state_next(406) <= (not reset) and ( ( state_cur(278) and to_stdl(funccall9 = 1) ) );
state_next(407) <= (not reset) and ( state_cur(408) or state_cur(406) );
state_next(408) <= (not reset) and ( ( state_cur(409) and in59 ) );
state_next(409) <= (not reset) and ( ( state_cur(417) and not ( in63 ) ) or state_cur(398) );
state_next(410) <= (not reset) and ( ( state_cur(411) and not ( in60 ) ) );
state_next(411) <= (not reset) and ( state_cur(412) or state_cur(236) );
state_next(412) <= (not reset) and ( ( state_cur(439) and not ( in71 ) and to_stdl(funccall8 = 0) ) );
state_next(413) <= (not reset) and ( ( state_cur(278) and to_stdl(funccall9 = 0) ) );
state_next(414) <= (not reset) and ( state_cur(415) or state_cur(413) );
state_next(415) <= (not reset) and ( ( state_cur(416) and in62 ) );
state_next(416) <= (not reset) and ( ( state_cur(417) and in63 ) or state_cur(410) );
state_next(417) <= (not reset) and ( ( state_cur(419) and not ( in64 ) ) );
state_next(418) <= (not reset) and ( ( state_cur(414) and in61 ) );
state_next(419) <= (not reset) and ( state_cur(421) or state_cur(420) );
state_next(420) <= (not reset) and ( ( state_cur(419) and in64 ) );
state_next(421) <= (not reset) and ( ( state_cur(422) and not ( in65 ) ) );
state_next(422) <= (not reset) and ( state_cur(261) or state_cur(0) );
state_next(423) <= (not reset) and ( ( state_cur(265) and not ( not (in51) ) ) );
state_next(424) <= (not reset) and ( state_cur(435) );
state_next(425) <= (not reset) and ( state_cur(146) );
state_next(426) <= (not reset) and ( ( state_cur(39) and not ( in9 ) ) );
state_next(427) <= (not reset) and ( state_cur(429) );
state_next(428) <= (not reset) and ( state_cur(378) );
state_next(429) <= (not reset) and ( state_cur(431) or ( state_cur(428) and not ( in69 ) ) or ( state_cur(427) and in68 ) );
state_next(430) <= (not reset) and ( state_cur(41) );
state_next(431) <= (not reset) and ( state_cur(379) );
state_next(432) <= (not reset) and ( state_cur(271) );
state_next(433) <= (not reset) and ( state_cur(174) );
state_next(434) <= (not reset) and ( state_cur(143) );
state_next(435) <= (not reset) and ( state_cur(173) or state_cur(27) );
state_next(436) <= (not reset) and ( state_cur(181) );
state_next(437) <= (not reset) and ( state_cur(443) or ( state_cur(157) and not ( in37 ) ) );
state_next(438) <= (not reset) and ( state_cur(334) );
state_next(439) <= (not reset) and ( state_cur(440) or state_cur(220) );
state_next(440) <= (not reset) and ( ( state_cur(472) ) or ( state_cur(468) ) );
state_next(441) <= (not reset) and ( ( state_cur(433) and not ( in70 ) ) or ( state_cur(366) and in53 ) or state_cur(36) );
state_next(442) <= (not reset) and ( state_cur(153) );
state_next(443) <= (not reset) and ( state_cur(132) );
state_next(444) <= (not reset) and ( ( state_cur(66) and not ( in18 ) ) );
state_next(445) <= (not reset) and ( ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 1) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 1) ) );
state_next(446) <= (not reset) and ( ( state_cur(449) and not ( in73 ) ) or ( state_cur(448) and not ( in72 ) ) );
state_next(447) <= (not reset) and ( state_cur(450) );
state_next(448) <= (not reset) and ( ( state_cur(449) and in73 ) );
state_next(449) <= (not reset) and ( state_cur(447) or state_cur(363) );
state_next(450) <= (not reset) and ( ( state_cur(448) and in72 ) );
state_next(451) <= (not reset) and ( ( state_cur(452) and in75 ) );
state_next(452) <= (not reset) and ( state_cur(446) or state_cur(383) );
state_next(453) <= (not reset) and ( state_cur(123) );
state_next(454) <= (not reset) and ( state_cur(324) );
state_next(455) <= (not reset) and ( state_cur(222) );
state_next(456) <= (not reset) and ( state_cur(149) );
state_next(457) <= reset or ( ( state_cur(457) and not (in77) ) );
state_next(458) <= (not reset) and ( ( state_cur(407) and in58 ) );
state_next(459) <= (not reset) and ( ( state_cur(424) and in67 ) );
state_next(460) <= (not reset) and ( state_cur(459) );
state_next(461) <= (not reset) and ( ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 2) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 2) ) );
state_next(462) <= (not reset) and ( ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 3) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 3) ) );
state_next(463) <= (not reset) and ( state_cur(464) );
state_next(464) <= (not reset) and ( state_cur(144) );
state_next(465) <= (not reset) and ( state_cur(467) );
state_next(466) <= (not reset) and ( state_cur(437) );
state_next(467) <= (not reset) and ( state_cur(147) );
state_next(468) <= (not reset) and ( ( state_cur(414) and not ( in61 ) ) );
state_next(469) <= (not reset) and ( ( state_cur(411) and in60 ) );
state_next(470) <= (not reset) and ( ( state_cur(407) and not ( in58 ) ) );
state_next(471) <= (not reset) and ( ( state_cur(278) and to_stdl(funccall9 = 2) ) );
state_next(472) <= (not reset) and ( ( state_cur(403) and in57 ) );
state_next(473) <= (not reset) and ( state_cur(116) );
-- Assignment of buffers for buffered outputs
out1057_bufn <= state_cur(127) or state_cur(425);
out59_bufn <= state_cur(305) or state_cur(377);
out447_bufn <= state_cur(382) or state_cur(111);
out157_bufn <= state_cur(28) or state_cur(26) or ( state_cur(25) and not ( in6 ) );
out450_bufn <= state_cur(194) or state_cur(96);
out1012_bufn <= state_cur(221) or state_cur(291);
out1072_bufn <= state_cur(351) or state_cur(308);
out999_bufn <= state_cur(196) or state_cur(286);
out437_bufn <= state_cur(94) or state_cur(172);
out415_bufn <= state_cur(330) or state_cur(98);
out426_bufn <= state_cur(321) or state_cur(223) or state_cur(224) or state_cur(107);
out375_bufn <= state_cur(360) or state_cur(315);
out704_bufn <= state_cur(356) or state_cur(193) or state_cur(311) or state_cur(310) or state_cur(95) or state_cur(362);
out973_bufn <= state_cur(275) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 4) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 4) );
out11_bufn <= state_cur(222) or state_cur(153) or state_cur(181) or state_cur(109) or state_cur(364) or state_cur(120) or state_cur(215) or state_cur(394) or state_cur(231) or state_cur(201) or state_cur(228) or state_cur(33) or state_cur(352) or state_cur(117) or state_cur(1) or state_cur(162) or state_cur(400) or state_cur(442) or state_cur(150) or state_cur(358) or state_cur(203) or state_cur(189) or state_cur(279) or state_cur(274) or state_cur(272) or state_cur(198) or state_cur(232) or state_cur(280) or state_cur(233) or state_cur(225) or state_cur(230) or state_cur(218) or state_cur(227) or state_cur(226) or state_cur(367) or state_cur(370) or state_cur(373) or state_cur(62) or state_cur(344) or state_cur(182) or state_cur(359) or state_cur(204) or state_cur(118) or state_cur(371) or state_cur(343) or state_cur(336) or state_cur(455) or state_cur(88) or state_cur(361) or state_cur(156) or state_cur(335) or state_cur(151) or state_cur(166) or state_cur(119) or state_cur(180) or state_cur(337) or state_cur(347) or state_cur(345) or state_cur(199) or state_cur(436) or state_cur(112) or state_cur(208) or state_cur(369) or state_cur(385);
out549_bufn <= state_cur(87) or state_cur(465);
out453_bufn <= state_cur(304) or state_cur(380);
out1231_bufn <= state_cur(261) or state_cur(0) or state_cur(421) or state_cur(420) or state_cur(415) or state_cur(413) or state_cur(412) or state_cur(236) or state_cur(408) or state_cur(406) or state_cur(405) or state_cur(402) or state_cur(401) or state_cur(276);
out87_bufn <= state_cur(147) or state_cur(467) or state_cur(312) or state_cur(10) or state_cur(465) or state_cur(21) or state_cur(96) or state_cur(317) or state_cur(140);
out401_bufn <= state_cur(4) or state_cur(306);
out990_bufn <= state_cur(316) or state_cur(281);
out378_bufn <= state_cur(376) or state_cur(292);
out1302_bufn <= state_cur(132) or state_cur(443) or ( state_cur(157) and not ( in37 ) );
out27_bufn <= ( state_cur(448) and in72 ) or ( state_cur(433) and not ( in70 ) ) or ( state_cur(366) and in53 ) or state_cur(36) or state_cur(431) or ( state_cur(428) and not ( in69 ) ) or ( state_cur(427) and in68 ) or state_cur(193) or state_cur(311) or state_cur(310) or state_cur(95) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 4) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 4) ) or state_cur(362) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 0) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 0) ) or state_cur(186) or ( state_cur(126) and in32 ) or state_cur(136) or state_cur(135) or ( state_cur(64) and in17 ) or ( state_cur(45) and in12 ) or ( state_cur(77) and to_stdl(funccall3 = 1) ) or ( state_cur(75) and to_stdl(funccall3 = 1) ) or ( state_cur(77) and to_stdl(funccall3 = 3) ) or ( state_cur(75) and to_stdl(funccall3 = 3) ) or ( state_cur(2) and in0 );
out569_bufn <= ( state_cur(138) and not ( in35 ) ) or ( state_cur(207) and to_stdl(funccall1 = 5) );
out1030_bufn <= state_cur(438) or state_cur(101);
out537_bufn <= state_cur(293) or state_cur(110);
out77_bufn <= state_cur(144) or state_cur(464) or state_cur(143) or state_cur(155) or state_cur(114) or state_cur(313) or state_cur(309) or state_cur(308) or state_cur(108) or state_cur(304) or state_cur(434) or state_cur(301) or state_cur(103) or state_cur(101) or state_cur(298) or state_cur(297) or state_cur(100) or state_cur(97) or state_cur(294) or state_cur(293) or state_cur(94) or state_cur(291) or state_cur(91) or state_cur(289) or state_cur(288) or state_cur(287) or state_cur(286) or state_cur(285) or state_cur(284) or state_cur(90) or state_cur(92) or state_cur(281) or state_cur(84) or state_cur(277) or state_cur(269) or state_cur(268) or state_cur(267) or state_cur(58) or state_cur(85) or state_cur(9) or state_cur(463) or state_cur(111) or state_cur(314) or state_cur(307) or state_cur(104) or state_cur(300) or state_cur(102) or state_cur(106) or state_cur(299) or state_cur(98) or state_cur(290) or state_cur(296) or state_cur(295) or state_cur(93) or state_cur(99) or state_cur(292) or state_cur(315) or state_cur(89) or state_cur(283) or state_cur(282) or state_cur(302) or state_cur(56) or state_cur(266) or state_cur(327);
out1318_bufn <= ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 3) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 3) ) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 1) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 1) );
out533_bufn <= state_cur(219) or state_cur(9);
out32_bufn <= state_cur(305) or state_cur(176) or state_cur(317) or state_cur(377);
out1027_bufn <= state_cur(142) or state_cur(298);
out599_bufn <= ( state_cur(35) and to_stdl(funccall6 = 0) ) or state_cur(186) or ( state_cur(126) and in32 );
out668_bufn <= state_cur(84) or state_cur(456);
out568_bufn <= state_cur(261) or state_cur(0) or state_cur(421) or state_cur(420) or state_cur(415) or state_cur(413) or state_cur(412) or state_cur(236) or state_cur(401) or state_cur(276) or ( state_cur(207) and to_stdl(funccall1 = 4) ) or ( state_cur(207) and to_stdl(funccall1 = 5) );
out225_bufn <= ( state_cur(39) and not ( in9 ) ) or ( state_cur(53) and not ( in14 ) );
out700_bufn <= state_cur(143) or state_cur(473);
out638_bufn <= ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 4) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 4) ) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 0) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 0) );
out670_bufn <= state_cur(312) or state_cur(348);
out433_bufn <= state_cur(116) or state_cur(307);
out896_bufn <= ( state_cur(411) and in60 ) or ( state_cur(399) and in56 );
out575_bufn <= state_cur(163) or state_cur(11) or ( state_cur(160) and not ( in38 ) );
out428_bufn <= state_cur(197) or state_cur(104);
out72_bufn <= state_cur(144) or state_cur(464) or state_cur(143) or state_cur(155) or state_cur(114) or state_cur(313) or state_cur(309) or state_cur(308) or state_cur(108) or state_cur(304) or state_cur(434) or state_cur(301) or state_cur(103) or state_cur(101) or state_cur(298) or state_cur(297) or state_cur(100) or state_cur(97) or state_cur(294) or state_cur(293) or state_cur(94) or state_cur(291) or state_cur(91) or state_cur(289) or state_cur(288) or state_cur(287) or state_cur(286) or state_cur(285) or state_cur(284) or state_cur(90) or state_cur(92) or state_cur(281) or state_cur(84) or state_cur(277) or state_cur(269) or state_cur(268) or state_cur(267) or state_cur(58) or state_cur(85) or state_cur(9) or state_cur(463) or state_cur(111) or state_cur(314) or state_cur(307) or state_cur(104) or state_cur(300) or state_cur(102) or state_cur(106) or state_cur(299) or state_cur(98) or state_cur(290) or state_cur(296) or state_cur(295) or state_cur(93) or state_cur(99) or state_cur(292) or state_cur(315) or state_cur(89) or state_cur(283) or state_cur(282) or state_cur(302) or state_cur(56) or state_cur(266) or ( state_cur(82) and in24 ) or state_cur(327);
out404_bufn <= state_cur(115) or state_cur(312) or state_cur(185) or state_cur(176) or state_cur(194) or state_cur(348) or state_cur(96) or state_cur(317);
out98_bufn <= ( state_cur(396) and to_stdl(funccall0 = 15) ) or ( state_cur(396) and to_stdl(funccall0 = 16) );
out67_bufn <= ( state_cur(424) and in67 ) or ( state_cur(252) and not ( in49 ) ) or state_cur(202);
out635_bufn <= state_cur(165) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 0) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 0) );
out381_bufn <= state_cur(145) or state_cur(99);
out222_bufn <= ( state_cur(433) and not ( in70 ) ) or ( state_cur(366) and in53 ) or state_cur(36) or state_cur(41) or ( state_cur(64) and in17 ) or ( state_cur(53) and not ( in14 ) );
out339_bufn <= state_cur(273) or ( state_cur(76) and in22 ) or ( state_cur(76) and not ( in22 ) );
out268_bufn <= state_cur(41) or ( state_cur(53) and in14 );
out419_bufn <= state_cur(375) or state_cur(106);
out559_bufn <= ( state_cur(138) and not ( in35 ) ) or state_cur(353) or state_cur(214) or state_cur(152);
out1002_bufn <= state_cur(60) or state_cur(287);
out1006_bufn <= state_cur(37) or state_cur(289);
out276_bufn <= state_cur(318) or state_cur(266);
out205_bufn <= state_cur(116) or state_cur(149) or state_cur(334) or state_cur(387) or state_cur(60) or state_cur(342) or state_cur(196) or state_cur(195) or state_cur(216) or state_cur(351) or state_cur(381) or state_cur(355) or state_cur(375) or state_cur(221) or state_cur(368) or ( state_cur(82) and not ( in24 ) ) or state_cur(175) or state_cur(404) or state_cur(37) or state_cur(219) or state_cur(200) or state_cur(382) or state_cur(339) or state_cur(177) or state_cur(349) or state_cur(197) or state_cur(438) or state_cur(113) or state_cur(142) or state_cur(141) or state_cur(145) or state_cur(325) or state_cur(323) or state_cur(330) or state_cur(320) or state_cur(326) or state_cur(316) or state_cur(329) or state_cur(318) or state_cur(357) or state_cur(346) or state_cur(340) or state_cur(178) or state_cur(376) or state_cur(55) or state_cur(86) or state_cur(360) or state_cur(473) or state_cur(384) or state_cur(192) or state_cur(456) or state_cur(322) or state_cur(341) or state_cur(319) or state_cur(110) or state_cur(332) or state_cur(331) or state_cur(380) or state_cur(303) or state_cur(172) or state_cur(388) or state_cur(350) or state_cur(372) or state_cur(328);
out943_bufn <= state_cur(329) or state_cur(85);
out1080_bufn <= state_cur(193) or state_cur(311);
out408_bufn <= state_cur(322) or state_cur(295);
out252_bufn <= state_cur(431) or ( state_cur(428) and not ( in69 ) ) or ( state_cur(427) and in68 ) or ( state_cur(39) and not ( in9 ) ) or state_cur(426) or ( state_cur(45) and in12 );
out71_bufn <= state_cur(341) or state_cur(327);
out672_bufn <= state_cur(434) or state_cur(192);
out357_bufn <= state_cur(319) or state_cur(282);
out441_bufn <= state_cur(195) or state_cur(314);
out1084_bufn <= state_cur(387) or state_cur(313);
out144_bufn <= ( state_cur(78) and in23 ) or ( state_cur(73) and not ( in20 ) ) or ( state_cur(72) ) or ( state_cur(454) and in76 );
out574_bufn <= state_cur(184) or state_cur(154) or ( state_cur(170) and not ( in39 ) ) or ( state_cur(160) and not ( in38 ) );
out210_bufn <= ( state_cur(39) and not ( in9 ) ) or ( state_cur(40) and in10 );
out128_bufn <= state_cur(306) or ( state_cur(82) and in24 );
out360_bufn <= state_cur(288) or state_cur(388);
out948_bufn <= state_cur(141) or state_cur(58);
out506_bufn <= ( state_cur(453) and to_stdl(funccall4 = 1) ) or ( state_cur(131) and to_stdl(funccall4 = 1) ) or ( state_cur(70) and to_stdl(funccall4 = 1) ) or ( state_cur(453) and to_stdl(funccall4 = 0) ) or ( state_cur(131) and to_stdl(funccall4 = 0) ) or ( state_cur(70) and to_stdl(funccall4 = 0) );
out207_bufn <= state_cur(93) or state_cur(328);
out1083_bufn <= state_cur(342) or state_cur(309);
out491_bufn <= state_cur(146) or state_cur(171);
out4_bufn <= state_cur(147) or state_cur(467) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 3) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 3) ) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 2) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 2) ) or state_cur(446) or state_cur(383) or state_cur(447) or state_cur(363) or state_cur(450) or ( state_cur(449) and not ( in73 ) ) or ( state_cur(448) and not ( in72 ) ) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 1) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 1) ) or state_cur(132) or ( state_cur(433) and not ( in70 ) ) or ( state_cur(366) and in53 ) or state_cur(36) or state_cur(41) or state_cur(431) or ( state_cur(428) and not ( in69 ) ) or ( state_cur(427) and in68 ) or state_cur(146) or ( state_cur(265) and not ( not (in51) ) ) or ( state_cur(419) and in64 ) or ( state_cur(278) and to_stdl(funccall9 = 0) ) or ( state_cur(411) and not ( in60 ) ) or ( state_cur(278) and to_stdl(funccall9 = 1) ) or ( state_cur(439) and not ( in71 ) and to_stdl(funccall8 = 1) ) or ( state_cur(399) and not ( in56 ) ) or ( state_cur(396) and to_stdl(funccall0 = 0) ) or ( state_cur(338) and in52 ) or ( state_cur(251) and in48 ) or ( state_cur(249) and not ( in47 ) ) or ( state_cur(249) and in47 ) or ( state_cur(246) and not ( in46 ) ) or ( state_cur(243) ) or ( state_cur(242) ) or ( state_cur(238) ) or ( state_cur(237) ) or ( state_cur(212) and in43 ) or ( state_cur(211) ) or ( state_cur(207) and to_stdl(funccall1 = 0) ) or ( state_cur(207) and to_stdl(funccall1 = 3) ) or ( state_cur(179) and in40 ) or ( state_cur(170) and in39 ) or ( state_cur(160) and in38 ) or ( state_cur(148) and in36 ) or ( state_cur(137) and not ( in34 ) ) or ( state_cur(130) and not ( in33 ) ) or ( state_cur(130) and in33 ) or ( state_cur(390) and not ( in54 ) ) or ( state_cur(262) and not ( not (in50) ) ) or ( state_cur(428) and in69 ) or ( state_cur(43) and not ( in11 ) ) or ( state_cur(2) and not ( in0 ) ) or ( state_cur(396) and to_stdl(funccall0 = 5) ) or ( state_cur(244) ) or ( state_cur(137) and in34 ) or ( state_cur(126) and not ( in32 ) and not ( in31 ) and not ( in30 ) and not ( in29 ) and in28 ) or ( state_cur(126) and not ( in32 ) and not ( in31 ) and not ( in30 ) and in29 ) or ( state_cur(126) and not ( in32 ) and not ( in31 ) and in30 ) or ( state_cur(126) and not ( in32 ) and in31 ) or ( state_cur(105) and in25 ) or ( state_cur(78) and in23 ) or ( state_cur(73) and not ( in20 ) ) or ( state_cur(72) ) or state_cur(312) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 4) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 4) ) or ( state_cur(396) and to_stdl(funccall0 = 9) ) or state_cur(164) or state_cur(374) or state_cur(365) or ( state_cur(210) and in42 ) or ( state_cur(209) and not ( in41 ) ) or ( state_cur(210) and not ( in42 ) ) or state_cur(191) or state_cur(176) or state_cur(426) or state_cur(194) or state_cur(124) or state_cur(348) or ( state_cur(433) and in70 ) or ( state_cur(59) and not ( in16 ) ) or state_cur(87) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 0) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 0) ) or state_cur(10) or state_cur(465) or state_cur(21) or state_cur(136) or state_cur(135) or state_cur(171) or state_cur(354) or state_cur(183) or state_cur(96) or state_cur(317) or state_cur(122) or ( state_cur(80) and to_stdl(funccall2 = 2) ) or ( state_cur(79) and to_stdl(funccall2 = 2) ) or ( state_cur(64) and in17 ) or ( state_cur(64) and not ( in17 ) ) or ( state_cur(54) and not ( in15 ) ) or state_cur(430) or state_cur(52) or ( state_cur(45) and in12 ) or ( state_cur(45) and not ( in12 ) ) or ( state_cur(40) and not ( in10 ) ) or state_cur(188) or state_cur(38) or ( state_cur(121) and in26 ) or ( state_cur(454) and in76 ) or ( state_cur(17) and in3 ) or ( state_cur(82) and in24 ) or ( state_cur(396) and to_stdl(funccall0 = 15) ) or ( state_cur(396) and to_stdl(funccall0 = 16) ) or state_cur(140) or ( state_cur(252) and not ( in49 ) ) or state_cur(202) or ( state_cur(6) and in1 ) or ( state_cur(2) and in0 ) or ( state_cur(422) and in65 );
out784_bufn <= state_cur(115) or state_cur(185);
out3_bufn <= ( state_cur(419) and in64 ) or ( state_cur(278) and to_stdl(funccall9 = 0) ) or ( state_cur(278) and to_stdl(funccall9 = 1) ) or ( state_cur(439) and not ( in71 ) and to_stdl(funccall8 = 1) ) or ( state_cur(422) and in65 );
out746_bufn <= state_cur(247) or state_cur(239) or state_cur(213) or state_cur(205);
out528_bufn <= state_cur(297) or state_cur(332);
out372_bufn <= state_cur(381) or state_cur(89);
out418_bufn <= state_cur(334) or state_cur(299);
out708_bufn <= state_cur(285) or state_cur(86);
out706_bufn <= state_cur(193) or state_cur(362);
out445_bufn <= state_cur(267) or state_cur(303);
out1021_bufn <= state_cur(323) or state_cur(100);
out405_bufn <= state_cur(193) or state_cur(115) or state_cur(312) or state_cur(311) or state_cur(310) or state_cur(95) or state_cur(185) or state_cur(176) or state_cur(362) or state_cur(194) or state_cur(348) or state_cur(96) or state_cur(317);
out764_bufn <= state_cur(284) or state_cur(178);
out581_bufn <= state_cur(253) or state_cur(133);
out776_bufn <= state_cur(91) or state_cur(346);
out213_bufn <= state_cur(184) or state_cur(154) or state_cur(255) or state_cur(12) or state_cur(68) or state_cur(63) or state_cur(57) or state_cur(50) or state_cur(49) or state_cur(44) or state_cur(42) or state_cur(34);
out674_bufn <= state_cur(90) or state_cur(384);
out1326_bufn <= state_cur(447) or state_cur(363) or ( state_cur(449) and in73 );
out334_bufn <= ( state_cur(270) ) or ( state_cur(30) and in8 ) or ( state_cur(25) and in6 ) or ( state_cur(15) ) or ( state_cur(76) and in22 ) or ( state_cur(76) and not ( in22 ) ) or ( state_cur(74) and in21 );
out843_bufn <= state_cur(275) or state_cur(165);
out175_bufn <= state_cur(32) or state_cur(31) or ( state_cur(30) and not ( in8 ) );
out1036_bufn <= state_cur(355) or state_cur(301);
out1015_bufn <= state_cur(320) or state_cur(294);
out236_bufn <= state_cur(378) or state_cur(429) or ( state_cur(427) and not ( in68 ) );
out395_bufn <= ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 4) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 4) ) or state_cur(164) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 0) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 0) ) or state_cur(306);
out1340_bufn <= state_cur(446) or state_cur(383) or ( state_cur(452) and in75 );
out993_bufn <= state_cur(200) or state_cur(92);
out356_bufn <= state_cur(149) or state_cur(302);
out273_bufn <= state_cur(102) or state_cur(372);
out403_bufn <= state_cur(176) or state_cur(317);
out286_bufn <= state_cur(290) or state_cur(350);
out364_bufn <= state_cur(176) or state_cur(194) or state_cur(124) or state_cur(348) or state_cur(87) or state_cur(354) or state_cur(183) or state_cur(122);
out697_bufn <= state_cur(253) or state_cur(191) or ( state_cur(252) and in49 );
out283_bufn <= state_cur(174) or state_cur(441) or ( state_cur(366) and not ( in53 ) );
out282_bufn <= state_cur(331) or state_cur(56);
out1319_bufn <= ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 3) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 3) ) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 2) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 2) ) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 1) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 1) );
out409_bufn <= state_cur(326) or state_cur(296);
out1092_bufn <= state_cur(339) or state_cur(155);
out1075_bufn <= state_cur(356) or state_cur(95);
out925_bufn <= ( state_cur(51) and to_stdl(funccall5 = 0) ) or ( state_cur(35) and to_stdl(funccall6 = 1) );
out78_bufn <= state_cur(144) or state_cur(464) or state_cur(143) or state_cur(235) or state_cur(155) or state_cur(114) or state_cur(313) or state_cur(309) or state_cur(308) or state_cur(108) or state_cur(304) or state_cur(434) or state_cur(301) or state_cur(103) or state_cur(101) or state_cur(298) or state_cur(297) or state_cur(100) or state_cur(97) or state_cur(294) or state_cur(293) or state_cur(94) or state_cur(291) or state_cur(91) or state_cur(289) or state_cur(288) or state_cur(287) or state_cur(286) or state_cur(285) or state_cur(284) or state_cur(90) or state_cur(92) or state_cur(281) or state_cur(84) or state_cur(277) or state_cur(269) or state_cur(268) or state_cur(267) or state_cur(58) or state_cur(85) or state_cur(9) or state_cur(463) or state_cur(111) or state_cur(314) or state_cur(307) or state_cur(104) or state_cur(300) or state_cur(102) or state_cur(106) or state_cur(299) or state_cur(98) or state_cur(290) or state_cur(296) or state_cur(295) or state_cur(93) or state_cur(99) or state_cur(292) or state_cur(315) or state_cur(89) or state_cur(283) or state_cur(282) or state_cur(302) or state_cur(56) or state_cur(266) or state_cur(327);
out1089_bufn <= state_cur(368) or state_cur(114);
out362_bufn <= state_cur(124) or state_cur(87) or state_cur(171) or state_cur(354) or state_cur(183) or state_cur(122);
out982_bufn <= state_cur(357) or state_cur(277);
out979_bufn <= ( state_cur(82) and not ( in24 ) ) or state_cur(269);
out952_bufn <= state_cur(113) or state_cur(268);
out1109_bufn <= state_cur(464) or state_cur(177);
out16_bufn <= state_cur(459) or state_cur(440) or state_cur(220) or state_cur(161) or state_cur(139) or state_cur(83) or state_cur(16) or state_cur(19) or state_cur(18) or state_cur(14) or state_cur(7) or state_cur(5) or state_cur(8) or state_cur(3);
out703_bufn <= state_cur(310) or state_cur(362);
out371_bufn <= state_cur(216) or state_cur(283);
out956_bufn <= state_cur(271) or ( state_cur(256) ) or ( state_cur(254) );
out1107_bufn <= state_cur(144) or state_cur(349);
out1033_bufn <= state_cur(175) or state_cur(103);
out148_bufn <= state_cur(146) or ( state_cur(121) and in26 );
out351_bufn <= state_cur(321) or state_cur(223) or state_cur(224) or state_cur(107) or state_cur(83) or state_cur(16);
out740_bufn <= ( state_cur(396) and to_stdl(funccall0 = 0) ) or ( state_cur(338) and in52 ) or ( state_cur(251) and in48 ) or ( state_cur(249) and not ( in47 ) ) or ( state_cur(249) and in47 ) or ( state_cur(246) and not ( in46 ) ) or ( state_cur(243) ) or ( state_cur(242) ) or ( state_cur(238) ) or ( state_cur(237) ) or ( state_cur(212) and in43 ) or ( state_cur(211) ) or ( state_cur(207) and to_stdl(funccall1 = 0) ) or ( state_cur(207) and to_stdl(funccall1 = 3) ) or ( state_cur(179) and in40 ) or ( state_cur(170) and in39 ) or ( state_cur(160) and in38 ) or ( state_cur(148) and in36 ) or ( state_cur(137) and not ( in34 ) ) or ( state_cur(130) and not ( in33 ) ) or ( state_cur(130) and in33 ) or ( state_cur(396) and to_stdl(funccall0 = 5) ) or ( state_cur(244) ) or ( state_cur(137) and in34 ) or ( state_cur(126) and not ( in32 ) and not ( in31 ) and not ( in30 ) and not ( in29 ) and in28 ) or ( state_cur(126) and not ( in32 ) and not ( in31 ) and not ( in30 ) and in29 ) or ( state_cur(126) and not ( in32 ) and not ( in31 ) and in30 ) or ( state_cur(126) and not ( in32 ) and in31 ) or state_cur(365);
out391_bufn <= state_cur(127) or state_cur(4) or state_cur(425) or state_cur(306);
out129_bufn <= state_cur(356) or ( state_cur(82) and in24 );
out338_bufn <= ( state_cur(256) ) or ( state_cur(254) ) or ( state_cur(453) and to_stdl(funccall4 = 1) ) or ( state_cur(131) and to_stdl(funccall4 = 1) ) or ( state_cur(70) and to_stdl(funccall4 = 1) ) or state_cur(190) or state_cur(187) or state_cur(186) or ( state_cur(126) and in32 ) or ( state_cur(453) and to_stdl(funccall4 = 0) ) or ( state_cur(131) and to_stdl(funccall4 = 0) ) or ( state_cur(70) and to_stdl(funccall4 = 0) ) or state_cur(273) or ( state_cur(76) and in22 ) or ( state_cur(76) and not ( in22 ) );
out425_bufn <= state_cur(55) or state_cur(300);
out1078_bufn <= state_cur(311) or state_cur(310) or state_cur(95);
out349_bufn <= ( state_cur(80) and to_stdl(funccall2 = 1) ) or ( state_cur(79) and to_stdl(funccall2 = 1) ) or ( state_cur(80) and to_stdl(funccall2 = 0) ) or ( state_cur(79) and to_stdl(funccall2 = 0) );
out590_bufn <= state_cur(165) or state_cur(186) or ( state_cur(126) and in32 );
out325_bufn <= state_cur(273) or state_cur(432) or state_cur(71) or ( state_cur(80) and to_stdl(funccall2 = 2) ) or ( state_cur(79) and to_stdl(funccall2 = 2) );
out112_bufn <= state_cur(459) or state_cur(14) or state_cur(7) or state_cur(5);
out224_bufn <= ( state_cur(54) and in15 ) or ( state_cur(53) and not ( in14 ) );
out1220_bufn <= ( state_cur(265) and not ( not (in51) ) ) or ( state_cur(390) and not ( in54 ) );
out1250_bufn <= ( state_cur(407) and in58 ) or ( state_cur(414) and in61 );
out365_bufn <= ( state_cur(105) and in25 ) or state_cur(176) or state_cur(194) or state_cur(124) or state_cur(348) or state_cur(87) or state_cur(171) or state_cur(354) or state_cur(183) or state_cur(122);
out699_bufn <= ( state_cur(453) and to_stdl(funccall4 = 1) ) or ( state_cur(131) and to_stdl(funccall4 = 1) ) or ( state_cur(70) and to_stdl(funccall4 = 1) ) or state_cur(191) or ( state_cur(252) and in49 );
out488_bufn <= ( state_cur(105) and in25 ) or state_cur(171);
out1069_bufn <= state_cur(404) or state_cur(108);
out530_bufn <= state_cur(340) or state_cur(463);
out326_bufn <= ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 2) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 2) ) or ( state_cur(80) and to_stdl(funccall2 = 2) ) or ( state_cur(79) and to_stdl(funccall2 = 2) );
out602_bufn <= state_cur(255) or state_cur(12) or state_cur(163) or state_cur(11);
out83_bufn <= state_cur(147) or state_cur(467) or state_cur(146) or state_cur(10) or state_cur(465) or state_cur(21) or state_cur(140);
out311_bufn <= ( state_cur(433) and not ( in70 ) ) or ( state_cur(366) and in53 ) or state_cur(36) or state_cur(41) or ( state_cur(64) and in17 );
out253_bufn <= state_cur(431) or ( state_cur(428) and not ( in69 ) ) or ( state_cur(427) and in68 ) or state_cur(426) or ( state_cur(45) and in12 );
out209_bufn <= state_cur(426) or ( state_cur(39) and in9 );
out1240_bufn <= ( state_cur(417) and in63 ) or state_cur(410) or ( state_cur(417) and not ( in63 ) ) or state_cur(398);
out1018_bufn <= state_cur(325) or state_cur(97);
out1152_bufn <= state_cur(429) or state_cur(441);
out1236_bufn <= state_cur(408) or state_cur(406) or state_cur(405) or state_cur(402);
out130_bufn <= state_cur(356) or state_cur(186) or ( state_cur(126) and in32 ) or ( state_cur(82) and in24 );
out567_bufn <= ( state_cur(207) and to_stdl(funccall1 = 4) ) or ( state_cur(207) and to_stdl(funccall1 = 5) );
out646_bufn <= ( state_cur(29) and in7 ) or ( state_cur(24) and in5 );
-- Assignment of non-buffered outputs
out26 <=
state_cur(3);
out2 <=
state_cur(466) or state_cur(253) or state_cur(202) or state_cur(191) or state_cur(19) or state_cur(0);
out931 <=
state_cur(261);
out715 <=
state_cur(201);
out410 <=
state_cur(98);
out628 <=
state_cur(165);
out734 <=
state_cur(229) or state_cur(206);
out942 <=
state_cur(265);
out122 <=
state_cur(16);
out892 <=
state_cur(255);
out601 <=
state_cur(159);
out809 <=
state_cur(232);
out376 <=
state_cur(91);
out241 <=
state_cur(45);
out986 <=
state_cur(280);
out1323 <=
state_cur(446);
out455 <=
state_cur(117);
out53 <=
state_cur(377) or state_cur(354) or state_cur(306) or state_cur(305) or state_cur(140) or state_cur(4);
out733 <=
state_cur(206);
out229 <=
state_cur(41);
out901 <=
state_cur(469) or state_cur(462) or state_cur(461) or state_cur(445) or state_cur(257);
out60 <=
state_cur(425) or state_cur(377) or state_cur(306) or state_cur(305) or state_cur(127) or state_cur(4);
out228 <=
state_cur(444) or state_cur(441) or state_cur(430) or state_cur(68) or state_cur(67) or state_cur(57) or state_cur(41);
out160 <=
state_cur(25);
out561 <=
state_cur(150);
out743 <=
state_cur(208);
out921 <=
state_cur(259);
out382 <=
state_cur(93);
out566 <=
state_cur(151);
out99 <=
state_cur(255) or state_cur(163) or state_cur(12) or state_cur(11);
out765 <=
state_cur(217);
out366 <=
state_cur(88);
out1005 <=
state_cur(289);
out1119 <=
state_cur(345);
out1356 <=
state_cur(461);
out25 <=
state_cur(8) or state_cur(3);
out802 <=
state_cur(230);
out918 <=
state_cur(259) or state_cur(258);
out258 <=
state_cur(50);
out640 <=
state_cur(166);
out710 <=
state_cur(198);
out1014 <=
state_cur(294);
out505 <=
state_cur(443) or state_cur(437) or state_cur(133) or state_cur(132);
out1303 <=
state_cur(439);
out424 <=
state_cur(104);
out920 <=
state_cur(258);
out180 <=
state_cur(31);
out974 <=
state_cur(276);
out1339 <=
state_cur(450);
out300 <=
state_cur(64);
out472 <=
state_cur(123);
out143 <=
state_cur(324) or state_cur(20);
out1301 <=
state_cur(437);
out479 <=
state_cur(125);
out464 <=
state_cur(120);
out643 <=
state_cur(167);
out636 <=
state_cur(420) or state_cur(276) or state_cur(275) or state_cur(236) or state_cur(165);
out1022 <=
state_cur(297);
out153 <=
state_cur(23);
out263 <=
state_cur(51);
out690 <=
state_cur(213) or state_cur(187);
out712 <=
state_cur(199);
out828 <=
state_cur(235);
out772 <=
state_cur(220);
out342 <=
state_cur(76);
out40 <=
state_cur(465) or state_cur(425) or state_cur(306) or state_cur(127) or state_cur(87) or state_cur(4);
out1223 <=
state_cur(394);
out443 <=
state_cur(112);
out679 <=
state_cur(180);
out1073 <=
state_cur(309);
out150 <=
state_cur(21);
out299 <=
state_cur(68) or state_cur(63);
out1349 <=
state_cur(455);
out1383 <=
state_cur(471);
out572 <=
state_cur(153);
out1298 <=
state_cur(436);
out1311 <=
state_cur(442);
out607 <=
state_cur(161);
out737 <=
state_cur(207);
out510 <=
state_cur(396) or state_cur(365) or state_cur(207) or state_cur(134);
out165 <=
state_cur(28) or state_cur(26);
out462 <=
state_cur(119);
out514 <=
state_cur(136) or state_cur(135);
out531 <=
state_cur(143);
out872 <=
state_cur(243);
out791 <=
state_cur(226);
out417 <=
state_cur(101);
out297 <=
state_cur(63);
out1121 <=
state_cur(347);
out614 <=
state_cur(164);
out64 <=
state_cur(5);
out589 <=
state_cur(158);
out231 <=
state_cur(42);
out888 <=
state_cur(271) or state_cur(256) or state_cur(254);
out1324 <=
state_cur(447);
out1150 <=
state_cur(364);
out1295 <=
state_cur(435);
out152 <=
state_cur(159) or state_cur(22);
out310 <=
state_cur(444) or state_cur(67);
out694 <=
state_cur(189);
out718 <=
state_cur(202);
out759 <=
state_cur(214);
out722 <=
state_cur(203);
out1387 <=
state_cur(472);
out82 <=
state_cur(473) or state_cur(464) or state_cur(463) or state_cur(456) or state_cur(438) or state_cur(434) or state_cur(404) or state_cur(388) or
state_cur(387) or state_cur(384) or state_cur(382) or state_cur(381) or state_cur(380) or state_cur(376) or state_cur(375) or state_cur(372) or
state_cur(368) or state_cur(362) or state_cur(360) or state_cur(357) or state_cur(356) or state_cur(355) or state_cur(351) or state_cur(350) or
state_cur(349) or state_cur(348) or state_cur(346) or state_cur(342) or state_cur(341) or state_cur(340) or state_cur(339) or state_cur(334) or
state_cur(332) or state_cur(331) or state_cur(330) or state_cur(329) or state_cur(328) or state_cur(327) or state_cur(326) or state_cur(325) or
state_cur(323) or state_cur(322) or state_cur(321) or state_cur(320) or state_cur(319) or state_cur(318) or state_cur(317) or state_cur(316) or
state_cur(315) or state_cur(314) or state_cur(313) or state_cur(312) or state_cur(311) or state_cur(310) or state_cur(309) or state_cur(308) or
state_cur(307) or state_cur(304) or state_cur(303) or state_cur(302) or state_cur(301) or state_cur(300) or state_cur(299) or state_cur(298) or
state_cur(297) or state_cur(296) or state_cur(295) or state_cur(294) or state_cur(293) or state_cur(292) or state_cur(291) or state_cur(290) or
state_cur(289) or state_cur(288) or state_cur(287) or state_cur(286) or state_cur(285) or state_cur(284) or state_cur(283) or state_cur(282) or
state_cur(281) or state_cur(278) or state_cur(277) or state_cur(269) or state_cur(268) or state_cur(267) or state_cur(266) or state_cur(224) or
state_cur(221) or state_cur(219) or state_cur(216) or state_cur(200) or state_cur(197) or state_cur(196) or state_cur(195) or state_cur(194) or
state_cur(193) or state_cur(192) or state_cur(185) or state_cur(178) or state_cur(177) or state_cur(176) or state_cur(175) or state_cur(172) or
state_cur(155) or state_cur(149) or state_cur(145) or state_cur(144) or state_cur(143) or state_cur(142) or state_cur(141) or state_cur(116) or
state_cur(115) or state_cur(114) or state_cur(113) or state_cur(111) or state_cur(110) or state_cur(108) or state_cur(106) or state_cur(104) or
state_cur(103) or state_cur(102) or state_cur(101) or state_cur(100) or state_cur(99) or state_cur(98) or state_cur(97) or state_cur(96) or
state_cur(95) or state_cur(94) or state_cur(93) or state_cur(92) or state_cur(91) or state_cur(90) or state_cur(89) or state_cur(86) or
state_cur(85) or state_cur(84) or state_cur(60) or state_cur(58) or state_cur(56) or state_cur(55) or state_cur(37) or state_cur(16) or
state_cur(9);
out1139 <=
state_cur(361);
out558 <=
state_cur(147);
out696 <=
state_cur(190);
out1381 <=
state_cur(470);
out1293 <=
state_cur(435);
out519 <=
state_cur(139);
out1292 <=
state_cur(434);
out895 <=
state_cur(256);
out1176 <=
state_cur(429) or state_cur(379) or state_cur(378);
out170 <=
state_cur(173) or state_cur(27);
out434 <=
state_cur(109);
out341 <=
state_cur(77) or state_cur(75);
out1007 <=
state_cur(290);
out595 <=
state_cur(158);
out874 <=
state_cur(244);
out1364 <=
state_cur(464);
out621 <=
state_cur(164);
out962 <=
state_cur(273);
out767 <=
state_cur(374) or state_cur(220) or state_cur(217);
out523 <=
state_cur(139);
out350 <=
state_cur(81);
out745 <=
state_cur(209);
out863 <=
state_cur(241);
out958 <=
state_cur(272);
out1182 <=
state_cur(446) or state_cur(383);
out13 <=
state_cur(1);
out1 <=
state_cur(0);
out1101 <=
state_cur(336);
out1344 <=
state_cur(452);
out749 <=
state_cur(210);
out972 <=
state_cur(275);
out289 <=
state_cur(61);
out1290 <=
state_cur(432);
out985 <=
state_cur(279);
out279 <=
state_cur(57);
out517 <=
state_cur(138);
out1035 <=
state_cur(302);
out1000 <=
state_cur(287);
out1085 <=
state_cur(314);
out1289 <=
state_cur(431);
out85 <=
state_cur(377) or state_cur(305) or state_cur(124) or state_cur(10);
out35 <=
state_cur(306) or state_cur(183) or state_cur(171) or state_cur(147) or state_cur(146) or state_cur(4);
out304 <=
state_cur(65);
out347 <=
state_cur(80) or state_cur(79);
out1190 <=
state_cur(389);
out649 <=
state_cur(167);
out156 <=
state_cur(24);
out1228 <=
state_cur(396);
out266 <=
state_cur(51);
out651 <=
state_cur(168);
out866 <=
state_cur(242);
out508 <=
state_cur(133);
out1114 <=
state_cur(344);
out245 <=
state_cur(46);
out44 <=
state_cur(354) or state_cur(306) or state_cur(21) or state_cur(4);
out1174 <=
state_cur(431) or state_cur(378);
out80 <=
state_cur(9);
out134 <=
state_cur(17);
out1187 <=
state_cur(391) or state_cur(386);
out1032 <=
state_cur(301);
out1287 <=
state_cur(430);
out989 <=
state_cur(281);
out538 <=
state_cur(146);
out1104 <=
state_cur(337);
out981 <=
state_cur(278);
out1286 <=
state_cur(429);
out724 <=
state_cur(204);
out487 <=
state_cur(127);
out658 <=
state_cur(169);
out1215 <=
state_cur(393) or state_cur(390);
out407 <=
state_cur(97);
out534 <=
state_cur(144);
out1175 <=
state_cur(378);
out858 <=
state_cur(239);
out1284 <=
state_cur(429);
out402 <=
state_cur(356) or state_cur(171) or state_cur(146) or state_cur(95);
out755 <=
state_cur(212);
out255 <=
state_cur(48);
out93 <=
state_cur(11);
out467 <=
state_cur(122);
out379 <=
state_cur(92);
out664 <=
state_cur(174);
out429 <=
state_cur(106);
out322 <=
state_cur(123) or state_cur(81) or state_cur(71);
out949 <=
state_cur(268);
out826 <=
state_cur(389) or state_cur(235);
out681 <=
state_cur(181);
out905 <=
state_cur(462) or state_cur(461) or state_cur(445) or state_cur(257);
out15 <=
state_cur(2);
out794 <=
state_cur(227);
out795 <=
state_cur(228);
out139 <=
state_cur(19);
out193 <=
state_cur(35);
out1019 <=
state_cur(296);
out171 <=
state_cur(28);
out173 <=
state_cur(29);
out610 <=
state_cur(162);
out1279 <=
state_cur(427);
out440 <=
state_cur(111);
out480 <=
state_cur(134) or state_cur(125);
out860 <=
state_cur(239);
out1158 <=
state_cur(369);
out189 <=
state_cur(33);
out902 <=
state_cur(257);
out1134 <=
state_cur(358);
out799 <=
state_cur(229);
out955 <=
state_cur(270);
out1278 <=
state_cur(426);
out1098 <=
state_cur(335);
out963 <=
state_cur(274);
out373 <=
state_cur(90);
out728 <=
state_cur(213) or state_cur(205);
out1160 <=
state_cur(370);
out570 <=
state_cur(353) or state_cur(214) or state_cur(152);
out937 <=
state_cur(262);
out1275 <=
state_cur(426);
out114 <=
state_cur(14);
out812 <=
state_cur(233);
out787 <=
state_cur(225);
out7 <=
state_cur(421) or state_cur(420) or state_cur(415) or state_cur(413) or state_cur(412) or state_cur(408) or state_cur(406) or state_cur(405) or
state_cur(402) or state_cur(401) or state_cur(275) or state_cur(261) or state_cur(165) or state_cur(0);
out396 <=
state_cur(95);
out762 <=
state_cur(215);
out978 <=
state_cur(277);
out933 <=
state_cur(410) or state_cur(398) or state_cur(261);
out938 <=
state_cur(263);
out313 <=
state_cur(67);
out1131 <=
state_cur(356);
out778 <=
state_cur(222);
out848 <=
state_cur(236);
out882 <=
state_cur(251) or state_cur(250) or state_cur(248);
out1229 <=
state_cur(398);
out1180 <=
state_cur(450) or state_cur(383);
out1155 <=
state_cur(367);
out947 <=
state_cur(267);
out232 <=
state_cur(426) or state_cur(258) or state_cur(158) or state_cur(42);
out201 <=
state_cur(36);
out783 <=
state_cur(223);
out996 <=
state_cur(284);
out1094 <=
state_cur(333);
out420 <=
state_cur(102);
out107 <=
state_cur(12);
out1269 <=
state_cur(425);
out414 <=
state_cur(100);
out1011 <=
state_cur(292);
out333 <=
state_cur(123) or state_cur(72);
out296 <=
state_cur(62);
out335 <=
state_cur(73);
out726 <=
state_cur(205);
out1151 <=
state_cur(366);
out256 <=
state_cur(49);
out111 <=
state_cur(255) or state_cur(12);
out1068 <=
state_cur(307);
out202 <=
state_cur(174) or state_cur(36);
out1368 <=
state_cur(467);
out1181 <=
state_cur(383);
out1137 <=
state_cur(359);
out1308 <=
state_cur(441);
out768 <=
state_cur(218);
out500 <=
state_cur(131);
out14 <=
state_cur(455) or state_cur(442) or state_cur(436) or state_cur(400) or state_cur(394) or state_cur(385) or state_cur(373) or state_cur(370) or
state_cur(369) or state_cur(367) or state_cur(364) or state_cur(361) or state_cur(359) or state_cur(358) or state_cur(352) or state_cur(347) or
state_cur(345) or state_cur(344) or state_cur(343) or state_cur(337) or state_cur(336) or state_cur(335) or state_cur(280) or state_cur(279) or
state_cur(274) or state_cur(272) or state_cur(233) or state_cur(232) or state_cur(231) or state_cur(230) or state_cur(228) or state_cur(227) or
state_cur(226) or state_cur(225) or state_cur(223) or state_cur(222) or state_cur(218) or state_cur(215) or state_cur(208) or state_cur(204) or
state_cur(203) or state_cur(201) or state_cur(199) or state_cur(198) or state_cur(189) or state_cur(182) or state_cur(181) or state_cur(180) or
state_cur(166) or state_cur(162) or state_cur(156) or state_cur(153) or state_cur(151) or state_cur(150) or state_cur(120) or state_cur(119) or
state_cur(118) or state_cur(117) or state_cur(112) or state_cur(109) or state_cur(88) or state_cur(62) or state_cur(33) or state_cur(3) or
state_cur(1);
out1164 <=
state_cur(371);
out1125 <=
state_cur(352);
out1016 <=
state_cur(295);
out688 <=
state_cur(186);
out1026 <=
state_cur(299);
out1329 <=
state_cur(449);
out191 <=
state_cur(34);
out855 <=
state_cur(238);
out597 <=
state_cur(258) or state_cur(158);
out184 <=
state_cur(32) or state_cur(31);
out162 <=
state_cur(26);
out422 <=
state_cur(103);
out197 <=
state_cur(188) or state_cur(38) or state_cur(35);
out104 <=
state_cur(12);
out1266 <=
state_cur(423);
out117 <=
state_cur(15);
out1024 <=
state_cur(298);
out221 <=
state_cur(41);
out1088 <=
state_cur(315);
out1128 <=
state_cur(354);
out923 <=
state_cur(260) or state_cur(259);
out1029 <=
state_cur(300);
out137 <=
state_cur(19) or state_cur(18);
out515 <=
state_cur(136);
out991 <=
state_cur(282);
out1375 <=
state_cur(468);
out957 <=
state_cur(271);
out264 <=
state_cur(430) or state_cur(52) or state_cur(51);
out1262 <=
state_cur(421);
out663 <=
state_cur(173);
out1111 <=
state_cur(343);
out119 <=
state_cur(15);
out998 <=
state_cur(286);
out731 <=
state_cur(206);
out1366 <=
state_cur(466);
out320 <=
state_cur(453) or state_cur(131) or state_cur(70);
out208 <=
state_cur(38);
out994 <=
state_cur(283);
out136 <=
state_cur(18);
out1145 <=
state_cur(363);
out1126 <=
state_cur(353);
out478 <=
state_cur(124);
out753 <=
state_cur(211);
out1141 <=
state_cur(362);
out951 <=
state_cur(269);
out370 <=
state_cur(89);
out259 <=
state_cur(57) or state_cur(50);
out332 <=
state_cur(72);
out1370 <=
state_cur(472) or state_cur(468);
out281 <=
state_cur(58);
out234 <=
state_cur(429) or state_cur(426) or state_cur(379) or state_cur(188) or state_cur(49) or state_cur(48) or state_cur(42);
out314 <=
state_cur(68);
out1185 <=
state_cur(385);
out1353 <=
state_cur(459);
out907 <=
state_cur(257);
out1258 <=
state_cur(420);
out698 <=
state_cur(191);
out212 <=
state_cur(40);
out468 <=
state_cur(467) or state_cur(377) or state_cur(305) or state_cur(122);
out876 <=
state_cur(245);
out498 <=
state_cur(129);
out251 <=
state_cur(379) or state_cur(48);
out1009 <=
state_cur(291);
out656 <=
state_cur(168);
out612 <=
state_cur(163);
out177 <=
state_cur(30);
out944 <=
state_cur(266);
out894 <=
state_cur(255);
out928 <=
state_cur(261) or state_cur(260);
out267 <=
state_cur(52);
out384 <=
state_cur(94);
out1171 <=
state_cur(374);
out815 <=
state_cur(234);
out230 <=
state_cur(260) or state_cur(259) or state_cur(57) or state_cur(41);
out739 <=
state_cur(365) or state_cur(207);
out88 <=
state_cur(467) or state_cur(465) or state_cur(425) or state_cur(354) or state_cur(348) or state_cur(317) or state_cur(312) or state_cur(311) or
state_cur(310) or state_cur(194) or state_cur(193) or state_cur(185) or state_cur(183) or state_cur(176) or state_cur(171) or state_cur(147) or
state_cur(146) or state_cur(140) or state_cur(127) or state_cur(124) or state_cur(122) or state_cur(115) or state_cur(96) or state_cur(87) or
state_cur(21) or state_cur(10);
out997 <=
state_cur(285);
out1362 <=
state_cur(462);
out806 <=
state_cur(231);
out1037 <=
state_cur(304);
out1147 <=
state_cur(447) or state_cur(363);
out1253 <=
state_cur(471) or state_cur(470) or state_cur(458) or state_cur(418);
out1169 <=
state_cur(373);
out316 <=
state_cur(70);
out317 <=
state_cur(131) or state_cur(123) or state_cur(81) or state_cur(77) or state_cur(75) or state_cur(71) or state_cur(70);
out133 <=
state_cur(371) or state_cur(362) or state_cur(107) or state_cur(95) or state_cur(83) or state_cur(16);
out1252 <=
state_cur(418);
out1096 <=
state_cur(333);
out186 <=
state_cur(32);
out1346 <=
state_cur(453);
out1146 <=
state_cur(363);
out363 <=
state_cur(87);
out887 <=
state_cur(254);
out659 <=
state_cur(190) or state_cur(169);
out661 <=
state_cur(171);
out346 <=
state_cur(79);
out270 <=
state_cur(54);
out1363 <=
state_cur(463);
out886 <=
state_cur(253);
out1341 <=
state_cur(451);
out92 <=
state_cur(11);
out1213 <=
state_cur(390);
out324 <=
state_cur(71);
out578 <=
state_cur(156);
out344 <=
state_cur(77);
out929 <=
state_cur(260);
out355 <=
state_cur(84);
out953 <=
state_cur(270);
out146 <=
state_cur(324) or state_cur(261) or state_cur(20);
out1365 <=
state_cur(465);
out348 <=
state_cur(80);
out358 <=
state_cur(85);
out513 <=
state_cur(135);
out1217 <=
state_cur(391);
out305 <=
state_cur(67) or state_cur(65);
out903 <=
state_cur(461) or state_cur(257);
out239 <=
state_cur(44);
out497 <=
state_cur(134) or state_cur(129) or state_cur(128);
out1337 <=
state_cur(450);
out861 <=
state_cur(247) or state_cur(239);
out448 <=
state_cur(114);
out1070 <=
state_cur(308);
out527 <=
state_cur(140);
out247 <=
state_cur(47);
out1091 <=
state_cur(327);
out496 <=
state_cur(128);
out328 <=
state_cur(432) or state_cur(273) or state_cur(71);
out1186 <=
state_cur(386);
out1309 <=
state_cur(441);
out526 <=
state_cur(161) or state_cur(139);
out199 <=
state_cur(35);
out154 <=
state_cur(435) or state_cur(253) or state_cur(133) or state_cur(23);
out1243 <=
state_cur(410);
out55 <=
state_cur(377) or state_cur(306) or state_cur(305) or state_cur(4);
out1082 <=
state_cur(313);
out240 <=
state_cur(49) or state_cur(44);
out1320 <=
state_cur(445);
out458 <=
state_cur(118);
out879 <=
state_cur(247);
out936 <=
state_cur(264) or state_cur(263) or state_cur(262);
out84 <=
state_cur(10);
out1221 <=
state_cur(423) or state_cur(397) or state_cur(395) or state_cur(392);
out1003 <=
state_cur(288);
out192 <=
state_cur(42) or state_cur(34);
out692 <=
state_cur(188);
out852 <=
state_cur(237);
out275 <=
state_cur(56);
out775 <=
state_cur(440) or state_cur(220);
out412 <=
state_cur(99);
out306 <=
state_cur(66);
out1013 <=
state_cur(293);
out1235 <=
state_cur(400);
out577 <=
state_cur(184) or state_cur(163) or state_cur(154);
out1166 <=
state_cur(371);
out432 <=
state_cur(108);
out1327 <=
state_cur(448);
out1378 <=
state_cur(469);
out49 <=
state_cur(306) or state_cur(171) or state_cur(146) or state_cur(4);
out65 <=
state_cur(459) or state_cur(14) or state_cur(7) or state_cur(5);
out246 <=
state_cur(48) or state_cur(46);
out939 <=
state_cur(264);
out504 <=
state_cur(132);
out667 <=
state_cur(444) or state_cur(441) or state_cur(174);
out683 <=
state_cur(182);
out686 <=
state_cur(183);
-- Assignment of buffered outputs
out1057 <= out1057_buf;
out59 <= out59_buf;
out447 <= out447_buf;
out157 <= out157_buf;
out450 <= out450_buf;
out1012 <= out1012_buf;
out1072 <= out1072_buf;
out999 <= out999_buf;
out437 <= out437_buf;
out415 <= out415_buf;
out426 <= out426_buf;
out375 <= out375_buf;
out704 <= out704_buf;
out973 <= out973_buf;
out11 <= out11_buf;
out549 <= out549_buf;
out453 <= out453_buf;
out1231 <= out1231_buf;
out87 <= out87_buf;
out401 <= out401_buf;
out990 <= out990_buf;
out378 <= out378_buf;
out1302 <= out1302_buf;
out27 <= out27_buf;
out569 <= out569_buf;
out1030 <= out1030_buf;
out537 <= out537_buf;
out77 <= out77_buf;
out1318 <= out1318_buf;
out533 <= out533_buf;
out32 <= out32_buf;
out1027 <= out1027_buf;
out599 <= out599_buf;
out668 <= out668_buf;
out568 <= out568_buf;
out225 <= out225_buf;
out700 <= out700_buf;
out638 <= out638_buf;
out670 <= out670_buf;
out433 <= out433_buf;
out896 <= out896_buf;
out575 <= out575_buf;
out428 <= out428_buf;
out72 <= out72_buf;
out404 <= out404_buf;
out98 <= out98_buf;
out67 <= out67_buf;
out635 <= out635_buf;
out381 <= out381_buf;
out222 <= out222_buf;
out339 <= out339_buf;
out268 <= out268_buf;
out419 <= out419_buf;
out559 <= out559_buf;
out1002 <= out1002_buf;
out1006 <= out1006_buf;
out276 <= out276_buf;
out205 <= out205_buf;
out943 <= out943_buf;
out1080 <= out1080_buf;
out408 <= out408_buf;
out252 <= out252_buf;
out71 <= out71_buf;
out672 <= out672_buf;
out357 <= out357_buf;
out441 <= out441_buf;
out1084 <= out1084_buf;
out144 <= out144_buf;
out574 <= out574_buf;
out210 <= out210_buf;
out128 <= out128_buf;
out360 <= out360_buf;
out948 <= out948_buf;
out506 <= out506_buf;
out207 <= out207_buf;
out1083 <= out1083_buf;
out491 <= out491_buf;
out4 <= out4_buf;
out784 <= out784_buf;
out3 <= out3_buf;
out746 <= out746_buf;
out528 <= out528_buf;
out372 <= out372_buf;
out418 <= out418_buf;
out708 <= out708_buf;
out706 <= out706_buf;
out445 <= out445_buf;
out1021 <= out1021_buf;
out405 <= out405_buf;
out764 <= out764_buf;
out581 <= out581_buf;
out776 <= out776_buf;
out213 <= out213_buf;
out674 <= out674_buf;
out1326 <= out1326_buf;
out334 <= out334_buf;
out843 <= out843_buf;
out175 <= out175_buf;
out1036 <= out1036_buf;
out1015 <= out1015_buf;
out236 <= out236_buf;
out395 <= out395_buf;
out1340 <= out1340_buf;
out993 <= out993_buf;
out356 <= out356_buf;
out273 <= out273_buf;
out403 <= out403_buf;
out286 <= out286_buf;
out364 <= out364_buf;
out697 <= out697_buf;
out283 <= out283_buf;
out282 <= out282_buf;
out1319 <= out1319_buf;
out409 <= out409_buf;
out1092 <= out1092_buf;
out1075 <= out1075_buf;
out925 <= out925_buf;
out78 <= out78_buf;
out1089 <= out1089_buf;
out362 <= out362_buf;
out982 <= out982_buf;
out979 <= out979_buf;
out952 <= out952_buf;
out1109 <= out1109_buf;
out16 <= out16_buf;
out703 <= out703_buf;
out371 <= out371_buf;
out956 <= out956_buf;
out1107 <= out1107_buf;
out1033 <= out1033_buf;
out148 <= out148_buf;
out351 <= out351_buf;
out740 <= out740_buf;
out391 <= out391_buf;
out129 <= out129_buf;
out338 <= out338_buf;
out425 <= out425_buf;
out1078 <= out1078_buf;
out349 <= out349_buf;
out590 <= out590_buf;
out325 <= out325_buf;
out112 <= out112_buf;
out224 <= out224_buf;
out1220 <= out1220_buf;
out1250 <= out1250_buf;
out365 <= out365_buf;
out699 <= out699_buf;
out488 <= out488_buf;
out1069 <= out1069_buf;
out530 <= out530_buf;
out326 <= out326_buf;
out602 <= out602_buf;
out83 <= out83_buf;
out311 <= out311_buf;
out253 <= out253_buf;
out209 <= out209_buf;
out1240 <= out1240_buf;
out1018 <= out1018_buf;
out1152 <= out1152_buf;
out1236 <= out1236_buf;
out130 <= out130_buf;
out567 <= out567_buf;
out646 <= out646_buf;
end architecture;
| gpl-2.0 | 16d363fb81ceb407dc26a374a1f32203 | 0.638504 | 2.504639 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2880.vhd | 4 | 2,086 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2880.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b00x00p07n01i02880ent IS
procedure proc1(constant flag:in integer; variable ret:inout integer);
procedure proc1(constant flag:in integer; variable ret:inout integer) is
begin
if (flag = 0) then
ret:= -1;
else
proc1((flag-1),ret);
end if;
ret:= ret + 1;
end proc1;
END c02s01b00x00p07n01i02880ent;
ARCHITECTURE c02s01b00x00p07n01i02880arch OF c02s01b00x00p07n01i02880ent IS
BEGIN
TESTING: PROCESS
variable x:integer;
BEGIN
x:=99;
assert (x=99) report "Initialization of integer variables incorrect"
severity failure;
proc1(3,x);
assert NOT( x=3 )
report "***PASSED TEST: c02s01b00x00p07n01i02880"
severity NOTE;
assert ( x=3 )
report "***FAILED TEST: c02s01b00x00p07n01i02880 - Procedure resursion call test incorrect."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b00x00p07n01i02880arch;
| gpl-2.0 | 72008a2fc5e61a263179991d65cf00b0 | 0.667785 | 3.646853 | false | true | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/cos.vhd | 4 | 1,691 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity cos is
port ( theta : in real; result : out real );
end entity cos;
--------------------------------------------------
architecture series of cos is
begin
summation : process (theta) is
variable sum, term : real;
variable n : natural;
begin
sum := 1.0;
term := 1.0;
n := 0;
while abs term > abs (sum / 1.0E6) loop
n := n + 2;
term := (-term) * theta**2 / real(((n-1) * n));
sum := sum + term;
end loop;
result <= sum;
end process summation;
end architecture series;
architecture fixed_length_series of cos is
begin
summation : process (theta) is
variable sum, term : real;
begin
sum := 1.0;
term := 1.0;
for n in 1 to 9 loop
term := (-term) * theta**2 / real(((2*n-1) * 2*n));
sum := sum + term;
end loop;
result <= sum;
end process summation;
end architecture fixed_length_series;
| gpl-2.0 | c3d66c0a09cf11bdeff1e88f034d1ce7 | 0.636901 | 3.825792 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2305.vhd | 4 | 1,981 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2305.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p37n01i02305ent IS
END c07s02b06x00p37n01i02305ent;
ARCHITECTURE c07s02b06x00p37n01i02305arch OF c07s02b06x00p37n01i02305ent IS
BEGIN
TESTING: PROCESS
BEGIN
-- Test dividing the predefined type TIME.
assert ((1 hr / 1 min) = 60);
assert ((1 min / 1 sec) = 60);
wait for 5 sec;
assert NOT( ((1 hr / 1 min) = 60) and
((1 min / 1 sec) = 60) )
report "***PASSED TEST: c07s02b06x00p37n01i02305"
severity NOTE;
assert ( ((1 hr / 1 min) = 60) and
((1 min / 1 sec) = 60) )
report "***FAILED TEST: c07s02b06x00p37n01i02305 - Division of a physical type by another physical type (predefined TIME) test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p37n01i02305arch;
| gpl-2.0 | 0845a385f3888bae7defcda63f0869a7 | 0.640586 | 3.621572 | false | true | false | false |
lfmunoz/vhdl | ip_blocks/sip_router_async_s1d2_x4_b/src/fifo_async_fwft_64x513_v8_2/fifo_generator_v8_2.vhd | 1 | 341,898 | -------------------------------------------------------------------------------
--
-- FIFO Generator - VHDL Behavioral Model
--
-------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Filename: fifo_generator_v8_2.vhd
--
-- Author : Xilinx
--
-------------------------------------------------------------------------------
-- Structure:
--
-- fifo_generator_v8_2.vhd
-- |
-- +-fifo_generator_v8_2_conv
-- |
-- +-fifo_generator_v8_2_bhv_as
-- |
-- +-fifo_generator_v8_2_bhv_ss
-- |
-- +-fifo_generator_v8_2_bhv_preload0
--
-------------------------------------------------------------------------------
-- Description:
--
-- The VHDL behavioral model for the FIFO Generator.
--
-- The behavioral model has three parts:
-- - The behavioral model for independent clocks FIFOs (_as)
-- - The behavioral model for common clock FIFOs (_ss)
-- - The "preload logic" block which implements First-word Fall-through
--
-------------------------------------------------------------------------------
--#############################################################################
--#############################################################################
-- Independent Clocks FIFO Behavioral Model
--#############################################################################
--#############################################################################
-------------------------------------------------------------------------------
-- Library Declaration
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-------------------------------------------------------------------------------
-- Independent Clocks Entity Declaration - This is NOT the top-level entity
-------------------------------------------------------------------------------
ENTITY fifo_generator_v8_2_bhv_as IS
GENERIC (
---------------------------------------------------------------------------
-- Generic Declarations
---------------------------------------------------------------------------
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 2;
C_HAS_RST : integer := 1;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 2;
C_MEMORY_TYPE : integer := 1;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 0;
C_RD_DEPTH : integer := 256;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 0;
C_WR_DEPTH : integer := 256;
C_WR_PNTR_WIDTH : integer := 8;
C_TCQ : time := 100 ps;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0
);
PORT(
---------------------------------------------------------------------------
-- Input and Output Declarations
---------------------------------------------------------------------------
RST : IN std_logic;
RST_FULL_GEN : IN std_logic := '0';
RST_FULL_FF : IN std_logic := '0';
WR_RST : IN std_logic;
RD_RST : IN std_logic;
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0);
RD_CLK : IN std_logic;
RD_EN : IN std_logic;
RD_EN_USER : IN std_logic;
WR_CLK : IN std_logic;
WR_EN : IN std_logic;
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
USER_EMPTY_FB : IN std_logic := '1';
EMPTY : OUT std_logic := '1';
FULL : OUT std_logic := '0';
ALMOST_EMPTY : OUT std_logic := '1';
ALMOST_FULL : OUT std_logic := '0';
PROG_EMPTY : OUT std_logic := '1';
PROG_FULL : OUT std_logic := '0';
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
VALID : OUT std_logic := '0';
WR_ACK : OUT std_logic := '0';
UNDERFLOW : OUT std_logic := '0';
OVERFLOW : OUT std_logic := '0';
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SBITERR : OUT std_logic := '0';
DBITERR : OUT std_logic := '0'
);
END fifo_generator_v8_2_bhv_as;
-------------------------------------------------------------------------------
-- Architecture Heading
-------------------------------------------------------------------------------
ARCHITECTURE behavioral OF fifo_generator_v8_2_bhv_as IS
-----------------------------------------------------------------------------
-- FUNCTION actual_fifo_depth
-- Returns the actual depth of the FIFO (may differ from what the user
-- specified)
--
-- The FIFO depth is always represented as 2^n (16,32,64,128,256)
-- However, the ACTUAL fifo depth may be 2^n+1 or 2^n-1 depending on certain
-- options. This function returns the actual depth of the fifo, as seen by
-- the user.
-------------------------------------------------------------------------------
FUNCTION actual_fifo_depth(
C_FIFO_DEPTH : integer;
C_PRELOAD_REGS : integer;
C_PRELOAD_LATENCY : integer)
RETURN integer IS
BEGIN
RETURN C_FIFO_DEPTH - 1;
END actual_fifo_depth;
-----------------------------------------------------------------------------
-- FUNCTION div_roundup
-- Returns data_value / divisor, with the result rounded-up (if fractional)
-------------------------------------------------------------------------------
FUNCTION divroundup (
data_value : integer;
divisor : integer)
RETURN integer IS
VARIABLE div : integer;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
-----------------------------------------------------------------------------
-- FUNCTION int_2_std_logic
-- Returns a single bit (as std_logic) from an integer 1/0 value.
-------------------------------------------------------------------------------
FUNCTION int_2_std_logic(value : integer) RETURN std_logic IS
BEGIN
IF (value=1) THEN
RETURN '1';
ELSE
RETURN '0';
END IF;
END int_2_std_logic;
-----------------------------------------------------------------------------
-- FUNCTION if_then_else
-- Returns a true case or flase case based on the condition
-------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : integer;
false_case : integer)
RETURN integer IS
VARIABLE retval : integer := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-----------------------------------------------------------------------------
-- FUNCTION hexstr_to_std_logic_vec
-- Returns a std_logic_vector for a hexadecimal string
-------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
-----------------------------------------------------------------------------
-- FUNCTION get_lesser
-- Returns a minimum value
-------------------------------------------------------------------------------
FUNCTION get_lesser(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a < b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
-----------------------------------------------------------------------------
-- Derived Constants
-----------------------------------------------------------------------------
CONSTANT C_FIFO_WR_DEPTH : integer
:= actual_fifo_depth(C_WR_DEPTH, C_PRELOAD_REGS, C_PRELOAD_LATENCY);
CONSTANT C_FIFO_RD_DEPTH : integer
:= actual_fifo_depth(C_RD_DEPTH, C_PRELOAD_REGS, C_PRELOAD_LATENCY);
CONSTANT C_SMALLER_DATA_WIDTH : integer
:= get_lesser(C_DIN_WIDTH, C_DOUT_WIDTH);
CONSTANT C_DEPTH_RATIO_WR : integer
:= if_then_else( (C_WR_DEPTH > C_RD_DEPTH), (C_WR_DEPTH/C_RD_DEPTH), 1);
CONSTANT C_DEPTH_RATIO_RD : integer
:= if_then_else( (C_RD_DEPTH > C_WR_DEPTH), (C_RD_DEPTH/C_WR_DEPTH), 1);
-- "Extra Words" is the number of write words which fit into the two
-- first-word fall-through output register stages (if using FWFT).
-- For ratios of 1:4 and 1:8, the fractional result is rounded up to 1.
-- This value is used to calculate the adjusted PROG_FULL threshold
-- value for FWFT.
-- EXTRA_WORDS = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD
-- WR_DEPTH : RD_DEPTH = 1:2 => EXTRA_WORDS = 1
-- WR_DEPTH : RD_DEPTH = 1:4 => EXTRA_WORDS = 1 (rounded to ceiling)
-- WR_DEPTH : RD_DEPTH = 2:1 => EXTRA_WORDS = 4
-- WR_DEPTH : RD_DEPTH = 4:1 => EXTRA_WORDS = 8
CONSTANT EXTRA_WORDS : integer := divroundup(2 * C_DEPTH_RATIO_WR, C_DEPTH_RATIO_RD);
-- "Extra words dc" is used for calculating the adjusted WR_DATA_COUNT
-- value for the core when using FWFT.
-- extra_words_dc = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD
-- C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
-- -----------------|------------------|-----------------|---------------
-- 1 | 8 | C_RD_PNTR_WIDTH | 2
-- 1 | 4 | C_RD_PNTR_WIDTH | 2
-- 1 | 2 | C_RD_PNTR_WIDTH | 2
-- 1 | 1 | C_WR_PNTR_WIDTH | 2
-- 2 | 1 | C_WR_PNTR_WIDTH | 4
-- 4 | 1 | C_WR_PNTR_WIDTH | 8
-- 8 | 1 | C_WR_PNTR_WIDTH | 16
CONSTANT EXTRA_WORDS_DC : integer
:= if_then_else ((C_DEPTH_RATIO_WR = 1),2,
(2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD));
CONSTANT C_PE_THR_ASSERT_ADJUSTED : integer
:=if_then_else((C_PRELOAD_REGS=1 and C_PRELOAD_LATENCY=0),
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2, --FWFT
C_PROG_EMPTY_THRESH_ASSERT_VAL ); --NO FWFT
CONSTANT C_PE_THR_NEGATE_ADJUSTED : integer
:=if_then_else((C_PRELOAD_REGS=1 and C_PRELOAD_LATENCY=0),
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2, --FWFT
C_PROG_EMPTY_THRESH_NEGATE_VAL); --NO FWFT
CONSTANT C_PE_THR_ASSERT_VAL_I : integer := C_PE_THR_ASSERT_ADJUSTED;
CONSTANT C_PE_THR_NEGATE_VAL_I : integer := C_PE_THR_NEGATE_ADJUSTED;
CONSTANT C_PF_THR_ASSERT_ADJUSTED : integer
:=if_then_else((C_PRELOAD_REGS=1 and C_PRELOAD_LATENCY=0),
C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC, --FWFT
C_PROG_FULL_THRESH_ASSERT_VAL ); --NO FWFT
CONSTANT C_PF_THR_NEGATE_ADJUSTED : integer
:=if_then_else((C_PRELOAD_REGS=1 and C_PRELOAD_LATENCY=0),
C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC, --FWFT
C_PROG_FULL_THRESH_NEGATE_VAL); --NO FWFT
-- NO_ERR_INJECTION will be 1 if ECC is OFF or ECC is ON but no error
-- injection is selected.
CONSTANT NO_ERR_INJECTION : integer
:= if_then_else(C_USE_ECC = 0,1,
if_then_else(C_ERROR_INJECTION_TYPE = 0,1,0));
-- SBIT_ERR_INJECTION will be 1 if ECC is ON and single bit error injection
-- is selected.
CONSTANT SBIT_ERR_INJECTION : integer
:= if_then_else((C_USE_ECC = 1 AND C_ERROR_INJECTION_TYPE = 1),1,0);
-- DBIT_ERR_INJECTION will be 1 if ECC is ON and double bit error injection
-- is selected.
CONSTANT DBIT_ERR_INJECTION : integer
:= if_then_else((C_USE_ECC = 1 AND C_ERROR_INJECTION_TYPE = 2),1,0);
-- BOTH_ERR_INJECTION will be 1 if ECC is ON and both single and double bit
-- error injection are selected.
CONSTANT BOTH_ERR_INJECTION : integer
:= if_then_else((C_USE_ECC = 1 AND C_ERROR_INJECTION_TYPE = 3),1,0);
CONSTANT C_DATA_WIDTH : integer := if_then_else(NO_ERR_INJECTION = 1, C_DIN_WIDTH, C_DIN_WIDTH+2);
-------------------------------------------------------------------------------
-- Signals Declaration
-------------------------------------------------------------------------------
SIGNAL wr_point : integer := 0;
SIGNAL rd_point : integer := 0;
SIGNAL wr_point_d1 : integer := 0;
SIGNAL rd_point_d1 : integer := 0;
SIGNAL num_wr_words : integer := 0;
SIGNAL num_rd_words : integer := 0;
SIGNAL adj_wr_point : integer := 0;
SIGNAL adj_rd_point : integer := 0;
SIGNAL adj_wr_point_d1: integer := 0;
SIGNAL adj_rd_point_d1: integer := 0;
SIGNAL wr_rst_i : std_logic := '0';
SIGNAL rd_rst_i : std_logic := '0';
SIGNAL wr_rst_d1 : std_logic := '0';
SIGNAL wr_ack_i : std_logic := '0';
SIGNAL overflow_i : std_logic := '0';
SIGNAL valid_i : std_logic := '0';
SIGNAL valid_d1 : std_logic := '0';
SIGNAL valid_out : std_logic := '0';
SIGNAL underflow_i : std_logic := '0';
SIGNAL prog_full_reg : std_logic := '0';
SIGNAL prog_empty_reg : std_logic := '1';
SIGNAL dout_i : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SIGNAL width_gt1 : std_logic := '0';
SIGNAL sbiterr_i : std_logic := '0';
SIGNAL dbiterr_i : std_logic := '0';
SIGNAL wr_pntr : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd1 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd2 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd3 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL adj_wr_pntr_rd : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_data_count_int : std_logic_vector(C_WR_PNTR_WIDTH DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wdc_fwft_ext_as : std_logic_vector(C_WR_PNTR_WIDTH DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rdc_fwft_ext_as : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0)
:= (OTHERS => '0');
SIGNAL rd_pntr : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr_d1 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr_d2 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr_d3 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr_d4 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL adj_rd_pntr_wr : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_data_count_int : std_logic_vector(C_RD_PNTR_WIDTH DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL empty_int : boolean := TRUE;
SIGNAL empty_comb : std_logic := '1';
SIGNAL ram_rd_en : std_logic := '0';
SIGNAL ram_rd_en_d1 : std_logic := '0';
SIGNAL empty_comb_d1 : std_logic := '1';
SIGNAL almost_empty_int : boolean := TRUE;
SIGNAL full_int : boolean := FALSE;
SIGNAL full_comb : std_logic := '0';
SIGNAL ram_wr_en : std_logic := '0';
SIGNAL almost_full_int : boolean := FALSE;
SIGNAL rd_fwft_cnt : std_logic_vector(3 downto 0) := (others=>'0');
SIGNAL stage1_valid : std_logic := '0';
SIGNAL stage2_valid : std_logic := '0';
SIGNAL diff_pntr_wr : integer := 0;
SIGNAL diff_pntr_rd : integer := 0;
SIGNAL pf_input_thr_assert_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL pf_input_thr_negate_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
-------------------------------------------------------------------------------
--Linked List types
-------------------------------------------------------------------------------
TYPE listtyp;
TYPE listptr IS ACCESS listtyp;
TYPE listtyp IS RECORD
data : std_logic_vector(C_SMALLER_DATA_WIDTH + 1 DOWNTO 0);
older : listptr;
newer : listptr;
END RECORD;
-------------------------------------------------------------------------------
--Processes for linked list implementation. The functions are
--1. "newlist" - Create a new linked list
--2. "add" - Add a data element to a linked list
--3. "read" - Read the data from the tail of the linked list
--4. "remove" - Remove the tail from the linked list
--5. "sizeof" - Calculate the size of the linked list
-------------------------------------------------------------------------------
--1. Create a new linked list
PROCEDURE newlist (
head : INOUT listptr;
tail : INOUT listptr;
cntr : INOUT integer) IS
BEGIN
head := NULL;
tail := NULL;
cntr := 0;
END;
--2. Add a data element to a linked list
PROCEDURE add (
head : INOUT listptr;
tail : INOUT listptr;
data : IN std_logic_vector;
cntr : INOUT integer;
inj_err : IN std_logic_vector(2 DOWNTO 0)
) IS
VARIABLE oldhead : listptr;
VARIABLE newhead : listptr;
VARIABLE corrupted_data : std_logic_vector(1 DOWNTO 0);
BEGIN
--------------------------------------------------------------------------
--a. Create a pointer to the existing head, if applicable
--b. Create a new node for the list
--c. Make the new node point to the old head
--d. Make the old head point back to the new node (for doubly-linked list)
--e. Put the data into the new head node
--f. If the new head we just created is the only node in the list,
-- make the tail point to it
--g. Return the new head pointer
--------------------------------------------------------------------------
IF (head /= NULL) THEN
oldhead := head;
END IF;
newhead := NEW listtyp;
newhead.older := oldhead;
IF (head /= NULL) THEN
oldhead.newer := newhead;
END IF;
CASE (inj_err(1 DOWNTO 0)) IS
-- For both error injection, pass only the double bit error injection
-- as dbit error has priority over single bit error injection
WHEN "11" => newhead.data := inj_err(1) & '0' & data;
WHEN "10" => newhead.data := inj_err(1) & '0' & data;
WHEN "01" => newhead.data := '0' & inj_err(0) & data;
WHEN OTHERS => newhead.data := '0' & '0' & data;
END CASE;
-- Increment the counter when data is added to the list
cntr := cntr + 1;
IF (newhead.older = NULL) THEN
tail := newhead;
END IF;
head := newhead;
END;
--3. Read the data from the tail of the linked list
PROCEDURE read (
tail : INOUT listptr;
data : OUT std_logic_vector;
err_type : OUT std_logic_vector(1 DOWNTO 0)
) IS
VARIABLE data_int : std_logic_vector(C_SMALLER_DATA_WIDTH + 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE err_type_int : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
BEGIN
data_int := tail.data;
-- MSB two bits carry the error injection type.
err_type_int := data_int(data_int'high DOWNTO C_SMALLER_DATA_WIDTH);
IF (err_type_int(1) = '0') THEN
data := data_int(C_SMALLER_DATA_WIDTH - 1 DOWNTO 0);
ELSIF (C_DOUT_WIDTH = 2) THEN
data := NOT data_int(C_SMALLER_DATA_WIDTH - 1 DOWNTO 0);
ELSIF (C_DOUT_WIDTH > 2) THEN
data := NOT data_int(data_int'high-2) & NOT data_int(data_int'high-3) &
data_int(data_int'high-4 DOWNTO 0);
ELSE
data := data_int(C_SMALLER_DATA_WIDTH - 1 DOWNTO 0);
END IF;
err_type := err_type_int;
END;
--4. Remove the tail from the linked list
PROCEDURE remove (
head : INOUT listptr;
tail : INOUT listptr;
cntr : INOUT integer) IS
VARIABLE oldtail : listptr;
VARIABLE newtail : listptr;
BEGIN
--------------------------------------------------------------------------
--Make a copy of the old tail pointer
--a. If there is no newer node, then set the tail pointer to nothing
-- (list is empty)
-- otherwise, make the next newer node the new tail, and make it point
-- to nothing older
--b. Clean up the memory for the old tail node
--c. If the new tail is nothing, then we have an empty list, and head
-- should also be set to nothing
--d. Return the new tail
--------------------------------------------------------------------------
oldtail := tail;
IF (oldtail.newer = NULL) THEN
newtail := NULL;
ELSE
newtail := oldtail.newer;
newtail.older := NULL;
END IF;
DEALLOCATE(oldtail);
IF (newtail = NULL) THEN
head := NULL;
END IF;
tail := newtail;
-- Decrement the counter when data is removed from the list
cntr := cntr - 1;
END;
--5. Calculate the size of the linked list
PROCEDURE sizeof (head : INOUT listptr; size : OUT integer) IS
VARIABLE curlink : listptr;
VARIABLE tmpsize : integer := 0;
BEGIN
--------------------------------------------------------------------------
--a. If head is null, then there is nothing in the list to traverse
-- start with the head node (which implies at least one node exists)
-- Loop through each node until you find the one that points to nothing
-- (the tail)
--b. Return the number of nodes
--------------------------------------------------------------------------
IF (head /= NULL) THEN
curlink := head;
tmpsize := 1;
WHILE (curlink.older /= NULL) LOOP
tmpsize := tmpsize + 1;
curlink := curlink.older;
END LOOP;
END IF;
size := tmpsize;
END;
-----------------------------------------------------------------------------
-- converts integer to specified length std_logic_vector : dropping least
-- significant bits if integer is bigger than what can be represented by
-- the vector
-----------------------------------------------------------------------------
FUNCTION count(
fifo_count : IN integer;
pointer_width : IN integer;
counter_width : IN integer)
RETURN std_logic_vector IS
VARIABLE temp : std_logic_vector(pointer_width-1 DOWNTO 0)
:= (OTHERS => '0');
VARIABLE output : std_logic_vector(counter_width - 1 DOWNTO 0)
:= (OTHERS => '0');
BEGIN
temp := CONV_STD_LOGIC_VECTOR(fifo_count, pointer_width);
IF (counter_width <= pointer_width) THEN
output := temp(pointer_width - 1 DOWNTO pointer_width - counter_width);
ELSE
output := temp(counter_width - 1 DOWNTO 0);
END IF;
RETURN output;
END count;
-------------------------------------------------------------------------------
-- architecture begins here
-------------------------------------------------------------------------------
BEGIN
-------------------------------------------------------------------------------
-- Asynchronous FIFO
-------------------------------------------------------------------------------
gnll_afifo: IF (C_FIFO_TYPE /= 3) GENERATE
wr_pntr <= conv_std_logic_vector(wr_point,C_WR_PNTR_WIDTH);
rd_pntr <= conv_std_logic_vector(rd_point,C_RD_PNTR_WIDTH);
wr_rst_i <= WR_RST;
rd_rst_i <= RD_RST;
-------------------------------------------------------------------------------
-- calculate number of words in wr and rd domain according to the deepest port
--
-- These steps circumvent the linked-list data structure and keep track of
-- wr_point and rd_point pointers much like the core itself does. The behavioral
-- model uses these to calculate WR_DATA_COUNT and RD_DATA_COUNT. This was done
-- because the sizeof() function always returns the exact number of words in
-- the linked list, and can not account for delays when crossing clock domains.
-------------------------------------------------------------------------------
adj_wr_point <= wr_point * C_DEPTH_RATIO_RD;
adj_rd_point <= rd_point * C_DEPTH_RATIO_WR;
adj_wr_point_d1<= wr_point_d1 * C_DEPTH_RATIO_RD;
adj_rd_point_d1<= rd_point_d1 * C_DEPTH_RATIO_WR;
width_gt1 <= '1' WHEN (C_DIN_WIDTH = 2) ELSE '0';
PROCESS (adj_wr_point, adj_wr_point_d1, adj_rd_point, adj_rd_point_d1)
BEGIN
IF (adj_wr_point >= adj_rd_point_d1) THEN
num_wr_words <= adj_wr_point - adj_rd_point_d1;
ELSE
num_wr_words <= C_WR_DEPTH*C_DEPTH_RATIO_RD + adj_wr_point - adj_rd_point_d1;
END IF;
IF (adj_wr_point_d1 >= adj_rd_point) THEN
num_rd_words <= adj_wr_point_d1 - adj_rd_point;
ELSE
num_rd_words <= C_RD_DEPTH*C_DEPTH_RATIO_WR + adj_wr_point_d1 - adj_rd_point;
END IF;
END PROCESS;
-------------------------------------------------------------------------------
--Calculate WR_ACK based on C_WR_ACK_LOW parameters
-------------------------------------------------------------------------------
gwalow : IF (C_WR_ACK_LOW = 0) GENERATE
WR_ACK <= wr_ack_i;
END GENERATE gwalow;
gwahgh : IF (C_WR_ACK_LOW = 1) GENERATE
WR_ACK <= NOT wr_ack_i;
END GENERATE gwahgh;
-------------------------------------------------------------------------------
--Calculate OVERFLOW based on C_OVERFLOW_LOW parameters
-------------------------------------------------------------------------------
govlow : IF (C_OVERFLOW_LOW = 0) GENERATE
OVERFLOW <= overflow_i;
END GENERATE govlow;
govhgh : IF (C_OVERFLOW_LOW = 1) GENERATE
OVERFLOW <= NOT overflow_i;
END GENERATE govhgh;
-------------------------------------------------------------------------------
--Calculate VALID based on C_VALID_LOW
-------------------------------------------------------------------------------
gnvl : IF (C_VALID_LOW = 0) GENERATE
VALID <= valid_out;
END GENERATE gnvl;
gnvh : IF (C_VALID_LOW = 1) GENERATE
VALID <= NOT valid_out;
END GENERATE gnvh;
-------------------------------------------------------------------------------
--Calculate UNDERFLOW based on C_UNDERFLOW_LOW
-------------------------------------------------------------------------------
gnul : IF (C_UNDERFLOW_LOW = 0) GENERATE
UNDERFLOW <= underflow_i;
END GENERATE gnul;
gnuh : IF (C_UNDERFLOW_LOW = 1) GENERATE
UNDERFLOW <= NOT underflow_i;
END GENERATE gnuh;
-------------------------------------------------------------------------------
--Assign PROG_FULL and PROG_EMPTY
-------------------------------------------------------------------------------
PROG_FULL <= prog_full_reg;
PROG_EMPTY <= prog_empty_reg;
-------------------------------------------------------------------------------
--Assign RD_DATA_COUNT and WR_DATA_COUNT
-------------------------------------------------------------------------------
rdc: IF (C_HAS_RD_DATA_COUNT=1) GENERATE
grdc_fwft_ext: IF (C_USE_FWFT_DATA_COUNT = 1) GENERATE
RD_DATA_COUNT <= rdc_fwft_ext_as(C_RD_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH);
END GENERATE grdc_fwft_ext;
gnrdc_fwft_ext: IF (C_USE_FWFT_DATA_COUNT = 0) GENERATE
RD_DATA_COUNT <= rd_data_count_int(C_RD_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH);
END GENERATE gnrdc_fwft_ext;
END GENERATE rdc;
nrdc: IF (C_HAS_RD_DATA_COUNT=0) GENERATE
RD_DATA_COUNT <= (OTHERS=>'0');
END GENERATE nrdc;
wdc: IF (C_HAS_WR_DATA_COUNT = 1) GENERATE
gwdc_fwft_ext: IF (C_USE_FWFT_DATA_COUNT = 1) GENERATE
WR_DATA_COUNT <= wdc_fwft_ext_as(C_WR_PNTR_WIDTH DOWNTO C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH);
END GENERATE gwdc_fwft_ext;
gnwdc_fwft_ext: IF (C_USE_FWFT_DATA_COUNT = 0) GENERATE
WR_DATA_COUNT <= wr_data_count_int(C_WR_PNTR_WIDTH DOWNTO C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH);
END GENERATE gnwdc_fwft_ext;
END GENERATE wdc;
nwdc: IF (C_HAS_WR_DATA_COUNT=0) GENERATE
WR_DATA_COUNT <= (OTHERS=>'0');
END GENERATE nwdc;
-------------------------------------------------------------------------------
-- Write data count calculation if Use Extra Logic option is used
-------------------------------------------------------------------------------
wdc_fwft_ext: IF (C_HAS_WR_DATA_COUNT = 1 AND C_USE_FWFT_DATA_COUNT = 1) GENERATE
CONSTANT C_PNTR_WIDTH : integer
:= if_then_else ((C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH),
C_WR_PNTR_WIDTH, C_RD_PNTR_WIDTH);
SIGNAL adjusted_wr_pntr : std_logic_vector (C_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SIGNAL adjusted_rd_pntr : std_logic_vector (C_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
CONSTANT EXTRA_WORDS : std_logic_vector (C_PNTR_WIDTH DOWNTO 0)
:= conv_std_logic_vector(
if_then_else ((C_DEPTH_RATIO_WR=1),2
,(2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD))
,C_PNTR_WIDTH+1);
SIGNAL diff_wr_rd_tmp : std_logic_vector (C_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SIGNAL diff_wr_rd : std_logic_vector (C_PNTR_WIDTH DOWNTO 0)
:= (OTHERS => '0');
SIGNAL wr_data_count_i : std_logic_vector (C_PNTR_WIDTH DOWNTO 0)
:= (OTHERS => '0');
BEGIN
-----------------------------------------------------------------------------
--Adjust write and read pointer to the deepest port width
-----------------------------------------------------------------------------
--C_PNTR_WIDTH=C_WR_PNTR_WIDTH
gpadr: IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
adjusted_wr_pntr <= wr_pntr;
adjusted_rd_pntr(C_PNTR_WIDTH-1 DOWNTO C_PNTR_WIDTH-C_RD_PNTR_WIDTH)
<= rd_pntr_wr;
adjusted_rd_pntr(C_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0)<=(OTHERS=>'0');
END GENERATE gpadr;
--C_PNTR_WIDTH=C_RD_PNTR_WIDTH
gpadw: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE
adjusted_wr_pntr(C_PNTR_WIDTH-1 DOWNTO C_PNTR_WIDTH-C_WR_PNTR_WIDTH)
<= wr_pntr;
adjusted_wr_pntr(C_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0)<=(OTHERS=>'0');
adjusted_rd_pntr <= rd_pntr_wr;
END GENERATE gpadw;
--C_PNTR_WIDTH=C_WR_PNTR_WIDTH=C_RD_PNTR_WIDTH
ngpad: IF (C_WR_PNTR_WIDTH = C_RD_PNTR_WIDTH) GENERATE
adjusted_wr_pntr <= wr_pntr;
adjusted_rd_pntr <= rd_pntr_wr;
END GENERATE ngpad;
-----------------------------------------------------------------------------
--Calculate words in write domain
-----------------------------------------------------------------------------
--Subtract the pointers to get the number of words in the RAM, *THEN* pad
--the result
diff_wr_rd_tmp <= adjusted_wr_pntr - adjusted_rd_pntr;
diff_wr_rd <= '0' & diff_wr_rd_tmp;
pwdc : PROCESS (WR_CLK, wr_rst_i)
BEGIN
IF (wr_rst_i = '1') THEN
wr_data_count_i <= (OTHERS=>'0');
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
wr_data_count_i <= diff_wr_rd + extra_words;
END IF;
END PROCESS pwdc;
gdc0: IF (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH) GENERATE
wdc_fwft_ext_as
<= wr_data_count_i(C_PNTR_WIDTH DOWNTO 0);
END GENERATE gdc0;
gdc1: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE
wdc_fwft_ext_as
<= wr_data_count_i(C_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH);
END GENERATE gdc1;
END GENERATE wdc_fwft_ext;
-------------------------------------------------------------------------------
-- Read data count calculation if Use Extra Logic option is used
-------------------------------------------------------------------------------
rdc_fwft_ext: IF (C_HAS_RD_DATA_COUNT = 1 AND C_USE_FWFT_DATA_COUNT = 1) GENERATE
SIGNAL diff_wr_rd_tmp : std_logic_vector (C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SIGNAL diff_wr_rd : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0)
:= (OTHERS => '0');
SIGNAL zero : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0)
:= (OTHERS => '0');
SIGNAL one : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0)
:= conv_std_logic_vector(1, C_RD_PNTR_WIDTH+1);
SIGNAL two : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0)
:= conv_std_logic_vector(2, C_RD_PNTR_WIDTH+1);
SIGNAL adjusted_wr_pntr_r : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
BEGIN
----------------------------------------------------------------------------
-- If write depth is smaller than read depth, pad write pointer.
-- If write depth is bigger than read depth, trim write pointer.
----------------------------------------------------------------------------
gpad : IF (C_RD_PNTR_WIDTH>C_WR_PNTR_WIDTH) GENERATE
adjusted_wr_pntr_r(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH)
<= WR_PNTR_RD;
adjusted_wr_pntr_r(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0)
<= (OTHERS => '0');
END GENERATE gpad;
gtrim : IF (C_RD_PNTR_WIDTH<=C_WR_PNTR_WIDTH) GENERATE
adjusted_wr_pntr_r
<= WR_PNTR_RD(C_WR_PNTR_WIDTH-1 DOWNTO C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH);
END GENERATE gtrim;
-----------------------------------------------------------------------------
-- This accounts for preload 0 by explicitly handling the preload states
-- which do not have both output stages filled. As a result, the rd_data_count
-- produced will always accurately reflect the number of READABLE words at
-- a given time.
-----------------------------------------------------------------------------
diff_wr_rd_tmp <= adjusted_wr_pntr_r - RD_PNTR;
diff_wr_rd <= '0' & diff_wr_rd_tmp;
prdc : PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i = '1') THEN
rdc_fwft_ext_as <= zero;
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
IF (stage2_valid = '0') THEN
rdc_fwft_ext_as <= zero;
ELSIF (stage2_valid = '1' AND stage1_valid = '0') THEN
rdc_fwft_ext_as <= one;
ELSE
rdc_fwft_ext_as <= diff_wr_rd + two;
END IF;
END IF;
END PROCESS prdc;
END GENERATE rdc_fwft_ext;
-------------------------------------------------------------------------------
-- Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
-------------------------------------------------------------------------------
gpad : IF (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) GENERATE
adj_wr_pntr_rd(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH)
<= wr_pntr_rd;
adj_wr_pntr_rd(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0)
<= (OTHERS => '0');
END GENERATE gpad;
gtrim : IF (C_RD_PNTR_WIDTH<=C_WR_PNTR_WIDTH) GENERATE
adj_wr_pntr_rd
<= wr_pntr_rd(C_WR_PNTR_WIDTH-1 DOWNTO C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH);
END GENERATE gtrim;
-------------------------------------------------------------------------------
-- Generate Empty
-------------------------------------------------------------------------------
-- ram_rd_en used to determine EMPTY should depend on the EMPTY.
ram_rd_en <= RD_EN AND (NOT empty_comb);
empty_int <= ((adj_wr_pntr_rd = rd_pntr) OR (ram_rd_en = '1' AND
(adj_wr_pntr_rd = conv_std_logic_vector((conv_integer(rd_pntr)+1),C_RD_PNTR_WIDTH))));
-------------------------------------------------------------------------------
-- Generate Almost Empty
-------------------------------------------------------------------------------
almost_empty_int <= ((adj_wr_pntr_rd = conv_std_logic_vector((conv_integer(rd_pntr)+1),C_RD_PNTR_WIDTH)) OR (ram_rd_en = '1' AND
(adj_wr_pntr_rd = conv_std_logic_vector((conv_integer(rd_pntr)+2),C_RD_PNTR_WIDTH))));
-------------------------------------------------------------------------------
-- Registering Empty & Almost Empty
-- Generate read data count if Use Extra Logic is not selected.
-------------------------------------------------------------------------------
empty_proc : PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i = '1') THEN
empty_comb <= '1' AFTER C_TCQ;
empty_comb_d1 <= '1' AFTER C_TCQ;
ALMOST_EMPTY <= '1' AFTER C_TCQ;
rd_data_count_int <= (OTHERS => '0') AFTER C_TCQ;
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
rd_data_count_int <= ((adj_wr_pntr_rd(C_RD_PNTR_WIDTH-1 DOWNTO 0) -
rd_pntr(C_RD_PNTR_WIDTH-1 DOWNTO 0)) & '0') AFTER C_TCQ;
empty_comb_d1 <= empty_comb AFTER C_TCQ;
IF (empty_int) THEN
empty_comb <= '1' AFTER C_TCQ;
ELSE
empty_comb <= '0' AFTER C_TCQ;
END IF;
IF (empty_comb = '0') THEN
IF (almost_empty_int) THEN
ALMOST_EMPTY <= '1' AFTER C_TCQ;
ELSE
ALMOST_EMPTY <= '0' AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS empty_proc;
-------------------------------------------------------------------------------
-- Read pointer adjustment based on pointers width for FULL/ALMOST_FULL generation
-------------------------------------------------------------------------------
gfpad : IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
adj_rd_pntr_wr
(C_WR_PNTR_WIDTH-1 DOWNTO C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH)
<= rd_pntr_wr;
adj_rd_pntr_wr(C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0)
<= (OTHERS => '0');
END GENERATE gfpad;
gftrim : IF (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) GENERATE
adj_rd_pntr_wr
<= rd_pntr_wr(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH);
END GENERATE gftrim;
-------------------------------------------------------------------------------
-- Generate Full
-------------------------------------------------------------------------------
-- ram_wr_en used to determine FULL should depend on the FULL.
ram_wr_en <= WR_EN AND (NOT full_comb);
full_int <= ((adj_rd_pntr_wr = conv_std_logic_vector((conv_integer(wr_pntr)+1),C_WR_PNTR_WIDTH)) OR (ram_wr_en = '1' AND
(adj_rd_pntr_wr = conv_std_logic_vector((conv_integer(wr_pntr)+2),C_WR_PNTR_WIDTH))));
-------------------------------------------------------------------------------
-- Generate Almost Full
-------------------------------------------------------------------------------
almost_full_int <= ((adj_rd_pntr_wr = conv_std_logic_vector((conv_integer(wr_pntr)+2),C_WR_PNTR_WIDTH)) OR (ram_wr_en = '1' AND
(adj_rd_pntr_wr = conv_std_logic_vector((conv_integer(wr_pntr)+3),C_WR_PNTR_WIDTH))));
-------------------------------------------------------------------------------
-- Registering Full & Almost Full
-- Generate write data count if Use Extra Logic is not selected.
-------------------------------------------------------------------------------
full_proc : PROCESS (WR_CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
full_comb <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ALMOST_FULL <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
wr_data_count_int <= (OTHERS => '0') AFTER C_TCQ;
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
wr_data_count_int <= ((wr_pntr(C_WR_PNTR_WIDTH-1 DOWNTO 0) -
adj_rd_pntr_wr(C_WR_PNTR_WIDTH-1 DOWNTO 0)) & '0') AFTER C_TCQ;
IF (full_int) THEN
full_comb <= '1' AFTER C_TCQ;
ELSE
full_comb <= '0' AFTER C_TCQ;
END IF;
IF (RST_FULL_GEN = '1') THEN
ALMOST_FULL <= '0' AFTER C_TCQ;
ELSIF (full_comb = '0') THEN
IF (almost_full_int) THEN
ALMOST_FULL <= '1' AFTER C_TCQ;
ELSE
ALMOST_FULL <= '0' AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS full_proc;
-------------------------------------------------------------------------------
-- Counter that determines the FWFT read duration.
-------------------------------------------------------------------------------
-- C_PRELOAD_LATENCY will be 0 for Non-Built-in FIFO with FWFT.
grd_fwft: IF (C_PRELOAD_LATENCY = 0) GENERATE
SIGNAL user_empty_fb_d1 : std_logic := '1';
BEGIN
grd_fwft_proc : PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i = '1') THEN
rd_fwft_cnt <= (others => '0');
user_empty_fb_d1 <= '1';
stage1_valid <= '0';
stage2_valid <= '0';
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
user_empty_fb_d1 <= USER_EMPTY_FB;
IF (user_empty_fb_d1 = '0' AND USER_EMPTY_FB = '1') THEN
rd_fwft_cnt <= (others => '0') AFTER C_TCQ;
ELSIF (empty_comb = '0') THEN
IF (RD_EN = '1' AND rd_fwft_cnt < X"5") THEN
rd_fwft_cnt <= rd_fwft_cnt + "1" AFTER C_TCQ;
END IF;
END IF;
IF (stage1_valid = '0' AND stage2_valid = '0') THEN
IF (empty_comb = '0') THEN
stage1_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '0' AFTER C_TCQ;
END IF;
ELSIF (stage1_valid = '1' AND stage2_valid = '0') THEN
IF (empty_comb = '1') THEN
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
END IF;
ELSIF (stage1_valid = '0' AND stage2_valid = '1') THEN
IF (empty_comb = '1' AND RD_EN_USER = '1') THEN
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '0' AFTER C_TCQ;
ELSIF (empty_comb = '0' AND RD_EN_USER = '1') THEN
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '0' AFTER C_TCQ;
ELSIF (empty_comb = '0' AND RD_EN_USER = '0') THEN
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
END IF;
ELSIF (stage1_valid = '1' AND stage2_valid = '1') THEN
IF (empty_comb = '1' AND RD_EN_USER = '1') THEN
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
END IF;
ELSE
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '0' AFTER C_TCQ;
END IF;
END IF;
END PROCESS grd_fwft_proc;
END GENERATE grd_fwft;
gnrd_fwft: IF (C_PRELOAD_LATENCY > 0) GENERATE
rd_fwft_cnt <= X"2";
END GENERATE gnrd_fwft;
-------------------------------------------------------------------------------
-- Assign FULL, EMPTY, ALMOST_FULL and ALMOST_EMPTY
-------------------------------------------------------------------------------
FULL <= full_comb;
EMPTY <= empty_comb;
-------------------------------------------------------------------------------
-- Asynchronous FIFO using linked lists
-------------------------------------------------------------------------------
FIFO_PROC : PROCESS (WR_CLK, RD_CLK, rd_rst_i, wr_rst_i)
--Declare the linked-list head/tail pointers and the size value
VARIABLE head : listptr;
VARIABLE tail : listptr;
VARIABLE size : integer := 0;
VARIABLE cntr : integer := 0;
VARIABLE cntr_size_var_int : integer := 0;
--Data is the internal version of the DOUT bus
VARIABLE data : std_logic_vector(c_dout_width - 1 DOWNTO 0)
:= hexstr_to_std_logic_vec( C_DOUT_RST_VAL, c_dout_width);
VARIABLE err_type : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
--Temporary values for calculating adjusted prog_empty/prog_full thresholds
VARIABLE prog_empty_actual_assert_thresh : integer := 0;
VARIABLE prog_empty_actual_negate_thresh : integer := 0;
VARIABLE prog_full_actual_assert_thresh : integer := 0;
VARIABLE prog_full_actual_negate_thresh : integer := 0;
VARIABLE diff_pntr : integer := 0;
BEGIN
-- Calculate the current contents of the FIFO (size)
-- Warning: This value should only be calculated once each time this
-- process is entered.
-- It is updated instantaneously for both write and read operations,
-- so it is not ideal to use for signals which must consider the
-- latency of crossing clock domains.
-- cntr_size_var_int is updated only once when the process is entered
-- This variable is used in the conditions instead of cntr which has the
-- latest value.
cntr_size_var_int := cntr;
-- RESET CONDITIONS
IF wr_rst_i = '1' THEN
wr_point <= 0 after C_TCQ;
wr_point_d1 <= 0 after C_TCQ;
wr_pntr_rd1 <= (OTHERS => '0') after C_TCQ;
rd_pntr_wr_d2 <= (OTHERS => '0') after C_TCQ;
rd_pntr_wr_d3 <= (OTHERS => '0') after C_TCQ;
rd_pntr_wr_d4 <= (OTHERS => '0') after C_TCQ;
rd_pntr_wr <= (OTHERS => '0') after C_TCQ;
--Create new linked list
newlist(head, tail,cntr);
diff_pntr := 0;
---------------------------------------------------------------------------
-- Write to FIFO
---------------------------------------------------------------------------
ELSIF WR_CLK'event AND WR_CLK = '1' THEN
-- Delay the write pointer before passing to RD_CLK domain to accommodate
-- the binary to gray converion
wr_pntr_rd1 <= wr_pntr after C_TCQ;
-- Read pointer synchronization in WR_CLK domain
rd_pntr_wr_d2 <= rd_pntr_wr_d1 after C_TCQ;
rd_pntr_wr_d3 <= rd_pntr_wr_d2 after C_TCQ;
rd_pntr_wr_d4 <= rd_pntr_wr_d2 after C_TCQ;
-- Delay the synchronized read pointer to accommodate the gray to binary
-- converion in WR_CLK domain
rd_pntr_wr <= rd_pntr_wr_d4 after C_TCQ;
wr_point_d1 <= wr_point after C_TCQ;
--The following IF statement setup default values of full_i and almost_full_i.
--The values might be overwritten in the next IF statement.
--If writing, then it is not possible to predict how many
--words will actually be in the FIFO after the write concludes
--(because the number of reads which happen in this time can
-- not be determined).
--Therefore, treat it pessimistically and always assume that
-- the write will happen without a read (assume the FIFO is
-- C_DEPTH_RATIO_RD fuller than it is).
--Note:
--1. cntr_size_var_int is the deepest depth between write depth and read depth
-- cntr_size_var_int/C_DEPTH_RATIO_RD is number of words in the write domain.
--2. cntr_size_var_int+C_DEPTH_RATIO_RD: number of write words in the next clock cycle
-- if wr_en=1 (C_DEPTH_RATIO_RD=one write word)
--3. For asymmetric FIFO, if write width is narrower than read width. Don't
-- have to consider partial words.
--4. For asymmetric FIFO, if read width is narrower than write width,
-- the worse case that FIFO is going to full is depicted in the following
-- diagram. Both rd_pntr_a and rd_pntr_b will cause FIFO full. rd_pntr_a
-- is the worse case. Therefore, in the calculation, actual FIFO depth is
-- substarcted to one write word and added one read word.
-- -------
-- | | |
-- wr_pntr-->| |---
-- | | |
-- ---|---
-- | | |
-- | |---
-- | | |
-- ---|---
-- | | |<--rd_pntr_a
-- | |---
-- | | |<--rd_pntr_b
-- ---|---
-- Update full_i and almost_full_i if user is writing to the FIFO.
-- Assign overflow and wr_ack.
IF WR_EN = '1' THEN
IF full_comb /= '1' THEN
-- User is writing to a FIFO which is NOT reporting FULL
IF cntr_size_var_int/C_DEPTH_RATIO_RD = C_FIFO_WR_DEPTH THEN
-- FIFO really is Full
--Report Overflow and do not acknowledge the write
ELSIF cntr_size_var_int/C_DEPTH_RATIO_RD + 1 = C_FIFO_WR_DEPTH THEN
-- FIFO is almost full
-- This write will succeed, and FIFO will go FULL
FOR h IN C_DEPTH_RATIO_RD DOWNTO 1 LOOP
add(head, tail,
DIN((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),cntr,
(width_gt1 & INJECTDBITERR & INJECTSBITERR));
END LOOP;
wr_point <= (wr_point + 1) MOD C_WR_DEPTH after C_TCQ;
ELSIF cntr_size_var_int/C_DEPTH_RATIO_RD + 2 = C_FIFO_WR_DEPTH THEN
-- FIFO is one away from almost full
-- This write will succeed, and FIFO will go almost_full_i
FOR h IN C_DEPTH_RATIO_RD DOWNTO 1 LOOP
add(head, tail,
DIN((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),cntr,
(width_gt1 & INJECTDBITERR & INJECTSBITERR));
END LOOP;
wr_point <= (wr_point + 1) MOD C_WR_DEPTH after C_TCQ;
ELSE
-- FIFO is no where near FULL
--Write will succeed, no change in status
FOR h IN C_DEPTH_RATIO_RD DOWNTO 1 LOOP
add(head, tail,
DIN((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),cntr,
(width_gt1 & INJECTDBITERR & INJECTSBITERR));
END LOOP;
wr_point <= (wr_point + 1) MOD C_WR_DEPTH after C_TCQ;
END IF;
ELSE --IF full_i = '1'
-- User is writing to a FIFO which IS reporting FULL
--Write will fail
END IF; --full_i
ELSE --WR_EN/='1'
--No write attempted, so neither overflow or acknowledge
END IF; --WR_EN
END IF; --WR_CLK
---------------------------------------------------------------------------
-- Read from FIFO
---------------------------------------------------------------------------
IF rd_rst_i = '1' THEN
-- Whenever user is attempting to read from
-- an EMPTY FIFO, the core should report an underflow error, even if
-- the core is in a RESET condition.
rd_point <= 0 after C_TCQ;
rd_point_d1 <= 0 after C_TCQ;
rd_pntr_wr_d1 <= (OTHERS => '0') after C_TCQ;
wr_pntr_rd2 <= (OTHERS => '0') after C_TCQ;
wr_pntr_rd3 <= (OTHERS => '0') after C_TCQ;
wr_pntr_rd <= (OTHERS => '0') after C_TCQ;
-- DRAM resets asynchronously
IF (C_MEMORY_TYPE = 2 AND C_USE_DOUT_RST = 1) THEN
data := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
END IF;
-- BRAM resets synchronously
IF (C_MEMORY_TYPE < 2 AND C_USE_DOUT_RST = 1) THEN
IF (RD_CLK'event AND RD_CLK = '1') THEN
data := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
END IF;
END IF;
-- Reset only if ECC is not selected as ECC does not support reset.
IF (C_USE_ECC = 0) THEN
err_type := (OTHERS => '0');
END IF ;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN
-- Delay the read pointer before passing to WR_CLK domain to accommodate
-- the binary to gray converion
rd_pntr_wr_d1 <= rd_pntr after C_TCQ;
-- Write pointer synchronization in RD_CLK domain
wr_pntr_rd2 <= wr_pntr_rd1 after C_TCQ;
wr_pntr_rd3 <= wr_pntr_rd2 after C_TCQ;
-- Delay the synchronized write pointer to accommodate the gray to binary
-- converion in RD_CLK domain
wr_pntr_rd <= wr_pntr_rd3 after C_TCQ;
rd_point_d1 <= rd_point after C_TCQ;
---------------------------------------------------------------------------
-- Read Latency 1
---------------------------------------------------------------------------
--The following IF statement setup default values of empty_i and
--almost_empty_i. The values might be overwritten in the next IF statement.
--Note:
--cntr_size_var_int/C_DEPTH_RATIO_WR : number of words in read domain.
IF (ram_rd_en = '1') THEN
IF empty_comb /= '1' THEN
IF cntr_size_var_int/C_DEPTH_RATIO_WR = 2 THEN
--FIFO is going almost empty
FOR h IN C_DEPTH_RATIO_WR DOWNTO 1 LOOP
read(tail,
data((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),
err_type);
remove(head, tail,cntr);
END LOOP;
rd_point <= (rd_point + 1) MOD C_RD_DEPTH after C_TCQ;
ELSIF cntr_size_var_int/C_DEPTH_RATIO_WR = 1 THEN
--FIFO is going empty
FOR h IN C_DEPTH_RATIO_WR DOWNTO 1 LOOP
read(tail,
data((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),
err_type);
remove(head, tail,cntr);
END LOOP;
rd_point <= (rd_point + 1) MOD C_RD_DEPTH after C_TCQ;
ELSIF cntr_size_var_int/C_DEPTH_RATIO_WR = 0 THEN
--FIFO is empty
ELSE
--FIFO is not empty
FOR h IN C_DEPTH_RATIO_WR DOWNTO 1 LOOP
read(tail,
data((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),
err_type);
remove(head, tail,cntr);
END LOOP;
rd_point <= (rd_point + 1) MOD C_RD_DEPTH after C_TCQ;
END IF;
ELSE
--FIFO is empty
END IF;
END IF; --RD_EN
END IF; --RD_CLK
dout_i <= data after C_TCQ;
sbiterr_i <= err_type(0) after C_TCQ;
dbiterr_i <= err_type(1) after C_TCQ;
END PROCESS;
-----------------------------------------------------------------------------
-- Programmable FULL flags
-----------------------------------------------------------------------------
proc_pf_input: PROCESS(PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT,PROG_FULL_THRESH_NEGATE)
BEGIN
IF (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0) THEN -- FWFT
IF (C_PROG_FULL_TYPE = 3) THEN -- Single threshold input
pf_input_thr_assert_val <= PROG_FULL_THRESH - conv_integer(EXTRA_WORDS_DC);
ELSE -- Multiple threshold inputs
pf_input_thr_assert_val <= PROG_FULL_THRESH_ASSERT - conv_std_logic_vector(EXTRA_WORDS_DC,C_WR_PNTR_WIDTH);
pf_input_thr_negate_val <= PROG_FULL_THRESH_NEGATE - conv_std_logic_vector(EXTRA_WORDS_DC,C_WR_PNTR_WIDTH);
END IF;
ELSE -- STD
IF (C_PROG_FULL_TYPE = 3) THEN -- Single threshold input
pf_input_thr_assert_val <= PROG_FULL_THRESH;
ELSE -- Multiple threshold inputs
pf_input_thr_assert_val <= PROG_FULL_THRESH_ASSERT;
pf_input_thr_negate_val <= PROG_FULL_THRESH_NEGATE;
END IF;
END IF;
END PROCESS proc_pf_input;
proc_pf: PROCESS(WR_CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
prog_full_reg <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
diff_pntr_wr <= 0;
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
IF (ram_wr_en = '0') THEN
diff_pntr_wr <= conv_integer(wr_pntr - adj_rd_pntr_wr) after C_TCQ;
ELSIF (ram_wr_en = '1') THEN
diff_pntr_wr <= conv_integer(wr_pntr - adj_rd_pntr_wr) + 1 after C_TCQ;
END IF;
IF (RST_FULL_GEN = '1') THEN
prog_full_reg <= '0' after C_TCQ;
ELSIF (C_PROG_FULL_TYPE = 1) THEN
IF (full_comb = '0') THEN
IF (diff_pntr_wr >= C_PF_THR_ASSERT_ADJUSTED) THEN
prog_full_reg <= '1' after C_TCQ;
ELSE
prog_full_reg <= '0' after C_TCQ;
END IF;
ELSE
prog_full_reg <= prog_full_reg after C_TCQ;
END IF;
ELSIF (C_PROG_FULL_TYPE = 2) THEN
IF (full_comb = '0') THEN
IF (diff_pntr_wr >= C_PF_THR_ASSERT_ADJUSTED) THEN
prog_full_reg <= '1' after C_TCQ;
ELSIF (diff_pntr_wr < C_PF_THR_NEGATE_ADJUSTED) THEN
prog_full_reg <= '0' after C_TCQ;
ELSE
prog_full_reg <= prog_full_reg after C_TCQ;
END IF;
ELSE
prog_full_reg <= prog_full_reg after C_TCQ;
END IF;
ELSIF (C_PROG_FULL_TYPE = 3) THEN
IF (full_comb = '0') THEN
IF (diff_pntr_wr >= conv_integer(pf_input_thr_assert_val)) THEN
prog_full_reg <= '1' after C_TCQ;
ELSE
prog_full_reg <= '0' after C_TCQ;
END IF;
ELSE
prog_full_reg <= prog_full_reg after C_TCQ;
END IF;
ELSIF (C_PROG_FULL_TYPE = 4) THEN
IF (full_comb = '0') THEN
IF (diff_pntr_wr >= conv_integer(pf_input_thr_assert_val)) THEN
prog_full_reg <= '1' after C_TCQ;
ELSIF (diff_pntr_wr < conv_integer(pf_input_thr_negate_val)) THEN
prog_full_reg <= '0' after C_TCQ;
ELSE
prog_full_reg <= prog_full_reg after C_TCQ;
END IF;
ELSE
prog_full_reg <= prog_full_reg after C_TCQ;
END IF;
END IF; --C_PROG_FULL_TYPE
END IF; -- WR_CLK
END PROCESS proc_pf;
---------------------------------------------------------------------------
-- Programmable EMPTY Flags
---------------------------------------------------------------------------
proc_pe: PROCESS(RD_CLK, rd_rst_i)
VARIABLE pe_thr_assert_val : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE pe_thr_negate_val : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
IF (rd_rst_i = '1') THEN
diff_pntr_rd <= 0;
prog_empty_reg <= '1';
pe_thr_assert_val := (OTHERS => '0');
pe_thr_negate_val := (OTHERS => '0');
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
IF (ram_rd_en = '0') THEN
diff_pntr_rd <= conv_integer(adj_wr_pntr_rd - rd_pntr) after C_TCQ;
ELSIF (ram_rd_en = '1') THEN
diff_pntr_rd <= conv_integer(adj_wr_pntr_rd - rd_pntr) - 1 after C_TCQ;
ELSE
diff_pntr_rd <= diff_pntr_rd after C_TCQ;
END IF;
IF (C_PROG_EMPTY_TYPE = 1) THEN
IF (empty_comb = '0') THEN
IF (diff_pntr_rd <= C_PE_THR_ASSERT_VAL_I) THEN
prog_empty_reg <= '1' after C_TCQ;
ELSE
prog_empty_reg <= '0' after C_TCQ;
END IF;
ELSE
prog_empty_reg <= prog_empty_reg after C_TCQ;
END IF;
ELSIF (C_PROG_EMPTY_TYPE = 2) THEN
IF (empty_comb = '0') THEN
IF (diff_pntr_rd <= C_PE_THR_ASSERT_VAL_I) THEN
prog_empty_reg <= '1' after C_TCQ;
ELSIF (diff_pntr_rd > C_PE_THR_NEGATE_VAL_I) THEN
prog_empty_reg <= '0' after C_TCQ;
ELSE
prog_empty_reg <= prog_empty_reg after C_TCQ;
END IF;
ELSE
prog_empty_reg <= prog_empty_reg after C_TCQ;
END IF;
ELSIF (C_PROG_EMPTY_TYPE = 3) THEN
-- If empty input threshold is selected, then subtract 2 for FWFT to
-- compensate the FWFT stage, otherwise assign the input value.
IF (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0) THEN -- FWFT
pe_thr_assert_val := PROG_EMPTY_THRESH - "10";
ELSE
pe_thr_assert_val := PROG_EMPTY_THRESH;
END IF;
IF (empty_comb = '0') THEN
IF (diff_pntr_rd <= pe_thr_assert_val) THEN
prog_empty_reg <= '1' after C_TCQ;
ELSE
prog_empty_reg <= '0' after C_TCQ;
END IF;
ELSE
prog_empty_reg <= prog_empty_reg after C_TCQ;
END IF;
ELSIF (C_PROG_EMPTY_TYPE = 4) THEN
-- If empty input threshold is selected, then subtract 2 for FWFT to
-- compensate the FWFT stage, otherwise assign the input value.
IF (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0) THEN -- FWFT
pe_thr_assert_val := PROG_EMPTY_THRESH_ASSERT - "10";
pe_thr_negate_val := PROG_EMPTY_THRESH_NEGATE - "10";
ELSE
pe_thr_assert_val := PROG_EMPTY_THRESH_ASSERT;
pe_thr_negate_val := PROG_EMPTY_THRESH_NEGATE;
END IF;
IF (empty_comb = '0') THEN
IF (diff_pntr_rd <= conv_integer(pe_thr_assert_val)) THEN
prog_empty_reg <= '1' after C_TCQ;
ELSIF (diff_pntr_rd > conv_integer(pe_thr_negate_val)) THEN
prog_empty_reg <= '0' after C_TCQ;
ELSE
prog_empty_reg <= prog_empty_reg after C_TCQ;
END IF;
ELSE
prog_empty_reg <= prog_empty_reg after C_TCQ;
END IF;
END IF; --C_PROG_EMPTY_TYPE
END IF; -- RD_CLK
END PROCESS proc_pe;
-----------------------------------------------------------------------------
-- overflow_i generation: Asynchronous FIFO
-----------------------------------------------------------------------------
govflw: IF (C_HAS_OVERFLOW = 1) GENERATE
povflw: PROCESS (WR_CLK)
BEGIN
IF WR_CLK'event AND WR_CLK = '1' THEN
overflow_i <= full_comb AND WR_EN after C_TCQ;
END IF;
END PROCESS povflw;
END GENERATE govflw;
-----------------------------------------------------------------------------
-- underflow_i generation: Asynchronous FIFO
-----------------------------------------------------------------------------
gunflw: IF (C_HAS_UNDERFLOW = 1) GENERATE
punflw: PROCESS (RD_CLK)
BEGIN
IF RD_CLK'event AND RD_CLK = '1' THEN
underflow_i <= empty_comb and RD_EN after C_TCQ;
END IF;
END PROCESS punflw;
END GENERATE gunflw;
-----------------------------------------------------------------------------
-- wr_ack_i generation: Asynchronous FIFO
-----------------------------------------------------------------------------
gwack: IF (C_HAS_WR_ACK = 1) GENERATE
pwack: PROCESS (WR_CLK,wr_rst_i)
BEGIN
IF wr_rst_i = '1' THEN
wr_ack_i <= '0' after C_TCQ;
ELSIF WR_CLK'event AND WR_CLK = '1' THEN
wr_ack_i <= '0' after C_TCQ;
IF WR_EN = '1' THEN
IF full_comb /= '1' THEN
wr_ack_i <= '1' after C_TCQ;
END IF;
END IF;
END IF;
END PROCESS pwack;
END GENERATE gwack;
----------------------------------------------------------------------------
-- valid_i generation: Asynchronous FIFO
----------------------------------------------------------------------------
gvld_i: IF (C_HAS_VALID = 1) GENERATE
PROCESS (rd_rst_i , RD_CLK )
BEGIN
IF rd_rst_i = '1' THEN
valid_i <= '0' after C_TCQ;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN
valid_i <= '0' after C_TCQ;
IF RD_EN = '1' THEN
IF empty_comb /= '1' THEN
valid_i <= '1' after C_TCQ;
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------
-- Delay valid_d1
--if C_MEMORY_TYPE=0 or 1, C_USE_EMBEDDED_REG=1
-----------------------------------------------------------------
gv0_as: IF (C_USE_EMBEDDED_REG=1
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)) GENERATE
PROCESS (rd_rst_i , RD_CLK )
BEGIN
IF rd_rst_i = '1' THEN
valid_d1 <= '0' after C_TCQ;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN
valid_d1 <= valid_i after C_TCQ;
END IF;
END PROCESS;
END GENERATE gv0_as;
gv1_as: IF NOT (C_USE_EMBEDDED_REG=1
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)) GENERATE
valid_d1 <= valid_i;
END GENERATE gv1_as;
END GENERATE gvld_i;
-----------------------------------------------------------------------------
--Use delayed Valid AND DOUT if we have a LATENCY=2 configurations
-- ( if C_MEMORY_TYPE=0 or 1, C_PRELOAD_REGS=0, C_USE_EMBEDDED_REG=1 )
--Otherwise, connect the valid and DOUT values up directly, with no
--additional latency.
-----------------------------------------------------------------------------
gv0: IF (C_PRELOAD_LATENCY=2
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)) GENERATE
gv1: IF (C_HAS_VALID = 1) GENERATE
valid_out <= valid_d1;
END GENERATE gv1;
PROCESS (rd_rst_i , RD_CLK )
BEGIN
IF (rd_rst_i = '1') THEN
-- BRAM resets synchronously
IF (C_USE_DOUT_RST = 1) THEN
IF (RD_CLK 'event AND RD_CLK = '1') THEN
DOUT <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
END IF;
IF (C_USE_ECC = 0) THEN
SBITERR <= '0' after C_TCQ;
DBITERR <= '0' after C_TCQ;
END IF;
ram_rd_en_d1 <= '0' after C_TCQ;
ELSIF (RD_CLK 'event AND RD_CLK = '1') THEN
ram_rd_en_d1 <= ram_rd_en after C_TCQ;
IF (ram_rd_en_d1 = '1') THEN
DOUT <= dout_i after C_TCQ;
SBITERR <= sbiterr_i after C_TCQ;
DBITERR <= dbiterr_i after C_TCQ;
END IF;
END IF;
END PROCESS;
END GENERATE gv0;
gv1: IF NOT (C_PRELOAD_LATENCY=2
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)) GENERATE
gv2a: IF (C_HAS_VALID = 1) GENERATE
valid_out <= valid_i;
END GENERATE gv2a;
DOUT <= dout_i;
SBITERR <= sbiterr_i after C_TCQ;
DBITERR <= dbiterr_i after C_TCQ;
END GENERATE gv1;
END GENERATE gnll_afifo;
-------------------------------------------------------------------------------
-- Low Latency Asynchronous FIFO
-------------------------------------------------------------------------------
gll_afifo: IF (C_FIFO_TYPE = 3) GENERATE
TYPE mem_array IS ARRAY (0 TO C_WR_DEPTH-1) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SIGNAL memory : mem_array := (OTHERS => (OTHERS => '0'));
SIGNAL write_allow : std_logic := '0';
SIGNAL read_allow : std_logic := '0';
SIGNAL wr_pntr_ll_afifo : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL rd_pntr_ll_afifo : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL rd_pntr_ll_afifo_q : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL ll_afifo_full : std_logic := '0';
SIGNAL ll_afifo_empty : std_logic := '1';
SIGNAL wr_pntr_eq_rd_pntr : std_logic := '0';
SIGNAL wr_pntr_eq_rd_pntr_plus1 : std_logic := '0';
SIGNAL rd_pntr_eq_wr_pntr_plus1 : std_logic := '0';
SIGNAL rd_pntr_eq_wr_pntr_plus2 : std_logic := '0';
BEGIN
wr_rst_i <= WR_RST;
rd_rst_i <= RD_RST;
write_allow <= WR_EN AND (NOT ll_afifo_full);
read_allow <= RD_EN AND (NOT ll_afifo_empty);
wrptr_proc : PROCESS (WR_CLK,wr_rst_i)
BEGIN
IF (wr_rst_i = '1') THEN
wr_pntr_ll_afifo <= (OTHERS => '0');
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
IF (write_allow = '1') THEN
wr_pntr_ll_afifo <= wr_pntr_ll_afifo + "1" AFTER C_TCQ;
END IF;
END IF;
END PROCESS wrptr_proc;
-------------------------------------------------------------------------------
-- Fill the Memory
-------------------------------------------------------------------------------
wr_mem : PROCESS (WR_CLK)
BEGIN
IF (WR_CLK'event AND WR_CLK = '1') THEN
IF (write_allow = '1') THEN
memory(conv_integer(wr_pntr_ll_afifo)) <= DIN AFTER C_TCQ;
END IF;
END IF;
END PROCESS wr_mem;
rdptr_proc : PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i = '1') THEN
rd_pntr_ll_afifo_q <= (OTHERS => '0');
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
rd_pntr_ll_afifo_q <= rd_pntr_ll_afifo AFTER C_TCQ;
END IF;
END PROCESS rdptr_proc;
rd_pntr_ll_afifo <= rd_pntr_ll_afifo_q + "1" WHEN (read_allow = '1') ELSE rd_pntr_ll_afifo_q;
-------------------------------------------------------------------------------
-- Generate DOUT for DRAM
-------------------------------------------------------------------------------
rd_mem : PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK = '1') THEN
DOUT <= memory(conv_integer(rd_pntr_ll_afifo)) AFTER C_TCQ;
END IF;
END PROCESS rd_mem;
-------------------------------------------------------------------------------
-- Generate EMPTY
-------------------------------------------------------------------------------
wr_pntr_eq_rd_pntr <= '1' WHEN (wr_pntr_ll_afifo = rd_pntr_ll_afifo_q) ELSE '0';
wr_pntr_eq_rd_pntr_plus1 <= '1' WHEN (wr_pntr_ll_afifo = conv_std_logic_vector(
(conv_integer(rd_pntr_ll_afifo_q)+1),
C_RD_PNTR_WIDTH)) ELSE '0';
proc_empty : PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i = '1') THEN
ll_afifo_empty <= '1';
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
ll_afifo_empty <= wr_pntr_eq_rd_pntr OR (read_allow AND wr_pntr_eq_rd_pntr_plus1) AFTER C_TCQ;
END IF;
END PROCESS proc_empty;
-------------------------------------------------------------------------------
-- Generate FULL
-------------------------------------------------------------------------------
rd_pntr_eq_wr_pntr_plus1 <= '1' WHEN (rd_pntr_ll_afifo_q = conv_std_logic_vector(
(conv_integer(wr_pntr_ll_afifo)+1),
C_WR_PNTR_WIDTH)) ELSE '0';
rd_pntr_eq_wr_pntr_plus2 <= '1' WHEN (rd_pntr_ll_afifo_q = conv_std_logic_vector(
(conv_integer(wr_pntr_ll_afifo)+2),
C_WR_PNTR_WIDTH)) ELSE '0';
proc_full : PROCESS (WR_CLK, wr_rst_i)
BEGIN
IF (wr_rst_i = '1') THEN
ll_afifo_full <= '1';
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
ll_afifo_full <= rd_pntr_eq_wr_pntr_plus1 OR (write_allow AND rd_pntr_eq_wr_pntr_plus2) AFTER C_TCQ;
END IF;
END PROCESS proc_full;
EMPTY <= ll_afifo_empty;
FULL <= ll_afifo_full;
END GENERATE gll_afifo;
END behavioral;
--#############################################################################
--#############################################################################
-- Common Clock FIFO Behavioral Model
--#############################################################################
--#############################################################################
-------------------------------------------------------------------------------
-- Library Declaration
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-------------------------------------------------------------------------------
-- Common-Clock Entity Declaration - This is NOT the top-level entity
-------------------------------------------------------------------------------
ENTITY fifo_generator_v8_2_bhv_ss IS
GENERIC (
--------------------------------------------------------------------------------
-- Generic Declarations (alphabetical)
--------------------------------------------------------------------------------
C_DATA_COUNT_WIDTH : integer := 2;
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_DATA_COUNT : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RST : integer := 0;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_MEMORY_TYPE : integer := 1;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DEPTH : integer := 256;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DEPTH : integer := 256;
C_WR_PNTR_WIDTH : integer := 8;
C_TCQ : time := 100 ps;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
CLK : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
RST_FULL_GEN : IN std_logic := '0';
RST_FULL_FF : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
RD_EN : IN std_logic := '0';
WR_EN : IN std_logic := '0';
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
EMPTY : OUT std_logic := '1';
FULL : OUT std_logic := '0';
ALMOST_EMPTY : OUT std_logic := '1';
ALMOST_FULL : OUT std_logic := '0';
PROG_EMPTY : OUT std_logic := '1';
PROG_FULL : OUT std_logic := '0';
OVERFLOW : OUT std_logic := '0';
WR_ACK : OUT std_logic := '0';
VALID : OUT std_logic := '0';
UNDERFLOW : OUT std_logic := '0';
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SBITERR : OUT std_logic := '0';
DBITERR : OUT std_logic := '0'
);
END fifo_generator_v8_2_bhv_ss;
-------------------------------------------------------------------------------
-- Architecture Heading
-------------------------------------------------------------------------------
ARCHITECTURE behavioral OF fifo_generator_v8_2_bhv_ss IS
-----------------------------------------------------------------------------
-- FUNCTION actual_fifo_depth
-- Returns the actual depth of the FIFO (may differ from what the user
-- specified)
--
-- The FIFO depth is always represented as 2^n (16,32,64,128,256)
-- However, the ACTUAL fifo depth may be 2^n+1 or 2^n-1 depending on certain
-- options. This function returns the actual depth of the fifo, as seen by
-- the user.
-------------------------------------------------------------------------------
FUNCTION actual_fifo_depth(
C_FIFO_DEPTH : integer;
C_PRELOAD_REGS : integer;
C_PRELOAD_LATENCY : integer;
C_COMMON_CLOCK : integer)
RETURN integer IS
BEGIN
RETURN C_FIFO_DEPTH;
END actual_fifo_depth;
-----------------------------------------------------------------------------
-- FUNCTION int_2_std_logic
-- Returns a single bit (as std_logic) from an integer 1/0 value.
-------------------------------------------------------------------------------
FUNCTION int_2_std_logic(value : integer) RETURN std_logic IS
BEGIN
IF (value=1) THEN
RETURN '1';
ELSE
RETURN '0';
END IF;
END int_2_std_logic;
-----------------------------------------------------------------------------
-- FUNCTION hexstr_to_std_logic_vec
-- Returns a std_logic_vector for a hexadecimal string
-------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
-----------------------------------------------------------------------------
-- FUNCTION get_lesser
-- Returns a minimum value
-------------------------------------------------------------------------------
FUNCTION get_lesser(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a < b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
-----------------------------------------------------------------------------
-- FUNCTION if_then_else
-- Returns a true case or flase case based on the condition
-------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : integer;
false_case : integer)
RETURN integer IS
VARIABLE retval : integer := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
--------------------------------------------------------------------------------
-- Constant Declaration
--------------------------------------------------------------------------------
CONSTANT C_FIFO_WR_DEPTH : integer
:= actual_fifo_depth(C_WR_DEPTH, C_PRELOAD_REGS, C_PRELOAD_LATENCY, 1);
CONSTANT C_SMALLER_DATA_WIDTH : integer := get_lesser(C_DIN_WIDTH, C_DOUT_WIDTH);
CONSTANT C_FIFO_DEPTH : integer := C_WR_DEPTH;
CONSTANT C_DATA_WIDTH : integer := if_then_else((C_USE_ECC = 1 AND C_ERROR_INJECTION_TYPE /= 0),
C_DIN_WIDTH+2, C_DIN_WIDTH);
TYPE mem_array IS ARRAY (0 TO C_FIFO_DEPTH-1) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
-------------------------------------------------------------------------------
-- Internal Signals
-------------------------------------------------------------------------------
SIGNAL memory : mem_array := (OTHERS => (OTHERS => '0'));
SIGNAL wr_pntr : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_pntr : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL write_allow : std_logic := '0';
SIGNAL read_allow : std_logic := '0';
SIGNAL empty_i : std_logic := '1';
SIGNAL full_i : std_logic := '0';
SIGNAL almost_empty_i : std_logic := '1';
SIGNAL almost_full_i : std_logic := '0';
SIGNAL rst_asreg : std_logic := '0';
SIGNAL rst_asreg_d1 : std_logic := '0';
SIGNAL rst_asreg_d2 : std_logic := '0';
SIGNAL rst_comb : std_logic := '0';
SIGNAL rst_reg : std_logic := '0';
SIGNAL rst_i : std_logic := '0';
SIGNAL srst_i : std_logic := '0';
-- FULL_FLAG_RESET value given for SRST as well.
SIGNAL srst_i_d1 : std_logic := '0';
SIGNAL srst_i_d2 : std_logic := '0';
SIGNAL diff_count : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SIGNAL wr_ack_i : std_logic := '0';
SIGNAL overflow_i : std_logic := '0';
SIGNAL valid_i : std_logic := '0';
SIGNAL valid_d1 : std_logic := '0';
SIGNAL underflow_i : std_logic := '0';
--The delayed reset is used to deassert prog_full
SIGNAL rst_q : std_logic := '0';
SIGNAL prog_full_reg : std_logic := '0';
SIGNAL prog_full_noreg : std_logic := '0';
SIGNAL prog_empty_reg : std_logic := '1';
SIGNAL prog_empty_noreg: std_logic := '1';
SIGNAL dout_i : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SIGNAL sbiterr_i : std_logic := '0';
SIGNAL dbiterr_i : std_logic := '0';
SIGNAL ram_rd_en_d1 : std_logic := '0';
SIGNAL mem_pntr : integer := 0;
SIGNAL ram_wr_en_i : std_logic := '0';
SIGNAL ram_rd_en_i : std_logic := '0';
SIGNAL comp1 : std_logic := '0';
SIGNAL comp0 : std_logic := '0';
SIGNAL going_full : std_logic := '0';
SIGNAL leaving_full : std_logic := '0';
SIGNAL ram_full_comb : std_logic := '0';
SIGNAL ecomp1 : std_logic := '0';
SIGNAL ecomp0 : std_logic := '0';
SIGNAL going_empty : std_logic := '0';
SIGNAL leaving_empty : std_logic := '0';
SIGNAL ram_empty_comb : std_logic := '0';
-------------------------------------------------------------------------------
-- architecture begins here
-------------------------------------------------------------------------------
BEGIN
rst_i <= RST;
--SRST
gsrst : IF (C_HAS_SRST=1) GENERATE
srst_i <= SRST;
END GENERATE gsrst;
--No SRST
nosrst : IF (C_HAS_SRST=0) GENERATE
srst_i <= '0';
END GENERATE nosrst;
gdc : IF (C_HAS_DATA_COUNT = 1) GENERATE
SIGNAL diff_count : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
diff_count <= wr_pntr - rd_pntr;
gdcb : IF (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) GENERATE
DATA_COUNT(C_RD_PNTR_WIDTH-1 DOWNTO 0) <= diff_count;
DATA_COUNT(C_DATA_COUNT_WIDTH-1) <= '0' ;
END GENERATE;
gdcs : IF (C_DATA_COUNT_WIDTH <= C_RD_PNTR_WIDTH) GENERATE
DATA_COUNT <=
diff_count(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH);
END GENERATE;
END GENERATE gdc;
gndc : IF (C_HAS_DATA_COUNT = 0) GENERATE
DATA_COUNT <= (OTHERS => '0');
END GENERATE gndc;
-------------------------------------------------------------------------------
--Calculate WR_ACK based on C_WR_ACK_LOW parameters
-------------------------------------------------------------------------------
gwalow : IF (C_WR_ACK_LOW = 0) GENERATE
WR_ACK <= wr_ack_i;
END GENERATE gwalow;
gwahgh : IF (C_WR_ACK_LOW = 1) GENERATE
WR_ACK <= NOT wr_ack_i;
END GENERATE gwahgh;
-------------------------------------------------------------------------------
--Calculate OVERFLOW based on C_OVERFLOW_LOW parameters
-------------------------------------------------------------------------------
govlow : IF (C_OVERFLOW_LOW = 0) GENERATE
OVERFLOW <= overflow_i;
END GENERATE govlow;
govhgh : IF (C_OVERFLOW_LOW = 1) GENERATE
OVERFLOW <= NOT overflow_i;
END GENERATE govhgh;
-------------------------------------------------------------------------------
--Calculate VALID based on C_PRELOAD_LATENCY and C_VALID_LOW settings
-------------------------------------------------------------------------------
gvlat1 : IF (C_PRELOAD_LATENCY = 1 OR C_PRELOAD_LATENCY=2) GENERATE
gnvl : IF (C_VALID_LOW = 0) GENERATE
VALID <= valid_d1;
END GENERATE gnvl;
gnvh : IF (C_VALID_LOW = 1) GENERATE
VALID <= NOT valid_d1;
END GENERATE gnvh;
END GENERATE gvlat1;
-------------------------------------------------------------------------------
-- Calculate UNDERFLOW based on C_PRELOAD_LATENCY and C_UNDERFLOW_LOW settings
-------------------------------------------------------------------------------
guflat1 : IF (C_PRELOAD_LATENCY = 1 OR C_PRELOAD_LATENCY=2) GENERATE
gnul : IF (C_UNDERFLOW_LOW = 0) GENERATE
UNDERFLOW <= underflow_i;
END GENERATE gnul;
gnuh : IF (C_UNDERFLOW_LOW = 1) GENERATE
UNDERFLOW <= NOT underflow_i;
END GENERATE gnuh;
END GENERATE guflat1;
FULL <= full_i;
ALMOST_FULL <= almost_full_i;
EMPTY <= empty_i;
ALMOST_EMPTY <= almost_empty_i;
write_allow <= WR_EN AND (NOT full_i);
read_allow <= RD_EN AND (NOT empty_i);
wrptr_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
wr_pntr <= (OTHERS => '0');
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1') THEN
wr_pntr <= (OTHERS => '0') AFTER C_TCQ;
ELSIF (write_allow = '1') THEN
wr_pntr <= wr_pntr + "1" AFTER C_TCQ;
END IF;
END IF;
END PROCESS wrptr_proc;
gecc_mem: IF (C_USE_ECC = 1 AND C_ERROR_INJECTION_TYPE /= 0) GENERATE
wr_mem : PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF (write_allow = '1') THEN
memory(conv_integer(wr_pntr)) <= INJECTDBITERR & INJECTSBITERR & DIN AFTER C_TCQ;
END IF;
END IF;
END PROCESS wr_mem;
END GENERATE gecc_mem;
gnecc_mem: IF NOT (C_USE_ECC = 1 AND C_ERROR_INJECTION_TYPE /= 0) GENERATE
wr_mem : PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF (write_allow = '1') THEN
memory(conv_integer(wr_pntr)) <= DIN AFTER C_TCQ;
END IF;
END IF;
END PROCESS wr_mem;
END GENERATE gnecc_mem;
rdptr_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
rd_pntr <= (OTHERS => '0');
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1') THEN
rd_pntr <= (OTHERS => '0') AFTER C_TCQ;
ELSIF (read_allow = '1') THEN
rd_pntr <= rd_pntr + "1" AFTER C_TCQ;
END IF;
END IF;
END PROCESS rdptr_proc;
-------------------------------------------------------------------------------
-- Generate DOUT for common clock low latency FIFO
-------------------------------------------------------------------------------
gll_dout: IF(C_FIFO_TYPE = 2) GENERATE
SIGNAL dout_q : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
dout_i <= memory(conv_integer(rd_pntr)) when (read_allow = '1') else dout_q;
dout_reg : PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
dout_q <= dout_i AFTER C_TCQ;
END IF;
END PROCESS dout_reg;
END GENERATE gll_dout;
gnll_dout: IF (C_FIFO_TYPE < 2) GENERATE
-------------------------------------------------------------------------------
-- Generate DOUT for BRAM
-------------------------------------------------------------------------------
gbm_dout: IF (C_MEMORY_TYPE < 2) GENERATE
BEGIN
rd_mem : PROCESS (CLK)
VARIABLE dout_tmp : STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF (RST_FULL_FF = '1' OR srst_i = '1') THEN
IF (C_USE_DOUT_RST = 1) THEN
dout_i <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) AFTER C_TCQ;
END IF;
ELSIF (read_allow = '1') THEN
dout_tmp := memory(conv_integer(rd_pntr));
IF (C_USE_ECC = 1 AND C_ERROR_INJECTION_TYPE /= 0) THEN
IF (dout_tmp(dout_tmp'high) = '1') THEN
IF (C_DOUT_WIDTH > 2) THEN
dout_i <= dout_tmp(C_DOUT_WIDTH-1 DOWNTO 2) & NOT dout_tmp(1 DOWNTO 0) AFTER C_TCQ;
ELSIF (C_DOUT_WIDTH = 2) THEN
dout_i <= NOT dout_tmp(1 DOWNTO 0) AFTER C_TCQ;
ELSE
dout_i(0) <= dout_tmp(0) AFTER C_TCQ;
END IF;
dbiterr_i <= dout_tmp(dout_tmp'high) AFTER C_TCQ;
sbiterr_i <= '0' AFTER C_TCQ;
ELSE
dout_i <= dout_tmp(C_DOUT_WIDTH-1 DOWNTO 0) AFTER C_TCQ;
sbiterr_i <= dout_tmp(dout_tmp'high-1) AFTER C_TCQ;
dbiterr_i <= '0' AFTER C_TCQ;
END IF;
ELSE
dout_i <= dout_tmp AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS rd_mem;
END GENERATE gbm_dout;
-------------------------------------------------------------------------------
-- Generate DOUT for DRAM
-------------------------------------------------------------------------------
gdm_dout: IF (C_MEMORY_TYPE = 2 OR C_MEMORY_TYPE = 3) GENERATE
rd_mem : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
IF (C_USE_DOUT_RST = 1) THEN
dout_i <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
END IF;
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1') THEN
IF (C_USE_DOUT_RST = 1) THEN
dout_i <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) AFTER C_TCQ;
END IF;
ELSIF (read_allow = '1') THEN
dout_i <= memory(conv_integer(rd_pntr)) AFTER C_TCQ;
END IF;
END IF;
END PROCESS rd_mem;
END GENERATE gdm_dout;
END GENERATE gnll_dout;
-------------------------------------------------------------------------------
-- Generate FULL flag
-------------------------------------------------------------------------------
comp1 <= '1' WHEN (rd_pntr = (wr_pntr + "1")) ELSE '0';
comp0 <= '1' WHEN (rd_pntr = wr_pntr) ELSE '0';
going_full <= (comp1 AND write_allow AND NOT read_allow);
leaving_full <= (comp0 AND read_allow) OR RST_FULL_GEN;
ram_full_comb <= going_full OR (NOT leaving_full AND full_i);
full_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1' OR srst_i_d1 = '1' OR srst_i_d2 = '1') THEN
full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSE
full_i <= ram_full_comb AFTER C_TCQ;
END IF;
END IF;
END PROCESS full_proc;
-------------------------------------------------------------------------------
-- Generate ALMOST_FULL flag
-------------------------------------------------------------------------------
gaf_ss: IF (C_HAS_ALMOST_FULL = 1 OR C_PROG_FULL_TYPE > 2 OR C_PROG_EMPTY_TYPE > 2) GENERATE
SIGNAL fcomp2 : std_logic := '0';
SIGNAL going_afull : std_logic := '0';
SIGNAL leaving_afull : std_logic := '0';
SIGNAL ram_afull_comb : std_logic := '0';
BEGIN
fcomp2 <= '1' WHEN (rd_pntr = (wr_pntr + "10")) ELSE '0';
going_afull <= (fcomp2 AND write_allow AND NOT read_allow);
leaving_afull <= (comp1 AND read_allow AND NOT write_allow) OR RST_FULL_GEN;
ram_afull_comb <= going_afull OR (NOT leaving_afull AND almost_full_i);
af_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
almost_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1' OR srst_i_d1 = '1' OR srst_i_d2 = '1') THEN
almost_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSE
almost_full_i <= ram_afull_comb AFTER C_TCQ;
END IF;
END IF;
END PROCESS af_proc;
END GENERATE gaf_ss;
-------------------------------------------------------------------------------
-- Generate EMPTY flag
-------------------------------------------------------------------------------
ecomp1 <= '1' WHEN (wr_pntr = (rd_pntr + "1")) ELSE '0';
ecomp0 <= '1' WHEN (wr_pntr = rd_pntr) ELSE '0';
going_empty <= (ecomp1 AND NOT write_allow AND read_allow);
leaving_empty <= (ecomp0 AND write_allow);
ram_empty_comb <= going_empty OR (NOT leaving_empty AND empty_i);
empty_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
empty_i <= '1';
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1' OR srst_i_d1 = '1' OR srst_i_d2 = '1') THEN
empty_i <= '1' AFTER C_TCQ;
ELSE
empty_i <= ram_empty_comb AFTER C_TCQ;
END IF;
END IF;
END PROCESS empty_proc;
-------------------------------------------------------------------------------
-- Generate ALMOST_EMPTY flag
-------------------------------------------------------------------------------
gae_ss: IF (C_HAS_ALMOST_EMPTY = 1) GENERATE
SIGNAL ecomp2 : std_logic := '0';
SIGNAL going_aempty : std_logic := '0';
SIGNAL leaving_aempty : std_logic := '0';
SIGNAL ram_aempty_comb : std_logic := '1';
BEGIN
ecomp2 <= '1' WHEN (wr_pntr = (rd_pntr + "10")) ELSE '0';
going_aempty <= (ecomp2 AND NOT write_allow AND read_allow);
leaving_aempty <= (ecomp1 AND write_allow AND NOT read_allow);
ram_aempty_comb <= going_aempty OR (NOT leaving_aempty AND almost_empty_i);
ae_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
almost_empty_i <= '1';
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1' OR srst_i_d1 = '1' OR srst_i_d2 = '1') THEN
almost_empty_i <= '1' AFTER C_TCQ;
ELSE
almost_empty_i <= ram_aempty_comb AFTER C_TCQ;
END IF;
END IF;
END PROCESS ae_proc;
END GENERATE gae_ss;
-------------------------------------------------------------------------------
-- Generate PROG_FULL and PROG_EMPTY flags
-------------------------------------------------------------------------------
gpf_pe: IF (C_PROG_FULL_TYPE /= 0 OR C_PROG_EMPTY_TYPE /= 0) GENERATE
SIGNAL diff_pntr : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pntr_pe : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL write_allow_q : std_logic := '0';
SIGNAL read_allow_q : std_logic := '0';
SIGNAL write_only : std_logic := '0';
SIGNAL write_only_q : std_logic := '0';
SIGNAL read_only : std_logic := '0';
SIGNAL read_only_q : std_logic := '0';
SIGNAL prog_full_i : std_logic := int_2_std_logic(C_FULL_FLAGS_RST_VAL);
SIGNAL prog_empty_i : std_logic := '1';
CONSTANT C_PF_ASSERT_VAL : integer := if_then_else(C_PRELOAD_LATENCY = 0,
C_PROG_FULL_THRESH_ASSERT_VAL - 2, -- FWFT
C_PROG_FULL_THRESH_ASSERT_VAL); -- STD
CONSTANT C_PF_NEGATE_VAL : integer := if_then_else(C_PRELOAD_LATENCY = 0,
C_PROG_FULL_THRESH_NEGATE_VAL - 2, -- FWFT
C_PROG_FULL_THRESH_NEGATE_VAL); -- STD
CONSTANT C_PE_ASSERT_VAL : integer := if_then_else(C_PRELOAD_LATENCY = 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2,
C_PROG_EMPTY_THRESH_ASSERT_VAL);
CONSTANT C_PE_NEGATE_VAL : integer := if_then_else(C_PRELOAD_LATENCY = 0,
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL);
BEGIN
write_only <= write_allow AND NOT read_allow;
write_only_q <= write_allow_q AND NOT read_allow_q;
read_only <= read_allow AND NOT write_allow;
read_only_q <= read_allow_q AND NOT write_allow_q;
wr_rd_q_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
write_allow_q <= '0';
read_allow_q <= '0';
diff_pntr <= (OTHERS => '0');
diff_pntr_pe <= (OTHERS => '0');
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1' OR srst_i_d1 = '1' OR srst_i_d2 = '1') THEN
write_allow_q <= '0' AFTER C_TCQ;
read_allow_q <= '0' AFTER C_TCQ;
diff_pntr <= (OTHERS => '0') AFTER C_TCQ;
diff_pntr_pe <= (OTHERS => '0') AFTER C_TCQ;
ELSE
write_allow_q <= write_allow AFTER C_TCQ;
read_allow_q <= read_allow AFTER C_TCQ;
-- Add 1 to the difference pointer value when only write happens.
IF (write_only = '1') THEN
diff_pntr <= wr_pntr - rd_pntr + "1" AFTER C_TCQ;
ELSE
diff_pntr <= wr_pntr - rd_pntr AFTER C_TCQ;
END IF;
-- Add 1 to the difference pointer value when write or both write & read or no write & read happen.
IF (read_only = '1') THEN
diff_pntr_pe <= wr_pntr - rd_pntr - "1" AFTER C_TCQ;
ELSE
diff_pntr_pe <= wr_pntr - rd_pntr AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS wr_rd_q_proc;
-------------------------------------------------------------------------------
-- Generate PROG_FULL flag
-------------------------------------------------------------------------------
gpf: IF (C_PROG_FULL_TYPE /= 0) GENERATE
-------------------------------------------------------------------------------
-- Generate PROG_FULL for single programmable threshold constant
-------------------------------------------------------------------------------
gpf1: IF (C_PROG_FULL_TYPE = 1) GENERATE
pf1_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSIF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr) = C_PF_ASSERT_VAL) AND write_only_q = '1') THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr) = C_PF_ASSERT_VAL) AND read_only_q = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
END IF;
END PROCESS pf1_proc;
END GENERATE gpf1;
-------------------------------------------------------------------------------
-- Generate PROG_FULL for multiple programmable threshold constants
-------------------------------------------------------------------------------
gpf2: IF (C_PROG_FULL_TYPE = 2) GENERATE
pf2_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSIF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr) = C_PF_ASSERT_VAL) AND write_only_q = '1') THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr) = C_PF_NEGATE_VAL) AND read_only_q = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
END IF;
END PROCESS pf2_proc;
END GENERATE gpf2;
-------------------------------------------------------------------------------
-- Generate PROG_FULL for single programmable threshold input port
-------------------------------------------------------------------------------
gpf3: IF (C_PROG_FULL_TYPE = 3) GENERATE
SIGNAL pf_assert_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
pf_assert_val <= PROG_FULL_THRESH - "10" WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_FULL_THRESH;
pf3_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSIF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF (almost_full_i = '0') THEN
IF (conv_integer(diff_pntr) > pf_assert_val) THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF (conv_integer(diff_pntr) = pf_assert_val) THEN
IF (read_only_q = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSE
prog_full_i <= '1' AFTER C_TCQ;
END IF;
ELSE
prog_full_i <= '0' AFTER C_TCQ;
END IF;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
END IF;
END PROCESS pf3_proc;
END GENERATE gpf3;
-------------------------------------------------------------------------------
-- Generate PROG_FULL for multiple programmable threshold input ports
-------------------------------------------------------------------------------
gpf4: IF (C_PROG_FULL_TYPE = 4) GENERATE
SIGNAL pf_assert_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL pf_negate_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
pf_assert_val <= PROG_FULL_THRESH_ASSERT - "10" WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_FULL_THRESH_ASSERT;
pf_negate_val <= PROG_FULL_THRESH_NEGATE - "10" WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_FULL_THRESH_NEGATE;
pf4_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSIF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF (almost_full_i = '0') THEN
IF (conv_integer(diff_pntr) >= pf_assert_val) THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF (((conv_integer(diff_pntr) = pf_negate_val) AND read_only_q = '1') OR
(conv_integer(diff_pntr) < pf_negate_val)) THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
END IF;
END PROCESS pf4_proc;
END GENERATE gpf4;
PROG_FULL <= prog_full_i;
END GENERATE gpf;
-------------------------------------------------------------------------------
-- Generate PROG_EMPTY flag
-------------------------------------------------------------------------------
gpe: IF (C_PROG_EMPTY_TYPE /= 0) GENERATE
-------------------------------------------------------------------------------
-- Generate PROG_EMPTY for single programmable threshold constant
-------------------------------------------------------------------------------
gpe1: IF (C_PROG_EMPTY_TYPE = 1) GENERATE
pe1_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
prog_empty_i <= '1';
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1') THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr_pe) = C_PE_ASSERT_VAL) AND read_only_q = '1') THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr_pe) = C_PE_ASSERT_VAL) AND write_only_q = '1') THEN
prog_empty_i <= '0' AFTER C_TCQ;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
END IF;
END PROCESS pe1_proc;
END GENERATE gpe1;
-------------------------------------------------------------------------------
-- Generate PROG_EMPTY for multiple programmable threshold constants
-------------------------------------------------------------------------------
gpe2: IF (C_PROG_EMPTY_TYPE = 2) GENERATE
pe2_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
prog_empty_i <= '1';
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1') THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr_pe) = C_PE_ASSERT_VAL) AND read_only_q = '1') THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr_pe) = C_PE_NEGATE_VAL) AND write_only_q = '1') THEN
prog_empty_i <= '0' AFTER C_TCQ;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
END IF;
END PROCESS pe2_proc;
END GENERATE gpe2;
-------------------------------------------------------------------------------
-- Generate PROG_EMPTY for single programmable threshold input port
-------------------------------------------------------------------------------
gpe3: IF (C_PROG_EMPTY_TYPE = 3) GENERATE
SIGNAL pe_assert_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
pe_assert_val <= PROG_EMPTY_THRESH - "10" WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_EMPTY_THRESH;
pe3_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
prog_empty_i <= '1';
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1') THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (almost_full_i = '0') THEN
IF (conv_integer(diff_pntr_pe) < pe_assert_val) THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (conv_integer(diff_pntr_pe) = pe_assert_val) THEN
IF (write_only_q = '1') THEN
prog_empty_i <= '0' AFTER C_TCQ;
ELSE
prog_empty_i <= '1' AFTER C_TCQ;
END IF;
ELSE
prog_empty_i <= '0' AFTER C_TCQ;
END IF;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
END IF;
END PROCESS pe3_proc;
END GENERATE gpe3;
-------------------------------------------------------------------------------
-- Generate PROG_EMPTY for multiple programmable threshold input ports
-------------------------------------------------------------------------------
gpe4: IF (C_PROG_EMPTY_TYPE = 4) GENERATE
SIGNAL pe_assert_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL pe_negate_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
pe_assert_val <= PROG_EMPTY_THRESH_ASSERT - "10" WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_EMPTY_THRESH_ASSERT;
pe_negate_val <= PROG_EMPTY_THRESH_NEGATE - "10" WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_EMPTY_THRESH_NEGATE;
pe4_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
prog_empty_i <= '1';
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1') THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (almost_full_i = '0') THEN
IF (conv_integer(diff_pntr_pe) <= pe_assert_val) THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (((conv_integer(diff_pntr_pe) = pe_negate_val) AND write_only_q = '1') OR
(conv_integer(diff_pntr_pe) > pe_negate_val)) THEN
prog_empty_i <= '0' AFTER C_TCQ;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
END IF;
END PROCESS pe4_proc;
END GENERATE gpe4;
PROG_EMPTY <= prog_empty_i;
END GENERATE gpe;
END GENERATE gpf_pe;
-------------------------------------------------------------------------------
-- overflow_i generation: Synchronous FIFO
-------------------------------------------------------------------------------
govflw: IF (C_HAS_OVERFLOW = 1) GENERATE
povflw: PROCESS (CLK)
BEGIN
IF CLK'event AND CLK = '1' THEN
overflow_i <= full_i AND WR_EN after C_TCQ;
END IF;
END PROCESS povflw;
END GENERATE govflw;
-------------------------------------------------------------------------------
-- underflow_i generation: Synchronous FIFO
-------------------------------------------------------------------------------
gunflw: IF (C_HAS_UNDERFLOW = 1) GENERATE
punflw: PROCESS (CLK)
BEGIN
IF CLK'event AND CLK = '1' THEN
underflow_i <= empty_i and RD_EN after C_TCQ;
END IF;
END PROCESS punflw;
END GENERATE gunflw;
-------------------------------------------------------------------------------
-- wr_ack_i generation: Synchronous FIFO
-------------------------------------------------------------------------------
gwack: IF (C_HAS_WR_ACK = 1) GENERATE
pwack: PROCESS (CLK,rst_i)
BEGIN
IF rst_i = '1' THEN
wr_ack_i <= '0' after C_TCQ;
ELSIF CLK'event AND CLK = '1' THEN
wr_ack_i <= '0' after C_TCQ;
IF srst_i = '1' THEN
wr_ack_i <= '0' after C_TCQ;
ELSIF WR_EN = '1' THEN
IF full_i /= '1' THEN
wr_ack_i <= '1' after C_TCQ;
END IF;
END IF;
END IF;
END PROCESS pwack;
END GENERATE gwack;
-----------------------------------------------------------------------------
-- valid_i generation: Synchronous FIFO
-----------------------------------------------------------------------------
gvld_i: IF (C_HAS_VALID = 1) GENERATE
PROCESS (rst_i , CLK )
BEGIN
IF rst_i = '1' THEN
valid_i <= '0' after C_TCQ;
ELSIF CLK'event AND CLK = '1' THEN
IF srst_i = '1' THEN
valid_i <= '0' after C_TCQ;
ELSE --srst_i=0
-- Setup default value for underflow and valid
valid_i <= '0' after C_TCQ;
IF RD_EN = '1' THEN
IF empty_i /= '1' THEN
valid_i <= '1' after C_TCQ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE gvld_i;
-----------------------------------------------------------------------------
--Delay Valid AND DOUT
--if C_MEMORY_TYPE=0 or 1, C_USE_EMBEDDED_REG=1, STD
-----------------------------------------------------------------------------
gnll_fifo1: IF (C_FIFO_TYPE < 2) GENERATE
gv0: IF (C_USE_EMBEDDED_REG=1 AND (NOT (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0))
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)) GENERATE
PROCESS (rst_i , CLK )
BEGIN
IF (rst_i = '1') THEN
IF (C_USE_DOUT_RST = 1) THEN
IF (CLK'event AND CLK = '1') THEN
DOUT <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
END IF;
IF (C_USE_ECC = 0) THEN
SBITERR <= '0' after C_TCQ;
DBITERR <= '0' after C_TCQ;
END IF;
ram_rd_en_d1 <= '0' after C_TCQ;
valid_d1 <= '0' after C_TCQ;
ELSIF (CLK 'event AND CLK = '1') THEN
ram_rd_en_d1 <= RD_EN AND (NOT empty_i) after C_TCQ;
valid_d1 <= valid_i after C_TCQ;
IF (srst_i = '1') THEN
IF (C_USE_DOUT_RST = 1) THEN
DOUT <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
ram_rd_en_d1 <= '0' after C_TCQ;
valid_d1 <= '0' after C_TCQ;
ELSIF (ram_rd_en_d1 = '1') THEN
DOUT <= dout_i after C_TCQ;
SBITERR <= sbiterr_i after C_TCQ;
DBITERR <= dbiterr_i after C_TCQ;
END IF;
END IF;
END PROCESS;
END GENERATE gv0;
END GENERATE gnll_fifo1;
gv1: IF (C_FIFO_TYPE = 2 OR (NOT(C_USE_EMBEDDED_REG=1 AND (NOT (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0))
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)))) GENERATE
valid_d1 <= valid_i;
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
END GENERATE gv1;
END behavioral;
--#############################################################################
--#############################################################################
-- Preload Latency 0 (First-Word Fall-Through) Module
--#############################################################################
--#############################################################################
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fifo_generator_v8_2_bhv_preload0 IS
GENERIC (
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_HAS_RST : integer := 0;
C_HAS_SRST : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USERVALID_LOW : integer := 0;
C_USERUNDERFLOW_LOW : integer := 0;
C_TCQ : time := 100 ps;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0
);
PORT (
RD_CLK : IN std_logic;
RD_RST : IN std_logic;
SRST : IN std_logic;
RD_EN : IN std_logic;
FIFOEMPTY : IN std_logic;
FIFODATA : IN std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
FIFOSBITERR : IN std_logic;
FIFODBITERR : IN std_logic;
USERDATA : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
USERVALID : OUT std_logic;
USERUNDERFLOW : OUT std_logic;
USEREMPTY : OUT std_logic;
USERALMOSTEMPTY : OUT std_logic;
RAMVALID : OUT std_logic;
FIFORDEN : OUT std_logic;
USERSBITERR : OUT std_logic := '0';
USERDBITERR : OUT std_logic := '0'
);
END fifo_generator_v8_2_bhv_preload0;
ARCHITECTURE behavioral OF fifo_generator_v8_2_bhv_preload0 IS
-----------------------------------------------------------------------------
-- FUNCTION hexstr_to_std_logic_vec
-- Returns a std_logic_vector for a hexadecimal string
-------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
SIGNAL USERDATA_int : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
SIGNAL preloadstage1 : std_logic := '0';
SIGNAL preloadstage2 : std_logic := '0';
SIGNAL ram_valid_i : std_logic := '0';
SIGNAL read_data_valid_i : std_logic := '0';
SIGNAL ram_regout_en : std_logic := '0';
SIGNAL ram_rd_en : std_logic := '0';
SIGNAL empty_i : std_logic := '1';
SIGNAL empty_q : std_logic := '1';
SIGNAL rd_en_q : std_logic := '0';
SIGNAL almost_empty_i : std_logic := '1';
SIGNAL almost_empty_q : std_logic := '1';
SIGNAL rd_rst_i : std_logic := '0';
SIGNAL srst_i : std_logic := '0';
BEGIN -- behavioral
grst: IF (C_HAS_RST = 1 OR C_ENABLE_RST_SYNC = 0) GENERATE
rd_rst_i <= RD_RST;
end generate grst;
ngrst: IF (C_HAS_RST = 0 AND C_ENABLE_RST_SYNC = 1) GENERATE
rd_rst_i <= '0';
END GENERATE ngrst;
--SRST
gsrst : IF (C_HAS_SRST=1) GENERATE
srst_i <= SRST;
END GENERATE gsrst;
--SRST
ngsrst : IF (C_HAS_SRST=0) GENERATE
srst_i <= '0';
END GENERATE ngsrst;
gnll_fifo: IF (C_FIFO_TYPE /= 2) GENERATE
--------------------------------------------------------------------------------
-- preloadstage2 indicates that stage2 needs to be updated. This is true
-- whenever read_data_valid is false, and RAM_valid is true.
--------------------------------------------------------------------------------
preloadstage2 <= ram_valid_i AND (NOT read_data_valid_i OR RD_EN);
--------------------------------------------------------------------------------
-- preloadstage1 indicates that stage1 needs to be updated. This is true
-- whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
-- false (indicating that Stage1 needs updating), or preloadstage2 is active
-- (indicating that Stage2 is going to update, so Stage1, therefore, must
-- also be updated to keep it valid.
--------------------------------------------------------------------------------
preloadstage1 <= (((NOT ram_valid_i) OR preloadstage2) AND (NOT FIFOEMPTY));
--------------------------------------------------------------------------------
-- Calculate RAM_REGOUT_EN
-- The output registers are controlled by the ram_regout_en signal.
-- These registers should be updated either when the output in Stage2 is
-- invalid (preloadstage2), OR when the user is reading, in which case the
-- Stage2 value will go invalid unless it is replenished.
--------------------------------------------------------------------------------
ram_regout_en <= preloadstage2;
--------------------------------------------------------------------------------
-- Calculate RAM_RD_EN
-- RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
-- update the value in Stage1.
-- One case when this happens is when preloadstage1=true, which indicates
-- that the data in Stage1 or Stage2 is invalid, and needs to automatically
-- be updated.
-- The other case is when the user is reading from the FIFO, which guarantees
-- that Stage1 or Stage2 will be invalid on the next clock cycle, unless it is
-- replinished by data from the memory. So, as long as the RAM has data in it,
-- a read of the RAM should occur.
--------------------------------------------------------------------------------
ram_rd_en <= (RD_EN AND NOT FIFOEMPTY) OR preloadstage1;
END GENERATE gnll_fifo;
gll_fifo: IF (C_FIFO_TYPE = 2) GENERATE
SIGNAL empty_d1 : STD_LOGIC := '1';
SIGNAL fe_of_empty : STD_LOGIC := '0';
SIGNAL curr_state : STD_LOGIC := '0';
SIGNAL next_state : STD_LOGIC := '0';
SIGNAL leaving_empty_fwft : STD_LOGIC := '0';
SIGNAL going_empty_fwft : STD_LOGIC := '0';
BEGIN
fsm_proc: PROCESS (curr_state, FIFOEMPTY, RD_EN)
BEGIN
CASE curr_state IS
WHEN '0' =>
IF (FIFOEMPTY = '0') THEN
next_state <= '1';
ELSE
next_state <= '0';
END IF;
WHEN '1' =>
IF (FIFOEMPTY = '1' AND RD_EN = '1') THEN
next_state <= '0';
ELSE
next_state <= '1';
END IF;
WHEN OTHERS =>
next_state <= '0';
END CASE;
END PROCESS fsm_proc;
empty_reg: PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i = '1') THEN
empty_d1 <= '1';
empty_i <= '1';
ram_valid_i <= '0';
curr_state <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF (srst_i = '1') THEN
empty_d1 <= '1' AFTER C_TCQ;
empty_i <= '1' AFTER C_TCQ;
ram_valid_i <= '0' AFTER C_TCQ;
curr_state <= '0' AFTER C_TCQ;
ELSE
empty_d1 <= FIFOEMPTY AFTER C_TCQ;
curr_state <= next_state AFTER C_TCQ;
empty_i <= going_empty_fwft OR (NOT leaving_empty_fwft AND empty_i) AFTER C_TCQ;
ram_valid_i <= next_state AFTER C_TCQ;
END IF;
END IF;
END PROCESS empty_reg;
fe_of_empty <= empty_d1 AND (NOT FIFOEMPTY);
prege: PROCESS (curr_state, FIFOEMPTY, RD_EN)
BEGIN
CASE curr_state IS
WHEN '0' =>
IF (FIFOEMPTY = '0') THEN
ram_regout_en <= '1';
ram_rd_en <= '1';
ELSE
ram_regout_en <= '0';
ram_rd_en <= '0';
END IF;
WHEN '1' =>
IF (FIFOEMPTY = '0' AND RD_EN = '1') THEN
ram_regout_en <= '1';
ram_rd_en <= '1';
ELSE
ram_regout_en <= '0';
ram_rd_en <= '0';
END IF;
WHEN OTHERS =>
ram_regout_en <= '0';
ram_rd_en <= '0';
END CASE;
END PROCESS prege;
ple: PROCESS (curr_state, fe_of_empty) -- Leaving Empty
BEGIN
CASE curr_state IS
WHEN '0' =>
leaving_empty_fwft <= fe_of_empty;
WHEN '1' =>
leaving_empty_fwft <= '1';
WHEN OTHERS =>
leaving_empty_fwft <= '0';
END CASE;
END PROCESS ple;
pge: PROCESS (curr_state, FIFOEMPTY, RD_EN) -- Going Empty
BEGIN
CASE curr_state IS
WHEN '1' =>
IF (FIFOEMPTY = '1' AND RD_EN = '1') THEN
going_empty_fwft <= '1';
ELSE
going_empty_fwft <= '0';
END IF;
WHEN OTHERS =>
going_empty_fwft <= '0';
END CASE;
END PROCESS pge;
END GENERATE gll_fifo;
--------------------------------------------------------------------------------
-- Calculate ram_valid
-- ram_valid indicates that the data in Stage1 is valid.
--
-- If the RAM is being read from on this clock cycle (ram_rd_en=1), then
-- ram_valid is certainly going to be true.
-- If the RAM is not being read from, but the output registers are being
-- updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
-- therefore causing ram_valid to be false.
-- Otherwise, ram_valid will remain unchanged.
--------------------------------------------------------------------------------
gvalid: IF (C_FIFO_TYPE < 2) GENERATE
regout_valid: PROCESS (RD_CLK, rd_rst_i)
BEGIN -- PROCESS regout_valid
IF rd_rst_i = '1' THEN -- asynchronous reset (active high)
ram_valid_i <= '0' after C_TCQ;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN -- rising clock edge
IF srst_i = '1' THEN -- synchronous reset (active high)
ram_valid_i <= '0' after C_TCQ;
ELSE
IF ram_rd_en = '1' THEN
ram_valid_i <= '1' after C_TCQ;
ELSE
IF ram_regout_en = '1' THEN
ram_valid_i <= '0' after C_TCQ;
ELSE
ram_valid_i <= ram_valid_i after C_TCQ;
END IF;
END IF;
END IF;
END IF;
END PROCESS regout_valid;
END GENERATE gvalid;
--------------------------------------------------------------------------------
-- Calculate READ_DATA_VALID
-- READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
-- Stage2 has valid data whenever Stage1 had valid data and ram_regout_en_i=1,
-- such that the data in Stage1 is propogated into Stage2.
--------------------------------------------------------------------------------
regout_dvalid : PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i='1') THEN
read_data_valid_i <= '0' after C_TCQ;
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF (srst_i='1') THEN
read_data_valid_i <= '0' after C_TCQ;
ELSE
read_data_valid_i <= ram_valid_i OR (read_data_valid_i AND NOT RD_EN) after C_TCQ;
END IF;
END IF; --RD_CLK
END PROCESS regout_dvalid;
-------------------------------------------------------------------------------
-- Calculate EMPTY
-- Defined as the inverse of READ_DATA_VALID
--
-- Description:
--
-- If read_data_valid_i indicates that the output is not valid,
-- and there is no valid data on the output of the ram to preload it
-- with, then we will report empty.
--
-- If there is no valid data on the output of the ram and we are
-- reading, then the FIFO will go empty.
--
-------------------------------------------------------------------------------
gempty: IF (C_FIFO_TYPE < 2) GENERATE
regout_empty : PROCESS (RD_CLK, rd_rst_i) --This is equivalent to (NOT read_data_valid_i)
BEGIN
IF (rd_rst_i='1') THEN
empty_i <= '1' after C_TCQ;
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF (srst_i='1') THEN
empty_i <= '1' after C_TCQ;
ELSE
empty_i <= (NOT ram_valid_i AND NOT read_data_valid_i) OR (NOT ram_valid_i AND RD_EN) after C_TCQ;
END IF;
END IF; --RD_CLK
END PROCESS regout_empty;
END GENERATE gempty;
regout_empty_q: PROCESS (RD_CLK)
BEGIN -- PROCESS regout_rd_en
IF RD_CLK'event AND RD_CLK = '1' THEN --
empty_q <= empty_i after C_TCQ;
END IF;
END PROCESS regout_empty_q;
regout_rd_en: PROCESS (RD_CLK)
BEGIN -- PROCESS regout_rd_en
IF RD_CLK'event AND RD_CLK = '1' THEN -- rising clock edge
rd_en_q <= RD_EN after C_TCQ;
END IF;
END PROCESS regout_rd_en;
-------------------------------------------------------------------------------
-- Calculate user_almost_empty
-- user_almost_empty is defined such that, unless more words are written
-- to the FIFO, the next read will cause the FIFO to go EMPTY.
--
-- In most cases, whenever the output registers are updated (due to a user
-- read or a preload condition), then user_almost_empty will update to
-- whatever RAM_EMPTY is.
--
-- The exception is when the output is valid, the user is not reading, and
-- Stage1 is not empty. In this condition, Stage1 will be preloaded from the
-- memory, so we need to make sure user_almost_empty deasserts properly under
-- this condition.
-------------------------------------------------------------------------------
regout_aempty: PROCESS (RD_CLK, rd_rst_i)
BEGIN -- PROCESS regout_empty
IF rd_rst_i = '1' THEN -- asynchronous reset (active high)
almost_empty_i <= '1' after C_TCQ;
almost_empty_q <= '1' after C_TCQ;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN -- rising clock edge
IF srst_i = '1' THEN -- synchronous reset (active high)
almost_empty_i <= '1' after C_TCQ;
almost_empty_q <= '1' after C_TCQ;
ELSE
IF ((ram_regout_en = '1') OR (FIFOEMPTY = '0' AND read_data_valid_i = '1' AND RD_EN='0')) THEN
almost_empty_i <= FIFOEMPTY after C_TCQ;
END IF;
almost_empty_q <= almost_empty_i after C_TCQ;
END IF;
END IF;
END PROCESS regout_aempty;
USEREMPTY <= empty_i;
USERALMOSTEMPTY <= almost_empty_i;
FIFORDEN <= ram_rd_en;
RAMVALID <= ram_valid_i;
guvh: IF C_USERVALID_LOW=0 GENERATE
USERVALID <= read_data_valid_i;
END GENERATE guvh;
guvl: if C_USERVALID_LOW=1 GENERATE
USERVALID <= NOT read_data_valid_i;
END GENERATE guvl;
gufh: IF C_USERUNDERFLOW_LOW=0 GENERATE
USERUNDERFLOW <= empty_q AND rd_en_q;
END GENERATE gufh;
gufl: if C_USERUNDERFLOW_LOW=1 GENERATE
USERUNDERFLOW <= NOT (empty_q AND rd_en_q);
END GENERATE gufl;
regout_lat0: PROCESS (RD_CLK, rd_rst_i)
BEGIN -- PROCESS regout_lat0
IF (rd_rst_i = '1') THEN -- asynchronous reset (active high)
IF (C_USE_ECC = 0) THEN -- Reset S/DBITERR only if ECC is OFF
USERSBITERR <= '0' after C_TCQ;
USERDBITERR <= '0' after C_TCQ;
END IF;
-- DRAM resets asynchronously
IF (C_USE_DOUT_RST = 1 AND C_MEMORY_TYPE = 2) THEN
USERDATA_int <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
-- BRAM resets synchronously
IF (C_USE_DOUT_RST = 1 AND C_MEMORY_TYPE < 2) THEN
IF (RD_CLK'event AND RD_CLK = '1') THEN
USERDATA_int <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
END IF;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN -- rising clock edge
IF (srst_i = '1') THEN -- synchronous reset (active high)
IF (C_USE_ECC = 0) THEN -- Reset S/DBITERR only if ECC is OFF
USERSBITERR <= '0' after C_TCQ;
USERDBITERR <= '0' after C_TCQ;
END IF;
IF (C_USE_DOUT_RST = 1) THEN -- synchronous reset (active high)
USERDATA_int <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
ELSE
IF (ram_regout_en = '1') THEN
USERDATA_int <= FIFODATA after C_TCQ;
USERSBITERR <= FIFOSBITERR after C_TCQ;
USERDBITERR <= FIFODBITERR after C_TCQ;
END IF;
END IF;
END IF;
END PROCESS regout_lat0;
USERDATA <= USERDATA_int ; -- rle, fixed bug R62
END behavioral;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Top-level Behavioral Model for Conventional FIFO
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY XilinxCoreLib;
USE XilinxCoreLib.fifo_generator_v8_2_bhv_as;
USE XilinxCoreLib.fifo_generator_v8_2_bhv_ss;
-------------------------------------------------------------------------------
-- Top-level Entity Declaration - This is the top-level of the conventional
-- FIFO Bhv Model
-------------------------------------------------------------------------------
ENTITY fifo_generator_v8_2_conv IS
GENERIC (
---------------------------------------------------------------------------
-- Generic Declarations
---------------------------------------------------------------------------
C_COMMON_CLOCK : integer := 0;
C_COUNT_TYPE : integer := 0; --not used
C_DATA_COUNT_WIDTH : integer := 2;
C_DEFAULT_VALUE : string := ""; --not used
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_ENABLE_RLOCS : integer := 0; --not used
C_FAMILY : string := ""; --not used in bhv model
C_FULL_FLAGS_RST_VAL : integer := 0;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_BACKUP : integer := 0; --not used
C_HAS_DATA_COUNT : integer := 0;
C_HAS_INT_CLK : integer := 0; --not used in bhv model
C_HAS_MEMINIT_FILE : integer := 0; --not used
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 0;
C_HAS_RD_RST : integer := 0; --not used
C_HAS_RST : integer := 1;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 0;
C_HAS_WR_RST : integer := 0; --not used
C_IMPLEMENTATION_TYPE : integer := 0;
C_INIT_WR_PNTR_VAL : integer := 0; --not used
C_MEMORY_TYPE : integer := 1;
C_MIF_FILE_NAME : string := ""; --not used
C_OPTIMIZATION_MODE : integer := 0; --not used
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PRIM_FIFO_TYPE : string := "4kx4"; --not used in bhv model
C_PROG_EMPTY_THRESH_ASSERT_VAL: integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL: integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 2;
C_RD_DEPTH : integer := 256;
C_RD_FREQ : integer := 1; --not used in bhv model
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FIFO16_FLAGS : integer := 0; --not used in bhv model
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 2;
C_WR_DEPTH : integer := 256;
C_WR_FREQ : integer := 1; --not used in bhv model
C_WR_PNTR_WIDTH : integer := 8;
C_WR_RESPONSE_LATENCY : integer := 1; --not used
C_MSGON_VAL : integer := 1; --not used in bhv model
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
BACKUP : IN std_logic := '0';
BACKUP_MARKER : IN std_logic := '0';
CLK : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_CLK : IN std_logic := '0';
WR_RST : IN std_logic := '0';
RD_CLK : IN std_logic := '0';
RD_RST : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0); --
WR_EN : IN std_logic; --Mandatory input
RD_EN : IN std_logic; --Mandatory input
--Mandatory input
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
INT_CLK : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
FULL : OUT std_logic;
ALMOST_FULL : OUT std_logic;
WR_ACK : OUT std_logic;
OVERFLOW : OUT std_logic;
EMPTY : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
VALID : OUT std_logic;
UNDERFLOW : OUT std_logic;
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
SBITERR : OUT std_logic := '0';
DBITERR : OUT std_logic := '0'
);
END fifo_generator_v8_2_conv;
-------------------------------------------------------------------------------
-- Definition of Parameters
-------------------------------------------------------------------------------
-- C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0)
-- C_COUNT_TYPE : --not used
-- C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus
-- C_DEFAULT_VALUE : --not used
-- C_DIN_WIDTH : Width of DIN bus
-- C_DOUT_RST_VAL : Reset value of DOUT
-- C_DOUT_WIDTH : Width of DOUT bus
-- C_ENABLE_RLOCS : --not used
-- C_FAMILY : not used in bhv model
-- C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1)
-- C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag
-- C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag
-- C_HAS_BACKUP : --not used
-- C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus
-- C_HAS_INT_CLK : not used in bhv model
-- C_HAS_MEMINIT_FILE : --not used
-- C_HAS_OVERFLOW : 1=Core has OVERFLOW flag
-- C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus
-- C_HAS_RD_RST : --not used
-- C_HAS_RST : 1=Core has Async Rst
-- C_HAS_SRST : 1=Core has Sync Rst
-- C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag
-- C_HAS_VALID : 1=Core has VALID flag
-- C_HAS_WR_ACK : 1=Core has WR_ACK flag
-- C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus
-- C_HAS_WR_RST : --not used
-- C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram
-- 1=Common-Clock ShiftRam
-- 2=Indep. Clocks Bram/Dram
-- 3=Virtex-4 Built-in
-- 4=Virtex-5 Built-in
-- C_INIT_WR_PNTR_VAL : --not used
-- C_MEMORY_TYPE : 1=Block RAM
-- 2=Distributed RAM
-- 3=Shift RAM
-- 4=Built-in FIFO
-- C_MIF_FILE_NAME : --not used
-- C_OPTIMIZATION_MODE : --not used
-- C_OVERFLOW_LOW : 1=OVERFLOW active low
-- C_PRELOAD_LATENCY : Latency of read: 0, 1, 2
-- C_PRELOAD_REGS : 1=Use output registers
-- C_PRIM_FIFO_TYPE : not used in bhv model
-- C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold
-- C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold
-- C_PROG_EMPTY_TYPE : 0=No programmable empty
-- 1=Single prog empty thresh constant
-- 2=Multiple prog empty thresh constants
-- 3=Single prog empty thresh input
-- 4=Multiple prog empty thresh inputs
-- C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold
-- C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold
-- C_PROG_FULL_TYPE : 0=No prog full
-- 1=Single prog full thresh constant
-- 2=Multiple prog full thresh constants
-- 3=Single prog full thresh input
-- 4=Multiple prog full thresh inputs
-- C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus
-- C_RD_DEPTH : Depth of read interface (2^N)
-- C_RD_FREQ : not used in bhv model
-- C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH)
-- C_UNDERFLOW_LOW : 1=UNDERFLOW active low
-- C_USE_DOUT_RST : 1=Resets DOUT on RST
-- C_USE_ECC : not used in bhv model
-- C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register
-- C_USE_FIFO16_FLAGS : not used in bhv model
-- C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count
-- C_VALID_LOW : 1=VALID active low
-- C_WR_ACK_LOW : 1=WR_ACK active low
-- C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus
-- C_WR_DEPTH : Depth of write interface (2^N)
-- C_WR_FREQ : not used in bhv model
-- C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH)
-- C_WR_RESPONSE_LATENCY : --not used
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- BACKUP : Not used
-- BACKUP_MARKER: Not used
-- CLK : Clock
-- DIN : Input data bus
-- PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag
-- PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag
-- PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag
-- PROG_FULL_THRESH : Threshold for Programmable Full Flag
-- PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag
-- PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag
-- RD_CLK : Read Domain Clock
-- RD_EN : Read enable
-- RD_RST : Not used
-- RST : Asynchronous Reset
-- SRST : Synchronous Reset
-- WR_CLK : Write Domain Clock
-- WR_EN : Write enable
-- WR_RST : Not used
-- INT_CLK : Internal Clock
-- ALMOST_EMPTY : One word remaining in FIFO
-- ALMOST_FULL : One empty space remaining in FIFO
-- DATA_COUNT : Number of data words in fifo( synchronous to CLK)
-- DOUT : Output data bus
-- EMPTY : Empty flag
-- FULL : Full flag
-- OVERFLOW : Last write rejected
-- PROG_EMPTY : Programmable Empty Flag
-- PROG_FULL : Programmable Full Flag
-- RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)
-- UNDERFLOW : Last read rejected
-- VALID : Last read acknowledged, DOUT bus VALID
-- WR_ACK : Last write acknowledged
-- WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)
-- SBITERR : Single Bit ECC Error Detected
-- DBITERR : Double Bit ECC Error Detected
-------------------------------------------------------------------------------
ARCHITECTURE behavioral OF fifo_generator_v8_2_conv IS
-----------------------------------------------------------------------------
-- FUNCTION two_comp
-- Returns a 2's complement value
-------------------------------------------------------------------------------
FUNCTION two_comp(
vect : std_logic_vector)
RETURN std_logic_vector IS
VARIABLE local_vect : std_logic_vector(vect'high DOWNTO 0);
VARIABLE toggle : integer := 0;
BEGIN
FOR i IN 0 TO vect'high LOOP
IF (toggle = 1) THEN
IF (vect(i) = '0') THEN
local_vect(i) := '1';
ELSE
local_vect(i) := '0';
END IF;
ELSE
local_vect(i) := vect(i);
IF (vect(i) = '1') THEN
toggle := 1;
END IF;
END IF;
END LOOP;
RETURN local_vect;
END two_comp;
-----------------------------------------------------------------------------
-- FUNCTION int_2_std_logic_vector
-- Returns a std_logic_vector for an integer value for a given width.
-------------------------------------------------------------------------------
FUNCTION int_2_std_logic_vector(
value, bitwidth : integer )
RETURN std_logic_vector IS
VARIABLE running_value : integer := value;
VARIABLE running_result : std_logic_vector(bitwidth-1 DOWNTO 0);
BEGIN
IF (value < 0) THEN
running_value := -1 * value;
END IF;
FOR i IN 0 TO bitwidth-1 LOOP
IF running_value MOD 2 = 0 THEN
running_result(i) := '0';
ELSE
running_result(i) := '1';
END IF;
running_value := running_value/2;
END LOOP;
IF (value < 0) THEN -- find the 2s complement
RETURN two_comp(running_result);
ELSE
RETURN running_result;
END IF;
END int_2_std_logic_vector;
COMPONENT fifo_generator_v8_2_bhv_as
GENERIC (
--------------------------------------------------------------------------------
-- Generic Declarations
--------------------------------------------------------------------------------
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 2;
C_HAS_RST : integer := 1;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 2;
C_MEMORY_TYPE : integer := 1;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 0;
C_RD_DEPTH : integer := 256;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 0;
C_WR_DEPTH : integer := 256;
C_WR_PNTR_WIDTH : integer := 8;
C_TCQ : time := 100 ps;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0);
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
RD_CLK : IN std_logic;
RD_EN : IN std_logic;
RD_EN_USER : IN std_logic;
RST : IN std_logic;
RST_FULL_GEN : IN std_logic := '0';
RST_FULL_FF : IN std_logic := '0';
WR_RST : IN std_logic;
RD_RST : IN std_logic;
WR_CLK : IN std_logic;
WR_EN : IN std_logic;
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
USER_EMPTY_FB : IN std_logic := '1';
ALMOST_EMPTY : OUT std_logic;
ALMOST_FULL : OUT std_logic;
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
EMPTY : OUT std_logic;
FULL : OUT std_logic;
OVERFLOW : OUT std_logic;
PROG_EMPTY : OUT std_logic;
PROG_FULL : OUT std_logic;
VALID : OUT std_logic;
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
UNDERFLOW : OUT std_logic;
WR_ACK : OUT std_logic;
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
DBITERR : OUT std_logic := '0';
SBITERR : OUT std_logic := '0'
);
END COMPONENT;
COMPONENT fifo_generator_v8_2_bhv_ss
GENERIC (
--------------------------------------------------------------------------------
-- Generic Declarations (alphabetical)
--------------------------------------------------------------------------------
C_DATA_COUNT_WIDTH : integer := 2;
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_DATA_COUNT : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RST : integer := 0;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_MEMORY_TYPE : integer := 1;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DEPTH : integer := 256;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_ECC : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DEPTH : integer := 256;
C_WR_PNTR_WIDTH : integer := 8;
C_TCQ : time := 100 ps;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
CLK : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
RD_EN : IN std_logic := '0';
RST : IN std_logic := '0';
RST_FULL_GEN : IN std_logic := '0';
RST_FULL_FF : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_EN : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
ALMOST_EMPTY : OUT std_logic;
ALMOST_FULL : OUT std_logic;
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
EMPTY : OUT std_logic;
FULL : OUT std_logic;
OVERFLOW : OUT std_logic;
PROG_EMPTY : OUT std_logic;
PROG_FULL : OUT std_logic;
VALID : OUT std_logic;
UNDERFLOW : OUT std_logic;
WR_ACK : OUT std_logic;
DBITERR : OUT std_logic := '0';
SBITERR : OUT std_logic := '0'
);
END COMPONENT;
COMPONENT fifo_generator_v8_2_bhv_preload0
GENERIC (
C_DOUT_RST_VAL : string;
C_DOUT_WIDTH : integer;
C_HAS_RST : integer;
C_HAS_SRST : integer;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USERVALID_LOW : integer := 0;
C_USERUNDERFLOW_LOW : integer := 0;
C_TCQ : time := 100 ps;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0
);
PORT (
RD_CLK : IN std_logic;
RD_RST : IN std_logic;
SRST : IN std_logic;
RD_EN : IN std_logic;
FIFOEMPTY : IN std_logic;
FIFODATA : IN std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
FIFOSBITERR : IN std_logic;
FIFODBITERR : IN std_logic;
USERDATA : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
USERVALID : OUT std_logic;
USERUNDERFLOW : OUT std_logic;
USEREMPTY : OUT std_logic;
USERALMOSTEMPTY : OUT std_logic;
RAMVALID : OUT std_logic;
FIFORDEN : OUT std_logic;
USERSBITERR : OUT std_logic;
USERDBITERR : OUT std_logic
);
END COMPONENT;
-- Constant to have clock to register delay
CONSTANT C_TCQ : time := 100 ps;
SIGNAL zero : std_logic := '0';
SIGNAL CLK_INT : std_logic := '0';
-----------------------------------------------------------------------------
-- Internal Signals for delayed input signals
-- All the input signals except Clock are delayed by 100 ps and then given to
-- the models.
-----------------------------------------------------------------------------
SIGNAL rst_delayed : std_logic := '0';
SIGNAL srst_delayed : std_logic := '0';
SIGNAL wr_rst_delayed : std_logic := '0';
SIGNAL rd_rst_delayed : std_logic := '0';
SIGNAL din_delayed : std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wr_en_delayed : std_logic := '0';
SIGNAL rd_en_delayed : std_logic := '0';
SIGNAL prog_empty_thresh_delayed : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL prog_empty_thresh_assert_delayed : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL prog_empty_thresh_negate_delayed : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL prog_full_thresh_delayed : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL prog_full_thresh_assert_delayed : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL prog_full_thresh_negate_delayed : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL injectdbiterr_delayed : std_logic := '0';
SIGNAL injectsbiterr_delayed : std_logic := '0';
-----------------------------------------------------------------------------
-- Internal Signals
-- In the normal case, these signals tie directly to the FIFO's inputs and
-- outputs.
-- In the case of Preload Latency 0 or 1, these are the intermediate
-- signals between the internal FIFO and the preload logic.
-----------------------------------------------------------------------------
SIGNAL rd_en_fifo_in : std_logic;
SIGNAL dout_fifo_out : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
SIGNAL empty_fifo_out : std_logic;
SIGNAL almost_empty_fifo_out : std_logic;
SIGNAL valid_fifo_out : std_logic;
SIGNAL underflow_fifo_out : std_logic;
SIGNAL rd_data_count_fifo_out : std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
SIGNAL wr_data_count_fifo_out : std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
SIGNAL data_count_fifo_out : std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
SIGNAL DATA_COUNT_FWFT : std_logic_vector(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL SS_FWFT_RD : std_logic := '0' ;
SIGNAL SS_FWFT_WR : std_logic := '0' ;
SIGNAL FULL_int : std_logic ;
SIGNAL dout_p0_out : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
signal valid_p0_out : std_logic;
signal empty_p0_out : std_logic;
signal underflow_p0_out : std_logic;
signal almost_empty_p0_out : std_logic;
signal empty_p0_out_q : std_logic;
signal almost_empty_p0_out_q : std_logic;
SIGNAL ram_valid : std_logic; --Internal signal used to monitor the
--ram_valid state
signal rst_fwft : std_logic;
signal sbiterr_fifo_out : std_logic;
signal dbiterr_fifo_out : std_logic;
signal wr_rst_i : std_logic := '0';
signal rd_rst_i : std_logic := '0';
signal rst_i : std_logic := '0';
signal rst_full_gen_i : std_logic := '0';
signal rst_full_ff_i : std_logic := '0';
signal rst_2_sync : std_logic := '0';
signal clk_2_sync : std_logic := '0';
-----------------------------------------------------------------------------
-- FUNCTION if_then_else
-- Returns a true case or flase case based on the condition
-------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : integer;
false_case : integer)
RETURN integer IS
VARIABLE retval : integer := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-----------------------------------------------------------------------------
-- FUNCTION log2roundup
-- Returns a log2 of the input value
-----------------------------------------------------------------------------
FUNCTION log2roundup (
data_value : integer)
RETURN integer IS
VARIABLE width : integer := 0;
VARIABLE cnt : integer := 1;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
CONSTANT FULL_FLAGS_RST_VAL : integer := if_then_else((C_HAS_SRST = 1),0,C_FULL_FLAGS_RST_VAL);
CONSTANT IS_WR_PNTR_WIDTH_CORRECT : integer := if_then_else((C_WR_PNTR_WIDTH = log2roundup(C_WR_DEPTH)),1,0);
CONSTANT IS_RD_PNTR_WIDTH_CORRECT : integer := if_then_else((C_RD_PNTR_WIDTH = log2roundup(C_RD_DEPTH)),1,0);
BEGIN
rst_delayed <= RST AFTER C_TCQ;
srst_delayed <= SRST AFTER C_TCQ;
wr_rst_delayed <= WR_RST AFTER C_TCQ;
rd_rst_delayed <= RD_RST AFTER C_TCQ;
din_delayed <= DIN AFTER C_TCQ;
wr_en_delayed <= WR_EN AFTER C_TCQ;
rd_en_delayed <= RD_EN AFTER C_TCQ;
prog_empty_thresh_delayed <= PROG_EMPTY_THRESH AFTER C_TCQ;
prog_empty_thresh_assert_delayed <= PROG_EMPTY_THRESH_ASSERT AFTER C_TCQ;
prog_empty_thresh_negate_delayed <= PROG_EMPTY_THRESH_NEGATE AFTER C_TCQ;
prog_full_thresh_delayed <= PROG_FULL_THRESH AFTER C_TCQ;
prog_full_thresh_assert_delayed <= PROG_FULL_THRESH_ASSERT AFTER C_TCQ;
prog_full_thresh_negate_delayed <= PROG_FULL_THRESH_NEGATE AFTER C_TCQ;
injectdbiterr_delayed <= INJECTDBITERR AFTER C_TCQ;
injectsbiterr_delayed <= INJECTSBITERR AFTER C_TCQ;
--Assign Ground Signal
zero <= '0';
ASSERT (C_MEMORY_TYPE /= 4) REPORT "FAILURE : Behavioral models for Virtex-4, Virtex-5, Virtex-6 and 7-Series FPGA's built-in FIFO configurations is currently not supported. Please select the structural simulation model option in CORE Generator. You can enable this in CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information." SEVERITY FAILURE;
--
ASSERT (C_IMPLEMENTATION_TYPE /= 2) REPORT "WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information." SEVERITY NOTE;
ASSERT (IS_WR_PNTR_WIDTH_CORRECT /= 0) REPORT "FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH." SEVERITY FAILURE;
ASSERT (IS_RD_PNTR_WIDTH_CORRECT /= 0) REPORT "FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH." SEVERITY FAILURE;
gen_ss : IF ((C_IMPLEMENTATION_TYPE = 0) OR (C_IMPLEMENTATION_TYPE = 1)) GENERATE
fgss : fifo_generator_v8_2_bhv_ss
GENERIC MAP (
C_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH,
C_DIN_WIDTH => C_DIN_WIDTH,
C_DOUT_RST_VAL => C_DOUT_RST_VAL,
C_DOUT_WIDTH => C_DOUT_WIDTH,
C_FULL_FLAGS_RST_VAL => FULL_FLAGS_RST_VAL,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_DATA_COUNT => C_HAS_DATA_COUNT,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_HAS_RST => C_HAS_RST,
C_HAS_SRST => C_HAS_SRST,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_HAS_VALID => C_HAS_VALID,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_MEMORY_TYPE => C_MEMORY_TYPE,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY,
C_PRELOAD_REGS => C_PRELOAD_REGS,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL,
C_PROG_EMPTY_THRESH_NEGATE_VAL => C_PROG_EMPTY_THRESH_NEGATE_VAL,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => C_PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE,
C_RD_DEPTH => C_RD_DEPTH,
C_RD_PNTR_WIDTH => C_RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_USE_ECC => C_USE_ECC,
C_USE_DOUT_RST => C_USE_DOUT_RST,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG,
C_VALID_LOW => C_VALID_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DEPTH => C_WR_DEPTH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH,
C_TCQ => C_TCQ,
C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE,
C_FIFO_TYPE => C_FIFO_TYPE
)
PORT MAP(
--Inputs
CLK => CLK,
DIN => din_delayed,
PROG_EMPTY_THRESH => prog_empty_thresh_delayed,
PROG_EMPTY_THRESH_ASSERT => prog_empty_thresh_assert_delayed,
PROG_EMPTY_THRESH_NEGATE => prog_empty_thresh_negate_delayed,
PROG_FULL_THRESH => prog_full_thresh_delayed,
PROG_FULL_THRESH_ASSERT => prog_full_thresh_assert_delayed,
PROG_FULL_THRESH_NEGATE => prog_full_thresh_negate_delayed,
RD_EN => rd_en_fifo_in,
RST => rst_i,
SRST => srst_delayed,
RST_FULL_GEN => rst_full_gen_i,
RST_FULL_FF => rst_full_ff_i,
WR_EN => wr_en_delayed,
INJECTDBITERR => injectdbiterr_delayed,
INJECTSBITERR => injectsbiterr_delayed,
--Outputs
ALMOST_EMPTY => almost_empty_fifo_out,
ALMOST_FULL => ALMOST_FULL,
DATA_COUNT => data_count_fifo_out,
DOUT => dout_fifo_out,
EMPTY => empty_fifo_out,
FULL => FULL_int,
OVERFLOW => OVERFLOW,
PROG_EMPTY => PROG_EMPTY,
PROG_FULL => PROG_FULL,
UNDERFLOW => underflow_fifo_out,
VALID => valid_fifo_out,
WR_ACK => WR_ACK,
DBITERR => dbiterr_fifo_out,
SBITERR => sbiterr_fifo_out
);
END GENERATE gen_ss;
gen_as : IF (C_IMPLEMENTATION_TYPE = 2 OR C_FIFO_TYPE = 3) GENERATE
fgas : fifo_generator_v8_2_bhv_as
GENERIC MAP (
C_DIN_WIDTH => C_DIN_WIDTH,
C_DOUT_RST_VAL => C_DOUT_RST_VAL,
C_DOUT_WIDTH => C_DOUT_WIDTH,
C_FULL_FLAGS_RST_VAL => C_FULL_FLAGS_RST_VAL,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_HAS_RD_DATA_COUNT => C_HAS_RD_DATA_COUNT,
C_HAS_RST => C_HAS_RST,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_HAS_VALID => C_HAS_VALID,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_DATA_COUNT,
C_MEMORY_TYPE => C_MEMORY_TYPE,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY,
C_PRELOAD_REGS => C_PRELOAD_REGS,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL,
C_PROG_EMPTY_THRESH_NEGATE_VAL => C_PROG_EMPTY_THRESH_NEGATE_VAL,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => C_PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE,
C_RD_DATA_COUNT_WIDTH => C_RD_DATA_COUNT_WIDTH,
C_RD_DEPTH => C_RD_DEPTH,
C_RD_PNTR_WIDTH => C_RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_USE_ECC => C_USE_ECC,
C_USE_DOUT_RST => C_USE_DOUT_RST,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG,
C_USE_FWFT_DATA_COUNT => C_USE_FWFT_DATA_COUNT,
C_VALID_LOW => C_VALID_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => C_WR_DATA_COUNT_WIDTH,
C_WR_DEPTH => C_WR_DEPTH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH,
C_TCQ => C_TCQ,
C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE,
C_FIFO_TYPE => C_FIFO_TYPE
)
PORT MAP(
--Inputs
WR_CLK => WR_CLK,
RD_CLK => RD_CLK,
RST => rst_i,
RST_FULL_GEN => rst_full_gen_i,
RST_FULL_FF => rst_full_ff_i,
WR_RST => wr_rst_i,
RD_RST => rd_rst_i,
DIN => din_delayed,
RD_EN => rd_en_fifo_in,
WR_EN => wr_en_delayed,
RD_EN_USER => rd_en_delayed,
PROG_FULL_THRESH => prog_full_thresh_delayed,
PROG_EMPTY_THRESH_ASSERT => prog_empty_thresh_assert_delayed,
PROG_EMPTY_THRESH_NEGATE => prog_empty_thresh_negate_delayed,
PROG_EMPTY_THRESH => prog_empty_thresh_delayed,
PROG_FULL_THRESH_ASSERT => prog_full_thresh_assert_delayed,
PROG_FULL_THRESH_NEGATE => prog_full_thresh_negate_delayed,
INJECTDBITERR => injectdbiterr_delayed,
INJECTSBITERR => injectsbiterr_delayed,
USER_EMPTY_FB => empty_p0_out,
--Outputs
DOUT => dout_fifo_out,
FULL => FULL_int,
ALMOST_FULL => ALMOST_FULL,
WR_ACK => WR_ACK,
OVERFLOW => OVERFLOW,
EMPTY => empty_fifo_out,
ALMOST_EMPTY => almost_empty_fifo_out,
VALID => valid_fifo_out,
UNDERFLOW => underflow_fifo_out,
RD_DATA_COUNT => rd_data_count_fifo_out,
WR_DATA_COUNT => wr_data_count_fifo_out,
PROG_FULL => PROG_FULL,
PROG_EMPTY => PROG_EMPTY,
DBITERR => dbiterr_fifo_out,
SBITERR => sbiterr_fifo_out
);
END GENERATE gen_as;
-------------------------------------------------------------------------
-- Connect internal clock used for FWFT logic based on C_COMMON_CLOCK ---
-------------------------------------------------------------------------
clock_fwft_common: IF (C_COMMON_CLOCK=1 ) GENERATE
CLK_INT <= CLK;
END GENERATE clock_fwft_common;
clock_fwft: IF (C_COMMON_CLOCK= 0 ) GENERATE
CLK_INT <= RD_CLK;
END GENERATE clock_fwft;
-----------------------------------------------------------------------------
-- Connect Internal Signals
-- In the normal case, these signals tie directly to the FIFO's inputs and
-- outputs.
-- In the case of Preload Latency 0 or 1, these are the intermediate
-- signals between the internal FIFO and the preload logic.
-----------------------------------------------------------------------------
latnrm: IF (C_PRELOAD_LATENCY=1 OR C_PRELOAD_LATENCY=2 OR C_FIFO_TYPE = 3) GENERATE
rd_en_fifo_in <= rd_en_delayed;
DOUT <= dout_fifo_out;
VALID <= valid_fifo_out;
EMPTY <= empty_fifo_out;
ALMOST_EMPTY <= almost_empty_fifo_out;
UNDERFLOW <= underflow_fifo_out;
RD_DATA_COUNT <= rd_data_count_fifo_out;
WR_DATA_COUNT <= wr_data_count_fifo_out;
SBITERR <= sbiterr_fifo_out;
DBITERR <= dbiterr_fifo_out;
END GENERATE latnrm;
lat0: IF ((C_PRELOAD_REGS = 1) AND (C_PRELOAD_LATENCY = 0) AND C_FIFO_TYPE /= 3) GENERATE
rst_fwft <= rd_rst_i WHEN (C_COMMON_CLOCK = 0) ELSE rst_i WHEN (C_HAS_RST = 1) ELSE '0';
lat0logic : fifo_generator_v8_2_bhv_preload0
GENERIC MAP (
C_DOUT_RST_VAL => C_DOUT_RST_VAL,
C_DOUT_WIDTH => C_DOUT_WIDTH,
C_HAS_RST => C_HAS_RST,
C_HAS_SRST => C_HAS_SRST,
C_USE_DOUT_RST => C_USE_DOUT_RST,
C_USE_ECC => C_USE_ECC,
C_USERVALID_LOW => C_VALID_LOW,
C_USERUNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE,
C_MEMORY_TYPE => C_MEMORY_TYPE,
C_FIFO_TYPE => C_FIFO_TYPE
)
PORT MAP (
RD_CLK => CLK_INT,
RD_RST => rst_fwft,
SRST => srst_delayed,
RD_EN => rd_en_delayed,
FIFOEMPTY => empty_fifo_out,
FIFODATA => dout_fifo_out,
FIFOSBITERR => sbiterr_fifo_out,
FIFODBITERR => dbiterr_fifo_out,
USERDATA => dout_p0_out,
USERVALID => valid_p0_out,
USEREMPTY => empty_p0_out,
USERALMOSTEMPTY => almost_empty_p0_out,
USERUNDERFLOW => underflow_p0_out,
RAMVALID => ram_valid, --Used for observing the state of the ram_valid
FIFORDEN => rd_en_fifo_in,
USERSBITERR => SBITERR,
USERDBITERR => DBITERR
);
rdcg: IF (C_USE_FWFT_DATA_COUNT=1 AND (C_RD_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH)) GENERATE
eclk: PROCESS (CLK_INT,rst_fwft)
BEGIN -- process eclk
IF (rst_fwft='1') THEN
empty_p0_out_q <= '1' after C_TCQ;
almost_empty_p0_out_q <= '1' after C_TCQ;
ELSIF CLK_INT'event AND CLK_INT = '1' THEN -- rising clock edge
empty_p0_out_q <= empty_p0_out after C_TCQ;
almost_empty_p0_out_q <= almost_empty_p0_out after C_TCQ;
END IF;
END PROCESS eclk;
rcsproc: PROCESS (rd_data_count_fifo_out, empty_p0_out_q,
almost_empty_p0_out_q,rst_fwft)
BEGIN -- process rcsproc
IF (empty_p0_out_q='1' OR rst_fwft='1') THEN
RD_DATA_COUNT <= int_2_std_logic_vector(0, C_RD_DATA_COUNT_WIDTH);
ELSIF (almost_empty_p0_out_q='1') THEN
RD_DATA_COUNT <= int_2_std_logic_vector(1, C_RD_DATA_COUNT_WIDTH);
ELSE
RD_DATA_COUNT <= rd_data_count_fifo_out ;
END IF;
END PROCESS rcsproc;
END GENERATE rdcg;
rdcg1: IF (C_USE_FWFT_DATA_COUNT=1 AND (C_RD_DATA_COUNT_WIDTH <= C_RD_PNTR_WIDTH)) GENERATE
eclk1: PROCESS (CLK_INT,rst_fwft)
BEGIN -- process eclk
IF (rst_fwft='1') THEN
empty_p0_out_q <= '1' after C_TCQ;
almost_empty_p0_out_q <= '1' after C_TCQ;
ELSIF CLK_INT'event AND CLK_INT = '1' THEN -- rising clock edge
empty_p0_out_q <= empty_p0_out after C_TCQ;
almost_empty_p0_out_q <= almost_empty_p0_out after C_TCQ;
END IF;
END PROCESS eclk1;
rcsproc1: PROCESS (rd_data_count_fifo_out, empty_p0_out_q,
almost_empty_p0_out_q,rst_fwft)
BEGIN -- process rcsproc
IF (empty_p0_out_q='1' OR rst_fwft='1') THEN
RD_DATA_COUNT <= int_2_std_logic_vector(0, C_RD_DATA_COUNT_WIDTH);
ELSIF (almost_empty_p0_out_q='1') THEN
RD_DATA_COUNT <= int_2_std_logic_vector(0, C_RD_DATA_COUNT_WIDTH);
ELSE
RD_DATA_COUNT <= rd_data_count_fifo_out ;
END IF;
END PROCESS rcsproc1;
END GENERATE rdcg1;
nrdcg: IF (C_USE_FWFT_DATA_COUNT=0) GENERATE
RD_DATA_COUNT <= rd_data_count_fifo_out;
END GENERATE nrdcg;
WR_DATA_COUNT <= wr_data_count_fifo_out;
---------------------------------------------------
-- logics for common-clock data count with fwft
-- For common-clock FIFOs with FWFT, data count
-- is calculated as an up-down counter to maintain
-- accuracy.
---------------------------------------------------
gfwft_rd: IF (C_VALID_LOW = 0) GENERATE
SS_FWFT_RD <= rd_en_delayed AND valid_p0_out ;
END GENERATE gfwft_rd;
ngfwft_rd: IF (C_VALID_LOW = 1) GENERATE
SS_FWFT_RD <= rd_en_delayed AND NOT valid_p0_out ;
END GENERATE ngfwft_rd;
SS_FWFT_WR <= wr_en_delayed AND (NOT FULL_int) ;
cc_data_cnt: IF (C_HAS_DATA_COUNT = 1 AND C_USE_FWFT_DATA_COUNT = 1) GENERATE
count_fwft: PROCESS (CLK, rst_fwft)
BEGIN
IF (rst_fwft = '1' AND C_HAS_RST=1) THEN
DATA_COUNT_FWFT <= (OTHERS=>'0') after C_TCQ;
ELSIF CLK'event AND CLK = '1' THEN
IF (srst_delayed='1' AND C_HAS_SRST=1) THEN
DATA_COUNT_FWFT <= (OTHERS=>'0') after C_TCQ;
ELSE
IF (SS_FWFT_WR = '0' and SS_FWFT_RD ='0') THEN
DATA_COUNT_FWFT <= DATA_COUNT_FWFT after C_TCQ;
ELSIF (SS_FWFT_WR = '0' and SS_FWFT_RD ='1') THEN
DATA_COUNT_FWFT <= DATA_COUNT_FWFT - 1 after C_TCQ;
ELSIF (SS_FWFT_WR = '1' and SS_FWFT_RD ='0') THEN
DATA_COUNT_FWFT <= DATA_COUNT_FWFT + 1 after C_TCQ;
ELSE
DATA_COUNT_FWFT <= DATA_COUNT_FWFT after C_TCQ;
END IF ;
END IF;
END IF;
END PROCESS count_fwft;
END GENERATE cc_data_cnt;
----------------------------------------------
DOUT <= dout_p0_out;
VALID <= valid_p0_out;
EMPTY <= empty_p0_out;
ALMOST_EMPTY <= almost_empty_p0_out;
UNDERFLOW <= underflow_p0_out;
END GENERATE lat0;
gdc_fwft: IF (C_HAS_DATA_COUNT = 1) GENERATE
begin
ss_count: IF ((NOT ((C_PRELOAD_REGS = 1) AND (C_PRELOAD_LATENCY = 0)) ) OR
(C_USE_FWFT_DATA_COUNT = 0) )GENERATE
begin
DATA_COUNT <= data_count_fifo_out ;
end generate ss_count ;
ss_count_fwft1: IF ((C_PRELOAD_REGS = 1) AND (C_PRELOAD_LATENCY = 0) AND
(C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) AND
(C_USE_FWFT_DATA_COUNT = 1) ) GENERATE
begin
DATA_COUNT <= DATA_COUNT_FWFT(C_RD_PNTR_WIDTH DOWNTO 0) ;
end generate ss_count_fwft1 ;
ss_count_fwft2: IF ((C_PRELOAD_REGS = 1) AND (C_PRELOAD_LATENCY = 0) AND
(C_DATA_COUNT_WIDTH <= C_RD_PNTR_WIDTH) AND
(C_USE_FWFT_DATA_COUNT = 1)) GENERATE
begin
DATA_COUNT <= DATA_COUNT_FWFT(C_RD_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1) ;
end generate ss_count_fwft2 ;
end generate gdc_fwft;
FULL <= FULL_int;
-------------------------------------------------------------------------------
-- If there is a reset input, generate internal reset signals
-- The latency of reset will match the core behavior
-------------------------------------------------------------------------------
--Single RST
grst_sync : IF (C_ENABLE_RST_SYNC = 1 OR C_FIFO_TYPE = 3) GENERATE
grst : IF (C_HAS_RST = 1) GENERATE
gic_rst : IF (C_COMMON_CLOCK = 0 OR C_FIFO_TYPE = 3) GENERATE
SIGNAL rd_rst_asreg : std_logic:= '0';
SIGNAL rd_rst_asreg_d1 : std_logic:= '0';
SIGNAL rd_rst_asreg_d2 : std_logic:= '0';
SIGNAL rd_rst_comb : std_logic:= '0';
SIGNAL rd_rst_reg : std_logic:= '0';
SIGNAL wr_rst_asreg : std_logic:= '0';
SIGNAL wr_rst_asreg_d1 : std_logic:= '0';
SIGNAL wr_rst_asreg_d2 : std_logic:= '0';
SIGNAL wr_rst_comb : std_logic:= '0';
SIGNAL wr_rst_reg : std_logic:= '0';
BEGIN
PROCESS (WR_CLK, rst_delayed)
BEGIN
IF (rst_delayed = '1') THEN
wr_rst_asreg <= '1' after C_TCQ;
ELSIF (WR_CLK'event and WR_CLK = '1') THEN
IF (wr_rst_asreg_d1 = '1') THEN
wr_rst_asreg <= '0' after C_TCQ;
END IF;
END IF;
IF (WR_CLK'event and WR_CLK = '1') THEN
wr_rst_asreg_d1 <= wr_rst_asreg after C_TCQ;
wr_rst_asreg_d2 <= wr_rst_asreg_d1 after C_TCQ;
END IF;
END PROCESS;
PROCESS (wr_rst_asreg, wr_rst_asreg_d2)
BEGIN
wr_rst_comb <= NOT wr_rst_asreg_d2 AND wr_rst_asreg;
END PROCESS;
PROCESS (WR_CLK, wr_rst_comb)
BEGIN
IF (wr_rst_comb = '1') THEN
wr_rst_reg <= '1' after C_TCQ;
ELSIF (WR_CLK'event and WR_CLK = '1') THEN
wr_rst_reg <= '0' after C_TCQ;
END IF;
END PROCESS;
PROCESS (RD_CLK, rst_delayed)
BEGIN
IF (rst_delayed = '1') THEN
rd_rst_asreg <= '1' after C_TCQ;
ELSIF (RD_CLK'event and RD_CLK = '1') THEN
IF (rd_rst_asreg_d1 = '1') THEN
rd_rst_asreg <= '0' after C_TCQ;
END IF;
END IF;
IF (RD_CLK'event and RD_CLK = '1') THEN
rd_rst_asreg_d1 <= rd_rst_asreg after C_TCQ;
rd_rst_asreg_d2 <= rd_rst_asreg_d1 after C_TCQ;
END IF;
END PROCESS;
PROCESS (rd_rst_asreg, rd_rst_asreg_d2)
BEGIN
rd_rst_comb <= NOT rd_rst_asreg_d2 AND rd_rst_asreg;
END PROCESS;
PROCESS (RD_CLK, rd_rst_comb)
BEGIN
IF (rd_rst_comb = '1') THEN
rd_rst_reg <= '1' after C_TCQ;
ELSIF (RD_CLK'event and RD_CLK = '1') THEN
rd_rst_reg <= '0' after C_TCQ;
END IF;
END PROCESS;
wr_rst_i <= wr_rst_reg;
rd_rst_i <= rd_rst_reg;
END GENERATE gic_rst;
gcc_rst : IF (C_COMMON_CLOCK = 1) GENERATE
SIGNAL rst_asreg : std_logic := '0';
SIGNAL rst_asreg_d1 : std_logic := '0';
SIGNAL rst_asreg_d2 : std_logic := '0';
SIGNAL rst_comb : std_logic := '0';
SIGNAL rst_reg : std_logic := '0';
BEGIN
PROCESS (CLK, rst_delayed)
BEGIN
IF (rst_delayed = '1') THEN
rst_asreg <= '1' after C_TCQ;
ELSIF (CLK'event and CLK = '1') THEN
IF (rst_asreg_d1 = '1') THEN
rst_asreg <= '0' after C_TCQ;
ELSE
rst_asreg <= rst_asreg after C_TCQ;
END IF;
END IF;
IF (CLK'event and CLK = '1') THEN
rst_asreg_d1 <= rst_asreg after C_TCQ;
rst_asreg_d2 <= rst_asreg_d1 after C_TCQ;
END IF;
END PROCESS;
PROCESS (rst_asreg, rst_asreg_d2)
BEGIN
rst_comb <= NOT rst_asreg_d2 AND rst_asreg;
END PROCESS;
PROCESS (CLK, rst_comb)
BEGIN
IF (rst_comb = '1') THEN
rst_reg <= '1' after C_TCQ;
ELSIF (CLK'event and CLK = '1') THEN
rst_reg <= '0' after C_TCQ;
END IF;
END PROCESS;
rst_i <= rst_reg;
END GENERATE gcc_rst;
END GENERATE grst;
gnrst : IF (C_HAS_RST = 0) GENERATE
wr_rst_i <= '0';
rd_rst_i <= '0';
rst_i <= '0';
END GENERATE gnrst;
END GENERATE grst_sync;
gnrst_sync : IF (C_ENABLE_RST_SYNC = 0) GENERATE
wr_rst_i <= wr_rst_delayed;
rd_rst_i <= rd_rst_delayed;
rst_i <= '0';
END GENERATE gnrst_sync;
rst_2_sync <= rst_delayed WHEN (C_ENABLE_RST_SYNC = 1) ELSE wr_rst_delayed;
clk_2_sync <= CLK WHEN (C_COMMON_CLOCK = 1) ELSE WR_CLK;
grstd1 : IF (C_HAS_RST = 1 OR C_HAS_SRST = 1 OR C_ENABLE_RST_SYNC = 0) GENERATE
-- RST_FULL_GEN replaces the reset falling edge detection used to de-assert
-- FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.
-- RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &
-- PROG_FULL
grst_full: IF (C_FULL_FLAGS_RST_VAL = 1) GENERATE
SIGNAL rst_d1 : STD_LOGIC := '1';
SIGNAL rst_d2 : STD_LOGIC := '1';
SIGNAL rst_d3 : STD_LOGIC := '1';
BEGIN
grst_f: IF (C_HAS_SRST = 0) GENERATE
prst: PROCESS (rst_2_sync, clk_2_sync)
BEGIN
IF (rst_2_sync = '1') THEN
rst_d1 <= '1';
rst_d2 <= '1';
rst_d3 <= '1';
rst_full_gen_i <= '0';
ELSIF (clk_2_sync'event AND clk_2_sync = '1') THEN
rst_d1 <= '0' AFTER C_TCQ;
rst_d2 <= rst_d1 AFTER C_TCQ;
rst_d3 <= rst_d2 AFTER C_TCQ;
rst_full_gen_i <= rst_d3 AFTER C_TCQ;
END IF;
END PROCESS prst;
rst_full_ff_i <= rst_d2;
END GENERATE grst_f;
ngrst_f: IF (C_HAS_SRST = 1) GENERATE
prst: PROCESS (clk_2_sync)
BEGIN
IF (clk_2_sync'event AND clk_2_sync = '1') THEN
IF (srst_delayed = '1') THEN
rst_d1 <= '1' AFTER C_TCQ;
rst_d2 <= '1' AFTER C_TCQ;
rst_d3 <= '1' AFTER C_TCQ;
rst_full_gen_i <= '0' AFTER C_TCQ;
ELSE
rst_d1 <= '0' AFTER C_TCQ;
rst_d2 <= rst_d1 AFTER C_TCQ;
rst_d3 <= rst_d2 AFTER C_TCQ;
rst_full_gen_i <= rst_d3 AFTER C_TCQ;
END IF;
END IF;
END PROCESS prst;
rst_full_ff_i <= '0';
END GENERATE ngrst_f;
END GENERATE grst_full;
gnrst_full: IF (C_FULL_FLAGS_RST_VAL = 0) GENERATE
rst_full_gen_i <= '0';
rst_full_ff_i <= wr_rst_i WHEN (C_COMMON_CLOCK = 0) ELSE rst_i;
END GENERATE gnrst_full;
END GENERATE grstd1;
END behavioral;
-------------------------------------------------------------------------------
--
-- Register Slice
-- Register one AXI channel on forward and/or reverse signal path
--
----------------------------------------------------------------------------
--
-- Structure:
-- reg_slice
--
----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY fifo_generator_v8_2_axic_reg_slice IS
GENERIC (
C_FAMILY : string := "";
C_DATA_WIDTH : integer := 32;
C_REG_CONFIG : integer := 0
);
PORT (
-- System Signals
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
-- Slave side
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC := '0';
-- Master side
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_VALID : OUT STD_LOGIC := '0';
M_READY : IN STD_LOGIC
);
END fifo_generator_v8_2_axic_reg_slice;
ARCHITECTURE xilinx OF fifo_generator_v8_2_axic_reg_slice IS
SIGNAL storage_data1 : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_ready_i : STD_LOGIC := '0'; -- local signal of output
SIGNAL m_valid_i : STD_LOGIC := '0'; -- local signal of output
SIGNAL areset_d1 : STD_LOGIC := '0'; -- Reset delay register
-- Constant to have clock to register delay
CONSTANT TFF : time := 100 ps;
BEGIN
--------------------------------------------------------------------
--
-- Both FWD and REV mode
--
--------------------------------------------------------------------
gfwd_rev: IF (C_REG_CONFIG = 0) GENERATE
CONSTANT ZERO : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10";
CONSTANT ONE : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11";
CONSTANT TWO : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01";
SIGNAL state : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL storage_data2 : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL load_s1 : STD_LOGIC;
SIGNAL load_s2 : STD_LOGIC;
SIGNAL load_s1_from_s2 : BOOLEAN;
BEGIN
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
-- Reset delay register
PROCESS(ACLK)
BEGIN
IF (ACLK'event AND ACLK = '1') THEN
areset_d1 <= ARESET AFTER TFF;
END IF;
END PROCESS;
-- Load storage1 with either slave side data or from storage2
PROCESS(ACLK)
BEGIN
IF (ACLK'event AND ACLK = '1') THEN
IF (load_s1 = '1') THEN
IF (load_s1_from_s2) THEN
storage_data1 <= storage_data2 AFTER TFF;
ELSE
storage_data1 <= S_PAYLOAD_DATA AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
-- Load storage2 with slave side data
PROCESS(ACLK)
BEGIN
IF (ACLK'event AND ACLK = '1') THEN
IF (load_s2 = '1') THEN
storage_data2 <= S_PAYLOAD_DATA AFTER TFF;
END IF;
END IF;
END PROCESS;
M_PAYLOAD_DATA <= storage_data1;
-- Always load s2 on a valid transaction even if it's unnecessary
load_s2 <= S_VALID AND s_ready_i;
-- Loading s1
PROCESS(state,S_VALID,M_READY)
BEGIN
IF ((state = ZERO AND S_VALID = '1') OR -- Load when empty on slave transaction
-- Load when ONE if we both have read and write at the same time
(state = ONE AND S_VALID = '1' AND M_READY = '1') OR
-- Load when TWO and we have a transaction on Master side
(state = TWO AND M_READY = '1')) THEN
load_s1 <= '1';
ELSE
load_s1 <= '0';
END IF;
END PROCESS;
load_s1_from_s2 <= (state = TWO);
-- State Machine for handling output signals
PROCESS(ACLK)
BEGIN
IF (ACLK'event AND ACLK = '1') THEN
IF (ARESET = '1') THEN
s_ready_i <= '0' AFTER TFF;
state <= ZERO AFTER TFF;
ELSIF (areset_d1 = '1') THEN
s_ready_i <= '1' AFTER TFF;
ELSE
CASE (state) IS
WHEN ZERO => -- No transaction stored locally
IF (S_VALID = '1') THEN -- Got one so move to ONE
state <= ONE AFTER TFF;
END IF;
WHEN ONE => -- One transaction stored locally
IF (M_READY = '1' AND S_VALID = '0') THEN -- Read out one so move to ZERO
state <= ZERO AFTER TFF;
END IF;
IF (M_READY = '0' AND S_VALID = '1') THEN -- Got another one so move to TWO
state <= TWO AFTER TFF;
s_ready_i <= '0' AFTER TFF;
END IF;
WHEN TWO => -- TWO transaction stored locally
IF (M_READY = '1') THEN -- Read out one so move to ONE
state <= ONE AFTER TFF;
s_ready_i <= '1' AFTER TFF;
END IF;
WHEN OTHERS =>
state <= state AFTER TFF;
END CASE;
END IF;
END IF;
END PROCESS;
-- s_ready_i <= state(1);
m_valid_i <= state(0);
END GENERATE gfwd_rev;
--------------------------------------------------------------------
--
-- C_REG_CONFIG = 1
-- Light-weight mode.
-- 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
-- Operates same as 1-deep FIFO
--
--------------------------------------------------------------------
gfwd_rev_pipeline1: IF (C_REG_CONFIG = 1) GENERATE
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
-- Reset delay register
PROCESS(ACLK)
BEGIN
IF (ACLK'event AND ACLK = '1') THEN
areset_d1 <= ARESET AFTER TFF;
END IF;
END PROCESS;
-- Load storage1 with slave side data
PROCESS(ACLK)
BEGIN
IF (ACLK'event AND ACLK = '1') THEN
IF (ARESET = '1') THEN
s_ready_i <= '0' AFTER TFF;
m_valid_i <= '0' AFTER TFF;
ELSIF (areset_d1 = '1') THEN
s_ready_i <= '1' AFTER TFF;
ELSIF (m_valid_i = '1' AND M_READY = '1') THEN
s_ready_i <= '1' AFTER TFF;
m_valid_i <= '0' AFTER TFF;
ELSIF (S_VALID = '1' AND s_ready_i = '1') THEN
s_ready_i <= '0' AFTER TFF;
m_valid_i <= '1' AFTER TFF;
END IF;
IF (m_valid_i = '0') THEN
storage_data1 <= S_PAYLOAD_DATA AFTER TFF;
END IF;
END IF;
END PROCESS;
M_PAYLOAD_DATA <= storage_data1;
END GENERATE gfwd_rev_pipeline1;
end xilinx;-- reg_slice
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Top-level Behavioral Model for AXI
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY XilinxCoreLib;
USE XilinxCoreLib.fifo_generator_v8_2_conv;
-------------------------------------------------------------------------------
-- Top-level Entity Declaration - This is the top-level of the AXI FIFO Bhv Model
-------------------------------------------------------------------------------
ENTITY fifo_generator_v8_2 IS
GENERIC (
-------------------------------------------------------------------------
-- Generic Declarations
-------------------------------------------------------------------------
C_COMMON_CLOCK : integer := 0;
C_COUNT_TYPE : integer := 0;
C_DATA_COUNT_WIDTH : integer := 2;
C_DEFAULT_VALUE : string := "";
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_ENABLE_RLOCS : integer := 0;
C_FAMILY : string := "";
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_BACKUP : integer := 0;
C_HAS_DATA_COUNT : integer := 0;
C_HAS_INT_CLK : integer := 0;
C_HAS_MEMINIT_FILE : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 0;
C_HAS_RD_RST : integer := 0;
C_HAS_RST : integer := 1;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 0;
C_HAS_WR_RST : integer := 0;
C_IMPLEMENTATION_TYPE : integer := 0;
C_INIT_WR_PNTR_VAL : integer := 0;
C_MEMORY_TYPE : integer := 1;
C_MIF_FILE_NAME : string := "";
C_OPTIMIZATION_MODE : integer := 0;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PRIM_FIFO_TYPE : string := "4kx4";
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 2;
C_RD_DEPTH : integer := 256;
C_RD_FREQ : integer := 1;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FIFO16_FLAGS : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 2;
C_WR_DEPTH : integer := 256;
C_WR_FREQ : integer := 1;
C_WR_PNTR_WIDTH : integer := 8;
C_WR_RESPONSE_LATENCY : integer := 1;
C_MSGON_VAL : integer := 1;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL : integer := 0;
C_HAS_AXI_RD_CHANNEL : integer := 0;
C_HAS_SLAVE_CE : integer := 0;
C_HAS_MASTER_CE : integer := 0;
C_ADD_NGC_CONSTRAINT : integer := 0;
C_USE_COMMON_OVERFLOW : integer := 0;
C_USE_COMMON_UNDERFLOW : integer := 0;
C_USE_DEFAULT_SETTINGS : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH : integer := 0;
C_AXI_ADDR_WIDTH : integer := 0;
C_AXI_DATA_WIDTH : integer := 0;
C_HAS_AXI_AWUSER : integer := 0;
C_HAS_AXI_WUSER : integer := 0;
C_HAS_AXI_BUSER : integer := 0;
C_HAS_AXI_ARUSER : integer := 0;
C_HAS_AXI_RUSER : integer := 0;
C_AXI_ARUSER_WIDTH : integer := 0;
C_AXI_AWUSER_WIDTH : integer := 0;
C_AXI_WUSER_WIDTH : integer := 0;
C_AXI_BUSER_WIDTH : integer := 0;
C_AXI_RUSER_WIDTH : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA : integer := 0;
C_HAS_AXIS_TID : integer := 0;
C_HAS_AXIS_TDEST : integer := 0;
C_HAS_AXIS_TUSER : integer := 0;
C_HAS_AXIS_TREADY : integer := 0;
C_HAS_AXIS_TLAST : integer := 0;
C_HAS_AXIS_TSTRB : integer := 0;
C_HAS_AXIS_TKEEP : integer := 0;
C_AXIS_TDATA_WIDTH : integer := 1;
C_AXIS_TID_WIDTH : integer := 1;
C_AXIS_TDEST_WIDTH : integer := 1;
C_AXIS_TUSER_WIDTH : integer := 1;
C_AXIS_TSTRB_WIDTH : integer := 1;
C_AXIS_TKEEP_WIDTH : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH : integer := 0;
C_IMPLEMENTATION_TYPE_RACH : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Sync FIFO
-- 3 = Low Latency Async FIFO
C_APPLICATION_TYPE_WACH : integer := 0;
C_APPLICATION_TYPE_WDCH : integer := 0;
C_APPLICATION_TYPE_WRCH : integer := 0;
C_APPLICATION_TYPE_RACH : integer := 0;
C_APPLICATION_TYPE_RDCH : integer := 0;
C_APPLICATION_TYPE_AXIS : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH : integer := 0;
C_USE_ECC_WDCH : integer := 0;
C_USE_ECC_WRCH : integer := 0;
C_USE_ECC_RACH : integer := 0;
C_USE_ECC_RDCH : integer := 0;
C_USE_ECC_AXIS : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH : integer := 0;
C_ERROR_INJECTION_TYPE_RACH : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH : integer := 1;
C_DIN_WIDTH_WDCH : integer := 1;
C_DIN_WIDTH_WRCH : integer := 1;
C_DIN_WIDTH_RACH : integer := 1;
C_DIN_WIDTH_RDCH : integer := 1;
C_DIN_WIDTH_AXIS : integer := 1;
C_WR_DEPTH_WACH : integer := 16;
C_WR_DEPTH_WDCH : integer := 16;
C_WR_DEPTH_WRCH : integer := 16;
C_WR_DEPTH_RACH : integer := 16;
C_WR_DEPTH_RDCH : integer := 16;
C_WR_DEPTH_AXIS : integer := 16;
C_WR_PNTR_WIDTH_WACH : integer := 4;
C_WR_PNTR_WIDTH_WDCH : integer := 4;
C_WR_PNTR_WIDTH_WRCH : integer := 4;
C_WR_PNTR_WIDTH_RACH : integer := 4;
C_WR_PNTR_WIDTH_RDCH : integer := 4;
C_WR_PNTR_WIDTH_AXIS : integer := 4;
C_HAS_DATA_COUNTS_WACH : integer := 0;
C_HAS_DATA_COUNTS_WDCH : integer := 0;
C_HAS_DATA_COUNTS_WRCH : integer := 0;
C_HAS_DATA_COUNTS_RACH : integer := 0;
C_HAS_DATA_COUNTS_RDCH : integer := 0;
C_HAS_DATA_COUNTS_AXIS : integer := 0;
C_HAS_PROG_FLAGS_WACH : integer := 0;
C_HAS_PROG_FLAGS_WDCH : integer := 0;
C_HAS_PROG_FLAGS_WRCH : integer := 0;
C_HAS_PROG_FLAGS_RACH : integer := 0;
C_HAS_PROG_FLAGS_RDCH : integer := 0;
C_HAS_PROG_FLAGS_AXIS : integer := 0;
C_PROG_FULL_TYPE_WACH : integer := 0;
C_PROG_FULL_TYPE_WDCH : integer := 0;
C_PROG_FULL_TYPE_WRCH : integer := 0;
C_PROG_FULL_TYPE_RACH : integer := 0;
C_PROG_FULL_TYPE_RDCH : integer := 0;
C_PROG_FULL_TYPE_AXIS : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer := 0;
C_PROG_EMPTY_TYPE_WACH : integer := 0;
C_PROG_EMPTY_TYPE_WDCH : integer := 0;
C_PROG_EMPTY_TYPE_WRCH : integer := 0;
C_PROG_EMPTY_TYPE_RACH : integer := 0;
C_PROG_EMPTY_TYPE_RDCH : integer := 0;
C_PROG_EMPTY_TYPE_AXIS : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer := 0;
C_REG_SLICE_MODE_WACH : integer := 0;
C_REG_SLICE_MODE_WDCH : integer := 0;
C_REG_SLICE_MODE_WRCH : integer := 0;
C_REG_SLICE_MODE_RACH : integer := 0;
C_REG_SLICE_MODE_RDCH : integer := 0;
C_REG_SLICE_MODE_AXIS : integer := 0
);
PORT(
------------------------------------------------------------------------------
-- Input and Output Declarations
------------------------------------------------------------------------------
-- Conventional FIFO Interface Signals
BACKUP : IN std_logic := '0';
BACKUP_MARKER : IN std_logic := '0';
CLK : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_CLK : IN std_logic := '0';
WR_RST : IN std_logic := '0';
RD_CLK : IN std_logic := '0';
RD_RST : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
WR_EN : IN std_logic := '0';
RD_EN : IN std_logic := '0';
-- Optional inputs
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
INT_CLK : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
FULL : OUT std_logic;
ALMOST_FULL : OUT std_logic;
WR_ACK : OUT std_logic;
OVERFLOW : OUT std_logic;
EMPTY : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
VALID : OUT std_logic;
UNDERFLOW : OUT std_logic;
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
SBITERR : OUT std_logic;
DBITERR : OUT std_logic;
-- AXI Global Signal
M_ACLK : IN std_logic := '0';
S_ACLK : IN std_logic := '0';
S_ARESETN : IN std_logic := '0';
M_ACLK_EN : IN std_logic := '0';
S_ACLK_EN : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWUSER : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WDATA : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WSTRB : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WLAST : IN std_logic := '0';
S_AXI_WUSER : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic := '0';
M_AXI_WID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic := '0';
M_AXI_BID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BUSER : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BVALID : IN std_logic := '0';
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARUSER : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic := '0';
M_AXI_RID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RDATA : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RLAST : IN std_logic := '0';
M_AXI_RUSER : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RVALID : IN std_logic := '0';
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic := '0';
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TSTRB : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TKEEP : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TLAST : IN std_logic := '0';
S_AXIS_TID : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TDEST : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TUSER : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic := '0';
M_AXIS_TDATA : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic := '0';
AXI_AW_INJECTDBITERR : IN std_logic := '0';
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic := '0';
AXI_W_INJECTDBITERR : IN std_logic := '0';
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic := '0';
AXI_B_INJECTDBITERR : IN std_logic := '0';
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic := '0';
AXI_AR_INJECTDBITERR : IN std_logic := '0';
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic := '0';
AXI_R_INJECTDBITERR : IN std_logic := '0';
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic := '0';
AXIS_INJECTDBITERR : IN std_logic := '0';
AXIS_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic
);
END fifo_generator_v8_2;
ARCHITECTURE behavioral OF fifo_generator_v8_2 IS
COMPONENT fifo_generator_v8_2_conv IS
GENERIC (
---------------------------------------------------------------------------
-- Generic Declarations
---------------------------------------------------------------------------
C_COMMON_CLOCK : integer := 0;
C_COUNT_TYPE : integer := 0; --not used
C_DATA_COUNT_WIDTH : integer := 2;
C_DEFAULT_VALUE : string := ""; --not used
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_ENABLE_RLOCS : integer := 0; --not used
C_FAMILY : string := ""; --not used in bhv model
C_FULL_FLAGS_RST_VAL : integer := 0;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_BACKUP : integer := 0; --not used
C_HAS_DATA_COUNT : integer := 0;
C_HAS_INT_CLK : integer := 0; --not used in bhv model
C_HAS_MEMINIT_FILE : integer := 0; --not used
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 0;
C_HAS_RD_RST : integer := 0; --not used
C_HAS_RST : integer := 1;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 0;
C_HAS_WR_RST : integer := 0; --not used
C_IMPLEMENTATION_TYPE : integer := 0;
C_INIT_WR_PNTR_VAL : integer := 0; --not used
C_MEMORY_TYPE : integer := 1;
C_MIF_FILE_NAME : string := ""; --not used
C_OPTIMIZATION_MODE : integer := 0; --not used
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PRIM_FIFO_TYPE : string := "4kx4"; --not used in bhv model
C_PROG_EMPTY_THRESH_ASSERT_VAL: integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL: integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 2;
C_RD_DEPTH : integer := 256;
C_RD_FREQ : integer := 1; --not used in bhv model
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FIFO16_FLAGS : integer := 0; --not used in bhv model
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 2;
C_WR_DEPTH : integer := 256;
C_WR_FREQ : integer := 1; --not used in bhv model
C_WR_PNTR_WIDTH : integer := 8;
C_WR_RESPONSE_LATENCY : integer := 1; --not used
C_MSGON_VAL : integer := 1; --not used in bhv model
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
BACKUP : IN std_logic := '0';
BACKUP_MARKER : IN std_logic := '0';
CLK : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_CLK : IN std_logic := '0';
WR_RST : IN std_logic := '0';
RD_CLK : IN std_logic := '0';
RD_RST : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0); --
WR_EN : IN std_logic; --Mandatory input
RD_EN : IN std_logic; --Mandatory input
--Mandatory input
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
INT_CLK : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
FULL : OUT std_logic;
ALMOST_FULL : OUT std_logic;
WR_ACK : OUT std_logic;
OVERFLOW : OUT std_logic;
EMPTY : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
VALID : OUT std_logic;
UNDERFLOW : OUT std_logic;
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
SBITERR : OUT std_logic := '0';
DBITERR : OUT std_logic := '0'
);
END COMPONENT;
COMPONENT fifo_generator_v8_2_axic_reg_slice IS
GENERIC (
C_FAMILY : string := "";
C_DATA_WIDTH : integer := 32;
C_REG_CONFIG : integer := 0
);
PORT (
-- System Signals
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
-- Slave side
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC := '0';
-- Master side
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_VALID : OUT STD_LOGIC := '0';
M_READY : IN STD_LOGIC
);
END COMPONENT;
CONSTANT C_AXI_LEN_WIDTH : integer := 8;
CONSTANT C_AXI_SIZE_WIDTH : integer := 3;
CONSTANT C_AXI_BURST_WIDTH : integer := 2;
CONSTANT C_AXI_LOCK_WIDTH : integer := 2;
CONSTANT C_AXI_CACHE_WIDTH : integer := 4;
CONSTANT C_AXI_PROT_WIDTH : integer := 3;
CONSTANT C_AXI_QOS_WIDTH : integer := 4;
CONSTANT C_AXI_REGION_WIDTH : integer := 4;
CONSTANT C_AXI_BRESP_WIDTH : integer := 2;
CONSTANT C_AXI_RRESP_WIDTH : integer := 2;
-----------------------------------------------------------------------------
-- FUNCTION if_then_else
-- Returns a true case or flase case based on the condition
-------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : integer;
false_case : integer)
RETURN integer IS
VARIABLE retval : integer := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
------------------------------------------------------------------------------
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed and returns string.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : string;
false_case : string)
RETURN string IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
--------------------------------------------------------
-- FUNCION : map_ready_valid
-- Returns the READY signal that is mapped out of FULL or ALMOST_FULL or PROG_FULL
-- Returns the VALID signal that is mapped out of EMPTY or ALMOST_EMPTY or PROG_EMPTY
--------------------------------------------------------
FUNCTION map_ready_valid(
pf_pe_type : integer;
full_empty : std_logic;
af_ae : std_logic;
pf_pe : std_logic)
RETURN std_logic IS
BEGIN
IF (pf_pe_type = 5) THEN
RETURN NOT full_empty;
ELSIF (pf_pe_type = 6) THEN
RETURN NOT af_ae;
ELSE
RETURN NOT pf_pe;
END IF;
END map_ready_valid;
SIGNAL inverted_reset : std_logic := '0';
BEGIN
inverted_reset <= NOT S_ARESETN;
---------------------------------------------------------------------------
-- Top level instance for Conventional FIFO.
---------------------------------------------------------------------------
gconvfifo: IF (C_INTERFACE_TYPE = 0) GENERATE
inst_conv_fifo: fifo_generator_v8_2_conv
GENERIC map(
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_DIN_WIDTH => C_DIN_WIDTH,
C_DOUT_RST_VAL => if_then_else(C_USE_DOUT_RST = 1, C_DOUT_RST_VAL, "0"),
C_DOUT_WIDTH => C_DOUT_WIDTH,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_FAMILY => C_FAMILY,
C_FULL_FLAGS_RST_VAL => C_FULL_FLAGS_RST_VAL,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_DATA_COUNT => C_HAS_DATA_COUNT,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_HAS_RD_DATA_COUNT => C_HAS_RD_DATA_COUNT,
C_HAS_RD_RST => C_HAS_RD_RST,
C_HAS_RST => C_HAS_RST,
C_HAS_SRST => C_HAS_SRST,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_HAS_VALID => C_HAS_VALID,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_DATA_COUNT,
C_HAS_WR_RST => C_HAS_WR_RST,
C_IMPLEMENTATION_TYPE => C_IMPLEMENTATION_TYPE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MEMORY_TYPE => C_MEMORY_TYPE,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY,
C_PRELOAD_REGS => C_PRELOAD_REGS,
C_PRIM_FIFO_TYPE => C_PRIM_FIFO_TYPE,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL,
C_PROG_EMPTY_THRESH_NEGATE_VAL => C_PROG_EMPTY_THRESH_NEGATE_VAL,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => C_PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE,
C_RD_DATA_COUNT_WIDTH => C_RD_DATA_COUNT_WIDTH,
C_RD_DEPTH => C_RD_DEPTH,
C_RD_FREQ => C_RD_FREQ,
C_RD_PNTR_WIDTH => C_RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_USE_DOUT_RST => C_USE_DOUT_RST,
C_USE_ECC => C_USE_ECC,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_USE_FWFT_DATA_COUNT => C_USE_FWFT_DATA_COUNT,
C_VALID_LOW => C_VALID_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => C_WR_DATA_COUNT_WIDTH,
C_WR_DEPTH => C_WR_DEPTH,
C_WR_FREQ => C_WR_FREQ,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE,
-- Enable Distributed RAM Low latency FIFO for FWFT Built-in FIFO, otherwise use Distributed RAM
C_FIFO_TYPE => if_then_else((C_PRELOAD_LATENCY /= 0 AND C_MEMORY_TYPE = 4), 1,if_then_else((C_IMPLEMENTATION_TYPE > 2), 2, 0))
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
CLK => CLK,
RST => RST,
SRST => SRST,
WR_CLK => WR_CLK,
WR_RST => WR_RST,
RD_CLK => RD_CLK,
RD_RST => RD_RST,
DIN => DIN,
WR_EN => WR_EN,
RD_EN => RD_EN,
PROG_EMPTY_THRESH => PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => PROG_EMPTY_THRESH_ASSERT,
PROG_EMPTY_THRESH_NEGATE => PROG_EMPTY_THRESH_NEGATE,
PROG_FULL_THRESH => PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => PROG_FULL_THRESH_ASSERT,
PROG_FULL_THRESH_NEGATE => PROG_FULL_THRESH_NEGATE,
INT_CLK => INT_CLK,
INJECTDBITERR => INJECTDBITERR,
INJECTSBITERR => INJECTSBITERR,
--Outputs
DOUT => DOUT,
FULL => FULL,
ALMOST_FULL => ALMOST_FULL,
WR_ACK => WR_ACK,
OVERFLOW => OVERFLOW,
EMPTY => EMPTY,
ALMOST_EMPTY => ALMOST_EMPTY,
VALID => VALID,
UNDERFLOW => UNDERFLOW,
DATA_COUNT => DATA_COUNT,
RD_DATA_COUNT => RD_DATA_COUNT,
WR_DATA_COUNT => WR_DATA_COUNT,
PROG_FULL => PROG_FULL,
PROG_EMPTY => PROG_EMPTY,
SBITERR => SBITERR,
DBITERR => DBITERR
);
END GENERATE gconvfifo; -- End of conventional FIFO
---------------------------------------------------------------------------
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Top level instance for ramfifo in AXI Streaming FIFO core. It implements:
-- * BRAM based FIFO
-- * Dist RAM based FIFO
---------------------------------------------------------------------------
---------------------------------------------------------------------------
---------------------------------------------------------------------------
gaxis_fifo: IF ((C_INTERFACE_TYPE = 1) AND (C_AXI_TYPE = 0) AND (C_AXIS_TYPE < 2)) GENERATE
SIGNAL axis_din : std_logic_vector(C_DIN_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL axis_dout : std_logic_vector(C_DIN_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL axis_full : std_logic := '0';
SIGNAL axis_almost_full : std_logic := '0';
SIGNAL axis_prog_full : std_logic := '0';
SIGNAL axis_empty : std_logic := '0';
SIGNAL axis_almost_empty : std_logic := '0';
SIGNAL axis_prog_empty : std_logic := '0';
SIGNAL axis_s_axis_tready : std_logic := '0';
SIGNAL axis_m_axis_tvalid : std_logic := '0';
SIGNAL axis_wr_en : std_logic := '0';
SIGNAL axis_rd_en : std_logic := '0';
CONSTANT TDATA_OFFSET : integer := if_then_else(C_HAS_AXIS_TDATA = 1,C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH,C_DIN_WIDTH_AXIS);
CONSTANT TSTRB_OFFSET : integer := if_then_else(C_HAS_AXIS_TSTRB = 1,TDATA_OFFSET-C_AXIS_TSTRB_WIDTH,TDATA_OFFSET);
CONSTANT TKEEP_OFFSET : integer := if_then_else(C_HAS_AXIS_TKEEP = 1,TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH,TSTRB_OFFSET);
CONSTANT TID_OFFSET : integer := if_then_else(C_HAS_AXIS_TID = 1,TKEEP_OFFSET-C_AXIS_TID_WIDTH,TKEEP_OFFSET);
CONSTANT TDEST_OFFSET : integer := if_then_else(C_HAS_AXIS_TDEST = 1,TID_OFFSET-C_AXIS_TDEST_WIDTH,TID_OFFSET);
CONSTANT TUSER_OFFSET : integer := if_then_else(C_HAS_AXIS_TUSER = 1,TDEST_OFFSET-C_AXIS_TUSER_WIDTH,TDEST_OFFSET);
BEGIN
-- Generate the DIN to FIFO by concatinating the AXIS optional ports
gdin1: IF (C_HAS_AXIS_TDATA = 1) GENERATE
axis_din(C_DIN_WIDTH_AXIS-1 DOWNTO TDATA_OFFSET) <= S_AXIS_TDATA;
M_AXIS_TDATA <= axis_dout(C_DIN_WIDTH_AXIS-1 DOWNTO TDATA_OFFSET);
END GENERATE gdin1;
gdin2: IF (C_HAS_AXIS_TSTRB = 1) GENERATE
axis_din(TDATA_OFFSET-1 DOWNTO TSTRB_OFFSET) <= S_AXIS_TSTRB;
M_AXIS_TSTRB <= axis_dout(TDATA_OFFSET-1 DOWNTO TSTRB_OFFSET);
END GENERATE gdin2;
gdin3: IF (C_HAS_AXIS_TKEEP = 1) GENERATE
axis_din(TSTRB_OFFSET-1 DOWNTO TKEEP_OFFSET) <= S_AXIS_TKEEP;
M_AXIS_TKEEP <= axis_dout(TSTRB_OFFSET-1 DOWNTO TKEEP_OFFSET);
END GENERATE gdin3;
gdin4: IF (C_HAS_AXIS_TID = 1) GENERATE
axis_din(TKEEP_OFFSET-1 DOWNTO TID_OFFSET) <= S_AXIS_TID;
M_AXIS_TID <= axis_dout(TKEEP_OFFSET-1 DOWNTO TID_OFFSET);
END GENERATE gdin4;
gdin5: IF (C_HAS_AXIS_TDEST = 1) GENERATE
axis_din(TID_OFFSET-1 DOWNTO TDEST_OFFSET) <= S_AXIS_TDEST;
M_AXIS_TDEST <= axis_dout(TID_OFFSET-1 DOWNTO TDEST_OFFSET);
END GENERATE gdin5;
gdin6: IF (C_HAS_AXIS_TUSER = 1) GENERATE
axis_din(TDEST_OFFSET-1 DOWNTO TUSER_OFFSET) <= S_AXIS_TUSER;
M_AXIS_TUSER <= axis_dout(TDEST_OFFSET-1 DOWNTO TUSER_OFFSET);
END GENERATE gdin6;
gdin7: IF (C_HAS_AXIS_TLAST = 1) GENERATE
axis_din(0) <= S_AXIS_TLAST;
M_AXIS_TLAST <= axis_dout(0);
END GENERATE gdin7;
-- Write protection
-- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt
gaxis_wr_en1: IF (C_PROG_FULL_TYPE_AXIS = 5) GENERATE
axis_wr_en <= S_AXIS_TVALID;
END GENERATE gaxis_wr_en1;
-- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL
gaxis_wr_en2: IF (C_PROG_FULL_TYPE_AXIS /= 5) GENERATE
axis_wr_en <= axis_s_axis_tready AND S_AXIS_TVALID;
END GENERATE gaxis_wr_en2;
-- Read protection
-- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt
gaxis_rd_en1: IF (C_PROG_EMPTY_TYPE_AXIS = 5) GENERATE
axis_rd_en <= M_AXIS_TREADY;
END GENERATE gaxis_rd_en1;
-- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY
gaxis_rd_en2: IF (C_PROG_EMPTY_TYPE_AXIS /= 5) GENERATE
axis_rd_en <= axis_m_axis_tvalid AND M_AXIS_TREADY;
END GENERATE gaxis_rd_en2;
gaxisf: IF (C_AXIS_TYPE = 0) GENERATE
axisf : fifo_generator_v8_2_conv
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_AXIS = 1 OR C_IMPLEMENTATION_TYPE_AXIS = 11),1,2),
C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_AXIS <= 6),0,2), -- CCBI
C_PRELOAD_REGS => 1, -- Always FWFT for AXI
C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI
C_DIN_WIDTH => C_DIN_WIDTH_AXIS,
C_WR_DEPTH => C_WR_DEPTH_AXIS,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_AXIS,
C_DOUT_WIDTH => C_DIN_WIDTH_AXIS,
C_RD_DEPTH => C_WR_DEPTH_AXIS,
C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_AXIS,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_AXIS,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_AXIS,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_AXIS,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS,
C_USE_ECC => C_USE_ECC_AXIS,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_AXIS,
C_HAS_ALMOST_EMPTY => if_then_else((C_PROG_EMPTY_TYPE_AXIS = 6), 1, 0),
C_HAS_ALMOST_FULL => if_then_else((C_PROG_FULL_TYPE_AXIS = 6), 1, 0),
-- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO
C_FIFO_TYPE => C_APPLICATION_TYPE_AXIS,
-- Place holder parameters for the new features
-- C_USE_SYNC_CLK => 0,
-- C_BYTE_STRB_WIDTH => 8,
-- C_USE_INPUT_CE => C_HAS_SLAVE_CE,
-- C_USE_OUTPUT_CE => C_HAS_MASTER_CE,
C_HAS_WR_RST => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_DOUT_RST_VAL => "0",
C_HAS_VALID => 0,
C_VALID_LOW => C_VALID_LOW,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_HAS_WR_ACK => 0,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_AXIS = 1), 1, 0),
C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_AXIS+1,
C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_AXIS = 1), 1, 0),
C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_AXIS+1,
C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true
C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_AXIS = 1), 1, 0),
C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_AXIS+1,
C_FULL_FLAGS_RST_VAL => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_DOUT_RST => 0,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => 1,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_RD_FREQ => C_RD_FREQ,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_WR_FREQ => C_WR_FREQ,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
INT_CLK => INT_CLK,
CLK => S_ACLK,
WR_CLK => S_ACLK,
RD_CLK => M_ACLK,
RST => inverted_reset,
SRST => '0',
WR_RST => inverted_reset,
RD_RST => inverted_reset,
WR_EN => axis_wr_en,--S_AXIS_TVALID,
RD_EN => axis_rd_en,--M_AXIS_TREADY,
PROG_FULL_THRESH => AXIS_PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => (OTHERS => '0'),
PROG_FULL_THRESH_NEGATE => (OTHERS => '0'),
PROG_EMPTY_THRESH => AXIS_PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'),
PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'),
INJECTDBITERR => AXIS_INJECTDBITERR,
INJECTSBITERR => AXIS_INJECTSBITERR,
-- Place holder parameters for the new features
-- INPUT_CE => S_ACLK_EN,
-- OUTPUT_CE => M_ACLK_EN,
-- END_OF_PACKET => '0',
-- BYTE_STROBE => (OTHERS => '0'),
DIN => axis_din,
DOUT => axis_dout,
FULL => axis_full,
ALMOST_FULL => axis_almost_full,
PROG_FULL => axis_prog_full,
EMPTY => axis_empty,
ALMOST_EMPTY => axis_almost_empty,
PROG_EMPTY => axis_prog_empty,
WR_ACK => OPEN,
OVERFLOW => AXIS_OVERFLOW,
VALID => OPEN,
UNDERFLOW => AXIS_UNDERFLOW,
DATA_COUNT => AXIS_DATA_COUNT,
RD_DATA_COUNT => AXIS_RD_DATA_COUNT,
WR_DATA_COUNT => AXIS_WR_DATA_COUNT,
SBITERR => AXIS_SBITERR,
DBITERR => AXIS_DBITERR
);
axis_s_axis_tready <= map_ready_valid(C_PROG_FULL_TYPE_AXIS,axis_full,axis_almost_full,axis_prog_full);
axis_m_axis_tvalid <= map_ready_valid(C_PROG_EMPTY_TYPE_AXIS,axis_empty,axis_almost_empty,axis_prog_empty);
S_AXIS_TREADY <= axis_s_axis_tready;--map_ready_valid(C_PROG_FULL_TYPE_AXIS,axis_full,axis_almost_full,axis_prog_full);
M_AXIS_TVALID <= axis_m_axis_tvalid;--map_ready_valid(C_PROG_EMPTY_TYPE_AXIS,axis_empty,axis_almost_empty,axis_prog_empty);
END GENERATE gaxisf;
-- Register Slice for AXI Streaming
gaxis_reg_slice: IF (C_AXIS_TYPE = 1) GENERATE
axis_reg_slice: fifo_generator_v8_2_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_AXIS,
C_REG_CONFIG => C_REG_SLICE_MODE_AXIS
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => inverted_reset,
-- Slave side
S_PAYLOAD_DATA => axis_din,
S_VALID => S_AXIS_TVALID,
S_READY => S_AXIS_TREADY,
-- Master side
M_PAYLOAD_DATA => axis_dout,
M_VALID => M_AXIS_TVALID,
M_READY => M_AXIS_TREADY
);
END GENERATE gaxis_reg_slice;
END GENERATE gaxis_fifo;
gaxifull: IF (C_INTERFACE_TYPE = 1) AND (C_AXI_TYPE /= 0) GENERATE
SIGNAL axi_rd_underflow_i : std_logic := '0';
SIGNAL axi_rd_overflow_i : std_logic := '0';
SIGNAL axi_wr_underflow_i : std_logic := '0';
SIGNAL axi_wr_overflow_i : std_logic := '0';
BEGIN
gwrch: IF (C_HAS_AXI_WR_CHANNEL = 1) GENERATE
SIGNAL wach_din : std_logic_vector(C_DIN_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wach_dout : std_logic_vector(C_DIN_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wach_full : std_logic := '0';
SIGNAL wach_almost_full : std_logic := '0';
SIGNAL wach_prog_full : std_logic := '0';
SIGNAL wach_empty : std_logic := '0';
SIGNAL wach_almost_empty : std_logic := '0';
SIGNAL wach_prog_empty : std_logic := '0';
SIGNAL wdch_din : std_logic_vector(C_DIN_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wdch_dout : std_logic_vector(C_DIN_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wdch_full : std_logic := '0';
SIGNAL wdch_almost_full : std_logic := '0';
SIGNAL wdch_prog_full : std_logic := '0';
SIGNAL wdch_empty : std_logic := '0';
SIGNAL wdch_almost_empty : std_logic := '0';
SIGNAL wdch_prog_empty : std_logic := '0';
SIGNAL wrch_din : std_logic_vector(C_DIN_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wrch_dout : std_logic_vector(C_DIN_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wrch_full : std_logic := '0';
SIGNAL wrch_almost_full : std_logic := '0';
SIGNAL wrch_prog_full : std_logic := '0';
SIGNAL wrch_empty : std_logic := '0';
SIGNAL wrch_almost_empty : std_logic := '0';
SIGNAL wrch_prog_empty : std_logic := '0';
SIGNAL axi_aw_underflow_i : std_logic := '0';
SIGNAL axi_w_underflow_i : std_logic := '0';
SIGNAL axi_b_underflow_i : std_logic := '0';
SIGNAL axi_aw_overflow_i : std_logic := '0';
SIGNAL axi_w_overflow_i : std_logic := '0';
SIGNAL axi_b_overflow_i : std_logic := '0';
SIGNAL wach_s_axi_awready : std_logic := '0';
SIGNAL wach_m_axi_awvalid : std_logic := '0';
SIGNAL wach_wr_en : std_logic := '0';
SIGNAL wach_rd_en : std_logic := '0';
SIGNAL wdch_s_axi_wready : std_logic := '0';
SIGNAL wdch_m_axi_wvalid : std_logic := '0';
SIGNAL wdch_wr_en : std_logic := '0';
SIGNAL wdch_rd_en : std_logic := '0';
SIGNAL wrch_s_axi_bvalid : std_logic := '0';
SIGNAL wrch_m_axi_bready : std_logic := '0';
SIGNAL wrch_wr_en : std_logic := '0';
SIGNAL wrch_rd_en : std_logic := '0';
CONSTANT AWID_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH,C_DIN_WIDTH_WACH);
CONSTANT AWADDR_OFFSET : integer := AWID_OFFSET - C_AXI_ADDR_WIDTH;
CONSTANT AWLEN_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,AWADDR_OFFSET - C_AXI_LEN_WIDTH,AWADDR_OFFSET);
CONSTANT AWSIZE_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,AWLEN_OFFSET - C_AXI_SIZE_WIDTH,AWLEN_OFFSET);
CONSTANT AWBURST_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,AWSIZE_OFFSET - C_AXI_BURST_WIDTH,AWSIZE_OFFSET);
CONSTANT AWLOCK_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,AWBURST_OFFSET - C_AXI_LOCK_WIDTH,AWBURST_OFFSET);
CONSTANT AWCACHE_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,AWLOCK_OFFSET - C_AXI_CACHE_WIDTH,AWLOCK_OFFSET);
CONSTANT AWPROT_OFFSET : integer := AWCACHE_OFFSET - C_AXI_PROT_WIDTH;
CONSTANT AWQOS_OFFSET : integer := AWPROT_OFFSET - C_AXI_QOS_WIDTH;
CONSTANT AWREGION_OFFSET : integer := AWQOS_OFFSET - C_AXI_REGION_WIDTH;
CONSTANT AWUSER_OFFSET : integer := if_then_else(C_HAS_AXI_AWUSER = 1,AWREGION_OFFSET-C_AXI_AWUSER_WIDTH,AWREGION_OFFSET);
CONSTANT WID_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH,C_DIN_WIDTH_WDCH);
CONSTANT WDATA_OFFSET : integer := WID_OFFSET - C_AXI_DATA_WIDTH;
CONSTANT WSTRB_OFFSET : integer := WDATA_OFFSET - C_AXI_DATA_WIDTH/8;
CONSTANT WUSER_OFFSET : integer := if_then_else(C_HAS_AXI_WUSER = 1,WSTRB_OFFSET-C_AXI_WUSER_WIDTH,WSTRB_OFFSET);
CONSTANT BID_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH,C_DIN_WIDTH_WRCH);
CONSTANT BRESP_OFFSET : integer := BID_OFFSET - C_AXI_BRESP_WIDTH;
CONSTANT BUSER_OFFSET : integer := if_then_else(C_HAS_AXI_BUSER = 1,BRESP_OFFSET-C_AXI_BUSER_WIDTH,BRESP_OFFSET);
BEGIN
-- Form the DIN to FIFO by concatinating the AXI Full Write Address Channel optional ports
axi_full_din_wr_ch: IF (C_AXI_TYPE = 1) GENERATE
gwach1: IF (C_WACH_TYPE < 2) GENERATE
gwach_din1: IF (C_HAS_AXI_AWUSER = 1) GENERATE
wach_din <= S_AXI_AWID & S_AXI_AWADDR & S_AXI_AWLEN & S_AXI_AWSIZE & S_AXI_AWBURST &
S_AXI_AWLOCK & S_AXI_AWCACHE & S_AXI_AWPROT & S_AXI_AWQOS & S_AXI_AWREGION &
S_AXI_AWUSER;
M_AXI_AWUSER <= wach_dout(AWREGION_OFFSET-1 DOWNTO AWUSER_OFFSET);
END GENERATE gwach_din1;
gwach_din2: IF (C_HAS_AXI_AWUSER = 0) GENERATE
wach_din <= S_AXI_AWID & S_AXI_AWADDR & S_AXI_AWLEN & S_AXI_AWSIZE & S_AXI_AWBURST &
S_AXI_AWLOCK & S_AXI_AWCACHE & S_AXI_AWPROT & S_AXI_AWQOS & S_AXI_AWREGION;
M_AXI_AWUSER <= (OTHERS => '0');
END GENERATE gwach_din2;
M_AXI_AWID <= wach_dout(C_DIN_WIDTH_WACH-1 DOWNTO AWID_OFFSET);
M_AXI_AWADDR <= wach_dout(AWID_OFFSET-1 DOWNTO AWADDR_OFFSET);
M_AXI_AWLEN <= wach_dout(AWADDR_OFFSET-1 DOWNTO AWLEN_OFFSET);
M_AXI_AWSIZE <= wach_dout(AWLEN_OFFSET-1 DOWNTO AWSIZE_OFFSET);
M_AXI_AWBURST <= wach_dout(AWSIZE_OFFSET-1 DOWNTO AWBURST_OFFSET);
M_AXI_AWLOCK <= wach_dout(AWBURST_OFFSET-1 DOWNTO AWLOCK_OFFSET);
M_AXI_AWCACHE <= wach_dout(AWLOCK_OFFSET-1 DOWNTO AWCACHE_OFFSET);
M_AXI_AWPROT <= wach_dout(AWCACHE_OFFSET-1 DOWNTO AWPROT_OFFSET);
M_AXI_AWQOS <= wach_dout(AWPROT_OFFSET-1 DOWNTO AWQOS_OFFSET);
M_AXI_AWREGION <= wach_dout(AWQOS_OFFSET-1 DOWNTO AWREGION_OFFSET);
END GENERATE gwach1;
-- Generate the DIN to FIFO by concatinating the AXI Full Write Data Channel optional ports
gwdch1: IF (C_WDCH_TYPE < 2) GENERATE
gwdch_din1: IF (C_HAS_AXI_WUSER = 1) GENERATE
wdch_din <= S_AXI_WID & S_AXI_WDATA & S_AXI_WSTRB & S_AXI_WUSER & S_AXI_WLAST;
M_AXI_WLAST <= wdch_dout(0);
M_AXI_WUSER <= wdch_dout(WSTRB_OFFSET-1 DOWNTO WUSER_OFFSET);
END GENERATE gwdch_din1;
gwdch_din2: IF (C_HAS_AXI_WUSER = 0) GENERATE
wdch_din <= S_AXI_WID & S_AXI_WDATA & S_AXI_WSTRB & S_AXI_WLAST;
M_AXI_WLAST <= wdch_dout(0);
M_AXI_WUSER <= (OTHERS => '0');
END GENERATE gwdch_din2;
M_AXI_WID <= wdch_dout(C_DIN_WIDTH_WDCH-1 DOWNTO WID_OFFSET);
M_AXI_WDATA <= wdch_dout(WID_OFFSET-1 DOWNTO WDATA_OFFSET);
M_AXI_WSTRB <= wdch_dout(WDATA_OFFSET-1 DOWNTO WSTRB_OFFSET);
END GENERATE gwdch1;
-- Generate the DIN to FIFO by concatinating the AXI Full Write Response Channel optional ports
gwrch1: IF (C_WRCH_TYPE < 2) GENERATE
gwrch_din1: IF (C_HAS_AXI_BUSER = 1) GENERATE
wrch_din <= M_AXI_BID & M_AXI_BRESP & M_AXI_BUSER;
S_AXI_BUSER <= wrch_dout(BRESP_OFFSET-1 DOWNTO BUSER_OFFSET);
END GENERATE gwrch_din1;
gwrch_din2: IF (C_HAS_AXI_BUSER = 0) GENERATE
wrch_din <= M_AXI_BID & M_AXI_BRESP;
S_AXI_BUSER <= (OTHERS => '0');
END GENERATE gwrch_din2;
S_AXI_BID <= wrch_dout(C_DIN_WIDTH_WRCH-1 DOWNTO BID_OFFSET);
S_AXI_BRESP <= wrch_dout(BID_OFFSET-1 DOWNTO BRESP_OFFSET);
END GENERATE gwrch1;
END GENERATE axi_full_din_wr_ch;
-- Form the DIN to FIFO by concatinating the AXI Lite Write Address Channel optional ports
axi_lite_din_wr_ch: IF (C_AXI_TYPE = 2) GENERATE
gwach1: IF (C_WACH_TYPE < 2) GENERATE
wach_din <= S_AXI_AWADDR & S_AXI_AWPROT;
M_AXI_AWADDR <= wach_dout(C_DIN_WIDTH_WACH-1 DOWNTO AWADDR_OFFSET);
M_AXI_AWPROT <= wach_dout(AWADDR_OFFSET-1 DOWNTO AWPROT_OFFSET);
END GENERATE gwach1;
gwdch1: IF (C_WDCH_TYPE < 2) GENERATE
wdch_din <= S_AXI_WDATA & S_AXI_WSTRB;
M_AXI_WDATA <= wdch_dout(C_DIN_WIDTH_WDCH-1 DOWNTO WDATA_OFFSET);
M_AXI_WSTRB <= wdch_dout(WDATA_OFFSET-1 DOWNTO WSTRB_OFFSET);
END GENERATE gwdch1;
gwrch1: IF (C_WRCH_TYPE < 2) GENERATE
wrch_din <= M_AXI_BRESP;
S_AXI_BRESP <= wrch_dout(C_DIN_WIDTH_WRCH-1 DOWNTO BRESP_OFFSET);
END GENERATE gwrch1;
END GENERATE axi_lite_din_wr_ch;
-- Write protection for Write Address Channel
-- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt
gwach_wr_en1: IF (C_PROG_FULL_TYPE_WACH = 5) GENERATE
wach_wr_en <= S_AXI_AWVALID;
END GENERATE gwach_wr_en1;
-- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL
gwach_wr_en2: IF (C_PROG_FULL_TYPE_WACH /= 5) GENERATE
wach_wr_en <= wach_s_axi_awready AND S_AXI_AWVALID;
END GENERATE gwach_wr_en2;
-- Write protection for Write Data Channel
-- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt
gwdch_wr_en1: IF (C_PROG_FULL_TYPE_WDCH = 5) GENERATE
wdch_wr_en <= S_AXI_WVALID;
END GENERATE gwdch_wr_en1;
-- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL
gwdch_wr_en2: IF (C_PROG_FULL_TYPE_WDCH /= 5) GENERATE
wdch_wr_en <= wdch_s_axi_wready AND S_AXI_WVALID;
END GENERATE gwdch_wr_en2;
-- Write protection for Write Response Channel
-- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt
gwrch_wr_en1: IF (C_PROG_FULL_TYPE_WRCH = 5) GENERATE
wrch_wr_en <= M_AXI_BVALID;
END GENERATE gwrch_wr_en1;
-- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL
gwrch_wr_en2: IF (C_PROG_FULL_TYPE_WRCH /= 5) GENERATE
wrch_wr_en <= wrch_m_axi_bready AND M_AXI_BVALID;
END GENERATE gwrch_wr_en2;
-- Read protection for Write Address Channel
-- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt
gwach_rd_en1: IF (C_PROG_EMPTY_TYPE_WACH = 5) GENERATE
wach_rd_en <= M_AXI_AWREADY;
END GENERATE gwach_rd_en1;
-- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY
gwach_rd_en2: IF (C_PROG_EMPTY_TYPE_WACH /= 5) GENERATE
wach_rd_en <= wach_m_axi_awvalid AND M_AXI_AWREADY;
END GENERATE gwach_rd_en2;
-- Read protection for Write Data Channel
-- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt
gwdch_rd_en1: IF (C_PROG_EMPTY_TYPE_WDCH = 5) GENERATE
wdch_rd_en <= M_AXI_WREADY;
END GENERATE gwdch_rd_en1;
-- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY
gwdch_rd_en2: IF (C_PROG_EMPTY_TYPE_WDCH /= 5) GENERATE
wdch_rd_en <= wdch_m_axi_wvalid AND M_AXI_WREADY;
END GENERATE gwdch_rd_en2;
-- Read protection for Write Response Channel
-- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt
gwrch_rd_en1: IF (C_PROG_EMPTY_TYPE_WRCH = 5) GENERATE
wrch_rd_en <= S_AXI_BREADY;
END GENERATE gwrch_rd_en1;
-- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY
gwrch_rd_en2: IF (C_PROG_EMPTY_TYPE_WRCH /= 5) GENERATE
wrch_rd_en <= wrch_s_axi_bvalid AND S_AXI_BREADY;
END GENERATE gwrch_rd_en2;
gwach2: IF (C_WACH_TYPE = 0) GENERATE
axi_wach : fifo_generator_v8_2_conv
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WACH = 1 OR C_IMPLEMENTATION_TYPE_WACH = 11),1,2),
C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WACH <= 6),0,2), -- CCBI
C_PRELOAD_REGS => 1, -- Always FWFT for AXI
C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI
C_DIN_WIDTH => C_DIN_WIDTH_WACH,
C_WR_DEPTH => C_WR_DEPTH_WACH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_WACH,
C_DOUT_WIDTH => C_DIN_WIDTH_WACH,
C_RD_DEPTH => C_WR_DEPTH_WACH,
C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_WACH,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_WACH,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_WACH,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_WACH,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH,
C_USE_ECC => C_USE_ECC_WACH,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_WACH,
C_HAS_ALMOST_EMPTY => if_then_else((C_PROG_EMPTY_TYPE_WACH = 6), 1, 0),
C_HAS_ALMOST_FULL => if_then_else((C_PROG_FULL_TYPE_WACH = 6), 1, 0),
-- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO
C_FIFO_TYPE => C_APPLICATION_TYPE_WACH,
-- Place holder parameters for the new features
-- C_USE_SYNC_CLK => 0,
-- C_BYTE_STRB_WIDTH => 8,
-- C_USE_INPUT_CE => 0,
-- C_USE_OUTPUT_CE => 0,
C_HAS_WR_RST => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_DOUT_RST_VAL => "0",
C_HAS_VALID => C_HAS_VALID,
C_VALID_LOW => C_VALID_LOW,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_WACH = 1), 1, 0),
C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WACH+1,
C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WACH = 1), 1, 0),
C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WACH+1,
C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true
C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WACH = 1), 1, 0),
C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WACH+1,
C_FULL_FLAGS_RST_VAL => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_DOUT_RST => 0,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => 1,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_RD_FREQ => C_RD_FREQ,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_WR_FREQ => C_WR_FREQ,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
INT_CLK => INT_CLK,
CLK => S_ACLK,
WR_CLK => S_ACLK,
RD_CLK => M_ACLK,
RST => inverted_reset,
SRST => '0',
WR_RST => inverted_reset,
RD_RST => inverted_reset,
WR_EN => wach_wr_en,--S_AXI_AWVALID,
RD_EN => wach_rd_en,--M_AXI_AWREADY,
PROG_FULL_THRESH => AXI_AW_PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => (OTHERS => '0'),
PROG_FULL_THRESH_NEGATE => (OTHERS => '0'),
PROG_EMPTY_THRESH => AXI_AW_PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'),
PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'),
INJECTDBITERR => AXI_AW_INJECTDBITERR,
INJECTSBITERR => AXI_AW_INJECTSBITERR,
-- Place holder parameters for the new features
-- INPUT_CE => AXI_AW_INPUT_CE,
-- OUTPUT_CE => AXI_AW_OUTPUT_CE,
-- END_OF_PACKET => AXI_AW_END_OF_PACKET,
-- BYTE_STROBE => AXI_AW_BYTE_STROBE,
DIN => wach_din,
DOUT => wach_dout,
FULL => wach_full,
ALMOST_FULL => wach_almost_full,
PROG_FULL => wach_prog_full,
EMPTY => wach_empty,
ALMOST_EMPTY => wach_almost_empty,
PROG_EMPTY => wach_prog_empty,
WR_ACK => OPEN,
OVERFLOW => axi_aw_overflow_i,
VALID => OPEN,
UNDERFLOW => axi_aw_underflow_i,
DATA_COUNT => AXI_AW_DATA_COUNT,
RD_DATA_COUNT => AXI_AW_RD_DATA_COUNT,
WR_DATA_COUNT => AXI_AW_WR_DATA_COUNT,
SBITERR => AXI_AW_SBITERR,
DBITERR => AXI_AW_DBITERR
);
wach_s_axi_awready <= map_ready_valid(C_PROG_FULL_TYPE_WACH,wach_full,wach_almost_full,wach_prog_full);
wach_m_axi_awvalid <= map_ready_valid(C_PROG_EMPTY_TYPE_WACH,wach_empty,wach_almost_empty,wach_prog_empty);
S_AXI_AWREADY <= wach_s_axi_awready;--map_ready_valid(C_PROG_FULL_TYPE_WACH,wach_full,wach_almost_full,wach_prog_full);
M_AXI_AWVALID <= wach_m_axi_awvalid;--map_ready_valid(C_PROG_EMPTY_TYPE_WACH,wach_empty,wach_almost_empty,wach_prog_empty);
gaxi_wr_ch_uf1: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE
AXI_AW_UNDERFLOW <= axi_aw_underflow_i;
END GENERATE gaxi_wr_ch_uf1;
gaxi_wr_ch_of1: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE
AXI_AW_OVERFLOW <= axi_aw_overflow_i;
END GENERATE gaxi_wr_ch_of1;
END GENERATE gwach2;
-- Register Slice for Write Address Channel
gwach_reg_slice: IF (C_WACH_TYPE = 1) GENERATE
wach_reg_slice: fifo_generator_v8_2_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_WACH,
C_REG_CONFIG => C_REG_SLICE_MODE_WACH
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => inverted_reset,
-- Slave side
S_PAYLOAD_DATA => wach_din,
S_VALID => S_AXI_AWVALID,
S_READY => S_AXI_AWREADY,
-- Master side
M_PAYLOAD_DATA => wach_dout,
M_VALID => M_AXI_AWVALID,
M_READY => M_AXI_AWREADY
);
END GENERATE gwach_reg_slice;
gwdch2: IF (C_WDCH_TYPE = 0) GENERATE
axi_wdch : fifo_generator_v8_2_conv
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WDCH = 1 OR C_IMPLEMENTATION_TYPE_WDCH = 11),1,2),
C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WDCH <= 6),0,2), -- CCBI
C_PRELOAD_REGS => 1, -- Always FWFT for AXI
C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI
C_DIN_WIDTH => C_DIN_WIDTH_WDCH,
C_WR_DEPTH => C_WR_DEPTH_WDCH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_WDCH,
C_DOUT_WIDTH => C_DIN_WIDTH_WDCH,
C_RD_DEPTH => C_WR_DEPTH_WDCH,
C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_WDCH,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_WDCH,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_WDCH,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_WDCH,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH,
C_USE_ECC => C_USE_ECC_WDCH,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_WDCH,
C_HAS_ALMOST_EMPTY => if_then_else((C_PROG_EMPTY_TYPE_WDCH = 6), 1, 0),
C_HAS_ALMOST_FULL => if_then_else((C_PROG_FULL_TYPE_WDCH = 6), 1, 0),
-- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO
C_FIFO_TYPE => C_APPLICATION_TYPE_WDCH,
-- Place holder parameters for the new features
-- C_USE_SYNC_CLK => 0,
-- C_BYTE_STRB_WIDTH => 8,
-- C_USE_INPUT_CE => 0,
-- C_USE_OUTPUT_CE => 0,
C_HAS_WR_RST => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_DOUT_RST_VAL => "0",
C_HAS_VALID => C_HAS_VALID,
C_VALID_LOW => C_VALID_LOW,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_WDCH = 1), 1, 0),
C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WDCH+1,
C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WDCH = 1), 1, 0),
C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WDCH+1,
C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true
C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WDCH = 1), 1, 0),
C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WDCH+1,
C_FULL_FLAGS_RST_VAL => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_DOUT_RST => 0,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => 1,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_RD_FREQ => C_RD_FREQ,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_WR_FREQ => C_WR_FREQ,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
INT_CLK => INT_CLK,
CLK => S_ACLK,
WR_CLK => S_ACLK,
RD_CLK => M_ACLK,
RST => inverted_reset,
SRST => '0',
WR_RST => inverted_reset,
RD_RST => inverted_reset,
WR_EN => wdch_wr_en,--S_AXI_WVALID,
RD_EN => wdch_rd_en,--M_AXI_WREADY,
PROG_FULL_THRESH => AXI_W_PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => (OTHERS => '0'),
PROG_FULL_THRESH_NEGATE => (OTHERS => '0'),
PROG_EMPTY_THRESH => AXI_W_PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'),
PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'),
INJECTDBITERR => AXI_W_INJECTDBITERR,
INJECTSBITERR => AXI_W_INJECTSBITERR,
-- Place holder parameters for the new features
-- INPUT_CE => AXI_W_INPUT_CE,
-- OUTPUT_CE => AXI_W_OUTPUT_CE,
-- END_OF_PACKET => AXI_W_END_OF_PACKET,
-- BYTE_STROBE => AXI_W_BYTE_STROBE,
DIN => wdch_din,
DOUT => wdch_dout,
FULL => wdch_full,
ALMOST_FULL => wdch_almost_full,
PROG_FULL => wdch_prog_full,
EMPTY => wdch_empty,
ALMOST_EMPTY => wdch_almost_empty,
PROG_EMPTY => wdch_prog_empty,
WR_ACK => OPEN,
OVERFLOW => axi_w_overflow_i,
VALID => OPEN,
UNDERFLOW => axi_w_underflow_i,
DATA_COUNT => AXI_W_DATA_COUNT,
RD_DATA_COUNT => AXI_W_RD_DATA_COUNT,
WR_DATA_COUNT => AXI_W_WR_DATA_COUNT,
SBITERR => AXI_W_SBITERR,
DBITERR => AXI_W_DBITERR
);
wdch_s_axi_wready <= map_ready_valid(C_PROG_FULL_TYPE_WDCH,wdch_full,wdch_almost_full,wdch_prog_full);
wdch_m_axi_wvalid <= map_ready_valid(C_PROG_EMPTY_TYPE_WDCH,wdch_empty,wdch_almost_empty,wdch_prog_empty);
S_AXI_WREADY <= wdch_s_axi_wready;--map_ready_valid(C_PROG_FULL_TYPE_WDCH,wdch_full,wdch_almost_full,wdch_prog_full);
M_AXI_WVALID <= wdch_m_axi_wvalid;--map_ready_valid(C_PROG_EMPTY_TYPE_WDCH,wdch_empty,wdch_almost_empty,wdch_prog_empty);
gaxi_wr_ch_uf2: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE
AXI_W_UNDERFLOW <= axi_w_underflow_i;
END GENERATE gaxi_wr_ch_uf2;
gaxi_wr_ch_of2: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE
AXI_W_OVERFLOW <= axi_w_overflow_i;
END GENERATE gaxi_wr_ch_of2;
END GENERATE gwdch2;
-- Register Slice for Write Data Channel
gwdch_reg_slice: IF (C_WDCH_TYPE = 1) GENERATE
wdch_reg_slice: fifo_generator_v8_2_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_WDCH,
C_REG_CONFIG => C_REG_SLICE_MODE_WDCH
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => inverted_reset,
-- Slave side
S_PAYLOAD_DATA => wdch_din,
S_VALID => S_AXI_WVALID,
S_READY => S_AXI_WREADY,
-- Master side
M_PAYLOAD_DATA => wdch_dout,
M_VALID => M_AXI_WVALID,
M_READY => M_AXI_WREADY
);
END GENERATE gwdch_reg_slice;
gwrch2: IF (C_WRCH_TYPE = 0) GENERATE
axi_wrch : fifo_generator_v8_2_conv -- Write Response Channel
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WRCH = 1 OR C_IMPLEMENTATION_TYPE_WRCH = 11),1,2),
C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WRCH <= 6),0,2), -- CCBI
C_PRELOAD_REGS => 1, -- Always FWFT for AXI
C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI
C_DIN_WIDTH => C_DIN_WIDTH_WRCH,
C_WR_DEPTH => C_WR_DEPTH_WRCH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_WRCH,
C_DOUT_WIDTH => C_DIN_WIDTH_WRCH,
C_RD_DEPTH => C_WR_DEPTH_WRCH,
C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_WRCH,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_WRCH,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_WRCH,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_WRCH,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH,
C_USE_ECC => C_USE_ECC_WRCH,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_WRCH,
C_HAS_ALMOST_EMPTY => if_then_else((C_PROG_EMPTY_TYPE_WRCH = 6), 1, 0),
C_HAS_ALMOST_FULL => if_then_else((C_PROG_FULL_TYPE_WRCH = 6), 1, 0),
-- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO
C_FIFO_TYPE => C_APPLICATION_TYPE_WRCH,
-- Place holder parameters for the new features
-- C_USE_SYNC_CLK => 0,
-- C_BYTE_STRB_WIDTH => 8,
-- C_USE_INPUT_CE => 0,
-- C_USE_OUTPUT_CE => 0,
C_HAS_WR_RST => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_DOUT_RST_VAL => "0",
C_HAS_VALID => C_HAS_VALID,
C_VALID_LOW => C_VALID_LOW,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_WRCH = 1), 1, 0),
C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WRCH+1,
C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WRCH = 1), 1, 0),
C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WRCH+1,
C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true
C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WRCH = 1), 1, 0),
C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WRCH+1,
C_FULL_FLAGS_RST_VAL => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_DOUT_RST => 0,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => 1,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_RD_FREQ => C_RD_FREQ,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_WR_FREQ => C_WR_FREQ,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
INT_CLK => INT_CLK,
CLK => S_ACLK,
WR_CLK => S_ACLK,
RD_CLK => M_ACLK,
RST => inverted_reset,
SRST => '0',
WR_RST => inverted_reset,
RD_RST => inverted_reset,
WR_EN => wrch_wr_en,--M_AXI_BVALID,
RD_EN => wrch_rd_en,--S_AXI_BREADY,
PROG_FULL_THRESH => AXI_B_PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => (OTHERS => '0'),
PROG_FULL_THRESH_NEGATE => (OTHERS => '0'),
PROG_EMPTY_THRESH => AXI_B_PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'),
PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'),
INJECTDBITERR => AXI_B_INJECTDBITERR,
INJECTSBITERR => AXI_B_INJECTSBITERR,
-- Place holder parameters for the new features
-- INPUT_CE => AXI_B_INPUT_CE,
-- OUTPUT_CE => AXI_B_OUTPUT_CE,
-- END_OF_PACKET => AXI_B_END_OF_PACKET,
-- BYTE_STROBE => AXI_B_BYTE_STROBE,
DIN => wrch_din,
DOUT => wrch_dout,
FULL => wrch_full,
ALMOST_FULL => wrch_almost_full,
PROG_FULL => wrch_prog_full,
EMPTY => wrch_empty,
ALMOST_EMPTY => wrch_almost_empty,
PROG_EMPTY => wrch_prog_empty,
WR_ACK => OPEN,
OVERFLOW => axi_b_overflow_i,
VALID => OPEN,
UNDERFLOW => axi_b_underflow_i,
DATA_COUNT => AXI_B_DATA_COUNT,
RD_DATA_COUNT => AXI_B_RD_DATA_COUNT,
WR_DATA_COUNT => AXI_B_WR_DATA_COUNT,
SBITERR => AXI_B_SBITERR,
DBITERR => AXI_B_DBITERR
);
wrch_s_axi_bvalid <= map_ready_valid(C_PROG_EMPTY_TYPE_WRCH,wrch_empty,wrch_almost_empty,wrch_prog_empty);
wrch_m_axi_bready <= map_ready_valid(C_PROG_FULL_TYPE_WRCH,wrch_full,wrch_almost_full,wrch_prog_full);
S_AXI_BVALID <= wrch_s_axi_bvalid;--map_ready_valid(C_PROG_EMPTY_TYPE_WRCH,wrch_empty,wrch_almost_empty,wrch_prog_empty);
M_AXI_BREADY <= wrch_m_axi_bready;--map_ready_valid(C_PROG_FULL_TYPE_WRCH,wrch_full,wrch_almost_full,wrch_prog_full);
gaxi_wr_ch_uf3: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE
AXI_B_UNDERFLOW <= axi_b_underflow_i;
END GENERATE gaxi_wr_ch_uf3;
gaxi_wr_ch_of3: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE
AXI_B_OVERFLOW <= axi_b_overflow_i;
END GENERATE gaxi_wr_ch_of3;
END GENERATE gwrch2;
-- Register Slice for Write Response Channel
gwrch_reg_slice: IF (C_WRCH_TYPE = 1) GENERATE
wrch_reg_slice: fifo_generator_v8_2_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_WRCH,
C_REG_CONFIG => C_REG_SLICE_MODE_WRCH
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => inverted_reset,
-- Slave side
S_PAYLOAD_DATA => wrch_din,
S_VALID => M_AXI_BVALID,
S_READY => M_AXI_BREADY,
-- Master side
M_PAYLOAD_DATA => wrch_dout,
M_VALID => S_AXI_BVALID,
M_READY => S_AXI_BREADY
);
END GENERATE gwrch_reg_slice;
gaxi_wr_ch_uf4: IF (C_USE_COMMON_UNDERFLOW = 1) GENERATE
axi_wr_underflow_i <= axi_aw_underflow_i OR axi_w_underflow_i OR axi_b_underflow_i;
END GENERATE gaxi_wr_ch_uf4;
gaxi_wr_ch_of4: IF (C_USE_COMMON_OVERFLOW = 1) GENERATE
axi_wr_overflow_i <= axi_aw_overflow_i OR axi_w_overflow_i OR axi_b_overflow_i;
END GENERATE gaxi_wr_ch_of4;
END GENERATE gwrch;
grdch: IF (C_HAS_AXI_RD_CHANNEL = 1) GENERATE
SIGNAL rach_din : std_logic_vector(C_DIN_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rach_dout : std_logic_vector(C_DIN_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rach_full : std_logic := '0';
SIGNAL rach_almost_full : std_logic := '0';
SIGNAL rach_prog_full : std_logic := '0';
SIGNAL rach_empty : std_logic := '0';
SIGNAL rach_almost_empty : std_logic := '0';
SIGNAL rach_prog_empty : std_logic := '0';
SIGNAL rdch_din : std_logic_vector(C_DIN_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdch_dout : std_logic_vector(C_DIN_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdch_full : std_logic := '0';
SIGNAL rdch_almost_full : std_logic := '0';
SIGNAL rdch_prog_full : std_logic := '0';
SIGNAL rdch_empty : std_logic := '0';
SIGNAL rdch_almost_empty : std_logic := '0';
SIGNAL rdch_prog_empty : std_logic := '0';
SIGNAL axi_ar_underflow_i : std_logic := '0';
SIGNAL axi_ar_overflow_i : std_logic := '0';
SIGNAL axi_r_underflow_i : std_logic := '0';
SIGNAL axi_r_overflow_i : std_logic := '0';
SIGNAL rach_s_axi_arready : std_logic := '0';
SIGNAL rach_m_axi_arvalid : std_logic := '0';
SIGNAL rach_wr_en : std_logic := '0';
SIGNAL rach_rd_en : std_logic := '0';
SIGNAL rdch_m_axi_rready : std_logic := '0';
SIGNAL rdch_s_axi_rvalid : std_logic := '0';
SIGNAL rdch_wr_en : std_logic := '0';
SIGNAL rdch_rd_en : std_logic := '0';
CONSTANT ARID_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH,C_DIN_WIDTH_RACH);
CONSTANT ARADDR_OFFSET : integer := ARID_OFFSET - C_AXI_ADDR_WIDTH;
CONSTANT ARLEN_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,ARADDR_OFFSET - C_AXI_LEN_WIDTH,ARADDR_OFFSET);
CONSTANT ARSIZE_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,ARLEN_OFFSET - C_AXI_SIZE_WIDTH,ARLEN_OFFSET);
CONSTANT ARBURST_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,ARSIZE_OFFSET - C_AXI_BURST_WIDTH,ARSIZE_OFFSET);
CONSTANT ARLOCK_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,ARBURST_OFFSET - C_AXI_LOCK_WIDTH,ARBURST_OFFSET);
CONSTANT ARCACHE_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,ARLOCK_OFFSET - C_AXI_CACHE_WIDTH,ARLOCK_OFFSET);
CONSTANT ARPROT_OFFSET : integer := ARCACHE_OFFSET - C_AXI_PROT_WIDTH;
CONSTANT ARQOS_OFFSET : integer := ARPROT_OFFSET - C_AXI_QOS_WIDTH;
CONSTANT ARREGION_OFFSET : integer := ARQOS_OFFSET - C_AXI_REGION_WIDTH;
CONSTANT ARUSER_OFFSET : integer := if_then_else(C_HAS_AXI_ARUSER = 1,ARREGION_OFFSET-C_AXI_ARUSER_WIDTH,ARREGION_OFFSET);
CONSTANT RID_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH,C_DIN_WIDTH_RDCH);
CONSTANT RDATA_OFFSET : integer := RID_OFFSET - C_AXI_DATA_WIDTH;
CONSTANT RRESP_OFFSET : integer := RDATA_OFFSET - C_AXI_RRESP_WIDTH;
CONSTANT RUSER_OFFSET : integer := if_then_else(C_HAS_AXI_RUSER = 1,RRESP_OFFSET-C_AXI_RUSER_WIDTH,RRESP_OFFSET);
BEGIN
-- Form the DIN to FIFO by concatinating the AXI Full Write Address Channel optional ports
axi_full_din_rd_ch: IF (C_AXI_TYPE = 1) GENERATE
grach1: IF (C_RACH_TYPE < 2) GENERATE
grach_din1: IF (C_HAS_AXI_ARUSER = 1) GENERATE
rach_din <= S_AXI_ARID & S_AXI_ARADDR & S_AXI_ARLEN & S_AXI_ARSIZE & S_AXI_ARBURST &
S_AXI_ARLOCK & S_AXI_ARCACHE & S_AXI_ARPROT & S_AXI_ARQOS & S_AXI_ARREGION &
S_AXI_ARUSER;
M_AXI_ARUSER <= rach_dout(ARREGION_OFFSET-1 DOWNTO ARUSER_OFFSET);
END GENERATE grach_din1;
grach_din2: IF (C_HAS_AXI_ARUSER = 0) GENERATE
rach_din <= S_AXI_ARID & S_AXI_ARADDR & S_AXI_ARLEN & S_AXI_ARSIZE & S_AXI_ARBURST &
S_AXI_ARLOCK & S_AXI_ARCACHE & S_AXI_ARPROT & S_AXI_ARQOS & S_AXI_ARREGION;
M_AXI_ARUSER <= (OTHERS => '0');
END GENERATE grach_din2;
M_AXI_ARID <= rach_dout(C_DIN_WIDTH_RACH-1 DOWNTO ARID_OFFSET);
M_AXI_ARADDR <= rach_dout(ARID_OFFSET-1 DOWNTO ARADDR_OFFSET);
M_AXI_ARLEN <= rach_dout(ARADDR_OFFSET-1 DOWNTO ARLEN_OFFSET);
M_AXI_ARSIZE <= rach_dout(ARLEN_OFFSET-1 DOWNTO ARSIZE_OFFSET);
M_AXI_ARBURST <= rach_dout(ARSIZE_OFFSET-1 DOWNTO ARBURST_OFFSET);
M_AXI_ARLOCK <= rach_dout(ARBURST_OFFSET-1 DOWNTO ARLOCK_OFFSET);
M_AXI_ARCACHE <= rach_dout(ARLOCK_OFFSET-1 DOWNTO ARCACHE_OFFSET);
M_AXI_ARPROT <= rach_dout(ARCACHE_OFFSET-1 DOWNTO ARPROT_OFFSET);
M_AXI_ARQOS <= rach_dout(ARPROT_OFFSET-1 DOWNTO ARQOS_OFFSET);
M_AXI_ARREGION <= rach_dout(ARQOS_OFFSET-1 DOWNTO ARREGION_OFFSET);
END GENERATE grach1;
-- Generate the DIN to FIFO by concatinating the AXI Full Read Data Channel optional ports
grdch1: IF (C_RDCH_TYPE < 2) GENERATE
grdch_din1: IF (C_HAS_AXI_RUSER = 1) GENERATE
rdch_din <= M_AXI_RID & M_AXI_RDATA & M_AXI_RRESP & M_AXI_RUSER & M_AXI_RLAST;
S_AXI_RLAST <= rdch_dout(0);
S_AXI_RUSER <= rdch_dout(RRESP_OFFSET-1 DOWNTO RUSER_OFFSET);
END GENERATE grdch_din1;
grdch_din2: IF (C_HAS_AXI_RUSER = 0) GENERATE
rdch_din <= M_AXI_RID & M_AXI_RDATA & M_AXI_RRESP & M_AXI_RLAST;
S_AXI_RLAST <= rdch_dout(0);
S_AXI_RUSER <= (OTHERS => '0');
END GENERATE grdch_din2;
S_AXI_RID <= rdch_dout(C_DIN_WIDTH_RDCH-1 DOWNTO RID_OFFSET);
S_AXI_RDATA <= rdch_dout(RID_OFFSET-1 DOWNTO RDATA_OFFSET);
S_AXI_RRESP <= rdch_dout(RDATA_OFFSET-1 DOWNTO RRESP_OFFSET);
END GENERATE grdch1;
END GENERATE axi_full_din_rd_ch;
-- Form the DIN to FIFO by concatinating the AXI Lite Read Address Channel optional ports
axi_lite_din_rd_ch: IF (C_AXI_TYPE = 2) GENERATE
grach1: IF (C_RACH_TYPE < 2) GENERATE
rach_din <= S_AXI_ARADDR & S_AXI_ARPROT;
M_AXI_ARADDR <= rach_dout(C_DIN_WIDTH_RACH-1 DOWNTO ARADDR_OFFSET);
M_AXI_ARPROT <= rach_dout(ARADDR_OFFSET-1 DOWNTO ARPROT_OFFSET);
END GENERATE grach1;
grdch1: IF (C_RDCH_TYPE < 2) GENERATE
rdch_din <= M_AXI_RDATA & M_AXI_RRESP;
S_AXI_RDATA <= rdch_dout(C_DIN_WIDTH_RDCH-1 DOWNTO RDATA_OFFSET);
S_AXI_RRESP <= rdch_dout(RDATA_OFFSET-1 DOWNTO RRESP_OFFSET);
END GENERATE grdch1;
END GENERATE axi_lite_din_rd_ch;
-- Write protection for Read Address Channel
-- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt
grach_wr_en1: IF (C_PROG_FULL_TYPE_RACH = 5) GENERATE
rach_wr_en <= S_AXI_ARVALID;
END GENERATE grach_wr_en1;
-- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL
grach_wr_en2: IF (C_PROG_FULL_TYPE_RACH /= 5) GENERATE
rach_wr_en <= rach_s_axi_arready AND S_AXI_ARVALID;
END GENERATE grach_wr_en2;
-- Write protection for Read Data Channel
-- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt
grdch_wr_en1: IF (C_PROG_FULL_TYPE_RDCH = 5) GENERATE
rdch_wr_en <= M_AXI_RVALID;
END GENERATE grdch_wr_en1;
-- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL
grdch_wr_en2: IF (C_PROG_FULL_TYPE_RDCH /= 5) GENERATE
rdch_wr_en <= rdch_m_axi_rready AND M_AXI_RVALID;
END GENERATE grdch_wr_en2;
-- Read protection for Read Address Channel
-- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt
grach_rd_en1: IF (C_PROG_EMPTY_TYPE_RACH = 5) GENERATE
rach_rd_en <= M_AXI_ARREADY;
END GENERATE grach_rd_en1;
-- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY
grach_rd_en2: IF (C_PROG_EMPTY_TYPE_RACH /= 5) GENERATE
rach_rd_en <= rach_m_axi_arvalid AND M_AXI_ARREADY;
END GENERATE grach_rd_en2;
-- Read protection for Read Data Channel
-- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt
grdch_rd_en1: IF (C_PROG_EMPTY_TYPE_RDCH = 5) GENERATE
rdch_rd_en <= S_AXI_RREADY;
END GENERATE grdch_rd_en1;
-- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY
grdch_rd_en2: IF (C_PROG_EMPTY_TYPE_RDCH /= 5) GENERATE
rdch_rd_en <= rdch_s_axi_rvalid AND S_AXI_RREADY;
END GENERATE grdch_rd_en2;
grach2: IF (C_RACH_TYPE = 0) GENERATE
axi_rach : fifo_generator_v8_2_conv
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_RACH = 1 OR C_IMPLEMENTATION_TYPE_RACH = 11),1,2),
C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_RACH <= 6),0,2), -- CCBI
C_PRELOAD_REGS => 1, -- Always FWFT for AXI
C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI
C_DIN_WIDTH => C_DIN_WIDTH_RACH,
C_WR_DEPTH => C_WR_DEPTH_RACH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_RACH,
C_DOUT_WIDTH => C_DIN_WIDTH_RACH,
C_RD_DEPTH => C_WR_DEPTH_RACH,
C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_RACH,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_RACH,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_RACH,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_RACH,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH,
C_USE_ECC => C_USE_ECC_RACH,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_RACH,
C_HAS_ALMOST_EMPTY => if_then_else((C_PROG_EMPTY_TYPE_RACH = 6), 1, 0),
C_HAS_ALMOST_FULL => if_then_else((C_PROG_FULL_TYPE_RACH = 6), 1, 0),
-- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO
C_FIFO_TYPE => C_APPLICATION_TYPE_RACH,
-- Place holder parameters for the new features
-- C_USE_SYNC_CLK => 0,
-- C_BYTE_STRB_WIDTH => 8,
-- C_USE_INPUT_CE => 0,
-- C_USE_OUTPUT_CE => 0,
C_HAS_WR_RST => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_DOUT_RST_VAL => "0",
C_HAS_VALID => C_HAS_VALID,
C_VALID_LOW => C_VALID_LOW,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_RACH = 1), 1, 0),
C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RACH+1,
C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_RACH = 1), 1, 0),
C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RACH+1,
C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true
C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_RACH = 1), 1, 0),
C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RACH+1,
C_FULL_FLAGS_RST_VAL => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_DOUT_RST => 0,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => 1,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_WR_FREQ => C_WR_FREQ,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_RD_FREQ => C_RD_FREQ,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
INT_CLK => INT_CLK,
CLK => S_ACLK,
WR_CLK => S_ACLK,
RD_CLK => M_ACLK,
RST => inverted_reset,
SRST => '0',
WR_RST => inverted_reset,
RD_RST => inverted_reset,
WR_EN => rach_wr_en,--S_AXI_ARVALID,
RD_EN => rach_rd_en,--M_AXI_ARREADY,
PROG_FULL_THRESH => AXI_AR_PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => (OTHERS => '0'),
PROG_FULL_THRESH_NEGATE => (OTHERS => '0'),
PROG_EMPTY_THRESH => AXI_AR_PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'),
PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'),
INJECTDBITERR => AXI_AR_INJECTDBITERR,
INJECTSBITERR => AXI_AR_INJECTSBITERR,
-- Place holder parameters for the new features
-- INPUT_CE => AXI_AR_INPUT_CE,
-- OUTPUT_CE => AXI_AR_OUTPUT_CE,
-- END_OF_PACKET => AXI_AR_END_OF_PACKET,
-- BYTE_STROBE => AXI_AR_BYTE_STROBE,
DIN => rach_din,
DOUT => rach_dout,
FULL => rach_full,
ALMOST_FULL => rach_almost_full,
PROG_FULL => rach_prog_full,
EMPTY => rach_empty,
ALMOST_EMPTY => rach_almost_empty,
PROG_EMPTY => rach_prog_empty,
WR_ACK => OPEN,
OVERFLOW => axi_ar_overflow_i,
VALID => OPEN,
UNDERFLOW => axi_ar_underflow_i,
DATA_COUNT => AXI_AR_DATA_COUNT,
RD_DATA_COUNT => AXI_AR_RD_DATA_COUNT,
WR_DATA_COUNT => AXI_AR_WR_DATA_COUNT,
SBITERR => AXI_AR_SBITERR,
DBITERR => AXI_AR_DBITERR
);
rach_s_axi_arready <= map_ready_valid(C_PROG_FULL_TYPE_RACH,rach_full,rach_almost_full,rach_prog_full);
rach_m_axi_arvalid <= map_ready_valid(C_PROG_EMPTY_TYPE_RACH,rach_empty,rach_almost_empty,rach_prog_empty);
S_AXI_ARREADY <= rach_s_axi_arready;--map_ready_valid(C_PROG_FULL_TYPE_RACH,rach_full,rach_almost_full,rach_prog_full);
M_AXI_ARVALID <= rach_m_axi_arvalid;--map_ready_valid(C_PROG_EMPTY_TYPE_RACH,rach_empty,rach_almost_empty,rach_prog_empty);
gaxi_rd_ch_uf1: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE
AXI_AR_UNDERFLOW <= axi_ar_underflow_i;
END GENERATE gaxi_rd_ch_uf1;
gaxi_rd_ch_of1: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE
AXI_AR_OVERFLOW <= axi_ar_overflow_i;
END GENERATE gaxi_rd_ch_of1;
END GENERATE grach2;
-- Register Slice for Read Address Channel
grach_reg_slice: IF (C_RACH_TYPE = 1) GENERATE
rach_reg_slice: fifo_generator_v8_2_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_RACH,
C_REG_CONFIG => C_REG_SLICE_MODE_RACH
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => inverted_reset,
-- Slave side
S_PAYLOAD_DATA => rach_din,
S_VALID => S_AXI_ARVALID,
S_READY => S_AXI_ARREADY,
-- Master side
M_PAYLOAD_DATA => rach_dout,
M_VALID => M_AXI_ARVALID,
M_READY => M_AXI_ARREADY
);
END GENERATE grach_reg_slice;
grdch2: IF (C_RDCH_TYPE = 0) GENERATE
axi_rdch : fifo_generator_v8_2_conv
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_RDCH = 1 OR C_IMPLEMENTATION_TYPE_RDCH = 11),1,2),
C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_RDCH <= 6),0,2), -- CCBI
C_PRELOAD_REGS => 1, -- Always FWFT for AXI
C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI
C_DIN_WIDTH => C_DIN_WIDTH_RDCH,
C_WR_DEPTH => C_WR_DEPTH_RDCH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_RDCH,
C_DOUT_WIDTH => C_DIN_WIDTH_RDCH,
C_RD_DEPTH => C_WR_DEPTH_RDCH,
C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_RDCH,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_RDCH,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_RDCH,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_RDCH,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH,
C_USE_ECC => C_USE_ECC_RDCH,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_RDCH,
C_HAS_ALMOST_EMPTY => if_then_else((C_PROG_EMPTY_TYPE_RDCH = 6), 1, 0),
C_HAS_ALMOST_FULL => if_then_else((C_PROG_FULL_TYPE_RDCH = 6), 1, 0),
-- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO
C_FIFO_TYPE => C_APPLICATION_TYPE_RDCH,
-- Place holder parameters for the new features
-- C_USE_SYNC_CLK => 0,
-- C_BYTE_STRB_WIDTH => 8,
-- C_USE_INPUT_CE => 0,
-- C_USE_OUTPUT_CE => 0,
C_HAS_WR_RST => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_DOUT_RST_VAL => "0",
C_HAS_VALID => C_HAS_VALID,
C_VALID_LOW => C_VALID_LOW,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_RDCH = 1), 1, 0),
C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RDCH+1,
C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_RDCH = 1), 1, 0),
C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RDCH+1,
C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true
C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_RDCH = 1), 1, 0),
C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RDCH+1,
C_FULL_FLAGS_RST_VAL => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_DOUT_RST => 0,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => 1,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_WR_FREQ => C_WR_FREQ,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_RD_FREQ => C_RD_FREQ,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
INT_CLK => INT_CLK,
CLK => S_ACLK,
WR_CLK => S_ACLK,
RD_CLK => M_ACLK,
RST => inverted_reset,
SRST => '0',
WR_RST => inverted_reset,
RD_RST => inverted_reset,
WR_EN => rdch_wr_en,--M_AXI_RVALID,
RD_EN => rdch_rd_en,--S_AXI_RREADY,
PROG_FULL_THRESH => AXI_R_PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => (OTHERS => '0'),
PROG_FULL_THRESH_NEGATE => (OTHERS => '0'),
PROG_EMPTY_THRESH => AXI_R_PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'),
PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'),
INJECTDBITERR => AXI_R_INJECTDBITERR,
INJECTSBITERR => AXI_R_INJECTSBITERR,
-- Place holder parameters for the new features
-- INPUT_CE => AXI_R_INPUT_CE,
-- OUTPUT_CE => AXI_R_OUTPUT_CE,
-- END_OF_PACKET => AXI_R_END_OF_PACKET,
-- BYTE_STROBE => AXI_R_BYTE_STROBE,
DIN => rdch_din,
DOUT => rdch_dout,
FULL => rdch_full,
ALMOST_FULL => rdch_almost_full,
PROG_FULL => rdch_prog_full,
EMPTY => rdch_empty,
ALMOST_EMPTY => rdch_almost_empty,
PROG_EMPTY => rdch_prog_empty,
WR_ACK => OPEN,
OVERFLOW => axi_r_overflow_i,
VALID => OPEN,
UNDERFLOW => axi_r_underflow_i,
DATA_COUNT => AXI_R_DATA_COUNT,
RD_DATA_COUNT => AXI_R_RD_DATA_COUNT,
WR_DATA_COUNT => AXI_R_WR_DATA_COUNT,
SBITERR => AXI_R_SBITERR,
DBITERR => AXI_R_DBITERR
);
rdch_s_axi_rvalid <= map_ready_valid(C_PROG_EMPTY_TYPE_RDCH,rdch_empty,rdch_almost_empty,rdch_prog_empty);
rdch_m_axi_rready <= map_ready_valid(C_PROG_FULL_TYPE_RDCH,rdch_full,rdch_almost_full,rdch_prog_full);
S_AXI_RVALID <= rdch_s_axi_rvalid;--map_ready_valid(C_PROG_EMPTY_TYPE_RDCH,rdch_empty,rdch_almost_empty,rdch_prog_empty);
M_AXI_RREADY <= rdch_m_axi_rready;--map_ready_valid(C_PROG_FULL_TYPE_RDCH,rdch_full,rdch_almost_full,rdch_prog_full);
gaxi_rd_ch_uf2: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE
AXI_R_UNDERFLOW <= axi_r_underflow_i;
END GENERATE gaxi_rd_ch_uf2;
gaxi_rd_ch_of2: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE
AXI_R_OVERFLOW <= axi_r_overflow_i;
END GENERATE gaxi_rd_ch_of2;
END GENERATE grdch2;
-- Register Slice for Read Data Channel
grdch_reg_slice: IF (C_RDCH_TYPE = 1) GENERATE
rdch_reg_slice: fifo_generator_v8_2_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_RDCH,
C_REG_CONFIG => C_REG_SLICE_MODE_RDCH
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => inverted_reset,
-- Slave side
S_PAYLOAD_DATA => rdch_din,
S_VALID => M_AXI_RVALID,
S_READY => M_AXI_RREADY,
-- Master side
M_PAYLOAD_DATA => rdch_dout,
M_VALID => S_AXI_RVALID,
M_READY => S_AXI_RREADY
);
END GENERATE grdch_reg_slice;
gaxi_rd_ch_uf3: IF (C_USE_COMMON_UNDERFLOW = 1) GENERATE
axi_rd_underflow_i <= axi_ar_underflow_i OR axi_r_underflow_i;
END GENERATE gaxi_rd_ch_uf3;
gaxi_rd_ch_of3: IF (C_USE_COMMON_OVERFLOW = 1) GENERATE
axi_rd_overflow_i <= axi_ar_overflow_i OR axi_r_overflow_i;
END GENERATE gaxi_rd_ch_of3;
END GENERATE grdch;
gaxi_comm_uf: IF (C_USE_COMMON_UNDERFLOW = 1) GENERATE
grdwr_uf1: IF (C_HAS_AXI_WR_CHANNEL = 1 AND C_HAS_AXI_RD_CHANNEL = 1) GENERATE
UNDERFLOW <= axi_wr_underflow_i OR axi_rd_underflow_i;
END GENERATE grdwr_uf1;
grdwr_uf2: IF (C_HAS_AXI_WR_CHANNEL = 1 AND C_HAS_AXI_RD_CHANNEL = 0) GENERATE
UNDERFLOW <= axi_wr_underflow_i;
END GENERATE grdwr_uf2;
grdwr_uf3: IF (C_HAS_AXI_WR_CHANNEL = 0 AND C_HAS_AXI_RD_CHANNEL = 1) GENERATE
UNDERFLOW <= axi_rd_underflow_i;
END GENERATE grdwr_uf3;
END GENERATE gaxi_comm_uf;
gaxi_comm_of: IF (C_USE_COMMON_OVERFLOW = 1) GENERATE
grdwr_of1: IF (C_HAS_AXI_WR_CHANNEL = 1 AND C_HAS_AXI_RD_CHANNEL = 1) GENERATE
OVERFLOW <= axi_wr_overflow_i OR axi_rd_overflow_i;
END GENERATE grdwr_of1;
grdwr_of2: IF (C_HAS_AXI_WR_CHANNEL = 1 AND C_HAS_AXI_RD_CHANNEL = 0) GENERATE
OVERFLOW <= axi_wr_overflow_i;
END GENERATE grdwr_of2;
grdwr_of3: IF (C_HAS_AXI_WR_CHANNEL = 0 AND C_HAS_AXI_RD_CHANNEL = 1) GENERATE
OVERFLOW <= axi_rd_overflow_i;
END GENERATE grdwr_of3;
END GENERATE gaxi_comm_of;
END GENERATE gaxifull;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Pass Through Logic or Wiring Logic
---------------------------------------------------------------------------
---------------------------------------------------------------------------
---------------------------------------------------------------------------
gaxi_pass_through: IF (C_WACH_TYPE = 2 OR C_WDCH_TYPE = 2 OR C_WRCH_TYPE = 2 OR
C_RACH_TYPE = 2 OR C_RDCH_TYPE = 2 OR C_AXIS_TYPE = 2) GENERATE
gwach_pass_through: IF (C_WACH_TYPE = 2) GENERATE -- Wiring logic for Write Address Channel
M_AXI_AWID <= S_AXI_AWID;
M_AXI_AWADDR <= S_AXI_AWADDR;
M_AXI_AWLEN <= S_AXI_AWLEN;
M_AXI_AWSIZE <= S_AXI_AWSIZE;
M_AXI_AWBURST <= S_AXI_AWBURST;
M_AXI_AWLOCK <= S_AXI_AWLOCK;
M_AXI_AWCACHE <= S_AXI_AWCACHE;
M_AXI_AWPROT <= S_AXI_AWPROT;
M_AXI_AWQOS <= S_AXI_AWQOS;
M_AXI_AWREGION <= S_AXI_AWREGION;
M_AXI_AWUSER <= S_AXI_AWUSER;
S_AXI_AWREADY <= M_AXI_AWREADY;
M_AXI_AWVALID <= S_AXI_AWVALID;
END GENERATE gwach_pass_through;
-- Wiring logic for Write Data Channel
gwdch_pass_through: IF (C_WDCH_TYPE = 2) GENERATE
M_AXI_WID <= S_AXI_WID;
M_AXI_WDATA <= S_AXI_WDATA;
M_AXI_WSTRB <= S_AXI_WSTRB;
M_AXI_WLAST <= S_AXI_WLAST;
M_AXI_WUSER <= S_AXI_WUSER;
S_AXI_WREADY <= M_AXI_WREADY;
M_AXI_WVALID <= S_AXI_WVALID;
END GENERATE gwdch_pass_through;
-- Wiring logic for Write Response Channel
gwrch_pass_through: IF (C_WRCH_TYPE = 2) GENERATE
S_AXI_BID <= M_AXI_BID;
S_AXI_BRESP <= M_AXI_BRESP;
S_AXI_BUSER <= M_AXI_BUSER;
M_AXI_BREADY <= S_AXI_BREADY;
S_AXI_BVALID <= M_AXI_BVALID;
END GENERATE gwrch_pass_through;
-- Pass Through Logic for Read Channel
grach_pass_through: IF (C_RACH_TYPE = 2) GENERATE -- Wiring logic for Read Address Channel
M_AXI_ARID <= S_AXI_ARID;
M_AXI_ARADDR <= S_AXI_ARADDR;
M_AXI_ARLEN <= S_AXI_ARLEN;
M_AXI_ARSIZE <= S_AXI_ARSIZE;
M_AXI_ARBURST <= S_AXI_ARBURST;
M_AXI_ARLOCK <= S_AXI_ARLOCK;
M_AXI_ARCACHE <= S_AXI_ARCACHE;
M_AXI_ARPROT <= S_AXI_ARPROT;
M_AXI_ARQOS <= S_AXI_ARQOS;
M_AXI_ARREGION <= S_AXI_ARREGION;
M_AXI_ARUSER <= S_AXI_ARUSER;
S_AXI_ARREADY <= M_AXI_ARREADY;
M_AXI_ARVALID <= S_AXI_ARVALID;
END GENERATE grach_pass_through;
grdch_pass_through: IF (C_RDCH_TYPE = 2) GENERATE -- Wiring logic for Read Data Channel
S_AXI_RID <= M_AXI_RID;
S_AXI_RLAST <= M_AXI_RLAST;
S_AXI_RUSER <= M_AXI_RUSER;
S_AXI_RDATA <= M_AXI_RDATA;
S_AXI_RRESP <= M_AXI_RRESP;
S_AXI_RVALID <= M_AXI_RVALID;
M_AXI_RREADY <= S_AXI_RREADY;
END GENERATE grdch_pass_through;
gaxis_pass_through: IF (C_AXIS_TYPE = 2) GENERATE -- Wiring logic for AXI Streaming
M_AXIS_TDATA <= S_AXIS_TDATA;
M_AXIS_TSTRB <= S_AXIS_TSTRB;
M_AXIS_TKEEP <= S_AXIS_TKEEP;
M_AXIS_TID <= S_AXIS_TID;
M_AXIS_TDEST <= S_AXIS_TDEST;
M_AXIS_TUSER <= S_AXIS_TUSER;
M_AXIS_TLAST <= S_AXIS_TLAST;
S_AXIS_TREADY <= M_AXIS_TREADY;
M_AXIS_TVALID <= S_AXIS_TVALID;
END GENERATE gaxis_pass_through;
END GENERATE gaxi_pass_through;
END behavioral;
| mit | 1b2a83969121a32f3a540348744ba980 | 0.461521 | 3.843235 | false | false | false | false |
hubertokf/VHDL-Fast-Adders | CLAH/CLA2bits/8bits/CLAH8bits/CLAH8bits.vhd | 1 | 2,889 | LIBRARY Ieee;
USE ieee.std_logic_1164.all;
ENTITY CLAH8bits IS
PORT (
val1,val2: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CarryIn: IN STD_LOGIC;
CarryOut: OUT STD_LOGIC;
clk: IN STD_LOGIC;
rst: IN STD_LOGIC;
SomaResult:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END CLAH8bits;
ARCHITECTURE strc_CLAH8bits of CLAH8bits is
SIGNAL Cin_sig, Cout_sig: STD_LOGIC;
SIGNAL P0_sig, P1_sig, P2_sig, P3_sig: STD_LOGIC;
SIGNAL G0_sig, G1_sig, G2_sig, G3_sig: STD_LOGIC;
SIGNAL Cout1_temp_sig, Cout2_temp_sig, Cout3_temp_sig: STD_LOGIC;
SIGNAL A_sig, B_sig, Out_sig: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SomaT1,SomaT2,SomaT3,SomaT4:STD_LOGIC_VECTOR(1 DOWNTO 0);
Component CLA2bits
PORT (
val1,val2: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
SomaResult:OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
CarryIn: IN STD_LOGIC;
P, G: OUT STD_LOGIC
);
end component;
Component Reg1Bit
PORT (
valIn: in std_logic;
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic
);
end component;
Component Reg8Bit
PORT (
valIn: in std_logic_vector(7 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(7 downto 0)
);
end component;
Component CLGB
PORT (
P0, P1, G0, G1, Cin: IN STD_LOGIC;
Cout1, Cout2: OUT STD_LOGIC
);
end component;
BEGIN
--registradores--
Reg_CarryIn: Reg1Bit PORT MAP (
valIn=>CarryIn,
clk=>clk,
rst=>rst,
valOut=>Cin_sig
);
Reg_A: Reg8Bit PORT MAP (
valIn=>val1,
clk=>clk,
rst=>rst,
valOut=>A_sig
);
Reg_B: Reg8Bit PORT MAP (
valIn=>val2,
clk=>clk,
rst=>rst,
valOut=>B_sig
);
Reg_CarryOut: Reg1Bit PORT MAP (
valIn=>Cout_sig,
clk=>clk,
rst=>rst,
valOut=>CarryOut
);
Reg_Ssoma: Reg8Bit PORT MAP (
valIn=>Out_sig,
clk=>clk,
rst=>rst,
valOut=>SomaResult
);
Som1: CLA2bits PORT MAP(
val1(1 DOWNTO 0) => A_sig(1 DOWNTO 0),
val2(1 DOWNTO 0) => B_sig(1 DOWNTO 0),
CarryIn=>Cin_sig,
P=>P0_sig,
G=>G0_sig,
SomaResult=>SomaT1
);
CLGB1: CLGB PORT MAP(
P0=>P0_sig,
G0=>G0_sig,
P1=>P1_sig,
G1=>G1_sig,
Cin=>Cin_sig,
Cout1=>Cout1_temp_sig,
Cout2=>Cout2_temp_sig
);
Som2: CLA2bits PORT MAP(
val1(1 DOWNTO 0) => A_sig(3 DOWNTO 2),
val2(1 DOWNTO 0) => B_sig(3 DOWNTO 2),
CarryIn=>Cout1_temp_sig,
P=>P1_sig,
G=>G1_sig,
SomaResult=>SomaT2
);
Som3: CLA2bits PORT MAP(
val1(1 DOWNTO 0) => A_sig(5 DOWNTO 4),
val2(1 DOWNTO 0) => B_sig(5 DOWNTO 4),
CarryIn=>Cout2_temp_sig,
P=>P2_sig,
G=>G2_sig,
SomaResult=>SomaT3
);
CLGB2: CLGB PORT MAP(
P0=>P2_sig,
G0=>G2_sig,
P1=>P3_sig,
G1=>G3_sig,
Cin=>Cout2_temp_sig,
Cout1=>Cout3_temp_sig,
Cout2=>Cout_sig
);
Som4: CLA2bits PORT MAP(
val1(1 DOWNTO 0) => A_sig(7 DOWNTO 6),
val2(1 DOWNTO 0) => B_sig(7 DOWNTO 6),
CarryIn=>Cout3_temp_sig,
P=>P3_sig,
G=>G3_sig,
SomaResult=>SomaT4
);
Out_sig <= SomaT4 & SomaT3 & SomaT2 & SomaT1;
END strc_CLAH8bits; | mit | 40472caae7222298ac7b28facaefbb70 | 0.641052 | 2.322347 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug040/p_jinfo_comps_info_id.vhd | 2 | 1,485 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity p_jinfo_comps_info_id is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
wa0_en : in std_logic
);
end p_jinfo_comps_info_id;
architecture augh of p_jinfo_comps_info_id is
-- Embedded RAM
type ram_type is array (0 to 2) of std_logic_vector(7 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 3 else (others => '-');
end architecture;
| gpl-2.0 | 32ab09c3ab2cfc064c63558a56e9837b | 0.670707 | 2.861272 | false | false | false | false |
nickg/nvc | test/regress/func21.vhd | 1 | 489 | entity func21 is
end entity;
architecture test of func21 is
type rec is record
x, y : integer;
end record;
function func (r : rec) return integer is
begin
return r.x + r.y;
end function;
begin
p1: process is
variable a, b : integer;
begin
assert func(r.x => 1, r.y => 2) = 3;
a := 4;
b := 5;
wait for 1 ns;
assert func(r.x => a, r.y => b) = 9;
wait;
end process;
end architecture;
| gpl-3.0 | f2abad25e03acebb96994edd16ce5aeb | 0.519427 | 3.395833 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_20.vhd | 3 | 4,325 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_20.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
library ieee; use ieee.std_logic_1164.all;
entity control_section is
end entity control_section;
-- end not in book
architecture structural of control_section is
component reg is
generic ( width : positive );
port ( clk : in std_logic;
d : in std_logic_vector(0 to width - 1);
q : out std_logic_vector(0 to width - 1) );
end component reg;
for flag_reg : reg
use entity work.reg(gate_level)
-- workaround for MTI bug mt023
-- reverted for ghdl
port map ( clock => clk, data_in => d, data_out => q );
-- port map ( clock => clk, data_in => d, data_out => q, reset_n => '1' );
-- end workaround
-- . . .
-- not in book
signal clock_phase1, zero_result, neg_result, overflow_result,
zero_flag, neg_flag, overflow_flag : std_logic;
-- end not in book
begin
flag_reg : component reg
generic map ( width => 3 )
port map ( clk => clock_phase1,
d(0) => zero_result, d(1) => neg_result,
d(2) => overflow_result,
q(0) => zero_flag, q(1) => neg_flag,
q(2) => overflow_flag );
-- . . .
-- not in book
stimulus : process is
begin
clock_phase1 <= '0';
zero_result <= '0'; neg_result <= '0'; overflow_result <= '0'; wait for 10 ns;
clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns;
zero_result <= '0'; neg_result <= '0'; overflow_result <= '1'; wait for 10 ns;
clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns;
zero_result <= '0'; neg_result <= '1'; overflow_result <= '0'; wait for 10 ns;
clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns;
zero_result <= '0'; neg_result <= '1'; overflow_result <= '1'; wait for 10 ns;
clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns;
zero_result <= '1'; neg_result <= '0'; overflow_result <= '0'; wait for 10 ns;
clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns;
zero_result <= '1'; neg_result <= '0'; overflow_result <= '1'; wait for 10 ns;
clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns;
zero_result <= '1'; neg_result <= '1'; overflow_result <= '0'; wait for 10 ns;
clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns;
zero_result <= '1'; neg_result <= '1'; overflow_result <= '1'; wait for 10 ns;
clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns;
wait;
end process stimulus;
-- end not in book
end architecture structural;
| gpl-2.0 | c981aa08e29f279731cc5a3e7660f142 | 0.468671 | 4.282178 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1288/issue.vhdl | 1 | 1,522 | library ieee;
use ieee.std_logic_1164.all;
entity sequencer is
generic (
seq : string
);
port (
clk : in std_logic;
data : out std_logic
);
end entity sequencer;
architecture rtl of sequencer is
signal index : natural := seq'low;
signal ch : character;
function to_bit (a : in character) return std_logic is
variable ret : std_logic;
begin
case a is
when '0' | '_' => ret := '0';
when '1' | '-' => ret := '1';
when others => ret := 'X';
end case;
return ret;
end function to_bit;
begin
process (clk) is
begin
if rising_edge(clk) then
if (index < seq'high) then
index <= index + 1;
end if;
end if;
end process;
ch <= seq(index);
data <= to_bit(ch);
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
entity issue is
port (
clk : in std_logic
);
end entity issue;
architecture psl of issue is
component sequencer is
generic (
seq : string
);
port (
clk : in std_logic;
data : out std_logic
);
end component sequencer;
signal a, b : std_logic;
begin
-- 01234567890
SEQ_A : sequencer generic map ("__-_-______") port map (clk, a);
SEQ_B : sequencer generic map ("_____-_-___") port map (clk, b);
-- All is sensitive to rising edge of clk
default clock is rising_edge(clk);
-- This assertion holds
NEXT_EVENT_a : assert always (a -> next_e[3 to 5] (b));
end architecture psl; | gpl-2.0 | 751ebbfc018550669769082ca4bc2a0f | 0.569645 | 3.523148 | false | false | false | false |
nickg/nvc | test/regress/vests26.vhd | 1 | 10,191 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc992.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
PACKAGE c06s03b00x00p08n01i00992pkg IS
--
-- This packages contains declarations of User attributes
--
-- ----------------------------------------------------------------------
--
TYPE RESISTANCE IS RANGE 0 TO 1E9
UNITS
pf;
nf = 1000 pf;
mf = 1000 nf;
END UNITS;
TYPE t_logic IS (
U, D,
Z0, Z1, ZDX, DZX, ZX,
W0, W1, WZ0, WZ1, WDX, DWX, WZX, ZWX, WX,
R0, R1, RW0, RW1, RZ0, RZ1, RDX, DRX, RZX, ZRX, RWX, WRX, RX,
F0, F1, FR0, FR1, FW0, FW1, FZ0, FZ1, FDX, DFX, FZX, ZFX, FWX, WFX, FRX, RFX, FX
);
--
-- Scalar types Declarations
--
SUBTYPE st_scl1 IS BOOLEAN;
SUBTYPE st_scl2 IS BIT;
SUBTYPE st_scl3 IS CHARACTER;
SUBTYPE st_scl4 IS INTEGER;
SUBTYPE st_scl5 IS REAL;
SUBTYPE st_scl6 IS TIME;
SUBTYPE st_scl7 IS RESISTANCE;
SUBTYPE st_scl8 IS t_logic;
--
-- character string types
--
SUBTYPE st_str1 IS STRING;
SUBTYPE st_str2 IS STRING (1 TO 4);
--
-- Scalar types with a range constraint
--
SUBTYPE cst_scl1 IS BOOLEAN RANGE TRUE TO TRUE;
SUBTYPE cst_scl2 IS BIT RANGE '0' TO '0';
SUBTYPE cst_scl3 IS CHARACTER RANGE 'a' TO 'z';
SUBTYPE cst_scl4 IS INTEGER RANGE 10 DOWNTO 0;
SUBTYPE cst_scl5 IS REAL RANGE 0.0 TO 10.0;
SUBTYPE cst_scl6 IS TIME RANGE 0 fs TO 10 ns;
SUBTYPE cst_scl7 IS RESISTANCE RANGE 0 pf TO 10000 pf;
SUBTYPE cst_scl8 IS t_logic RANGE F0 TO FX;
-- -----------------------------------------------------------------------------------------
-- Attribute Declarations
-- -----------------------------------------------------------------------------------------
--
ATTRIBUTE atr_scl1 : st_scl1;
ATTRIBUTE atr_scl2 : st_scl2;
ATTRIBUTE atr_scl3 : st_scl3;
ATTRIBUTE atr_scl4 : st_scl4;
ATTRIBUTE atr_scl5 : st_scl5;
ATTRIBUTE atr_scl6 : st_scl6;
ATTRIBUTE atr_scl7 : st_scl7;
ATTRIBUTE atr_scl8 : st_scl8;
ATTRIBUTE atr_str1 : st_str1;
ATTRIBUTE atr_str2 : st_str2;
ATTRIBUTE cat_scl1 : cst_scl1;
ATTRIBUTE cat_scl2 : cst_scl2;
ATTRIBUTE cat_scl3 : cst_scl3;
ATTRIBUTE cat_scl4 : cst_scl4;
ATTRIBUTE cat_scl5 : cst_scl5;
ATTRIBUTE cat_scl6 : cst_scl6;
ATTRIBUTE cat_scl7 : cst_scl7;
ATTRIBUTE cat_scl8 : cst_scl8;
-- =========================================================================================
--
-- Apply attributes to the package
--
ATTRIBUTE atr_scl1 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS TRUE;
ATTRIBUTE atr_scl2 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS '0';
ATTRIBUTE atr_scl3 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS 'z';
ATTRIBUTE atr_scl4 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS 0;
ATTRIBUTE atr_scl5 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS 10.0;
ATTRIBUTE atr_scl6 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS 10 ns;
ATTRIBUTE atr_scl7 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS 10000 pf;
ATTRIBUTE atr_scl8 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS FX;
ATTRIBUTE atr_str1 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS "packit";
ATTRIBUTE atr_str2 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS "pack";
ATTRIBUTE cat_scl1 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS TRUE;
ATTRIBUTE cat_scl2 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS '0';
ATTRIBUTE cat_scl3 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS 'z';
ATTRIBUTE cat_scl4 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS 0;
ATTRIBUTE cat_scl5 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS 10.0;
ATTRIBUTE cat_scl6 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS 10 ns;
ATTRIBUTE cat_scl7 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS 10000 pf;
ATTRIBUTE cat_scl8 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS FX;
--
END;
use work.all;
use c06s03b00x00p08n01i00992pkg.all;
ENTITY vests26 IS
END vests26;
ARCHITECTURE c06s03b00x00p08n01i00992arch OF vests26 IS
BEGIN
TESTING: PROCESS
BEGIN
ASSERT c06s03b00x00p08n01i00992pkg'atr_scl1 = TRUE
REPORT "ERROR: Wrong value for 'atr_scl1" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00992pkg'atr_scl2 = '0'
REPORT "ERROR: Wrong value for 'atr_scl2" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00992pkg'atr_scl3 = 'z'
REPORT "ERROR: Wrong value for 'atr_scl3" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00992pkg'atr_scl4 = 0
REPORT "ERROR: Wrong value for 'atr_scl4" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00992pkg'atr_scl5 = 10.0
REPORT "ERROR: Wrong value for 'atr_scl5" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00992pkg'atr_scl6 = 10 ns
REPORT "ERROR: Wrong value for 'atr_scl6" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00992pkg'atr_scl7 = 10000 pf
REPORT "ERROR: Wrong value for 'atr_scl7" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00992pkg'atr_scl8 = FX
REPORT "ERROR: Wrong value for 'atr_scl8" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00992pkg'atr_str1 = "packit"
REPORT "ERROR: Wrong value for 'atr_str1" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00992pkg'atr_str2 = "pack"
REPORT "ERROR: Wrong value for 'atr_str2" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00992pkg'cat_scl1 = TRUE
REPORT "ERROR: Wrong value for 'cat_scl1" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00992pkg'cat_scl2 = '0'
REPORT "ERROR: Wrong value for 'cat_scl2" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00992pkg'cat_scl3 = 'z'
REPORT "ERROR: Wrong value for 'cat_scl3" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00992pkg'cat_scl4 = 0
REPORT "ERROR: Wrong value for 'cat_scl4" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00992pkg'cat_scl5 = 10.0
REPORT "ERROR: Wrong value for 'cat_scl5" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00992pkg'cat_scl6 = 10 ns
REPORT "ERROR: Wrong value for 'cat_scl6" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00992pkg'cat_scl7 = 10000 pf
REPORT "ERROR: Wrong value for 'cat_scl7" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00992pkg'cat_scl8 = FX
REPORT "ERROR: Wrong value for 'cat_scl8" SEVERITY FAILURE;
assert NOT( c06s03b00x00p08n01i00992pkg'atr_scl1 = TRUE
and c06s03b00x00p08n01i00992pkg'atr_scl2 = '0'
and c06s03b00x00p08n01i00992pkg'atr_scl3 = 'z'
and c06s03b00x00p08n01i00992pkg'atr_scl4 = 0
and c06s03b00x00p08n01i00992pkg'atr_scl5 = 10.0
and c06s03b00x00p08n01i00992pkg'atr_scl6 = 10 ns
and c06s03b00x00p08n01i00992pkg'atr_scl7 = 10000 pf
and c06s03b00x00p08n01i00992pkg'atr_scl8 = FX
and c06s03b00x00p08n01i00992pkg'atr_str1 = "packit"
and c06s03b00x00p08n01i00992pkg'atr_str2 = "pack"
and c06s03b00x00p08n01i00992pkg'cat_scl1 = TRUE
and c06s03b00x00p08n01i00992pkg'cat_scl2 = '0'
and c06s03b00x00p08n01i00992pkg'cat_scl3 = 'z'
and c06s03b00x00p08n01i00992pkg'cat_scl4 = 0
and c06s03b00x00p08n01i00992pkg'cat_scl5 = 10.0
and c06s03b00x00p08n01i00992pkg'cat_scl6 = 10 ns
and c06s03b00x00p08n01i00992pkg'cat_scl7 = 10000 pf
and c06s03b00x00p08n01i00992pkg'cat_scl8 = FX)
report "***PASSED TEST: c06s03b00x00p08n01i00992"
severity NOTE;
assert ( c06s03b00x00p08n01i00992pkg'atr_scl1 = TRUE
and c06s03b00x00p08n01i00992pkg'atr_scl2 = '0'
and c06s03b00x00p08n01i00992pkg'atr_scl3 = 'z'
and c06s03b00x00p08n01i00992pkg'atr_scl4 = 0
and c06s03b00x00p08n01i00992pkg'atr_scl5 = 10.0
and c06s03b00x00p08n01i00992pkg'atr_scl6 = 10 ns
and c06s03b00x00p08n01i00992pkg'atr_scl7 = 10000 pf
and c06s03b00x00p08n01i00992pkg'atr_scl8 = FX
and c06s03b00x00p08n01i00992pkg'atr_str1 = "packit"
and c06s03b00x00p08n01i00992pkg'atr_str2 = "pack"
and c06s03b00x00p08n01i00992pkg'cat_scl1 = TRUE
and c06s03b00x00p08n01i00992pkg'cat_scl2 = '0'
and c06s03b00x00p08n01i00992pkg'cat_scl3 = 'z'
and c06s03b00x00p08n01i00992pkg'cat_scl4 = 0
and c06s03b00x00p08n01i00992pkg'cat_scl5 = 10.0
and c06s03b00x00p08n01i00992pkg'cat_scl6 = 10 ns
and c06s03b00x00p08n01i00992pkg'cat_scl7 = 10000 pf
and c06s03b00x00p08n01i00992pkg'cat_scl8 = FX)
report "***FAILED TEST: c06s03b00x00p08n01i00992 - Expanded name denotes a primary unit contained in design library test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p08n01i00992arch;
| gpl-3.0 | 2ae922235d06b56a8244b1e1b80824aa | 0.63772 | 2.986811 | false | false | false | false |
nickg/nvc | test/parse/protected.vhd | 1 | 1,111 | package p is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
end protected SharedCounter;
type SharedCounter is protected body
variable counter: Integer := 0;
procedure increment (N: Integer := 1) is
begin
counter := counter + N;
end procedure increment;
procedure decrement (N: Integer := 1) is
begin
counter := counter - N;
end procedure decrement;
impure function value return Integer is
begin
return counter;
end function value;
procedure add10 is
begin
increment(10);
end procedure;
end protected body;
procedure proc_1 (x : integer);
type pt2 is protected
procedure proc_1 (y : integer);
end protected;
type pt2 is protected body
procedure proc_2 is
begin
proc_1(y => 5); -- OK
end procedure;
end protected body;
end package;
| gpl-3.0 | 2e88aec13bbf10a93c8606014bda5e3c | 0.572457 | 5.167442 | false | false | false | false |
snow4life/PipelinedDLX | synthesis/DLX_synth_opt.vhdl | 1 | 810,206 |
library IEEE;
use IEEE.std_logic_1164.all;
package CONV_PACK_DLX is
-- define attributes
attribute ENUM_ENCODING : STRING;
end CONV_PACK_DLX;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity SNPS_CLOCK_GATE_HIGH_DLX_0 is
port( CLK, EN : in std_logic; ENCLK : out std_logic; TE : in std_logic);
end SNPS_CLOCK_GATE_HIGH_DLX_0;
architecture SYN_USE_DEFA_ARCH_NAME of SNPS_CLOCK_GATE_HIGH_DLX_0 is
component TLATNTSCAX2
port( E, SE, CK : in std_logic; ECK : out std_logic);
end component;
begin
latch : TLATNTSCAX2 port map( E => EN, SE => TE, CK => CLK, ECK => ENCLK);
end SYN_USE_DEFA_ARCH_NAME;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity DLX is
port( CLOCK, RESET : in std_logic; PORT_PC : out std_logic_vector (31
downto 0); PORT_INSTR_IRAM : in std_logic_vector (31 downto 0);
PORT_REGB, PORT_ALU : out std_logic_vector (31 downto 0);
PORT_DATA_RAM : in std_logic_vector (31 downto 0); PORT_SIZE : out
std_logic_vector (1 downto 0); PORT_R_W, PORT_EN, RF_ENABLE, RF_RD1,
RF_RD2, RF_WR : out std_logic; RF_ADD_WR, RF_ADD_RD1, RF_ADD_RD2 :
out std_logic_vector (4 downto 0); RF_DATAIN : out std_logic_vector
(31 downto 0); RF_OUT1, RF_OUT2 : in std_logic_vector (31 downto 0));
end DLX;
architecture SYN_RTL of DLX is
component INVXL
port( A : in std_logic; Y : out std_logic);
end component;
component OR3XL
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component XOR2XL
port( A, B : in std_logic; Y : out std_logic);
end component;
component OAI31XL
port( A0, A1, A2, B0 : in std_logic; Y : out std_logic);
end component;
component AOI22XL
port( A0, A1, B0, B1 : in std_logic; Y : out std_logic);
end component;
component NAND3BXL
port( AN, B, C : in std_logic; Y : out std_logic);
end component;
component AO21XL
port( A0, A1, B0 : in std_logic; Y : out std_logic);
end component;
component OAI21XL
port( A0, A1, B0 : in std_logic; Y : out std_logic);
end component;
component AND3XL
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component NOR4XL
port( A, B, C, D : in std_logic; Y : out std_logic);
end component;
component OA21XL
port( A0, A1, B0 : in std_logic; Y : out std_logic);
end component;
component AOI31XL
port( A0, A1, A2, B0 : in std_logic; Y : out std_logic);
end component;
component AOI21XL
port( A0, A1, B0 : in std_logic; Y : out std_logic);
end component;
component OAI211XL
port( A0, A1, B0, C0 : in std_logic; Y : out std_logic);
end component;
component XNOR2XL
port( A, B : in std_logic; Y : out std_logic);
end component;
component NAND3XL
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component NOR3XL
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component OAI2BB1XL
port( A0N, A1N, B0 : in std_logic; Y : out std_logic);
end component;
component NAND2XL
port( A, B : in std_logic; Y : out std_logic);
end component;
component NOR2XL
port( A, B : in std_logic; Y : out std_logic);
end component;
component OAI33XL
port( A0, A1, A2, B0, B1, B2 : in std_logic; Y : out std_logic);
end component;
component OAI2B11XL
port( A1N, A0, B0, C0 : in std_logic; Y : out std_logic);
end component;
component AOI211XL
port( A0, A1, B0, C0 : in std_logic; Y : out std_logic);
end component;
component AND4XL
port( A, B, C, D : in std_logic; Y : out std_logic);
end component;
component AO22XL
port( A0, A1, B0, B1 : in std_logic; Y : out std_logic);
end component;
component NOR3BXL
port( AN, B, C : in std_logic; Y : out std_logic);
end component;
component AOI2BB1XL
port( A0N, A1N, B0 : in std_logic; Y : out std_logic);
end component;
component AOI32XL
port( A0, A1, A2, B0, B1 : in std_logic; Y : out std_logic);
end component;
component OAI2B2XL
port( A1N, A0, B0, B1 : in std_logic; Y : out std_logic);
end component;
component OAI221XL
port( A0, A1, B0, B1, C0 : in std_logic; Y : out std_logic);
end component;
component OAI32XL
port( A0, A1, A2, B0, B1 : in std_logic; Y : out std_logic);
end component;
component CLKINVX1
port( A : in std_logic; Y : out std_logic);
end component;
component AND2XL
port( A, B : in std_logic; Y : out std_logic);
end component;
component NAND2BXL
port( AN, B : in std_logic; Y : out std_logic);
end component;
component NOR2BXL
port( AN, B : in std_logic; Y : out std_logic);
end component;
component OR4XL
port( A, B, C, D : in std_logic; Y : out std_logic);
end component;
component NAND4XL
port( A, B, C, D : in std_logic; Y : out std_logic);
end component;
component AOI33XL
port( A0, A1, A2, B0, B1, B2 : in std_logic; Y : out std_logic);
end component;
component AOI2B1XL
port( A1N, A0, B0 : in std_logic; Y : out std_logic);
end component;
component OAI22XL
port( A0, A1, B0, B1 : in std_logic; Y : out std_logic);
end component;
component AOI222XL
port( A0, A1, B0, B1, C0, C1 : in std_logic; Y : out std_logic);
end component;
component OR2XL
port( A, B : in std_logic; Y : out std_logic);
end component;
component BUFX2
port( A : in std_logic; Y : out std_logic);
end component;
component CLKBUFX1
port( A : in std_logic; Y : out std_logic);
end component;
component CLKBUFX3
port( A : in std_logic; Y : out std_logic);
end component;
component OAI2BB2XL
port( B0, B1, A0N, A1N : in std_logic; Y : out std_logic);
end component;
component MXI2XL
port( A, B, S0 : in std_logic; Y : out std_logic);
end component;
component AOI221XL
port( A0, A1, B0, B1, C0 : in std_logic; Y : out std_logic);
end component;
component OAI222XL
port( A0, A1, B0, B1, C0, C1 : in std_logic; Y : out std_logic);
end component;
component CLKINVX2
port( A : in std_logic; Y : out std_logic);
end component;
component AO2B2XL
port( B0, B1, A0, A1N : in std_logic; Y : out std_logic);
end component;
component CLKBUFX2
port( A : in std_logic; Y : out std_logic);
end component;
component XNOR3XL
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component INVX4
port( A : in std_logic; Y : out std_logic);
end component;
component OAI222X2
port( A0, A1, B0, B1, C0, C1 : in std_logic; Y : out std_logic);
end component;
component AOI21BXL
port( A0, A1, B0N : in std_logic; Y : out std_logic);
end component;
component XOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component AO22X1
port( A0, A1, B0, B1 : in std_logic; Y : out std_logic);
end component;
component AND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component INVX1
port( A : in std_logic; Y : out std_logic);
end component;
component AND4X1
port( A, B, C, D : in std_logic; Y : out std_logic);
end component;
component NAND3X1
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component INVX2
port( A : in std_logic; Y : out std_logic);
end component;
component CLKNAND2X4
port( A, B : in std_logic; Y : out std_logic);
end component;
component OAI222X1
port( A0, A1, B0, B1, C0, C1 : in std_logic; Y : out std_logic);
end component;
component INVX3
port( A : in std_logic; Y : out std_logic);
end component;
component ADDFHXL
port( A, B, CI : in std_logic; CO, S : out std_logic);
end component;
component ADDFHX1
port( A, B, CI : in std_logic; CO, S : out std_logic);
end component;
component ADDFXL
port( A, B, CI : in std_logic; CO, S : out std_logic);
end component;
component EDFFXL
port( D, E, CK : in std_logic; Q, QN : out std_logic);
end component;
component EDFFTRXL
port( RN, D, E, CK : in std_logic; Q, QN : out std_logic);
end component;
component DFFRQXL
port( D, CK, RN : in std_logic; Q : out std_logic);
end component;
component SNPS_CLOCK_GATE_HIGH_DLX_0
port( CLK, EN : in std_logic; ENCLK : out std_logic; TE : in std_logic
);
end component;
component XOR3XL
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component MX2XL
port( A, B, S0 : in std_logic; Y : out std_logic);
end component;
component TLATXL
port( G, D : in std_logic; Q, QN : out std_logic);
end component;
signal X_Logic1_port, PORT_PC_31_port, PORT_PC_30_port, PORT_PC_29_port,
PORT_PC_28_port, PORT_PC_27_port, PORT_PC_26_port, PORT_PC_25_port,
PORT_PC_24_port, PORT_PC_23_port, PORT_PC_22_port, PORT_PC_21_port,
PORT_PC_20_port, PORT_PC_19_port, PORT_PC_18_port, PORT_PC_17_port,
PORT_PC_16_port, PORT_PC_15_port, PORT_PC_14_port, PORT_PC_13_port,
PORT_PC_12_port, PORT_PC_11_port, PORT_PC_10_port, PORT_PC_9_port,
PORT_PC_8_port, PORT_PC_7_port, PORT_PC_6_port, PORT_PC_5_port,
PORT_PC_4_port, PORT_PC_3_port, PORT_PC_2_port, PORT_ALU_31_port,
PORT_ALU_30_port, PORT_ALU_29_port, PORT_ALU_28_port, PORT_ALU_27_port,
PORT_ALU_26_port, PORT_ALU_25_port, PORT_ALU_24_port, PORT_ALU_23_port,
PORT_ALU_22_port, PORT_ALU_21_port, PORT_ALU_20_port, PORT_ALU_19_port,
PORT_ALU_18_port, PORT_ALU_17_port, PORT_ALU_16_port, PORT_ALU_15_port,
PORT_ALU_14_port, PORT_ALU_13_port, PORT_ALU_12_port, PORT_ALU_11_port,
PORT_ALU_10_port, PORT_ALU_9_port, PORT_ALU_8_port, PORT_ALU_7_port,
PORT_ALU_6_port, PORT_ALU_5_port, PORT_ALU_4_port, PORT_ALU_3_port,
PORT_ALU_2_port, PORT_ALU_1_port, PORT_ALU_0_port, PORT_R_W_port,
RF_WR_port, RF_ADD_WR_4_port, RF_ADD_WR_3_port, RF_ADD_WR_2_port,
RF_ADD_WR_1_port, RF_ADD_WR_0_port, RF_ADD_RD1_4_port, RF_ADD_RD1_3_port,
RF_ADD_RD1_2_port, RF_ADD_RD1_1_port, RF_ADD_RD1_0_port,
RF_ADD_RD2_4_port, RF_ADD_RD2_3_port, RF_ADD_RD2_2_port,
RF_ADD_RD2_1_port, RF_ADD_RD2_0_port, EX_ALU_B_31_port, EX_ALU_SEL_1_port
, EX_ALU_SEL_0_port, EX_COMPARATOR_CW_5_port, EX_COMPARATOR_CW_4_port,
EX_COMPARATOR_CW_3_port, EX_COMPARATOR_CW_2_port, EX_COMPARATOR_CW_1_port
, EX_COMPARATOR_CW_0_port, EX_LOGIC_CW_3_port, EX_LOGIC_CW_2_port,
EX_SHIFTER_CW_1_port, EX_SHIFTER_CW_0_port, EX_ADD_SUB,
EX_ALU_OUT_31_port, EX_ALU_OUT_30_port, EX_ALU_OUT_29_port,
EX_ALU_OUT_28_port, EX_ALU_OUT_27_port, EX_ALU_OUT_26_port,
EX_ALU_OUT_25_port, EX_ALU_OUT_24_port, EX_ALU_OUT_23_port,
EX_ALU_OUT_22_port, EX_ALU_OUT_21_port, EX_ALU_OUT_20_port,
EX_ALU_OUT_19_port, EX_ALU_OUT_18_port, EX_ALU_OUT_17_port,
EX_ALU_OUT_16_port, EX_ALU_OUT_15_port, EX_ALU_OUT_14_port,
EX_ALU_OUT_13_port, EX_ALU_OUT_12_port, EX_ALU_OUT_11_port,
EX_ALU_OUT_10_port, EX_ALU_OUT_9_port, EX_ALU_OUT_8_port,
EX_ALU_OUT_7_port, EX_ALU_OUT_6_port, EX_ALU_OUT_5_port,
EX_ALU_OUT_4_port, EX_ALU_OUT_3_port, EX_ALU_OUT_2_port,
EX_ALU_OUT_1_port, EX_ALU_OUT_0_port, EX_MULT_OUT_31_port,
EX_MULT_OUT_30_port, EX_MULT_OUT_29_port, EX_MULT_OUT_28_port,
EX_MULT_OUT_27_port, EX_MULT_OUT_26_port, EX_MULT_OUT_25_port,
EX_MULT_OUT_24_port, EX_MULT_OUT_23_port, EX_MULT_OUT_22_port,
EX_MULT_OUT_21_port, EX_MULT_OUT_20_port, EX_MULT_OUT_19_port,
EX_MULT_OUT_18_port, EX_MULT_OUT_17_port, EX_MULT_OUT_16_port,
EX_MULT_OUT_15_port, EX_MULT_OUT_14_port, EX_MULT_OUT_13_port,
EX_MULT_OUT_12_port, EX_MULT_OUT_11_port, EX_MULT_OUT_10_port,
EX_MULT_OUT_9_port, EX_MULT_OUT_8_port, EX_MULT_OUT_7_port,
EX_MULT_OUT_6_port, EX_MULT_OUT_5_port, EX_MULT_OUT_4_port,
EX_MULT_OUT_3_port, EX_MULT_OUT_1_port, ID_SIGN_EXT_CONTROL,
ID_IMM16_EXT_31_port, ID_IMM16_SHL2_31_port, ID_IMM16_SHL2_16_port,
ID_IMM16_SHL2_15_port, ID_IMM16_SHL2_14_port, ID_IMM16_SHL2_13_port,
ID_IMM16_SHL2_12_port, ID_IMM16_SHL2_11_port, ID_IMM16_SHL2_10_port,
ID_IMM16_SHL2_9_port, ID_IMM16_SHL2_8_port, ID_IMM16_SHL2_7_port,
ID_IMM16_SHL2_6_port, ID_IMM16_SHL2_5_port, ID_IMM16_SHL2_4_port,
ID_IMM16_SHL2_3_port, ID_IMM16_SHL2_2_port, WB_SIGN_EXT_16_CONTROL,
WB_DATA_EXT_16_31_port, WB_DATA_EXT_16_30_port, WB_DATA_EXT_16_29_port,
WB_DATA_EXT_16_28_port, WB_DATA_EXT_16_27_port, WB_DATA_EXT_16_26_port,
WB_DATA_EXT_16_25_port, WB_DATA_EXT_16_24_port, WB_DATA_EXT_16_23_port,
WB_DATA_EXT_16_22_port, WB_DATA_EXT_16_21_port, WB_DATA_EXT_16_20_port,
WB_DATA_EXT_16_19_port, WB_DATA_EXT_16_18_port, WB_DATA_EXT_16_17_port,
WB_DATA_EXT_16_16_port, WB_DATA_EXT_16_15_port, WB_DATA_EXT_16_14_port,
WB_DATA_EXT_16_13_port, WB_DATA_EXT_16_12_port, WB_DATA_EXT_16_11_port,
WB_DATA_EXT_16_10_port, WB_DATA_EXT_16_9_port, WB_DATA_EXT_16_8_port,
WB_DATA_EXT_16_7_port, WB_DATA_EXT_16_6_port, WB_DATA_EXT_16_5_port,
WB_DATA_EXT_16_4_port, WB_DATA_EXT_16_3_port, WB_DATA_EXT_16_2_port,
WB_DATA_EXT_16_1_port, WB_DATA_EXT_16_0_port, WB_DATA_EXT_8_9_port,
WB_DATA_EXT_8_6_port, WB_DATA_EXT_8_5_port, WB_DATA_EXT_8_4_port,
WB_DATA_EXT_8_3_port, WB_DATA_EXT_8_2_port, WB_DATA_EXT_8_1_port,
WB_DATA_EXT_8_0_port, ID_REGA_ZERO, IF_STALL_SEL, IF_PC_INC_31_port,
IF_PC_INC_30_port, IF_PC_INC_29_port, IF_PC_INC_28_port,
IF_PC_INC_27_port, IF_PC_INC_26_port, IF_PC_INC_25_port,
IF_PC_INC_24_port, IF_PC_INC_23_port, IF_PC_INC_22_port,
IF_PC_INC_21_port, IF_PC_INC_20_port, IF_PC_INC_19_port,
IF_PC_INC_18_port, IF_PC_INC_17_port, IF_PC_INC_16_port,
IF_PC_INC_15_port, IF_PC_INC_14_port, IF_PC_INC_13_port,
IF_PC_INC_12_port, IF_PC_INC_11_port, IF_PC_INC_10_port, IF_PC_INC_9_port
, IF_PC_INC_8_port, IF_PC_INC_7_port, IF_PC_INC_6_port, IF_PC_INC_5_port,
IF_PC_INC_4_port, IF_PC_INC_3_port, IF_PC_INC_2_port, IF_PC_INC_1_port,
IF_PC_INC_0_port, ID_INSTR_31, ID_INSTR_30, ID_INSTR_29, ID_INSTR_28,
ID_INSTR_27, ID_INSTR_26, ID_PC_31_port, ID_PC_30_port, ID_PC_29_port,
ID_PC_28_port, ID_PC_27_port, ID_PC_26_port, ID_PC_25_port, ID_PC_24_port
, ID_PC_23_port, ID_PC_22_port, ID_PC_21_port, ID_PC_20_port,
ID_PC_19_port, ID_PC_18_port, ID_PC_17_port, ID_PC_16_port, ID_PC_15_port
, ID_PC_14_port, ID_PC_13_port, ID_PC_12_port, ID_PC_11_port,
ID_PC_10_port, ID_PC_9_port, ID_PC_8_port, ID_PC_7_port, ID_PC_6_port,
ID_PC_5_port, ID_PC_4_port, ID_PC_3_port, ID_PC_2_port, EX_REGA_31_port,
EX_REGA_30_port, EX_REGA_29_port, EX_REGA_28_port, EX_REGA_27_port,
EX_REGA_26_port, EX_REGA_25_port, EX_REGA_24_port, EX_REGA_23_port,
EX_REGA_22_port, EX_REGA_21_port, EX_REGA_20_port, EX_REGA_19_port,
EX_REGA_18_port, EX_REGA_17_port, EX_REGA_16_port, EX_REGA_15_port,
EX_REGA_14_port, EX_REGA_13_port, EX_REGA_12_port, EX_REGA_11_port,
EX_REGA_10_port, EX_REGA_9_port, EX_REGA_8_port, EX_REGA_7_port,
EX_REGA_6_port, EX_REGA_5_port, EX_REGA_4_port, EX_REGA_3_port,
EX_REGA_2_port, EX_REGA_1_port, EX_REGA_0_port, EX_REGB_31_port,
EX_REGB_30_port, EX_REGB_29_port, EX_REGB_28_port, EX_REGB_27_port,
EX_REGB_26_port, EX_REGB_25_port, EX_REGB_24_port, EX_REGB_23_port,
EX_REGB_22_port, EX_REGB_21_port, EX_REGB_20_port, EX_REGB_19_port,
EX_REGB_18_port, EX_REGB_17_port, EX_REGB_16_port, EX_REGB_15_port,
EX_REGB_14_port, EX_REGB_13_port, EX_REGB_12_port, EX_REGB_11_port,
EX_REGB_10_port, EX_REGB_9_port, EX_REGB_8_port, EX_REGB_7_port,
EX_REGB_6_port, EX_REGB_5_port, EX_REGB_4_port, EX_REGB_3_port,
EX_REGB_2_port, EX_REGB_1_port, EX_REGB_0_port, EX_IMM16_EXT_31_port,
EX_IMM16_EXT_30_port, EX_IMM16_EXT_29_port, EX_IMM16_EXT_28_port,
EX_IMM16_EXT_27_port, EX_IMM16_EXT_26_port, EX_IMM16_EXT_25_port,
EX_IMM16_EXT_24_port, EX_IMM16_EXT_23_port, EX_IMM16_EXT_22_port,
EX_IMM16_EXT_21_port, EX_IMM16_EXT_20_port, EX_IMM16_EXT_19_port,
EX_IMM16_EXT_18_port, EX_IMM16_EXT_17_port, EX_IMM16_EXT_16_port,
EX_IMM16_EXT_15_port, EX_IMM16_EXT_14_port, EX_IMM16_EXT_13_port,
EX_IMM16_EXT_12_port, EX_IMM16_EXT_11_port, EX_IMM16_EXT_10_port,
EX_IMM16_EXT_9_port, EX_IMM16_EXT_8_port, EX_IMM16_EXT_7_port,
EX_IMM16_EXT_6_port, EX_IMM16_EXT_5_port, EX_IMM16_EXT_4_port,
EX_IMM16_EXT_3_port, EX_IMM16_EXT_2_port, EX_IMM16_EXT_1_port,
EX_IMM16_EXT_0_port, EX_PC_31_port, EX_PC_30_port, EX_PC_29_port,
EX_PC_28_port, EX_PC_27_port, EX_PC_26_port, EX_PC_25_port, EX_PC_24_port
, EX_PC_23_port, EX_PC_22_port, EX_PC_21_port, EX_PC_20_port,
EX_PC_19_port, EX_PC_18_port, EX_PC_17_port, EX_PC_16_port, EX_PC_15_port
, EX_PC_14_port, EX_PC_13_port, EX_PC_12_port, EX_PC_11_port,
EX_PC_10_port, EX_PC_9_port, EX_PC_8_port, EX_PC_7_port, EX_PC_6_port,
EX_PC_5_port, EX_PC_4_port, EX_PC_3_port, EX_PC_2_port, EX_PC_1_port,
EX_PC_0_port, ID_INSTR_AFTER_CU_31_port, ID_INSTR_AFTER_CU_30_port,
ID_INSTR_AFTER_CU_29_port, ID_INSTR_AFTER_CU_28_port,
ID_INSTR_AFTER_CU_27_port, ID_INSTR_AFTER_CU_26_port,
ID_INSTR_AFTER_CU_20_port, ID_INSTR_AFTER_CU_19_port,
ID_INSTR_AFTER_CU_18_port, ID_INSTR_AFTER_CU_17_port,
ID_INSTR_AFTER_CU_16_port, ID_INSTR_AFTER_CU_15_port,
ID_INSTR_AFTER_CU_14_port, ID_INSTR_AFTER_CU_13_port,
ID_INSTR_AFTER_CU_12_port, ID_INSTR_AFTER_CU_11_port,
ID_INSTR_AFTER_CU_10_port, ID_INSTR_AFTER_CU_9_port,
ID_INSTR_AFTER_CU_8_port, ID_INSTR_AFTER_CU_7_port,
ID_INSTR_AFTER_CU_6_port, ID_INSTR_AFTER_CU_5_port,
ID_INSTR_AFTER_CU_4_port, ID_INSTR_AFTER_CU_3_port,
ID_INSTR_AFTER_CU_2_port, ID_INSTR_AFTER_CU_1_port,
ID_INSTR_AFTER_CU_0_port, EX_INSTR_31_port, EX_INSTR_30_port,
EX_INSTR_29_port, EX_INSTR_28_port, EX_INSTR_27_port, EX_INSTR_26_port,
EX_INSTR_20_port, EX_INSTR_19_port, EX_INSTR_18_port, EX_INSTR_17_port,
EX_INSTR_16_port, EX_INSTR_15_port, EX_INSTR_14_port, EX_INSTR_13_port,
EX_INSTR_12_port, EX_INSTR_11_port, EX_INSTR_10_port, EX_INSTR_9_port,
EX_INSTR_8_port, EX_INSTR_7_port, EX_INSTR_6_port, EX_INSTR_5_port,
EX_INSTR_4_port, EX_INSTR_3_port, EX_INSTR_2_port, EX_INSTR_1_port,
EX_INSTR_0_port, MEM_INSTR_31_port, MEM_INSTR_30_port, MEM_INSTR_29_port,
MEM_INSTR_28_port, MEM_INSTR_27_port, MEM_INSTR_26_port,
MEM_INSTR_20_port, MEM_INSTR_19_port, MEM_INSTR_18_port,
MEM_INSTR_17_port, MEM_INSTR_16_port, MEM_INSTR_15_port,
MEM_INSTR_14_port, MEM_INSTR_13_port, MEM_INSTR_12_port,
MEM_INSTR_11_port, MEM_INSTR_10_port, MEM_INSTR_9_port, MEM_INSTR_8_port,
MEM_INSTR_7_port, MEM_INSTR_6_port, MEM_INSTR_5_port, MEM_INSTR_4_port,
MEM_INSTR_3_port, MEM_INSTR_2_port, MEM_INSTR_1_port, MEM_INSTR_0_port,
WB_DATA_RAM_31_port, WB_DATA_RAM_30_port, WB_DATA_RAM_29_port,
WB_DATA_RAM_28_port, WB_DATA_RAM_27_port, WB_DATA_RAM_26_port,
WB_DATA_RAM_25_port, WB_DATA_RAM_24_port, WB_DATA_RAM_23_port,
WB_DATA_RAM_22_port, WB_DATA_RAM_21_port, WB_DATA_RAM_20_port,
WB_DATA_RAM_19_port, WB_DATA_RAM_18_port, WB_DATA_RAM_17_port,
WB_DATA_RAM_16_port, WB_DATA_RAM_15_port, WB_DATA_RAM_14_port,
WB_DATA_RAM_13_port, WB_DATA_RAM_12_port, WB_DATA_RAM_11_port,
WB_DATA_RAM_10_port, WB_DATA_RAM_9_port, WB_DATA_RAM_8_port,
WB_DATA_RAM_7_port, WB_DATA_RAM_6_port, WB_DATA_RAM_5_port,
WB_DATA_RAM_4_port, WB_DATA_RAM_3_port, WB_DATA_RAM_2_port,
WB_DATA_RAM_1_port, WB_DATA_RAM_0_port, WB_ALU_31_port, WB_ALU_30_port,
WB_ALU_29_port, WB_ALU_28_port, WB_ALU_27_port, WB_ALU_26_port,
WB_ALU_25_port, WB_ALU_24_port, WB_ALU_23_port, WB_ALU_22_port,
WB_ALU_21_port, WB_ALU_20_port, WB_ALU_19_port, WB_ALU_18_port,
WB_ALU_17_port, WB_ALU_16_port, WB_ALU_15_port, WB_ALU_14_port,
WB_ALU_13_port, WB_ALU_12_port, WB_ALU_11_port, WB_ALU_10_port,
WB_ALU_9_port, WB_ALU_8_port, WB_ALU_7_port, WB_ALU_6_port, WB_ALU_5_port
, WB_ALU_4_port, WB_ALU_3_port, WB_ALU_2_port, WB_ALU_1_port,
WB_ALU_0_port, WB_INSTR_31, WB_INSTR_30, WB_INSTR_29, WB_INSTR_28,
WB_INSTR_27, WB_INSTR_26, WB_INSTR_20_port, WB_INSTR_19_port,
WB_INSTR_18_port, WB_INSTR_17_port, WB_INSTR_16_port, WB_INSTR_15_port,
WB_INSTR_14_port, WB_INSTR_13_port, WB_INSTR_12_port, WB_INSTR_11_port,
WB_INSTR_10_port, WB_INSTR_9_port, WB_INSTR_8_port, WB_INSTR_7_port,
WB_INSTR_6_port, WB_INSTR_5_port, WB_INSTR_4_port, WB_INSTR_3_port,
WB_INSTR_2_port, WB_INSTR_1_port, WB_INSTR_0_port, N730, N731, N732, N733
, N734, N735, N736, N737, N738, N739, N740, N741, N742, N743, N744, N745,
N746, N747, N748, N749, N750, N751, N752, N753, N754, N755, N756, N757,
N758, N759, N760, N761, N764, N765, N766, N767, N768, N769, N770, N771,
N772, N773, N774, N775, N776, N777, N778, N779, N780, N781, N782, N783,
N784, N785, N786, N787, N788, N789, N790, N791, N792, N793, N794, N795,
ID_PC_SUM_31_port, ID_PC_SUM_30_port, ID_PC_SUM_29_port,
ID_PC_SUM_28_port, ID_PC_SUM_27_port, ID_PC_SUM_26_port,
ID_PC_SUM_25_port, ID_PC_SUM_24_port, ID_PC_SUM_23_port,
ID_PC_SUM_22_port, ID_PC_SUM_21_port, ID_PC_SUM_20_port,
ID_PC_SUM_19_port, ID_PC_SUM_18_port, ID_PC_SUM_17_port,
ID_PC_SUM_16_port, ID_PC_SUM_15_port, ID_PC_SUM_14_port,
ID_PC_SUM_13_port, ID_PC_SUM_12_port, ID_PC_SUM_11_port,
ID_PC_SUM_10_port, ID_PC_SUM_9_port, ID_PC_SUM_8_port, ID_PC_SUM_7_port,
ID_PC_SUM_6_port, ID_PC_SUM_5_port, ID_PC_SUM_4_port, ID_PC_SUM_3_port,
ID_PC_SUM_2_port, ID_PC_SUM_1_port, ID_PC_SUM_0_port, N4708, N4710, N4712
, N4716, N4717, N4719, N4721, N4722, N4723, N4724, N4726, N4727, N4728,
N4729, N4730, N4831, N4832, N4833, N4834, N4835, N4836, N4837, N4839,
N4840, N4841, N4842, N4843, N4844, N4845, N4846, N4847, N4848, N4849,
N4850, N4851, N4852, N4853, N4854, N4855, N4856, N4857, N4860, N4861,
N4862, N4863, N4864, N4865, N4866, N4867, N4868, N4869, N4870, N4871,
N4872, N4873, N4874, N4875, N4876, N4877, N4878, N4879, N4880, N4881,
N4882, N4883, N4884, N4885, N4886, N4887, N4888, N4889, N4890, N4891,
n319, n320, n321, n686, n688, n690, n697, n1189, n1190, n1191, n1192,
n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202,
n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1211, n1212, n1213,
n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1222, n1223, n1225,
n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235,
n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245,
n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255,
n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265,
n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275,
n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285,
n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295,
n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305,
n1306, n1307, n1308, n1309, n1310, n1312, n1313, n1314, n1315, n1316,
n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326,
n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336,
n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346,
n1347, n1348, n1349, n1351, n1352, n1353, n1355, n1356, n1357, n1358,
n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367, n1368,
n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377, n1378,
n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387, n1388,
n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397, n1398,
n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407, n1408,
n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418,
n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428,
n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438,
n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448,
n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458,
n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468,
n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478,
n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487, n1488,
n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497, n1498,
n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507, n1508,
n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518,
n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527, n1528,
n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539,
n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549,
n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559,
n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569,
n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1580,
n1581, n1582, n1583, n1584, n1585, n1587, n1588, n1589, n1590,
ALU_instance_n39, ALU_instance_n38, ALU_instance_n37, ALU_instance_n36,
ALU_instance_n35, ALU_instance_n34, ALU_instance_n33, ALU_instance_n32,
ALU_instance_n31, ALU_instance_n30, ALU_instance_n29, ALU_instance_n28,
ALU_instance_n27, ALU_instance_n26, ALU_instance_n25, ALU_instance_n24,
ALU_instance_n23, ALU_instance_n22, ALU_instance_n21, ALU_instance_n20,
ALU_instance_n19, ALU_instance_n18, ALU_instance_n17, ALU_instance_n16,
ALU_instance_n15, ALU_instance_n14, ALU_instance_n13, ALU_instance_n12,
ALU_instance_n11, ALU_instance_n10, ALU_instance_n9, ALU_instance_n8,
ALU_instance_n7, ALU_instance_n6, ALU_instance_n5, ALU_instance_n4,
ALU_instance_SHIFTER_OUT_0_port, ALU_instance_SHIFTER_OUT_1_port,
ALU_instance_SHIFTER_OUT_2_port, ALU_instance_SHIFTER_OUT_3_port,
ALU_instance_SHIFTER_OUT_4_port, ALU_instance_SHIFTER_OUT_5_port,
ALU_instance_SHIFTER_OUT_6_port, ALU_instance_SHIFTER_OUT_7_port,
ALU_instance_SHIFTER_OUT_8_port, ALU_instance_SHIFTER_OUT_9_port,
ALU_instance_SHIFTER_OUT_10_port, ALU_instance_SHIFTER_OUT_11_port,
ALU_instance_SHIFTER_OUT_12_port, ALU_instance_SHIFTER_OUT_13_port,
ALU_instance_SHIFTER_OUT_14_port, ALU_instance_SHIFTER_OUT_15_port,
ALU_instance_SHIFTER_OUT_16_port, ALU_instance_SHIFTER_OUT_17_port,
ALU_instance_SHIFTER_OUT_18_port, ALU_instance_SHIFTER_OUT_19_port,
ALU_instance_SHIFTER_OUT_20_port, ALU_instance_SHIFTER_OUT_21_port,
ALU_instance_SHIFTER_OUT_22_port, ALU_instance_SHIFTER_OUT_23_port,
ALU_instance_SHIFTER_OUT_24_port, ALU_instance_SHIFTER_OUT_25_port,
ALU_instance_SHIFTER_OUT_26_port, ALU_instance_SHIFTER_OUT_27_port,
ALU_instance_SHIFTER_OUT_28_port, ALU_instance_SHIFTER_OUT_29_port,
ALU_instance_SHIFTER_OUT_30_port, ALU_instance_SHIFTER_OUT_31_port,
ALU_instance_LOGIC_OUT_0_port, ALU_instance_LOGIC_OUT_1_port,
ALU_instance_LOGIC_OUT_2_port, ALU_instance_LOGIC_OUT_3_port,
ALU_instance_LOGIC_OUT_4_port, ALU_instance_LOGIC_OUT_5_port,
ALU_instance_LOGIC_OUT_6_port, ALU_instance_LOGIC_OUT_7_port,
ALU_instance_LOGIC_OUT_8_port, ALU_instance_LOGIC_OUT_9_port,
ALU_instance_LOGIC_OUT_10_port, ALU_instance_LOGIC_OUT_11_port,
ALU_instance_LOGIC_OUT_12_port, ALU_instance_LOGIC_OUT_13_port,
ALU_instance_LOGIC_OUT_14_port, ALU_instance_LOGIC_OUT_15_port,
ALU_instance_LOGIC_OUT_16_port, ALU_instance_LOGIC_OUT_17_port,
ALU_instance_LOGIC_OUT_18_port, ALU_instance_LOGIC_OUT_19_port,
ALU_instance_LOGIC_OUT_20_port, ALU_instance_LOGIC_OUT_21_port,
ALU_instance_LOGIC_OUT_22_port, ALU_instance_LOGIC_OUT_23_port,
ALU_instance_LOGIC_OUT_24_port, ALU_instance_LOGIC_OUT_25_port,
ALU_instance_LOGIC_OUT_26_port, ALU_instance_LOGIC_OUT_27_port,
ALU_instance_LOGIC_OUT_28_port, ALU_instance_LOGIC_OUT_29_port,
ALU_instance_LOGIC_OUT_30_port, ALU_instance_LOGIC_OUT_31_port,
ALU_instance_COMPARATOR_OUT_0_port, ALU_instance_ADDER_OUT_0_port,
ALU_instance_ADDER_OUT_1_port, ALU_instance_ADDER_OUT_2_port,
ALU_instance_ADDER_OUT_3_port, ALU_instance_ADDER_OUT_4_port,
ALU_instance_ADDER_OUT_5_port, ALU_instance_ADDER_OUT_6_port,
ALU_instance_ADDER_OUT_7_port, ALU_instance_ADDER_OUT_8_port,
ALU_instance_ADDER_OUT_9_port, ALU_instance_ADDER_OUT_10_port,
ALU_instance_ADDER_OUT_11_port, ALU_instance_ADDER_OUT_12_port,
ALU_instance_ADDER_OUT_13_port, ALU_instance_ADDER_OUT_14_port,
ALU_instance_ADDER_OUT_15_port, ALU_instance_ADDER_OUT_16_port,
ALU_instance_ADDER_OUT_17_port, ALU_instance_ADDER_OUT_18_port,
ALU_instance_ADDER_OUT_19_port, ALU_instance_ADDER_OUT_20_port,
ALU_instance_ADDER_OUT_21_port, ALU_instance_ADDER_OUT_22_port,
ALU_instance_ADDER_OUT_23_port, ALU_instance_ADDER_OUT_24_port,
ALU_instance_ADDER_OUT_25_port, ALU_instance_ADDER_OUT_26_port,
ALU_instance_ADDER_OUT_27_port, ALU_instance_ADDER_OUT_28_port,
ALU_instance_ADDER_OUT_29_port, ALU_instance_ADDER_OUT_30_port,
ALU_instance_ADDER_OUT_31_port, ALU_instance_INTERNAL_B_0_port,
ALU_instance_INTERNAL_B_1_port, ALU_instance_INTERNAL_B_2_port,
ALU_instance_INTERNAL_B_3_port, ALU_instance_INTERNAL_B_4_port,
ALU_instance_INTERNAL_B_5_port, ALU_instance_INTERNAL_B_6_port,
ALU_instance_INTERNAL_B_7_port, ALU_instance_INTERNAL_B_8_port,
ALU_instance_INTERNAL_B_9_port, ALU_instance_INTERNAL_B_10_port,
ALU_instance_INTERNAL_B_11_port, ALU_instance_INTERNAL_B_12_port,
ALU_instance_INTERNAL_B_13_port, ALU_instance_INTERNAL_B_14_port,
ALU_instance_INTERNAL_B_15_port, ALU_instance_INTERNAL_B_16_port,
ALU_instance_INTERNAL_B_17_port, ALU_instance_INTERNAL_B_18_port,
ALU_instance_INTERNAL_B_19_port, ALU_instance_INTERNAL_B_20_port,
ALU_instance_INTERNAL_B_21_port, ALU_instance_INTERNAL_B_22_port,
ALU_instance_INTERNAL_B_23_port, ALU_instance_INTERNAL_B_24_port,
ALU_instance_INTERNAL_B_25_port, ALU_instance_INTERNAL_B_26_port,
ALU_instance_INTERNAL_B_27_port, ALU_instance_INTERNAL_B_28_port,
ALU_instance_INTERNAL_B_29_port, ALU_instance_INTERNAL_B_30_port,
ALU_instance_INTERNAL_B_31_port, ALU_instance_OVERFLOW, ALU_instance_ZERO
, BOOTH_instance_n461, BOOTH_instance_n460, BOOTH_instance_n459,
BOOTH_instance_n458, BOOTH_instance_n457, BOOTH_instance_n456,
BOOTH_instance_n455, BOOTH_instance_n454, BOOTH_instance_n453,
BOOTH_instance_n452, BOOTH_instance_n451, BOOTH_instance_n450,
BOOTH_instance_n449, BOOTH_instance_n448, BOOTH_instance_n447,
BOOTH_instance_n445, BOOTH_instance_n443, BOOTH_instance_n442,
BOOTH_instance_n441, BOOTH_instance_n440, BOOTH_instance_n439,
BOOTH_instance_n438, BOOTH_instance_n437, BOOTH_instance_n436,
BOOTH_instance_n435, BOOTH_instance_n434, BOOTH_instance_n432,
BOOTH_instance_n431, BOOTH_instance_n430, BOOTH_instance_n429,
BOOTH_instance_n428, BOOTH_instance_n427, BOOTH_instance_n426,
BOOTH_instance_n425, BOOTH_instance_n424, BOOTH_instance_n423,
BOOTH_instance_n422, BOOTH_instance_n421, BOOTH_instance_n419,
BOOTH_instance_n418, BOOTH_instance_n417, BOOTH_instance_n416,
BOOTH_instance_n415, BOOTH_instance_n414, BOOTH_instance_n413,
BOOTH_instance_n412, BOOTH_instance_n411, BOOTH_instance_n410,
BOOTH_instance_n409, BOOTH_instance_n408, BOOTH_instance_n406,
BOOTH_instance_n405, BOOTH_instance_n404, BOOTH_instance_n403,
BOOTH_instance_n402, BOOTH_instance_n401, BOOTH_instance_n400,
BOOTH_instance_n399, BOOTH_instance_n398, BOOTH_instance_n397,
BOOTH_instance_n396, BOOTH_instance_n395, BOOTH_instance_n394,
BOOTH_instance_n393, BOOTH_instance_n392, BOOTH_instance_n391,
BOOTH_instance_n390, BOOTH_instance_n389, BOOTH_instance_n388,
BOOTH_instance_n387, BOOTH_instance_n386, BOOTH_instance_n385,
BOOTH_instance_n384, BOOTH_instance_n383, BOOTH_instance_n382,
BOOTH_instance_n380, BOOTH_instance_n379, BOOTH_instance_n378,
BOOTH_instance_n377, BOOTH_instance_n376, BOOTH_instance_n375,
BOOTH_instance_n374, BOOTH_instance_n373, BOOTH_instance_n372,
BOOTH_instance_n371, BOOTH_instance_n370, BOOTH_instance_n369,
BOOTH_instance_n368, BOOTH_instance_n367, BOOTH_instance_n366,
BOOTH_instance_n365, BOOTH_instance_n364, BOOTH_instance_n363,
BOOTH_instance_n362, BOOTH_instance_n361, BOOTH_instance_n360,
BOOTH_instance_n359, BOOTH_instance_n358, BOOTH_instance_n357,
BOOTH_instance_n356, BOOTH_instance_n355, BOOTH_instance_n353,
BOOTH_instance_n352, BOOTH_instance_n351, BOOTH_instance_n350,
BOOTH_instance_n349, BOOTH_instance_n348, BOOTH_instance_n347,
BOOTH_instance_n346, BOOTH_instance_n345, BOOTH_instance_n344,
BOOTH_instance_n343, BOOTH_instance_n342, BOOTH_instance_n341,
BOOTH_instance_n340, BOOTH_instance_n339, BOOTH_instance_n338,
BOOTH_instance_n337, BOOTH_instance_n336, BOOTH_instance_n335,
BOOTH_instance_n334, BOOTH_instance_n333, BOOTH_instance_n332,
BOOTH_instance_n331, BOOTH_instance_n330, BOOTH_instance_n329,
BOOTH_instance_n328, BOOTH_instance_n327, BOOTH_instance_n326,
BOOTH_instance_n323, BOOTH_instance_n322, BOOTH_instance_n321,
BOOTH_instance_n320, BOOTH_instance_n319, BOOTH_instance_n318,
BOOTH_instance_n317, BOOTH_instance_n316, BOOTH_instance_n315,
BOOTH_instance_n314, BOOTH_instance_n313, BOOTH_instance_n312,
BOOTH_instance_n311, BOOTH_instance_n310, BOOTH_instance_n309,
BOOTH_instance_n308, BOOTH_instance_n307, BOOTH_instance_n306,
BOOTH_instance_n305, BOOTH_instance_n304, BOOTH_instance_n303,
BOOTH_instance_n302, BOOTH_instance_n301, BOOTH_instance_n300,
BOOTH_instance_n299, BOOTH_instance_n297, BOOTH_instance_n296,
BOOTH_instance_n295, BOOTH_instance_n294, BOOTH_instance_n293,
BOOTH_instance_n292, BOOTH_instance_n291, BOOTH_instance_n290,
BOOTH_instance_n288, BOOTH_instance_n287, BOOTH_instance_n286,
BOOTH_instance_n285, BOOTH_instance_n284, BOOTH_instance_n283,
BOOTH_instance_n282, BOOTH_instance_n281, BOOTH_instance_n280,
BOOTH_instance_n278, BOOTH_instance_n277, BOOTH_instance_n276,
BOOTH_instance_n275, BOOTH_instance_n274, BOOTH_instance_n273,
BOOTH_instance_n272, BOOTH_instance_n271, BOOTH_instance_n269,
BOOTH_instance_n268, BOOTH_instance_n267, BOOTH_instance_n266,
BOOTH_instance_n265, BOOTH_instance_n264, BOOTH_instance_n263,
BOOTH_instance_n261, BOOTH_instance_n260, BOOTH_instance_n259,
BOOTH_instance_n258, BOOTH_instance_n257, BOOTH_instance_n256,
BOOTH_instance_n255, BOOTH_instance_n254, BOOTH_instance_n253,
BOOTH_instance_n252, BOOTH_instance_n251, BOOTH_instance_n249,
BOOTH_instance_n248, BOOTH_instance_n247, BOOTH_instance_n246,
BOOTH_instance_n245, BOOTH_instance_n244, BOOTH_instance_n243,
BOOTH_instance_n242, BOOTH_instance_n241, BOOTH_instance_n239,
BOOTH_instance_n238, BOOTH_instance_n237, BOOTH_instance_n236,
BOOTH_instance_n235, BOOTH_instance_n234, BOOTH_instance_n233,
BOOTH_instance_n232, BOOTH_instance_n231, BOOTH_instance_n229,
BOOTH_instance_n228, BOOTH_instance_n227, BOOTH_instance_n226,
BOOTH_instance_n225, BOOTH_instance_n224, BOOTH_instance_n223,
BOOTH_instance_n222, BOOTH_instance_n221, BOOTH_instance_n219,
BOOTH_instance_n218, BOOTH_instance_n217, BOOTH_instance_n216,
BOOTH_instance_n215, BOOTH_instance_n214, BOOTH_instance_n213,
BOOTH_instance_n212, BOOTH_instance_n211, BOOTH_instance_n209,
BOOTH_instance_n208, BOOTH_instance_n207, BOOTH_instance_n206,
BOOTH_instance_n205, BOOTH_instance_n204, BOOTH_instance_n203,
BOOTH_instance_n202, BOOTH_instance_n201, BOOTH_instance_n199,
BOOTH_instance_n198, BOOTH_instance_n197, BOOTH_instance_n196,
BOOTH_instance_n195, BOOTH_instance_n194, BOOTH_instance_n193,
BOOTH_instance_n192, BOOTH_instance_n191, BOOTH_instance_n189,
BOOTH_instance_n188, BOOTH_instance_n187, BOOTH_instance_n186,
BOOTH_instance_n185, BOOTH_instance_n184, BOOTH_instance_n183,
BOOTH_instance_n182, BOOTH_instance_n181, BOOTH_instance_n180,
BOOTH_instance_n179, BOOTH_instance_n177, BOOTH_instance_n176,
BOOTH_instance_n175, BOOTH_instance_n174, BOOTH_instance_n173,
BOOTH_instance_n172, BOOTH_instance_n171, BOOTH_instance_n170,
BOOTH_instance_n169, BOOTH_instance_n168, BOOTH_instance_n167,
BOOTH_instance_n166, BOOTH_instance_n163, BOOTH_instance_n162,
BOOTH_instance_n161, BOOTH_instance_n160, BOOTH_instance_n159,
BOOTH_instance_n158, BOOTH_instance_n157, BOOTH_instance_n156,
BOOTH_instance_n155, BOOTH_instance_n152, BOOTH_instance_n151,
BOOTH_instance_n150, BOOTH_instance_n149, BOOTH_instance_n148,
BOOTH_instance_n147, BOOTH_instance_n146, BOOTH_instance_n145,
BOOTH_instance_partial_products_2_16_port,
BOOTH_instance_partial_products_2_17_port,
BOOTH_instance_partial_products_2_18_port,
BOOTH_instance_partial_products_2_19_port,
BOOTH_instance_partial_products_2_20_port,
BOOTH_instance_partial_products_2_21_port,
BOOTH_instance_partial_products_2_22_port,
BOOTH_instance_partial_products_2_23_port,
BOOTH_instance_partial_products_2_24_port,
BOOTH_instance_partial_products_2_25_port,
BOOTH_instance_partial_products_2_26_port,
BOOTH_instance_partial_products_2_27_port,
BOOTH_instance_partial_products_2_28_port,
BOOTH_instance_partial_products_2_29_port,
BOOTH_instance_partial_products_2_30_port,
BOOTH_instance_partial_products_2_31_port,
BOOTH_instance_partial_products_3_10_port,
BOOTH_instance_partial_products_3_11_port,
BOOTH_instance_partial_products_3_12_port,
BOOTH_instance_partial_products_3_13_port,
BOOTH_instance_partial_products_3_14_port,
BOOTH_instance_partial_products_3_15_port,
BOOTH_instance_partial_products_3_16_port,
BOOTH_instance_partial_products_3_17_port,
BOOTH_instance_partial_products_3_18_port,
BOOTH_instance_partial_products_3_19_port,
BOOTH_instance_partial_products_3_20_port,
BOOTH_instance_partial_products_3_21_port,
BOOTH_instance_partial_products_3_22_port,
BOOTH_instance_partial_products_3_23_port,
BOOTH_instance_partial_products_3_24_port,
BOOTH_instance_partial_products_3_25_port,
BOOTH_instance_partial_products_3_26_port,
BOOTH_instance_partial_products_3_27_port,
BOOTH_instance_partial_products_3_28_port,
BOOTH_instance_partial_products_3_29_port,
BOOTH_instance_partial_products_3_30_port,
BOOTH_instance_partial_products_3_31_port,
BOOTH_instance_partial_products_3_8_port,
BOOTH_instance_partial_products_3_9_port,
BOOTH_instance_partial_products_4_10_port,
BOOTH_instance_partial_products_4_11_port,
BOOTH_instance_partial_products_4_12_port,
BOOTH_instance_partial_products_4_13_port,
BOOTH_instance_partial_products_4_14_port,
BOOTH_instance_partial_products_4_15_port,
BOOTH_instance_partial_products_4_16_port,
BOOTH_instance_partial_products_4_17_port,
BOOTH_instance_partial_products_4_18_port,
BOOTH_instance_partial_products_4_19_port,
BOOTH_instance_partial_products_4_20_port,
BOOTH_instance_partial_products_4_21_port,
BOOTH_instance_partial_products_4_22_port,
BOOTH_instance_partial_products_4_23_port,
BOOTH_instance_partial_products_4_24_port,
BOOTH_instance_partial_products_4_25_port,
BOOTH_instance_partial_products_4_26_port,
BOOTH_instance_partial_products_4_27_port,
BOOTH_instance_partial_products_4_28_port,
BOOTH_instance_partial_products_4_29_port,
BOOTH_instance_partial_products_4_30_port,
BOOTH_instance_partial_products_4_8_port,
BOOTH_instance_partial_products_4_9_port,
BOOTH_instance_partial_products_6_12_port,
BOOTH_instance_partial_products_6_13_port,
BOOTH_instance_partial_products_6_14_port,
BOOTH_instance_partial_products_6_15_port,
BOOTH_instance_partial_products_6_16_port,
BOOTH_instance_partial_products_6_17_port,
BOOTH_instance_partial_products_6_18_port,
BOOTH_instance_partial_products_6_19_port,
BOOTH_instance_partial_products_6_20_port,
BOOTH_instance_partial_products_6_21_port,
BOOTH_instance_partial_products_6_22_port,
BOOTH_instance_partial_products_6_23_port,
BOOTH_instance_partial_products_6_24_port,
BOOTH_instance_partial_products_6_25_port,
BOOTH_instance_partial_products_6_26_port,
BOOTH_instance_partial_products_6_27_port,
BOOTH_instance_partial_products_6_28_port,
BOOTH_instance_partial_products_6_29_port,
BOOTH_instance_partial_products_6_30_port,
BOOTH_instance_partial_products_6_31_port,
BOOTH_instance_partial_products_7_10_port,
BOOTH_instance_partial_products_7_11_port,
BOOTH_instance_partial_products_7_12_port,
BOOTH_instance_partial_products_7_13_port,
BOOTH_instance_partial_products_7_14_port,
BOOTH_instance_partial_products_7_15_port,
BOOTH_instance_partial_products_7_16_port,
BOOTH_instance_partial_products_7_17_port,
BOOTH_instance_partial_products_7_18_port,
BOOTH_instance_partial_products_7_19_port,
BOOTH_instance_partial_products_7_20_port,
BOOTH_instance_partial_products_7_21_port,
BOOTH_instance_partial_products_7_22_port,
BOOTH_instance_partial_products_7_23_port,
BOOTH_instance_partial_products_7_24_port,
BOOTH_instance_partial_products_7_25_port,
BOOTH_instance_partial_products_7_26_port,
BOOTH_instance_partial_products_7_27_port,
BOOTH_instance_partial_products_7_28_port,
BOOTH_instance_partial_products_7_29_port,
BOOTH_instance_partial_products_7_30_port,
BOOTH_instance_partial_products_7_31_port,
BOOTH_instance_partial_products_7_4_port,
BOOTH_instance_partial_products_7_5_port,
BOOTH_instance_partial_products_7_6_port,
BOOTH_instance_partial_products_7_7_port,
BOOTH_instance_partial_products_7_8_port,
BOOTH_instance_partial_products_7_9_port,
BOOTH_instance_partial_products_8_10_port,
BOOTH_instance_partial_products_8_11_port,
BOOTH_instance_partial_products_8_12_port,
BOOTH_instance_partial_products_8_13_port,
BOOTH_instance_partial_products_8_14_port,
BOOTH_instance_partial_products_8_15_port,
BOOTH_instance_partial_products_8_16_port,
BOOTH_instance_partial_products_8_17_port,
BOOTH_instance_partial_products_8_18_port,
BOOTH_instance_partial_products_8_19_port,
BOOTH_instance_partial_products_8_20_port,
BOOTH_instance_partial_products_8_21_port,
BOOTH_instance_partial_products_8_22_port,
BOOTH_instance_partial_products_8_23_port,
BOOTH_instance_partial_products_8_24_port,
BOOTH_instance_partial_products_8_25_port,
BOOTH_instance_partial_products_8_26_port,
BOOTH_instance_partial_products_8_27_port,
BOOTH_instance_partial_products_8_28_port,
BOOTH_instance_partial_products_8_29_port,
BOOTH_instance_partial_products_8_30_port,
BOOTH_instance_partial_products_8_31_port,
BOOTH_instance_partial_products_8_4_port,
BOOTH_instance_partial_products_8_5_port,
BOOTH_instance_partial_products_8_6_port,
BOOTH_instance_partial_products_8_7_port,
BOOTH_instance_partial_products_8_8_port,
BOOTH_instance_partial_products_8_9_port, BOOTH_instance_N225_port,
BOOTH_instance_N224_port, BOOTH_instance_N223_port,
BOOTH_instance_N222_port, BOOTH_instance_N221_port, BOOTH_instance_N220,
BOOTH_instance_N219_port, BOOTH_instance_N218_port,
BOOTH_instance_N217_port, BOOTH_instance_N216_port,
BOOTH_instance_N215_port, BOOTH_instance_N214_port,
BOOTH_instance_N213_port, BOOTH_instance_N212_port,
BOOTH_instance_N211_port, BOOTH_instance_partial_products_5_12_port,
BOOTH_instance_partial_products_5_13_port,
BOOTH_instance_partial_products_5_14_port,
BOOTH_instance_partial_products_5_15_port,
BOOTH_instance_partial_products_5_16_port,
BOOTH_instance_partial_products_5_17_port,
BOOTH_instance_partial_products_5_18_port,
BOOTH_instance_partial_products_5_19_port,
BOOTH_instance_partial_products_5_20_port,
BOOTH_instance_partial_products_5_21_port,
BOOTH_instance_partial_products_5_22_port,
BOOTH_instance_partial_products_5_23_port,
BOOTH_instance_partial_products_5_24_port,
BOOTH_instance_partial_products_5_25_port,
BOOTH_instance_partial_products_5_26_port,
BOOTH_instance_partial_products_5_27_port,
BOOTH_instance_partial_products_5_28_port,
BOOTH_instance_partial_products_5_29_port,
BOOTH_instance_partial_products_5_30_port,
BOOTH_instance_partial_products_5_31_port,
BOOTH_instance_decoded_8_16_port, BOOTH_instance_decoded_8_17_port,
BOOTH_instance_decoded_8_18_port, BOOTH_instance_decoded_8_19_port,
BOOTH_instance_decoded_8_20_port, BOOTH_instance_decoded_8_21_port,
BOOTH_instance_decoded_8_22_port, BOOTH_instance_decoded_8_23_port,
BOOTH_instance_decoded_8_24_port, BOOTH_instance_decoded_8_25_port,
BOOTH_instance_decoded_8_26_port, BOOTH_instance_decoded_8_27_port,
BOOTH_instance_decoded_8_28_port, BOOTH_instance_decoded_8_29_port,
BOOTH_instance_decoded_8_30_port, BOOTH_instance_decoded_8_31_port,
BOOTH_instance_decoded_5_10_port, BOOTH_instance_decoded_5_11_port,
BOOTH_instance_decoded_5_12_port, BOOTH_instance_decoded_5_13_port,
BOOTH_instance_decoded_5_14_port, BOOTH_instance_decoded_5_15_port,
BOOTH_instance_decoded_5_16_port, BOOTH_instance_decoded_5_17_port,
BOOTH_instance_decoded_5_18_port, BOOTH_instance_decoded_5_19_port,
BOOTH_instance_decoded_5_20_port, BOOTH_instance_decoded_5_21_port,
BOOTH_instance_decoded_5_22_port, BOOTH_instance_decoded_5_23_port,
BOOTH_instance_decoded_5_24_port, BOOTH_instance_decoded_5_25_port,
BOOTH_instance_decoded_5_26_port, BOOTH_instance_decoded_5_31_port,
BOOTH_instance_decoded_4_10_port, BOOTH_instance_decoded_4_11_port,
BOOTH_instance_decoded_4_12_port, BOOTH_instance_decoded_4_13_port,
BOOTH_instance_decoded_4_14_port, BOOTH_instance_decoded_4_15_port,
BOOTH_instance_decoded_4_16_port, BOOTH_instance_decoded_4_17_port,
BOOTH_instance_decoded_4_18_port, BOOTH_instance_decoded_4_19_port,
BOOTH_instance_decoded_4_20_port, BOOTH_instance_decoded_4_21_port,
BOOTH_instance_decoded_4_22_port, BOOTH_instance_decoded_4_23_port,
BOOTH_instance_decoded_4_24_port, BOOTH_instance_decoded_4_31_port,
BOOTH_instance_decoded_3_6_port, BOOTH_instance_decoded_3_7_port,
BOOTH_instance_decoded_3_8_port, BOOTH_instance_decoded_3_9_port,
BOOTH_instance_decoded_3_10_port, BOOTH_instance_decoded_3_11_port,
BOOTH_instance_decoded_3_12_port, BOOTH_instance_decoded_3_13_port,
BOOTH_instance_decoded_3_14_port, BOOTH_instance_decoded_3_15_port,
BOOTH_instance_decoded_3_16_port, BOOTH_instance_decoded_3_17_port,
BOOTH_instance_decoded_3_18_port, BOOTH_instance_decoded_3_19_port,
BOOTH_instance_decoded_3_20_port, BOOTH_instance_decoded_3_21_port,
BOOTH_instance_decoded_3_22_port, BOOTH_instance_decoded_3_31_port,
BOOTH_instance_decoded_2_6_port, BOOTH_instance_decoded_2_7_port,
BOOTH_instance_decoded_2_8_port, BOOTH_instance_decoded_2_9_port,
BOOTH_instance_decoded_2_10_port, BOOTH_instance_decoded_2_11_port,
BOOTH_instance_decoded_2_12_port, BOOTH_instance_decoded_2_13_port,
BOOTH_instance_decoded_2_14_port, BOOTH_instance_decoded_2_15_port,
BOOTH_instance_decoded_2_16_port, BOOTH_instance_decoded_2_17_port,
BOOTH_instance_decoded_2_18_port, BOOTH_instance_decoded_2_19_port,
BOOTH_instance_decoded_2_20_port, BOOTH_instance_decoded_2_31_port,
BOOTH_instance_decoded_1_2_port, BOOTH_instance_decoded_1_3_port,
BOOTH_instance_decoded_1_4_port, BOOTH_instance_decoded_1_5_port,
BOOTH_instance_decoded_1_6_port, BOOTH_instance_decoded_1_7_port,
BOOTH_instance_decoded_1_8_port, BOOTH_instance_decoded_1_9_port,
BOOTH_instance_decoded_1_10_port, BOOTH_instance_decoded_1_11_port,
BOOTH_instance_decoded_1_12_port, BOOTH_instance_decoded_1_13_port,
BOOTH_instance_decoded_1_14_port, BOOTH_instance_decoded_1_15_port,
BOOTH_instance_decoded_1_16_port, BOOTH_instance_decoded_1_17_port,
BOOTH_instance_decoded_1_18_port, BOOTH_instance_decoded_1_31_port,
BOOTH_instance_decoded_0_31_port, PC_instance_n33,
WB_SIGN_EXT_16_instance_n34, WB_SIGN_EXT_16_instance_n33,
WB_SIGN_EXT_16_instance_n28, WB_SIGN_EXT_16_instance_n27,
WB_SIGN_EXT_16_instance_n25, WB_SIGN_EXT_16_instance_n24,
WB_SIGN_EXT_16_instance_n23, WB_SIGN_EXT_16_instance_n22,
zero_instance_n10, zero_instance_n9, zero_instance_n8, zero_instance_n7,
zero_instance_n6, zero_instance_n5, zero_instance_n4, zero_instance_n3,
zero_instance_n2, zero_instance_n1, ID_EX_REGB_REG_instance_n34,
ID_EX_INSTR_REG_instance_n34, MEM_WB_ALU_REG_instance_n34,
add_502_carry_4_port, add_502_carry_5_port, add_502_carry_6_port,
add_502_carry_7_port, add_502_carry_8_port, add_502_carry_9_port,
add_502_carry_10_port, add_502_carry_11_port, add_502_carry_12_port,
add_502_carry_13_port, add_502_carry_14_port, add_502_carry_15_port,
add_502_carry_16_port, add_502_carry_17_port, add_502_carry_18_port,
add_502_carry_19_port, add_502_carry_20_port, add_502_carry_21_port,
add_502_carry_22_port, add_502_carry_23_port, add_502_carry_24_port,
add_502_carry_25_port, add_502_carry_26_port, add_502_carry_27_port,
add_502_carry_28_port, add_502_carry_29_port, add_502_carry_30_port,
add_502_carry_31_port, add_545_carry_3_port, add_545_carry_4_port,
add_545_carry_5_port, add_545_carry_6_port, add_545_carry_7_port,
add_545_carry_8_port, add_545_carry_9_port, add_545_carry_10_port,
add_545_carry_11_port, add_545_carry_12_port, add_545_carry_13_port,
add_545_carry_14_port, add_545_carry_15_port, add_545_carry_16_port,
add_545_carry_17_port, add_545_carry_18_port, add_545_carry_19_port,
add_545_carry_20_port, add_545_carry_21_port, add_545_carry_22_port,
add_545_carry_23_port, add_545_carry_24_port, add_545_carry_25_port,
add_545_carry_26_port, add_545_carry_27_port, add_545_carry_28_port,
add_545_carry_29_port, add_545_carry_30_port, add_545_carry_31_port,
ALU_instance_CARRY_SELECT_ADDER_I_CARRY_1_port,
ALU_instance_CARRY_SELECT_ADDER_I_CARRY_2_port,
ALU_instance_CARRY_SELECT_ADDER_I_CARRY_3_port,
ALU_instance_CARRY_SELECT_ADDER_I_CARRY_4_port,
ALU_instance_CARRY_SELECT_ADDER_I_CARRY_5_port,
ALU_instance_CARRY_SELECT_ADDER_I_CARRY_6_port,
ALU_instance_CARRY_SELECT_ADDER_I_CARRY_7_port,
ALU_instance_COMPARATOR_GENERIC_I_n19,
ALU_instance_COMPARATOR_GENERIC_I_n18,
ALU_instance_COMPARATOR_GENERIC_I_n17,
ALU_instance_COMPARATOR_GENERIC_I_n16,
ALU_instance_COMPARATOR_GENERIC_I_n15,
ALU_instance_COMPARATOR_GENERIC_I_n14,
ALU_instance_COMPARATOR_GENERIC_I_n13,
ALU_instance_COMPARATOR_GENERIC_I_n12,
ALU_instance_COMPARATOR_GENERIC_I_n11,
ALU_instance_COMPARATOR_GENERIC_I_n10,
ALU_instance_COMPARATOR_GENERIC_I_n9,
ALU_instance_COMPARATOR_GENERIC_I_n8,
ALU_instance_COMPARATOR_GENERIC_I_n7,
ALU_instance_COMPARATOR_GENERIC_I_n6,
ALU_instance_COMPARATOR_GENERIC_I_n5,
ALU_instance_COMPARATOR_GENERIC_I_n4, ALU_instance_LOGIC_GENERIC_I_n127,
ALU_instance_LOGIC_GENERIC_I_n126, ALU_instance_LOGIC_GENERIC_I_n124,
ALU_instance_LOGIC_GENERIC_I_n123, ALU_instance_LOGIC_GENERIC_I_n121,
ALU_instance_LOGIC_GENERIC_I_n120, ALU_instance_LOGIC_GENERIC_I_n118,
ALU_instance_LOGIC_GENERIC_I_n117, ALU_instance_LOGIC_GENERIC_I_n115,
ALU_instance_LOGIC_GENERIC_I_n114, ALU_instance_LOGIC_GENERIC_I_n112,
ALU_instance_LOGIC_GENERIC_I_n111, ALU_instance_LOGIC_GENERIC_I_n109,
ALU_instance_LOGIC_GENERIC_I_n108, ALU_instance_LOGIC_GENERIC_I_n106,
ALU_instance_LOGIC_GENERIC_I_n105, ALU_instance_LOGIC_GENERIC_I_n103,
ALU_instance_LOGIC_GENERIC_I_n102, ALU_instance_LOGIC_GENERIC_I_n100,
ALU_instance_LOGIC_GENERIC_I_n99, ALU_instance_LOGIC_GENERIC_I_n97,
ALU_instance_LOGIC_GENERIC_I_n96, ALU_instance_LOGIC_GENERIC_I_n94,
ALU_instance_LOGIC_GENERIC_I_n93, ALU_instance_LOGIC_GENERIC_I_n91,
ALU_instance_LOGIC_GENERIC_I_n90, ALU_instance_LOGIC_GENERIC_I_n88,
ALU_instance_LOGIC_GENERIC_I_n87, ALU_instance_LOGIC_GENERIC_I_n85,
ALU_instance_LOGIC_GENERIC_I_n84, ALU_instance_LOGIC_GENERIC_I_n82,
ALU_instance_LOGIC_GENERIC_I_n81, ALU_instance_LOGIC_GENERIC_I_n79,
ALU_instance_LOGIC_GENERIC_I_n78, ALU_instance_LOGIC_GENERIC_I_n76,
ALU_instance_LOGIC_GENERIC_I_n75, ALU_instance_LOGIC_GENERIC_I_n73,
ALU_instance_LOGIC_GENERIC_I_n72, ALU_instance_LOGIC_GENERIC_I_n70,
ALU_instance_LOGIC_GENERIC_I_n69, ALU_instance_LOGIC_GENERIC_I_n67,
ALU_instance_LOGIC_GENERIC_I_n66, ALU_instance_LOGIC_GENERIC_I_n64,
ALU_instance_LOGIC_GENERIC_I_n63, ALU_instance_LOGIC_GENERIC_I_n61,
ALU_instance_LOGIC_GENERIC_I_n60, ALU_instance_LOGIC_GENERIC_I_n58,
ALU_instance_LOGIC_GENERIC_I_n57, ALU_instance_LOGIC_GENERIC_I_n55,
ALU_instance_LOGIC_GENERIC_I_n54, ALU_instance_LOGIC_GENERIC_I_n52,
ALU_instance_LOGIC_GENERIC_I_n51, ALU_instance_LOGIC_GENERIC_I_n49,
ALU_instance_LOGIC_GENERIC_I_n46, ALU_instance_LOGIC_GENERIC_I_n45,
ALU_instance_LOGIC_GENERIC_I_n43, ALU_instance_LOGIC_GENERIC_I_n42,
ALU_instance_LOGIC_GENERIC_I_n40, ALU_instance_LOGIC_GENERIC_I_n39,
ALU_instance_LOGIC_GENERIC_I_n37, ALU_instance_LOGIC_GENERIC_I_n36,
ALU_instance_LOGIC_GENERIC_I_n34, ALU_instance_LOGIC_GENERIC_I_n33,
ALU_instance_SHIFTER_GENERIC_I_n89, ALU_instance_SHIFTER_GENERIC_I_n88,
ALU_instance_SHIFTER_GENERIC_I_n86, ALU_instance_SHIFTER_GENERIC_I_n85,
ALU_instance_SHIFTER_GENERIC_I_n84, ALU_instance_SHIFTER_GENERIC_I_n83,
ALU_instance_SHIFTER_GENERIC_I_n82, ALU_instance_SHIFTER_GENERIC_I_n81,
ALU_instance_SHIFTER_GENERIC_I_n80, ALU_instance_SHIFTER_GENERIC_I_n79,
ALU_instance_SHIFTER_GENERIC_I_n78, ALU_instance_SHIFTER_GENERIC_I_n77,
ALU_instance_SHIFTER_GENERIC_I_n76, ALU_instance_SHIFTER_GENERIC_I_n75,
ALU_instance_SHIFTER_GENERIC_I_n74, ALU_instance_SHIFTER_GENERIC_I_n73,
ALU_instance_SHIFTER_GENERIC_I_n72, ALU_instance_SHIFTER_GENERIC_I_n71,
ALU_instance_SHIFTER_GENERIC_I_n70, ALU_instance_SHIFTER_GENERIC_I_n69,
ALU_instance_SHIFTER_GENERIC_I_n68, ALU_instance_SHIFTER_GENERIC_I_n67,
ALU_instance_SHIFTER_GENERIC_I_n66, ALU_instance_SHIFTER_GENERIC_I_n65,
ALU_instance_SHIFTER_GENERIC_I_n64, ALU_instance_SHIFTER_GENERIC_I_n63,
ALU_instance_SHIFTER_GENERIC_I_n62, ALU_instance_SHIFTER_GENERIC_I_n61,
ALU_instance_SHIFTER_GENERIC_I_n60, ALU_instance_SHIFTER_GENERIC_I_n59,
ALU_instance_SHIFTER_GENERIC_I_n58, ALU_instance_SHIFTER_GENERIC_I_n57,
ALU_instance_SHIFTER_GENERIC_I_n56, ALU_instance_SHIFTER_GENERIC_I_n55,
ALU_instance_SHIFTER_GENERIC_I_n54, ALU_instance_SHIFTER_GENERIC_I_n53,
ALU_instance_SHIFTER_GENERIC_I_n52, ALU_instance_SHIFTER_GENERIC_I_n51,
ALU_instance_SHIFTER_GENERIC_I_n50, ALU_instance_SHIFTER_GENERIC_I_n49,
ALU_instance_SHIFTER_GENERIC_I_n48, ALU_instance_SHIFTER_GENERIC_I_n47,
ALU_instance_SHIFTER_GENERIC_I_n46, ALU_instance_SHIFTER_GENERIC_I_n45,
ALU_instance_SHIFTER_GENERIC_I_n44, ALU_instance_SHIFTER_GENERIC_I_n43,
ALU_instance_SHIFTER_GENERIC_I_n42, ALU_instance_SHIFTER_GENERIC_I_n41,
ALU_instance_SHIFTER_GENERIC_I_n40, ALU_instance_SHIFTER_GENERIC_I_n39,
ALU_instance_SHIFTER_GENERIC_I_n38, ALU_instance_SHIFTER_GENERIC_I_n37,
ALU_instance_SHIFTER_GENERIC_I_n36, ALU_instance_SHIFTER_GENERIC_I_n35,
ALU_instance_SHIFTER_GENERIC_I_n34, ALU_instance_SHIFTER_GENERIC_I_n33,
ALU_instance_SHIFTER_GENERIC_I_n32, ALU_instance_SHIFTER_GENERIC_I_n31,
ALU_instance_SHIFTER_GENERIC_I_n30, ALU_instance_SHIFTER_GENERIC_I_n29,
ALU_instance_SHIFTER_GENERIC_I_n28, ALU_instance_SHIFTER_GENERIC_I_n27,
ALU_instance_SHIFTER_GENERIC_I_n26, ALU_instance_SHIFTER_GENERIC_I_n25,
ALU_instance_SHIFTER_GENERIC_I_n13, ALU_instance_SHIFTER_GENERIC_I_n12,
ALU_instance_SHIFTER_GENERIC_I_n11, ALU_instance_SHIFTER_GENERIC_I_N265,
ALU_instance_SHIFTER_GENERIC_I_N264, ALU_instance_SHIFTER_GENERIC_I_N263,
ALU_instance_SHIFTER_GENERIC_I_N262, ALU_instance_SHIFTER_GENERIC_I_N261,
ALU_instance_SHIFTER_GENERIC_I_N260, ALU_instance_SHIFTER_GENERIC_I_N259,
ALU_instance_SHIFTER_GENERIC_I_N258, ALU_instance_SHIFTER_GENERIC_I_N257,
ALU_instance_SHIFTER_GENERIC_I_N256, ALU_instance_SHIFTER_GENERIC_I_N255,
ALU_instance_SHIFTER_GENERIC_I_N254, ALU_instance_SHIFTER_GENERIC_I_N253,
ALU_instance_SHIFTER_GENERIC_I_N252, ALU_instance_SHIFTER_GENERIC_I_N251,
ALU_instance_SHIFTER_GENERIC_I_N250, ALU_instance_SHIFTER_GENERIC_I_N249,
ALU_instance_SHIFTER_GENERIC_I_N248, ALU_instance_SHIFTER_GENERIC_I_N247,
ALU_instance_SHIFTER_GENERIC_I_N246, ALU_instance_SHIFTER_GENERIC_I_N245,
ALU_instance_SHIFTER_GENERIC_I_N244, ALU_instance_SHIFTER_GENERIC_I_N243,
ALU_instance_SHIFTER_GENERIC_I_N242, ALU_instance_SHIFTER_GENERIC_I_N241,
ALU_instance_SHIFTER_GENERIC_I_N240, ALU_instance_SHIFTER_GENERIC_I_N239,
ALU_instance_SHIFTER_GENERIC_I_N238, ALU_instance_SHIFTER_GENERIC_I_N237,
ALU_instance_SHIFTER_GENERIC_I_N236, ALU_instance_SHIFTER_GENERIC_I_N235,
ALU_instance_SHIFTER_GENERIC_I_N234, ALU_instance_SHIFTER_GENERIC_I_N233,
ALU_instance_SHIFTER_GENERIC_I_N232, ALU_instance_SHIFTER_GENERIC_I_N231,
ALU_instance_SHIFTER_GENERIC_I_N230, ALU_instance_SHIFTER_GENERIC_I_N229,
ALU_instance_SHIFTER_GENERIC_I_N228, ALU_instance_SHIFTER_GENERIC_I_N227,
ALU_instance_SHIFTER_GENERIC_I_N226, ALU_instance_SHIFTER_GENERIC_I_N225,
ALU_instance_SHIFTER_GENERIC_I_N224, ALU_instance_SHIFTER_GENERIC_I_N223,
ALU_instance_SHIFTER_GENERIC_I_N222, ALU_instance_SHIFTER_GENERIC_I_N221,
ALU_instance_SHIFTER_GENERIC_I_N220, ALU_instance_SHIFTER_GENERIC_I_N219,
ALU_instance_SHIFTER_GENERIC_I_N218, ALU_instance_SHIFTER_GENERIC_I_N217,
ALU_instance_SHIFTER_GENERIC_I_N216, ALU_instance_SHIFTER_GENERIC_I_N215,
ALU_instance_SHIFTER_GENERIC_I_N214, ALU_instance_SHIFTER_GENERIC_I_N213,
ALU_instance_SHIFTER_GENERIC_I_N212, ALU_instance_SHIFTER_GENERIC_I_N211,
ALU_instance_SHIFTER_GENERIC_I_N210, ALU_instance_SHIFTER_GENERIC_I_N209,
ALU_instance_SHIFTER_GENERIC_I_N208, ALU_instance_SHIFTER_GENERIC_I_N207,
ALU_instance_SHIFTER_GENERIC_I_N206, ALU_instance_SHIFTER_GENERIC_I_N205,
ALU_instance_SHIFTER_GENERIC_I_N204, ALU_instance_SHIFTER_GENERIC_I_N203,
ALU_instance_SHIFTER_GENERIC_I_N202, ALU_instance_SHIFTER_GENERIC_I_N168,
ALU_instance_SHIFTER_GENERIC_I_N167, ALU_instance_SHIFTER_GENERIC_I_N166,
ALU_instance_SHIFTER_GENERIC_I_N165, ALU_instance_SHIFTER_GENERIC_I_N164,
ALU_instance_SHIFTER_GENERIC_I_N163, ALU_instance_SHIFTER_GENERIC_I_N162,
ALU_instance_SHIFTER_GENERIC_I_N161, ALU_instance_SHIFTER_GENERIC_I_N160,
ALU_instance_SHIFTER_GENERIC_I_N159, ALU_instance_SHIFTER_GENERIC_I_N158,
ALU_instance_SHIFTER_GENERIC_I_N157, ALU_instance_SHIFTER_GENERIC_I_N156,
ALU_instance_SHIFTER_GENERIC_I_N155, ALU_instance_SHIFTER_GENERIC_I_N154,
ALU_instance_SHIFTER_GENERIC_I_N153, ALU_instance_SHIFTER_GENERIC_I_N152,
ALU_instance_SHIFTER_GENERIC_I_N151, ALU_instance_SHIFTER_GENERIC_I_N150,
ALU_instance_SHIFTER_GENERIC_I_N149, ALU_instance_SHIFTER_GENERIC_I_N148,
ALU_instance_SHIFTER_GENERIC_I_N147, ALU_instance_SHIFTER_GENERIC_I_N146,
ALU_instance_SHIFTER_GENERIC_I_N145, ALU_instance_SHIFTER_GENERIC_I_N144,
ALU_instance_SHIFTER_GENERIC_I_N143, ALU_instance_SHIFTER_GENERIC_I_N142,
ALU_instance_SHIFTER_GENERIC_I_N141, ALU_instance_SHIFTER_GENERIC_I_N140,
ALU_instance_SHIFTER_GENERIC_I_N139, ALU_instance_SHIFTER_GENERIC_I_N138,
ALU_instance_SHIFTER_GENERIC_I_N137, ALU_instance_SHIFTER_GENERIC_I_N135,
ALU_instance_SHIFTER_GENERIC_I_N134, ALU_instance_SHIFTER_GENERIC_I_N133,
ALU_instance_SHIFTER_GENERIC_I_N132, ALU_instance_SHIFTER_GENERIC_I_N131,
ALU_instance_SHIFTER_GENERIC_I_N130, ALU_instance_SHIFTER_GENERIC_I_N129,
ALU_instance_SHIFTER_GENERIC_I_N128, ALU_instance_SHIFTER_GENERIC_I_N127,
ALU_instance_SHIFTER_GENERIC_I_N126, ALU_instance_SHIFTER_GENERIC_I_N125,
ALU_instance_SHIFTER_GENERIC_I_N124, ALU_instance_SHIFTER_GENERIC_I_N123,
ALU_instance_SHIFTER_GENERIC_I_N122, ALU_instance_SHIFTER_GENERIC_I_N121,
ALU_instance_SHIFTER_GENERIC_I_N120, ALU_instance_SHIFTER_GENERIC_I_N119,
ALU_instance_SHIFTER_GENERIC_I_N118, ALU_instance_SHIFTER_GENERIC_I_N117,
ALU_instance_SHIFTER_GENERIC_I_N116, ALU_instance_SHIFTER_GENERIC_I_N115,
ALU_instance_SHIFTER_GENERIC_I_N114, ALU_instance_SHIFTER_GENERIC_I_N113,
ALU_instance_SHIFTER_GENERIC_I_N112, ALU_instance_SHIFTER_GENERIC_I_N111,
ALU_instance_SHIFTER_GENERIC_I_N110, ALU_instance_SHIFTER_GENERIC_I_N109,
ALU_instance_SHIFTER_GENERIC_I_N108, ALU_instance_SHIFTER_GENERIC_I_N107,
ALU_instance_SHIFTER_GENERIC_I_N106, ALU_instance_SHIFTER_GENERIC_I_N105,
BOOTH_instance_add_0_root_add_53_G7_carry_5_port,
BOOTH_instance_add_0_root_add_53_G7_carry_6_port,
BOOTH_instance_add_0_root_add_53_G7_carry_7_port,
BOOTH_instance_add_0_root_add_53_G7_carry_8_port,
BOOTH_instance_add_0_root_add_53_G7_carry_9_port,
BOOTH_instance_add_0_root_add_53_G7_carry_10_port,
BOOTH_instance_add_0_root_add_53_G7_carry_11_port,
BOOTH_instance_add_0_root_add_53_G7_carry_12_port,
BOOTH_instance_add_0_root_add_53_G7_carry_13_port,
BOOTH_instance_add_0_root_add_53_G7_carry_14_port,
BOOTH_instance_add_0_root_add_53_G7_carry_15_port,
BOOTH_instance_add_0_root_add_53_G7_carry_16_port,
BOOTH_instance_add_0_root_add_53_G7_carry_17_port,
BOOTH_instance_add_0_root_add_53_G7_carry_18_port,
BOOTH_instance_add_0_root_add_53_G7_carry_19_port,
BOOTH_instance_add_0_root_add_53_G7_carry_20_port,
BOOTH_instance_add_0_root_add_53_G7_carry_21_port,
BOOTH_instance_add_0_root_add_53_G7_carry_22_port,
BOOTH_instance_add_0_root_add_53_G7_carry_23_port,
BOOTH_instance_add_0_root_add_53_G7_carry_24_port,
BOOTH_instance_add_0_root_add_53_G7_carry_25_port,
BOOTH_instance_add_0_root_add_53_G7_carry_26_port,
BOOTH_instance_add_0_root_add_53_G7_carry_27_port,
BOOTH_instance_add_0_root_add_53_G7_carry_28_port,
BOOTH_instance_add_0_root_add_53_G7_carry_29_port,
BOOTH_instance_add_0_root_add_53_G7_carry_30_port,
BOOTH_instance_add_0_root_add_53_G7_carry_31_port,
BOOTH_instance_add_1_root_add_53_G7_carry_13_port,
BOOTH_instance_add_1_root_add_53_G7_carry_14_port,
BOOTH_instance_add_1_root_add_53_G7_carry_15_port,
BOOTH_instance_add_1_root_add_53_G7_carry_16_port,
BOOTH_instance_add_1_root_add_53_G7_carry_17_port,
BOOTH_instance_add_1_root_add_53_G7_carry_18_port,
BOOTH_instance_add_1_root_add_53_G7_carry_19_port,
BOOTH_instance_add_1_root_add_53_G7_carry_20_port,
BOOTH_instance_add_1_root_add_53_G7_carry_21_port,
BOOTH_instance_add_1_root_add_53_G7_carry_22_port,
BOOTH_instance_add_1_root_add_53_G7_carry_23_port,
BOOTH_instance_add_1_root_add_53_G7_carry_24_port,
BOOTH_instance_add_1_root_add_53_G7_carry_25_port,
BOOTH_instance_add_1_root_add_53_G7_carry_26_port,
BOOTH_instance_add_1_root_add_53_G7_carry_27_port,
BOOTH_instance_add_1_root_add_53_G7_carry_28_port,
BOOTH_instance_add_1_root_add_53_G7_carry_29_port,
BOOTH_instance_add_1_root_add_53_G7_carry_30_port,
BOOTH_instance_add_1_root_add_53_G7_carry_31_port,
BOOTH_instance_add_2_root_add_53_G7_carry_9_port,
BOOTH_instance_add_2_root_add_53_G7_carry_10_port,
BOOTH_instance_add_2_root_add_53_G7_carry_11_port,
BOOTH_instance_add_2_root_add_53_G7_carry_12_port,
BOOTH_instance_add_2_root_add_53_G7_carry_13_port,
BOOTH_instance_add_2_root_add_53_G7_carry_14_port,
BOOTH_instance_add_2_root_add_53_G7_carry_15_port,
BOOTH_instance_add_2_root_add_53_G7_carry_16_port,
BOOTH_instance_add_2_root_add_53_G7_carry_17_port,
BOOTH_instance_add_2_root_add_53_G7_carry_18_port,
BOOTH_instance_add_2_root_add_53_G7_carry_19_port,
BOOTH_instance_add_2_root_add_53_G7_carry_20_port,
BOOTH_instance_add_2_root_add_53_G7_carry_21_port,
BOOTH_instance_add_2_root_add_53_G7_carry_22_port,
BOOTH_instance_add_2_root_add_53_G7_carry_23_port,
BOOTH_instance_add_2_root_add_53_G7_carry_24_port,
BOOTH_instance_add_2_root_add_53_G7_carry_25_port,
BOOTH_instance_add_2_root_add_53_G7_carry_26_port,
BOOTH_instance_add_2_root_add_53_G7_carry_27_port,
BOOTH_instance_add_2_root_add_53_G7_carry_28_port,
BOOTH_instance_add_2_root_add_53_G7_carry_29_port,
BOOTH_instance_add_2_root_add_53_G7_carry_30_port,
BOOTH_instance_add_2_root_add_53_G7_carry_31_port,
BOOTH_instance_add_3_root_add_53_G7_carry_17_port,
BOOTH_instance_add_3_root_add_53_G7_carry_18_port,
BOOTH_instance_add_3_root_add_53_G7_carry_19_port,
BOOTH_instance_add_3_root_add_53_G7_carry_20_port,
BOOTH_instance_add_3_root_add_53_G7_carry_21_port,
BOOTH_instance_add_3_root_add_53_G7_carry_22_port,
BOOTH_instance_add_3_root_add_53_G7_carry_23_port,
BOOTH_instance_add_3_root_add_53_G7_carry_24_port,
BOOTH_instance_add_3_root_add_53_G7_carry_25_port,
BOOTH_instance_add_3_root_add_53_G7_carry_26_port,
BOOTH_instance_add_3_root_add_53_G7_carry_27_port,
BOOTH_instance_add_3_root_add_53_G7_carry_28_port,
BOOTH_instance_add_3_root_add_53_G7_carry_29_port,
BOOTH_instance_add_3_root_add_53_G7_carry_30_port,
BOOTH_instance_add_3_root_add_53_G7_carry_31_port,
BOOTH_instance_add_5_root_add_53_G7_carry_11_port,
BOOTH_instance_add_5_root_add_53_G7_carry_12_port,
BOOTH_instance_add_5_root_add_53_G7_carry_13_port,
BOOTH_instance_add_5_root_add_53_G7_carry_14_port,
BOOTH_instance_add_5_root_add_53_G7_carry_15_port,
BOOTH_instance_add_5_root_add_53_G7_carry_16_port,
BOOTH_instance_add_5_root_add_53_G7_carry_17_port,
BOOTH_instance_add_5_root_add_53_G7_carry_18_port,
BOOTH_instance_add_5_root_add_53_G7_carry_19_port,
BOOTH_instance_add_5_root_add_53_G7_carry_20_port,
BOOTH_instance_add_5_root_add_53_G7_carry_21_port,
BOOTH_instance_add_5_root_add_53_G7_carry_22_port,
BOOTH_instance_add_5_root_add_53_G7_carry_23_port,
BOOTH_instance_add_5_root_add_53_G7_carry_24_port,
BOOTH_instance_add_5_root_add_53_G7_carry_25_port,
BOOTH_instance_add_5_root_add_53_G7_carry_26_port,
BOOTH_instance_add_5_root_add_53_G7_carry_27_port,
BOOTH_instance_add_5_root_add_53_G7_carry_28_port,
BOOTH_instance_add_5_root_add_53_G7_carry_29_port,
BOOTH_instance_add_5_root_add_53_G7_carry_30_port,
BOOTH_instance_add_5_root_add_53_G7_carry_31_port,
BOOTH_instance_add_6_root_add_53_G7_carry_7_port,
BOOTH_instance_add_6_root_add_53_G7_carry_8_port,
BOOTH_instance_add_6_root_add_53_G7_carry_9_port,
BOOTH_instance_add_6_root_add_53_G7_carry_10_port,
BOOTH_instance_add_6_root_add_53_G7_carry_11_port,
BOOTH_instance_add_6_root_add_53_G7_carry_12_port,
BOOTH_instance_add_6_root_add_53_G7_carry_13_port,
BOOTH_instance_add_6_root_add_53_G7_carry_14_port,
BOOTH_instance_add_6_root_add_53_G7_carry_15_port,
BOOTH_instance_add_6_root_add_53_G7_carry_16_port,
BOOTH_instance_add_6_root_add_53_G7_carry_17_port,
BOOTH_instance_add_6_root_add_53_G7_carry_18_port,
BOOTH_instance_add_6_root_add_53_G7_carry_19_port,
BOOTH_instance_add_6_root_add_53_G7_carry_20_port,
BOOTH_instance_add_6_root_add_53_G7_carry_21_port,
BOOTH_instance_add_6_root_add_53_G7_carry_22_port,
BOOTH_instance_add_6_root_add_53_G7_carry_23_port,
BOOTH_instance_add_6_root_add_53_G7_carry_24_port,
BOOTH_instance_add_6_root_add_53_G7_carry_25_port,
BOOTH_instance_add_6_root_add_53_G7_carry_26_port,
BOOTH_instance_add_6_root_add_53_G7_carry_27_port,
BOOTH_instance_add_6_root_add_53_G7_carry_28_port,
BOOTH_instance_add_6_root_add_53_G7_carry_29_port,
BOOTH_instance_add_6_root_add_53_G7_carry_30_port,
BOOTH_instance_add_6_root_add_53_G7_carry_31_port,
BOOTH_instance_add_7_root_add_53_G7_carry_3_port,
BOOTH_instance_add_7_root_add_53_G7_carry_4_port,
BOOTH_instance_add_7_root_add_53_G7_carry_5_port,
BOOTH_instance_add_7_root_add_53_G7_carry_6_port,
BOOTH_instance_add_7_root_add_53_G7_carry_7_port,
BOOTH_instance_add_7_root_add_53_G7_carry_8_port,
BOOTH_instance_add_7_root_add_53_G7_carry_9_port,
BOOTH_instance_add_7_root_add_53_G7_carry_10_port,
BOOTH_instance_add_7_root_add_53_G7_carry_11_port,
BOOTH_instance_add_7_root_add_53_G7_carry_12_port,
BOOTH_instance_add_7_root_add_53_G7_carry_13_port,
BOOTH_instance_add_7_root_add_53_G7_carry_14_port,
BOOTH_instance_add_7_root_add_53_G7_carry_15_port,
BOOTH_instance_add_7_root_add_53_G7_carry_16_port,
BOOTH_instance_add_7_root_add_53_G7_carry_17_port,
BOOTH_instance_add_7_root_add_53_G7_carry_18_port,
BOOTH_instance_add_7_root_add_53_G7_carry_19_port,
BOOTH_instance_add_7_root_add_53_G7_carry_20_port,
BOOTH_instance_add_7_root_add_53_G7_carry_21_port,
BOOTH_instance_add_7_root_add_53_G7_carry_22_port,
BOOTH_instance_add_7_root_add_53_G7_carry_23_port,
BOOTH_instance_add_7_root_add_53_G7_carry_24_port,
BOOTH_instance_add_7_root_add_53_G7_carry_25_port,
BOOTH_instance_add_7_root_add_53_G7_carry_26_port,
BOOTH_instance_add_7_root_add_53_G7_carry_27_port,
BOOTH_instance_add_7_root_add_53_G7_carry_28_port,
BOOTH_instance_add_7_root_add_53_G7_carry_29_port,
BOOTH_instance_add_7_root_add_53_G7_carry_30_port,
BOOTH_instance_add_7_root_add_53_G7_carry_31_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_C1,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_S1_0_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_S1_1_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_S1_2_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_S1_3_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_C0,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_S0_0_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_S0_1_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_S0_2_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_S0_3_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_n2,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_C1,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_S1_0_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_S1_1_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_S1_2_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_S1_3_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_C0,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_S0_0_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_S0_1_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_S0_2_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_S0_3_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_n2,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_C1,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_S1_0_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_S1_1_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_S1_2_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_S1_3_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_C0,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_S0_0_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_S0_1_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_S0_2_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_S0_3_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_n2,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_C1,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_S1_0_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_S1_1_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_S1_2_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_S1_3_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_C0,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_S0_0_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_S0_1_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_S0_2_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_S0_3_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_n2,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_C1,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_S1_0_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_S1_1_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_S1_2_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_S1_3_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_C0,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_S0_0_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_S0_1_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_S0_2_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_S0_3_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_n2,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_C1,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_S1_0_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_S1_1_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_S1_2_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_S1_3_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_C0,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_S0_0_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_S0_1_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_S0_2_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_S0_3_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_n2,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_C1,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_S1_0_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_S1_1_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_S1_2_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_S1_3_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_C0,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_S0_0_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_S0_1_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_S0_2_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_S0_3_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_n2,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_C1,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_S1_0_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_S1_1_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_S1_2_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_S1_3_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_C0,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_S0_0_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_S0_1_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_S0_2_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_S0_3_port,
ALU_instance_SHIFTER_GENERIC_I_C88_n8,
ALU_instance_SHIFTER_GENERIC_I_C88_n7,
ALU_instance_SHIFTER_GENERIC_I_C88_n6,
ALU_instance_SHIFTER_GENERIC_I_C88_n5,
ALU_instance_SHIFTER_GENERIC_I_C88_n4,
ALU_instance_SHIFTER_GENERIC_I_C88_n3,
ALU_instance_SHIFTER_GENERIC_I_C88_n2,
ALU_instance_SHIFTER_GENERIC_I_C88_n1,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_0_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_1_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_2_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_3_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_4_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_5_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_6_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_7_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_8_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_9_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_10_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_11_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_12_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_13_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_14_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_15_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_16_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_17_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_18_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_19_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_20_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_21_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_22_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_23_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_24_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_25_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_26_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_27_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_28_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_29_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_30_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_31_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_0_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_1_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_2_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_3_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_4_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_5_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_6_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_7_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_8_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_9_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_10_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_11_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_12_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_13_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_14_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_15_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_16_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_17_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_18_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_19_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_20_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_21_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_22_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_23_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_24_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_25_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_26_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_27_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_28_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_29_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_30_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_31_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_0_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_1_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_2_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_3_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_4_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_5_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_6_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_7_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_8_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_9_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_10_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_11_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_12_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_13_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_14_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_15_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_16_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_17_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_18_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_19_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_20_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_21_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_22_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_23_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_24_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_25_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_26_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_27_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_28_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_29_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_30_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_31_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_0_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_1_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_2_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_3_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_4_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_5_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_6_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_7_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_8_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_9_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_10_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_11_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_12_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_13_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_14_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_15_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_16_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_17_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_18_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_19_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_20_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_21_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_22_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_23_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_24_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_25_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_26_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_27_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_28_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_29_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_30_port,
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_31_port,
ALU_instance_SHIFTER_GENERIC_I_C86_n179,
ALU_instance_SHIFTER_GENERIC_I_C86_n178,
ALU_instance_SHIFTER_GENERIC_I_C86_n177,
ALU_instance_SHIFTER_GENERIC_I_C86_n176,
ALU_instance_SHIFTER_GENERIC_I_C86_n175,
ALU_instance_SHIFTER_GENERIC_I_C86_n174,
ALU_instance_SHIFTER_GENERIC_I_C86_n172,
ALU_instance_SHIFTER_GENERIC_I_C86_n170,
ALU_instance_SHIFTER_GENERIC_I_C86_n169,
ALU_instance_SHIFTER_GENERIC_I_C86_n168,
ALU_instance_SHIFTER_GENERIC_I_C86_n167,
ALU_instance_SHIFTER_GENERIC_I_C86_n166,
ALU_instance_SHIFTER_GENERIC_I_C86_n165,
ALU_instance_SHIFTER_GENERIC_I_C86_n163,
ALU_instance_SHIFTER_GENERIC_I_C86_n162,
ALU_instance_SHIFTER_GENERIC_I_C86_n159,
ALU_instance_SHIFTER_GENERIC_I_C86_n156,
ALU_instance_SHIFTER_GENERIC_I_C86_n155,
ALU_instance_SHIFTER_GENERIC_I_C86_n153,
ALU_instance_SHIFTER_GENERIC_I_C86_n151,
ALU_instance_SHIFTER_GENERIC_I_C86_n150,
ALU_instance_SHIFTER_GENERIC_I_C86_n149,
ALU_instance_SHIFTER_GENERIC_I_C86_n148,
ALU_instance_SHIFTER_GENERIC_I_C86_n146,
ALU_instance_SHIFTER_GENERIC_I_C86_n145,
ALU_instance_SHIFTER_GENERIC_I_C86_n144,
ALU_instance_SHIFTER_GENERIC_I_C86_n143,
ALU_instance_SHIFTER_GENERIC_I_C86_n141,
ALU_instance_SHIFTER_GENERIC_I_C86_n140,
ALU_instance_SHIFTER_GENERIC_I_C86_n139,
ALU_instance_SHIFTER_GENERIC_I_C86_n138,
ALU_instance_SHIFTER_GENERIC_I_C86_n137,
ALU_instance_SHIFTER_GENERIC_I_C86_n133,
ALU_instance_SHIFTER_GENERIC_I_C86_n132,
ALU_instance_SHIFTER_GENERIC_I_C86_n131,
ALU_instance_SHIFTER_GENERIC_I_C86_n130,
ALU_instance_SHIFTER_GENERIC_I_C86_n129,
ALU_instance_SHIFTER_GENERIC_I_C86_n128,
ALU_instance_SHIFTER_GENERIC_I_C86_n126,
ALU_instance_SHIFTER_GENERIC_I_C86_n125,
ALU_instance_SHIFTER_GENERIC_I_C86_n124,
ALU_instance_SHIFTER_GENERIC_I_C86_n122,
ALU_instance_SHIFTER_GENERIC_I_C86_n121,
ALU_instance_SHIFTER_GENERIC_I_C86_n120,
ALU_instance_SHIFTER_GENERIC_I_C86_n119,
ALU_instance_SHIFTER_GENERIC_I_C86_n118,
ALU_instance_SHIFTER_GENERIC_I_C86_n117,
ALU_instance_SHIFTER_GENERIC_I_C86_n116,
ALU_instance_SHIFTER_GENERIC_I_C86_n115,
ALU_instance_SHIFTER_GENERIC_I_C86_n114,
ALU_instance_SHIFTER_GENERIC_I_C86_n113,
ALU_instance_SHIFTER_GENERIC_I_C86_n112,
ALU_instance_SHIFTER_GENERIC_I_C86_n110,
ALU_instance_SHIFTER_GENERIC_I_C86_n109,
ALU_instance_SHIFTER_GENERIC_I_C86_n108,
ALU_instance_SHIFTER_GENERIC_I_C86_n107,
ALU_instance_SHIFTER_GENERIC_I_C86_n105,
ALU_instance_SHIFTER_GENERIC_I_C86_n104,
ALU_instance_SHIFTER_GENERIC_I_C86_n103,
ALU_instance_SHIFTER_GENERIC_I_C86_n102,
ALU_instance_SHIFTER_GENERIC_I_C86_n100,
ALU_instance_SHIFTER_GENERIC_I_C86_n99,
ALU_instance_SHIFTER_GENERIC_I_C86_n98,
ALU_instance_SHIFTER_GENERIC_I_C86_n97,
ALU_instance_SHIFTER_GENERIC_I_C86_n96,
ALU_instance_SHIFTER_GENERIC_I_C86_n95,
ALU_instance_SHIFTER_GENERIC_I_C86_n94,
ALU_instance_SHIFTER_GENERIC_I_C86_n93,
ALU_instance_SHIFTER_GENERIC_I_C86_n92,
ALU_instance_SHIFTER_GENERIC_I_C86_n91,
ALU_instance_SHIFTER_GENERIC_I_C86_n90,
ALU_instance_SHIFTER_GENERIC_I_C86_n89,
ALU_instance_SHIFTER_GENERIC_I_C86_n88,
ALU_instance_SHIFTER_GENERIC_I_C86_n87,
ALU_instance_SHIFTER_GENERIC_I_C86_n86,
ALU_instance_SHIFTER_GENERIC_I_C86_n85,
ALU_instance_SHIFTER_GENERIC_I_C86_n84,
ALU_instance_SHIFTER_GENERIC_I_C86_n83,
ALU_instance_SHIFTER_GENERIC_I_C86_n82,
ALU_instance_SHIFTER_GENERIC_I_C86_n81,
ALU_instance_SHIFTER_GENERIC_I_C86_n80,
ALU_instance_SHIFTER_GENERIC_I_C86_n79,
ALU_instance_SHIFTER_GENERIC_I_C86_n77,
ALU_instance_SHIFTER_GENERIC_I_C86_n76,
ALU_instance_SHIFTER_GENERIC_I_C86_n75,
ALU_instance_SHIFTER_GENERIC_I_C86_n74,
ALU_instance_SHIFTER_GENERIC_I_C86_n72,
ALU_instance_SHIFTER_GENERIC_I_C86_n71,
ALU_instance_SHIFTER_GENERIC_I_C86_n70,
ALU_instance_SHIFTER_GENERIC_I_C86_n69,
ALU_instance_SHIFTER_GENERIC_I_C86_n68,
ALU_instance_SHIFTER_GENERIC_I_C86_n67,
ALU_instance_SHIFTER_GENERIC_I_C86_n66,
ALU_instance_SHIFTER_GENERIC_I_C86_n65,
ALU_instance_SHIFTER_GENERIC_I_C86_n64,
ALU_instance_SHIFTER_GENERIC_I_C86_n63,
ALU_instance_SHIFTER_GENERIC_I_C86_n62,
ALU_instance_SHIFTER_GENERIC_I_C86_n61,
ALU_instance_SHIFTER_GENERIC_I_C86_n60,
ALU_instance_SHIFTER_GENERIC_I_C86_n59,
ALU_instance_SHIFTER_GENERIC_I_C86_n58,
ALU_instance_SHIFTER_GENERIC_I_C86_n57,
ALU_instance_SHIFTER_GENERIC_I_C86_n56,
ALU_instance_SHIFTER_GENERIC_I_C86_n55,
ALU_instance_SHIFTER_GENERIC_I_C86_n54,
ALU_instance_SHIFTER_GENERIC_I_C86_n53,
ALU_instance_SHIFTER_GENERIC_I_C86_n51,
ALU_instance_SHIFTER_GENERIC_I_C86_n50,
ALU_instance_SHIFTER_GENERIC_I_C86_n49,
ALU_instance_SHIFTER_GENERIC_I_C86_n48,
ALU_instance_SHIFTER_GENERIC_I_C86_n47,
ALU_instance_SHIFTER_GENERIC_I_C86_n46,
ALU_instance_SHIFTER_GENERIC_I_C86_n45,
ALU_instance_SHIFTER_GENERIC_I_C86_n44,
ALU_instance_SHIFTER_GENERIC_I_C86_n43,
ALU_instance_SHIFTER_GENERIC_I_C86_n42,
ALU_instance_SHIFTER_GENERIC_I_C86_n41,
ALU_instance_SHIFTER_GENERIC_I_C86_n40,
ALU_instance_SHIFTER_GENERIC_I_C86_n39,
ALU_instance_SHIFTER_GENERIC_I_C86_n38,
ALU_instance_SHIFTER_GENERIC_I_C86_n37,
ALU_instance_SHIFTER_GENERIC_I_C86_n36,
ALU_instance_SHIFTER_GENERIC_I_C86_n35,
ALU_instance_SHIFTER_GENERIC_I_C86_n34,
ALU_instance_SHIFTER_GENERIC_I_C86_n33,
ALU_instance_SHIFTER_GENERIC_I_C86_n32,
ALU_instance_SHIFTER_GENERIC_I_C86_n31,
ALU_instance_SHIFTER_GENERIC_I_C86_n30,
ALU_instance_SHIFTER_GENERIC_I_C86_n29,
ALU_instance_SHIFTER_GENERIC_I_C86_n28,
ALU_instance_SHIFTER_GENERIC_I_C86_n27,
ALU_instance_SHIFTER_GENERIC_I_C86_n25,
ALU_instance_SHIFTER_GENERIC_I_C86_n24,
ALU_instance_SHIFTER_GENERIC_I_C86_n23,
ALU_instance_SHIFTER_GENERIC_I_C86_n22,
ALU_instance_SHIFTER_GENERIC_I_C86_n21,
ALU_instance_SHIFTER_GENERIC_I_C86_n20,
ALU_instance_SHIFTER_GENERIC_I_C86_n19,
ALU_instance_SHIFTER_GENERIC_I_C86_n18,
ALU_instance_SHIFTER_GENERIC_I_C86_n17,
ALU_instance_SHIFTER_GENERIC_I_C86_n16,
ALU_instance_SHIFTER_GENERIC_I_C86_n15,
ALU_instance_SHIFTER_GENERIC_I_C86_n14,
ALU_instance_SHIFTER_GENERIC_I_C86_n13,
ALU_instance_SHIFTER_GENERIC_I_C86_n12,
ALU_instance_SHIFTER_GENERIC_I_C86_n11,
ALU_instance_SHIFTER_GENERIC_I_C86_n10,
ALU_instance_SHIFTER_GENERIC_I_C86_n9,
ALU_instance_SHIFTER_GENERIC_I_C86_n8,
ALU_instance_SHIFTER_GENERIC_I_C86_n7,
ALU_instance_SHIFTER_GENERIC_I_C86_n6,
ALU_instance_SHIFTER_GENERIC_I_C86_n5,
ALU_instance_SHIFTER_GENERIC_I_C86_n4,
ALU_instance_SHIFTER_GENERIC_I_C86_n3,
ALU_instance_SHIFTER_GENERIC_I_C86_n2,
ALU_instance_SHIFTER_GENERIC_I_C50_n163,
ALU_instance_SHIFTER_GENERIC_I_C50_n162,
ALU_instance_SHIFTER_GENERIC_I_C50_n161,
ALU_instance_SHIFTER_GENERIC_I_C50_n160,
ALU_instance_SHIFTER_GENERIC_I_C50_n159,
ALU_instance_SHIFTER_GENERIC_I_C50_n158,
ALU_instance_SHIFTER_GENERIC_I_C50_n157,
ALU_instance_SHIFTER_GENERIC_I_C50_n156,
ALU_instance_SHIFTER_GENERIC_I_C50_n155,
ALU_instance_SHIFTER_GENERIC_I_C50_n153,
ALU_instance_SHIFTER_GENERIC_I_C50_n152,
ALU_instance_SHIFTER_GENERIC_I_C50_n151,
ALU_instance_SHIFTER_GENERIC_I_C50_n150,
ALU_instance_SHIFTER_GENERIC_I_C50_n149,
ALU_instance_SHIFTER_GENERIC_I_C50_n148,
ALU_instance_SHIFTER_GENERIC_I_C50_n147,
ALU_instance_SHIFTER_GENERIC_I_C50_n146,
ALU_instance_SHIFTER_GENERIC_I_C50_n145,
ALU_instance_SHIFTER_GENERIC_I_C50_n144,
ALU_instance_SHIFTER_GENERIC_I_C50_n143,
ALU_instance_SHIFTER_GENERIC_I_C50_n142,
ALU_instance_SHIFTER_GENERIC_I_C50_n139,
ALU_instance_SHIFTER_GENERIC_I_C50_n138,
ALU_instance_SHIFTER_GENERIC_I_C50_n134,
ALU_instance_SHIFTER_GENERIC_I_C50_n132,
ALU_instance_SHIFTER_GENERIC_I_C50_n130,
ALU_instance_SHIFTER_GENERIC_I_C50_n128,
ALU_instance_SHIFTER_GENERIC_I_C50_n127,
ALU_instance_SHIFTER_GENERIC_I_C50_n124,
ALU_instance_SHIFTER_GENERIC_I_C50_n123,
ALU_instance_SHIFTER_GENERIC_I_C50_n122,
ALU_instance_SHIFTER_GENERIC_I_C50_n120,
ALU_instance_SHIFTER_GENERIC_I_C50_n119,
ALU_instance_SHIFTER_GENERIC_I_C50_n118,
ALU_instance_SHIFTER_GENERIC_I_C50_n117,
ALU_instance_SHIFTER_GENERIC_I_C50_n114,
ALU_instance_SHIFTER_GENERIC_I_C50_n113,
ALU_instance_SHIFTER_GENERIC_I_C50_n111,
ALU_instance_SHIFTER_GENERIC_I_C50_n107,
ALU_instance_SHIFTER_GENERIC_I_C50_n104,
ALU_instance_SHIFTER_GENERIC_I_C50_n103,
ALU_instance_SHIFTER_GENERIC_I_C50_n102,
ALU_instance_SHIFTER_GENERIC_I_C50_n101,
ALU_instance_SHIFTER_GENERIC_I_C50_n100,
ALU_instance_SHIFTER_GENERIC_I_C50_n99,
ALU_instance_SHIFTER_GENERIC_I_C50_n98,
ALU_instance_SHIFTER_GENERIC_I_C50_n97,
ALU_instance_SHIFTER_GENERIC_I_C50_n96,
ALU_instance_SHIFTER_GENERIC_I_C50_n95,
ALU_instance_SHIFTER_GENERIC_I_C50_n94,
ALU_instance_SHIFTER_GENERIC_I_C50_n93,
ALU_instance_SHIFTER_GENERIC_I_C50_n92,
ALU_instance_SHIFTER_GENERIC_I_C50_n91,
ALU_instance_SHIFTER_GENERIC_I_C50_n90,
ALU_instance_SHIFTER_GENERIC_I_C50_n89,
ALU_instance_SHIFTER_GENERIC_I_C50_n87,
ALU_instance_SHIFTER_GENERIC_I_C50_n86,
ALU_instance_SHIFTER_GENERIC_I_C50_n84,
ALU_instance_SHIFTER_GENERIC_I_C50_n81,
ALU_instance_SHIFTER_GENERIC_I_C50_n80,
ALU_instance_SHIFTER_GENERIC_I_C50_n79,
ALU_instance_SHIFTER_GENERIC_I_C50_n78,
ALU_instance_SHIFTER_GENERIC_I_C50_n77,
ALU_instance_SHIFTER_GENERIC_I_C50_n76,
ALU_instance_SHIFTER_GENERIC_I_C50_n75,
ALU_instance_SHIFTER_GENERIC_I_C50_n74,
ALU_instance_SHIFTER_GENERIC_I_C50_n73,
ALU_instance_SHIFTER_GENERIC_I_C50_n72,
ALU_instance_SHIFTER_GENERIC_I_C50_n70,
ALU_instance_SHIFTER_GENERIC_I_C50_n68,
ALU_instance_SHIFTER_GENERIC_I_C50_n67,
ALU_instance_SHIFTER_GENERIC_I_C50_n66,
ALU_instance_SHIFTER_GENERIC_I_C50_n65,
ALU_instance_SHIFTER_GENERIC_I_C50_n64,
ALU_instance_SHIFTER_GENERIC_I_C50_n63,
ALU_instance_SHIFTER_GENERIC_I_C50_n61,
ALU_instance_SHIFTER_GENERIC_I_C50_n60,
ALU_instance_SHIFTER_GENERIC_I_C50_n58,
ALU_instance_SHIFTER_GENERIC_I_C50_n57,
ALU_instance_SHIFTER_GENERIC_I_C50_n56,
ALU_instance_SHIFTER_GENERIC_I_C50_n55,
ALU_instance_SHIFTER_GENERIC_I_C50_n54,
ALU_instance_SHIFTER_GENERIC_I_C50_n53,
ALU_instance_SHIFTER_GENERIC_I_C50_n50,
ALU_instance_SHIFTER_GENERIC_I_C50_n49,
ALU_instance_SHIFTER_GENERIC_I_C50_n48,
ALU_instance_SHIFTER_GENERIC_I_C50_n47,
ALU_instance_SHIFTER_GENERIC_I_C50_n46,
ALU_instance_SHIFTER_GENERIC_I_C50_n45,
ALU_instance_SHIFTER_GENERIC_I_C50_n43,
ALU_instance_SHIFTER_GENERIC_I_C50_n42,
ALU_instance_SHIFTER_GENERIC_I_C50_n40,
ALU_instance_SHIFTER_GENERIC_I_C50_n39,
ALU_instance_SHIFTER_GENERIC_I_C50_n38,
ALU_instance_SHIFTER_GENERIC_I_C50_n37,
ALU_instance_SHIFTER_GENERIC_I_C50_n36,
ALU_instance_SHIFTER_GENERIC_I_C50_n35,
ALU_instance_SHIFTER_GENERIC_I_C50_n34,
ALU_instance_SHIFTER_GENERIC_I_C50_n33,
ALU_instance_SHIFTER_GENERIC_I_C50_n32,
ALU_instance_SHIFTER_GENERIC_I_C50_n31,
ALU_instance_SHIFTER_GENERIC_I_C50_n30,
ALU_instance_SHIFTER_GENERIC_I_C50_n29,
ALU_instance_SHIFTER_GENERIC_I_C50_n28,
ALU_instance_SHIFTER_GENERIC_I_C50_n27,
ALU_instance_SHIFTER_GENERIC_I_C50_n26,
ALU_instance_SHIFTER_GENERIC_I_C50_n25,
ALU_instance_SHIFTER_GENERIC_I_C50_n24,
ALU_instance_SHIFTER_GENERIC_I_C50_n23,
ALU_instance_SHIFTER_GENERIC_I_C50_n22,
ALU_instance_SHIFTER_GENERIC_I_C50_n21,
ALU_instance_SHIFTER_GENERIC_I_C50_n20,
ALU_instance_SHIFTER_GENERIC_I_C50_n19,
ALU_instance_SHIFTER_GENERIC_I_C50_n18,
ALU_instance_SHIFTER_GENERIC_I_C50_n17,
ALU_instance_SHIFTER_GENERIC_I_C50_n16,
ALU_instance_SHIFTER_GENERIC_I_C50_n15,
ALU_instance_SHIFTER_GENERIC_I_C50_n14,
ALU_instance_SHIFTER_GENERIC_I_C50_n13,
ALU_instance_SHIFTER_GENERIC_I_C50_n12,
ALU_instance_SHIFTER_GENERIC_I_C50_n11,
ALU_instance_SHIFTER_GENERIC_I_C50_n10,
ALU_instance_SHIFTER_GENERIC_I_C50_n9,
ALU_instance_SHIFTER_GENERIC_I_C50_n8,
ALU_instance_SHIFTER_GENERIC_I_C50_n7,
ALU_instance_SHIFTER_GENERIC_I_C50_n6,
ALU_instance_SHIFTER_GENERIC_I_C50_n5,
ALU_instance_SHIFTER_GENERIC_I_C50_n4,
ALU_instance_SHIFTER_GENERIC_I_C50_n2,
ALU_instance_SHIFTER_GENERIC_I_C48_n163,
ALU_instance_SHIFTER_GENERIC_I_C48_n162,
ALU_instance_SHIFTER_GENERIC_I_C48_n161,
ALU_instance_SHIFTER_GENERIC_I_C48_n160,
ALU_instance_SHIFTER_GENERIC_I_C48_n159,
ALU_instance_SHIFTER_GENERIC_I_C48_n158,
ALU_instance_SHIFTER_GENERIC_I_C48_n157,
ALU_instance_SHIFTER_GENERIC_I_C48_n156,
ALU_instance_SHIFTER_GENERIC_I_C48_n155,
ALU_instance_SHIFTER_GENERIC_I_C48_n152,
ALU_instance_SHIFTER_GENERIC_I_C48_n151,
ALU_instance_SHIFTER_GENERIC_I_C48_n150,
ALU_instance_SHIFTER_GENERIC_I_C48_n149,
ALU_instance_SHIFTER_GENERIC_I_C48_n148,
ALU_instance_SHIFTER_GENERIC_I_C48_n147,
ALU_instance_SHIFTER_GENERIC_I_C48_n146,
ALU_instance_SHIFTER_GENERIC_I_C48_n145,
ALU_instance_SHIFTER_GENERIC_I_C48_n144,
ALU_instance_SHIFTER_GENERIC_I_C48_n143,
ALU_instance_SHIFTER_GENERIC_I_C48_n142,
ALU_instance_SHIFTER_GENERIC_I_C48_n141,
ALU_instance_SHIFTER_GENERIC_I_C48_n140,
ALU_instance_SHIFTER_GENERIC_I_C48_n138,
ALU_instance_SHIFTER_GENERIC_I_C48_n135,
ALU_instance_SHIFTER_GENERIC_I_C48_n134,
ALU_instance_SHIFTER_GENERIC_I_C48_n131,
ALU_instance_SHIFTER_GENERIC_I_C48_n130,
ALU_instance_SHIFTER_GENERIC_I_C48_n129,
ALU_instance_SHIFTER_GENERIC_I_C48_n128,
ALU_instance_SHIFTER_GENERIC_I_C48_n127,
ALU_instance_SHIFTER_GENERIC_I_C48_n125,
ALU_instance_SHIFTER_GENERIC_I_C48_n124,
ALU_instance_SHIFTER_GENERIC_I_C48_n121,
ALU_instance_SHIFTER_GENERIC_I_C48_n118,
ALU_instance_SHIFTER_GENERIC_I_C48_n117,
ALU_instance_SHIFTER_GENERIC_I_C48_n115,
ALU_instance_SHIFTER_GENERIC_I_C48_n114,
ALU_instance_SHIFTER_GENERIC_I_C48_n112,
ALU_instance_SHIFTER_GENERIC_I_C48_n111,
ALU_instance_SHIFTER_GENERIC_I_C48_n110,
ALU_instance_SHIFTER_GENERIC_I_C48_n109,
ALU_instance_SHIFTER_GENERIC_I_C48_n108,
ALU_instance_SHIFTER_GENERIC_I_C48_n107,
ALU_instance_SHIFTER_GENERIC_I_C48_n106,
ALU_instance_SHIFTER_GENERIC_I_C48_n105,
ALU_instance_SHIFTER_GENERIC_I_C48_n104,
ALU_instance_SHIFTER_GENERIC_I_C48_n103,
ALU_instance_SHIFTER_GENERIC_I_C48_n102,
ALU_instance_SHIFTER_GENERIC_I_C48_n101,
ALU_instance_SHIFTER_GENERIC_I_C48_n100,
ALU_instance_SHIFTER_GENERIC_I_C48_n99,
ALU_instance_SHIFTER_GENERIC_I_C48_n98,
ALU_instance_SHIFTER_GENERIC_I_C48_n97,
ALU_instance_SHIFTER_GENERIC_I_C48_n96,
ALU_instance_SHIFTER_GENERIC_I_C48_n94,
ALU_instance_SHIFTER_GENERIC_I_C48_n93,
ALU_instance_SHIFTER_GENERIC_I_C48_n92,
ALU_instance_SHIFTER_GENERIC_I_C48_n91,
ALU_instance_SHIFTER_GENERIC_I_C48_n90,
ALU_instance_SHIFTER_GENERIC_I_C48_n89,
ALU_instance_SHIFTER_GENERIC_I_C48_n88,
ALU_instance_SHIFTER_GENERIC_I_C48_n87,
ALU_instance_SHIFTER_GENERIC_I_C48_n86,
ALU_instance_SHIFTER_GENERIC_I_C48_n85,
ALU_instance_SHIFTER_GENERIC_I_C48_n84,
ALU_instance_SHIFTER_GENERIC_I_C48_n83,
ALU_instance_SHIFTER_GENERIC_I_C48_n82,
ALU_instance_SHIFTER_GENERIC_I_C48_n81,
ALU_instance_SHIFTER_GENERIC_I_C48_n80,
ALU_instance_SHIFTER_GENERIC_I_C48_n79,
ALU_instance_SHIFTER_GENERIC_I_C48_n78,
ALU_instance_SHIFTER_GENERIC_I_C48_n77,
ALU_instance_SHIFTER_GENERIC_I_C48_n76,
ALU_instance_SHIFTER_GENERIC_I_C48_n75,
ALU_instance_SHIFTER_GENERIC_I_C48_n74,
ALU_instance_SHIFTER_GENERIC_I_C48_n73,
ALU_instance_SHIFTER_GENERIC_I_C48_n71,
ALU_instance_SHIFTER_GENERIC_I_C48_n69,
ALU_instance_SHIFTER_GENERIC_I_C48_n68,
ALU_instance_SHIFTER_GENERIC_I_C48_n67,
ALU_instance_SHIFTER_GENERIC_I_C48_n66,
ALU_instance_SHIFTER_GENERIC_I_C48_n65,
ALU_instance_SHIFTER_GENERIC_I_C48_n62,
ALU_instance_SHIFTER_GENERIC_I_C48_n61,
ALU_instance_SHIFTER_GENERIC_I_C48_n59,
ALU_instance_SHIFTER_GENERIC_I_C48_n58,
ALU_instance_SHIFTER_GENERIC_I_C48_n57,
ALU_instance_SHIFTER_GENERIC_I_C48_n56,
ALU_instance_SHIFTER_GENERIC_I_C48_n55,
ALU_instance_SHIFTER_GENERIC_I_C48_n54,
ALU_instance_SHIFTER_GENERIC_I_C48_n53,
ALU_instance_SHIFTER_GENERIC_I_C48_n52,
ALU_instance_SHIFTER_GENERIC_I_C48_n50,
ALU_instance_SHIFTER_GENERIC_I_C48_n48,
ALU_instance_SHIFTER_GENERIC_I_C48_n47,
ALU_instance_SHIFTER_GENERIC_I_C48_n46,
ALU_instance_SHIFTER_GENERIC_I_C48_n45,
ALU_instance_SHIFTER_GENERIC_I_C48_n44,
ALU_instance_SHIFTER_GENERIC_I_C48_n43,
ALU_instance_SHIFTER_GENERIC_I_C48_n42,
ALU_instance_SHIFTER_GENERIC_I_C48_n41,
ALU_instance_SHIFTER_GENERIC_I_C48_n40,
ALU_instance_SHIFTER_GENERIC_I_C48_n39,
ALU_instance_SHIFTER_GENERIC_I_C48_n38,
ALU_instance_SHIFTER_GENERIC_I_C48_n37,
ALU_instance_SHIFTER_GENERIC_I_C48_n36,
ALU_instance_SHIFTER_GENERIC_I_C48_n35,
ALU_instance_SHIFTER_GENERIC_I_C48_n34,
ALU_instance_SHIFTER_GENERIC_I_C48_n33,
ALU_instance_SHIFTER_GENERIC_I_C48_n32,
ALU_instance_SHIFTER_GENERIC_I_C48_n31,
ALU_instance_SHIFTER_GENERIC_I_C48_n30,
ALU_instance_SHIFTER_GENERIC_I_C48_n29,
ALU_instance_SHIFTER_GENERIC_I_C48_n28,
ALU_instance_SHIFTER_GENERIC_I_C48_n27,
ALU_instance_SHIFTER_GENERIC_I_C48_n26,
ALU_instance_SHIFTER_GENERIC_I_C48_n25,
ALU_instance_SHIFTER_GENERIC_I_C48_n24,
ALU_instance_SHIFTER_GENERIC_I_C48_n23,
ALU_instance_SHIFTER_GENERIC_I_C48_n22,
ALU_instance_SHIFTER_GENERIC_I_C48_n21,
ALU_instance_SHIFTER_GENERIC_I_C48_n20,
ALU_instance_SHIFTER_GENERIC_I_C48_n19,
ALU_instance_SHIFTER_GENERIC_I_C48_n18,
ALU_instance_SHIFTER_GENERIC_I_C48_n17,
ALU_instance_SHIFTER_GENERIC_I_C48_n16,
ALU_instance_SHIFTER_GENERIC_I_C48_n15,
ALU_instance_SHIFTER_GENERIC_I_C48_n14,
ALU_instance_SHIFTER_GENERIC_I_C48_n13,
ALU_instance_SHIFTER_GENERIC_I_C48_n12,
ALU_instance_SHIFTER_GENERIC_I_C48_n11,
ALU_instance_SHIFTER_GENERIC_I_C48_n10,
ALU_instance_SHIFTER_GENERIC_I_C48_n9,
ALU_instance_SHIFTER_GENERIC_I_C48_n8,
ALU_instance_SHIFTER_GENERIC_I_C48_n7,
ALU_instance_SHIFTER_GENERIC_I_C48_n6,
ALU_instance_SHIFTER_GENERIC_I_C48_n5,
ALU_instance_SHIFTER_GENERIC_I_C48_n4,
ALU_instance_SHIFTER_GENERIC_I_C48_n3,
ALU_instance_SHIFTER_GENERIC_I_C48_n2,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_RCA0_add_1_root_add_20_2_carry_1_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_RCA0_add_1_root_add_20_2_carry_2_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_RCA0_add_1_root_add_20_2_carry_3_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_RCA1_add_1_root_add_20_2_carry_1_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_RCA1_add_1_root_add_20_2_carry_2_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_RCA1_add_1_root_add_20_2_carry_3_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_RCA0_add_1_root_add_20_2_carry_1_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_RCA0_add_1_root_add_20_2_carry_2_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_RCA0_add_1_root_add_20_2_carry_3_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_RCA1_add_1_root_add_20_2_carry_1_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_RCA1_add_1_root_add_20_2_carry_2_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_RCA1_add_1_root_add_20_2_carry_3_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_RCA0_add_1_root_add_20_2_carry_1_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_RCA0_add_1_root_add_20_2_carry_2_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_RCA0_add_1_root_add_20_2_carry_3_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_RCA1_add_1_root_add_20_2_carry_1_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_RCA1_add_1_root_add_20_2_carry_2_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_RCA1_add_1_root_add_20_2_carry_3_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_RCA0_add_1_root_add_20_2_carry_1_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_RCA0_add_1_root_add_20_2_carry_2_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_RCA0_add_1_root_add_20_2_carry_3_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_RCA1_add_1_root_add_20_2_carry_1_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_RCA1_add_1_root_add_20_2_carry_2_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_RCA1_add_1_root_add_20_2_carry_3_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_RCA0_add_1_root_add_20_2_carry_1_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_RCA0_add_1_root_add_20_2_carry_2_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_RCA0_add_1_root_add_20_2_carry_3_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_RCA1_add_1_root_add_20_2_carry_1_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_RCA1_add_1_root_add_20_2_carry_2_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_RCA1_add_1_root_add_20_2_carry_3_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_RCA0_add_1_root_add_20_2_carry_1_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_RCA0_add_1_root_add_20_2_carry_2_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_RCA0_add_1_root_add_20_2_carry_3_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_RCA1_add_1_root_add_20_2_carry_1_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_RCA1_add_1_root_add_20_2_carry_2_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_RCA1_add_1_root_add_20_2_carry_3_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_RCA0_add_1_root_add_20_2_carry_1_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_RCA0_add_1_root_add_20_2_carry_2_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_RCA0_add_1_root_add_20_2_carry_3_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_RCA1_add_1_root_add_20_2_carry_1_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_RCA1_add_1_root_add_20_2_carry_2_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_RCA1_add_1_root_add_20_2_carry_3_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_RCA0_add_1_root_add_20_2_carry_1_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_RCA0_add_1_root_add_20_2_carry_2_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_RCA0_add_1_root_add_20_2_carry_3_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_RCA1_add_1_root_add_20_2_carry_1_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_RCA1_add_1_root_add_20_2_carry_2_port,
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_RCA1_add_1_root_add_20_2_carry_3_port,
EX_MEM_OUT_REG_instance_n34, EX_MEM_REGB_REG_instance_n34,
ID_EX_PC_REG_instance_n34, ID_EX_REGA_REG_instance_n34,
ID_EX_IMM16_EXT_REG_instance_n34, n1591, n1592, n1593, n1594, n1595,
n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605,
n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615,
n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625,
n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635,
n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645,
n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655,
n1656, n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665,
n1666, n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675,
n1676, n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685,
n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695,
n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705,
n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715,
n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725,
n1726, n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735,
n1736, n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745,
n1746, n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755,
n1756, n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765,
n1766, n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775,
n1776, n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785,
n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795,
n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805,
n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815,
n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825,
n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835,
n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845,
n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855,
n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865,
n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875,
n1876, n1877, n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885,
n1886, n1887, n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895,
n1896, n1897, n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905,
n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915,
n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925,
n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935,
n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945,
n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955,
n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965,
n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975,
n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985,
n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995,
n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005,
n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015,
n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025,
n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035,
n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045,
n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055,
n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065,
n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075,
n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085,
n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095,
n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105,
n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115,
n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125,
n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135,
n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145,
n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153, n2154, n2155,
n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163, n2164, n2165,
n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173, n2174, n2175,
n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183, n2184, n2185,
n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193, n2194, n2195,
n2196, n2197 : std_logic;
begin
PORT_PC <= ( PORT_PC_31_port, PORT_PC_30_port, PORT_PC_29_port,
PORT_PC_28_port, PORT_PC_27_port, PORT_PC_26_port, PORT_PC_25_port,
PORT_PC_24_port, PORT_PC_23_port, PORT_PC_22_port, PORT_PC_21_port,
PORT_PC_20_port, PORT_PC_19_port, PORT_PC_18_port, PORT_PC_17_port,
PORT_PC_16_port, PORT_PC_15_port, PORT_PC_14_port, PORT_PC_13_port,
PORT_PC_12_port, PORT_PC_11_port, PORT_PC_10_port, PORT_PC_9_port,
PORT_PC_8_port, PORT_PC_7_port, PORT_PC_6_port, PORT_PC_5_port,
PORT_PC_4_port, PORT_PC_3_port, PORT_PC_2_port, IF_PC_INC_1_port,
IF_PC_INC_0_port );
PORT_ALU <= ( PORT_ALU_31_port, PORT_ALU_30_port, PORT_ALU_29_port,
PORT_ALU_28_port, PORT_ALU_27_port, PORT_ALU_26_port, PORT_ALU_25_port,
PORT_ALU_24_port, PORT_ALU_23_port, PORT_ALU_22_port, PORT_ALU_21_port,
PORT_ALU_20_port, PORT_ALU_19_port, PORT_ALU_18_port, PORT_ALU_17_port,
PORT_ALU_16_port, PORT_ALU_15_port, PORT_ALU_14_port, PORT_ALU_13_port,
PORT_ALU_12_port, PORT_ALU_11_port, PORT_ALU_10_port, PORT_ALU_9_port,
PORT_ALU_8_port, PORT_ALU_7_port, PORT_ALU_6_port, PORT_ALU_5_port,
PORT_ALU_4_port, PORT_ALU_3_port, PORT_ALU_2_port, PORT_ALU_1_port,
PORT_ALU_0_port );
PORT_R_W <= PORT_R_W_port;
RF_ENABLE <= X_Logic1_port;
RF_WR <= RF_WR_port;
RF_ADD_WR <= ( RF_ADD_WR_4_port, RF_ADD_WR_3_port, RF_ADD_WR_2_port,
RF_ADD_WR_1_port, RF_ADD_WR_0_port );
RF_ADD_RD1 <= ( RF_ADD_RD1_4_port, RF_ADD_RD1_3_port, RF_ADD_RD1_2_port,
RF_ADD_RD1_1_port, RF_ADD_RD1_0_port );
RF_ADD_RD2 <= ( RF_ADD_RD2_4_port, RF_ADD_RD2_3_port, RF_ADD_RD2_2_port,
RF_ADD_RD2_1_port, RF_ADD_RD2_0_port );
X_Logic1_port <= '1';
n686 <= '1';
ID_HAZARD_MEM_reg : TLATXL port map( G => N4716, D => N4710, Q => n2108, QN
=> n319);
ID_HAZARD_WB_reg : TLATXL port map( G => N4717, D => N4708, Q => n2107, QN
=> n320);
ID_HAZARD_EX_reg : TLATXL port map( G => N4717, D => N4712, Q => n2106, QN
=> n321);
MEM_WB_INSTR_REG_instance_Q_reg_16_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => MEM_INSTR_16_port, E
=> X_Logic1_port, CK => CLOCK, Q => WB_INSTR_16_port
, QN => n2105);
MEM_WB_INSTR_REG_instance_Q_reg_17_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => MEM_INSTR_17_port,
E => X_Logic1_port, CK => CLOCK, Q =>
WB_INSTR_17_port, QN => n2104);
MEM_WB_INSTR_REG_instance_Q_reg_18_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => MEM_INSTR_18_port,
E => X_Logic1_port, CK => CLOCK, Q =>
WB_INSTR_18_port, QN => n2103);
MEM_WB_INSTR_REG_instance_Q_reg_19_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => MEM_INSTR_19_port
, E => X_Logic1_port, CK => CLOCK, Q =>
WB_INSTR_19_port, QN => n2102);
MEM_WB_INSTR_REG_instance_Q_reg_20_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
MEM_INSTR_20_port, E => X_Logic1_port, CK => CLOCK,
Q => WB_INSTR_20_port, QN => n2101);
MEM_WB_DATA_RAM_REG_instance_Q_reg_16_inst : EDFFTRXL port map( RN =>
PC_instance_n33, D => PORT_DATA_RAM(16), E =>
X_Logic1_port, CK => CLOCK, Q => WB_DATA_RAM_16_port
, QN => n2100);
MEM_WB_DATA_RAM_REG_instance_Q_reg_17_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
PORT_DATA_RAM(17), E => X_Logic1_port, CK => CLOCK,
Q => WB_DATA_RAM_17_port, QN => n2099);
MEM_WB_DATA_RAM_REG_instance_Q_reg_18_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => PORT_DATA_RAM(18),
E => X_Logic1_port, CK => CLOCK, Q =>
WB_DATA_RAM_18_port, QN => n2098);
MEM_WB_DATA_RAM_REG_instance_Q_reg_19_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => PORT_DATA_RAM(19),
E => X_Logic1_port, CK => CLOCK, Q =>
WB_DATA_RAM_19_port, QN => n2097);
MEM_WB_DATA_RAM_REG_instance_Q_reg_20_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
PORT_DATA_RAM(20), E => X_Logic1_port, CK => CLOCK,
Q => WB_DATA_RAM_20_port, QN => n2096);
MEM_WB_DATA_RAM_REG_instance_Q_reg_21_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => PORT_DATA_RAM(21), E
=> X_Logic1_port, CK => CLOCK, Q =>
WB_DATA_RAM_21_port, QN => n2095);
MEM_WB_DATA_RAM_REG_instance_Q_reg_22_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => PORT_DATA_RAM(22)
, E => X_Logic1_port, CK => CLOCK, Q =>
WB_DATA_RAM_22_port, QN => n2094);
MEM_WB_DATA_RAM_REG_instance_Q_reg_23_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => PORT_DATA_RAM(23),
E => X_Logic1_port, CK => CLOCK, Q =>
WB_DATA_RAM_23_port, QN => n2093);
MEM_WB_DATA_RAM_REG_instance_Q_reg_24_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_DATA_RAM(24),
E => X_Logic1_port, CK => CLOCK, Q =>
WB_DATA_RAM_24_port, QN => n2092);
MEM_WB_DATA_RAM_REG_instance_Q_reg_25_inst : EDFFTRXL port map( RN =>
PC_instance_n33, D => PORT_DATA_RAM(25), E =>
X_Logic1_port, CK => CLOCK, Q => WB_DATA_RAM_25_port
, QN => n2091);
MEM_WB_DATA_RAM_REG_instance_Q_reg_26_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_DATA_RAM(26),
E => X_Logic1_port, CK => CLOCK, Q =>
WB_DATA_RAM_26_port, QN => n2090);
MEM_WB_DATA_RAM_REG_instance_Q_reg_27_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
PORT_DATA_RAM(27), E => X_Logic1_port, CK => CLOCK,
Q => WB_DATA_RAM_27_port, QN => n2089);
MEM_WB_DATA_RAM_REG_instance_Q_reg_28_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => PORT_DATA_RAM(28),
E => X_Logic1_port, CK => CLOCK, Q =>
WB_DATA_RAM_28_port, QN => n2088);
MEM_WB_DATA_RAM_REG_instance_Q_reg_29_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => PORT_DATA_RAM(29),
E => X_Logic1_port, CK => CLOCK, Q =>
WB_DATA_RAM_29_port, QN => n2087);
MEM_WB_DATA_RAM_REG_instance_Q_reg_30_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_DATA_RAM(30),
E => X_Logic1_port, CK => CLOCK, Q =>
WB_DATA_RAM_30_port, QN => n2086);
MEM_WB_DATA_RAM_REG_instance_Q_reg_31_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => PORT_DATA_RAM(31), E
=> X_Logic1_port, CK => CLOCK, Q =>
WB_DATA_RAM_31_port, QN => n2085);
MEM_WB_DATA_RAM_REG_instance_Q_reg_0_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => PORT_DATA_RAM(0),
E => X_Logic1_port, CK => CLOCK, Q =>
WB_DATA_RAM_0_port, QN => n2084);
MEM_WB_DATA_RAM_REG_instance_Q_reg_1_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => PORT_DATA_RAM(1),
E => X_Logic1_port, CK => CLOCK, Q =>
WB_DATA_RAM_1_port, QN => n2083);
MEM_WB_DATA_RAM_REG_instance_Q_reg_2_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => PORT_DATA_RAM(2),
E => X_Logic1_port, CK => CLOCK, Q =>
WB_DATA_RAM_2_port, QN => n2082);
MEM_WB_DATA_RAM_REG_instance_Q_reg_3_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => PORT_DATA_RAM(3),
E => X_Logic1_port, CK => CLOCK, Q =>
WB_DATA_RAM_3_port, QN => n2081);
MEM_WB_DATA_RAM_REG_instance_Q_reg_4_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => PORT_DATA_RAM(4), E
=> X_Logic1_port, CK => CLOCK, Q =>
WB_DATA_RAM_4_port, QN => n2080);
MEM_WB_DATA_RAM_REG_instance_Q_reg_5_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => PORT_DATA_RAM(5),
E => X_Logic1_port, CK => CLOCK, Q =>
WB_DATA_RAM_5_port, QN => n2079);
MEM_WB_DATA_RAM_REG_instance_Q_reg_6_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => PORT_DATA_RAM(6),
E => X_Logic1_port, CK => CLOCK, Q =>
WB_DATA_RAM_6_port, QN => n2078);
MEM_WB_ALU_REG_instance_Q_reg_0_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_ALU_0_port, E
=> X_Logic1_port, CK => CLOCK, Q => WB_ALU_0_port,
QN => n2077);
MEM_WB_ALU_REG_instance_Q_reg_1_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_ALU_1_port, E
=> X_Logic1_port, CK => CLOCK, Q => WB_ALU_1_port,
QN => n2076);
MEM_WB_ALU_REG_instance_Q_reg_2_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_ALU_2_port, E
=> X_Logic1_port, CK => CLOCK, Q => WB_ALU_2_port,
QN => n2075);
MEM_WB_ALU_REG_instance_Q_reg_3_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_ALU_3_port, E
=> X_Logic1_port, CK => CLOCK, Q => WB_ALU_3_port,
QN => n2074);
MEM_WB_ALU_REG_instance_Q_reg_4_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_ALU_4_port, E
=> X_Logic1_port, CK => CLOCK, Q => WB_ALU_4_port,
QN => n2073);
MEM_WB_ALU_REG_instance_Q_reg_5_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_ALU_5_port, E
=> X_Logic1_port, CK => CLOCK, Q => WB_ALU_5_port,
QN => n2072);
MEM_WB_ALU_REG_instance_Q_reg_6_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_ALU_6_port, E
=> X_Logic1_port, CK => CLOCK, Q => WB_ALU_6_port,
QN => n2071);
MEM_WB_DATA_RAM_REG_instance_Q_reg_7_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_DATA_RAM(7),
E => X_Logic1_port, CK => CLOCK, Q =>
WB_DATA_RAM_7_port, QN => n2070);
MEM_WB_DATA_RAM_REG_instance_Q_reg_8_inst : EDFFTRXL port map( RN =>
PC_instance_n33, D => PORT_DATA_RAM(8), E =>
X_Logic1_port, CK => CLOCK, Q => WB_DATA_RAM_8_port,
QN => n2069);
MEM_WB_DATA_RAM_REG_instance_Q_reg_9_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => PORT_DATA_RAM(9),
E => X_Logic1_port, CK => CLOCK, Q =>
WB_DATA_RAM_9_port, QN => n2068);
MEM_WB_DATA_RAM_REG_instance_Q_reg_10_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => PORT_DATA_RAM(10),
E => X_Logic1_port, CK => CLOCK, Q =>
WB_DATA_RAM_10_port, QN => n2067);
MEM_WB_DATA_RAM_REG_instance_Q_reg_11_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => PORT_DATA_RAM(11),
E => X_Logic1_port, CK => CLOCK, Q =>
WB_DATA_RAM_11_port, QN => n2066);
MEM_WB_DATA_RAM_REG_instance_Q_reg_12_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => PORT_DATA_RAM(12), E
=> X_Logic1_port, CK => CLOCK, Q =>
WB_DATA_RAM_12_port, QN => n2065);
MEM_WB_DATA_RAM_REG_instance_Q_reg_13_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => PORT_DATA_RAM(13)
, E => X_Logic1_port, CK => CLOCK, Q =>
WB_DATA_RAM_13_port, QN => n2064);
MEM_WB_DATA_RAM_REG_instance_Q_reg_14_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => PORT_DATA_RAM(14),
E => X_Logic1_port, CK => CLOCK, Q =>
WB_DATA_RAM_14_port, QN => n2063);
MEM_WB_DATA_RAM_REG_instance_Q_reg_15_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_DATA_RAM(15),
E => X_Logic1_port, CK => CLOCK, Q =>
WB_DATA_RAM_15_port, QN => n2062);
MEM_WB_ALU_REG_instance_Q_reg_7_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_ALU_7_port, E
=> X_Logic1_port, CK => CLOCK, Q => WB_ALU_7_port,
QN => n2061);
MEM_WB_ALU_REG_instance_Q_reg_8_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_ALU_8_port, E
=> X_Logic1_port, CK => CLOCK, Q => WB_ALU_8_port,
QN => n2060);
MEM_WB_ALU_REG_instance_Q_reg_9_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_ALU_9_port, E
=> X_Logic1_port, CK => CLOCK, Q => WB_ALU_9_port,
QN => n2059);
MEM_WB_ALU_REG_instance_Q_reg_10_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_ALU_10_port,
E => X_Logic1_port, CK => CLOCK, Q => WB_ALU_10_port
, QN => n2058);
MEM_WB_ALU_REG_instance_Q_reg_11_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_ALU_11_port,
E => X_Logic1_port, CK => CLOCK, Q => WB_ALU_11_port
, QN => n2057);
MEM_WB_ALU_REG_instance_Q_reg_12_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_ALU_12_port,
E => X_Logic1_port, CK => CLOCK, Q => WB_ALU_12_port
, QN => n2056);
MEM_WB_ALU_REG_instance_Q_reg_13_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_ALU_13_port,
E => X_Logic1_port, CK => CLOCK, Q => WB_ALU_13_port
, QN => n2055);
MEM_WB_ALU_REG_instance_Q_reg_14_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_ALU_14_port,
E => X_Logic1_port, CK => CLOCK, Q => WB_ALU_14_port
, QN => n2054);
MEM_WB_ALU_REG_instance_Q_reg_15_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_ALU_15_port,
E => X_Logic1_port, CK => CLOCK, Q => WB_ALU_15_port
, QN => n2053);
MEM_WB_ALU_REG_instance_Q_reg_16_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_ALU_16_port,
E => X_Logic1_port, CK => CLOCK, Q => WB_ALU_16_port
, QN => n2052);
MEM_WB_ALU_REG_instance_Q_reg_17_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_ALU_17_port,
E => X_Logic1_port, CK => CLOCK, Q => WB_ALU_17_port
, QN => n2051);
MEM_WB_ALU_REG_instance_Q_reg_18_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_ALU_18_port,
E => X_Logic1_port, CK => CLOCK, Q => WB_ALU_18_port
, QN => n2050);
MEM_WB_ALU_REG_instance_Q_reg_19_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_ALU_19_port,
E => X_Logic1_port, CK => CLOCK, Q => WB_ALU_19_port
, QN => n2049);
MEM_WB_ALU_REG_instance_Q_reg_20_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_ALU_20_port,
E => X_Logic1_port, CK => CLOCK, Q => WB_ALU_20_port
, QN => n2048);
MEM_WB_ALU_REG_instance_Q_reg_21_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_ALU_21_port,
E => X_Logic1_port, CK => CLOCK, Q => WB_ALU_21_port
, QN => n2047);
MEM_WB_ALU_REG_instance_Q_reg_22_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_ALU_22_port,
E => X_Logic1_port, CK => CLOCK, Q => WB_ALU_22_port
, QN => n2046);
MEM_WB_ALU_REG_instance_Q_reg_23_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_ALU_23_port,
E => X_Logic1_port, CK => CLOCK, Q => WB_ALU_23_port
, QN => n2045);
MEM_WB_ALU_REG_instance_Q_reg_24_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_ALU_24_port,
E => X_Logic1_port, CK => CLOCK, Q => WB_ALU_24_port
, QN => n2044);
MEM_WB_ALU_REG_instance_Q_reg_25_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_ALU_25_port,
E => X_Logic1_port, CK => CLOCK, Q => WB_ALU_25_port
, QN => n2043);
MEM_WB_ALU_REG_instance_Q_reg_26_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_ALU_26_port,
E => X_Logic1_port, CK => CLOCK, Q => WB_ALU_26_port
, QN => n2042);
MEM_WB_ALU_REG_instance_Q_reg_27_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_ALU_27_port,
E => X_Logic1_port, CK => CLOCK, Q => WB_ALU_27_port
, QN => n2041);
MEM_WB_ALU_REG_instance_Q_reg_28_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_ALU_28_port,
E => X_Logic1_port, CK => CLOCK, Q => WB_ALU_28_port
, QN => n2040);
MEM_WB_ALU_REG_instance_Q_reg_29_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_ALU_29_port,
E => X_Logic1_port, CK => CLOCK, Q => WB_ALU_29_port
, QN => n2039);
MEM_WB_ALU_REG_instance_Q_reg_30_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_ALU_30_port,
E => X_Logic1_port, CK => CLOCK, Q => WB_ALU_30_port
, QN => n2038);
MEM_WB_ALU_REG_instance_Q_reg_31_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_ALU_31_port,
E => X_Logic1_port, CK => CLOCK, Q => WB_ALU_31_port
, QN => n2037);
MEM_WB_INSTR_REG_instance_Q_reg_4_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => MEM_INSTR_4_port,
E => X_Logic1_port, CK => CLOCK, Q =>
WB_INSTR_4_port, QN => n2036);
MEM_WB_INSTR_REG_instance_Q_reg_5_inst : EDFFTRXL port map( RN =>
PC_instance_n33, D => MEM_INSTR_5_port, E =>
X_Logic1_port, CK => CLOCK, Q => WB_INSTR_5_port, QN
=> n2035);
MEM_WB_INSTR_REG_instance_Q_reg_6_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
MEM_INSTR_6_port, E => X_Logic1_port, CK => CLOCK, Q
=> WB_INSTR_6_port, QN => n2034);
MEM_WB_INSTR_REG_instance_Q_reg_9_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => MEM_INSTR_9_port,
E => X_Logic1_port, CK => CLOCK, Q =>
WB_INSTR_9_port, QN => n2033);
MEM_WB_INSTR_REG_instance_Q_reg_8_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => MEM_INSTR_8_port,
E => X_Logic1_port, CK => CLOCK, Q =>
WB_INSTR_8_port, QN => n2032);
MEM_WB_INSTR_REG_instance_Q_reg_10_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => MEM_INSTR_10_port, E
=> X_Logic1_port, CK => CLOCK, Q => WB_INSTR_10_port
, QN => n2031);
MEM_WB_INSTR_REG_instance_Q_reg_7_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => MEM_INSTR_7_port,
E => X_Logic1_port, CK => CLOCK, Q =>
WB_INSTR_7_port, QN => n2030);
MEM_WB_INSTR_REG_instance_Q_reg_0_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => MEM_INSTR_0_port,
E => X_Logic1_port, CK => CLOCK, Q =>
WB_INSTR_0_port, QN => n2029);
MEM_WB_INSTR_REG_instance_Q_reg_11_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => MEM_INSTR_11_port,
E => X_Logic1_port, CK => CLOCK, Q =>
WB_INSTR_11_port, QN => n2028);
MEM_WB_INSTR_REG_instance_Q_reg_12_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => MEM_INSTR_12_port,
E => X_Logic1_port, CK => CLOCK, Q =>
WB_INSTR_12_port, QN => n2027);
MEM_WB_INSTR_REG_instance_Q_reg_13_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => MEM_INSTR_13_port
, E => X_Logic1_port, CK => CLOCK, Q =>
WB_INSTR_13_port, QN => n2026);
MEM_WB_INSTR_REG_instance_Q_reg_14_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => MEM_INSTR_14_port,
E => X_Logic1_port, CK => CLOCK, Q =>
WB_INSTR_14_port, QN => n2025);
MEM_WB_INSTR_REG_instance_Q_reg_15_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => MEM_INSTR_15_port
, E => X_Logic1_port, CK => CLOCK, Q =>
WB_INSTR_15_port, QN => n2024);
MEM_WB_INSTR_REG_instance_Q_reg_1_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => MEM_INSTR_1_port, E
=> X_Logic1_port, CK => CLOCK, Q => WB_INSTR_1_port,
QN => n2023);
MEM_WB_INSTR_REG_instance_Q_reg_3_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => MEM_INSTR_3_port,
E => X_Logic1_port, CK => CLOCK, Q =>
WB_INSTR_3_port, QN => n2022);
MEM_WB_INSTR_REG_instance_Q_reg_2_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => MEM_INSTR_2_port,
E => X_Logic1_port, CK => CLOCK, Q =>
WB_INSTR_2_port, QN => n2021);
PC_instance_Q_reg_0_inst : EDFFTRXL port map( RN => PC_instance_n33, D =>
N730, E => n2157, CK => n1628, Q => IF_PC_INC_0_port
, QN => n2020);
PC_instance_Q_reg_1_inst : EDFFTRXL port map( RN => PC_instance_n33, D =>
N731, E => n2157, CK => n1628, Q => IF_PC_INC_1_port
, QN => n2019);
IF_ID_PC_REG_instance_Q_reg_0_inst : EDFFTRXL port map( RN =>
PC_instance_n33, D => IF_PC_INC_0_port, E => n2156,
CK => n1628, Q => ID_PC_SUM_0_port, QN => n2018);
IF_ID_PC_REG_instance_Q_reg_1_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => IF_PC_INC_1_port, E
=> n2156, CK => n1628, Q => ID_PC_SUM_1_port, QN =>
n2017);
ID_EX_INSTR_REG_instance_Q_reg_14_inst : EDFFTRXL port map( RN =>
ID_EX_INSTR_REG_instance_n34, D =>
ID_INSTR_AFTER_CU_14_port, E => n686, CK => CLOCK, Q
=> EX_INSTR_14_port, QN => n2016);
ID_EX_INSTR_REG_instance_Q_reg_11_inst : EDFFTRXL port map( RN =>
ID_EX_INSTR_REG_instance_n34, D =>
ID_INSTR_AFTER_CU_11_port, E => n686, CK => CLOCK, Q
=> EX_INSTR_11_port, QN => n2015);
ID_EX_INSTR_REG_instance_Q_reg_16_inst : EDFFTRXL port map( RN =>
ID_EX_INSTR_REG_instance_n34, D =>
ID_INSTR_AFTER_CU_16_port, E => n686, CK => CLOCK, Q
=> EX_INSTR_16_port, QN => n2014);
EX_MEM_INSTR_REG_instance_Q_reg_14_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => EX_INSTR_14_port,
E => n686, CK => CLOCK, Q => MEM_INSTR_14_port, QN
=> n2013);
EX_MEM_INSTR_REG_instance_Q_reg_11_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => EX_INSTR_11_port, E
=> n686, CK => CLOCK, Q => MEM_INSTR_11_port, QN =>
n2012);
IF_ID_PC_REG_instance_Q_reg_31_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => PORT_PC_31_port,
E => n2155, CK => n1628, Q => ID_PC_31_port, QN =>
n2011);
ID_EX_INSTR_REG_instance_Q_reg_19_inst : EDFFTRXL port map( RN =>
ID_EX_INSTR_REG_instance_n34, D =>
ID_INSTR_AFTER_CU_19_port, E => n686, CK => CLOCK, Q
=> EX_INSTR_19_port, QN => n2010);
IF_ID_PC_REG_instance_Q_reg_24_inst : EDFFTRXL port map( RN =>
PC_instance_n33, D => PORT_PC_24_port, E => n2156,
CK => n1628, Q => ID_PC_24_port, QN => n2009);
IF_ID_PC_REG_instance_Q_reg_25_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => PORT_PC_25_port, E
=> n2156, CK => n1628, Q => ID_PC_25_port, QN =>
n2008);
PC_instance_Q_reg_31_inst : EDFFTRXL port map( RN => PC_instance_n33, D =>
N761, E => n2155, CK => n1628, Q => PORT_PC_31_port,
QN => n2007);
EX_MEM_INSTR_REG_instance_Q_reg_19_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => EX_INSTR_19_port,
E => n686, CK => CLOCK, Q => MEM_INSTR_19_port, QN
=> n2006);
EX_MEM_INSTR_REG_instance_Q_reg_16_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => EX_INSTR_16_port,
E => n686, CK => CLOCK, Q => MEM_INSTR_16_port, QN
=> n2005);
ID_EX_INSTR_REG_instance_Q_reg_12_inst : EDFFTRXL port map( RN =>
ID_EX_INSTR_REG_instance_n34, D =>
ID_INSTR_AFTER_CU_12_port, E => n686, CK => CLOCK, Q
=> EX_INSTR_12_port, QN => n2004);
EX_MEM_INSTR_REG_instance_Q_reg_12_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => EX_INSTR_12_port,
E => n686, CK => CLOCK, Q => MEM_INSTR_12_port, QN
=> n2003);
ID_EX_INSTR_REG_instance_Q_reg_15_inst : EDFFTRXL port map( RN =>
ID_EX_INSTR_REG_instance_n34, D =>
ID_INSTR_AFTER_CU_15_port, E => n686, CK => CLOCK, Q
=> EX_INSTR_15_port, QN => n2002);
ID_EX_INSTR_REG_instance_Q_reg_17_inst : EDFFTRXL port map( RN =>
ID_EX_INSTR_REG_instance_n34, D =>
ID_INSTR_AFTER_CU_17_port, E => n686, CK => CLOCK, Q
=> EX_INSTR_17_port, QN => n2001);
ID_EX_INSTR_REG_instance_Q_reg_13_inst : EDFFTRXL port map( RN =>
ID_EX_INSTR_REG_instance_n34, D =>
ID_INSTR_AFTER_CU_13_port, E => n686, CK => CLOCK, Q
=> EX_INSTR_13_port, QN => n2000);
ID_EX_INSTR_REG_instance_Q_reg_18_inst : EDFFTRXL port map( RN =>
ID_EX_INSTR_REG_instance_n34, D =>
ID_INSTR_AFTER_CU_18_port, E => n686, CK => CLOCK, Q
=> EX_INSTR_18_port, QN => n1999);
EX_MEM_INSTR_REG_instance_Q_reg_15_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => EX_INSTR_15_port,
E => n686, CK => CLOCK, Q => MEM_INSTR_15_port, QN
=> n1998);
EX_MEM_INSTR_REG_instance_Q_reg_13_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
EX_INSTR_13_port, E => n686, CK => CLOCK, Q =>
MEM_INSTR_13_port, QN => n1997);
IF_ID_PC_REG_instance_Q_reg_26_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => PORT_PC_26_port,
E => n2156, CK => n1628, Q => ID_PC_26_port, QN =>
n1996);
IF_ID_PC_REG_instance_Q_reg_27_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_PC_27_port, E
=> n2155, CK => n1628, Q => ID_PC_27_port, QN =>
n1995);
IF_ID_PC_REG_instance_Q_reg_28_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => PORT_PC_28_port, E
=> n2155, CK => n1628, Q => ID_PC_28_port, QN =>
n1994);
IF_ID_PC_REG_instance_Q_reg_29_inst : EDFFTRXL port map( RN =>
PC_instance_n33, D => PORT_PC_29_port, E => n2155,
CK => n1628, Q => ID_PC_29_port, QN => n1993);
IF_ID_PC_REG_instance_Q_reg_30_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => PORT_PC_30_port, E
=> n2155, CK => n1628, Q => ID_PC_30_port, QN =>
n1992);
PC_instance_Q_reg_22_inst : EDFFTRXL port map( RN => PC_instance_n33, D =>
N752, E => n2157, CK => n1628, Q => PORT_PC_22_port,
QN => n1991);
PC_instance_Q_reg_23_inst : EDFFTRXL port map( RN => PC_instance_n33, D =>
N753, E => n2157, CK => n1628, Q => PORT_PC_23_port,
QN => n1990);
PC_instance_Q_reg_24_inst : EDFFTRXL port map( RN => PC_instance_n33, D =>
N754, E => n2157, CK => n1628, Q => PORT_PC_24_port,
QN => n1989);
PC_instance_Q_reg_25_inst : EDFFTRXL port map( RN => PC_instance_n33, D =>
N755, E => n2157, CK => n1628, Q => PORT_PC_25_port,
QN => n1988);
PC_instance_Q_reg_26_inst : EDFFTRXL port map( RN => PC_instance_n33, D =>
N756, E => n2157, CK => n1628, Q => PORT_PC_26_port,
QN => n1987);
PC_instance_Q_reg_27_inst : EDFFTRXL port map( RN => PC_instance_n33, D =>
N757, E => n2157, CK => n1628, Q => PORT_PC_27_port,
QN => n1986);
PC_instance_Q_reg_28_inst : EDFFTRXL port map( RN => PC_instance_n33, D =>
N758, E => n2157, CK => n1628, Q => PORT_PC_28_port,
QN => n1985);
PC_instance_Q_reg_29_inst : EDFFTRXL port map( RN => PC_instance_n33, D =>
N759, E => n2157, CK => n1628, Q => PORT_PC_29_port,
QN => n1984);
PC_instance_Q_reg_30_inst : EDFFTRXL port map( RN => PC_instance_n33, D =>
N760, E => n2157, CK => n1628, Q => PORT_PC_30_port,
QN => n1983);
ID_EX_INSTR_REG_instance_Q_reg_20_inst : EDFFTRXL port map( RN =>
ID_EX_INSTR_REG_instance_n34, D =>
ID_INSTR_AFTER_CU_20_port, E => n686, CK => CLOCK, Q
=> EX_INSTR_20_port, QN => n1982);
EX_MEM_INSTR_REG_instance_Q_reg_20_inst : EDFFTRXL port map( RN =>
PC_instance_n33, D => EX_INSTR_20_port, E => n686,
CK => CLOCK, Q => MEM_INSTR_20_port, QN => n1981);
EX_MEM_INSTR_REG_instance_Q_reg_17_inst : EDFFTRXL port map( RN =>
PC_instance_n33, D => EX_INSTR_17_port, E => n686,
CK => CLOCK, Q => MEM_INSTR_17_port, QN => n1980);
EX_MEM_INSTR_REG_instance_Q_reg_18_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
EX_INSTR_18_port, E => n686, CK => CLOCK, Q =>
MEM_INSTR_18_port, QN => n1979);
EX_MEM_INSTR_REG_instance_Q_reg_28_inst : EDFFTRXL port map( RN =>
PC_instance_n33, D => EX_INSTR_28_port, E => n686,
CK => CLOCK, Q => MEM_INSTR_28_port, QN => n1978);
EX_MEM_INSTR_REG_instance_Q_reg_30_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => EX_INSTR_30_port,
E => n686, CK => CLOCK, Q => MEM_INSTR_30_port, QN
=> n1977);
IF_ID_INSTR_REG_instance_Q_reg_21_inst : EDFFTRXL port map( RN =>
PC_instance_n33, D => N785, E => n2156, CK => n1628,
Q => RF_ADD_RD1_0_port, QN => n1976);
EX_MEM_INSTR_REG_instance_Q_reg_26_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => EX_INSTR_26_port,
E => n686, CK => CLOCK, Q => MEM_INSTR_26_port, QN
=> n1975);
ID_EX_REGA_REG_instance_Q_reg_16_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => RF_OUT1(16), E =>
n686, CK => CLOCK, Q => EX_REGA_16_port, QN => n1974
);
ID_EX_REGA_REG_instance_Q_reg_17_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => RF_OUT1(17), E =>
n686, CK => CLOCK, Q => EX_REGA_17_port, QN => n1973
);
ID_EX_REGA_REG_instance_Q_reg_18_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => RF_OUT1(18), E =>
n686, CK => CLOCK, Q => EX_REGA_18_port, QN => n1972
);
ID_EX_REGA_REG_instance_Q_reg_19_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => RF_OUT1(19), E =>
n686, CK => CLOCK, Q => EX_REGA_19_port, QN => n1971
);
ID_EX_REGA_REG_instance_Q_reg_20_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => RF_OUT1(20), E =>
n686, CK => CLOCK, Q => EX_REGA_20_port, QN => n1970
);
ID_EX_REGA_REG_instance_Q_reg_21_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => RF_OUT1(21), E =>
n686, CK => CLOCK, Q => EX_REGA_21_port, QN => n1969
);
ID_EX_REGA_REG_instance_Q_reg_22_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => RF_OUT1(22), E =>
n686, CK => CLOCK, Q => EX_REGA_22_port, QN => n1968
);
ID_EX_REGA_REG_instance_Q_reg_23_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => RF_OUT1(23), E =>
n686, CK => CLOCK, Q => EX_REGA_23_port, QN => n1967
);
ID_EX_REGA_REG_instance_Q_reg_24_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => RF_OUT1(24), E =>
n686, CK => CLOCK, Q => EX_REGA_24_port, QN => n1966
);
ID_EX_REGA_REG_instance_Q_reg_25_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => RF_OUT1(25), E =>
n686, CK => CLOCK, Q => EX_REGA_25_port, QN => n1965
);
ID_EX_REGA_REG_instance_Q_reg_26_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => RF_OUT1(26), E =>
n686, CK => CLOCK, Q => EX_REGA_26_port, QN => n1964
);
ID_EX_REGA_REG_instance_Q_reg_27_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => RF_OUT1(27), E =>
n686, CK => CLOCK, Q => EX_REGA_27_port, QN => n1963
);
ID_EX_REGA_REG_instance_Q_reg_28_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => RF_OUT1(28), E =>
n686, CK => CLOCK, Q => EX_REGA_28_port, QN => n1962
);
ID_EX_REGA_REG_instance_Q_reg_29_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => RF_OUT1(29), E =>
n686, CK => CLOCK, Q => EX_REGA_29_port, QN => n1961
);
ID_EX_REGA_REG_instance_Q_reg_30_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => RF_OUT1(30), E =>
n686, CK => CLOCK, Q => EX_REGA_30_port, QN => n1960
);
ID_EX_REGA_REG_instance_Q_reg_31_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => RF_OUT1(31), E =>
n686, CK => CLOCK, Q => EX_REGA_31_port, QN => n1959
);
ID_EX_PC_REG_instance_Q_reg_16_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => ID_PC_16_port, E =>
n686, CK => CLOCK, Q => EX_PC_16_port, QN => n1958);
ID_EX_PC_REG_instance_Q_reg_17_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => ID_PC_17_port, E =>
n686, CK => CLOCK, Q => EX_PC_17_port, QN => n1957);
ID_EX_PC_REG_instance_Q_reg_18_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => ID_PC_18_port, E =>
n686, CK => CLOCK, Q => EX_PC_18_port, QN => n1956);
ID_EX_PC_REG_instance_Q_reg_19_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => ID_PC_19_port, E =>
n686, CK => CLOCK, Q => EX_PC_19_port, QN => n1955);
ID_EX_PC_REG_instance_Q_reg_20_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => ID_PC_20_port, E =>
n686, CK => CLOCK, Q => EX_PC_20_port, QN => n1954);
ID_EX_PC_REG_instance_Q_reg_21_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => ID_PC_21_port, E =>
n686, CK => CLOCK, Q => EX_PC_21_port, QN => n1953);
ID_EX_PC_REG_instance_Q_reg_22_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => ID_PC_22_port, E =>
n686, CK => CLOCK, Q => EX_PC_22_port, QN => n1952);
ID_EX_PC_REG_instance_Q_reg_23_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => ID_PC_23_port, E =>
n686, CK => CLOCK, Q => EX_PC_23_port, QN => n1951);
ID_EX_PC_REG_instance_Q_reg_24_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => ID_PC_24_port, E =>
n686, CK => CLOCK, Q => EX_PC_24_port, QN => n1950);
ID_EX_PC_REG_instance_Q_reg_25_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => ID_PC_25_port, E =>
n686, CK => CLOCK, Q => EX_PC_25_port, QN => n1949);
ID_EX_PC_REG_instance_Q_reg_26_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => ID_PC_26_port, E =>
n686, CK => CLOCK, Q => EX_PC_26_port, QN => n1948);
ID_EX_PC_REG_instance_Q_reg_27_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => ID_PC_27_port, E =>
n686, CK => CLOCK, Q => EX_PC_27_port, QN => n1947);
ID_EX_PC_REG_instance_Q_reg_28_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => ID_PC_28_port, E =>
n686, CK => CLOCK, Q => EX_PC_28_port, QN => n1946);
ID_EX_PC_REG_instance_Q_reg_29_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => ID_PC_29_port, E =>
n686, CK => CLOCK, Q => EX_PC_29_port, QN => n1945);
ID_EX_PC_REG_instance_Q_reg_30_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => ID_PC_30_port, E =>
n686, CK => CLOCK, Q => EX_PC_30_port, QN => n1944);
ID_EX_PC_REG_instance_Q_reg_31_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => ID_PC_31_port, E =>
n686, CK => CLOCK, Q => EX_PC_31_port, QN => n1943);
ID_EX_IMM16_EXT_REG_instance_Q_reg_16_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
ID_IMM16_EXT_31_port, E => n686, CK => CLOCK, Q =>
EX_IMM16_EXT_16_port, QN => n1676);
ID_EX_IMM16_EXT_REG_instance_Q_reg_17_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
ID_IMM16_EXT_31_port, E => n686, CK => CLOCK, Q =>
EX_IMM16_EXT_17_port, QN => n1675);
ID_EX_IMM16_EXT_REG_instance_Q_reg_18_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
ID_IMM16_EXT_31_port, E => n686, CK => CLOCK, Q =>
EX_IMM16_EXT_18_port, QN => n1674);
ID_EX_IMM16_EXT_REG_instance_Q_reg_19_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
ID_IMM16_EXT_31_port, E => n686, CK => CLOCK, Q =>
EX_IMM16_EXT_19_port, QN => n1673);
ID_EX_IMM16_EXT_REG_instance_Q_reg_20_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
ID_IMM16_EXT_31_port, E => n686, CK => CLOCK, Q =>
EX_IMM16_EXT_20_port, QN => n1672);
ID_EX_IMM16_EXT_REG_instance_Q_reg_21_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
ID_IMM16_EXT_31_port, E => n686, CK => CLOCK, Q =>
EX_IMM16_EXT_21_port, QN => n1671);
ID_EX_IMM16_EXT_REG_instance_Q_reg_22_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
ID_IMM16_EXT_31_port, E => n686, CK => CLOCK, Q =>
EX_IMM16_EXT_22_port, QN => n1942);
ID_EX_IMM16_EXT_REG_instance_Q_reg_23_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
ID_IMM16_EXT_31_port, E => n686, CK => CLOCK, Q =>
EX_IMM16_EXT_23_port, QN => n1941);
ID_EX_IMM16_EXT_REG_instance_Q_reg_24_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
ID_IMM16_EXT_31_port, E => n686, CK => CLOCK, Q =>
EX_IMM16_EXT_24_port, QN => n1940);
ID_EX_IMM16_EXT_REG_instance_Q_reg_25_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
ID_IMM16_EXT_31_port, E => n686, CK => CLOCK, Q =>
EX_IMM16_EXT_25_port, QN => n1939);
ID_EX_IMM16_EXT_REG_instance_Q_reg_26_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
ID_IMM16_EXT_31_port, E => n686, CK => CLOCK, Q =>
EX_IMM16_EXT_26_port, QN => n1938);
ID_EX_IMM16_EXT_REG_instance_Q_reg_27_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
ID_IMM16_EXT_31_port, E => n686, CK => CLOCK, Q =>
EX_IMM16_EXT_27_port, QN => n1937);
ID_EX_IMM16_EXT_REG_instance_Q_reg_28_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
ID_IMM16_EXT_31_port, E => n686, CK => CLOCK, Q =>
EX_IMM16_EXT_28_port, QN => n1936);
ID_EX_IMM16_EXT_REG_instance_Q_reg_29_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
ID_IMM16_EXT_31_port, E => n686, CK => CLOCK, Q =>
EX_IMM16_EXT_29_port, QN => n1935);
ID_EX_IMM16_EXT_REG_instance_Q_reg_30_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
ID_IMM16_EXT_31_port, E => n686, CK => CLOCK, Q =>
EX_IMM16_EXT_30_port, QN => n1934);
ID_EX_IMM16_EXT_REG_instance_Q_reg_31_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
ID_IMM16_EXT_31_port, E => n686, CK => CLOCK, Q =>
EX_IMM16_EXT_31_port, QN => n1693);
ID_EX_REGB_REG_instance_Q_reg_16_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => RF_OUT2(16), E =>
n686, CK => CLOCK, Q => EX_REGB_16_port, QN => n1933
);
ID_EX_REGB_REG_instance_Q_reg_17_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => RF_OUT2(17), E =>
n686, CK => CLOCK, Q => EX_REGB_17_port, QN => n1932
);
ID_EX_REGB_REG_instance_Q_reg_18_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => RF_OUT2(18), E =>
n686, CK => CLOCK, Q => EX_REGB_18_port, QN => n1931
);
ID_EX_REGB_REG_instance_Q_reg_19_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => RF_OUT2(19), E =>
n686, CK => CLOCK, Q => EX_REGB_19_port, QN => n1930
);
ID_EX_REGB_REG_instance_Q_reg_20_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => RF_OUT2(20), E =>
n686, CK => CLOCK, Q => EX_REGB_20_port, QN => n1929
);
ID_EX_REGB_REG_instance_Q_reg_21_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => RF_OUT2(21), E =>
n686, CK => CLOCK, Q => EX_REGB_21_port, QN => n1928
);
ID_EX_REGB_REG_instance_Q_reg_22_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => RF_OUT2(22), E =>
n686, CK => CLOCK, Q => EX_REGB_22_port, QN => n1927
);
ID_EX_REGB_REG_instance_Q_reg_23_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => RF_OUT2(23), E =>
n686, CK => CLOCK, Q => EX_REGB_23_port, QN => n1926
);
ID_EX_REGB_REG_instance_Q_reg_24_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => RF_OUT2(24), E =>
n686, CK => CLOCK, Q => EX_REGB_24_port, QN => n1925
);
ID_EX_REGB_REG_instance_Q_reg_25_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => RF_OUT2(25), E =>
n686, CK => CLOCK, Q => EX_REGB_25_port, QN => n1924
);
ID_EX_REGB_REG_instance_Q_reg_26_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => RF_OUT2(26), E =>
n686, CK => CLOCK, Q => EX_REGB_26_port, QN => n1923
);
ID_EX_REGB_REG_instance_Q_reg_27_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => RF_OUT2(27), E =>
n686, CK => CLOCK, Q => EX_REGB_27_port, QN => n1922
);
ID_EX_REGB_REG_instance_Q_reg_28_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => RF_OUT2(28), E =>
n686, CK => CLOCK, Q => EX_REGB_28_port, QN => n1921
);
ID_EX_REGB_REG_instance_Q_reg_29_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => RF_OUT2(29), E =>
n686, CK => CLOCK, Q => EX_REGB_29_port, QN => n1920
);
ID_EX_REGB_REG_instance_Q_reg_30_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => RF_OUT2(30), E =>
n686, CK => CLOCK, Q => EX_REGB_30_port, QN => n1919
);
ID_EX_REGB_REG_instance_Q_reg_31_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => RF_OUT2(31), E =>
n686, CK => CLOCK, Q => EX_REGB_31_port, QN => n1918
);
IF_ID_PC_REG_instance_Q_reg_9_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => PORT_PC_9_port, E =>
n2155, CK => n1628, Q => ID_PC_9_port, QN => n1917);
IF_ID_PC_REG_instance_Q_reg_10_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => PORT_PC_10_port,
E => n2155, CK => n1628, Q => ID_PC_10_port, QN =>
n1916);
IF_ID_PC_REG_instance_Q_reg_11_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => PORT_PC_11_port, E
=> n2155, CK => n1628, Q => ID_PC_11_port, QN =>
n1915);
IF_ID_PC_REG_instance_Q_reg_12_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => PORT_PC_12_port, E
=> n2155, CK => n1628, Q => ID_PC_12_port, QN =>
n1914);
IF_ID_PC_REG_instance_Q_reg_13_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
PORT_PC_13_port, E => n2155, CK => n1628, Q =>
ID_PC_13_port, QN => n1913);
IF_ID_PC_REG_instance_Q_reg_14_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_PC_14_port, E
=> n2155, CK => n1628, Q => ID_PC_14_port, QN =>
n1912);
IF_ID_PC_REG_instance_Q_reg_15_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => PORT_PC_15_port, E
=> n2155, CK => n1628, Q => ID_PC_15_port, QN =>
n1911);
IF_ID_PC_REG_instance_Q_reg_16_inst : EDFFTRXL port map( RN =>
PC_instance_n33, D => PORT_PC_16_port, E => n2155,
CK => n1628, Q => ID_PC_16_port, QN => n1910);
IF_ID_PC_REG_instance_Q_reg_17_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => PORT_PC_17_port, E
=> n2155, CK => n1628, Q => ID_PC_17_port, QN =>
n1909);
IF_ID_PC_REG_instance_Q_reg_18_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => PORT_PC_18_port,
E => n2155, CK => n1628, Q => ID_PC_18_port, QN =>
n1908);
IF_ID_PC_REG_instance_Q_reg_19_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => PORT_PC_19_port, E
=> n2155, CK => n1628, Q => ID_PC_19_port, QN =>
n1907);
IF_ID_PC_REG_instance_Q_reg_20_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => PORT_PC_20_port, E
=> n2155, CK => n1628, Q => ID_PC_20_port, QN =>
n1906);
IF_ID_PC_REG_instance_Q_reg_21_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
PORT_PC_21_port, E => n2155, CK => n1628, Q =>
ID_PC_21_port, QN => n1905);
IF_ID_PC_REG_instance_Q_reg_22_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => PORT_PC_22_port, E
=> n2156, CK => n1628, Q => ID_PC_22_port, QN =>
n1904);
IF_ID_PC_REG_instance_Q_reg_23_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => PORT_PC_23_port, E
=> n2156, CK => n1628, Q => ID_PC_23_port, QN =>
n1903);
IF_ID_INSTR_REG_instance_Q_reg_15_inst : EDFFTRXL port map( RN =>
PC_instance_n33, D => N779, E => n2156, CK => n1628,
Q => ID_IMM16_SHL2_31_port, QN => n1902);
PC_instance_Q_reg_3_inst : EDFFTRXL port map( RN => PC_instance_n33, D =>
N733, E => n2156, CK => n1628, Q => PORT_PC_3_port,
QN => n1901);
PC_instance_Q_reg_4_inst : EDFFTRXL port map( RN => PC_instance_n33, D =>
N734, E => n2157, CK => n1628, Q => PORT_PC_4_port,
QN => n1900);
PC_instance_Q_reg_6_inst : EDFFTRXL port map( RN => PC_instance_n33, D =>
N736, E => n2157, CK => n1628, Q => PORT_PC_6_port,
QN => n1899);
PC_instance_Q_reg_7_inst : EDFFTRXL port map( RN => PC_instance_n33, D =>
N737, E => n2157, CK => n1628, Q => PORT_PC_7_port,
QN => n1898);
PC_instance_Q_reg_8_inst : EDFFTRXL port map( RN => PC_instance_n33, D =>
N738, E => n2157, CK => n1628, Q => PORT_PC_8_port,
QN => n1897);
PC_instance_Q_reg_9_inst : EDFFTRXL port map( RN => PC_instance_n33, D =>
N739, E => n2157, CK => n1628, Q => PORT_PC_9_port,
QN => n1896);
PC_instance_Q_reg_10_inst : EDFFTRXL port map( RN => PC_instance_n33, D =>
N740, E => n2157, CK => n1628, Q => PORT_PC_10_port,
QN => n1895);
PC_instance_Q_reg_11_inst : EDFFTRXL port map( RN => PC_instance_n33, D =>
N741, E => n2157, CK => n1628, Q => PORT_PC_11_port,
QN => n1894);
PC_instance_Q_reg_12_inst : EDFFTRXL port map( RN => PC_instance_n33, D =>
N742, E => n2157, CK => n1628, Q => PORT_PC_12_port,
QN => n1893);
PC_instance_Q_reg_13_inst : EDFFTRXL port map( RN => PC_instance_n33, D =>
N743, E => n2157, CK => n1628, Q => PORT_PC_13_port,
QN => n1892);
PC_instance_Q_reg_14_inst : EDFFTRXL port map( RN => PC_instance_n33, D =>
N744, E => n2157, CK => n1628, Q => PORT_PC_14_port,
QN => n1891);
PC_instance_Q_reg_15_inst : EDFFTRXL port map( RN => PC_instance_n33, D =>
N745, E => n2157, CK => n1628, Q => PORT_PC_15_port,
QN => n1890);
PC_instance_Q_reg_16_inst : EDFFTRXL port map( RN => PC_instance_n33, D =>
N746, E => n2157, CK => n1628, Q => PORT_PC_16_port,
QN => n1889);
PC_instance_Q_reg_17_inst : EDFFTRXL port map( RN => PC_instance_n33, D =>
N747, E => n2157, CK => n1628, Q => PORT_PC_17_port,
QN => n1888);
PC_instance_Q_reg_18_inst : EDFFTRXL port map( RN => PC_instance_n33, D =>
N748, E => n2157, CK => n1628, Q => PORT_PC_18_port,
QN => n1887);
PC_instance_Q_reg_19_inst : EDFFTRXL port map( RN => PC_instance_n33, D =>
N749, E => n2157, CK => n1628, Q => PORT_PC_19_port,
QN => n1886);
PC_instance_Q_reg_20_inst : EDFFTRXL port map( RN => PC_instance_n33, D =>
N750, E => n2157, CK => n1628, Q => PORT_PC_20_port,
QN => n1885);
PC_instance_Q_reg_21_inst : EDFFTRXL port map( RN => PC_instance_n33, D =>
N751, E => n2157, CK => n1628, Q => PORT_PC_21_port,
QN => n1884);
IF_ID_INSTR_REG_instance_Q_reg_11_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => N775, E => n2156,
CK => n1628, Q => ID_IMM16_SHL2_13_port, QN => n1883
);
IF_ID_INSTR_REG_instance_Q_reg_12_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => N776, E => n2156,
CK => n1628, Q => ID_IMM16_SHL2_14_port, QN => n1882
);
IF_ID_INSTR_REG_instance_Q_reg_13_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D => N777, E =>
n2156, CK => n1628, Q => ID_IMM16_SHL2_15_port, QN
=> n1881);
IF_ID_INSTR_REG_instance_Q_reg_14_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => N778, E => n2156,
CK => n1628, Q => ID_IMM16_SHL2_16_port, QN => n1880
);
ID_EX_REGA_REG_instance_Q_reg_7_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => RF_OUT1(7), E =>
n686, CK => CLOCK, Q => EX_REGA_7_port, QN => n1879)
;
ID_EX_REGA_REG_instance_Q_reg_8_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => RF_OUT1(8), E =>
n686, CK => CLOCK, Q => EX_REGA_8_port, QN => n1878)
;
ID_EX_REGA_REG_instance_Q_reg_9_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => RF_OUT1(9), E =>
n686, CK => CLOCK, Q => EX_REGA_9_port, QN => n1877)
;
ID_EX_REGA_REG_instance_Q_reg_10_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => RF_OUT1(10), E =>
n686, CK => CLOCK, Q => EX_REGA_10_port, QN => n1876
);
ID_EX_REGA_REG_instance_Q_reg_11_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => RF_OUT1(11), E =>
n686, CK => CLOCK, Q => EX_REGA_11_port, QN => n1875
);
ID_EX_REGA_REG_instance_Q_reg_12_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => RF_OUT1(12), E =>
n686, CK => CLOCK, Q => EX_REGA_12_port, QN => n1874
);
ID_EX_REGA_REG_instance_Q_reg_13_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => RF_OUT1(13), E =>
n686, CK => CLOCK, Q => EX_REGA_13_port, QN => n1873
);
ID_EX_REGA_REG_instance_Q_reg_14_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => RF_OUT1(14), E =>
n686, CK => CLOCK, Q => EX_REGA_14_port, QN => n1872
);
ID_EX_REGA_REG_instance_Q_reg_15_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => RF_OUT1(15), E =>
n686, CK => CLOCK, Q => EX_REGA_15_port, QN => n1871
);
ID_EX_PC_REG_instance_Q_reg_7_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => ID_PC_7_port, E =>
n686, CK => CLOCK, Q => EX_PC_7_port, QN => n1870);
ID_EX_PC_REG_instance_Q_reg_8_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => ID_PC_8_port, E =>
n686, CK => CLOCK, Q => EX_PC_8_port, QN => n1666);
ID_EX_PC_REG_instance_Q_reg_9_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => ID_PC_9_port, E =>
n686, CK => CLOCK, Q => EX_PC_9_port, QN => n1667);
ID_EX_PC_REG_instance_Q_reg_10_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => ID_PC_10_port, E =>
n686, CK => CLOCK, Q => EX_PC_10_port, QN => n1650);
ID_EX_PC_REG_instance_Q_reg_11_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => ID_PC_11_port, E =>
n686, CK => CLOCK, Q => EX_PC_11_port, QN => n1668);
ID_EX_PC_REG_instance_Q_reg_12_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => ID_PC_12_port, E =>
n686, CK => CLOCK, Q => EX_PC_12_port, QN => n1669);
ID_EX_PC_REG_instance_Q_reg_13_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => ID_PC_13_port, E =>
n686, CK => CLOCK, Q => EX_PC_13_port, QN => n1869);
ID_EX_PC_REG_instance_Q_reg_14_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => ID_PC_14_port, E =>
n686, CK => CLOCK, Q => EX_PC_14_port, QN => n1868);
ID_EX_PC_REG_instance_Q_reg_15_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => ID_PC_15_port, E =>
n686, CK => CLOCK, Q => EX_PC_15_port, QN => n1867);
ID_EX_IMM16_EXT_REG_instance_Q_reg_4_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
ID_IMM16_SHL2_6_port, E => n686, CK => CLOCK, Q =>
EX_IMM16_EXT_4_port, QN => n1664);
ID_EX_IMM16_EXT_REG_instance_Q_reg_5_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
ID_IMM16_SHL2_7_port, E => n686, CK => CLOCK, Q =>
EX_IMM16_EXT_5_port, QN => n1658);
ID_EX_IMM16_EXT_REG_instance_Q_reg_6_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
ID_IMM16_SHL2_8_port, E => n686, CK => CLOCK, Q =>
EX_IMM16_EXT_6_port, QN => n1653);
ID_EX_IMM16_EXT_REG_instance_Q_reg_7_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
ID_IMM16_SHL2_9_port, E => n686, CK => CLOCK, Q =>
EX_IMM16_EXT_7_port, QN => n1659);
ID_EX_IMM16_EXT_REG_instance_Q_reg_8_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
ID_IMM16_SHL2_10_port, E => n686, CK => CLOCK, Q =>
EX_IMM16_EXT_8_port, QN => n1655);
ID_EX_IMM16_EXT_REG_instance_Q_reg_9_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
ID_IMM16_SHL2_11_port, E => n686, CK => CLOCK, Q =>
EX_IMM16_EXT_9_port, QN => n1657);
ID_EX_IMM16_EXT_REG_instance_Q_reg_10_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
ID_IMM16_SHL2_12_port, E => n686, CK => CLOCK, Q =>
EX_IMM16_EXT_10_port, QN => n1656);
ID_EX_IMM16_EXT_REG_instance_Q_reg_11_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
ID_IMM16_SHL2_13_port, E => n686, CK => CLOCK, Q =>
EX_IMM16_EXT_11_port, QN => n1649);
ID_EX_IMM16_EXT_REG_instance_Q_reg_12_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
ID_IMM16_SHL2_14_port, E => n686, CK => CLOCK, Q =>
EX_IMM16_EXT_12_port, QN => n1654);
ID_EX_IMM16_EXT_REG_instance_Q_reg_13_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
ID_IMM16_SHL2_15_port, E => n686, CK => CLOCK, Q =>
EX_IMM16_EXT_13_port, QN => n1661);
ID_EX_IMM16_EXT_REG_instance_Q_reg_14_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
ID_IMM16_SHL2_16_port, E => n686, CK => CLOCK, Q =>
EX_IMM16_EXT_14_port, QN => n1652);
ID_EX_IMM16_EXT_REG_instance_Q_reg_15_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D => n2109, E =>
n686, CK => CLOCK, Q => EX_IMM16_EXT_15_port, QN =>
n1660);
ID_EX_REGB_REG_instance_Q_reg_4_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => RF_OUT2(4), E =>
n686, CK => CLOCK, Q => EX_REGB_4_port, QN => n1866)
;
ID_EX_REGB_REG_instance_Q_reg_5_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => RF_OUT2(5), E =>
n686, CK => CLOCK, Q => EX_REGB_5_port, QN => n1865)
;
ID_EX_REGB_REG_instance_Q_reg_6_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => RF_OUT2(6), E =>
n686, CK => CLOCK, Q => EX_REGB_6_port, QN => n1864)
;
ID_EX_REGB_REG_instance_Q_reg_7_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => RF_OUT2(7), E =>
n686, CK => CLOCK, Q => EX_REGB_7_port, QN => n1863)
;
ID_EX_REGB_REG_instance_Q_reg_8_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => RF_OUT2(8), E =>
n686, CK => CLOCK, Q => EX_REGB_8_port, QN => n1862)
;
ID_EX_REGB_REG_instance_Q_reg_9_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => RF_OUT2(9), E =>
n686, CK => CLOCK, Q => EX_REGB_9_port, QN => n1861)
;
ID_EX_REGB_REG_instance_Q_reg_10_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => RF_OUT2(10), E =>
n686, CK => CLOCK, Q => EX_REGB_10_port, QN => n1860
);
ID_EX_REGB_REG_instance_Q_reg_11_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => RF_OUT2(11), E =>
n686, CK => CLOCK, Q => EX_REGB_11_port, QN => n1859
);
ID_EX_REGB_REG_instance_Q_reg_12_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => RF_OUT2(12), E =>
n686, CK => CLOCK, Q => EX_REGB_12_port, QN => n1858
);
ID_EX_REGB_REG_instance_Q_reg_13_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => RF_OUT2(13), E =>
n686, CK => CLOCK, Q => EX_REGB_13_port, QN => n1857
);
ID_EX_REGB_REG_instance_Q_reg_14_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => RF_OUT2(14), E =>
n686, CK => CLOCK, Q => EX_REGB_14_port, QN => n1856
);
ID_EX_REGB_REG_instance_Q_reg_15_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => RF_OUT2(15), E =>
n686, CK => CLOCK, Q => EX_REGB_15_port, QN => n1855
);
ID_EX_REGA_REG_instance_Q_reg_5_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => RF_OUT1(5), E =>
n686, CK => CLOCK, Q => EX_REGA_5_port, QN => n1854)
;
ID_EX_REGA_REG_instance_Q_reg_6_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => RF_OUT1(6), E =>
n686, CK => CLOCK, Q => EX_REGA_6_port, QN => n1853)
;
ID_EX_PC_REG_instance_Q_reg_5_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => ID_PC_5_port, E =>
n686, CK => CLOCK, Q => EX_PC_5_port, QN => n1852);
ID_EX_PC_REG_instance_Q_reg_6_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => ID_PC_6_port, E =>
n686, CK => CLOCK, Q => EX_PC_6_port, QN => n1851);
ID_EX_INSTR_REG_instance_Q_reg_9_inst : EDFFTRXL port map( RN =>
ID_EX_INSTR_REG_instance_n34, D =>
ID_INSTR_AFTER_CU_9_port, E => n686, CK => CLOCK, Q
=> EX_INSTR_9_port, QN => n1850);
ID_EX_INSTR_REG_instance_Q_reg_8_inst : EDFFTRXL port map( RN =>
ID_EX_INSTR_REG_instance_n34, D =>
ID_INSTR_AFTER_CU_8_port, E => n686, CK => CLOCK, Q
=> EX_INSTR_8_port, QN => n1849);
ID_EX_INSTR_REG_instance_Q_reg_7_inst : EDFFTRXL port map( RN =>
ID_EX_INSTR_REG_instance_n34, D =>
ID_INSTR_AFTER_CU_7_port, E => n686, CK => CLOCK, Q
=> EX_INSTR_7_port, QN => n1848);
IF_ID_PC_REG_instance_Q_reg_3_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => PORT_PC_3_port, E
=> n2155, CK => n1628, Q => ID_PC_3_port, QN =>
n1847);
IF_ID_PC_REG_instance_Q_reg_4_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => PORT_PC_4_port, E
=> n2155, CK => n1628, Q => ID_PC_4_port, QN =>
n1846);
IF_ID_PC_REG_instance_Q_reg_5_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
PORT_PC_5_port, E => n2155, CK => n1628, Q =>
ID_PC_5_port, QN => n1845);
IF_ID_PC_REG_instance_Q_reg_6_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => PORT_PC_6_port, E
=> n2155, CK => n1628, Q => ID_PC_6_port, QN =>
n1844);
IF_ID_PC_REG_instance_Q_reg_7_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => PORT_PC_7_port, E
=> n2155, CK => n1628, Q => ID_PC_7_port, QN =>
n1843);
IF_ID_PC_REG_instance_Q_reg_8_inst : EDFFTRXL port map( RN =>
PC_instance_n33, D => PORT_PC_8_port, E => n2155, CK
=> n1628, Q => ID_PC_8_port, QN => n1842);
ID_EX_INSTR_REG_instance_Q_reg_10_inst : EDFFTRXL port map( RN =>
ID_EX_INSTR_REG_instance_n34, D =>
ID_INSTR_AFTER_CU_10_port, E => n686, CK => CLOCK, Q
=> EX_INSTR_10_port, QN => n1841);
ID_EX_INSTR_REG_instance_Q_reg_6_inst : EDFFTRXL port map( RN =>
ID_EX_INSTR_REG_instance_n34, D =>
ID_INSTR_AFTER_CU_6_port, E => n686, CK => CLOCK, Q
=> EX_INSTR_6_port, QN => n1840);
ID_EX_INSTR_REG_instance_Q_reg_4_inst : EDFFTRXL port map( RN =>
ID_EX_INSTR_REG_instance_n34, D =>
ID_INSTR_AFTER_CU_4_port, E => n686, CK => CLOCK, Q
=> EX_INSTR_4_port, QN => n1839);
IF_ID_PC_REG_instance_Q_reg_2_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => PORT_PC_2_port, E
=> n2156, CK => n1628, Q => ID_PC_2_port, QN =>
n1838);
ID_EX_IMM16_EXT_REG_instance_Q_reg_3_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
ID_IMM16_SHL2_5_port, E => n686, CK => CLOCK, Q =>
EX_IMM16_EXT_3_port, QN => n1837);
ID_EX_REGA_REG_instance_Q_reg_2_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => RF_OUT1(2), E =>
n686, CK => CLOCK, Q => EX_REGA_2_port, QN => n1836)
;
ID_EX_REGA_REG_instance_Q_reg_3_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => RF_OUT1(3), E =>
n686, CK => CLOCK, Q => EX_REGA_3_port, QN => n1835)
;
ID_EX_REGA_REG_instance_Q_reg_4_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => RF_OUT1(4), E =>
n686, CK => CLOCK, Q => EX_REGA_4_port, QN => n1834)
;
ID_EX_PC_REG_instance_Q_reg_2_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => ID_PC_2_port, E =>
n686, CK => CLOCK, Q => EX_PC_2_port, QN => n1833);
ID_EX_PC_REG_instance_Q_reg_3_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => ID_PC_3_port, E =>
n686, CK => CLOCK, Q => EX_PC_3_port, QN => n1832);
ID_EX_PC_REG_instance_Q_reg_4_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => ID_PC_4_port, E =>
n686, CK => CLOCK, Q => EX_PC_4_port, QN => n1665);
ID_EX_IMM16_EXT_REG_instance_Q_reg_0_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
ID_IMM16_SHL2_2_port, E => n686, CK => CLOCK, Q =>
EX_IMM16_EXT_0_port, QN => n1662);
ID_EX_IMM16_EXT_REG_instance_Q_reg_1_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
ID_IMM16_SHL2_3_port, E => n686, CK => CLOCK, Q =>
EX_IMM16_EXT_1_port, QN => n1831);
ID_EX_IMM16_EXT_REG_instance_Q_reg_2_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
ID_IMM16_SHL2_4_port, E => n686, CK => CLOCK, Q =>
EX_IMM16_EXT_2_port, QN => n1663);
ID_EX_REGB_REG_instance_Q_reg_0_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => RF_OUT2(0), E =>
n686, CK => CLOCK, Q => EX_REGB_0_port, QN => n1830)
;
ID_EX_REGB_REG_instance_Q_reg_1_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => RF_OUT2(1), E =>
n686, CK => CLOCK, Q => EX_REGB_1_port, QN => n1829)
;
ID_EX_REGB_REG_instance_Q_reg_2_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => RF_OUT2(2), E =>
n686, CK => CLOCK, Q => EX_REGB_2_port, QN => n1828)
;
ID_EX_REGB_REG_instance_Q_reg_3_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => RF_OUT2(3), E =>
n686, CK => CLOCK, Q => EX_REGB_3_port, QN => n1827)
;
ID_EX_REGA_REG_instance_Q_reg_0_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => RF_OUT1(0), E =>
n686, CK => CLOCK, Q => EX_REGA_0_port, QN => n1826)
;
ID_EX_REGA_REG_instance_Q_reg_1_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => RF_OUT1(1), E =>
n686, CK => CLOCK, Q => EX_REGA_1_port, QN => n1825)
;
ID_EX_PC_REG_instance_Q_reg_0_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => ID_PC_SUM_0_port, E
=> n686, CK => CLOCK, Q => EX_PC_0_port, QN => n1824
);
ID_EX_PC_REG_instance_Q_reg_1_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => ID_PC_SUM_1_port, E
=> n686, CK => CLOCK, Q => EX_PC_1_port, QN => n1823
);
add_545_U1_30 : ADDFHXL port map( A => ID_PC_30_port, B => n2109, CI =>
add_545_carry_30_port, CO => add_545_carry_31_port,
S => ID_PC_SUM_30_port);
add_545_U1_3 : ADDFXL port map( A => ID_PC_3_port, B => ID_IMM16_SHL2_3_port
, CI => add_545_carry_3_port, CO =>
add_545_carry_4_port, S => ID_PC_SUM_3_port);
add_545_U1_9 : ADDFHXL port map( A => ID_PC_9_port, B =>
ID_IMM16_SHL2_9_port, CI => add_545_carry_9_port, CO
=> add_545_carry_10_port, S => ID_PC_SUM_9_port);
add_545_U1_10 : ADDFHXL port map( A => ID_PC_10_port, B =>
ID_IMM16_SHL2_10_port, CI => add_545_carry_10_port,
CO => add_545_carry_11_port, S => ID_PC_SUM_10_port)
;
add_545_U1_11 : ADDFHXL port map( A => ID_PC_11_port, B =>
ID_IMM16_SHL2_11_port, CI => add_545_carry_11_port,
CO => add_545_carry_12_port, S => ID_PC_SUM_11_port)
;
add_545_U1_12 : ADDFHXL port map( A => ID_PC_12_port, B =>
ID_IMM16_SHL2_12_port, CI => add_545_carry_12_port,
CO => add_545_carry_13_port, S => ID_PC_SUM_12_port)
;
add_545_U1_13 : ADDFHXL port map( A => ID_PC_13_port, B =>
ID_IMM16_SHL2_13_port, CI => add_545_carry_13_port,
CO => add_545_carry_14_port, S => ID_PC_SUM_13_port)
;
add_545_U1_14 : ADDFHXL port map( A => ID_PC_14_port, B =>
ID_IMM16_SHL2_14_port, CI => add_545_carry_14_port,
CO => add_545_carry_15_port, S => ID_PC_SUM_14_port)
;
add_545_U1_15 : ADDFHXL port map( A => ID_PC_15_port, B =>
ID_IMM16_SHL2_15_port, CI => add_545_carry_15_port,
CO => add_545_carry_16_port, S => ID_PC_SUM_15_port)
;
add_545_U1_16 : ADDFHXL port map( A => ID_PC_16_port, B =>
ID_IMM16_SHL2_16_port, CI => add_545_carry_16_port,
CO => add_545_carry_17_port, S => ID_PC_SUM_16_port)
;
add_545_U1_17 : ADDFHXL port map( A => ID_PC_17_port, B => n2109, CI =>
add_545_carry_17_port, CO => add_545_carry_18_port,
S => ID_PC_SUM_17_port);
add_545_U1_18 : ADDFHXL port map( A => ID_PC_18_port, B => n2109, CI =>
add_545_carry_18_port, CO => add_545_carry_19_port,
S => ID_PC_SUM_18_port);
add_545_U1_19 : ADDFHXL port map( A => ID_PC_19_port, B => n2109, CI =>
add_545_carry_19_port, CO => add_545_carry_20_port,
S => ID_PC_SUM_19_port);
add_545_U1_20 : ADDFHXL port map( A => ID_PC_20_port, B => n2109, CI =>
add_545_carry_20_port, CO => add_545_carry_21_port,
S => ID_PC_SUM_20_port);
add_545_U1_21 : ADDFHXL port map( A => ID_PC_21_port, B => n2109, CI =>
add_545_carry_21_port, CO => add_545_carry_22_port,
S => ID_PC_SUM_21_port);
add_545_U1_22 : ADDFHXL port map( A => ID_PC_22_port, B => n2109, CI =>
add_545_carry_22_port, CO => add_545_carry_23_port,
S => ID_PC_SUM_22_port);
add_545_U1_23 : ADDFHXL port map( A => ID_PC_23_port, B => n2109, CI =>
add_545_carry_23_port, CO => add_545_carry_24_port,
S => ID_PC_SUM_23_port);
add_545_U1_24 : ADDFHXL port map( A => ID_PC_24_port, B => n2109, CI =>
add_545_carry_24_port, CO => add_545_carry_25_port,
S => ID_PC_SUM_24_port);
add_545_U1_25 : ADDFHXL port map( A => ID_PC_25_port, B => n2109, CI =>
add_545_carry_25_port, CO => add_545_carry_26_port,
S => ID_PC_SUM_25_port);
add_545_U1_26 : ADDFHXL port map( A => ID_PC_26_port, B => n2109, CI =>
add_545_carry_26_port, CO => add_545_carry_27_port,
S => ID_PC_SUM_26_port);
add_545_U1_27 : ADDFHXL port map( A => ID_PC_27_port, B => n2109, CI =>
add_545_carry_27_port, CO => add_545_carry_28_port,
S => ID_PC_SUM_27_port);
add_545_U1_28 : ADDFHXL port map( A => ID_PC_28_port, B => n2109, CI =>
add_545_carry_28_port, CO => add_545_carry_29_port,
S => ID_PC_SUM_28_port);
add_545_U1_29 : ADDFHXL port map( A => ID_PC_29_port, B => n2109, CI =>
add_545_carry_29_port, CO => add_545_carry_30_port,
S => ID_PC_SUM_29_port);
add_545_U1_8 : ADDFHXL port map( A => ID_PC_8_port, B =>
ID_IMM16_SHL2_8_port, CI => add_545_carry_8_port, CO
=> add_545_carry_9_port, S => ID_PC_SUM_8_port);
add_545_U1_7 : ADDFHXL port map( A => ID_PC_7_port, B =>
ID_IMM16_SHL2_7_port, CI => add_545_carry_7_port, CO
=> add_545_carry_8_port, S => ID_PC_SUM_7_port);
add_545_U1_6 : ADDFHXL port map( A => ID_PC_6_port, B =>
ID_IMM16_SHL2_6_port, CI => add_545_carry_6_port, CO
=> add_545_carry_7_port, S => ID_PC_SUM_6_port);
add_545_U1_5 : ADDFHXL port map( A => ID_PC_5_port, B =>
ID_IMM16_SHL2_5_port, CI => add_545_carry_5_port, CO
=> add_545_carry_6_port, S => ID_PC_SUM_5_port);
add_545_U1_4 : ADDFHXL port map( A => ID_PC_4_port, B =>
ID_IMM16_SHL2_4_port, CI => add_545_carry_4_port, CO
=> add_545_carry_5_port, S => ID_PC_SUM_4_port);
add_545_U1_31 : XOR3XL port map( A => ID_PC_31_port, B => n2109, C =>
add_545_carry_31_port, Y => ID_PC_SUM_31_port);
EX_MEM_REGB_REG_instance_Q_reg_0_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => EX_REGB_0_port, E
=> n686, CK => CLOCK, Q => PORT_REGB(0), QN => n1821
);
EX_MEM_REGB_REG_instance_Q_reg_1_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => EX_REGB_1_port, E
=> n686, CK => CLOCK, Q => PORT_REGB(1), QN => n1820
);
EX_MEM_REGB_REG_instance_Q_reg_2_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => EX_REGB_2_port, E
=> n686, CK => CLOCK, Q => PORT_REGB(2), QN => n1819
);
EX_MEM_REGB_REG_instance_Q_reg_3_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => EX_REGB_3_port, E
=> n686, CK => CLOCK, Q => PORT_REGB(3), QN => n1818
);
EX_MEM_REGB_REG_instance_Q_reg_4_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => EX_REGB_4_port, E
=> n686, CK => CLOCK, Q => PORT_REGB(4), QN => n1817
);
EX_MEM_REGB_REG_instance_Q_reg_5_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => EX_REGB_5_port, E
=> n686, CK => CLOCK, Q => PORT_REGB(5), QN => n1816
);
EX_MEM_REGB_REG_instance_Q_reg_6_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => EX_REGB_6_port, E
=> n686, CK => CLOCK, Q => PORT_REGB(6), QN => n1815
);
EX_MEM_REGB_REG_instance_Q_reg_7_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => EX_REGB_7_port, E
=> n686, CK => CLOCK, Q => PORT_REGB(7), QN => n1814
);
EX_MEM_REGB_REG_instance_Q_reg_8_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => EX_REGB_8_port, E
=> n686, CK => CLOCK, Q => PORT_REGB(8), QN => n1813
);
EX_MEM_REGB_REG_instance_Q_reg_9_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => EX_REGB_9_port, E
=> n686, CK => CLOCK, Q => PORT_REGB(9), QN => n1812
);
EX_MEM_REGB_REG_instance_Q_reg_10_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => EX_REGB_10_port,
E => n686, CK => CLOCK, Q => PORT_REGB(10), QN =>
n1811);
EX_MEM_REGB_REG_instance_Q_reg_11_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => EX_REGB_11_port,
E => n686, CK => CLOCK, Q => PORT_REGB(11), QN =>
n1810);
EX_MEM_REGB_REG_instance_Q_reg_12_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => EX_REGB_12_port,
E => n686, CK => CLOCK, Q => PORT_REGB(12), QN =>
n1809);
EX_MEM_REGB_REG_instance_Q_reg_13_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => EX_REGB_13_port,
E => n686, CK => CLOCK, Q => PORT_REGB(13), QN =>
n1808);
EX_MEM_REGB_REG_instance_Q_reg_14_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => EX_REGB_14_port,
E => n686, CK => CLOCK, Q => PORT_REGB(14), QN =>
n1807);
EX_MEM_REGB_REG_instance_Q_reg_15_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => EX_REGB_15_port,
E => n686, CK => CLOCK, Q => PORT_REGB(15), QN =>
n1806);
EX_MEM_REGB_REG_instance_Q_reg_16_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => EX_REGB_16_port,
E => n686, CK => CLOCK, Q => PORT_REGB(16), QN =>
n1805);
EX_MEM_REGB_REG_instance_Q_reg_17_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => EX_REGB_17_port,
E => n686, CK => CLOCK, Q => PORT_REGB(17), QN =>
n1804);
EX_MEM_REGB_REG_instance_Q_reg_18_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => EX_REGB_18_port,
E => n686, CK => CLOCK, Q => PORT_REGB(18), QN =>
n1803);
EX_MEM_REGB_REG_instance_Q_reg_19_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => EX_REGB_19_port,
E => n686, CK => CLOCK, Q => PORT_REGB(19), QN =>
n1802);
EX_MEM_REGB_REG_instance_Q_reg_20_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => EX_REGB_20_port,
E => n686, CK => CLOCK, Q => PORT_REGB(20), QN =>
n1801);
EX_MEM_REGB_REG_instance_Q_reg_21_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => EX_REGB_21_port,
E => n686, CK => CLOCK, Q => PORT_REGB(21), QN =>
n1800);
EX_MEM_REGB_REG_instance_Q_reg_22_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => EX_REGB_22_port,
E => n686, CK => CLOCK, Q => PORT_REGB(22), QN =>
n1799);
EX_MEM_REGB_REG_instance_Q_reg_23_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => EX_REGB_23_port,
E => n686, CK => CLOCK, Q => PORT_REGB(23), QN =>
n1798);
EX_MEM_REGB_REG_instance_Q_reg_24_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => EX_REGB_24_port,
E => n686, CK => CLOCK, Q => PORT_REGB(24), QN =>
n1797);
EX_MEM_REGB_REG_instance_Q_reg_25_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => EX_REGB_25_port,
E => n686, CK => CLOCK, Q => PORT_REGB(25), QN =>
n1796);
EX_MEM_REGB_REG_instance_Q_reg_26_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => EX_REGB_26_port,
E => n686, CK => CLOCK, Q => PORT_REGB(26), QN =>
n1795);
EX_MEM_REGB_REG_instance_Q_reg_27_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => EX_REGB_27_port,
E => n686, CK => CLOCK, Q => PORT_REGB(27), QN =>
n1794);
EX_MEM_REGB_REG_instance_Q_reg_28_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => EX_REGB_28_port,
E => n686, CK => CLOCK, Q => PORT_REGB(28), QN =>
n1793);
EX_MEM_REGB_REG_instance_Q_reg_29_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => EX_REGB_29_port,
E => n686, CK => CLOCK, Q => PORT_REGB(29), QN =>
n1792);
EX_MEM_REGB_REG_instance_Q_reg_30_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => EX_REGB_30_port,
E => n686, CK => CLOCK, Q => PORT_REGB(30), QN =>
n1791);
EX_MEM_REGB_REG_instance_Q_reg_31_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => EX_REGB_31_port,
E => n686, CK => CLOCK, Q => PORT_REGB(31), QN =>
n1790);
MEM_WB_INSTR_REG_instance_Q_reg_26_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => MEM_INSTR_26_port,
E => X_Logic1_port, CK => CLOCK, Q => WB_INSTR_26,
QN => n1789);
MEM_WB_INSTR_REG_instance_Q_reg_31_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => MEM_INSTR_31_port,
E => X_Logic1_port, CK => CLOCK, Q => WB_INSTR_31,
QN => n1788);
MEM_WB_INSTR_REG_instance_Q_reg_28_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => MEM_INSTR_28_port, E
=> X_Logic1_port, CK => CLOCK, Q => WB_INSTR_28, QN
=> n1787);
MEM_WB_INSTR_REG_instance_Q_reg_29_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => MEM_INSTR_29_port,
E => X_Logic1_port, CK => CLOCK, Q => WB_INSTR_29,
QN => n1786);
MEM_WB_INSTR_REG_instance_Q_reg_27_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => MEM_INSTR_27_port,
E => X_Logic1_port, CK => CLOCK, Q => WB_INSTR_27,
QN => n1785);
MEM_WB_INSTR_REG_instance_Q_reg_30_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => MEM_INSTR_30_port
, E => X_Logic1_port, CK => CLOCK, Q => WB_INSTR_30,
QN => n1784);
EX_MEM_INSTR_REG_instance_Q_reg_0_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => EX_INSTR_0_port, E
=> n686, CK => CLOCK, Q => MEM_INSTR_0_port, QN =>
n1783);
EX_MEM_INSTR_REG_instance_Q_reg_1_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => EX_INSTR_1_port, E
=> n686, CK => CLOCK, Q => MEM_INSTR_1_port, QN =>
n1782);
EX_MEM_INSTR_REG_instance_Q_reg_2_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
EX_INSTR_2_port, E => n686, CK => CLOCK, Q =>
MEM_INSTR_2_port, QN => n1781);
EX_MEM_INSTR_REG_instance_Q_reg_3_inst : EDFFTRXL port map( RN =>
PC_instance_n33, D => EX_INSTR_3_port, E => n686, CK
=> CLOCK, Q => MEM_INSTR_3_port, QN => n1780);
EX_MEM_INSTR_REG_instance_Q_reg_4_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
EX_INSTR_4_port, E => n686, CK => CLOCK, Q =>
MEM_INSTR_4_port, QN => n1779);
EX_MEM_INSTR_REG_instance_Q_reg_5_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => EX_INSTR_5_port, E
=> n686, CK => CLOCK, Q => MEM_INSTR_5_port, QN =>
n1778);
EX_MEM_INSTR_REG_instance_Q_reg_6_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => EX_INSTR_6_port, E
=> n686, CK => CLOCK, Q => MEM_INSTR_6_port, QN =>
n1777);
EX_MEM_INSTR_REG_instance_Q_reg_7_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => EX_INSTR_7_port, E
=> n686, CK => CLOCK, Q => MEM_INSTR_7_port, QN =>
n1776);
EX_MEM_INSTR_REG_instance_Q_reg_8_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => EX_INSTR_8_port, E
=> n686, CK => CLOCK, Q => MEM_INSTR_8_port, QN =>
n1775);
EX_MEM_INSTR_REG_instance_Q_reg_9_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => EX_INSTR_9_port, E
=> n686, CK => CLOCK, Q => MEM_INSTR_9_port, QN =>
n1774);
EX_MEM_INSTR_REG_instance_Q_reg_10_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => EX_INSTR_10_port,
E => n686, CK => CLOCK, Q => MEM_INSTR_10_port, QN
=> n1773);
EX_MEM_OUT_REG_instance_Q_reg_0_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => N4860, E => n686,
CK => CLOCK, Q => PORT_ALU_0_port, QN => n1772);
EX_MEM_OUT_REG_instance_Q_reg_1_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => N4861, E => n686,
CK => CLOCK, Q => PORT_ALU_1_port, QN => n1771);
EX_MEM_OUT_REG_instance_Q_reg_2_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => N4862, E => n686,
CK => CLOCK, Q => PORT_ALU_2_port, QN => n1770);
EX_MEM_OUT_REG_instance_Q_reg_3_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => N4863, E => n686,
CK => CLOCK, Q => PORT_ALU_3_port, QN => n1769);
EX_MEM_OUT_REG_instance_Q_reg_4_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => N4864, E => n686,
CK => CLOCK, Q => PORT_ALU_4_port, QN => n1768);
EX_MEM_OUT_REG_instance_Q_reg_5_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => N4865, E => n686,
CK => CLOCK, Q => PORT_ALU_5_port, QN => n1767);
EX_MEM_OUT_REG_instance_Q_reg_6_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => N4866, E => n686,
CK => CLOCK, Q => PORT_ALU_6_port, QN => n1766);
EX_MEM_OUT_REG_instance_Q_reg_7_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => N4867, E => n686,
CK => CLOCK, Q => PORT_ALU_7_port, QN => n1765);
EX_MEM_OUT_REG_instance_Q_reg_8_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => N4868, E => n686,
CK => CLOCK, Q => PORT_ALU_8_port, QN => n1764);
EX_MEM_OUT_REG_instance_Q_reg_9_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => N4869, E => n686,
CK => CLOCK, Q => PORT_ALU_9_port, QN => n1763);
EX_MEM_OUT_REG_instance_Q_reg_10_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => N4870, E => n686,
CK => CLOCK, Q => PORT_ALU_10_port, QN => n1762);
EX_MEM_OUT_REG_instance_Q_reg_11_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => N4871, E => n686,
CK => CLOCK, Q => PORT_ALU_11_port, QN => n1761);
EX_MEM_OUT_REG_instance_Q_reg_12_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => N4872, E => n686,
CK => CLOCK, Q => PORT_ALU_12_port, QN => n1760);
EX_MEM_OUT_REG_instance_Q_reg_13_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => N4873, E => n686,
CK => CLOCK, Q => PORT_ALU_13_port, QN => n1759);
EX_MEM_OUT_REG_instance_Q_reg_14_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => N4874, E => n686,
CK => CLOCK, Q => PORT_ALU_14_port, QN => n1758);
EX_MEM_OUT_REG_instance_Q_reg_15_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => N4875, E => n686,
CK => CLOCK, Q => PORT_ALU_15_port, QN => n1757);
EX_MEM_OUT_REG_instance_Q_reg_16_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => N4876, E => n686,
CK => CLOCK, Q => PORT_ALU_16_port, QN => n1756);
EX_MEM_OUT_REG_instance_Q_reg_17_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => N4877, E => n686,
CK => CLOCK, Q => PORT_ALU_17_port, QN => n1755);
EX_MEM_OUT_REG_instance_Q_reg_18_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => N4878, E => n686,
CK => CLOCK, Q => PORT_ALU_18_port, QN => n1754);
EX_MEM_OUT_REG_instance_Q_reg_19_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => N4879, E => n686,
CK => CLOCK, Q => PORT_ALU_19_port, QN => n1753);
EX_MEM_OUT_REG_instance_Q_reg_20_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => N4880, E => n686,
CK => CLOCK, Q => PORT_ALU_20_port, QN => n1752);
EX_MEM_OUT_REG_instance_Q_reg_21_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => N4881, E => n686,
CK => CLOCK, Q => PORT_ALU_21_port, QN => n1751);
EX_MEM_OUT_REG_instance_Q_reg_22_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => N4882, E => n686,
CK => CLOCK, Q => PORT_ALU_22_port, QN => n1750);
EX_MEM_OUT_REG_instance_Q_reg_23_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => N4883, E => n686,
CK => CLOCK, Q => PORT_ALU_23_port, QN => n1749);
EX_MEM_OUT_REG_instance_Q_reg_24_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => N4884, E => n686,
CK => CLOCK, Q => PORT_ALU_24_port, QN => n1748);
EX_MEM_OUT_REG_instance_Q_reg_25_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => N4885, E => n686,
CK => CLOCK, Q => PORT_ALU_25_port, QN => n1747);
EX_MEM_OUT_REG_instance_Q_reg_26_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => N4886, E => n686,
CK => CLOCK, Q => PORT_ALU_26_port, QN => n1746);
EX_MEM_OUT_REG_instance_Q_reg_27_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => N4887, E => n686,
CK => CLOCK, Q => PORT_ALU_27_port, QN => n1745);
EX_MEM_OUT_REG_instance_Q_reg_28_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => N4888, E => n686,
CK => CLOCK, Q => PORT_ALU_28_port, QN => n1744);
IF_ID_INSTR_REG_instance_Q_reg_25_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => N789, E => n2156,
CK => n1628, Q => RF_ADD_RD1_4_port, QN => n1743);
EX_MEM_INSTR_REG_instance_Q_reg_27_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => EX_INSTR_27_port,
E => n686, CK => CLOCK, Q => MEM_INSTR_27_port, QN
=> n1742);
IF_ID_INSTR_REG_instance_Q_reg_24_inst : EDFFTRXL port map( RN =>
PC_instance_n33, D => N788, E => n2156, CK => n1628,
Q => RF_ADD_RD1_3_port, QN => n1741);
IF_ID_INSTR_REG_instance_Q_reg_26_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => N790, E => n2156,
CK => n1628, Q => ID_INSTR_26, QN => n1740);
IF_ID_INSTR_REG_instance_Q_reg_23_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => N787, E => n2156,
CK => n1628, Q => RF_ADD_RD1_2_port, QN => n1739);
IF_ID_INSTR_REG_instance_Q_reg_17_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => N781, E => n2156,
CK => n1628, Q => RF_ADD_RD2_1_port, QN => n1738);
IF_ID_INSTR_REG_instance_Q_reg_30_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => N794, E => n2156, CK
=> n1628, Q => ID_INSTR_30, QN => n1737);
IF_ID_INSTR_REG_instance_Q_reg_19_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => N783, E => n2156,
CK => n1628, Q => RF_ADD_RD2_3_port, QN => n1736);
IF_ID_INSTR_REG_instance_Q_reg_16_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => N780, E => n2156,
CK => n1628, Q => RF_ADD_RD2_0_port, QN => n1735);
EX_MEM_INSTR_REG_instance_Q_reg_29_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D =>
EX_INSTR_29_port, E => n686, CK => CLOCK, Q =>
MEM_INSTR_29_port, QN => n1734);
IF_ID_INSTR_REG_instance_Q_reg_29_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => N793, E => n2156,
CK => n1628, Q => ID_INSTR_29, QN => n1733);
IF_ID_INSTR_REG_instance_Q_reg_22_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D => N786, E =>
n2156, CK => n1628, Q => RF_ADD_RD1_1_port, QN =>
n1732);
IF_ID_INSTR_REG_instance_Q_reg_27_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => N791, E => n2156, CK
=> n1628, Q => ID_INSTR_27, QN => n1731);
IF_ID_INSTR_REG_instance_Q_reg_18_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => N782, E => n2156, CK
=> n1628, Q => RF_ADD_RD2_2_port, QN => n1730);
IF_ID_INSTR_REG_instance_Q_reg_20_inst : EDFFTRXL port map( RN =>
EX_MEM_REGB_REG_instance_n34, D => N784, E => n2156,
CK => n1628, Q => RF_ADD_RD2_4_port, QN => n1729);
IF_ID_INSTR_REG_instance_Q_reg_31_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D => N795, E =>
n2156, CK => n1628, Q => ID_INSTR_31, QN => n1728);
IF_ID_INSTR_REG_instance_Q_reg_28_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => N792, E => n2156,
CK => n1628, Q => ID_INSTR_28, QN => n1727);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_0_30 : MX2XL port map( A => n1691, B
=> n1682, S0 => n2163, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_30_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_1_30 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_30_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_28_port,
S0 => n1601, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_30_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_2_30 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_30_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_26_port,
S0 => n1602, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_30_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_3_30 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_30_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_22_port,
S0 => n2175, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_30_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_0_31 : MX2XL port map( A => n1692, B
=> n1691, S0 => n2163, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_31_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_1_31 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_31_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_29_port,
S0 => n1601, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_31_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_2_31 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_31_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_27_port,
S0 => n1602, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_31_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_3_31 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_31_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_23_port,
S0 => n2175, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_31_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_0_5 : MX2XL port map( A => N4723, B =>
n2190, S0 => n2164, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_5_port);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_0_15 : MX2XL port map( A => n1651, B
=> n2177, S0 => n2164, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_15_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_0_17 : MX2XL port map( A => n1679, B
=> n1684, S0 => n2163, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_17_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_0_18 : MX2XL port map( A => n1689, B
=> n1679, S0 => n2164, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_18_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_0_19 : MX2XL port map( A => n1688, B
=> n1689, S0 => n2163, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_19_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_0_20 : MX2XL port map( A => n1683, B
=> n1688, S0 => n2164, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_20_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_0_21 : MX2XL port map( A => n1686, B
=> n1683, S0 => n2163, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_21_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_0_22 : MX2XL port map( A => n1687, B
=> n1686, S0 => n2164, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_22_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_0_23 : MX2XL port map( A => n1678, B
=> n1687, S0 => n2163, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_23_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_0_24 : MX2XL port map( A => n1685, B
=> n1678, S0 => n2164, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_24_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_0_25 : MX2XL port map( A => n1677, B
=> n1685, S0 => n2163, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_25_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_0_26 : MX2XL port map( A => n1680, B
=> n1677, S0 => n2164, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_26_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_0_27 : MX2XL port map( A => n1681, B
=> n1680, S0 => n2164, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_27_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_0_28 : MX2XL port map( A => n1690, B
=> n1681, S0 => n2164, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_28_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_0_29 : MX2XL port map( A => n1682, B
=> n1690, S0 => n2163, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_29_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_0_16 : MX2XL port map( A => n1684, B
=> n1651, S0 => n2164, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_16_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_0_2 : MX2XL port map( A => n2193, B =>
n2115, S0 => n2163, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_2_port);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_0_6 : MX2XL port map( A => N4724, B =>
N4723, S0 => n2164, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_6_port);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_0_7 : MX2XL port map( A => n2189, B =>
N4724, S0 => n2164, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_7_port);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_0_1 : MX2XL port map( A => n2116, B =>
ALU_instance_SHIFTER_GENERIC_I_N202, S0 => n2163, Y
=>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_1_port);
PC_instance_Q_reg_2_inst : EDFFTRXL port map( RN => PC_instance_n33, D =>
N732, E => n2156, CK => n1628, Q => PORT_PC_2_port,
QN => n1726);
IF_ID_INSTR_REG_instance_Q_reg_10_inst : EDFFTRXL port map( RN =>
ID_EX_REGB_REG_instance_n34, D => N774, E => n2156,
CK => n1628, Q => ID_IMM16_SHL2_12_port, QN => n1725
);
IF_ID_INSTR_REG_instance_Q_reg_7_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => N771, E => n2156,
CK => n1628, Q => ID_IMM16_SHL2_9_port, QN => n1724)
;
IF_ID_INSTR_REG_instance_Q_reg_8_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => N772, E => n2156,
CK => n1628, Q => ID_IMM16_SHL2_10_port, QN => n1723
);
IF_ID_INSTR_REG_instance_Q_reg_9_inst : EDFFTRXL port map( RN =>
ID_EX_PC_REG_instance_n34, D => N773, E => n2156, CK
=> n1628, Q => ID_IMM16_SHL2_11_port, QN => n1722);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_RCA0_add_1_root_add_20_2_U1_3 :
ADDFXL port map( A => n1692, B =>
ALU_instance_INTERNAL_B_31_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_RCA0_add_1_root_add_20_2_carry_3_port,
CO => ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_C0, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_S0_3_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_RCA1_add_1_root_add_20_2_U1_3 :
ADDFXL port map( A => n1692, B =>
ALU_instance_INTERNAL_B_31_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_RCA1_add_1_root_add_20_2_carry_3_port,
CO => ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_C1, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_S1_3_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_RCA0_add_1_root_add_20_2_U1_3 :
ADDFXL port map( A => n1681, B =>
ALU_instance_INTERNAL_B_27_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_RCA0_add_1_root_add_20_2_carry_3_port,
CO => ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_C0, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_S0_3_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_RCA0_add_1_root_add_20_2_U1_3 :
ADDFXL port map( A => n1651, B =>
ALU_instance_INTERNAL_B_15_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_RCA0_add_1_root_add_20_2_carry_3_port,
CO => ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_C0, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_S0_3_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_RCA0_add_1_root_add_20_2_U1_3 :
ADDFXL port map( A => n1688, B =>
ALU_instance_INTERNAL_B_19_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_RCA0_add_1_root_add_20_2_carry_3_port,
CO => ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_C0, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_S0_3_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_RCA0_add_1_root_add_20_2_U1_3 :
ADDFXL port map( A => n1678, B =>
ALU_instance_INTERNAL_B_23_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_RCA0_add_1_root_add_20_2_carry_3_port,
CO => ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_C0, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_S0_3_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_RCA1_add_1_root_add_20_2_U1_3 :
ADDFXL port map( A => n1681, B =>
ALU_instance_INTERNAL_B_27_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_RCA1_add_1_root_add_20_2_carry_3_port,
CO => ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_C1, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_S1_3_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_RCA1_add_1_root_add_20_2_U1_3 :
ADDFXL port map( A => n1651, B =>
ALU_instance_INTERNAL_B_15_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_RCA1_add_1_root_add_20_2_carry_3_port,
CO => ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_C1, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_S1_3_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_RCA1_add_1_root_add_20_2_U1_3 :
ADDFXL port map( A => n1688, B =>
ALU_instance_INTERNAL_B_19_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_RCA1_add_1_root_add_20_2_carry_3_port,
CO => ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_C1, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_S1_3_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_RCA1_add_1_root_add_20_2_U1_3 :
ADDFXL port map( A => n1678, B =>
ALU_instance_INTERNAL_B_23_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_RCA1_add_1_root_add_20_2_carry_3_port,
CO => ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_C1, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_S1_3_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_RCA1_add_1_root_add_20_2_U1_2 :
ADDFXL port map( A => n1691, B =>
ALU_instance_INTERNAL_B_30_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_RCA1_add_1_root_add_20_2_carry_2_port,
CO =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_RCA1_add_1_root_add_20_2_carry_3_port, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_S1_2_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_RCA0_add_1_root_add_20_2_U1_2 :
ADDFXL port map( A => n1691, B =>
ALU_instance_INTERNAL_B_30_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_RCA0_add_1_root_add_20_2_carry_2_port,
CO =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_RCA0_add_1_root_add_20_2_carry_3_port, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_S0_2_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_RCA1_add_1_root_add_20_2_U1_2 :
ADDFXL port map( A => n1680, B =>
ALU_instance_INTERNAL_B_26_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_RCA1_add_1_root_add_20_2_carry_2_port,
CO =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_RCA1_add_1_root_add_20_2_carry_3_port, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_S1_2_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_RCA0_add_1_root_add_20_2_U1_2 :
ADDFXL port map( A => n1680, B =>
ALU_instance_INTERNAL_B_26_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_RCA0_add_1_root_add_20_2_carry_2_port,
CO =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_RCA0_add_1_root_add_20_2_carry_3_port, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_S0_2_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_RCA1_add_1_root_add_20_2_U1_2 :
ADDFXL port map( A => n1689, B =>
ALU_instance_INTERNAL_B_18_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_RCA1_add_1_root_add_20_2_carry_2_port,
CO =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_RCA1_add_1_root_add_20_2_carry_3_port, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_S1_2_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_RCA0_add_1_root_add_20_2_U1_2 :
ADDFXL port map( A => n1689, B =>
ALU_instance_INTERNAL_B_18_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_RCA0_add_1_root_add_20_2_carry_2_port,
CO =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_RCA0_add_1_root_add_20_2_carry_3_port, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_S0_2_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_RCA1_add_1_root_add_20_2_U1_2 :
ADDFXL port map( A => n1687, B =>
ALU_instance_INTERNAL_B_22_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_RCA1_add_1_root_add_20_2_carry_2_port,
CO =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_RCA1_add_1_root_add_20_2_carry_3_port, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_S1_2_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_RCA0_add_1_root_add_20_2_U1_2 :
ADDFXL port map( A => n1687, B =>
ALU_instance_INTERNAL_B_22_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_RCA0_add_1_root_add_20_2_carry_2_port,
CO =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_RCA0_add_1_root_add_20_2_carry_3_port, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_S0_2_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_RCA0_add_1_root_add_20_2_U1_1 :
ADDFXL port map( A => n1677, B =>
ALU_instance_INTERNAL_B_25_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_RCA0_add_1_root_add_20_2_carry_1_port,
CO =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_RCA0_add_1_root_add_20_2_carry_2_port, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_S0_1_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_RCA0_add_1_root_add_20_2_U1_1 :
ADDFXL port map( A => n1679, B =>
ALU_instance_INTERNAL_B_17_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_RCA0_add_1_root_add_20_2_carry_1_port,
CO =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_RCA0_add_1_root_add_20_2_carry_2_port, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_S0_1_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_RCA0_add_1_root_add_20_2_U1_1 :
ADDFXL port map( A => n1686, B =>
ALU_instance_INTERNAL_B_21_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_RCA0_add_1_root_add_20_2_carry_1_port,
CO =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_RCA0_add_1_root_add_20_2_carry_2_port, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_S0_1_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_RCA1_add_1_root_add_20_2_U1_1 :
ADDFXL port map( A => n1682, B =>
ALU_instance_INTERNAL_B_29_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_RCA1_add_1_root_add_20_2_carry_1_port,
CO =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_RCA1_add_1_root_add_20_2_carry_2_port, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_S1_1_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_RCA1_add_1_root_add_20_2_U1_1 :
ADDFXL port map( A => n1677, B =>
ALU_instance_INTERNAL_B_25_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_RCA1_add_1_root_add_20_2_carry_1_port,
CO =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_RCA1_add_1_root_add_20_2_carry_2_port, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_S1_1_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_RCA1_add_1_root_add_20_2_U1_1 :
ADDFXL port map( A => n1679, B =>
ALU_instance_INTERNAL_B_17_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_RCA1_add_1_root_add_20_2_carry_1_port,
CO =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_RCA1_add_1_root_add_20_2_carry_2_port, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_S1_1_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_RCA1_add_1_root_add_20_2_U1_1 :
ADDFXL port map( A => n1686, B =>
ALU_instance_INTERNAL_B_21_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_RCA1_add_1_root_add_20_2_carry_1_port,
CO =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_RCA1_add_1_root_add_20_2_carry_2_port, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_S1_1_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_RCA0_add_1_root_add_20_2_U1_1 :
ADDFXL port map( A => n1682, B =>
ALU_instance_INTERNAL_B_29_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_RCA0_add_1_root_add_20_2_carry_1_port,
CO =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_RCA0_add_1_root_add_20_2_carry_2_port, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_S0_1_port
);
IF_ID_INSTR_REG_instance_Q_reg_0_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D => N764, E =>
n2156, CK => n1628, Q => ID_IMM16_SHL2_2_port, QN =>
n1720);
ID_EX_INSTR_REG_instance_Q_reg_5_inst : EDFFTRXL port map( RN =>
ID_EX_INSTR_REG_instance_n34, D =>
ID_INSTR_AFTER_CU_5_port, E => n686, CK => CLOCK, Q
=> EX_INSTR_5_port, QN => n1719);
IF_ID_INSTR_REG_instance_Q_reg_2_inst : EDFFTRXL port map( RN =>
PC_instance_n33, D => N766, E => n2156, CK => n1628,
Q => ID_IMM16_SHL2_4_port, QN => n1718);
IF_ID_INSTR_REG_instance_Q_reg_5_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => N769, E => n2156,
CK => n1628, Q => ID_IMM16_SHL2_7_port, QN => n1717)
;
IF_ID_INSTR_REG_instance_Q_reg_4_inst : EDFFTRXL port map( RN =>
ID_EX_IMM16_EXT_REG_instance_n34, D => N768, E =>
n2156, CK => n1628, Q => ID_IMM16_SHL2_6_port, QN =>
n1716);
IF_ID_INSTR_REG_instance_Q_reg_6_inst : EDFFTRXL port map( RN =>
PC_instance_n33, D => N770, E => n2156, CK => n1628,
Q => ID_IMM16_SHL2_8_port, QN => n1715);
IF_ID_INSTR_REG_instance_Q_reg_1_inst : EDFFTRXL port map( RN =>
MEM_WB_ALU_REG_instance_n34, D => N765, E => n2156,
CK => n1628, Q => ID_IMM16_SHL2_3_port, QN => n1714)
;
IF_ID_INSTR_REG_instance_Q_reg_3_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => N767, E => n2156,
CK => n1628, Q => ID_IMM16_SHL2_5_port, QN => n1713)
;
ID_EX_INSTR_REG_instance_Q_reg_0_inst : EDFFTRXL port map( RN =>
ID_EX_INSTR_REG_instance_n34, D =>
ID_INSTR_AFTER_CU_0_port, E => n686, CK => CLOCK, Q
=> EX_INSTR_0_port, QN => n1712);
ID_EX_INSTR_REG_instance_Q_reg_3_inst : EDFFTRXL port map( RN =>
ID_EX_INSTR_REG_instance_n34, D =>
ID_INSTR_AFTER_CU_3_port, E => n686, CK => CLOCK, Q
=> EX_INSTR_3_port, QN => n1711);
ID_EX_INSTR_REG_instance_Q_reg_1_inst : EDFFTRXL port map( RN =>
ID_EX_INSTR_REG_instance_n34, D =>
ID_INSTR_AFTER_CU_1_port, E => n686, CK => CLOCK, Q
=> EX_INSTR_1_port, QN => n1710);
ID_EX_INSTR_REG_instance_Q_reg_2_inst : EDFFTRXL port map( RN =>
ID_EX_INSTR_REG_instance_n34, D =>
ID_INSTR_AFTER_CU_2_port, E => n686, CK => CLOCK, Q
=> EX_INSTR_2_port, QN => n1709);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_4_31 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_31_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_15_port,
S0 => N4831, Y =>
ALU_instance_SHIFTER_GENERIC_I_N265);
BOOTH_instance_add_3_root_add_53_G7_U1_26 : ADDFHXL port map( A =>
BOOTH_instance_decoded_8_26_port, B =>
BOOTH_instance_partial_products_2_26_port, CI =>
BOOTH_instance_add_3_root_add_53_G7_carry_26_port,
CO =>
BOOTH_instance_add_3_root_add_53_G7_carry_27_port, S
=> BOOTH_instance_partial_products_6_26_port);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_RCA1_add_1_root_add_20_2_U1_2 :
ADDFXL port map( A => n2120, B =>
ALU_instance_INTERNAL_B_6_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_RCA1_add_1_root_add_20_2_carry_2_port,
CO =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_RCA1_add_1_root_add_20_2_carry_3_port, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_S1_2_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_RCA0_add_1_root_add_20_2_U1_2 :
ADDFXL port map( A => N4724, B =>
ALU_instance_INTERNAL_B_6_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_RCA0_add_1_root_add_20_2_carry_2_port,
CO =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_RCA0_add_1_root_add_20_2_carry_3_port, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_S0_2_port
);
BOOTH_instance_add_5_root_add_53_G7_U1_20 : ADDFXL port map( A =>
BOOTH_instance_decoded_4_20_port, B =>
BOOTH_instance_decoded_5_20_port, CI =>
BOOTH_instance_add_5_root_add_53_G7_carry_20_port,
CO =>
BOOTH_instance_add_5_root_add_53_G7_carry_21_port, S
=> BOOTH_instance_partial_products_4_20_port);
BOOTH_instance_add_5_root_add_53_G7_U1_18 : ADDFXL port map( A =>
BOOTH_instance_decoded_4_18_port, B =>
BOOTH_instance_decoded_5_18_port, CI =>
BOOTH_instance_add_5_root_add_53_G7_carry_18_port,
CO =>
BOOTH_instance_add_5_root_add_53_G7_carry_19_port, S
=> BOOTH_instance_partial_products_4_18_port);
BOOTH_instance_add_5_root_add_53_G7_U1_17 : ADDFXL port map( A =>
BOOTH_instance_decoded_4_17_port, B =>
BOOTH_instance_decoded_5_17_port, CI =>
BOOTH_instance_add_5_root_add_53_G7_carry_17_port,
CO =>
BOOTH_instance_add_5_root_add_53_G7_carry_18_port, S
=> BOOTH_instance_partial_products_4_17_port);
BOOTH_instance_add_5_root_add_53_G7_U1_16 : ADDFXL port map( A =>
BOOTH_instance_decoded_4_16_port, B =>
BOOTH_instance_decoded_5_16_port, CI =>
BOOTH_instance_add_5_root_add_53_G7_carry_16_port,
CO =>
BOOTH_instance_add_5_root_add_53_G7_carry_17_port, S
=> BOOTH_instance_partial_products_4_16_port);
BOOTH_instance_add_6_root_add_53_G7_U1_13 : ADDFXL port map( A =>
BOOTH_instance_decoded_2_13_port, B =>
BOOTH_instance_decoded_3_13_port, CI =>
BOOTH_instance_add_6_root_add_53_G7_carry_13_port,
CO =>
BOOTH_instance_add_6_root_add_53_G7_carry_14_port, S
=> BOOTH_instance_partial_products_3_13_port);
BOOTH_instance_add_7_root_add_53_G7_U1_9 : ADDFHXL port map( A =>
BOOTH_instance_N218_port, B =>
BOOTH_instance_decoded_1_9_port, CI =>
BOOTH_instance_add_7_root_add_53_G7_carry_9_port, CO
=> BOOTH_instance_add_7_root_add_53_G7_carry_10_port
, S => BOOTH_instance_partial_products_8_9_port);
BOOTH_instance_add_7_root_add_53_G7_U1_8 : ADDFHXL port map( A =>
BOOTH_instance_N217_port, B =>
BOOTH_instance_decoded_1_8_port, CI =>
BOOTH_instance_add_7_root_add_53_G7_carry_8_port, CO
=> BOOTH_instance_add_7_root_add_53_G7_carry_9_port,
S => BOOTH_instance_partial_products_8_8_port);
BOOTH_instance_add_7_root_add_53_G7_U1_4 : ADDFHXL port map( A =>
BOOTH_instance_N213_port, B =>
BOOTH_instance_decoded_1_4_port, CI =>
BOOTH_instance_add_7_root_add_53_G7_carry_4_port, CO
=> BOOTH_instance_add_7_root_add_53_G7_carry_5_port,
S => BOOTH_instance_partial_products_8_4_port);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_RCA0_add_1_root_add_20_2_U1_1 :
ADDFXL port map( A => n2118, B =>
ALU_instance_INTERNAL_B_5_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_RCA0_add_1_root_add_20_2_carry_1_port,
CO =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_RCA0_add_1_root_add_20_2_carry_2_port, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_S0_1_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_RCA0_add_1_root_add_20_2_U1_1 :
ADDFXL port map( A => N4719, B =>
ALU_instance_INTERNAL_B_1_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_RCA0_add_1_root_add_20_2_carry_1_port,
CO =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_RCA0_add_1_root_add_20_2_carry_2_port, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_S0_1_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_RCA1_add_1_root_add_20_2_U1_1 :
ADDFXL port map( A => n2117, B =>
ALU_instance_INTERNAL_B_5_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_RCA1_add_1_root_add_20_2_carry_1_port,
CO =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_RCA1_add_1_root_add_20_2_carry_2_port, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_S1_1_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_RCA1_add_1_root_add_20_2_U1_1 :
ADDFXL port map( A => n2116, B =>
ALU_instance_INTERNAL_B_1_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_RCA1_add_1_root_add_20_2_carry_1_port,
CO =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_RCA1_add_1_root_add_20_2_carry_2_port, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_S1_1_port
);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_1_28 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_28_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_26_port,
S0 => n1601, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_28_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_2_28 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_28_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_24_port,
S0 => n2160, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_28_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_3_28 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_28_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_20_port,
S0 => n2175, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_28_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_1_29 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_29_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_27_port,
S0 => n1601, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_29_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_2_29 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_29_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_25_port,
S0 => n2161, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_29_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_3_29 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_29_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_21_port,
S0 => n2175, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_29_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_0_3 : MX2XL port map( A => N4721, B =>
n2193, S0 => n2164, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_3_port);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_1_4 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_4_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_2_port,
S0 => n1601, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_4_port);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_1_5 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_5_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_3_port,
S0 => n1601, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_5_port);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_1_6 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_6_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_4_port,
S0 => n1601, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_6_port);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_1_7 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_7_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_5_port,
S0 => n1601, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_7_port);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_1_8 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_8_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_6_port,
S0 => n1601, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_8_port);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_1_9 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_9_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_7_port,
S0 => n1601, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_9_port);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_1_10 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_10_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_8_port,
S0 => n1601, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_10_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_1_11 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_11_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_9_port,
S0 => n1601, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_11_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_1_12 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_12_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_10_port,
S0 => n1601, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_12_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_1_13 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_13_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_11_port,
S0 => n2159, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_13_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_1_14 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_14_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_12_port,
S0 => n2158, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_14_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_1_15 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_15_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_13_port,
S0 => n1601, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_15_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_1_16 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_16_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_14_port,
S0 => n1601, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_16_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_1_17 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_17_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_15_port,
S0 => n1601, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_17_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_1_18 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_18_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_16_port,
S0 => n1601, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_18_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_1_19 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_19_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_17_port,
S0 => n1601, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_19_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_1_20 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_20_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_18_port,
S0 => n1601, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_20_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_1_21 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_21_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_19_port,
S0 => n1601, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_21_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_1_22 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_22_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_20_port,
S0 => n1601, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_22_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_1_23 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_23_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_21_port,
S0 => n1601, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_23_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_1_24 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_24_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_22_port,
S0 => n1601, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_24_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_1_25 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_25_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_23_port,
S0 => n1601, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_25_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_1_26 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_26_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_24_port,
S0 => n1601, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_26_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_1_27 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_27_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_25_port,
S0 => n1601, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_27_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_0_10 : MX2XL port map( A => n2183, B
=> n2185, S0 => n2164, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_10_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_0_11 : MX2XL port map( A => n2181, B
=> n2183, S0 => n2164, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_11_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_1_2 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_2_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_0_port,
S0 => n1601, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_2_port);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_1_3 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_3_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_1_port,
S0 => n1601, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_3_port);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_2_4 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_4_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_0_port,
S0 => n1602, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_4_port);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_2_5 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_5_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_1_port,
S0 => n2161, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_5_port);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_RCA0_add_1_root_add_20_2_U1_3 :
ADDFXL port map( A => n2181, B =>
ALU_instance_INTERNAL_B_11_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_RCA0_add_1_root_add_20_2_carry_3_port,
CO => ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_C0, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_S0_3_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_RCA1_add_1_root_add_20_2_U1_3 :
ADDFXL port map( A => n2181, B =>
ALU_instance_INTERNAL_B_11_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_RCA1_add_1_root_add_20_2_carry_3_port,
CO => ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_C1, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_S1_3_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_RCA1_add_1_root_add_20_2_U1_2 :
ADDFXL port map( A => n2183, B =>
ALU_instance_INTERNAL_B_10_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_RCA1_add_1_root_add_20_2_carry_2_port,
CO =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_RCA1_add_1_root_add_20_2_carry_3_port, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_S1_2_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_RCA0_add_1_root_add_20_2_U1_2 :
ADDFXL port map( A => n2183, B =>
ALU_instance_INTERNAL_B_10_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_RCA0_add_1_root_add_20_2_carry_2_port,
CO =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_RCA0_add_1_root_add_20_2_carry_3_port, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_S0_2_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_RCA1_add_1_root_add_20_2_U1_2 :
ADDFXL port map( A => n2177, B =>
ALU_instance_INTERNAL_B_14_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_RCA1_add_1_root_add_20_2_carry_2_port,
CO =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_RCA1_add_1_root_add_20_2_carry_3_port, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_S1_2_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_RCA0_add_1_root_add_20_2_U1_2 :
ADDFXL port map( A => n2177, B =>
ALU_instance_INTERNAL_B_14_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_RCA0_add_1_root_add_20_2_carry_2_port,
CO =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_RCA0_add_1_root_add_20_2_carry_3_port, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_S0_2_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_RCA0_add_1_root_add_20_2_U1_1 :
ADDFXL port map( A => n2185, B =>
ALU_instance_INTERNAL_B_9_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_RCA0_add_1_root_add_20_2_carry_1_port,
CO =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_RCA0_add_1_root_add_20_2_carry_2_port, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_S0_1_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_RCA1_add_1_root_add_20_2_U1_1 :
ADDFXL port map( A => n2185, B =>
ALU_instance_INTERNAL_B_9_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_RCA1_add_1_root_add_20_2_carry_1_port,
CO =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_RCA1_add_1_root_add_20_2_carry_2_port, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_S1_1_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_RCA1_add_1_root_add_20_2_U1_1 :
ADDFXL port map( A => n2178, B =>
ALU_instance_INTERNAL_B_13_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_RCA1_add_1_root_add_20_2_carry_1_port,
CO =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_RCA1_add_1_root_add_20_2_carry_2_port, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_S1_1_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_RCA0_add_1_root_add_20_2_U1_1 :
ADDFXL port map( A => n2178, B =>
ALU_instance_INTERNAL_B_13_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_RCA0_add_1_root_add_20_2_carry_1_port,
CO =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_RCA0_add_1_root_add_20_2_carry_2_port, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_S0_1_port
);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_4_28 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_28_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_12_port,
S0 => n2167, Y =>
ALU_instance_SHIFTER_GENERIC_I_N262);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_4_29 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_29_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_13_port,
S0 => N4831, Y =>
ALU_instance_SHIFTER_GENERIC_I_N263);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_4_30 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_30_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_14_port,
S0 => N4831, Y =>
ALU_instance_SHIFTER_GENERIC_I_N264);
BOOTH_instance_add_0_root_add_53_G7_U1_31 : XOR3XL port map( A =>
BOOTH_instance_partial_products_7_31_port, B =>
BOOTH_instance_partial_products_8_31_port, C =>
BOOTH_instance_add_0_root_add_53_G7_carry_31_port, Y
=> EX_MULT_OUT_31_port);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_RCA0_add_1_root_add_20_2_U1_3 :
ADDFXL port map( A => n2189, B =>
ALU_instance_INTERNAL_B_7_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_RCA0_add_1_root_add_20_2_carry_3_port,
CO => ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_C0, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_S0_3_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_RCA1_add_1_root_add_20_2_U1_3 :
ADDFXL port map( A => n2189, B =>
ALU_instance_INTERNAL_B_7_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_RCA1_add_1_root_add_20_2_carry_3_port,
CO => ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_C1, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_S1_3_port
);
BOOTH_instance_add_3_root_add_53_G7_U1_30 : ADDFHXL port map( A =>
BOOTH_instance_decoded_8_30_port, B =>
BOOTH_instance_partial_products_2_30_port, CI =>
BOOTH_instance_add_3_root_add_53_G7_carry_30_port,
CO =>
BOOTH_instance_add_3_root_add_53_G7_carry_31_port, S
=> BOOTH_instance_partial_products_6_30_port);
BOOTH_instance_add_1_root_add_53_G7_U1_13 : ADDFHXL port map( A =>
BOOTH_instance_partial_products_5_13_port, B =>
BOOTH_instance_partial_products_6_13_port, CI =>
BOOTH_instance_add_1_root_add_53_G7_carry_13_port,
CO =>
BOOTH_instance_add_1_root_add_53_G7_carry_14_port, S
=> BOOTH_instance_partial_products_8_13_port);
BOOTH_instance_add_5_root_add_53_G7_U1_11 : ADDFXL port map( A =>
BOOTH_instance_decoded_4_11_port, B =>
BOOTH_instance_decoded_5_11_port, CI =>
BOOTH_instance_add_5_root_add_53_G7_carry_11_port,
CO =>
BOOTH_instance_add_5_root_add_53_G7_carry_12_port, S
=> BOOTH_instance_partial_products_4_11_port);
BOOTH_instance_add_6_root_add_53_G7_U1_7 : ADDFXL port map( A =>
BOOTH_instance_decoded_2_7_port, B =>
BOOTH_instance_decoded_3_7_port, CI =>
BOOTH_instance_add_6_root_add_53_G7_carry_7_port, CO
=> BOOTH_instance_add_6_root_add_53_G7_carry_8_port,
S => BOOTH_instance_partial_products_7_7_port);
BOOTH_instance_add_0_root_add_53_G7_U1_5 : ADDFXL port map( A =>
BOOTH_instance_partial_products_7_5_port, B =>
BOOTH_instance_partial_products_8_5_port, CI =>
BOOTH_instance_add_0_root_add_53_G7_carry_5_port, CO
=> BOOTH_instance_add_0_root_add_53_G7_carry_6_port,
S => EX_MULT_OUT_5_port);
BOOTH_instance_add_7_root_add_53_G7_U1_3 : ADDFHXL port map( A =>
BOOTH_instance_N212_port, B =>
BOOTH_instance_decoded_1_3_port, CI =>
BOOTH_instance_add_7_root_add_53_G7_carry_3_port, CO
=> BOOTH_instance_add_7_root_add_53_G7_carry_4_port,
S => EX_MULT_OUT_3_port);
BOOTH_instance_add_3_root_add_53_G7_U1_29 : ADDFHXL port map( A =>
BOOTH_instance_decoded_8_29_port, B =>
BOOTH_instance_partial_products_2_29_port, CI =>
BOOTH_instance_add_3_root_add_53_G7_carry_29_port,
CO =>
BOOTH_instance_add_3_root_add_53_G7_carry_30_port, S
=> BOOTH_instance_partial_products_6_29_port);
BOOTH_instance_add_3_root_add_53_G7_U1_28 : ADDFHXL port map( A =>
BOOTH_instance_decoded_8_28_port, B =>
BOOTH_instance_partial_products_2_28_port, CI =>
BOOTH_instance_add_3_root_add_53_G7_carry_28_port,
CO =>
BOOTH_instance_add_3_root_add_53_G7_carry_29_port, S
=> BOOTH_instance_partial_products_6_28_port);
BOOTH_instance_add_1_root_add_53_G7_U1_26 : ADDFHXL port map( A =>
BOOTH_instance_partial_products_5_26_port, B =>
BOOTH_instance_partial_products_6_26_port, CI =>
BOOTH_instance_add_1_root_add_53_G7_carry_26_port,
CO =>
BOOTH_instance_add_1_root_add_53_G7_carry_27_port, S
=> BOOTH_instance_partial_products_8_26_port);
BOOTH_instance_add_3_root_add_53_G7_U1_27 : ADDFHXL port map( A =>
BOOTH_instance_decoded_8_27_port, B =>
BOOTH_instance_partial_products_2_27_port, CI =>
BOOTH_instance_add_3_root_add_53_G7_carry_27_port,
CO =>
BOOTH_instance_add_3_root_add_53_G7_carry_28_port, S
=> BOOTH_instance_partial_products_6_27_port);
BOOTH_instance_add_5_root_add_53_G7_U1_26 : ADDFXL port map( A =>
BOOTH_instance_decoded_4_31_port, B =>
BOOTH_instance_decoded_5_26_port, CI =>
BOOTH_instance_add_5_root_add_53_G7_carry_26_port,
CO =>
BOOTH_instance_add_5_root_add_53_G7_carry_27_port, S
=> BOOTH_instance_partial_products_4_26_port);
BOOTH_instance_add_5_root_add_53_G7_U1_25 : ADDFXL port map( A =>
BOOTH_instance_decoded_4_31_port, B =>
BOOTH_instance_decoded_5_25_port, CI =>
BOOTH_instance_add_5_root_add_53_G7_carry_25_port,
CO =>
BOOTH_instance_add_5_root_add_53_G7_carry_26_port, S
=> BOOTH_instance_partial_products_4_25_port);
BOOTH_instance_add_1_root_add_53_G7_U1_24 : ADDFHXL port map( A =>
BOOTH_instance_partial_products_5_24_port, B =>
BOOTH_instance_partial_products_6_24_port, CI =>
BOOTH_instance_add_1_root_add_53_G7_carry_24_port,
CO =>
BOOTH_instance_add_1_root_add_53_G7_carry_25_port, S
=> BOOTH_instance_partial_products_8_24_port);
BOOTH_instance_add_3_root_add_53_G7_U1_25 : ADDFHXL port map( A =>
BOOTH_instance_decoded_8_25_port, B =>
BOOTH_instance_partial_products_2_25_port, CI =>
BOOTH_instance_add_3_root_add_53_G7_carry_25_port,
CO =>
BOOTH_instance_add_3_root_add_53_G7_carry_26_port, S
=> BOOTH_instance_partial_products_6_25_port);
BOOTH_instance_add_5_root_add_53_G7_U1_24 : ADDFXL port map( A =>
BOOTH_instance_decoded_4_24_port, B =>
BOOTH_instance_decoded_5_24_port, CI =>
BOOTH_instance_add_5_root_add_53_G7_carry_24_port,
CO =>
BOOTH_instance_add_5_root_add_53_G7_carry_25_port, S
=> BOOTH_instance_partial_products_4_24_port);
BOOTH_instance_add_3_root_add_53_G7_U1_24 : ADDFHXL port map( A =>
BOOTH_instance_decoded_8_24_port, B =>
BOOTH_instance_partial_products_2_24_port, CI =>
BOOTH_instance_add_3_root_add_53_G7_carry_24_port,
CO =>
BOOTH_instance_add_3_root_add_53_G7_carry_25_port, S
=> BOOTH_instance_partial_products_6_24_port);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_RCA1_add_1_root_add_20_2_U1_2 :
ADDFXL port map( A => n2193, B =>
ALU_instance_INTERNAL_B_2_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_RCA1_add_1_root_add_20_2_carry_2_port,
CO =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_RCA1_add_1_root_add_20_2_carry_3_port, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_S1_2_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_RCA0_add_1_root_add_20_2_U1_2 :
ADDFXL port map( A => n2193, B =>
ALU_instance_INTERNAL_B_2_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_RCA0_add_1_root_add_20_2_carry_2_port,
CO =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_RCA0_add_1_root_add_20_2_carry_3_port, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_S0_2_port
);
BOOTH_instance_add_5_root_add_53_G7_U1_23 : ADDFXL port map( A =>
BOOTH_instance_decoded_4_23_port, B =>
BOOTH_instance_decoded_5_23_port, CI =>
BOOTH_instance_add_5_root_add_53_G7_carry_23_port,
CO =>
BOOTH_instance_add_5_root_add_53_G7_carry_24_port, S
=> BOOTH_instance_partial_products_4_23_port);
BOOTH_instance_add_1_root_add_53_G7_U1_22 : ADDFHXL port map( A =>
BOOTH_instance_partial_products_5_22_port, B =>
BOOTH_instance_partial_products_6_22_port, CI =>
BOOTH_instance_add_1_root_add_53_G7_carry_22_port,
CO =>
BOOTH_instance_add_1_root_add_53_G7_carry_23_port, S
=> BOOTH_instance_partial_products_8_22_port);
BOOTH_instance_add_3_root_add_53_G7_U1_23 : ADDFHXL port map( A =>
BOOTH_instance_decoded_8_23_port, B =>
BOOTH_instance_partial_products_2_23_port, CI =>
BOOTH_instance_add_3_root_add_53_G7_carry_23_port,
CO =>
BOOTH_instance_add_3_root_add_53_G7_carry_24_port, S
=> BOOTH_instance_partial_products_6_23_port);
BOOTH_instance_add_5_root_add_53_G7_U1_22 : ADDFXL port map( A =>
BOOTH_instance_decoded_4_22_port, B =>
BOOTH_instance_decoded_5_22_port, CI =>
BOOTH_instance_add_5_root_add_53_G7_carry_22_port,
CO =>
BOOTH_instance_add_5_root_add_53_G7_carry_23_port, S
=> BOOTH_instance_partial_products_4_22_port);
BOOTH_instance_add_6_root_add_53_G7_U1_22 : ADDFXL port map( A =>
BOOTH_instance_decoded_2_31_port, B =>
BOOTH_instance_decoded_3_22_port, CI =>
BOOTH_instance_add_6_root_add_53_G7_carry_22_port,
CO =>
BOOTH_instance_add_6_root_add_53_G7_carry_23_port, S
=> BOOTH_instance_partial_products_3_22_port);
BOOTH_instance_add_1_root_add_53_G7_U1_21 : ADDFHXL port map( A =>
BOOTH_instance_partial_products_5_21_port, B =>
BOOTH_instance_partial_products_6_21_port, CI =>
BOOTH_instance_add_1_root_add_53_G7_carry_21_port,
CO =>
BOOTH_instance_add_1_root_add_53_G7_carry_22_port, S
=> BOOTH_instance_partial_products_8_21_port);
BOOTH_instance_add_3_root_add_53_G7_U1_22 : ADDFHXL port map( A =>
BOOTH_instance_decoded_8_22_port, B =>
BOOTH_instance_partial_products_2_22_port, CI =>
BOOTH_instance_add_3_root_add_53_G7_carry_22_port,
CO =>
BOOTH_instance_add_3_root_add_53_G7_carry_23_port, S
=> BOOTH_instance_partial_products_6_22_port);
BOOTH_instance_add_5_root_add_53_G7_U1_21 : ADDFXL port map( A =>
BOOTH_instance_decoded_4_21_port, B =>
BOOTH_instance_decoded_5_21_port, CI =>
BOOTH_instance_add_5_root_add_53_G7_carry_21_port,
CO =>
BOOTH_instance_add_5_root_add_53_G7_carry_22_port, S
=> BOOTH_instance_partial_products_4_21_port);
BOOTH_instance_add_2_root_add_53_G7_U1_20 : ADDFXL port map( A =>
BOOTH_instance_partial_products_3_20_port, B =>
BOOTH_instance_partial_products_4_20_port, CI =>
BOOTH_instance_add_2_root_add_53_G7_carry_20_port,
CO =>
BOOTH_instance_add_2_root_add_53_G7_carry_21_port, S
=> BOOTH_instance_partial_products_7_20_port);
BOOTH_instance_add_1_root_add_53_G7_U1_20 : ADDFHXL port map( A =>
BOOTH_instance_partial_products_5_20_port, B =>
BOOTH_instance_partial_products_6_20_port, CI =>
BOOTH_instance_add_1_root_add_53_G7_carry_20_port,
CO =>
BOOTH_instance_add_1_root_add_53_G7_carry_21_port, S
=> BOOTH_instance_partial_products_8_20_port);
BOOTH_instance_add_3_root_add_53_G7_U1_21 : ADDFHXL port map( A =>
BOOTH_instance_decoded_8_21_port, B =>
BOOTH_instance_partial_products_2_21_port, CI =>
BOOTH_instance_add_3_root_add_53_G7_carry_21_port,
CO =>
BOOTH_instance_add_3_root_add_53_G7_carry_22_port, S
=> BOOTH_instance_partial_products_6_21_port);
BOOTH_instance_add_5_root_add_53_G7_U1_19 : ADDFXL port map( A =>
BOOTH_instance_decoded_4_19_port, B =>
BOOTH_instance_decoded_5_19_port, CI =>
BOOTH_instance_add_5_root_add_53_G7_carry_19_port,
CO =>
BOOTH_instance_add_5_root_add_53_G7_carry_20_port, S
=> BOOTH_instance_partial_products_4_19_port);
BOOTH_instance_add_2_root_add_53_G7_U1_18 : ADDFXL port map( A =>
BOOTH_instance_partial_products_3_18_port, B =>
BOOTH_instance_partial_products_4_18_port, CI =>
BOOTH_instance_add_2_root_add_53_G7_carry_18_port,
CO =>
BOOTH_instance_add_2_root_add_53_G7_carry_19_port, S
=> BOOTH_instance_partial_products_7_18_port);
BOOTH_instance_add_1_root_add_53_G7_U1_18 : ADDFHXL port map( A =>
BOOTH_instance_partial_products_5_18_port, B =>
BOOTH_instance_partial_products_6_18_port, CI =>
BOOTH_instance_add_1_root_add_53_G7_carry_18_port,
CO =>
BOOTH_instance_add_1_root_add_53_G7_carry_19_port, S
=> BOOTH_instance_partial_products_8_18_port);
BOOTH_instance_add_3_root_add_53_G7_U1_19 : ADDFHXL port map( A =>
BOOTH_instance_decoded_8_19_port, B =>
BOOTH_instance_partial_products_2_19_port, CI =>
BOOTH_instance_add_3_root_add_53_G7_carry_19_port,
CO =>
BOOTH_instance_add_3_root_add_53_G7_carry_20_port, S
=> BOOTH_instance_partial_products_6_19_port);
BOOTH_instance_add_2_root_add_53_G7_U1_17 : ADDFXL port map( A =>
BOOTH_instance_partial_products_3_17_port, B =>
BOOTH_instance_partial_products_4_17_port, CI =>
BOOTH_instance_add_2_root_add_53_G7_carry_17_port,
CO =>
BOOTH_instance_add_2_root_add_53_G7_carry_18_port, S
=> BOOTH_instance_partial_products_7_17_port);
BOOTH_instance_add_6_root_add_53_G7_U1_18 : ADDFXL port map( A =>
BOOTH_instance_decoded_2_18_port, B =>
BOOTH_instance_decoded_3_18_port, CI =>
BOOTH_instance_add_6_root_add_53_G7_carry_18_port,
CO =>
BOOTH_instance_add_6_root_add_53_G7_carry_19_port, S
=> BOOTH_instance_partial_products_3_18_port);
BOOTH_instance_add_1_root_add_53_G7_U1_15 : ADDFHXL port map( A =>
BOOTH_instance_partial_products_5_15_port, B =>
BOOTH_instance_partial_products_6_15_port, CI =>
BOOTH_instance_add_1_root_add_53_G7_carry_15_port,
CO =>
BOOTH_instance_add_1_root_add_53_G7_carry_16_port, S
=> BOOTH_instance_partial_products_8_15_port);
BOOTH_instance_add_7_root_add_53_G7_U1_17 : ADDFHXL port map( A =>
BOOTH_instance_decoded_0_31_port, B =>
BOOTH_instance_decoded_1_17_port, CI =>
BOOTH_instance_add_7_root_add_53_G7_carry_17_port,
CO =>
BOOTH_instance_add_7_root_add_53_G7_carry_18_port, S
=> BOOTH_instance_partial_products_2_17_port);
BOOTH_instance_add_5_root_add_53_G7_U1_15 : ADDFXL port map( A =>
BOOTH_instance_decoded_4_15_port, B =>
BOOTH_instance_decoded_5_15_port, CI =>
BOOTH_instance_add_5_root_add_53_G7_carry_15_port,
CO =>
BOOTH_instance_add_5_root_add_53_G7_carry_16_port, S
=> BOOTH_instance_partial_products_4_15_port);
BOOTH_instance_add_2_root_add_53_G7_U1_14 : ADDFXL port map( A =>
BOOTH_instance_partial_products_3_14_port, B =>
BOOTH_instance_partial_products_4_14_port, CI =>
BOOTH_instance_add_2_root_add_53_G7_carry_14_port,
CO =>
BOOTH_instance_add_2_root_add_53_G7_carry_15_port, S
=> BOOTH_instance_partial_products_7_14_port);
BOOTH_instance_add_6_root_add_53_G7_U1_15 : ADDFXL port map( A =>
BOOTH_instance_decoded_2_15_port, B =>
BOOTH_instance_decoded_3_15_port, CI =>
BOOTH_instance_add_6_root_add_53_G7_carry_15_port,
CO =>
BOOTH_instance_add_6_root_add_53_G7_carry_16_port, S
=> BOOTH_instance_partial_products_3_15_port);
BOOTH_instance_add_5_root_add_53_G7_U1_14 : ADDFXL port map( A =>
BOOTH_instance_decoded_4_14_port, B =>
BOOTH_instance_decoded_5_14_port, CI =>
BOOTH_instance_add_5_root_add_53_G7_carry_14_port,
CO =>
BOOTH_instance_add_5_root_add_53_G7_carry_15_port, S
=> BOOTH_instance_partial_products_4_14_port);
BOOTH_instance_add_5_root_add_53_G7_U1_13 : ADDFXL port map( A =>
BOOTH_instance_decoded_4_13_port, B =>
BOOTH_instance_decoded_5_13_port, CI =>
BOOTH_instance_add_5_root_add_53_G7_carry_13_port,
CO =>
BOOTH_instance_add_5_root_add_53_G7_carry_14_port, S
=> BOOTH_instance_partial_products_4_13_port);
BOOTH_instance_add_7_root_add_53_G7_U1_14 : ADDFHXL port map( A =>
BOOTH_instance_N223_port, B =>
BOOTH_instance_decoded_1_14_port, CI =>
BOOTH_instance_add_7_root_add_53_G7_carry_14_port,
CO =>
BOOTH_instance_add_7_root_add_53_G7_carry_15_port, S
=> BOOTH_instance_partial_products_6_14_port);
BOOTH_instance_add_5_root_add_53_G7_U1_12 : ADDFXL port map( A =>
BOOTH_instance_decoded_4_12_port, B =>
BOOTH_instance_decoded_5_12_port, CI =>
BOOTH_instance_add_5_root_add_53_G7_carry_12_port,
CO =>
BOOTH_instance_add_5_root_add_53_G7_carry_13_port, S
=> BOOTH_instance_partial_products_4_12_port);
BOOTH_instance_add_0_root_add_53_G7_U1_10 : ADDFXL port map( A =>
BOOTH_instance_partial_products_7_10_port, B =>
BOOTH_instance_partial_products_8_10_port, CI =>
BOOTH_instance_add_0_root_add_53_G7_carry_10_port,
CO =>
BOOTH_instance_add_0_root_add_53_G7_carry_11_port, S
=> EX_MULT_OUT_10_port);
BOOTH_instance_add_2_root_add_53_G7_U1_10 : ADDFXL port map( A =>
BOOTH_instance_partial_products_3_10_port, B =>
BOOTH_instance_partial_products_4_10_port, CI =>
BOOTH_instance_add_2_root_add_53_G7_carry_10_port,
CO =>
BOOTH_instance_add_2_root_add_53_G7_carry_11_port, S
=> BOOTH_instance_partial_products_7_10_port);
BOOTH_instance_add_6_root_add_53_G7_U1_11 : ADDFXL port map( A =>
BOOTH_instance_decoded_2_11_port, B =>
BOOTH_instance_decoded_3_11_port, CI =>
BOOTH_instance_add_6_root_add_53_G7_carry_11_port,
CO =>
BOOTH_instance_add_6_root_add_53_G7_carry_12_port, S
=> BOOTH_instance_partial_products_3_11_port);
BOOTH_instance_add_7_root_add_53_G7_U1_11 : ADDFHXL port map( A =>
BOOTH_instance_N220, B =>
BOOTH_instance_decoded_1_11_port, CI =>
BOOTH_instance_add_7_root_add_53_G7_carry_11_port,
CO =>
BOOTH_instance_add_7_root_add_53_G7_carry_12_port, S
=> BOOTH_instance_partial_products_8_11_port);
BOOTH_instance_add_0_root_add_53_G7_U1_8 : ADDFXL port map( A =>
BOOTH_instance_partial_products_7_8_port, B =>
BOOTH_instance_partial_products_8_8_port, CI =>
BOOTH_instance_add_0_root_add_53_G7_carry_8_port, CO
=> BOOTH_instance_add_0_root_add_53_G7_carry_9_port,
S => EX_MULT_OUT_8_port);
BOOTH_instance_add_6_root_add_53_G7_U1_9 : ADDFXL port map( A =>
BOOTH_instance_decoded_2_9_port, B =>
BOOTH_instance_decoded_3_9_port, CI =>
BOOTH_instance_add_6_root_add_53_G7_carry_9_port, CO
=> BOOTH_instance_add_6_root_add_53_G7_carry_10_port
, S => BOOTH_instance_partial_products_3_9_port);
BOOTH_instance_add_0_root_add_53_G7_U1_6 : ADDFXL port map( A =>
BOOTH_instance_partial_products_7_6_port, B =>
BOOTH_instance_partial_products_8_6_port, CI =>
BOOTH_instance_add_0_root_add_53_G7_carry_6_port, CO
=> BOOTH_instance_add_0_root_add_53_G7_carry_7_port,
S => EX_MULT_OUT_6_port);
BOOTH_instance_add_7_root_add_53_G7_U1_7 : ADDFHXL port map( A =>
BOOTH_instance_N216_port, B =>
BOOTH_instance_decoded_1_7_port, CI =>
BOOTH_instance_add_7_root_add_53_G7_carry_7_port, CO
=> BOOTH_instance_add_7_root_add_53_G7_carry_8_port,
S => BOOTH_instance_partial_products_8_7_port);
BOOTH_instance_add_7_root_add_53_G7_U1_6 : ADDFHXL port map( A =>
BOOTH_instance_N215_port, B =>
BOOTH_instance_decoded_1_6_port, CI =>
BOOTH_instance_add_7_root_add_53_G7_carry_6_port, CO
=> BOOTH_instance_add_7_root_add_53_G7_carry_7_port,
S => BOOTH_instance_partial_products_8_6_port);
BOOTH_instance_add_3_root_add_53_G7_U1_31 : XOR3XL port map( A =>
BOOTH_instance_decoded_8_31_port, B =>
BOOTH_instance_partial_products_2_31_port, C =>
BOOTH_instance_add_3_root_add_53_G7_carry_31_port, Y
=> BOOTH_instance_partial_products_6_31_port);
BOOTH_instance_add_1_root_add_53_G7_U1_31 : XOR3XL port map( A =>
BOOTH_instance_partial_products_5_31_port, B =>
BOOTH_instance_partial_products_6_31_port, C =>
BOOTH_instance_add_1_root_add_53_G7_carry_31_port, Y
=> BOOTH_instance_partial_products_8_31_port);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_3_16 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_16_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_8_port,
S0 => n2175, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_16_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_3_17 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_17_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_9_port,
S0 => n2175, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_17_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_3_18 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_18_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_10_port,
S0 => n2175, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_18_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_3_19 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_19_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_11_port,
S0 => n2175, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_19_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_3_20 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_20_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_12_port,
S0 => n2175, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_20_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_3_21 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_21_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_13_port,
S0 => n2175, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_21_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_3_22 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_22_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_14_port,
S0 => n2175, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_22_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_3_23 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_23_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_15_port,
S0 => n2175, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_23_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_2_24 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_24_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_20_port,
S0 => n2160, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_24_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_3_24 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_24_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_16_port,
S0 => n2175, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_24_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_2_25 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_25_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_21_port,
S0 => n2161, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_25_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_3_25 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_25_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_17_port,
S0 => n2175, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_25_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_2_26 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_26_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_22_port,
S0 => n2161, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_26_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_3_26 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_26_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_18_port,
S0 => n2175, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_26_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_2_27 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_27_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_23_port,
S0 => n2160, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_27_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_3_27 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_27_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_19_port,
S0 => n2175, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_27_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_0_4 : MX2XL port map( A => n2190, B =>
N4721, S0 => n2164, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_4_port);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_0_8 : MX2XL port map( A => n2187, B =>
n2189, S0 => n2164, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_8_port);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_0_9 : MX2XL port map( A => n2185, B =>
n2187, S0 => n2164, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_9_port);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_0_12 : MX2XL port map( A => n2179, B
=> n2181, S0 => n2164, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_12_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_0_13 : MX2XL port map( A => n2178, B
=> n2179, S0 => n2164, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_13_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_0_14 : MX2XL port map( A => n2177, B
=> n2178, S0 => n2164, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_14_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_2_8 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_8_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_4_port,
S0 => n1602, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_8_port);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_2_9 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_9_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_5_port,
S0 => n2160, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_9_port);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_2_10 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_10_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_6_port,
S0 => n2161, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_10_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_2_11 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_11_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_7_port,
S0 => n2161, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_11_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_2_12 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_12_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_8_port,
S0 => n1602, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_12_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_2_13 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_13_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_9_port,
S0 => n2160, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_13_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_2_14 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_14_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_10_port,
S0 => n2160, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_14_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_2_15 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_15_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_11_port,
S0 => n2161, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_15_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_2_16 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_16_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_12_port,
S0 => n2160, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_16_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_2_17 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_17_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_13_port,
S0 => n2160, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_17_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_2_18 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_18_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_14_port,
S0 => n2161, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_18_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_2_19 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_19_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_15_port,
S0 => n2161, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_19_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_2_20 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_20_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_16_port,
S0 => n1602, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_20_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_2_21 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_21_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_17_port,
S0 => n1602, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_21_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_2_22 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_22_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_18_port,
S0 => n1602, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_22_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_2_23 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_23_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_19_port,
S0 => n1602, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_23_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_3_12 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_12_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_4_port,
S0 => n2175, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_12_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_3_13 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_13_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_5_port,
S0 => n2175, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_13_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_3_14 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_14_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_6_port,
S0 => n2175, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_14_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_3_15 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_15_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_7_port,
S0 => n2175, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_15_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_3_8 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_8_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_0_port,
S0 => n2175, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_8_port);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_3_9 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_9_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_1_port,
S0 => n2175, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_9_port);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_3_10 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_10_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_2_port,
S0 => n2175, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_10_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_3_11 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_11_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_3_port,
S0 => n2175, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_11_port)
;
ALU_instance_SHIFTER_GENERIC_I_C88_M1_2_6 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_6_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_2_port,
S0 => n2160, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_6_port);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_2_7 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_7_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_3_port,
S0 => n2160, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_7_port);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_4_16 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_16_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_0_port,
S0 => n2171, Y =>
ALU_instance_SHIFTER_GENERIC_I_N250);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_4_17 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_17_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_1_port,
S0 => n2171, Y =>
ALU_instance_SHIFTER_GENERIC_I_N251);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_4_20 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_20_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_4_port,
S0 => n2171, Y =>
ALU_instance_SHIFTER_GENERIC_I_N254);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_4_18 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_18_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_2_port,
S0 => n2171, Y =>
ALU_instance_SHIFTER_GENERIC_I_N252);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_4_19 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_19_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_3_port,
S0 => n2167, Y =>
ALU_instance_SHIFTER_GENERIC_I_N253);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_4_21 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_21_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_5_port,
S0 => N4831, Y =>
ALU_instance_SHIFTER_GENERIC_I_N255);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_4_22 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_22_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_6_port,
S0 => N4831, Y =>
ALU_instance_SHIFTER_GENERIC_I_N256);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_4_23 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_23_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_7_port,
S0 => n2167, Y =>
ALU_instance_SHIFTER_GENERIC_I_N257);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_4_24 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_24_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_8_port,
S0 => N4831, Y =>
ALU_instance_SHIFTER_GENERIC_I_N258);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_4_25 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_25_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_9_port,
S0 => N4831, Y =>
ALU_instance_SHIFTER_GENERIC_I_N259);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_4_26 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_26_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_10_port,
S0 => N4831, Y =>
ALU_instance_SHIFTER_GENERIC_I_N260);
ALU_instance_SHIFTER_GENERIC_I_C88_M1_4_27 : MX2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_27_port,
B =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_11_port,
S0 => N4831, Y =>
ALU_instance_SHIFTER_GENERIC_I_N261);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_RCA0_add_1_root_add_20_2_U1_3 :
ADDFXL port map( A => N4721, B =>
ALU_instance_INTERNAL_B_3_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_RCA0_add_1_root_add_20_2_carry_3_port,
CO => ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_C0, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_S0_3_port
);
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_RCA1_add_1_root_add_20_2_U1_3 :
ADDFXL port map( A => N4721, B =>
ALU_instance_INTERNAL_B_3_port, CI =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_RCA1_add_1_root_add_20_2_carry_3_port,
CO => ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_C1, S
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_S1_3_port
);
BOOTH_instance_add_1_root_add_53_G7_U1_30 : ADDFHXL port map( A =>
BOOTH_instance_partial_products_5_30_port, B =>
BOOTH_instance_partial_products_6_30_port, CI =>
BOOTH_instance_add_1_root_add_53_G7_carry_30_port,
CO =>
BOOTH_instance_add_1_root_add_53_G7_carry_31_port, S
=> BOOTH_instance_partial_products_8_30_port);
BOOTH_instance_add_5_root_add_53_G7_U1_30 : ADDFXL port map( A =>
BOOTH_instance_decoded_4_31_port, B =>
BOOTH_instance_decoded_5_31_port, CI =>
BOOTH_instance_add_5_root_add_53_G7_carry_30_port,
CO =>
BOOTH_instance_add_5_root_add_53_G7_carry_31_port, S
=> BOOTH_instance_partial_products_4_30_port);
BOOTH_instance_add_1_root_add_53_G7_U1_29 : ADDFHXL port map( A =>
BOOTH_instance_partial_products_5_29_port, B =>
BOOTH_instance_partial_products_6_29_port, CI =>
BOOTH_instance_add_1_root_add_53_G7_carry_29_port,
CO =>
BOOTH_instance_add_1_root_add_53_G7_carry_30_port, S
=> BOOTH_instance_partial_products_8_29_port);
BOOTH_instance_add_5_root_add_53_G7_U1_29 : ADDFXL port map( A =>
BOOTH_instance_decoded_4_31_port, B =>
BOOTH_instance_decoded_5_31_port, CI =>
BOOTH_instance_add_5_root_add_53_G7_carry_29_port,
CO =>
BOOTH_instance_add_5_root_add_53_G7_carry_30_port, S
=> BOOTH_instance_partial_products_4_29_port);
BOOTH_instance_add_1_root_add_53_G7_U1_28 : ADDFHXL port map( A =>
BOOTH_instance_partial_products_5_28_port, B =>
BOOTH_instance_partial_products_6_28_port, CI =>
BOOTH_instance_add_1_root_add_53_G7_carry_28_port,
CO =>
BOOTH_instance_add_1_root_add_53_G7_carry_29_port, S
=> BOOTH_instance_partial_products_8_28_port);
BOOTH_instance_add_5_root_add_53_G7_U1_28 : ADDFXL port map( A =>
BOOTH_instance_decoded_4_31_port, B =>
BOOTH_instance_decoded_5_31_port, CI =>
BOOTH_instance_add_5_root_add_53_G7_carry_28_port,
CO =>
BOOTH_instance_add_5_root_add_53_G7_carry_29_port, S
=> BOOTH_instance_partial_products_4_28_port);
BOOTH_instance_add_1_root_add_53_G7_U1_27 : ADDFHXL port map( A =>
BOOTH_instance_partial_products_5_27_port, B =>
BOOTH_instance_partial_products_6_27_port, CI =>
BOOTH_instance_add_1_root_add_53_G7_carry_27_port,
CO =>
BOOTH_instance_add_1_root_add_53_G7_carry_28_port, S
=> BOOTH_instance_partial_products_8_27_port);
BOOTH_instance_add_5_root_add_53_G7_U1_27 : ADDFXL port map( A =>
BOOTH_instance_decoded_4_31_port, B =>
BOOTH_instance_decoded_5_31_port, CI =>
BOOTH_instance_add_5_root_add_53_G7_carry_27_port,
CO =>
BOOTH_instance_add_5_root_add_53_G7_carry_28_port, S
=> BOOTH_instance_partial_products_4_27_port);
BOOTH_instance_add_2_root_add_53_G7_U1_26 : ADDFXL port map( A =>
BOOTH_instance_partial_products_3_26_port, B =>
BOOTH_instance_partial_products_4_26_port, CI =>
BOOTH_instance_add_2_root_add_53_G7_carry_26_port,
CO =>
BOOTH_instance_add_2_root_add_53_G7_carry_27_port, S
=> BOOTH_instance_partial_products_7_26_port);
BOOTH_instance_add_2_root_add_53_G7_U1_25 : ADDFXL port map( A =>
BOOTH_instance_partial_products_3_25_port, B =>
BOOTH_instance_partial_products_4_25_port, CI =>
BOOTH_instance_add_2_root_add_53_G7_carry_25_port,
CO =>
BOOTH_instance_add_2_root_add_53_G7_carry_26_port, S
=> BOOTH_instance_partial_products_7_25_port);
BOOTH_instance_add_1_root_add_53_G7_U1_25 : ADDFHXL port map( A =>
BOOTH_instance_partial_products_5_25_port, B =>
BOOTH_instance_partial_products_6_25_port, CI =>
BOOTH_instance_add_1_root_add_53_G7_carry_25_port,
CO =>
BOOTH_instance_add_1_root_add_53_G7_carry_26_port, S
=> BOOTH_instance_partial_products_8_25_port);
BOOTH_instance_add_2_root_add_53_G7_U1_24 : ADDFXL port map( A =>
BOOTH_instance_partial_products_3_24_port, B =>
BOOTH_instance_partial_products_4_24_port, CI =>
BOOTH_instance_add_2_root_add_53_G7_carry_24_port,
CO =>
BOOTH_instance_add_2_root_add_53_G7_carry_25_port, S
=> BOOTH_instance_partial_products_7_24_port);
BOOTH_instance_add_2_root_add_53_G7_U1_23 : ADDFXL port map( A =>
BOOTH_instance_partial_products_3_23_port, B =>
BOOTH_instance_partial_products_4_23_port, CI =>
BOOTH_instance_add_2_root_add_53_G7_carry_23_port,
CO =>
BOOTH_instance_add_2_root_add_53_G7_carry_24_port, S
=> BOOTH_instance_partial_products_7_23_port);
BOOTH_instance_add_1_root_add_53_G7_U1_23 : ADDFHXL port map( A =>
BOOTH_instance_partial_products_5_23_port, B =>
BOOTH_instance_partial_products_6_23_port, CI =>
BOOTH_instance_add_1_root_add_53_G7_carry_23_port,
CO =>
BOOTH_instance_add_1_root_add_53_G7_carry_24_port, S
=> BOOTH_instance_partial_products_8_23_port);
BOOTH_instance_add_2_root_add_53_G7_U1_22 : ADDFXL port map( A =>
BOOTH_instance_partial_products_3_22_port, B =>
BOOTH_instance_partial_products_4_22_port, CI =>
BOOTH_instance_add_2_root_add_53_G7_carry_22_port,
CO =>
BOOTH_instance_add_2_root_add_53_G7_carry_23_port, S
=> BOOTH_instance_partial_products_7_22_port);
BOOTH_instance_add_0_root_add_53_G7_U1_21 : ADDFXL port map( A =>
BOOTH_instance_partial_products_7_21_port, B =>
BOOTH_instance_partial_products_8_21_port, CI =>
BOOTH_instance_add_0_root_add_53_G7_carry_21_port,
CO =>
BOOTH_instance_add_0_root_add_53_G7_carry_22_port, S
=> EX_MULT_OUT_21_port);
BOOTH_instance_add_0_root_add_53_G7_U1_19 : ADDFXL port map( A =>
BOOTH_instance_partial_products_7_19_port, B =>
BOOTH_instance_partial_products_8_19_port, CI =>
BOOTH_instance_add_0_root_add_53_G7_carry_19_port,
CO =>
BOOTH_instance_add_0_root_add_53_G7_carry_20_port, S
=> EX_MULT_OUT_19_port);
BOOTH_instance_add_0_root_add_53_G7_U1_17 : ADDFXL port map( A =>
BOOTH_instance_partial_products_7_17_port, B =>
BOOTH_instance_partial_products_8_17_port, CI =>
BOOTH_instance_add_0_root_add_53_G7_carry_17_port,
CO =>
BOOTH_instance_add_0_root_add_53_G7_carry_18_port, S
=> EX_MULT_OUT_17_port);
BOOTH_instance_add_1_root_add_53_G7_U1_16 : ADDFHXL port map( A =>
BOOTH_instance_partial_products_5_16_port, B =>
BOOTH_instance_partial_products_6_16_port, CI =>
BOOTH_instance_add_1_root_add_53_G7_carry_16_port,
CO =>
BOOTH_instance_add_1_root_add_53_G7_carry_17_port, S
=> BOOTH_instance_partial_products_8_16_port);
BOOTH_instance_add_2_root_add_53_G7_U1_15 : ADDFXL port map( A =>
BOOTH_instance_partial_products_3_15_port, B =>
BOOTH_instance_partial_products_4_15_port, CI =>
BOOTH_instance_add_2_root_add_53_G7_carry_15_port,
CO =>
BOOTH_instance_add_2_root_add_53_G7_carry_16_port, S
=> BOOTH_instance_partial_products_7_15_port);
BOOTH_instance_add_0_root_add_53_G7_U1_14 : ADDFXL port map( A =>
BOOTH_instance_partial_products_7_14_port, B =>
BOOTH_instance_partial_products_8_14_port, CI =>
BOOTH_instance_add_0_root_add_53_G7_carry_14_port,
CO =>
BOOTH_instance_add_0_root_add_53_G7_carry_15_port, S
=> EX_MULT_OUT_14_port);
BOOTH_instance_add_0_root_add_53_G7_U1_11 : ADDFXL port map( A =>
BOOTH_instance_partial_products_7_11_port, B =>
BOOTH_instance_partial_products_8_11_port, CI =>
BOOTH_instance_add_0_root_add_53_G7_carry_11_port,
CO =>
BOOTH_instance_add_0_root_add_53_G7_carry_12_port, S
=> EX_MULT_OUT_11_port);
BOOTH_instance_add_2_root_add_53_G7_U1_11 : ADDFXL port map( A =>
BOOTH_instance_partial_products_3_11_port, B =>
BOOTH_instance_partial_products_4_11_port, CI =>
BOOTH_instance_add_2_root_add_53_G7_carry_11_port,
CO =>
BOOTH_instance_add_2_root_add_53_G7_carry_12_port, S
=> BOOTH_instance_partial_products_7_11_port);
BOOTH_instance_add_0_root_add_53_G7_U1_7 : ADDFXL port map( A =>
BOOTH_instance_partial_products_7_7_port, B =>
BOOTH_instance_partial_products_8_7_port, CI =>
BOOTH_instance_add_0_root_add_53_G7_carry_7_port, CO
=> BOOTH_instance_add_0_root_add_53_G7_carry_8_port,
S => EX_MULT_OUT_7_port);
BOOTH_instance_add_6_root_add_53_G7_U1_31 : XOR3XL port map( A =>
BOOTH_instance_decoded_2_31_port, B =>
BOOTH_instance_decoded_3_31_port, C =>
BOOTH_instance_add_6_root_add_53_G7_carry_31_port, Y
=> BOOTH_instance_partial_products_3_31_port);
BOOTH_instance_add_2_root_add_53_G7_U1_30 : ADDFXL port map( A =>
BOOTH_instance_partial_products_3_30_port, B =>
BOOTH_instance_partial_products_4_30_port, CI =>
BOOTH_instance_add_2_root_add_53_G7_carry_30_port,
CO =>
BOOTH_instance_add_2_root_add_53_G7_carry_31_port, S
=> BOOTH_instance_partial_products_7_30_port);
BOOTH_instance_add_7_root_add_53_G7_U1_30 : ADDFHXL port map( A =>
BOOTH_instance_decoded_0_31_port, B =>
BOOTH_instance_decoded_1_31_port, CI =>
BOOTH_instance_add_7_root_add_53_G7_carry_30_port,
CO =>
BOOTH_instance_add_7_root_add_53_G7_carry_31_port, S
=> BOOTH_instance_partial_products_2_30_port);
BOOTH_instance_add_7_root_add_53_G7_U1_29 : ADDFHXL port map( A =>
BOOTH_instance_decoded_0_31_port, B =>
BOOTH_instance_decoded_1_31_port, CI =>
BOOTH_instance_add_7_root_add_53_G7_carry_29_port,
CO =>
BOOTH_instance_add_7_root_add_53_G7_carry_30_port, S
=> BOOTH_instance_partial_products_2_29_port);
BOOTH_instance_add_0_root_add_53_G7_U1_25 : ADDFXL port map( A =>
BOOTH_instance_partial_products_7_25_port, B =>
BOOTH_instance_partial_products_8_25_port, CI =>
BOOTH_instance_add_0_root_add_53_G7_carry_25_port,
CO =>
BOOTH_instance_add_0_root_add_53_G7_carry_26_port, S
=> EX_MULT_OUT_25_port);
BOOTH_instance_add_7_root_add_53_G7_U1_28 : ADDFHXL port map( A =>
BOOTH_instance_decoded_0_31_port, B =>
BOOTH_instance_decoded_1_31_port, CI =>
BOOTH_instance_add_7_root_add_53_G7_carry_28_port,
CO =>
BOOTH_instance_add_7_root_add_53_G7_carry_29_port, S
=> BOOTH_instance_partial_products_2_28_port);
BOOTH_instance_add_7_root_add_53_G7_U1_27 : ADDFHXL port map( A =>
BOOTH_instance_decoded_0_31_port, B =>
BOOTH_instance_decoded_1_31_port, CI =>
BOOTH_instance_add_7_root_add_53_G7_carry_27_port,
CO =>
BOOTH_instance_add_7_root_add_53_G7_carry_28_port, S
=> BOOTH_instance_partial_products_2_27_port);
BOOTH_instance_add_0_root_add_53_G7_U1_23 : ADDFXL port map( A =>
BOOTH_instance_partial_products_7_23_port, B =>
BOOTH_instance_partial_products_8_23_port, CI =>
BOOTH_instance_add_0_root_add_53_G7_carry_23_port,
CO =>
BOOTH_instance_add_0_root_add_53_G7_carry_24_port, S
=> EX_MULT_OUT_23_port);
BOOTH_instance_add_7_root_add_53_G7_U1_26 : ADDFHXL port map( A =>
BOOTH_instance_decoded_0_31_port, B =>
BOOTH_instance_decoded_1_31_port, CI =>
BOOTH_instance_add_7_root_add_53_G7_carry_26_port,
CO =>
BOOTH_instance_add_7_root_add_53_G7_carry_27_port, S
=> BOOTH_instance_partial_products_2_26_port);
BOOTH_instance_add_7_root_add_53_G7_U1_25 : ADDFHXL port map( A =>
BOOTH_instance_decoded_0_31_port, B =>
BOOTH_instance_decoded_1_31_port, CI =>
BOOTH_instance_add_7_root_add_53_G7_carry_25_port,
CO =>
BOOTH_instance_add_7_root_add_53_G7_carry_26_port, S
=> BOOTH_instance_partial_products_2_25_port);
BOOTH_instance_add_7_root_add_53_G7_U1_24 : ADDFHXL port map( A =>
BOOTH_instance_decoded_0_31_port, B =>
BOOTH_instance_decoded_1_31_port, CI =>
BOOTH_instance_add_7_root_add_53_G7_carry_24_port,
CO =>
BOOTH_instance_add_7_root_add_53_G7_carry_25_port, S
=> BOOTH_instance_partial_products_2_24_port);
BOOTH_instance_add_7_root_add_53_G7_U1_23 : ADDFHXL port map( A =>
BOOTH_instance_decoded_0_31_port, B =>
BOOTH_instance_decoded_1_31_port, CI =>
BOOTH_instance_add_7_root_add_53_G7_carry_23_port,
CO =>
BOOTH_instance_add_7_root_add_53_G7_carry_24_port, S
=> BOOTH_instance_partial_products_2_23_port);
BOOTH_instance_add_7_root_add_53_G7_U1_22 : ADDFHXL port map( A =>
BOOTH_instance_decoded_0_31_port, B =>
BOOTH_instance_decoded_1_31_port, CI =>
BOOTH_instance_add_7_root_add_53_G7_carry_22_port,
CO =>
BOOTH_instance_add_7_root_add_53_G7_carry_23_port, S
=> BOOTH_instance_partial_products_2_22_port);
BOOTH_instance_add_7_root_add_53_G7_U1_20 : ADDFHXL port map( A =>
BOOTH_instance_decoded_0_31_port, B =>
BOOTH_instance_decoded_1_31_port, CI =>
BOOTH_instance_add_7_root_add_53_G7_carry_20_port,
CO =>
BOOTH_instance_add_7_root_add_53_G7_carry_21_port, S
=> BOOTH_instance_partial_products_2_20_port);
BOOTH_instance_add_7_root_add_53_G7_U1_31 : XOR3XL port map( A =>
BOOTH_instance_decoded_0_31_port, B =>
BOOTH_instance_decoded_1_31_port, C =>
BOOTH_instance_add_7_root_add_53_G7_carry_31_port, Y
=> BOOTH_instance_partial_products_2_31_port);
BOOTH_instance_add_3_root_add_53_G7_U1_17 : ADDFHX1 port map( A =>
BOOTH_instance_decoded_8_17_port, B =>
BOOTH_instance_partial_products_2_17_port, CI =>
BOOTH_instance_add_3_root_add_53_G7_carry_17_port,
CO =>
BOOTH_instance_add_3_root_add_53_G7_carry_18_port, S
=> BOOTH_instance_partial_products_6_17_port);
EX_MEM_OUT_REG_instance_Q_reg_29_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => N4889, E => n686,
CK => CLOCK, Q => PORT_ALU_29_port, QN => n1639);
EX_MEM_OUT_REG_instance_Q_reg_30_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => N4890, E => n686,
CK => CLOCK, Q => PORT_ALU_30_port, QN => n1638);
EX_MEM_OUT_REG_instance_Q_reg_31_inst : EDFFTRXL port map( RN =>
EX_MEM_OUT_REG_instance_n34, D => N4891, E => n686,
CK => CLOCK, Q => PORT_ALU_31_port, QN => n1637);
BOOTH_instance_add_6_root_add_53_G7_U1_12 : ADDFXL port map( A =>
BOOTH_instance_decoded_2_12_port, B =>
BOOTH_instance_decoded_3_12_port, CI =>
BOOTH_instance_add_6_root_add_53_G7_carry_12_port,
CO =>
BOOTH_instance_add_6_root_add_53_G7_carry_13_port, S
=> BOOTH_instance_partial_products_3_12_port);
BOOTH_instance_add_6_root_add_53_G7_U1_8 : ADDFXL port map( A =>
BOOTH_instance_decoded_2_8_port, B =>
BOOTH_instance_decoded_3_8_port, CI =>
BOOTH_instance_add_6_root_add_53_G7_carry_8_port, CO
=> BOOTH_instance_add_6_root_add_53_G7_carry_9_port,
S => BOOTH_instance_partial_products_3_8_port);
BOOTH_instance_add_0_root_add_53_G7_U1_12 : ADDFXL port map( A =>
BOOTH_instance_partial_products_7_12_port, B =>
BOOTH_instance_partial_products_8_12_port, CI =>
BOOTH_instance_add_0_root_add_53_G7_carry_12_port,
CO =>
BOOTH_instance_add_0_root_add_53_G7_carry_13_port, S
=> EX_MULT_OUT_12_port);
BOOTH_instance_add_2_root_add_53_G7_U1_12 : ADDFXL port map( A =>
BOOTH_instance_partial_products_3_12_port, B =>
BOOTH_instance_partial_products_4_12_port, CI =>
BOOTH_instance_add_2_root_add_53_G7_carry_12_port,
CO =>
BOOTH_instance_add_2_root_add_53_G7_carry_13_port, S
=> BOOTH_instance_partial_products_7_12_port);
BOOTH_instance_add_0_root_add_53_G7_U1_9 : ADDFXL port map( A =>
BOOTH_instance_partial_products_7_9_port, B =>
BOOTH_instance_partial_products_8_9_port, CI =>
BOOTH_instance_add_0_root_add_53_G7_carry_9_port, CO
=> BOOTH_instance_add_0_root_add_53_G7_carry_10_port
, S => EX_MULT_OUT_9_port);
BOOTH_instance_add_2_root_add_53_G7_U1_16 : ADDFXL port map( A =>
BOOTH_instance_partial_products_3_16_port, B =>
BOOTH_instance_partial_products_4_16_port, CI =>
BOOTH_instance_add_2_root_add_53_G7_carry_16_port,
CO =>
BOOTH_instance_add_2_root_add_53_G7_carry_17_port, S
=> BOOTH_instance_partial_products_7_16_port);
BOOTH_instance_add_1_root_add_53_G7_U1_14 : ADDFHXL port map( A =>
BOOTH_instance_partial_products_5_14_port, B =>
BOOTH_instance_partial_products_6_14_port, CI =>
BOOTH_instance_add_1_root_add_53_G7_carry_14_port,
CO =>
BOOTH_instance_add_1_root_add_53_G7_carry_15_port, S
=> BOOTH_instance_partial_products_8_14_port);
BOOTH_instance_add_6_root_add_53_G7_U1_20 : ADDFXL port map( A =>
BOOTH_instance_decoded_2_20_port, B =>
BOOTH_instance_decoded_3_20_port, CI =>
BOOTH_instance_add_6_root_add_53_G7_carry_20_port,
CO =>
BOOTH_instance_add_6_root_add_53_G7_carry_21_port, S
=> BOOTH_instance_partial_products_3_20_port);
BOOTH_instance_add_0_root_add_53_G7_U1_15 : ADDFXL port map( A =>
BOOTH_instance_partial_products_7_15_port, B =>
BOOTH_instance_partial_products_8_15_port, CI =>
BOOTH_instance_add_0_root_add_53_G7_carry_15_port,
CO =>
BOOTH_instance_add_0_root_add_53_G7_carry_16_port, S
=> EX_MULT_OUT_15_port);
BOOTH_instance_add_2_root_add_53_G7_U1_21 : ADDFXL port map( A =>
BOOTH_instance_partial_products_3_21_port, B =>
BOOTH_instance_partial_products_4_21_port, CI =>
BOOTH_instance_add_2_root_add_53_G7_carry_21_port,
CO =>
BOOTH_instance_add_2_root_add_53_G7_carry_22_port, S
=> BOOTH_instance_partial_products_7_21_port);
BOOTH_instance_add_0_root_add_53_G7_U1_16 : ADDFXL port map( A =>
BOOTH_instance_partial_products_7_16_port, B =>
BOOTH_instance_partial_products_8_16_port, CI =>
BOOTH_instance_add_0_root_add_53_G7_carry_16_port,
CO =>
BOOTH_instance_add_0_root_add_53_G7_carry_17_port, S
=> EX_MULT_OUT_16_port);
BOOTH_instance_add_0_root_add_53_G7_U1_18 : ADDFXL port map( A =>
BOOTH_instance_partial_products_7_18_port, B =>
BOOTH_instance_partial_products_8_18_port, CI =>
BOOTH_instance_add_0_root_add_53_G7_carry_18_port,
CO =>
BOOTH_instance_add_0_root_add_53_G7_carry_19_port, S
=> EX_MULT_OUT_18_port);
BOOTH_instance_add_0_root_add_53_G7_U1_27 : ADDFHX1 port map( A =>
BOOTH_instance_partial_products_7_27_port, B =>
BOOTH_instance_partial_products_8_27_port, CI =>
BOOTH_instance_add_0_root_add_53_G7_carry_27_port,
CO =>
BOOTH_instance_add_0_root_add_53_G7_carry_28_port, S
=> EX_MULT_OUT_27_port);
BOOTH_instance_add_2_root_add_53_G7_U1_29 : ADDFXL port map( A =>
BOOTH_instance_partial_products_3_29_port, B =>
BOOTH_instance_partial_products_4_29_port, CI =>
BOOTH_instance_add_2_root_add_53_G7_carry_29_port,
CO =>
BOOTH_instance_add_2_root_add_53_G7_carry_30_port, S
=> BOOTH_instance_partial_products_7_29_port);
BOOTH_instance_add_0_root_add_53_G7_U1_28 : ADDFXL port map( A =>
BOOTH_instance_partial_products_7_28_port, B =>
BOOTH_instance_partial_products_8_28_port, CI =>
BOOTH_instance_add_0_root_add_53_G7_carry_28_port,
CO =>
BOOTH_instance_add_0_root_add_53_G7_carry_29_port, S
=> EX_MULT_OUT_28_port);
BOOTH_instance_add_2_root_add_53_G7_U1_27 : ADDFXL port map( A =>
BOOTH_instance_partial_products_3_27_port, B =>
BOOTH_instance_partial_products_4_27_port, CI =>
BOOTH_instance_add_2_root_add_53_G7_carry_27_port,
CO =>
BOOTH_instance_add_2_root_add_53_G7_carry_28_port, S
=> BOOTH_instance_partial_products_7_27_port);
BOOTH_instance_add_2_root_add_53_G7_U1_28 : ADDFXL port map( A =>
BOOTH_instance_partial_products_3_28_port, B =>
BOOTH_instance_partial_products_4_28_port, CI =>
BOOTH_instance_add_2_root_add_53_G7_carry_28_port,
CO =>
BOOTH_instance_add_2_root_add_53_G7_carry_29_port, S
=> BOOTH_instance_partial_products_7_28_port);
BOOTH_instance_add_0_root_add_53_G7_U1_29 : ADDFXL port map( A =>
BOOTH_instance_partial_products_7_29_port, B =>
BOOTH_instance_partial_products_8_29_port, CI =>
BOOTH_instance_add_0_root_add_53_G7_carry_29_port,
CO =>
BOOTH_instance_add_0_root_add_53_G7_carry_30_port, S
=> EX_MULT_OUT_29_port);
BOOTH_instance_add_2_root_add_53_G7_U1_9 : ADDFXL port map( A =>
BOOTH_instance_partial_products_3_9_port, B =>
BOOTH_instance_partial_products_4_9_port, CI =>
BOOTH_instance_add_2_root_add_53_G7_carry_9_port, CO
=> BOOTH_instance_add_2_root_add_53_G7_carry_10_port
, S => BOOTH_instance_partial_products_7_9_port);
BOOTH_instance_add_0_root_add_53_G7_U1_13 : ADDFXL port map( A =>
BOOTH_instance_partial_products_7_13_port, B =>
BOOTH_instance_partial_products_8_13_port, CI =>
BOOTH_instance_add_0_root_add_53_G7_carry_13_port,
CO =>
BOOTH_instance_add_0_root_add_53_G7_carry_14_port, S
=> EX_MULT_OUT_13_port);
BOOTH_instance_add_6_root_add_53_G7_U1_16 : ADDFXL port map( A =>
BOOTH_instance_decoded_2_16_port, B =>
BOOTH_instance_decoded_3_16_port, CI =>
BOOTH_instance_add_6_root_add_53_G7_carry_16_port,
CO =>
BOOTH_instance_add_6_root_add_53_G7_carry_17_port, S
=> BOOTH_instance_partial_products_3_16_port);
BOOTH_instance_add_6_root_add_53_G7_U1_14 : ADDFXL port map( A =>
BOOTH_instance_decoded_2_14_port, B =>
BOOTH_instance_decoded_3_14_port, CI =>
BOOTH_instance_add_6_root_add_53_G7_carry_14_port,
CO =>
BOOTH_instance_add_6_root_add_53_G7_carry_15_port, S
=> BOOTH_instance_partial_products_3_14_port);
BOOTH_instance_add_6_root_add_53_G7_U1_17 : ADDFXL port map( A =>
BOOTH_instance_decoded_2_17_port, B =>
BOOTH_instance_decoded_3_17_port, CI =>
BOOTH_instance_add_6_root_add_53_G7_carry_17_port,
CO =>
BOOTH_instance_add_6_root_add_53_G7_carry_18_port, S
=> BOOTH_instance_partial_products_3_17_port);
BOOTH_instance_add_6_root_add_53_G7_U1_10 : ADDFXL port map( A =>
BOOTH_instance_decoded_2_10_port, B =>
BOOTH_instance_decoded_3_10_port, CI =>
BOOTH_instance_add_6_root_add_53_G7_carry_10_port,
CO =>
BOOTH_instance_add_6_root_add_53_G7_carry_11_port, S
=> BOOTH_instance_partial_products_3_10_port);
BOOTH_instance_add_2_root_add_53_G7_U1_13 : ADDFXL port map( A =>
BOOTH_instance_partial_products_3_13_port, B =>
BOOTH_instance_partial_products_4_13_port, CI =>
BOOTH_instance_add_2_root_add_53_G7_carry_13_port,
CO =>
BOOTH_instance_add_2_root_add_53_G7_carry_14_port, S
=> BOOTH_instance_partial_products_7_13_port);
BOOTH_instance_add_6_root_add_53_G7_U1_19 : ADDFXL port map( A =>
BOOTH_instance_decoded_2_19_port, B =>
BOOTH_instance_decoded_3_19_port, CI =>
BOOTH_instance_add_6_root_add_53_G7_carry_19_port,
CO =>
BOOTH_instance_add_6_root_add_53_G7_carry_20_port, S
=> BOOTH_instance_partial_products_3_19_port);
BOOTH_instance_add_2_root_add_53_G7_U1_19 : ADDFXL port map( A =>
BOOTH_instance_partial_products_3_19_port, B =>
BOOTH_instance_partial_products_4_19_port, CI =>
BOOTH_instance_add_2_root_add_53_G7_carry_19_port,
CO =>
BOOTH_instance_add_2_root_add_53_G7_carry_20_port, S
=> BOOTH_instance_partial_products_7_19_port);
clk_gate_IF_ID_INSTR_REG_instance_Q_reg : SNPS_CLOCK_GATE_HIGH_DLX_0 port
map( CLK => CLOCK, EN => n1626, ENCLK => n1628, TE
=> n1627);
IF_STALL_REG_instance_Q_reg : DFFRQXL port map( D =>
ID_EX_IMM16_EXT_REG_instance_n34, CK => CLOCK, RN =>
n1625, Q => IF_STALL_SEL);
EX_MEM_INSTR_REG_instance_Q_reg_31_inst : EDFFTRXL port map( RN =>
ID_EX_REGA_REG_instance_n34, D => EX_INSTR_31_port,
E => n1621, CK => CLOCK, Q => MEM_INSTR_31_port, QN
=> n1409);
PC_instance_Q_reg_5_inst : EDFFTRXL port map( RN => PC_instance_n33, D =>
N735, E => n697, CK => n1628, Q => PORT_PC_5_port,
QN => n1620);
ID_EX_INSTR_REG_instance_Q_reg_26_inst : EDFFTRXL port map( RN =>
ID_EX_INSTR_REG_instance_n34, D =>
ID_INSTR_AFTER_CU_26_port, E => n686, CK => CLOCK, Q
=> EX_INSTR_26_port, QN => n1613);
ID_EX_INSTR_REG_instance_Q_reg_30_inst : EDFFTRXL port map( RN =>
ID_EX_INSTR_REG_instance_n34, D =>
ID_INSTR_AFTER_CU_30_port, E => n686, CK => CLOCK, Q
=> EX_INSTR_30_port, QN => n1611);
ID_EX_INSTR_REG_instance_Q_reg_29_inst : EDFFTRXL port map( RN =>
ID_EX_INSTR_REG_instance_n34, D =>
ID_INSTR_AFTER_CU_29_port, E => n686, CK => CLOCK, Q
=> EX_INSTR_29_port, QN => n1605);
ID_EX_INSTR_REG_instance_Q_reg_28_inst : EDFFTRXL port map( RN =>
ID_EX_INSTR_REG_instance_n34, D =>
ID_INSTR_AFTER_CU_28_port, E => n686, CK => CLOCK, Q
=> EX_INSTR_28_port, QN => n1604);
ID_EX_INSTR_REG_instance_Q_reg_27_inst : EDFFTRXL port map( RN =>
ID_EX_INSTR_REG_instance_n34, D =>
ID_INSTR_AFTER_CU_27_port, E => n686, CK => CLOCK, Q
=> EX_INSTR_27_port, QN => n1603);
ID_EX_INSTR_REG_instance_Q_reg_31_inst : EDFFXL port map( D => n1624, E =>
n1622, CK => CLOCK, Q => EX_INSTR_31_port, QN =>
n1566);
BOOTH_instance_add_0_root_add_53_G7_U1_20 : ADDFXL port map( A =>
BOOTH_instance_partial_products_7_20_port, B =>
BOOTH_instance_partial_products_8_20_port, CI =>
BOOTH_instance_add_0_root_add_53_G7_carry_20_port,
CO =>
BOOTH_instance_add_0_root_add_53_G7_carry_21_port, S
=> EX_MULT_OUT_20_port);
BOOTH_instance_add_0_root_add_53_G7_U1_22 : ADDFXL port map( A =>
BOOTH_instance_partial_products_7_22_port, B =>
BOOTH_instance_partial_products_8_22_port, CI =>
BOOTH_instance_add_0_root_add_53_G7_carry_22_port,
CO =>
BOOTH_instance_add_0_root_add_53_G7_carry_23_port, S
=> EX_MULT_OUT_22_port);
BOOTH_instance_add_0_root_add_53_G7_U1_24 : ADDFXL port map( A =>
BOOTH_instance_partial_products_7_24_port, B =>
BOOTH_instance_partial_products_8_24_port, CI =>
BOOTH_instance_add_0_root_add_53_G7_carry_24_port,
CO =>
BOOTH_instance_add_0_root_add_53_G7_carry_25_port, S
=> EX_MULT_OUT_24_port);
BOOTH_instance_add_0_root_add_53_G7_U1_26 : ADDFXL port map( A =>
BOOTH_instance_partial_products_7_26_port, B =>
BOOTH_instance_partial_products_8_26_port, CI =>
BOOTH_instance_add_0_root_add_53_G7_carry_26_port,
CO =>
BOOTH_instance_add_0_root_add_53_G7_carry_27_port, S
=> EX_MULT_OUT_26_port);
BOOTH_instance_add_0_root_add_53_G7_U1_30 : ADDFHX1 port map( A =>
BOOTH_instance_partial_products_7_30_port, B =>
BOOTH_instance_partial_products_8_30_port, CI =>
BOOTH_instance_add_0_root_add_53_G7_carry_30_port,
CO =>
BOOTH_instance_add_0_root_add_53_G7_carry_31_port, S
=> EX_MULT_OUT_30_port);
BOOTH_instance_add_1_root_add_53_G7_U1_17 : ADDFHXL port map( A =>
BOOTH_instance_partial_products_5_17_port, B =>
BOOTH_instance_partial_products_6_17_port, CI =>
BOOTH_instance_add_1_root_add_53_G7_carry_17_port,
CO =>
BOOTH_instance_add_1_root_add_53_G7_carry_18_port, S
=> BOOTH_instance_partial_products_8_17_port);
BOOTH_instance_add_1_root_add_53_G7_U1_19 : ADDFHXL port map( A =>
BOOTH_instance_partial_products_5_19_port, B =>
BOOTH_instance_partial_products_6_19_port, CI =>
BOOTH_instance_add_1_root_add_53_G7_carry_19_port,
CO =>
BOOTH_instance_add_1_root_add_53_G7_carry_20_port, S
=> BOOTH_instance_partial_products_8_19_port);
BOOTH_instance_add_6_root_add_53_G7_U1_30 : ADDFXL port map( A =>
BOOTH_instance_decoded_2_31_port, B =>
BOOTH_instance_decoded_3_31_port, CI =>
BOOTH_instance_add_6_root_add_53_G7_carry_30_port,
CO =>
BOOTH_instance_add_6_root_add_53_G7_carry_31_port, S
=> BOOTH_instance_partial_products_3_30_port);
BOOTH_instance_add_7_root_add_53_G7_U1_13 : ADDFHX1 port map( A =>
BOOTH_instance_N222_port, B =>
BOOTH_instance_decoded_1_13_port, CI =>
BOOTH_instance_add_7_root_add_53_G7_carry_13_port,
CO =>
BOOTH_instance_add_7_root_add_53_G7_carry_14_port, S
=> BOOTH_instance_partial_products_6_13_port);
BOOTH_instance_add_7_root_add_53_G7_U1_15 : ADDFHXL port map( A =>
BOOTH_instance_N224_port, B =>
BOOTH_instance_decoded_1_15_port, CI =>
BOOTH_instance_add_7_root_add_53_G7_carry_15_port,
CO =>
BOOTH_instance_add_7_root_add_53_G7_carry_16_port, S
=> BOOTH_instance_partial_products_6_15_port);
BOOTH_instance_add_3_root_add_53_G7_U1_20 : ADDFHXL port map( A =>
BOOTH_instance_decoded_8_20_port, B =>
BOOTH_instance_partial_products_2_20_port, CI =>
BOOTH_instance_add_3_root_add_53_G7_carry_20_port,
CO =>
BOOTH_instance_add_3_root_add_53_G7_carry_21_port, S
=> BOOTH_instance_partial_products_6_20_port);
BOOTH_instance_add_6_root_add_53_G7_U1_21 : ADDFXL port map( A =>
BOOTH_instance_decoded_2_31_port, B =>
BOOTH_instance_decoded_3_21_port, CI =>
BOOTH_instance_add_6_root_add_53_G7_carry_21_port,
CO =>
BOOTH_instance_add_6_root_add_53_G7_carry_22_port, S
=> BOOTH_instance_partial_products_3_21_port);
BOOTH_instance_add_6_root_add_53_G7_U1_23 : ADDFXL port map( A =>
BOOTH_instance_decoded_2_31_port, B =>
BOOTH_instance_decoded_3_31_port, CI =>
BOOTH_instance_add_6_root_add_53_G7_carry_23_port,
CO =>
BOOTH_instance_add_6_root_add_53_G7_carry_24_port, S
=> BOOTH_instance_partial_products_3_23_port);
BOOTH_instance_add_6_root_add_53_G7_U1_24 : ADDFXL port map( A =>
BOOTH_instance_decoded_2_31_port, B =>
BOOTH_instance_decoded_3_31_port, CI =>
BOOTH_instance_add_6_root_add_53_G7_carry_24_port,
CO =>
BOOTH_instance_add_6_root_add_53_G7_carry_25_port, S
=> BOOTH_instance_partial_products_3_24_port);
BOOTH_instance_add_6_root_add_53_G7_U1_25 : ADDFXL port map( A =>
BOOTH_instance_decoded_2_31_port, B =>
BOOTH_instance_decoded_3_31_port, CI =>
BOOTH_instance_add_6_root_add_53_G7_carry_25_port,
CO =>
BOOTH_instance_add_6_root_add_53_G7_carry_26_port, S
=> BOOTH_instance_partial_products_3_25_port);
BOOTH_instance_add_6_root_add_53_G7_U1_26 : ADDFXL port map( A =>
BOOTH_instance_decoded_2_31_port, B =>
BOOTH_instance_decoded_3_31_port, CI =>
BOOTH_instance_add_6_root_add_53_G7_carry_26_port,
CO =>
BOOTH_instance_add_6_root_add_53_G7_carry_27_port, S
=> BOOTH_instance_partial_products_3_26_port);
BOOTH_instance_add_6_root_add_53_G7_U1_27 : ADDFXL port map( A =>
BOOTH_instance_decoded_2_31_port, B =>
BOOTH_instance_decoded_3_31_port, CI =>
BOOTH_instance_add_6_root_add_53_G7_carry_27_port,
CO =>
BOOTH_instance_add_6_root_add_53_G7_carry_28_port, S
=> BOOTH_instance_partial_products_3_27_port);
BOOTH_instance_add_6_root_add_53_G7_U1_28 : ADDFXL port map( A =>
BOOTH_instance_decoded_2_31_port, B =>
BOOTH_instance_decoded_3_31_port, CI =>
BOOTH_instance_add_6_root_add_53_G7_carry_28_port,
CO =>
BOOTH_instance_add_6_root_add_53_G7_carry_29_port, S
=> BOOTH_instance_partial_products_3_28_port);
BOOTH_instance_add_6_root_add_53_G7_U1_29 : ADDFXL port map( A =>
BOOTH_instance_decoded_2_31_port, B =>
BOOTH_instance_decoded_3_31_port, CI =>
BOOTH_instance_add_6_root_add_53_G7_carry_29_port,
CO =>
BOOTH_instance_add_6_root_add_53_G7_carry_30_port, S
=> BOOTH_instance_partial_products_3_29_port);
BOOTH_instance_add_7_root_add_53_G7_U1_18 : ADDFHXL port map( A =>
BOOTH_instance_decoded_0_31_port, B =>
BOOTH_instance_decoded_1_18_port, CI =>
BOOTH_instance_add_7_root_add_53_G7_carry_18_port,
CO =>
BOOTH_instance_add_7_root_add_53_G7_carry_19_port, S
=> BOOTH_instance_partial_products_2_18_port);
BOOTH_instance_add_7_root_add_53_G7_U1_21 : ADDFHXL port map( A =>
BOOTH_instance_decoded_0_31_port, B =>
BOOTH_instance_decoded_1_31_port, CI =>
BOOTH_instance_add_7_root_add_53_G7_carry_21_port,
CO =>
BOOTH_instance_add_7_root_add_53_G7_carry_22_port, S
=> BOOTH_instance_partial_products_2_21_port);
BOOTH_instance_add_7_root_add_53_G7_U1_19 : ADDFHXL port map( A =>
BOOTH_instance_decoded_0_31_port, B =>
BOOTH_instance_decoded_1_31_port, CI =>
BOOTH_instance_add_7_root_add_53_G7_carry_19_port,
CO =>
BOOTH_instance_add_7_root_add_53_G7_carry_20_port, S
=> BOOTH_instance_partial_products_2_19_port);
BOOTH_instance_add_7_root_add_53_G7_U1_5 : ADDFHXL port map( A =>
BOOTH_instance_N214_port, B =>
BOOTH_instance_decoded_1_5_port, CI =>
BOOTH_instance_add_7_root_add_53_G7_carry_5_port, CO
=> BOOTH_instance_add_7_root_add_53_G7_carry_6_port,
S => BOOTH_instance_partial_products_8_5_port);
BOOTH_instance_add_7_root_add_53_G7_U1_10 : ADDFHX1 port map( A =>
BOOTH_instance_N219_port, B =>
BOOTH_instance_decoded_1_10_port, CI =>
BOOTH_instance_add_7_root_add_53_G7_carry_10_port,
CO =>
BOOTH_instance_add_7_root_add_53_G7_carry_11_port, S
=> BOOTH_instance_partial_products_8_10_port);
BOOTH_instance_add_7_root_add_53_G7_U1_12 : ADDFHX1 port map( A =>
BOOTH_instance_N221_port, B =>
BOOTH_instance_decoded_1_12_port, CI =>
BOOTH_instance_add_7_root_add_53_G7_carry_12_port,
CO =>
BOOTH_instance_add_7_root_add_53_G7_carry_13_port, S
=> BOOTH_instance_partial_products_6_12_port);
BOOTH_instance_add_7_root_add_53_G7_U1_16 : ADDFHX1 port map( A =>
BOOTH_instance_N225_port, B =>
BOOTH_instance_decoded_1_16_port, CI =>
BOOTH_instance_add_7_root_add_53_G7_carry_16_port,
CO =>
BOOTH_instance_add_7_root_add_53_G7_carry_17_port, S
=> BOOTH_instance_partial_products_2_16_port);
BOOTH_instance_add_3_root_add_53_G7_U1_18 : ADDFHXL port map( A =>
BOOTH_instance_decoded_8_18_port, B =>
BOOTH_instance_partial_products_2_18_port, CI =>
BOOTH_instance_add_3_root_add_53_G7_carry_18_port,
CO =>
BOOTH_instance_add_3_root_add_53_G7_carry_19_port, S
=> BOOTH_instance_partial_products_6_18_port);
U1339 : INVX1 port map( A => n1699, Y => BOOTH_instance_n425);
U1340 : CLKINVX1 port map( A => N4721, Y => n2192);
U1341 : CLKINVX1 port map( A => n2112, Y => BOOTH_instance_n316);
U1342 : INVX3 port map( A => n2166, Y => n2163);
U1343 : CLKINVX2 port map( A => n688, Y => n2166);
U1344 : OAI222XL port map( A0 => BOOTH_instance_n308, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n20, B0 =>
BOOTH_instance_n290, B1 => BOOTH_instance_n445, C0
=> n1647, C1 => BOOTH_instance_n447, Y =>
BOOTH_instance_N211_port);
U1345 : OAI222X1 port map( A0 => BOOTH_instance_n299, A1 => n2128, B0 =>
BOOTH_instance_n269, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n22, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n46, C1 =>
BOOTH_instance_n447, Y => BOOTH_instance_N214_port);
U1346 : CLKNAND2X4 port map( A => n2163, B => n1593, Y =>
BOOTH_instance_n447);
U1347 : INVXL port map( A => n1610, Y => n1591);
U1348 : INVXL port map( A => n1591, Y => n1592);
U1349 : INVX2 port map( A => n1591, Y => n1593);
U1350 : NAND3X1 port map( A => n2159, B => n2176, C => n690, Y =>
BOOTH_instance_n434);
U1351 : INVX1 port map( A => BOOTH_instance_n434, Y => BOOTH_instance_n424);
U1352 : XOR2X1 port map( A => N4723, B => BOOTH_instance_n457, Y =>
BOOTH_instance_n269);
U1353 : AND4X1 port map( A => n1570, B => n1377, C => n1571, D => n1572, Y
=> n1594);
U1354 : NOR2XL port map( A => n2162, B => n2174, Y => n1595);
U1355 : NAND2XL port map( A => n2163, B => n2158, Y => BOOTH_instance_n445);
U1356 : INVX1 port map( A => n1647, Y => n2193);
U1357 : AND2X1 port map( A => n1635, B => n1636, Y => n1647);
U1358 : AO22X1 port map( A0 => EX_PC_3_port, A1 => n2142, B0 =>
EX_REGA_3_port, B1 => n2140, Y => N4721);
U1359 : XOR2X1 port map( A => BOOTH_instance_n459, B => n2191, Y =>
BOOTH_instance_n299);
U1360 : CLKINVX2 port map( A => n1593, Y => n1601);
U1361 : INVXL port map( A => BOOTH_instance_n269, Y => n1596);
U1362 : AND2XL port map( A => BOOTH_instance_decoded_2_6_port, B =>
BOOTH_instance_decoded_3_6_port, Y =>
BOOTH_instance_add_6_root_add_53_G7_carry_7_port);
U1363 : NAND2XL port map( A => n2192, B => BOOTH_instance_n460, Y => n1634);
U1364 : XNOR2XL port map( A => N4831, B => n2176, Y => BOOTH_instance_n419);
U1365 : NAND2XL port map( A => n2174, B => BOOTH_instance_n443, Y =>
BOOTH_instance_n422);
U1366 : NAND2XL port map( A => n1630, B => n1631, Y => BOOTH_instance_n405);
U1367 : OAI221XL port map( A0 => BOOTH_instance_n307, A1 =>
BOOTH_instance_n421, B0 => BOOTH_instance_n308, B1
=> BOOTH_instance_n422, C0 => BOOTH_instance_n432, Y
=> BOOTH_instance_decoded_1_3_port);
U1368 : AO22XL port map( A0 => EX_PC_1_port, A1 => n2142, B0 =>
EX_REGA_1_port, B1 => n2140, Y => n2115);
U1369 : NOR2XL port map( A => n1602, B => n2174, Y => n1597);
U1370 : NOR2XL port map( A => n2162, B => n2174, Y => n1598);
U1371 : NOR2XL port map( A => EX_ALU_SEL_0_port, B => EX_ALU_SEL_1_port, Y
=> n1599);
U1372 : AOI21BXL port map( A0 => EX_IMM16_EXT_3_port, A1 => n2153, B0N =>
n1352, Y => n1600);
U1373 : AO2B2XL port map( B0 => EX_REGB_2_port, B1 => n1189, A0 => n2153,
A1N => n1663, Y => n690);
U1374 : OR2XL port map( A => BOOTH_instance_n398, B => BOOTH_instance_n290,
Y => n1631);
U1375 : OAI222X2 port map( A0 => BOOTH_instance_n290, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n20, B0 =>
BOOTH_instance_n280, B1 => BOOTH_instance_n445, C0
=> n2192, C1 => BOOTH_instance_n447, Y =>
BOOTH_instance_N212_port);
U1376 : OAI222XL port map( A0 => BOOTH_instance_n280, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n20, B0 =>
BOOTH_instance_n299, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n46, C0 => n2191,
C1 => BOOTH_instance_n447, Y =>
BOOTH_instance_N213_port);
U1377 : OAI222XL port map( A0 => BOOTH_instance_n269, A1 => n2127, B0 =>
BOOTH_instance_n259, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n22, C0 =>
BOOTH_instance_n260, C1 => BOOTH_instance_n447, Y =>
BOOTH_instance_N215_port);
U1378 : CLKINVX1 port map( A => n2145, Y => n2144);
U1379 : CLKINVX1 port map( A => n1351, Y => n2145);
U1380 : INVXL port map( A => n1592, Y => n2159);
U1381 : INVXL port map( A => n2162, Y => n1602);
U1382 : CLKINVX1 port map( A => n2162, Y => n2160);
U1383 : NAND2BXL port map( AN => n2163, B => n2158, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n20);
U1384 : NOR2XL port map( A => n1611, B => n1629, Y => n1584);
U1385 : XOR2XL port map( A => BOOTH_instance_n458, B => BOOTH_instance_n260,
Y => BOOTH_instance_n259);
U1386 : AND4XL port map( A => n1545, B => n1541, C => n1543, D => n1538, Y
=> n1551);
U1387 : NOR2XL port map( A => n1566, B => n1613, Y => n1573);
U1388 : NOR2XL port map( A => n1612, B => EX_INSTR_27_port, Y => n1563);
U1389 : INVXL port map( A => N4728, Y => n2184);
U1390 : AO22XL port map( A0 => EX_PC_6_port, A1 => n2142, B0 =>
EX_REGA_6_port, B1 => n2140, Y => N4724);
U1391 : CLKBUFX1 port map( A => n1189, Y => n2152);
U1392 : AO22XL port map( A0 => EX_PC_5_port, A1 => n2142, B0 =>
EX_REGA_5_port, B1 => n2140, Y => N4723);
U1393 : NAND2XL port map( A => BOOTH_instance_n419, B => BOOTH_instance_n396
, Y => BOOTH_instance_n397);
U1394 : NAND2XL port map( A => N4832, B => BOOTH_instance_n419, Y =>
BOOTH_instance_n398);
U1395 : AO22XL port map( A0 => EX_PC_1_port, A1 => n2142, B0 =>
EX_REGA_1_port, B1 => n2140, Y => n2116);
U1396 : AO22XL port map( A0 => EX_PC_1_port, A1 => n2142, B0 =>
EX_REGA_1_port, B1 => n2140, Y => N4719);
U1397 : AO22XL port map( A0 => EX_IMM16_EXT_30_port, A1 => n2153, B0 =>
EX_REGB_30_port, B1 => n2151, Y => N4857);
U1398 : AO22XL port map( A0 => EX_IMM16_EXT_29_port, A1 => n2153, B0 =>
EX_REGB_29_port, B1 => n2151, Y => N4856);
U1399 : AO22XL port map( A0 => EX_IMM16_EXT_28_port, A1 => n2153, B0 =>
EX_REGB_28_port, B1 => n2151, Y => N4855);
U1400 : AO22XL port map( A0 => EX_IMM16_EXT_27_port, A1 => n2153, B0 =>
EX_REGB_27_port, B1 => n2151, Y => N4854);
U1401 : AO22XL port map( A0 => EX_IMM16_EXT_26_port, A1 => n2153, B0 =>
EX_REGB_26_port, B1 => n2151, Y => N4853);
U1402 : AO22XL port map( A0 => EX_IMM16_EXT_25_port, A1 => n2153, B0 =>
EX_REGB_25_port, B1 => n2151, Y => N4852);
U1403 : AO22XL port map( A0 => EX_IMM16_EXT_24_port, A1 => n2153, B0 =>
EX_REGB_24_port, B1 => n2151, Y => N4851);
U1404 : AO22XL port map( A0 => EX_IMM16_EXT_23_port, A1 => n2153, B0 =>
EX_REGB_23_port, B1 => n2151, Y => N4850);
U1405 : AO22XL port map( A0 => EX_IMM16_EXT_22_port, A1 => n2153, B0 =>
EX_REGB_22_port, B1 => n2151, Y => N4849);
U1406 : NAND2BXL port map( AN => n2156, B => PC_instance_n33, Y => n1626);
U1407 : NOR2BXL port map( AN => ID_EX_INSTR_REG_instance_n34, B => n1623, Y
=> n1624);
U1408 : INVXL port map( A => ID_INSTR_AFTER_CU_31_port, Y => n1623);
U1409 : AOI221XL port map( A0 => N4719, A1 => BOOTH_instance_n400, B0 =>
BOOTH_instance_n320, B1 => BOOTH_instance_n401, C0
=> BOOTH_instance_n405, Y => BOOTH_instance_n404);
U1410 : NAND2XL port map( A => N4840, B => BOOTH_instance_n322, Y => n1606);
U1411 : AOI22XL port map( A0 => EX_PC_7_port, A1 => n2142, B0 =>
EX_REGA_7_port, B1 => n2140, Y => n1607);
U1412 : AOI22XL port map( A0 => EX_PC_13_port, A1 => n2143, B0 =>
EX_REGA_13_port, B1 => n2141, Y => n1608);
U1413 : OAI21XL port map( A0 => BOOTH_instance_n448, A1 =>
BOOTH_instance_n156, B0 => BOOTH_instance_n151, Y =>
n1609);
U1414 : AOI22XL port map( A0 => EX_IMM16_EXT_1_port, A1 => n2153, B0 =>
EX_REGB_1_port, B1 => n1189, Y => n1610);
U1415 : OR2XL port map( A => EX_INSTR_30_port, B => EX_INSTR_29_port, Y =>
n1612);
U1416 : INVXL port map( A => n1698, Y => BOOTH_instance_n401);
U1417 : INVXL port map( A => n1708, Y => n1374);
U1418 : NOR2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_n88, B =>
ALU_instance_SHIFTER_GENERIC_I_n89, Y => n1614);
U1419 : NOR2XL port map( A => EX_SHIFTER_CW_1_port, B =>
ALU_instance_SHIFTER_GENERIC_I_n88, Y => n1615);
U1420 : NOR2XL port map( A => EX_SHIFTER_CW_1_port, B =>
EX_SHIFTER_CW_0_port, Y => n1616);
U1421 : INVXL port map( A => n2168, Y => n2167);
U1422 : AO22XL port map( A0 => EX_PC_5_port, A1 => n2142, B0 =>
EX_REGA_5_port, B1 => n2140, Y => n2117);
U1423 : AO22XL port map( A0 => EX_PC_6_port, A1 => n2142, B0 =>
EX_REGA_6_port, B1 => n2140, Y => n2119);
U1424 : NOR2XL port map( A => n1309, B => n1310, Y => n1617);
U1425 : NAND3XL port map( A => n320, B => n319, C => n321, Y => n1618);
U1426 : NOR2XL port map( A => n2149, B => n1330, Y => n1619);
n1621 <= '1';
n1622 <= '1';
n1625 <= '1';
n1627 <= '0';
U1431 : XOR2XL port map( A => n2193, B => BOOTH_instance_n461, Y =>
BOOTH_instance_n290);
U1432 : NAND2XL port map( A => n1566, B => EX_INSTR_26_port, Y => n1629);
U1433 : OR2XL port map( A => BOOTH_instance_n397, B => n1647, Y => n1630);
U1434 : XNOR3XL port map( A => BOOTH_instance_partial_products_3_31_port, B
=> n1640, C =>
BOOTH_instance_add_2_root_add_53_G7_carry_31_port, Y
=> BOOTH_instance_partial_products_7_31_port);
U1435 : OAI221XL port map( A0 => n2192, A1 => BOOTH_instance_n397, B0 =>
BOOTH_instance_n280, B1 => BOOTH_instance_n398, C0
=> BOOTH_instance_n403, Y =>
BOOTH_instance_decoded_2_7_port);
U1436 : INVXL port map( A => n1568, Y => n1399);
U1437 : OAI2BB2XL port map( B0 => n2171, B1 =>
ALU_instance_LOGIC_GENERIC_I_n49, A0N => N4831, A1N
=> n1642, Y => ALU_instance_LOGIC_OUT_4_port);
U1438 : NOR2XL port map( A => n1398, B => EX_INSTR_28_port, Y => n1581);
U1439 : NAND3XL port map( A => n1397, B => EX_INSTR_27_port, C => n1399, Y
=> n1525);
U1440 : NOR2XL port map( A => n1576, B => EX_INSTR_27_port, Y => n1580);
U1441 : INVXL port map( A => EX_INSTR_27_port, Y => n1398);
U1442 : NAND2XL port map( A => BOOTH_instance_n443, B => n1600, Y =>
BOOTH_instance_n421);
U1443 : INVXL port map( A => n2162, Y => n2161);
U1444 : NOR3XL port map( A => n2116, B => n2193, C => n2112, Y =>
BOOTH_instance_n460);
U1445 : CLKBUFX1 port map( A => n1355, Y => n2140);
U1446 : CLKBUFX1 port map( A => n1355, Y => n2141);
U1447 : INVX4 port map( A => n1594, Y => n2153);
U1448 : AOI211XL port map( A0 => n1547, A1 => n1563, B0 => n2153, C0 =>
n1564, Y => n1353);
U1449 : AOI22XL port map( A0 => BOOTH_instance_n400, A1 => N4721, B0 =>
BOOTH_instance_n401, B1 => BOOTH_instance_n292, Y =>
BOOTH_instance_n402);
U1450 : NOR2XL port map( A => n2153, B => n1353, Y => n1189);
U1451 : AO22XL port map( A0 => EX_PC_16_port, A1 => n2143, B0 =>
EX_REGA_16_port, B1 => n2141, Y => n1684);
U1452 : AO22XL port map( A0 => EX_PC_22_port, A1 => n2143, B0 =>
EX_REGA_22_port, B1 => n2141, Y => n1687);
U1453 : AO22XL port map( A0 => EX_PC_17_port, A1 => n2143, B0 =>
EX_REGA_17_port, B1 => n2141, Y => n1679);
U1454 : AO22XL port map( A0 => EX_PC_23_port, A1 => n2143, B0 =>
EX_REGA_23_port, B1 => n2141, Y => n1678);
U1455 : AO22XL port map( A0 => EX_PC_21_port, A1 => n2143, B0 =>
EX_REGA_21_port, B1 => n2141, Y => n1686);
U1456 : AO22XL port map( A0 => EX_PC_20_port, A1 => n2143, B0 =>
EX_REGA_20_port, B1 => n2141, Y => n1683);
U1457 : AO22XL port map( A0 => EX_PC_18_port, A1 => n2143, B0 =>
EX_REGA_18_port, B1 => n2141, Y => n1689);
U1458 : AO22XL port map( A0 => EX_PC_19_port, A1 => n2143, B0 =>
EX_REGA_19_port, B1 => n2141, Y => n1688);
U1459 : NAND2XL port map( A => n1633, B => n1634, Y => BOOTH_instance_n280);
U1460 : INVXL port map( A => n1593, Y => n2158);
U1461 : NAND2XL port map( A => N4721, B => n1632, Y => n1633);
U1462 : INVXL port map( A => BOOTH_instance_n460, Y => n1632);
U1463 : NAND2XL port map( A => EX_PC_2_port, B => n2142, Y => n1635);
U1464 : NAND2XL port map( A => EX_REGA_2_port, B => n2140, Y => n1636);
U1465 : INVXL port map( A => BOOTH_instance_n408, Y => BOOTH_instance_n400);
U1466 : NOR2XL port map( A => BOOTH_instance_n459, B => n2190, Y =>
BOOTH_instance_n457);
U1467 : INVXL port map( A => n1355, Y => n2142);
U1468 : AOI22XL port map( A0 => BOOTH_instance_n400, A1 => n2193, B0 =>
BOOTH_instance_n401, B1 => BOOTH_instance_n310, Y =>
BOOTH_instance_n403);
U1469 : CLKBUFX1 port map( A => n2152, Y => n2151);
U1470 : INVXL port map( A => n1600, Y => n2174);
U1471 : NAND3XL port map( A => n2174, B => BOOTH_instance_n396, C => n2167,
Y => BOOTH_instance_n408);
U1472 : INVXL port map( A => BOOTH_instance_n320, Y => BOOTH_instance_n308);
U1473 : OR2XL port map( A => n2163, B => n2159, Y => n1643);
U1474 : AO22XL port map( A0 => n2195, A1 => n2191, B0 => n2190, B1 =>
EX_LOGIC_CW_3_port, Y => n1642);
U1475 : XNOR2XL port map( A => n2115, B => BOOTH_instance_n316, Y =>
BOOTH_instance_n320);
U1476 : NOR2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_N202, B =>
n2115, Y => BOOTH_instance_n461);
U1477 : NOR2XL port map( A => n1565, B => n1613, Y => n1397);
U1478 : AOI211XL port map( A0 => n1569, A1 => n1573, B0 => n1574, C0 =>
n1558, Y => n1572);
U1479 : INVXL port map( A => N4832, Y => BOOTH_instance_n396);
U1480 : INVXL port map( A => n1535, Y => n1570);
U1481 : INVXL port map( A => N4722, Y => n2191);
U1482 : CLKBUFX1 port map( A => n1600, Y => n2176);
U1483 : AO22XL port map( A0 => EX_PC_5_port, A1 => n2142, B0 =>
EX_REGA_5_port, B1 => n2140, Y => n2118);
U1484 : AO22XL port map( A0 => EX_PC_6_port, A1 => n2142, B0 =>
EX_REGA_6_port, B1 => n2140, Y => n2120);
U1485 : AO22XL port map( A0 => EX_PC_0_port, A1 => n2142, B0 =>
EX_REGA_0_port, B1 => n2140, Y => n2112);
U1486 : NOR2XL port map( A => EX_INSTR_28_port, B => EX_INSTR_26_port, Y =>
n1577);
U1487 : AO22XL port map( A0 => EX_PC_0_port, A1 => n2142, B0 =>
EX_REGA_0_port, B1 => n2140, Y => n2111);
U1488 : AO22XL port map( A0 => EX_PC_0_port, A1 => n2142, B0 =>
EX_REGA_0_port, B1 => n2140, Y =>
ALU_instance_SHIFTER_GENERIC_I_N202);
U1489 : XOR2XL port map( A => n2187, B => BOOTH_instance_n455, Y =>
BOOTH_instance_n239);
U1490 : XOR2XL port map( A => n2181, B => BOOTH_instance_n452, Y =>
BOOTH_instance_n209);
U1491 : XOR2XL port map( A => n2178, B => BOOTH_instance_n449, Y =>
BOOTH_instance_n189);
U1492 : INVXL port map( A => n2173, Y => n2171);
U1493 : INVXL port map( A => BOOTH_instance_n151, Y => BOOTH_instance_n157);
U1494 : CLKINVX2 port map( A => n1695, Y => BOOTH_instance_decoded_1_31_port
);
U1495 : XNOR3XL port map( A => BOOTH_instance_decoded_4_31_port, B =>
BOOTH_instance_decoded_5_31_port, C =>
BOOTH_instance_add_5_root_add_53_G7_carry_31_port, Y
=> n1640);
U1496 : CLKINVX1 port map( A => n1696, Y => BOOTH_instance_decoded_0_31_port
);
U1497 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C48_n109, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n55);
U1498 : INVXL port map( A => n1697, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n75);
U1499 : INVXL port map( A => n2173, Y => n2169);
U1500 : INVXL port map( A => n2172, Y => n2170);
U1501 : XOR2XL port map( A => BOOTH_instance_n450, B => n1670, Y =>
BOOTH_instance_n177);
U1502 : XOR2XL port map( A => BOOTH_instance_n456, B => n1607, Y =>
BOOTH_instance_n249);
U1503 : XOR2XL port map( A => BOOTH_instance_n453, B => n2186, Y =>
BOOTH_instance_n229);
U1504 : XOR2XL port map( A => BOOTH_instance_n451, B => n2180, Y =>
BOOTH_instance_n199);
U1505 : XOR2XL port map( A => n2183, B => BOOTH_instance_n454, Y =>
BOOTH_instance_n219);
U1506 : NAND2XL port map( A => BOOTH_instance_n317, B => BOOTH_instance_n315
, Y => BOOTH_instance_n166);
U1507 : CLKINVX1 port map( A => n1608, Y => n2178);
U1508 : INVXL port map( A => BOOTH_instance_n155, Y => BOOTH_instance_n168);
U1509 : NAND2XL port map( A => BOOTH_instance_n448, B => BOOTH_instance_n156
, Y => BOOTH_instance_n151);
U1510 : AO2B2XL port map( B0 => EX_ALU_OUT_0_port, B1 => n2144, A0 => n2145,
A1N => n1641, Y => N4860);
U1511 : AO21XL port map( A0 => n2129, A1 => BOOTH_instance_n447, B0 =>
BOOTH_instance_n316, Y => n1641);
U1512 : AOI21XL port map( A0 => n1706, A1 => BOOTH_instance_n350, B0 =>
BOOTH_instance_n157, Y =>
BOOTH_instance_decoded_4_31_port);
U1513 : CLKINVX1 port map( A => n1670, Y => n2177);
U1514 : INVXL port map( A => EX_ADD_SUB, Y => n2137);
U1515 : XOR2XL port map( A => n2135, B => n2174, Y =>
ALU_instance_INTERNAL_B_3_port);
U1516 : AOI21XL port map( A0 => BOOTH_instance_n323, A1 => n1703, B0 =>
BOOTH_instance_n157, Y =>
BOOTH_instance_decoded_5_31_port);
U1517 : INVXL port map( A => n1700, Y => BOOTH_instance_decoded_3_31_port);
U1518 : INVXL port map( A => n1701, Y => BOOTH_instance_decoded_2_31_port);
U1519 : NAND2XL port map( A => n2163, B => n2158, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n46);
U1520 : NAND2XL port map( A => n2159, B => n2165, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n44);
U1521 : NOR2BXL port map( AN => n2175, B =>
ALU_instance_SHIFTER_GENERIC_I_C50_n139, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n73);
U1522 : NOR2XL port map( A => n2176, B => n2161, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n74);
U1523 : AND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_C86_n133, B =>
n2162, Y => ALU_instance_SHIFTER_GENERIC_I_C86_n18);
U1524 : AND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_C48_n152, B =>
n2162, Y => ALU_instance_SHIFTER_GENERIC_I_C48_n8);
U1525 : AND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_C50_n153, B =>
n2162, Y => ALU_instance_SHIFTER_GENERIC_I_C50_n8);
U1526 : NOR2XL port map( A => n2166, B => n2158, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n48);
U1527 : NOR2XL port map( A => n2163, B => n2159, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n49);
U1528 : NOR2XL port map( A => n2163, B => n2159, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n50);
U1529 : NAND2XL port map( A => n2163, B => n2158, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n22);
U1530 : NAND2XL port map( A => n2159, B => n2163, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n43);
U1531 : NOR2BXL port map( AN => n2163, B => n2158, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n25);
U1532 : OR2XL port map( A => n2166, B => n2158, Y => n1644);
U1533 : NAND2XL port map( A => n2159, B => n2165, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n45);
U1534 : AO2B2XL port map( B0 => EX_ALU_OUT_2_port, B1 => n2144, A0 => n2145,
A1N => n1645, Y => N4862);
U1535 : XNOR2XL port map( A => BOOTH_instance_decoded_1_2_port, B =>
BOOTH_instance_N211_port, Y => n1645);
U1536 : NOR2XL port map( A => n1600, B => n2113, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n84);
U1537 : NAND2XL port map( A => n2174, B => n2162, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n70);
U1538 : CLKBUFX1 port map( A => n1615, Y => n2133);
U1539 : NOR2XL port map( A => ALU_instance_n23, B => EX_ALU_SEL_0_port, Y =>
ALU_instance_n6);
U1540 : INVXL port map( A => n1531, Y => EX_LOGIC_CW_3_port);
U1541 : NOR3XL port map( A => n2146, B => n1227, C => n2147, Y => n1646);
U1542 : AND2XL port map( A => EX_ALU_SEL_0_port, B => EX_ALU_SEL_1_port, Y
=> ALU_instance_n5);
U1543 : INVXL port map( A => n1702, Y => ALU_instance_SHIFTER_GENERIC_I_n13)
;
U1544 : CLKINVX1 port map( A => n2184, Y => n2183);
U1545 : OAI221XL port map( A0 => n1647, A1 => BOOTH_instance_n186, B0 =>
BOOTH_instance_n290, B1 => n1606, C0 =>
BOOTH_instance_n319, Y => BOOTH_instance_n305);
U1546 : NAND2XL port map( A => n1648, B => BOOTH_instance_n348, Y =>
BOOTH_instance_n323);
U1547 : NAND2XL port map( A => N4836, B => BOOTH_instance_n371, Y =>
BOOTH_instance_n350);
U1548 : NAND2XL port map( A => N4834, B => BOOTH_instance_n395, Y =>
BOOTH_instance_n374);
U1549 : NAND2XL port map( A => N4842, B => BOOTH_instance_n317, Y =>
BOOTH_instance_n158);
U1550 : INVXL port map( A => n1651, Y => BOOTH_instance_n156);
U1551 : INVXL port map( A => n2120, Y => BOOTH_instance_n260);
U1552 : NAND3XL port map( A => N4841, B => BOOTH_instance_n315, C => N4840,
Y => BOOTH_instance_n155);
U1553 : INVXL port map( A => n2116, Y => BOOTH_instance_n307);
U1554 : INVXL port map( A => N4727, Y => n2186);
U1555 : INVXL port map( A => N4730, Y => n2180);
U1556 : INVXL port map( A => N4726, Y => n2188);
U1557 : INVXL port map( A => N4729, Y => n2182);
U1558 : INVXL port map( A => N4842, Y => BOOTH_instance_n315);
U1559 : INVXL port map( A => N4836, Y => BOOTH_instance_n346);
U1560 : INVXL port map( A => N4840, Y => BOOTH_instance_n318);
U1561 : INVXL port map( A => n1706, Y => BOOTH_instance_n353);
U1562 : INVXL port map( A => n1707, Y => BOOTH_instance_n377);
U1563 : INVXL port map( A => n1704, Y => BOOTH_instance_n176);
U1564 : INVXL port map( A => n1721, Y => BOOTH_instance_n150);
U1565 : INVXL port map( A => n1705, Y => BOOTH_instance_n326);
U1566 : INVXL port map( A => n1703, Y => BOOTH_instance_n327);
U1567 : INVXL port map( A => EX_ADD_SUB, Y => n2135);
U1568 : INVXL port map( A => EX_ADD_SUB, Y => n2136);
U1569 : XOR2XL port map( A => n2137, B => N4841, Y =>
ALU_instance_INTERNAL_B_14_port);
U1570 : XOR2XL port map( A => n2135, B => N4833, Y =>
ALU_instance_INTERNAL_B_6_port);
U1571 : XOR2XL port map( A => n2137, B => n1648, Y =>
ALU_instance_INTERNAL_B_11_port);
U1572 : XOR2XL port map( A => n2137, B => N4837, Y =>
ALU_instance_INTERNAL_B_10_port);
U1573 : XOR2XL port map( A => n2135, B => N4836, Y =>
ALU_instance_INTERNAL_B_9_port);
U1574 : XOR2XL port map( A => n2135, B => N4832, Y =>
ALU_instance_INTERNAL_B_5_port);
U1575 : XOR2XL port map( A => n2135, B => N4834, Y =>
ALU_instance_INTERNAL_B_7_port);
U1576 : XOR2XL port map( A => n2137, B => N4840, Y =>
ALU_instance_INTERNAL_B_13_port);
U1577 : AOI222XL port map( A0 => n2126, A1 => n2193, B0 => n2116, B1 =>
n2130, C0 => n2111, C1 => n2159, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n100);
U1578 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n49, A1
=> n1682, B0 => n2125, B1 => n1691, C0 => n2158, C1
=> n1692, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n86);
U1579 : OAI221XL port map( A0 => n2127, A1 => n2192, B0 => n2129, B1 =>
n1647, C0 => ALU_instance_SHIFTER_GENERIC_I_C86_n159
, Y => ALU_instance_SHIFTER_GENERIC_I_C86_n74);
U1580 : OAI221XL port map( A0 => n2127, A1 => n2191, B0 => n2192, B1 =>
n2129, C0 => ALU_instance_SHIFTER_GENERIC_I_C86_n179
, Y => ALU_instance_SHIFTER_GENERIC_I_C86_n99);
U1581 : OAI221XL port map( A0 => n2128, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n166, B0 => n2129
, B1 => n2191, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n174, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n92);
U1582 : AOI222XL port map( A0 => n2125, A1 => n1691, B0 => n2124, B1 =>
n1692, C0 => ALU_instance_SHIFTER_GENERIC_I_C50_n49,
C1 => n1682, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n64);
U1583 : AOI221XL port map( A0 => n2124, A1 => n2177, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n52, B1 => n1651,
C0 => ALU_instance_SHIFTER_GENERIC_I_C48_n156, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n129);
U1584 : AOI221XL port map( A0 => n2124, A1 => n1684, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n52, B1 => n1679,
C0 => ALU_instance_SHIFTER_GENERIC_I_C48_n146, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n114);
U1585 : AOI221XL port map( A0 => n2124, A1 => n1651, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n52, B1 => n1684,
C0 => ALU_instance_SHIFTER_GENERIC_I_C48_n128, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n97);
U1586 : INVXL port map( A => n690, Y => n2162);
U1587 : INVXL port map( A => n688, Y => n2165);
U1588 : CLKBUFX1 port map( A => EX_LOGIC_CW_2_port, Y => n2195);
U1589 : CLKBUFX1 port map( A => EX_LOGIC_CW_2_port, Y => n2194);
U1590 : NAND3XL port map( A => n1533, B => n1531, C => n1546, Y =>
EX_ALU_SEL_1_port);
U1591 : NAND2XL port map( A => n1516, B => n1517, Y => n1292);
U1592 : INVXL port map( A => n2121, Y => n1310);
U1593 : INVXL port map( A => n1618, Y => n1522);
U1594 : CLKBUFX1 port map( A => n1211, Y => n2149);
U1595 : NOR3XL port map( A => EX_INSTR_30_port, B => EX_INSTR_31_port, C =>
n1576, Y => n1535);
U1596 : AO2B2XL port map( B0 => EX_REGB_11_port, B1 => n2151, A0 => n2153,
A1N => n1649, Y => n1648);
U1597 : AO2B2XL port map( B0 => EX_REGA_10_port, B1 => n2141, A0 => n2142,
A1N => n1650, Y => N4728);
U1598 : AO22XL port map( A0 => EX_PC_15_port, A1 => n2143, B0 =>
EX_REGA_15_port, B1 => n2141, Y => n1651);
U1599 : NOR2XL port map( A => n1611, B => EX_INSTR_31_port, Y => n1575);
U1600 : AO2B2XL port map( B0 => EX_REGB_14_port, B1 => n2151, A0 => n2153,
A1N => n1652, Y => N4841);
U1601 : NAND2XL port map( A => EX_INSTR_26_port, B => n1356, Y => n1355);
U1602 : AO2B2XL port map( B0 => EX_REGB_6_port, B1 => n2152, A0 => n2153,
A1N => n1653, Y => N4833);
U1603 : AO2B2XL port map( B0 => EX_REGB_12_port, B1 => n2151, A0 => n2153,
A1N => n1654, Y => N4839);
U1604 : AO2B2XL port map( B0 => EX_REGB_8_port, B1 => n2152, A0 => n2153,
A1N => n1655, Y => N4835);
U1605 : AO2B2XL port map( B0 => EX_REGB_10_port, B1 => n2151, A0 => n2153,
A1N => n1656, Y => N4837);
U1606 : AO2B2XL port map( B0 => EX_REGB_9_port, B1 => n2152, A0 => n2153,
A1N => n1657, Y => N4836);
U1607 : AO2B2XL port map( B0 => EX_REGB_5_port, B1 => n2152, A0 => n2153,
A1N => n1658, Y => N4832);
U1608 : AO2B2XL port map( B0 => EX_REGB_7_port, B1 => n2152, A0 => n2153,
A1N => n1659, Y => N4834);
U1609 : AO2B2XL port map( B0 => EX_REGB_15_port, B1 => n2151, A0 => n2153,
A1N => n1660, Y => N4842);
U1610 : AO2B2XL port map( B0 => EX_REGB_13_port, B1 => n2151, A0 => n2153,
A1N => n1661, Y => N4840);
U1611 : AO2B2XL port map( B0 => EX_REGB_0_port, B1 => n2152, A0 => n2153,
A1N => n1662, Y => n688);
U1612 : INVXL port map( A => EX_INSTR_29_port, Y => n1576);
U1613 : INVXL port map( A => EX_INSTR_28_port, Y => n1565);
U1614 : AO2B2XL port map( B0 => EX_REGB_4_port, B1 => n1189, A0 => n2153,
A1N => n1664, Y => N4831);
U1615 : AO2B2XL port map( B0 => EX_REGA_4_port, B1 => n2140, A0 => n2142,
A1N => n1665, Y => N4722);
U1616 : AO2B2XL port map( B0 => EX_REGA_8_port, B1 => n2141, A0 => n2142,
A1N => n1666, Y => N4726);
U1617 : AO2B2XL port map( B0 => EX_REGA_9_port, B1 => n2141, A0 => n2142,
A1N => n1667, Y => N4727);
U1618 : AO2B2XL port map( B0 => EX_REGA_11_port, B1 => n2141, A0 => n2142,
A1N => n1668, Y => N4729);
U1619 : AO2B2XL port map( B0 => EX_REGA_12_port, B1 => n2141, A0 => n2142,
A1N => n1669, Y => N4730);
U1620 : AOI22XL port map( A0 => EX_PC_14_port, A1 => n2143, B0 =>
EX_REGA_14_port, B1 => n2141, Y => n1670);
U1621 : AO2B2XL port map( B0 => EX_REGB_21_port, B1 => n2151, A0 => n2153,
A1N => n1671, Y => N4848);
U1622 : AO2B2XL port map( B0 => EX_REGB_20_port, B1 => n2151, A0 => n2153,
A1N => n1672, Y => N4847);
U1623 : AO2B2XL port map( B0 => EX_REGB_19_port, B1 => n2151, A0 => n2153,
A1N => n1673, Y => N4846);
U1624 : AO2B2XL port map( B0 => EX_REGB_18_port, B1 => n2151, A0 => n2153,
A1N => n1674, Y => N4845);
U1625 : AO2B2XL port map( B0 => EX_REGB_17_port, B1 => n2151, A0 => n2153,
A1N => n1675, Y => N4844);
U1626 : AO2B2XL port map( B0 => EX_REGB_16_port, B1 => n2151, A0 => n2153,
A1N => n1676, Y => N4843);
U1627 : INVXL port map( A => EX_INSTR_1_port, Y => n1560);
U1628 : AO22XL port map( A0 => EX_PC_25_port, A1 => n2143, B0 =>
EX_REGA_25_port, B1 => n2141, Y => n1677);
U1629 : AO22XL port map( A0 => EX_PC_26_port, A1 => n2143, B0 =>
EX_REGA_26_port, B1 => n2141, Y => n1680);
U1630 : AO22XL port map( A0 => EX_PC_27_port, A1 => n2143, B0 =>
EX_REGA_27_port, B1 => n2141, Y => n1681);
U1631 : AO22XL port map( A0 => EX_PC_29_port, A1 => n2143, B0 =>
EX_REGA_29_port, B1 => n2141, Y => n1682);
U1632 : AO22XL port map( A0 => EX_PC_24_port, A1 => n2143, B0 =>
EX_REGA_24_port, B1 => n2141, Y => n1685);
U1633 : AO22XL port map( A0 => EX_PC_28_port, A1 => n2143, B0 =>
EX_REGA_28_port, B1 => n2141, Y => n1690);
U1634 : AO22XL port map( A0 => EX_PC_30_port, A1 => n2143, B0 =>
EX_REGA_30_port, B1 => n2141, Y => n1691);
U1635 : AO22XL port map( A0 => EX_PC_31_port, A1 => n2143, B0 =>
EX_REGA_31_port, B1 => n2141, Y => n1692);
U1636 : AO2B2XL port map( B0 => EX_REGB_31_port, B1 => n2152, A0 => n2153,
A1N => n1693, Y => EX_ALU_B_31_port);
U1637 : CLKBUFX2 port map( A => ID_IMM16_SHL2_31_port, Y => n2109);
U1638 : NOR4XL port map( A => ID_INSTR_27, B => ID_INSTR_29, C =>
ID_INSTR_30, D => ID_INSTR_31, Y => n1516);
U1639 : NOR3XL port map( A => n1195, B => ID_INSTR_28, C => n1293, Y =>
n1226);
U1640 : NOR3XL port map( A => ID_INSTR_29, B => ID_INSTR_31, C => n1484, Y
=> n1291);
U1641 : NAND2XL port map( A => n1532, B => n1533, Y => EX_LOGIC_CW_2_port);
U1642 : INVXL port map( A => ID_INSTR_28, Y => n1290);
U1643 : INVXL port map( A => ID_INSTR_26, Y => n1518);
U1644 : OAI31XL port map( A0 => n1196, A1 => ID_INSTR_27, A2 => n1521, B0 =>
n1198, Y => n1370);
U1645 : NAND2XL port map( A => IF_STALL_SEL, B => n1618, Y => n697);
U1646 : INVXL port map( A => ID_INSTR_30, Y => n1483);
U1647 : NOR3BXL port map( AN => n1436, B => n1213, C => MEM_INSTR_28_port, Y
=> n1435);
U1648 : CLKBUFX1 port map( A => n1342, Y => n2121);
U1649 : NAND4XL port map( A => n1215, B => MEM_INSTR_29_port, C => n1444, D
=> n1220, Y => n1216);
U1650 : INVXL port map( A => WB_INSTR_30, Y => n1340);
U1651 : INVXL port map( A => MEM_INSTR_28_port, Y => n1220);
U1652 : INVXL port map( A => WB_INSTR_29, Y => n1471);
U1653 : INVXL port map( A => n1822, Y => WB_SIGN_EXT_16_CONTROL);
U1654 : INVXL port map( A => MEM_INSTR_26_port, Y => n1445);
U1655 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C48_n41, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n3);
U1656 : NOR2XL port map( A => ALU_instance_COMPARATOR_GENERIC_I_n9, B =>
ALU_instance_ZERO, Y =>
ALU_instance_COMPARATOR_GENERIC_I_n7);
U1657 : INVXL port map( A => BOOTH_instance_n239, Y => BOOTH_instance_n232);
U1658 : INVXL port map( A => BOOTH_instance_n209, Y => BOOTH_instance_n202);
U1659 : INVXL port map( A => BOOTH_instance_n189, Y => BOOTH_instance_n180);
U1660 : INVXL port map( A => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_3_port,
Y => ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_n2);
U1661 : INVXL port map( A => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_2_port,
Y => ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_n2);
U1662 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C48_n43, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n21);
U1663 : NOR2XL port map( A => n1697, B => n2171, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n16);
U1664 : NOR2XL port map( A => n1697, B => n2171, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n41);
U1665 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C86_n132, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n3);
U1666 : OAI21XL port map( A0 => n2170, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n8, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n3, Y =>
ALU_instance_SHIFTER_GENERIC_I_N206);
U1667 : OAI21XL port map( A0 => n2170, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n9, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n3, Y =>
ALU_instance_SHIFTER_GENERIC_I_N205);
U1668 : OAI21XL port map( A0 => n2170, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n115, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n3, Y =>
ALU_instance_SHIFTER_GENERIC_I_N203);
U1669 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C50_n122, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n10);
U1670 : OR2XL port map( A => n1697, B => n2171, Y => n1694);
U1671 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C50_n38, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n6);
U1672 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C86_n11, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n55);
U1673 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C48_n38, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n6);
U1674 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C48_n107, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n103);
U1675 : NOR4XL port map( A => ALU_instance_ADDER_OUT_5_port, B =>
ALU_instance_ADDER_OUT_4_port, C =>
ALU_instance_ADDER_OUT_3_port, D =>
ALU_instance_ADDER_OUT_31_port, Y =>
ALU_instance_COMPARATOR_GENERIC_I_n18);
U1676 : OAI2BB2XL port map( B0 => BOOTH_instance_n293, B1 =>
BOOTH_instance_n294, A0N => BOOTH_instance_n295, A1N
=> BOOTH_instance_n296, Y => BOOTH_instance_n286);
U1677 : NOR2XL port map( A => BOOTH_instance_n296, B => BOOTH_instance_n295,
Y => BOOTH_instance_n294);
U1678 : NOR2XL port map( A => ALU_instance_COMPARATOR_GENERIC_I_n10, B =>
ALU_instance_COMPARATOR_GENERIC_I_n11, Y =>
ALU_instance_ZERO);
U1679 : NAND4XL port map( A => ALU_instance_COMPARATOR_GENERIC_I_n12, B =>
ALU_instance_COMPARATOR_GENERIC_I_n13, C =>
ALU_instance_COMPARATOR_GENERIC_I_n14, D =>
ALU_instance_COMPARATOR_GENERIC_I_n15, Y =>
ALU_instance_COMPARATOR_GENERIC_I_n11);
U1680 : NAND4XL port map( A => ALU_instance_COMPARATOR_GENERIC_I_n16, B =>
ALU_instance_COMPARATOR_GENERIC_I_n17, C =>
ALU_instance_COMPARATOR_GENERIC_I_n18, D =>
ALU_instance_COMPARATOR_GENERIC_I_n19, Y =>
ALU_instance_COMPARATOR_GENERIC_I_n10);
U1681 : NOR4XL port map( A => ALU_instance_ADDER_OUT_12_port, B =>
ALU_instance_ADDER_OUT_11_port, C =>
ALU_instance_ADDER_OUT_10_port, D =>
ALU_instance_ADDER_OUT_0_port, Y =>
ALU_instance_COMPARATOR_GENERIC_I_n12);
U1682 : NOR2XL port map( A => BOOTH_instance_n451, B => n2179, Y =>
BOOTH_instance_n449);
U1683 : AO22XL port map( A0 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_C1,
A1 => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_2_port
, B0 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_C0,
B1 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_n2, Y
=> ALU_instance_CARRY_SELECT_ADDER_I_CARRY_3_port);
U1684 : AO22XL port map( A0 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_C1,
A1 => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_1_port
, B0 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_C0,
B1 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_n2, Y
=> ALU_instance_CARRY_SELECT_ADDER_I_CARRY_2_port);
U1685 : NOR2XL port map( A => BOOTH_instance_n456, B => n2189, Y =>
BOOTH_instance_n455);
U1686 : AOI22XL port map( A0 => BOOTH_instance_n400, A1 => n2190, B0 =>
BOOTH_instance_n401, B1 => BOOTH_instance_n272, Y =>
BOOTH_instance_n399);
U1687 : AOI22XL port map( A0 => BOOTH_instance_n400, A1 => n2189, B0 =>
BOOTH_instance_n401, B1 => BOOTH_instance_n242, Y =>
BOOTH_instance_n416);
U1688 : AOI22XL port map( A0 => BOOTH_instance_n400, A1 => n2187, B0 =>
BOOTH_instance_n401, B1 => BOOTH_instance_n232, Y =>
BOOTH_instance_n415);
U1689 : AOI22XL port map( A0 => BOOTH_instance_n400, A1 => n2185, B0 =>
BOOTH_instance_n401, B1 => BOOTH_instance_n222, Y =>
BOOTH_instance_n414);
U1690 : AOI22XL port map( A0 => BOOTH_instance_n400, A1 => n2181, B0 =>
BOOTH_instance_n401, B1 => BOOTH_instance_n202, Y =>
BOOTH_instance_n412);
U1691 : AOI22XL port map( A0 => BOOTH_instance_n400, A1 => n2179, B0 =>
BOOTH_instance_n401, B1 => BOOTH_instance_n192, Y =>
BOOTH_instance_n411);
U1692 : AOI22XL port map( A0 => BOOTH_instance_n400, A1 => n2178, B0 =>
BOOTH_instance_n401, B1 => BOOTH_instance_n180, Y =>
BOOTH_instance_n410);
U1693 : AOI22XL port map( A0 => BOOTH_instance_n400, A1 => n2177, B0 =>
BOOTH_instance_n401, B1 => BOOTH_instance_n169, Y =>
BOOTH_instance_n409);
U1694 : AOI21XL port map( A0 => BOOTH_instance_n422, A1 =>
BOOTH_instance_n421, B0 => BOOTH_instance_n316, Y =>
BOOTH_instance_decoded_1_2_port);
U1695 : AO2B2XL port map( B0 => BOOTH_instance_n170, B1 =>
BOOTH_instance_n171, A0 => BOOTH_instance_n172, A1N
=> BOOTH_instance_n173, Y => BOOTH_instance_n159);
U1696 : NOR2XL port map( A => BOOTH_instance_n171, B => BOOTH_instance_n170,
Y => BOOTH_instance_n173);
U1697 : AO21XL port map( A0 => BOOTH_instance_n422, A1 => n1699, B0 =>
BOOTH_instance_n157, Y => n1695);
U1698 : OAI21XL port map( A0 => BOOTH_instance_n424, A1 =>
BOOTH_instance_n425, B0 => n2111, Y =>
BOOTH_instance_n432);
U1699 : OAI2BB1XL port map( A0N => BOOTH_instance_n159, A1N =>
BOOTH_instance_n160, B0 => BOOTH_instance_n161, Y =>
BOOTH_instance_n147);
U1700 : OAI21XL port map( A0 => BOOTH_instance_n160, A1 =>
BOOTH_instance_n159, B0 => BOOTH_instance_n162, Y =>
BOOTH_instance_n161);
U1701 : AO21XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n22, A1 =>
n2127, B0 => BOOTH_instance_n157, Y => n1696);
U1702 : INVXL port map( A => BOOTH_instance_n299, Y => BOOTH_instance_n272);
U1703 : INVXL port map( A => BOOTH_instance_n177, Y => BOOTH_instance_n169);
U1704 : INVXL port map( A => BOOTH_instance_n280, Y => BOOTH_instance_n292);
U1705 : INVXL port map( A => BOOTH_instance_n259, Y => BOOTH_instance_n252);
U1706 : INVXL port map( A => BOOTH_instance_n199, Y => BOOTH_instance_n192);
U1707 : INVXL port map( A => BOOTH_instance_n219, Y => BOOTH_instance_n212);
U1708 : INVXL port map( A => BOOTH_instance_n229, Y => BOOTH_instance_n222);
U1709 : INVXL port map( A => BOOTH_instance_n249, Y => BOOTH_instance_n242);
U1710 : INVXL port map( A => BOOTH_instance_n166, Y => BOOTH_instance_n282);
U1711 : AO2B2XL port map( B0 => BOOTH_instance_n223, B1 =>
BOOTH_instance_n224, A0 => BOOTH_instance_n225, A1N
=> BOOTH_instance_n226, Y => BOOTH_instance_n215);
U1712 : NOR2XL port map( A => BOOTH_instance_n224, B => BOOTH_instance_n223,
Y => BOOTH_instance_n226);
U1713 : AO2B2XL port map( B0 => BOOTH_instance_n203, B1 =>
BOOTH_instance_n204, A0 => BOOTH_instance_n205, A1N
=> BOOTH_instance_n206, Y => BOOTH_instance_n195);
U1714 : NOR2XL port map( A => BOOTH_instance_n204, B => BOOTH_instance_n203,
Y => BOOTH_instance_n206);
U1715 : AO2B2XL port map( B0 => BOOTH_instance_n193, B1 =>
BOOTH_instance_n194, A0 => BOOTH_instance_n195, A1N
=> BOOTH_instance_n196, Y => BOOTH_instance_n183);
U1716 : NOR2XL port map( A => BOOTH_instance_n194, B => BOOTH_instance_n193,
Y => BOOTH_instance_n196);
U1717 : AO2B2XL port map( B0 => BOOTH_instance_n181, B1 =>
BOOTH_instance_n182, A0 => BOOTH_instance_n183, A1N
=> BOOTH_instance_n184, Y => BOOTH_instance_n172);
U1718 : NOR2XL port map( A => BOOTH_instance_n182, B => BOOTH_instance_n181,
Y => BOOTH_instance_n184);
U1719 : XNOR2XL port map( A => BOOTH_instance_n297, B => BOOTH_instance_n296
, Y => BOOTH_instance_partial_products_5_16_port);
U1720 : XOR2XL port map( A => BOOTH_instance_partial_products_2_16_port, B
=> BOOTH_instance_decoded_8_16_port, Y =>
BOOTH_instance_partial_products_6_16_port);
U1721 : XOR2XL port map( A => BOOTH_instance_n295, B => BOOTH_instance_n293,
Y => BOOTH_instance_n297);
U1722 : XNOR2XL port map( A => BOOTH_instance_n227, B => BOOTH_instance_n224
, Y => BOOTH_instance_partial_products_5_23_port);
U1723 : XNOR2XL port map( A => BOOTH_instance_n225, B => BOOTH_instance_n223
, Y => BOOTH_instance_n227);
U1724 : XNOR2XL port map( A => BOOTH_instance_n207, B => BOOTH_instance_n204
, Y => BOOTH_instance_partial_products_5_25_port);
U1725 : XNOR2XL port map( A => BOOTH_instance_n205, B => BOOTH_instance_n203
, Y => BOOTH_instance_n207);
U1726 : XNOR2XL port map( A => BOOTH_instance_n185, B => BOOTH_instance_n182
, Y => BOOTH_instance_partial_products_5_27_port);
U1727 : XNOR2XL port map( A => BOOTH_instance_n183, B => BOOTH_instance_n181
, Y => BOOTH_instance_n185);
U1728 : XNOR2XL port map( A => BOOTH_instance_n174, B => BOOTH_instance_n171
, Y => BOOTH_instance_partial_products_5_28_port);
U1729 : XNOR2XL port map( A => BOOTH_instance_n172, B => BOOTH_instance_n170
, Y => BOOTH_instance_n174);
U1730 : XOR2XL port map( A => BOOTH_instance_n159, B => BOOTH_instance_n163,
Y => BOOTH_instance_partial_products_5_29_port);
U1731 : XNOR2XL port map( A => BOOTH_instance_n162, B => BOOTH_instance_n146
, Y => BOOTH_instance_n163);
U1732 : XOR2XL port map( A => BOOTH_instance_n147, B => BOOTH_instance_n152,
Y => BOOTH_instance_partial_products_5_30_port);
U1733 : XNOR2XL port map( A => BOOTH_instance_n145, B => BOOTH_instance_n146
, Y => BOOTH_instance_n152);
U1734 : INVXL port map( A => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_5_port,
Y => ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_n2);
U1735 : INVXL port map( A => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_4_port,
Y => ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_n2);
U1736 : INVXL port map( A => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_1_port,
Y => ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_n2);
U1737 : INVXL port map( A => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_7_port,
Y => ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_n2);
U1738 : INVXL port map( A => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_6_port,
Y => ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_n2);
U1739 : XOR2XL port map( A => n2137, B => n2163, Y =>
ALU_instance_INTERNAL_B_0_port);
U1740 : INVXL port map( A => ALU_instance_OVERFLOW, Y =>
ALU_instance_COMPARATOR_GENERIC_I_n9);
U1741 : AOI221XL port map( A0 => n2124, A1 => n2178, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n52, B1 => n2177,
C0 => ALU_instance_SHIFTER_GENERIC_I_C48_n142, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n43);
U1742 : AO22XL port map( A0 => n2179, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n48, B0 => n2181,
B1 => ALU_instance_SHIFTER_GENERIC_I_C50_n49, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n142);
U1743 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_n47, B =>
ALU_instance_SHIFTER_GENERIC_I_n48, Y =>
ALU_instance_SHIFTER_OUT_27_port);
U1744 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_N261, B =>
n2134, Y => ALU_instance_SHIFTER_GENERIC_I_n47);
U1745 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_N229, A1 =>
n2131, B0 => ALU_instance_SHIFTER_GENERIC_I_N132, B1
=> n1616, C0 => ALU_instance_SHIFTER_GENERIC_I_N164,
C1 => n2133, Y => ALU_instance_SHIFTER_GENERIC_I_n48
);
U1746 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_n49, B =>
ALU_instance_SHIFTER_GENERIC_I_n50, Y =>
ALU_instance_SHIFTER_OUT_26_port);
U1747 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_N260, B =>
n2134, Y => ALU_instance_SHIFTER_GENERIC_I_n49);
U1748 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_N228, A1 =>
n2131, B0 => ALU_instance_SHIFTER_GENERIC_I_N131, B1
=> n1616, C0 => ALU_instance_SHIFTER_GENERIC_I_N163,
C1 => n2133, Y => ALU_instance_SHIFTER_GENERIC_I_n50
);
U1749 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_n51, B =>
ALU_instance_SHIFTER_GENERIC_I_n52, Y =>
ALU_instance_SHIFTER_OUT_25_port);
U1750 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_N259, B =>
n2134, Y => ALU_instance_SHIFTER_GENERIC_I_n51);
U1751 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_N227, A1 =>
n2131, B0 => ALU_instance_SHIFTER_GENERIC_I_N130, B1
=> n1616, C0 => ALU_instance_SHIFTER_GENERIC_I_N162,
C1 => n2133, Y => ALU_instance_SHIFTER_GENERIC_I_n52
);
U1752 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_n53, B =>
ALU_instance_SHIFTER_GENERIC_I_n54, Y =>
ALU_instance_SHIFTER_OUT_24_port);
U1753 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_N258, B =>
n2134, Y => ALU_instance_SHIFTER_GENERIC_I_n53);
U1754 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_N226, A1 =>
n2131, B0 => ALU_instance_SHIFTER_GENERIC_I_N129, B1
=> n1616, C0 => ALU_instance_SHIFTER_GENERIC_I_N161,
C1 => n2133, Y => ALU_instance_SHIFTER_GENERIC_I_n54
);
U1755 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_n55, B =>
ALU_instance_SHIFTER_GENERIC_I_n56, Y =>
ALU_instance_SHIFTER_OUT_23_port);
U1756 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_N257, B =>
n2134, Y => ALU_instance_SHIFTER_GENERIC_I_n55);
U1757 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_N225, A1 =>
n2131, B0 => ALU_instance_SHIFTER_GENERIC_I_N128, B1
=> n1616, C0 => ALU_instance_SHIFTER_GENERIC_I_N160,
C1 => n2133, Y => ALU_instance_SHIFTER_GENERIC_I_n56
);
U1758 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_n57, B =>
ALU_instance_SHIFTER_GENERIC_I_n58, Y =>
ALU_instance_SHIFTER_OUT_22_port);
U1759 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_N256, B =>
n2134, Y => ALU_instance_SHIFTER_GENERIC_I_n57);
U1760 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_N224, A1 =>
n2131, B0 => ALU_instance_SHIFTER_GENERIC_I_N127, B1
=> n1616, C0 => ALU_instance_SHIFTER_GENERIC_I_N159,
C1 => n2133, Y => ALU_instance_SHIFTER_GENERIC_I_n58
);
U1761 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_n59, B =>
ALU_instance_SHIFTER_GENERIC_I_n60, Y =>
ALU_instance_SHIFTER_OUT_21_port);
U1762 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_N255, B =>
n2134, Y => ALU_instance_SHIFTER_GENERIC_I_n59);
U1763 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_N223, A1 =>
n2131, B0 => ALU_instance_SHIFTER_GENERIC_I_N126, B1
=> n1616, C0 => ALU_instance_SHIFTER_GENERIC_I_N158,
C1 => n2133, Y => ALU_instance_SHIFTER_GENERIC_I_n60
);
U1764 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_n65, B =>
ALU_instance_SHIFTER_GENERIC_I_n66, Y =>
ALU_instance_SHIFTER_OUT_19_port);
U1765 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_N253, B =>
n2134, Y => ALU_instance_SHIFTER_GENERIC_I_n65);
U1766 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_N221, A1 =>
ALU_instance_SHIFTER_GENERIC_I_n13, B0 =>
ALU_instance_SHIFTER_GENERIC_I_N124, B1 => n2132, C0
=> ALU_instance_SHIFTER_GENERIC_I_N156, C1 => n1615,
Y => ALU_instance_SHIFTER_GENERIC_I_n66);
U1767 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_n67, B =>
ALU_instance_SHIFTER_GENERIC_I_n68, Y =>
ALU_instance_SHIFTER_OUT_18_port);
U1768 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_N252, B =>
n1614, Y => ALU_instance_SHIFTER_GENERIC_I_n67);
U1769 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_N220, A1 =>
ALU_instance_SHIFTER_GENERIC_I_n13, B0 =>
ALU_instance_SHIFTER_GENERIC_I_N123, B1 => n2132, C0
=> ALU_instance_SHIFTER_GENERIC_I_N155, C1 => n1615,
Y => ALU_instance_SHIFTER_GENERIC_I_n68);
U1770 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_n75, B =>
ALU_instance_SHIFTER_GENERIC_I_n76, Y =>
ALU_instance_SHIFTER_OUT_14_port);
U1771 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_N248, B =>
n1614, Y => ALU_instance_SHIFTER_GENERIC_I_n75);
U1772 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_N216, A1 =>
ALU_instance_SHIFTER_GENERIC_I_n13, B0 =>
ALU_instance_SHIFTER_GENERIC_I_N119, B1 => n1616, C0
=> ALU_instance_SHIFTER_GENERIC_I_N151, C1 => n1615,
Y => ALU_instance_SHIFTER_GENERIC_I_n76);
U1773 : NOR2BXL port map( AN =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_14_port,
B => n2167, Y => ALU_instance_SHIFTER_GENERIC_I_N248
);
U1774 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_n77, B =>
ALU_instance_SHIFTER_GENERIC_I_n78, Y =>
ALU_instance_SHIFTER_OUT_13_port);
U1775 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_N247, B =>
n1614, Y => ALU_instance_SHIFTER_GENERIC_I_n77);
U1776 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_N215, A1 =>
ALU_instance_SHIFTER_GENERIC_I_n13, B0 =>
ALU_instance_SHIFTER_GENERIC_I_N118, B1 => n1616, C0
=> ALU_instance_SHIFTER_GENERIC_I_N150, C1 => n1615,
Y => ALU_instance_SHIFTER_GENERIC_I_n78);
U1777 : NOR2BXL port map( AN =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_13_port,
B => n2167, Y => ALU_instance_SHIFTER_GENERIC_I_N247
);
U1778 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_n81, B =>
ALU_instance_SHIFTER_GENERIC_I_n82, Y =>
ALU_instance_SHIFTER_OUT_11_port);
U1779 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_N245, B =>
n1614, Y => ALU_instance_SHIFTER_GENERIC_I_n81);
U1780 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_N213, A1 =>
ALU_instance_SHIFTER_GENERIC_I_n13, B0 =>
ALU_instance_SHIFTER_GENERIC_I_N116, B1 => n1616, C0
=> ALU_instance_SHIFTER_GENERIC_I_N148, C1 => n1615,
Y => ALU_instance_SHIFTER_GENERIC_I_n82);
U1781 : NOR2BXL port map( AN =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_11_port,
B => n2167, Y => ALU_instance_SHIFTER_GENERIC_I_N245
);
U1782 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_n83, B =>
ALU_instance_SHIFTER_GENERIC_I_n84, Y =>
ALU_instance_SHIFTER_OUT_10_port);
U1783 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_N244, B =>
n1614, Y => ALU_instance_SHIFTER_GENERIC_I_n83);
U1784 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_N212, A1 =>
ALU_instance_SHIFTER_GENERIC_I_n13, B0 =>
ALU_instance_SHIFTER_GENERIC_I_N115, B1 => n1616, C0
=> ALU_instance_SHIFTER_GENERIC_I_N147, C1 => n1615,
Y => ALU_instance_SHIFTER_GENERIC_I_n84);
U1785 : NOR2BXL port map( AN =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_10_port,
B => n2167, Y => ALU_instance_SHIFTER_GENERIC_I_N244
);
U1786 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_n35, B =>
ALU_instance_SHIFTER_GENERIC_I_n36, Y =>
ALU_instance_SHIFTER_OUT_3_port);
U1787 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_N237, B =>
n1614, Y => ALU_instance_SHIFTER_GENERIC_I_n35);
U1788 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_N205, A1 =>
n2131, B0 => ALU_instance_SHIFTER_GENERIC_I_N108, B1
=> n1616, C0 => ALU_instance_SHIFTER_GENERIC_I_N140,
C1 => n2133, Y => ALU_instance_SHIFTER_GENERIC_I_n36
);
U1789 : NOR2XL port map( A => n2169, B =>
ALU_instance_SHIFTER_GENERIC_I_C88_n5, Y =>
ALU_instance_SHIFTER_GENERIC_I_N237);
U1790 : NOR4XL port map( A => ALU_instance_ADDER_OUT_9_port, B =>
ALU_instance_ADDER_OUT_8_port, C =>
ALU_instance_ADDER_OUT_7_port, D =>
ALU_instance_ADDER_OUT_6_port, Y =>
ALU_instance_COMPARATOR_GENERIC_I_n19);
U1791 : NOR4XL port map( A => ALU_instance_ADDER_OUT_1_port, B =>
ALU_instance_ADDER_OUT_19_port, C =>
ALU_instance_ADDER_OUT_18_port, D =>
ALU_instance_ADDER_OUT_17_port, Y =>
ALU_instance_COMPARATOR_GENERIC_I_n14);
U1792 : OAI21XL port map( A0 => n2170, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n6, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n3, Y =>
ALU_instance_SHIFTER_GENERIC_I_N208);
U1793 : OAI21XL port map( A0 => n2167, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n108, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n55, Y =>
ALU_instance_SHIFTER_GENERIC_I_N121);
U1794 : OAI21XL port map( A0 => n2169, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n56, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n55, Y =>
ALU_instance_SHIFTER_GENERIC_I_N123);
U1795 : OAI21XL port map( A0 => n2169, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n28, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n3, Y =>
ALU_instance_SHIFTER_GENERIC_I_N216);
U1796 : OAI21XL port map( A0 => n2169, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n60, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n3, Y =>
ALU_instance_SHIFTER_GENERIC_I_N212);
U1797 : OAI21XL port map( A0 => n2170, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n2, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n3, Y =>
ALU_instance_SHIFTER_GENERIC_I_N211);
U1798 : OAI21XL port map( A0 => n2169, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n35, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n55, Y =>
ALU_instance_SHIFTER_GENERIC_I_N125);
U1799 : OAI21XL port map( A0 => n2167, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n39, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n55, Y =>
ALU_instance_SHIFTER_GENERIC_I_N124);
U1800 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C48_n59, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n27);
U1801 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C48_n2, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n33);
U1802 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C48_n12, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n37);
U1803 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C48_n46, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n52);
U1804 : NOR2XL port map( A => n2170, B =>
ALU_instance_SHIFTER_GENERIC_I_C50_n33, Y =>
ALU_instance_SHIFTER_GENERIC_I_N158);
U1805 : NOR2XL port map( A => n2171, B =>
ALU_instance_SHIFTER_GENERIC_I_C50_n39, Y =>
ALU_instance_SHIFTER_GENERIC_I_N156);
U1806 : AO22XL port map( A0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_S1_3_port,
A1 => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_1_port
, B0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_S0_3_port,
B1 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_n2, Y
=> ALU_instance_ADDER_OUT_7_port);
U1807 : AO22XL port map( A0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_S1_2_port,
A1 => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_3_port
, B0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_S0_2_port,
B1 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_n2, Y
=> ALU_instance_ADDER_OUT_14_port);
U1808 : AO22XL port map( A0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_S1_2_port,
A1 => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_2_port
, B0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_S0_2_port,
B1 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_n2, Y
=> ALU_instance_ADDER_OUT_10_port);
U1809 : AO22XL port map( A0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_S1_0_port,
A1 => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_1_port
, B0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_S0_0_port,
B1 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_n2, Y
=> ALU_instance_ADDER_OUT_4_port);
U1810 : XNOR2XL port map( A => n2190, B => ALU_instance_INTERNAL_B_4_port, Y
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_S1_0_port
);
U1811 : XOR2XL port map( A => ALU_instance_INTERNAL_B_4_port, B => n2190, Y
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_S0_0_port
);
U1812 : AO22XL port map( A0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_S1_3_port,
A1 => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_2_port
, B0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_S0_3_port,
B1 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_n2, Y
=> ALU_instance_ADDER_OUT_11_port);
U1813 : AO22XL port map( A0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_S1_1_port,
A1 => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_2_port
, B0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_S0_1_port,
B1 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_n2, Y
=> ALU_instance_ADDER_OUT_9_port);
U1814 : AO22XL port map( A0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_S1_1_port,
A1 => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_3_port
, B0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_S0_1_port,
B1 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_n2, Y
=> ALU_instance_ADDER_OUT_13_port);
U1815 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_n11, B =>
ALU_instance_SHIFTER_GENERIC_I_n12, Y =>
ALU_instance_SHIFTER_OUT_9_port);
U1816 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_N243, B =>
n1614, Y => ALU_instance_SHIFTER_GENERIC_I_n11);
U1817 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_N211, A1 =>
ALU_instance_SHIFTER_GENERIC_I_n13, B0 =>
ALU_instance_SHIFTER_GENERIC_I_N114, B1 => n2132, C0
=> ALU_instance_SHIFTER_GENERIC_I_N146, C1 => n1615,
Y => ALU_instance_SHIFTER_GENERIC_I_n12);
U1818 : NOR2BXL port map( AN =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_9_port,
B => n2167, Y => ALU_instance_SHIFTER_GENERIC_I_N243
);
U1819 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_n25, B =>
ALU_instance_SHIFTER_GENERIC_I_n26, Y =>
ALU_instance_SHIFTER_OUT_8_port);
U1820 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_N242, B =>
n1614, Y => ALU_instance_SHIFTER_GENERIC_I_n25);
U1821 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_N210, A1 =>
ALU_instance_SHIFTER_GENERIC_I_n13, B0 =>
ALU_instance_SHIFTER_GENERIC_I_N113, B1 => n2132, C0
=> ALU_instance_SHIFTER_GENERIC_I_N145, C1 => n1615,
Y => ALU_instance_SHIFTER_GENERIC_I_n26);
U1822 : NOR2BXL port map( AN =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_8_port,
B => n2167, Y => ALU_instance_SHIFTER_GENERIC_I_N242
);
U1823 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_n27, B =>
ALU_instance_SHIFTER_GENERIC_I_n28, Y =>
ALU_instance_SHIFTER_OUT_7_port);
U1824 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_N241, B =>
n1614, Y => ALU_instance_SHIFTER_GENERIC_I_n27);
U1825 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_N209, A1 =>
ALU_instance_SHIFTER_GENERIC_I_n13, B0 =>
ALU_instance_SHIFTER_GENERIC_I_N112, B1 => n2132, C0
=> ALU_instance_SHIFTER_GENERIC_I_N144, C1 => n1615,
Y => ALU_instance_SHIFTER_GENERIC_I_n28);
U1826 : NOR2XL port map( A => n2169, B =>
ALU_instance_SHIFTER_GENERIC_I_C88_n1, Y =>
ALU_instance_SHIFTER_GENERIC_I_N241);
U1827 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_n29, B =>
ALU_instance_SHIFTER_GENERIC_I_n30, Y =>
ALU_instance_SHIFTER_OUT_6_port);
U1828 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_N240, B =>
n1614, Y => ALU_instance_SHIFTER_GENERIC_I_n29);
U1829 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_N208, A1 =>
n2131, B0 => ALU_instance_SHIFTER_GENERIC_I_N111, B1
=> n2132, C0 => ALU_instance_SHIFTER_GENERIC_I_N143,
C1 => n2133, Y => ALU_instance_SHIFTER_GENERIC_I_n30
);
U1830 : NOR2XL port map( A => n2169, B =>
ALU_instance_SHIFTER_GENERIC_I_C88_n2, Y =>
ALU_instance_SHIFTER_GENERIC_I_N240);
U1831 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_n31, B =>
ALU_instance_SHIFTER_GENERIC_I_n32, Y =>
ALU_instance_SHIFTER_OUT_5_port);
U1832 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_N239, B =>
n1614, Y => ALU_instance_SHIFTER_GENERIC_I_n31);
U1833 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_N207, A1 =>
n2131, B0 => ALU_instance_SHIFTER_GENERIC_I_N110, B1
=> n2132, C0 => ALU_instance_SHIFTER_GENERIC_I_N142,
C1 => n2133, Y => ALU_instance_SHIFTER_GENERIC_I_n32
);
U1834 : NOR2XL port map( A => n2169, B =>
ALU_instance_SHIFTER_GENERIC_I_C88_n3, Y =>
ALU_instance_SHIFTER_GENERIC_I_N239);
U1835 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_n33, B =>
ALU_instance_SHIFTER_GENERIC_I_n34, Y =>
ALU_instance_SHIFTER_OUT_4_port);
U1836 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_N238, B =>
n1614, Y => ALU_instance_SHIFTER_GENERIC_I_n33);
U1837 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_N206, A1 =>
ALU_instance_SHIFTER_GENERIC_I_n13, B0 =>
ALU_instance_SHIFTER_GENERIC_I_N109, B1 => n2132, C0
=> ALU_instance_SHIFTER_GENERIC_I_N141, C1 => n1615,
Y => ALU_instance_SHIFTER_GENERIC_I_n34);
U1838 : NOR2XL port map( A => n2169, B =>
ALU_instance_SHIFTER_GENERIC_I_C88_n4, Y =>
ALU_instance_SHIFTER_GENERIC_I_N238);
U1839 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_n61, B =>
ALU_instance_SHIFTER_GENERIC_I_n62, Y =>
ALU_instance_SHIFTER_OUT_20_port);
U1840 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_N254, B =>
n2134, Y => ALU_instance_SHIFTER_GENERIC_I_n61);
U1841 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_N222, A1 =>
ALU_instance_SHIFTER_GENERIC_I_n13, B0 =>
ALU_instance_SHIFTER_GENERIC_I_N125, B1 => n2132, C0
=> ALU_instance_SHIFTER_GENERIC_I_N157, C1 => n1615,
Y => ALU_instance_SHIFTER_GENERIC_I_n62);
U1842 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_n69, B =>
ALU_instance_SHIFTER_GENERIC_I_n70, Y =>
ALU_instance_SHIFTER_OUT_17_port);
U1843 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_N251, B =>
n1614, Y => ALU_instance_SHIFTER_GENERIC_I_n69);
U1844 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_N219, A1 =>
ALU_instance_SHIFTER_GENERIC_I_n13, B0 =>
ALU_instance_SHIFTER_GENERIC_I_N122, B1 => n2132, C0
=> ALU_instance_SHIFTER_GENERIC_I_N154, C1 => n1615,
Y => ALU_instance_SHIFTER_GENERIC_I_n70);
U1845 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_n71, B =>
ALU_instance_SHIFTER_GENERIC_I_n72, Y =>
ALU_instance_SHIFTER_OUT_16_port);
U1846 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_N250, B =>
n1614, Y => ALU_instance_SHIFTER_GENERIC_I_n71);
U1847 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_N218, A1 =>
ALU_instance_SHIFTER_GENERIC_I_n13, B0 =>
ALU_instance_SHIFTER_GENERIC_I_N121, B1 => n1616, C0
=> ALU_instance_SHIFTER_GENERIC_I_N153, C1 => n1615,
Y => ALU_instance_SHIFTER_GENERIC_I_n72);
U1848 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_n73, B =>
ALU_instance_SHIFTER_GENERIC_I_n74, Y =>
ALU_instance_SHIFTER_OUT_15_port);
U1849 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_N249, B =>
n1614, Y => ALU_instance_SHIFTER_GENERIC_I_n73);
U1850 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_N217, A1 =>
ALU_instance_SHIFTER_GENERIC_I_n13, B0 =>
ALU_instance_SHIFTER_GENERIC_I_N120, B1 => n2132, C0
=> ALU_instance_SHIFTER_GENERIC_I_N152, C1 => n1615,
Y => ALU_instance_SHIFTER_GENERIC_I_n74);
U1851 : NOR2BXL port map( AN =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_15_port,
B => n2167, Y => ALU_instance_SHIFTER_GENERIC_I_N249
);
U1852 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_n79, B =>
ALU_instance_SHIFTER_GENERIC_I_n80, Y =>
ALU_instance_SHIFTER_OUT_12_port);
U1853 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_N246, B =>
n1614, Y => ALU_instance_SHIFTER_GENERIC_I_n79);
U1854 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_N214, A1 =>
ALU_instance_SHIFTER_GENERIC_I_n13, B0 =>
ALU_instance_SHIFTER_GENERIC_I_N117, B1 => n1616, C0
=> ALU_instance_SHIFTER_GENERIC_I_N149, C1 => n1615,
Y => ALU_instance_SHIFTER_GENERIC_I_n80);
U1855 : NOR2BXL port map( AN =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_12_port,
B => n2167, Y => ALU_instance_SHIFTER_GENERIC_I_N246
);
U1856 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_n41, B =>
ALU_instance_SHIFTER_GENERIC_I_n42, Y =>
ALU_instance_SHIFTER_OUT_2_port);
U1857 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_N236, B =>
n1614, Y => ALU_instance_SHIFTER_GENERIC_I_n41);
U1858 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_N204, A1 =>
n2131, B0 => ALU_instance_SHIFTER_GENERIC_I_N107, B1
=> n2132, C0 => ALU_instance_SHIFTER_GENERIC_I_N139,
C1 => n2133, Y => ALU_instance_SHIFTER_GENERIC_I_n42
);
U1859 : NOR2XL port map( A => n2170, B =>
ALU_instance_SHIFTER_GENERIC_I_C88_n6, Y =>
ALU_instance_SHIFTER_GENERIC_I_N236);
U1860 : NOR2XL port map( A => n2170, B =>
ALU_instance_SHIFTER_GENERIC_I_C50_n79, Y =>
ALU_instance_SHIFTER_GENERIC_I_N154);
U1861 : INVXL port map( A => n2124, Y => n2123);
U1862 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C50_n45, Y =>
n2124);
U1863 : INVXL port map( A => BOOTH_instance_n160, Y => BOOTH_instance_n146);
U1864 : CLKBUFX1 port map( A => ALU_instance_SHIFTER_GENERIC_I_C50_n48, Y =>
n2125);
U1865 : CLKBUFX1 port map( A => ALU_instance_SHIFTER_GENERIC_I_C86_n25, Y =>
n2130);
U1866 : CLKBUFX1 port map( A => ALU_instance_SHIFTER_GENERIC_I_C50_n49, Y =>
n2126);
U1867 : CLKBUFX1 port map( A => ALU_instance_SHIFTER_GENERIC_I_C86_n20, Y =>
n2127);
U1868 : CLKBUFX1 port map( A => ALU_instance_SHIFTER_GENERIC_I_C50_n43, Y =>
n2122);
U1869 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C50_n66, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n90);
U1870 : CLKBUFX1 port map( A => ALU_instance_SHIFTER_GENERIC_I_C86_n20, Y =>
n2128);
U1871 : CLKBUFX1 port map( A => ALU_instance_SHIFTER_GENERIC_I_C86_n22, Y =>
n2129);
U1872 : NOR2XL port map( A => n2172, B => n2113, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n132);
U1873 : AND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_C48_n152, B =>
n2160, Y => ALU_instance_SHIFTER_GENERIC_I_C48_n10);
U1874 : AND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_C86_n133, B =>
n2160, Y => ALU_instance_SHIFTER_GENERIC_I_C86_n14);
U1875 : NOR2XL port map( A => n2172, B => n1697, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n98);
U1876 : NOR3XL port map( A => ALU_instance_SHIFTER_GENERIC_I_C50_n66, B =>
n2167, C => n2174, Y =>
ALU_instance_SHIFTER_GENERIC_I_N164);
U1877 : NAND2XL port map( A => n1595, B => n2172, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n11);
U1878 : NAND2XL port map( A => n1598, B => n2172, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n38);
U1879 : NAND2XL port map( A => n1598, B => n2172, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n38);
U1880 : OAI21XL port map( A0 => n2170, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n5, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n3, Y =>
ALU_instance_SHIFTER_GENERIC_I_N209);
U1881 : OAI21XL port map( A0 => n2170, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n7, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n3, Y =>
ALU_instance_SHIFTER_GENERIC_I_N207);
U1882 : OAI21XL port map( A0 => n2170, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n4, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n3, Y =>
ALU_instance_SHIFTER_GENERIC_I_N210);
U1883 : OAI21XL port map( A0 => n2169, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n19, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n55, Y =>
ALU_instance_SHIFTER_GENERIC_I_N128);
U1884 : OAI21XL port map( A0 => n2170, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n68, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n55, Y =>
ALU_instance_SHIFTER_GENERIC_I_N131);
U1885 : OAI21XL port map( A0 => n2169, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n4, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n55, Y =>
ALU_instance_SHIFTER_GENERIC_I_N130);
U1886 : OAI21XL port map( A0 => n2169, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n91, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n55, Y =>
ALU_instance_SHIFTER_GENERIC_I_N122);
U1887 : OAI21XL port map( A0 => n2169, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n13, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n55, Y =>
ALU_instance_SHIFTER_GENERIC_I_N129);
U1888 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_C48_n73, B =>
n2160, Y => ALU_instance_SHIFTER_GENERIC_I_C48_n81);
U1889 : OAI21XL port map( A0 => n2170, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n35, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n3, Y =>
ALU_instance_SHIFTER_GENERIC_I_N204);
U1890 : OAI21XL port map( A0 => n2170, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n12, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n3, Y =>
ALU_instance_SHIFTER_GENERIC_I_N217);
U1891 : OAI21XL port map( A0 => n2170, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n37, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n3, Y =>
ALU_instance_SHIFTER_GENERIC_I_N215);
U1892 : OAI21XL port map( A0 => n2170, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n45, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n3, Y =>
ALU_instance_SHIFTER_GENERIC_I_N214);
U1893 : OAI21XL port map( A0 => n2170, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n53, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n3, Y =>
ALU_instance_SHIFTER_GENERIC_I_N213);
U1894 : OA21XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n110, A1
=> n1697, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n112, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n8);
U1895 : OA21XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n118, A1
=> n1697, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n112, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n9);
U1896 : OA21XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n69, A1 =>
n1697, B0 => ALU_instance_SHIFTER_GENERIC_I_C86_n112
, Y => ALU_instance_SHIFTER_GENERIC_I_C86_n115);
U1897 : OAI21XL port map( A0 => n2169, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n54, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n55, Y =>
ALU_instance_SHIFTER_GENERIC_I_N135);
U1898 : OAI21XL port map( A0 => n2169, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n65, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n55, Y =>
ALU_instance_SHIFTER_GENERIC_I_N134);
U1899 : OAI21XL port map( A0 => n2169, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n66, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n55, Y =>
ALU_instance_SHIFTER_GENERIC_I_N133);
U1900 : OAI21XL port map( A0 => n2169, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n67, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n55, Y =>
ALU_instance_SHIFTER_GENERIC_I_N132);
U1901 : OAI21XL port map( A0 => n2169, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n25, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n55, Y =>
ALU_instance_SHIFTER_GENERIC_I_N127);
U1902 : OAI21XL port map( A0 => n2169, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n31, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n55, Y =>
ALU_instance_SHIFTER_GENERIC_I_N126);
U1903 : NOR2XL port map( A => n2170, B =>
ALU_instance_SHIFTER_GENERIC_I_C50_n21, Y =>
ALU_instance_SHIFTER_GENERIC_I_N160);
U1904 : NOR2XL port map( A => n2171, B =>
ALU_instance_SHIFTER_GENERIC_I_C50_n27, Y =>
ALU_instance_SHIFTER_GENERIC_I_N159);
U1905 : NOR2XL port map( A => n2171, B =>
ALU_instance_SHIFTER_GENERIC_I_C50_n36, Y =>
ALU_instance_SHIFTER_GENERIC_I_N157);
U1906 : NAND2XL port map( A => n2160, B =>
ALU_instance_SHIFTER_GENERIC_I_C86_n84, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n71);
U1907 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C86_n91, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n118);
U1908 : NAND2XL port map( A => n2160, B =>
ALU_instance_SHIFTER_GENERIC_I_C50_n153, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n122);
U1909 : NOR2XL port map( A => n2171, B =>
ALU_instance_SHIFTER_GENERIC_I_C50_n56, Y =>
ALU_instance_SHIFTER_GENERIC_I_N155);
U1910 : NOR2XL port map( A => n2171, B =>
ALU_instance_SHIFTER_GENERIC_I_C50_n94, Y =>
ALU_instance_SHIFTER_GENERIC_I_N153);
U1911 : NOR2XL port map( A => n2170, B =>
ALU_instance_SHIFTER_GENERIC_I_C50_n14, Y =>
ALU_instance_SHIFTER_GENERIC_I_N161);
U1912 : NOR2XL port map( A => n2170, B =>
ALU_instance_SHIFTER_GENERIC_I_C50_n4, Y =>
ALU_instance_SHIFTER_GENERIC_I_N162);
U1913 : NOR2XL port map( A => n2170, B =>
ALU_instance_SHIFTER_GENERIC_I_C50_n67, Y =>
ALU_instance_SHIFTER_GENERIC_I_N163);
U1914 : NAND2XL port map( A => n2160, B => n2174, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n107);
U1915 : CLKBUFX1 port map( A => ALU_instance_n6, Y => n2139);
U1916 : OR2XL port map( A => n1602, B => n2174, Y => n1697);
U1917 : NAND2XL port map( A => n2160, B => n2174, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n139);
U1918 : CLKBUFX1 port map( A => ALU_instance_SHIFTER_GENERIC_I_n13, Y =>
n2131);
U1919 : NOR2XL port map( A => n2169, B =>
ALU_instance_SHIFTER_GENERIC_I_C88_n8, Y =>
ALU_instance_SHIFTER_GENERIC_I_N234);
U1920 : CLKBUFX1 port map( A => ALU_instance_n5, Y => n2138);
U1921 : CLKBUFX1 port map( A => EX_LOGIC_CW_3_port, Y => n2197);
U1922 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C86_n105, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n69);
U1923 : AND2XL port map( A => n2175, B => n2172, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n152);
U1924 : AND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_C50_n54, B =>
ALU_instance_SHIFTER_GENERIC_I_C86_n16, Y =>
ALU_instance_SHIFTER_GENERIC_I_N168);
U1925 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C48_n80, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n104);
U1926 : CLKBUFX1 port map( A => n1614, Y => n2134);
U1927 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C88_n1, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_7_port);
U1928 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C88_n2, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_6_port);
U1929 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C88_n3, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_5_port);
U1930 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C88_n4, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_4_port);
U1931 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C88_n5, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_3_port);
U1932 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C88_n6, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_2_port);
U1933 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C88_n7, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_1_port);
U1934 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C88_n8, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_4_0_port);
U1935 : CLKBUFX1 port map( A => n1646, Y => n2148);
U1936 : INVXL port map( A => n1619, Y => n1309);
U1937 : INVXL port map( A => n1199, Y => n1421);
U1938 : CLKBUFX1 port map( A => n1208, Y => n2150);
U1939 : OAI221XL port map( A0 => BOOTH_instance_n155, A1 =>
BOOTH_instance_n307, B0 => BOOTH_instance_n308, B1
=> n1721, C0 => BOOTH_instance_n309, Y =>
BOOTH_instance_n295);
U1940 : AOI22XL port map( A0 => BOOTH_instance_n310, A1 =>
BOOTH_instance_n149, B0 => n2193, B1 =>
BOOTH_instance_n282, Y => BOOTH_instance_n309);
U1941 : OAI221XL port map( A0 => BOOTH_instance_n186, A1 => n2192, B0 =>
BOOTH_instance_n280, B1 => n1606, C0 =>
BOOTH_instance_n313, Y => BOOTH_instance_n306);
U1942 : AOI22XL port map( A0 => n2193, A1 => BOOTH_instance_n188, B0 =>
BOOTH_instance_n176, B1 => BOOTH_instance_n310, Y =>
BOOTH_instance_n313);
U1943 : OAI221XL port map( A0 => BOOTH_instance_n166, A1 =>
BOOTH_instance_n307, B0 => BOOTH_instance_n308, B1
=> BOOTH_instance_n158, C0 => BOOTH_instance_n314, Y
=> BOOTH_instance_n302);
U1944 : OAI21XL port map( A0 => BOOTH_instance_n150, A1 =>
BOOTH_instance_n168, B0 => n2111, Y =>
BOOTH_instance_n314);
U1945 : NOR3XL port map( A => n2183, B => n2185, C => BOOTH_instance_n453, Y
=> BOOTH_instance_n452);
U1946 : AOI21XL port map( A0 => BOOTH_instance_n158, A1 =>
BOOTH_instance_n166, B0 => BOOTH_instance_n316, Y =>
BOOTH_instance_n304);
U1947 : NOR4XL port map( A => ALU_instance_ADDER_OUT_27_port, B =>
ALU_instance_ADDER_OUT_26_port, C =>
ALU_instance_ADDER_OUT_25_port, D =>
ALU_instance_ADDER_OUT_24_port, Y =>
ALU_instance_COMPARATOR_GENERIC_I_n16);
U1948 : NOR4XL port map( A => ALU_instance_ADDER_OUT_30_port, B =>
ALU_instance_ADDER_OUT_2_port, C =>
ALU_instance_ADDER_OUT_29_port, D =>
ALU_instance_ADDER_OUT_28_port, Y =>
ALU_instance_COMPARATOR_GENERIC_I_n17);
U1949 : NAND2XL port map( A => BOOTH_instance_n348, B => BOOTH_instance_n345
, Y => BOOTH_instance_n328);
U1950 : NAND2XL port map( A => BOOTH_instance_n395, B => BOOTH_instance_n372
, Y => BOOTH_instance_n373);
U1951 : NAND2XL port map( A => BOOTH_instance_n371, B => BOOTH_instance_n346
, Y => BOOTH_instance_n349);
U1952 : AOI2B1XL port map( A1N => BOOTH_instance_n301, A0 =>
BOOTH_instance_n302, B0 => BOOTH_instance_n303, Y =>
BOOTH_instance_n293);
U1953 : AOI21XL port map( A0 => BOOTH_instance_n304, A1 =>
BOOTH_instance_n305, B0 => BOOTH_instance_n306, Y =>
BOOTH_instance_n301);
U1954 : NAND2XL port map( A => BOOTH_instance_n322, B => BOOTH_instance_n318
, Y => BOOTH_instance_n186);
U1955 : AO22XL port map( A0 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_C1,
A1 => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_5_port
, B0 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_C0,
B1 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_n2, Y
=> ALU_instance_CARRY_SELECT_ADDER_I_CARRY_6_port);
U1956 : AO22XL port map( A0 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_C1,
A1 => n2137, B0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_C0, B1 =>
EX_ADD_SUB, Y =>
ALU_instance_CARRY_SELECT_ADDER_I_CARRY_1_port);
U1957 : AO22XL port map( A0 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_C1,
A1 => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_4_port
, B0 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_C0,
B1 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_n2, Y
=> ALU_instance_CARRY_SELECT_ADDER_I_CARRY_5_port);
U1958 : AO22XL port map( A0 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_C1,
A1 => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_3_port
, B0 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_C0,
B1 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_n2, Y
=> ALU_instance_CARRY_SELECT_ADDER_I_CARRY_4_port);
U1959 : AO22XL port map( A0 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_C1,
A1 => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_6_port
, B0 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_C0,
B1 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_n2, Y
=> ALU_instance_CARRY_SELECT_ADDER_I_CARRY_7_port);
U1960 : AOI22XL port map( A0 => BOOTH_instance_n352, A1 => n2193, B0 =>
BOOTH_instance_n353, B1 => BOOTH_instance_n310, Y =>
BOOTH_instance_n368);
U1961 : AOI22XL port map( A0 => BOOTH_instance_n352, A1 => n2190, B0 =>
BOOTH_instance_n353, B1 => BOOTH_instance_n272, Y =>
BOOTH_instance_n366);
U1962 : AOI22XL port map( A0 => BOOTH_instance_n400, A1 => n2183, B0 =>
BOOTH_instance_n401, B1 => BOOTH_instance_n212, Y =>
BOOTH_instance_n413);
U1963 : AOI21XL port map( A0 => BOOTH_instance_n398, A1 =>
BOOTH_instance_n397, B0 => BOOTH_instance_n316, Y =>
BOOTH_instance_partial_products_7_4_port);
U1964 : AOI21XL port map( A0 => BOOTH_instance_n323, A1 =>
BOOTH_instance_n328, B0 => BOOTH_instance_n316, Y =>
BOOTH_instance_decoded_5_10_port);
U1965 : AOI21XL port map( A0 => BOOTH_instance_n374, A1 =>
BOOTH_instance_n373, B0 => BOOTH_instance_n316, Y =>
BOOTH_instance_decoded_3_6_port);
U1966 : AOI21XL port map( A0 => BOOTH_instance_n350, A1 =>
BOOTH_instance_n349, B0 => BOOTH_instance_n316, Y =>
BOOTH_instance_partial_products_4_8_port);
U1967 : NAND2XL port map( A => BOOTH_instance_n449, B => n1608, Y =>
BOOTH_instance_n450);
U1968 : NAND2XL port map( A => BOOTH_instance_n457, B =>
ALU_instance_SHIFTER_GENERIC_I_C50_n46, Y =>
BOOTH_instance_n458);
U1969 : NOR2XL port map( A => n2185, B => BOOTH_instance_n453, Y =>
BOOTH_instance_n454);
U1970 : AO22XL port map( A0 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_C1,
A1 => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_7_port
, B0 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_C0,
B1 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_n2, Y
=> ALU_instance_OVERFLOW);
U1971 : OAI31XL port map( A0 => BOOTH_instance_n145, A1 =>
BOOTH_instance_n146, A2 => BOOTH_instance_n147, B0
=> BOOTH_instance_n148, Y =>
BOOTH_instance_partial_products_5_31_port);
U1972 : OAI21XL port map( A0 => BOOTH_instance_n149, A1 =>
BOOTH_instance_n150, B0 => BOOTH_instance_n151, Y =>
BOOTH_instance_n148);
U1973 : INVXL port map( A => BOOTH_instance_n355, Y => BOOTH_instance_n352);
U1974 : INVXL port map( A => BOOTH_instance_n382, Y => BOOTH_instance_n376);
U1975 : NAND3XL port map( A => ALU_instance_SHIFTER_GENERIC_I_C50_n46, B =>
BOOTH_instance_n260, C => BOOTH_instance_n457, Y =>
BOOTH_instance_n456);
U1976 : NAND2XL port map( A => BOOTH_instance_n460, B => n2192, Y =>
BOOTH_instance_n459);
U1977 : NAND2XL port map( A => BOOTH_instance_n452, B => n2182, Y =>
BOOTH_instance_n451);
U1978 : INVXL port map( A => BOOTH_instance_n175, Y => BOOTH_instance_n188);
U1979 : NAND2XL port map( A => BOOTH_instance_n455, B => n2188, Y =>
BOOTH_instance_n453);
U1980 : OAI21XL port map( A0 => BOOTH_instance_n376, A1 =>
BOOTH_instance_n377, B0 =>
ALU_instance_SHIFTER_GENERIC_I_N202, Y =>
BOOTH_instance_n380);
U1981 : OAI21XL port map( A0 => BOOTH_instance_n326, A1 =>
BOOTH_instance_n327, B0 => n2112, Y =>
BOOTH_instance_n344);
U1982 : XOR2XL port map( A => n2136, B => n2159, Y =>
ALU_instance_INTERNAL_B_1_port);
U1983 : XOR2XL port map( A => n2135, B => n2160, Y =>
ALU_instance_INTERNAL_B_2_port);
U1984 : AO22XL port map( A0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_S1_1_port,
A1 => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_7_port
, B0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_S0_1_port,
B1 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_n2, Y
=> ALU_instance_ADDER_OUT_29_port);
U1985 : AO22XL port map( A0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_S1_1_port,
A1 => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_6_port
, B0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_S0_1_port,
B1 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_n2, Y
=> ALU_instance_ADDER_OUT_25_port);
U1986 : AO22XL port map( A0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_S1_2_port,
A1 => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_6_port
, B0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_S0_2_port,
B1 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_n2, Y
=> ALU_instance_ADDER_OUT_26_port);
U1987 : AO22XL port map( A0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_S1_2_port,
A1 => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_7_port
, B0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_S0_2_port,
B1 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_n2, Y
=> ALU_instance_ADDER_OUT_30_port);
U1988 : AO22XL port map( A0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_S1_3_port,
A1 => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_6_port
, B0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_S0_3_port,
B1 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_n2, Y
=> ALU_instance_ADDER_OUT_27_port);
U1989 : AO22XL port map( A0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_S1_3_port,
A1 => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_7_port
, B0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_S0_3_port,
B1 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_n2, Y
=> ALU_instance_ADDER_OUT_31_port);
U1990 : AND3XL port map( A => BOOTH_instance_n449, B => n1608, C => n1670, Y
=> BOOTH_instance_n448);
U1991 : INVXL port map( A => BOOTH_instance_n158, Y => BOOTH_instance_n149);
U1992 : OR3XL port map( A => n2174, B => n2167, C => BOOTH_instance_n396, Y
=> n1698);
U1993 : OR3XL port map( A => n2158, B => n690, C => n1600, Y => n1699);
U1994 : INVXL port map( A => BOOTH_instance_n290, Y => BOOTH_instance_n310);
U1995 : CLKINVX1 port map( A => n2186, Y => n2185);
U1996 : NAND3XL port map( A => n1555, B => n1557, C => n1551, Y => n1574);
U1997 : CLKINVX1 port map( A => n2182, Y => n2181);
U1998 : CLKINVX1 port map( A => n1607, Y => n2189);
U1999 : AND3XL port map( A => BOOTH_instance_n306, B => BOOTH_instance_n305,
C => BOOTH_instance_n304, Y => BOOTH_instance_n303);
U2000 : OAI2BB1XL port map( A0N => BOOTH_instance_n283, A1N =>
BOOTH_instance_n284, B0 => BOOTH_instance_n285, Y =>
BOOTH_instance_n275);
U2001 : OAI21XL port map( A0 => BOOTH_instance_n284, A1 =>
BOOTH_instance_n283, B0 => BOOTH_instance_n286, Y =>
BOOTH_instance_n285);
U2002 : NAND2XL port map( A => ALU_instance_n21, B => ALU_instance_n22, Y =>
EX_ALU_OUT_0_port);
U2003 : AOI22XL port map( A0 => ALU_instance_LOGIC_OUT_0_port, A1 =>
ALU_instance_n6, B0 => ALU_instance_ADDER_OUT_0_port
, B1 => n1599, Y => ALU_instance_n21);
U2004 : AO2B2XL port map( B0 => BOOTH_instance_n263, B1 =>
BOOTH_instance_n264, A0 => BOOTH_instance_n265, A1N
=> BOOTH_instance_n266, Y => BOOTH_instance_n255);
U2005 : NOR2XL port map( A => BOOTH_instance_n264, B => BOOTH_instance_n263,
Y => BOOTH_instance_n266);
U2006 : AO2B2XL port map( B0 => BOOTH_instance_n253, B1 =>
BOOTH_instance_n254, A0 => BOOTH_instance_n255, A1N
=> BOOTH_instance_n256, Y => BOOTH_instance_n245);
U2007 : NOR2XL port map( A => BOOTH_instance_n254, B => BOOTH_instance_n253,
Y => BOOTH_instance_n256);
U2008 : AO2B2XL port map( B0 => BOOTH_instance_n243, B1 =>
BOOTH_instance_n244, A0 => BOOTH_instance_n245, A1N
=> BOOTH_instance_n246, Y => BOOTH_instance_n235);
U2009 : NOR2XL port map( A => BOOTH_instance_n244, B => BOOTH_instance_n243,
Y => BOOTH_instance_n246);
U2010 : AO2B2XL port map( B0 => BOOTH_instance_n233, B1 =>
BOOTH_instance_n234, A0 => BOOTH_instance_n235, A1N
=> BOOTH_instance_n236, Y => BOOTH_instance_n225);
U2011 : NOR2XL port map( A => BOOTH_instance_n234, B => BOOTH_instance_n233,
Y => BOOTH_instance_n236);
U2012 : AO2B2XL port map( B0 => BOOTH_instance_n213, B1 =>
BOOTH_instance_n214, A0 => BOOTH_instance_n215, A1N
=> BOOTH_instance_n216, Y => BOOTH_instance_n205);
U2013 : NOR2XL port map( A => BOOTH_instance_n214, B => BOOTH_instance_n213,
Y => BOOTH_instance_n216);
U2014 : AO2B2XL port map( B0 => BOOTH_instance_n273, B1 =>
BOOTH_instance_n274, A0 => BOOTH_instance_n275, A1N
=> BOOTH_instance_n276, Y => BOOTH_instance_n265);
U2015 : NOR2XL port map( A => BOOTH_instance_n274, B => BOOTH_instance_n273,
Y => BOOTH_instance_n276);
U2016 : CLKINVX1 port map( A => n2180, Y => n2179);
U2017 : CLKINVX1 port map( A => n2188, Y => n2187);
U2018 : CLKINVX1 port map( A => n2191, Y => n2190);
U2019 : OAI221XL port map( A0 => n2192, A1 => BOOTH_instance_n421, B0 =>
BOOTH_instance_n280, B1 => BOOTH_instance_n422, C0
=> BOOTH_instance_n429, Y =>
BOOTH_instance_decoded_1_5_port);
U2020 : AOI22XL port map( A0 => BOOTH_instance_n424, A1 => n2193, B0 =>
BOOTH_instance_n425, B1 => BOOTH_instance_n310, Y =>
BOOTH_instance_n429);
U2021 : OAI221XL port map( A0 => n2191, A1 => BOOTH_instance_n421, B0 =>
BOOTH_instance_n299, B1 => BOOTH_instance_n422, C0
=> BOOTH_instance_n428, Y =>
BOOTH_instance_decoded_1_6_port);
U2022 : AOI22XL port map( A0 => BOOTH_instance_n424, A1 => N4721, B0 =>
BOOTH_instance_n425, B1 => BOOTH_instance_n292, Y =>
BOOTH_instance_n428);
U2023 : OAI222XL port map( A0 => BOOTH_instance_n259, A1 => n2127, B0 =>
BOOTH_instance_n249, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n22, C0 => n1607,
C1 => BOOTH_instance_n447, Y =>
BOOTH_instance_N216_port);
U2024 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n46, A1
=> BOOTH_instance_n421, B0 => BOOTH_instance_n269,
B1 => BOOTH_instance_n422, C0 => BOOTH_instance_n427
, Y => BOOTH_instance_decoded_1_7_port);
U2025 : AOI22XL port map( A0 => BOOTH_instance_n424, A1 => n2190, B0 =>
BOOTH_instance_n425, B1 => BOOTH_instance_n272, Y =>
BOOTH_instance_n427);
U2026 : XOR2XL port map( A => BOOTH_instance_decoded_3_6_port, B =>
BOOTH_instance_decoded_2_6_port, Y =>
BOOTH_instance_partial_products_7_6_port);
U2027 : OAI221XL port map( A0 => n2192, A1 => BOOTH_instance_n373, B0 =>
BOOTH_instance_n280, B1 => BOOTH_instance_n374, C0
=> BOOTH_instance_n375, Y =>
BOOTH_instance_decoded_3_9_port);
U2028 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n46, A1
=> BOOTH_instance_n397, B0 => BOOTH_instance_n269,
B1 => BOOTH_instance_n398, C0 => BOOTH_instance_n399
, Y => BOOTH_instance_decoded_2_9_port);
U2029 : AOI22XL port map( A0 => BOOTH_instance_n376, A1 => n2193, B0 =>
BOOTH_instance_n377, B1 => BOOTH_instance_n310, Y =>
BOOTH_instance_n375);
U2030 : XOR2XL port map( A => BOOTH_instance_partial_products_4_8_port, B =>
BOOTH_instance_partial_products_3_8_port, Y =>
BOOTH_instance_partial_products_7_8_port);
U2031 : OAI221XL port map( A0 => n2191, A1 => BOOTH_instance_n373, B0 =>
BOOTH_instance_n299, B1 => BOOTH_instance_n374, C0
=> BOOTH_instance_n394, Y =>
BOOTH_instance_decoded_3_10_port);
U2032 : OAI221XL port map( A0 => BOOTH_instance_n260, A1 =>
BOOTH_instance_n397, B0 => BOOTH_instance_n259, B1
=> BOOTH_instance_n398, C0 => BOOTH_instance_n418, Y
=> BOOTH_instance_decoded_2_10_port);
U2033 : AOI22XL port map( A0 => BOOTH_instance_n376, A1 => N4721, B0 =>
BOOTH_instance_n377, B1 => BOOTH_instance_n292, Y =>
BOOTH_instance_n394);
U2034 : OAI221XL port map( A0 => n2186, A1 => BOOTH_instance_n421, B0 =>
BOOTH_instance_n229, B1 => BOOTH_instance_n422, C0
=> BOOTH_instance_n441, Y =>
BOOTH_instance_decoded_1_11_port);
U2035 : OAI222XL port map( A0 => BOOTH_instance_n219, A1 => n2127, B0 =>
BOOTH_instance_n209, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n22, C0 => n2182,
C1 => BOOTH_instance_n447, Y => BOOTH_instance_N220)
;
U2036 : AOI22XL port map( A0 => BOOTH_instance_n424, A1 => n2187, B0 =>
BOOTH_instance_n425, B1 => BOOTH_instance_n232, Y =>
BOOTH_instance_n441);
U2037 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n46, A1
=> BOOTH_instance_n373, B0 => BOOTH_instance_n269,
B1 => BOOTH_instance_n374, C0 => BOOTH_instance_n393
, Y => BOOTH_instance_decoded_3_11_port);
U2038 : OAI221XL port map( A0 => n1607, A1 => BOOTH_instance_n397, B0 =>
BOOTH_instance_n249, B1 => BOOTH_instance_n398, C0
=> BOOTH_instance_n417, Y =>
BOOTH_instance_decoded_2_11_port);
U2039 : AOI22XL port map( A0 => BOOTH_instance_n376, A1 => n2190, B0 =>
BOOTH_instance_n377, B1 => BOOTH_instance_n272, Y =>
BOOTH_instance_n393);
U2040 : XOR2XL port map( A => BOOTH_instance_decoded_5_10_port, B =>
BOOTH_instance_decoded_4_10_port, Y =>
BOOTH_instance_partial_products_4_10_port);
U2041 : OAI221XL port map( A0 => n2182, A1 => BOOTH_instance_n421, B0 =>
BOOTH_instance_n209, B1 => BOOTH_instance_n422, C0
=> BOOTH_instance_n439, Y =>
BOOTH_instance_decoded_1_13_port);
U2042 : OAI222XL port map( A0 => BOOTH_instance_n199, A1 => n2127, B0 =>
BOOTH_instance_n189, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n22, C0 => n1608,
C1 => BOOTH_instance_n447, Y =>
BOOTH_instance_N222_port);
U2043 : AOI22XL port map( A0 => BOOTH_instance_n424, A1 => n2183, B0 =>
BOOTH_instance_n425, B1 => BOOTH_instance_n212, Y =>
BOOTH_instance_n439);
U2044 : OAI221XL port map( A0 => n2191, A1 => BOOTH_instance_n349, B0 =>
BOOTH_instance_n299, B1 => BOOTH_instance_n350, C0
=> BOOTH_instance_n367, Y =>
BOOTH_instance_decoded_4_12_port);
U2045 : INVXL port map( A => BOOTH_instance_n342, Y =>
BOOTH_instance_decoded_5_12_port);
U2046 : AOI22XL port map( A0 => BOOTH_instance_n352, A1 => N4721, B0 =>
BOOTH_instance_n353, B1 => BOOTH_instance_n292, Y =>
BOOTH_instance_n367);
U2047 : OAI221XL port map( A0 => n2180, A1 => BOOTH_instance_n421, B0 =>
BOOTH_instance_n199, B1 => BOOTH_instance_n422, C0
=> BOOTH_instance_n438, Y =>
BOOTH_instance_decoded_1_14_port);
U2048 : OAI222XL port map( A0 => BOOTH_instance_n189, A1 => n2127, B0 =>
BOOTH_instance_n177, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n22, C0 => n1670,
C1 => BOOTH_instance_n447, Y =>
BOOTH_instance_N223_port);
U2049 : AOI22XL port map( A0 => BOOTH_instance_n424, A1 => n2181, B0 =>
BOOTH_instance_n425, B1 => BOOTH_instance_n202, Y =>
BOOTH_instance_n438);
U2050 : OAI221XL port map( A0 => n2192, A1 => BOOTH_instance_n328, B0 =>
BOOTH_instance_n280, B1 => BOOTH_instance_n323, C0
=> BOOTH_instance_n341, Y =>
BOOTH_instance_decoded_5_13_port);
U2051 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n46, A1
=> BOOTH_instance_n349, B0 => BOOTH_instance_n269,
B1 => BOOTH_instance_n350, C0 => BOOTH_instance_n366
, Y => BOOTH_instance_decoded_4_13_port);
U2052 : AOI22XL port map( A0 => BOOTH_instance_n326, A1 => n2193, B0 =>
BOOTH_instance_n327, B1 => BOOTH_instance_n310, Y =>
BOOTH_instance_n341);
U2053 : OAI221XL port map( A0 => n1608, A1 => BOOTH_instance_n421, B0 =>
BOOTH_instance_n189, B1 => BOOTH_instance_n422, C0
=> BOOTH_instance_n437, Y =>
BOOTH_instance_decoded_1_15_port);
U2054 : OAI222XL port map( A0 => BOOTH_instance_n177, A1 => n2127, B0 =>
n1609, B1 => ALU_instance_SHIFTER_GENERIC_I_C86_n22,
C0 => BOOTH_instance_n156, C1 => BOOTH_instance_n447
, Y => BOOTH_instance_N224_port);
U2055 : AOI22XL port map( A0 => BOOTH_instance_n424, A1 => n2179, B0 =>
BOOTH_instance_n425, B1 => BOOTH_instance_n192, Y =>
BOOTH_instance_n437);
U2056 : XOR2XL port map( A => BOOTH_instance_partial_products_6_12_port, B
=> BOOTH_instance_partial_products_5_12_port, Y =>
BOOTH_instance_partial_products_8_12_port);
U2057 : OAI221XL port map( A0 => n2191, A1 => BOOTH_instance_n328, B0 =>
BOOTH_instance_n299, B1 => BOOTH_instance_n323, C0
=> BOOTH_instance_n340, Y =>
BOOTH_instance_decoded_5_14_port);
U2058 : OAI221XL port map( A0 => BOOTH_instance_n260, A1 =>
BOOTH_instance_n349, B0 => BOOTH_instance_n259, B1
=> BOOTH_instance_n350, C0 => BOOTH_instance_n365, Y
=> BOOTH_instance_decoded_4_14_port);
U2059 : AOI22XL port map( A0 => BOOTH_instance_n326, A1 => N4721, B0 =>
BOOTH_instance_n327, B1 => BOOTH_instance_n292, Y =>
BOOTH_instance_n340);
U2060 : OAI22XL port map( A0 => n1609, A1 => n2127, B0 =>
BOOTH_instance_n157, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n22, Y =>
BOOTH_instance_N225_port);
U2061 : OAI221XL port map( A0 => n1670, A1 => BOOTH_instance_n421, B0 =>
BOOTH_instance_n177, B1 => BOOTH_instance_n422, C0
=> BOOTH_instance_n436, Y =>
BOOTH_instance_decoded_1_16_port);
U2062 : AOI22XL port map( A0 => BOOTH_instance_n424, A1 => n2178, B0 =>
BOOTH_instance_n425, B1 => BOOTH_instance_n180, Y =>
BOOTH_instance_n436);
U2063 : XOR2XL port map( A => BOOTH_instance_n305, B => BOOTH_instance_n304,
Y => BOOTH_instance_partial_products_5_14_port);
U2064 : OAI221XL port map( A0 => n2186, A1 => BOOTH_instance_n373, B0 =>
BOOTH_instance_n229, B1 => BOOTH_instance_n374, C0
=> BOOTH_instance_n389, Y =>
BOOTH_instance_decoded_3_15_port);
U2065 : OAI221XL port map( A0 => n2182, A1 => BOOTH_instance_n397, B0 =>
BOOTH_instance_n209, B1 => BOOTH_instance_n398, C0
=> BOOTH_instance_n413, Y =>
BOOTH_instance_decoded_2_15_port);
U2066 : AOI22XL port map( A0 => BOOTH_instance_n376, A1 => n2187, B0 =>
BOOTH_instance_n377, B1 => BOOTH_instance_n232, Y =>
BOOTH_instance_n389);
U2067 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n46, A1
=> BOOTH_instance_n328, B0 => BOOTH_instance_n269,
B1 => BOOTH_instance_n323, C0 => BOOTH_instance_n339
, Y => BOOTH_instance_decoded_5_15_port);
U2068 : OAI221XL port map( A0 => n1607, A1 => BOOTH_instance_n349, B0 =>
BOOTH_instance_n249, B1 => BOOTH_instance_n350, C0
=> BOOTH_instance_n364, Y =>
BOOTH_instance_decoded_4_15_port);
U2069 : AOI22XL port map( A0 => BOOTH_instance_n326, A1 => n2190, B0 =>
BOOTH_instance_n327, B1 => BOOTH_instance_n272, Y =>
BOOTH_instance_n339);
U2070 : OAI221XL port map( A0 => BOOTH_instance_n156, A1 =>
BOOTH_instance_n421, B0 => n1609, B1 =>
BOOTH_instance_n422, C0 => BOOTH_instance_n435, Y =>
BOOTH_instance_decoded_1_17_port);
U2071 : AOI22XL port map( A0 => BOOTH_instance_n424, A1 => n2177, B0 =>
BOOTH_instance_n425, B1 => BOOTH_instance_n169, Y =>
BOOTH_instance_n435);
U2072 : XOR2XL port map( A => BOOTH_instance_n302, B => BOOTH_instance_n311,
Y => BOOTH_instance_partial_products_5_15_port);
U2073 : AOI2B1XL port map( A1N => BOOTH_instance_n306, A0 =>
BOOTH_instance_n312, B0 => BOOTH_instance_n303, Y =>
BOOTH_instance_n311);
U2074 : NAND2XL port map( A => BOOTH_instance_n304, B => BOOTH_instance_n305
, Y => BOOTH_instance_n312);
U2075 : OAI222XL port map( A0 => n1609, A1 => n1699, B0 =>
BOOTH_instance_n156, B1 => BOOTH_instance_n434, C0
=> BOOTH_instance_n157, C1 => BOOTH_instance_n422, Y
=> BOOTH_instance_decoded_1_18_port);
U2076 : OAI221XL port map( A0 => n2182, A1 => BOOTH_instance_n373, B0 =>
BOOTH_instance_n209, B1 => BOOTH_instance_n374, C0
=> BOOTH_instance_n387, Y =>
BOOTH_instance_decoded_3_17_port);
U2077 : OAI221XL port map( A0 => n1608, A1 => BOOTH_instance_n397, B0 =>
BOOTH_instance_n189, B1 => BOOTH_instance_n398, C0
=> BOOTH_instance_n411, Y =>
BOOTH_instance_decoded_2_17_port);
U2078 : AOI22XL port map( A0 => BOOTH_instance_n376, A1 => n2183, B0 =>
BOOTH_instance_n377, B1 => BOOTH_instance_n212, Y =>
BOOTH_instance_n387);
U2079 : XNOR2XL port map( A => BOOTH_instance_n287, B => BOOTH_instance_n284
, Y => BOOTH_instance_partial_products_5_17_port);
U2080 : XNOR2XL port map( A => BOOTH_instance_n286, B => BOOTH_instance_n283
, Y => BOOTH_instance_n287);
U2081 : OAI221XL port map( A0 => n2180, A1 => BOOTH_instance_n373, B0 =>
BOOTH_instance_n199, B1 => BOOTH_instance_n374, C0
=> BOOTH_instance_n386, Y =>
BOOTH_instance_decoded_3_18_port);
U2082 : OAI221XL port map( A0 => n1670, A1 => BOOTH_instance_n397, B0 =>
BOOTH_instance_n177, B1 => BOOTH_instance_n398, C0
=> BOOTH_instance_n410, Y =>
BOOTH_instance_decoded_2_18_port);
U2083 : AOI22XL port map( A0 => BOOTH_instance_n376, A1 => n2181, B0 =>
BOOTH_instance_n377, B1 => BOOTH_instance_n202, Y =>
BOOTH_instance_n386);
U2084 : NOR2XL port map( A => BOOTH_instance_n315, B => n2192, Y =>
BOOTH_instance_decoded_8_19_port);
U2085 : XNOR2XL port map( A => BOOTH_instance_n277, B => BOOTH_instance_n274
, Y => BOOTH_instance_partial_products_5_18_port);
U2086 : XNOR2XL port map( A => BOOTH_instance_n275, B => BOOTH_instance_n273
, Y => BOOTH_instance_n277);
U2087 : OAI221XL port map( A0 => n1608, A1 => BOOTH_instance_n373, B0 =>
BOOTH_instance_n189, B1 => BOOTH_instance_n374, C0
=> BOOTH_instance_n385, Y =>
BOOTH_instance_decoded_3_19_port);
U2088 : OAI221XL port map( A0 => BOOTH_instance_n156, A1 =>
BOOTH_instance_n397, B0 => n1609, B1 =>
BOOTH_instance_n398, C0 => BOOTH_instance_n409, Y =>
BOOTH_instance_decoded_2_19_port);
U2089 : AOI22XL port map( A0 => BOOTH_instance_n376, A1 => n2179, B0 =>
BOOTH_instance_n377, B1 => BOOTH_instance_n192, Y =>
BOOTH_instance_n385);
U2090 : OAI221XL port map( A0 => n2186, A1 => BOOTH_instance_n328, B0 =>
BOOTH_instance_n229, B1 => BOOTH_instance_n323, C0
=> BOOTH_instance_n335, Y =>
BOOTH_instance_decoded_5_19_port);
U2091 : OAI221XL port map( A0 => n2182, A1 => BOOTH_instance_n349, B0 =>
BOOTH_instance_n209, B1 => BOOTH_instance_n350, C0
=> BOOTH_instance_n360, Y =>
BOOTH_instance_decoded_4_19_port);
U2092 : AOI22XL port map( A0 => BOOTH_instance_n326, A1 => n2187, B0 =>
BOOTH_instance_n327, B1 => BOOTH_instance_n232, Y =>
BOOTH_instance_n335);
U2093 : NOR2XL port map( A => BOOTH_instance_n315, B => n2191, Y =>
BOOTH_instance_decoded_8_20_port);
U2094 : XNOR2XL port map( A => BOOTH_instance_n267, B => BOOTH_instance_n264
, Y => BOOTH_instance_partial_products_5_19_port);
U2095 : XNOR2XL port map( A => BOOTH_instance_n265, B => BOOTH_instance_n263
, Y => BOOTH_instance_n267);
U2096 : OAI222XL port map( A0 => n1609, A1 => n1698, B0 =>
BOOTH_instance_n156, B1 => BOOTH_instance_n408, C0
=> BOOTH_instance_n157, C1 => BOOTH_instance_n398, Y
=> BOOTH_instance_decoded_2_20_port);
U2097 : OAI221XL port map( A0 => n1670, A1 => BOOTH_instance_n373, B0 =>
BOOTH_instance_n177, B1 => BOOTH_instance_n374, C0
=> BOOTH_instance_n384, Y =>
BOOTH_instance_decoded_3_20_port);
U2098 : AOI22XL port map( A0 => BOOTH_instance_n376, A1 => n2178, B0 =>
BOOTH_instance_n377, B1 => BOOTH_instance_n180, Y =>
BOOTH_instance_n384);
U2099 : NOR2XL port map( A => BOOTH_instance_n315, B =>
ALU_instance_SHIFTER_GENERIC_I_C50_n46, Y =>
BOOTH_instance_decoded_8_21_port);
U2100 : XNOR2XL port map( A => BOOTH_instance_n257, B => BOOTH_instance_n254
, Y => BOOTH_instance_partial_products_5_20_port);
U2101 : XNOR2XL port map( A => BOOTH_instance_n255, B => BOOTH_instance_n253
, Y => BOOTH_instance_n257);
U2102 : OAI221XL port map( A0 => BOOTH_instance_n156, A1 =>
BOOTH_instance_n373, B0 => n1609, B1 =>
BOOTH_instance_n374, C0 => BOOTH_instance_n383, Y =>
BOOTH_instance_decoded_3_21_port);
U2103 : AOI22XL port map( A0 => BOOTH_instance_n376, A1 => n2177, B0 =>
BOOTH_instance_n377, B1 => BOOTH_instance_n169, Y =>
BOOTH_instance_n383);
U2104 : OAI221XL port map( A0 => n2182, A1 => BOOTH_instance_n328, B0 =>
BOOTH_instance_n209, B1 => BOOTH_instance_n323, C0
=> BOOTH_instance_n333, Y =>
BOOTH_instance_decoded_5_21_port);
U2105 : OAI221XL port map( A0 => n1608, A1 => BOOTH_instance_n349, B0 =>
BOOTH_instance_n189, B1 => BOOTH_instance_n350, C0
=> BOOTH_instance_n358, Y =>
BOOTH_instance_decoded_4_21_port);
U2106 : AOI22XL port map( A0 => BOOTH_instance_n326, A1 => n2183, B0 =>
BOOTH_instance_n327, B1 => BOOTH_instance_n212, Y =>
BOOTH_instance_n333);
U2107 : NOR2XL port map( A => BOOTH_instance_n315, B => BOOTH_instance_n260,
Y => BOOTH_instance_decoded_8_22_port);
U2108 : XNOR2XL port map( A => BOOTH_instance_n247, B => BOOTH_instance_n244
, Y => BOOTH_instance_partial_products_5_21_port);
U2109 : XNOR2XL port map( A => BOOTH_instance_n245, B => BOOTH_instance_n243
, Y => BOOTH_instance_n247);
U2110 : OAI222XL port map( A0 => n1609, A1 => n1707, B0 =>
BOOTH_instance_n156, B1 => BOOTH_instance_n382, C0
=> BOOTH_instance_n157, C1 => BOOTH_instance_n374, Y
=> BOOTH_instance_decoded_3_22_port);
U2111 : OAI221XL port map( A0 => n2180, A1 => BOOTH_instance_n328, B0 =>
BOOTH_instance_n199, B1 => BOOTH_instance_n323, C0
=> BOOTH_instance_n332, Y =>
BOOTH_instance_decoded_5_22_port);
U2112 : OAI221XL port map( A0 => n1670, A1 => BOOTH_instance_n349, B0 =>
BOOTH_instance_n177, B1 => BOOTH_instance_n350, C0
=> BOOTH_instance_n357, Y =>
BOOTH_instance_decoded_4_22_port);
U2113 : AOI22XL port map( A0 => BOOTH_instance_n326, A1 => n2181, B0 =>
BOOTH_instance_n327, B1 => BOOTH_instance_n202, Y =>
BOOTH_instance_n332);
U2114 : NOR2XL port map( A => BOOTH_instance_n315, B => n1607, Y =>
BOOTH_instance_decoded_8_23_port);
U2115 : XNOR2XL port map( A => BOOTH_instance_n237, B => BOOTH_instance_n234
, Y => BOOTH_instance_partial_products_5_22_port);
U2116 : XNOR2XL port map( A => BOOTH_instance_n235, B => BOOTH_instance_n233
, Y => BOOTH_instance_n237);
U2117 : OAI221XL port map( A0 => n1608, A1 => BOOTH_instance_n328, B0 =>
BOOTH_instance_n189, B1 => BOOTH_instance_n323, C0
=> BOOTH_instance_n331, Y =>
BOOTH_instance_decoded_5_23_port);
U2118 : OAI221XL port map( A0 => BOOTH_instance_n156, A1 =>
BOOTH_instance_n349, B0 => n1609, B1 =>
BOOTH_instance_n350, C0 => BOOTH_instance_n356, Y =>
BOOTH_instance_decoded_4_23_port);
U2119 : AOI22XL port map( A0 => BOOTH_instance_n326, A1 => n2179, B0 =>
BOOTH_instance_n327, B1 => BOOTH_instance_n192, Y =>
BOOTH_instance_n331);
U2120 : NOR2XL port map( A => BOOTH_instance_n315, B => n2188, Y =>
BOOTH_instance_decoded_8_24_port);
U2121 : OAI222XL port map( A0 => BOOTH_instance_n156, A1 =>
BOOTH_instance_n355, B0 => BOOTH_instance_n157, B1
=> BOOTH_instance_n350, C0 => n1609, C1 => n1706, Y
=> BOOTH_instance_decoded_4_24_port);
U2122 : OAI221XL port map( A0 => n1670, A1 => BOOTH_instance_n328, B0 =>
BOOTH_instance_n177, B1 => BOOTH_instance_n323, C0
=> BOOTH_instance_n330, Y =>
BOOTH_instance_decoded_5_24_port);
U2123 : AOI22XL port map( A0 => BOOTH_instance_n326, A1 => n2178, B0 =>
BOOTH_instance_n327, B1 => BOOTH_instance_n180, Y =>
BOOTH_instance_n330);
U2124 : NOR2XL port map( A => BOOTH_instance_n315, B => n2186, Y =>
BOOTH_instance_decoded_8_25_port);
U2125 : XNOR2XL port map( A => BOOTH_instance_n217, B => BOOTH_instance_n214
, Y => BOOTH_instance_partial_products_5_24_port);
U2126 : XNOR2XL port map( A => BOOTH_instance_n215, B => BOOTH_instance_n213
, Y => BOOTH_instance_n217);
U2127 : OAI221XL port map( A0 => BOOTH_instance_n156, A1 =>
BOOTH_instance_n328, B0 => n1609, B1 =>
BOOTH_instance_n323, C0 => BOOTH_instance_n329, Y =>
BOOTH_instance_decoded_5_25_port);
U2128 : AOI22XL port map( A0 => BOOTH_instance_n326, A1 => n2177, B0 =>
BOOTH_instance_n327, B1 => BOOTH_instance_n169, Y =>
BOOTH_instance_n329);
U2129 : OAI222XL port map( A0 => n1609, A1 => n1703, B0 =>
BOOTH_instance_n156, B1 => n1705, C0 =>
BOOTH_instance_n157, C1 => BOOTH_instance_n323, Y =>
BOOTH_instance_decoded_5_26_port);
U2130 : NOR2XL port map( A => BOOTH_instance_n315, B => n2182, Y =>
BOOTH_instance_decoded_8_27_port);
U2131 : XNOR2XL port map( A => BOOTH_instance_n197, B => BOOTH_instance_n194
, Y => BOOTH_instance_partial_products_5_26_port);
U2132 : XNOR2XL port map( A => BOOTH_instance_n195, B => BOOTH_instance_n193
, Y => BOOTH_instance_n197);
U2133 : NOR2XL port map( A => BOOTH_instance_n315, B => n2180, Y =>
BOOTH_instance_decoded_8_28_port);
U2134 : NOR2XL port map( A => BOOTH_instance_n315, B => n1608, Y =>
BOOTH_instance_decoded_8_29_port);
U2135 : AND2XL port map( A => BOOTH_instance_N211_port, B =>
BOOTH_instance_decoded_1_2_port, Y =>
BOOTH_instance_add_7_root_add_53_G7_carry_3_port);
U2136 : OAI221XL port map( A0 => BOOTH_instance_n307, A1 =>
BOOTH_instance_n397, B0 => BOOTH_instance_n308, B1
=> BOOTH_instance_n398, C0 => BOOTH_instance_n406, Y
=> BOOTH_instance_partial_products_7_5_port);
U2137 : AND2XL port map( A => BOOTH_instance_partial_products_7_4_port, B =>
BOOTH_instance_partial_products_8_4_port, Y =>
BOOTH_instance_add_0_root_add_53_G7_carry_5_port);
U2138 : OAI21XL port map( A0 => BOOTH_instance_n400, A1 =>
BOOTH_instance_n401, B0 =>
ALU_instance_SHIFTER_GENERIC_I_N202, Y =>
BOOTH_instance_n406);
U2139 : OAI221XL port map( A0 => BOOTH_instance_n307, A1 =>
BOOTH_instance_n373, B0 => BOOTH_instance_n308, B1
=> BOOTH_instance_n374, C0 => BOOTH_instance_n380, Y
=> BOOTH_instance_decoded_3_7_port);
U2140 : OAI221XL port map( A0 => BOOTH_instance_n307, A1 =>
BOOTH_instance_n349, B0 => BOOTH_instance_n308, B1
=> BOOTH_instance_n350, C0 => BOOTH_instance_n351, Y
=> BOOTH_instance_partial_products_4_9_port);
U2141 : AND2XL port map( A => BOOTH_instance_partial_products_3_8_port, B =>
BOOTH_instance_partial_products_4_8_port, Y =>
BOOTH_instance_add_2_root_add_53_G7_carry_9_port);
U2142 : OAI21XL port map( A0 => BOOTH_instance_n352, A1 =>
BOOTH_instance_n353, B0 => n2112, Y =>
BOOTH_instance_n351);
U2143 : OAI221XL port map( A0 => BOOTH_instance_n307, A1 =>
BOOTH_instance_n328, B0 => BOOTH_instance_n308, B1
=> BOOTH_instance_n323, C0 => BOOTH_instance_n344, Y
=> BOOTH_instance_decoded_5_11_port);
U2144 : OAI221XL port map( A0 => n2192, A1 => BOOTH_instance_n349, B0 =>
BOOTH_instance_n280, B1 => BOOTH_instance_n350, C0
=> BOOTH_instance_n368, Y =>
BOOTH_instance_decoded_4_11_port);
U2145 : AND2XL port map( A => BOOTH_instance_decoded_4_10_port, B =>
BOOTH_instance_decoded_5_10_port, Y =>
BOOTH_instance_add_5_root_add_53_G7_carry_11_port);
U2146 : OAI221XL port map( A0 => BOOTH_instance_n307, A1 =>
BOOTH_instance_n186, B0 => BOOTH_instance_n308, B1
=> n1606, C0 => BOOTH_instance_n321, Y =>
BOOTH_instance_partial_products_5_13_port);
U2147 : AND2XL port map( A => BOOTH_instance_partial_products_5_12_port, B
=> BOOTH_instance_partial_products_6_12_port, Y =>
BOOTH_instance_add_1_root_add_53_G7_carry_13_port);
U2148 : OAI21XL port map( A0 => BOOTH_instance_n188, A1 =>
BOOTH_instance_n176, B0 => n2111, Y =>
BOOTH_instance_n321);
U2149 : NOR2XL port map( A => BOOTH_instance_n315, B => BOOTH_instance_n307,
Y => BOOTH_instance_decoded_8_17_port);
U2150 : AND2XL port map( A => BOOTH_instance_decoded_8_16_port, B =>
BOOTH_instance_partial_products_2_16_port, Y =>
BOOTH_instance_add_3_root_add_53_G7_carry_17_port);
U2151 : NOR2XL port map( A => BOOTH_instance_n315, B => n1670, Y =>
BOOTH_instance_decoded_8_30_port);
U2152 : XOR2XL port map( A => n2135, B => n2171, Y =>
ALU_instance_INTERNAL_B_4_port);
U2153 : AO22XL port map( A0 => EX_MULT_OUT_31_port, A1 => n2145, B0 =>
EX_ALU_OUT_31_port, B1 => n2144, Y => N4891);
U2154 : OAI2BB1XL port map( A0N => ALU_instance_ADDER_OUT_31_port, A1N =>
n1599, B0 => ALU_instance_n39, Y =>
EX_ALU_OUT_31_port);
U2155 : AOI22XL port map( A0 => ALU_instance_SHIFTER_OUT_31_port, A1 =>
ALU_instance_n5, B0 =>
ALU_instance_LOGIC_OUT_31_port, B1 =>
ALU_instance_n6, Y => ALU_instance_n39);
U2156 : AOI221XL port map( A0 => n2124, A1 => n2179, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n52, B1 => n2178,
C0 => ALU_instance_SHIFTER_GENERIC_I_C48_n148, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n59);
U2157 : AO22XL port map( A0 => n2181, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n48, B0 => n2183,
B1 => ALU_instance_SHIFTER_GENERIC_I_C50_n49, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n148);
U2158 : AOI221XL port map( A0 => n2124, A1 => n2181, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n52, B1 => n2179,
C0 => ALU_instance_SHIFTER_GENERIC_I_C48_n94, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n2);
U2159 : AO22XL port map( A0 => n2183, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n48, B0 => n2185,
B1 => ALU_instance_SHIFTER_GENERIC_I_C50_n49, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n94);
U2160 : AOI221XL port map( A0 => n2124, A1 => n2183, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n52, B1 => n2181,
C0 => ALU_instance_SHIFTER_GENERIC_I_C48_n151, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n12);
U2161 : AO22XL port map( A0 => n2185, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n48, B0 => n2187,
B1 => ALU_instance_SHIFTER_GENERIC_I_C50_n49, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n151);
U2162 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n76, A1
=> n1595, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n77, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n74, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n78, C1 => n1597,
Y => ALU_instance_SHIFTER_GENERIC_I_C50_n27);
U2163 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n68, A1
=> n1595, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n70, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n74, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n11, C1 => n1597,
Y => ALU_instance_SHIFTER_GENERIC_I_C50_n33);
U2164 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n25, A1
=> n1597, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n75, B1 => n1595,
C0 => ALU_instance_SHIFTER_GENERIC_I_C50_n90, C1 =>
n2175, Y => ALU_instance_SHIFTER_GENERIC_I_C50_n39);
U2165 : OAI222XL port map( A0 => n1609, A1 => n1704, B0 =>
BOOTH_instance_n156, B1 => BOOTH_instance_n175, C0
=> BOOTH_instance_n157, C1 => n1606, Y =>
BOOTH_instance_n171);
U2166 : AOI222XL port map( A0 => n2112, A1 =>
ALU_instance_SHIFTER_GENERIC_I_n13, B0 =>
ALU_instance_SHIFTER_GENERIC_I_N105, B1 => n2132, C0
=> ALU_instance_SHIFTER_GENERIC_I_N137, C1 => n1615,
Y => ALU_instance_SHIFTER_GENERIC_I_n86);
U2167 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n35, A1
=> ALU_instance_SHIFTER_GENERIC_I_C50_n38, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n94, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C50_n150, Y =>
ALU_instance_SHIFTER_GENERIC_I_N137);
U2168 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n34, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n38, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n108, B1 => n2172
, C0 => ALU_instance_SHIFTER_GENERIC_I_C48_n149, Y
=> ALU_instance_SHIFTER_GENERIC_I_N105);
U2169 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n10, A1
=> ALU_instance_SHIFTER_GENERIC_I_C50_n16, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n16, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n151, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n8, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n19, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n150);
U2170 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_n39, B =>
ALU_instance_SHIFTER_GENERIC_I_n40, Y =>
ALU_instance_SHIFTER_OUT_30_port);
U2171 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_N264, B =>
n2134, Y => ALU_instance_SHIFTER_GENERIC_I_n39);
U2172 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_N232, A1 =>
n2131, B0 => ALU_instance_SHIFTER_GENERIC_I_N135, B1
=> n1616, C0 => ALU_instance_SHIFTER_GENERIC_I_N167,
C1 => n2133, Y => ALU_instance_SHIFTER_GENERIC_I_n40
);
U2173 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_n43, B =>
ALU_instance_SHIFTER_GENERIC_I_n44, Y =>
ALU_instance_SHIFTER_OUT_29_port);
U2174 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_N263, B =>
n2134, Y => ALU_instance_SHIFTER_GENERIC_I_n43);
U2175 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_N231, A1 =>
n2131, B0 => ALU_instance_SHIFTER_GENERIC_I_N134, B1
=> n1616, C0 => ALU_instance_SHIFTER_GENERIC_I_N166,
C1 => n2133, Y => ALU_instance_SHIFTER_GENERIC_I_n44
);
U2176 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_n45, B =>
ALU_instance_SHIFTER_GENERIC_I_n46, Y =>
ALU_instance_SHIFTER_OUT_28_port);
U2177 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_N262, B =>
n2134, Y => ALU_instance_SHIFTER_GENERIC_I_n45);
U2178 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_N230, A1 =>
n2131, B0 => ALU_instance_SHIFTER_GENERIC_I_N133, B1
=> n1616, C0 => ALU_instance_SHIFTER_GENERIC_I_N165,
C1 => n2133, Y => ALU_instance_SHIFTER_GENERIC_I_n46
);
U2179 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_n63, B =>
ALU_instance_SHIFTER_GENERIC_I_n64, Y =>
ALU_instance_SHIFTER_OUT_1_port);
U2180 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_N235, B =>
n1614, Y => ALU_instance_SHIFTER_GENERIC_I_n63);
U2181 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_N203, A1 =>
ALU_instance_SHIFTER_GENERIC_I_n13, B0 =>
ALU_instance_SHIFTER_GENERIC_I_N106, B1 => n1616, C0
=> ALU_instance_SHIFTER_GENERIC_I_N138, C1 => n1615,
Y => ALU_instance_SHIFTER_GENERIC_I_n64);
U2182 : NOR2XL port map( A => n2169, B =>
ALU_instance_SHIFTER_GENERIC_I_C88_n7, Y =>
ALU_instance_SHIFTER_GENERIC_I_N235);
U2183 : OAI221XL port map( A0 => n2127, A1 => n2180, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n46, B1 => n2182,
C0 => ALU_instance_SHIFTER_GENERIC_I_C86_n148, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n62);
U2184 : AOI22XL port map( A0 => n2178, A1 => n2130, B0 => n2177, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n50, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n148);
U2185 : OAI221XL port map( A0 => n2127, A1 => n1607, B0 => n2129, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n155, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n156, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n76);
U2186 : AOI22XL port map( A0 => n2187, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n25, B0 => n2185,
B1 => ALU_instance_SHIFTER_GENERIC_I_C48_n50, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n156);
U2187 : OAI221XL port map( A0 => n2128, A1 => n2186, B0 => n2129, B1 =>
n2188, C0 => ALU_instance_SHIFTER_GENERIC_I_C86_n172
, Y => ALU_instance_SHIFTER_GENERIC_I_C86_n90);
U2188 : AOI22XL port map( A0 => n2183, A1 => n2130, B0 => n2181, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n50, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n172);
U2189 : OAI221XL port map( A0 => n2128, A1 => n2188, B0 => n2129, B1 =>
n1607, C0 => ALU_instance_SHIFTER_GENERIC_I_C86_n178
, Y => ALU_instance_SHIFTER_GENERIC_I_C86_n97);
U2190 : AOI22XL port map( A0 => n2185, A1 => n2130, B0 => n2183, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n50, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n178);
U2191 : OAI221XL port map( A0 => n2127, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n155, B0 => n2129
, B1 => ALU_instance_SHIFTER_GENERIC_I_C86_n166, C0
=> ALU_instance_SHIFTER_GENERIC_I_C86_n167, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n83);
U2192 : AOI22XL port map( A0 => n2189, A1 => n2130, B0 => n2187, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n50, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n167);
U2193 : AOI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n102, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n103, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n83, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n104, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n105, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n56);
U2194 : AO22XL port map( A0 => n1598, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n84, B0 => n1597,
B1 => ALU_instance_SHIFTER_GENERIC_I_C48_n29, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n105);
U2195 : AOI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n69, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n103, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n71, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n104, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n106, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n91);
U2196 : AO22XL port map( A0 => n1598, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n11, B0 => n1597,
B1 => ALU_instance_SHIFTER_GENERIC_I_C48_n9, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n106);
U2197 : AOI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n69, A1
=> n1598, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n71, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n75, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n73, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n4);
U2198 : AOI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n82, A1
=> n1595, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n83, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n75, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n84, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n4);
U2199 : AOI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n91, A1
=> n1595, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n92, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n75, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n84, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n5);
U2200 : AOI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n98, A1
=> n1595, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n99, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n75, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n84, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n6);
U2201 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C86_n100, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n98);
U2202 : AOI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n105, A1
=> n1595, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n74, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n75, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n84, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n7);
U2203 : AOI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n17, A1
=> n1598, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n16, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n75, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n157, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n108);
U2204 : OAI2BB2XL port map( B0 => ALU_instance_SHIFTER_GENERIC_I_C48_n107,
B1 => ALU_instance_SHIFTER_GENERIC_I_C48_n89, A0N =>
ALU_instance_SHIFTER_GENERIC_I_C48_n75, A1N =>
ALU_instance_SHIFTER_GENERIC_I_C48_n104, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n157);
U2205 : AOI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n70, A1
=> ALU_instance_SHIFTER_GENERIC_I_C50_n92, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n68, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n74, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n93, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n79);
U2206 : AO22XL port map( A0 => n1595, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n11, B0 => n1597,
B1 => ALU_instance_SHIFTER_GENERIC_I_C50_n9, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n93);
U2207 : AOI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n78, A1
=> n1595, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n31, B1 => n1597,
C0 => ALU_instance_SHIFTER_GENERIC_I_C50_n91, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n56);
U2208 : AO22XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n92, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n77, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n74, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n76, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n91);
U2209 : AOI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n18, A1
=> n1595, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n17, B1 => n1597,
C0 => ALU_instance_SHIFTER_GENERIC_I_C50_n157, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n94);
U2210 : AO22XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n92, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n65, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n74, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n72, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n157);
U2211 : OAI221XL port map( A0 => BOOTH_instance_n158, A1 =>
BOOTH_instance_n269, B0 => BOOTH_instance_n166, B1
=> ALU_instance_SHIFTER_GENERIC_I_C50_n46, C0 =>
BOOTH_instance_n271, Y => BOOTH_instance_n263);
U2212 : AOI22XL port map( A0 => n2190, A1 => BOOTH_instance_n168, B0 =>
BOOTH_instance_n272, B1 => BOOTH_instance_n150, Y =>
BOOTH_instance_n271);
U2213 : OAI221XL port map( A0 => BOOTH_instance_n158, A1 =>
BOOTH_instance_n239, B0 => BOOTH_instance_n166, B1
=> n2188, C0 => BOOTH_instance_n241, Y =>
BOOTH_instance_n233);
U2214 : AOI22XL port map( A0 => n2189, A1 => BOOTH_instance_n168, B0 =>
BOOTH_instance_n242, B1 => BOOTH_instance_n150, Y =>
BOOTH_instance_n241);
U2215 : OAI221XL port map( A0 => BOOTH_instance_n158, A1 =>
BOOTH_instance_n209, B0 => BOOTH_instance_n166, B1
=> n2182, C0 => BOOTH_instance_n211, Y =>
BOOTH_instance_n203);
U2216 : AOI22XL port map( A0 => n2183, A1 => BOOTH_instance_n168, B0 =>
BOOTH_instance_n212, B1 => BOOTH_instance_n150, Y =>
BOOTH_instance_n211);
U2217 : OAI221XL port map( A0 => BOOTH_instance_n158, A1 =>
BOOTH_instance_n177, B0 => n1670, B1 =>
BOOTH_instance_n166, C0 => BOOTH_instance_n179, Y =>
BOOTH_instance_n170);
U2218 : AOI22XL port map( A0 => n2178, A1 => BOOTH_instance_n168, B0 =>
BOOTH_instance_n180, B1 => BOOTH_instance_n150, Y =>
BOOTH_instance_n179);
U2219 : OAI221XL port map( A0 => BOOTH_instance_n155, A1 => n2192, B0 =>
n1721, B1 => BOOTH_instance_n280, C0 =>
BOOTH_instance_n281, Y => BOOTH_instance_n273);
U2220 : AOI22XL port map( A0 => BOOTH_instance_n272, A1 =>
BOOTH_instance_n149, B0 => n2190, B1 =>
BOOTH_instance_n282, Y => BOOTH_instance_n281);
U2221 : OAI221XL port map( A0 => BOOTH_instance_n186, A1 => n2188, B0 =>
n1606, B1 => BOOTH_instance_n239, C0 =>
BOOTH_instance_n258, Y => BOOTH_instance_n254);
U2222 : AOI22XL port map( A0 => n2189, A1 => BOOTH_instance_n188, B0 =>
BOOTH_instance_n242, B1 => BOOTH_instance_n176, Y =>
BOOTH_instance_n258);
U2223 : OAI221XL port map( A0 => BOOTH_instance_n186, A1 => n2186, B0 =>
n1606, B1 => BOOTH_instance_n229, C0 =>
BOOTH_instance_n248, Y => BOOTH_instance_n244);
U2224 : AOI22XL port map( A0 => n2187, A1 => BOOTH_instance_n188, B0 =>
BOOTH_instance_n232, B1 => BOOTH_instance_n176, Y =>
BOOTH_instance_n248);
U2225 : OAI221XL port map( A0 => BOOTH_instance_n186, A1 => n2182, B0 =>
n1606, B1 => BOOTH_instance_n209, C0 =>
BOOTH_instance_n228, Y => BOOTH_instance_n224);
U2226 : AOI22XL port map( A0 => n2183, A1 => BOOTH_instance_n188, B0 =>
BOOTH_instance_n212, B1 => BOOTH_instance_n176, Y =>
BOOTH_instance_n228);
U2227 : OAI221XL port map( A0 => BOOTH_instance_n186, A1 => n2180, B0 =>
n1606, B1 => BOOTH_instance_n199, C0 =>
BOOTH_instance_n218, Y => BOOTH_instance_n214);
U2228 : AOI22XL port map( A0 => n2181, A1 => BOOTH_instance_n188, B0 =>
BOOTH_instance_n202, B1 => BOOTH_instance_n176, Y =>
BOOTH_instance_n218);
U2229 : OAI221XL port map( A0 => BOOTH_instance_n186, A1 => n1608, B0 =>
n1606, B1 => BOOTH_instance_n189, C0 =>
BOOTH_instance_n208, Y => BOOTH_instance_n204);
U2230 : AOI22XL port map( A0 => n2179, A1 => BOOTH_instance_n188, B0 =>
BOOTH_instance_n192, B1 => BOOTH_instance_n176, Y =>
BOOTH_instance_n208);
U2231 : OAI221XL port map( A0 => n1670, A1 => BOOTH_instance_n186, B0 =>
BOOTH_instance_n177, B1 => n1606, C0 =>
BOOTH_instance_n198, Y => BOOTH_instance_n194);
U2232 : AOI22XL port map( A0 => n2178, A1 => BOOTH_instance_n188, B0 =>
BOOTH_instance_n180, B1 => BOOTH_instance_n176, Y =>
BOOTH_instance_n198);
U2233 : OAI221XL port map( A0 => BOOTH_instance_n156, A1 =>
BOOTH_instance_n186, B0 => n1609, B1 => n1606, C0 =>
BOOTH_instance_n187, Y => BOOTH_instance_n182);
U2234 : AOI22XL port map( A0 => BOOTH_instance_n188, A1 => n2177, B0 =>
BOOTH_instance_n176, B1 => BOOTH_instance_n169, Y =>
BOOTH_instance_n187);
U2235 : OAI221XL port map( A0 => BOOTH_instance_n186, A1 => n2191, B0 =>
n1606, B1 => BOOTH_instance_n299, C0 =>
BOOTH_instance_n300, Y => BOOTH_instance_n296);
U2236 : AOI22XL port map( A0 => N4721, A1 => BOOTH_instance_n188, B0 =>
BOOTH_instance_n292, B1 => BOOTH_instance_n176, Y =>
BOOTH_instance_n300);
U2237 : OAI221XL port map( A0 => BOOTH_instance_n186, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n46, B0 => n1606,
B1 => BOOTH_instance_n269, C0 => BOOTH_instance_n288
, Y => BOOTH_instance_n284);
U2238 : AOI22XL port map( A0 => n2190, A1 => BOOTH_instance_n188, B0 =>
BOOTH_instance_n272, B1 => BOOTH_instance_n176, Y =>
BOOTH_instance_n288);
U2239 : OAI222XL port map( A0 => n1721, A1 => n1609, B0 =>
BOOTH_instance_n155, B1 => BOOTH_instance_n156, C0
=> BOOTH_instance_n157, C1 => BOOTH_instance_n158, Y
=> BOOTH_instance_n145);
U2240 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n116, A1
=> n1694, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n9, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C86_n117, Y =>
ALU_instance_SHIFTER_GENERIC_I_N221);
U2241 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C86_n15, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n116);
U2242 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n55, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n56, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n18, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n90, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n14, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n92, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n117);
U2243 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n125, A1
=> n1694, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n115, B1 => n2172
, C0 => ALU_instance_SHIFTER_GENERIC_I_C86_n126, Y
=> ALU_instance_SHIFTER_GENERIC_I_N219);
U2244 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C86_n39, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n125);
U2245 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n55, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n67, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n18, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n76, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n14, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n74, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n126);
U2246 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n18, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n3, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n19, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C48_n20, Y =>
ALU_instance_SHIFTER_GENERIC_I_N112);
U2247 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n6, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n21, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n8, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n22, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n10, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n23, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n20);
U2248 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n18, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n38, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n39, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C48_n40, Y =>
ALU_instance_SHIFTER_GENERIC_I_N108);
U2249 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n10, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n22, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n41, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n42, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n8, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n21, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n40);
U2250 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n44, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n45, B0 =>
n2129, B1 => ALU_instance_SHIFTER_GENERIC_I_C48_n47,
C0 => ALU_instance_SHIFTER_GENERIC_I_C48_n48, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n42);
U2251 : AOI22XL port map( A0 => n2190, A1 => n2125, B0 => N4721, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n50, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n48);
U2252 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C86_n169, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n53);
U2253 : OAI211XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n118, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n70, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n71, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n170, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n169);
U2254 : AOI22XL port map( A0 => n1595, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n92, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n75, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n90, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n170);
U2255 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C48_n88, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n35);
U2256 : OAI211XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n89, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n80, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n81, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n90, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n88);
U2257 : AOI22XL port map( A0 => n1598, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n75, B0 => n1597,
B1 => ALU_instance_SHIFTER_GENERIC_I_C48_n17, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n90);
U2258 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C86_n68, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n2);
U2259 : OAI211XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n69, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n70, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n71, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n72, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n68);
U2260 : AOI22XL port map( A0 => n1595, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n74, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n75, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n76, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n72);
U2261 : AOI22XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n68, A1
=> n1597, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n70, B1 => n1595,
Y => ALU_instance_SHIFTER_GENERIC_I_C50_n4);
U2262 : NOR4XL port map( A => ALU_instance_ADDER_OUT_23_port, B =>
ALU_instance_ADDER_OUT_22_port, C =>
ALU_instance_ADDER_OUT_21_port, D =>
ALU_instance_ADDER_OUT_20_port, Y =>
ALU_instance_COMPARATOR_GENERIC_I_n15);
U2263 : NOR4XL port map( A => ALU_instance_ADDER_OUT_16_port, B =>
ALU_instance_ADDER_OUT_15_port, C =>
ALU_instance_ADDER_OUT_14_port, D =>
ALU_instance_ADDER_OUT_13_port, Y =>
ALU_instance_COMPARATOR_GENERIC_I_n13);
U2264 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n88, A1
=> n1694, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n5, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C86_n89, Y =>
ALU_instance_SHIFTER_GENERIC_I_N225);
U2265 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C86_n19, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n88);
U2266 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n55, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n15, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n18, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n56, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n14, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n90, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n89);
U2267 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n95, A1
=> n1694, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n6, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C86_n96, Y =>
ALU_instance_SHIFTER_GENERIC_I_N224);
U2268 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C86_n32, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n95);
U2269 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n55, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n30, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n18, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n62, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n14, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n97, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n96);
U2270 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n103, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n3, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n7, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C86_n104, Y =>
ALU_instance_SHIFTER_GENERIC_I_N223);
U2271 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C86_n41, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n103);
U2272 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n55, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n39, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n18, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n67, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n14, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n76, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n104);
U2273 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n26, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n3, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n27, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C50_n28, Y =>
ALU_instance_SHIFTER_GENERIC_I_N143);
U2274 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n6, A1
=> ALU_instance_SHIFTER_GENERIC_I_C50_n29, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n8, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n30, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n10, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n31, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n28);
U2275 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n32, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n3, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n33, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C50_n34, Y =>
ALU_instance_SHIFTER_GENERIC_I_N142);
U2276 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n6, A1
=> ALU_instance_SHIFTER_GENERIC_I_C50_n12, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n8, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n7, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n10, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n9, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n34);
U2277 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n10, A1
=> n1694, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n53, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C86_n54, Y =>
ALU_instance_SHIFTER_GENERIC_I_N229);
U2278 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n55, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n19, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n18, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n15, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n14, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n56, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n54);
U2279 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n27, A1
=> n1694, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n60, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C86_n61, Y =>
ALU_instance_SHIFTER_GENERIC_I_N228);
U2280 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n55, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n32, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n18, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n30, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n14, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n62, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n61);
U2281 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n36, A1
=> n1694, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n2, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C86_n66, Y =>
ALU_instance_SHIFTER_GENERIC_I_N227);
U2282 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n55, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n41, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n18, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n39, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n14, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n67, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n66);
U2283 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n44, A1
=> n1694, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n4, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C86_n80, Y =>
ALU_instance_SHIFTER_GENERIC_I_N226);
U2284 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n55, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n49, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n18, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n47, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n14, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n81, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n80);
U2285 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n121, A1
=> n1694, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n35, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C86_n122, Y =>
ALU_instance_SHIFTER_GENERIC_I_N220);
U2286 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C86_n30, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n121);
U2287 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n55, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n62, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n18, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n97, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n14, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n99, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n122);
U2288 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n129, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n3, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n66, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C48_n130, Y =>
ALU_instance_SHIFTER_GENERIC_I_N117);
U2289 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n6, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n16, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n8, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n17, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n10, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n75, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n130);
U2290 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n43, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n3, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n67, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C48_n131, Y =>
ALU_instance_SHIFTER_GENERIC_I_N116);
U2291 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n6, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n22, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n8, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n23, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n10, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n77, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n131);
U2292 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n59, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n3, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n68, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C48_n143, Y =>
ALU_instance_SHIFTER_GENERIC_I_N115);
U2293 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n6, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n28, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n8, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n29, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n10, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n84, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n143);
U2294 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n2, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n3, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n4, B1 => n2173,
C0 => ALU_instance_SHIFTER_GENERIC_I_C48_n5, Y =>
ALU_instance_SHIFTER_GENERIC_I_N114);
U2295 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n6, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n7, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n8, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n9, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n10, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n11, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n5);
U2296 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n12, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n3, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n13, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C48_n14, Y =>
ALU_instance_SHIFTER_GENERIC_I_N113);
U2297 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n6, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n15, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n8, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n16, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n10, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n17, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n14);
U2298 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n24, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n3, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n25, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C48_n26, Y =>
ALU_instance_SHIFTER_GENERIC_I_N111);
U2299 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n6, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n27, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n8, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n28, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n10, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n29, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n26);
U2300 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n30, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n3, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n31, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C48_n32, Y =>
ALU_instance_SHIFTER_GENERIC_I_N110);
U2301 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n6, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n33, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n8, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n7, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n10, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n9, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n32);
U2302 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n34, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n3, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n35, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C48_n36, Y =>
ALU_instance_SHIFTER_GENERIC_I_N109);
U2303 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n6, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n37, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n8, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n15, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n10, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n16, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n36);
U2304 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n24, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n38, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n56, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C48_n57, Y =>
ALU_instance_SHIFTER_GENERIC_I_N107);
U2305 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n10, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n28, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n41, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n58, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n8, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n27, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n57);
U2306 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n44, A1
=> n2191, B0 => n2129, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n45, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n61, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n58);
U2307 : AOI22XL port map( A0 => N4721, A1 => n2125, B0 => n2193, B1 => n2126
, Y => ALU_instance_SHIFTER_GENERIC_I_C48_n61);
U2308 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n2, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n3, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n4, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C50_n5, Y =>
ALU_instance_SHIFTER_GENERIC_I_N146);
U2309 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C50_n12, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n2);
U2310 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n6, A1
=> ALU_instance_SHIFTER_GENERIC_I_C50_n7, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n8, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n9, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n10, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n11, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n5);
U2311 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n20, A1
=> ALU_instance_SHIFTER_GENERIC_I_C50_n38, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n39, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C50_n40, Y =>
ALU_instance_SHIFTER_GENERIC_I_N140);
U2312 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n10, A1
=> ALU_instance_SHIFTER_GENERIC_I_C50_n24, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n16, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n42, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n8, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n23, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n40);
U2313 : OAI221XL port map( A0 => n2122, A1 => BOOTH_instance_n260, B0 =>
n2123, B1 => ALU_instance_SHIFTER_GENERIC_I_C50_n46,
C0 => ALU_instance_SHIFTER_GENERIC_I_C50_n47, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n42);
U2314 : AOI22XL port map( A0 => n2190, A1 => n2125, B0 => N4721, B1 => n2126
, Y => ALU_instance_SHIFTER_GENERIC_I_C50_n47);
U2315 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n26, A1
=> ALU_instance_SHIFTER_GENERIC_I_C50_n38, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n56, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C50_n57, Y =>
ALU_instance_SHIFTER_GENERIC_I_N139);
U2316 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n10, A1
=> ALU_instance_SHIFTER_GENERIC_I_C50_n30, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n16, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n58, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n8, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n29, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n57);
U2317 : OAI221XL port map( A0 => n2122, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n46, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n44, B1 => n2191,
C0 => ALU_instance_SHIFTER_GENERIC_I_C50_n60, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n58);
U2318 : AOI22XL port map( A0 => N4721, A1 => n2125, B0 => n2193, B1 => n2126
, Y => ALU_instance_SHIFTER_GENERIC_I_C50_n60);
U2319 : MXI2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_C50_n54, B =>
ALU_instance_SHIFTER_GENERIC_I_C50_n73, S0 => n2162,
Y => ALU_instance_SHIFTER_GENERIC_I_C50_n66);
U2320 : AOI21XL port map( A0 => n1704, A1 => n1606, B0 =>
BOOTH_instance_n157, Y => BOOTH_instance_n160);
U2321 : AO22XL port map( A0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_S1_0_port,
A1 => n2137, B0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_S0_0_port,
B1 => EX_ADD_SUB, Y => ALU_instance_ADDER_OUT_0_port
);
U2322 : XNOR2XL port map( A => n2111, B => ALU_instance_INTERNAL_B_0_port, Y
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_S1_0_port
);
U2323 : XOR2XL port map( A => ALU_instance_INTERNAL_B_0_port, B => n2111, Y
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_S0_0_port
);
U2324 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C86_n138, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n12);
U2325 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n118, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n139, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n140, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n70, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n141, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n138);
U2326 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C86_n92, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n140);
U2327 : AOI22XL port map( A0 => n1595, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n90, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n75, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n56, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n141);
U2328 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C86_n149, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n37);
U2329 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n69, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n139, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n150, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n70, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n151, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n149);
U2330 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C86_n74, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n150);
U2331 : AOI22XL port map( A0 => n1595, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n76, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n75, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n67, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n151);
U2332 : AOI22XL port map( A0 => BOOTH_instance_n352, A1 => n2189, B0 =>
BOOTH_instance_n353, B1 => BOOTH_instance_n242, Y =>
BOOTH_instance_n363);
U2333 : AOI22XL port map( A0 => BOOTH_instance_n352, A1 => n2187, B0 =>
BOOTH_instance_n353, B1 => BOOTH_instance_n232, Y =>
BOOTH_instance_n362);
U2334 : AOI22XL port map( A0 => BOOTH_instance_n352, A1 => n2185, B0 =>
BOOTH_instance_n353, B1 => BOOTH_instance_n222, Y =>
BOOTH_instance_n361);
U2335 : AOI22XL port map( A0 => BOOTH_instance_n352, A1 => n2183, B0 =>
BOOTH_instance_n353, B1 => BOOTH_instance_n212, Y =>
BOOTH_instance_n360);
U2336 : AOI22XL port map( A0 => BOOTH_instance_n352, A1 => n2181, B0 =>
BOOTH_instance_n353, B1 => BOOTH_instance_n202, Y =>
BOOTH_instance_n359);
U2337 : AOI22XL port map( A0 => BOOTH_instance_n352, A1 => n2179, B0 =>
BOOTH_instance_n353, B1 => BOOTH_instance_n192, Y =>
BOOTH_instance_n358);
U2338 : AOI22XL port map( A0 => BOOTH_instance_n352, A1 => n2178, B0 =>
BOOTH_instance_n353, B1 => BOOTH_instance_n180, Y =>
BOOTH_instance_n357);
U2339 : OAI221XL port map( A0 => BOOTH_instance_n158, A1 =>
BOOTH_instance_n229, B0 => BOOTH_instance_n166, B1
=> n2186, C0 => BOOTH_instance_n231, Y =>
BOOTH_instance_n223);
U2340 : AOI22XL port map( A0 => n2187, A1 => BOOTH_instance_n168, B0 =>
BOOTH_instance_n232, B1 => BOOTH_instance_n150, Y =>
BOOTH_instance_n231);
U2341 : AOI22XL port map( A0 => BOOTH_instance_n352, A1 => n2177, B0 =>
BOOTH_instance_n353, B1 => BOOTH_instance_n169, Y =>
BOOTH_instance_n356);
U2342 : OAI221XL port map( A0 => BOOTH_instance_n158, A1 =>
BOOTH_instance_n199, B0 => BOOTH_instance_n166, B1
=> n2180, C0 => BOOTH_instance_n201, Y =>
BOOTH_instance_n193);
U2343 : AOI22XL port map( A0 => n2181, A1 => BOOTH_instance_n168, B0 =>
BOOTH_instance_n202, B1 => BOOTH_instance_n150, Y =>
BOOTH_instance_n201);
U2344 : OAI221XL port map( A0 => BOOTH_instance_n158, A1 =>
BOOTH_instance_n189, B0 => BOOTH_instance_n166, B1
=> n1608, C0 => BOOTH_instance_n191, Y =>
BOOTH_instance_n181);
U2345 : AOI22XL port map( A0 => n2179, A1 => BOOTH_instance_n168, B0 =>
BOOTH_instance_n192, B1 => BOOTH_instance_n150, Y =>
BOOTH_instance_n191);
U2346 : OAI221XL port map( A0 => n1609, A1 => BOOTH_instance_n158, B0 =>
BOOTH_instance_n156, B1 => BOOTH_instance_n166, C0
=> BOOTH_instance_n167, Y => BOOTH_instance_n162);
U2347 : AOI22XL port map( A0 => n2177, A1 => BOOTH_instance_n168, B0 =>
BOOTH_instance_n169, B1 => BOOTH_instance_n150, Y =>
BOOTH_instance_n167);
U2348 : AOI21XL port map( A0 => n1606, A1 => BOOTH_instance_n186, B0 =>
BOOTH_instance_n316, Y =>
BOOTH_instance_partial_products_5_12_port);
U2349 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C50_n64, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n70);
U2350 : NOR2XL port map( A => BOOTH_instance_n315, B => BOOTH_instance_n316,
Y => BOOTH_instance_decoded_8_16_port);
U2351 : OA21XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n100, A1
=> n1697, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n112, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n35);
U2352 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C48_n86, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n69);
U2353 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C48_n114, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n28);
U2354 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C48_n97, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n7);
U2355 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C48_n129, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n15);
U2356 : AO21XL port map( A0 => BOOTH_instance_n374, A1 => n1707, B0 =>
BOOTH_instance_n157, Y => n1700);
U2357 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C50_n55, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n77);
U2358 : AND2XL port map( A => ALU_instance_INTERNAL_B_12_port, B => n2179, Y
=>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_RCA0_add_1_root_add_20_2_carry_1_port);
U2359 : AO22XL port map( A0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_S1_1_port,
A1 => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_5_port
, B0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_S0_1_port,
B1 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_n2, Y
=> ALU_instance_ADDER_OUT_21_port);
U2360 : AO22XL port map( A0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_S1_2_port,
A1 => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_4_port
, B0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_S0_2_port,
B1 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_n2, Y
=> ALU_instance_ADDER_OUT_18_port);
U2361 : AO22XL port map( A0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_S1_3_port,
A1 => n2137, B0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_S0_3_port,
B1 => EX_ADD_SUB, Y => ALU_instance_ADDER_OUT_3_port
);
U2362 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C48_n74, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n89);
U2363 : AO22XL port map( A0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_S1_0_port,
A1 => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_2_port
, B0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_S0_0_port,
B1 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_n2, Y
=> ALU_instance_ADDER_OUT_8_port);
U2364 : XNOR2XL port map( A => n2187, B => ALU_instance_INTERNAL_B_8_port, Y
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_S1_0_port
);
U2365 : XOR2XL port map( A => ALU_instance_INTERNAL_B_8_port, B => n2187, Y
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_S0_0_port
);
U2366 : AO22XL port map( A0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_S1_2_port,
A1 => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_5_port
, B0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_S0_2_port,
B1 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_n2, Y
=> ALU_instance_ADDER_OUT_22_port);
U2367 : AO22XL port map( A0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_S1_3_port,
A1 => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_4_port
, B0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_S0_3_port,
B1 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_n2, Y
=> ALU_instance_ADDER_OUT_19_port);
U2368 : AO22XL port map( A0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_S1_3_port,
A1 => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_3_port
, B0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_S0_3_port,
B1 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_n2, Y
=> ALU_instance_ADDER_OUT_15_port);
U2369 : AO22XL port map( A0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_S1_2_port,
A1 => n2137, B0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_S0_2_port,
B1 => EX_ADD_SUB, Y => ALU_instance_ADDER_OUT_2_port
);
U2370 : AO22XL port map( A0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_S1_0_port,
A1 => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_3_port
, B0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_S0_0_port,
B1 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_n2, Y
=> ALU_instance_ADDER_OUT_12_port);
U2371 : XNOR2XL port map( A => n2179, B => ALU_instance_INTERNAL_B_12_port,
Y =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_S1_0_port);
U2372 : XOR2XL port map( A => ALU_instance_INTERNAL_B_12_port, B => n2179, Y
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_S0_0_port
);
U2373 : AO22XL port map( A0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_S1_1_port,
A1 => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_1_port
, B0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_S0_1_port,
B1 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_n2, Y
=> ALU_instance_ADDER_OUT_5_port);
U2374 : AO22XL port map( A0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_S1_3_port,
A1 => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_5_port
, B0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_S0_3_port,
B1 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_n2, Y
=> ALU_instance_ADDER_OUT_23_port);
U2375 : AO22XL port map( A0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_S1_1_port,
A1 => n2137, B0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_S0_1_port,
B1 => EX_ADD_SUB, Y => ALU_instance_ADDER_OUT_1_port
);
U2376 : AO22XL port map( A0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_S1_2_port,
A1 => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_1_port
, B0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_S0_2_port,
B1 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_n2, Y
=> ALU_instance_ADDER_OUT_6_port);
U2377 : AO22XL port map( A0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_S1_1_port,
A1 => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_4_port
, B0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_S0_1_port,
B1 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_n2, Y
=> ALU_instance_ADDER_OUT_17_port);
U2378 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C86_n144, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n28);
U2379 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n100, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n139, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n145, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n70, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n146, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n144);
U2380 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C86_n99, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n145);
U2381 : AOI22XL port map( A0 => n1595, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n97, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n75, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n62, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n146);
U2382 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C50_n102, Y =>
ALU_instance_SHIFTER_GENERIC_I_N150);
U2383 : AOI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n9, A1
=> ALU_instance_SHIFTER_GENERIC_I_C50_n6, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n7, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n16, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n103, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n102);
U2384 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C50_n104, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n103);
U2385 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n10, A1
=> ALU_instance_SHIFTER_GENERIC_I_C50_n68, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n98, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n70, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n8, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n11, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n104);
U2386 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C86_n129, Y =>
ALU_instance_SHIFTER_GENERIC_I_N218);
U2387 : AOI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n81, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n55, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n47, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n16, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n130, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n129);
U2388 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C86_n131, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n130);
U2389 : AOI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n14, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n82, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n18, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n83, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n132, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n131);
U2390 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C48_n110, Y =>
ALU_instance_SHIFTER_GENERIC_I_N120);
U2391 : AOI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n23, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n6, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n22, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n41, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n111, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n110);
U2392 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C48_n112, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n111);
U2393 : AOI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n10, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n76, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n8, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n77, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n109, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n112);
U2394 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C50_n95, Y =>
ALU_instance_SHIFTER_GENERIC_I_N152);
U2395 : AOI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n25, A1
=> ALU_instance_SHIFTER_GENERIC_I_C50_n6, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n24, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n16, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n96, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n95);
U2396 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C50_n97, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n96);
U2397 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n10, A1
=> ALU_instance_SHIFTER_GENERIC_I_C50_n73, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n98, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n54, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n8, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n75, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n97);
U2398 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C50_n99, Y =>
ALU_instance_SHIFTER_GENERIC_I_N151);
U2399 : AOI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n31, A1
=> ALU_instance_SHIFTER_GENERIC_I_C50_n6, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n30, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n16, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n100, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n99);
U2400 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C50_n101, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n100);
U2401 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n10, A1
=> ALU_instance_SHIFTER_GENERIC_I_C50_n76, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n98, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n77, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n8, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n78, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n101);
U2402 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C50_n118, Y =>
ALU_instance_SHIFTER_GENERIC_I_N149);
U2403 : AOI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n17, A1
=> ALU_instance_SHIFTER_GENERIC_I_C50_n6, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n16, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n16, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n119, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n118);
U2404 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C50_n120, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n119);
U2405 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n10, A1
=> ALU_instance_SHIFTER_GENERIC_I_C50_n72, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n98, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n65, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n8, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n18, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n120);
U2406 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C86_n176, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n60);
U2407 : OAI211XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n100, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n70, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n71, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n177, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n176);
U2408 : AOI22XL port map( A0 => n1595, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n99, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n75, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n97, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n177);
U2409 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C86_n162, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n45);
U2410 : OAI211XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n110, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n70, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n71, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n163, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n162);
U2411 : AOI22XL port map( A0 => n1595, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n83, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n75, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n81, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n163);
U2412 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C48_n99, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n39);
U2413 : OAI211XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n100, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n80, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n81, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n101, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n99);
U2414 : AOI22XL port map( A0 => n1598, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n77, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n75, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n23, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n101);
U2415 : AO21XL port map( A0 => BOOTH_instance_n398, A1 => n1698, B0 =>
BOOTH_instance_n157, Y => n1701);
U2416 : OR2XL port map( A => ALU_instance_INTERNAL_B_12_port, B => n2179, Y
=>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_3_RCA1_add_1_root_add_20_2_carry_1_port);
U2417 : OR2XL port map( A => ALU_instance_INTERNAL_B_8_port, B => n2187, Y
=>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_RCA1_add_1_root_add_20_2_carry_1_port);
U2418 : AND2XL port map( A => ALU_instance_INTERNAL_B_8_port, B => n2187, Y
=>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_2_RCA0_add_1_root_add_20_2_carry_1_port);
U2419 : AO22XL port map( A0 => EX_MULT_OUT_1_port, A1 => n2145, B0 =>
EX_ALU_OUT_1_port, B1 => n2144, Y => N4861);
U2420 : OAI222XL port map( A0 => BOOTH_instance_n316, A1 => n2127, B0 =>
BOOTH_instance_n308, B1 => n2129, C0 =>
BOOTH_instance_n307, C1 => BOOTH_instance_n447, Y =>
EX_MULT_OUT_1_port);
U2421 : OAI2BB1XL port map( A0N => ALU_instance_ADDER_OUT_1_port, A1N =>
n1599, B0 => ALU_instance_n20, Y =>
EX_ALU_OUT_1_port);
U2422 : AOI22XL port map( A0 => ALU_instance_SHIFTER_OUT_1_port, A1 =>
ALU_instance_n5, B0 => ALU_instance_LOGIC_OUT_1_port
, B1 => ALU_instance_n6, Y => ALU_instance_n20);
U2423 : AO22XL port map( A0 => EX_MULT_OUT_3_port, A1 => n2145, B0 =>
EX_ALU_OUT_3_port, B1 => n2144, Y => N4863);
U2424 : OAI2BB1XL port map( A0N => ALU_instance_ADDER_OUT_3_port, A1N =>
n1599, B0 => ALU_instance_n18, Y =>
EX_ALU_OUT_3_port);
U2425 : AOI22XL port map( A0 => ALU_instance_SHIFTER_OUT_3_port, A1 =>
ALU_instance_n5, B0 => ALU_instance_LOGIC_OUT_3_port
, B1 => ALU_instance_n6, Y => ALU_instance_n18);
U2426 : OAI2B2XL port map( A1N => n2175, A0 =>
ALU_instance_LOGIC_GENERIC_I_n51, B0 => n2175, B1 =>
ALU_instance_LOGIC_GENERIC_I_n52, Y =>
ALU_instance_LOGIC_OUT_3_port);
U2427 : OAI2BB1XL port map( A0N => ALU_instance_ADDER_OUT_2_port, A1N =>
n1599, B0 => ALU_instance_n19, Y =>
EX_ALU_OUT_2_port);
U2428 : AOI22XL port map( A0 => ALU_instance_SHIFTER_OUT_2_port, A1 => n2138
, B0 => ALU_instance_LOGIC_OUT_2_port, B1 =>
ALU_instance_n6, Y => ALU_instance_n19);
U2429 : AO22XL port map( A0 => EX_MULT_OUT_4_port, A1 => n2145, B0 =>
EX_ALU_OUT_4_port, B1 => n2144, Y => N4864);
U2430 : XOR2XL port map( A => BOOTH_instance_partial_products_8_4_port, B =>
BOOTH_instance_partial_products_7_4_port, Y =>
EX_MULT_OUT_4_port);
U2431 : OAI2BB1XL port map( A0N => ALU_instance_ADDER_OUT_4_port, A1N =>
n1599, B0 => ALU_instance_n17, Y =>
EX_ALU_OUT_4_port);
U2432 : AOI22XL port map( A0 => ALU_instance_SHIFTER_OUT_4_port, A1 =>
ALU_instance_n5, B0 => ALU_instance_LOGIC_OUT_4_port
, B1 => ALU_instance_n6, Y => ALU_instance_n17);
U2433 : INVXL port map( A => n2141, Y => n2143);
U2434 : AOI221XL port map( A0 => n1708, A1 => n1530, B0 => n1523, B1 =>
n1548, C0 => n1558, Y => n1546);
U2435 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n73, A1
=> n1595, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n54, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n74, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n75, C1 => n1597,
Y => ALU_instance_SHIFTER_GENERIC_I_C50_n21);
U2436 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n72, A1
=> n1595, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n65, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n74, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n18, C1 => n1597,
Y => ALU_instance_SHIFTER_GENERIC_I_C50_n36);
U2437 : AOI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n102, A1
=> n1598, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n83, B1 => n1597,
C0 => ALU_instance_SHIFTER_GENERIC_I_C48_n73, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n68);
U2438 : AOI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n74, A1
=> n1598, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n75, B1 => n1597,
C0 => ALU_instance_SHIFTER_GENERIC_I_C48_n73, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n13);
U2439 : AOI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n76, A1
=> n1598, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n77, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n75, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n73, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n19);
U2440 : OR2XL port map( A => EX_SHIFTER_CW_0_port, B =>
ALU_instance_SHIFTER_GENERIC_I_n89, Y => n1702);
U2441 : OAI221XL port map( A0 => n2122, A1 => n1670, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n45, B1 => n1608,
C0 => ALU_instance_SHIFTER_GENERIC_I_C50_n127, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n23);
U2442 : AOI22XL port map( A0 => n2179, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n48, B0 => n2181,
B1 => ALU_instance_SHIFTER_GENERIC_I_C50_n49, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n127);
U2443 : AOI221XL port map( A0 => n2124, A1 => n2187, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n52, B1 => n2185,
C0 => ALU_instance_SHIFTER_GENERIC_I_C48_n62, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n24);
U2444 : OAI2B2XL port map( A1N => n2189, A0 => n1644, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n47, B1 => n1643,
Y => ALU_instance_SHIFTER_GENERIC_I_C48_n62);
U2445 : AOI221XL port map( A0 => n2124, A1 => n2189, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n52, B1 => n2187,
C0 => ALU_instance_SHIFTER_GENERIC_I_C48_n98, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n30);
U2446 : OAI22XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n47, A1
=> n1644, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n45, B1 => n1643,
Y => ALU_instance_SHIFTER_GENERIC_I_C48_n98);
U2447 : AOI221XL port map( A0 => n2124, A1 => n2185, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n52, B1 => n2183,
C0 => ALU_instance_SHIFTER_GENERIC_I_C48_n53, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n18);
U2448 : AO22XL port map( A0 => n2187, A1 => n2125, B0 => n2189, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n49, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n53);
U2449 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n143, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n3, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n67, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C50_n144, Y =>
ALU_instance_SHIFTER_GENERIC_I_N147);
U2450 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C50_n29, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n143);
U2451 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n6, A1
=> ALU_instance_SHIFTER_GENERIC_I_C50_n30, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n8, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n31, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n10, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n78, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n144);
U2452 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n114, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n3, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n54, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C48_n115, Y =>
ALU_instance_SHIFTER_GENERIC_I_N119);
U2453 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n6, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n29, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n8, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n84, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n10, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n83, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n115);
U2454 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n97, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n3, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n65, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C48_n118, Y =>
ALU_instance_SHIFTER_GENERIC_I_N118);
U2455 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n6, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n9, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n8, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n11, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n10, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n71, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n118);
U2456 : AOI22XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n76, A1
=> n1597, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n77, B1 => n1598,
Y => ALU_instance_SHIFTER_GENERIC_I_C50_n67);
U2457 : AOI22XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n72, A1
=> n1597, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n65, B1 => n1598,
Y => ALU_instance_SHIFTER_GENERIC_I_C50_n14);
U2458 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n35, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n3, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n36, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C50_n37, Y =>
ALU_instance_SHIFTER_GENERIC_I_N141);
U2459 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n6, A1
=> ALU_instance_SHIFTER_GENERIC_I_C50_n19, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n8, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n16, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n10, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n17, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n37);
U2460 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n20, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n3, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n21, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C50_n22, Y =>
ALU_instance_SHIFTER_GENERIC_I_N144);
U2461 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n6, A1
=> ALU_instance_SHIFTER_GENERIC_I_C50_n23, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n8, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n24, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n10, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n25, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n22);
U2462 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n108, A1
=> n1694, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n8, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C86_n109, Y =>
ALU_instance_SHIFTER_GENERIC_I_N222);
U2463 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C86_n49, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n108);
U2464 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n55, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n47, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n18, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n81, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n14, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n83, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n109);
U2465 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n13, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n3, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n14, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C50_n15, Y =>
ALU_instance_SHIFTER_GENERIC_I_N145);
U2466 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C50_n19, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n13);
U2467 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n6, A1
=> ALU_instance_SHIFTER_GENERIC_I_C50_n16, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n8, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n17, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n10, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n18, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n15);
U2468 : OAI2B2XL port map( A1N => n2164, A0 =>
ALU_instance_LOGIC_GENERIC_I_n126, B0 => n2163, B1
=> ALU_instance_LOGIC_GENERIC_I_n127, Y =>
ALU_instance_LOGIC_OUT_0_port);
U2469 : NAND2XL port map( A => n2195, B => n2112, Y =>
ALU_instance_LOGIC_GENERIC_I_n127);
U2470 : AOI22XL port map( A0 => n2194, A1 => BOOTH_instance_n316, B0 =>
ALU_instance_SHIFTER_GENERIC_I_N202, B1 =>
EX_LOGIC_CW_3_port, Y =>
ALU_instance_LOGIC_GENERIC_I_n126);
U2471 : NAND2XL port map( A => n2195, B => n2190, Y =>
ALU_instance_LOGIC_GENERIC_I_n49);
U2472 : MXI2XL port map( A => n2113, B => BOOTH_instance_n307, S0 => n2126,
Y => ALU_instance_SHIFTER_GENERIC_I_C86_n105);
U2473 : NOR2BXL port map( AN => ALU_instance_SHIFTER_GENERIC_I_C50_n49, B =>
ALU_instance_SHIFTER_GENERIC_I_C50_n139, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n54);
U2474 : NOR2XL port map( A => n2173, B =>
ALU_instance_SHIFTER_GENERIC_I_C50_n139, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n109);
U2475 : OAI2B11XL port map( A1N => ALU_instance_SHIFTER_GENERIC_I_C50_n75,
A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n122, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n123, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n124, Y =>
ALU_instance_SHIFTER_GENERIC_I_N148);
U2476 : AOI22XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n6, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n24, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n16, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n23, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n124);
U2477 : AOI32XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n90, A1
=> n1600, A2 => n2171, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n8, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n25, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n123);
U2478 : AOI22XL port map( A0 => n2195, A1 => n2186, B0 => EX_LOGIC_CW_3_port
, B1 => n2185, Y => ALU_instance_LOGIC_GENERIC_I_n33
);
U2479 : AOI22XL port map( A0 => n2194, A1 => n1670, B0 => n2177, B1 =>
EX_LOGIC_CW_3_port, Y =>
ALU_instance_LOGIC_GENERIC_I_n111);
U2480 : AOI22XL port map( A0 => n2194, A1 => n1608, B0 => n2178, B1 =>
EX_LOGIC_CW_3_port, Y =>
ALU_instance_LOGIC_GENERIC_I_n114);
U2481 : AOI22XL port map( A0 => n2194, A1 => n2180, B0 => n2179, B1 =>
EX_LOGIC_CW_3_port, Y =>
ALU_instance_LOGIC_GENERIC_I_n117);
U2482 : AOI22XL port map( A0 => n2194, A1 => n2182, B0 => n2181, B1 =>
EX_LOGIC_CW_3_port, Y =>
ALU_instance_LOGIC_GENERIC_I_n120);
U2483 : AOI22XL port map( A0 => n2195, A1 => n2188, B0 => n2187, B1 => n2197
, Y => ALU_instance_LOGIC_GENERIC_I_n36);
U2484 : AOI22XL port map( A0 => n2195, A1 => n1607, B0 => n2189, B1 =>
EX_LOGIC_CW_3_port, Y =>
ALU_instance_LOGIC_GENERIC_I_n39);
U2485 : AOI22XL port map( A0 => n2194, A1 => n2192, B0 => N4721, B1 => n2197
, Y => ALU_instance_LOGIC_GENERIC_I_n51);
U2486 : OAI221XL port map( A0 => BOOTH_instance_n307, A1 => n2128, B0 =>
n2113, B1 => n2129, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n175, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n91);
U2487 : AOI22XL port map( A0 => n2130, A1 => n2193, B0 => N4721, B1 => n2126
, Y => ALU_instance_SHIFTER_GENERIC_I_C86_n175);
U2488 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n43, A1
=> n1608, B0 => n2123, B1 => n2180, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n149, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n29);
U2489 : AOI22XL port map( A0 => n2181, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n48, B0 => n2183,
B1 => n2126, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n149);
U2490 : OAI221XL port map( A0 => n2122, A1 => n2180, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n44, B1 => n2182,
C0 => ALU_instance_SHIFTER_GENERIC_I_C50_n84, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n12);
U2491 : AOI22XL port map( A0 => n2183, A1 => n2125, B0 => n2185, B1 => n2126
, Y => ALU_instance_SHIFTER_GENERIC_I_C50_n84);
U2492 : OAI221XL port map( A0 => n2122, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n119, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n45, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n113, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n114, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n7);
U2493 : AOI22XL port map( A0 => n2177, A1 => n2125, B0 => n2178, B1 => n2126
, Y => ALU_instance_SHIFTER_GENERIC_I_C50_n114);
U2494 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n43, A1
=> ALU_instance_SHIFTER_GENERIC_I_C50_n113, B0 =>
n2123, B1 => n1670, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n156, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n16);
U2495 : AOI22XL port map( A0 => n2178, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n48, B0 => n2179,
B1 => n2126, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n156);
U2496 : NOR2XL port map( A => n2176, B => n2171, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n153);
U2497 : AOI2B1XL port map( A1N => n2114, A0 => n2161, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n84, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n112);
U2498 : NOR2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_C50_n64, B =>
ALU_instance_SHIFTER_GENERIC_I_C48_n3, Y =>
ALU_instance_SHIFTER_GENERIC_I_N166);
U2499 : OA21XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n86, A1 =>
n1697, B0 => ALU_instance_SHIFTER_GENERIC_I_C48_n117
, Y => ALU_instance_SHIFTER_GENERIC_I_C48_n65);
U2500 : OA21XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n79, A1 =>
n1697, B0 => ALU_instance_SHIFTER_GENERIC_I_C48_n117
, Y => ALU_instance_SHIFTER_GENERIC_I_C48_n54);
U2501 : OA21XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n89, A1 =>
n1697, B0 => ALU_instance_SHIFTER_GENERIC_I_C48_n117
, Y => ALU_instance_SHIFTER_GENERIC_I_C48_n66);
U2502 : OA21XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n100, A1
=> n1697, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n117, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n67);
U2503 : NOR2XL port map( A => n2162, B => n2176, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n92);
U2504 : NAND2XL port map( A => n2174, B => n2162, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n80);
U2505 : NOR2XL port map( A => n1600, B => n2171, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n133);
U2506 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C48_n76, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n100);
U2507 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C86_n82, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n110);
U2508 : NOR2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_C50_n55, B =>
ALU_instance_SHIFTER_GENERIC_I_C48_n3, Y =>
ALU_instance_SHIFTER_GENERIC_I_N167);
U2509 : NAND2XL port map( A => n2195, B => n2183, Y =>
ALU_instance_LOGIC_GENERIC_I_n124);
U2510 : NAND2XL port map( A => n2195, B => n2185, Y =>
ALU_instance_LOGIC_GENERIC_I_n34);
U2511 : NAND2XL port map( A => n2195, B => n2181, Y =>
ALU_instance_LOGIC_GENERIC_I_n121);
U2512 : NAND2XL port map( A => n2195, B => n2189, Y =>
ALU_instance_LOGIC_GENERIC_I_n40);
U2513 : NAND2XL port map( A => n2196, B => n2178, Y =>
ALU_instance_LOGIC_GENERIC_I_n115);
U2514 : NAND2XL port map( A => n2195, B => N4721, Y =>
ALU_instance_LOGIC_GENERIC_I_n52);
U2515 : NAND2XL port map( A => n2196, B => n2177, Y =>
ALU_instance_LOGIC_GENERIC_I_n112);
U2516 : NAND2XL port map( A => n2195, B => n2179, Y =>
ALU_instance_LOGIC_GENERIC_I_n118);
U2517 : NAND2XL port map( A => n2195, B => n2187, Y =>
ALU_instance_LOGIC_GENERIC_I_n37);
U2518 : NAND2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_7_port,
B => n1600, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_n1);
U2519 : NAND2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_6_port,
B => n1600, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_n2);
U2520 : NAND2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_5_port,
B => n1600, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_n3);
U2521 : NAND2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_4_port,
B => n1600, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_n4);
U2522 : NOR2XL port map( A => BOOTH_instance_n315, B => BOOTH_instance_n156,
Y => BOOTH_instance_decoded_8_31_port);
U2523 : NAND2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_0_port,
B => n1600, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_n8);
U2524 : NAND2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_3_port,
B => n1600, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_n5);
U2525 : NAND2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_2_port,
B => n1600, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_n6);
U2526 : NAND2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_1_port,
B => n1600, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_n7);
U2527 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C48_n78, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n25);
U2528 : OAI211XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n79, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n80, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n81, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n82, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n78);
U2529 : AOI22XL port map( A0 => n1598, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n83, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n75, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n84, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n82);
U2530 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C48_n85, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n31);
U2531 : OAI211XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n86, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n80, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n81, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n87, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n85);
U2532 : AOI22XL port map( A0 => n1598, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n71, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n75, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n11, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n87);
U2533 : CLKINVX2 port map( A => n1600, Y => n2175);
U2534 : INVXL port map( A => EX_SHIFTER_CW_0_port, Y =>
ALU_instance_SHIFTER_GENERIC_I_n88);
U2535 : INVXL port map( A => EX_ALU_SEL_1_port, Y => ALU_instance_n23);
U2536 : CLKINVX2 port map( A => n2165, Y => n2164);
U2537 : AND2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_3_port,
B => n2162, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_3_port);
U2538 : AND2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_2_port,
B => n2162, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_2_port);
U2539 : AND2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_0_port,
B => n2162, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_0_port);
U2540 : AND2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_1_port,
B => n2162, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_3_1_port);
U2541 : CLKBUFX1 port map( A => n2173, Y => n2172);
U2542 : AND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_C50_n65, B =>
ALU_instance_SHIFTER_GENERIC_I_C86_n16, Y =>
ALU_instance_SHIFTER_GENERIC_I_N165);
U2543 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C48_n79, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n102);
U2544 : AND2XL port map( A => n2112, B => n2166, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_0_port);
U2545 : CLKBUFX1 port map( A => n1616, Y => n2132);
U2546 : INVXL port map( A => n1536, Y => n1548);
U2547 : NOR2XL port map( A => n1197, B => n1478, Y => n1190);
U2548 : CLKINVX1 port map( A => n1292, Y => n1227);
U2549 : CLKBUFX1 port map( A => n1225, Y => n2147);
U2550 : INVXL port map( A => n1485, Y => n1479);
U2551 : NAND2XL port map( A => n1619, B => n1310, Y => n1207);
U2552 : NOR2XL port map( A => n1440, B => n1190, Y => n1199);
U2553 : INVXL port map( A => n1368, Y => n1367);
U2554 : INVXL port map( A => n1338, Y => n1495);
U2555 : NAND2XL port map( A => WB_DATA_EXT_8_9_port, B => n1330, Y => n1208)
;
U2556 : CLKBUFX1 port map( A => WB_SIGN_EXT_16_instance_n27, Y => n2110);
U2557 : INVXL port map( A => n1493, Y => n1507);
U2558 : AOI22XL port map( A0 => BOOTH_instance_n188, A1 => n2116, B0 =>
BOOTH_instance_n176, B1 => BOOTH_instance_n320, Y =>
BOOTH_instance_n319);
U2559 : AOI222XL port map( A0 => EX_COMPARATOR_CW_1_port, A1 =>
ALU_instance_COMPARATOR_GENERIC_I_n6, B0 =>
EX_COMPARATOR_CW_2_port, B1 =>
ALU_instance_COMPARATOR_GENERIC_I_n7, C0 =>
EX_COMPARATOR_CW_5_port, C1 =>
ALU_instance_COMPARATOR_GENERIC_I_n8, Y =>
ALU_instance_COMPARATOR_GENERIC_I_n5);
U2560 : OAI31XL port map( A0 => n1537, A1 => n1374, A2 => n1542, B0 => n1543
, Y => EX_COMPARATOR_CW_2_port);
U2561 : INVXL port map( A => ALU_instance_COMPARATOR_GENERIC_I_n7, Y =>
ALU_instance_COMPARATOR_GENERIC_I_n8);
U2562 : INVXL port map( A => ALU_instance_ZERO, Y =>
ALU_instance_COMPARATOR_GENERIC_I_n6);
U2563 : AOI221XL port map( A0 => N4719, A1 => BOOTH_instance_n326, B0 =>
BOOTH_instance_n320, B1 => BOOTH_instance_n327, C0
=> BOOTH_instance_n343, Y => BOOTH_instance_n342);
U2564 : OAI22XL port map( A0 => BOOTH_instance_n328, A1 => n1647, B0 =>
BOOTH_instance_n323, B1 => BOOTH_instance_n290, Y =>
BOOTH_instance_n343);
U2565 : INVXL port map( A => BOOTH_instance_n404, Y =>
BOOTH_instance_decoded_2_6_port);
U2566 : XNOR2XL port map( A => BOOTH_instance_n347, B => N4836, Y =>
BOOTH_instance_n348);
U2567 : XNOR2XL port map( A => N4841, B => BOOTH_instance_n318, Y =>
BOOTH_instance_n317);
U2568 : XNOR2XL port map( A => N4833, B => BOOTH_instance_n396, Y =>
BOOTH_instance_n395);
U2569 : XNOR2XL port map( A => N4835, B => BOOTH_instance_n372, Y =>
BOOTH_instance_n371);
U2570 : XNOR2XL port map( A => n690, B => n1593, Y => BOOTH_instance_n443);
U2571 : OAI22XL port map( A0 => BOOTH_instance_n373, A1 => n1647, B0 =>
BOOTH_instance_n374, B1 => BOOTH_instance_n290, Y =>
BOOTH_instance_n379);
U2572 : OAI22XL port map( A0 => BOOTH_instance_n421, A1 => n1647, B0 =>
BOOTH_instance_n422, B1 => BOOTH_instance_n290, Y =>
BOOTH_instance_n431);
U2573 : OR3XL port map( A => N4837, B => N4836, C => BOOTH_instance_n345, Y
=> n1703);
U2574 : OR3XL port map( A => n1648, B => N4839, C => BOOTH_instance_n318, Y
=> n1704);
U2575 : OR3XL port map( A => BOOTH_instance_n346, B => n1648, C =>
BOOTH_instance_n347, Y => n1705);
U2576 : AOI22XL port map( A0 => BOOTH_instance_n352, A1 => n2118, B0 =>
BOOTH_instance_n353, B1 => n1596, Y =>
BOOTH_instance_n365);
U2577 : AOI22XL port map( A0 => BOOTH_instance_n352, A1 => n2120, B0 =>
BOOTH_instance_n353, B1 => BOOTH_instance_n252, Y =>
BOOTH_instance_n364);
U2578 : NAND3XL port map( A => N4834, B => BOOTH_instance_n346, C => N4835,
Y => BOOTH_instance_n355);
U2579 : NAND3XL port map( A => N4832, B => BOOTH_instance_n372, C => N4833,
Y => BOOTH_instance_n382);
U2580 : AOI22XL port map( A0 => BOOTH_instance_n400, A1 => n2117, B0 =>
BOOTH_instance_n401, B1 => n1596, Y =>
BOOTH_instance_n418);
U2581 : AOI22XL port map( A0 => BOOTH_instance_n400, A1 => n2119, B0 =>
BOOTH_instance_n401, B1 => BOOTH_instance_n252, Y =>
BOOTH_instance_n417);
U2582 : NAND3XL port map( A => N4839, B => BOOTH_instance_n318, C => n1648,
Y => BOOTH_instance_n175);
U2583 : INVXL port map( A => N4834, Y => BOOTH_instance_n372);
U2584 : NAND3XL port map( A => n1580, B => n1565, C => n1584, Y => n1555);
U2585 : NAND3XL port map( A => n1575, B => n1580, C => n1528, Y => n1557);
U2586 : NAND3XL port map( A => n1580, B => n1577, C => n1575, Y => n1545);
U2587 : NAND2XL port map( A => n1575, B => n1576, Y => n1568);
U2588 : AOI32XL port map( A0 => EX_ALU_SEL_0_port, A1 => ALU_instance_n23,
A2 => ALU_instance_COMPARATOR_OUT_0_port, B0 =>
ALU_instance_SHIFTER_OUT_0_port, B1 => n2138, Y =>
ALU_instance_n22);
U2589 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_n85, B =>
ALU_instance_SHIFTER_GENERIC_I_n86, Y =>
ALU_instance_SHIFTER_OUT_0_port);
U2590 : NAND2XL port map( A => ALU_instance_COMPARATOR_GENERIC_I_n4, B =>
ALU_instance_COMPARATOR_GENERIC_I_n5, Y =>
ALU_instance_COMPARATOR_OUT_0_port);
U2591 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_N234, B =>
n1614, Y => ALU_instance_SHIFTER_GENERIC_I_n85);
U2592 : OR2XL port map( A => ALU_instance_INTERNAL_B_0_port, B => n2111, Y
=>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_RCA1_add_1_root_add_20_2_carry_1_port);
U2593 : INVXL port map( A => BOOTH_instance_n369, Y =>
BOOTH_instance_decoded_4_10_port);
U2594 : AOI221XL port map( A0 => n2115, A1 => BOOTH_instance_n352, B0 =>
BOOTH_instance_n320, B1 => BOOTH_instance_n353, C0
=> BOOTH_instance_n370, Y => BOOTH_instance_n369);
U2595 : OAI22XL port map( A0 => BOOTH_instance_n349, A1 => n1647, B0 =>
BOOTH_instance_n350, B1 => BOOTH_instance_n290, Y =>
BOOTH_instance_n370);
U2596 : AO22XL port map( A0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_S1_0_port,
A1 => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_7_port
, B0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_S0_0_port,
B1 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_n2, Y
=> ALU_instance_ADDER_OUT_28_port);
U2597 : XNOR2XL port map( A => n1690, B => ALU_instance_INTERNAL_B_28_port,
Y =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_S1_0_port);
U2598 : XOR2XL port map( A => ALU_instance_INTERNAL_B_28_port, B => n1690, Y
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_S0_0_port
);
U2599 : AO22XL port map( A0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_S1_0_port,
A1 => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_6_port
, B0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_S0_0_port,
B1 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_n2, Y
=> ALU_instance_ADDER_OUT_24_port);
U2600 : XNOR2XL port map( A => n1685, B => ALU_instance_INTERNAL_B_24_port,
Y =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_S1_0_port);
U2601 : XOR2XL port map( A => ALU_instance_INTERNAL_B_24_port, B => n1685, Y
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_S0_0_port
);
U2602 : OAI2BB1XL port map( A0N => n1528, A1N => n1399, B0 => n1525, Y =>
n1558);
U2603 : XOR2XL port map( A => N4839, B => n1648, Y => BOOTH_instance_n322);
U2604 : OR3XL port map( A => N4834, B => N4835, C => BOOTH_instance_n346, Y
=> n1706);
U2605 : OR3XL port map( A => N4832, B => N4833, C => BOOTH_instance_n372, Y
=> n1707);
U2606 : AND3XL port map( A => n1577, B => n1566, C => n1563, Y => n1708);
U2607 : INVXL port map( A => n1581, Y => n1567);
U2608 : INVXL port map( A => N4837, Y => BOOTH_instance_n347);
U2609 : INVXL port map( A => n1569, Y => n1400);
U2610 : OR2XL port map( A => n1397, B => n1528, Y => n1547);
U2611 : OR2XL port map( A => ALU_instance_INTERNAL_B_4_port, B => n2190, Y
=>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_RCA1_add_1_root_add_20_2_carry_1_port);
U2612 : AND2XL port map( A => ALU_instance_INTERNAL_B_0_port, B => n2111, Y
=>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_0_RCA0_add_1_root_add_20_2_carry_1_port);
U2613 : AND2XL port map( A => ALU_instance_INTERNAL_B_4_port, B => n2190, Y
=>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_1_RCA0_add_1_root_add_20_2_carry_1_port);
U2614 : INVXL port map( A => BOOTH_instance_n430, Y =>
BOOTH_instance_decoded_1_4_port);
U2615 : AOI221XL port map( A0 => n2115, A1 => BOOTH_instance_n424, B0 =>
BOOTH_instance_n320, B1 => BOOTH_instance_n425, C0
=> BOOTH_instance_n431, Y => BOOTH_instance_n430);
U2616 : OAI221XL port map( A0 => BOOTH_instance_n260, A1 =>
BOOTH_instance_n421, B0 => BOOTH_instance_n259, B1
=> BOOTH_instance_n422, C0 => BOOTH_instance_n426, Y
=> BOOTH_instance_decoded_1_8_port);
U2617 : OAI222XL port map( A0 => BOOTH_instance_n249, A1 => n2127, B0 =>
BOOTH_instance_n239, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n22, C0 => n2188,
C1 => BOOTH_instance_n447, Y =>
BOOTH_instance_N217_port);
U2618 : AOI22XL port map( A0 => BOOTH_instance_n424, A1 => n2118, B0 =>
BOOTH_instance_n425, B1 => n1596, Y =>
BOOTH_instance_n426);
U2619 : INVXL port map( A => BOOTH_instance_n378, Y =>
BOOTH_instance_decoded_3_8_port);
U2620 : OAI221XL port map( A0 => n2191, A1 => BOOTH_instance_n397, B0 =>
BOOTH_instance_n299, B1 => BOOTH_instance_n398, C0
=> BOOTH_instance_n402, Y =>
BOOTH_instance_decoded_2_8_port);
U2621 : AOI221XL port map( A0 => n2116, A1 => BOOTH_instance_n376, B0 =>
BOOTH_instance_n320, B1 => BOOTH_instance_n377, C0
=> BOOTH_instance_n379, Y => BOOTH_instance_n378);
U2622 : OAI221XL port map( A0 => n1607, A1 => BOOTH_instance_n421, B0 =>
BOOTH_instance_n249, B1 => BOOTH_instance_n422, C0
=> BOOTH_instance_n423, Y =>
BOOTH_instance_decoded_1_9_port);
U2623 : OAI222XL port map( A0 => BOOTH_instance_n239, A1 => n2127, B0 =>
BOOTH_instance_n229, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n22, C0 => n2186,
C1 => BOOTH_instance_n447, Y =>
BOOTH_instance_N218_port);
U2624 : AOI22XL port map( A0 => BOOTH_instance_n424, A1 => n2120, B0 =>
BOOTH_instance_n425, B1 => BOOTH_instance_n252, Y =>
BOOTH_instance_n423);
U2625 : OAI221XL port map( A0 => n2188, A1 => BOOTH_instance_n421, B0 =>
BOOTH_instance_n239, B1 => BOOTH_instance_n422, C0
=> BOOTH_instance_n442, Y =>
BOOTH_instance_decoded_1_10_port);
U2626 : OAI222XL port map( A0 => BOOTH_instance_n229, A1 => n2127, B0 =>
BOOTH_instance_n219, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n22, C0 => n2184,
C1 => BOOTH_instance_n447, Y =>
BOOTH_instance_N219_port);
U2627 : AOI22XL port map( A0 => BOOTH_instance_n424, A1 => n2189, B0 =>
BOOTH_instance_n425, B1 => BOOTH_instance_n242, Y =>
BOOTH_instance_n442);
U2628 : OAI221XL port map( A0 => n2184, A1 => BOOTH_instance_n421, B0 =>
BOOTH_instance_n219, B1 => BOOTH_instance_n422, C0
=> BOOTH_instance_n440, Y =>
BOOTH_instance_decoded_1_12_port);
U2629 : OAI222XL port map( A0 => BOOTH_instance_n209, A1 => n2127, B0 =>
BOOTH_instance_n199, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n22, C0 => n2180,
C1 => BOOTH_instance_n447, Y =>
BOOTH_instance_N221_port);
U2630 : AOI22XL port map( A0 => BOOTH_instance_n424, A1 => n2185, B0 =>
BOOTH_instance_n425, B1 => BOOTH_instance_n222, Y =>
BOOTH_instance_n440);
U2631 : OAI221XL port map( A0 => BOOTH_instance_n260, A1 =>
BOOTH_instance_n373, B0 => BOOTH_instance_n259, B1
=> BOOTH_instance_n374, C0 => BOOTH_instance_n392, Y
=> BOOTH_instance_decoded_3_12_port);
U2632 : OAI221XL port map( A0 => n2188, A1 => BOOTH_instance_n397, B0 =>
BOOTH_instance_n239, B1 => BOOTH_instance_n398, C0
=> BOOTH_instance_n416, Y =>
BOOTH_instance_decoded_2_12_port);
U2633 : AOI22XL port map( A0 => BOOTH_instance_n376, A1 => N4723, B0 =>
BOOTH_instance_n377, B1 => n1596, Y =>
BOOTH_instance_n392);
U2634 : OAI221XL port map( A0 => n1607, A1 => BOOTH_instance_n373, B0 =>
BOOTH_instance_n249, B1 => BOOTH_instance_n374, C0
=> BOOTH_instance_n391, Y =>
BOOTH_instance_decoded_3_13_port);
U2635 : OAI221XL port map( A0 => n2186, A1 => BOOTH_instance_n397, B0 =>
BOOTH_instance_n229, B1 => BOOTH_instance_n398, C0
=> BOOTH_instance_n415, Y =>
BOOTH_instance_decoded_2_13_port);
U2636 : AOI22XL port map( A0 => BOOTH_instance_n376, A1 => N4724, B0 =>
BOOTH_instance_n377, B1 => BOOTH_instance_n252, Y =>
BOOTH_instance_n391);
U2637 : OAI221XL port map( A0 => n2188, A1 => BOOTH_instance_n373, B0 =>
BOOTH_instance_n239, B1 => BOOTH_instance_n374, C0
=> BOOTH_instance_n390, Y =>
BOOTH_instance_decoded_3_14_port);
U2638 : OAI221XL port map( A0 => n2184, A1 => BOOTH_instance_n397, B0 =>
BOOTH_instance_n219, B1 => BOOTH_instance_n398, C0
=> BOOTH_instance_n414, Y =>
BOOTH_instance_decoded_2_14_port);
U2639 : AOI22XL port map( A0 => BOOTH_instance_n376, A1 => n2189, B0 =>
BOOTH_instance_n377, B1 => BOOTH_instance_n242, Y =>
BOOTH_instance_n390);
U2640 : OAI221XL port map( A0 => n2184, A1 => BOOTH_instance_n373, B0 =>
BOOTH_instance_n219, B1 => BOOTH_instance_n374, C0
=> BOOTH_instance_n388, Y =>
BOOTH_instance_decoded_3_16_port);
U2641 : OAI221XL port map( A0 => n2180, A1 => BOOTH_instance_n397, B0 =>
BOOTH_instance_n199, B1 => BOOTH_instance_n398, C0
=> BOOTH_instance_n412, Y =>
BOOTH_instance_decoded_2_16_port);
U2642 : AOI22XL port map( A0 => BOOTH_instance_n376, A1 => n2185, B0 =>
BOOTH_instance_n377, B1 => BOOTH_instance_n222, Y =>
BOOTH_instance_n388);
U2643 : OAI221XL port map( A0 => BOOTH_instance_n260, A1 =>
BOOTH_instance_n328, B0 => BOOTH_instance_n259, B1
=> BOOTH_instance_n323, C0 => BOOTH_instance_n338, Y
=> BOOTH_instance_decoded_5_16_port);
U2644 : OAI221XL port map( A0 => n2188, A1 => BOOTH_instance_n349, B0 =>
BOOTH_instance_n239, B1 => BOOTH_instance_n350, C0
=> BOOTH_instance_n363, Y =>
BOOTH_instance_decoded_4_16_port);
U2645 : AOI22XL port map( A0 => BOOTH_instance_n326, A1 => n2117, B0 =>
BOOTH_instance_n327, B1 => n1596, Y =>
BOOTH_instance_n338);
U2646 : OAI221XL port map( A0 => n1607, A1 => BOOTH_instance_n328, B0 =>
BOOTH_instance_n249, B1 => BOOTH_instance_n323, C0
=> BOOTH_instance_n337, Y =>
BOOTH_instance_decoded_5_17_port);
U2647 : OAI221XL port map( A0 => n2186, A1 => BOOTH_instance_n349, B0 =>
BOOTH_instance_n229, B1 => BOOTH_instance_n350, C0
=> BOOTH_instance_n362, Y =>
BOOTH_instance_decoded_4_17_port);
U2648 : AOI22XL port map( A0 => BOOTH_instance_n326, A1 => n2119, B0 =>
BOOTH_instance_n327, B1 => BOOTH_instance_n252, Y =>
BOOTH_instance_n337);
U2649 : NOR2XL port map( A => BOOTH_instance_n315, B => n1647, Y =>
BOOTH_instance_decoded_8_18_port);
U2650 : OAI221XL port map( A0 => n2188, A1 => BOOTH_instance_n328, B0 =>
BOOTH_instance_n239, B1 => BOOTH_instance_n323, C0
=> BOOTH_instance_n336, Y =>
BOOTH_instance_decoded_5_18_port);
U2651 : OAI221XL port map( A0 => n2184, A1 => BOOTH_instance_n349, B0 =>
BOOTH_instance_n219, B1 => BOOTH_instance_n350, C0
=> BOOTH_instance_n361, Y =>
BOOTH_instance_decoded_4_18_port);
U2652 : AOI22XL port map( A0 => BOOTH_instance_n326, A1 => n2189, B0 =>
BOOTH_instance_n327, B1 => BOOTH_instance_n242, Y =>
BOOTH_instance_n336);
U2653 : OAI221XL port map( A0 => n2184, A1 => BOOTH_instance_n328, B0 =>
BOOTH_instance_n219, B1 => BOOTH_instance_n323, C0
=> BOOTH_instance_n334, Y =>
BOOTH_instance_decoded_5_20_port);
U2654 : OAI221XL port map( A0 => n2180, A1 => BOOTH_instance_n349, B0 =>
BOOTH_instance_n199, B1 => BOOTH_instance_n350, C0
=> BOOTH_instance_n359, Y =>
BOOTH_instance_decoded_4_20_port);
U2655 : AOI22XL port map( A0 => BOOTH_instance_n326, A1 => n2185, B0 =>
BOOTH_instance_n327, B1 => BOOTH_instance_n222, Y =>
BOOTH_instance_n334);
U2656 : NOR2XL port map( A => BOOTH_instance_n315, B => n2184, Y =>
BOOTH_instance_decoded_8_26_port);
U2657 : INVXL port map( A => n2111, Y => n2113);
U2658 : AO22XL port map( A0 => EX_MULT_OUT_30_port, A1 => n2145, B0 =>
EX_ALU_OUT_30_port, B1 => n2144, Y => N4890);
U2659 : OAI2BB1XL port map( A0N => ALU_instance_ADDER_OUT_30_port, A1N =>
n1599, B0 => ALU_instance_n24, Y =>
EX_ALU_OUT_30_port);
U2660 : AOI22XL port map( A0 => ALU_instance_SHIFTER_OUT_30_port, A1 =>
ALU_instance_n5, B0 =>
ALU_instance_LOGIC_OUT_30_port, B1 =>
ALU_instance_n6, Y => ALU_instance_n24);
U2661 : OAI2B2XL port map( A1N => N4857, A0 =>
ALU_instance_LOGIC_GENERIC_I_n57, B0 => N4857, B1 =>
ALU_instance_LOGIC_GENERIC_I_n58, Y =>
ALU_instance_LOGIC_OUT_30_port);
U2662 : AO22XL port map( A0 => EX_MULT_OUT_29_port, A1 => n2145, B0 =>
EX_ALU_OUT_29_port, B1 => n2144, Y => N4889);
U2663 : OAI2BB1XL port map( A0N => ALU_instance_ADDER_OUT_29_port, A1N =>
n1599, B0 => ALU_instance_n25, Y =>
EX_ALU_OUT_29_port);
U2664 : AOI22XL port map( A0 => ALU_instance_SHIFTER_OUT_29_port, A1 =>
ALU_instance_n5, B0 =>
ALU_instance_LOGIC_OUT_29_port, B1 =>
ALU_instance_n6, Y => ALU_instance_n25);
U2665 : OAI2B2XL port map( A1N => N4856, A0 =>
ALU_instance_LOGIC_GENERIC_I_n63, B0 => N4856, B1 =>
ALU_instance_LOGIC_GENERIC_I_n64, Y =>
ALU_instance_LOGIC_OUT_29_port);
U2666 : AO22XL port map( A0 => EX_MULT_OUT_28_port, A1 => n2145, B0 =>
EX_ALU_OUT_28_port, B1 => n2144, Y => N4888);
U2667 : OAI2BB1XL port map( A0N => ALU_instance_ADDER_OUT_28_port, A1N =>
n1599, B0 => ALU_instance_n26, Y =>
EX_ALU_OUT_28_port);
U2668 : AOI22XL port map( A0 => ALU_instance_SHIFTER_OUT_28_port, A1 =>
ALU_instance_n5, B0 =>
ALU_instance_LOGIC_OUT_28_port, B1 =>
ALU_instance_n6, Y => ALU_instance_n26);
U2669 : OAI2B2XL port map( A1N => N4855, A0 =>
ALU_instance_LOGIC_GENERIC_I_n66, B0 => N4855, B1 =>
ALU_instance_LOGIC_GENERIC_I_n67, Y =>
ALU_instance_LOGIC_OUT_28_port);
U2670 : AO22XL port map( A0 => EX_MULT_OUT_27_port, A1 => n2145, B0 =>
EX_ALU_OUT_27_port, B1 => n2144, Y => N4887);
U2671 : OAI2BB1XL port map( A0N => ALU_instance_ADDER_OUT_27_port, A1N =>
n1599, B0 => ALU_instance_n27, Y =>
EX_ALU_OUT_27_port);
U2672 : AOI22XL port map( A0 => ALU_instance_SHIFTER_OUT_27_port, A1 =>
n2138, B0 => ALU_instance_LOGIC_OUT_27_port, B1 =>
ALU_instance_n6, Y => ALU_instance_n27);
U2673 : OAI2B2XL port map( A1N => N4854, A0 =>
ALU_instance_LOGIC_GENERIC_I_n69, B0 => N4854, B1 =>
ALU_instance_LOGIC_GENERIC_I_n70, Y =>
ALU_instance_LOGIC_OUT_27_port);
U2674 : AO22XL port map( A0 => EX_MULT_OUT_26_port, A1 => n2145, B0 =>
EX_ALU_OUT_26_port, B1 => n2144, Y => N4886);
U2675 : OAI2BB1XL port map( A0N => ALU_instance_ADDER_OUT_26_port, A1N =>
n1599, B0 => ALU_instance_n28, Y =>
EX_ALU_OUT_26_port);
U2676 : AOI22XL port map( A0 => ALU_instance_SHIFTER_OUT_26_port, A1 =>
n2138, B0 => ALU_instance_LOGIC_OUT_26_port, B1 =>
n2139, Y => ALU_instance_n28);
U2677 : OAI2B2XL port map( A1N => N4853, A0 =>
ALU_instance_LOGIC_GENERIC_I_n72, B0 => N4853, B1 =>
ALU_instance_LOGIC_GENERIC_I_n73, Y =>
ALU_instance_LOGIC_OUT_26_port);
U2678 : AO22XL port map( A0 => EX_MULT_OUT_25_port, A1 => n2145, B0 =>
EX_ALU_OUT_25_port, B1 => n2144, Y => N4885);
U2679 : OAI2BB1XL port map( A0N => ALU_instance_ADDER_OUT_25_port, A1N =>
n1599, B0 => ALU_instance_n29, Y =>
EX_ALU_OUT_25_port);
U2680 : AOI22XL port map( A0 => ALU_instance_SHIFTER_OUT_25_port, A1 =>
n2138, B0 => ALU_instance_LOGIC_OUT_25_port, B1 =>
n2139, Y => ALU_instance_n29);
U2681 : OAI2B2XL port map( A1N => N4852, A0 =>
ALU_instance_LOGIC_GENERIC_I_n75, B0 => N4852, B1 =>
ALU_instance_LOGIC_GENERIC_I_n76, Y =>
ALU_instance_LOGIC_OUT_25_port);
U2682 : AO22XL port map( A0 => EX_MULT_OUT_24_port, A1 => n2145, B0 =>
EX_ALU_OUT_24_port, B1 => n2144, Y => N4884);
U2683 : OAI2BB1XL port map( A0N => ALU_instance_ADDER_OUT_24_port, A1N =>
n1599, B0 => ALU_instance_n30, Y =>
EX_ALU_OUT_24_port);
U2684 : AOI22XL port map( A0 => ALU_instance_SHIFTER_OUT_24_port, A1 =>
ALU_instance_n5, B0 =>
ALU_instance_LOGIC_OUT_24_port, B1 => n2139, Y =>
ALU_instance_n30);
U2685 : OAI2B2XL port map( A1N => N4851, A0 =>
ALU_instance_LOGIC_GENERIC_I_n78, B0 => N4851, B1 =>
ALU_instance_LOGIC_GENERIC_I_n79, Y =>
ALU_instance_LOGIC_OUT_24_port);
U2686 : AO22XL port map( A0 => EX_MULT_OUT_23_port, A1 => n2145, B0 =>
EX_ALU_OUT_23_port, B1 => n2144, Y => N4883);
U2687 : OAI2BB1XL port map( A0N => ALU_instance_ADDER_OUT_23_port, A1N =>
n1599, B0 => ALU_instance_n31, Y =>
EX_ALU_OUT_23_port);
U2688 : AOI22XL port map( A0 => ALU_instance_SHIFTER_OUT_23_port, A1 =>
n2138, B0 => ALU_instance_LOGIC_OUT_23_port, B1 =>
n2139, Y => ALU_instance_n31);
U2689 : OAI2B2XL port map( A1N => N4850, A0 =>
ALU_instance_LOGIC_GENERIC_I_n81, B0 => N4850, B1 =>
ALU_instance_LOGIC_GENERIC_I_n82, Y =>
ALU_instance_LOGIC_OUT_23_port);
U2690 : AO22XL port map( A0 => EX_MULT_OUT_22_port, A1 => n2145, B0 =>
EX_ALU_OUT_22_port, B1 => n2144, Y => N4882);
U2691 : OAI2BB1XL port map( A0N => ALU_instance_ADDER_OUT_22_port, A1N =>
n1599, B0 => ALU_instance_n32, Y =>
EX_ALU_OUT_22_port);
U2692 : AOI22XL port map( A0 => ALU_instance_SHIFTER_OUT_22_port, A1 =>
n2138, B0 => ALU_instance_LOGIC_OUT_22_port, B1 =>
n2139, Y => ALU_instance_n32);
U2693 : OAI2B2XL port map( A1N => N4849, A0 =>
ALU_instance_LOGIC_GENERIC_I_n84, B0 => N4849, B1 =>
ALU_instance_LOGIC_GENERIC_I_n85, Y =>
ALU_instance_LOGIC_OUT_22_port);
U2694 : AO22XL port map( A0 => EX_MULT_OUT_21_port, A1 => n2145, B0 =>
EX_ALU_OUT_21_port, B1 => n2144, Y => N4881);
U2695 : OAI2BB1XL port map( A0N => ALU_instance_ADDER_OUT_21_port, A1N =>
n1599, B0 => ALU_instance_n33, Y =>
EX_ALU_OUT_21_port);
U2696 : AOI22XL port map( A0 => ALU_instance_SHIFTER_OUT_21_port, A1 =>
n2138, B0 => ALU_instance_LOGIC_OUT_21_port, B1 =>
n2139, Y => ALU_instance_n33);
U2697 : OAI2B2XL port map( A1N => N4848, A0 =>
ALU_instance_LOGIC_GENERIC_I_n87, B0 => N4848, B1 =>
ALU_instance_LOGIC_GENERIC_I_n88, Y =>
ALU_instance_LOGIC_OUT_21_port);
U2698 : AO22XL port map( A0 => EX_MULT_OUT_20_port, A1 => n2145, B0 =>
EX_ALU_OUT_20_port, B1 => n2144, Y => N4880);
U2699 : OAI2BB1XL port map( A0N => ALU_instance_ADDER_OUT_20_port, A1N =>
n1599, B0 => ALU_instance_n34, Y =>
EX_ALU_OUT_20_port);
U2700 : AOI22XL port map( A0 => ALU_instance_SHIFTER_OUT_20_port, A1 =>
n2138, B0 => ALU_instance_LOGIC_OUT_20_port, B1 =>
n2139, Y => ALU_instance_n34);
U2701 : OAI2B2XL port map( A1N => N4847, A0 =>
ALU_instance_LOGIC_GENERIC_I_n90, B0 => N4847, B1 =>
ALU_instance_LOGIC_GENERIC_I_n91, Y =>
ALU_instance_LOGIC_OUT_20_port);
U2702 : AO22XL port map( A0 => EX_MULT_OUT_19_port, A1 => n2145, B0 =>
EX_ALU_OUT_19_port, B1 => n2144, Y => N4879);
U2703 : OAI2BB1XL port map( A0N => ALU_instance_ADDER_OUT_19_port, A1N =>
n1599, B0 => ALU_instance_n35, Y =>
EX_ALU_OUT_19_port);
U2704 : AOI22XL port map( A0 => ALU_instance_SHIFTER_OUT_19_port, A1 =>
n2138, B0 => ALU_instance_LOGIC_OUT_19_port, B1 =>
n2139, Y => ALU_instance_n35);
U2705 : OAI2B2XL port map( A1N => N4846, A0 =>
ALU_instance_LOGIC_GENERIC_I_n96, B0 => N4846, B1 =>
ALU_instance_LOGIC_GENERIC_I_n97, Y =>
ALU_instance_LOGIC_OUT_19_port);
U2706 : AO22XL port map( A0 => EX_MULT_OUT_18_port, A1 => n2145, B0 =>
EX_ALU_OUT_18_port, B1 => n2144, Y => N4878);
U2707 : OAI2BB1XL port map( A0N => ALU_instance_ADDER_OUT_18_port, A1N =>
n1599, B0 => ALU_instance_n36, Y =>
EX_ALU_OUT_18_port);
U2708 : AOI22XL port map( A0 => ALU_instance_SHIFTER_OUT_18_port, A1 =>
n2138, B0 => ALU_instance_LOGIC_OUT_18_port, B1 =>
n2139, Y => ALU_instance_n36);
U2709 : OAI2B2XL port map( A1N => N4845, A0 =>
ALU_instance_LOGIC_GENERIC_I_n99, B0 => N4845, B1 =>
ALU_instance_LOGIC_GENERIC_I_n100, Y =>
ALU_instance_LOGIC_OUT_18_port);
U2710 : INVXL port map( A => n1648, Y => BOOTH_instance_n345);
U2711 : INVXL port map( A => n2167, Y => n2173);
U2712 : OAI221XL port map( A0 => n2127, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n113, B0 => n2129
, B1 => ALU_instance_SHIFTER_GENERIC_I_C86_n119, C0
=> ALU_instance_SHIFTER_GENERIC_I_C86_n120, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n15);
U2713 : AOI22XL port map( A0 => n1689, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n25, B0 => n1688,
B1 => n2126, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n120);
U2714 : OAI221XL port map( A0 => n2127, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n119, B0 => n2129
, B1 => ALU_instance_SHIFTER_GENERIC_I_C50_n113, C0
=> ALU_instance_SHIFTER_GENERIC_I_C86_n124, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n30);
U2715 : AOI22XL port map( A0 => n1679, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n25, B0 => n1689,
B1 => n2126, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n124);
U2716 : OAI221XL port map( A0 => n2127, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n113, B0 => n2129
, B1 => n1670, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n128, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n39);
U2717 : AOI22XL port map( A0 => n1684, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n25, B0 => n1679,
B1 => n2126, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n128);
U2718 : AOI22XL port map( A0 => n2190, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n25, B0 => N4723,
B1 => ALU_instance_SHIFTER_GENERIC_I_C48_n50, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n159);
U2719 : AOI22XL port map( A0 => n2119, A1 => n2130, B0 => n2189, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n50, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n174);
U2720 : AOI22XL port map( A0 => n2117, A1 => n2130, B0 => N4724, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n50, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n179);
U2721 : AO22XL port map( A0 => n1651, A1 => n2125, B0 => n2177, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n49, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n146);
U2722 : AO22XL port map( A0 => n2177, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n48, B0 => n2178,
B1 => ALU_instance_SHIFTER_GENERIC_I_C50_n49, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n128);
U2723 : AO22XL port map( A0 => n2178, A1 => n2125, B0 => n2179, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n49, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n156);
U2724 : OAI221XL port map( A0 => n2127, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n86, B0 => n2129,
B1 => ALU_instance_SHIFTER_GENERIC_I_C86_n93, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n94, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n19);
U2725 : AOI22XL port map( A0 => n1687, A1 => n2130, B0 => n1678, B1 => n2126
, Y => ALU_instance_SHIFTER_GENERIC_I_C86_n94);
U2726 : OAI221XL port map( A0 => n2127, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n93, B0 => n2129,
B1 => ALU_instance_SHIFTER_GENERIC_I_C48_n125, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n102, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n32);
U2727 : AOI22XL port map( A0 => n1686, A1 => n2130, B0 => n1687, B1 => n2126
, Y => ALU_instance_SHIFTER_GENERIC_I_C86_n102);
U2728 : OAI221XL port map( A0 => n2128, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n125, B0 => n2129
, B1 => ALU_instance_SHIFTER_GENERIC_I_C50_n128, C0
=> ALU_instance_SHIFTER_GENERIC_I_C86_n107, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n41);
U2729 : AOI22XL port map( A0 => n1683, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n25, B0 => n1686,
B1 => n2126, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n107);
U2730 : OAI221XL port map( A0 => n2128, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n128, B0 => n2129
, B1 => ALU_instance_SHIFTER_GENERIC_I_C86_n113, C0
=> ALU_instance_SHIFTER_GENERIC_I_C86_n114, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n49);
U2731 : AOI22XL port map( A0 => n1688, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n25, B0 => n1683,
B1 => n2126, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n114);
U2732 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n44, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n21, B0 =>
n2129, B1 => ALU_instance_SHIFTER_GENERIC_I_C48_n140
, C0 => ALU_instance_SHIFTER_GENERIC_I_C48_n141, Y
=> ALU_instance_SHIFTER_GENERIC_I_C48_n76);
U2733 : AOI22XL port map( A0 => n1690, A1 => n2125, B0 => n1681, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n50, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n141);
U2734 : OAI221XL port map( A0 => n2128, A1 => n1647, B0 =>
BOOTH_instance_n307, B1 => n2129, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n168, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n82);
U2735 : AOI22XL port map( A0 => n2130, A1 => N4721, B0 => n2190, B1 => n2126
, Y => ALU_instance_SHIFTER_GENERIC_I_C86_n168);
U2736 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n43, A1
=> ALU_instance_SHIFTER_GENERIC_I_C50_n139, B0 =>
n2123, B1 => ALU_instance_SHIFTER_GENERIC_I_C48_n140
, C0 => ALU_instance_SHIFTER_GENERIC_I_C50_n159, Y
=> ALU_instance_SHIFTER_GENERIC_I_C50_n65);
U2737 : AOI22XL port map( A0 => n1682, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n48, B0 => n1690,
B1 => ALU_instance_SHIFTER_GENERIC_I_C50_n49, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n159);
U2738 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_n37, B =>
ALU_instance_SHIFTER_GENERIC_I_n38, Y =>
ALU_instance_SHIFTER_OUT_31_port);
U2739 : NAND2XL port map( A => ALU_instance_SHIFTER_GENERIC_I_N265, B =>
n2134, Y => ALU_instance_SHIFTER_GENERIC_I_n37);
U2740 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_N233, A1 =>
n2131, B0 => n1692, B1 => n1616, C0 =>
ALU_instance_SHIFTER_GENERIC_I_N168, C1 => n2133, Y
=> ALU_instance_SHIFTER_GENERIC_I_n38);
U2741 : OAI221XL port map( A0 => n2127, A1 => n1608, B0 => n2129, B1 =>
n2180, C0 => ALU_instance_SHIFTER_GENERIC_I_C86_n143
, Y => ALU_instance_SHIFTER_GENERIC_I_C86_n56);
U2742 : AOI22XL port map( A0 => n2177, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n25, B0 => n1651,
B1 => ALU_instance_SHIFTER_GENERIC_I_C48_n50, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n143);
U2743 : OAI221XL port map( A0 => n2127, A1 => n2182, B0 => n2129, B1 =>
n2184, C0 => ALU_instance_SHIFTER_GENERIC_I_C86_n153
, Y => ALU_instance_SHIFTER_GENERIC_I_C86_n67);
U2744 : AOI22XL port map( A0 => n2179, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n25, B0 => n2178,
B1 => ALU_instance_SHIFTER_GENERIC_I_C48_n50, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n153);
U2745 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n44, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n140, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n22, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n139, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n159, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n74);
U2746 : AOI22XL port map( A0 => n1682, A1 => n2125, B0 => n1690, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n50, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n159);
U2747 : OAI221XL port map( A0 => n2127, A1 => n2184, B0 => n2129, B1 =>
n2186, C0 => ALU_instance_SHIFTER_GENERIC_I_C86_n165
, Y => ALU_instance_SHIFTER_GENERIC_I_C86_n81);
U2748 : AOI22XL port map( A0 => n2181, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n25, B0 => n2179,
B1 => ALU_instance_SHIFTER_GENERIC_I_C48_n50, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n165);
U2749 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n44, A1
=> ALU_instance_SHIFTER_GENERIC_I_C50_n128, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n125, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n22, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n160, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n16);
U2750 : AOI22XL port map( A0 => n1679, A1 => n2125, B0 => n1684, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n50, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n160);
U2751 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n44, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n50, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n46, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n42, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n134, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n77);
U2752 : AOI22XL port map( A0 => n1685, A1 => n2125, B0 => n1678, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n50, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n134);
U2753 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n43, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n125, B0 =>
n2123, B1 => ALU_instance_SHIFTER_GENERIC_I_C50_n128
, C0 => ALU_instance_SHIFTER_GENERIC_I_C50_n160, Y
=> ALU_instance_SHIFTER_GENERIC_I_C50_n17);
U2754 : AOI22XL port map( A0 => n1679, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n48, B0 => n1684,
B1 => ALU_instance_SHIFTER_GENERIC_I_C50_n49, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n160);
U2755 : OAI221XL port map( A0 => n2122, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n50, B0 => n2123,
B1 => ALU_instance_SHIFTER_GENERIC_I_C86_n58, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n145, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n78);
U2756 : AOI22XL port map( A0 => n1678, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n48, B0 => n1687,
B1 => n2126, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n145);
U2757 : OAI221XL port map( A0 => n2122, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n140, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n44, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n21, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n138, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n73);
U2758 : AOI22XL port map( A0 => n1690, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n48, B0 => n1681,
B1 => n2126, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n138);
U2759 : OAI221XL port map( A0 => n2122, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n23, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n45, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n33, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n111, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n68);
U2760 : AOI22XL port map( A0 => n1680, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n48, B0 => n1677,
B1 => ALU_instance_SHIFTER_GENERIC_I_C50_n49, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n111);
U2761 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n44, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n58, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n22, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n50, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n144, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n84);
U2762 : AOI22XL port map( A0 => n1678, A1 => n2125, B0 => n1687, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n50, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n144);
U2763 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n44, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n64, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n22, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n58, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n124, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n11);
U2764 : AOI22XL port map( A0 => n1687, A1 => n2125, B0 => n1686, B1 => n2126
, Y => ALU_instance_SHIFTER_GENERIC_I_C48_n124);
U2765 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n44, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n125, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n22, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n93, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n127, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n9);
U2766 : AOI22XL port map( A0 => n1689, A1 => n2125, B0 => n1679, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n50, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n127);
U2767 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n125, A1
=> n1644, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n128, B1 => n1643
, C0 => ALU_instance_SHIFTER_GENERIC_I_C48_n145, Y
=> ALU_instance_SHIFTER_GENERIC_I_C48_n29);
U2768 : AOI22XL port map( A0 => n1683, A1 => n2124, B0 => n1686, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n52, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n145);
U2769 : OAI221XL port map( A0 => n2122, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n58, B0 => n2123,
B1 => ALU_instance_SHIFTER_GENERIC_I_C86_n64, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n107, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n11);
U2770 : AOI22XL port map( A0 => n1687, A1 => n2125, B0 => n1686, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n49, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n107);
U2771 : OAI221XL port map( A0 => BOOTH_instance_n158, A1 =>
BOOTH_instance_n259, B0 => BOOTH_instance_n166, B1
=> BOOTH_instance_n260, C0 => BOOTH_instance_n261, Y
=> BOOTH_instance_n253);
U2772 : AOI22XL port map( A0 => n2118, A1 => BOOTH_instance_n168, B0 =>
n1596, B1 => BOOTH_instance_n150, Y =>
BOOTH_instance_n261);
U2773 : OAI221XL port map( A0 => BOOTH_instance_n158, A1 =>
BOOTH_instance_n249, B0 => BOOTH_instance_n166, B1
=> n1607, C0 => BOOTH_instance_n251, Y =>
BOOTH_instance_n243);
U2774 : AOI22XL port map( A0 => n2120, A1 => BOOTH_instance_n168, B0 =>
BOOTH_instance_n252, B1 => BOOTH_instance_n150, Y =>
BOOTH_instance_n251);
U2775 : OAI221XL port map( A0 => BOOTH_instance_n158, A1 =>
BOOTH_instance_n219, B0 => BOOTH_instance_n166, B1
=> n2184, C0 => BOOTH_instance_n221, Y =>
BOOTH_instance_n213);
U2776 : AOI22XL port map( A0 => n2185, A1 => BOOTH_instance_n168, B0 =>
BOOTH_instance_n222, B1 => BOOTH_instance_n150, Y =>
BOOTH_instance_n221);
U2777 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n43, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n21, B0 =>
n2123, B1 => ALU_instance_SHIFTER_GENERIC_I_C86_n23,
C0 => ALU_instance_SHIFTER_GENERIC_I_C50_n148, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n76);
U2778 : AOI22XL port map( A0 => n1681, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n48, B0 => n1680,
B1 => n2126, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n148);
U2779 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n43, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n33, B0 =>
n2123, B1 => ALU_instance_SHIFTER_GENERIC_I_C86_n42,
C0 => ALU_instance_SHIFTER_GENERIC_I_C50_n158, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n72);
U2780 : AOI22XL port map( A0 => n1677, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n48, B0 => n1685,
B1 => n2126, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n158);
U2781 : AOI22XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n49, A1
=> n1691, B0 => n2125, B1 => n1692, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n55);
U2782 : OAI221XL port map( A0 => BOOTH_instance_n186, A1 =>
BOOTH_instance_n260, B0 => n1606, B1 =>
BOOTH_instance_n259, C0 => BOOTH_instance_n278, Y =>
BOOTH_instance_n274);
U2783 : AOI22XL port map( A0 => N4723, A1 => BOOTH_instance_n188, B0 =>
n1596, B1 => BOOTH_instance_n176, Y =>
BOOTH_instance_n278);
U2784 : OAI221XL port map( A0 => BOOTH_instance_n186, A1 => n1607, B0 =>
n1606, B1 => BOOTH_instance_n249, C0 =>
BOOTH_instance_n268, Y => BOOTH_instance_n264);
U2785 : AOI22XL port map( A0 => N4724, A1 => BOOTH_instance_n188, B0 =>
BOOTH_instance_n252, B1 => BOOTH_instance_n176, Y =>
BOOTH_instance_n268);
U2786 : OAI221XL port map( A0 => BOOTH_instance_n186, A1 => n2184, B0 =>
n1606, B1 => BOOTH_instance_n219, C0 =>
BOOTH_instance_n238, Y => BOOTH_instance_n234);
U2787 : AOI22XL port map( A0 => n2185, A1 => BOOTH_instance_n188, B0 =>
BOOTH_instance_n222, B1 => BOOTH_instance_n176, Y =>
BOOTH_instance_n238);
U2788 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n44, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n42, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n46, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n33, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n158, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n75);
U2789 : AOI22XL port map( A0 => n1677, A1 => n2125, B0 => n1685, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n50, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n158);
U2790 : OAI221XL port map( A0 => BOOTH_instance_n155, A1 => n1647, B0 =>
n1721, B1 => BOOTH_instance_n290, C0 =>
BOOTH_instance_n291, Y => BOOTH_instance_n283);
U2791 : AOI22XL port map( A0 => BOOTH_instance_n292, A1 =>
BOOTH_instance_n149, B0 => N4721, B1 =>
BOOTH_instance_n282, Y => BOOTH_instance_n291);
U2792 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n10, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n15, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n41, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n150, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n8, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n37, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n149);
U2793 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n44, A1
=> n1647, B0 => n2129, B1 => n2192, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n155, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n150);
U2794 : AOI22XL port map( A0 => N4719, A1 => n2125, B0 => n2111, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n50, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n155);
U2795 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n30, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n38, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n91, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C48_n92, Y =>
ALU_instance_SHIFTER_GENERIC_I_N106);
U2796 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n10, A1
=> ALU_instance_SHIFTER_GENERIC_I_C48_n7, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n41, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n93, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n8, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n33, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n92);
U2797 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n44, A1
=> n2192, B0 => n2129, B1 => n2191, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n96, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n93);
U2798 : AOI22XL port map( A0 => n2193, A1 => n2125, B0 => N4719, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n50, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n96);
U2799 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n10, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n11, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n12, B1 => n2173,
C0 => ALU_instance_SHIFTER_GENERIC_I_C86_n13, Y =>
ALU_instance_SHIFTER_GENERIC_I_N233);
U2800 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n14, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n15, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n16, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n17, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n18, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n19, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n13);
U2801 : OAI221XL port map( A0 => n2127, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n21, B0 => n2129,
B1 => ALU_instance_SHIFTER_GENERIC_I_C86_n23, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n24, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n17);
U2802 : INVXL port map( A => n1682, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n21);
U2803 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n27, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n11, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n28, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C86_n29, Y =>
ALU_instance_SHIFTER_GENERIC_I_N232);
U2804 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n14, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n30, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n16, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n31, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n18, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n32, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n29);
U2805 : OAI221XL port map( A0 => n2127, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n23, B0 => n2129,
B1 => ALU_instance_SHIFTER_GENERIC_I_C86_n33, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n34, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n31);
U2806 : AOI22XL port map( A0 => n1682, A1 => n2130, B0 => n1691, B1 => n2126
, Y => ALU_instance_SHIFTER_GENERIC_I_C86_n34);
U2807 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n36, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n11, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n37, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C86_n38, Y =>
ALU_instance_SHIFTER_GENERIC_I_N231);
U2808 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n14, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n39, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n16, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n40, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n18, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n41, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n38);
U2809 : OAI221XL port map( A0 => n2128, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n33, B0 => n2129,
B1 => ALU_instance_SHIFTER_GENERIC_I_C86_n42, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n43, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n40);
U2810 : AOI22XL port map( A0 => n1690, A1 => n2130, B0 => n1682, B1 => n2126
, Y => ALU_instance_SHIFTER_GENERIC_I_C86_n43);
U2811 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n44, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n11, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n45, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C86_n46, Y =>
ALU_instance_SHIFTER_GENERIC_I_N230);
U2812 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n14, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n47, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n16, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n48, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n18, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n49, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n46);
U2813 : OAI221XL port map( A0 => n2128, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n42, B0 => n2129,
B1 => ALU_instance_SHIFTER_GENERIC_I_C86_n50, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n51, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n48);
U2814 : AOI22XL port map( A0 => n1681, A1 => n2130, B0 => n1690, B1 => n2126
, Y => ALU_instance_SHIFTER_GENERIC_I_C86_n51);
U2815 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n32, A1
=> ALU_instance_SHIFTER_GENERIC_I_C50_n38, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n79, B1 => n2172,
C0 => ALU_instance_SHIFTER_GENERIC_I_C50_n80, Y =>
ALU_instance_SHIFTER_GENERIC_I_N138);
U2816 : AOI222XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n10, A1
=> ALU_instance_SHIFTER_GENERIC_I_C50_n7, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n16, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n81, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n8, C1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n12, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n80);
U2817 : OAI221XL port map( A0 => n2122, A1 => n2191, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n45, B1 => n2192,
C0 => ALU_instance_SHIFTER_GENERIC_I_C50_n86, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n81);
U2818 : AOI22XL port map( A0 => n2193, A1 => n2125, B0 => N4719, B1 => n2126
, Y => ALU_instance_SHIFTER_GENERIC_I_C50_n86);
U2819 : OAI211XL port map( A0 => n1540, A1 => n1539, B0 => n1537, C0 =>
n1544, Y => n1553);
U2820 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C86_n93, A1
=> n1644, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n125, B1 => n1643
, C0 => ALU_instance_SHIFTER_GENERIC_I_C48_n135, Y
=> ALU_instance_SHIFTER_GENERIC_I_C48_n23);
U2821 : AOI22XL port map( A0 => n1686, A1 => n2124, B0 => n1687, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n52, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n135);
U2822 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n43, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n64, B0 =>
n2123, B1 => ALU_instance_SHIFTER_GENERIC_I_C50_n132
, C0 => ALU_instance_SHIFTER_GENERIC_I_C50_n161, Y
=> ALU_instance_SHIFTER_GENERIC_I_C50_n18);
U2823 : AOI22XL port map( A0 => n1686, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n48, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n49, B1 => n1683,
Y => ALU_instance_SHIFTER_GENERIC_I_C50_n161);
U2824 : OAI221XL port map( A0 => n2122, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n93, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n44, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n125, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n117, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n9);
U2825 : AOI22XL port map( A0 => n1689, A1 => n2125, B0 => n1679, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n49, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n117);
U2826 : OAI221XL port map( A0 => n2122, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n42, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n45, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n50, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n142, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n75);
U2827 : AOI22XL port map( A0 => n1685, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n48, B0 => n1678,
B1 => n2126, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n142);
U2828 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n43, A1
=> n2182, B0 => n2123, B1 => n2184, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n152, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n19);
U2829 : AOI22XL port map( A0 => n2185, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n48, B0 => n2187,
B1 => n2126, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n152);
U2830 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C48_n161, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n17);
U2831 : AOI221XL port map( A0 => n2124, A1 => n1687, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n52, B1 => n1678,
C0 => ALU_instance_SHIFTER_GENERIC_I_C48_n162, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n161);
U2832 : OAI2B2XL port map( A1N => n1686, A0 => n1644, B0 => n1643, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n93, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n162);
U2833 : XOR2XL port map( A => n2136, B => N4842, Y =>
ALU_instance_INTERNAL_B_15_port);
U2834 : XOR2XL port map( A => n2136, B => N4848, Y =>
ALU_instance_INTERNAL_B_21_port);
U2835 : XOR2XL port map( A => n2136, B => N4844, Y =>
ALU_instance_INTERNAL_B_17_port);
U2836 : XOR2XL port map( A => n2136, B => N4849, Y =>
ALU_instance_INTERNAL_B_22_port);
U2837 : XOR2XL port map( A => n2136, B => N4852, Y =>
ALU_instance_INTERNAL_B_25_port);
U2838 : XOR2XL port map( A => n2136, B => N4845, Y =>
ALU_instance_INTERNAL_B_18_port);
U2839 : XOR2XL port map( A => n2135, B => N4856, Y =>
ALU_instance_INTERNAL_B_29_port);
U2840 : XOR2XL port map( A => n2136, B => N4850, Y =>
ALU_instance_INTERNAL_B_23_port);
U2841 : XOR2XL port map( A => n2136, B => N4853, Y =>
ALU_instance_INTERNAL_B_26_port);
U2842 : XOR2XL port map( A => n2136, B => N4846, Y =>
ALU_instance_INTERNAL_B_19_port);
U2843 : XOR2XL port map( A => n2135, B => N4857, Y =>
ALU_instance_INTERNAL_B_30_port);
U2844 : XOR2XL port map( A => n2135, B => N4854, Y =>
ALU_instance_INTERNAL_B_27_port);
U2845 : XOR2XL port map( A => n2135, B => EX_ALU_B_31_port, Y =>
ALU_instance_INTERNAL_B_31_port);
U2846 : INVXL port map( A => n1561, Y => n1588);
U2847 : AND2XL port map( A => ALU_instance_INTERNAL_B_28_port, B => n1690, Y
=>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_RCA0_add_1_root_add_20_2_carry_1_port);
U2848 : AO22XL port map( A0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_S1_0_port,
A1 => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_4_port
, B0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_S0_0_port,
B1 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_n2, Y
=> ALU_instance_ADDER_OUT_16_port);
U2849 : XNOR2XL port map( A => n1684, B => ALU_instance_INTERNAL_B_16_port,
Y =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_S1_0_port);
U2850 : XOR2XL port map( A => ALU_instance_INTERNAL_B_16_port, B => n1684, Y
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_S0_0_port
);
U2851 : AO22XL port map( A0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_S1_0_port,
A1 => ALU_instance_CARRY_SELECT_ADDER_I_CARRY_5_port
, B0 =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_S0_0_port,
B1 => ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_n2, Y
=> ALU_instance_ADDER_OUT_20_port);
U2852 : XNOR2XL port map( A => n1683, B => ALU_instance_INTERNAL_B_20_port,
Y =>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_S1_0_port);
U2853 : XOR2XL port map( A => ALU_instance_INTERNAL_B_20_port, B => n1683, Y
=> ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_S0_0_port
);
U2854 : INVXL port map( A => n1556, Y => n1544);
U2855 : OR3XL port map( A => N4840, B => N4841, C => BOOTH_instance_n315, Y
=> n1721);
U2856 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_N202, Y => n2114
);
U2857 : OR2XL port map( A => ALU_instance_INTERNAL_B_20_port, B => n1683, Y
=>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_RCA1_add_1_root_add_20_2_carry_1_port);
U2858 : OR2XL port map( A => ALU_instance_INTERNAL_B_16_port, B => n1684, Y
=>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_RCA1_add_1_root_add_20_2_carry_1_port);
U2859 : OR2XL port map( A => ALU_instance_INTERNAL_B_24_port, B => n1685, Y
=>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_RCA1_add_1_root_add_20_2_carry_1_port);
U2860 : OR2XL port map( A => ALU_instance_INTERNAL_B_28_port, B => n1690, Y
=>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_7_RCA1_add_1_root_add_20_2_carry_1_port);
U2861 : AND2XL port map( A => ALU_instance_INTERNAL_B_20_port, B => n1683, Y
=>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_5_RCA0_add_1_root_add_20_2_carry_1_port);
U2862 : AND2XL port map( A => ALU_instance_INTERNAL_B_16_port, B => n1684, Y
=>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_4_RCA0_add_1_root_add_20_2_carry_1_port);
U2863 : AND2XL port map( A => ALU_instance_INTERNAL_B_24_port, B => n1685, Y
=>
ALU_instance_CARRY_SELECT_ADDER_I_CSB_6_RCA0_add_1_root_add_20_2_carry_1_port);
U2864 : XOR2XL port map( A => n2137, B => N4839, Y =>
ALU_instance_INTERNAL_B_12_port);
U2865 : AO22XL port map( A0 => EX_MULT_OUT_5_port, A1 => n2145, B0 =>
EX_ALU_OUT_5_port, B1 => n2144, Y => N4865);
U2866 : OAI2BB1XL port map( A0N => ALU_instance_ADDER_OUT_5_port, A1N =>
n1599, B0 => ALU_instance_n16, Y =>
EX_ALU_OUT_5_port);
U2867 : AOI22XL port map( A0 => ALU_instance_SHIFTER_OUT_5_port, A1 =>
ALU_instance_n5, B0 => ALU_instance_LOGIC_OUT_5_port
, B1 => ALU_instance_n6, Y => ALU_instance_n16);
U2868 : OAI2B2XL port map( A1N => N4832, A0 =>
ALU_instance_LOGIC_GENERIC_I_n45, B0 => N4832, B1 =>
ALU_instance_LOGIC_GENERIC_I_n46, Y =>
ALU_instance_LOGIC_OUT_5_port);
U2869 : XOR2XL port map( A => n2135, B => N4835, Y =>
ALU_instance_INTERNAL_B_8_port);
U2870 : XOR2XL port map( A => n2136, B => N4847, Y =>
ALU_instance_INTERNAL_B_20_port);
U2871 : XOR2XL port map( A => n2136, B => N4843, Y =>
ALU_instance_INTERNAL_B_16_port);
U2872 : XOR2XL port map( A => n2136, B => N4851, Y =>
ALU_instance_INTERNAL_B_24_port);
U2873 : XOR2XL port map( A => n2135, B => N4855, Y =>
ALU_instance_INTERNAL_B_28_port);
U2874 : AO22XL port map( A0 => EX_MULT_OUT_17_port, A1 => n2145, B0 =>
EX_ALU_OUT_17_port, B1 => n2144, Y => N4877);
U2875 : OAI2BB1XL port map( A0N => ALU_instance_ADDER_OUT_17_port, A1N =>
n1599, B0 => ALU_instance_n37, Y =>
EX_ALU_OUT_17_port);
U2876 : AOI22XL port map( A0 => ALU_instance_SHIFTER_OUT_17_port, A1 =>
n2138, B0 => ALU_instance_LOGIC_OUT_17_port, B1 =>
n2139, Y => ALU_instance_n37);
U2877 : OAI2B2XL port map( A1N => N4844, A0 =>
ALU_instance_LOGIC_GENERIC_I_n102, B0 => N4844, B1
=> ALU_instance_LOGIC_GENERIC_I_n103, Y =>
ALU_instance_LOGIC_OUT_17_port);
U2878 : AO22XL port map( A0 => EX_MULT_OUT_16_port, A1 => n2145, B0 =>
EX_ALU_OUT_16_port, B1 => n2144, Y => N4876);
U2879 : OAI2BB1XL port map( A0N => ALU_instance_ADDER_OUT_16_port, A1N =>
n1599, B0 => ALU_instance_n38, Y =>
EX_ALU_OUT_16_port);
U2880 : AOI22XL port map( A0 => ALU_instance_SHIFTER_OUT_16_port, A1 =>
n2138, B0 => ALU_instance_LOGIC_OUT_16_port, B1 =>
n2139, Y => ALU_instance_n38);
U2881 : OAI2B2XL port map( A1N => N4843, A0 =>
ALU_instance_LOGIC_GENERIC_I_n105, B0 => N4843, B1
=> ALU_instance_LOGIC_GENERIC_I_n106, Y =>
ALU_instance_LOGIC_OUT_16_port);
U2882 : AO22XL port map( A0 => EX_MULT_OUT_15_port, A1 => n2145, B0 =>
EX_ALU_OUT_15_port, B1 => n2144, Y => N4875);
U2883 : OAI2BB1XL port map( A0N => ALU_instance_ADDER_OUT_15_port, A1N =>
n1599, B0 => ALU_instance_n4, Y =>
EX_ALU_OUT_15_port);
U2884 : AOI22XL port map( A0 => ALU_instance_SHIFTER_OUT_15_port, A1 =>
n2138, B0 => ALU_instance_LOGIC_OUT_15_port, B1 =>
n2139, Y => ALU_instance_n4);
U2885 : OAI2B2XL port map( A1N => N4842, A0 =>
ALU_instance_LOGIC_GENERIC_I_n108, B0 => N4842, B1
=> ALU_instance_LOGIC_GENERIC_I_n109, Y =>
ALU_instance_LOGIC_OUT_15_port);
U2886 : AO22XL port map( A0 => EX_MULT_OUT_14_port, A1 => n2145, B0 =>
EX_ALU_OUT_14_port, B1 => n2144, Y => N4874);
U2887 : OAI2BB1XL port map( A0N => ALU_instance_ADDER_OUT_14_port, A1N =>
n1599, B0 => ALU_instance_n7, Y =>
EX_ALU_OUT_14_port);
U2888 : AOI22XL port map( A0 => ALU_instance_SHIFTER_OUT_14_port, A1 =>
ALU_instance_n5, B0 =>
ALU_instance_LOGIC_OUT_14_port, B1 =>
ALU_instance_n6, Y => ALU_instance_n7);
U2889 : OAI2B2XL port map( A1N => N4841, A0 =>
ALU_instance_LOGIC_GENERIC_I_n111, B0 => N4841, B1
=> ALU_instance_LOGIC_GENERIC_I_n112, Y =>
ALU_instance_LOGIC_OUT_14_port);
U2890 : AO22XL port map( A0 => EX_MULT_OUT_13_port, A1 => n2145, B0 =>
EX_ALU_OUT_13_port, B1 => n2144, Y => N4873);
U2891 : OAI2BB1XL port map( A0N => ALU_instance_ADDER_OUT_13_port, A1N =>
n1599, B0 => ALU_instance_n8, Y =>
EX_ALU_OUT_13_port);
U2892 : AOI22XL port map( A0 => ALU_instance_SHIFTER_OUT_13_port, A1 =>
ALU_instance_n5, B0 =>
ALU_instance_LOGIC_OUT_13_port, B1 =>
ALU_instance_n6, Y => ALU_instance_n8);
U2893 : OAI2B2XL port map( A1N => N4840, A0 =>
ALU_instance_LOGIC_GENERIC_I_n114, B0 => N4840, B1
=> ALU_instance_LOGIC_GENERIC_I_n115, Y =>
ALU_instance_LOGIC_OUT_13_port);
U2894 : AO22XL port map( A0 => EX_MULT_OUT_12_port, A1 => n2145, B0 =>
EX_ALU_OUT_12_port, B1 => n2144, Y => N4872);
U2895 : OAI2BB1XL port map( A0N => ALU_instance_ADDER_OUT_12_port, A1N =>
n1599, B0 => ALU_instance_n9, Y =>
EX_ALU_OUT_12_port);
U2896 : AOI22XL port map( A0 => ALU_instance_SHIFTER_OUT_12_port, A1 =>
n2138, B0 => ALU_instance_LOGIC_OUT_12_port, B1 =>
ALU_instance_n6, Y => ALU_instance_n9);
U2897 : OAI2B2XL port map( A1N => N4839, A0 =>
ALU_instance_LOGIC_GENERIC_I_n117, B0 => N4839, B1
=> ALU_instance_LOGIC_GENERIC_I_n118, Y =>
ALU_instance_LOGIC_OUT_12_port);
U2898 : AO22XL port map( A0 => EX_MULT_OUT_11_port, A1 => n2145, B0 =>
EX_ALU_OUT_11_port, B1 => n2144, Y => N4871);
U2899 : OAI2BB1XL port map( A0N => ALU_instance_ADDER_OUT_11_port, A1N =>
n1599, B0 => ALU_instance_n10, Y =>
EX_ALU_OUT_11_port);
U2900 : AOI22XL port map( A0 => ALU_instance_SHIFTER_OUT_11_port, A1 =>
ALU_instance_n5, B0 =>
ALU_instance_LOGIC_OUT_11_port, B1 => n2139, Y =>
ALU_instance_n10);
U2901 : OAI2B2XL port map( A1N => n1648, A0 =>
ALU_instance_LOGIC_GENERIC_I_n120, B0 => n1648, B1
=> ALU_instance_LOGIC_GENERIC_I_n121, Y =>
ALU_instance_LOGIC_OUT_11_port);
U2902 : AO22XL port map( A0 => EX_MULT_OUT_10_port, A1 => n2145, B0 =>
EX_ALU_OUT_10_port, B1 => n2144, Y => N4870);
U2903 : OAI2BB1XL port map( A0N => ALU_instance_ADDER_OUT_10_port, A1N =>
n1599, B0 => ALU_instance_n11, Y =>
EX_ALU_OUT_10_port);
U2904 : AOI22XL port map( A0 => ALU_instance_SHIFTER_OUT_10_port, A1 =>
ALU_instance_n5, B0 =>
ALU_instance_LOGIC_OUT_10_port, B1 => n2139, Y =>
ALU_instance_n11);
U2905 : OAI2B2XL port map( A1N => N4837, A0 =>
ALU_instance_LOGIC_GENERIC_I_n123, B0 => N4837, B1
=> ALU_instance_LOGIC_GENERIC_I_n124, Y =>
ALU_instance_LOGIC_OUT_10_port);
U2906 : AO22XL port map( A0 => EX_MULT_OUT_9_port, A1 => n2145, B0 =>
EX_ALU_OUT_9_port, B1 => n2144, Y => N4869);
U2907 : OAI2BB1XL port map( A0N => ALU_instance_ADDER_OUT_9_port, A1N =>
n1599, B0 => ALU_instance_n12, Y =>
EX_ALU_OUT_9_port);
U2908 : AOI22XL port map( A0 => ALU_instance_SHIFTER_OUT_9_port, A1 =>
ALU_instance_n5, B0 => ALU_instance_LOGIC_OUT_9_port
, B1 => ALU_instance_n6, Y => ALU_instance_n12);
U2909 : OAI2B2XL port map( A1N => N4836, A0 =>
ALU_instance_LOGIC_GENERIC_I_n33, B0 => N4836, B1 =>
ALU_instance_LOGIC_GENERIC_I_n34, Y =>
ALU_instance_LOGIC_OUT_9_port);
U2910 : AO22XL port map( A0 => EX_MULT_OUT_8_port, A1 => n2145, B0 =>
EX_ALU_OUT_8_port, B1 => n2144, Y => N4868);
U2911 : OAI2BB1XL port map( A0N => ALU_instance_ADDER_OUT_8_port, A1N =>
n1599, B0 => ALU_instance_n13, Y =>
EX_ALU_OUT_8_port);
U2912 : AOI22XL port map( A0 => ALU_instance_SHIFTER_OUT_8_port, A1 =>
ALU_instance_n5, B0 => ALU_instance_LOGIC_OUT_8_port
, B1 => ALU_instance_n6, Y => ALU_instance_n13);
U2913 : OAI2B2XL port map( A1N => N4835, A0 =>
ALU_instance_LOGIC_GENERIC_I_n36, B0 => N4835, B1 =>
ALU_instance_LOGIC_GENERIC_I_n37, Y =>
ALU_instance_LOGIC_OUT_8_port);
U2914 : AO22XL port map( A0 => EX_MULT_OUT_7_port, A1 => n2145, B0 =>
EX_ALU_OUT_7_port, B1 => n2144, Y => N4867);
U2915 : OAI2BB1XL port map( A0N => ALU_instance_ADDER_OUT_7_port, A1N =>
n1599, B0 => ALU_instance_n14, Y =>
EX_ALU_OUT_7_port);
U2916 : AOI22XL port map( A0 => ALU_instance_SHIFTER_OUT_7_port, A1 =>
ALU_instance_n5, B0 => ALU_instance_LOGIC_OUT_7_port
, B1 => ALU_instance_n6, Y => ALU_instance_n14);
U2917 : OAI2B2XL port map( A1N => N4834, A0 =>
ALU_instance_LOGIC_GENERIC_I_n39, B0 => N4834, B1 =>
ALU_instance_LOGIC_GENERIC_I_n40, Y =>
ALU_instance_LOGIC_OUT_7_port);
U2918 : AO22XL port map( A0 => EX_MULT_OUT_6_port, A1 => n2145, B0 =>
EX_ALU_OUT_6_port, B1 => n2144, Y => N4866);
U2919 : OAI2BB1XL port map( A0N => ALU_instance_ADDER_OUT_6_port, A1N =>
n1599, B0 => ALU_instance_n15, Y =>
EX_ALU_OUT_6_port);
U2920 : AOI22XL port map( A0 => ALU_instance_SHIFTER_OUT_6_port, A1 =>
ALU_instance_n5, B0 => ALU_instance_LOGIC_OUT_6_port
, B1 => ALU_instance_n6, Y => ALU_instance_n15);
U2921 : OAI2B2XL port map( A1N => N4833, A0 =>
ALU_instance_LOGIC_GENERIC_I_n42, B0 => N4833, B1 =>
ALU_instance_LOGIC_GENERIC_I_n43, Y =>
ALU_instance_LOGIC_OUT_6_port);
U2922 : AOI32XL port map( A0 => n1535, A1 => n1398, A2 => n1547, B0 => n1527
, B1 => n1534, Y => n1531);
U2923 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n44, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n113, B0 =>
n2129, B1 => ALU_instance_SHIFTER_GENERIC_I_C50_n128
, C0 => ALU_instance_SHIFTER_GENERIC_I_C48_n138, Y
=> ALU_instance_SHIFTER_GENERIC_I_C48_n22);
U2924 : AOI22XL port map( A0 => n1684, A1 => n2125, B0 => n1651, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n50, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n138);
U2925 : OAI221XL port map( A0 => n2127, A1 => n1670, B0 => n2129, B1 =>
n1608, C0 => ALU_instance_SHIFTER_GENERIC_I_C86_n137
, Y => ALU_instance_SHIFTER_GENERIC_I_C86_n47);
U2926 : AOI22XL port map( A0 => n1651, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n25, B0 => n1684,
B1 => n2126, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n137);
U2927 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n43, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n86, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n93, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n44, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n146, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n31);
U2928 : AOI22XL port map( A0 => n2125, A1 => n1688, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n49, B1 => n1689,
Y => ALU_instance_SHIFTER_GENERIC_I_C50_n146);
U2929 : OAI221XL port map( A0 => n2122, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n132, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n45, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n86, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n134, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n25);
U2930 : AOI22XL port map( A0 => n2125, A1 => n1683, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n49, B1 => n1688,
Y => ALU_instance_SHIFTER_GENERIC_I_C50_n134);
U2931 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n44, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n23, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n46, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n21, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n147, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n83);
U2932 : AOI22XL port map( A0 => n1681, A1 => n2125, B0 => n1680, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n50, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n147);
U2933 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n44, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n33, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n22, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n23, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n121, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n71);
U2934 : AOI22XL port map( A0 => n1680, A1 => n2125, B0 => n1677, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n49, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n121);
U2935 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C50_n61, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n26);
U2936 : OAI221XL port map( A0 => n2122, A1 => n2186, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n44, B1 => n2188,
C0 => ALU_instance_SHIFTER_GENERIC_I_C50_n63, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n61);
U2937 : AOI22XL port map( A0 => n2189, A1 => n2125, B0 => n2119, B1 => n2126
, Y => ALU_instance_SHIFTER_GENERIC_I_C50_n63);
U2938 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C50_n87, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n32);
U2939 : OAI221XL port map( A0 => n2122, A1 => n2188, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n45, B1 => n1607,
C0 => ALU_instance_SHIFTER_GENERIC_I_C50_n89, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n87);
U2940 : AOI22XL port map( A0 => N4724, A1 => n2125, B0 => n2117, B1 => n2126
, Y => ALU_instance_SHIFTER_GENERIC_I_C50_n89);
U2941 : OAI2B2XL port map( A1N => n1525, A0 => n1708, B0 => n1530, B1 =>
n1374, Y => EX_SHIFTER_CW_0_port);
U2942 : AOI221XL port map( A0 => n2124, A1 => n2119, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n52, B1 => n2189,
C0 => ALU_instance_SHIFTER_GENERIC_I_C48_n163, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n34);
U2943 : OAI22XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C48_n45, A1
=> n1644, B0 => n2191, B1 => n1643, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n163);
U2944 : OAI31XL port map( A0 => n1544, A1 => n1549, A2 => n1536, B0 => n1557
, Y => EX_COMPARATOR_CW_5_port);
U2945 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n43, A1
=> n2192, B0 => n2123, B1 => n1647, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n155, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n151);
U2946 : AOI22XL port map( A0 => n2115, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n48, B0 =>
ALU_instance_SHIFTER_GENERIC_I_N202, B1 => n2126, Y
=> ALU_instance_SHIFTER_GENERIC_I_C50_n155);
U2947 : NAND3XL port map( A => n1546, B => n1551, C => n1552, Y =>
EX_ALU_SEL_0_port);
U2948 : AOI211XL port map( A0 => n1708, A1 => n1553, B0 =>
EX_COMPARATOR_CW_5_port, C0 =>
EX_COMPARATOR_CW_1_port, Y => n1552);
U2949 : MXI2XL port map( A => n1691, B => n1692, S0 => n1643, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n79);
U2950 : OAI2B2XL port map( A1N => n1601, A0 =>
ALU_instance_LOGIC_GENERIC_I_n93, B0 => n1601, B1 =>
ALU_instance_LOGIC_GENERIC_I_n94, Y =>
ALU_instance_LOGIC_OUT_1_port);
U2951 : NAND2XL port map( A => n2195, B => N4719, Y =>
ALU_instance_LOGIC_GENERIC_I_n94);
U2952 : AOI22XL port map( A0 => n2194, A1 => BOOTH_instance_n307, B0 =>
n2115, B1 => EX_LOGIC_CW_3_port, Y =>
ALU_instance_LOGIC_GENERIC_I_n93);
U2953 : OAI2B2XL port map( A1N => n2161, A0 =>
ALU_instance_LOGIC_GENERIC_I_n60, B0 => n1602, B1 =>
ALU_instance_LOGIC_GENERIC_I_n61, Y =>
ALU_instance_LOGIC_OUT_2_port);
U2954 : NAND2XL port map( A => n2195, B => n2193, Y =>
ALU_instance_LOGIC_GENERIC_I_n61);
U2955 : AOI22XL port map( A0 => n2194, A1 => n1647, B0 => n2193, B1 => n2197
, Y => ALU_instance_LOGIC_GENERIC_I_n60);
U2956 : OAI2B2XL port map( A1N => EX_ALU_B_31_port, A0 =>
ALU_instance_LOGIC_GENERIC_I_n54, B0 =>
EX_ALU_B_31_port, B1 =>
ALU_instance_LOGIC_GENERIC_I_n55, Y =>
ALU_instance_LOGIC_OUT_31_port);
U2957 : NAND2XL port map( A => n2196, B => n1692, Y =>
ALU_instance_LOGIC_GENERIC_I_n55);
U2958 : AOI22XL port map( A0 => n2194, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n139, B0 => n1692
, B1 => EX_LOGIC_CW_3_port, Y =>
ALU_instance_LOGIC_GENERIC_I_n54);
U2959 : NOR3XL port map( A => n1542, B => n1559, C => n1560, Y => n1530);
U2960 : AOI22XL port map( A0 => n2194, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n140, B0 => n1691
, B1 => n2197, Y => ALU_instance_LOGIC_GENERIC_I_n57
);
U2961 : AOI22XL port map( A0 => n2196, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n21, B0 => n1682,
B1 => n2197, Y => ALU_instance_LOGIC_GENERIC_I_n63);
U2962 : AOI22XL port map( A0 => n2194, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n23, B0 => n1690,
B1 => n2197, Y => ALU_instance_LOGIC_GENERIC_I_n66);
U2963 : AOI22XL port map( A0 => n2196, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n33, B0 => n1681,
B1 => n2197, Y => ALU_instance_LOGIC_GENERIC_I_n69);
U2964 : AOI22XL port map( A0 => n2194, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n42, B0 => n1680,
B1 => n2197, Y => ALU_instance_LOGIC_GENERIC_I_n72);
U2965 : AOI22XL port map( A0 => n2196, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n50, B0 => n1677,
B1 => n2197, Y => ALU_instance_LOGIC_GENERIC_I_n75);
U2966 : AOI22XL port map( A0 => n2196, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n58, B0 => n1685,
B1 => n2197, Y => ALU_instance_LOGIC_GENERIC_I_n78);
U2967 : AOI22XL port map( A0 => n2194, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n64, B0 => n1678,
B1 => n2197, Y => ALU_instance_LOGIC_GENERIC_I_n81);
U2968 : AOI22XL port map( A0 => n2194, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n132, B0 => n1687
, B1 => n2197, Y => ALU_instance_LOGIC_GENERIC_I_n84
);
U2969 : AOI22XL port map( A0 => n2196, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n86, B0 => n1686,
B1 => n2197, Y => ALU_instance_LOGIC_GENERIC_I_n87);
U2970 : AOI22XL port map( A0 => n2194, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n93, B0 => n1683,
B1 => n2197, Y => ALU_instance_LOGIC_GENERIC_I_n90);
U2971 : AOI22XL port map( A0 => n2194, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n125, B0 => n1688
, B1 => EX_LOGIC_CW_3_port, Y =>
ALU_instance_LOGIC_GENERIC_I_n96);
U2972 : AOI22XL port map( A0 => n2194, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n128, B0 => n1689
, B1 => EX_LOGIC_CW_3_port, Y =>
ALU_instance_LOGIC_GENERIC_I_n99);
U2973 : AOI22XL port map( A0 => n2194, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n113, B0 => n1679
, B1 => EX_LOGIC_CW_3_port, Y =>
ALU_instance_LOGIC_GENERIC_I_n102);
U2974 : AOI22XL port map( A0 => n2194, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n119, B0 => n1684
, B1 => EX_LOGIC_CW_3_port, Y =>
ALU_instance_LOGIC_GENERIC_I_n105);
U2975 : AOI22XL port map( A0 => n2194, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n113, B0 => n1651
, B1 => EX_LOGIC_CW_3_port, Y =>
ALU_instance_LOGIC_GENERIC_I_n108);
U2976 : AOI22XL port map( A0 => n2194, A1 => n2184, B0 => n2183, B1 =>
EX_LOGIC_CW_3_port, Y =>
ALU_instance_LOGIC_GENERIC_I_n123);
U2977 : AOI22XL port map( A0 => n2195, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n47, B0 => N4724,
B1 => EX_LOGIC_CW_3_port, Y =>
ALU_instance_LOGIC_GENERIC_I_n42);
U2978 : AOI22XL port map( A0 => n2195, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n45, B0 => N4723,
B1 => EX_LOGIC_CW_3_port, Y =>
ALU_instance_LOGIC_GENERIC_I_n45);
U2979 : AOI22XL port map( A0 => n1691, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n25, B0 => n1692,
B1 => n2126, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n24);
U2980 : OAI221XL port map( A0 => n2122, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n128, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n45, B1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n113, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n130, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n24);
U2981 : AOI22XL port map( A0 => n1684, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n48, B0 => n1651,
B1 => n2126, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n130);
U2982 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n43, A1
=> ALU_instance_SHIFTER_GENERIC_I_C86_n113, B0 =>
n2123, B1 => ALU_instance_SHIFTER_GENERIC_I_C86_n119
, C0 => ALU_instance_SHIFTER_GENERIC_I_C50_n147, Y
=> ALU_instance_SHIFTER_GENERIC_I_C50_n30);
U2983 : AOI22XL port map( A0 => n1651, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n48, B0 => n2177,
B1 => n2126, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n147);
U2984 : NAND2XL port map( A => n2195, B => N4723, Y =>
ALU_instance_LOGIC_GENERIC_I_n46);
U2985 : NAND2XL port map( A => n2195, B => N4724, Y =>
ALU_instance_LOGIC_GENERIC_I_n43);
U2986 : AOI21XL port map( A0 => n2160, A1 => n1692, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n73, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n117);
U2987 : NAND2XL port map( A => n1708, B => n1542, Y => n1536);
U2988 : NAND2XL port map( A => n2196, B => n1651, Y =>
ALU_instance_LOGIC_GENERIC_I_n109);
U2989 : NAND2XL port map( A => n2196, B => n1678, Y =>
ALU_instance_LOGIC_GENERIC_I_n82);
U2990 : NAND2XL port map( A => n2196, B => n1679, Y =>
ALU_instance_LOGIC_GENERIC_I_n103);
U2991 : NAND2XL port map( A => n2196, B => n1682, Y =>
ALU_instance_LOGIC_GENERIC_I_n64);
U2992 : NAND2XL port map( A => n2196, B => n1681, Y =>
ALU_instance_LOGIC_GENERIC_I_n70);
U2993 : NAND2XL port map( A => n2196, B => n1680, Y =>
ALU_instance_LOGIC_GENERIC_I_n73);
U2994 : NAND2XL port map( A => n2196, B => n1677, Y =>
ALU_instance_LOGIC_GENERIC_I_n76);
U2995 : NAND2XL port map( A => n2196, B => n1689, Y =>
ALU_instance_LOGIC_GENERIC_I_n100);
U2996 : NAND2XL port map( A => n2196, B => n1687, Y =>
ALU_instance_LOGIC_GENERIC_I_n85);
U2997 : NAND2XL port map( A => n2196, B => n1686, Y =>
ALU_instance_LOGIC_GENERIC_I_n88);
U2998 : NAND2XL port map( A => n2196, B => n1688, Y =>
ALU_instance_LOGIC_GENERIC_I_n97);
U2999 : NAND2XL port map( A => n2196, B => n1691, Y =>
ALU_instance_LOGIC_GENERIC_I_n58);
U3000 : NAND2XL port map( A => n2196, B => n1690, Y =>
ALU_instance_LOGIC_GENERIC_I_n67);
U3001 : NAND2XL port map( A => n2196, B => n1685, Y =>
ALU_instance_LOGIC_GENERIC_I_n79);
U3002 : NAND2XL port map( A => n2196, B => n1683, Y =>
ALU_instance_LOGIC_GENERIC_I_n91);
U3003 : NAND2XL port map( A => n2196, B => n1684, Y =>
ALU_instance_LOGIC_GENERIC_I_n106);
U3004 : INVXL port map( A => n2117, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n45);
U3005 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C86_n57, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n10);
U3006 : OAI221XL port map( A0 => n2128, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n50, B0 => n2129,
B1 => ALU_instance_SHIFTER_GENERIC_I_C86_n58, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n59, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n57);
U3007 : AOI22XL port map( A0 => n1680, A1 => n2130, B0 => n1681, B1 => n2126
, Y => ALU_instance_SHIFTER_GENERIC_I_C86_n59);
U3008 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C86_n63, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n27);
U3009 : OAI221XL port map( A0 => n2127, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n58, B0 => n2129,
B1 => ALU_instance_SHIFTER_GENERIC_I_C86_n64, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n65, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n63);
U3010 : AOI22XL port map( A0 => n1677, A1 => n2130, B0 => n1680, B1 => n2126
, Y => ALU_instance_SHIFTER_GENERIC_I_C86_n65);
U3011 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C86_n77, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n36);
U3012 : OAI221XL port map( A0 => n2127, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n64, B0 => n2129,
B1 => ALU_instance_SHIFTER_GENERIC_I_C50_n132, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C86_n79, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n77);
U3013 : AOI22XL port map( A0 => n1685, A1 => n2130, B0 => n1677, B1 => n2126
, Y => ALU_instance_SHIFTER_GENERIC_I_C86_n79);
U3014 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C86_n85, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n44);
U3015 : OAI221XL port map( A0 => n2128, A1 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n132, B0 => n2129
, B1 => ALU_instance_SHIFTER_GENERIC_I_C86_n86, C0
=> ALU_instance_SHIFTER_GENERIC_I_C86_n87, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n85);
U3016 : AOI22XL port map( A0 => n1678, A1 => n2130, B0 => n1685, B1 => n2126
, Y => ALU_instance_SHIFTER_GENERIC_I_C86_n87);
U3017 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C50_n50, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n20);
U3018 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n43, A1
=> n2184, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C48_n44, B1 => n2186,
C0 => ALU_instance_SHIFTER_GENERIC_I_C50_n53, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n50);
U3019 : AOI22XL port map( A0 => n2187, A1 => n2125, B0 => n2189, B1 => n2126
, Y => ALU_instance_SHIFTER_GENERIC_I_C50_n53);
U3020 : INVXL port map( A => ALU_instance_SHIFTER_GENERIC_I_C50_n162, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n35);
U3021 : OAI221XL port map( A0 => ALU_instance_SHIFTER_GENERIC_I_C50_n43, A1
=> n1607, B0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n45, B1 =>
BOOTH_instance_n260, C0 =>
ALU_instance_SHIFTER_GENERIC_I_C50_n163, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n162);
U3022 : AOI22XL port map( A0 => N4723, A1 => n2125, B0 => n2190, B1 => n2126
, Y => ALU_instance_SHIFTER_GENERIC_I_C50_n163);
U3023 : INVXL port map( A => n2119, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n47);
U3024 : INVXL port map( A => n2118, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n46);
U3025 : INVXL port map( A => N4723, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n166);
U3026 : INVXL port map( A => N4724, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n155);
U3027 : INVXL port map( A => n1559, Y => n1523);
U3028 : CLKBUFX1 port map( A => EX_LOGIC_CW_2_port, Y => n2196);
U3029 : INVXL port map( A => n1688, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n125);
U3030 : INVXL port map( A => EX_SHIFTER_CW_1_port, Y =>
ALU_instance_SHIFTER_GENERIC_I_n89);
U3031 : AND2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_1_port,
B => n1593, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_1_port);
U3032 : AND2XL port map( A =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_1_0_port,
B => n1593, Y =>
ALU_instance_SHIFTER_GENERIC_I_C88_ML_int_2_0_port);
U3033 : INVXL port map( A => n1692, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n139);
U3034 : INVXL port map( A => n1651, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n113);
U3035 : INVXL port map( A => n1678, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n64);
U3036 : INVXL port map( A => n1679, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n113);
U3037 : INVXL port map( A => n1681, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n33);
U3038 : INVXL port map( A => n1680, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n42);
U3039 : INVXL port map( A => n1677, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n50);
U3040 : INVXL port map( A => n1689, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n128);
U3041 : INVXL port map( A => n1687, Y =>
ALU_instance_SHIFTER_GENERIC_I_C50_n132);
U3042 : INVXL port map( A => n1686, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n86);
U3043 : INVXL port map( A => n1691, Y =>
ALU_instance_SHIFTER_GENERIC_I_C48_n140);
U3044 : INVXL port map( A => n1690, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n23);
U3045 : INVXL port map( A => n1685, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n58);
U3046 : INVXL port map( A => n1683, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n93);
U3047 : INVXL port map( A => n1684, Y =>
ALU_instance_SHIFTER_GENERIC_I_C86_n119);
U3048 : NOR2XL port map( A => n1483, B => n1293, Y => n1195);
U3049 : AOI21XL port map( A0 => n1290, A1 => n1291, B0 => n1227, Y => n1225)
;
U3050 : OAI2BB2XL port map( B0 => ID_REGA_ZERO, B1 => n1479, A0N => n1194,
A1N => ID_REGA_ZERO, Y => n1517);
U3051 : NOR2XL port map( A => zero_instance_n1, B => zero_instance_n2, Y =>
ID_REGA_ZERO);
U3052 : NAND4XL port map( A => zero_instance_n7, B => zero_instance_n8, C =>
zero_instance_n9, D => zero_instance_n10, Y =>
zero_instance_n1);
U3053 : NOR2XL port map( A => n1290, B => n1518, Y => n1485);
U3054 : NOR2XL port map( A => n1370, B => n1190, Y => n1498);
U3055 : INVXL port map( A => n1516, Y => n1478);
U3056 : CLKBUFX1 port map( A => n1226, Y => n2146);
U3057 : CLKBUFX3 port map( A => n697, Y => n2156);
U3058 : CLKBUFX1 port map( A => n697, Y => n2154);
U3059 : BUFX2 port map( A => n697, Y => n2155);
U3060 : INVXL port map( A => n1291, Y => n1293);
U3061 : INVXL port map( A => n1358, Y => N4717);
U3062 : BUFX2 port map( A => n697, Y => n2157);
U3063 : INVXL port map( A => n1520, Y => n1197);
U3064 : NOR2XL port map( A => n1484, B => n1618, Y =>
ID_INSTR_AFTER_CU_27_port);
U3065 : NOR2XL port map( A => n1481, B => n1618, Y =>
ID_INSTR_AFTER_CU_29_port);
U3066 : NOR2XL port map( A => n1488, B => n1618, Y =>
ID_INSTR_AFTER_CU_31_port);
U3067 : NOR2XL port map( A => n1205, B => n1618, Y =>
ID_INSTR_AFTER_CU_7_port);
U3068 : NOR2XL port map( A => n1204, B => n1618, Y =>
ID_INSTR_AFTER_CU_9_port);
U3069 : NOR2XL port map( A => n1203, B => n1618, Y =>
ID_INSTR_AFTER_CU_8_port);
U3070 : NOR2XL port map( A => n1433, B => n1618, Y =>
ID_INSTR_AFTER_CU_17_port);
U3071 : NOR2XL port map( A => n1432, B => n1618, Y =>
ID_INSTR_AFTER_CU_16_port);
U3072 : NOR2XL port map( A => n1434, B => n1618, Y =>
ID_INSTR_AFTER_CU_19_port);
U3073 : NAND2XL port map( A => n1522, B => n1290, Y =>
ID_INSTR_AFTER_CU_28_port);
U3074 : NAND2XL port map( A => n1522, B => n1483, Y =>
ID_INSTR_AFTER_CU_30_port);
U3075 : NAND2XL port map( A => n1522, B => n1518, Y =>
ID_INSTR_AFTER_CU_26_port);
U3076 : AND2XL port map( A => n2109, B => n1522, Y =>
ID_INSTR_AFTER_CU_15_port);
U3077 : OAI32XL port map( A0 => n1373, A1 => n1374, A2 => n1375, B0 => n1376
, B1 => n1377, Y => n1368);
U3078 : OR2XL port map( A => n1378, B => n1379, Y => n1375);
U3079 : OAI32XL port map( A0 => n1441, A1 => n1422, A2 => n1442, B0 => n1443
, B1 => n1216, Y => n1439);
U3080 : OR2XL port map( A => n1446, B => n1447, Y => n1442);
U3081 : INVXL port map( A => n1438, Y => n1443);
U3082 : OAI32XL port map( A0 => n1359, A1 => n1360, A2 => n1361, B0 => n1357
, B1 => n1362, Y => N4712);
U3083 : NAND2XL port map( A => n1194, B => n1195, Y => n1359);
U3084 : AOI21XL port map( A0 => n1190, A1 => n1363, B0 => n1364, Y => n1362)
;
U3085 : AOI22XL port map( A0 => n1365, A1 => n1366, B0 => n1367, B1 => n1361
, Y => n1364);
U3086 : OAI2B2XL port map( A1N => n1369, A0 => n1361, B0 => n1376, B1 =>
n1374, Y => n1363);
U3087 : XNOR2XL port map( A => RF_ADD_WR_2_port, B => n1427, Y => n1474);
U3088 : XNOR2XL port map( A => RF_ADD_WR_1_port, B => n1433, Y => n1490);
U3089 : XNOR2XL port map( A => RF_ADD_WR_4_port, B => n1407, Y => n1475);
U3090 : OAI2B2XL port map( A1N => n1360, A0 => n1368, B0 => n1371, B1 =>
n1372, Y => n1365);
U3091 : NAND4XL port map( A => n1343, B => n1344, C => n1340, D => n1348, Y
=> n1493);
U3092 : NOR3XL port map( A => n1419, B => n1435, C => n1417, Y => n1413);
U3093 : NAND3XL port map( A => n1344, B => n1471, C => n1339, Y => n1338);
U3094 : OAI21XL port map( A0 => n1369, A1 => n1368, B0 => n1370, Y => n1366)
;
U3095 : INVXL port map( A => n1435, Y => n1422);
U3096 : OAI211XL port map( A0 => n1328, A1 => n1309, B0 => n1208, C0 =>
n1329, Y => RF_DATAIN(7));
U3097 : NAND2XL port map( A => WB_DATA_EXT_16_7_port, B => n2149, Y => n1329
);
U3098 : NOR2XL port map( A => n1822, B => n1328, Y => WB_DATA_EXT_16_7_port)
;
U3099 : OAI211XL port map( A0 => n1326, A1 => n1309, B0 => n1208, C0 =>
n1327, Y => RF_DATAIN(8));
U3100 : NAND2XL port map( A => WB_DATA_EXT_16_8_port, B => n2149, Y => n1327
);
U3101 : NOR2XL port map( A => n1822, B => n1326, Y => WB_DATA_EXT_16_8_port)
;
U3102 : OAI211XL port map( A0 => n1324, A1 => n1309, B0 => n1208, C0 =>
n1325, Y => RF_DATAIN(9));
U3103 : NAND2XL port map( A => WB_DATA_EXT_16_9_port, B => n2149, Y => n1325
);
U3104 : NOR2XL port map( A => n1324, B => n1822, Y => WB_DATA_EXT_16_9_port)
;
U3105 : OAI211XL port map( A0 => n1322, A1 => n1309, B0 => n1208, C0 =>
n1323, Y => RF_DATAIN(10));
U3106 : NAND2XL port map( A => WB_DATA_EXT_16_10_port, B => n2149, Y =>
n1323);
U3107 : NOR2XL port map( A => n1822, B => n1322, Y => WB_DATA_EXT_16_10_port
);
U3108 : OAI211XL port map( A0 => n1320, A1 => n1309, B0 => n1208, C0 =>
n1321, Y => RF_DATAIN(11));
U3109 : NAND2XL port map( A => WB_DATA_EXT_16_11_port, B => n2149, Y =>
n1321);
U3110 : NOR2XL port map( A => n1822, B => n1320, Y => WB_DATA_EXT_16_11_port
);
U3111 : OAI211XL port map( A0 => n1318, A1 => n1309, B0 => n1208, C0 =>
n1319, Y => RF_DATAIN(12));
U3112 : NAND2XL port map( A => WB_DATA_EXT_16_12_port, B => n2149, Y =>
n1319);
U3113 : NOR2XL port map( A => n1822, B => n1318, Y => WB_DATA_EXT_16_12_port
);
U3114 : OAI211XL port map( A0 => n1316, A1 => n1309, B0 => n1208, C0 =>
n1317, Y => RF_DATAIN(13));
U3115 : NAND2XL port map( A => WB_DATA_EXT_16_13_port, B => n2149, Y =>
n1317);
U3116 : NOR2XL port map( A => n1822, B => n1316, Y => WB_DATA_EXT_16_13_port
);
U3117 : OAI211XL port map( A0 => n1314, A1 => n1309, B0 => n1208, C0 =>
n1315, Y => RF_DATAIN(14));
U3118 : NAND2XL port map( A => WB_DATA_EXT_16_14_port, B => n2149, Y =>
n1315);
U3119 : NOR2XL port map( A => n1822, B => n1314, Y => WB_DATA_EXT_16_14_port
);
U3120 : OAI211XL port map( A0 => n1312, A1 => n1309, B0 => n1208, C0 =>
n1313, Y => RF_DATAIN(15));
U3121 : NAND2XL port map( A => WB_DATA_EXT_16_15_port, B => n2149, Y =>
n1313);
U3122 : INVXL port map( A => n2110, Y => WB_DATA_EXT_16_15_port);
U3123 : AOI31XL port map( A0 => n1194, A1 => n1195, A2 => n1357, B0 => n1358
, Y => N4716);
U3124 : INVXL port map( A => n1328, Y => WB_DATA_EXT_8_9_port);
U3125 : INVXL port map( A => n1312, Y => WB_DATA_EXT_16_31_port);
U3126 : NAND2XL port map( A => WB_DATA_EXT_16_31_port, B =>
WB_SIGN_EXT_16_CONTROL, Y =>
WB_SIGN_EXT_16_instance_n27);
U3127 : OR3XL port map( A => n1370, B => n1371, C => n1372, Y => n1440);
U3128 : NAND3XL port map( A => n1203, B => n1204, C => n1205, Y => n1202);
U3129 : INVXL port map( A => n1216, Y => n1417);
U3130 : INVXL port map( A => n1341, Y => n1330);
U3131 : NAND2BXL port map( AN => PORT_R_W_port, B => n1216, Y => PORT_EN);
U3132 : NAND2XL port map( A => n1445, B => n1219, Y => n1213);
U3133 : AND3XL port map( A => n1397, B => n1398, C => n1399, Y => n1357);
U3134 : INVXL port map( A => n1215, Y => n1212);
U3135 : NAND2XL port map( A => n1199, B => n1191, Y => RF_RD1);
U3136 : INVXL port map( A => WB_DATA_EXT_8_0_port, Y =>
WB_SIGN_EXT_16_instance_n34);
U3137 : INVXL port map( A => WB_DATA_EXT_8_1_port, Y =>
WB_SIGN_EXT_16_instance_n33);
U3138 : INVXL port map( A => WB_DATA_EXT_8_2_port, Y =>
WB_SIGN_EXT_16_instance_n28);
U3139 : INVXL port map( A => WB_DATA_EXT_8_3_port, Y =>
WB_SIGN_EXT_16_instance_n25);
U3140 : INVXL port map( A => WB_DATA_EXT_8_4_port, Y =>
WB_SIGN_EXT_16_instance_n24);
U3141 : INVXL port map( A => WB_DATA_EXT_8_5_port, Y =>
WB_SIGN_EXT_16_instance_n23);
U3142 : INVXL port map( A => WB_DATA_EXT_8_6_port, Y =>
WB_SIGN_EXT_16_instance_n22);
U3143 : AND2XL port map( A => n1214, B => n1215, Y => PORT_SIZE(0));
U3144 : OAI2BB1XL port map( A0N => WB_DATA_EXT_8_0_port, A1N => n1330, B0 =>
n1337, Y => RF_DATAIN(0));
U3145 : AOI22XL port map( A0 => n1619, A1 => WB_DATA_EXT_8_0_port, B0 =>
WB_DATA_EXT_16_0_port, B1 => n2149, Y => n1337);
U3146 : NOR2XL port map( A => n1822, B => WB_SIGN_EXT_16_instance_n34, Y =>
WB_DATA_EXT_16_0_port);
U3147 : OAI2BB1XL port map( A0N => WB_DATA_EXT_8_1_port, A1N => n1330, B0 =>
n1336, Y => RF_DATAIN(1));
U3148 : AOI22XL port map( A0 => n1619, A1 => WB_DATA_EXT_8_1_port, B0 =>
WB_DATA_EXT_16_1_port, B1 => n1211, Y => n1336);
U3149 : NOR2XL port map( A => n1822, B => WB_SIGN_EXT_16_instance_n33, Y =>
WB_DATA_EXT_16_1_port);
U3150 : OAI2BB1XL port map( A0N => WB_DATA_EXT_8_2_port, A1N => n1330, B0 =>
n1335, Y => RF_DATAIN(2));
U3151 : AOI22XL port map( A0 => n1619, A1 => WB_DATA_EXT_8_2_port, B0 =>
WB_DATA_EXT_16_2_port, B1 => n1211, Y => n1335);
U3152 : NOR2XL port map( A => n1822, B => WB_SIGN_EXT_16_instance_n28, Y =>
WB_DATA_EXT_16_2_port);
U3153 : OAI2BB1XL port map( A0N => WB_DATA_EXT_8_3_port, A1N => n1330, B0 =>
n1334, Y => RF_DATAIN(3));
U3154 : AOI22XL port map( A0 => n1619, A1 => WB_DATA_EXT_8_3_port, B0 =>
WB_DATA_EXT_16_3_port, B1 => n1211, Y => n1334);
U3155 : NOR2XL port map( A => n1822, B => WB_SIGN_EXT_16_instance_n25, Y =>
WB_DATA_EXT_16_3_port);
U3156 : OAI2BB1XL port map( A0N => WB_DATA_EXT_8_4_port, A1N => n1330, B0 =>
n1333, Y => RF_DATAIN(4));
U3157 : AOI22XL port map( A0 => n1619, A1 => WB_DATA_EXT_8_4_port, B0 =>
WB_DATA_EXT_16_4_port, B1 => n1211, Y => n1333);
U3158 : NOR2XL port map( A => n1822, B => WB_SIGN_EXT_16_instance_n24, Y =>
WB_DATA_EXT_16_4_port);
U3159 : OAI2BB1XL port map( A0N => WB_DATA_EXT_8_5_port, A1N => n1330, B0 =>
n1332, Y => RF_DATAIN(5));
U3160 : AOI22XL port map( A0 => n1619, A1 => WB_DATA_EXT_8_5_port, B0 =>
WB_DATA_EXT_16_5_port, B1 => n1211, Y => n1332);
U3161 : NOR2XL port map( A => n1822, B => WB_SIGN_EXT_16_instance_n23, Y =>
WB_DATA_EXT_16_5_port);
U3162 : OAI2BB1XL port map( A0N => WB_DATA_EXT_8_6_port, A1N => n1330, B0 =>
n1331, Y => RF_DATAIN(6));
U3163 : AOI22XL port map( A0 => n1619, A1 => WB_DATA_EXT_8_6_port, B0 =>
WB_DATA_EXT_16_6_port, B1 => n1211, Y => n1331);
U3164 : NOR2XL port map( A => n1822, B => WB_SIGN_EXT_16_instance_n22, Y =>
WB_DATA_EXT_16_6_port);
U3165 : AOI222XL port map( A0 => EX_COMPARATOR_CW_3_port, A1 =>
ALU_instance_OVERFLOW, B0 => EX_COMPARATOR_CW_0_port
, B1 => ALU_instance_ZERO, C0 =>
EX_COMPARATOR_CW_4_port, C1 =>
ALU_instance_COMPARATOR_GENERIC_I_n9, Y =>
ALU_instance_COMPARATOR_GENERIC_I_n4);
U3166 : OAI31XL port map( A0 => n1539, A1 => n1374, A2 => n1540, B0 => n1541
, Y => EX_COMPARATOR_CW_3_port);
U3167 : OAI21XL port map( A0 => n1536, A1 => n1537, B0 => n1538, Y =>
EX_COMPARATOR_CW_4_port);
U3168 : OAI31XL port map( A0 => n1544, A1 => EX_INSTR_2_port, A2 => n1536,
B0 => n1545, Y => EX_COMPARATOR_CW_0_port);
U3169 : OAI2B11XL port map( A1N => n1356, A0 => EX_INSTR_26_port, B0 =>
n1374, C0 => n1351, Y => n1564);
U3170 : OAI22XL port map( A0 => n1567, A1 => n1568, B0 => EX_INSTR_31_port,
B1 => n1400, Y => n1356);
U3171 : NOR3XL port map( A => EX_INSTR_29_port, B => EX_INSTR_30_port, C =>
n1567, Y => n1569);
U3172 : OAI211XL port map( A0 => n1584, A1 => n1585, B0 => n1581, C0 =>
EX_INSTR_29_port, Y => n1543);
U3173 : AND2XL port map( A => n1573, B => EX_INSTR_30_port, Y => n1585);
U3174 : NOR2XL port map( A => n1565, B => EX_INSTR_26_port, Y => n1528);
U3175 : NAND4XL port map( A => EX_INSTR_30_port, B => n1577, C =>
EX_INSTR_29_port, D => EX_INSTR_27_port, Y => n1538)
;
U3176 : NAND3XL port map( A => EX_INSTR_30_port, B => n1580, C => n1397, Y
=> n1541);
U3177 : NAND2BXL port map( AN => n1578, B => n1611, Y => n1377);
U3178 : AOI33XL port map( A0 => n1580, A1 => EX_INSTR_31_port, A2 => n1577,
B0 => EX_INSTR_29_port, B1 => n1573, B2 => n1581, Y
=> n1578);
U3179 : OAI211XL port map( A0 => n1547, A1 => n1577, B0 => EX_INSTR_31_port,
C0 => n1563, Y => n1571);
U3180 : AOI2B1XL port map( A1N => n2153, A0 => EX_REGB_3_port, B0 => n1353,
Y => n1352);
U3181 : INVXL port map( A => N4831, Y => n2168);
U3182 : NAND4XL port map( A => n1563, B => EX_INSTR_26_port, C => n1565, D
=> n1566, Y => n1351);
U3183 : NOR3XL port map( A => EX_INSTR_6_port, B => EX_INSTR_10_port, C =>
n1590, Y => n1561);
U3184 : OR3XL port map( A => EX_INSTR_9_port, B => EX_INSTR_8_port, C =>
EX_INSTR_7_port, Y => n1590);
U3185 : NOR3XL port map( A => n1550, B => EX_INSTR_1_port, C => n1540, Y =>
n1556);
U3186 : NAND3BXL port map( AN => EX_INSTR_4_port, B => EX_INSTR_5_port, C =>
n1561, Y => n1550);
U3187 : OAI32XL port map( A0 => n1553, A1 => n1582, A2 => n1374, B0 => n1574
, B1 => n1583, Y => EX_ADD_SUB);
U3188 : OAI21XL port map( A0 => n1567, A1 => n1570, B0 => n1374, Y => n1583)
;
U3189 : NOR3XL port map( A => n1550, B => EX_INSTR_2_port, C => n1560, Y =>
n1582);
U3190 : NAND3XL port map( A => EX_INSTR_3_port, B => EX_INSTR_5_port, C =>
n1587, Y => n1537);
U3191 : NOR3XL port map( A => n1560, B => EX_INSTR_2_port, C => n1588, Y =>
n1587);
U3192 : INVXL port map( A => EX_INSTR_2_port, Y => n1549);
U3193 : NAND3XL port map( A => EX_INSTR_5_port, B => EX_INSTR_0_port, C =>
n1589, Y => n1539);
U3194 : NOR3XL port map( A => n1549, B => EX_INSTR_1_port, C => n1588, Y =>
n1589);
U3195 : INVXL port map( A => EX_INSTR_3_port, Y => n1540);
U3196 : NAND2XL port map( A => n1228, B => n1229, Y => N760);
U3197 : AOI22XL port map( A0 => RF_OUT1(30), A1 => n1646, B0 =>
IF_PC_INC_30_port, B1 => n1225, Y => n1229);
U3198 : AOI22XL port map( A0 => ID_PC_30_port, A1 => n1226, B0 =>
ID_PC_SUM_30_port, B1 => n1227, Y => n1228);
U3199 : XOR2XL port map( A => PORT_PC_30_port, B => add_502_carry_30_port, Y
=> IF_PC_INC_30_port);
U3200 : NAND2XL port map( A => n1230, B => n1231, Y => N759);
U3201 : AOI22XL port map( A0 => RF_OUT1(29), A1 => n2148, B0 =>
IF_PC_INC_29_port, B1 => n1225, Y => n1231);
U3202 : AOI22XL port map( A0 => ID_PC_29_port, A1 => n1226, B0 =>
ID_PC_SUM_29_port, B1 => n1227, Y => n1230);
U3203 : XOR2XL port map( A => PORT_PC_29_port, B => add_502_carry_29_port, Y
=> IF_PC_INC_29_port);
U3204 : NAND2XL port map( A => n1232, B => n1233, Y => N758);
U3205 : AOI22XL port map( A0 => RF_OUT1(28), A1 => n1646, B0 =>
IF_PC_INC_28_port, B1 => n2147, Y => n1233);
U3206 : AOI22XL port map( A0 => ID_PC_28_port, A1 => n1226, B0 =>
ID_PC_SUM_28_port, B1 => n1227, Y => n1232);
U3207 : XOR2XL port map( A => PORT_PC_28_port, B => add_502_carry_28_port, Y
=> IF_PC_INC_28_port);
U3208 : NAND2XL port map( A => n1234, B => n1235, Y => N757);
U3209 : AOI22XL port map( A0 => RF_OUT1(27), A1 => n2148, B0 =>
IF_PC_INC_27_port, B1 => n1225, Y => n1235);
U3210 : AOI22XL port map( A0 => ID_PC_27_port, A1 => n1226, B0 =>
ID_PC_SUM_27_port, B1 => n1227, Y => n1234);
U3211 : XOR2XL port map( A => PORT_PC_27_port, B => add_502_carry_27_port, Y
=> IF_PC_INC_27_port);
U3212 : NAND2XL port map( A => n1236, B => n1237, Y => N756);
U3213 : AOI22XL port map( A0 => RF_OUT1(26), A1 => n2148, B0 =>
IF_PC_INC_26_port, B1 => n1225, Y => n1237);
U3214 : AOI22XL port map( A0 => ID_PC_26_port, A1 => n1226, B0 =>
ID_PC_SUM_26_port, B1 => n1227, Y => n1236);
U3215 : XOR2XL port map( A => PORT_PC_26_port, B => add_502_carry_26_port, Y
=> IF_PC_INC_26_port);
U3216 : NAND2XL port map( A => n1238, B => n1239, Y => N755);
U3217 : AOI22XL port map( A0 => RF_OUT1(25), A1 => n1646, B0 =>
IF_PC_INC_25_port, B1 => n2147, Y => n1239);
U3218 : AOI22XL port map( A0 => RF_ADD_RD1_4_port, A1 => n1226, B0 =>
ID_PC_SUM_25_port, B1 => n1227, Y => n1238);
U3219 : XOR2XL port map( A => PORT_PC_25_port, B => add_502_carry_25_port, Y
=> IF_PC_INC_25_port);
U3220 : NAND2XL port map( A => n1222, B => n1223, Y => N761);
U3221 : AOI22XL port map( A0 => RF_OUT1(31), A1 => n2148, B0 =>
IF_PC_INC_31_port, B1 => n1225, Y => n1223);
U3222 : AOI22XL port map( A0 => ID_PC_31_port, A1 => n2146, B0 =>
ID_PC_SUM_31_port, B1 => n1227, Y => n1222);
U3223 : XOR2XL port map( A => PORT_PC_31_port, B => add_502_carry_31_port, Y
=> IF_PC_INC_31_port);
U3224 : AND2XL port map( A => ID_PC_2_port, B => ID_IMM16_SHL2_2_port, Y =>
add_545_carry_3_port);
U3225 : AOI33XL port map( A0 => n1535, A1 => EX_INSTR_27_port, A2 => n1528,
B0 => n1548, B1 => EX_INSTR_1_port, B2 => n1534, Y
=> n1533);
U3226 : OAI31XL port map( A0 => n1554, A1 => EX_INSTR_2_port, A2 => n1374,
B0 => n1555, Y => EX_COMPARATOR_CW_1_port);
U3227 : NAND2XL port map( A => n1556, B => EX_INSTR_0_port, Y => n1554);
U3228 : NOR3XL port map( A => n1549, B => EX_INSTR_3_port, C => n1550, Y =>
n1534);
U3229 : OAI21XL port map( A0 => n1523, A1 => n1374, B0 => n1524, Y =>
EX_SHIFTER_CW_1_port);
U3230 : AOI31XL port map( A0 => n1525, A1 => n1374, A2 => n1526, B0 => n1527
, Y => n1524);
U3231 : NAND3XL port map( A => n1528, B => EX_INSTR_27_port, C => n1399, Y
=> n1526);
U3232 : AOI33XL port map( A0 => n1527, A1 => EX_INSTR_0_port, A2 => n1534,
B0 => n1397, B1 => n1398, B2 => n1535, Y => n1532);
U3233 : NAND3XL port map( A => EX_INSTR_2_port, B => n1561, C => n1562, Y =>
n1559);
U3234 : NOR3XL port map( A => EX_INSTR_3_port, B => EX_INSTR_5_port, C =>
EX_INSTR_4_port, Y => n1562);
U3235 : NOR2XL port map( A => n1374, B => EX_INSTR_1_port, Y => n1527);
U3236 : INVXL port map( A => EX_INSTR_0_port, Y => n1542);
U3237 : NAND2XL port map( A => n1240, B => n1241, Y => N754);
U3238 : AOI22XL port map( A0 => RF_OUT1(24), A1 => n1646, B0 =>
IF_PC_INC_24_port, B1 => n1225, Y => n1241);
U3239 : AOI22XL port map( A0 => RF_ADD_RD1_3_port, A1 => n2146, B0 =>
ID_PC_SUM_24_port, B1 => n1227, Y => n1240);
U3240 : XOR2XL port map( A => PORT_PC_24_port, B => add_502_carry_24_port, Y
=> IF_PC_INC_24_port);
U3241 : NAND2XL port map( A => n1242, B => n1243, Y => N753);
U3242 : AOI22XL port map( A0 => RF_OUT1(23), A1 => n2148, B0 =>
IF_PC_INC_23_port, B1 => n2147, Y => n1243);
U3243 : AOI22XL port map( A0 => RF_ADD_RD1_2_port, A1 => n1226, B0 =>
ID_PC_SUM_23_port, B1 => n1227, Y => n1242);
U3244 : XOR2XL port map( A => PORT_PC_23_port, B => add_502_carry_23_port, Y
=> IF_PC_INC_23_port);
U3245 : NAND2XL port map( A => n1244, B => n1245, Y => N752);
U3246 : AOI22XL port map( A0 => RF_OUT1(22), A1 => n2148, B0 =>
IF_PC_INC_22_port, B1 => n2147, Y => n1245);
U3247 : AOI22XL port map( A0 => RF_ADD_RD1_1_port, A1 => n2146, B0 =>
ID_PC_SUM_22_port, B1 => n1227, Y => n1244);
U3248 : XOR2XL port map( A => PORT_PC_22_port, B => add_502_carry_22_port, Y
=> IF_PC_INC_22_port);
U3249 : NAND2XL port map( A => n1246, B => n1247, Y => N751);
U3250 : AOI22XL port map( A0 => RF_OUT1(21), A1 => n2148, B0 =>
IF_PC_INC_21_port, B1 => n2147, Y => n1247);
U3251 : AOI22XL port map( A0 => RF_ADD_RD1_0_port, A1 => n2146, B0 =>
ID_PC_SUM_21_port, B1 => n1227, Y => n1246);
U3252 : XOR2XL port map( A => PORT_PC_21_port, B => add_502_carry_21_port, Y
=> IF_PC_INC_21_port);
U3253 : NAND2XL port map( A => n1248, B => n1249, Y => N750);
U3254 : AOI22XL port map( A0 => RF_OUT1(20), A1 => n2148, B0 =>
IF_PC_INC_20_port, B1 => n2147, Y => n1249);
U3255 : AOI22XL port map( A0 => RF_ADD_RD2_4_port, A1 => n2146, B0 =>
ID_PC_SUM_20_port, B1 => n1227, Y => n1248);
U3256 : XOR2XL port map( A => PORT_PC_20_port, B => add_502_carry_20_port, Y
=> IF_PC_INC_20_port);
U3257 : NAND2XL port map( A => n1250, B => n1251, Y => N749);
U3258 : AOI22XL port map( A0 => RF_OUT1(19), A1 => n2148, B0 =>
IF_PC_INC_19_port, B1 => n2147, Y => n1251);
U3259 : AOI22XL port map( A0 => RF_ADD_RD2_3_port, A1 => n2146, B0 =>
ID_PC_SUM_19_port, B1 => n1227, Y => n1250);
U3260 : XOR2XL port map( A => PORT_PC_19_port, B => add_502_carry_19_port, Y
=> IF_PC_INC_19_port);
U3261 : NAND2XL port map( A => n1252, B => n1253, Y => N748);
U3262 : AOI22XL port map( A0 => RF_OUT1(18), A1 => n1646, B0 =>
IF_PC_INC_18_port, B1 => n2147, Y => n1253);
U3263 : AOI22XL port map( A0 => RF_ADD_RD2_2_port, A1 => n2146, B0 =>
ID_PC_SUM_18_port, B1 => n1227, Y => n1252);
U3264 : XOR2XL port map( A => PORT_PC_18_port, B => add_502_carry_18_port, Y
=> IF_PC_INC_18_port);
U3265 : NAND2XL port map( A => n1254, B => n1255, Y => N747);
U3266 : AOI22XL port map( A0 => RF_OUT1(17), A1 => n1646, B0 =>
IF_PC_INC_17_port, B1 => n2147, Y => n1255);
U3267 : AOI22XL port map( A0 => RF_ADD_RD2_1_port, A1 => n2146, B0 =>
ID_PC_SUM_17_port, B1 => n1227, Y => n1254);
U3268 : XOR2XL port map( A => PORT_PC_17_port, B => add_502_carry_17_port, Y
=> IF_PC_INC_17_port);
U3269 : NAND2XL port map( A => n1256, B => n1257, Y => N746);
U3270 : AOI22XL port map( A0 => RF_OUT1(16), A1 => n1646, B0 =>
IF_PC_INC_16_port, B1 => n2147, Y => n1257);
U3271 : AOI22XL port map( A0 => RF_ADD_RD2_0_port, A1 => n2146, B0 =>
ID_PC_SUM_16_port, B1 => n1227, Y => n1256);
U3272 : XOR2XL port map( A => PORT_PC_16_port, B => add_502_carry_16_port, Y
=> IF_PC_INC_16_port);
U3273 : NAND2XL port map( A => n1258, B => n1259, Y => N745);
U3274 : AOI22XL port map( A0 => RF_OUT1(15), A1 => n2148, B0 =>
IF_PC_INC_15_port, B1 => n2147, Y => n1259);
U3275 : AOI22XL port map( A0 => n2109, A1 => n2146, B0 => ID_PC_SUM_15_port,
B1 => n1227, Y => n1258);
U3276 : XOR2XL port map( A => PORT_PC_15_port, B => add_502_carry_15_port, Y
=> IF_PC_INC_15_port);
U3277 : NAND2XL port map( A => n1260, B => n1261, Y => N744);
U3278 : AOI22XL port map( A0 => RF_OUT1(14), A1 => n1646, B0 =>
IF_PC_INC_14_port, B1 => n2147, Y => n1261);
U3279 : AOI22XL port map( A0 => ID_IMM16_SHL2_16_port, A1 => n2146, B0 =>
ID_PC_SUM_14_port, B1 => n1227, Y => n1260);
U3280 : XOR2XL port map( A => PORT_PC_14_port, B => add_502_carry_14_port, Y
=> IF_PC_INC_14_port);
U3281 : NAND2XL port map( A => n1262, B => n1263, Y => N743);
U3282 : AOI22XL port map( A0 => RF_OUT1(13), A1 => n1646, B0 =>
IF_PC_INC_13_port, B1 => n2147, Y => n1263);
U3283 : AOI22XL port map( A0 => ID_IMM16_SHL2_15_port, A1 => n2146, B0 =>
ID_PC_SUM_13_port, B1 => n1227, Y => n1262);
U3284 : XOR2XL port map( A => PORT_PC_13_port, B => add_502_carry_13_port, Y
=> IF_PC_INC_13_port);
U3285 : NAND2XL port map( A => n1264, B => n1265, Y => N742);
U3286 : AOI22XL port map( A0 => RF_OUT1(12), A1 => n1646, B0 =>
IF_PC_INC_12_port, B1 => n2147, Y => n1265);
U3287 : AOI22XL port map( A0 => ID_IMM16_SHL2_14_port, A1 => n2146, B0 =>
ID_PC_SUM_12_port, B1 => n1227, Y => n1264);
U3288 : XOR2XL port map( A => PORT_PC_12_port, B => add_502_carry_12_port, Y
=> IF_PC_INC_12_port);
U3289 : NAND2XL port map( A => n1266, B => n1267, Y => N741);
U3290 : AOI22XL port map( A0 => RF_OUT1(11), A1 => n1646, B0 =>
IF_PC_INC_11_port, B1 => n2147, Y => n1267);
U3291 : AOI22XL port map( A0 => ID_IMM16_SHL2_13_port, A1 => n2146, B0 =>
ID_PC_SUM_11_port, B1 => n1227, Y => n1266);
U3292 : XOR2XL port map( A => PORT_PC_11_port, B => add_502_carry_11_port, Y
=> IF_PC_INC_11_port);
U3293 : NAND2XL port map( A => n1268, B => n1269, Y => N740);
U3294 : AOI22XL port map( A0 => RF_OUT1(10), A1 => n1646, B0 =>
IF_PC_INC_10_port, B1 => n2147, Y => n1269);
U3295 : AOI22XL port map( A0 => ID_IMM16_SHL2_12_port, A1 => n2146, B0 =>
ID_PC_SUM_10_port, B1 => n1227, Y => n1268);
U3296 : XOR2XL port map( A => PORT_PC_10_port, B => add_502_carry_10_port, Y
=> IF_PC_INC_10_port);
U3297 : AND2XL port map( A => PORT_PC_2_port, B => PORT_PC_3_port, Y =>
add_502_carry_4_port);
U3298 : AND2XL port map( A => add_502_carry_29_port, B => PORT_PC_29_port, Y
=> add_502_carry_30_port);
U3299 : AND2XL port map( A => add_502_carry_28_port, B => PORT_PC_28_port, Y
=> add_502_carry_29_port);
U3300 : AND2XL port map( A => add_502_carry_27_port, B => PORT_PC_27_port, Y
=> add_502_carry_28_port);
U3301 : AND2XL port map( A => add_502_carry_26_port, B => PORT_PC_26_port, Y
=> add_502_carry_27_port);
U3302 : AND2XL port map( A => add_502_carry_25_port, B => PORT_PC_25_port, Y
=> add_502_carry_26_port);
U3303 : AND2XL port map( A => add_502_carry_24_port, B => PORT_PC_24_port, Y
=> add_502_carry_25_port);
U3304 : AND2XL port map( A => add_502_carry_23_port, B => PORT_PC_23_port, Y
=> add_502_carry_24_port);
U3305 : AND2XL port map( A => add_502_carry_22_port, B => PORT_PC_22_port, Y
=> add_502_carry_23_port);
U3306 : AND2XL port map( A => add_502_carry_21_port, B => PORT_PC_21_port, Y
=> add_502_carry_22_port);
U3307 : AND2XL port map( A => add_502_carry_20_port, B => PORT_PC_20_port, Y
=> add_502_carry_21_port);
U3308 : AND2XL port map( A => add_502_carry_19_port, B => PORT_PC_19_port, Y
=> add_502_carry_20_port);
U3309 : AND2XL port map( A => add_502_carry_18_port, B => PORT_PC_18_port, Y
=> add_502_carry_19_port);
U3310 : AND2XL port map( A => add_502_carry_17_port, B => PORT_PC_17_port, Y
=> add_502_carry_18_port);
U3311 : AND2XL port map( A => add_502_carry_16_port, B => PORT_PC_16_port, Y
=> add_502_carry_17_port);
U3312 : AND2XL port map( A => add_502_carry_15_port, B => PORT_PC_15_port, Y
=> add_502_carry_16_port);
U3313 : AND2XL port map( A => add_502_carry_14_port, B => PORT_PC_14_port, Y
=> add_502_carry_15_port);
U3314 : AND2XL port map( A => add_502_carry_13_port, B => PORT_PC_13_port, Y
=> add_502_carry_14_port);
U3315 : AND2XL port map( A => add_502_carry_12_port, B => PORT_PC_12_port, Y
=> add_502_carry_13_port);
U3316 : AND2XL port map( A => add_502_carry_11_port, B => PORT_PC_11_port, Y
=> add_502_carry_12_port);
U3317 : AND2XL port map( A => add_502_carry_10_port, B => PORT_PC_10_port, Y
=> add_502_carry_11_port);
U3318 : AND2XL port map( A => add_502_carry_9_port, B => PORT_PC_9_port, Y
=> add_502_carry_10_port);
U3319 : AND2XL port map( A => add_502_carry_8_port, B => PORT_PC_8_port, Y
=> add_502_carry_9_port);
U3320 : AND2XL port map( A => add_502_carry_7_port, B => PORT_PC_7_port, Y
=> add_502_carry_8_port);
U3321 : AND2XL port map( A => add_502_carry_6_port, B => PORT_PC_6_port, Y
=> add_502_carry_7_port);
U3322 : AND2XL port map( A => add_502_carry_5_port, B => PORT_PC_5_port, Y
=> add_502_carry_6_port);
U3323 : AND2XL port map( A => add_502_carry_4_port, B => PORT_PC_4_port, Y
=> add_502_carry_5_port);
U3324 : AND2XL port map( A => add_502_carry_30_port, B => PORT_PC_30_port, Y
=> add_502_carry_31_port);
U3325 : AOI21XL port map( A0 => ID_INSTR_28, A1 => n1481, B0 => n1520, Y =>
n1521);
U3326 : NOR3XL port map( A => n1478, B => ID_INSTR_28, C => n1518, Y =>
n1358);
U3327 : NOR4XL port map( A => RF_OUT1(27), B => RF_OUT1(26), C =>
RF_OUT1(25), D => RF_OUT1(24), Y => zero_instance_n7
);
U3328 : NOR4XL port map( A => RF_OUT1(23), B => RF_OUT1(22), C =>
RF_OUT1(21), D => RF_OUT1(20), Y => zero_instance_n6
);
U3329 : NOR4XL port map( A => RF_OUT1(9), B => RF_OUT1(8), C => RF_OUT1(7),
D => RF_OUT1(6), Y => zero_instance_n10);
U3330 : NOR4XL port map( A => RF_OUT1(30), B => RF_OUT1(2), C => RF_OUT1(29)
, D => RF_OUT1(28), Y => zero_instance_n8);
U3331 : NOR4XL port map( A => RF_OUT1(5), B => RF_OUT1(4), C => RF_OUT1(3),
D => RF_OUT1(31), Y => zero_instance_n9);
U3332 : NOR2XL port map( A => n1290, B => ID_INSTR_26, Y => n1194);
U3333 : NOR2XL port map( A => ID_INSTR_26, B => ID_INSTR_28, Y => n1520);
U3334 : NAND4XL port map( A => zero_instance_n3, B => zero_instance_n4, C =>
zero_instance_n5, D => zero_instance_n6, Y =>
zero_instance_n2);
U3335 : NOR4XL port map( A => RF_OUT1(12), B => RF_OUT1(11), C =>
RF_OUT1(10), D => RF_OUT1(0), Y => zero_instance_n3)
;
U3336 : NOR4XL port map( A => RF_OUT1(16), B => RF_OUT1(15), C =>
RF_OUT1(14), D => RF_OUT1(13), Y => zero_instance_n4
);
U3337 : NOR4XL port map( A => RF_OUT1(1), B => RF_OUT1(19), C => RF_OUT1(18)
, D => RF_OUT1(17), Y => zero_instance_n5);
U3338 : NAND2XL port map( A => ID_INSTR_31, B => n1483, Y => n1196);
U3339 : INVXL port map( A => ID_INSTR_27, Y => n1484);
U3340 : INVXL port map( A => ID_INSTR_29, Y => n1481);
U3341 : INVXL port map( A => ID_INSTR_31, Y => n1488);
U3342 : INVXL port map( A => ID_IMM16_SHL2_9_port, Y => n1205);
U3343 : INVXL port map( A => ID_IMM16_SHL2_11_port, Y => n1204);
U3344 : INVXL port map( A => ID_IMM16_SHL2_10_port, Y => n1203);
U3345 : INVXL port map( A => RF_ADD_RD2_1_port, Y => n1433);
U3346 : AND2XL port map( A => ID_SIGN_EXT_CONTROL, B => n2109, Y =>
ID_IMM16_EXT_31_port);
U3347 : NAND4XL port map( A => n1498, B => n1515, C => N4717, D => n1292, Y
=> ID_SIGN_EXT_CONTROL);
U3348 : OAI211XL port map( A0 => n1519, A1 => n1520, B0 => n1488, C0 =>
ID_INSTR_29, Y => n1515);
U3349 : AOI21XL port map( A0 => ID_INSTR_28, A1 => ID_INSTR_27, B0 => n1483,
Y => n1519);
U3350 : NAND2XL port map( A => n1286, B => n1287, Y => N731);
U3351 : AOI22XL port map( A0 => n2146, A1 => ID_IMM16_SHL2_3_port, B0 =>
ID_PC_SUM_1_port, B1 => n1227, Y => n1286);
U3352 : AOI22XL port map( A0 => RF_OUT1(1), A1 => n2148, B0 =>
IF_PC_INC_1_port, B1 => n2147, Y => n1287);
U3353 : NAND2XL port map( A => n1288, B => n1289, Y => N730);
U3354 : AOI22XL port map( A0 => ID_IMM16_SHL2_2_port, A1 => n2146, B0 =>
ID_PC_SUM_0_port, B1 => n1227, Y => n1288);
U3355 : AOI22XL port map( A0 => RF_OUT1(0), A1 => n2148, B0 =>
IF_PC_INC_0_port, B1 => n2147, Y => n1289);
U3356 : NAND2XL port map( A => n1270, B => n1271, Y => N739);
U3357 : AOI22XL port map( A0 => RF_OUT1(9), A1 => n1646, B0 =>
IF_PC_INC_9_port, B1 => n2147, Y => n1271);
U3358 : AOI22XL port map( A0 => ID_IMM16_SHL2_11_port, A1 => n2146, B0 =>
ID_PC_SUM_9_port, B1 => n1227, Y => n1270);
U3359 : XOR2XL port map( A => PORT_PC_9_port, B => add_502_carry_9_port, Y
=> IF_PC_INC_9_port);
U3360 : NAND2XL port map( A => n1272, B => n1273, Y => N738);
U3361 : AOI22XL port map( A0 => ID_IMM16_SHL2_10_port, A1 => n2146, B0 =>
ID_PC_SUM_8_port, B1 => n1227, Y => n1272);
U3362 : AOI22XL port map( A0 => RF_OUT1(8), A1 => n1646, B0 =>
IF_PC_INC_8_port, B1 => n2147, Y => n1273);
U3363 : XOR2XL port map( A => PORT_PC_8_port, B => add_502_carry_8_port, Y
=> IF_PC_INC_8_port);
U3364 : NAND2XL port map( A => n1274, B => n1275, Y => N737);
U3365 : AOI22XL port map( A0 => ID_IMM16_SHL2_9_port, A1 => n2146, B0 =>
ID_PC_SUM_7_port, B1 => n1227, Y => n1274);
U3366 : AOI22XL port map( A0 => RF_OUT1(7), A1 => n1646, B0 =>
IF_PC_INC_7_port, B1 => n2147, Y => n1275);
U3367 : XOR2XL port map( A => PORT_PC_7_port, B => add_502_carry_7_port, Y
=> IF_PC_INC_7_port);
U3368 : NAND2XL port map( A => n1276, B => n1277, Y => N736);
U3369 : AOI22XL port map( A0 => ID_IMM16_SHL2_8_port, A1 => n2146, B0 =>
ID_PC_SUM_6_port, B1 => n1227, Y => n1276);
U3370 : AOI22XL port map( A0 => RF_OUT1(6), A1 => n2148, B0 =>
IF_PC_INC_6_port, B1 => n2147, Y => n1277);
U3371 : XOR2XL port map( A => PORT_PC_6_port, B => add_502_carry_6_port, Y
=> IF_PC_INC_6_port);
U3372 : NAND2XL port map( A => n1278, B => n1279, Y => N735);
U3373 : AOI22XL port map( A0 => ID_IMM16_SHL2_7_port, A1 => n2146, B0 =>
ID_PC_SUM_5_port, B1 => n1227, Y => n1278);
U3374 : AOI22XL port map( A0 => RF_OUT1(5), A1 => n2148, B0 =>
IF_PC_INC_5_port, B1 => n2147, Y => n1279);
U3375 : XOR2XL port map( A => PORT_PC_5_port, B => add_502_carry_5_port, Y
=> IF_PC_INC_5_port);
U3376 : NAND2XL port map( A => n1280, B => n1281, Y => N734);
U3377 : AOI22XL port map( A0 => ID_IMM16_SHL2_6_port, A1 => n2146, B0 =>
ID_PC_SUM_4_port, B1 => n1227, Y => n1280);
U3378 : AOI22XL port map( A0 => RF_OUT1(4), A1 => n2148, B0 =>
IF_PC_INC_4_port, B1 => n2147, Y => n1281);
U3379 : XOR2XL port map( A => PORT_PC_4_port, B => add_502_carry_4_port, Y
=> IF_PC_INC_4_port);
U3380 : NAND2XL port map( A => n1282, B => n1283, Y => N733);
U3381 : AOI22XL port map( A0 => n2146, A1 => ID_IMM16_SHL2_5_port, B0 =>
ID_PC_SUM_3_port, B1 => n1227, Y => n1282);
U3382 : AOI22XL port map( A0 => RF_OUT1(3), A1 => n2148, B0 =>
IF_PC_INC_3_port, B1 => n2147, Y => n1283);
U3383 : XOR2XL port map( A => PORT_PC_3_port, B => PORT_PC_2_port, Y =>
IF_PC_INC_3_port);
U3384 : NAND2XL port map( A => n1284, B => n1285, Y => N732);
U3385 : AOI22XL port map( A0 => n2146, A1 => ID_IMM16_SHL2_4_port, B0 =>
ID_PC_SUM_2_port, B1 => n1227, Y => n1284);
U3386 : AOI22XL port map( A0 => RF_OUT1(2), A1 => n2148, B0 =>
IF_PC_INC_2_port, B1 => n2147, Y => n1285);
U3387 : XOR2XL port map( A => ID_IMM16_SHL2_2_port, B => ID_PC_2_port, Y =>
ID_PC_SUM_2_port);
U3388 : OR4XL port map( A => n1196, B => n1484, C => n1518, D => ID_INSTR_28
, Y => n1198);
U3389 : INVXL port map( A => RF_ADD_RD2_3_port, Y => n1434);
U3390 : INVXL port map( A => RF_ADD_RD2_0_port, Y => n1432);
U3391 : NOR2BXL port map( AN => RF_ADD_RD2_2_port, B => n1618, Y =>
ID_INSTR_AFTER_CU_18_port);
U3392 : NOR2BXL port map( AN => RF_ADD_RD2_4_port, B => n1618, Y =>
ID_INSTR_AFTER_CU_20_port);
U3393 : INVXL port map( A => PORT_PC_2_port, Y => IF_PC_INC_2_port);
U3394 : NAND2BXL port map( AN => PORT_INSTR_IRAM(26), B => n2154, Y => N790)
;
U3395 : NAND2BXL port map( AN => PORT_INSTR_IRAM(30), B => n2154, Y => N794)
;
U3396 : NAND2BXL port map( AN => PORT_INSTR_IRAM(28), B => n2154, Y => N792)
;
U3397 : AND2XL port map( A => ID_IMM16_SHL2_5_port, B => n1522, Y =>
ID_INSTR_AFTER_CU_3_port);
U3398 : AND2XL port map( A => ID_IMM16_SHL2_3_port, B => n1522, Y =>
ID_INSTR_AFTER_CU_1_port);
U3399 : AND2XL port map( A => ID_IMM16_SHL2_12_port, B => n1522, Y =>
ID_INSTR_AFTER_CU_10_port);
U3400 : AND2XL port map( A => ID_IMM16_SHL2_8_port, B => n1522, Y =>
ID_INSTR_AFTER_CU_6_port);
U3401 : AND2XL port map( A => ID_IMM16_SHL2_6_port, B => n1522, Y =>
ID_INSTR_AFTER_CU_4_port);
U3402 : AND2XL port map( A => ID_IMM16_SHL2_7_port, B => n1522, Y =>
ID_INSTR_AFTER_CU_5_port);
U3403 : AND2XL port map( A => ID_IMM16_SHL2_4_port, B => n1522, Y =>
ID_INSTR_AFTER_CU_2_port);
U3404 : AND2XL port map( A => ID_IMM16_SHL2_2_port, B => n1522, Y =>
ID_INSTR_AFTER_CU_0_port);
U3405 : AND2XL port map( A => ID_IMM16_SHL2_15_port, B => n1522, Y =>
ID_INSTR_AFTER_CU_13_port);
U3406 : AND2XL port map( A => ID_IMM16_SHL2_14_port, B => n1522, Y =>
ID_INSTR_AFTER_CU_12_port);
U3407 : AND2XL port map( A => ID_IMM16_SHL2_13_port, B => n1522, Y =>
ID_INSTR_AFTER_CU_11_port);
U3408 : AND2XL port map( A => ID_IMM16_SHL2_16_port, B => n1522, Y =>
ID_INSTR_AFTER_CU_14_port);
U3409 : AND2XL port map( A => PORT_INSTR_IRAM(25), B => n2154, Y => N789);
U3410 : AND2XL port map( A => PORT_INSTR_IRAM(16), B => n2154, Y => N780);
U3411 : AND2XL port map( A => PORT_INSTR_IRAM(17), B => n2154, Y => N781);
U3412 : AND2XL port map( A => PORT_INSTR_IRAM(31), B => n2154, Y => N795);
U3413 : AND2XL port map( A => PORT_INSTR_IRAM(27), B => n2154, Y => N791);
U3414 : AND2XL port map( A => PORT_INSTR_IRAM(0), B => n2155, Y => N764);
U3415 : AND2XL port map( A => PORT_INSTR_IRAM(29), B => n2154, Y => N793);
U3416 : AND2XL port map( A => PORT_INSTR_IRAM(20), B => n2154, Y => N784);
U3417 : AND2XL port map( A => PORT_INSTR_IRAM(21), B => n2154, Y => N785);
U3418 : AND2XL port map( A => PORT_INSTR_IRAM(24), B => n2154, Y => N788);
U3419 : AND2XL port map( A => PORT_INSTR_IRAM(19), B => n2154, Y => N783);
U3420 : AND2XL port map( A => PORT_INSTR_IRAM(23), B => n2154, Y => N787);
U3421 : AND2XL port map( A => PORT_INSTR_IRAM(22), B => n2154, Y => N786);
U3422 : AND2XL port map( A => PORT_INSTR_IRAM(18), B => n2154, Y => N782);
U3423 : AND2XL port map( A => PORT_INSTR_IRAM(14), B => n2154, Y => N778);
U3424 : AND2XL port map( A => PORT_INSTR_IRAM(13), B => n2154, Y => N777);
U3425 : AND2XL port map( A => PORT_INSTR_IRAM(12), B => n2154, Y => N776);
U3426 : AND2XL port map( A => PORT_INSTR_IRAM(11), B => n2154, Y => N775);
U3427 : AND2XL port map( A => PORT_INSTR_IRAM(9), B => n2155, Y => N773);
U3428 : AND2XL port map( A => PORT_INSTR_IRAM(8), B => n2155, Y => N772);
U3429 : AND2XL port map( A => PORT_INSTR_IRAM(7), B => n2155, Y => N771);
U3430 : AND2XL port map( A => PORT_INSTR_IRAM(3), B => n2155, Y => N767);
U3431 : AND2XL port map( A => PORT_INSTR_IRAM(1), B => n2155, Y => N765);
U3432 : AND2XL port map( A => PORT_INSTR_IRAM(2), B => n2155, Y => N766);
U3433 : AND2XL port map( A => PORT_INSTR_IRAM(5), B => n2155, Y => N769);
U3434 : AND2XL port map( A => PORT_INSTR_IRAM(4), B => n2155, Y => N768);
U3435 : AND2XL port map( A => PORT_INSTR_IRAM(10), B => n2154, Y => N774);
U3436 : AND2XL port map( A => PORT_INSTR_IRAM(6), B => n2155, Y => N770);
U3437 : AND2XL port map( A => PORT_INSTR_IRAM(15), B => n2154, Y => N779);
U3438 : CLKINVX1 port map( A => RESET, Y => ID_EX_IMM16_EXT_REG_instance_n34
);
U3439 : CLKINVX1 port map( A => RESET, Y => ID_EX_REGA_REG_instance_n34);
U3440 : CLKINVX1 port map( A => RESET, Y => ID_EX_PC_REG_instance_n34);
U3441 : CLKINVX1 port map( A => RESET, Y => EX_MEM_REGB_REG_instance_n34);
U3442 : CLKINVX1 port map( A => RESET, Y => EX_MEM_OUT_REG_instance_n34);
U3443 : CLKINVX1 port map( A => RESET, Y => MEM_WB_ALU_REG_instance_n34);
U3444 : CLKINVX1 port map( A => RESET, Y => ID_EX_REGB_REG_instance_n34);
U3445 : CLKINVX1 port map( A => RESET, Y => PC_instance_n33);
U3446 : INVXL port map( A => RESET, Y => ID_EX_INSTR_REG_instance_n34);
U3447 : OAI32XL port map( A0 => n1503, A1 => WB_INSTR_28, A2 => n1347, B0 =>
n1504, B1 => n1505, Y => n1468);
U3448 : OR3XL port map( A => WB_INSTR_6_port, B => WB_INSTR_10_port, C =>
n1514, Y => n1504);
U3449 : NAND3XL port map( A => n1340, B => n1348, C => n1471, Y => n1503);
U3450 : OAI211XL port map( A0 => WB_INSTR_5_port, A1 => n1506, B0 => n1507,
C0 => n1508, Y => n1505);
U3451 : OAI33XL port map( A0 => n1448, A1 => n1449, A2 => n1450, B0 => n1441
, B1 => n1447, B2 => n1446, Y => n1438);
U3452 : XOR2XL port map( A => RF_ADD_RD2_2_port, B => MEM_INSTR_13_port, Y
=> n1449);
U3453 : XOR2XL port map( A => RF_ADD_RD2_4_port, B => MEM_INSTR_15_port, Y
=> n1450);
U3454 : NAND3XL port map( A => n1454, B => n1455, C => n1456, Y => n1448);
U3455 : OAI221XL port map( A0 => n1478, A1 => n1479, B0 => n1480, B1 =>
n1481, C0 => n1482, Y => n1372);
U3456 : INVXL port map( A => n1195, Y => n1482);
U3457 : AOI32XL port map( A0 => n1196, A1 => n1484, A2 => n1485, B0 => n1486
, B1 => n1290, Y => n1480);
U3458 : OAI21XL port map( A0 => n1484, A1 => n1483, B0 => ID_INSTR_31, Y =>
n1486);
U3459 : AOI22XL port map( A0 => WB_ALU_15_port, A1 => n2121, B0 =>
WB_DATA_RAM_15_port, B1 => n1310, Y => n1312);
U3460 : AOI22XL port map( A0 => WB_ALU_7_port, A1 => n2121, B0 =>
WB_DATA_RAM_7_port, B1 => n1310, Y => n1328);
U3461 : AOI22XL port map( A0 => WB_ALU_8_port, A1 => n2121, B0 =>
WB_DATA_RAM_8_port, B1 => n1310, Y => n1326);
U3462 : AOI22XL port map( A0 => WB_ALU_9_port, A1 => n2121, B0 =>
WB_DATA_RAM_9_port, B1 => n1310, Y => n1324);
U3463 : AOI22XL port map( A0 => WB_ALU_10_port, A1 => n2121, B0 =>
WB_DATA_RAM_10_port, B1 => n1310, Y => n1322);
U3464 : AOI22XL port map( A0 => WB_ALU_11_port, A1 => n2121, B0 =>
WB_DATA_RAM_11_port, B1 => n1310, Y => n1320);
U3465 : AOI22XL port map( A0 => WB_ALU_12_port, A1 => n2121, B0 =>
WB_DATA_RAM_12_port, B1 => n1310, Y => n1318);
U3466 : AOI22XL port map( A0 => WB_ALU_13_port, A1 => n2121, B0 =>
WB_DATA_RAM_13_port, B1 => n1310, Y => n1316);
U3467 : AOI22XL port map( A0 => WB_ALU_14_port, A1 => n2121, B0 =>
WB_DATA_RAM_14_port, B1 => n1310, Y => n1314);
U3468 : OAI31XL port map( A0 => n1391, A1 => n1392, A2 => n1393, B0 => n1360
, Y => n1369);
U3469 : XOR2XL port map( A => RF_ADD_RD2_2_port, B => EX_INSTR_18_port, Y =>
n1392);
U3470 : XOR2XL port map( A => RF_ADD_RD2_4_port, B => EX_INSTR_20_port, Y =>
n1393);
U3471 : NAND3XL port map( A => n1394, B => n1395, C => n1396, Y => n1391);
U3472 : OAI211XL port map( A0 => EX_INSTR_31_port, A1 => n1400, B0 => n1377,
C0 => n1374, Y => n1361);
U3473 : NOR3XL port map( A => n1347, B => WB_INSTR_31, C => n1349, Y =>
n1339);
U3474 : NOR4XL port map( A => n1445, B => n1220, C => MEM_INSTR_27_port, D
=> MEM_INSTR_29_port, Y => n1214);
U3475 : XNOR2XL port map( A => EX_INSTR_17_port, B => RF_ADD_RD2_1_port, Y
=> n1396);
U3476 : XNOR2XL port map( A => MEM_INSTR_12_port, B => RF_ADD_RD2_1_port, Y
=> n1456);
U3477 : XNOR2XL port map( A => EX_INSTR_16_port, B => RF_ADD_RD2_0_port, Y
=> n1395);
U3478 : XNOR2XL port map( A => MEM_INSTR_11_port, B => RF_ADD_RD2_0_port, Y
=> n1455);
U3479 : XNOR2XL port map( A => EX_INSTR_19_port, B => RF_ADD_RD2_3_port, Y
=> n1394);
U3480 : XNOR2XL port map( A => MEM_INSTR_14_port, B => RF_ADD_RD2_3_port, Y
=> n1454);
U3481 : XNOR2XL port map( A => EX_INSTR_11_port, B => n1384, Y => n1378);
U3482 : XNOR2XL port map( A => MEM_INSTR_11_port, B => n1384, Y => n1446);
U3483 : XNOR2XL port map( A => n1407, B => EX_INSTR_20_port, Y => n1406);
U3484 : XNOR2XL port map( A => n1427, B => MEM_INSTR_18_port, Y => n1425);
U3485 : XNOR2XL port map( A => n1408, B => EX_INSTR_19_port, Y => n1404);
U3486 : XNOR2XL port map( A => n1433, B => MEM_INSTR_17_port, Y => n1429);
U3487 : NOR2XL port map( A => n1409, B => MEM_INSTR_30_port, Y => n1215);
U3488 : AOI211XL port map( A0 => WB_INSTR_0_port, A1 => n1512, B0 => n1513,
C0 => WB_INSTR_3_port, Y => n1506);
U3489 : INVXL port map( A => WB_INSTR_2_port, Y => n1513);
U3490 : OAI31XL port map( A0 => n1464, A1 => WB_INSTR_30, A2 => WB_INSTR_29,
B0 => n1341, Y => n1463);
U3491 : AOI22XL port map( A0 => n1466, A1 => WB_INSTR_26, B0 => n1467, B1 =>
WB_INSTR_31, Y => n1464);
U3492 : OAI21XL port map( A0 => WB_INSTR_30, A1 => n1338, B0 =>
WB_SIGN_EXT_16_CONTROL, Y => n1211);
U3493 : OAI21XL port map( A0 => n1445, A1 => n1219, B0 => n1213, Y => n1444)
;
U3494 : NOR4XL port map( A => n1428, B => n1429, C => n1430, D => n1431, Y
=> n1414);
U3495 : XOR2XL port map( A => RF_ADD_RD2_2_port, B => MEM_INSTR_18_port, Y
=> n1430);
U3496 : XNOR2XL port map( A => n1432, B => MEM_INSTR_16_port, Y => n1431);
U3497 : XNOR2XL port map( A => n1434, B => MEM_INSTR_19_port, Y => n1428);
U3498 : NOR4XL port map( A => n1423, B => n1424, C => n1425, D => n1426, Y
=> n1415);
U3499 : XOR2XL port map( A => RF_ADD_RD1_1_port, B => MEM_INSTR_17_port, Y
=> n1424);
U3500 : XNOR2XL port map( A => n1384, B => MEM_INSTR_16_port, Y => n1426);
U3501 : XNOR2XL port map( A => n1408, B => MEM_INSTR_19_port, Y => n1423);
U3502 : NOR4XL port map( A => n1417, B => n1418, C => n1419, D => n1420, Y
=> n1416);
U3503 : NAND2XL port map( A => n1421, B => n1422, Y => n1418);
U3504 : XNOR2XL port map( A => n1407, B => MEM_INSTR_20_port, Y => n1420);
U3505 : OAI2B2XL port map( A1N => n1467, A0 => WB_INSTR_26, B0 =>
WB_INSTR_29, B1 => n1349, Y => n1469);
U3506 : NOR2XL port map( A => WB_INSTR_29, B => WB_INSTR_27, Y => n1343);
U3507 : AOI32XL port map( A0 => WB_INSTR_1_port, A1 => n1509, A2 =>
WB_INSTR_2_port, B0 => WB_INSTR_4_port, B1 => n1510,
Y => n1508);
U3508 : NAND2XL port map( A => WB_INSTR_3_port, B => n1511, Y => n1510);
U3509 : AO21XL port map( A0 => WB_INSTR_0_port, A1 => WB_INSTR_5_port, B0 =>
WB_INSTR_3_port, Y => n1509);
U3510 : OAI2BB1XL port map( A0N => WB_INSTR_0_port, A1N => WB_INSTR_2_port,
B0 => n1512, Y => n1511);
U3511 : AOI32XL port map( A0 => n1214, A1 => n1409, A2 => MEM_INSTR_30_port,
B0 => n1410, B1 => n1411, Y => N4710);
U3512 : AOI32XL port map( A0 => n1412, A1 => n1413, A2 => n1414, B0 => n1415
, B1 => n1416, Y => n1411);
U3513 : AOI32XL port map( A0 => n1190, A1 => n1438, A2 => n1435, B0 => n1439
, B1 => n1440, Y => n1410);
U3514 : AOI2BB1XL port map( A0N => n1190, A1N => n1370, B0 => n1437, Y =>
n1412);
U3515 : NOR3XL port map( A => MEM_INSTR_29_port, B => MEM_INSTR_31_port, C
=> MEM_INSTR_30_port, Y => n1436);
U3516 : NOR3BXL port map( AN => n1217, B => n1212, C => MEM_INSTR_29_port, Y
=> PORT_R_W_port);
U3517 : XNOR2XL port map( A => n1218, B => n1219, Y => n1217);
U3518 : NAND2XL port map( A => MEM_INSTR_26_port, B => n1220, Y => n1218);
U3519 : OAI211XL port map( A0 => WB_INSTR_31, A1 => n1459, B0 => n1460, C0
=> n1461, Y => RF_WR_port);
U3520 : AOI31XL port map( A0 => WB_INSTR_29, A1 => n1462, A2 => WB_INSTR_30,
B0 => n1463, Y => n1461);
U3521 : INVXL port map( A => n1468, Y => n1460);
U3522 : AOI211XL port map( A0 => WB_INSTR_30, A1 => n1469, B0 => n1466, C0
=> n1470, Y => n1459);
U3523 : AO22XL port map( A0 => WB_ALU_0_port, A1 => n2121, B0 =>
WB_DATA_RAM_0_port, B1 => n1310, Y =>
WB_DATA_EXT_8_0_port);
U3524 : AO22XL port map( A0 => WB_ALU_1_port, A1 => n2121, B0 =>
WB_DATA_RAM_1_port, B1 => n1310, Y =>
WB_DATA_EXT_8_1_port);
U3525 : AO22XL port map( A0 => WB_ALU_2_port, A1 => n2121, B0 =>
WB_DATA_RAM_2_port, B1 => n1310, Y =>
WB_DATA_EXT_8_2_port);
U3526 : AO22XL port map( A0 => WB_ALU_3_port, A1 => n2121, B0 =>
WB_DATA_RAM_3_port, B1 => n1310, Y =>
WB_DATA_EXT_8_3_port);
U3527 : AO22XL port map( A0 => WB_ALU_4_port, A1 => n2121, B0 =>
WB_DATA_RAM_4_port, B1 => n1310, Y =>
WB_DATA_EXT_8_4_port);
U3528 : AO22XL port map( A0 => WB_ALU_5_port, A1 => n2121, B0 =>
WB_DATA_RAM_5_port, B1 => n1310, Y =>
WB_DATA_EXT_8_5_port);
U3529 : AO22XL port map( A0 => WB_ALU_6_port, A1 => n2121, B0 =>
WB_DATA_RAM_6_port, B1 => n1310, Y =>
WB_DATA_EXT_8_6_port);
U3530 : AND4XL port map( A => WB_INSTR_29, B => WB_INSTR_28, C => n1339, D
=> n1340, Y => n1822);
U3531 : AOI211XL port map( A0 => MEM_INSTR_29_port, A1 => MEM_INSTR_28_port,
B0 => n1212, C0 => n1213, Y => PORT_SIZE(1));
U3532 : NAND3XL port map( A => WB_INSTR_31, B => n1343, C => n1465, Y =>
n1341);
U3533 : NOR3XL port map( A => WB_INSTR_26, B => WB_INSTR_30, C =>
WB_INSTR_28, Y => n1465);
U3534 : OAI2B11XL port map( A1N => WB_DATA_RAM_16_port, A0 => n1207, B0 =>
n1208, C0 => n1308, Y => RF_DATAIN(16));
U3535 : AOI22XL port map( A0 => WB_ALU_16_port, A1 => n1617, B0 =>
WB_DATA_EXT_16_16_port, B1 => n2149, Y => n1308);
U3536 : OAI21XL port map( A0 => WB_SIGN_EXT_16_CONTROL, A1 =>
WB_SIGN_EXT_16_instance_n34, B0 =>
WB_SIGN_EXT_16_instance_n27, Y =>
WB_DATA_EXT_16_16_port);
U3537 : OAI2B11XL port map( A1N => WB_DATA_RAM_17_port, A0 => n1207, B0 =>
n1208, C0 => n1307, Y => RF_DATAIN(17));
U3538 : AOI22XL port map( A0 => WB_ALU_17_port, A1 => n1617, B0 =>
WB_DATA_EXT_16_17_port, B1 => n2149, Y => n1307);
U3539 : OAI21XL port map( A0 => WB_SIGN_EXT_16_CONTROL, A1 =>
WB_SIGN_EXT_16_instance_n33, B0 => n2110, Y =>
WB_DATA_EXT_16_17_port);
U3540 : OAI2B11XL port map( A1N => WB_DATA_RAM_18_port, A0 => n1207, B0 =>
n1208, C0 => n1306, Y => RF_DATAIN(18));
U3541 : AOI22XL port map( A0 => WB_ALU_18_port, A1 => n1617, B0 =>
WB_DATA_EXT_16_18_port, B1 => n2149, Y => n1306);
U3542 : OAI21XL port map( A0 => WB_SIGN_EXT_16_CONTROL, A1 =>
WB_SIGN_EXT_16_instance_n28, B0 =>
WB_SIGN_EXT_16_instance_n27, Y =>
WB_DATA_EXT_16_18_port);
U3543 : OAI2B11XL port map( A1N => WB_DATA_RAM_19_port, A0 => n1207, B0 =>
n2150, C0 => n1305, Y => RF_DATAIN(19));
U3544 : AOI22XL port map( A0 => WB_ALU_19_port, A1 => n1617, B0 =>
WB_DATA_EXT_16_19_port, B1 => n2149, Y => n1305);
U3545 : OAI21XL port map( A0 => WB_SIGN_EXT_16_CONTROL, A1 =>
WB_SIGN_EXT_16_instance_n25, B0 => n2110, Y =>
WB_DATA_EXT_16_19_port);
U3546 : OAI2B11XL port map( A1N => WB_DATA_RAM_20_port, A0 => n1207, B0 =>
n2150, C0 => n1304, Y => RF_DATAIN(20));
U3547 : AOI22XL port map( A0 => WB_ALU_20_port, A1 => n1617, B0 =>
WB_DATA_EXT_16_20_port, B1 => n2149, Y => n1304);
U3548 : OAI21XL port map( A0 => WB_SIGN_EXT_16_CONTROL, A1 =>
WB_SIGN_EXT_16_instance_n24, B0 =>
WB_SIGN_EXT_16_instance_n27, Y =>
WB_DATA_EXT_16_20_port);
U3549 : OAI2B11XL port map( A1N => WB_DATA_RAM_21_port, A0 => n1207, B0 =>
n2150, C0 => n1303, Y => RF_DATAIN(21));
U3550 : AOI22XL port map( A0 => WB_ALU_21_port, A1 => n1617, B0 =>
WB_DATA_EXT_16_21_port, B1 => n2149, Y => n1303);
U3551 : OAI21XL port map( A0 => WB_SIGN_EXT_16_CONTROL, A1 =>
WB_SIGN_EXT_16_instance_n23, B0 => n2110, Y =>
WB_DATA_EXT_16_21_port);
U3552 : OAI2B11XL port map( A1N => WB_DATA_RAM_22_port, A0 => n1207, B0 =>
n2150, C0 => n1302, Y => RF_DATAIN(22));
U3553 : AOI22XL port map( A0 => WB_ALU_22_port, A1 => n1617, B0 =>
WB_DATA_EXT_16_22_port, B1 => n1211, Y => n1302);
U3554 : OAI21XL port map( A0 => WB_SIGN_EXT_16_CONTROL, A1 =>
WB_SIGN_EXT_16_instance_n22, B0 =>
WB_SIGN_EXT_16_instance_n27, Y =>
WB_DATA_EXT_16_22_port);
U3555 : OAI2B11XL port map( A1N => WB_DATA_RAM_23_port, A0 => n1207, B0 =>
n2150, C0 => n1301, Y => RF_DATAIN(23));
U3556 : AOI22XL port map( A0 => WB_ALU_23_port, A1 => n1617, B0 =>
WB_DATA_EXT_16_23_port, B1 => n1211, Y => n1301);
U3557 : OAI21XL port map( A0 => WB_SIGN_EXT_16_CONTROL, A1 => n1328, B0 =>
n2110, Y => WB_DATA_EXT_16_23_port);
U3558 : OAI2B11XL port map( A1N => WB_DATA_RAM_24_port, A0 => n1207, B0 =>
n2150, C0 => n1300, Y => RF_DATAIN(24));
U3559 : AOI22XL port map( A0 => WB_ALU_24_port, A1 => n1617, B0 =>
WB_DATA_EXT_16_24_port, B1 => n1211, Y => n1300);
U3560 : OAI21XL port map( A0 => WB_SIGN_EXT_16_CONTROL, A1 => n1326, B0 =>
WB_SIGN_EXT_16_instance_n27, Y =>
WB_DATA_EXT_16_24_port);
U3561 : OAI2B11XL port map( A1N => WB_DATA_RAM_25_port, A0 => n1207, B0 =>
n2150, C0 => n1299, Y => RF_DATAIN(25));
U3562 : AOI22XL port map( A0 => WB_ALU_25_port, A1 => n1617, B0 =>
WB_DATA_EXT_16_25_port, B1 => n1211, Y => n1299);
U3563 : OAI21XL port map( A0 => WB_SIGN_EXT_16_CONTROL, A1 => n1324, B0 =>
n2110, Y => WB_DATA_EXT_16_25_port);
U3564 : OAI2B11XL port map( A1N => WB_DATA_RAM_26_port, A0 => n1207, B0 =>
n2150, C0 => n1298, Y => RF_DATAIN(26));
U3565 : AOI22XL port map( A0 => WB_ALU_26_port, A1 => n1617, B0 =>
WB_DATA_EXT_16_26_port, B1 => n1211, Y => n1298);
U3566 : OAI21XL port map( A0 => WB_SIGN_EXT_16_CONTROL, A1 => n1322, B0 =>
WB_SIGN_EXT_16_instance_n27, Y =>
WB_DATA_EXT_16_26_port);
U3567 : OAI2B11XL port map( A1N => WB_DATA_RAM_27_port, A0 => n1207, B0 =>
n2150, C0 => n1297, Y => RF_DATAIN(27));
U3568 : AOI22XL port map( A0 => WB_ALU_27_port, A1 => n1617, B0 =>
WB_DATA_EXT_16_27_port, B1 => n1211, Y => n1297);
U3569 : OAI21XL port map( A0 => WB_SIGN_EXT_16_CONTROL, A1 => n1320, B0 =>
n2110, Y => WB_DATA_EXT_16_27_port);
U3570 : OAI2B11XL port map( A1N => WB_DATA_RAM_28_port, A0 => n1207, B0 =>
n2150, C0 => n1296, Y => RF_DATAIN(28));
U3571 : AOI22XL port map( A0 => WB_ALU_28_port, A1 => n1617, B0 =>
WB_DATA_EXT_16_28_port, B1 => n1211, Y => n1296);
U3572 : OAI21XL port map( A0 => WB_SIGN_EXT_16_CONTROL, A1 => n1318, B0 =>
WB_SIGN_EXT_16_instance_n27, Y =>
WB_DATA_EXT_16_28_port);
U3573 : OAI2B11XL port map( A1N => WB_DATA_RAM_29_port, A0 => n1207, B0 =>
n2150, C0 => n1295, Y => RF_DATAIN(29));
U3574 : AOI22XL port map( A0 => WB_ALU_29_port, A1 => n1617, B0 =>
WB_DATA_EXT_16_29_port, B1 => n1211, Y => n1295);
U3575 : OAI21XL port map( A0 => WB_SIGN_EXT_16_CONTROL, A1 => n1316, B0 =>
n2110, Y => WB_DATA_EXT_16_29_port);
U3576 : OAI2B11XL port map( A1N => WB_DATA_RAM_30_port, A0 => n1207, B0 =>
n2150, C0 => n1294, Y => RF_DATAIN(30));
U3577 : AOI22XL port map( A0 => WB_ALU_30_port, A1 => n1617, B0 =>
WB_DATA_EXT_16_30_port, B1 => n1211, Y => n1294);
U3578 : OAI21XL port map( A0 => WB_SIGN_EXT_16_CONTROL, A1 => n1314, B0 =>
n2110, Y => WB_DATA_EXT_16_30_port);
U3579 : OAI2B11XL port map( A1N => WB_DATA_RAM_31_port, A0 => n1207, B0 =>
n2150, C0 => n1209, Y => RF_DATAIN(31));
U3580 : AOI22XL port map( A0 => WB_ALU_31_port, A1 => n1617, B0 =>
WB_DATA_EXT_16_31_port, B1 => n1211, Y => n1209);
U3581 : NOR2XL port map( A => n1349, B => WB_INSTR_28, Y => n1466);
U3582 : OAI2BB1XL port map( A0N => WB_INSTR_17_port, A1N => n1493, B0 =>
n1497, Y => RF_ADD_WR_1_port);
U3583 : AOI21XL port map( A0 => WB_INSTR_12_port, A1 => n1468, B0 => n1495,
Y => n1497);
U3584 : OAI2BB1XL port map( A0N => WB_INSTR_18_port, A1N => n1493, B0 =>
n1496, Y => RF_ADD_WR_2_port);
U3585 : AOI21XL port map( A0 => WB_INSTR_13_port, A1 => n1468, B0 => n1495,
Y => n1496);
U3586 : OAI2BB1XL port map( A0N => WB_INSTR_20_port, A1N => n1493, B0 =>
n1494, Y => RF_ADD_WR_4_port);
U3587 : AOI21XL port map( A0 => WB_INSTR_15_port, A1 => n1468, B0 => n1495,
Y => n1494);
U3588 : NAND3BXL port map( AN => n1498, B => n1499, C => n1500, Y => n1489);
U3589 : XNOR2XL port map( A => RF_ADD_RD2_0_port, B => RF_ADD_WR_0_port, Y
=> n1499);
U3590 : XNOR2XL port map( A => RF_ADD_RD2_3_port, B => RF_ADD_WR_3_port, Y
=> n1500);
U3591 : INVXL port map( A => WB_INSTR_28, Y => n1344);
U3592 : INVXL port map( A => n1380, Y => n1376);
U3593 : OAI33XL port map( A0 => n1381, A1 => n1382, A2 => n1383, B0 => n1373
, B1 => n1379, B2 => n1378, Y => n1380);
U3594 : XOR2XL port map( A => RF_ADD_RD2_2_port, B => EX_INSTR_13_port, Y =>
n1382);
U3595 : XOR2XL port map( A => RF_ADD_RD2_4_port, B => EX_INSTR_15_port, Y =>
n1383);
U3596 : NOR2XL port map( A => n1344, B => WB_INSTR_27, Y => n1467);
U3597 : NAND2XL port map( A => n1200, B => n1201, Y => n1191);
U3598 : NOR4XL port map( A => n1206, B => N4717, C => ID_IMM16_SHL2_12_port,
D => ID_IMM16_SHL2_2_port, Y => n1200);
U3599 : NOR4XL port map( A => n1202, B => ID_IMM16_SHL2_6_port, C =>
ID_IMM16_SHL2_8_port, D => ID_IMM16_SHL2_7_port, Y
=> n1201);
U3600 : NAND3XL port map( A => ID_IMM16_SHL2_4_port, B =>
ID_IMM16_SHL2_3_port, C => ID_IMM16_SHL2_5_port, Y
=> n1206);
U3601 : OAI2BB1XL port map( A0N => WB_INSTR_16_port, A1N => n1493, B0 =>
n1502, Y => RF_ADD_WR_0_port);
U3602 : AOI21XL port map( A0 => WB_INSTR_11_port, A1 => n1468, B0 => n1495,
Y => n1502);
U3603 : OAI2BB1XL port map( A0N => WB_INSTR_19_port, A1N => n1493, B0 =>
n1501, Y => RF_ADD_WR_3_port);
U3604 : AOI21XL port map( A0 => WB_INSTR_14_port, A1 => n1468, B0 => n1495,
Y => n1501);
U3605 : INVXL port map( A => WB_INSTR_27, Y => n1349);
U3606 : AOI21XL port map( A0 => WB_INSTR_30, A1 => WB_INSTR_27, B0 => n1471,
Y => n1470);
U3607 : NAND3XL port map( A => n1401, B => n1402, C => n1403, Y => n1360);
U3608 : NOR3XL port map( A => n1404, B => n1405, C => n1406, Y => n1403);
U3609 : XNOR2XL port map( A => EX_INSTR_16_port, B => RF_ADD_RD1_0_port, Y
=> n1401);
U3610 : XNOR2XL port map( A => EX_INSTR_18_port, B => RF_ADD_RD1_2_port, Y
=> n1402);
U3611 : NAND3XL port map( A => n1385, B => n1386, C => n1387, Y => n1373);
U3612 : XNOR2XL port map( A => EX_INSTR_14_port, B => RF_ADD_RD1_3_port, Y
=> n1385);
U3613 : XNOR2XL port map( A => EX_INSTR_15_port, B => RF_ADD_RD1_4_port, Y
=> n1386);
U3614 : XNOR2XL port map( A => EX_INSTR_13_port, B => RF_ADD_RD1_2_port, Y
=> n1387);
U3615 : NAND3XL port map( A => n1451, B => n1452, C => n1453, Y => n1441);
U3616 : XNOR2XL port map( A => MEM_INSTR_15_port, B => RF_ADD_RD1_4_port, Y
=> n1451);
U3617 : XNOR2XL port map( A => MEM_INSTR_14_port, B => RF_ADD_RD1_3_port, Y
=> n1452);
U3618 : XNOR2XL port map( A => MEM_INSTR_13_port, B => RF_ADD_RD1_2_port, Y
=> n1453);
U3619 : NAND3XL port map( A => n1476, B => n1421, C => n1477, Y => n1472);
U3620 : XNOR2XL port map( A => RF_ADD_RD1_3_port, B => RF_ADD_WR_3_port, Y
=> n1476);
U3621 : XNOR2XL port map( A => RF_ADD_RD1_0_port, B => RF_ADD_WR_0_port, Y
=> n1477);
U3622 : INVXL port map( A => WB_INSTR_31, Y => n1348);
U3623 : INVXL port map( A => WB_INSTR_26, Y => n1347);
U3624 : NAND3XL port map( A => n1388, B => n1389, C => n1390, Y => n1381);
U3625 : XNOR2XL port map( A => EX_INSTR_14_port, B => RF_ADD_RD2_3_port, Y
=> n1388);
U3626 : XNOR2XL port map( A => EX_INSTR_11_port, B => RF_ADD_RD2_0_port, Y
=> n1389);
U3627 : XNOR2XL port map( A => EX_INSTR_12_port, B => RF_ADD_RD2_1_port, Y
=> n1390);
U3628 : AND3XL port map( A => n1436, B => MEM_INSTR_27_port, C => n1220, Y
=> n1419);
U3629 : INVXL port map( A => MEM_INSTR_27_port, Y => n1219);
U3630 : OAI211XL port map( A0 => n1343, A1 => n1344, B0 => n1345, C0 =>
n1346, Y => n1342);
U3631 : AOI21XL port map( A0 => WB_INSTR_27, A1 => n1347, B0 => n1348, Y =>
n1346);
U3632 : AOI31XL port map( A0 => n1349, A1 => n1344, A2 => WB_INSTR_26, B0 =>
WB_INSTR_30, Y => n1345);
U3633 : OA21XL port map( A0 => n1457, A1 => n1458, B0 => RF_WR_port, Y =>
N4708);
U3634 : NOR4XL port map( A => n1472, B => n1473, C => n1474, D => n1475, Y
=> n1458);
U3635 : NOR4XL port map( A => n1489, B => n1490, C => n1491, D => n1492, Y
=> n1457);
U3636 : XOR2XL port map( A => RF_ADD_WR_1_port, B => RF_ADD_RD1_1_port, Y =>
n1473);
U3637 : AND3XL port map( A => n1487, B => n1488, C => n1194, Y => n1371);
U3638 : OAI21XL port map( A0 => ID_INSTR_30, A1 => n1481, B0 => ID_INSTR_27,
Y => n1487);
U3639 : XOR2XL port map( A => EX_INSTR_12_port, B => RF_ADD_RD1_1_port, Y =>
n1379);
U3640 : XOR2XL port map( A => MEM_INSTR_12_port, B => RF_ADD_RD1_1_port, Y
=> n1447);
U3641 : XOR2XL port map( A => RF_ADD_WR_2_port, B => RF_ADD_RD2_2_port, Y =>
n1491);
U3642 : XOR2XL port map( A => RF_ADD_WR_4_port, B => RF_ADD_RD2_4_port, Y =>
n1492);
U3643 : XOR2XL port map( A => RF_ADD_RD1_1_port, B => EX_INSTR_17_port, Y =>
n1405);
U3644 : AO21XL port map( A0 => WB_INSTR_26, A1 => n1467, B0 => n1466, Y =>
n1462);
U3645 : NAND3BXL port map( AN => n1190, B => n1191, C => n1192, Y => RF_RD2)
;
U3646 : AOI22XL port map( A0 => ID_INSTR_29, A1 => n1193, B0 => n1194, B1 =>
n1195, Y => n1192);
U3647 : OAI31XL port map( A0 => n1196, A1 => ID_INSTR_27, A2 => n1197, B0 =>
n1198, Y => n1193);
U3648 : INVXL port map( A => RF_ADD_RD1_0_port, Y => n1384);
U3649 : INVXL port map( A => RF_ADD_RD1_2_port, Y => n1427);
U3650 : INVXL port map( A => RF_ADD_RD1_4_port, Y => n1407);
U3651 : INVXL port map( A => RF_ADD_RD1_3_port, Y => n1408);
U3652 : XOR2XL port map( A => RF_ADD_RD2_4_port, B => MEM_INSTR_20_port, Y
=> n1437);
U3653 : OR3XL port map( A => WB_INSTR_9_port, B => WB_INSTR_8_port, C =>
WB_INSTR_7_port, Y => n1514);
U3654 : INVXL port map( A => WB_INSTR_1_port, Y => n1512);
end SYN_RTL;
| lgpl-2.1 | ea454eb19675fc111526bbf92e6ae71a | 0.505527 | 3.244289 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug017/call9.vhdl | 2 | 550 | entity call9 is
end;
use std.textio.all;
architecture behav of call9 is
procedure check_acc (l1, l2 : inout line) is
begin
assert l1 = null;
assert l2 = null;
l1 := new string'("Hello world");
assert l1 /= null;
assert l2 = null report "incorrect aliasing";
l2 := new string'("second");
assert l2 /= null;
assert l2 /= l1 report "incorrect aliasing";
end check_acc;
begin
process
variable l : line;
begin
check_acc (l, l);
report "SUCCESS" severity note;
wait;
end process;
end behav;
| gpl-2.0 | e9559ea7dc9bd8d9130bfe6b753d1d3b | 0.629091 | 3.459119 | false | false | false | false |
nickg/nvc | test/elab/issue442.vhd | 1 | 1,072 | entity SAMPLE is
generic (
MIN_NUM : integer := 0;
MAX_NUM : integer := 7
);
port (
I_PORT : in bit_vector(MIN_NUM to MAX_NUM);
O_PORT : out bit_vector(MIN_NUM to MAX_NUM)
);
end SAMPLE;
architecture SAMPLE_ARCH_1 of SAMPLE is
begin
end SAMPLE_ARCH_1;
entity ISSUE442 is
end ISSUE442;
architecture MODEL of ISSUE442 is
signal I_PORT : bit_vector(1 to 4);
signal O_PORT : bit_vector(1 to 4);
component SAMPLE
generic (
MIN_NUM : integer := 0;
MAX_NUM : integer := 7
);
port (
I_PORT : in bit_vector(MIN_NUM to MAX_NUM);
O_PORT : out bit_vector(MIN_NUM to MAX_NUM)
);
end component;
begin
DUT: SAMPLE
generic map(MIN_NUM=>1, MAX_NUM=>4)
port map(I_PORT=>I_PORT,O_PORT=>O_PORT);
end MODEL;
configuration ISSUE442_1 of ISSUE442 is
for MODEL
for DUT : SAMPLE
use entity WORK.SAMPLE(SAMPLE_ARCH_1);
end for;
end for;
end ISSUE442_1;
| gpl-3.0 | ebb818eaf485a31d9234e1e661b68d98 | 0.547575 | 3.371069 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ip/design_1_axi_bram_ctrl_0_0/synth/design_1_axi_bram_ctrl_0_0.vhd | 1 | 16,623 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_bram_ctrl_v4_0_7;
USE axi_bram_ctrl_v4_0_7.axi_bram_ctrl;
ENTITY design_1_axi_bram_ctrl_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_axi_bram_ctrl_0_0;
ARCHITECTURE design_1_axi_bram_ctrl_0_0_arch OF design_1_axi_bram_ctrl_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_bram_ctrl IS
GENERIC (
C_BRAM_INST_MODE : STRING;
C_MEMORY_DEPTH : INTEGER;
C_BRAM_ADDR_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
C_SINGLE_PORT_BRAM : INTEGER;
C_FAMILY : STRING;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
C_ECC : INTEGER;
C_ECC_TYPE : INTEGER;
C_FAULT_INJECT : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ecc_interrupt : OUT STD_LOGIC;
ecc_ue : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_ctrl_awvalid : IN STD_LOGIC;
s_axi_ctrl_awready : OUT STD_LOGIC;
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wvalid : IN STD_LOGIC;
s_axi_ctrl_wready : OUT STD_LOGIC;
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_bvalid : OUT STD_LOGIC;
s_axi_ctrl_bready : IN STD_LOGIC;
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_arvalid : IN STD_LOGIC;
s_axi_ctrl_arready : OUT STD_LOGIC;
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_rvalid : OUT STD_LOGIC;
s_axi_ctrl_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_bram_ctrl;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "axi_bram_ctrl,Vivado 2016.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_bram_ctrl_0_0_arch : ARCHITECTURE IS "design_1_axi_bram_ctrl_0_0,axi_bram_ctrl,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "design_1_axi_bram_ctrl_0_0,axi_bram_ctrl,{x_ipProduct=Vivado 2016.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_bram_ctrl,x_ipVersion=4.0,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,C_BRAM_INST_MODE=EXTERNAL,C_MEMORY_DEPTH=2048,C_BRAM_ADDR_WIDTH=11,C_S_AXI_ADDR_WIDTH=13,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ID_WIDTH=12,C_S_AXI_PROTOCOL=AXI4,C_S_AXI_SUPPORTS_NARROW_BURST=0,C_SINGLE_PORT_BRAM=1,C_FAMILY=zynq,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WIDTH=32,C_ECC=0,C_ECC_TYPE=0,C_F" &
"AULT_INJECT=0,C_ECC_ONOFF_RESET_VALUE=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : axi_bram_ctrl
GENERIC MAP (
C_BRAM_INST_MODE => "EXTERNAL",
C_MEMORY_DEPTH => 2048,
C_BRAM_ADDR_WIDTH => 11,
C_S_AXI_ADDR_WIDTH => 13,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 12,
C_S_AXI_PROTOCOL => "AXI4",
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
C_SINGLE_PORT_BRAM => 1,
C_FAMILY => "zynq",
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32,
C_ECC => 0,
C_ECC_TYPE => 0,
C_FAULT_INJECT => 0,
C_ECC_ONOFF_RESET_VALUE => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_rready => '0',
bram_rst_a => bram_rst_a,
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a,
bram_rddata_b => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END design_1_axi_bram_ctrl_0_0_arch;
| gpl-3.0 | dc34efa55f7cb23a546b2192cd59b872 | 0.67569 | 3.055699 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc438.vhd | 4 | 3,862 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc438.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00438ent IS
END c03s02b01x01p19n01i00438ent;
ARCHITECTURE c03s02b01x01p19n01i00438arch OF c03s02b01x01p19n01i00438ent IS
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C10 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
function complex_scalar(s : record_std_package) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return record_std_package is
begin
return C10;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : record_std_package;
signal S2 : record_std_package;
signal S3 : record_std_package := C10;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C10) and (S2 = C10))
report "***PASSED TEST: c03s02b01x01p19n01i00438"
severity NOTE;
assert ((S1 = C10) and (S2 = C10))
report "***FAILED TEST: c03s02b01x01p19n01i00438 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00438arch;
| gpl-2.0 | de02d0312fd5302d2fe8da018461bf57 | 0.596582 | 3.771484 | false | false | false | false |
tgingold/ghdl | testsuite/synth/synth109/ram1.vhdl | 1 | 941 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ram1 is
generic (
WIDTHB : integer := 32;
SIZEB : integer := 64;
ADDRWIDTHB : integer := 6
);
port (
clkB : in std_logic;
enB : in std_logic;
weB : in std_logic;
addrB : in std_logic_vector(ADDRWIDTHB-1 downto 0);
diB : in std_logic_vector(WIDTHB-1 downto 0);
doB : out std_logic_vector(WIDTHB-1 downto 0)
);
end ram1;
architecture behavioral of ram1 is
type ramType is array (0 to SIZEB-1) of std_logic_vector(WIDTHB-1 downto 0);
shared variable ram : ramType := (others => (others => '0'));
begin
process (clkB)
begin
if rising_edge(clkB) then
if enB = '1' then
if weB = '1' then
ram(to_integer(unsigned(addrB))) := diB;
end if;
doB <= ram(to_integer(unsigned(addrB)));
end if;
end if;
end process;
end behavioral;
| gpl-2.0 | dc9409a7c0d6d9f0850fa8310d69192e | 0.589798 | 3.267361 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug017/call6a.vhdl | 2 | 346 | entity call6a is
end;
architecture behav of call6a is
procedure check (s : string) is
begin
wait for 1 ns;
assert s (2) = 'a';
end;
begin
process
variable c : character := 'a';
begin
check ("bac");
wait for 2 ns;
check ((1 => 'e', 2 => c, 3 => 'c'));
report "SUCCESS";
wait;
end process;
end behav;
| gpl-2.0 | 8abb738e139ca45eba67b6d2699172d1 | 0.560694 | 3.203704 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_05.vhd | 4 | 2,960 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_05.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_07_05 is
end entity fg_07_05;
architecture interpreter of fg_07_05 is
subtype word is bit_vector(31 downto 0);
signal address_bus, data_bus_in : word := X"0000_0000";
signal mem_read, mem_request, mem_ready, reset : bit := '0';
begin
-- code from book
instruction_interpreter : process is
-- . . .
-- not in book
variable mem_address_reg, mem_data_reg : word;
-- end not in book
procedure read_memory is
begin
address_bus <= mem_address_reg;
mem_read <= '1';
mem_request <= '1';
wait until mem_ready = '1' or reset = '1';
if reset = '1' then
return;
end if;
mem_data_reg := data_bus_in;
mem_request <= '0';
wait until mem_ready = '0';
end procedure read_memory;
begin
-- . . . -- initialization
-- not in book
if reset = '1' then
wait until reset = '0';
end if;
-- end not in book
loop
-- . . .
read_memory;
exit when reset = '1';
-- . . .
end loop;
end process instruction_interpreter;
-- end code from book
memory : process is
begin
wait until mem_request = '1';
data_bus_in <= X"1111_1111";
mem_ready <= '1' after 10 ns;
wait until mem_request = '0';
mem_ready <= '0' after 10 ns;
end process memory;
reset <= '1' after 85 ns;
end architecture interpreter;
| gpl-2.0 | ff86ff19b7f3bdefff8d4fea14a6c299 | 0.481757 | 4.625 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/generators/memory_board.vhd | 4 | 2,490 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
library ieee; use ieee.std_logic_1164.all;
entity DRAM is
port ( a : in std_logic_vector(0 to 10);
d : inout std_logic_vector(0 to 3);
cs, we, ras, cas : in std_logic );
end entity DRAM;
architecture empty of DRAM is
begin
d <= (others => 'Z');
end architecture empty;
library ieee; use ieee.std_logic_1164.all;
entity memory_board is
end entity memory_board;
-- end not in book
architecture chip_level of memory_board is
component DRAM is
port ( a : in std_logic_vector(0 to 10);
d : inout std_logic_vector(0 to 3);
cs, we, ras, cas : in std_logic );
end component DRAM;
signal buffered_address : std_logic_vector(0 to 10);
signal DRAM_data : std_logic_vector(0 to 31);
signal bank_select : std_logic_vector(0 to 3);
signal buffered_we, buffered_ras, buffered_cas : std_logic;
-- . . . -- other declarations
begin
bank_array : for bank_index in 0 to 3 generate
begin
nibble_array : for nibble_index in 0 to 7 generate
constant data_lo : natural := nibble_index * 4;
constant data_hi : natural := nibble_index * 4 + 3;
begin
a_DRAM : component DRAM
port map ( a => buffered_address,
d => DRAM_data(data_lo to data_hi),
cs => bank_select(bank_index),
we => buffered_we,
ras => buffered_ras,
cas => buffered_cas );
end generate nibble_array;
end generate bank_array;
-- . . . -- other component instances, etc
-- not in book
buffered_address <= "01010101010";
DRAM_data <= X"01234567";
-- end not in book
end architecture chip_level;
| gpl-2.0 | 7919fa931fc32a7cc8c5ff308beadea1 | 0.648193 | 3.789954 | false | false | false | false |
tgingold/ghdl | testsuite/synth/dff01/tb_dff12.vhdl | 1 | 879 | entity tb_dff12 is
end tb_dff12;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff12 is
signal clk : std_logic;
signal rstn : std_logic;
signal din : std_logic;
signal dout : std_logic;
begin
dut: entity work.dff12
port map (
q => dout,
d => din,
clk => clk,
rstn => rstn);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rstn <= '1';
wait for 1 ns;
assert dout = '1' severity failure;
rstn <= '0';
pulse;
assert dout = '0' severity failure;
rstn <= '1';
din <= '1';
pulse;
assert dout = '1' severity failure;
din <= '0';
pulse;
assert dout = '0' severity failure;
din <= '1';
pulse;
assert dout = '1' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 21693e7e451400e5efdfd1f9a9f03147 | 0.554039 | 3.380769 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2077.vhd | 4 | 7,675 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2077.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n02i02077ent IS
END c07s02b04x00p01n02i02077ent;
ARCHITECTURE c07s02b04x00p01n02i02077arch OF c07s02b04x00p01n02i02077ent IS
BEGIN
TESTING: PROCESS
variable A : bit_vector (1 to 32);
constant AA : bit_vector (1 to 32) := x"0000ffff";
variable B : bit_vector (32 downto 1);
variable C : bit_vector (15 downto 0);
variable D, DD : bit_vector (0 to 15);
variable E : bit_vector (0 to 47);
variable F : bit_vector (47 downto 0);
alias FF : bit_vector (47 downto 0) is F;
variable Q, R : bit;
BEGIN
A := x"ffffffff";
B := x"00000000";
C := x"ffff";
D := x"0000";
E := x"ffffffffffff";
FF := x"000000000000";
Q := '1';
R := '0';
assert NOT( ( C & Q = b"11111111111111111") and
( C & R = b"11111111111111110") and
( D & Q = b"00000000000000001") and
( D & R = b"00000000000000000") and
( Q & C = b"11111111111111111") and
( R & C = b"01111111111111111") and
( Q & D = b"10000000000000000") and
( R & D = b"00000000000000000") and
( A & Q = Q & A) and
( B & R = R & B) and
( A & R = C & (C & R)) and
( R & A = (R & C) & C) and
( R & R & R & R & C = x"0ffff") and
( C & R & R & R & R = x"ffff0") and
( E & Q = Q & E) and
( F & Q = not (E & R)) and
( A & A = x"ffffffffffffffff") and
( A & B = x"ffffffff00000000") and
( A & C = x"ffffffffffff") and
( A & D = x"ffffffff0000") and
( A & E = x"ffffffffffffffffffff") and
( A & F = x"ffffffff000000000000") and
( B & A = x"00000000ffffffff") and
( B & B = x"0000000000000000") and
( B & C = x"00000000ffff") and
( B & D = x"000000000000") and
( B & E = x"00000000ffffffffffff") and
( B & F = x"00000000000000000000") and
( C & A = x"ffffffffffff") and
( C & B = x"ffff00000000") and
( C & C = x"ffffffff") and
( C & D = x"ffff0000") and
( C & E = x"ffffffffffffffff") and
( C & F = x"ffff000000000000") and
( D & A = x"0000ffffffff") and
( D & B = x"000000000000") and
( D & C = x"0000ffff") and
( D & D = x"00000000") and
( D & E = x"0000ffffffffffff") and
( D & F = x"0000000000000000") and
( E & A = x"ffffffffffffffffffff") and
( E & B = x"ffffffffffff00000000") and
( E & C = x"ffffffffffffffff") and
( E & D = x"ffffffffffff0000") and
( E & E = x"ffffffffffffffffffffffff") and
( E & F = x"ffffffffffff000000000000") and
( F & A = x"000000000000ffffffff") and
( F & B = x"00000000000000000000") and
( F & C = x"000000000000ffff") and
( F & D = x"0000000000000000") and
( F & E = x"000000000000ffffffffffff") and
( F & F = x"000000000000000000000000") )
report "***PASSED TEST: c07s02b04x00p01n02i02077"
severity NOTE;
assert ( ( C & Q = b"11111111111111111") and
( C & R = b"11111111111111110") and
( D & Q = b"00000000000000001") and
( D & R = b"00000000000000000") and
( Q & C = b"11111111111111111") and
( R & C = b"01111111111111111") and
( Q & D = b"10000000000000000") and
( R & D = b"00000000000000000") and
( A & Q = Q & A) and
( B & R = R & B) and
( A & R = C & (C & R)) and
( R & A = (R & C) & C) and
( R & R & R & R & C = x"0ffff") and
( C & R & R & R & R = x"ffff0") and
( E & Q = Q & E) and
( F & Q = not (E & R)) and
( A & A = x"ffffffffffffffff") and
( A & B = x"ffffffff00000000") and
( A & C = x"ffffffffffff") and
( A & D = x"ffffffff0000") and
( A & E = x"ffffffffffffffffffff") and
( A & F = x"ffffffff000000000000") and
( B & A = x"00000000ffffffff") and
( B & B = x"0000000000000000") and
( B & C = x"00000000ffff") and
( B & D = x"000000000000") and
( B & E = x"00000000ffffffffffff") and
( B & F = x"00000000000000000000") and
( C & A = x"ffffffffffff") and
( C & B = x"ffff00000000") and
( C & C = x"ffffffff") and
( C & D = x"ffff0000") and
( C & E = x"ffffffffffffffff") and
( C & F = x"ffff000000000000") and
( D & A = x"0000ffffffff") and
( D & B = x"000000000000") and
( D & C = x"0000ffff") and
( D & D = x"00000000") and
( D & E = x"0000ffffffffffff") and
( D & F = x"0000000000000000") and
( E & A = x"ffffffffffffffffffff") and
( E & B = x"ffffffffffff00000000") and
( E & C = x"ffffffffffffffff") and
( E & D = x"ffffffffffff0000") and
( E & E = x"ffffffffffffffffffffffff") and
( E & F = x"ffffffffffff000000000000") and
( F & A = x"000000000000ffffffff") and
( F & B = x"00000000000000000000") and
( F & C = x"000000000000ffff") and
( F & D = x"0000000000000000") and
( F & E = x"000000000000ffffffffffff") and
( F & F = x"000000000000000000000000") )
report "***FAILED TEST: c07s02b04x00p01n02i02077 - The operation of operator & test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n02i02077arch;
| gpl-2.0 | 99045b447f3c878241238bc1cfb5eed3 | 0.456156 | 3.893962 | false | false | false | false |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_reset_in/pr_region_alternate_reset_in_inst.vhd | 1 | 478 | component pr_region_alternate_reset_in is
port (
clk : in std_logic := 'X'; -- clk
in_reset : in std_logic := 'X'; -- reset
out_reset : out std_logic -- reset
);
end component pr_region_alternate_reset_in;
u0 : component pr_region_alternate_reset_in
port map (
clk => CONNECTED_TO_clk, -- clk.clk
in_reset => CONNECTED_TO_in_reset, -- in_reset.reset
out_reset => CONNECTED_TO_out_reset -- out_reset.reset
);
| mit | 5f804f008a23bef149e6c1187598e6f6 | 0.587866 | 2.914634 | false | false | false | false |
nickg/nvc | test/parse/vunit8.vhd | 1 | 7,330 | package my_logic is
type STD_ULOGIC is ( 'U', -- Uninitialized
'X', -- Forcing Unknown
'0', -- Forcing 0
'1', -- Forcing 1
'Z', -- High Impedance
'W', -- Weak Unknown
'L', -- Weak 0
'H', -- Weak 1
'-' -- Don't care
);
subtype std_logic is std_ulogic;
end package;
use work.my_logic.all;
package check_pkg is
type log_level_t is (
null_log_level,
trace,
debug,
pass,
info,
warning,
error,
failure,
custom_level1,
custom_level2,
custom_level3,
custom_level4,
custom_level5,
custom_level6,
custom_level7,
custom_level8);
constant check_result_tag : string := "<+/->";
function result (msg : string := "") return string;
type edge_t is (rising_edge, falling_edge, both_edges);
type trigger_event_t is (first_pipe, first_no_pipe, penultimate);
-----------------------------------------------------------------------------
-- check_equal
-----------------------------------------------------------------------------
procedure check_equal(
constant got : in integer;
constant expected : in integer;
constant msg : in string := check_result_tag;
constant level : in log_level_t := null_log_level;
constant path_offset : in natural := 0;
constant line_num : in natural := 0;
constant file_name : in string := "");
procedure check_equal(
variable pass : out boolean;
constant got : in integer;
constant expected : in integer;
constant msg : in string := check_result_tag;
constant level : in log_level_t := null_log_level;
constant path_offset : in natural := 0;
constant line_num : in natural := 0;
constant file_name : in string := "");
procedure check_equal(
constant got : in std_logic;
constant expected : in std_logic;
constant msg : in string := check_result_tag;
constant level : in log_level_t := null_log_level;
constant path_offset : in natural := 0;
constant line_num : in natural := 0;
constant file_name : in string := "");
procedure check_equal(
variable pass : out boolean;
constant got : in std_logic;
constant expected : in std_logic;
constant msg : in string := check_result_tag;
constant level : in log_level_t := null_log_level;
constant path_offset : in natural := 0;
constant line_num : in natural := 0;
constant file_name : in string := "");
procedure check_equal(
constant got : in std_logic;
constant expected : in boolean;
constant msg : in string := check_result_tag;
constant level : in log_level_t := null_log_level;
constant path_offset : in natural := 0;
constant line_num : in natural := 0;
constant file_name : in string := "");
procedure check_equal(
variable pass : out boolean;
constant got : in std_logic;
constant expected : in boolean;
constant msg : in string := check_result_tag;
constant level : in log_level_t := null_log_level;
constant path_offset : in natural := 0;
constant line_num : in natural := 0;
constant file_name : in string := "");
procedure check_equal(
constant got : in boolean;
constant expected : in std_logic;
constant msg : in string := check_result_tag;
constant level : in log_level_t := null_log_level;
constant path_offset : in natural := 0;
constant line_num : in natural := 0;
constant file_name : in string := "");
procedure check_equal(
variable pass : out boolean;
constant got : in boolean;
constant expected : in std_logic;
constant msg : in string := check_result_tag;
constant level : in log_level_t := null_log_level;
constant path_offset : in natural := 0;
constant line_num : in natural := 0;
constant file_name : in string := "");
procedure check_equal(
constant got : in boolean;
constant expected : in boolean;
constant msg : in string := check_result_tag;
constant level : in log_level_t := null_log_level;
constant path_offset : in natural := 0;
constant line_num : in natural := 0;
constant file_name : in string := "");
procedure check_equal(
variable pass : out boolean;
constant got : in boolean;
constant expected : in boolean;
constant msg : in string := check_result_tag;
constant level : in log_level_t := null_log_level;
constant path_offset : in natural := 0;
constant line_num : in natural := 0;
constant file_name : in string := "");
procedure check_equal(
variable pass : out boolean;
constant got : in string;
constant expected : in string;
constant msg : in string := check_result_tag;
constant level : in log_level_t := null_log_level;
constant path_offset : in natural := 0;
constant line_num : in natural := 0;
constant file_name : in string := "");
procedure check_equal(
constant got : in character;
constant expected : in character;
constant msg : in string := check_result_tag;
constant level : in log_level_t := null_log_level;
constant path_offset : in natural := 0;
constant line_num : in natural := 0;
constant file_name : in string := "");
procedure check_equal(
variable pass : out boolean;
constant got : in character;
constant expected : in character;
constant msg : in string := check_result_tag;
constant level : in log_level_t := null_log_level;
constant path_offset : in natural := 0;
constant line_num : in natural := 0;
constant file_name : in string := "");
procedure check_equal(
variable pass : out boolean;
constant got : in time;
constant expected : in time;
constant msg : in string := check_result_tag;
constant level : in log_level_t := null_log_level;
constant path_offset : in natural := 0;
constant line_num : in natural := 0;
constant file_name : in string := "");
-----------------------------------------------------------------------------
end package;
entity vunit8 is
end entity;
use work.check_pkg.all;
use work.my_logic.all;
architecture test of vunit8 is
begin
p1: process is
variable b : boolean;
begin
check_equal(true, '1', ""); -- OK
check_equal(b, '1', ""); -- OK
wait;
end process;
end architecture;
| gpl-3.0 | b7922f2006f13f99307d49d82ef56895 | 0.52292 | 4.176638 | false | false | false | false |
DE5Amigos/SylvesterTheDE2Bot | DE2Botv3Fall16Main/SONAR.vhd | 1 | 12,387 | -- SONAR.VHD (a peripheral module for SCOMP)
-- 2012.06.07
-- This sonar device is based on the summer 2001 project
-- by Clliff Cross, Matt Pinkston, Phap Dinh, and Vu Phan.
-- Interrupt functionality based on the summer 2014 project
-- by Team Twinkies
LIBRARY IEEE;
LIBRARY LPM;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE LPM.LPM_COMPONENTS.ALL;
ENTITY SONAR IS
PORT(CLOCK, -- 170 kHz
RESETN, -- active-low reset
CS, -- device select for I/O operations (should be high when I/O address is 0xA0 through 0xA7, and
-- also when an IO_CYCLE is ongoing
IO_WRITE, -- indication of OUT (vs. IN), when I/O operation occurring
ECHO : IN STD_LOGIC; -- active-high indication of echo (remains high until INIT lowered)
ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0); -- select one of eight internal registers for I/O, assuming
-- that device in fact supports usage of multiple registers between 0xA0 and 0xA7
INIT : OUT STD_LOGIC; -- initiate a ping (hold high until completion of echo/no-echo cycle)
LISTEN : OUT STD_LOGIC; -- listen (raise after INIT, allowing for blanking interval)
SONAR_NUM : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); -- select a sonar transducer for pinging
SONAR_INT : OUT STD_LOGIC; -- interrupt output
IO_DATA : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0) -- I/O data bus for host operations
);
END SONAR;
ARCHITECTURE behavior OF SONAR IS
SIGNAL INIT_INT : STD_LOGIC; -- Local (to architecture) copy of INIT
SIGNAL DISABLE_SON : STD_LOGIC; -- 1: disables all sonar activity 0: enables sonar scanning
SIGNAL SONAR_EN : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Stores 8 flags to determine whether a sonar is enabled
SIGNAL INT_EN : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Stores 8 flags to determine whether interrupts are enabled
SIGNAL DISTANCE : STD_LOGIC_VECTOR(15 DOWNTO 0); -- Used to store calculated distance at each iteration
TYPE SONAR_DATA IS ARRAY (17 DOWNTO 0) OF STD_LOGIC_VECTOR(15 DOWNTO 0); -- declare an array type
-- 17 = object_detected, 16 = alarms, 15 DOWNTO 8 = distance, 7 DOWNTO 0 = echo time
SIGNAL SONAR_RESULT : SONAR_DATA; -- and use it to store a sonar value (distance) for each sonar transducer
SIGNAL SELECTED_SONAR : STD_LOGIC_VECTOR(2 DOWNTO 0); -- At a given time, one sonar is going to be of interest
SIGNAL ECHO_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0); -- This will be used to time the echo
SIGNAL PING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0); -- This will be used to time the pinger process
SIGNAL ALARM_DIST : STD_LOGIC_VECTOR(15 DOWNTO 0); -- Stores maximum distance where alarm is triggered
-- These three constants assume a 170Khz clock, and would need to be changed if the clock changes
CONSTANT MIN_TIME : INTEGER := 25*17; -- minimum time that sonars must be off between readings.
CONSTANT MAX_DIST : STD_LOGIC_VECTOR(15 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(MIN_TIME+6300, 16); -- ignore echoes after ~5 meters
CONSTANT OFF_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(MIN_TIME, 16); -- creates the minimum cycle
CONSTANT BLANK_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(MIN_TIME + 8*17, 16); -- Ignore early false echoes
CONSTANT NO_ECHO : STD_LOGIC_VECTOR(15 DOWNTO 0) := x"7FFF"; -- use 0x7FFF (max positive number) as an indication that no echo was detected
SIGNAL IO_IN : STD_LOGIC; -- a derived signal that shows an IN is requested from this device (and it should drive IO data bus)
SIGNAL LATCH : STD_LOGIC; -- a signal that goes high when the host (SCOMP) does an IO_OUT to this device
SIGNAL PING_STARTED : STD_LOGIC; -- an indicator that a ping is in progress
SIGNAL PING_DONE : STD_LOGIC; -- an indicator that a ping has resulted in an echo, or too much time has passed for an echo
SIGNAL I : INTEGER; -- note that we CAN use actual integers. This will be used as an index below. Because it does
-- not actually need to be implemented as a "real" signal, it can be replaced with a VARIABLE
-- declaration within the PROCESS where it is used below.
BEGIN
-- Use LPM function to create bidirectional I/O data bus
IO_BUS: lpm_bustri
GENERIC MAP (
lpm_width => 16
)
PORT MAP (
data => SONAR_RESULT( CONV_INTEGER(ADDR)), -- this assumes that during an IN operation, the lowest five address bits
-- specify the value of interest. See definition of SONAR_RESULT above.
-- The upper address bits are decoded to produce the CS signal used below
enabledt => IO_IN, -- based on CS (see below)
tridata => IO_DATA
);
IO_IN <= (CS AND NOT(IO_WRITE)); -- Drive IO_DATA bus (see above) when this
-- device is selected (CS high), and
-- when it is not an OUT command.
LATCH <= CS AND IO_WRITE; -- Similarly, this produces a high (and a rising
-- edge suitable for latching), but only when an OUT command occurs
WITH SELECTED_SONAR SELECT -- SELECTED_SONAR is the internal signal with a sonar mapping that makes more logical sense.
SONAR_NUM <= "000" WHEN "001",
"001" WHEN "101",
"010" WHEN "011",
"011" WHEN "111",
"100" WHEN "000",
"101" WHEN "100",
"110" WHEN "010",
"111" WHEN "110",
"000" WHEN OTHERS;
INIT <= INIT_INT;
-- distance is the echo time minus a delay constant.
DISTANCE <= ECHO_TIME-30;
PINGER: PROCESS (CLOCK, RESETN) -- This process issues a ping after a PING_START signal and times the return
BEGIN
IF (RESETN = '0') THEN -- after reset, do NOT ping, and set all stored echo results to NO_ECHO
SONAR_RESULT( 16 ) <= x"0000"; --Least significant 8 bits used for alarm triggers
SONAR_RESULT( 17 ) <= x"0000"; --Least significant 8 bits used for objects detected
PING_TIME <= x"0000";
ECHO_TIME <= x"0000";
LISTEN <= '0';
INIT_INT <= '0';
PING_STARTED <= '0';
PING_DONE <= '0';
SELECTED_SONAR <= "000";
-- INITIALIZING SONAR timing values....
-- These next few lines of code are something new for this class. Beware of thinking of
-- this as equivalent to a series of 8 statements executed SEQUENTIALLY, with an integer "I"
-- stored somewhere. A VHDL synthesizer, such as that within Quartus, will create hardware
-- that assigns each of the 8 SONAR_RESULT values to NO_ECHO *concurrently* upon reset. In
-- other words, the FOR LOOP is a convenient shorthand notation to make 8 parallel assignments.
FOR I IN 0 to 7 LOOP
SONAR_RESULT( I ) <= NO_ECHO; -- "I" was declared as an INTEGER SIGNAL. Could have been a VARIABLE.
END LOOP;
-- However, it is worth noting that if the statement in the loop had been
-- SONAR_RESULT( I ) <= SONAR_RESULT( (I-1) MOD 8 )
-- then something else entirely would happen. First, it would be a circular buffer (like
-- a series of shift registers with the end wrapped around to the beginning). Second, it
-- would not be possible to implement it as a purely combinational logic assignment, since
-- it would infer some sort of latch (using some "current" values of SONAR_RESULT on
-- the right-hand side to define "next" values on the right-hand side).
ELSIF (RISING_EDGE(CLOCK)) THEN
IF (PING_STARTED /= '1') THEN -- a new ping should start
-- increment the sonar selection and check if it's enabled
SELECTED_SONAR <= SELECTED_SONAR+1;
IF SONAR_EN(CONV_INTEGER(SELECTED_SONAR)+1) = '1' THEN
PING_STARTED <= '1';
PING_DONE <= '0';
PING_TIME <= x"0000";
ECHO_TIME <= x"0000";
LISTEN <= '0'; -- Blank on (turn off after 1.2 ms)
END IF;
-- while not otherwise modifying SONAR_RESULT, make sure that
-- any disabled sonars return 'blank' information
FOR I IN 0 to 7 LOOP
IF (( SONAR_EN(I) = '0') AND (CONV_INTEGER(SELECTED_SONAR) /= I) ) THEN
SONAR_RESULT( 16 )( I ) <= '0';
SONAR_RESULT( 17 )( I ) <= '0';
SONAR_RESULT( I ) <= NO_ECHO;
SONAR_RESULT( I + 8 ) <= NO_ECHO;
END IF;
END LOOP;
ELSE -- Handle a ping already in progress
PING_TIME <= PING_TIME + 1; -- ... increment time counter (ALWAYS)
IF (PING_TIME >= OFF_TIME) THEN
ECHO_TIME <= ECHO_TIME + 1;
END IF;
IF ( (ECHO = '1') AND (PING_DONE = '0') ) THEN -- Save the result of a valid echo
PING_DONE <= '1';
-- Set alarm flag to 1 if within the programmed ALARM_DIST range.
IF ( (DISTANCE >= 10#0#) AND (DISTANCE <= CONV_INTEGER(ALARM_DIST)) ) THEN
SONAR_RESULT( 16 )( CONV_INTEGER('0'&SELECTED_SONAR) ) <= '1';
IF INT_EN(CONV_INTEGER(SELECTED_SONAR)) = '1' THEN
SONAR_INT <= '1';
END IF;
ELSE -- Set alarm flag to 0 otherwise
SONAR_RESULT( 16 )( CONV_INTEGER('0'&SELECTED_SONAR) ) <= '0';
END IF;
SONAR_RESULT( 17 )( CONV_INTEGER('0'&SELECTED_SONAR) ) <= '1';
SONAR_RESULT( CONV_INTEGER("00"&SELECTED_SONAR) ) <= ECHO_TIME;
SONAR_RESULT( CONV_INTEGER("00"&SELECTED_SONAR) + 8 ) <= DISTANCE;
END IF;
IF (PING_TIME = OFF_TIME) THEN -- Wait for OFF_TIME to pass before starting the ping
INIT_INT <= '1'; -- Issue a ping. This must stay high at least until the echo comes back
ELSIF (PING_TIME = BLANK_TIME) THEN -- ... turn off blanking at 1.1, going on 1.2 ms
LISTEN <= '1';
ELSIF (PING_TIME = MAX_DIST) THEN -- Stop listening at a specified distance
INIT_INT <= '0';
LISTEN <= '0';
SONAR_INT <= '0';
IF (PING_DONE = '0' ) THEN -- And if echo not found earlier, set NO_ECHO indicator
SONAR_RESULT( 16 )( CONV_INTEGER('0'&SELECTED_SONAR) ) <= '0';
SONAR_RESULT( 17 )( CONV_INTEGER('0'&SELECTED_SONAR) ) <= '0';
SONAR_RESULT( CONV_INTEGER("00"&SELECTED_SONAR)) <= NO_ECHO;
SONAR_RESULT( CONV_INTEGER("00"&SELECTED_SONAR) + 8) <= NO_ECHO;
END IF;
PING_STARTED <= '0';
END IF;
END IF;
END IF;
END PROCESS;
INPUT_HANDLER: PROCESS (RESETN, LATCH, CLOCK) -- write to address 0x12 (offset from base of 0xA0) will
-- set the enabled sonars. Writing to address offset 0x10
-- will set the alarm distance.
BEGIN
IF (RESETN = '0' ) THEN
SONAR_EN <= x"00";
ALARM_DIST <= x"0000";
INT_EN <= x"FF";
ELSE
IF (RISING_EDGE(LATCH)) THEN -- an "OUT" to this device has occurred
IF (ADDR = "10010") THEN
SONAR_EN <= IO_DATA(7 DOWNTO 0);
END IF;
IF (ADDR = "10000") THEN
ALARM_DIST <= IO_DATA;
END IF;
IF (ADDR = "10001") THEN
INT_EN <= IO_DATA(7 DOWNTO 0);
END IF;
END IF;
END IF;
END PROCESS;
END behavior;
| mit | 188382f81d79e4f00d3300a0d3e7b993 | 0.562929 | 4.052012 | false | false | false | false |
nickg/nvc | test/perf/grind.vhd | 1 | 5,747 | -- Courtesy of Brian Padalino
--
library ieee ;
use ieee.std_logic_1164.all ;
entity memory is
generic (
DEPTH : positive
) ;
port (
clock : in std_logic ;
write_addr : in natural range 0 to DEPTH-1 ;
write_data : in std_logic_vector ;
write_valid : in std_logic ;
read_addr : in natural range 0 to DEPTH-1 ;
read_data : out std_logic_vector ;
read_valid : in std_logic
) ;
end entity ;
architecture arch of memory is
type mem_t is array(natural range 0 to DEPTH-1) of std_logic_vector(write_data'range) ;
signal mem : mem_t := (others =>(others =>'0')) ;
begin
process(all)
begin
if( rising_edge(clock) ) then
if( write_valid = '1' ) then
mem(write_addr) <= write_data ;
end if ;
if( read_valid = '1' ) then
read_data <= mem(read_addr) ;
end if ;
end if ;
end process ;
end architecture ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.math_real.all ;
entity traffic_gen is
generic (
WIDTH : positive ;
DEPTH : positive ;
SEED : positive
) ;
port (
clock : in std_logic ;
write_addr : out natural range 0 to DEPTH-1 ;
write_data : out std_logic_vector(WIDTH-1 downto 0) ;
write_valid : out std_logic ;
read_addr : out natural range 0 to DEPTH-1 ;
read_valid : out std_logic
) ;
end entity ;
architecture arch of traffic_gen is
type rng_t is record
s1 : positive ;
s2 : positive ;
end record ;
procedure rand_std_logic(variable rng : inout rng_t ; signal y : out std_logic) is
variable r : real ;
begin
uniform(rng.s1, rng.s2, r) ;
y <= '1' when r > 0.5 else '0' ;
end procedure ;
procedure rand_slv(variable rng : inout rng_t ; signal y : out std_logic_vector) is
variable r : real ;
begin
for i in y'range loop
uniform(rng.s1, rng.s2, r) ;
y(i) <= '1' when r > 0.5 else '0' ;
end loop ;
end procedure ;
procedure rand_natural(variable rng : inout rng_t ; max : in positive ; signal y : out natural) is
variable r : real ;
begin
uniform(rng.s1, rng.s2, r) ;
y <= natural(real(max) * r) ;
end procedure ;
procedure randomize_write(variable rng : inout rng_t ; signal addr : out natural range 0 to DEPTH-1 ; signal data : out std_logic_vector(WIDTH-1 downto 0) ; signal valid : out std_logic ) is
begin
rand_natural(rng, DEPTH-1, addr) ;
rand_slv(rng, data) ;
rand_std_logic(rng, valid) ;
end procedure ;
procedure randomize_read(variable rng : inout rng_t ; signal addr : out natural range 0 to DEPTH-1 ; signal valid : out std_logic ) is
begin
rand_natural(rng, DEPTH-1, addr) ;
rand_std_logic(rng, valid) ;
end procedure ;
function create_rng(s1, s2 : in positive) return rng_t is
variable rv : rng_t ;
begin
rv.s1 := s1 ;
rv.s2 := s2 ;
return rv ;
end function ;
begin
process(all)
variable write_rng : rng_t := create_rng(SEED+WIDTH+DEPTH, SEED*WIDTH*DEPTH) ;
variable read_rng : rng_t := create_rng(SEED+WIDTH*DEPTH, SEED*WIDTH+DEPTH) ;
begin
if( rising_edge(clock) ) then
randomize_write(write_rng, write_addr, write_data, write_valid) ;
randomize_read(read_rng, read_addr, read_valid) ;
end if ;
end process ;
end architecture ;
library ieee ;
use ieee.std_logic_1164.all ;
entity grind is
generic (
MEMORY_WIDTH : positive := 256 ;
MEMORY_DEPTH : positive := 32768 ;
NUM_INSTANCES : positive := 128
) ;
end entity ;
architecture arch of grind is
subtype data_t is std_logic_vector(MEMORY_WIDTH-1 downto 0) ;
subtype addr_t is natural range 0 to MEMORY_DEPTH-1 ;
type datas_t is array(natural range 0 to NUM_INSTANCES-1) of data_t ;
type addrs_t is array(natural range 0 to NUM_INSTANCES-1) of addr_t ;
signal clock : std_logic := '0' ;
signal write_addrs : addrs_t ;
signal write_datas : datas_t ;
signal write_valids : std_logic_vector(0 to NUM_INSTANCES-1) ;
signal read_addrs : addrs_t ;
signal read_datas : datas_t ;
signal read_valids : std_logic_vector(0 to NUM_INSTANCES-1) ;
begin
clock <= not clock after 1 ns ;
create_memories : for i in write_addrs'range generate
U_traffic_gen : entity work.traffic_gen
generic map (
WIDTH => data_t'length,
DEPTH => MEMORY_DEPTH,
SEED => i+1
) port map (
clock => clock,
write_addr => write_addrs(i),
write_data => write_datas(i),
write_valid => write_valids(i),
read_addr => read_addrs(i),
read_valid => read_valids(i)
) ;
U_mem : entity work.memory
generic map (
DEPTH => MEMORY_DEPTH
) port map (
clock => clock,
write_addr => write_addrs(i),
write_data => write_datas(i),
write_valid => write_valids(i),
read_addr => read_addrs(i),
read_data => read_datas(i),
read_valid => read_valids(i)
) ;
end generate ;
tb : process
variable t : time := 35 us ;
begin
report "Starting testbench for " & time'image(t) ;
wait for t ;
report "Finished" ;
std.env.stop ;
end process ;
end architecture ;
| gpl-3.0 | 1f35ad702b930df77367bf8fa353ddbd | 0.553332 | 3.502133 | false | false | false | false |
nickg/nvc | test/sem/osvvm3.vhd | 1 | 1,684 | package my_logic is
type unsigned is array (natural range <>) of bit;
type signed is array (natural range <>) of bit;
function to_integer(x : unsigned) return integer;
function to_integer(x : signed) return integer;
end package;
use work.my_logic.all;
package codec_builder_pkg is
function from_byte_array (
constant byte_array : string)
return bit_vector;
constant integer_code_length : positive := 4;
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out work.my_logic.unsigned);
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out work.my_logic.signed);
end package codec_builder_pkg;
package body codec_builder_pkg is
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out integer) is
begin
result := to_integer(work.my_logic.signed(from_byte_array(code(index to index + integer_code_length - 1))));
index := index + integer_code_length;
end procedure decode;
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out work.my_logic.unsigned) is
variable result_bv : bit_vector(result'range);
begin
result := work.my_logic.unsigned(result_bv);
end;
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out work.my_logic.signed) is
variable result_bv : bit_vector(result'range);
begin
result := work.my_logic.signed(result_bv);
end;
end package body codec_builder_pkg;
| gpl-3.0 | cf576a2ea741cdff2b4189362737fbe8 | 0.673397 | 3.889145 | false | false | false | false |
tgingold/ghdl | libraries/openieee/v87/numeric_bit.vhdl | 2 | 9,907 | -- This -*- vhdl -*- file is part of GHDL.
-- IEEE 1076.3 compliant numeric bit package.
-- Copyright (C) 2015 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation; either version 2, or (at your option) any later
-- version.
--
-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with GCC; see the file COPYING2. If not see
-- <http://www.gnu.org/licenses/>.
package NUMERIC_BIT is
type UNSIGNED is array (natural range <>) of BIT;
type SIGNED is array (natural range <>) of BIT;
function TO_INTEGER (ARG : UNSIGNED) return NATURAL;
function TO_INTEGER (ARG : SIGNED) return INTEGER;
-- Convert ARG to an integer.
-- Simulation is aborted in case of overflow.
-- Issue a warning in case of non-logical value.
function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNSIGNED;
-- Convert ARG to unsigned.
-- Result index range is SIZE - 1 downto 0.
-- Issue a warning if value is truncated.
function TO_SIGNED (ARG : INTEGER; SIZE : NATURAL) return SIGNED;
-- Convert ARG to signed.
-- Result index range is SIZE - 1 downto 0.
-- Issue a warning if value is truncated.
function resize (ARG : UNSIGNED; NEW_SIZE: natural) return UNSIGNED;
function resize (ARG : SIGNED; NEW_SIZE: natural) return SIGNED;
-- Result index range is NEW_SIZE - 1 downto 0 (unless null array).
-- For SIGNED, the sign of the result is the sign of ARG.
function "=" (L, R : UNSIGNED) return BOOLEAN;
function "=" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
function "=" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
function "/=" (L, R : UNSIGNED) return BOOLEAN;
function "/=" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
function "/=" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
function "<" (L, R : UNSIGNED) return BOOLEAN;
function "<" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
function "<" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
function "<=" (L, R : UNSIGNED) return BOOLEAN;
function "<=" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
function "<=" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
function ">" (L, R : UNSIGNED) return BOOLEAN;
function ">" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
function ">" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
function ">=" (L, R : UNSIGNED) return BOOLEAN;
function ">=" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
function ">=" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
function "=" (L, R : SIGNED) return BOOLEAN;
function "=" (L : SIGNED; R : INTEGER) return BOOLEAN;
function "=" (L : INTEGER; R : SIGNED) return BOOLEAN;
function "/=" (L, R : SIGNED) return BOOLEAN;
function "/=" (L : SIGNED; R : INTEGER) return BOOLEAN;
function "/=" (L : INTEGER; R : SIGNED) return BOOLEAN;
function "<" (L, R : SIGNED) return BOOLEAN;
function "<" (L : SIGNED; R : INTEGER) return BOOLEAN;
function "<" (L : INTEGER; R : SIGNED) return BOOLEAN;
function "<=" (L, R : SIGNED) return BOOLEAN;
function "<=" (L : SIGNED; R : INTEGER) return BOOLEAN;
function "<=" (L : INTEGER; R : SIGNED) return BOOLEAN;
function ">" (L, R : SIGNED) return BOOLEAN;
function ">" (L : SIGNED; R : INTEGER) return BOOLEAN;
function ">" (L : INTEGER; R : SIGNED) return BOOLEAN;
function ">=" (L, R : SIGNED) return BOOLEAN;
function ">=" (L : SIGNED; R : INTEGER) return BOOLEAN;
function ">=" (L : INTEGER; R : SIGNED) return BOOLEAN;
-- Issue a warning in case of non-logical value.
function "-" (ARG : SIGNED) return SIGNED;
-- Compute -ARG.
-- Result index range is Arg'length - 1 downto 0.
function "abs" (ARG : SIGNED) return SIGNED;
-- Compute abs ARG.
-- Result index range is Arg'length - 1 downto 0.
function "+" (L, R : UNSIGNED) return UNSIGNED;
function "+" (L, R : SIGNED) return SIGNED;
function "-" (L, R : UNSIGNED) return UNSIGNED;
function "-" (L, R : SIGNED) return SIGNED;
-- Compute L +/- R.
-- Result index range is max (L'Length, R'Length) - 1 downto 0.
-- Issue a warning in case of non-logical value.
function "+" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
function "+" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
function "+" (L : SIGNED; R : INTEGER) return SIGNED;
function "+" (L : INTEGER; R : SIGNED) return SIGNED;
function "-" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
function "-" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
function "-" (L : SIGNED; R : INTEGER) return SIGNED;
function "-" (L : INTEGER; R : SIGNED) return SIGNED;
-- Compute L +/- R.
-- Result index range is V'Length - 1 downto 0, where V is the vector
-- parameter.
-- Issue a warning in case of non-logical value.
-- Issue a warning if value is truncated.
function "*" (L, R : UNSIGNED) return UNSIGNED;
function "*" (L, R : SIGNED) return SIGNED;
-- Compute L * R
-- Result index range is L'Length + R'Length - 1 downto 0.
function "*" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
function "*" (L : SIGNED; R : INTEGER) return SIGNED;
-- Compute L * R
-- R is converted to a vector of length L'length
function "*" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
function "*" (L : INTEGER; R : SIGNED) return SIGNED;
-- Compute L * R
-- L is converted to a vector of length R'length
function "/" (L, R : UNSIGNED) return UNSIGNED;
function "/" (L, R : SIGNED) return SIGNED;
function "rem" (L, R : UNSIGNED) return UNSIGNED;
function "rem" (L, R : SIGNED) return SIGNED;
function "mod" (L, R : UNSIGNED) return UNSIGNED;
function "mod" (L, R : SIGNED) return SIGNED;
-- Compute L op R
-- Result index range is L'Length - 1 downto 0.
-- Issue a warning in case of non-logical value.
-- Issue an error if R is 0.
function "/" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
function "/" (L : SIGNED; R : INTEGER) return SIGNED;
function "rem" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
function "rem" (L : SIGNED; R : INTEGER) return SIGNED;
function "mod" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
function "mod" (L : SIGNED; R : INTEGER) return SIGNED;
-- Compute L op R.
-- Result index range is L'Length - 1 downto 0.
-- Issue a warning in case of non-logical value.
-- Issue an error if R is 0.
function "/" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
function "/" (L : INTEGER; R : SIGNED) return SIGNED;
function "rem" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
function "rem" (L : INTEGER; R : SIGNED) return SIGNED;
function "mod" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
function "mod" (L : INTEGER; R : SIGNED) return SIGNED;
-- Compute L op R.
-- Result index range is R'Length - 1 downto 0.
-- Issue a warning in case of non-logical value.
-- Issue an error if R is 0.
-- Result may be truncated.
function "not" (l : UNSIGNED) return UNSIGNED;
function "not" (l : SIGNED) return SIGNED;
function "and" (l, r : UNSIGNED) return UNSIGNED;
function "and" (l, r : SIGNED) return SIGNED;
function "nand" (l, r : UNSIGNED) return UNSIGNED;
function "nand" (l, r : SIGNED) return SIGNED;
function "or" (l, r : UNSIGNED) return UNSIGNED;
function "or" (l, r : SIGNED) return SIGNED;
function "nor" (l, r : UNSIGNED) return UNSIGNED;
function "nor" (l, r : SIGNED) return SIGNED;
function "xor" (l, r : UNSIGNED) return UNSIGNED;
function "xor" (l, r : SIGNED) return SIGNED;
--function "xnor" (l, r : UNSIGNED) return UNSIGNED;
--function "xnor" (l, r : SIGNED) return SIGNED;
-- Compute L OP R.
-- Result index range is L'Length - 1 downto 0.
-- No specific handling of null array: the index range of the result
-- would be -1 downto 0 (without warning). This it not what is specified
-- in 1076.3, but corresponds to the standard implementation.
-- No specific handling of non-logical values. Behaviour is compatible
-- with std_logic_1164.
function shift_left (ARG : UNSIGNED; COUNT: NATURAL) return UNSIGNED;
function shift_left (ARG : SIGNED; COUNT: NATURAL) return SIGNED;
function shift_right (ARG : UNSIGNED; COUNT: NATURAL) return UNSIGNED;
function shift_right (ARG : SIGNED; COUNT: NATURAL) return SIGNED;
-- Result index range is ARG'Length - 1 downto 0.
function rotate_left (ARG : UNSIGNED; COUNT: NATURAL) return UNSIGNED;
function rotate_left (ARG : SIGNED; COUNT: NATURAL) return SIGNED;
function rotate_right (ARG : UNSIGNED; COUNT: NATURAL) return UNSIGNED;
function rotate_right (ARG : SIGNED; COUNT: NATURAL) return SIGNED;
-- Result index range is ARG'Length - 1 downto 0.
--function "sll" (ARG : UNSIGNED; COUNT: INTEGER) return UNSIGNED;
--function "sll" (ARG : SIGNED; COUNT: INTEGER) return SIGNED;
--function "srl" (ARG : UNSIGNED; COUNT: INTEGER) return UNSIGNED;
--function "srl" (ARG : SIGNED; COUNT: INTEGER) return SIGNED;
-- Result index range is ARG'Length - 1 downto 0.
--function "rol" (ARG : UNSIGNED; COUNT: INTEGER) return UNSIGNED;
--function "rol" (ARG : SIGNED; COUNT: INTEGER) return SIGNED;
--function "ror" (ARG : UNSIGNED; COUNT: INTEGER) return UNSIGNED;
--function "ror" (ARG : SIGNED; COUNT: INTEGER) return SIGNED;
-- Result index range is ARG'Length - 1 downto 0.
function rising_edge (signal s : bit) return boolean;
function falling_edge (signal s : bit) return boolean;
end NUMERIC_BIT;
| gpl-2.0 | 50c3c109ddc3b1c3bda91f55dfed0b0e | 0.648329 | 3.615693 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_mm2s_basic_wrap.vhd | 3 | 44,277 | -------------------------------------------------------------------------------
-- axi_datamover_mm2s_basic_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_mm2s_basic_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Basic Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_datamover Library Modules
library axi_datamover_v5_1_10;
use axi_datamover_v5_1_10.axi_datamover_reset;
use axi_datamover_v5_1_10.axi_datamover_cmd_status;
use axi_datamover_v5_1_10.axi_datamover_scc;
use axi_datamover_v5_1_10.axi_datamover_addr_cntl;
use axi_datamover_v5_1_10.axi_datamover_rddata_cntl;
use axi_datamover_v5_1_10.axi_datamover_rd_status_cntl;
use axi_datamover_v5_1_10.axi_datamover_skid_buf;
-------------------------------------------------------------------------------
entity axi_datamover_mm2s_basic_wrap is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_MM2S_ARID : Integer range 0 to 255 := 8;
-- Specifies the constant value to output on
-- the ARID output port
C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_MM2S_MDATA_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_MM2S_SDATA_WIDTH : Integer range 8 to 64 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 2 to 64 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1;
C_ENABLE_SKID_BUF : string := "11111";
C_MICRO_DMA : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock and Reset inputs -----------------------
mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- MM2S Halt request input control ---------------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- Error discrete output -------------------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional MM2S Command and Status Clock and Reset ----------
-- These are used when C_MM2S_STSCMD_IS_ASYNC = 1 --
mm2s_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
mm2s_cmd_wvalid : in std_logic; --
mm2s_cmd_wready : out std_logic; --
mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_MM2S_ADDR_WIDTH+36)-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------
mm2s_sts_wvalid : out std_logic; --
mm2s_sts_wready : in std_logic; --
mm2s_sts_wdata : out std_logic_vector(7 downto 0); --
mm2s_sts_wstrb : out std_logic_vector(0 downto 0); --
mm2s_sts_wlast : out std_logic; --
-------------------------------------------------------------
-- Address Posting contols ----------------------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
-------------------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------
mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------
mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); --
mm2s_rresp : In std_logic_vector(1 downto 0); --
mm2s_rlast : In std_logic; --
mm2s_rvalid : In std_logic; --
mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -----------------------------------------------
mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); --
mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); --
mm2s_strm_wlast : Out std_logic; --
mm2s_strm_wvalid : Out std_logic; --
mm2s_strm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) --
-------------------------------------------------------------------
);
end entity axi_datamover_mm2s_basic_wrap;
architecture implementation of axi_datamover_mm2s_basic_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_rdmux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Read data mux select control.
--
-------------------------------------------------------------------
function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
end case;
Return (num_addr_bits_needed);
end function func_calc_rdmux_sel_bits;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant INCLUDE_MM2S : integer range 0 to 2 := 2;
Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID;
Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH;
Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH;
Constant MM2S_MDATA_WIDTH : integer range 32 to 256 := C_MM2S_MDATA_WIDTH;
Constant MM2S_SDATA_WIDTH : integer range 8 to 256 := C_MM2S_SDATA_WIDTH;
Constant MM2S_CMD_WIDTH : integer := (C_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32);
Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S
Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := 1;
Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 64 := C_MM2S_STSCMD_FIFO_DEPTH;
Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := C_MM2S_STSCMD_IS_ASYNC;
Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := 2;
Constant MM2S_BURST_SIZE : integer range 16 to 256 := 16;
Constant RD_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant SEL_ADDR_WIDTH : integer := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH);
Constant DRE_ALIGN_ZEROS : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
-- obsoleted Constant DISABLE_WAIT_FOR_DATA : integer := 0;
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0);
signal sig_mm2s_cache_data : std_logic_vector(7 downto 0);
signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_cmplt : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2rsc_calc_error : std_logic := '0';
signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2rsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2rsc_calc_err : std_logic := '0';
signal sig_data2rsc_okay : std_logic := '0';
signal sig_data2rsc_decerr : std_logic := '0';
signal sig_data2rsc_slverr : std_logic := '0';
signal sig_data2rsc_cmd_cmplt : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_data2rsc_valid : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_data2skid_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2rsc_status_ready : std_logic := '0';
signal sig_rsc2stat_status_valid : std_logic := '0';
signal sig_rsc2mstr_halt_pipe : std_logic := '0';
signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_cache2mstr_command : std_logic_vector (7 downto 0);
signal mm2s_arcache_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug Support ------------------------------------------
mm2s_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the mm2s_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (mm2s_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"BEEF2222" ; -- 32 bit Constant indicating MM2S Basic type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2rsc_status_ready;
sig_dbg_data_1(7) <= sig_rsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error
sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake
-- Spare bits in debug1
sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits
GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters
mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters
sig_mm2s_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; --sg_ctl (3 downto 0); -- SG Cache from register
mm2s_aruser <= "0000";--sg_ctl (7 downto 4); -- Per Interface-X guidelines for Masters
-- sig_mm2s_cache_data <= mm2s_cmd_wdata(103 downto 96);
sig_mm2s_cache_data <= mm2s_cmd_wdata(79+(C_MM2S_ADDR_WIDTH-32) downto 72+(C_MM2S_ADDR_WIDTH-32));
end generate GEN_CACHE2;
-- Cache signal tie-off
-- Internal error output discrete ------------------------------
mm2s_err <= sig_calc2dm_calc_err;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_datamover_v5_1_10.axi_datamover_reset
generic map (
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC
)
port map (
primary_aclk => mm2s_aclk ,
primary_aresetn => mm2s_aresetn ,
secondary_awclk => mm2s_cmdsts_awclk ,
secondary_aresetn => mm2s_cmdsts_aresetn ,
halt_req => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => LOGIC_HIGH ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_datamover_v5_1_10.axi_datamover_cmd_status
generic map (
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO ,
C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
secondary_awclk => mm2s_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => mm2s_cmd_wvalid ,
cmd_wready => mm2s_cmd_wready ,
cmd_wdata => sig_mm2s_cmd_wdata ,
cache_data => sig_mm2s_cache_data ,
sts_wvalid => mm2s_sts_wvalid ,
sts_wready => mm2s_sts_wready ,
sts_wdata => mm2s_sts_wdata ,
sts_wstrb => mm2s_sts_wstrb ,
sts_wlast => mm2s_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_rsc2stat_status ,
stat2mstr_status_ready => sig_stat2rsc_status_ready ,
mst2stst_status_valid => sig_rsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Read Status Controller Block
--
------------------------------------------------------------
I_RD_STATUS_CNTLR : entity axi_datamover_v5_1_10.axi_datamover_rd_status_cntl
generic map (
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
calc2rsc_calc_error => sig_calc2dm_calc_err ,
addr2rsc_calc_error => sig_addr2rsc_calc_error ,
addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty ,
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_error => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2stat_status => sig_rsc2stat_status ,
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_SCC
--
-- Description:
-- Simple Command Calculator Block
--
------------------------------------------------------------
I_MSTR_SCC : entity axi_datamover_v5_1_10.axi_datamover_scc
generic map (
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_MAX_BURST_LEN => C_MM2S_BURST_SIZE ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
-- Clock input
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_sof => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_datamover_v5_1_10.axi_datamover_addr_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => DISABLE_WAIT_FOR_DATA ,
--C_ADDR_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_ADDR_FIFO_DEPTH => RD_ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_ADDR_ID => MM2S_ARID_VALUE ,
C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => mm2s_arid ,
addr2axi_aaddr => mm2s_araddr ,
addr2axi_alen => mm2s_arlen ,
addr2axi_asize => mm2s_arsize ,
addr2axi_aburst => mm2s_arburst ,
addr2axi_aprot => mm2s_arprot ,
addr2axi_avalid => mm2s_arvalid ,
addr2axi_acache => open ,
addr2axi_auser => open ,
axi2addr_aready => mm2s_arready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => mm2s_allow_addr_req ,
addr_req_posted => mm2s_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => LOGIC_LOW ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2rsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_RD_DATA_CNTL
--
-- Description:
-- Read Data Controller Block
--
------------------------------------------------------------
I_RD_DATA_CNTL : entity axi_datamover_v5_1_10.axi_datamover_rddata_cntl
generic map (
C_INCLUDE_DRE => INCLUDE_MM2S_DRE ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset -----------------------------------
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
-- Soft Shutdown Interface -----------------------------
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
-- External Address Pipelining Contol support
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
-- AXI Read Data Channel I/O -------------------------------
mm2s_rdata => mm2s_rdata ,
mm2s_rresp => mm2s_rresp ,
mm2s_rlast => mm2s_rlast ,
mm2s_rvalid => mm2s_rvalid ,
mm2s_rready => mm2s_rready ,
-- MM2S DRE Control -----------------------------------
mm2s_dre_new_align => open ,
mm2s_dre_use_autodest => open ,
mm2s_dre_src_align => open ,
mm2s_dre_dest_align => open ,
mm2s_dre_flush => open ,
-- AXI Master Stream -----------------------------------
mm2s_strm_wvalid => sig_data2skid_wvalid ,
mm2s_strm_wready => sig_data2skid_wready ,
mm2s_strm_wdata => sig_data2skid_wdata ,
mm2s_strm_wstrb => sig_data2skid_wstrb ,
mm2s_strm_wlast => sig_data2skid_wlast ,
-- MM2S Store and Forward Supplimental Control -----------
mm2s_data2sf_cmd_cmplt => open ,
-- Command Calculator Interface --------------------------
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => LOGIC_LOW ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => DRE_ALIGN_ZEROS ,
mstr2data_dre_dest_align => DRE_ALIGN_ZEROS ,
-- Address Controller Interface --------------------------
addr2data_addr_posted => sig_addr2data_addr_posted ,
-- Data Controller Halted Status
data2all_dcntlr_halted => sig_data2all_dcntlr_halted,
-- Output Stream Skid Buffer Halt control
data2skid_halt => sig_data2skid_halt ,
-- Read Status Controller Interface --------------------------
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_err => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_SKID_BUF
--
-- Description:
-- Instance for the MM2S Skid Buffer which provides for
-- registerd Master Stream outputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
I_MM2S_SKID_BUF : entity axi_datamover_v5_1_10.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => MM2S_SDATA_WIDTH
)
port map (
-- System Ports
aclk => mm2s_aclk ,
arst => sig_stream_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_data2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => sig_data2skid_wvalid ,
s_ready => sig_data2skid_wready ,
s_data => sig_data2skid_wdata ,
s_strb => sig_data2skid_wstrb ,
s_last => sig_data2skid_wlast ,
-- Master Side (Stream Data Output
m_valid => mm2s_strm_wvalid ,
m_ready => mm2s_strm_wready ,
m_data => mm2s_strm_wdata ,
m_strb => mm2s_strm_wstrb ,
m_last => mm2s_strm_wlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '0' generate
begin
mm2s_strm_wvalid <= sig_data2skid_wvalid;
sig_data2skid_wready <= mm2s_strm_wready;
mm2s_strm_wdata <= sig_data2skid_wdata;
mm2s_strm_wstrb <= sig_data2skid_wstrb;
mm2s_strm_wlast <= sig_data2skid_wlast;
end generate DISABLE_AXIS_SKID;
end implementation;
| gpl-3.0 | 4ed185b6194fd88e6e91adaaf6e3d4ad | 0.448992 | 4.138424 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu_types-1.vhd | 4 | 1,674 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package cpu_types is
constant word_size : positive := 16;
constant address_size : positive := 24;
subtype word is bit_vector(word_size - 1 downto 0);
subtype address is bit_vector(address_size - 1 downto 0);
type status_value is ( halted, idle, fetch, mem_read, mem_write,
io_read, io_write, int_ack );
subtype opcode is bit_vector(5 downto 0);
function extract_opcode ( instr_word : word ) return opcode;
constant op_nop : opcode := "000000";
constant op_breq : opcode := "000001";
constant op_brne : opcode := "000010";
constant op_add : opcode := "000011";
-- . . .
end package cpu_types;
-- not in book
package body cpu_types is
function extract_opcode ( instr_word : word ) return opcode is
begin
return work.cpu_types.op_nop;
end function extract_opcode;
end package body cpu_types;
-- end not in book
| gpl-2.0 | 4abe14929c0daefeecc2c605574804ac | 0.700717 | 3.893023 | false | false | false | false |
tgingold/ghdl | testsuite/synth/asgn01/tb_asgn04.vhdl | 1 | 696 | entity tb_asgn04 is
end tb_asgn04;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_asgn04 is
signal s0 : std_logic;
signal s1 : std_logic;
signal r : std_logic_vector (2 downto 0);
begin
dut: entity work.asgn04
port map (s0 => s0, s1 => s1, r => r);
process
begin
s0 <= '0';
s1 <= '0';
wait for 1 ns;
assert r = "000" severity failure;
s0 <= '0';
s1 <= '1';
wait for 1 ns;
assert r = "000" severity failure;
s0 <= '1';
s1 <= '0';
wait for 1 ns;
assert r = "010" severity failure;
s0 <= '1';
s1 <= '1';
wait for 1 ns;
assert r = "001" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | b479cc8eae984f4da1dbfe3ba8fa6865 | 0.558908 | 2.912134 | false | false | false | false |
nickg/nvc | test/regress/ieee2.vhd | 1 | 1,079 | library ieee;
use ieee.std_logic_1164.all;
entity sub is
port (
clk : out std_logic;
cnt : inout integer := 0);
end entity;
architecture test of sub is
signal clk_i : bit := '0';
signal clk_std : std_logic;
begin
clk_i <= not clk_i after 1 ns;
clk_std <= to_stdulogic(clk_i);
clk <= clk_std;
process (clk_std) is
begin
if rising_edge(clk_std) then
cnt <= cnt + 1;
end if;
end process;
end architecture;
-------------------------------------------------------------------------------
entity ieee2 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of ieee2 is
signal cnt : integer := 0;
signal clk : std_logic;
begin
sub_i: entity work.sub port map ( clk, cnt );
process (clk) is
begin
if rising_edge(clk) then
report "clock!";
end if;
end process;
process is
begin
wait for 10 ns;
report integer'image(cnt);
assert cnt = 5;
wait;
end process;
end architecture;
| gpl-3.0 | d1b30b6b7f64bb6b4d1dd215ab280737 | 0.531047 | 3.746528 | false | false | false | false |
tgingold/ghdl | testsuite/gna/ticket14/reprook.vhdl | 3 | 564 | entity reprook is
generic (
BUS_WIDTH : integer := 8;
ARRAY_WIDTH : integer := 2);
end entity reprook;
architecture behavioural of reprook is
type test_array_btype is array (integer range <>) of
bit_vector (BUS_WIDTH-1 downto 0);
subtype test_array_type is test_array_btype (ARRAY_WIDTH-1 downto 0);
signal s : test_array_type := (others => (others => '0'));
begin
failing_process : process
begin
assert s'left = 1;
assert s'right = 0;
wait;
end process failing_process;
end architecture behavioural;
| gpl-2.0 | 2ce10ac34984fefa0de065e3f17bad69 | 0.650709 | 3.63871 | false | true | false | false |
nickg/nvc | test/elab/ename1.vhd | 1 | 930 | entity bot is
end entity;
architecture test of bot is
signal x, y : natural;
begin
p1: process is
begin
wait for 5 ns;
x <= 5;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity ename1 is
end entity;
architecture test of ename1 is
begin
uut: entity work.bot;
p2: process is
begin
assert <<signal uut.x : integer>> = 0; -- OK
assert <<variable uut.x : integer>> = 0; -- Error
assert <<signal bot.x : integer>> = 0; -- Error
assert <<signal .ename1.uut.x : integer>> = 0; -- OK
assert <<signal .ename1.uut.x : bit>> = '0'; -- Error
assert <<signal ^.x : bit>> = '0'; -- Error
assert <<signal uut(1).x : integer>> = 0; -- Error
assert <<signal ^.^.^.^.x : bit>> = '0'; -- Error
wait;
end process;
end architecture;
| gpl-3.0 | 6a4580561edc8e686a1b0988cdbf70c3 | 0.492473 | 3.661417 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1177.vhd | 4 | 1,761 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1177.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s00b00x00p01n02i01177ent IS
END c08s00b00x00p01n02i01177ent;
ARCHITECTURE c08s00b00x00p01n02i01177arch OF c08s00b00x00p01n02i01177ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
if FALSE = FALSE then
end if;
k := 5;
assert NOT(k=5)
report "***PASSED TEST: c08s00b00x00p01n02i01177"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c08s00b00x00p01n02i01177 - Empty sequence of statement is permitted in 'if statement'."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s00b00x00p01n02i01177arch;
| gpl-2.0 | b38aa4a389f515c2178417caee078e60 | 0.666667 | 3.661123 | false | true | false | false |
tgingold/ghdl | testsuite/gna/issue228/tb.vhdl | 2 | 1,124 | library ieee;
use ieee.std_logic_1164.all;
entity foo is
port (
clk : in std_ulogic;
a0 : in std_ulogic
);
end entity;
architecture bar of foo is
begin
-- psl default clock is rising_edge(clk);
-- psl sequence rising_a0 is {not(a0); a0};
-- psl sequence falling_a0 is {a0; not(a0)};
-- psl cover {rising_a0};
-- psl cover {falling_a0} report "falling_a0 custom report";
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity foo_tb is
end entity;
architecture tb of foo_tb is
signal clk : std_ulogic := '0';
signal a0 : std_ulogic;
begin
clk_gen:
process
begin
for i in 0 to 10 loop
clk <= not(clk);
wait for 10 ns;
end loop;
wait;
end process;
test_driver:
process
begin
a0 <= '1';
wait until rising_edge(clk);
a0 <= '0';
wait until rising_edge(clk);
a0 <= '1';
wait until rising_edge(clk);
wait until rising_edge(clk);
wait;
end process;
dut:
entity work.foo(bar)
port map (
clk => clk,
a0 => a0);
end architecture;
| gpl-2.0 | e7315d001889939befc3e1c7108b63fb | 0.596085 | 3.193182 | false | false | false | false |
nickg/nvc | test/regress/vests18.vhd | 1 | 3,664 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc743.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p04n01i00743pkg is
type arrtype is array (1 to 5) of bit;
constant defcon1 : bit;
constant defcon2 : integer;
constant defcon3 : arrtype;
constant defcon4 : boolean;
component comp1
generic (
constant dgc1 : bit := defcon1;
constant dgc2 : integer := defcon2;
constant dgc3 : arrtype := defcon3;
constant dgc4 : boolean := defcon4
);
port ( signal dcent1 : inout bit := dgc1;
signal dcent2 : inout integer := dgc2;
signal dcent3 : inout arrtype := dgc3;
signal dcent4 : inout boolean := dgc4
);
end component;
end c01s01b01x01p04n01i00743pkg;
package body c01s01b01x01p04n01i00743pkg is
constant defcon1 : bit := '1';
constant defcon2 : integer := 113;
constant defcon3 : arrtype := ('1','0','1','0','1');
constant defcon4 : boolean := TRUE;
end c01s01b01x01p04n01i00743pkg;
use work.c01s01b01x01p04n01i00743pkg.all;
entity c01s01b01x01p04n01i00743ent_a is
generic (
constant gc1 : bit;
constant gc2 : integer;
constant gc3 : arrtype;
constant gc4 : boolean
);
port ( signal cent1 : inout bit;
signal cent2 : inout integer;
signal cent3 : inout arrtype;
signal cent4 : inout boolean
);
end c01s01b01x01p04n01i00743ent_a;
architecture c01s01b01x01p04n01i00743arch_a of c01s01b01x01p04n01i00743ent_a is
begin
p0: process
begin
wait for 1 ns;
if (gc1='1') and (gc2=113) and (gc3=('1','0','1','0','1')) and (gc4) then
assert FALSE
report "***PASSED TEST: c01s01b01x01p04n01i00743"
severity NOTE;
else
assert FALSE
report "***FAILED TEST: c01s01b01x01p04n01i00743 - Generic default to deferred constants."
severity ERROR;
end if;
wait;
end process;
end c01s01b01x01p04n01i00743arch_a;
use work.c01s01b01x01p04n01i00743pkg.all;
ENTITY vests18 IS
generic ( constant gen_con : integer := 1334 );
port ( signal ee1 : inout boolean := TRUE;
signal ee2 : inout bit;
signal ee3 : inout integer;
signal ee4 : inout arrtype
);
END vests18;
ARCHITECTURE c01s01b01x01p04n01i00743arch OF vests18 IS
for u1 : comp1 use
entity work.c01s01b01x01p04n01i00743ent_a(c01s01b01x01p04n01i00743arch_a)
generic map ( dgc1, dgc2, dgc3, dgc4 )
port map ( dcent1, dcent2, dcent3, dcent4 );
BEGIN
u1 : comp1;
END c01s01b01x01p04n01i00743arch;
| gpl-3.0 | 66fcd030fc6eb5fe2359beea91929e68 | 0.648199 | 3.450094 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue317/PoC/src/sim/sim_waveform.vhdl | 2 | 34,756 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Patrick Lehmann
-- Martin Zabel
--
-- Package: Simulation constants, functions and utilities.
--
-- Description:
-- -------------------------------------
-- .. TODO:: No documentation available.
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair of VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
library PoC;
use PoC.utils.all;
-- use PoC.strings.all;
use PoC.vectors.all;
use PoC.physical.all;
use PoC.sim_types.all;
-- use PoC.sim_random.all;
use PoC.simulation.all;
package waveform is
-- clock generation
-- ===========================================================================
procedure simGenerateClock(
signal Clock : out std_logic;
constant Frequency : in FREQ;
constant Phase : in T_PHASE := 0 deg;
constant DutyCycle : in T_DUTYCYCLE := 50 percent;
constant Wander : in T_WANDER := 0 permil
);
procedure simGenerateClock(
constant TestID : in T_SIM_TEST_ID;
signal Clock : out std_logic;
constant Frequency : in FREQ;
constant Phase : in T_PHASE := 0 deg;
constant DutyCycle : in T_DUTYCYCLE := 50 percent;
constant Wander : in T_WANDER := 0 permil
);
procedure simGenerateClock(
signal Clock : out std_logic;
constant Period : in time;
constant Phase : in T_PHASE := 0 deg;
constant DutyCycle : in T_DUTYCYCLE := 50 percent;
constant Wander : in T_WANDER := 0 permil
);
procedure simGenerateClock(
constant TestID : in T_SIM_TEST_ID;
signal Clock : out std_logic;
constant Period : in time;
constant Phase : in T_PHASE := 0 deg;
constant DutyCycle : in T_DUTYCYCLE := 50 percent;
constant Wander : in T_WANDER := 0 permil
);
procedure simWaitUntilRisingEdge(signal Clock : in std_logic; constant Times : in positive);
procedure simWaitUntilRisingEdge(constant TestID : in T_SIM_TEST_ID; signal Clock : in std_logic; constant Times : in positive);
procedure simWaitUntilFallingEdge(signal Clock : in std_logic; constant Times : in positive);
procedure simWaitUntilFallingEdge(constant TestID : in T_SIM_TEST_ID; signal Clock : in std_logic; constant Times : in positive);
procedure simGenerateClock2(constant TestID : in T_SIM_TEST_ID; signal Clock : out std_logic; signal Debug : out REAL; constant Period : in time);
-- waveform description
-- ===========================================================================
type T_SIM_WAVEFORM_TUPLE_SL is record
Delay : time;
Value : std_logic;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_8 is record
Delay : time;
Value : T_SLV_8;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_16 is record
Delay : time;
Value : T_SLV_16;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_24 is record
Delay : time;
Value : T_SLV_24;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_32 is record
Delay : time;
Value : T_SLV_32;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_48 is record
Delay : time;
Value : T_SLV_48;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_64 is record
Delay : time;
Value : T_SLV_64;
end record;
subtype T_SIM_WAVEFORM is TIME_VECTOR; -- use predefined physical type TIME here
type T_SIM_WAVEFORM_SL is array(natural range <>) of T_SIM_WAVEFORM_TUPLE_SL;
type T_SIM_WAVEFORM_SLV_8 is array(natural range <>) of T_SIM_WAVEFORM_TUPLE_SLV_8;
type T_SIM_WAVEFORM_SLV_16 is array(natural range <>) of T_SIM_WAVEFORM_TUPLE_SLV_16;
type T_SIM_WAVEFORM_SLV_24 is array(natural range <>) of T_SIM_WAVEFORM_TUPLE_SLV_24;
type T_SIM_WAVEFORM_SLV_32 is array(natural range <>) of T_SIM_WAVEFORM_TUPLE_SLV_32;
type T_SIM_WAVEFORM_SLV_48 is array(natural range <>) of T_SIM_WAVEFORM_TUPLE_SLV_48;
type T_SIM_WAVEFORM_SLV_64 is array(natural range <>) of T_SIM_WAVEFORM_TUPLE_SLV_64;
-- waveform generation procedures
-- ===========================================================================
-- TODO: get initial value from Waveform(0) if .Delay = o fs, otherwise use (others => 'U') ?
procedure simGenerateWaveform(
signal Wave : out boolean;
constant Waveform : in T_SIM_WAVEFORM;
constant InitialValue : in boolean := FALSE
);
procedure simGenerateWaveform(
constant TestID : in T_SIM_TEST_ID;
signal Wave : out boolean;
constant Waveform : in T_SIM_WAVEFORM;
constant InitialValue : in boolean := FALSE
);
procedure simGenerateWaveform(
signal Wave : out std_logic;
constant Waveform : in T_SIM_WAVEFORM;
constant InitialValue : in std_logic := '0'
);
procedure simGenerateWaveform(
constant TestID : in T_SIM_TEST_ID;
signal Wave : out std_logic;
constant Waveform : in T_SIM_WAVEFORM;
constant InitialValue : in std_logic := '0'
);
procedure simGenerateWaveform(
signal Wave : out std_logic;
constant Waveform : in T_SIM_WAVEFORM_SL;
constant InitialValue : in std_logic := '0'
);
procedure simGenerateWaveform(
constant TestID : in T_SIM_TEST_ID;
signal Wave : out std_logic;
constant Waveform : in T_SIM_WAVEFORM_SL;
constant InitialValue : in std_logic := '0'
);
procedure simGenerateWaveform(
signal Wave : out T_SLV_8;
constant Waveform : in T_SIM_WAVEFORM_SLV_8;
constant InitialValue : in T_SLV_8 := (others => '0')
);
procedure simGenerateWaveform(
constant TestID : in T_SIM_TEST_ID;
signal Wave : out T_SLV_8;
constant Waveform : in T_SIM_WAVEFORM_SLV_8;
constant InitialValue : in T_SLV_8 := (others => '0')
);
procedure simGenerateWaveform(
signal Wave : out T_SLV_16;
constant Waveform : in T_SIM_WAVEFORM_SLV_16;
constant InitialValue : in T_SLV_16 := (others => '0')
);
procedure simGenerateWaveform(
constant TestID : in T_SIM_TEST_ID;
signal Wave : out T_SLV_16;
constant Waveform : in T_SIM_WAVEFORM_SLV_16;
constant InitialValue : in T_SLV_16 := (others => '0')
);
procedure simGenerateWaveform(
signal Wave : out T_SLV_24;
constant Waveform : in T_SIM_WAVEFORM_SLV_24;
constant InitialValue : in T_SLV_24 := (others => '0')
);
procedure simGenerateWaveform(
constant TestID : in T_SIM_TEST_ID;
signal Wave : out T_SLV_24;
constant Waveform : in T_SIM_WAVEFORM_SLV_24;
constant InitialValue : in T_SLV_24 := (others => '0')
);
procedure simGenerateWaveform(
signal Wave : out T_SLV_32;
constant Waveform : in T_SIM_WAVEFORM_SLV_32;
constant InitialValue : in T_SLV_32 := (others => '0')
);
procedure simGenerateWaveform(
constant TestID : in T_SIM_TEST_ID;
signal Wave : out T_SLV_32;
constant Waveform : in T_SIM_WAVEFORM_SLV_32;
constant InitialValue : in T_SLV_32 := (others => '0')
);
procedure simGenerateWaveform(
signal Wave : out T_SLV_48;
constant Waveform : in T_SIM_WAVEFORM_SLV_48;
constant InitialValue : in T_SLV_48 := (others => '0')
);
procedure simGenerateWaveform(
constant TestID : in T_SIM_TEST_ID;
signal Wave : out T_SLV_48;
constant Waveform : in T_SIM_WAVEFORM_SLV_48;
constant InitialValue : in T_SLV_48 := (others => '0')
);
procedure simGenerateWaveform(
signal Wave : out T_SLV_64;
constant Waveform : in T_SIM_WAVEFORM_SLV_64;
constant InitialValue : in T_SLV_64 := (others => '0')
);
procedure simGenerateWaveform(
constant TestID : in T_SIM_TEST_ID;
signal Wave : out T_SLV_64;
constant Waveform : in T_SIM_WAVEFORM_SLV_64;
constant InitialValue : in T_SLV_64 := (others => '0')
);
function "*" (Wave : T_SIM_WAVEFORM; Times : natural) return T_SIM_WAVEFORM;
function ">" (Wave : T_SIM_WAVEFORM; Offset : time) return T_SIM_WAVEFORM;
function "<" (Wave : T_SIM_WAVEFORM; Offset : time) return T_SIM_WAVEFORM;
function "*" (Wave : T_SIM_WAVEFORM_SLV_8; Times : natural) return T_SIM_WAVEFORM_SLV_8;
function ">" (Wave : T_SIM_WAVEFORM_SLV_8; Offset : time) return T_SIM_WAVEFORM_SLV_8;
-- function "<" (Wave : T_SIM_WAVEFORM_SLV_8; Offset : TIME) return T_SIM_WAVEFORM_SLV_8;
function "*" (Wave : T_SIM_WAVEFORM_SLV_16; Times : natural) return T_SIM_WAVEFORM_SLV_16;
function ">" (Wave : T_SIM_WAVEFORM_SLV_16; Offset : time) return T_SIM_WAVEFORM_SLV_16;
-- function "<" (Wave : T_SIM_WAVEFORM_SLV_16; Offset : TIME) return T_SIM_WAVEFORM_SLV_16;
function "*" (Wave : T_SIM_WAVEFORM_SLV_24; Times : natural) return T_SIM_WAVEFORM_SLV_24;
function ">" (Wave : T_SIM_WAVEFORM_SLV_24; Offset : time) return T_SIM_WAVEFORM_SLV_24;
-- function "<" (Wave : T_SIM_WAVEFORM_SLV_24; Offset : TIME) return T_SIM_WAVEFORM_SLV_24;
function "*" (Wave : T_SIM_WAVEFORM_SLV_32; Times : natural) return T_SIM_WAVEFORM_SLV_32;
function ">" (Wave : T_SIM_WAVEFORM_SLV_32; Offset : time) return T_SIM_WAVEFORM_SLV_32;
-- function "<" (Wave : T_SIM_WAVEFORM_SLV_32; Offset : TIME) return T_SIM_WAVEFORM_SLV_32;
function "*" (Wave : T_SIM_WAVEFORM_SLV_48; Times : natural) return T_SIM_WAVEFORM_SLV_48;
function ">" (Wave : T_SIM_WAVEFORM_SLV_48; Offset : time) return T_SIM_WAVEFORM_SLV_48;
-- function "<" (Wave : T_SIM_WAVEFORM_SLV_48; Offset : TIME) return T_SIM_WAVEFORM_SLV_48;
function "*" (Wave : T_SIM_WAVEFORM_SLV_64; Times : natural) return T_SIM_WAVEFORM_SLV_64;
function ">" (Wave : T_SIM_WAVEFORM_SLV_64; Offset : time) return T_SIM_WAVEFORM_SLV_64;
-- function "<" (Wave : T_SIM_WAVEFORM_SLV_64; Offset : TIME) return T_SIM_WAVEFORM_SLV_64;
-- convert arrays to waveforms
-- TODO: optimize waveform if input data doesn't change
-- TODO: write single bit variant
function to_waveform(bv : bit_vector; Delay : time) return T_SIM_WAVEFORM;
function to_waveform(slv : std_logic_vector; Delay : time) return T_SIM_WAVEFORM_SL;
function to_waveform(slvv : T_SLVV_8; Delay : time) return T_SIM_WAVEFORM_SLV_8;
function to_waveform(slvv : T_SLVV_16; Delay : time) return T_SIM_WAVEFORM_SLV_16;
function to_waveform(slvv : T_SLVV_24; Delay : time) return T_SIM_WAVEFORM_SLV_24;
function to_waveform(slvv : T_SLVV_32; Delay : time) return T_SIM_WAVEFORM_SLV_32;
function to_waveform(slvv : T_SLVV_48; Delay : time) return T_SIM_WAVEFORM_SLV_48;
function to_waveform(slvv : T_SLVV_64; Delay : time) return T_SIM_WAVEFORM_SLV_64;
-- predefined common waveforms
function simGenerateWaveform_Reset(constant Pause : time := 0 ns; ResetPulse : time := 10 ns) return T_SIM_WAVEFORM;
-- TODO: integrate VCD simulation functions and procedures from sim_value_change_dump.vhdl here
end package;
package body waveform is
-- clock generation
-- ===========================================================================
procedure simGenerateClock(
signal Clock : out std_logic;
constant Frequency : in FREQ;
constant Phase : in T_PHASE := 0 deg;
constant DutyCycle : in T_DUTYCYCLE := 50 percent;
constant Wander : in T_WANDER := 0 permil
) is
constant Period : time := to_time(Frequency);
begin
simGenerateClock(C_SIM_DEFAULT_TEST_ID, Clock, Period, Phase, DutyCycle, Wander);
end procedure;
procedure simGenerateClock(
constant TestID : in T_SIM_TEST_ID;
signal Clock : out std_logic;
constant Frequency : in FREQ;
constant Phase : in T_PHASE := 0 deg;
constant DutyCycle : in T_DUTYCYCLE := 50 percent;
constant Wander : in T_WANDER := 0 permil
) is
constant Period : time := to_time(Frequency);
begin
simGenerateClock(TestID, Clock, Period, Phase, DutyCycle, Wander);
end procedure;
procedure simGenerateClock(
signal Clock : out std_logic;
constant Period : in time;
constant Phase : in T_PHASE := 0 deg;
constant DutyCycle : in T_DUTYCYCLE := 50 percent;
constant Wander : in T_WANDER := 0 permil
) is
begin
simGenerateClock(C_SIM_DEFAULT_TEST_ID, Clock, Period, Phase, DutyCycle, Wander);
end procedure;
procedure simGenerateClock(
constant TestID : in T_SIM_TEST_ID;
signal Clock : out std_logic;
constant Period : in time;
constant Phase : in T_PHASE := 0 deg;
constant DutyCycle : in T_DUTYCYCLE := 50 percent;
constant Wander : in T_WANDER := 0 permil
) is
constant NormalizedPhase : T_PHASE := ite((Phase >= 0 deg), Phase, Phase + 360 deg); -- move Phase into the range of 0° to 360°
constant PhaseAsFactor : REAL := real(NormalizedPhase / 1 second) / 1296000.0; -- 1,296,000 = 3,600 seconds * 360 degree per cycle
constant WanderAsFactor : REAL := real(Wander / 1 ppb) / 1.0e9;
constant DutyCycleAsFactor : REAL := real(DutyCycle / 1 permil) / 1000.0;
constant Delay : time := Period * PhaseAsFactor;
constant TimeHigh : time := Period * DutyCycleAsFactor + (Period * (WanderAsFactor / 2.0)); -- add 50% wander to the high level
constant TimeLow : time := Period - TimeHigh + (Period * WanderAsFactor); -- and 50% to the low level
constant ClockAfterRun_cy : positive := 5;
constant PROCESS_ID : T_SIM_PROCESS_ID := simRegisterProcess(TestID, "simGenerateClock(period=" & to_string(Period, 2) & ")", IsLowPriority => TRUE);
begin
-- report "simGenerateClock: (Instance: '" & Clock'instance_name & "')" & LF &
-- "Period: " & TIME'image(Period) & LF &
-- "Phase: " & T_PHASE'image(Phase) & LF &
-- "DutyCycle: " & T_DUTYCYCLE'image(DutyCycle) & LF &
-- "PhaseAsFactor: " & REAL'image(PhaseAsFactor) & LF &
-- "WanderAsFactor: " & REAL'image(WanderAsFactor) & LF &
-- "DutyCycleAsFactor: " & REAL'image(DutyCycleAsFactor) & LF &
-- "Delay: " & TIME'image(Delay) & LF &
-- "TimeHigh: " & TIME'image(TimeHigh) & LF &
-- "TimeLow: " & TIME'image(TimeLow)
-- severity NOTE;
if (Delay = 0 ns) then
null;
elsif (Delay <= TimeLow) then
Clock <= '0';
wait for Delay;
else
Clock <= '1';
wait for Delay - TimeLow;
Clock <= '0';
wait for TimeLow;
end if;
Clock <= '1';
while not simIsStopped(TestID) loop
wait for TimeHigh;
Clock <= '0';
wait for TimeLow;
Clock <= '1';
end loop;
simDeactivateProcess(PROCESS_ID);
-- create N more cycles to allow other processes to recognize the stop condition (clock after run)
for i in 1 to ClockAfterRun_cy loop
wait for TimeHigh;
Clock <= '0';
wait for TimeLow;
Clock <= '1';
end loop;
Clock <= '0';
end procedure;
type T_SIM_NORMAL_DIST_PARAMETER is record
StandardDeviation : REAL;
Mean : REAL;
end record;
type T_JITTER_DISTRIBUTION is array (natural range <>) of T_SIM_NORMAL_DIST_PARAMETER;
procedure simGenerateClock2(
constant TestID : in T_SIM_TEST_ID;
signal Clock : out std_logic;
signal Debug : out REAL;
constant Period : in time
) is
constant TimeHigh : time := Period * 0.5;
constant TimeLow : time := Period - TimeHigh;
constant JitterPeakPeak : REAL := 0.1; -- UI
constant JitterAsFactor : REAL := JitterPeakPeak / 4.0; -- Maximum jitter per edge
constant JitterDistribution : T_JITTER_DISTRIBUTION := (
-- 0 => (StandardDeviation => 0.2, Mean => -0.4),
-- 1 => (StandardDeviation => 0.2, Mean => 0.4)
-- 0 => (StandardDeviation => 0.2, Mean => -0.4),
-- 1 => (StandardDeviation => 0.3, Mean => -0.1),
-- 2 => (StandardDeviation => 0.5, Mean => 0.0),
-- 3 => (StandardDeviation => 0.3, Mean => 0.1),
-- 4 => (StandardDeviation => 0.2, Mean => 0.4)
0 => (StandardDeviation => 0.15, Mean => -0.6),
1 => (StandardDeviation => 0.2, Mean => -0.3),
2 => (StandardDeviation => 0.25, Mean => -0.2),
3 => (StandardDeviation => 0.3, Mean => 0.0),
4 => (StandardDeviation => 0.25, Mean => 0.2),
5 => (StandardDeviation => 0.2, Mean => 0.3),
6 => (StandardDeviation => 0.15, Mean => 0.6)
);
variable Seed : T_SIM_RAND_SEED;
variable rand : REAL;
variable Jitter : REAL;
variable Index : natural;
constant ClockAfterRun_cy : positive := 5;
begin
Clock <= '1';
randInitializeSeed(Seed);
while not simIsStopped(TestID) loop
ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, rand);
Index := scale(rand, 0, JitterDistribution'length * 10) mod JitterDistribution'length;
randNormalDistributedValue(Seed, rand, JitterDistribution(Index).StandardDeviation, JitterDistribution(Index).Mean, -1.0, 1.0);
Jitter := JitterAsFactor * rand;
Debug <= rand;
-- Debug <= integer(rand * 256.0 + 256.0);
wait for TimeHigh + (Period * Jitter);
Clock <= '0';
wait for TimeLow + (Period * Jitter);
Clock <= '1';
end loop;
-- create N more cycles to allow other processes to recognize the stop condition (clock after run)
for i in 1 to ClockAfterRun_cy loop
wait for TimeHigh;
Clock <= '0';
wait for TimeLow;
Clock <= '1';
end loop;
Clock <= '0';
end procedure;
procedure simWaitUntilRisingEdge(signal Clock : in std_logic; constant Times : in positive) is
begin
simWaitUntilRisingEdge(C_SIM_DEFAULT_TEST_ID, Clock, Times);
end procedure;
procedure simWaitUntilRisingEdge(constant TestID : in T_SIM_TEST_ID; signal Clock : in std_logic; constant Times : in positive) is
begin
for i in 1 to Times loop
wait until rising_edge(Clock);
exit when simIsStopped(TestID);
end loop;
end procedure;
procedure simWaitUntilFallingEdge(signal Clock : in std_logic; constant Times : in positive) is
begin
simWaitUntilFallingEdge(C_SIM_DEFAULT_TEST_ID, Clock, Times);
end procedure;
procedure simWaitUntilFallingEdge(constant TestID : in T_SIM_TEST_ID; signal Clock : in std_logic; constant Times : in positive) is
begin
for i in 1 to Times loop
wait until falling_edge(Clock);
exit when simIsStopped(TestID);
end loop;
end procedure;
-- waveform generation
-- ===========================================================================
procedure simGenerateWaveform(
signal Wave : out boolean;
constant Waveform : in T_SIM_WAVEFORM;
constant InitialValue : in boolean := FALSE
) is
begin
simGenerateWaveform(C_SIM_DEFAULT_TEST_ID, Wave, Waveform, InitialValue);
end procedure;
procedure simGenerateWaveform(
constant TestID : in T_SIM_TEST_ID;
signal Wave : out boolean;
constant Waveform : in T_SIM_WAVEFORM;
constant InitialValue : in boolean := FALSE
) is
constant PROCESS_ID : T_SIM_PROCESS_ID := simRegisterProcess(TestID, "simGenerateWaveform");
variable State : boolean;
begin
State := InitialValue;
Wave <= State;
for i in Waveform'range loop
wait for Waveform(i);
State := not State;
Wave <= State;
exit when simIsStopped(TestID);
end loop;
simDeactivateProcess(PROCESS_ID);
end procedure;
procedure simGenerateWaveform(
signal Wave : out std_logic;
constant Waveform : in T_SIM_WAVEFORM;
constant InitialValue : in std_logic := '0'
) is
begin
simGenerateWaveform(C_SIM_DEFAULT_TEST_ID, Wave, Waveform, InitialValue);
end procedure;
procedure simGenerateWaveform(
constant TestID : in T_SIM_TEST_ID;
signal Wave : out std_logic;
constant Waveform : in T_SIM_WAVEFORM;
constant InitialValue : in std_logic := '0'
) is
constant PROCESS_ID : T_SIM_PROCESS_ID := simRegisterProcess(TestID, "simGenerateWaveform");
variable State : std_logic;
begin
State := InitialValue;
Wave <= State;
for i in Waveform'range loop
wait for Waveform(i);
State := not State;
Wave <= State;
exit when simIsStopped(TestID);
end loop;
simDeactivateProcess(PROCESS_ID);
end procedure;
procedure simGenerateWaveform(
signal Wave : out std_logic;
constant Waveform : in T_SIM_WAVEFORM_SL;
constant InitialValue : in std_logic := '0'
) is
begin
simGenerateWaveform(C_SIM_DEFAULT_TEST_ID, Wave, Waveform, InitialValue);
end procedure;
procedure simGenerateWaveform(
constant TestID : in T_SIM_TEST_ID;
signal Wave : out std_logic;
constant Waveform : in T_SIM_WAVEFORM_SL;
constant InitialValue : in std_logic := '0'
) is
constant PROCESS_ID : T_SIM_PROCESS_ID := simRegisterProcess(TestID, "simGenerateWaveform");
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
exit when simIsStopped(TestID);
end loop;
simDeactivateProcess(PROCESS_ID);
end procedure;
procedure simGenerateWaveform(
signal Wave : out T_SLV_8;
constant Waveform : in T_SIM_WAVEFORM_SLV_8;
constant InitialValue : in T_SLV_8 := (others => '0')
) is
begin
simGenerateWaveform(C_SIM_DEFAULT_TEST_ID, Wave, Waveform, InitialValue);
end procedure;
procedure simGenerateWaveform(
constant TestID : in T_SIM_TEST_ID;
signal Wave : out T_SLV_8;
constant Waveform : in T_SIM_WAVEFORM_SLV_8;
constant InitialValue : in T_SLV_8 := (others => '0')
) is
constant PROCESS_ID : T_SIM_PROCESS_ID := simRegisterProcess(TestID, "simGenerateWaveform");
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
exit when simIsStopped(TestID);
end loop;
simDeactivateProcess(PROCESS_ID);
end procedure;
procedure simGenerateWaveform(
signal Wave : out T_SLV_16;
constant Waveform : in T_SIM_WAVEFORM_SLV_16;
constant InitialValue : in T_SLV_16 := (others => '0')
) is
begin
simGenerateWaveform(C_SIM_DEFAULT_TEST_ID, Wave, Waveform, InitialValue);
end procedure;
procedure simGenerateWaveform(
constant TestID : in T_SIM_TEST_ID;
signal Wave : out T_SLV_16;
constant Waveform : in T_SIM_WAVEFORM_SLV_16;
constant InitialValue : in T_SLV_16 := (others => '0')
) is
constant PROCESS_ID : T_SIM_PROCESS_ID := simRegisterProcess(TestID, "simGenerateWaveform");
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
exit when simIsStopped(TestID);
end loop;
simDeactivateProcess(PROCESS_ID);
end procedure;
procedure simGenerateWaveform(
signal Wave : out T_SLV_24;
constant Waveform : in T_SIM_WAVEFORM_SLV_24;
constant InitialValue : in T_SLV_24 := (others => '0')
) is
begin
simGenerateWaveform(C_SIM_DEFAULT_TEST_ID, Wave, Waveform, InitialValue);
end procedure;
procedure simGenerateWaveform(
constant TestID : in T_SIM_TEST_ID;
signal Wave : out T_SLV_24;
constant Waveform : in T_SIM_WAVEFORM_SLV_24;
constant InitialValue : in T_SLV_24 := (others => '0')
) is
constant PROCESS_ID : T_SIM_PROCESS_ID := simRegisterProcess(TestID, "simGenerateWaveform");
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
exit when simIsStopped(TestID);
end loop;
simDeactivateProcess(PROCESS_ID);
end procedure;
procedure simGenerateWaveform(
signal Wave : out T_SLV_32;
constant Waveform : in T_SIM_WAVEFORM_SLV_32;
constant InitialValue : in T_SLV_32 := (others => '0')
) is
begin
simGenerateWaveform(C_SIM_DEFAULT_TEST_ID, Wave, Waveform, InitialValue);
end procedure;
procedure simGenerateWaveform(
constant TestID : in T_SIM_TEST_ID;
signal Wave : out T_SLV_32;
constant Waveform : in T_SIM_WAVEFORM_SLV_32;
constant InitialValue : in T_SLV_32 := (others => '0')
) is
constant PROCESS_ID : T_SIM_PROCESS_ID := simRegisterProcess(TestID, "simGenerateWaveform");
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
exit when simIsStopped(TestID);
end loop;
simDeactivateProcess(PROCESS_ID);
end procedure;
procedure simGenerateWaveform(
signal Wave : out T_SLV_48;
constant Waveform : in T_SIM_WAVEFORM_SLV_48;
constant InitialValue : in T_SLV_48 := (others => '0')
) is
begin
simGenerateWaveform(C_SIM_DEFAULT_TEST_ID, Wave, Waveform, InitialValue);
end procedure;
procedure simGenerateWaveform(
constant TestID : in T_SIM_TEST_ID;
signal Wave : out T_SLV_48;
constant Waveform : in T_SIM_WAVEFORM_SLV_48;
constant InitialValue : in T_SLV_48 := (others => '0')
) is
constant PROCESS_ID : T_SIM_PROCESS_ID := simRegisterProcess(TestID, "simGenerateWaveform");
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
exit when simIsStopped(TestID);
end loop;
simDeactivateProcess(PROCESS_ID);
end procedure;
procedure simGenerateWaveform(
signal Wave : out T_SLV_64;
constant Waveform : in T_SIM_WAVEFORM_SLV_64;
constant InitialValue : in T_SLV_64 := (others => '0')
) is
begin
simGenerateWaveform(C_SIM_DEFAULT_TEST_ID, Wave, Waveform, InitialValue);
end procedure;
procedure simGenerateWaveform(
constant TestID : in T_SIM_TEST_ID;
signal Wave : out T_SLV_64;
constant Waveform : in T_SIM_WAVEFORM_SLV_64;
constant InitialValue : in T_SLV_64 := (others => '0')
) is
constant PROCESS_ID : T_SIM_PROCESS_ID := simRegisterProcess(TestID, "simGenerateWaveform");
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
exit when simIsStopped(TestID);
end loop;
simDeactivateProcess(PROCESS_ID);
end procedure;
-- Waveform arithmetic
function "*" (Wave : T_SIM_WAVEFORM; Times : natural) return T_SIM_WAVEFORM is
variable Result : T_SIM_WAVEFORM(0 to Wave'length * Times - 1);
begin
for i in 0 to Times - 1 loop
Result(i * Wave'length to (i + 1) * Wave'length - 1) := Wave;
end loop;
return Result;
end function;
function ">" (Wave : T_SIM_WAVEFORM; Offset : time) return T_SIM_WAVEFORM is
begin
return (Wave(Wave'low) + Offset) & Wave(Wave'low + 1 to Wave'high);
end function;
function "<" (Wave : T_SIM_WAVEFORM; Offset : time) return T_SIM_WAVEFORM is
variable Result : T_SIM_WAVEFORM(Wave'range);
variable TimePos : time;
begin
report "Has bugs" severity ERROR;
TimePos := 0 fs;
for i in Wave'range loop
TimePos := TimePos + Wave(i);
if TimePos > Offset then
return (TimePos - Offset) & Wave(i + 1 to Wave'high);
end if;
end loop;
return (0 => 0 fs);
end function;
function "*" (Wave : T_SIM_WAVEFORM_SLV_8; Times : natural) return T_SIM_WAVEFORM_SLV_8 is
variable Result : T_SIM_WAVEFORM_SLV_8(0 to Wave'length * Times - 1);
begin
for i in 0 to Times - 1 loop
Result(i * Wave'length to (i + 1) * Wave'length - 1) := Wave;
end loop;
return Result;
end function;
function ">" (Wave : T_SIM_WAVEFORM_SLV_8; Offset : time) return T_SIM_WAVEFORM_SLV_8 is
begin
return T_SIM_WAVEFORM_TUPLE_SLV_8'(
Delay => Wave(Wave'low).Delay + Offset,
Value => Wave(Wave'low).Value
) & Wave(Wave'low + 1 to Wave'high);
end function;
-- function "<" (Wave : T_SIM_WAVEFORM_SLV_8; Offset : TIME) return T_SIM_WAVEFORM_SLV_8 is
-- begin
-- report "Not implemented" severity FAILURE;
-- end function;
function "*" (Wave : T_SIM_WAVEFORM_SLV_16; Times : natural) return T_SIM_WAVEFORM_SLV_16 is
variable Result : T_SIM_WAVEFORM_SLV_16(0 to Wave'length * Times - 1);
begin
for i in 0 to Times - 1 loop
Result(i * Wave'length to (i + 1) * Wave'length - 1) := Wave;
end loop;
return Result;
end function;
function ">" (Wave : T_SIM_WAVEFORM_SLV_16; Offset : time) return T_SIM_WAVEFORM_SLV_16 is
begin
return T_SIM_WAVEFORM_TUPLE_SLV_16'(
Delay => Wave(Wave'low).Delay + Offset,
Value => Wave(Wave'low).Value
) & Wave(Wave'low + 1 to Wave'high);
end function;
-- function "<" (Wave : T_SIM_WAVEFORM_SLV_16; Offset : TIME) return T_SIM_WAVEFORM_SLV_16 is
-- begin
-- report "Not implemented" severity FAILURE;
-- end function;
function "*" (Wave : T_SIM_WAVEFORM_SLV_24; Times : natural) return T_SIM_WAVEFORM_SLV_24 is
variable Result : T_SIM_WAVEFORM_SLV_24(0 to Wave'length * Times - 1);
begin
for i in 0 to Times - 1 loop
Result(i * Wave'length to (i + 1) * Wave'length - 1) := Wave;
end loop;
return Result;
end function;
function ">" (Wave : T_SIM_WAVEFORM_SLV_24; Offset : time) return T_SIM_WAVEFORM_SLV_24 is
begin
return T_SIM_WAVEFORM_TUPLE_SLV_24'(
Delay => Wave(Wave'low).Delay + Offset,
Value => Wave(Wave'low).Value
) & Wave(Wave'low + 1 to Wave'high);
end function;
-- function "<" (Wave : T_SIM_WAVEFORM_SLV_24; Offset : TIME) return T_SIM_WAVEFORM_SLV_24 is
-- begin
-- report "Not implemented" severity FAILURE;
-- end function;
function "*" (Wave : T_SIM_WAVEFORM_SLV_32; Times : natural) return T_SIM_WAVEFORM_SLV_32 is
variable Result : T_SIM_WAVEFORM_SLV_32(0 to Wave'length * Times - 1);
begin
for i in 0 to Times - 1 loop
Result(i * Wave'length to (i + 1) * Wave'length - 1) := Wave;
end loop;
return Result;
end function;
function ">" (Wave : T_SIM_WAVEFORM_SLV_32; Offset : time) return T_SIM_WAVEFORM_SLV_32 is
begin
return T_SIM_WAVEFORM_TUPLE_SLV_32'(
Delay => Wave(Wave'low).Delay + Offset,
Value => Wave(Wave'low).Value
) & Wave(Wave'low + 1 to Wave'high);
end function;
-- function "<" (Wave : T_SIM_WAVEFORM_SLV_32; Offset : TIME) return T_SIM_WAVEFORM_SLV_32 is
-- begin
-- report "Not implemented" severity FAILURE;
-- end function;
function "*" (Wave : T_SIM_WAVEFORM_SLV_48; Times : natural) return T_SIM_WAVEFORM_SLV_48 is
variable Result : T_SIM_WAVEFORM_SLV_48(0 to Wave'length * Times - 1);
begin
for i in 0 to Times - 1 loop
Result(i * Wave'length to (i + 1) * Wave'length - 1) := Wave;
end loop;
return Result;
end function;
function ">" (Wave : T_SIM_WAVEFORM_SLV_48; Offset : time) return T_SIM_WAVEFORM_SLV_48 is
begin
return T_SIM_WAVEFORM_TUPLE_SLV_48'(
Delay => Wave(Wave'low).Delay + Offset,
Value => Wave(Wave'low).Value
) & Wave(Wave'low + 1 to Wave'high);
end function;
-- function "<" (Wave : T_SIM_WAVEFORM_SLV_48; Offset : TIME) return T_SIM_WAVEFORM_SLV_48 is
-- begin
-- report "Not implemented" severity FAILURE;
-- end function;
function "*" (Wave : T_SIM_WAVEFORM_SLV_64; Times : natural) return T_SIM_WAVEFORM_SLV_64 is
variable Result : T_SIM_WAVEFORM_SLV_64(0 to Wave'length * Times - 1);
begin
for i in 0 to Times - 1 loop
Result(i * Wave'length to (i + 1) * Wave'length - 1) := Wave;
end loop;
return Result;
end function;
function ">" (Wave : T_SIM_WAVEFORM_SLV_64; Offset : time) return T_SIM_WAVEFORM_SLV_64 is
begin
return T_SIM_WAVEFORM_TUPLE_SLV_64'(
Delay => Wave(Wave'low).Delay + Offset,
Value => Wave(Wave'low).Value
) & Wave(Wave'low + 1 to Wave'high);
end function;
-- function "<" (Wave : T_SIM_WAVEFORM_SLV_64; Offset : TIME) return T_SIM_WAVEFORM_SLV_64 is
-- begin
-- report "Not implemented" severity FAILURE;
-- end function;
function to_waveform(bv : bit_vector; Delay : time) return T_SIM_WAVEFORM is
variable Result : T_SIM_WAVEFORM(0 to bv'length - 1);
begin
report "Has bugs" severity ERROR;
for i in 0 to bv'length - 1 loop
Result(i) := Delay;
end loop;
return Result;
end function;
function to_waveform(slv : std_logic_vector; Delay : time) return T_SIM_WAVEFORM_SL is
variable Result : T_SIM_WAVEFORM_SL(0 to slv'length - 1);
begin
for i in 0 to slv'length - 1 loop
Result(i).Delay := Delay;
Result(i).Value := slv(i);
end loop;
return Result;
end function;
function to_waveform(slvv : T_SLVV_8; Delay : time) return T_SIM_WAVEFORM_SLV_8 is
variable Result : T_SIM_WAVEFORM_SLV_8(0 to slvv'length - 1);
begin
for i in 0 to slvv'length - 1 loop
Result(i).Delay := Delay;
Result(i).Value := slvv(i);
end loop;
return Result;
end function;
function to_waveform(slvv : T_SLVV_16; Delay : time) return T_SIM_WAVEFORM_SLV_16 is
variable Result : T_SIM_WAVEFORM_SLV_16(0 to slvv'length - 1);
begin
for i in 0 to slvv'length - 1 loop
Result(i).Delay := Delay;
Result(i).Value := slvv(i);
end loop;
return Result;
end function;
function to_waveform(slvv : T_SLVV_24; Delay : time) return T_SIM_WAVEFORM_SLV_24 is
variable Result : T_SIM_WAVEFORM_SLV_24(0 to slvv'length - 1);
begin
for i in 0 to slvv'length - 1 loop
Result(i).Delay := Delay;
Result(i).Value := slvv(i);
end loop;
return Result;
end function;
function to_waveform(slvv : T_SLVV_32; Delay : time) return T_SIM_WAVEFORM_SLV_32 is
variable Result : T_SIM_WAVEFORM_SLV_32(0 to slvv'length - 1);
begin
for i in 0 to slvv'length - 1 loop
Result(i).Delay := Delay;
Result(i).Value := slvv(i);
end loop;
return Result;
end function;
function to_waveform(slvv : T_SLVV_48; Delay : time) return T_SIM_WAVEFORM_SLV_48 is
variable Result : T_SIM_WAVEFORM_SLV_48(0 to slvv'length - 1);
begin
for i in 0 to slvv'length - 1 loop
Result(i).Delay := Delay;
Result(i).Value := slvv(i);
end loop;
return Result;
end function;
function to_waveform(slvv : T_SLVV_64; Delay : time) return T_SIM_WAVEFORM_SLV_64 is
variable Result : T_SIM_WAVEFORM_SLV_64(0 to slvv'length - 1);
begin
for i in 0 to slvv'length - 1 loop
Result(i).Delay := Delay;
Result(i).Value := slvv(i);
end loop;
return Result;
end function;
-- predefined common waveforms
function simGenerateWaveform_Reset(constant Pause : time := 0 ns; ResetPulse : time := 10 ns) return T_SIM_WAVEFORM is
variable p : time;
variable rp : time;
begin
-- WORKAROUND: for Mentor QuestaSim/ModelSim
-- Version: 10.4c
-- Issue:
-- return (0 => Pause, 1 => ResetPulse); always evaluates to (0 ns, 10 ns),
-- regardless of the passed function parameters
-- Bugfix:
-- The bugfix will be included in 10.5a, but this workaround must be
-- present until Altera updates the embedded ModelSim Altera Edition.
p := Pause;
rp := ResetPulse;
return (0 => p, 1 => rp);
end function;
end package body;
| gpl-2.0 | 0226ac05ee5fef9041d07038ab166aef | 0.659809 | 3.012134 | false | true | false | false |
tgingold/ghdl | testsuite/gna/bug019/PoC/src/io/uart/uart_rx.vhdl | 3 | 5,073 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: UART Receiver
--
-- Description:
-- ------------------------------------
-- TODO
--
-- old comments:
-- Serial configuration: 8 data bits, 1 stop bit, no parity
--
-- bclk_x8 = bit clock (defined by BAUD rate) times 8
-- dos = data out strobe, signals that dout is valid, active high for one
-- cycle
-- dout = data out = received byte
--
-- OUT_REGS:
-- If disabled, then dos is a combinatorial output. Further merging of logic is
-- possible but timing constraints might fail. If enabled, 9 more registers are
-- required. But now, dout toggles only after receiving of full byte.
--
--
-- License:
-- ============================================================================
-- Copyright 2008-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.components.all;
entity uart_rx is
generic (
OUT_REGS : boolean
);
port (
clk : in std_logic;
rst : in std_logic;
bclk_x8 : in std_logic;
rxd : in std_logic;
dos : out std_logic;
dout : out std_logic_vector(7 downto 0)
);
end entity;
architecture rtl of uart_rx is
type states is (IDLE, RDATA);
signal state : states := IDLE;
signal next_state : states;
-- registers
signal rxd_reg1 : std_logic := '1';
signal rxd_reg2 : std_logic := '1';
signal sr : std_logic_vector(7 downto 0) := (others => '0'); -- data only
signal bclk_cnt : unsigned(2 downto 0) := to_unsigned(4, 3);
signal shift_cnt : unsigned(3 downto 0) := (others => '0');
-- control signals
signal rxd_falling : std_logic;
signal bclk_rising : std_logic;
signal start_bclk : std_logic;
signal shift_sr : std_logic;
signal shift_done : std_logic;
signal put_data : std_logic;
begin
rxd_falling <= (not rxd_reg1) and rxd_reg2;
bclk_rising <= bclk_x8 when (comp_allone(bclk_cnt) = '1') else '0';
-- shift_cnt count from 0 to 9 (1 start bit + 8 data bits)
shift_cnt <= upcounter_next(cnt => shift_cnt, rst => start_bclk, en => shift_sr) when rising_edge(clk);
shift_done <= upcounter_equal(cnt => shift_cnt, value => 9);
bclk_cnt <= upcounter_next(cnt => bclk_cnt, rst => start_bclk, en => bclk_x8, init => 4) when rising_edge(clk);
process (state, rxd_falling, bclk_x8, bclk_rising, shift_done)
begin
next_state <= state;
start_bclk <= '0';
shift_sr <= '0';
put_data <= '0';
case state is
when IDLE =>
-- wait for start bit
if (rxd_falling and bclk_x8) = '1' then
next_state <= RDATA;
start_bclk <= '1'; -- = rst_shift_cnt
end if;
when RDATA =>
if bclk_rising = '1' then
-- bit clock keeps running
if shift_done = '1' then
-- stop bit reached
put_data <= '1';
next_state <= IDLE;
else
-- TODO: check start bit?
shift_sr <= '1';
end if;
end if;
when others => null;
end case;
end process;
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
state <= IDLE;
else
state <= next_state;
end if;
rxd_reg1 <= rxd;
if bclk_x8 = '1' then
-- align to bclk_x8, so when we can easily check for
-- the falling edge of the start bit
rxd_reg2 <= rxd_reg1;
end if;
if shift_sr = '1' then
-- shift into MSB
sr <= rxd_reg2 & sr(sr'left downto 1);
end if;
end if;
end process;
-- output
gOutRegs: if OUT_REGS = true generate
process (clk)
begin
if rising_edge(clk) then
dos <= put_data and rxd_reg2; -- check stop bit
dout <= sr;
end if;
end process;
end generate gOutRegs;
gNoOutRegs: if OUT_REGS = false generate
dos <= put_data and rxd_reg2; -- check stop bit
dout <= sr;
end generate gNoOutRegs;
end;
| gpl-2.0 | a6fdf2cc45fc2c2589abce7147a4b112 | 0.560024 | 3.501035 | false | false | false | false |
nickg/nvc | test/parse/guarded.vhd | 1 | 706 | entity e is end entity;
architecture a of e is
signal x, y, z, q, b : bit;
begin
x <= guarded y; -- Error
with b select z <= guarded q when others; -- Error
b1: block (b = '1') is
begin
x <= guarded y; -- OK
with b select z <= guarded q when others; -- OK
assert guard; -- OK
end block;
b2: block is
signal guard : boolean := true; -- OK
signal q : bit;
disconnect q : bit after 0 ns; -- OK (sem failure)
begin
x <= guarded y; -- OK
with b select z <= guarded q when others; -- OK
end block;
end architecture;
| gpl-3.0 | 4b873e06d5f2d3bb64100bd6c25bc37e | 0.470255 | 4.057471 | false | false | false | false |
lfmunoz/vhdl | ip_blocks/sip_check_data/async_fifo_align_64in_out/sim/async_fifo_align_64in_out.vhd | 1 | 33,486 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY async_fifo_align_64in_out IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END async_fifo_align_64in_out;
ARCHITECTURE async_fifo_align_64in_out_arch OF async_fifo_align_64in_out IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF async_fifo_align_64in_out_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 9,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 64,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 64,
C_ENABLE_RLOCS => 0,
C_FAMILY => "virtex7",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 1,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "512x72",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 510,
C_PROG_FULL_THRESH_NEGATE_VAL => 509,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 9,
C_RD_DEPTH => 512,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 9,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 9,
C_WR_DEPTH => 512,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 9,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => rst,
srst => '0',
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
valid => valid,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END async_fifo_align_64in_out_arch;
| mit | 2d3d6f63353dec77e98b39bbfd86b4aa | 0.607269 | 3.070702 | false | false | false | false |
DE5Amigos/SylvesterTheDE2Bot | DE2Botv3Fall16Main/altpll0.vhd | 1 | 18,727 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: altpll0.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altpll0 IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END altpll0;
ARCHITECTURE SYN OF altpll0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
compensate_clock : STRING;
gate_lock_signal : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
invalid_lock_multiplier : NATURAL;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
valid_lock_multiplier : NATURAL
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC ;
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire7_bv(0 DOWNTO 0) <= "0";
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
sub_wire3 <= sub_wire0(2);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
c2 <= sub_wire3;
locked <= sub_wire4;
sub_wire5 <= inclk0;
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 4,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
clk1_divide_by => 2,
clk1_duty_cycle => 50,
clk1_multiply_by => 1,
clk1_phase_shift => "0",
clk2_divide_by => 1,
clk2_duty_cycle => 50,
clk2_multiply_by => 2,
clk2_phase_shift => "0",
compensate_clock => "CLK0",
gate_lock_signal => "NO",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone II",
invalid_lock_multiplier => 5,
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
valid_lock_multiplier => 1
)
PORT MAP (
inclk => sub_wire6,
areset => areset,
clk => sub_wire0,
locked => sub_wire4
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "4"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "12.500000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "25.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "100.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "300.000"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll0.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| mit | 5eeb0da0cb74a9484a8fc1855353591b | 0.68452 | 3.246706 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug035/arith_prng_tb.vhdl | 2 | 4,840 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Testbench: Pseudo-Random Number Generator (PRNG).
--
-- Authors: Patrick Lehmann
--
-- Description:
-- ------------------------------------
-- Automated testbench for PoC.arith_prng
-- The Pseudo-Random Number Generator is instantiated for 8 bits. The
-- output sequence is compared to 256 pre calculated values.
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
LIBRARY PoC;
USE PoC.utils.ALL;
USE PoC.vectors.ALL;
USE PoC.strings.ALL;
USE PoC.simulation.ALL;
ENTITY arith_prng_tb IS
END;
ARCHITECTURE test OF arith_prng_tb IS
CONSTANT CLOCK_PERIOD_100MHZ : TIME := 10 ns;
CONSTANT COMPARE_LIST_8_BITS : T_SLVV_8(0 TO 255) := (
x"12", x"24", x"48", x"90", x"21", x"42", x"85", x"0A", x"14", x"28", x"51", x"A2", x"45", x"8B", x"17", x"2E",
x"5D", x"BB", x"77", x"EF", x"DE", x"BC", x"79", x"F2", x"E4", x"C9", x"93", x"27", x"4E", x"9C", x"38", x"70",
x"E1", x"C3", x"86", x"0C", x"18", x"31", x"63", x"C6", x"8C", x"19", x"33", x"67", x"CE", x"9D", x"3A", x"74",
x"E9", x"D2", x"A5", x"4B", x"96", x"2D", x"5B", x"B7", x"6E", x"DD", x"BA", x"75", x"EB", x"D6", x"AD", x"5A",
x"B5", x"6A", x"D5", x"AB", x"56", x"AC", x"58", x"B1", x"62", x"C4", x"88", x"11", x"22", x"44", x"89", x"13",
x"26", x"4C", x"98", x"30", x"61", x"C2", x"84", x"08", x"10", x"20", x"40", x"81", x"02", x"05", x"0B", x"16",
x"2C", x"59", x"B3", x"66", x"CC", x"99", x"32", x"65", x"CA", x"95", x"2B", x"57", x"AE", x"5C", x"B9", x"73",
x"E7", x"CF", x"9F", x"3E", x"7C", x"F8", x"F1", x"E2", x"C5", x"8A", x"15", x"2A", x"55", x"AA", x"54", x"A8",
x"50", x"A0", x"41", x"83", x"06", x"0D", x"1A", x"35", x"6B", x"D7", x"AF", x"5E", x"BD", x"7B", x"F6", x"EC",
x"D8", x"B0", x"60", x"C0", x"80", x"00", x"01", x"03", x"07", x"0F", x"1E", x"3D", x"7A", x"F4", x"E8", x"D0",
x"A1", x"43", x"87", x"0E", x"1C", x"39", x"72", x"E5", x"CB", x"97", x"2F", x"5F", x"BF", x"7F", x"FE", x"FD",
x"FB", x"F7", x"EE", x"DC", x"B8", x"71", x"E3", x"C7", x"8E", x"1D", x"3B", x"76", x"ED", x"DA", x"B4", x"68",
x"D1", x"A3", x"47", x"8F", x"1F", x"3F", x"7E", x"FC", x"F9", x"F3", x"E6", x"CD", x"9B", x"36", x"6D", x"DB",
x"B6", x"6C", x"D9", x"B2", x"64", x"C8", x"91", x"23", x"46", x"8D", x"1B", x"37", x"6F", x"DF", x"BE", x"7D",
x"FA", x"F5", x"EA", x"D4", x"A9", x"52", x"A4", x"49", x"92", x"25", x"4A", x"94", x"29", x"53", x"A6", x"4D",
x"9A", x"34", x"69", x"D3", x"A7", x"4F", x"9E", x"3C", x"78", x"F0", x"E0", x"C1", x"82", x"04", x"09", x"12"
);
SIGNAL SimStop : std_logic := '0';
SIGNAL Clock : STD_LOGIC := '1';
SIGNAL Reset : STD_LOGIC := '0';
SIGNAL Test_got : STD_LOGIC := '0';
SIGNAL PRNG_Value : T_SLV_8;
BEGIN
Clock <= Clock xnor SimStop after CLOCK_PERIOD_100MHZ / 2.0;
PROCESS
BEGIN
WAIT UNTIL rising_edge(Clock);
Reset <= '1';
WAIT UNTIL rising_edge(Clock);
Reset <= '0';
WAIT UNTIL rising_edge(Clock);
FOR I IN 0 TO 255 LOOP
Test_got <= '1';
WAIT UNTIL rising_edge(Clock);
tbAssert((PRNG_Value = COMPARE_LIST_8_BITS(I)), "I=" & integer'image(I) & " Value=" & raw_format_slv_hex(PRNG_Value) & " Expected=" & raw_format_slv_hex(COMPARE_LIST_8_BITS(I)));
END LOOP;
-- Report overall simulation result
tbPrintResult;
SimStop <= '1';
assert now < 3000 ns severity failure;
WAIT;
END PROCESS;
prng : entity PoC.arith_prng
generic map (
BITS => 8,
SEED => x"12"
)
port map (
clk => Clock,
rst => Reset, -- reset value to initial seed
got => Test_got, -- the current value has been got, and a new value should be calculated
val => PRNG_Value -- the pseudo-random number
);
END;
| gpl-2.0 | 00b2c717d973fb59c69b7bdee0c172ff | 0.529339 | 2.362128 | false | true | false | false |
nickg/nvc | lib/std.19/env.vhdl | 1 | 13,338 | -- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Environment package
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named std.
-- :
-- Developers: IEEE P1076 Working Group
-- :
-- Purpose : This packages defines basic tool interface subprograms
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
use work.textio.all;
package ENV is
procedure STOP (STATUS: INTEGER);
procedure STOP;
procedure FINISH (STATUS: INTEGER);
procedure FINISH;
function RESOLUTION_LIMIT return DELAY_LENGTH;
type DAYOFWEEK is (
SUNDAY, MONDAY, TUESDAY, WEDNESDAY, THURSDAY,
FRIDAY, SATURDAY
);
-- Calendar date/time, broken into parts. Second accomodates both
-- single and double leap-seconds. Dayofyear accomodates leap days.
-- Month 0 is January, 1 is February, 11 is December. Year is absolute
-- in AD, 1900 represents the year 1900.
--
type TIME_RECORD is record
microsecond : INTEGER range 0 to 999_999;
second : INTEGER range 0 to 61;
minute : INTEGER range 0 to 59;
hour : INTEGER range 0 to 23;
day : INTEGER range 1 to 31;
month : INTEGER range 0 to 11;
year : INTEGER range 1 to 4095;
weekday : DAYOFWEEK;
dayofyear : INTEGER range 0 to 365;
end record TIME_RECORD;
-- Current local time broken into parts.
-- Minimum legal resolution is 1 second.
impure function LOCALTIME return TIME_RECORD;
-- Current UTC time broken into parts.
-- Minimum legal resolution is 1 second.
impure function GMTIME return TIME_RECORD;
-- Number of seconds since midnight, Jan 1 1970, UTC.
-- Minimum legal resolution is 1 second.
impure function EPOCH return REAL;
-- Time conversion functions from epoch time.
function LOCALTIME(TIMER: REAL) return TIME_RECORD;
function GMTIME(TIMER: REAL) return TIME_RECORD;
-- Time conversion function from time in parts.
-- EPOCH and GMTIME accept TREC in local time.
-- LOCALTIME accepts TREC in UTC.
function EPOCH(TREC: TIME_RECORD) return REAL;
function LOCALTIME(TREC: TIME_RECORD) return TIME_RECORD;
function GMTIME(TREC: TIME_RECORD) return TIME_RECORD;
-- Time increment/decrement. DELTA argument is in seconds.
-- Returned TIME_RECORD is in local time or UTC per the TREC.
function "+"(TREC: TIME_RECORD; DELTA: REAL) return TIME_RECORD;
function "+"(DELTA: REAL; TREC: TIME_RECORD) return TIME_RECORD;
function "-"(TREC: TIME_RECORD; DELTA: REAL) return TIME_RECORD;
function "-"(DELTA: REAL; TREC: TIME_RECORD) return TIME_RECORD;
-- Time difference in seconds. TR1, TR2 must both be in local
-- time, or both in UTC.
function "-"(TR1, TR2: TIME_RECORD) return REAL;
-- Conversion between real seconds and VHDL TIME. SECONDS_TO_TIME
-- will cause an error if the resulting REAL_VAL would be less than
-- TIME'LOW or greater than TIME'HIGH.
function TIME_TO_SECONDS(TIME_VAL: IN TIME) return REAL;
function SECONDS_TO_TIME(REAL_VAL: IN REAL) return TIME;
-- Convert TIME_RECORD to a string in ISO 8601 format.
-- TO_STRING(x) => "1973-09-16T01:03:52"
-- TO_STRING(x, 6) => "1973-09-16T01:03:52.000001"
function TO_STRING(TREC: TIME_RECORD;
FRAC_DIGITS: INTEGER range 0 to 6 := 0)
return STRING;
impure function GETENV(Name : STRING) return STRING;
impure function GETENV(Name : STRING) return LINE;
impure function VHDL_VERSION return STRING;
function TOOL_TYPE return STRING;
function TOOL_VENDOR return STRING;
function TOOL_NAME return STRING;
function TOOL_EDITION return STRING;
function TOOL_VERSION return STRING;
type DIRECTORY_ITEMS is access LINE_VECTOR;
-- The predefined operations for this type are as follows:
-- function"=" (anonymous, anonymous: DIRECTORY_ITEMS) return BOOLEAN;
-- function"/=" (anonymous, anonymous: DIRECTORY_ITEMS) return BOOLEAN;
-- procedure DEALLOCATE (P: inout DIRECTORY_ITEMS);
type DIRECTORY is record
Name : LINE; -- current directory name; resolved to its canonical form
Items : DIRECTORY_ITEMS; -- list of pointers to directory item names
end record;
-- The predefined operations for this type are as follows:
-- function "="(anonymous, anonymous: DIRECTORY) return BOOLEAN;
-- function "/="(anonymous, anonymous: DIRECTORY) return BOOLEAN;
type DIR_OPEN_STATUS is (
STATUS_OK,
STATUS_NOT_FOUND,
STATUS_NO_DIRECTORY,
STATUS_ACCESS_DENIED,
STATUS_ERROR
);
-- The predefined operations for this type are as follows:
-- function "="(anonymous, anonymous: DIR_OPEN_STATUS) return BOOLEAN;
-- function "/="(anonymous, anonymous: DIR_OPEN_STATUS) return BOOLEAN;
-- function "<"(anonymous, anonymous: DIR_OPEN_STATUS) return BOOLEAN;
-- function "<="(anonymous, anonymous: DIR_OPEN_STATUS) return BOOLEAN;
-- function ">"(anonymous, anonymous: DIR_OPEN_STATUS) return BOOLEAN;
-- function ">="(anonymous, anonymous: DIR_OPEN_STATUS) return BOOLEAN;
-- function MINIMUM (L, R: DIR_OPEN_STATUS) return DIR_OPEN_STATUS;
-- function MAXIMUM (L, R: DIR_OPEN_STATUS) return DIR_OPEN_STATUS;
type DIR_CREATE_STATUS is (
STATUS_OK,
STATUS_ITEM_EXISTS,
STATUS_ACCESS_DENIED,
STATUS_ERROR
);
-- The predefined operations for this type are as follows:
-- function "="(anonymous, anonymous: DIR_CREATE_STATUS) return BOOLEAN;
-- function "/="(anonymous, anonymous: DIR_CREATE_STATUS) return BOOLEAN;
-- function "<"(anonymous, anonymous: DIR_CREATE_STATUS) return BOOLEAN;
-- function "<="(anonymous, anonymous: DIR_CREATE_STATUS) return BOOLEAN;
-- function ">"(anonymous, anonymous: DIR_CREATE_STATUS) return BOOLEAN;
-- function ">="(anonymous, anonymous: DIR_CREATE_STATUS) return BOOLEAN;
-- function MINIMUM (L, R: DIR_CREATE_STATUS) return DIR_CREATE_STATUS;
-- function MAXIMUM (L, R: DIR_CREATE_STATUS) return DIR_CREATE_STATUS;
type DIR_DELETE_STATUS is (
STATUS_OK,
STATUS_NO_DIRECTORY,
STATUS_NOT_EMPTY,
STATUS_ACCESS_DENIED,
STATUS_ERROR
);
-- The predefined operations for this type are as follows:
-- function "="(anonymous, anonymous: DIR_DELETE_STATUS) return BOOLEAN;
-- function "/="(anonymous, anonymous: DIR_DELETE_STATUS) return BOOLEAN;
-- function "<"(anonymous, anonymous: DIR_DELETE_STATUS) return BOOLEAN;
-- function "<="(anonymous, anonymous: DIR_DELETE_STATUS) return BOOLEAN;
-- function ">"(anonymous, anonymous: DIR_DELETE_STATUS) return BOOLEAN;
-- function ">="(anonymous, anonymous: DIR_DELETE_STATUS) return BOOLEAN;
-- function MINIMUM (L, R: DIR_DELETE_STATUS) return DIR_DELETE_STATUS;
-- function MAXIMUM (L, R: DIR_DELETE_STATUS) return DIR_DELETE_STATUS;
type FILE_DELETE_STATUS is (
STATUS_OK,
STATUS_NO_FILE,
STATUS_ACCESS_DENIED,
STATUS_ERROR
);
-- The predefined operations for this type are as follows:
-- function "="(anonymous, anonymous: FILE_DELETE_STATUS) return BOOLEAN;
-- function "/="(anonymous, anonymous: FILE_DELETE_STATUS) return BOOLEAN;
-- function "<"(anonymous, anonymous: FILE_DELETE_STATUS) return BOOLEAN;
-- function "<="(anonymous, anonymous: FILE_DELETE_STATUS) return BOOLEAN;
-- function ">"(anonymous, anonymous: FILE_DELETE_STATUS) return BOOLEAN;
-- function ">="(anonymous, anonymous: FILE_DELETE_STATUS) return BOOLEAN;
-- function MINIMUM (L, R: FILE_DELETE_STATUS) return FILE_DELETE_STATUS;
-- function MAXIMUM (L, R: FILE_DELETE_STATUS) return FILE_DELETE_STATUS;
procedure DIR_OPEN(Dir : out DIRECTORY; Path : in STRING; Status : out DIR_OPEN_STATUS);
impure function DIR_OPEN(Dir : out DIRECTORY; Path : in STRING) return DIR_OPEN_STATUS;
procedure DIR_CLOSE(variable Dir : inout DIRECTORY);
impure function DIR_ITEMEXISTS(Path : in STRING) return BOOLEAN;
impure function DIR_ITEMISDIR(Path : in STRING) return BOOLEAN;
impure function DIR_ITEMISFILE(Path : in STRING) return BOOLEAN;
procedure DIR_WORKINGDIR(Path : in STRING; Status : out DIR_OPEN_STATUS);
impure function DIR_WORKINGDIR(Path : in STRING) return DIR_OPEN_STATUS;
impure function DIR_WORKINGDIR return STRING;
procedure DIR_CREATEDIR(Path : in STRING; Status : out DIR_CREATE_STATUS);
procedure DIR_CREATEDIR(Path : in STRING; Parents : in BOOLEAN; Status : out DIR_CREATE_STATUS);
impure function DIR_CREATEDIR(Path : in STRING; Parents : in BOOLEAN := FALSE) return DIR_CREATE_STATUS;
procedure DIR_DELETEDIR(Path : in STRING; Status : out DIR_DELETE_STATUS);
procedure DIR_DELETEDIR(Path : in STRING; Recursive : in BOOLEAN; Status : out DIR_DELETE_STATUS);
impure function DIR_DELETEDIR(Path : in STRING; Recursive : in BOOLEAN := FALSE) return DIR_DELETE_STATUS;
procedure DIR_DELETEFILE(Path : in STRING; Status : out FILE_DELETE_STATUS);
impure function DIR_DELETEFILE(Path : in STRING) return FILE_DELETE_STATUS;
constant DIR_SEPARATOR : STRING;
type CALL_PATH_ELEMENT is record
name : LINE;
file_name : LINE;
file_path : LINE;
file_line : POSITIVE;
end record;
-- function "=" (anonymous, anonymous: CALL_PATH_ELEMENT) return BOOLEAN;
-- function "/=" (anonymous, anonymous: CALL_PATH_ELEMENT) return BOOLEAN;
impure function TO_STRING (variable call_path : inout CALL_PATH_ELEMENT ) return STRING;
type CALL_PATH_VECTOR is array (natural range <>) of CALL_PATH_ELEMENT;
-- function "=" (anonymous, anonymous: CALL_PATH_VECTOR) return BOOLEAN;
-- function "/=" (anonymous, anonymous: CALL_PATH_VECTOR) return BOOLEAN;
impure function TO_STRING (variable call_path : inout CALL_PATH_VECTOR; Separator : STRING := "" & LF ) return STRING;
type CALL_PATH_VECTOR_PTR is access CALL_PATH_VECTOR;
-- function "=" (anonymous, anonymous: CALL_PATH_VECTOR_PTR) return BOOLEAN;
-- function "/=" (anonymous, anonymous: CALL_PATH_VECTOR_PTR) return BOOLEAN;
-- procedure DEALLOCATE (P: inout CALL_PATH_VECTOR_PTR);
impure function TO_STRING (variable call_path : inout CALL_PATH_VECTOR_PTR; Separator : STRING := "" & LF ) return STRING;
impure function GET_CALL_PATH return CALL_PATH_VECTOR_PTR;
impure function FILE_NAME return LINE;
impure function FILE_NAME return STRING;
impure function FILE_PATH return LINE;
impure function FILE_PATH return STRING;
impure function FILE_LINE return POSITIVE;
impure function FILE_LINE return STRING;
-- VHDL Assert Failed
impure function IsVhdlAssertFailed return boolean;
impure function IsVhdlAssertFailed (Level : SEVERITY_LEVEL ) return boolean;
-- VHDL Assert Count
impure function GetVhdlAssertCount return natural;
impure function GetVhdlAssertCount (Level : SEVERITY_LEVEL ) return natural;
-- Clear VHDL Assert Errors
procedure ClearVhdlAssert;
-- Assert Enable, Disable/Ignore Asserts
procedure SetVhdlAssertEnable(Enable : boolean := TRUE);
procedure SetVhdlAssertEnable(Level : SEVERITY_LEVEL := NOTE; Enable : boolean := TRUE);
impure function GetVhdlAssertEnable(Level : SEVERITY_LEVEL := NOTE) return boolean;
-- Assert statement formatting
procedure SetVhdlAssertFormat(Level : SEVERITY_LEVEL; Format: string);
procedure SetVhdlAssertFormat(Level : SEVERITY_LEVEL; Format: string; Valid : out boolean);
impure function GetVhdlAssertFormat(Level : SEVERITY_LEVEL) return string;
-- VHDL Read Severity
procedure SetVhdlReadSeverity(Level: SEVERITY_LEVEL := FAILURE);
impure function GetVhdlReadSeverity return SEVERITY_LEVEL;
-- PSL Assert Failed
impure function PslAssertFailed return boolean;
-- PSL Is Covered
impure function PslIsCovered return boolean;
-- Psl Cover Asserts
procedure SetPslCoverAssert( Enable : boolean := TRUE);
impure function GetPslCoverAssert return boolean;
-- Psl Is AssertCovered
impure function PslIsAssertCovered return boolean;
-- Clear PSL State (Assert and Cover)
procedure ClearPslState;
end package ENV;
| gpl-3.0 | e1e03a417d47b9ae2ca2ce733b466760 | 0.699355 | 4.055336 | false | false | false | false |
nickg/nvc | test/sem/issue407.vhd | 1 | 988 | entity bug is
end entity;
architecture test of bug is
constant engnum : integer:=8;
subtype engrange is integer range 0 to engnum-1;
type bit_array is array(engrange) of bit;
type byte_array is array(engrange) of bit_vector(7 downto 0);
type mode_t is (RDBMG, C2ENC, C2DEC, C1DEC, WRBMG);
type mode_arr_t is array (natural range <>) of mode_t;
constant ECC_RD_DATA_VAL : bit := '1';
signal buf_ce : bit_vector(engrange);
signal bufmode : mode_arr_t(0 to 0);
signal index : natural := 0;
signal c2enc_ce, c2dec_ce, c1dec_ce : bit_vector(engrange);
signal task4_ce : bit := '1';
begin
ce: with bufmode(index) select buf_ce <=
(engrange => ECC_RD_DATA_VAL) WHEN RDBMG, -- OK
c2enc_ce when C2ENC,
c2dec_ce WHEN C2DEC,
c1dec_ce WHEN C1DEC,
(engrange => task4_ce) WHEN WRBMG, -- OK
(engrange => '0') WHEN others; -- OK
buf_ce <= (bit => '0'); -- Error
end architecture;
| gpl-3.0 | 0d8c205b4b073119f030b5b768adfa9c | 0.610324 | 3.049383 | false | false | false | false |
tgingold/ghdl | testsuite/synth/dff01/tb_dff03.vhdl | 1 | 776 | entity tb_dff03 is
end tb_dff03;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff03 is
signal clk : std_logic;
signal din : std_logic_vector (7 downto 0);
signal dout : std_logic_vector (7 downto 0);
begin
dut: entity work.dff03
port map (
q => dout,
d => din,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
din <= x"00";
pulse;
assert dout = x"00" severity failure;
din <= x"ab";
pulse;
assert dout = x"ab" severity failure;
pulse;
assert dout = x"ab" severity failure;
din <= x"12";
pulse;
assert dout = x"12" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | bf1aabf148635c4cbc5696b55ccd90bf | 0.582474 | 3.344828 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue610/repro2.vhdl | 1 | 274 | entity repro2 is
generic (l : natural := 10);
end repro2;
architecture behav of repro2 is
begin
process
variable v : string (0 to l);
alias a : string is v;
begin
v := (others => ' ');
a := (others => 'x');
wait;
end process;
end behav;
| gpl-2.0 | 70cb6c7db3194d434514eff17b0017cc | 0.565693 | 3.468354 | false | false | false | false |
nickg/nvc | test/sem/issue356.vhd | 2 | 631 | entity nvc_bug is
end nvc_bug;
architecture behav of nvc_bug is
type std_logic_vector is array (integer range <>) of integer;
function to_bitvector(x : std_logic_vector) return bit_vector;
signal mode : std_logic_vector(1 downto 0);
begin
process
begin
--nvc doesn't like the to_bitvector() below, fails in analysis.
case to_bitvector(mode) is
when "00" =>
when "01" =>
when "10" =>
when "11" =>
when others =>
end case;
assert false report "end of test" severity note;
wait;
end process;
end behav;
| gpl-3.0 | a0cdd8994f3baded1b4d92235adbb996 | 0.575277 | 3.993671 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue615/repr.vhdl | 1 | 311 | library ieee;
use ieee.std_logic_1164.all;
entity repr is
end entity;
architecture arch of repr is
constant CYCLE : time := 10 ns;
signal vec1 : std_logic_vector(31 downto 0);
signal vec2 : std_logic_vector(31 to 0);
begin
vec1 <= (others => '0');
vec2 <= (others => '0');
end arch;
| gpl-2.0 | a866232e95ad1f6323d0349e66202d85 | 0.62701 | 2.990385 | false | false | false | false |
nickg/nvc | test/regress/signal11.vhd | 1 | 1,104 | package pack is
signal x, y : integer := 0;
procedure inc(signal s : out integer);
end package;
package body pack is
procedure inc(signal s : out integer) is
begin
s <= x + 1;
end procedure;
procedure bar(signal s : in integer) is
begin
end procedure;
procedure foo is
begin
bar(x);
end procedure;
end package body;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
end entity;
architecture test of sub is
begin
process is
begin
report x'path_name;
report x'instance_name;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity signal11 is
end entity;
use work.pack.all;
architecture test of signal11 is
begin
process is
begin
assert x = 0;
inc(x);
wait for 1 ns;
assert x = 1;
wait for 1 ns;
assert y = 2;
wait;
end process;
y <= x + 1;
sub_i: entity work.sub;
end architecture;
| gpl-3.0 | cdbaeb4e7f1a8b86e7281306020f38e6 | 0.501812 | 4.246154 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug040/huff_make_dhuff_tb_dc_huffcode.vhd | 2 | 1,519 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity huff_make_dhuff_tb_dc_huffcode is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(8 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end huff_make_dhuff_tb_dc_huffcode;
architecture augh of huff_make_dhuff_tb_dc_huffcode is
-- Embedded RAM
type ram_type is array (0 to 256) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 257 else (others => '-');
end architecture;
| gpl-2.0 | 1de3f3c3c0960d54126150d34e21029c | 0.676103 | 2.893333 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug037/arith.pkg.vhdl | 2 | 5,838 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: VHDL package for component declarations, types and functions
-- associated to the PoC.arith namespace
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
package arith is
component arith_firstone is
generic (
N : positive -- Length of Token Chain
);
port (
tin : in std_logic := '1'; -- Enable: Fed Token
rqst : in std_logic_vector(N-1 downto 0); -- Request: Token Requests
grnt : out std_logic_vector(N-1 downto 0); -- Grant: Token Output
tout : out std_logic; -- Inactive: Unused Token
bin : out std_logic_vector(log2ceil(N)-1 downto 0) -- Binary Grant Index
);
end component;
component arith_counter_bcd is
generic (
DIGITS : positive);
port (
clk : in std_logic;
rst : in std_logic;
inc : in std_logic;
val : out T_BCD_VECTOR(DIGITS-1 downto 0));
end component;
component arith_counter_gray is
generic (
BITS : positive; -- Bit width of the counter
INIT : natural := 0 -- Initial/reset counter value
);
port (
clk : in std_logic;
rst : in std_logic; -- Reset to INIT value
inc : in std_logic; -- Increment
dec : in std_logic := '0'; -- Decrement
val : out std_logic_vector(BITS-1 downto 0); -- Value output
cry : out std_logic -- Carry output
);
end component;
component arith_div
generic (
N : positive;
RAPOW : positive;
REGISTERED : boolean);
port (
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
rdy : out std_logic;
arg1, arg2 : in std_logic_vector(N-1 downto 0);
res : out std_logic_vector(N-1 downto 0));
end component;
component arith_div_pipelined
generic (
DIVIDEND_BITS : POSITIVE;
DIVISOR_BITS : POSITIVE;
RADIX : POSITIVE
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
Enable : in STD_LOGIC;
Dividend : in STD_LOGIC_VECTOR(DIVIDEND_BITS - 1 downto 0);
Divisor : in STD_LOGIC_VECTOR(DIVISOR_BITS - 1 downto 0);
Quotient : out STD_LOGIC_VECTOR(DIVIDEND_BITS - 1 downto 0);
Valid : out STD_LOGIC
);
end component;
component arith_prng
generic (
BITS : positive;
SEED : std_logic_vector := "0"
);
port (
clk : in std_logic;
rst : in std_logic;
got : in std_logic;
val : out std_logic_vector(BITS-1 downto 0));
end component;
component arith_muls_wide
generic (
NA : integer range 2 to 18;
NB : integer range 19 to 36;
SPLIT : positive
);
port (
a : in signed(NA-1 downto 0);
b : in signed(NB-1 downto 0);
p : out signed(NA+NB-1 downto 0)
);
end component;
component arith_sqrt
generic (
N : positive
);
port (
rst : in std_logic;
clk : in std_logic;
arg : in std_logic_vector(N-1 downto 0);
start : in std_logic;
sqrt : out std_logic_vector((N-1)/2 downto 0);
rdy : out std_logic
);
end component;
type tArch is (AAM, CAI, CCA, PAI);
type tBlocking is (DFLT, FIX, ASC, DESC);
type tSkipping is (PLAIN, CCC, PPN_KS, PPN_BK);
component arith_addw is
generic (
N : positive; -- Operand Width
K : positive; -- Block Count
ARCH : tArch := AAM; -- Architecture
BLOCKING : tBlocking := DFLT; -- Blocking Scheme
SKIPPING : tSkipping := CCC; -- Carry Skip Scheme
P_INCLUSIVE : boolean := false -- Use Inclusive Propagate, i.e. c^1
);
port (
a, b : in std_logic_vector(N-1 downto 0);
cin : in std_logic;
s : out std_logic_vector(N-1 downto 0);
cout : out std_logic
);
end component;
component arith_same is
generic (
N : positive -- Input width
);
port (
g : in std_logic := '1'; -- Guard Input (!g => !y)
x : in std_logic_vector(N-1 downto 0); -- Input Vector
y : out std_logic -- All-same Output
);
end component;
component arith_inc_ovcy_xilinx is
generic (
N : positive -- Bit Width
);
port (
p : in std_logic_vector(N-1 downto 0); -- Argument
g : in std_logic; -- Increment Guard
v : out std_logic -- Overflow Output
);
end component;
end package;
| gpl-2.0 | 7bc28ee429e774d651c682bfac471182 | 0.556184 | 3.115261 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_addr_cntl.vhd | 7 | 41,879 | ----------------------------------------------------------------------------
-- axi_sg_addr_cntl.vhd
----------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_addr_cntl.vhd
--
-- Description:
-- This file implements the axi_sg Master Address Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_2;
Use axi_sg_v4_1_2.axi_sg_fifo;
-------------------------------------------------------------------------------
entity axi_sg_addr_cntl is
generic (
C_ADDR_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- sets the depth of the Command Queue FIFO
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the address bus width
C_ADDR_ID : Integer range 0 to 255 := 0;
-- Sets the value to be on the AxID output
C_ADDR_ID_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the AxID output
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Command Tag field width
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family
);
port (
-- Clock input ---------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------
-- AXI Address Channel I/O --------------------------------------------
addr2axi_aid : out std_logic_vector(C_ADDR_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
addr2axi_aaddr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
addr2axi_alen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
addr2axi_asize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
addr2axi_aburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_acache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_auser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_aprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
addr2axi_avalid : out std_logic; --
-- AXI Address Channel VALID output --
--
axi2addr_aready : in std_logic; --
-- AXI Address Channel READY input --
------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- Command Calculation Interface -----------------------------------------
mstr2addr_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : In std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : In std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
-- Sized to support 256 data beat bursts --
--
mstr2addr_size : In std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : In std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : In std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : In std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : In std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2addr_cmd_valid : in std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : out std_logic; --
-- Indication to the Command Calculator that the --
-- command is being accepted --
--------------------------------------------------------------------------
-- Halted Indication to Reset Module ------------------------------
addr2rst_stop_cmplt : out std_logic; --
-- Output flag indicating the address controller has stopped --
-- posting commands to the Address Channel due to a stop --
-- request vai the data2addr_stop_req input port --
------------------------------------------------------------------
-- Address Generation Control ---------------------------------------
allow_addr_req : in std_logic; --
-- Input used to enable/stall the posting of address requests. --
-- 0 = stall address request generation. --
-- 1 = Enable Address request geneartion --
--
addr_req_posted : out std_logic; --
-- Indication from the Address Channel Controller to external --
-- User logic that an address has been posted to the --
-- AXI Address Channel. --
---------------------------------------------------------------------
-- Data Channel Interface ---------------------------------------------
addr2data_addr_posted : Out std_logic; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel. --
--
data2addr_data_rdy : In std_logic; --
-- Indication that the Data Channel is ready to send the first --
-- databeat of the next command on the write data channel. --
-- This is used for the "wait for data" feature which keeps the --
-- address controller from issuing a transfer requset until the --
-- corresponding data is ready. This is expected to be held in --
-- the asserted state until the addr2data_addr_posted signal is --
-- asserted. --
--
data2addr_stop_req : In std_logic; --
-- Indication that the Data Channel has encountered an error --
-- or a soft shutdown request and needs the Address Controller --
-- to stop posting commands to the AXI Address channel --
-----------------------------------------------------------------------
-- Status Module Interface ---------------------------------------
addr2stat_calc_error : out std_logic; --
-- Indication to the Status Module that the Addr Cntl FIFO --
-- is loaded with a Calc error --
--
addr2stat_cmd_fifo_empty : out std_logic --
-- Indication to the Status Module that the Addr Cntl FIFO --
-- is empty --
------------------------------------------------------------------
);
end entity axi_sg_addr_cntl;
architecture implementation of axi_sg_addr_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Constant Declarations --------------------------------------------
Constant APROT_VALUE : std_logic_vector(2 downto 0) := (others => '0');
--'0' & -- bit 2, Normal Access
--'0' & -- bit 1, Nonsecure Access
--'0'; -- bit 0, Data Access
Constant LEN_WIDTH : integer := 8;
Constant SIZE_WIDTH : integer := 3;
Constant BURST_WIDTH : integer := 2;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant CALC_ERROR_WIDTH : integer := 1;
Constant ADDR_QUAL_WIDTH : integer := C_TAG_WIDTH + -- Cmd Tag field width
C_ADDR_WIDTH + -- Cmd Address field width
LEN_WIDTH + -- Cmd Len field width
SIZE_WIDTH + -- Cmd Size field width
BURST_WIDTH + -- Cmd Burst field width
CMD_CMPLT_WIDTH + -- Cmd Cmplt filed width
CALC_ERROR_WIDTH + -- Cmd Calc Error flag
8; -- Cmd Cache, user fields
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
-- Signal Declarations --------------------------------------------
signal sig_axi_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_axi_alen : std_logic_vector(7 downto 0) := (others => '0');
signal sig_axi_asize : std_logic_vector(2 downto 0) := (others => '0');
signal sig_axi_aburst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_axi_acache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_axi_auser : std_logic_vector(3 downto 0) := (others => '0');
signal sig_axi_avalid : std_logic := '0';
signal sig_axi_aready : std_logic := '0';
signal sig_addr_posted : std_logic := '0';
signal sig_calc_error : std_logic := '0';
signal sig_cmd_fifo_empty : std_logic := '0';
Signal sig_aq_fifo_data_in : std_logic_vector(ADDR_QUAL_WIDTH-1 downto 0) := (others => '0');
Signal sig_aq_fifo_data_out : std_logic_vector(ADDR_QUAL_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_fifo_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_fifo_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_fifo_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_fifo_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_calc_error : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len_reg : std_logic_vector(7 downto 0) := (others => '0');
signal sig_next_size_reg : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst_reg : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache_reg : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user_reg : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_addr_valid_reg : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_pop_addr_reg : std_logic := '0';
signal sig_push_addr_reg : std_logic := '0';
signal sig_addr_reg_empty : std_logic := '0';
signal sig_addr_reg_full : std_logic := '0';
signal sig_posted_to_axi : std_logic := '0';
-- obsoleted signal sig_set_wfd_flop : std_logic := '0';
-- obsoleted signal sig_clr_wfd_flop : std_logic := '0';
-- obsoleted signal sig_wait_for_data : std_logic := '0';
-- obsoleted signal sig_data2addr_data_rdy_reg : std_logic := '0';
signal sig_allow_addr_req : std_logic := '0';
signal sig_posted_to_axi_2 : std_logic := '0';
signal new_cmd_in : std_logic;
signal first_addr_valid : std_logic;
signal first_addr_valid_del : std_logic;
signal first_addr_int : std_logic_vector (C_ADDR_WIDTH-1 downto 0);
signal last_addr_int : std_logic_vector (C_ADDR_WIDTH-1 downto 0);
signal addr2axi_cache_int : std_logic_vector (7 downto 0);
signal addr2axi_cache_int1 : std_logic_vector (7 downto 0);
signal last_one : std_logic;
signal latch : std_logic;
signal first_one : std_logic;
signal latch_n : std_logic;
signal latch_n_del : std_logic;
signal mstr2addr_cache_info_int : std_logic_vector (7 downto 0);
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_posted_to_axi : signal is "TRUE"; -- definition
Attribute KEEP of sig_posted_to_axi_2 : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_posted_to_axi : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_posted_to_axi_2 : signal is "no";
begin --(architecture implementation)
-- AXI I/O Port assignments
addr2axi_aid <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_ADDR_ID, C_ADDR_ID_WIDTH));
addr2axi_aaddr <= sig_axi_addr ;
addr2axi_alen <= sig_axi_alen ;
addr2axi_asize <= sig_axi_asize ;
addr2axi_aburst <= sig_axi_aburst;
addr2axi_acache <= sig_axi_acache;
addr2axi_auser <= sig_axi_auser;
addr2axi_aprot <= APROT_VALUE ;
addr2axi_avalid <= sig_axi_avalid;
sig_axi_aready <= axi2addr_aready;
-- Command Calculator Handshake output
sig_fifo_wr_cmd_valid <= mstr2addr_cmd_valid ;
addr2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
-- Data Channel Controller synchro pulse output
addr2data_addr_posted <= sig_addr_posted;
-- Status Module Interface outputs
addr2stat_calc_error <= sig_calc_error ;
addr2stat_cmd_fifo_empty <= sig_addr_reg_empty and
sig_cmd_fifo_empty;
-- Flag Indicating the Address Controller has completed a Stop
addr2rst_stop_cmplt <= (data2addr_stop_req and -- normal shutdown case
sig_addr_reg_empty) or
(data2addr_stop_req and -- shutdown after error trap
sig_calc_error);
-- Assign the address posting control and status
sig_allow_addr_req <= allow_addr_req ;
addr_req_posted <= sig_posted_to_axi_2 ;
-- Internal logic ------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_FIFO
--
-- If Generate Description:
-- Implements the case where the cmd qualifier depth is
-- greater than 1.
--
------------------------------------------------------------
-- GEN_ADDR_FIFO : if (C_ADDR_FIFO_DEPTH > 1) generate
--
-- begin
--
-- -- Format the input FIFO data word
--
-- sig_aq_fifo_data_in <= mstr2addr_cache &
-- mstr2addr_user &
-- mstr2addr_calc_error &
-- mstr2addr_cmd_cmplt &
-- mstr2addr_burst &
-- mstr2addr_size &
-- mstr2addr_len &
-- mstr2addr_addr &
-- mstr2addr_tag ;
--
--
--
-- -- Rip fields from FIFO output data word
-- sig_fifo_next_cache <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH +
-- CMD_CMPLT_WIDTH +
-- CALC_ERROR_WIDTH + 7)
-- downto
-- (C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH +
-- CMD_CMPLT_WIDTH +
-- CALC_ERROR_WIDTH + 4)
-- );
--
-- sig_fifo_next_user <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH +
-- CMD_CMPLT_WIDTH +
-- CALC_ERROR_WIDTH + 3)
-- downto
-- (C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH +
-- CMD_CMPLT_WIDTH +
-- CALC_ERROR_WIDTH)
-- );
--
--
-- sig_fifo_calc_error <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH +
-- CMD_CMPLT_WIDTH +
-- CALC_ERROR_WIDTH)-1);
--
--
-- sig_fifo_next_cmd_cmplt <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH +
-- CMD_CMPLT_WIDTH)-1);
--
--
-- sig_fifo_next_burst <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH)-1
-- downto
-- C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH) ;
--
-- sig_fifo_next_size <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH)-1
-- downto
-- C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH) ;
--
-- sig_fifo_next_len <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH)-1
-- downto
-- C_ADDR_WIDTH +
-- C_TAG_WIDTH) ;
--
-- sig_fifo_next_addr <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH)-1
-- downto
-- C_TAG_WIDTH) ;
--
-- sig_fifo_next_tag <= sig_aq_fifo_data_out(C_TAG_WIDTH-1 downto 0);
--
--
--
-- ------------------------------------------------------------
-- -- Instance: I_ADDR_QUAL_FIFO
-- --
-- -- Description:
-- -- Instance for the Address/Qualifier FIFO
-- --
-- ------------------------------------------------------------
-- I_ADDR_QUAL_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
-- generic map (
--
-- C_DWIDTH => ADDR_QUAL_WIDTH ,
-- C_DEPTH => C_ADDR_FIFO_DEPTH ,
-- C_IS_ASYNC => USE_SYNC_FIFO ,
-- C_PRIM_TYPE => FIFO_PRIM_TYPE ,
-- C_FAMILY => C_FAMILY
--
-- )
-- port map (
--
-- -- Write Clock and reset
-- fifo_wr_reset => mmap_reset ,
-- fifo_wr_clk => primary_aclk ,
--
-- -- Write Side
-- fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
-- fifo_wr_tready => sig_fifo_wr_cmd_ready ,
-- fifo_wr_tdata => sig_aq_fifo_data_in ,
-- fifo_wr_full => open ,
--
--
-- -- Read Clock and reset
-- fifo_async_rd_reset => mmap_reset ,
-- fifo_async_rd_clk => primary_aclk ,
--
-- -- Read Side
-- fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
-- fifo_rd_tready => sig_fifo_rd_cmd_ready ,
-- fifo_rd_tdata => sig_aq_fifo_data_out ,
-- fifo_rd_empty => sig_cmd_fifo_empty
--
-- );
--
--
--
-- end generate GEN_ADDR_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_ADDR_FIFO
--
-- If Generate Description:
-- Implements the case where no additional FIFOing is needed
-- on the input command address/qualifiers.
--
------------------------------------------------------------
GEN_NO_ADDR_FIFO : if (C_ADDR_FIFO_DEPTH = 1) generate
begin
-- Bypass FIFO
sig_fifo_next_tag <= mstr2addr_tag ;
sig_fifo_next_addr <= mstr2addr_addr ;
sig_fifo_next_len <= mstr2addr_len ;
sig_fifo_next_size <= mstr2addr_size ;
sig_fifo_next_burst <= mstr2addr_burst ;
sig_fifo_next_cache <= mstr2addr_cache ;
sig_fifo_next_user <= mstr2addr_user ;
sig_fifo_next_cmd_cmplt <= mstr2addr_cmd_cmplt ;
sig_fifo_calc_error <= mstr2addr_calc_error ;
sig_cmd_fifo_empty <= sig_addr_reg_empty ;
sig_fifo_wr_cmd_ready <= sig_fifo_rd_cmd_ready ;
sig_fifo_rd_cmd_valid <= sig_fifo_wr_cmd_valid ;
end generate GEN_NO_ADDR_FIFO;
-- Output Register Logic -------------------------------------------
sig_axi_addr <= sig_next_addr_reg ;
sig_axi_alen <= sig_next_len_reg ;
sig_axi_asize <= sig_next_size_reg ;
sig_axi_aburst <= sig_next_burst_reg ;
sig_axi_acache <= sig_next_cache_reg ;
sig_axi_auser <= sig_next_user_reg ;
sig_axi_avalid <= sig_addr_valid_reg ;
sig_calc_error <= sig_calc_error_reg ;
sig_fifo_rd_cmd_ready <= sig_addr_reg_empty and
sig_allow_addr_req and
-- obsoleted not(sig_wait_for_data) and
not(data2addr_stop_req);
sig_addr_posted <= sig_posted_to_axi ;
-- Internal signals
sig_push_addr_reg <= sig_addr_reg_empty and
sig_fifo_rd_cmd_valid and
sig_allow_addr_req and
-- obsoleted not(sig_wait_for_data) and
not(data2addr_stop_req);
sig_pop_addr_reg <= not(sig_calc_error_reg) and
sig_axi_aready and
sig_addr_reg_full;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_FIFO_REG
--
-- Process Description:
-- This process implements a register for the Address
-- Control FIFO that operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_ADDR_FIFO_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_addr_reg = '1') then
sig_next_tag_reg <= (others => '0') ;
sig_next_addr_reg <= (others => '0') ;
sig_next_len_reg <= (others => '0') ;
sig_next_size_reg <= (others => '0') ;
sig_next_burst_reg <= (others => '0') ;
sig_next_cache_reg <= (others => '0') ;
sig_next_user_reg <= (others => '0') ;
sig_next_cmd_cmplt_reg <= '0' ;
sig_addr_valid_reg <= '0' ;
sig_calc_error_reg <= '0' ;
sig_addr_reg_empty <= '1' ;
sig_addr_reg_full <= '0' ;
elsif (sig_push_addr_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_addr_reg <= sig_fifo_next_addr ;
sig_next_len_reg <= sig_fifo_next_len ;
sig_next_size_reg <= sig_fifo_next_size ;
sig_next_burst_reg <= sig_fifo_next_burst ;
sig_next_cache_reg <= sig_fifo_next_cache ;
sig_next_user_reg <= sig_fifo_next_user ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_addr_valid_reg <= not(sig_fifo_calc_error);
sig_calc_error_reg <= sig_fifo_calc_error ;
sig_addr_reg_empty <= '0' ;
sig_addr_reg_full <= '1' ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_FIFO_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_POSTED_FLAG
--
-- Process Description:
-- This implements a FLOP that creates a 1 clock wide pulse
-- indicating a new address/qualifier set has been posted to
-- the AXI Addres Channel outputs. This is used to synchronize
-- the Data Channel Controller.
--
-------------------------------------------------------------
IMP_POSTED_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_posted_to_axi <= '0';
sig_posted_to_axi_2 <= '0';
elsif (sig_push_addr_reg = '1') then
sig_posted_to_axi <= '1';
sig_posted_to_axi_2 <= '1';
else
sig_posted_to_axi <= '0';
sig_posted_to_axi_2 <= '0';
end if;
end if;
end process IMP_POSTED_FLAG;
-- PROC_CMD_DETECT : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- first_addr_valid_del <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- first_addr_valid_del <= first_addr_valid;
-- end if;
-- end process PROC_CMD_DETECT;
--
-- PROC_ADDR_DET : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- first_addr_valid <= '0';
-- first_addr_int <= (others => '0');
-- last_addr_int <= (others => '0');
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- if (mstr2addr_cmd_valid = '1' and first_addr_valid = '0') then
-- first_addr_valid <= '1';
-- first_addr_int <= mstr2addr_addr;
-- last_addr_int <= last_addr_int;
-- elsif (mstr2addr_cmd_cmplt = '1') then
-- first_addr_valid <= '0';
-- first_addr_int <= first_addr_int;
-- last_addr_int <= mstr2addr_addr;
-- end if;
-- end if;
-- end process PROC_ADDR_DET;
--
-- latch <= first_addr_valid and (not first_addr_valid_del);
-- latch_n <= (not first_addr_valid) and first_addr_valid_del;
--
-- PROC_CACHE1 : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- mstr2addr_cache_info_int <= (others => '0');
-- latch_n_del <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- if (latch_n = '1') then
-- mstr2addr_cache_info_int <= mstr2addr_cache_info;
-- end if;
-- latch_n_del <= latch_n;
-- end if;
-- end process PROC_CACHE1;
--
--
-- PROC_CACHE : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- addr2axi_cache_int1 <= (others => '0');
-- first_one <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- first_one <= '0';
---- if (latch = '1' and first_one = '0') then -- first one
-- if (sig_addr_valid_reg = '0' and first_addr_valid = '0') then
-- addr2axi_cache_int1 <= mstr2addr_cache_info;
---- first_one <= '1';
---- elsif (latch_n_del = '1') then
---- addr2axi_cache_int <= mstr2addr_cache_info_int;
-- elsif ((first_addr_int = sig_next_addr_reg) and (sig_addr_valid_reg = '1')) then
-- addr2axi_cache_int1 <= addr2axi_cache_int1; --mstr2addr_cache_info (7 downto 4);
-- elsif ((last_addr_int >= sig_next_addr_reg) and (sig_addr_valid_reg = '1')) then
-- addr2axi_cache_int1 <= addr2axi_cache_int1; --mstr2addr_cache_info (7 downto 4);
-- end if;
-- end if;
-- end process PROC_CACHE;
--
--
-- PROC_CACHE2 : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- addr2axi_cache_int <= (others => '0');
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- addr2axi_cache_int <= addr2axi_cache_int1;
-- end if;
-- end process PROC_CACHE2;
--
--addr2axi_cache <= addr2axi_cache_int (3 downto 0);
--addr2axi_user <= addr2axi_cache_int (7 downto 4);
--
end implementation;
| gpl-3.0 | 697f02ca70ba6aac301a5b56658ea982 | 0.389861 | 4.802087 | false | false | false | false |
tgingold/ghdl | testsuite/gna/ticket14/scrambler_tb.vhd | 3 | 885 | library ieee;
use ieee.std_logic_1164.all;
entity scrambler_tb is
end entity scrambler_tb;
architecture behaviour of scrambler_tb is
constant clk_period : time := 10 ns;
signal clk, reset : std_logic;
signal en, seed : std_logic;
signal d_in, d_out : std_logic;
begin
uut: entity work.scrambler
port map (
clk => clk,
reset => reset,
en => en,
seed => seed,
d_in => d_out,
d_out => d_out);
-- Clock process definitions
clk_process: process
begin
for i in 1 to 10 loop
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end loop;
wait;
end process;
-- Stimulus process
stim_proc: process begin
-- Reset period
reset <= '1';
wait for clk_period * 2;
reset <= '0';
wait for clk_period * 3.5;
wait;
end process;
end architecture behaviour;
| gpl-2.0 | 3a80b57bb1b0693ea76ed9f38dbae0ba | 0.59548 | 3.289963 | false | false | false | false |
nickg/nvc | test/sem/record.vhd | 1 | 4,758 | package p is
type r1 is record -- OK
x : integer;
y : integer;
end record;
type r2 is record -- Error
x, x : integer;
end record;
type r3;
type r3 is record -- Error
x : r3;
end record;
type r4 is record
x, y, z : integer;
end record;
type r5 is record
x : r1;
y : integer;
end record;
type r1_vec is array (integer range <>) of r1;
type r6 is record
x : r1_vec; -- Error
end record;
end package;
package body p is
procedure p1 is
variable v1 : r1 := (1, 2); -- OK
variable v2 : r4 := (1, 2); -- Error
variable v3 : r1 := (1, v1); -- Error
variable v4 : r1 := (x => 1, y => 2); -- OK
variable v5 : r1 := (x => 1); -- Error
variable v6 : r1 := (x => 1, y => 2, q => 1); -- Error
variable v7 : r1 := (x => 1, y => v1); -- Error
variable v8 : r1 := (others => 9); -- OK
variable v9 : r1 := (x => 1, others => 2);
variable v10 : r1 := (x => 1, x => 2, y => 3); -- Error
variable v11 : r1 := (1, x => 4, y => 2); -- Error
variable v12 : r1 := (1, y => 4); -- OK
variable v13 : r1;
begin
end procedure;
procedure p2 is
variable v1 : r1;
variable v2 : r5;
begin
v1.x := 2;
v1.y := v1.x + 5;
v2.x.x := 3;
end procedure;
procedure p3 is
variable a1 : r1_vec; -- Error
begin
end procedure;
procedure p4 is
variable a2 : r1_vec(0 to 3); -- OK
begin
a2(2).x := 5; -- OK
a2(1).f := 2; -- Error
a2(0).x := a2(1).y; -- OK
end procedure;
procedure p5 is
subtype r1_sub is r1; -- OK
variable a : r1_sub; -- OK
begin
a.x := 5; -- OK
a.y := a.x + 2; -- OK
a.z := 2; -- Error
end procedure;
procedure p6 is
subtype r1_bad is r1(1 to 3); -- Error
begin
end procedure;
procedure p7 is
type rec is record
vec : bit_vector(1 to 3);
end record;
variable a : rec;
begin
assert a.vec'length = 3; -- OK
end procedure;
procedure p8 is
function make_r1 return r1 is
begin
return (x => 1, y => 2); -- OK
end function;
begin
assert make_r1.x = 1; -- OK
assert make_r1.z = 2; -- Error
end procedure;
type int_file is file of integer;
type r7 is record
a : int_file;
end record;
type r8 is record
a : integer range 1 to 10;
end record;
procedure p9 is
variable x : r8; -- OK
begin
end procedure;
procedure p10 is
variable x : r8 := (ack => '1'); -- Error
begin
end procedure;
type line is access string;
-- Copied from incorrect code in std.textio
procedure read (l : inout line;
value : out time;
good : out boolean ) is
type unit_spec_t is record
name : string(1 to 3);
length : positive;
unit : time;
end record;
type unit_map_t is array (natural range <>) of unit_spec_t;
constant unit_map : unit_spec_t := (
( "fs ", 2, fs ) );
variable scale, len : integer;
variable scale_good : boolean;
begin
good := false;
if not scale_good then
return;
end if;
for i in 0 to 0 loop
len := unit_map(i).length; -- Error
if l'length > len
and l.all(1 to len) = unit_map(i).name(1 to len)
then
value := scale * unit_map(i).unit;
good := true;
end if;
end loop;
end procedure;
procedure aggregates is
variable r : r1;
begin
r := (1 => 1); -- Error
r := (1, 2, 3); -- Error
r := (1, 2, others => 3); -- Error
r := (x to y => 4); -- Error
r := (x to z => 2); -- Error
end procedure;
procedure test1 is
variable r : foo; -- Error
begin
r.baz := 1; -- Error
end procedure;
procedure test2 is
procedure sub (x : integer) is
begin
end procedure;
begin
sub(x.z => 2); -- Error
end procedure;
end package body;
| gpl-3.0 | dd9a3239dad9fd6e7d1c38ad7f1226ab | 0.430223 | 3.758294 | false | false | false | false |
nickg/nvc | test/regress/wait21.vhd | 1 | 2,208 | package pack is
alias resolved_max is maximum [integer_vector return integer] ;
--function resolved_max (i : integer_vector) return integer;
subtype RdyType is resolved_max integer range 0 to integer'high ;
subtype AckType is resolved_max integer range -1 to integer'high ;
procedure request(signal rdy : inout RdyType;
signal ack : in AckType);
procedure wait_for(signal ack : inout AckType;
signal rdy : in RdyType);
type ctl_t is record
rdy : RdyType;
ack : AckType;
end record;
end package;
package body pack is
-- function resolved_max (i : integer_vector) return integer is
-- begin
-- return maximum(i);
-- end function;
procedure request(signal rdy : inout RdyType;
signal ack : in AckType) is
begin
rdy <= rdy + 1;
wait for 0 ns;
wait until rdy = ack;
end procedure;
procedure wait_for(signal ack : inout AckType;
signal rdy : in RdyType) is
begin
ack <= ack + 1;
wait until ack /= rdy;
end procedure;
end package body;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port ( ctl : inout ctl_t );
end entity;
architecture test of sub is
begin
p1: process is
begin
wait for 5 ns;
wait_for(ctl.ack, ctl.rdy);
report "processing in p2";
wait for 12 ns;
end process;
end architecture;
-------------------------------------------------------------------------------
use work.pack.all;
entity wait21 is
end entity;
architecture test of wait21 is
signal ctl : ctl_t;
signal done : boolean := false;
begin
uut: entity work.sub port map (ctl);
p2: process is
begin
request(ctl.rdy, ctl.ack);
assert now = 22 ns;
report "acked request";
wait for 2 ns;
request(ctl.rdy, ctl.ack);
assert now = 41 ns;
done <= true;
wait;
end process;
p3: process is
begin
wait for 1 hr;
assert done = true;
wait;
end process;
end architecture;
| gpl-3.0 | c25c4fdddbe84f38182a7e5a3c58413d | 0.543025 | 4.254335 | false | false | false | false |
tgingold/ghdl | libraries/ieee/std_logic_1164-body.vhdl | 2 | 32,260 | -- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Standard multivalue logic package
-- : (STD_LOGIC_1164 package body)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE model standards group (PAR 1164),
-- : Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines a standard for designers
-- : to use in describing the interconnection data types
-- : used in vhdl modeling.
-- :
-- Limitation: The logic system defined in this package may
-- : be insufficient for modeling switched transistors,
-- : since such a requirement is out of the scope of this
-- : effort. Furthermore, mathematics, primitives,
-- : timing standards, etc. are considered orthogonal
-- : issues as it relates to this package and are therefore
-- : beyond the scope of this effort.
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
package body std_logic_1164 is
-------------------------------------------------------------------
-- local types
-------------------------------------------------------------------
type stdlogic_1d is array (STD_ULOGIC) of STD_ULOGIC;
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
constant resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | X |
('U', 'X', '0', 'X', '0', '0', '0', '0', 'X'), -- | 0 |
('U', 'X', 'X', '1', '1', '1', '1', '1', 'X'), -- | 1 |
('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X'), -- | Z |
('U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X'), -- | W |
('U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X'), -- | L |
('U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X'), -- | H |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X') -- | - |
);
function resolved (s : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := 'Z'; -- weakest state default
begin
-- the test for a single driver is essential otherwise the
-- loop would return 'X' for a single driver of '-' and that
-- would conflict with the value of a single driver unresolved
-- signal.
if (s'length = 1) then return s(s'low);
else
for i in s'range loop
result := resolution_table(result, s(i));
end loop;
end if;
return result;
end resolved;
-------------------------------------------------------------------
-- tables for logical operations
-------------------------------------------------------------------
-- truth table for "and" function
constant and_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
('U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U'), -- | U |
('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X'), -- | X |
('0', '0', '0', '0', '0', '0', '0', '0', '0'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | 1 |
('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X'), -- | Z |
('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X'), -- | W |
('0', '0', '0', '0', '0', '0', '0', '0', '0'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | H |
('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X') -- | - |
);
-- truth table for "or" function
constant or_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
('U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U'), -- | U |
('U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | 0 |
('1', '1', '1', '1', '1', '1', '1', '1', '1'), -- | 1 |
('U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X'), -- | Z |
('U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | L |
('1', '1', '1', '1', '1', '1', '1', '1', '1'), -- | H |
('U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X') -- | - |
);
-- truth table for "xor" function
constant xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | 0 |
('U', 'X', '1', '0', 'X', 'X', '1', '0', 'X'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | L |
('U', 'X', '1', '0', 'X', 'X', '1', '0', 'X'), -- | H |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X') -- | - |
);
-- truth table for "not" function
constant not_table : stdlogic_1d :=
-- -------------------------------------------------
-- | U X 0 1 Z W L H - |
-- -------------------------------------------------
('U', 'X', '1', '0', 'X', 'X', '1', '0', 'X');
-------------------------------------------------------------------
-- overloaded logical operators ( with optimizing hints )
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is
begin
return (and_table(l, r));
end "and";
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is
begin
return (not_table (and_table(l, r)));
end "nand";
function "or" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is
begin
return (or_table(l, r));
end "or";
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is
begin
return (not_table (or_table(l, r)));
end "nor";
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is
begin
return (xor_table(l, r));
end "xor";
--START-!V87
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is
begin
return not_table(xor_table(l, r));
end "xnor";
--END-!V87
function "not" (l : STD_ULOGIC) return UX01 is
begin
return (not_table(l));
end "not";
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function "and" (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""and"": "
& "arguments of overloaded 'and' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := and_table (lv(i), rv(i));
end loop;
end if;
return result;
end "and";
function "and" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""and"": "
& "arguments of overloaded 'and' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := and_table (lv(i), rv(i));
end loop;
end if;
return result;
end "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function "nand" (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""nand"": "
& "arguments of overloaded 'nand' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := not_table(and_table (lv(i), rv(i)));
end loop;
end if;
return result;
end "nand";
function "nand" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""nand"": "
& "arguments of overloaded 'nand' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := not_table(and_table (lv(i), rv(i)));
end loop;
end if;
return result;
end "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function "or" (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""or"": "
& "arguments of overloaded 'or' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := or_table (lv(i), rv(i));
end loop;
end if;
return result;
end "or";
function "or" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""or"": "
& "arguments of overloaded 'or' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := or_table (lv(i), rv(i));
end loop;
end if;
return result;
end "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function "nor" (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""nor"": "
& "arguments of overloaded 'nor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := not_table(or_table (lv(i), rv(i)));
end loop;
end if;
return result;
end "nor";
function "nor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""nor"": "
& "arguments of overloaded 'nor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := not_table(or_table (lv(i), rv(i)));
end loop;
end if;
return result;
end "nor";
---------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function "xor" (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""xor"": "
& "arguments of overloaded 'xor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := xor_table (lv(i), rv(i));
end loop;
end if;
return result;
end "xor";
function "xor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""xor"": "
& "arguments of overloaded 'xor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := xor_table (lv(i), rv(i));
end loop;
end if;
return result;
end "xor";
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
--START-!V87
function "xnor" (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""xnor"": "
& "arguments of overloaded 'xnor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := not_table(xor_table (lv(i), rv(i)));
end loop;
end if;
return result;
end "xnor";
function "xnor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""xnor"": "
& "arguments of overloaded 'xnor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := not_table(xor_table (lv(i), rv(i)));
end loop;
end if;
return result;
end "xnor";
--END-!V87
-------------------------------------------------------------------
-- not
-------------------------------------------------------------------
function "not" (l : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => 'X');
begin
for i in result'range loop
result(i) := not_table(lv(i));
end loop;
return result;
end "not";
function "not" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => 'X');
begin
for i in result'range loop
result(i) := not_table(lv(i));
end loop;
return result;
end "not";
-------------------------------------------------------------------
-- conversion tables
-------------------------------------------------------------------
type logic_x01_table is array (STD_ULOGIC'low to STD_ULOGIC'high) of X01;
type logic_x01z_table is array (STD_ULOGIC'low to STD_ULOGIC'high) of X01Z;
type logic_ux01_table is array (STD_ULOGIC'low to STD_ULOGIC'high) of UX01;
----------------------------------------------------------
-- table name : cvt_to_x01
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : x01 -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_x01 (input_signal) = '1' ) then ...
--
----------------------------------------------------------
constant cvt_to_x01 : logic_x01_table := (
'X', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'X', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
----------------------------------------------------------
-- table name : cvt_to_x01z
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : x01z -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_x01z (input_signal) = '1' ) then ...
--
----------------------------------------------------------
constant cvt_to_x01z : logic_x01z_table := (
'X', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'Z', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
----------------------------------------------------------
-- table name : cvt_to_ux01
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : ux01 -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_ux01 (input_signal) = '1' ) then ...
--
----------------------------------------------------------
constant cvt_to_ux01 : logic_ux01_table := (
'U', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'X', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
-------------------------------------------------------------------
-- conversion functions
-------------------------------------------------------------------
function To_bit (s : STD_ULOGIC; xmap : BIT := '0') return BIT is
begin
case s is
when '0' | 'L' => return ('0');
when '1' | 'H' => return ('1');
when others => return xmap;
end case;
end To_bit;
--------------------------------------------------------------------
function To_bitvector (s : STD_LOGIC_VECTOR; xmap : BIT := '0')
return BIT_VECTOR
is
alias sv : STD_LOGIC_VECTOR (s'length-1 downto 0) is s;
variable result : BIT_VECTOR (s'length-1 downto 0);
begin
for i in result'range loop
case sv(i) is
when '0' | 'L' => result(i) := '0';
when '1' | 'H' => result(i) := '1';
when others => result(i) := xmap;
end case;
end loop;
return result;
end To_bitvector;
function To_bitvector (s : STD_ULOGIC_VECTOR; xmap : BIT := '0')
return BIT_VECTOR
is
alias sv : STD_ULOGIC_VECTOR (s'length-1 downto 0) is s;
variable result : BIT_VECTOR (s'length-1 downto 0);
begin
for i in result'range loop
case sv(i) is
when '0' | 'L' => result(i) := '0';
when '1' | 'H' => result(i) := '1';
when others => result(i) := xmap;
end case;
end loop;
return result;
end To_bitvector;
--------------------------------------------------------------------
function To_StdULogic (b : BIT) return STD_ULOGIC is
begin
case b is
when '0' => return '0';
when '1' => return '1';
end case;
end To_StdULogic;
--------------------------------------------------------------------
function To_StdLogicVector (b : BIT_VECTOR)
return STD_LOGIC_VECTOR
is
alias bv : BIT_VECTOR (b'length-1 downto 0) is b;
variable result : STD_LOGIC_VECTOR (b'length-1 downto 0);
begin
for i in result'range loop
case bv(i) is
when '0' => result(i) := '0';
when '1' => result(i) := '1';
end case;
end loop;
return result;
end To_StdLogicVector;
--------------------------------------------------------------------
function To_StdLogicVector (s : STD_ULOGIC_VECTOR)
return STD_LOGIC_VECTOR
is
alias sv : STD_ULOGIC_VECTOR (s'length-1 downto 0) is s;
variable result : STD_LOGIC_VECTOR (s'length-1 downto 0);
begin
for i in result'range loop
result(i) := sv(i);
end loop;
return result;
end To_StdLogicVector;
--------------------------------------------------------------------
function To_StdULogicVector (b : BIT_VECTOR)
return STD_ULOGIC_VECTOR
is
alias bv : BIT_VECTOR (b'length-1 downto 0) is b;
variable result : STD_ULOGIC_VECTOR (b'length-1 downto 0);
begin
for i in result'range loop
case bv(i) is
when '0' => result(i) := '0';
when '1' => result(i) := '1';
end case;
end loop;
return result;
end To_StdULogicVector;
--------------------------------------------------------------------
function To_StdULogicVector (s : STD_LOGIC_VECTOR)
return STD_ULOGIC_VECTOR
is
alias sv : STD_LOGIC_VECTOR (s'length-1 downto 0) is s;
variable result : STD_ULOGIC_VECTOR (s'length-1 downto 0);
begin
for i in result'range loop
result(i) := sv(i);
end loop;
return result;
end To_StdULogicVector;
-------------------------------------------------------------------
-- strength strippers and type convertors
-------------------------------------------------------------------
-------------------------------------------------------------------
-- to_x01
-------------------------------------------------------------------
function To_X01 (s : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias sv : STD_LOGIC_VECTOR (1 to s'length) is s;
variable result : STD_LOGIC_VECTOR (1 to s'length);
begin
for i in result'range loop
result(i) := cvt_to_x01 (sv(i));
end loop;
return result;
end To_X01;
function To_X01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias sv : STD_ULOGIC_VECTOR (1 to s'length) is s;
variable result : STD_ULOGIC_VECTOR (1 to s'length);
begin
for i in result'range loop
result(i) := cvt_to_x01 (sv(i));
end loop;
return result;
end To_X01;
--------------------------------------------------------------------
function To_X01 (s : STD_ULOGIC) return X01 is
begin
return (cvt_to_x01(s));
end To_X01;
--------------------------------------------------------------------
function To_X01 (b : BIT_VECTOR) return STD_LOGIC_VECTOR is
alias bv : BIT_VECTOR (1 to b'length) is b;
variable result : STD_LOGIC_VECTOR (1 to b'length);
begin
for i in result'range loop
case bv(i) is
when '0' => result(i) := '0';
when '1' => result(i) := '1';
end case;
end loop;
return result;
end To_X01;
function To_X01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR is
alias bv : BIT_VECTOR (1 to b'length) is b;
variable result : STD_ULOGIC_VECTOR (1 to b'length);
begin
for i in result'range loop
case bv(i) is
when '0' => result(i) := '0';
when '1' => result(i) := '1';
end case;
end loop;
return result;
end To_X01;
--------------------------------------------------------------------
function To_X01 (b : BIT) return X01 is
begin
case b is
when '0' => return('0');
when '1' => return('1');
end case;
end To_X01;
--------------------------------------------------------------------
-- to_x01z
-------------------------------------------------------------------
function To_X01Z (s : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias sv : STD_LOGIC_VECTOR (1 to s'length) is s;
variable result : STD_LOGIC_VECTOR (1 to s'length);
begin
for i in result'range loop
result(i) := cvt_to_x01z (sv(i));
end loop;
return result;
end To_X01Z;
function To_X01Z (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias sv : STD_ULOGIC_VECTOR (1 to s'length) is s;
variable result : STD_ULOGIC_VECTOR (1 to s'length);
begin
for i in result'range loop
result(i) := cvt_to_x01z (sv(i));
end loop;
return result;
end To_X01Z;
--------------------------------------------------------------------
function To_X01Z (s : STD_ULOGIC) return X01Z is
begin
return (cvt_to_x01z(s));
end To_X01Z;
--------------------------------------------------------------------
function To_X01Z (b : BIT_VECTOR) return STD_LOGIC_VECTOR is
alias bv : BIT_VECTOR (1 to b'length) is b;
variable result : STD_LOGIC_VECTOR (1 to b'length);
begin
for i in result'range loop
case bv(i) is
when '0' => result(i) := '0';
when '1' => result(i) := '1';
end case;
end loop;
return result;
end To_X01Z;
function To_X01Z (b : BIT_VECTOR) return STD_ULOGIC_VECTOR is
alias bv : BIT_VECTOR (1 to b'length) is b;
variable result : STD_ULOGIC_VECTOR (1 to b'length);
begin
for i in result'range loop
case bv(i) is
when '0' => result(i) := '0';
when '1' => result(i) := '1';
end case;
end loop;
return result;
end To_X01Z;
--------------------------------------------------------------------
function To_X01Z (b : BIT) return X01Z is
begin
case b is
when '0' => return('0');
when '1' => return('1');
end case;
end To_X01Z;
--------------------------------------------------------------------
-- to_ux01
-------------------------------------------------------------------
function To_UX01 (s : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias sv : STD_LOGIC_VECTOR (1 to s'length) is s;
variable result : STD_LOGIC_VECTOR (1 to s'length);
begin
for i in result'range loop
result(i) := cvt_to_ux01 (sv(i));
end loop;
return result;
end To_UX01;
function To_UX01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias sv : STD_ULOGIC_VECTOR (1 to s'length) is s;
variable result : STD_ULOGIC_VECTOR (1 to s'length);
begin
for i in result'range loop
result(i) := cvt_to_ux01 (sv(i));
end loop;
return result;
end To_UX01;
--------------------------------------------------------------------
function To_UX01 (s : STD_ULOGIC) return UX01 is
begin
return (cvt_to_ux01(s));
end To_UX01;
--------------------------------------------------------------------
function To_UX01 (b : BIT_VECTOR) return STD_LOGIC_VECTOR is
alias bv : BIT_VECTOR (1 to b'length) is b;
variable result : STD_LOGIC_VECTOR (1 to b'length);
begin
for i in result'range loop
case bv(i) is
when '0' => result(i) := '0';
when '1' => result(i) := '1';
end case;
end loop;
return result;
end To_UX01;
function To_UX01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR is
alias bv : BIT_VECTOR (1 to b'length) is b;
variable result : STD_ULOGIC_VECTOR (1 to b'length);
begin
for i in result'range loop
case bv(i) is
when '0' => result(i) := '0';
when '1' => result(i) := '1';
end case;
end loop;
return result;
end To_UX01;
--------------------------------------------------------------------
function To_UX01 (b : BIT) return UX01 is
begin
case b is
when '0' => return('0');
when '1' => return('1');
end case;
end To_UX01;
-------------------------------------------------------------------
-- edge detection
-------------------------------------------------------------------
function rising_edge (signal s : STD_ULOGIC) return BOOLEAN is
begin
return (s'event and (To_X01(s) = '1') and
(To_X01(s'last_value) = '0'));
end rising_edge;
function falling_edge (signal s : STD_ULOGIC) return BOOLEAN is
begin
return (s'event and (To_X01(s) = '0') and
(To_X01(s'last_value) = '1'));
end falling_edge;
-------------------------------------------------------------------
-- object contains an unknown
-------------------------------------------------------------------
function Is_X (s : STD_LOGIC_VECTOR) return BOOLEAN is
begin
for i in s'range loop
case s(i) is
when 'U' | 'X' | 'Z' | 'W' | '-' => return true;
when others => null;
end case;
end loop;
return false;
end Is_X;
function Is_X (s : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
for i in s'range loop
case s(i) is
when 'U' | 'X' | 'Z' | 'W' | '-' => return true;
when others => null;
end case;
end loop;
return false;
end Is_X;
--------------------------------------------------------------------
function Is_X (s : STD_ULOGIC) return BOOLEAN is
begin
case s is
when 'U' | 'X' | 'Z' | 'W' | '-' => return true;
when others => null;
end case;
return false;
end Is_X;
end std_logic_1164;
| gpl-2.0 | 61160b6a03aefa71070d2f186ca6e671 | 0.435524 | 3.785496 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_register.vhd | 3 | 49,418 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_register.vhd
--
-- Description: This entity encompasses the channel register set.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_register is
generic(
C_NUM_REGISTERS : integer := 11 ;
C_INCLUDE_SG : integer := 1 ;
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_MICRO_DMA : integer range 0 to 1 := 0 ;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
--C_CHANNEL_IS_S2MM : integer range 0 to 1 := 0 CR603034
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- AXI Interface Control --
axi2ip_wrce : in std_logic_vector --
(C_NUM_REGISTERS-1 downto 0) ; --
axi2ip_wrdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- DMASR Control --
stop_dma : in std_logic ; --
halted_clr : in std_logic ; --
halted_set : in std_logic ; --
idle_set : in std_logic ; --
idle_clr : in std_logic ; --
ioc_irq_set : in std_logic ; --
dly_irq_set : in std_logic ; --
irqdelay_status : in std_logic_vector(7 downto 0) ; --
irqthresh_status : in std_logic_vector(7 downto 0) ; --
irqthresh_wren : out std_logic ; --
irqdelay_wren : out std_logic ; --
dlyirq_dsble : out std_logic ; -- CR605888
--
-- Error Control --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
ftch_interr_set : in std_logic ; --
ftch_slverr_set : in std_logic ; --
ftch_decerr_set : in std_logic ; --
ftch_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_interr_set : in std_logic ; --
updt_slverr_set : in std_logic ; --
updt_decerr_set : in std_logic ; --
updt_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
error_in : in std_logic ; --
error_out : out std_logic ; --
introut : out std_logic ; --
soft_reset_in : in std_logic ; --
soft_reset_clr : in std_logic ; --
--
-- CURDESC Update --
update_curdesc : in std_logic ; --
new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
-- TAILDESC Update --
tailpntr_updated : out std_logic ; --
--
-- Channel Register Out --
sg_ctl : out std_logic_vector (7 downto 0) ;
dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
buffer_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
buffer_length : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
buffer_length_wren : out std_logic ; --
bytes_received : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
bytes_received_wren : in std_logic --
); --
end axi_dma_register;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_register is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant DMACR_INDEX : integer := 0; -- DMACR Register index
constant DMASR_INDEX : integer := 1; -- DMASR Register index
constant CURDESC_LSB_INDEX : integer := 2; -- CURDESC LSB Reg index
constant CURDESC_MSB_INDEX : integer := 3; -- CURDESC MSB Reg index
constant TAILDESC_LSB_INDEX : integer := 4; -- TAILDESC LSB Reg index
constant TAILDESC_MSB_INDEX : integer := 5; -- TAILDESC MSB Reg index
-- CR603034 moved s2mm back to offset 6
--constant SA_ADDRESS_INDEX : integer := 6; -- Buffer Address Reg (SA)
--constant DA_ADDRESS_INDEX : integer := 8; -- Buffer Address Reg (DA)
--
--
--constant BUFF_ADDRESS_INDEX : integer := address_index_select -- Buffer Address Reg (SA or DA)
-- (C_CHANNEL_IS_S2MM, -- Channel Type 1=rx 0=tx
-- SA_ADDRESS_INDEX, -- Source Address Index
-- DA_ADDRESS_INDEX); -- Destination Address Index
constant BUFF_ADDRESS_INDEX : integer := 6;
constant BUFF_ADDRESS_MSB_INDEX : integer := 7;
constant BUFF_LENGTH_INDEX : integer := 10; -- Buffer Length Reg
constant SGCTL_INDEX : integer := 11; -- Buffer Length Reg
constant ZERO_VALUE : std_logic_vector(31 downto 0) := (others => '0');
constant DMA_CONFIG : std_logic_vector(0 downto 0)
:= std_logic_vector(to_unsigned(C_INCLUDE_SG,1));
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal dmacr_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal dmasr_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 6) := (others => '0');
signal curdesc_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 6) := (others => '0');
signal taildesc_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal buffer_address_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal buffer_address_i_64 : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal buffer_length_i : std_logic_vector
(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
-- DMASR Signals
signal halted : std_logic := '0';
signal idle : std_logic := '0';
signal cmplt : std_logic := '0';
signal error : std_logic := '0';
signal dma_interr : std_logic := '0';
signal dma_slverr : std_logic := '0';
signal dma_decerr : std_logic := '0';
signal sg_interr : std_logic := '0';
signal sg_slverr : std_logic := '0';
signal sg_decerr : std_logic := '0';
signal ioc_irq : std_logic := '0';
signal dly_irq : std_logic := '0';
signal error_d1 : std_logic := '0';
signal error_re : std_logic := '0';
signal err_irq : std_logic := '0';
signal sg_ftch_error : std_logic := '0';
signal sg_updt_error : std_logic := '0';
signal error_pointer_set : std_logic := '0';
-- interrupt coalescing support signals
signal different_delay : std_logic := '0';
signal different_thresh : std_logic := '0';
signal threshold_is_zero : std_logic := '0';
-- soft reset support signals
signal soft_reset_i : std_logic := '0';
signal run_stop_clr : std_logic := '0';
signal sg_cache_info : std_logic_vector (7 downto 0);
signal diff_thresh_xor : std_logic_vector (7 downto 0);
signal sig_cur_updated : std_logic;
signal tmp11 : std_logic;
signal tailpntr_updated_d1 : std_logic;
signal tailpntr_updated_d2 : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
dmacr <= dmacr_i ;
dmasr <= dmasr_i ;
curdesc_lsb <= curdesc_lsb_i (31 downto 6) & "000000" ;
curdesc_msb <= curdesc_msb_i ;
taildesc_lsb <= taildesc_lsb_i (31 downto 6) & "000000" ;
taildesc_msb <= taildesc_msb_i ;
BUFF_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
buffer_address <= buffer_address_i_64 & buffer_address_i ;
end generate BUFF_ADDR_EQL64;
BUFF_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
buffer_address <= buffer_address_i ;
end generate BUFF_ADDR_EQL32;
buffer_length <= buffer_length_i ;
---------------------------------------------------------------------------
-- DMA Control Register
---------------------------------------------------------------------------
-- DMACR - Interrupt Delay Value
-------------------------------------------------------------------------------
DMACR_DELAY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT);
end if;
end if;
end process DMACR_DELAY;
-- If written delay is different than previous value then assert write enable
different_delay <= '1' when dmacr_i(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT)
/= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT)
else '0';
-- delay value different, drive write of delay value to interrupt controller
NEW_DELAY_WRITE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
irqdelay_wren <= '0';
-- If AXI Lite write to DMACR and delay different than current
-- setting then update delay value
elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_delay = '1')then
irqdelay_wren <= '1';
else
irqdelay_wren <= '0';
end if;
end if;
end process NEW_DELAY_WRITE;
-------------------------------------------------------------------------------
-- DMACR - Interrupt Threshold Value
-------------------------------------------------------------------------------
threshold_is_zero <= '1' when axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) = ZERO_THRESHOLD
else '0';
DMACR_THRESH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
-- On AXI Lite write
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
-- If value is 0 then set threshold to 1
if(threshold_is_zero='1')then
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
-- else set threshold to axi lite wrdata value
else
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT);
end if;
end if;
end if;
end process DMACR_THRESH;
--diff_thresh_xor <= dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) xor
-- axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT);
--different_thresh <= '0' when diff_thresh_xor = "00000000"
-- else '1';
-- If written threshold is different than previous value then assert write enable
different_thresh <= '1' when dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT)
/= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT)
else '0';
-- new treshold written therefore drive write of threshold out
NEW_THRESH_WRITE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
irqthresh_wren <= '0';
-- If AXI Lite write to DMACR and threshold different than current
-- setting then update threshold value
elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_thresh = '1')then
irqthresh_wren <= '1';
else
irqthresh_wren <= '0';
end if;
end if;
end process NEW_THRESH_WRITE;
-------------------------------------------------------------------------------
-- DMACR - Remainder of DMA Control Register, Bit 3 for Key hole operation
-------------------------------------------------------------------------------
DMACR_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1
downto DMACR_RESERVED5_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1 -- bit 15
downto DMACR_RESERVED5_BIT) <= ZERO_VALUE(DMACR_RESERVED15_BIT)
-- bit 14
& axi2ip_wrdata(DMACR_ERR_IRQEN_BIT)
-- bit 13
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT)
-- bit 12
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT)
-- bits 11 downto 3
& ZERO_VALUE(DMACR_RESERVED11_BIT downto DMACR_RESERVED5_BIT);
end if;
end if;
end process DMACR_REGISTER;
DMACR_REGISTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or C_ENABLE_MULTI_CHANNEL = 1)then
dmacr_i(DMACR_KH_BIT) <= '0';
dmacr_i(CYCLIC_BIT) <= '0';
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_KH_BIT) <= axi2ip_wrdata(DMACR_KH_BIT);
dmacr_i(CYCLIC_BIT) <= axi2ip_wrdata(CYCLIC_BIT);
end if;
end if;
end process DMACR_REGISTER1;
-------------------------------------------------------------------------------
-- DMACR - Reset Bit
-------------------------------------------------------------------------------
DMACR_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(soft_reset_clr = '1')then
dmacr_i(DMACR_RESET_BIT) <= '0';
-- If soft reset set in other channel then set
-- reset bit here too
elsif(soft_reset_in = '1')then
dmacr_i(DMACR_RESET_BIT) <= '1';
-- If DMACR Write then pass axi lite write bus to DMARC reset bit
elsif(soft_reset_i = '0' and axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_RESET_BIT) <= axi2ip_wrdata(DMACR_RESET_BIT);
end if;
end if;
end process DMACR_RESET;
soft_reset_i <= dmacr_i(DMACR_RESET_BIT);
-------------------------------------------------------------------------------
-- Tail Pointer Enable fixed at 1 for this release of axi dma
-------------------------------------------------------------------------------
dmacr_i(DMACR_TAILPEN_BIT) <= '1';
-------------------------------------------------------------------------------
-- DMACR - Run/Stop Bit
-------------------------------------------------------------------------------
run_stop_clr <= '1' when error = '1' -- MM2S DataMover Error
or error_in = '1' -- S2MM Error
or stop_dma = '1' -- Stop due to error
or soft_reset_i = '1' -- MM2S Soft Reset
or soft_reset_in = '1' -- S2MM Soft Reset
else '0';
DMACR_RUNSTOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_RS_BIT) <= '0';
-- Clear on sg error (i.e. error) or other channel
-- error (i.e. error_in) or dma error or soft reset
elsif(run_stop_clr = '1')then
dmacr_i(DMACR_RS_BIT) <= '0';
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_RS_BIT) <= axi2ip_wrdata(DMACR_RS_BIT);
end if;
end if;
end process DMACR_RUNSTOP;
---------------------------------------------------------------------------
-- DMA Status Halted bit (BIT 0) - Set by dma controller indicating DMA
-- channel is halted.
---------------------------------------------------------------------------
DMASR_HALTED : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or halted_set = '1')then
halted <= '1';
elsif(halted_clr = '1')then
halted <= '0';
end if;
end if;
end process DMASR_HALTED;
---------------------------------------------------------------------------
-- DMA Status Idle bit (BIT 1) - Set by dma controller indicating DMA
-- channel is IDLE waiting at tail pointer. Update of Tail Pointer
-- will cause engine to resume. Note: Halted channels return to a
-- reset condition.
---------------------------------------------------------------------------
DMASR_IDLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0'
or idle_clr = '1'
or halted_set = '1')then
idle <= '0';
elsif(idle_set = '1')then
idle <= '1';
end if;
end if;
end process DMASR_IDLE;
---------------------------------------------------------------------------
-- DMA Status Error bit (BIT 3)
-- Note: any error will cause entire engine to halt
---------------------------------------------------------------------------
error <= dma_interr
or dma_slverr
or dma_decerr
or sg_interr
or sg_slverr
or sg_decerr;
-- Scatter Gather Error
--sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set;
-- SG Update Errors or DMA errors assert flag on descriptor update
-- Used to latch current descriptor pointer
--sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set
-- or dma_interr or dma_slverr or dma_decerr;
-- Map out to halt opposing channel
error_out <= error;
SG_FTCH_ERROR_PROC : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_ftch_error <= '0';
sg_updt_error <= '0';
else
sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set;
sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set
or dma_interr or dma_slverr or dma_decerr;
end if;
end if;
end process SG_FTCH_ERROR_PROC;
---------------------------------------------------------------------------
-- DMA Status DMA Internal Error bit (BIT 4)
---------------------------------------------------------------------------
DMASR_DMAINTERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dma_interr <= '0';
elsif(dma_interr_set = '1' )then
dma_interr <= '1';
end if;
end if;
end process DMASR_DMAINTERR;
---------------------------------------------------------------------------
-- DMA Status DMA Slave Error bit (BIT 5)
---------------------------------------------------------------------------
DMASR_DMASLVERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dma_slverr <= '0';
elsif(dma_slverr_set = '1' )then
dma_slverr <= '1';
end if;
end if;
end process DMASR_DMASLVERR;
---------------------------------------------------------------------------
-- DMA Status DMA Decode Error bit (BIT 6)
---------------------------------------------------------------------------
DMASR_DMADECERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dma_decerr <= '0';
elsif(dma_decerr_set = '1' )then
dma_decerr <= '1';
end if;
end if;
end process DMASR_DMADECERR;
---------------------------------------------------------------------------
-- DMA Status SG Internal Error bit (BIT 8)
-- (SG Mode only - trimmed at build time if simple mode)
---------------------------------------------------------------------------
DMASR_SGINTERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_interr <= '0';
elsif(ftch_interr_set = '1' or updt_interr_set = '1')then
sg_interr <= '1';
end if;
end if;
end process DMASR_SGINTERR;
---------------------------------------------------------------------------
-- DMA Status SG Slave Error bit (BIT 9)
-- (SG Mode only - trimmed at build time if simple mode)
---------------------------------------------------------------------------
DMASR_SGSLVERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_slverr <= '0';
elsif(ftch_slverr_set = '1' or updt_slverr_set = '1')then
sg_slverr <= '1';
end if;
end if;
end process DMASR_SGSLVERR;
---------------------------------------------------------------------------
-- DMA Status SG Decode Error bit (BIT 10)
-- (SG Mode only - trimmed at build time if simple mode)
---------------------------------------------------------------------------
DMASR_SGDECERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_decerr <= '0';
elsif(ftch_decerr_set = '1' or updt_decerr_set = '1')then
sg_decerr <= '1';
end if;
end if;
end process DMASR_SGDECERR;
---------------------------------------------------------------------------
-- DMA Status IOC Interrupt status bit (BIT 11)
---------------------------------------------------------------------------
DMASR_IOCIRQ : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ioc_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
ioc_irq <= (ioc_irq and not(axi2ip_wrdata(DMASR_IOCIRQ_BIT)))
or ioc_irq_set;
elsif(ioc_irq_set = '1')then
ioc_irq <= '1';
end if;
end if;
end process DMASR_IOCIRQ;
---------------------------------------------------------------------------
-- DMA Status Delay Interrupt status bit (BIT 12)
---------------------------------------------------------------------------
DMASR_DLYIRQ : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dly_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
dly_irq <= (dly_irq and not(axi2ip_wrdata(DMASR_DLYIRQ_BIT)))
or dly_irq_set;
elsif(dly_irq_set = '1')then
dly_irq <= '1';
end if;
end if;
end process DMASR_DLYIRQ;
-- CR605888 Disable delay timer if halted or on delay irq set
--dlyirq_dsble <= dmasr_i(DMASR_HALTED_BIT) -- CR606348
dlyirq_dsble <= not dmacr_i(DMACR_RS_BIT) -- CR606348
or dmasr_i(DMASR_DLYIRQ_BIT);
---------------------------------------------------------------------------
-- DMA Status Error Interrupt status bit (BIT 12)
---------------------------------------------------------------------------
-- Delay error setting for generation of error strobe
GEN_ERROR_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
error_d1 <= '0';
else
error_d1 <= error;
end if;
end if;
end process GEN_ERROR_RE;
-- Generate rising edge pulse on error
error_re <= error and not error_d1;
DMASR_ERRIRQ : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
err_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
err_irq <= (err_irq and not(axi2ip_wrdata(DMASR_ERRIRQ_BIT)))
or error_re;
elsif(error_re = '1')then
err_irq <= '1';
end if;
end if;
end process DMASR_ERRIRQ;
---------------------------------------------------------------------------
-- DMA Interrupt OUT
---------------------------------------------------------------------------
REG_INTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or soft_reset_i = '1')then
introut <= '0';
else
introut <= (dly_irq and dmacr_i(DMACR_DLY_IRQEN_BIT))
or (ioc_irq and dmacr_i(DMACR_IOC_IRQEN_BIT))
or (err_irq and dmacr_i(DMACR_ERR_IRQEN_BIT));
end if;
end if;
end process;
---------------------------------------------------------------------------
-- DMA Status Register
---------------------------------------------------------------------------
dmasr_i <= irqdelay_status -- Bits 31 downto 24
& irqthresh_status -- Bits 23 downto 16
& '0' -- Bit 15
& err_irq -- Bit 14
& dly_irq -- Bit 13
& ioc_irq -- Bit 12
& '0' -- Bit 11
& sg_decerr -- Bit 10
& sg_slverr -- Bit 9
& sg_interr -- Bit 8
& '0' -- Bit 7
& dma_decerr -- Bit 6
& dma_slverr -- Bit 5
& dma_interr -- Bit 4
& DMA_CONFIG -- Bit 3
& '0' -- Bit 2
& idle -- Bit 1
& halted; -- Bit 0
-- Generate current descriptor and tail descriptor register for Scatter Gather Mode
GEN_DESC_REG_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
GEN_SG_CTL_REG : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
MM2S_SGCTL : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_cache_info <= "00000011"; --(others => '0');
elsif(axi2ip_wrce(SGCTL_INDEX) = '1' ) then
sg_cache_info <= axi2ip_wrdata(11 downto 8) & axi2ip_wrdata(3 downto 0);
else
sg_cache_info <= sg_cache_info;
end if;
end if;
end process MM2S_SGCTL;
sg_ctl <= sg_cache_info;
end generate GEN_SG_CTL_REG;
GEN_SG_NO_CTL_REG : if C_ENABLE_MULTI_CHANNEL = 0 generate
begin
sg_ctl <= "00000011"; --(others => '0');
end generate GEN_SG_NO_CTL_REG;
-- Signals not used for Scatter Gather Mode, only simple mode
buffer_address_i <= (others => '0');
buffer_length_i <= (others => '0');
buffer_length_wren <= '0';
---------------------------------------------------------------------------
-- Current Descriptor LSB Register
---------------------------------------------------------------------------
CURDESC_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc_lsb_i <= (others => '0');
error_pointer_set <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set = '0')then
-- Scatter Gather Fetch Error
if(sg_ftch_error = '1' or sg_updt_error = '1')then
curdesc_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 6);
error_pointer_set <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1')then
-- curdesc_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1')then
curdesc_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 6);
error_pointer_set <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC_LSB_INDEX) = '1' and dmasr_i(DMASR_HALTED_BIT) = '1')then
curdesc_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT);
-- & ZERO_VALUE(CURDESC_RESERVED_BIT5
-- downto CURDESC_RESERVED_BIT0);
error_pointer_set <= '0';
end if;
end if;
end if;
end process CURDESC_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC_LSB_INDEX) = '1')then
taildesc_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT);
-- & ZERO_VALUE(TAILDESC_RESERVED_BIT5
-- downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC_LSB_REGISTER;
---------------------------------------------------------------------------
-- Current Descriptor MSB Register
---------------------------------------------------------------------------
-- Scatter Gather Interface configured for 64-Bit SG Addresses
GEN_SG_ADDR_EQL64 :if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
CURDESC_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc_msb_i <= (others => '0');
elsif(error_pointer_set = '0')then
-- Scatter Gather Fetch Error
if(sg_ftch_error = '1' or sg_updt_error = '1')then
curdesc_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH - 1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1')then
-- curdesc_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1')then
curdesc_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC_MSB_INDEX) = '1' and dmasr_i(DMASR_HALTED_BIT) = '1')then
curdesc_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC_MSB_INDEX) = '1')then
taildesc_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC_MSB_REGISTER;
end generate GEN_SG_ADDR_EQL64;
-- Scatter Gather Interface configured for 32-Bit SG Addresses
GEN_SG_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
curdesc_msb_i <= (others => '0');
taildesc_msb_i <= (others => '0');
end generate GEN_SG_ADDR_EQL32;
-- Scatter Gather Interface configured for 32-Bit SG Addresses
GEN_TAILUPDATE_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
TAILPNTR_UPDT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then
tailpntr_updated_d1 <= '0';
elsif(axi2ip_wrce(TAILDESC_LSB_INDEX) = '1')then
tailpntr_updated_d1 <= '1';
else
tailpntr_updated_d1 <= '0';
end if;
end if;
end process TAILPNTR_UPDT_PROCESS;
TAILPNTR_UPDT_PROCESS_DEL : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
tailpntr_updated_d2 <= '0';
else
tailpntr_updated_d2 <= tailpntr_updated_d1;
end if;
end if;
end process TAILPNTR_UPDT_PROCESS_DEL;
tailpntr_updated <= tailpntr_updated_d1 and (not tailpntr_updated_d2);
end generate GEN_TAILUPDATE_EQL32;
-- Scatter Gather Interface configured for 64-Bit SG Addresses
GEN_TAILUPDATE_EQL64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
TAILPNTR_UPDT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then
tailpntr_updated_d1 <= '0';
elsif(axi2ip_wrce(TAILDESC_MSB_INDEX) = '1')then
tailpntr_updated_d1 <= '1';
else
tailpntr_updated_d1 <= '0';
end if;
end if;
end process TAILPNTR_UPDT_PROCESS;
TAILPNTR_UPDT_PROCESS_DEL : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
tailpntr_updated_d2 <= '0';
else
tailpntr_updated_d2 <= tailpntr_updated_d1;
end if;
end if;
end process TAILPNTR_UPDT_PROCESS_DEL;
tailpntr_updated <= tailpntr_updated_d1 and (not tailpntr_updated_d2);
end generate GEN_TAILUPDATE_EQL64;
end generate GEN_DESC_REG_FOR_SG;
-- Generate Buffer Address and Length Register for Simple DMA Mode
GEN_REG_FOR_SMPL : if C_INCLUDE_SG = 0 generate
begin
-- Signals not used for simple dma mode, only for sg mode
curdesc_lsb_i <= (others => '0');
curdesc_msb_i <= (others => '0');
taildesc_lsb_i <= (others => '0');
taildesc_msb_i <= (others => '0');
tailpntr_updated <= '0';
error_pointer_set <= '0';
-- Buffer Address register. Used for Source Address (SA) if MM2S
-- and used for Destination Address (DA) if S2MM
BUFFER_ADDR_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_address_i <= (others => '0');
elsif(axi2ip_wrce(BUFF_ADDRESS_INDEX) = '1')then
buffer_address_i <= axi2ip_wrdata;
end if;
end if;
end process BUFFER_ADDR_REGISTER;
GEN_BUFF_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
BUFFER_ADDR_REGISTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_address_i_64 <= (others => '0');
elsif(axi2ip_wrce(BUFF_ADDRESS_MSB_INDEX) = '1')then
buffer_address_i_64 <= axi2ip_wrdata;
end if;
end if;
end process BUFFER_ADDR_REGISTER1;
end generate GEN_BUFF_ADDR_EQL64;
-- Buffer Length register. Used for number of bytes to transfer if MM2S
-- and used for size of receive buffer is S2MM
BUFFER_LNGTH_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_length_i <= (others => '0');
-- Update with actual bytes received (Only for S2MM channel)
-- elsif(bytes_received_wren = '1')then
-- buffer_length_i <= bytes_received;
elsif(axi2ip_wrce(BUFF_LENGTH_INDEX) = '1')then
buffer_length_i <= axi2ip_wrdata(C_SG_LENGTH_WIDTH-1 downto 0);
end if;
end if;
end process BUFFER_LNGTH_REGISTER;
-- Buffer Length Write Enable control. Assertion of wren will
-- begin a transfer if channel is Idle.
BUFFER_LNGTH_WRITE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_length_wren <= '0';
-- Non-zero length value written
elsif(axi2ip_wrce(BUFF_LENGTH_INDEX) = '1'
and axi2ip_wrdata(C_SG_LENGTH_WIDTH-1 downto 0) /= ZERO_VALUE(C_SG_LENGTH_WIDTH-1 downto 0))then
buffer_length_wren <= '1';
else
buffer_length_wren <= '0';
end if;
end if;
end process BUFFER_LNGTH_WRITE;
end generate GEN_REG_FOR_SMPL;
end implementation;
| gpl-3.0 | 97e2453139624a50de4ae0d608a240b0 | 0.43383 | 4.421797 | false | false | false | false |
tgingold/ghdl | libraries/openieee/v87/numeric_std-body.vhdl | 1 | 80,784 | -- This -*- vhdl -*- file was generated from numeric_std-body.proto
-- This -*- vhdl -*- file is part of GHDL.
-- IEEE 1076.3 compliant numeric std package body.
-- The implementation is based only on the specifications.
-- Copyright (C) 2015 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation; either version 2, or (at your option) any later
-- version.
--
-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with GCC; see the file COPYING2. If not see
-- <http://www.gnu.org/licenses/>.
package body NUMERIC_STD is
constant NO_WARNING : Boolean := False;
constant null_unsigned : unsigned (0 downto 1) := (others => '0');
constant null_signed : signed (0 downto 1) := (others => '0');
subtype nat1 is natural range 0 to 1;
type nat1_to_sl_type is array (nat1) of std_ulogic;
constant nat1_to_01 : nat1_to_sl_type := (0 => '0', 1 => '1');
subtype sl_01 is std_ulogic range '0' to '1';
subtype sl_x01 is std_ulogic range 'X' to '1';
type carry_array is array (sl_01, sl_01, sl_01) of sl_01;
constant compute_carry : carry_array :=
('0' => ('0' => ('0' => '0', '1' => '0'),
'1' => ('0' => '0', '1' => '1')),
'1' => ('0' => ('0' => '0', '1' => '1'),
'1' => ('0' => '1', '1' => '1')));
constant compute_sum : carry_array :=
('0' => ('0' => ('0' => '0', '1' => '1'),
'1' => ('0' => '1', '1' => '0')),
'1' => ('0' => ('0' => '1', '1' => '0'),
'1' => ('0' => '0', '1' => '1')));
type sl_to_x01_array is array (std_ulogic) of sl_x01;
constant sl_to_x01 : sl_to_x01_array :=
('0' | 'L' => '0', '1' | 'H' => '1', others => 'X');
type compare_type is (compare_unknown,
compare_lt,
compare_eq,
compare_gt);
-- Match.
-- '-' matches with everything.
-- '0'/'L' matches, '1'/'H' matches.
type match_table_type is array (std_ulogic, std_ulogic) of boolean;
constant match_table: match_table_type :=
('0' | 'L' => ('0' | 'L' | '-' => true, others => false),
'1' | 'H' => ('1' | 'H' | '-' => true, others => false),
'-' => (others => true),
others => ('-' => true, others => false));
function MAX (L, R : natural) return natural is
begin
if L > R then
return L;
else
return R;
end if;
end MAX;
function TO_INTEGER (ARG : UNSIGNED) return NATURAL
is
variable argn : UNSIGNED (ARG'Length -1 downto 0);
variable res : natural := 0;
begin
if argn'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: null array detected, returning 0"
severity warning;
return 0;
end if;
argn := TO_01 (ARG, 'X');
if argn (0) = 'X' then
assert NO_WARNING
report
"NUMERIC_STD.TO_INTEGER: non logical value detected, returning 0"
severity warning;
return 0;
end if;
for i in argn'range loop
res := res + res;
if argn (i) = '1' then
res := res + 1;
end if;
end loop;
return res;
end TO_INTEGER;
function TO_INTEGER (ARG : SIGNED) return INTEGER
is
variable argn : SIGNED (ARG'Length -1 downto 0);
variable res : integer := 0;
variable b : STD_ULOGIC;
begin
if argn'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: null array detected, returning 0"
severity warning;
return 0;
end if;
argn := TO_01 (ARG, 'X');
if argn (0) = 'X' then
assert NO_WARNING
report
"NUMERIC_STD.TO_INTEGER: non logical value detected, returning 0"
severity warning;
return 0;
end if;
if argn (argn'left) = '1' then
-- Negative value
b := '0';
else
b := '1';
end if;
for i in argn'range loop
res := res + res;
if argn (i) = b then
res := res + 1;
end if;
end loop;
if b = '0' then
-- Avoid overflow.
res := -res - 1;
end if;
return res;
end TO_INTEGER;
function TO_01 (S : SIGNED; XMAP : STD_LOGIC := '0') return SIGNED
is
subtype res_type is SIGNED (S'Length - 1 downto 0);
variable res : res_type;
alias snorm: res_type is S;
begin
if S'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.TO_01: null array detected"
severity warning;
return null_signed;
else
for i in res_type'range loop
case snorm (i) is
when '0' | 'L' => res (i) := '0';
when '1' | 'H' => res (i) := '1';
when others =>
assert NO_WARNING
report "NUMERIC_STD.TO_01: non logical value detected"
severity warning;
res := (others => XMAP);
exit;
end case;
end loop;
end if;
return res;
end TO_01;
function TO_01 (S : UNSIGNED; XMAP : STD_LOGIC := '0') return UNSIGNED
is
subtype res_type is UNSIGNED (S'Length - 1 downto 0);
variable res : res_type;
alias snorm: res_type is S;
begin
if S'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.TO_01: null array detected"
severity warning;
return null_unsigned;
else
for i in res_type'range loop
case snorm (i) is
when '0' | 'L' => res (i) := '0';
when '1' | 'H' => res (i) := '1';
when others =>
assert NO_WARNING
report "NUMERIC_STD.TO_01: non logical value detected"
severity warning;
res := (others => XMAP);
exit;
end case;
end loop;
end if;
return res;
end TO_01;
function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNSIGNED
is
variable res : UNSIGNED (SIZE - 1 downto 0);
variable a : natural := arg;
variable d : nat1;
begin
if size = 0 then
return null_unsigned;
end if;
for i in res'reverse_range loop
d := a rem 2;
res (i) := nat1_to_01 (d);
a := a / 2;
end loop;
if a /= 0 then
assert NO_WARNING
report "NUMERIC_STD.TO_UNSIGNED: vector is truncated"
severity warning;
end if;
return res;
end TO_UNSIGNED;
function TO_SIGNED (ARG : INTEGER; SIZE : NATURAL) return SIGNED
is
variable res : SIGNED (SIZE - 1 downto 0);
variable v : integer := arg;
variable b0, b1 : std_ulogic;
variable d : nat1;
begin
if size = 0 then
return null_signed;
end if;
if arg < 0 then
-- Use one complement to avoid overflow:
-- -v = (not v) + 1
-- not v = -v - 1
-- not v = -(v + 1)
v := -(arg + 1);
b0 := '1';
b1 := '0';
else
v := arg;
b0 := '0';
b1 := '1';
end if;
for i in res'reverse_range loop
d := v rem 2;
v := v / 2;
if d = 0 then
res (i) := b0;
else
res (i) := b1;
end if;
end loop;
if v /= 0 or res (res'left) /= b0 then
assert NO_WARNING
report "NUMERIC_STD.TO_SIGNED: vector is truncated"
severity warning;
end if;
return res;
end TO_SIGNED;
function std_match (l, r : std_ulogic) return boolean is
begin
return match_table (l, r);
end std_match;
function std_match (l, r : std_ulogic_vector) return boolean
is
alias la : std_ulogic_vector (l'length downto 1) is l;
alias ra : std_ulogic_vector (r'length downto 1) is r;
begin
if la'left = 0 or ra'left = 0 then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null argument, returning false"
severity warning;
return false;
elsif la'left /= ra'left then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: args length mismatch, returning false"
severity warning;
return false;
else
for i in la'range loop
if not match_table (la (i), ra (i)) then
return false;
end if;
end loop;
return true;
end if;
end std_match;
function std_match (l, r : std_logic_vector) return boolean
is
alias la : std_logic_vector (l'length downto 1) is l;
alias ra : std_logic_vector (r'length downto 1) is r;
begin
if la'left = 0 or ra'left = 0 then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null argument, returning false"
severity warning;
return false;
elsif la'left /= ra'left then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: args length mismatch, returning false"
severity warning;
return false;
else
for i in la'range loop
if not match_table (la (i), ra (i)) then
return false;
end if;
end loop;
return true;
end if;
end std_match;
function std_match (l, r : UNSIGNED) return boolean
is
alias la : UNSIGNED (l'length downto 1) is l;
alias ra : UNSIGNED (r'length downto 1) is r;
begin
if la'left = 0 or ra'left = 0 then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null argument, returning false"
severity warning;
return false;
elsif la'left /= ra'left then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: args length mismatch, returning false"
severity warning;
return false;
else
for i in la'range loop
if not match_table (la (i), ra (i)) then
return false;
end if;
end loop;
return true;
end if;
end std_match;
function std_match (l, r : SIGNED) return boolean
is
alias la : SIGNED (l'length downto 1) is l;
alias ra : SIGNED (r'length downto 1) is r;
begin
if la'left = 0 or ra'left = 0 then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null argument, returning false"
severity warning;
return false;
elsif la'left /= ra'left then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: args length mismatch, returning false"
severity warning;
return false;
else
for i in la'range loop
if not match_table (la (i), ra (i)) then
return false;
end if;
end loop;
return true;
end if;
end std_match;
function "+" (l, r : UNSIGNED) return UNSIGNED
is
constant lft : integer := MAX (l'length, r'length) - 1;
subtype res_type is UNSIGNED (lft downto 0);
alias la : UNSIGNED (l'length - 1 downto 0) is l;
alias ra : UNSIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
variable lb, rb, carry : sl_x01;
begin
if la'left < 0 or ra'left < 0 then
return null_UNSIGNED;
end if;
carry := '0';
for i in 0 to lft loop
if i > la'left then
lb := '0';
else
lb := sl_to_x01 (la (i));
end if;
if i > ra'left then
rb := '0';
else
rb := sl_to_x01 (ra (i));
end if;
if lb = 'X' or rb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""+"": non logical value detected"
severity warning;
res := (others => 'X');
exit;
end if;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
return res;
end "+";
function "+" (l, r : SIGNED) return SIGNED
is
constant lft : integer := MAX (l'length, r'length) - 1;
subtype res_type is SIGNED (lft downto 0);
alias la : SIGNED (l'length - 1 downto 0) is l;
alias ra : SIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
variable lb, rb, carry : sl_x01;
begin
if la'left < 0 or ra'left < 0 then
return null_SIGNED;
end if;
carry := '0';
for i in 0 to lft loop
if i > la'left then
lb := l (l'left);
else
lb := sl_to_x01 (la (i));
end if;
if i > ra'left then
rb := r (r'left);
else
rb := sl_to_x01 (ra (i));
end if;
if lb = 'X' or rb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""+"": non logical value detected"
severity warning;
res := (others => 'X');
exit;
end if;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
return res;
end "+";
function "+" (l : UNSIGNED; r : NATURAL) return UNSIGNED
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : NATURAL;
variable rd : nat1;
variable res : res_type;
variable lb, rb, carry : sl_x01;
begin
if res'length < 0 then
return null_UNSIGNED;
end if;
carry := '0';
r1 := r;
for i in res'reverse_range loop
lb := sl_to_x01 (la (i));
r2 := r1 / 2;
rd := r1 - 2 * r2;
r1 := r2;
rb := nat1_to_01 (rd);
if lb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""+"": non logical value detected"
severity warning;
res := (others => 'X');
r1 := 0;
exit;
end if;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
if r1 /= 0 then
assert NO_WARNING
report "NUMERIC_STD.""+"": vector is truncated"
severity warning;
end if;
return res;
end "+";
function "+" (l : NATURAL; r : UNSIGNED) return UNSIGNED
is
subtype res_type is UNSIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : NATURAL;
variable ld : nat1;
variable res : res_type;
variable lb, rb, carry : sl_x01;
begin
if res'length < 0 then
return null_UNSIGNED;
end if;
carry := '0';
l1 := l;
for i in res'reverse_range loop
rb := sl_to_x01 (ra (i));
l2 := l1 / 2;
ld := l1 - 2 * l2;
l1 := l2;
lb := nat1_to_01 (ld);
if rb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""+"": non logical value detected"
severity warning;
res := (others => 'X');
l1 := 0;
exit;
end if;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
if l1 /= 0 then
assert NO_WARNING
report "NUMERIC_STD.""+"": vector is truncated"
severity warning;
end if;
return res;
end "+";
function "+" (l : SIGNED; r : INTEGER) return SIGNED
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : INTEGER;
variable rd : nat1;
constant rmsb : nat1 := boolean'pos(r < 0);
variable res : res_type;
variable lb, rb, carry : sl_x01;
begin
if res'length < 0 then
return null_SIGNED;
end if;
carry := '0';
r1 := r;
for i in res'reverse_range loop
lb := sl_to_x01 (la (i));
r2 := r1 / 2;
if r1 < 0 then
rd := 2 * r2 - r1;
r1 := r2 - rd;
else
rd := r1 - 2 * r2;
r1 := r2;
end if;
rb := nat1_to_01 (rd);
if lb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""+"": non logical value detected"
severity warning;
res := (others => 'X');
r1 := 0;
exit;
end if;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
if r1 /= -rmsb then
assert NO_WARNING
report "NUMERIC_STD.""+"": vector is truncated"
severity warning;
end if;
return res;
end "+";
function "+" (l : INTEGER; r : SIGNED) return SIGNED
is
subtype res_type is SIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : INTEGER;
variable ld : nat1;
constant lmsb : nat1 := boolean'pos(l < 0);
variable res : res_type;
variable lb, rb, carry : sl_x01;
begin
if res'length < 0 then
return null_SIGNED;
end if;
carry := '0';
l1 := l;
for i in res'reverse_range loop
rb := sl_to_x01 (ra (i));
l2 := l1 / 2;
if l1 < 0 then
ld := 2 * l2 - l1;
l1 := l2 - ld;
else
ld := l1 - 2 * l2;
l1 := l2;
end if;
lb := nat1_to_01 (ld);
if rb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""+"": non logical value detected"
severity warning;
res := (others => 'X');
l1 := 0;
exit;
end if;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
if l1 /= -lmsb then
assert NO_WARNING
report "NUMERIC_STD.""+"": vector is truncated"
severity warning;
end if;
return res;
end "+";
function "-" (l, r : UNSIGNED) return UNSIGNED
is
constant lft : integer := MAX (l'length, r'length) - 1;
subtype res_type is UNSIGNED (lft downto 0);
alias la : UNSIGNED (l'length - 1 downto 0) is l;
alias ra : UNSIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
variable lb, rb, carry : sl_x01;
begin
if la'left < 0 or ra'left < 0 then
return null_UNSIGNED;
end if;
carry := '1';
for i in 0 to lft loop
if i > la'left then
lb := '0';
else
lb := sl_to_x01 (la (i));
end if;
if i > ra'left then
rb := '0';
else
rb := sl_to_x01 (ra (i));
end if;
if lb = 'X' or rb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""-"": non logical value detected"
severity warning;
res := (others => 'X');
exit;
end if;
rb := not rb;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
return res;
end "-";
function "-" (l, r : SIGNED) return SIGNED
is
constant lft : integer := MAX (l'length, r'length) - 1;
subtype res_type is SIGNED (lft downto 0);
alias la : SIGNED (l'length - 1 downto 0) is l;
alias ra : SIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
variable lb, rb, carry : sl_x01;
begin
if la'left < 0 or ra'left < 0 then
return null_SIGNED;
end if;
carry := '1';
for i in 0 to lft loop
if i > la'left then
lb := l (l'left);
else
lb := sl_to_x01 (la (i));
end if;
if i > ra'left then
rb := r (r'left);
else
rb := sl_to_x01 (ra (i));
end if;
if lb = 'X' or rb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""-"": non logical value detected"
severity warning;
res := (others => 'X');
exit;
end if;
rb := not rb;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
return res;
end "-";
function "-" (l : UNSIGNED; r : NATURAL) return UNSIGNED
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : NATURAL;
variable rd : nat1;
variable res : res_type;
variable lb, rb, carry : sl_x01;
begin
if res'length < 0 then
return null_UNSIGNED;
end if;
carry := '1';
r1 := r;
for i in res'reverse_range loop
lb := sl_to_x01 (la (i));
r2 := r1 / 2;
rd := r1 - 2 * r2;
r1 := r2;
rb := nat1_to_01 (rd);
if lb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""-"": non logical value detected"
severity warning;
res := (others => 'X');
r1 := 0;
exit;
end if;
rb := not rb;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
if r1 /= 0 then
assert NO_WARNING
report "NUMERIC_STD.""-"": vector is truncated"
severity warning;
end if;
return res;
end "-";
function "-" (l : NATURAL; r : UNSIGNED) return UNSIGNED
is
subtype res_type is UNSIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : NATURAL;
variable ld : nat1;
variable res : res_type;
variable lb, rb, carry : sl_x01;
begin
if res'length < 0 then
return null_UNSIGNED;
end if;
carry := '1';
l1 := l;
for i in res'reverse_range loop
rb := sl_to_x01 (ra (i));
l2 := l1 / 2;
ld := l1 - 2 * l2;
l1 := l2;
lb := nat1_to_01 (ld);
if rb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""-"": non logical value detected"
severity warning;
res := (others => 'X');
l1 := 0;
exit;
end if;
rb := not rb;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
if l1 /= 0 then
assert NO_WARNING
report "NUMERIC_STD.""-"": vector is truncated"
severity warning;
end if;
return res;
end "-";
function "-" (l : SIGNED; r : INTEGER) return SIGNED
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : INTEGER;
variable rd : nat1;
constant rmsb : nat1 := boolean'pos(r < 0);
variable res : res_type;
variable lb, rb, carry : sl_x01;
begin
if res'length < 0 then
return null_SIGNED;
end if;
carry := '1';
r1 := r;
for i in res'reverse_range loop
lb := sl_to_x01 (la (i));
r2 := r1 / 2;
if r1 < 0 then
rd := 2 * r2 - r1;
r1 := r2 - rd;
else
rd := r1 - 2 * r2;
r1 := r2;
end if;
rb := nat1_to_01 (rd);
if lb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""-"": non logical value detected"
severity warning;
res := (others => 'X');
r1 := 0;
exit;
end if;
rb := not rb;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
if r1 /= -rmsb then
assert NO_WARNING
report "NUMERIC_STD.""-"": vector is truncated"
severity warning;
end if;
return res;
end "-";
function "-" (l : INTEGER; r : SIGNED) return SIGNED
is
subtype res_type is SIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : INTEGER;
variable ld : nat1;
constant lmsb : nat1 := boolean'pos(l < 0);
variable res : res_type;
variable lb, rb, carry : sl_x01;
begin
if res'length < 0 then
return null_SIGNED;
end if;
carry := '1';
l1 := l;
for i in res'reverse_range loop
rb := sl_to_x01 (ra (i));
l2 := l1 / 2;
if l1 < 0 then
ld := 2 * l2 - l1;
l1 := l2 - ld;
else
ld := l1 - 2 * l2;
l1 := l2;
end if;
lb := nat1_to_01 (ld);
if rb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""-"": non logical value detected"
severity warning;
res := (others => 'X');
l1 := 0;
exit;
end if;
rb := not rb;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
if l1 /= -lmsb then
assert NO_WARNING
report "NUMERIC_STD.""-"": vector is truncated"
severity warning;
end if;
return res;
end "-";
function "*" (L, R : UNSIGNED) return UNSIGNED
is
alias la : UNSIGNED (L'Length - 1 downto 0) is l;
alias ra : UNSIGNED (R'Length - 1 downto 0) is r;
variable res : UNSIGNED (L'length + R'Length -1 downto 0) := (others => '0');
variable rb, lb, vb, carry : sl_x01;
begin
if la'length = 0 or ra'length = 0 then
return null_UNSIGNED;
end if;
-- Shift and add L.
for i in natural range 0 to ra'left loop
rb := sl_to_x01 (ra (i));
if rb = '1' then
-- Compute res := res + shift_left (l, i).
carry := '0';
for j in la'reverse_range loop
lb := la (j);
vb := res (i + j);
res (i + j) := compute_sum (carry, vb, lb);
carry := compute_carry (carry, vb, lb);
end loop;
-- Propagate carry.
for j in i + la'length to res'left loop
exit when carry = '0';
vb := res (j);
res (j) := carry xor vb;
carry := carry and vb;
end loop;
elsif rb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""*"": non logical value detected"
severity warning;
end if;
end loop;
return res;
end "*";
function "*" (L, R : SIGNED) return SIGNED
is
alias la : SIGNED (L'Length - 1 downto 0) is l;
alias ra : SIGNED (R'Length - 1 downto 0) is r;
variable res : SIGNED (L'length + R'Length -1 downto 0) := (others => '0');
variable rb, lb, vb, carry : sl_x01;
begin
if la'length = 0 or ra'length = 0 then
return null_SIGNED;
end if;
-- Shift and add L.
for i in natural range 0 to ra'left - 1 loop
rb := sl_to_x01 (ra (i));
if rb = '1' then
-- Compute res := res + shift_left (l, i).
carry := '0';
for j in la'reverse_range loop
lb := la (j);
vb := res (i + j);
res (i + j) := compute_sum (carry, vb, lb);
carry := compute_carry (carry, vb, lb);
end loop;
-- Sign extend and propagate carry.
lb := la (la'left);
for j in i + l'length to res'left loop
vb := res (j);
res (j) := compute_sum (carry, vb, lb);
carry := compute_carry (carry, vb, lb);
end loop;
elsif rb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""*"": non logical value detected"
severity warning;
end if;
end loop;
if ra (ra'left) = '1' then
-- R is a negative number. It is considered as:
-- -2**n + (Rn-1 Rn-2 ... R0).
-- Compute res := res - 2**n * l.
carry := '1';
for i in la'reverse_range loop
vb := res (ra'length - 1 + i);
lb := not la (i);
res (ra'length - 1+ i) := compute_sum (carry, vb, lb);
carry := compute_carry (carry, vb, lb);
end loop;
vb := res (res'left);
lb := not la (la'left);
res (res'left) := compute_sum (carry, vb, lb);
end if;
return res;
end "*";
function "*" (L : UNSIGNED; R : NATURAL) return UNSIGNED
is
constant size : natural := l'length;
begin
if size = 0 then
return null_UNSIGNED;
end if;
return l * to_UNSIGNED (r, size);
end "*";
function "*" (L : SIGNED; R : INTEGER) return SIGNED
is
constant size : natural := l'length;
begin
if size = 0 then
return null_SIGNED;
end if;
return l * to_SIGNED (r, size);
end "*";
function "*" (L : NATURAL; R : UNSIGNED) return UNSIGNED
is
constant size : natural := r'length;
begin
if size = 0 then
return null_UNSIGNED;
end if;
return r * to_UNSIGNED (l, size);
end "*";
function "*" (L : INTEGER; R : SIGNED) return SIGNED
is
constant size : natural := r'length;
begin
if size = 0 then
return null_SIGNED;
end if;
return r * to_SIGNED (l, size);
end "*";
function has_0x (a : UNSIGNED) return sl_x01
is
variable res : sl_x01 := '0';
begin
for i in a'range loop
if a (i) = 'X' then
return 'X';
end if;
res := res or a (i);
end loop;
return res;
end has_0x;
-- All index range are normalized (N downto 0).
-- NUM and QUOT have the same range.
-- DEM and REMAIN have the same range.
-- No 'X'.
procedure divmod (num, dem : UNSIGNED; quot, remain : out UNSIGNED)
is
variable reg : unsigned (dem'left + 1 downto 0) := (others => '0');
variable sub : unsigned (dem'range) := (others => '0');
variable carry, d : sl_x01;
begin
for i in num'range loop
-- Shift
reg (reg'left downto 1) := reg (reg'left - 1 downto 0);
reg (0) := num (i);
-- Substract
carry := '1';
for j in dem'reverse_range loop
d := not dem (j);
sub (j) := compute_sum (carry, reg (j), d);
carry := compute_carry (carry, reg (j), d);
end loop;
carry := compute_carry (carry, reg (reg'left), '1');
-- Test
if carry = '0' then
-- Greater than
quot (i) := '0';
else
quot (i) := '1';
reg (reg'left) := '0';
reg (sub'range) := sub;
end if;
end loop;
remain := reg (dem'range);
end divmod;
function size_unsigned (n : natural) return natural
is
-- At least one bit (even for 0).
variable res : natural := 1;
variable n1 : natural := n;
begin
while n1 > 1 loop
res := res + 1;
n1 := n1 / 2;
end loop;
return res;
end size_unsigned;
function size_signed (n : integer) return natural
is
variable res : natural := 1;
variable n1 : natural;
begin
if n >= 0 then
n1 := n;
else
-- Use /N = -X -1 = -(X + 1) (No overflow).
n1 := -(n + 1);
end if;
while n1 /= 0 loop
res := res + 1;
n1 := n1 / 2;
end loop;
return res;
end size_signed;
function "/" (L, R : UNSIGNED) return UNSIGNED
is
subtype l_type is UNSIGNED (L'length - 1 downto 0);
subtype r_type is UNSIGNED (R'length - 1 downto 0);
alias la : l_type is l;
alias ra : r_type is r;
variable quot : l_type;
variable rema : r_type;
variable r0 : sl_x01 := has_0x (r);
begin
if la'length = 0 or ra'length = 0 then
return null_unsigned;
end if;
if has_0x (l) = 'X' or r0 = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""/"": non logical value detected"
severity warning;
return l_type'(others => 'X');
end if;
assert r0 /= '0'
report "NUMERIC_STD.""/"": division by 0"
severity error;
divmod (la, ra, quot, rema);
return quot;
end "/";
function "/" (L : UNSIGNED; R : NATURAL) return UNSIGNED
is
constant r_size : natural := size_unsigned (r);
begin
if l'length = 0 then
return null_unsigned;
end if;
return l / to_unsigned (r, r_size);
end "/";
function "/" (L : NATURAL; R : UNSIGNED) return UNSIGNED
is
constant l_size : natural := size_unsigned (l);
begin
if r'length = 0 then
return null_unsigned;
end if;
return resize (to_unsigned (l, l_size) / r, r'length);
end "/";
function "rem" (L, R : UNSIGNED) return UNSIGNED
is
subtype l_type is UNSIGNED (L'length - 1 downto 0);
subtype r_type is UNSIGNED (R'length - 1 downto 0);
alias la : l_type is l;
alias ra : r_type is r;
variable quot : l_type;
variable rema : r_type;
variable r0 : sl_x01 := has_0x (r);
begin
if la'length = 0 or ra'length = 0 then
return null_unsigned;
end if;
if has_0x (l) = 'X' or r0 = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""/"": non logical value detected"
severity warning;
return l_type'(others => 'X');
end if;
assert r0 /= '0'
report "NUMERIC_STD.""rem"": division by 0"
severity error;
divmod (la, ra, quot, rema);
return rema;
end "rem";
function "rem" (L : UNSIGNED; R : NATURAL) return UNSIGNED
is
constant r_size : natural := size_unsigned (r);
begin
if l'length = 0 then
return null_unsigned;
end if;
return resize (l rem to_unsigned (r, r_size), l'length);
end "rem";
function "rem" (L : NATURAL; R : UNSIGNED) return UNSIGNED
is
constant l_size : natural := size_unsigned (l);
begin
if r'length = 0 then
return null_unsigned;
end if;
return to_unsigned (l, l_size) rem r;
end "rem";
function "mod" (L, R : UNSIGNED) return UNSIGNED
is
subtype l_type is UNSIGNED (L'length - 1 downto 0);
subtype r_type is UNSIGNED (R'length - 1 downto 0);
alias la : l_type is l;
alias ra : r_type is r;
variable quot : l_type;
variable rema : r_type;
variable r0 : sl_x01 := has_0x (r);
begin
if la'length = 0 or ra'length = 0 then
return null_unsigned;
end if;
if has_0x (l) = 'X' or r0 = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""/"": non logical value detected"
severity warning;
return l_type'(others => 'X');
end if;
assert r0 /= '0'
report "NUMERIC_STD.""mod"": division by 0"
severity error;
divmod (la, ra, quot, rema);
return rema;
end "mod";
function "mod" (L : UNSIGNED; R : NATURAL) return UNSIGNED
is
constant r_size : natural := size_unsigned (r);
begin
if l'length = 0 then
return null_unsigned;
end if;
return resize (l mod to_unsigned (r, r_size), l'length);
end "mod";
function "mod" (L : NATURAL; R : UNSIGNED) return UNSIGNED
is
constant l_size : natural := size_unsigned (l);
begin
if r'length = 0 then
return null_unsigned;
end if;
return to_unsigned (l, l_size) mod r;
end "mod";
function has_0x (a : SIGNED) return sl_x01
is
variable res : sl_x01 := '0';
begin
for i in a'range loop
if a (i) = 'X' then
return 'X';
end if;
res := res or a (i);
end loop;
return res;
end has_0x;
function "-" (ARG : SIGNED) return SIGNED
is
subtype arg_type is SIGNED (ARG'length - 1 downto 0);
alias arga : arg_type is arg;
variable res : arg_type;
variable carry, a : sl_x01;
begin
if arga'length = 0 then
return null_signed;
end if;
if has_0x (arga) = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""-"": non logical value detected"
severity warning;
return arg_type'(others => 'X');
end if;
carry := '1';
for i in arga'reverse_range loop
a := not arga (i);
res (i) := carry xor a;
carry := carry and a;
end loop;
return res;
end "-";
function "abs" (ARG : SIGNED) return SIGNED
is
subtype arg_type is SIGNED (ARG'length - 1 downto 0);
alias arga : arg_type is arg;
variable res : arg_type;
variable carry, a : sl_x01;
begin
if arga'length = 0 then
return null_signed;
end if;
if has_0x (arga) = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""-"": non logical value detected"
severity warning;
return arg_type'(others => 'X');
end if;
if arga (arga'left) = '0' then
return arga;
end if;
carry := '1';
for i in arga'reverse_range loop
a := not arga (i);
res (i) := carry xor a;
carry := carry and a;
end loop;
return res;
end "abs";
function "/" (L, R : SIGNED) return SIGNED
is
subtype l_type is SIGNED (L'length - 1 downto 0);
subtype r_type is SIGNED (R'length - 1 downto 0);
alias la : l_type is l;
alias ra : r_type is r;
subtype l_utype is UNSIGNED (l_type'range);
subtype r_utype is UNSIGNED (r_type'range);
variable lu : l_utype;
variable ru : r_utype;
variable quot : l_utype;
variable rema : r_utype;
variable r0 : sl_x01 := has_0x (r);
begin
if la'length = 0 or ra'length = 0 then
return null_signed;
end if;
if has_0x (l) = 'X' or r0 = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""/"": non logical value detected"
severity warning;
return l_type'(others => 'X');
end if;
assert r0 /= '0'
report "NUMERIC_STD.""/"": division by 0"
severity error;
if la (la'left) = '1' then
lu := unsigned (-la);
else
lu := unsigned (la);
end if;
if ra (ra'left) = '1' then
ru := unsigned (-ra);
else
ru := unsigned (ra);
end if;
divmod (lu, ru, quot, rema);
if (ra (ra'left) xor la (la'left)) = '1' then
return -signed (quot);
else
return signed (quot);
end if;
end "/";
function "/" (L : SIGNED; R : INTEGER) return SIGNED
is
constant r_size : natural := size_signed (r);
begin
if l'length = 0 then
return null_signed;
end if;
return l / to_signed (r, r_size);
end "/";
function "/" (L : INTEGER; R : SIGNED) return SIGNED
is
constant l_size : natural := size_signed (l);
begin
if r'length = 0 then
return null_signed;
end if;
return resize (to_signed (l, max (l_size, r'length)) / r, r'length);
end "/";
function "rem" (L, R : SIGNED) return SIGNED
is
subtype l_type is SIGNED (L'length - 1 downto 0);
subtype r_type is SIGNED (R'length - 1 downto 0);
alias la : l_type is l;
alias ra : r_type is r;
subtype l_utype is UNSIGNED (l_type'range);
subtype r_utype is UNSIGNED (r_type'range);
variable lu : l_utype;
variable ru : r_utype;
variable quot : l_utype;
variable rema : r_utype;
variable r0 : sl_x01 := has_0x (r);
begin
if la'length = 0 or ra'length = 0 then
return null_signed;
end if;
if has_0x (l) = 'X' or r0 = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""rem"": non logical value detected"
severity warning;
return l_type'(others => 'X');
end if;
assert r0 /= '0'
report "NUMERIC_STD.""rem"": division by 0"
severity error;
if la (la'left) = '1' then
lu := unsigned (-la);
else
lu := unsigned (la);
end if;
if ra (ra'left) = '1' then
ru := unsigned (-ra);
else
ru := unsigned (ra);
end if;
divmod (lu, ru, quot, rema);
-- Result of rem has the sign of the dividend.
if la (la'left) = '1' then
return -signed (rema);
else
return signed (rema);
end if;
end "rem";
function "rem" (L : SIGNED; R : INTEGER) return SIGNED
is
constant r_size : natural := size_signed (r);
begin
if l'length = 0 then
return null_signed;
end if;
return resize (l rem to_signed (r, r_size), l'length);
end "rem";
function "rem" (L : INTEGER; R : SIGNED) return SIGNED
is
constant l_size : natural := size_signed (l);
begin
if r'length = 0 then
return null_signed;
end if;
return to_signed (l, l_size) rem r;
end "rem";
function "mod" (L, R : SIGNED) return SIGNED
is
subtype l_type is SIGNED (L'length - 1 downto 0);
subtype r_type is SIGNED (R'length - 1 downto 0);
alias la : l_type is l;
alias ra : r_type is r;
subtype l_utype is UNSIGNED (l_type'range);
subtype r_utype is UNSIGNED (r_type'range);
variable lu : l_utype;
variable ru : r_utype;
variable quot : l_utype;
variable rema : r_utype;
variable r0 : sl_x01 := has_0x (r);
begin
if la'length = 0 or ra'length = 0 then
return null_signed;
end if;
if has_0x (l) = 'X' or r0 = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""mod"": non logical value detected"
severity warning;
return l_type'(others => 'X');
end if;
assert r0 /= '0'
report "NUMERIC_STD.""mod"": division by 0"
severity error;
if la (la'left) = '1' then
lu := unsigned (-la);
else
lu := unsigned (la);
end if;
if ra (ra'left) = '1' then
ru := unsigned (-ra);
else
ru := unsigned (ra);
end if;
divmod (lu, ru, quot, rema);
-- Result of mod has the sign of the divisor.
if rema = r_utype'(others => '0') then
-- If the remainder is 0, then the modulus is 0.
return signed (rema);
else
if ra (ra'left) = '1' then
if la (la'left) = '1' then
return -signed (rema);
else
return ra + signed (rema);
end if;
else
if la (la'left) = '1' then
return ra - signed (rema);
else
return signed (rema);
end if;
end if;
end if;
end "mod";
function "mod" (L : SIGNED; R : INTEGER) return SIGNED
is
constant r_size : natural := size_signed (r);
begin
if l'length = 0 then
return null_signed;
end if;
return resize (l mod to_signed (r, r_size), l'length);
end "mod";
function "mod" (L : INTEGER; R : SIGNED) return SIGNED
is
constant l_size : natural := size_signed (l);
begin
if r'length = 0 then
return null_signed;
end if;
return to_signed (l, l_size) mod r;
end "mod";
function resize (ARG : UNSIGNED; NEW_SIZE: natural) return UNSIGNED
is
alias arg1 : UNSIGNED (ARG'length - 1 downto 0) is arg;
variable res : UNSIGNED (new_size - 1 downto 0) := (others => '0');
begin
if new_size = 0 then
return null_UNSIGNED;
end if;
if arg1'length = 0 then
return res;
end if;
if arg1'length > new_size then
-- Reduction.
res := arg1 (res'range);
else
-- Expansion
res (arg1'range) := arg1;
end if;
return res;
end resize;
function resize (ARG : SIGNED; NEW_SIZE: natural) return SIGNED
is
alias arg1 : SIGNED (ARG'length - 1 downto 0) is arg;
variable res : SIGNED (new_size - 1 downto 0) := (others => '0');
begin
if new_size = 0 then
return null_SIGNED;
end if;
if arg1'length = 0 then
return res;
end if;
if arg1'length > new_size then
-- Reduction.
res (res'left) := arg1 (arg1'left);
res (res'left - 1 downto 0) := arg1 (res'left - 1 downto 0);
else
-- Expansion
res (arg1'range) := arg1;
res (res'left downto arg1'length) := (others => arg1 (arg1'left));
end if;
return res;
end resize;
function "not" (l : UNSIGNED) return UNSIGNED
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable res : res_type;
begin
for I in res_type'range loop
res (I) := not la (I);
end loop;
return res;
end "not";
function "not" (l : SIGNED) return SIGNED
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable res : res_type;
begin
for I in res_type'range loop
res (I) := not la (I);
end loop;
return res;
end "not";
function "and" (l, r : UNSIGNED) return UNSIGNED
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : UNSIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""and"": arguments are not of the same length"
severity failure;
res := (others => 'X');
else
for I in res_type'range loop
res (I) := la (I) and ra (I);
end loop;
end if;
return res;
end "and";
function "and" (l, r : SIGNED) return SIGNED
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : SIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""and"": arguments are not of the same length"
severity failure;
res := (others => 'X');
else
for I in res_type'range loop
res (I) := la (I) and ra (I);
end loop;
end if;
return res;
end "and";
function "nand" (l, r : UNSIGNED) return UNSIGNED
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : UNSIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""nand"": arguments are not of the same length"
severity failure;
res := (others => 'X');
else
for I in res_type'range loop
res (I) := la (I) nand ra (I);
end loop;
end if;
return res;
end "nand";
function "nand" (l, r : SIGNED) return SIGNED
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : SIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""nand"": arguments are not of the same length"
severity failure;
res := (others => 'X');
else
for I in res_type'range loop
res (I) := la (I) nand ra (I);
end loop;
end if;
return res;
end "nand";
function "or" (l, r : UNSIGNED) return UNSIGNED
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : UNSIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""or"": arguments are not of the same length"
severity failure;
res := (others => 'X');
else
for I in res_type'range loop
res (I) := la (I) or ra (I);
end loop;
end if;
return res;
end "or";
function "or" (l, r : SIGNED) return SIGNED
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : SIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""or"": arguments are not of the same length"
severity failure;
res := (others => 'X');
else
for I in res_type'range loop
res (I) := la (I) or ra (I);
end loop;
end if;
return res;
end "or";
function "nor" (l, r : UNSIGNED) return UNSIGNED
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : UNSIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""nor"": arguments are not of the same length"
severity failure;
res := (others => 'X');
else
for I in res_type'range loop
res (I) := la (I) nor ra (I);
end loop;
end if;
return res;
end "nor";
function "nor" (l, r : SIGNED) return SIGNED
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : SIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""nor"": arguments are not of the same length"
severity failure;
res := (others => 'X');
else
for I in res_type'range loop
res (I) := la (I) nor ra (I);
end loop;
end if;
return res;
end "nor";
function "xor" (l, r : UNSIGNED) return UNSIGNED
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : UNSIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""xor"": arguments are not of the same length"
severity failure;
res := (others => 'X');
else
for I in res_type'range loop
res (I) := la (I) xor ra (I);
end loop;
end if;
return res;
end "xor";
function "xor" (l, r : SIGNED) return SIGNED
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : SIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""xor"": arguments are not of the same length"
severity failure;
res := (others => 'X');
else
for I in res_type'range loop
res (I) := la (I) xor ra (I);
end loop;
end if;
return res;
end "xor";
function ucompare (l, r : UNSIGNED) return compare_type
is
constant sz : integer := MAX (l'length, r'length) - 1;
alias la : UNSIGNED (l'length - 1 downto 0) is l;
alias ra : UNSIGNED (r'length - 1 downto 0) is r;
variable lb, rb : sl_x01;
variable res : compare_type;
begin
res := compare_eq;
for i in 0 to sz loop
if i > la'left then
lb := '0';
else
lb := sl_to_x01 (la (i));
end if;
if i > ra'left then
rb := '0';
else
rb := sl_to_x01 (ra (i));
end if;
if lb = 'X' or rb = 'X' then
return compare_unknown;
end if;
if lb = '1' and rb = '0' then
res := compare_gt;
elsif lb = '0' and rb = '1' then
res := compare_lt;
end if;
end loop;
return res;
end ucompare;
function scompare (l, r : SIGNED) return compare_type
is
constant sz : integer := MAX (l'length, r'length) - 1;
alias la : SIGNED (l'length - 1 downto 0) is l;
alias ra : SIGNED (r'length - 1 downto 0) is r;
variable lb, rb : sl_x01;
variable res : compare_type;
begin
-- Consider sign bit as S * -(2**N).
lb := sl_to_x01 (la (la'left));
rb := sl_to_x01 (ra (ra'left));
if lb = '1' and rb = '0' then
return compare_lt;
elsif lb = '0' and rb = '1' then
return compare_gt;
else
res := compare_eq;
end if;
for i in 0 to sz - 1 loop
if i > la'left then
lb := l (l'left);
else
lb := sl_to_x01 (la (i));
end if;
if i > ra'left then
rb := r (r'left);
else
rb := sl_to_x01 (ra (i));
end if;
if lb = 'X' or rb = 'X' then
return compare_unknown;
end if;
if lb = '1' and rb = '0' then
res := compare_gt;
elsif lb = '0' and rb = '1' then
res := compare_lt;
end if;
end loop;
return res;
end scompare;
function ucompare (l : UNSIGNED; r : NATURAL) return compare_type
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : NATURAL;
variable rd : nat1;
variable lb, rb : sl_x01;
variable res : compare_type;
begin
res := compare_eq;
r1 := r;
for i in la'reverse_range loop
lb := sl_to_x01 (la (i));
r2 := r1 / 2;
rd := r1 - 2 * r2;
r1 := r2;
rb := nat1_to_01 (rd);
if lb = 'X' then
return compare_unknown;
end if;
if lb = '1' and rb = '0' then
res := compare_gt;
elsif lb = '0' and rb = '1' then
res := compare_lt;
end if;
end loop;
if r1 /= 0 then
res := compare_lt;
end if;
return res;
end ucompare;
function scompare (l : SIGNED; r : INTEGER) return compare_type
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : INTEGER;
variable rd : nat1;
constant rmsb : nat1 := boolean'pos(r < 0);
variable lb, rb : sl_x01;
variable res : compare_type;
begin
res := compare_eq;
r1 := r;
for i in la'reverse_range loop
lb := sl_to_x01 (la (i));
r2 := r1 / 2;
if r1 < 0 then
rd := 2 * r2 - r1;
r1 := r2 - rd;
else
rd := r1 - 2 * r2;
r1 := r2;
end if;
rb := nat1_to_01 (rd);
if lb = 'X' then
return compare_unknown;
end if;
if lb = '1' and rb = '0' then
res := compare_gt;
elsif lb = '0' and rb = '1' then
res := compare_lt;
end if;
end loop;
if sl_to_x01 (l (l'left)) = '1' then
if r >= 0 then
res := compare_lt;
end if;
else
if r < 0 then
res := compare_gt;
end if;
end if;
return res;
end scompare;
function "=" (l, r : UNSIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""="": non logical value detected"
severity warning;
return false;
end if;
return res = compare_eq;
end "=";
function "=" (l, r : SIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""="": non logical value detected"
severity warning;
return false;
end if;
return res = compare_eq;
end "=";
function "=" (l : UNSIGNED; r : NATURAL) return boolean
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : NATURAL;
variable rd : nat1;
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""="": non logical value detected"
severity warning;
return false;
end if;
return res = compare_eq;
end "=";
function "=" (l : NATURAL; r : UNSIGNED) return boolean
is
subtype res_type is UNSIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : NATURAL;
variable ld : nat1;
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (r, l);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""="": non logical value detected"
severity warning;
return false;
end if;
return compare_eq = res;
end "=";
function "=" (l : SIGNED; r : INTEGER) return boolean
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : INTEGER;
variable rd : nat1;
constant rmsb : nat1 := boolean'pos(r < 0);
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""="": non logical value detected"
severity warning;
return false;
end if;
return res = compare_eq;
end "=";
function "=" (l : INTEGER; r : SIGNED) return boolean
is
subtype res_type is SIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : INTEGER;
variable ld : nat1;
constant lmsb : nat1 := boolean'pos(l < 0);
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (r, l);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""="": non logical value detected"
severity warning;
return false;
end if;
return compare_eq = res;
end "=";
function "/=" (l, r : UNSIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""/="": non logical value detected"
severity warning;
return false;
end if;
return res /= compare_eq;
end "/=";
function "/=" (l, r : SIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""/="": non logical value detected"
severity warning;
return false;
end if;
return res /= compare_eq;
end "/=";
function "/=" (l : UNSIGNED; r : NATURAL) return boolean
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : NATURAL;
variable rd : nat1;
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""/="": non logical value detected"
severity warning;
return false;
end if;
return res /= compare_eq;
end "/=";
function "/=" (l : NATURAL; r : UNSIGNED) return boolean
is
subtype res_type is UNSIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : NATURAL;
variable ld : nat1;
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (r, l);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""/="": non logical value detected"
severity warning;
return false;
end if;
return compare_eq /= res;
end "/=";
function "/=" (l : SIGNED; r : INTEGER) return boolean
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : INTEGER;
variable rd : nat1;
constant rmsb : nat1 := boolean'pos(r < 0);
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""/="": non logical value detected"
severity warning;
return false;
end if;
return res /= compare_eq;
end "/=";
function "/=" (l : INTEGER; r : SIGNED) return boolean
is
subtype res_type is SIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : INTEGER;
variable ld : nat1;
constant lmsb : nat1 := boolean'pos(l < 0);
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (r, l);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""/="": non logical value detected"
severity warning;
return false;
end if;
return compare_eq /= res;
end "/=";
function ">" (l, r : UNSIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD."">"": non logical value detected"
severity warning;
return false;
end if;
return res > compare_eq;
end ">";
function ">" (l, r : SIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD."">"": non logical value detected"
severity warning;
return false;
end if;
return res > compare_eq;
end ">";
function ">" (l : UNSIGNED; r : NATURAL) return boolean
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : NATURAL;
variable rd : nat1;
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD."">"": non logical value detected"
severity warning;
return false;
end if;
return res > compare_eq;
end ">";
function ">" (l : NATURAL; r : UNSIGNED) return boolean
is
subtype res_type is UNSIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : NATURAL;
variable ld : nat1;
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (r, l);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD."">"": non logical value detected"
severity warning;
return false;
end if;
return compare_eq > res;
end ">";
function ">" (l : SIGNED; r : INTEGER) return boolean
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : INTEGER;
variable rd : nat1;
constant rmsb : nat1 := boolean'pos(r < 0);
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD."">"": non logical value detected"
severity warning;
return false;
end if;
return res > compare_eq;
end ">";
function ">" (l : INTEGER; r : SIGNED) return boolean
is
subtype res_type is SIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : INTEGER;
variable ld : nat1;
constant lmsb : nat1 := boolean'pos(l < 0);
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (r, l);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD."">"": non logical value detected"
severity warning;
return false;
end if;
return compare_eq > res;
end ">";
function ">=" (l, r : UNSIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD."">="": non logical value detected"
severity warning;
return false;
end if;
return res >= compare_eq;
end ">=";
function ">=" (l, r : SIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD."">="": non logical value detected"
severity warning;
return false;
end if;
return res >= compare_eq;
end ">=";
function ">=" (l : UNSIGNED; r : NATURAL) return boolean
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : NATURAL;
variable rd : nat1;
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD."">="": non logical value detected"
severity warning;
return false;
end if;
return res >= compare_eq;
end ">=";
function ">=" (l : NATURAL; r : UNSIGNED) return boolean
is
subtype res_type is UNSIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : NATURAL;
variable ld : nat1;
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (r, l);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD."">="": non logical value detected"
severity warning;
return false;
end if;
return compare_eq >= res;
end ">=";
function ">=" (l : SIGNED; r : INTEGER) return boolean
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : INTEGER;
variable rd : nat1;
constant rmsb : nat1 := boolean'pos(r < 0);
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD."">="": non logical value detected"
severity warning;
return false;
end if;
return res >= compare_eq;
end ">=";
function ">=" (l : INTEGER; r : SIGNED) return boolean
is
subtype res_type is SIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : INTEGER;
variable ld : nat1;
constant lmsb : nat1 := boolean'pos(l < 0);
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (r, l);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD."">="": non logical value detected"
severity warning;
return false;
end if;
return compare_eq >= res;
end ">=";
function "<" (l, r : UNSIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""<"": non logical value detected"
severity warning;
return false;
end if;
return res < compare_eq;
end "<";
function "<" (l, r : SIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""<"": non logical value detected"
severity warning;
return false;
end if;
return res < compare_eq;
end "<";
function "<" (l : UNSIGNED; r : NATURAL) return boolean
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : NATURAL;
variable rd : nat1;
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""<"": non logical value detected"
severity warning;
return false;
end if;
return res < compare_eq;
end "<";
function "<" (l : NATURAL; r : UNSIGNED) return boolean
is
subtype res_type is UNSIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : NATURAL;
variable ld : nat1;
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (r, l);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""<"": non logical value detected"
severity warning;
return false;
end if;
return compare_eq < res;
end "<";
function "<" (l : SIGNED; r : INTEGER) return boolean
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : INTEGER;
variable rd : nat1;
constant rmsb : nat1 := boolean'pos(r < 0);
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""<"": non logical value detected"
severity warning;
return false;
end if;
return res < compare_eq;
end "<";
function "<" (l : INTEGER; r : SIGNED) return boolean
is
subtype res_type is SIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : INTEGER;
variable ld : nat1;
constant lmsb : nat1 := boolean'pos(l < 0);
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (r, l);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""<"": non logical value detected"
severity warning;
return false;
end if;
return compare_eq < res;
end "<";
function "<=" (l, r : UNSIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""<="": non logical value detected"
severity warning;
return false;
end if;
return res <= compare_eq;
end "<=";
function "<=" (l, r : SIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""<="": non logical value detected"
severity warning;
return false;
end if;
return res <= compare_eq;
end "<=";
function "<=" (l : UNSIGNED; r : NATURAL) return boolean
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : NATURAL;
variable rd : nat1;
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""<="": non logical value detected"
severity warning;
return false;
end if;
return res <= compare_eq;
end "<=";
function "<=" (l : NATURAL; r : UNSIGNED) return boolean
is
subtype res_type is UNSIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : NATURAL;
variable ld : nat1;
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (r, l);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""<="": non logical value detected"
severity warning;
return false;
end if;
return compare_eq <= res;
end "<=";
function "<=" (l : SIGNED; r : INTEGER) return boolean
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : INTEGER;
variable rd : nat1;
constant rmsb : nat1 := boolean'pos(r < 0);
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""<="": non logical value detected"
severity warning;
return false;
end if;
return res <= compare_eq;
end "<=";
function "<=" (l : INTEGER; r : SIGNED) return boolean
is
subtype res_type is SIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : INTEGER;
variable ld : nat1;
constant lmsb : nat1 := boolean'pos(l < 0);
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (r, l);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""<="": non logical value detected"
severity warning;
return false;
end if;
return compare_eq <= res;
end "<=";
function shift_left (ARG : UNSIGNED; COUNT: NATURAL) return UNSIGNED
is
subtype res_type is UNSIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
begin
if res'length = 0 then
return null_UNSIGNED;
end if;
if count <= arg1'left then
res (res'left downto count) := arg1 (arg1'left - count downto 0);
end if;
return res;
end shift_left;
function shift_right (ARG : UNSIGNED; COUNT: NATURAL) return UNSIGNED
is
subtype res_type is UNSIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
begin
if res'length = 0 then
return null_UNSIGNED;
end if;
if count <= arg1'left then
res (res'left - count downto 0) := arg1 (arg1'left downto count);
end if;
return res;
end shift_right;
function rotate_left (ARG : UNSIGNED; COUNT: natural) return UNSIGNED
is
subtype res_type is UNSIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
variable cnt : natural;
begin
if res'length = 0 then
return null_UNSIGNED;
end if;
cnt := count rem res'length;
res (res'left downto cnt) := arg1 (res'left - cnt downto 0);
res (cnt - 1 downto 0) := arg1 (res'left downto res'left - cnt + 1);
return res;
end rotate_left;
function rotate_right (ARG : UNSIGNED; COUNT: natural) return UNSIGNED
is
subtype res_type is UNSIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
variable cnt : natural;
begin
if res'length = 0 then
return null_UNSIGNED;
end if;
cnt := count rem res'length;
res (res'left - cnt downto 0) := arg1 (res'left downto cnt);
res (res'left downto res'left - cnt + 1) := arg1 (cnt - 1 downto 0);
return res;
end rotate_right;
function shift_left (ARG : SIGNED; COUNT: NATURAL) return SIGNED
is
subtype res_type is SIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
begin
if res'length = 0 then
return null_SIGNED;
end if;
if count <= arg1'left then
res (res'left downto count) := arg1 (arg1'left - count downto 0);
end if;
return res;
end shift_left;
function shift_right (ARG : SIGNED; COUNT: NATURAL) return SIGNED
is
subtype res_type is SIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => arg1 (arg1'left));
begin
if res'length = 0 then
return null_SIGNED;
end if;
if count <= arg1'left then
res (res'left - count downto 0) := arg1 (arg1'left downto count);
end if;
return res;
end shift_right;
function rotate_left (ARG : SIGNED; COUNT: natural) return SIGNED
is
subtype res_type is SIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
variable cnt : natural;
begin
if res'length = 0 then
return null_SIGNED;
end if;
cnt := count rem res'length;
res (res'left downto cnt) := arg1 (res'left - cnt downto 0);
res (cnt - 1 downto 0) := arg1 (res'left downto res'left - cnt + 1);
return res;
end rotate_left;
function rotate_right (ARG : SIGNED; COUNT: natural) return SIGNED
is
subtype res_type is SIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
variable cnt : natural;
begin
if res'length = 0 then
return null_SIGNED;
end if;
cnt := count rem res'length;
res (res'left - cnt downto 0) := arg1 (res'left downto cnt);
res (res'left downto res'left - cnt + 1) := arg1 (cnt - 1 downto 0);
return res;
end rotate_right;
end NUMERIC_STD;
| gpl-2.0 | 8362800dd12fdbc988ebf5aa85082428 | 0.544514 | 3.70841 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue317/PoC/tb/common/config_tb.vhdl | 2 | 4,154 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Patrick Lehmann
--
-- Testbench: Tests global constants, functions and settings
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair of VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
use PoC.config.all;
use PoC.utils.all;
-- simulation only packages
use PoC.sim_types.all;
use PoC.simulation.all;
entity config_tb is
end config_tb;
architecture tb of config_tb is
signal SimQuiet : boolean := true;
begin
procChecker : process
constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Checker");
begin
if not SimQuiet then
report "is simulation?: " & boolean'image(SIMULATION) severity note;
report "Vendor: " & T_VENDOR'image(VENDOR) severity note;
report "Device: " & T_DEVICE'image(DEVICE) severity note;
report "Device Family: " & T_DEVICE_FAMILY'image(DEVICE_FAMILY) severity note;
report "Device Subtype: " & T_DEVICE_SUBTYPE'image(DEVICE_SUBTYPE) severity note;
report "Device Series: " & T_DEVICE_SERIES'image(DEVICE_SERIES) severity note;
report "Device Generation: " & integer'image(DEVICE_GENERATION) severity note;
report "Device Number: " & integer'image(DEVICE_NUMBER) severity note;
report "--------------------------------------------------" severity note;
report "LUT fan-in: " & integer'image(LUT_FANIN) severity note;
report "Transceiver: " & T_TRANSCEIVER'image(TRANSCEIVER_TYPE) severity note;
end if;
simAssertion((SIMULATION = TRUE), "SIMULATION=" & boolean'image(SIMULATION) & " Expected=TRUE");
simAssertion((VENDOR = VENDOR_GENERIC), "VENDOR= " & T_VENDOR'image(VENDOR) & " Expected=VENDOR_XILINX");
simAssertion((DEVICE = DEVICE_GENERIC), "DEVICE=" & T_DEVICE'image(DEVICE) & " Expected=DEVICE_KINTEX7");
simAssertion((DEVICE_FAMILY = DEVICE_FAMILY_GENERIC), "DEVICE_FAMILY=" & T_DEVICE_FAMILY'image(DEVICE_FAMILY) & " Expected=DEVICE_FAMILY_KINTEX");
simAssertion((DEVICE_NUMBER = 0), "DEVICE_NUMBER=" & integer'image(DEVICE_NUMBER) & " Expected=325");
simAssertion((DEVICE_SUBTYPE = DEVICE_SUBTYPE_GENERIC), "DEVICE_SUBTYPE=" & T_DEVICE_SUBTYPE'image(DEVICE_SUBTYPE) & " Expected=DEVICE_SUBTYPE_T");
simAssertion((DEVICE_GENERATION = 0), "DEVICE_GENERATION=" & integer'image(DEVICE_GENERATION) & " Expected=7");
simAssertion((DEVICE_SERIES = DEVICE_SERIES_GENERIC), "DEVICE_SERIES=" & T_DEVICE_SERIES'image(DEVICE_SERIES) & " Expected=DEVICE_SERIES_7_SERIES");
simAssertion((LUT_FANIN = 6), "LUT_FANIN=" & integer'image(LUT_FANIN) & " Expected=6");
simAssertion((TRANSCEIVER_TYPE = TRANSCEIVER_GENERIC), "TRANSCEIVER_TYPE=" & T_TRANSCEIVER'image(TRANSCEIVER_TYPE) & " Expected=TRANSCEIVER_GTXE2");
-- This process is finished
simDeactivateProcess(simProcessID);
wait; -- forever
end process;
end architecture;
| gpl-2.0 | a70d0971a49a8735c3daa1aea5d2fa5b | 0.612422 | 3.732255 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc479.vhd | 4 | 3,296 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc479.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00479ent IS
END c03s02b01x01p19n01i00479ent;
ARCHITECTURE c03s02b01x01p19n01i00479arch OF c03s02b01x01p19n01i00479ent IS
type integer_vector is array (natural range <>) of integer;
function resolution5(i:in integer_vector) return integer is
variable temp : integer := 3;
begin
return temp;
end resolution5;
subtype integer_state is resolution5 integer;
constant C66 : integer_state := 3;
function complex_scalar(s : integer_state) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return integer_state is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : integer_state;
signal S2 : integer_state;
signal S3 : integer_state:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00479"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00479 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00479arch;
| gpl-2.0 | b7cddcf79afcea8d4c9158a3eb0df1ba | 0.657767 | 3.699214 | false | true | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3154.vhd | 4 | 2,685 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3154.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s03b00x00p01n01i03154ent IS
END c05s03b00x00p01n01i03154ent;
ARCHITECTURE c05s03b00x00p01n01i03154arch OF c05s03b00x00p01n01i03154ent IS
-- Define res function for SIG:
function RESFUNC( S : BIT_VECTOR ) return BIT is
begin
for I in S'RANGE loop
if (S(I) = '1') then
return '1';
end if;
end loop;
return '0';
end RESFUNC;
-- Define the signal.
subtype RBIT is RESFUNC BIT;
signal SIG : RBIT bus;
-- Define the disconnect specification.
disconnect SIG : RBIT after 0 ns;
-- Define the GUARD signal.
signal GUARD : BOOLEAN := FALSE;
BEGIN
-- Define the guarded signal assignment.
L1: block
begin
SIG <= guarded '1';
end block L1;
TESTING: PROCESS
variable pass : integer := 0;
BEGIN
-- 1. Turn on the GUARD, verify that SIG gets toggled.
GUARD <= TRUE;
wait on SIG;
assert( SIG = '1' );
if ( SIG = '1' ) then
pass := pass + 1;
end if;
-- 2. Turn off the GUARD, verify that SIG gets turned OFF.
GUARD <= FALSE;
wait on SIG;
assert( SIG = '0' );
if ( SIG = '0' ) then
pass := pass + 1;
end if;
wait for 50 ns;
assert NOT( pass = 2 )
report "***PASSED TEST: c05s03b00x00p01n01i03154"
severity NOTE;
assert ( pass = 2 )
report "***FAILED TEST: c05s03b00x00p01n01i03154 - Disconnect does not work properly."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s03b00x00p01n01i03154arch;
| gpl-2.0 | 82d90726b89383822706bc120c6189c7 | 0.626443 | 3.678082 | false | true | false | false |
nickg/nvc | test/regress/issue405.vhd | 1 | 1,905 | entity buf is
port ( a : in bit; y : out bit );
end entity;
architecture test of buf is
begin
y <= a after 1 ns;
end architecture;
-------------------------------------------------------------------------------
entity fanout_tree is
generic ( h : natural; d : positive );
port ( input : in bit; output : out bit_vector (0 to d**h - 1) );
end fanout_tree;
architecture recursive of fanout_tree is
component buf
port ( a : in bit; y : out bit );
end component;
component fanout_tree
generic ( h : natural; d : positive );
port ( input : in bit; output : out bit_vector(0 to d**h - 1) );
end component;
signal buffered_input : bit_vector(0 to d - 1);
begin
degenerate_tree : if h = 0 generate
output(0) <= input;
end generate degenerate_tree;
compound_tree : if h > 0 generate
subtree_array : for i in 0 to d - 1 generate
the_buffer : buf
port map ( a => input, y => buffered_input(i) );
the_subtree : fanout_tree
generic map ( h => h - 1, d => d )
port map ( input => buffered_input(i),
output => output(i * d**(h-1) to (i+1) * d**(h-1) -1) );
end generate subtree_array;
end generate compound_tree;
end recursive;
-------------------------------------------------------------------------------
entity issue405 is
end entity;
architecture test of issue405 is
signal input : bit;
signal output : bit_vector(0 to 4**3 - 1);
begin
top_i: entity work.fanout_tree
generic map ( h => 3, d => 4 )
port map ( input, output );
check: process is
begin
wait for 5 ns;
assert output = (output'range => '0');
input <= '1';
wait for 5 ns;
assert output = (output'range => '1');
wait;
end process;
end architecture;
| gpl-3.0 | 4367929deef862a6c87a3af790e5fab7 | 0.508136 | 3.919753 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue17/cond_assign_var.vhdl | 2 | 615 | library ieee ;
use ieee.std_logic_1164.all ;
use std.textio.all ;
entity cond_assign_var is
end entity cond_assign_var ;
architecture doit of cond_assign_var is
signal Clk : std_logic := '0' ;
signal Y : std_logic ;
begin
Clk <= not Clk after 10 ns ;
process (Clk)
variable A : std_logic ;
begin
A := 'H' when Clk = '1' else 'L' ;
Y <= A ;
-- Y <= 'H' when Clk = '1' else 'L' ;
end process ;
-- Y <= 'H' when Clk = '1' else 'L' ;
process
begin
wait for 500 ns ;
std.env.stop ;
end process ;
end architecture doit ;
| gpl-2.0 | 64f746810d06599e30f06119bfd87a54 | 0.539837 | 3.121827 | false | false | false | false |
tgingold/ghdl | testsuite/synth/fsm01/tb_fsm_7s.vhdl | 1 | 909 | entity tb_fsm_7s is
end tb_fsm_7s;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_fsm_7s is
signal clk : std_logic;
signal rst : std_logic;
signal din : std_logic;
signal done : std_logic;
begin
dut: entity work.fsm_7s
port map (
done => done,
d => din,
clk => clk,
rst => rst);
process
constant dat : std_logic_vector := b"1001010_1001010_1100010";
constant res : std_logic_vector := b"0000001_0000001_0000000";
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rst <= '1';
din <= '0';
pulse;
assert done = '0' severity failure;
-- Test the whole sequence.
rst <= '0';
for i in dat'range loop
din <= dat (i);
pulse;
assert done = res(i) severity failure;
end loop;
wait;
end process;
end behav;
| gpl-2.0 | 0b41b188cd2416817a51a2771b177923 | 0.575358 | 3.341912 | false | false | false | false |
lfmunoz/vhdl | ip_blocks/sip_router_async_s1d2_x4_b/src/sip_router_async_s1d2_x4_b.vhd | 1 | 18,383 |
-------------------------------------------------------------------------------------
-- FILE NAME : sip_router_async_s1d2_x4_b.vhd
--
-- AUTHOR : StellarIP (c) 4DSP
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity - sip_router_async_s1d2_x4_b
-- architecture - arch_sip_router_async_s1d2_x4_b
--
-- LANGUAGE : VHDL
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
-- sip_router_async_s1d2_x4_b
-- Notes: sip_router_async_s1d2_x4_b
-------------------------------------------------------------------------------------
-- Disclaimer: LIMITED WARRANTY AND DISCLAIMER. These designs are
-- provided to you as is. 4DSP specifically disclaims any
-- implied warranties of merchantability, non-infringement, or
-- fitness for a particular purpose. 4DSP does not warrant that
-- the functions contained in these designs will meet your
-- requirements, or that the operation of these designs will be
-- uninterrupted or error free, or that defects in the Designs
-- will be corrected. Furthermore, 4DSP does not warrant or
-- make any representations regarding use or the results of the
-- use of the designs in terms of correctness, accuracy,
-- reliability, or otherwise.
--
-- LIMITATION OF LIABILITY. In no event will 4DSP or its
-- licensors be liable for any loss of data, lost profits, cost
-- or procurement of substitute goods or services, or for any
-- special, incidental, consequential, or indirect damages
-- arising from the use or operation of the designs or
-- accompanying documentation, however caused and on any theory
-- of liability. This limitation will apply even if 4DSP
-- has been advised of the possibility of such damage. This
-- limitation shall apply not-withstanding the failure of the
-- essential purpose of any limited remedies herein.
--
----------------------------------------------
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
--library declaration
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_misc.all ;
-------------------------------------------------------------------------------------
--Entity Declaration
-------------------------------------------------------------------------------------
entity sip_router_async_s1d2_x4_b is
generic (
global_start_addr_gen : std_logic_vector(27 downto 0);
global_stop_addr_gen : std_logic_vector(27 downto 0);
private_start_addr_gen : std_logic_vector(27 downto 0);
private_stop_addr_gen : std_logic_vector(27 downto 0)
);
port (
--Wormhole 'cmdclk_in' of type 'cmdclk_in':
cmdclk_in_cmdclk : in std_logic;
--Wormhole 'cmd_in' of type 'cmd_in':
cmd_in_cmdin : in std_logic_vector(63 downto 0);
cmd_in_cmdin_val : in std_logic;
--Wormhole 'cmd_out' of type 'cmd_out':
cmd_out_cmdout : out std_logic_vector(63 downto 0);
cmd_out_cmdout_val : out std_logic;
--Wormhole 'clk' of type 'clkin':
clk_clkin : in std_logic_vector(31 downto 0);
--Wormhole 'rst' of type 'rst_in':
rst_rstin : in std_logic_vector(31 downto 0);
--Wormhole 'in0' of type 'wh_in':
in0_in_stop : out std_logic;
in0_in_dval : in std_logic;
in0_in_data : in std_logic_vector(63 downto 0);
--Wormhole 'in1' of type 'wh_in':
in1_in_stop : out std_logic;
in1_in_dval : in std_logic;
in1_in_data : in std_logic_vector(63 downto 0);
--Wormhole 'in2' of type 'wh_in':
in2_in_stop : out std_logic;
in2_in_dval : in std_logic;
in2_in_data : in std_logic_vector(63 downto 0);
--Wormhole 'in3' of type 'wh_in':
in3_in_stop : out std_logic;
in3_in_dval : in std_logic;
in3_in_data : in std_logic_vector(63 downto 0);
--Wormhole 'out0_0' of type 'wh_out':
out0_0_out_stop : in std_logic;
out0_0_out_dval : out std_logic;
out0_0_out_data : out std_logic_vector(63 downto 0);
--Wormhole 'out1_0' of type 'wh_out':
out1_0_out_stop : in std_logic;
out1_0_out_dval : out std_logic;
out1_0_out_data : out std_logic_vector(63 downto 0);
--Wormhole 'out2_0' of type 'wh_out':
out2_0_out_stop : in std_logic;
out2_0_out_dval : out std_logic;
out2_0_out_data : out std_logic_vector(63 downto 0);
--Wormhole 'out3_0' of type 'wh_out':
out3_0_out_stop : in std_logic;
out3_0_out_dval : out std_logic;
out3_0_out_data : out std_logic_vector(63 downto 0);
--Wormhole 'out0_1' of type 'wh_out':
out0_1_out_stop : in std_logic;
out0_1_out_dval : out std_logic;
out0_1_out_data : out std_logic_vector(63 downto 0);
--Wormhole 'out1_1' of type 'wh_out':
out1_1_out_stop : in std_logic;
out1_1_out_dval : out std_logic;
out1_1_out_data : out std_logic_vector(63 downto 0);
--Wormhole 'out2_1' of type 'wh_out':
out2_1_out_stop : in std_logic;
out2_1_out_dval : out std_logic;
out2_1_out_data : out std_logic_vector(63 downto 0);
--Wormhole 'out3_1' of type 'wh_out':
out3_1_out_stop : in std_logic;
out3_1_out_dval : out std_logic;
out3_1_out_data : out std_logic_vector(63 downto 0)
);
end entity sip_router_async_s1d2_x4_b;
-------------------------------------------------------------------------------------
--Architecture declaration
-------------------------------------------------------------------------------------
architecture arch_sip_router_async_s1d2_x4_b of sip_router_async_s1d2_x4_b is
-------------------------------------------------------------------------------------
--Constants declaration
-------------------------------------------------------------------------------------
constant CLK_INDEX_S0 : natural := 13;
constant CLK_INDEX_D0 : natural := 13;
constant CLK_INDEX_D1 : natural := 14;
constant DATA_WIDTH : natural := 64;
-------------------------------------------------------------------------------------
--Components Declaration
-------------------------------------------------------------------------------------
component sip_router_async_s1d2_x4_b_regs
generic
(
start_addr :std_logic_vector(27 downto 0):=x"0000000";
stop_addr :std_logic_vector(27 downto 0):=x"0000001"
);
port
(
reset :in std_logic;
--command if
clk_cmd :in std_logic; --cmd_in and cmd_out are synchronous to this clock;
out_cmd :out std_logic_vector(63 downto 0);
out_cmd_val :out std_logic;
in_cmd :in std_logic_vector(63 downto 0);
in_cmd_val :in std_logic;
--register interface
clk_reg :in std_logic;
reg0000 :out std_logic_vector(31 downto 0);
reg0001 :out std_logic_vector(31 downto 0)
);
end component;
COMPONENT fifo_async_fwft_64x513_v8_2
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT;
-------------------------------------------------------------------------------------
--Signal declaration
-------------------------------------------------------------------------------------
type std_lv_10 is array (natural range <>) of std_logic_vector(9 downto 0);
type std_lv_DATA_WIDTH is array (natural range <>) of std_logic_vector((DATA_WIDTH - 1) downto 0);
signal control_0 : std_logic_vector(31 downto 0);
signal d0_control_0_cc : std_logic_vector(31 downto 0);
signal d0_control_0 : std_logic_vector(31 downto 0);
signal d1_control_0_cc : std_logic_vector(31 downto 0);
signal d1_control_0 : std_logic_vector(31 downto 0);
signal s0_reset : std_logic_vector(2 downto 0);
signal d0_reset : std_logic_vector(2 downto 0);
signal d1_reset : std_logic_vector(2 downto 0);
signal wh_in_stop : std_logic_vector(0 to 3);
signal wh_in_dval : std_logic_vector(0 to 3);
signal wh_in_data : std_lv_DATA_WIDTH(0 to 3);
signal wh_out_0_stop : std_logic_vector(0 to 3);
signal wh_out_0_dval : std_logic_vector(0 to 3);
signal wh_out_0_data : std_lv_DATA_WIDTH(0 to 3);
signal wh_out_1_stop : std_logic_vector(0 to 3);
signal wh_out_1_dval : std_logic_vector(0 to 3);
signal wh_out_1_data : std_lv_DATA_WIDTH(0 to 3);
signal fifo_d0_wr_en : std_logic_vector(0 to 3);
signal fifo_d0_rd_en : std_logic_vector(0 to 3);
signal fifo_d0_dout : std_lv_DATA_WIDTH(0 to 3);
signal fifo_d0_valid : std_logic_vector(0 to 3);
signal fifo_d0_wr_data_count : std_lv_10(0 to 3);
signal fifo_d1_wr_en : std_logic_vector(0 to 3);
signal fifo_d1_rd_en : std_logic_vector(0 to 3);
signal fifo_d1_dout : std_lv_DATA_WIDTH(0 to 3);
signal fifo_d1_valid : std_logic_vector(0 to 3);
signal fifo_d1_wr_data_count : std_lv_10(0 to 3);
begin
-----------------------------------------------------------------------------------
--component instantiations
-----------------------------------------------------------------------------------
i_sip_router_async_s1d2_x4_b_regs:sip_router_async_s1d2_x4_b_regs
generic map
(
start_addr =>private_start_addr_gen,
stop_addr =>private_stop_addr_gen
)
port map
(
reset =>rst_rstin(2),
clk_cmd =>cmdclk_in_cmdclk,
out_cmd =>cmd_out_cmdout,
out_cmd_val =>cmd_out_cmdout_val,
in_cmd =>cmd_in_cmdin,
in_cmd_val =>cmd_in_cmdin_val,
clk_reg =>clk_clkin(CLK_INDEX_S0),
reg0000 =>open, --control_0,
reg0001 =>open
);
control_0 <= x"00000001";
-----------------------------------------------------
-- Source 0
-----------------------------------------------------
process(rst_rstin(2), clk_clkin(CLK_INDEX_S0))
begin
-- Local reset
if rst_rstin(2) = '1' then
s0_reset <= (others => '1');
elsif rising_edge(clk_clkin(CLK_INDEX_S0)) then
s0_reset <= s0_reset(1 downto 0) & '0';
end if;
end process;
process(clk_clkin(CLK_INDEX_S0))
begin
if rising_edge(clk_clkin(CLK_INDEX_S0)) then
if s0_reset(2) = '1' then
wh_in_stop <= (others => '1');
wh_in_dval <= (others => '0');
fifo_d0_wr_en <= "0000";
fifo_d1_wr_en <= "0000";
else
-- Register inputs
fifo_d0_wr_en(0) <= in0_in_dval and (not control_0(0));
fifo_d0_wr_en(1) <= in1_in_dval and (not control_0(0));
fifo_d0_wr_en(2) <= in2_in_dval and (not control_0(0));
fifo_d0_wr_en(3) <= in3_in_dval and (not control_0(0));
fifo_d1_wr_en(0) <= in0_in_dval and ( control_0(0));
fifo_d1_wr_en(1) <= in1_in_dval and ( control_0(0));
fifo_d1_wr_en(2) <= in2_in_dval and ( control_0(0));
fifo_d1_wr_en(3) <= in3_in_dval and ( control_0(0));
wh_in_data(0) <= in0_in_data;
wh_in_data(1) <= in1_in_data;
wh_in_data(2) <= in2_in_data;
wh_in_data(3) <= in3_in_data;
-- Register outputs
for i in 0 to 3 loop
if control_0(0) = '0' then
wh_in_stop(i) <= and_reduce(fifo_d0_wr_data_count(i)(8 downto 7));
else
wh_in_stop(i) <= and_reduce(fifo_d1_wr_data_count(i)(8 downto 7));
end if;
end loop;
end if;
end if;
end process;
in0_in_stop <= wh_in_stop(0);
in1_in_stop <= wh_in_stop(1);
in2_in_stop <= wh_in_stop(2);
in3_in_stop <= wh_in_stop(3);
gen_fifos:
for i in 0 to 3 generate
-- If the source and destinantion clock domains are the same then
-- the fifo could probably be replaced with a register
-- if CLK_INDEX_S0 = CLK_INDEX_D0 generate ....
fifo_d0:
fifo_async_fwft_64x513_v8_2
PORT MAP (
rst => rst_rstin(2),
wr_clk => clk_clkin(CLK_INDEX_S0),
rd_clk => clk_clkin(CLK_INDEX_D0),
din => wh_in_data(i),
wr_en => fifo_d0_wr_en(i),
rd_en => fifo_d0_rd_en(i),
dout => fifo_d0_dout(i),
full => open,
empty => open,
valid => fifo_d0_valid(i),
rd_data_count => open,
wr_data_count => fifo_d0_wr_data_count(i)
);
fifo_d1:
fifo_async_fwft_64x513_v8_2
PORT MAP (
rst => rst_rstin(2),
wr_clk => clk_clkin(CLK_INDEX_S0),
rd_clk => clk_clkin(CLK_INDEX_D1),
din => wh_in_data(i),
wr_en => fifo_d1_wr_en(i),
rd_en => fifo_d1_rd_en(i),
dout => fifo_d1_dout(i),
full => open,
empty => open,
valid => fifo_d1_valid(i),
rd_data_count => open,
wr_data_count => fifo_d1_wr_data_count(i)
);
fifo_d0_rd_en(i) <= (not wh_out_0_stop(i)) and (not d0_control_0(0)) and fifo_d0_valid(i);
fifo_d1_rd_en(i) <= (not wh_out_1_stop(i)) and ( d1_control_0(0)) and fifo_d1_valid(i);
end generate;
-----------------------------------------------------
-- Destination 0
-----------------------------------------------------
process(rst_rstin(2), clk_clkin(CLK_INDEX_D0))
begin
-- Local reset
if rst_rstin(2) = '1' then
d0_reset <= (others => '1');
elsif rising_edge(clk_clkin(CLK_INDEX_D0)) then
d0_reset <= d0_reset(1 downto 0) & '0';
end if;
end process;
process(clk_clkin(CLK_INDEX_D0))
begin
if rising_edge(clk_clkin(CLK_INDEX_D0)) then
-- Cross clock
d0_control_0_cc <= control_0;
d0_control_0 <= d0_control_0_cc;
if d0_reset(2) = '1' then
wh_out_0_stop <= (others => '1');
wh_out_0_dval <= (others => '0');
else
-- Register inputs
wh_out_0_stop(0) <= out0_0_out_stop;
wh_out_0_stop(1) <= out1_0_out_stop;
wh_out_0_stop(2) <= out2_0_out_stop;
wh_out_0_stop(3) <= out3_0_out_stop;
for i in 0 to 3 loop
wh_out_0_dval(i) <= fifo_d0_rd_en(i); --fifo_d0_valid(i);
wh_out_0_data(i) <= fifo_d0_dout(i);
end loop;
end if;
end if;
end process;
out0_0_out_dval <= wh_out_0_dval(0);
out1_0_out_dval <= wh_out_0_dval(1);
out2_0_out_dval <= wh_out_0_dval(2);
out3_0_out_dval <= wh_out_0_dval(3);
out0_0_out_data <= wh_out_0_data(0);
out1_0_out_data <= wh_out_0_data(1);
out2_0_out_data <= wh_out_0_data(2);
out3_0_out_data <= wh_out_0_data(3);
-----------------------------------------------------
-- Destination 1
-----------------------------------------------------
process(rst_rstin(2), clk_clkin(CLK_INDEX_D1))
begin
-- Local reset
if rst_rstin(2) = '1' then
d1_reset <= (others => '1');
elsif rising_edge(clk_clkin(CLK_INDEX_D1)) then
d1_reset <= d1_reset(1 downto 0) & '0';
end if;
end process;
process(clk_clkin(CLK_INDEX_D1))
begin
if rising_edge(clk_clkin(CLK_INDEX_D1)) then
-- Cross clock
d1_control_0_cc <= control_0;
d1_control_0 <= d1_control_0_cc;
if d1_reset(2) = '1' then
wh_out_1_stop <= (others => '1');
wh_out_1_dval <= (others => '0');
else
-- Register inputs
wh_out_1_stop(0) <= out0_1_out_stop;
wh_out_1_stop(1) <= out1_1_out_stop;
wh_out_1_stop(2) <= out2_1_out_stop;
wh_out_1_stop(3) <= out3_1_out_stop;
for i in 0 to 3 loop
wh_out_1_dval(i) <= fifo_d1_rd_en(i); --fifo_d1_valid(i);
wh_out_1_data(i) <= fifo_d1_dout(i);
end loop;
end if;
end if;
end process;
out0_1_out_dval <= wh_out_1_dval(0);
out1_1_out_dval <= wh_out_1_dval(1);
out2_1_out_dval <= wh_out_1_dval(2);
out3_1_out_dval <= wh_out_1_dval(3);
out0_1_out_data <= wh_out_1_data(0);
out1_1_out_data <= wh_out_1_data(1);
out2_1_out_data <= wh_out_1_data(2);
out3_1_out_data <= wh_out_1_data(3);
end architecture arch_sip_router_async_s1d2_x4_b ; -- of sip_router_async_s1d2_x4_b
| mit | bbf9db93e4c498661665005072783a13 | 0.468368 | 3.391072 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug084/func_test1.vhdl | 1 | 1,946 | library ieee;
use ieee.std_logic_1164.all;
package subp_type_decl is
constant NBITS: natural := 6;
function mod5 (dividend: std_logic_vector) return std_logic;
end package;
package body subp_type_decl is
function mod5 (dividend: std_logic_vector) return std_logic is
type remains is (r0, r1, r2, r3, r4); -- remainder values
type remain_array is array (NBITS downto 0) of remains;
type branch is array (remains, bit) of remains;
constant br_table: branch := ( r0 => ('0' => r0, '1' => r1),
r1 => ('0' => r2, '1' => r3),
r2 => ('0' => r4, '1' => r0),
r3 => ('0' => r1, '1' => r2),
r4 => ('0' => r3, '1' => r4)
);
variable remaind: remain_array := (others => r0);
variable tbit: bit_vector (NBITS - 1 downto 0);
begin
tbit := to_bitvector(dividend); -- little endian
for i in dividend'length - 1 downto 0 loop
remaind(i) := br_table(remaind(i + 1),tbit(i));
end loop;
if remaind(0) = r0 then
return '1';
else
return '0';
end if;
end function;
end package body;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.subp_type_decl.all;
entity func_test1 is
end entity;
architecture fum of func_test1 is
signal dividend: std_logic_vector (NBITS - 1 downto 0);
begin
process
variable errors: natural;
begin
errors := 0;
for i in 0 to 2 ** NBITS - 1 loop
dividend <= std_logic_vector(to_unsigned(i, NBITS));
wait for 0 ns;
report "mod5 (" & integer'image(i) & ") = " &
std_ulogic'image(mod5(dividend));
end loop;
wait;
end process;
end architecture;
| gpl-2.0 | aeacbca1724513dc73f5fc8a3ccb3bd4 | 0.510791 | 3.644195 | false | false | false | false |
nickg/nvc | test/regress/genpack11.vhd | 1 | 1,008 | package pack is generic ( x : string := "foo" ) ;
constant s : string := x ;
constant k : integer;
end package ;
package body pack is
constant k : integer := 42;
end package body;
-------------------------------------------------------------------------------
package pack2 is
function get_str return string;
constant kk : integer;
end package ;
package body pack2 is
package pack3 is new work.pack generic map (x => "bar") ;
use pack3.all;
function get_str return string is
begin
return pack3.s;
end function;
constant kk : integer := pack3.k + 1;
end package body ;
-------------------------------------------------------------------------------
entity genpack11 is
end entity;
use work.pack2.all;
architecture test of genpack11 is
signal s : string(1 to 3) := "bar";
begin
p1: process is
begin
assert get_str = "bar";
assert get_str = s;
assert kk = 43;
wait;
end process;
end architecture;
| gpl-3.0 | 193a40a9660b624fa06aed622c392393 | 0.52381 | 4.182573 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue317/PoC/src/common/components.vhdl | 2 | 12,848 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: Common primitives described as a function
--
-- Description:
-- -------------------------------------
-- This packages describes common primitives like flip flops and multiplexers
-- as a function to use them as one-liners.
--
-- ATTENSION:
-- The parameter 'constant INIT' of some functions is actually the reset
-- value, not the initial value after device programming (e.g. for FPGAs),
-- this value MUST be set via signal declaration!
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair of VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
package components is
-- implement an optional register stage
function registered(signal Clock : std_logic; constant IsRegistered : boolean) return boolean;
-- FlipFlop functions
-- ===========================================================================
-- RS-FlipFlops
function ffrs(q : std_logic; rst : std_logic := '0'; set : std_logic := '0') return std_logic; -- RS-FlipFlop with dominant rst
function ffsr(q : std_logic; rst : std_logic := '0'; set : std_logic := '0') return std_logic; -- RS-FlipFlop with dominant set
-- D-FlipFlops (Delay)
function ffdre(q : std_logic; d : std_logic; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : std_logic := '0') return std_logic; -- D-FlipFlop with reset and enable
function ffdre(q : std_logic_vector; d : std_logic_vector; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : std_logic_vector := (0 to 0 => '0')) return std_logic_vector; -- D-FlipFlop with reset and enable
function ffdse(q : std_logic; d : std_logic; set : std_logic := '0'; en : std_logic := '1') return std_logic; -- D-FlipFlop with set and enable
-- T-FlipFlops (Toggle)
function fftre(q : std_logic; t : std_logic; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : std_logic := '0') return std_logic; -- T-FlipFlop with reset and enable
function fftse(q : std_logic; t : std_logic; set : std_logic := '0'; en : std_logic := '1') return std_logic; -- T-FlipFlop with set and enable
-- counter
function upcounter_next(cnt : unsigned; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : natural := 0) return unsigned;
function upcounter_equal(cnt : unsigned; value : natural) return std_logic;
function downcounter_next(cnt : signed; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : integer := 0) return signed;
function downcounter_equal(cnt : signed; value : integer) return std_logic;
function downcounter_neg(cnt : signed) return std_logic;
-- shiftregisters
function shreg_left(q : std_logic_vector; i : std_logic; en : std_logic := '1') return std_logic_vector;
function shreg_right(q : std_logic_vector; i : std_logic; en : std_logic := '1') return std_logic_vector;
-- rotate registers
function rreg_left(q : std_logic_vector; en : std_logic := '1') return std_logic_vector;
function rreg_right(q : std_logic_vector; en : std_logic := '1') return std_logic_vector;
-- compare
function comp(value1 : std_logic_vector; value2 : std_logic_vector) return std_logic_vector;
function comp(value1 : unsigned; value2 : unsigned) return unsigned;
function comp(value1 : signed; value2 : signed) return signed;
function comp_allzero(value : std_logic_vector) return std_logic;
function comp_allzero(value : unsigned) return std_logic;
function comp_allzero(value : signed) return std_logic;
function comp_allone(value : std_logic_vector) return std_logic;
function comp_allone(value : unsigned) return std_logic;
function comp_allone(value : signed) return std_logic;
-- multiplexing
function mux(sel : std_logic; sl0 : std_logic; sl1 : std_logic) return std_logic;
function mux(sel : std_logic; slv0 : std_logic_vector; slv1 : std_logic_vector) return std_logic_vector;
function mux(sel : std_logic; us0 : unsigned; us1 : unsigned) return unsigned;
function mux(sel : std_logic; s0 : signed; s1 : signed) return signed;
end package;
package body components is
-- implement an optional register stage
-- ===========================================================================
function registered(signal Clock : std_logic; constant IsRegistered : boolean) return boolean is
begin
return ite(IsRegistered, rising_edge(Clock), TRUE);
end function;
-- FlipFlops
-- ===========================================================================
-- D-flipflop with reset and enable
function ffdre(q : std_logic; d : std_logic; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : std_logic := '0') return std_logic is
begin
if not SIMULATION then
if (INIT = '0') then
return ((d and en) or (q and not en)) and not rst;
elsif (INIT = '1') then
return ((d and en) or (q and not en)) or rst;
else
report "Unsupported INIT value for synthesis." severity FAILURE;
return 'X';
end if;
elsif (rst = '1') then
return INIT;
else
return ((d and en) or (q and not en));
end if;
end function;
function ffdre(q : std_logic_vector; d : std_logic_vector; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : std_logic_vector := (0 to 0 => '0')) return std_logic_vector is
constant INIT_I : std_logic_vector(q'range) := resize(INIT, q'length);
variable Result : std_logic_vector(q'range);
begin
for i in q'range loop
Result(i) := ffdre(q => q(i), d => d(i), rst => rst, en => en, INIT => INIT_I(i));
end loop;
return Result;
end function;
-- D-flipflop with set and enable
function ffdse(q : std_logic; d : std_logic; set : std_logic := '0'; en : std_logic := '1') return std_logic is
begin
return ffdre(q => q, d => d, rst => set, en => en, INIT => '1');
end function;
-- T-flipflop with reset and enable
function fftre(q : std_logic; t : std_logic; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : std_logic := '0') return std_logic is
begin
if not SIMULATION then
if (INIT = '0') then
return ((not q and (t and en)) or (q and not (t and en))) and not rst;
elsif (INIT = '1') then
return ((not q and (t and en)) or (q and not (t and en))) or rst;
else
report "Unsupported INIT value for synthesis." severity FAILURE;
return 'X';
end if;
elsif (rst = '1') then
return INIT;
else
return ((not q and (t and en)) or (q and not (t and en)));
end if;
end function;
-- T-flipflop with set and enable
function fftse(q : std_logic; t : std_logic; set : std_logic := '0'; en : std_logic := '1') return std_logic is
begin
return fftre(q => q, t => t, rst => set, en => en, INIT => '1');
end function;
-- RS-flipflop with dominant rst
function ffrs(q : std_logic; rst : std_logic := '0'; set : std_logic := '0') return std_logic is
begin
return (q or set) and not rst;
end function;
-- RS-flipflop with dominant set
function ffsr(q : std_logic; rst : std_logic := '0'; set : std_logic := '0') return std_logic is
begin
return (q and not rst) or set;
end function;
-- Counters
-- ===========================================================================
-- up-counter
function upcounter_next(cnt : unsigned; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : natural := 0) return unsigned is
begin
if (rst = '1') then
return to_unsigned(INIT, cnt'length);
elsif (en = '1') then
return cnt + 1;
else
return cnt;
end if;
end function;
function upcounter_equal(cnt : unsigned; value : natural) return std_logic is
begin
-- optimized comparison for only up counting values
return to_sl((cnt and to_unsigned(value, cnt'length)) = value);
end function;
-- down-counter
function downcounter_next(cnt : signed; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : integer := 0) return signed is
begin
if (rst = '1') then
return to_signed(INIT, cnt'length);
elsif (en = '1') then
return cnt - 1;
else
return cnt;
end if;
end function;
function downcounter_equal(cnt : signed; value : integer) return std_logic is
begin
-- optimized comparison for only down counting values
return to_sl((cnt nor to_signed(value, cnt'length)) /= value);
end function;
function downcounter_neg(cnt : signed) return std_logic is
begin
return cnt(cnt'high);
end function;
-- Shift/Rotate Registers
-- ===========================================================================
function shreg_left(q : std_logic_vector; i : std_logic; en : std_logic := '1') return std_logic_vector is
begin
return mux(en, q, q(q'left - 1 downto q'right) & i);
end function;
function shreg_right(q : std_logic_vector; i : std_logic; en : std_logic := '1') return std_logic_vector is
begin
return mux(en, q, i & q(q'left downto q'right - 1));
end function;
function rreg_left(q : std_logic_vector; en : std_logic := '1') return std_logic_vector is
begin
return mux(en, q, q(q'left - 1 downto q'right) & q(q'left));
end function;
function rreg_right(q : std_logic_vector; en : std_logic := '1') return std_logic_vector is
begin
return mux(en, q, q(q'right) & q(q'left downto q'right - 1));
end function;
-- compare functions
-- ===========================================================================
-- Returns, when
-- 1- => value1 < value2 (difference is negative)
-- 00 => value1 = value2 (difference is zero)
-- -1 => value1 > value2 (difference is positive)
function comp(value1 : std_logic_vector; value2 : std_logic_vector) return std_logic_vector is
begin
report "Comparing two STD_LOGIC_VECTORs - implicit conversion to UNSIGNED" severity WARNING;
return std_logic_vector(comp(unsigned(value1), unsigned(value2)));
end function;
function comp(value1 : unsigned; value2 : unsigned) return unsigned is
begin
if value1 < value2 then
return "10";
elsif value1 = value2 then
return "00";
else
return "01";
end if;
end function;
function comp(value1 : signed; value2 : signed) return signed is
begin
if value1 < value2 then
return "10";
elsif value1 = value2 then
return "00";
else
return "01";
end if;
end function;
function comp_allzero(value : std_logic_vector) return std_logic is
begin
return comp_allzero(unsigned(value));
end function;
function comp_allzero(value : unsigned) return std_logic is
begin
return to_sl(value = (value'range => '0'));
end function;
function comp_allzero(value : signed) return std_logic is
begin
return to_sl(value = (value'range => '0'));
end function;
function comp_allone(value : std_logic_vector) return std_logic is
begin
return comp_allone(unsigned(value));
end function;
function comp_allone(value : unsigned) return std_logic is
begin
return to_sl(value = (value'range => '1'));
end function;
function comp_allone(value : signed) return std_logic is
begin
return to_sl(value = (value'range => '1'));
end function;
-- multiplexers
function mux(sel : std_logic; sl0 : std_logic; sl1 : std_logic) return std_logic is
begin
return (sl0 and not sel) or (sl1 and sel);
end function;
function mux(sel : std_logic; slv0 : std_logic_vector; slv1 : std_logic_vector) return std_logic_vector is
begin
return (slv0 and not (slv0'range => sel)) or (slv1 and (slv1'range => sel));
end function;
function mux(sel : std_logic; us0 : unsigned; us1 : unsigned) return unsigned is
begin
return (us0 and not (us0'range => sel)) or (us1 and (us1'range => sel));
end function;
function mux(sel : std_logic; s0 : signed; s1 : signed) return signed is
begin
return (s0 and not (s0'range => sel)) or (s1 and (s1'range => sel));
end function;
end package body;
| gpl-2.0 | 269f0c1f90482cd1999ff364c68be559 | 0.629359 | 3.284254 | false | false | false | false |
nickg/nvc | test/regress/issue539.vhd | 1 | 1,253 | package my_package is
type slv_1_t is array (natural range <>) of bit_vector;
function addslvreg_f(arg0 : slv_1_t; arg1 : bit_vector) return slv_1_t;
end package my_package;
package body my_package is
function addslvreg_f(arg0 : slv_1_t; arg1 : bit_vector) return slv_1_t is
variable cb_v : bit_vector(0 downto 0);
variable arg_v,retval : arg0'subtype;
constant W : integer := arg0(0)'length-1;
begin
return retval;
end function addslvreg_f;
end package body;
-------------------------------------------------------------------------------
entity issue539 is
end entity;
use work.my_package.all;
architecture test of issue539 is
function get_elt_left (x : slv_1_t) return integer is
begin
return x(x'left)'left;
end function;
function get_elt_left_2 (x : slv_1_t) return integer is
begin
return x'element'left;
end function;
begin
p1: process is
variable v1 : slv_1_t(0 to 3)(5 to 6);
variable v2 : slv_1_t(0 to 3)(6 to 5);
begin
assert v1(1)'left = 5;
assert v2(5)'left = 6;
assert get_elt_left(v1) = 5;
assert get_elt_left(v2) = 6;
assert get_elt_left_2(v1) = 5;
assert get_elt_left_2(v2) = 6;
assert addslvreg_f(v1, "101") = v1;
wait;
end process;
end architecture;
| gpl-3.0 | a686c7449368c5a419fee067f6728407 | 0.623304 | 2.834842 | false | false | false | false |
nickg/nvc | test/regress/func14.vhd | 5 | 772 | entity func14 is
end entity;
architecture test of func14 is
begin
one: process is
function func(x : integer) return integer is
begin
return x * 2;
end function;
variable y : integer;
begin
y := 2;
wait for 1 ns;
assert func(y) = 4;
y := 4;
wait for 1 ns;
assert func(y) = 8;
wait;
end process;
two: process is
function func(x : integer) return integer is
begin
return x / 2;
end function;
variable y : integer;
begin
y := 2;
wait for 1 ns;
assert func(y) = 1;
y := 4;
wait for 1 ns;
assert func(y) = 2;
wait;
end process;
end architecture;
| gpl-3.0 | 454805ae74c2b2752402da7c688435f6 | 0.488342 | 4.063158 | false | false | false | false |
nickg/nvc | lib/ieee.08/numeric_std.vhdl | 1 | 75,849 | -- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Standard VHDL Synthesis Packages
-- : (NUMERIC_STD package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE DASC Synthesis Working Group,
-- : Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNRESOLVED_UNSIGNED: represents an UNSIGNED number
-- : in vector form
-- : -- > UNRESOLVED_SIGNED: represents a SIGNED number
-- : in vector form
-- : The base element type is type STD_ULOGIC.
-- : Aliases U_UNSIGNED and U_SIGNED are defined for the types
-- : UNRESOLVED_UNSIGNED and UNRESOLVED_SIGNED, respectively.
-- : Two numeric subtypes are defined:
-- : -- > UNSIGNED: represents UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The element subtypes are the same subtype as STD_LOGIC.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array
-- : is returned (exceptions, if any, are noted individually).
--
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
use STD.TEXTIO.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package NUMERIC_STD is
constant CopyRightNotice : STRING
:= "Copyright © 2008 IEEE. All rights reserved.";
--============================================================================
-- Numeric Array Type Definitions
--============================================================================
type UNRESOLVED_UNSIGNED is array (NATURAL range <>) of STD_ULOGIC;
type UNRESOLVED_SIGNED is array (NATURAL range <>) of STD_ULOGIC;
alias U_UNSIGNED is UNRESOLVED_UNSIGNED;
alias U_SIGNED is UNRESOLVED_SIGNED;
subtype UNSIGNED is (resolved) UNRESOLVED_UNSIGNED;
subtype SIGNED is (resolved) UNRESOLVED_SIGNED;
--============================================================================
-- Arithmetic Operators:
--===========================================================================
-- Id: A.1
function "abs" (ARG : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Returns the absolute value of an UNRESOLVED_SIGNED vector ARG.
-- Id: A.2
function "-" (ARG : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Returns the value of the unary minus operation on a
-- UNRESOLVED_SIGNED vector ARG.
--============================================================================
-- Id: A.3
function "+" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0)
-- Result: Adds two UNRESOLVED_UNSIGNED vectors that may be of different lengths.
-- Id: A.3R
function "+"(L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Similar to A.3 where R is a one bit UNRESOLVED_UNSIGNED
-- Id: A.3L
function "+"(L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Similar to A.3 where L is a one bit UNRESOLVED_UNSIGNED
-- Id: A.4
function "+" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0)
-- Result: Adds two UNRESOLVED_SIGNED vectors that may be of different lengths.
-- Id: A.4R
function "+"(L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Similar to A.4 where R is bit 0 of a non-negative.
-- Id: A.4L
function "+"(L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Similar to A.4 where L is bit 0 of a non-negative.
-- Id: A.5
function "+" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Adds an UNRESOLVED_UNSIGNED vector, L, with a nonnegative INTEGER, R.
-- Id: A.6
function "+" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Adds a nonnegative INTEGER, L, with an UNRESOLVED_UNSIGNED vector, R.
-- Id: A.7
function "+" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Adds an INTEGER, L(may be positive or negative), to an UNRESOLVED_SIGNED
-- vector, R.
-- Id: A.8
function "+" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Adds an UNRESOLVED_SIGNED vector, L, to an INTEGER, R.
--============================================================================
-- Id: A.9
function "-" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0)
-- Result: Subtracts two UNRESOLVED_UNSIGNED vectors that may be of different lengths.
-- Id: A.9R
function "-"(L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Similar to A.9 where R is a one bit UNRESOLVED_UNSIGNED
-- Id: A.9L
function "-"(L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Similar to A.9 where L is a one bit UNRESOLVED_UNSIGNED
-- Id: A.10
function "-" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0)
-- Result: Subtracts an UNRESOLVED_SIGNED vector, R, from another UNRESOLVED_SIGNED vector, L,
-- that may possibly be of different lengths.
-- Id: A.10R
function "-"(L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Similar to A.10 where R is bit 0 of a non-negative.
-- Id: A.10L
function "-"(L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Similar to A.10 where R is bit 0 of a non-negative.
-- Id: A.11
function "-" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Subtracts a nonnegative INTEGER, R, from an UNRESOLVED_UNSIGNED vector, L.
-- Id: A.12
function "-" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Subtracts an UNRESOLVED_UNSIGNED vector, R, from a nonnegative INTEGER, L.
-- Id: A.13
function "-" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Subtracts an INTEGER, R, from an UNRESOLVED_SIGNED vector, L.
-- Id: A.14
function "-" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Subtracts an UNRESOLVED_SIGNED vector, R, from an INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0)
-- Result: Performs the multiplication operation on two UNRESOLVED_UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.16
function "*" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED((L'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies two UNRESOLVED_SIGNED vectors that may possibly be of
-- different lengths.
-- Id: A.17
function "*" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED((L'LENGTH+L'LENGTH-1) downto 0)
-- Result: Multiplies an UNRESOLVED_UNSIGNED vector, L, with a nonnegative
-- INTEGER, R. R is converted to an UNRESOLVED_UNSIGNED vector of
-- SIZE L'LENGTH before multiplication.
-- Id: A.18
function "*" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED((R'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies an UNRESOLVED_UNSIGNED vector, R, with a nonnegative
-- INTEGER, L. L is converted to an UNRESOLVED_UNSIGNED vector of
-- SIZE R'LENGTH before multiplication.
-- Id: A.19
function "*" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED((L'LENGTH+L'LENGTH-1) downto 0)
-- Result: Multiplies an UNRESOLVED_SIGNED vector, L, with an INTEGER, R. R is
-- converted to an UNRESOLVED_SIGNED vector of SIZE L'LENGTH before
-- multiplication.
-- Id: A.20
function "*" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED((R'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies an UNRESOLVED_SIGNED vector, R, with an INTEGER, L. L is
-- converted to an UNRESOLVED_SIGNED vector of SIZE R'LENGTH before
-- multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNRESOLVED_UNSIGNED vector, L, by another UNRESOLVED_UNSIGNED vector, R.
-- Id: A.22
function "/" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNRESOLVED_SIGNED vector, L, by another UNRESOLVED_SIGNED vector, R.
-- Id: A.23
function "/" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNRESOLVED_UNSIGNED vector, L, by a nonnegative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Divides a nonnegative INTEGER, L, by an UNRESOLVED_UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.25
function "/" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNRESOLVED_SIGNED vector, L, by an INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.26
function "/" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Divides an INTEGER, L, by an UNRESOLVED_SIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNRESOLVED_UNSIGNED vectors.
-- Id: A.28
function "rem" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNRESOLVED_SIGNED vectors.
-- Id: A.29
function "rem" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNRESOLVED_UNSIGNED vector and R is a
-- nonnegative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNRESOLVED_UNSIGNED vector and L is a
-- nonnegative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.31
function "rem" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is UNRESOLVED_SIGNED vector and R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.32
function "rem" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is UNRESOLVED_SIGNED vector and L is an INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNRESOLVED_UNSIGNED vectors.
-- Id: A.34
function "mod" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNRESOLVED_SIGNED vectors.
-- Id: A.35
function "mod" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNRESOLVED_UNSIGNED vector and R
-- is a nonnegative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNRESOLVED_UNSIGNED vector and L
-- is a nonnegative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.37
function "mod" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNRESOLVED_SIGNED vector and
-- R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.38
function "mod" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
-- Id: A.39
function find_leftmost (ARG : UNRESOLVED_UNSIGNED; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- Id: A.40
function find_leftmost (ARG : UNRESOLVED_SIGNED; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- Id: A.41
function find_rightmost (ARG : UNRESOLVED_UNSIGNED; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- Id: A.42
function find_rightmost (ARG : UNRESOLVED_SIGNED; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNRESOLVED_UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.2
function ">" (L, R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNRESOLVED_SIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a nonnegative INTEGER and
-- R is an UNRESOLVED_UNSIGNED vector.
-- Id: C.4
function ">" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- Id: C.5
function ">" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNRESOLVED_UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.6
function ">" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNRESOLVED_SIGNED vector and
-- R is a INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNRESOLVED_UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.8
function "<" (L, R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNRESOLVED_SIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a nonnegative INTEGER and
-- R is an UNRESOLVED_UNSIGNED vector.
-- Id: C.10
function "<" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- Id: C.11
function "<" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNRESOLVED_UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.12
function "<" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNRESOLVED_SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNRESOLVED_UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.14
function "<=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNRESOLVED_SIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a nonnegative INTEGER and
-- R is an UNRESOLVED_UNSIGNED vector.
-- Id: C.16
function "<=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- Id: C.17
function "<=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNRESOLVED_UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.18
function "<=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNRESOLVED_SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNRESOLVED_UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.20
function ">=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNRESOLVED_SIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a nonnegative INTEGER and
-- R is an UNRESOLVED_UNSIGNED vector.
-- Id: C.22
function ">=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- Id: C.23
function ">=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNRESOLVED_UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.24
function ">=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNRESOLVED_SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNRESOLVED_UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.26
function "=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNRESOLVED_SIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a nonnegative INTEGER and
-- R is an UNRESOLVED_UNSIGNED vector.
-- Id: C.28
function "=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- Id: C.29
function "=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNRESOLVED_UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.30
function "=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNRESOLVED_SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNRESOLVED_UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.32
function "/=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNRESOLVED_SIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a nonnegative INTEGER and
-- R is an UNRESOLVED_UNSIGNED vector.
-- Id: C.34
function "/=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- Id: C.35
function "/=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNRESOLVED_UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.36
function "/=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNRESOLVED_SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.37
function MINIMUM (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED
-- Result: Returns the lesser of two UNRESOLVED_UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.38
function MINIMUM (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED
-- Result: Returns the lesser of two UNRESOLVED_SIGNED vectors that may be
-- of different lengths.
-- Id: C.39
function MINIMUM (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED
-- Result: Returns the lesser of a nonnegative INTEGER, L, and
-- an UNRESOLVED_UNSIGNED vector, R.
-- Id: C.40
function MINIMUM (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED
-- Result: Returns the lesser of an INTEGER, L, and an UNRESOLVED_SIGNED
-- vector, R.
-- Id: C.41
function MINIMUM (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED
-- Result: Returns the lesser of an UNRESOLVED_UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
-- Id: C.42
function MINIMUM (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED
-- Result: Returns the lesser of an UNRESOLVED_SIGNED vector, L, and
-- an INTEGER, R.
--============================================================================
-- Id: C.43
function MAXIMUM (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED
-- Result: Returns the greater of two UNRESOLVED_UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.44
function MAXIMUM (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED
-- Result: Returns the greater of two UNRESOLVED_SIGNED vectors that may be
-- of different lengths.
-- Id: C.45
function MAXIMUM (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED
-- Result: Returns the greater of a nonnegative INTEGER, L, and
-- an UNRESOLVED_UNSIGNED vector, R.
-- Id: C.46
function MAXIMUM (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED
-- Result: Returns the greater of an INTEGER, L, and an UNRESOLVED_SIGNED
-- vector, R.
-- Id: C.47
function MAXIMUM (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED
-- Result: Returns the greater of an UNRESOLVED_UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
-- Id: C.48
function MAXIMUM (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED
-- Result: Returns the greater of an UNRESOLVED_SIGNED vector, L, and
-- an INTEGER, R.
--============================================================================
-- Id: C.49
function "?>" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L and R are UNRESOLVED_UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.50
function "?>" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L and R are UNRESOLVED_SIGNED vectors possibly
-- of different lengths.
-- Id: C.51
function "?>" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is a nonnegative INTEGER and
-- R is an UNRESOLVED_UNSIGNED vector.
-- Id: C.52
function "?>" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is a INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- Id: C.53
function "?>" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is an UNRESOLVED_UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.54
function "?>" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is an UNRESOLVED_SIGNED vector and
-- R is a INTEGER.
--============================================================================
-- Id: C.55
function "?<" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L and R are UNRESOLVED_UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.56
function "?<" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L and R are UNRESOLVED_SIGNED vectors possibly
-- of different lengths.
-- Id: C.57
function "?<" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is a nonnegative INTEGER and
-- R is an UNRESOLVED_UNSIGNED vector.
-- Id: C.58
function "?<" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is an INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- Id: C.59
function "?<" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is an UNRESOLVED_UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.60
function "?<" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is an UNRESOLVED_SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.61
function "?<=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L and R are UNRESOLVED_UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.62
function "?<=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L and R are UNRESOLVED_SIGNED vectors possibly
-- of different lengths.
-- Id: C.63
function "?<=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is a nonnegative INTEGER and
-- R is an UNRESOLVED_UNSIGNED vector.
-- Id: C.64
function "?<=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is an INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- Id: C.65
function "?<=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is an UNRESOLVED_UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.66
function "?<=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is an UNRESOLVED_SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.67
function "?>=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L and R are UNRESOLVED_UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.68
function "?>=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L and R are UNRESOLVED_SIGNED vectors possibly
-- of different lengths.
-- Id: C.69
function "?>=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is a nonnegative INTEGER and
-- R is an UNRESOLVED_UNSIGNED vector.
-- Id: C.70
function "?>=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is an INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- Id: C.71
function "?>=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is an UNRESOLVED_UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.72
function "?>=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is an UNRESOLVED_SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.73
function "?=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L and R are UNRESOLVED_UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.74
function "?=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L and R are UNRESOLVED_SIGNED vectors possibly
-- of different lengths.
-- Id: C.75
function "?=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is a nonnegative INTEGER and
-- R is an UNRESOLVED_UNSIGNED vector.
-- Id: C.76
function "?=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is an INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- Id: C.77
function "?=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is an UNRESOLVED_UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.78
function "?=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is an UNRESOLVED_SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.79
function "?/=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L and R are UNRESOLVED_UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.80
function "?/=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L and R are UNRESOLVED_SIGNED vectors possibly
-- of different lengths.
-- Id: C.81
function "?/=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is a nonnegative INTEGER and
-- R is an UNRESOLVED_UNSIGNED vector.
-- Id: C.82
function "?/=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is an INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- Id: C.83
function "?/=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is an UNRESOLVED_UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.84
function "?/=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is an UNRESOLVED_SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNRESOLVED_UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT leftmost elements are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNRESOLVED_UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT rightmost elements are lost.
-- Id: S.3
function SHIFT_LEFT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNRESOLVED_SIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT leftmost elements are lost.
-- Id: S.4
function SHIFT_RIGHT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNRESOLVED_SIGNED vector COUNT times.
-- The vacated positions are filled with the leftmost
-- element, ARG'LEFT. The COUNT rightmost elements are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNRESOLVED_UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNRESOLVED_UNSIGNED vector COUNT times.
-- Id: S.7
function ROTATE_LEFT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-left of an UNRESOLVED_SIGNED
-- vector COUNT times.
-- Id: S.8
function ROTATE_RIGHT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-right of an UNRESOLVED_SIGNED
-- vector COUNT times.
--============================================================================
--============================================================================
------------------------------------------------------------------------------
-- Note: Function S.9 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.10 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE StdL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.12 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0)
-- Result: UNRESOLVED_SIGNED(SHIFT_RIGHT(UNRESOLVED_UNSIGNED(ARG), COUNT))
------------------------------------------------------------------------------
-- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.14 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.16 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.18 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.18
function "sla" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.20 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.20
function "sra" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.1
function RESIZE (ARG : UNRESOLVED_SIGNED; NEW_SIZE : NATURAL) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNRESOLVED_SIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with the sign bit (ARG'LEFT). When truncating,
-- the sign bit is retained along with the rightmost part.
-- Id: R.2
function RESIZE (ARG : UNRESOLVED_UNSIGNED; NEW_SIZE : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNRESOLVED_SIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
function RESIZE (ARG, SIZE_RES : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED (SIZE_RES'length-1 downto 0)
function RESIZE (ARG, SIZE_RES : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED (SIZE_RES'length-1 downto 0)
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : UNRESOLVED_UNSIGNED) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNRESOLVED_UNSIGNED vector.
-- Result: Converts the UNRESOLVED_UNSIGNED vector to an INTEGER.
-- Id: D.2
function TO_INTEGER (ARG : UNRESOLVED_SIGNED) return INTEGER;
-- Result subtype: INTEGER
-- Result: Converts an UNRESOLVED_SIGNED vector to an INTEGER.
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(SIZE-1 downto 0)
-- Result: Converts a nonnegative INTEGER to an UNRESOLVED_UNSIGNED vector with
-- the specified SIZE.
-- Id: D.4
function TO_SIGNED (ARG : INTEGER; SIZE : NATURAL) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(SIZE-1 downto 0)
-- Result: Converts an INTEGER to a UNRESOLVED_SIGNED vector of the specified SIZE.
function TO_UNSIGNED (ARG : NATURAL; SIZE_RES : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(SIZE_RES'length-1 downto 0)
function TO_SIGNED (ARG : INTEGER; SIZE_RES : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(SIZE_RES'length-1 downto 0)
--============================================================================
-- Logical Operators
--============================================================================
-- Id: L.1
function "not" (L : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.2
function "and" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.3
function "or" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.4
function "nand" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.5
function "nor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.6
function "xor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
-- ---------------------------------------------------------------------------
-- Note: Function L.7 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
-- ---------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
-- Id: L.8
function "not" (L : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.9
function "and" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.10
function "or" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.11
function "nand" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.12
function "nor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.13
function "xor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
-- ---------------------------------------------------------------------------
-- Note: Function L.14 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
-- ---------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
-- Id: L.15
function "and" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector AND operation
-- Id: L.16
function "and" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar AND operation
-- Id: L.17
function "or" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector OR operation
-- Id: L.18
function "or" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar OR operation
-- Id: L.19
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector NAND operation
-- Id: L.20
function "nand" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar NAND operation
-- Id: L.21
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector NOR operation
-- Id: L.22
function "nor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar NOR operation
-- Id: L.23
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector XOR operation
-- Id: L.24
function "xor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar XOR operation
------------------------------------------------------------------------------
-- Note: Function L.25 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.25
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector XNOR operation
------------------------------------------------------------------------------
-- Note: Function L.26 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.26
function "xnor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar XNOR operation
-- Id: L.27
function "and" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector AND operation
-- Id: L.28
function "and" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar AND operation
-- Id: L.29
function "or" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector OR operation
-- Id: L.30
function "or" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar OR operation
-- Id: L.31
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector NAND operation
-- Id: L.32
function "nand" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar NAND operation
-- Id: L.33
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector NOR operation
-- Id: L.34
function "nor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar NOR operation
-- Id: L.35
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector XOR operation
-- Id: L.36
function "xor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar XOR operation
------------------------------------------------------------------------------
-- Note: Function L.37 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.37
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector XNOR operation
------------------------------------------------------------------------------
-- Note: Function L.38 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.38
function "xnor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar XNOR operation
------------------------------------------------------------------------------
-- Note: Function L.39 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.39
function "and" (L : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC.
-- Result: Result of and'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.40 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.40
function "nand" (L : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC.
-- Result: Result of nand'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.41 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.41
function "or" (L : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC.
-- Result: Result of or'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.42 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.42
function "nor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC.
-- Result: Result of nor'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.43 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.43
function "xor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC.
-- Result: Result of xor'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.44 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.44
function "xnor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC.
-- Result: Result of xnor'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.45 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.45
function "and" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC.
-- Result: Result of and'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.46 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.46
function "nand" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC.
-- Result: Result of nand'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.47 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.47
function "or" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC.
-- Result: Result of or'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.48 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.48
function "nor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC.
-- Result: Result of nor'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.49 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.49
function "xor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC.
-- Result: Result of xor'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.50 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.50
function "xnor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC.
-- Result: Result of xnor'ing all of the bits of the vector.
--============================================================================
-- Match Functions
--============================================================================
-- Id: M.1
function STD_MATCH (L, R : STD_ULOGIC) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
-- Id: M.2
function STD_MATCH (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
-- Id: M.3
function STD_MATCH (L, R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
-- Id: M.5
function STD_MATCH (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
--============================================================================
-- Translation Functions
--============================================================================
-- Id: T.1
function TO_01 (S : UNRESOLVED_UNSIGNED; XMAP : STD_ULOGIC := '0') return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', and 'L' is translated
-- to '0'. If a value other than '0'|'1'|'H'|'L' is found,
-- the array is set to (others => XMAP), and a warning is
-- issued.
-- Id: T.2
function TO_01 (S : UNRESOLVED_SIGNED; XMAP : STD_ULOGIC := '0') return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', and 'L' is translated
-- to '0'. If a value other than '0'|'1'|'H'|'L' is found,
-- the array is set to (others => XMAP), and a warning is
-- issued.
-- Id: T.3
function TO_X01 (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', 'L' is translated to '0',
-- and values other than '0'|'1'|'H'|'L' are translated to 'X'.
-- Id: T.4
function TO_X01 (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', 'L' is translated to '0',
-- and values other than '0'|'1'|'H'|'L' are translated to 'X'.
-- Id: T.5
function TO_X01Z (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', 'L' is translated to '0',
-- and values other than '0'|'1'|'H'|'L'|'Z' are translated to 'X'.
-- Id: T.6
function TO_X01Z (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', 'L' is translated to '0',
-- and values other than '0'|'1'|'H'|'L'|'Z' are translated to 'X'.
-- Id: T.7
function TO_UX01 (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', 'L' is translated to '0',
-- and values other than 'U'|'0'|'1'|'H'|'L' are translated to 'X'.
-- Id: T.8
function TO_UX01 (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', 'L' is translated to '0',
-- and values other than 'U'|'0'|'1'|'H'|'L' are translated to 'X'.
-- Id: T.9
function IS_X (S : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: TRUE if S contains a 'U'|'X'|'Z'|'W'|'-' value, FALSE otherwise.
-- Id: T.10
function IS_X (S : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: TRUE if S contains a 'U'|'X'|'Z'|'W'|'-' value, FALSE otherwise.
--============================================================================
-- string conversion and write operations
--============================================================================
-- the following operations are predefined
-- function TO_STRING (value : UNRESOLVED_UNSIGNED) return STRING;
-- function TO_STRING (value : UNRESOLVED_SIGNED) return STRING;
-- explicitly defined operations
alias TO_BSTRING is TO_STRING [UNRESOLVED_UNSIGNED return STRING];
alias TO_BSTRING is TO_STRING [UNRESOLVED_SIGNED return STRING];
alias to_binary_string is TO_STRING [UNRESOLVED_UNSIGNED return STRING];
alias to_binary_string is TO_STRING [UNRESOLVED_SIGNED return STRING];
function TO_OSTRING (value : UNRESOLVED_UNSIGNED) return STRING;
function TO_OSTRING (value : UNRESOLVED_SIGNED) return STRING;
alias to_octal_string is TO_OSTRING [UNRESOLVED_UNSIGNED return STRING];
alias to_octal_string is TO_OSTRING [UNRESOLVED_SIGNED return STRING];
function to_hstring (value : UNRESOLVED_UNSIGNED) return STRING;
function to_hstring (value : UNRESOLVED_SIGNED) return STRING;
alias to_hex_string is to_hstring [UNRESOLVED_UNSIGNED return STRING];
alias to_hex_string is to_hstring [UNRESOLVED_SIGNED return STRING];
procedure READ(L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED; GOOD : out BOOLEAN);
procedure READ(L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED);
procedure READ(L : inout LINE; VALUE : out UNRESOLVED_SIGNED; GOOD : out BOOLEAN);
procedure READ(L : inout LINE; VALUE : out UNRESOLVED_SIGNED);
procedure WRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure WRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, UNRESOLVED_UNSIGNED, BOOLEAN];
alias BREAD is READ [LINE, UNRESOLVED_SIGNED, BOOLEAN];
alias BREAD is READ [LINE, UNRESOLVED_UNSIGNED];
alias BREAD is READ [LINE, UNRESOLVED_SIGNED];
alias BINARY_READ is READ [LINE, UNRESOLVED_UNSIGNED, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_SIGNED, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_UNSIGNED];
alias BINARY_READ is READ [LINE, UNRESOLVED_SIGNED];
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED);
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED);
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_UNSIGNED, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_SIGNED, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_UNSIGNED];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_SIGNED];
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED);
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED);
alias HEX_READ is HREAD [LINE, UNRESOLVED_UNSIGNED, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_SIGNED, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_UNSIGNED];
alias HEX_READ is HREAD [LINE, UNRESOLVED_SIGNED];
alias BWRITE is WRITE [LINE, UNRESOLVED_UNSIGNED, SIDE, WIDTH];
alias BWRITE is WRITE [LINE, UNRESOLVED_SIGNED, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_UNSIGNED, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_SIGNED, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure OWRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_UNSIGNED, SIDE, WIDTH];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_SIGNED, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure HWRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_UNSIGNED, SIDE, WIDTH];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_SIGNED, SIDE, WIDTH];
end package NUMERIC_STD;
| gpl-3.0 | 52406acbecf5371f2eb9bddc54ff8bf5 | 0.600285 | 4.323112 | false | false | false | false |
nickg/nvc | test/regress/vests42.vhd | 1 | 5,644 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc492.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY vests42 IS
END vests42;
ARCHITECTURE c03s02b02x00p01n01i00492arch OF vests42 IS
type etype is (one,two,three,four,five,six,seven);
type TR is record
i : integer;
b : bit;
bo : boolean;
bv : bit_vector (0 to 3);
r : real;
t : time;
e : etype;
c : character;
end record;
type T1 is record
t : time;
b : bit;
i : integer;
bo : boolean;
r : real;
bv : bit_vector (0 to 3);
e : etype;
c : character;
end record;
function FUNC1(signal recd1: TR) return T1 is
variable recd2:T1;
begin
recd2.bv := recd1.bv;
recd2.b := recd1.b;
recd2.bo := recd1.bo;
recd2.i := recd1.i;
recd2.r := recd1.r;
recd2.t := recd1.t;
recd2.e := recd1.e;
recd2.c := recd1.c;
return recd2;
end FUNC1;
function FUNC2(signal recd1: TR) return integer is
begin
return recd1.i;
end;
function FUNC3(signal recd1: TR) return bit is
begin
return recd1.b;
end;
function FUNC4(signal recd1: TR) return boolean is
begin
return recd1.bo;
end;
function FUNC5(signal recd1: TR) return bit_vector is
begin
return recd1.bv;
end;
function FUNC6(signal recd1: TR) return real is
begin
return recd1.r;
end;
function FUNC7(signal recd1: TR) return time is
begin
return recd1.t;
end;
function FUNC8(signal recd1: TR) return etype is
begin
return recd1.e;
end;
function FUNC9(signal recd1: TR) return character is
begin
return recd1.c;
end;
signal var1: TR;
signal var2: T1;
BEGIN
TESTING: PROCESS
variable OkayCount : integer := 0;
BEGIN
wait for 1 ns;
var2 <= (bv=>"0000",b=>'0',bo=>false,i=>0,r=>0.0,t=>1 ms,e=>one,c=>'a');
var1 <= (bv=>"0001",b=>'1',bo=>true,i=>777,r=>333.767,t=>44 ms,e=>seven,c=>'%');
wait for 1 ns;
var2 <= FUNC1(var1);
wait for 1 ns;
assert var2.bv = "0001" report "var2.bv /= 0001" severity note;
assert var2.b = '1' report "var2.b /= 1" severity note;
assert var2.bo = true report "var2.bo /= true" severity note;
assert var2.i = 777 report "var2.i /= 777" severity note;
assert var2.r = 333.767 report "var2.r /= 333.767" severity note;
assert var2.t = 44 ms report "var2.t /= 44 ms" severity note;
assert var2.e = seven report "var2.e /= seven" severity note;
assert var2.c = '%' report "var2.c /= c" severity note;
if var2 = (bv=>"0001",b=>'1',bo=>true,i=>777,r=>333.767,t=>44 ms,e=>seven,c=>'%') then
OkayCount := OkayCount + 1;
else
assert false report "bad return on FUNC1" severity note;
end if;
var2 <= (bv=>"0000",b=>'0',bo=>false,i=>0,r=>0.0,t=>1 ms,e=>one,c=>'a');
wait for 1 ns;
if var2 = (bv=>"0000",b=>'0',bo=>false,i=>0,r=>0.0,t=>1 ms,e=>one,c=>'a') then
OkayCount := OkayCount + 1;
end if;
var2.i <= FUNC2(var1);
var2.b <= FUNC3(var1);
var2.bo <= FUNC4(var1);
var2.bv <= FUNC5(var1);
var2.r <= FUNC6(var1);
var2.t <= FUNC7(var1);
var2.e <= FUNC8(var1);
var2.c <= FUNC9(var1);
wait for 1 ns;
assert var2.bv = "0001" report "var2.bv /= 0001" severity note;
assert var2.b = '1' report "var2.b /= 1" severity note;
assert var2.bo = true report "var2.bo /= true" severity note;
assert var2.i = 777 report "var2.i /= 777" severity note;
assert var2.r = 333.767 report "var2.r /= 333.767" severity note;
assert var2.t = 44 ms report "var2.t /= 44 ms" severity note;
assert var2.e = seven report "var2.e /= seven" severity note;
assert var2.c = '%' report "var2.c /= c" severity note;
if var2 = (bv=>"0001",b=>'1',bo=>true,i=>777,r=>333.767,t=>44 ms,e=>seven,c=>'%') then
OkayCount := OkayCount + 1;
else
assert false report "bad return on FUNC2-8" severity note;
end if;
wait for 1 ns;
assert NOT( OkayCount = 3 )
report "***PASSED TEST: c03s02b02x00p01n01i00492"
severity NOTE;
assert ( OkayCount = 3 )
report "***FAILED TEST: c03s02b02x00p01n01i00492 - Problem assigning record subelements in function."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b02x00p01n01i00492arch;
| gpl-3.0 | 2c6c47444a4d27b8d82ddcbc68b7a962 | 0.577782 | 3.243678 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_triangle_waveform.vhd | 4 | 1,475 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity tb_triangle_waveform is
end tb_triangle_waveform;
architecture TB_triangle_waveform of tb_triangle_waveform is
-- Component declarations
-- Signal declarations
terminal in_src : electrical;
begin
-- Signal assignments
-- Component instances
vio : entity work.triangle_waveform_wa(ideal)
port map(
pos => in_src,
neg => ELECTRICAL_REF
);
R1 : entity work.resistor(ideal)
generic map(
res => 10.0e9
)
port map(
p1 => in_src,
p2 => ELECTRICAL_REF
);
end TB_triangle_waveform;
| gpl-2.0 | ff12d6669313163623da872d84ad7ef3 | 0.682034 | 4.238506 | false | false | false | false |
tgingold/ghdl | testsuite/synth/slice01/tb_slice02.vhdl | 1 | 697 | entity tb_slice02 is
end tb_slice02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_slice02 is
signal clk : std_logic;
signal di : std_logic_vector (7 downto 0);
signal mask : std_logic_vector (1 downto 0);
signal do : std_logic_vector (7 downto 0);
begin
dut: entity work.slice02
generic map (w => 4)
port map (clk, di, mask, do);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
constant b0 : std_logic_vector (3 downto 0) := "1101";
begin
di <= x"12";
mask <= "11";
pulse;
assert do = x"12" severity error;
wait;
end process;
end behav;
| gpl-2.0 | 0c04c3c91d13c6b323c2928cabc2f0a8 | 0.606887 | 3.226852 | false | false | false | false |
nickg/nvc | test/parse/names.vhd | 1 | 10,397 | entity ee is
end entity;
architecture aa of ee is
function func1(x : integer) return integer;
function func2(x : integer) return integer;
function func2(x : bit) return integer;
function func3(x : character) return integer;
function func3(x : bit) return integer;
function func4(x : integer) return integer;
function func4(y : integer) return integer; -- Error
function func5(x : character) return integer;
function func5(y : bit) return integer;
type bool_vector is array (natural range <>) of boolean;
function func6(x : bit_vector) return integer;
function func6(x : bool_vector) return integer;
type my_int is range 1 to 100;
function func7(x : integer) return integer;
function func7(x : my_int) return integer;
function func8(x : bit_vector) return integer;
function func8(x : string) return integer;
begin
p1: process is
variable x : integer;
begin
x := func1(1); -- OK
x := func2(1); -- OK
x := func2('1'); -- OK
x := func3('a'); -- OK
x := func3('1'); -- Error
x := func5(x => '1'); -- OK
x := func5(y => '1'); -- OK
x := func5(z => '1'); -- Error
x := func5("101"); -- Error
x := func6("101"); -- OK
x := func6(('1', '0')); -- Error
x := func6((true, false)); -- Error
x := func6(bit_vector'(('1', '0'))); -- OK
x := func7(5); -- Error
x := func8("101"); -- Error
end process;
p2: process is
procedure proc1(x : integer);
procedure proc2(x : integer);
procedure proc2(x : bit);
procedure proc3(x : character);
procedure proc3(x : bit);
procedure proc4(x : integer);
procedure proc4(y : integer); -- Error
procedure proc5(x : character);
procedure proc5(y : bit);
procedure proc6(x : bit_vector);
procedure proc6(x : bool_vector);
procedure proc7(x : integer);
procedure proc7(x : my_int);
procedure proc8(x : bit_vector);
procedure proc8(x : string);
variable v : bit_vector(1 to 3);
variable proc8 : bit_vector(3 to 5); -- Error
begin
proc1(1); -- OK
proc2(1); -- OK
proc2('1'); -- OK
proc3('a'); -- OK
proc3('1'); -- Error
proc5(x => '1'); -- OK
proc5(y => '1'); -- OK
proc5(z => '1'); -- Error
proc5("101"); -- Error
proc6("101"); -- OK
proc6(('1', '0')); -- Error
proc6((true, false)); -- Error
proc6(bit_vector'(('1', '0'))); -- OK
proc7(5); -- Error
proc8("101"); -- Error
v(1); -- Error
foo(1, 2); -- Error
end process;
p3: process is
type line is access string;
variable l : line;
begin
assert now = 0 ns; -- OK
assert l = null; -- OK
end process;
p4: process is
type my_other_int is range 1 to 100;
variable x : my_int;
begin
x := 5 * (2 + 4); -- OK
end process;
p5: process is
type table_t is array (bit) of character;
constant table : table_t := ( '0' => '0',
'1' => '1' ); -- OK
begin
end process;
p6: process is
constant FPO_LOG_MAX_ITERATIONS : integer := 9;
type T_FPO_LOG_ALPHA is array (0 to FPO_LOG_MAX_ITERATIONS-1) of integer;
variable alpha : T_FPO_LOG_ALPHA;
begin
end process;
b7: block is
constant WIDTH : integer := 5;
begin
gen: for i in 0 to WIDTH - 1 generate
end generate;
end block;
b8: block is
impure function get_foo return integer;
attribute foreign of get_foo : function is "_get_foo";
begin
end block;
p9: process is
type unsigned is array (natural range <>) of bit;
function "<"(x, y : unsigned) return boolean is -- OK
begin
return x(0) = '0';
end function;
variable a, b : unsigned(1 to 3);
begin
assert a < b; -- OK (should be user-defined)
end process;
p10: process is
procedure finish;
procedure stop_impl(finish, have_status : boolean; status : integer) is
begin
end procedure;
procedure stop(status : integer) is
begin
-- OK
stop_impl(finish => false, have_status => true, status => status);
end procedure;
begin
end process;
p11: process is
function foo return bit is
begin
return '1';
end function;
function foo return bit_vector is
begin
return "11";
end function;
variable x : bit_vector(1 to 2);
variable y : bit;
begin
x := foo; -- OK
y := foo; -- OK
end process;
b12: block is
signal x : bit_vector(3 downto 0);
signal y : integer;
begin
decode_y: with x select y <= -- OK
0 when X"0",
1 when X"1",
2 when X"2",
3 when X"3";
end block;
p13: process is
begin
assert integer'value("5") = 5; -- OK
end process;
b14: block is
function foo return integer is
begin
return 1;
end function;
procedure check is
type mytype is (foo);
begin
assert foo = foo; -- Error
end procedure;
begin
end block;
b15: block is
type mytype is (a, b);
function "+"(x, y : mytype) return mytype is
variable d : integer;
begin
d := "+".d; -- OK
d := "+".x; -- Error
return a;
end function;
begin
end block;
b16: block is
-- From VESTS tc290.vhd
type mytime is range 1 to 30
units
fs;
end units;
begin
testing: process
variable t,a :mytime;
variable b :integer;
begin
a:=30 fs;
b := 10;
t:= a/b;
end process;
end block;
p17: assert nothere(1) = 5; -- Error
p18: process is
type myrec is record
x, y : bit;
end record;
variable r : myrec;
begin
assert r.x = '1'; -- OK
end process;
p19: process is
procedure p19_proc(x : in integer; y : out integer);
function p19_func(x : integer) return integer;
begin
-- p19_proc(5, p19_func(y) => 4); -- OK (not supported by sem)
end process;
p20: process is
type bit_ptr is access bit;
variable b : bit_ptr;
begin
assert b.all = '1'; -- OK
end process;
p21: process is
subtype my_int is integer range 1 to 20;
begin
assert my_int'base'left = 1; -- OK
end process;
p22: process is
subtype my_int is integer range 1 to 5;
constant c : bit_vector(1 to 10) := (
my_int => '1', others => '0' ); -- OK
begin
end process;
p23: process is
type typ;
function p23_func(x : typ) return integer;
type typ is (a, b, c);
function p23_func(x : typ) return integer is -- OK
begin
return 5;
end function;
begin
end process;
p24: process is
variable v : bit_vector(8+23+2 downto 0); -- OK
begin
end process;
p25: process is
variable b : bit;
begin
b := fnork(b, '1'); -- Error ("fnork" undeclared)
end process;
p26: process is
type my_bit_vector is array (natural range <>) of bit;
procedure p26_1(x : integer; y : bit_vector);
procedure p26_1(x : integer; y : my_bit_vector);
variable v : my_bit_vector(1 to 3);
begin
p26_1(x => 1, y => v); -- OK
p26_1(x => 1, y => 2); -- Error
end process;
p27: process is
type my_bit_vector is array (natural range <>) of bit;
function "="(l, r : my_bit_vector) return boolean;
variable v : my_bit_vector(1 to 3);
variable b : bit;
begin
assert b and v = "101"; -- Error
end process;
p28: process is
function p28_1 (x : integer; y : boolean) return boolean;
procedure p28_1 (x : integer; y : boolean);
function p28_2 return boolean;
procedure p28_2;
begin
assert p28_1(x => 1, y => true); -- OK
p28_1(x => 1, y => true); -- OK
assert p28_2; -- OK
p28_2; -- OK
end process;
p29: process is
type unsigned is array (natural range <>) of bit;
variable mult : bit_vector(1 downto 0);
variable p : unsigned(1 downto 0);
variable u : bit_vector(4 downto 0);
begin
u := bit_vector('1' & (unsigned(mult) & p)); -- OK
end process;
p30: process is
variable x : integer;
variable c : character;
begin
x := x.y + 1; -- Error
c := std.standard.'.'; -- OK
foo.bar.p(1, 2, 3); -- Error
end process;
p31: process is
type list;
type list_ptr is access list;
type list is record
f : integer;
end record;
procedure p is
type list is range 1 to 10;
variable x : list_ptr; -- OK
begin
x.all.f := 1; -- OK
end procedure;
begin
p;
end process;
p32: process is
begin
assert std.standard.bit_vector'("101") = "101"; -- OK
assert std.standard.true'(1) = 1; -- Error
end process;
end architecture;
| gpl-3.0 | 111536607f16909b88170be4e9865628 | 0.473406 | 3.971352 | false | false | false | false |
nickg/nvc | test/regress/array7.vhd | 1 | 526 | entity array7 is
end entity;
architecture test of array7 is
type t_bv_array is array (natural range <>) of bit_vector;
subtype t_byte_array is t_bv_array(open)(7 downto 0);
signal s : t_byte_array(1 to 3);
begin
p1: process is
begin
assert s(1) = X"00";
s(2) <= X"ab";
wait for 1 ns;
assert s = (X"00", X"ab", X"00");
s(1 to 2) <= (X"01", X"02");
wait for 1 ns;
assert s = (X"01", X"02", X"00");
wait;
end process;
end architecture;
| gpl-3.0 | a8dadf49332a19b7afb803864758fb0d | 0.532319 | 2.988636 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/pwl_load.vhd | 4 | 1,871 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity pwl_load is
generic ( load_enable : boolean := true;
res_init : resistance;
res1 : resistance;
t1 : time;
res2 : resistance;
t2 : time );
port ( terminal p1, p2 : electrical );
end entity pwl_load;
----------------------------------------------------------------
architecture ideal of pwl_load is
quantity v across i through p1 to p2;
signal res_signal : resistance := res_init;
begin
load_present : if load_enable generate
if domain = quiescent_domain or domain = frequency_domain use
v == i * res_init;
else
v == i * res_signal'ramp(1.0e-6, 1.0e-6);
end use;
create_event : process is
begin
wait for t1;
res_signal <= res1;
wait for t2 - t1;
res_signal <= res2;
wait;
end process create_event;
end generate load_present;
load_absent : if not load_enable generate
i == 0.0;
end generate load_absent;
end architecture ideal;
| gpl-2.0 | 7d4bd5f73fbe27746253bf350b8a8624 | 0.640299 | 4.023656 | false | false | false | false |
nickg/nvc | test/regress/issue497.vhd | 1 | 497 | entity test is
end entity;
architecture rtl of test is
signal sig : bit_vector(1 downto 0);
begin
end architecture;
entity issue497 is
end entity;
architecture rtl of issue497 is
begin
i_test : entity work.test;
p_proc : process
alias sig is <<signal i_test.sig : bit_vector>>;
begin
assert sig = "00";
sig <= force "11";
wait for 1 ns;
assert sig = "11";
sig <= release;
wait for 1 ns;
assert sig = "00";
wait;
end process;
end architecture;
| gpl-3.0 | 5b8af2aa02ba9ab14c49c64856fa23a3 | 0.639839 | 3.427586 | false | true | false | false |
nickg/nvc | test/sem/seq.vhd | 1 | 6,767 | entity seq is
end entity;
architecture test of seq is
begin
-- If statements
process is
variable v : integer;
begin
if true then -- OK
report "hello";
end if;
if 1 then -- Not boolean
end if;
if false then
x := 5; -- Error in statement
end if;
if true or false then
null;
else
v := true; -- Error in else part
end if;
if false then
null;
elsif true then
null;
elsif x > 2 then
g := v; -- Error
else
v := 1;
end if;
end process;
-- Null statements
process is
begin
null;
end process;
-- Return statements
process is
begin
return 1; -- Error
end process;
-- While statements
process is
variable n : integer := 5;
begin
while n > 0 loop -- OK
n := n - 1;
end loop;
loop -- OK
null;
end loop;
loop
return 5; -- Error
end loop;
while 5 loop -- Error
null;
end loop;
end process;
-- For
process is
variable v : integer;
begin
for i in 0 to 10 loop -- OK
v := i + 1;
end loop;
for i in bit'range loop -- OK
null;
end loop;
for i in x'range loop -- Error
null;
end loop;
end process;
-- Case
process is
type letter is (A, B, C);
variable l : letter;
variable v : bit_vector(0 to 3);
constant k : bit := '1';
variable n : bit;
variable i : integer;
begin
l := A;
case l is -- OK
when a =>
null;
when b | c =>
null;
end case;
case l is -- OK
when a =>
null;
when others =>
null;
end case;
case l is -- Others not last
when others =>
null;
when a =>
null;
end case;
case l is
when l => -- Not locally static
null;
when others =>
end case;
case v is
when "0101" => -- OK
null;
when "1101" => -- OK
null;
end case;
case v is
when (0 to 3 => k) => -- OK
null;
when (0 to 3 => n) => -- Not locally static
null;
end case;
case i is
when 1 => -- OK
null;
when integer'(5) => -- OK
null;
when (1 + 5) * 7 => -- OK
null;
when i + 2 => -- Not locally static
null;
end case;
case bit is -- Error
when '1' => null;
when '0' => null;
end case;
case i is
when 1 to 6 => -- OK
null;
when 7 to 6.1612 => -- Error
null;
end case;
case i is
when n to k => -- Error
null;
end case;
case i is
when 1 to i => -- Error
null;
end case;
end process;
-- Exit
process is
begin
loop
exit when false; -- OK
exit when 1; -- Not boolean
end loop;
end process;
-- Procedure call
process is
procedure add1(x : in integer; y : out integer) is
begin
y := x + 1;
end procedure;
variable a, b : integer;
begin
add1(a, b); -- OK
add1(1, b); -- OK
add1(3, 6); -- Error
end process;
-- Next
process is
begin
loop
next when false; -- OK
next when 1; -- Not boolean
next; -- OK
end loop;
next; -- Not in loop
l1: loop
next foo; -- Not a label
end loop;
l2: loop
l3: loop
l4: loop
next l2; -- OK
end loop;
end loop;
end loop;
end process;
-- Statement labels
dup: process is begin end process;
dup: process is begin end process;
-- Loop over enumeration
process is
begin
for c in character loop -- OK
end loop;
for c in integer loop -- OK
end loop;
for c in real loop -- Error
end loop;
end process;
-- Signal assignment to variable
process is
variable i : integer;
begin
i <= 1; -- Error
end process;
-- Corner cases in discrete range
drange: process is
begin
for i in 1 range 1 to 2 loop -- Error
end loop;
for i in integer range 1.0 to 2.0 loop -- Error
end loop;
for i in real range real'(1.0) to real'(2.0) loop -- Error
end loop;
end process;
-- Variable assignment to aggregate
process is
type int_vec is array (natural range <>) of integer;
variable v : int_vec(1 to 2);
variable a, b : integer;
begin
(a, b) := v; -- OK
(a, 1) := v; -- Error
(v(a), b) := v; -- Error
(others => a) := v; -- Error
(1 to 2 => a) := v; -- Error
end process;
-- Wrong class for procedure arguments
process is
procedure p1(signal x : bit);
variable v : bit;
begin
p1(v); -- Error
p1('1'); -- Error
end process;
-- Invalid use of loop parameter
process is
procedure p1 (x : out integer);
begin
for i in 1 to 10 loop
i := 5; -- Error
p1(i); -- Error
end loop;
end process;
end architecture;
| gpl-3.0 | 3714319a5f5390d085e2127bfb4c334b | 0.371065 | 4.907179 | false | false | false | false |
DE5Amigos/SylvesterTheDE2Bot | DE2Botv3Fall16Main/i2c_oneshot_ctrl.vhd | 1 | 3,115 | -- Controller for the one-shot I2C master.
-- This is mostly a state machine used to control
-- the various muxes and registers used for the I2C
-- device.
-- Author: Kevin Johnson. Last modified: 18 June 2014
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity i2c_oneshot_ctrl is
port(
resetn : in std_logic;
clk : in std_logic;
i2c_busy : in std_logic;
tx_addr : out std_logic_vector(7 downto 0);
tx_byte : out std_logic_vector(7 downto 0);
comm_en : out std_logic
);
end entity;
architecture main of i2c_oneshot_ctrl is
-- Build an enumerated type for the state machine
type state_type is (delay, idle, Tx2, Tx1);
-- Register used to hold the current state
signal state : state_type;
type register_array is array(8 downto 0) of std_logic_vector(15 downto 0);
signal commands : register_array;
signal cmd_num : integer range 0 to 9;
signal go : std_logic; -- tells state machine when to leave idle
signal prev_busy : std_logic; -- previous value of i2c_busy
begin
tx_addr <= x"34"; -- set the I2C controller's address
commands(0) <=
x"1E00"; -- full reset
commands(1) <=
x"0E53"; -- dsp master, 16-bit, data on 2nd clock
commands(2) <=
x"1019"; -- usb mode, 32khz sampling
commands(3) <=
x"05F9"; -- 0db headphone volume
commands(4) <=
x"1201"; -- activate digital interface
commands(5) <=
x"0812"; -- dac-to-output, disable inputs
commands(6) <=
x"0180"; -- mute line-in
commands(7) <=
x"0C67"; -- power up dac and output
commands(8) <=
x"0A00"; -- disable dac soft mute
-- The main state machine
state_machine : process (clk, resetn)
begin
if resetn = '0' then
state <= delay;
comm_en <= '0';
cmd_num <= 9;
elsif (rising_edge(clk)) then
prev_busy <= i2c_busy; -- used to detect transitions
case state is
when delay => -- necessary for the controller to initialize
if cmd_num = 0 then
state <= idle;
else
cmd_num <= cmd_num - 1;
end if;
when idle =>
if cmd_num <= 8 then -- this is the signal to start
state <= Tx2;
tx_byte <= commands(cmd_num)(15 downto 8);
else -- not starting
state <= idle;
end if;
when Tx2 =>
comm_en <= '1'; -- safe to start transaction
if (prev_busy = '0') and (i2c_busy = '1') then -- busy just went high
tx_byte <= commands(cmd_num)(7 downto 0); -- prepare next byte
elsif (prev_busy = '1') and (i2c_busy = '0') then -- just went low
state <= Tx1;
end if;
when Tx1 =>
if (prev_busy = '0') and (i2c_busy = '1') then -- busy just went high
comm_en <= '0'; -- end communication
elsif (prev_busy = '1') and (i2c_busy = '0') then -- just went low
state <= idle;
cmd_num <= cmd_num + 1;
end if;
when others =>
state <= idle;
end case;
end if;
end process;
end main;
| mit | f0f78973bd255c6d124faae863d8d9f6 | 0.575281 | 3.108782 | false | false | false | false |
tgingold/ghdl | testsuite/synth/synth76/dff01.vhdl | 2 | 606 | library ieee;
use ieee.std_logic_1164.all;
entity dff01 is
port (q : out std_logic_vector (3 downto 0);
d : std_logic_vector (3 downto 0);
en : std_logic;
rst : std_logic;
clk : std_logic);
end dff01;
architecture behav of dff01 is
signal t : std_logic_vector (7 downto 0);
signal a : std_logic_vector (3 downto 0);
begin
a <= d xor b"0101";
process (clk) is
begin
if rst = '1' then
q <= x"0";
elsif rising_edge (clk) then
if en = '1' then
q <= d;
t (7 downto 4) <= a;
end if;
end if;
end process;
end behav;
| gpl-2.0 | ef13eb2634e807ca29b08fc6477fad15 | 0.559406 | 3.107692 | false | false | false | false |
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