repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
DE5Amigos/SylvesterTheDE2Bot | DE2Botv3Fall16Main/DAC_BEEP.vhd | 1 | 2,398 | LIBRARY IEEE;
LIBRARY ALTERA_MF;
LIBRARY LPM;
USE ALTERA_MF.ALTERA_MF_COMPONENTS.ALL;
USE LPM.LPM_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DAC_BEEP IS
PORT(
RESETN : IN STD_LOGIC;
FSEL : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DURATION : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CS : IN STD_LOGIC;
CLK_32Hz : IN STD_LOGIC;
DAC_WCLK : IN STD_LOGIC;
DAC_BCLK : IN STD_LOGIC;
DAC_DAT : OUT STD_LOGIC
);
END DAC_BEEP;
ARCHITECTURE a OF DAC_BEEP IS
signal timer : std_logic_vector(15 downto 0);
signal phase : std_logic_vector(15 downto 0);
signal step : std_logic_vector(7 downto 0);
signal sounddata : std_logic_vector(15 downto 0);
BEGIN
-- ROM to hold the waveform
SOUND_LUT : altsyncram
GENERIC MAP (
lpm_type => "altsyncram",
width_a => 16,
numwords_a => 512,
widthad_a => 9,
init_file => "SOUND.mif",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE"
)
PORT MAP (
clock0 => NOT(DAC_WCLK),
address_a => phase(10 DOWNTO 2), -- input is angle
q_a => sounddata -- output is amplitude
);
-- shift register to serialize the data to the DAC
DAC_SHIFT : lpm_shiftreg
GENERIC MAP (
lpm_direction => "LEFT",
lpm_type => "LPM_SHIFTREG",
lpm_width => 32
)
PORT MAP (
load => DAC_WCLK,
clock => NOT(DAC_BCLK),
data => sounddata & sounddata,
shiftout => DAC_DAT
);
-- process to perform DDS
PROCESS(RESETN, CS) BEGIN
IF RESETN = '0' THEN
phase <= x"0000";
ELSIF RISING_EDGE(DAC_WCLK) THEN
IF step = x"00" THEN
phase <= x"0000";
ELSE
phase <= phase + step; -- increment the phase
END IF;
END IF;
END PROCESS;
-- process to catch data from SCOMP and run the timer
PROCESS(RESETN, CS, CLK_32Hz) BEGIN
IF RESETN = '0' THEN
timer <= x"0000";
step <= x"00";
ELSIF CS = '1' THEN
timer <= ("000000"&DURATION&"00")-1; -- -1 so that 0 is infinite
step <= FSEL;
ELSIF RISING_EDGE(CLK_32Hz) THEN
IF timer /= x"FFFF" THEN
timer <= timer - 1;
IF timer = x"0000" THEN
step <= x"00";
END IF;
END IF;
END IF;
END PROCESS;
END a;
| mit | 74d2bb4160e062492cbe9e910af5e4f8 | 0.605505 | 2.949569 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2384.vhd | 4 | 3,733 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2384.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p06n03i02384ent IS
END c07s03b02x00p06n03i02384ent;
ARCHITECTURE c07s03b02x00p06n03i02384arch OF c07s03b02x00p06n03i02384ent IS
BEGIN
TESTING: PROCESS
-- Declare ascending and descending ranges.
subtype BYTE is BIT_VECTOR( 0 to 7 );
type NIBBLE is ARRAY ( 3 downto 0 ) of BIT;
-- Declare array variables of these types.
variable BYTEV : BYTE;
variable NIBV : NIBBLE;
BEGIN
-- Verify that they were initialized properly.
for I in 0 to 7 loop
assert( BYTEV( I ) = '0' );
end loop;
for I in 3 downto 0 loop
assert( NIBV( I ) = '0' );
end loop;
-- Set their values with aggregates and check them.
-- 1. Ascending first.
BYTEV := BYTE'( '1','1','1','1','1','1','1','0' );
assert( BYTEV( 0 ) = '1' );
assert( BYTEV( 1 ) = '1' );
assert( BYTEV( 2 ) = '1' );
assert( BYTEV( 3 ) = '1' );
assert( BYTEV( 4 ) = '1' );
assert( BYTEV( 5 ) = '1' );
assert( BYTEV( 6 ) = '1' );
assert( BYTEV( 7 ) = '0' );
-- 2. Descending next.
NIBV := NIBBLE'( '1','1','1','0' );
assert( NIBV( 1 ) = '1' );
assert( NIBV( 2 ) = '1' );
assert( NIBV( 3 ) = '1' );
assert( NIBV( 0 ) = '0' );
wait for 5 ns;
assert NOT( ( BYTEV( 0 ) = '1' ) and
( BYTEV( 1 ) = '1' ) and
( BYTEV( 2 ) = '1' ) and
( BYTEV( 3 ) = '1' ) and
( BYTEV( 4 ) = '1' ) and
( BYTEV( 5 ) = '1' ) and
( BYTEV( 6 ) = '1' ) and
( BYTEV( 7 ) = '0' ) and
( NIBV( 1 ) = '1' ) and
( NIBV( 2 ) = '1' ) and
( NIBV( 3 ) = '1' ) and
( NIBV( 0 ) = '0' ) )
report "***PASSED TEST: c07s03b02x00p06n03i02384"
severity NOTE;
assert ( ( BYTEV( 0 ) = '1' ) and
( BYTEV( 1 ) = '1' ) and
( BYTEV( 2 ) = '1' ) and
( BYTEV( 3 ) = '1' ) and
( BYTEV( 4 ) = '1' ) and
( BYTEV( 5 ) = '1' ) and
( BYTEV( 6 ) = '1' ) and
( BYTEV( 7 ) = '0' ) and
( NIBV( 1 ) = '1' ) and
( NIBV( 2 ) = '1' ) and
( NIBV( 3 ) = '1' ) and
( NIBV( 0 ) = '0' ) )
report "***FAILED TEST: c07s03b02x00p06n03i02384 - Element positional association test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p06n03i02384arch;
| gpl-2.0 | b5d53fe97ca3f5d19041a3ab1593fb87 | 0.502545 | 3.450092 | false | true | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mact-bv.vhd | 4 | 4,306 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_mact-bv.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture bench_verify of mac_test is
signal clk, clr, behavioral_ovf, rtl_ovf : std_ulogic := '0';
signal x_real, x_imag,
y_real, y_imag,
behavioral_s_real, behavioral_s_imag,
rtl_s_real, rtl_s_imag : std_ulogic_vector(15 downto 0);
type complex is record
re, im : real;
end record;
signal x, y, behavioral_s, rtl_s : complex := (0.0, 0.0);
constant Tpw_clk : time := 50 ns;
begin
x_real_converter : entity work.to_vector(behavioral) port map (x.re, x_real);
x_imag_converter : entity work.to_vector(behavioral) port map (x.im, x_imag);
y_real_converter : entity work.to_vector(behavioral) port map (y.re, y_real);
y_imag_converter : entity work.to_vector(behavioral) port map (y.im, y_imag);
dut_behavioral : entity work.mac(behavioral)
port map ( clk, clr,
x_real, x_imag, y_real, y_imag,
behavioral_s_real, behavioral_s_imag, behavioral_ovf );
dut_rtl : entity work.mac(rtl)
port map ( clk, clr,
x_real, x_imag, y_real, y_imag,
rtl_s_real, rtl_s_imag, rtl_ovf );
behavioral_s_real_converter :
entity work.to_fp(behavioral) port map (behavioral_s_real, behavioral_s.re);
behavioral_s_imag_converter :
entity work.to_fp(behavioral) port map (behavioral_s_imag, behavioral_s.im);
rtl_s_real_converter :
entity work.to_fp(behavioral) port map (rtl_s_real, rtl_s.re);
rtl_s_imag_converter :
entity work.to_fp(behavioral) port map (rtl_s_imag, rtl_s.im);
clock_gen : process is
begin
clk <= '1' after Tpw_clk, '0' after 2 * Tpw_clk;
wait for 2 * Tpw_clk;
end process clock_gen;
stimulus : process is
begin
-- first sequence
clr <= '1'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '1'; wait until clk = '0';
x <= (+0.2, +0.2); y <= (+0.2, +0.2); clr <= '1'; wait until clk = '0';
x <= (+0.1, -0.1); y <= (+0.1, +0.1); clr <= '1'; wait until clk = '0';
x <= (+0.1, -0.1); y <= (+0.1, +0.1); clr <= '0'; wait until clk = '0';
-- should be (0.4, 0.58) when it falls out the other end
clr <= '0'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '0'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.1, +0.1); clr <= '0'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '1'; wait until clk = '0';
x <= (-0.5, +0.5); y <= (-0.5, +0.5); clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '1'; wait until clk = '0';
wait;
end process stimulus;
verifier : process
constant epsilon : real := 4.0E-5; -- 1-bit error in 15-bit mantissa
begin
wait until clk = '0';
assert behavioral_ovf = rtl_ovf
report "Overflow flags differ" severity error;
if behavioral_ovf = '0' and rtl_ovf = '0' then
assert abs (behavioral_s.re - rtl_s.re) < epsilon
report "Real sums differ" severity error;
assert abs (behavioral_s.im - rtl_s.im) < epsilon
report "Imag sums differ" severity error;
end if;
end process verifier;
end architecture bench_verify;
| gpl-2.0 | b70406bfdd01c49527f7b503ff0ed1ce | 0.580585 | 3.106782 | false | false | false | false |
nickg/nvc | test/regress/elab35.vhd | 1 | 2,255 | library ieee;
use ieee.std_logic_1164.all;
package types_pkg is
type sl2d_t is array(natural range <>,natural range <>) of std_logic;
type slv_7_0_t is array(natural range <>) of std_logic_vector(7 downto 0);
subtype ram_bank_t is slv_7_0_t(0 to 32767);
type ram_t is array(0 to 3) of ram_bank_t;
end package;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.types_pkg.all;
entity sub is
generic (
width : integer;
depth_log2 : integer;
init : sl2d_t := (0 downto 1 => (0 downto 1 => '0'))
);
end entity;
architecture test of sub is
subtype ram_word_t is std_logic_vector(width-1 downto 0);
type ram_t is array(natural range <>) of ram_word_t;
function ram_init return ram_t is
variable r : ram_t(0 to (2**depth_log2)-1);
begin
r := (others => (others => '0'));
if init'high = r'high then
for i in 0 to r'length-1 loop
for j in 0 to width-1 loop
r(i)(j) := init(i,j);
end loop;
end loop;
end if;
return r;
end function ram_init;
signal ram : ram_t(0 to (2**depth_log2)-1) := ram_init;
begin
end architecture;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.types_pkg.all;
entity elab35 is
end entity;
architecture test of elab35 is
constant size_log2 : integer := 16;
function rambank2sl2d(constant x : ram_bank_t) return sl2d_t is
variable r : sl2d_t(0 to (2**(size_log2-2))-1,7 downto 0);
begin
for i in 0 to r'length-1 loop
for j in 0 to 7 loop
r(i,j) := x(i)(j);
end loop;
end loop;
return r;
end function rambank2sl2d;
constant ram_init : ram_t := (others => (others => (others => '0') ) );
begin
g: for i in 0 to 3 generate
RAM: entity work.sub
generic map (
width => 8,
depth_log2 => size_log2-2,
init => rambank2sl2d(ram_init(i))
);
end generate;
end architecture;
| gpl-3.0 | 9d8b6df7cd52fb87e65a6f1dff2b0a0b | 0.514856 | 3.469231 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_18.vhd | 4 | 2,727 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_18.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_07_18 is
end entity fg_07_18;
architecture test of fg_07_18 is
constant target_host_id : natural := 10;
constant my_host_id : natural := 5;
type pkt_types is (control_pkt, other_pkt);
type pkt_header is record
dest, src : natural;
pkt_type : pkt_types;
seq : natural;
end record;
begin
-- code from book
network_driver : process is
constant seq_modulo : natural := 2**5;
subtype seq_number is natural range 0 to seq_modulo-1;
variable next_seq_number : seq_number := 0;
-- . . .
-- not in book
variable new_header : pkt_header;
-- end not in book
impure function generate_seq_number return seq_number is
variable number : seq_number;
begin
number := next_seq_number;
next_seq_number := (next_seq_number + 1) mod seq_modulo;
return number;
end function generate_seq_number;
begin -- network_driver
-- not in book
wait for 10 ns;
-- end not in book
-- . . .
new_header := pkt_header'( dest => target_host_id,
src => my_host_id,
pkt_type => control_pkt,
seq => generate_seq_number );
-- . . .
end process network_driver;
-- end code from book
end architecture test;
| gpl-2.0 | 3a80a121bd1536252e30cb1ae2e68adc | 0.512285 | 4.661538 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug077/repro.vhdl | 1 | 539 | package pkg is
type my_inputs is record
a : bit;
w : bit_vector;
end record;
end pkg;
use work.pkg.all;
entity child is
port (i : my_inputs);
end;
architecture behav of child is
begin
assert i.w = (i.w'range => i.a);
end behav;
entity repro is
end repro;
use work.pkg.all;
architecture behav of repro is
signal s : bit_vector (7 downto 0);
signal a : bit;
begin
inst : entity work.child
port map(
i.a => a,
i.w => s);
process
begin
a <= '0';
s <= x"01";
wait;
end process;
end;
| gpl-2.0 | 55c19fbdae35516fca285e0d02293be1 | 0.602968 | 2.961538 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_register_s2mm.vhd | 3 | 174,357 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_register_s2mm.vhd
--
-- Description: This entity encompasses the channel register set.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_register_s2mm is
generic(
C_NUM_REGISTERS : integer := 11 ;
C_INCLUDE_SG : integer := 1 ;
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1 ;
C_MICRO_DMA : integer range 0 to 1 := 0 ;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
--C_CHANNEL_IS_S2MM : integer range 0 to 1 := 0 CR603034
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- AXI Interface Control --
axi2ip_wrce : in std_logic_vector --
(C_NUM_REGISTERS-1 downto 0) ; --
axi2ip_wrdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- DMASR Control --
stop_dma : in std_logic ; --
halted_clr : in std_logic ; --
halted_set : in std_logic ; --
idle_set : in std_logic ; --
idle_clr : in std_logic ; --
ioc_irq_set : in std_logic ; --
dly_irq_set : in std_logic ; --
irqdelay_status : in std_logic_vector(7 downto 0) ; --
irqthresh_status : in std_logic_vector(7 downto 0) ; --
irqthresh_wren : out std_logic ; --
irqdelay_wren : out std_logic ; --
dlyirq_dsble : out std_logic ; -- CR605888
--
-- Error Control --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
ftch_interr_set : in std_logic ; --
ftch_slverr_set : in std_logic ; --
ftch_decerr_set : in std_logic ; --
ftch_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_interr_set : in std_logic ; --
updt_slverr_set : in std_logic ; --
updt_decerr_set : in std_logic ; --
updt_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
error_in : in std_logic ; --
error_out : out std_logic ; --
introut : out std_logic ; --
soft_reset_in : in std_logic ; --
soft_reset_clr : in std_logic ; --
--
-- CURDESC Update --
update_curdesc : in std_logic ; --
tdest_in : in std_logic_vector (5 downto 0) ;
new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
-- TAILDESC Update --
tailpntr_updated : out std_logic ; --
--
-- Channel Register Out --
sg_ctl : out std_logic_vector (7 downto 0) ;
dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc1_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc1_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc1_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc1_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc2_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc2_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc2_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc2_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc3_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc3_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc3_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc3_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc4_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc4_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc4_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc4_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc5_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc5_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc5_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc5_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc6_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc6_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc6_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc6_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc7_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc7_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc7_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc7_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc8_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc8_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc8_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc8_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc9_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc9_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc9_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc9_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc10_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc10_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc10_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc10_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc11_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc11_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc11_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc11_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc12_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc12_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc12_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc12_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc13_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc13_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc13_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc13_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc14_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc14_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc14_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc14_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc15_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc15_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc15_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc15_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
buffer_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
buffer_length : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
buffer_length_wren : out std_logic ; --
bytes_received : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
bytes_received_wren : in std_logic --
); --
end axi_dma_register_s2mm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_register_s2mm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant SGCTL_INDEX : integer := 0;
constant DMACR_INDEX : integer := 1; -- DMACR Register index
constant DMASR_INDEX : integer := 2; -- DMASR Register index
constant CURDESC_LSB_INDEX : integer := 3; -- CURDESC LSB Reg index
constant CURDESC_MSB_INDEX : integer := 4; -- CURDESC MSB Reg index
constant TAILDESC_LSB_INDEX : integer := 5; -- TAILDESC LSB Reg index
constant TAILDESC_MSB_INDEX : integer := 6; -- TAILDESC MSB Reg index
constant CURDESC1_LSB_INDEX : integer := 17; -- CURDESC LSB Reg index
constant CURDESC1_MSB_INDEX : integer := 18; -- CURDESC MSB Reg index
constant TAILDESC1_LSB_INDEX : integer := 19; -- TAILDESC LSB Reg index
constant TAILDESC1_MSB_INDEX : integer := 20; -- TAILDESC MSB Reg index
constant CURDESC2_LSB_INDEX : integer := 25; -- CURDESC LSB Reg index
constant CURDESC2_MSB_INDEX : integer := 26; -- CURDESC MSB Reg index
constant TAILDESC2_LSB_INDEX : integer := 27; -- TAILDESC LSB Reg index
constant TAILDESC2_MSB_INDEX : integer := 28; -- TAILDESC MSB Reg index
constant CURDESC3_LSB_INDEX : integer := 33; -- CURDESC LSB Reg index
constant CURDESC3_MSB_INDEX : integer := 34; -- CURDESC MSB Reg index
constant TAILDESC3_LSB_INDEX : integer := 35; -- TAILDESC LSB Reg index
constant TAILDESC3_MSB_INDEX : integer := 36; -- TAILDESC MSB Reg index
constant CURDESC4_LSB_INDEX : integer := 41; -- CURDESC LSB Reg index
constant CURDESC4_MSB_INDEX : integer := 42; -- CURDESC MSB Reg index
constant TAILDESC4_LSB_INDEX : integer := 43; -- TAILDESC LSB Reg index
constant TAILDESC4_MSB_INDEX : integer := 44; -- TAILDESC MSB Reg index
constant CURDESC5_LSB_INDEX : integer := 49; -- CURDESC LSB Reg index
constant CURDESC5_MSB_INDEX : integer := 50; -- CURDESC MSB Reg index
constant TAILDESC5_LSB_INDEX : integer := 51; -- TAILDESC LSB Reg index
constant TAILDESC5_MSB_INDEX : integer := 52; -- TAILDESC MSB Reg index
constant CURDESC6_LSB_INDEX : integer := 57; -- CURDESC LSB Reg index
constant CURDESC6_MSB_INDEX : integer := 58; -- CURDESC MSB Reg index
constant TAILDESC6_LSB_INDEX : integer := 59; -- TAILDESC LSB Reg index
constant TAILDESC6_MSB_INDEX : integer := 60; -- TAILDESC MSB Reg index
constant CURDESC7_LSB_INDEX : integer := 65; -- CURDESC LSB Reg index
constant CURDESC7_MSB_INDEX : integer := 66; -- CURDESC MSB Reg index
constant TAILDESC7_LSB_INDEX : integer := 67; -- TAILDESC LSB Reg index
constant TAILDESC7_MSB_INDEX : integer := 68; -- TAILDESC MSB Reg index
constant CURDESC8_LSB_INDEX : integer := 73; -- CURDESC LSB Reg index
constant CURDESC8_MSB_INDEX : integer := 74; -- CURDESC MSB Reg index
constant TAILDESC8_LSB_INDEX : integer := 75; -- TAILDESC LSB Reg index
constant TAILDESC8_MSB_INDEX : integer := 76; -- TAILDESC MSB Reg index
constant CURDESC9_LSB_INDEX : integer := 81; -- CURDESC LSB Reg index
constant CURDESC9_MSB_INDEX : integer := 82; -- CURDESC MSB Reg index
constant TAILDESC9_LSB_INDEX : integer := 83; -- TAILDESC LSB Reg index
constant TAILDESC9_MSB_INDEX : integer := 84; -- TAILDESC MSB Reg index
constant CURDESC10_LSB_INDEX : integer := 89; -- CURDESC LSB Reg index
constant CURDESC10_MSB_INDEX : integer := 90; -- CURDESC MSB Reg index
constant TAILDESC10_LSB_INDEX : integer := 91; -- TAILDESC LSB Reg index
constant TAILDESC10_MSB_INDEX : integer := 92; -- TAILDESC MSB Reg index
constant CURDESC11_LSB_INDEX : integer := 97; -- CURDESC LSB Reg index
constant CURDESC11_MSB_INDEX : integer := 98; -- CURDESC MSB Reg index
constant TAILDESC11_LSB_INDEX : integer := 99; -- TAILDESC LSB Reg index
constant TAILDESC11_MSB_INDEX : integer := 100; -- TAILDESC MSB Reg index
constant CURDESC12_LSB_INDEX : integer := 105; -- CURDESC LSB Reg index
constant CURDESC12_MSB_INDEX : integer := 106; -- CURDESC MSB Reg index
constant TAILDESC12_LSB_INDEX : integer := 107; -- TAILDESC LSB Reg index
constant TAILDESC12_MSB_INDEX : integer := 108; -- TAILDESC MSB Reg index
constant CURDESC13_LSB_INDEX : integer := 113; -- CURDESC LSB Reg index
constant CURDESC13_MSB_INDEX : integer := 114; -- CURDESC MSB Reg index
constant TAILDESC13_LSB_INDEX : integer := 115; -- TAILDESC LSB Reg index
constant TAILDESC13_MSB_INDEX : integer := 116; -- TAILDESC MSB Reg index
constant CURDESC14_LSB_INDEX : integer := 121; -- CURDESC LSB Reg index
constant CURDESC14_MSB_INDEX : integer := 122; -- CURDESC MSB Reg index
constant TAILDESC14_LSB_INDEX : integer := 123; -- TAILDESC LSB Reg index
constant TAILDESC14_MSB_INDEX : integer := 124; -- TAILDESC MSB Reg index
constant CURDESC15_LSB_INDEX : integer := 129; -- CURDESC LSB Reg index
constant CURDESC15_MSB_INDEX : integer := 130; -- CURDESC MSB Reg index
constant TAILDESC15_LSB_INDEX : integer := 131; -- TAILDESC LSB Reg index
constant TAILDESC15_MSB_INDEX : integer := 132; -- TAILDESC MSB Reg index
-- CR603034 moved s2mm back to offset 6
--constant SA_ADDRESS_INDEX : integer := 6; -- Buffer Address Reg (SA)
--constant DA_ADDRESS_INDEX : integer := 8; -- Buffer Address Reg (DA)
--
--
--constant BUFF_ADDRESS_INDEX : integer := address_index_select -- Buffer Address Reg (SA or DA)
-- (C_CHANNEL_IS_S2MM, -- Channel Type 1=rx 0=tx
-- SA_ADDRESS_INDEX, -- Source Address Index
-- DA_ADDRESS_INDEX); -- Destination Address Index
constant BUFF_ADDRESS_INDEX : integer := 7;
constant BUFF_ADDRESS_MSB_INDEX : integer := 8;
constant BUFF_LENGTH_INDEX : integer := 11; -- Buffer Length Reg
constant ZERO_VALUE : std_logic_vector(31 downto 0) := (others => '0');
constant DMA_CONFIG : std_logic_vector(0 downto 0)
:= std_logic_vector(to_unsigned(C_INCLUDE_SG,1));
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal dmacr_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal dmasr_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 6) := (others => '0');
signal curdesc_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 6) := (others => '0');
signal taildesc_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal buffer_address_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal buffer_address_64_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal buffer_length_i : std_logic_vector
(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal curdesc1_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc1_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc1_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc1_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc2_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc2_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc2_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc2_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc3_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc3_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc3_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc3_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc4_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc4_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc4_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc4_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc5_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc5_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc5_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc5_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc6_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc6_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc6_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc6_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc7_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc7_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc7_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc7_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc8_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc8_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc8_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc8_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc9_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc9_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc9_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc9_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc10_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc10_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc10_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc10_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc11_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc11_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc11_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc11_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc12_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc12_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc12_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc12_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc13_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc13_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc13_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc13_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc14_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc14_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc14_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc14_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc15_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc15_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc15_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc15_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal update_curdesc1 : std_logic := '0';
signal update_curdesc2 : std_logic := '0';
signal update_curdesc3 : std_logic := '0';
signal update_curdesc4 : std_logic := '0';
signal update_curdesc5 : std_logic := '0';
signal update_curdesc6 : std_logic := '0';
signal update_curdesc7 : std_logic := '0';
signal update_curdesc8 : std_logic := '0';
signal update_curdesc9 : std_logic := '0';
signal update_curdesc10 : std_logic := '0';
signal update_curdesc11 : std_logic := '0';
signal update_curdesc12 : std_logic := '0';
signal update_curdesc13 : std_logic := '0';
signal update_curdesc14 : std_logic := '0';
signal update_curdesc15 : std_logic := '0';
signal dest0 : std_logic := '0';
signal dest1 : std_logic := '0';
signal dest2 : std_logic := '0';
signal dest3 : std_logic := '0';
signal dest4 : std_logic := '0';
signal dest5 : std_logic := '0';
signal dest6 : std_logic := '0';
signal dest7 : std_logic := '0';
signal dest8 : std_logic := '0';
signal dest9 : std_logic := '0';
signal dest10 : std_logic := '0';
signal dest11 : std_logic := '0';
signal dest12 : std_logic := '0';
signal dest13 : std_logic := '0';
signal dest14 : std_logic := '0';
signal dest15 : std_logic := '0';
-- DMASR Signals
signal halted : std_logic := '0';
signal idle : std_logic := '0';
signal cmplt : std_logic := '0';
signal error : std_logic := '0';
signal dma_interr : std_logic := '0';
signal dma_slverr : std_logic := '0';
signal dma_decerr : std_logic := '0';
signal sg_interr : std_logic := '0';
signal sg_slverr : std_logic := '0';
signal sg_decerr : std_logic := '0';
signal ioc_irq : std_logic := '0';
signal dly_irq : std_logic := '0';
signal error_d1 : std_logic := '0';
signal error_re : std_logic := '0';
signal err_irq : std_logic := '0';
signal sg_ftch_error : std_logic := '0';
signal sg_updt_error : std_logic := '0';
signal error_pointer_set : std_logic := '0';
signal error_pointer_set1 : std_logic := '0';
signal error_pointer_set2 : std_logic := '0';
signal error_pointer_set3 : std_logic := '0';
signal error_pointer_set4 : std_logic := '0';
signal error_pointer_set5 : std_logic := '0';
signal error_pointer_set6 : std_logic := '0';
signal error_pointer_set7 : std_logic := '0';
signal error_pointer_set8 : std_logic := '0';
signal error_pointer_set9 : std_logic := '0';
signal error_pointer_set10 : std_logic := '0';
signal error_pointer_set11 : std_logic := '0';
signal error_pointer_set12 : std_logic := '0';
signal error_pointer_set13 : std_logic := '0';
signal error_pointer_set14 : std_logic := '0';
signal error_pointer_set15 : std_logic := '0';
-- interrupt coalescing support signals
signal different_delay : std_logic := '0';
signal different_thresh : std_logic := '0';
signal threshold_is_zero : std_logic := '0';
-- soft reset support signals
signal soft_reset_i : std_logic := '0';
signal run_stop_clr : std_logic := '0';
signal tail_update_lsb : std_logic := '0';
signal tail_update_msb : std_logic := '0';
signal sg_cache_info : std_logic_vector (7 downto 0);
signal halt_free : std_logic := '0';
signal tmp11 : std_logic := '0';
signal sig_cur_updated : std_logic := '0';
signal tailpntr_updated_d1 : std_logic;
signal tailpntr_updated_d2 : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
GEN_MULTI_CH : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
halt_free <= '1';
end generate GEN_MULTI_CH;
GEN_NOMULTI_CH : if C_ENABLE_MULTI_CHANNEL = 0 generate
begin
halt_free <= dmasr_i(DMASR_HALTED_BIT);
end generate GEN_NOMULTI_CH;
GEN_DESC_UPDATE_FOR_SG : if C_NUM_S2MM_CHANNELS = 1 generate
begin
update_curdesc1 <= '0';
update_curdesc2 <= '0';
update_curdesc3 <= '0';
update_curdesc4 <= '0';
update_curdesc5 <= '0';
update_curdesc6 <= '0';
update_curdesc7 <= '0';
update_curdesc8 <= '0';
update_curdesc9 <= '0';
update_curdesc10 <= '0';
update_curdesc11 <= '0';
update_curdesc12 <= '0';
update_curdesc13 <= '0';
update_curdesc14 <= '0';
update_curdesc15 <= '0';
end generate GEN_DESC_UPDATE_FOR_SG;
dest0 <= '1' when tdest_in (4 downto 0) = "00000" else '0';
dest1 <= '1' when tdest_in (4 downto 0) = "00001" else '0';
dest2 <= '1' when tdest_in (4 downto 0) = "00010" else '0';
dest3 <= '1' when tdest_in (4 downto 0) = "00011" else '0';
dest4 <= '1' when tdest_in (4 downto 0) = "00100" else '0';
dest5 <= '1' when tdest_in (4 downto 0) = "00101" else '0';
dest6 <= '1' when tdest_in (4 downto 0) = "00110" else '0';
dest7 <= '1' when tdest_in (4 downto 0) = "00111" else '0';
dest8 <= '1' when tdest_in (4 downto 0) = "01000" else '0';
dest9 <= '1' when tdest_in (4 downto 0) = "01001" else '0';
dest10 <= '1' when tdest_in (4 downto 0) = "01010" else '0';
dest11 <= '1' when tdest_in (4 downto 0) = "01011" else '0';
dest12 <= '1' when tdest_in (4 downto 0) = "01100" else '0';
dest13 <= '1' when tdest_in (4 downto 0) = "01101" else '0';
dest14 <= '1' when tdest_in (4 downto 0) = "01110" else '0';
dest15 <= '1' when tdest_in (4 downto 0) = "01111" else '0';
GEN_DESC_UPDATE_FOR_SG_CH : if C_NUM_S2MM_CHANNELS > 1 generate
update_curdesc1 <= update_curdesc when tdest_in (4 downto 0) = "00001" else '0';
update_curdesc2 <= update_curdesc when tdest_in (4 downto 0) = "00010" else '0';
update_curdesc3 <= update_curdesc when tdest_in (4 downto 0) = "00011" else '0';
update_curdesc4 <= update_curdesc when tdest_in (4 downto 0) = "00100" else '0';
update_curdesc5 <= update_curdesc when tdest_in (4 downto 0) = "00101" else '0';
update_curdesc6 <= update_curdesc when tdest_in (4 downto 0) = "00110" else '0';
update_curdesc7 <= update_curdesc when tdest_in (4 downto 0) = "00111" else '0';
update_curdesc8 <= update_curdesc when tdest_in (4 downto 0) = "01000" else '0';
update_curdesc9 <= update_curdesc when tdest_in (4 downto 0) = "01001" else '0';
update_curdesc10 <= update_curdesc when tdest_in (4 downto 0) = "01010" else '0';
update_curdesc11 <= update_curdesc when tdest_in (4 downto 0) = "01011" else '0';
update_curdesc12 <= update_curdesc when tdest_in (4 downto 0) = "01100" else '0';
update_curdesc13 <= update_curdesc when tdest_in (4 downto 0) = "01101" else '0';
update_curdesc14 <= update_curdesc when tdest_in (4 downto 0) = "01110" else '0';
update_curdesc15 <= update_curdesc when tdest_in (4 downto 0) = "01111" else '0';
end generate GEN_DESC_UPDATE_FOR_SG_CH;
GEN_DA_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
buffer_address <= buffer_address_64_i & buffer_address_i ;
end generate GEN_DA_ADDR_EQL64;
GEN_DA_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
buffer_address <= buffer_address_i ;
end generate GEN_DA_ADDR_EQL32;
dmacr <= dmacr_i ;
dmasr <= dmasr_i ;
curdesc_lsb <= curdesc_lsb_i (31 downto 6) & "000000" ;
curdesc_msb <= curdesc_msb_i ;
taildesc_lsb <= taildesc_lsb_i (31 downto 6) & "000000" ;
taildesc_msb <= taildesc_msb_i ;
buffer_length <= buffer_length_i ;
curdesc1_lsb <= curdesc1_lsb_i ;
curdesc1_msb <= curdesc1_msb_i ;
taildesc1_lsb <= taildesc1_lsb_i ;
taildesc1_msb <= taildesc1_msb_i ;
curdesc2_lsb <= curdesc2_lsb_i ;
curdesc2_msb <= curdesc2_msb_i ;
taildesc2_lsb <= taildesc2_lsb_i ;
taildesc2_msb <= taildesc2_msb_i ;
curdesc3_lsb <= curdesc3_lsb_i ;
curdesc3_msb <= curdesc3_msb_i ;
taildesc3_lsb <= taildesc3_lsb_i ;
taildesc3_msb <= taildesc3_msb_i ;
curdesc4_lsb <= curdesc4_lsb_i ;
curdesc4_msb <= curdesc4_msb_i ;
taildesc4_lsb <= taildesc4_lsb_i ;
taildesc4_msb <= taildesc4_msb_i ;
curdesc5_lsb <= curdesc5_lsb_i ;
curdesc5_msb <= curdesc5_msb_i ;
taildesc5_lsb <= taildesc5_lsb_i ;
taildesc5_msb <= taildesc5_msb_i ;
curdesc6_lsb <= curdesc6_lsb_i ;
curdesc6_msb <= curdesc6_msb_i ;
taildesc6_lsb <= taildesc6_lsb_i ;
taildesc6_msb <= taildesc6_msb_i ;
curdesc7_lsb <= curdesc7_lsb_i ;
curdesc7_msb <= curdesc7_msb_i ;
taildesc7_lsb <= taildesc7_lsb_i ;
taildesc7_msb <= taildesc7_msb_i ;
curdesc8_lsb <= curdesc8_lsb_i ;
curdesc8_msb <= curdesc8_msb_i ;
taildesc8_lsb <= taildesc8_lsb_i ;
taildesc8_msb <= taildesc8_msb_i ;
curdesc9_lsb <= curdesc9_lsb_i ;
curdesc9_msb <= curdesc9_msb_i ;
taildesc9_lsb <= taildesc9_lsb_i ;
taildesc9_msb <= taildesc9_msb_i ;
curdesc10_lsb <= curdesc10_lsb_i ;
curdesc10_msb <= curdesc10_msb_i ;
taildesc10_lsb <= taildesc10_lsb_i ;
taildesc10_msb <= taildesc10_msb_i ;
curdesc11_lsb <= curdesc11_lsb_i ;
curdesc11_msb <= curdesc11_msb_i ;
taildesc11_lsb <= taildesc11_lsb_i ;
taildesc11_msb <= taildesc11_msb_i ;
curdesc12_lsb <= curdesc12_lsb_i ;
curdesc12_msb <= curdesc12_msb_i ;
taildesc12_lsb <= taildesc12_lsb_i ;
taildesc12_msb <= taildesc12_msb_i ;
curdesc13_lsb <= curdesc13_lsb_i ;
curdesc13_msb <= curdesc13_msb_i ;
taildesc13_lsb <= taildesc13_lsb_i ;
taildesc13_msb <= taildesc13_msb_i ;
curdesc14_lsb <= curdesc14_lsb_i ;
curdesc14_msb <= curdesc14_msb_i ;
taildesc14_lsb <= taildesc14_lsb_i ;
taildesc14_msb <= taildesc14_msb_i ;
curdesc15_lsb <= curdesc15_lsb_i ;
curdesc15_msb <= curdesc15_msb_i ;
taildesc15_lsb <= taildesc15_lsb_i ;
taildesc15_msb <= taildesc15_msb_i ;
---------------------------------------------------------------------------
-- DMA Control Register
---------------------------------------------------------------------------
-- DMACR - Interrupt Delay Value
-------------------------------------------------------------------------------
DMACR_DELAY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT);
end if;
end if;
end process DMACR_DELAY;
-- If written delay is different than previous value then assert write enable
different_delay <= '1' when dmacr_i(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT)
/= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT)
else '0';
-- delay value different, drive write of delay value to interrupt controller
NEW_DELAY_WRITE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
irqdelay_wren <= '0';
-- If AXI Lite write to DMACR and delay different than current
-- setting then update delay value
elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_delay = '1')then
irqdelay_wren <= '1';
else
irqdelay_wren <= '0';
end if;
end if;
end process NEW_DELAY_WRITE;
-------------------------------------------------------------------------------
-- DMACR - Interrupt Threshold Value
-------------------------------------------------------------------------------
threshold_is_zero <= '1' when axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) = ZERO_THRESHOLD
else '0';
DMACR_THRESH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
-- On AXI Lite write
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
-- If value is 0 then set threshold to 1
if(threshold_is_zero='1')then
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
-- else set threshold to axi lite wrdata value
else
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT);
end if;
end if;
end if;
end process DMACR_THRESH;
-- If written threshold is different than previous value then assert write enable
different_thresh <= '1' when dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT)
/= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT)
else '0';
-- new treshold written therefore drive write of threshold out
NEW_THRESH_WRITE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
irqthresh_wren <= '0';
-- If AXI Lite write to DMACR and threshold different than current
-- setting then update threshold value
elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_thresh = '1')then
irqthresh_wren <= '1';
else
irqthresh_wren <= '0';
end if;
end if;
end process NEW_THRESH_WRITE;
-------------------------------------------------------------------------------
-- DMACR - Remainder of DMA Control Register, Key Hole write bit (3)
-------------------------------------------------------------------------------
DMACR_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1
downto DMACR_RESERVED5_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1 -- bit 15
downto DMACR_RESERVED5_BIT) <= ZERO_VALUE(DMACR_RESERVED15_BIT)
-- bit 14
& axi2ip_wrdata(DMACR_ERR_IRQEN_BIT)
-- bit 13
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT)
-- bit 12
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT)
-- bits 11 downto 3
& ZERO_VALUE(DMACR_RESERVED11_BIT downto DMACR_RESERVED5_BIT);
end if;
end if;
end process DMACR_REGISTER;
DMACR_REGISTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or C_ENABLE_MULTI_CHANNEL = 1)then
dmacr_i(DMACR_KH_BIT) <= '0';
dmacr_i(CYCLIC_BIT) <= '0';
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_KH_BIT) <= axi2ip_wrdata(DMACR_KH_BIT);
dmacr_i(CYCLIC_BIT) <= axi2ip_wrdata(CYCLIC_BIT);
end if;
end if;
end process DMACR_REGISTER1;
-------------------------------------------------------------------------------
-- DMACR - Reset Bit
-------------------------------------------------------------------------------
DMACR_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(soft_reset_clr = '1')then
dmacr_i(DMACR_RESET_BIT) <= '0';
-- If soft reset set in other channel then set
-- reset bit here too
elsif(soft_reset_in = '1')then
dmacr_i(DMACR_RESET_BIT) <= '1';
-- If DMACR Write then pass axi lite write bus to DMARC reset bit
elsif(soft_reset_i = '0' and axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_RESET_BIT) <= axi2ip_wrdata(DMACR_RESET_BIT);
end if;
end if;
end process DMACR_RESET;
soft_reset_i <= dmacr_i(DMACR_RESET_BIT);
-------------------------------------------------------------------------------
-- Tail Pointer Enable fixed at 1 for this release of axi dma
-------------------------------------------------------------------------------
dmacr_i(DMACR_TAILPEN_BIT) <= '1';
-------------------------------------------------------------------------------
-- DMACR - Run/Stop Bit
-------------------------------------------------------------------------------
run_stop_clr <= '1' when error = '1' -- MM2S DataMover Error
or error_in = '1' -- S2MM Error
or stop_dma = '1' -- Stop due to error
or soft_reset_i = '1' -- MM2S Soft Reset
or soft_reset_in = '1' -- S2MM Soft Reset
else '0';
DMACR_RUNSTOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_RS_BIT) <= '0';
-- Clear on sg error (i.e. error) or other channel
-- error (i.e. error_in) or dma error or soft reset
elsif(run_stop_clr = '1')then
dmacr_i(DMACR_RS_BIT) <= '0';
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_RS_BIT) <= axi2ip_wrdata(DMACR_RS_BIT);
end if;
end if;
end process DMACR_RUNSTOP;
---------------------------------------------------------------------------
-- DMA Status Halted bit (BIT 0) - Set by dma controller indicating DMA
-- channel is halted.
---------------------------------------------------------------------------
DMASR_HALTED : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or halted_set = '1')then
halted <= '1';
elsif(halted_clr = '1')then
halted <= '0';
end if;
end if;
end process DMASR_HALTED;
---------------------------------------------------------------------------
-- DMA Status Idle bit (BIT 1) - Set by dma controller indicating DMA
-- channel is IDLE waiting at tail pointer. Update of Tail Pointer
-- will cause engine to resume. Note: Halted channels return to a
-- reset condition.
---------------------------------------------------------------------------
DMASR_IDLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0'
or idle_clr = '1'
or halted_set = '1')then
idle <= '0';
elsif(idle_set = '1')then
idle <= '1';
end if;
end if;
end process DMASR_IDLE;
---------------------------------------------------------------------------
-- DMA Status Error bit (BIT 3)
-- Note: any error will cause entire engine to halt
---------------------------------------------------------------------------
error <= dma_interr
or dma_slverr
or dma_decerr
or sg_interr
or sg_slverr
or sg_decerr;
-- Scatter Gather Error
--sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set;
-- SG Update Errors or DMA errors assert flag on descriptor update
-- Used to latch current descriptor pointer
--sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set
-- or dma_interr or dma_slverr or dma_decerr;
-- Map out to halt opposing channel
error_out <= error;
SG_FTCH_ERROR_PROC : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_ftch_error <= '0';
sg_updt_error <= '0';
else
sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set;
sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set
or dma_interr or dma_slverr or dma_decerr;
end if;
end if;
end process SG_FTCH_ERROR_PROC;
---------------------------------------------------------------------------
-- DMA Status DMA Internal Error bit (BIT 4)
---------------------------------------------------------------------------
DMASR_DMAINTERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dma_interr <= '0';
elsif(dma_interr_set = '1' )then
dma_interr <= '1';
end if;
end if;
end process DMASR_DMAINTERR;
---------------------------------------------------------------------------
-- DMA Status DMA Slave Error bit (BIT 5)
---------------------------------------------------------------------------
DMASR_DMASLVERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dma_slverr <= '0';
elsif(dma_slverr_set = '1' )then
dma_slverr <= '1';
end if;
end if;
end process DMASR_DMASLVERR;
---------------------------------------------------------------------------
-- DMA Status DMA Decode Error bit (BIT 6)
---------------------------------------------------------------------------
DMASR_DMADECERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dma_decerr <= '0';
elsif(dma_decerr_set = '1' )then
dma_decerr <= '1';
end if;
end if;
end process DMASR_DMADECERR;
---------------------------------------------------------------------------
-- DMA Status SG Internal Error bit (BIT 8)
-- (SG Mode only - trimmed at build time if simple mode)
---------------------------------------------------------------------------
DMASR_SGINTERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_interr <= '0';
elsif(ftch_interr_set = '1' or updt_interr_set = '1')then
sg_interr <= '1';
end if;
end if;
end process DMASR_SGINTERR;
---------------------------------------------------------------------------
-- DMA Status SG Slave Error bit (BIT 9)
-- (SG Mode only - trimmed at build time if simple mode)
---------------------------------------------------------------------------
DMASR_SGSLVERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_slverr <= '0';
elsif(ftch_slverr_set = '1' or updt_slverr_set = '1')then
sg_slverr <= '1';
end if;
end if;
end process DMASR_SGSLVERR;
---------------------------------------------------------------------------
-- DMA Status SG Decode Error bit (BIT 10)
-- (SG Mode only - trimmed at build time if simple mode)
---------------------------------------------------------------------------
DMASR_SGDECERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_decerr <= '0';
elsif(ftch_decerr_set = '1' or updt_decerr_set = '1')then
sg_decerr <= '1';
end if;
end if;
end process DMASR_SGDECERR;
---------------------------------------------------------------------------
-- DMA Status IOC Interrupt status bit (BIT 11)
---------------------------------------------------------------------------
DMASR_IOCIRQ : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ioc_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
ioc_irq <= (ioc_irq and not(axi2ip_wrdata(DMASR_IOCIRQ_BIT)))
or ioc_irq_set;
elsif(ioc_irq_set = '1')then
ioc_irq <= '1';
end if;
end if;
end process DMASR_IOCIRQ;
---------------------------------------------------------------------------
-- DMA Status Delay Interrupt status bit (BIT 12)
---------------------------------------------------------------------------
DMASR_DLYIRQ : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dly_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
dly_irq <= (dly_irq and not(axi2ip_wrdata(DMASR_DLYIRQ_BIT)))
or dly_irq_set;
elsif(dly_irq_set = '1')then
dly_irq <= '1';
end if;
end if;
end process DMASR_DLYIRQ;
-- CR605888 Disable delay timer if halted or on delay irq set
--dlyirq_dsble <= dmasr_i(DMASR_HALTED_BIT) -- CR606348
dlyirq_dsble <= not dmacr_i(DMACR_RS_BIT) -- CR606348
or dmasr_i(DMASR_DLYIRQ_BIT);
---------------------------------------------------------------------------
-- DMA Status Error Interrupt status bit (BIT 12)
---------------------------------------------------------------------------
-- Delay error setting for generation of error strobe
GEN_ERROR_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
error_d1 <= '0';
else
error_d1 <= error;
end if;
end if;
end process GEN_ERROR_RE;
-- Generate rising edge pulse on error
error_re <= error and not error_d1;
DMASR_ERRIRQ : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
err_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
err_irq <= (err_irq and not(axi2ip_wrdata(DMASR_ERRIRQ_BIT)))
or error_re;
elsif(error_re = '1')then
err_irq <= '1';
end if;
end if;
end process DMASR_ERRIRQ;
---------------------------------------------------------------------------
-- DMA Interrupt OUT
---------------------------------------------------------------------------
REG_INTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or soft_reset_i = '1')then
introut <= '0';
else
introut <= (dly_irq and dmacr_i(DMACR_DLY_IRQEN_BIT))
or (ioc_irq and dmacr_i(DMACR_IOC_IRQEN_BIT))
or (err_irq and dmacr_i(DMACR_ERR_IRQEN_BIT));
end if;
end if;
end process;
---------------------------------------------------------------------------
-- DMA Status Register
---------------------------------------------------------------------------
dmasr_i <= irqdelay_status -- Bits 31 downto 24
& irqthresh_status -- Bits 23 downto 16
& '0' -- Bit 15
& err_irq -- Bit 14
& dly_irq -- Bit 13
& ioc_irq -- Bit 12
& '0' -- Bit 11
& sg_decerr -- Bit 10
& sg_slverr -- Bit 9
& sg_interr -- Bit 8
& '0' -- Bit 7
& dma_decerr -- Bit 6
& dma_slverr -- Bit 5
& dma_interr -- Bit 4
& DMA_CONFIG -- Bit 3
& '0' -- Bit 2
& idle -- Bit 1
& halted; -- Bit 0
-- Generate current descriptor and tail descriptor register for Scatter Gather Mode
GEN_DESC_REG_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
GEN_SG_CTL_REG : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
MM2S_SGCTL : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_cache_info <= "00000011"; --(others => '0');
elsif(axi2ip_wrce(SGCTL_INDEX) = '1' ) then
sg_cache_info <= axi2ip_wrdata(11 downto 8) & axi2ip_wrdata(3 downto 0);
else
sg_cache_info <= sg_cache_info;
end if;
end if;
end process MM2S_SGCTL;
sg_ctl <= sg_cache_info;
end generate GEN_SG_CTL_REG;
GEN_SG_NO_CTL_REG : if C_ENABLE_MULTI_CHANNEL = 0 generate
begin
sg_ctl <= "00000011"; --(others => '0');
end generate GEN_SG_NO_CTL_REG;
-- Signals not used for Scatter Gather Mode, only simple mode
buffer_address_i <= (others => '0');
buffer_length_i <= (others => '0');
buffer_length_wren <= '0';
---------------------------------------------------------------------------
-- Current Descriptor LSB Register
---------------------------------------------------------------------------
CURDESC_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc_lsb_i <= (others => '0');
error_pointer_set <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest0 = '1')then
curdesc_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 6);
error_pointer_set <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest0 = '1')then
-- curdesc_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest0 = '1')then
curdesc_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 6);
error_pointer_set <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC_LSB_INDEX) = '1' and halt_free = '1')then
curdesc_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT);
-- & ZERO_VALUE(CURDESC_RESERVED_BIT5
-- downto CURDESC_RESERVED_BIT0);
error_pointer_set <= '0';
end if;
end if;
end if;
end process CURDESC_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC_LSB_INDEX) = '1')then
taildesc_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT);
-- & ZERO_VALUE(TAILDESC_RESERVED_BIT5
-- downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC_LSB_REGISTER;
GEN_DESC1_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 1 generate
CURDESC1_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc1_lsb_i <= (others => '0');
error_pointer_set1 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set1 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest1 = '1')then
curdesc1_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set1 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest1 = '1')then
-- curdesc1_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set1 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc1 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest1 = '1')then
curdesc1_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set1 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC1_LSB_INDEX) = '1' and halt_free = '1')then
curdesc1_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set1 <= '0';
end if;
end if;
end if;
end process CURDESC1_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC1_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc1_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC1_LSB_INDEX) = '1')then
taildesc1_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC1_LSB_REGISTER;
end generate GEN_DESC1_REG_FOR_SG;
GEN_DESC2_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 2 generate
CURDESC2_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc2_lsb_i <= (others => '0');
error_pointer_set2 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set2 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest2 = '1')then
curdesc2_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set2 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest2 = '1')then
-- curdesc2_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set2 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc2 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest2 = '1')then
curdesc2_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set2 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC2_LSB_INDEX) = '1' and halt_free = '1')then
curdesc2_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set2 <= '0';
end if;
end if;
end if;
end process CURDESC2_LSB_REGISTER;
TAILDESC2_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc2_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC2_LSB_INDEX) = '1')then
taildesc2_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC2_LSB_REGISTER;
end generate GEN_DESC2_REG_FOR_SG;
GEN_DESC3_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 3 generate
CURDESC3_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc3_lsb_i <= (others => '0');
error_pointer_set3 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set3 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest3 = '1')then
curdesc3_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set3 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest3 = '1')then
-- curdesc3_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set3 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc3 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest3 = '1')then
curdesc3_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set3 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC3_LSB_INDEX) = '1' and halt_free = '1')then
curdesc3_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set3 <= '0';
end if;
end if;
end if;
end process CURDESC3_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC3_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc3_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC3_LSB_INDEX) = '1')then
taildesc3_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC3_LSB_REGISTER;
end generate GEN_DESC3_REG_FOR_SG;
GEN_DESC4_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 4 generate
CURDESC4_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc4_lsb_i <= (others => '0');
error_pointer_set4 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set4 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest4 = '1')then
curdesc4_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set4 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest4 = '1')then
-- curdesc4_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set4 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc4 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest4 = '1')then
curdesc4_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set4 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC4_LSB_INDEX) = '1' and halt_free = '1')then
curdesc4_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set4 <= '0';
end if;
end if;
end if;
end process CURDESC4_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC4_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc4_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC4_LSB_INDEX) = '1')then
taildesc4_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC4_LSB_REGISTER;
end generate GEN_DESC4_REG_FOR_SG;
GEN_DESC5_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 5 generate
CURDESC5_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc5_lsb_i <= (others => '0');
error_pointer_set5 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set5 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest5 = '1')then
curdesc5_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set5 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest5 = '1')then
-- curdesc5_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set5 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc5 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest5 = '1')then
curdesc5_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set5 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC5_LSB_INDEX) = '1' and halt_free = '1')then
curdesc5_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set5 <= '0';
end if;
end if;
end if;
end process CURDESC5_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC5_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc5_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC5_LSB_INDEX) = '1')then
taildesc5_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC5_LSB_REGISTER;
end generate GEN_DESC5_REG_FOR_SG;
GEN_DESC6_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 6 generate
CURDESC6_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc6_lsb_i <= (others => '0');
error_pointer_set6 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set6 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest6 = '1')then
curdesc6_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set6 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest6 = '1')then
-- curdesc6_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set6 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc6 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest6 = '1')then
curdesc6_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set6 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC6_LSB_INDEX) = '1' and halt_free = '1')then
curdesc6_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set6 <= '0';
end if;
end if;
end if;
end process CURDESC6_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC6_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc6_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC6_LSB_INDEX) = '1')then
taildesc6_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC6_LSB_REGISTER;
end generate GEN_DESC6_REG_FOR_SG;
GEN_DESC7_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 7 generate
CURDESC7_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc7_lsb_i <= (others => '0');
error_pointer_set7 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set7 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest7 = '1')then
curdesc7_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set7 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest7 = '1')then
-- curdesc7_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set7 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc7 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest7 = '1')then
curdesc7_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set7 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC7_LSB_INDEX) = '1' and halt_free = '1')then
curdesc7_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set7 <= '0';
end if;
end if;
end if;
end process CURDESC7_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC7_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc7_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC7_LSB_INDEX) = '1')then
taildesc7_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC7_LSB_REGISTER;
end generate GEN_DESC7_REG_FOR_SG;
GEN_DESC8_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 8 generate
CURDESC8_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc8_lsb_i <= (others => '0');
error_pointer_set8 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set8 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest8 = '1')then
curdesc8_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set8 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest8 = '1')then
-- curdesc8_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set8 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc8 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest8 = '1')then
curdesc8_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set8 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC8_LSB_INDEX) = '1' and halt_free = '1')then
curdesc8_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set8 <= '0';
end if;
end if;
end if;
end process CURDESC8_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC8_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc8_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC8_LSB_INDEX) = '1')then
taildesc8_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC8_LSB_REGISTER;
end generate GEN_DESC8_REG_FOR_SG;
GEN_DESC9_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 9 generate
CURDESC9_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc9_lsb_i <= (others => '0');
error_pointer_set9 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set9 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest9 = '1')then
curdesc9_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set9 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest9 = '1')then
-- curdesc9_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set9 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc9 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest9 = '1')then
curdesc9_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set9 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC9_LSB_INDEX) = '1' and halt_free = '1')then
curdesc9_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set9 <= '0';
end if;
end if;
end if;
end process CURDESC9_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC9_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc9_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC9_LSB_INDEX) = '1')then
taildesc9_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC9_LSB_REGISTER;
end generate GEN_DESC9_REG_FOR_SG;
GEN_DESC10_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 10 generate
CURDESC10_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc10_lsb_i <= (others => '0');
error_pointer_set10 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set10 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest10 = '1')then
curdesc10_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set10 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest10 = '1')then
-- curdesc10_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set10 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc10 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest10 = '1')then
curdesc10_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set10 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC10_LSB_INDEX) = '1' and halt_free = '1')then
curdesc10_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set10 <= '0';
end if;
end if;
end if;
end process CURDESC10_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC10_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc10_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC10_LSB_INDEX) = '1')then
taildesc10_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC10_LSB_REGISTER;
end generate GEN_DESC10_REG_FOR_SG;
GEN_DESC11_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 11 generate
CURDESC11_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc11_lsb_i <= (others => '0');
error_pointer_set11 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set11 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest11 = '1')then
curdesc11_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set11 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest11 = '1')then
-- curdesc11_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set11 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc11 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest11 = '1')then
curdesc11_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set11 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC11_LSB_INDEX) = '1' and halt_free = '1')then
curdesc11_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set11 <= '0';
end if;
end if;
end if;
end process CURDESC11_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC11_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc11_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC11_LSB_INDEX) = '1')then
taildesc11_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC11_LSB_REGISTER;
end generate GEN_DESC11_REG_FOR_SG;
GEN_DESC12_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 12 generate
CURDESC12_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc12_lsb_i <= (others => '0');
error_pointer_set12 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set12 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest12 = '1')then
curdesc12_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set12 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest12 = '1')then
-- curdesc12_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set12 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc12 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest12 = '1')then
curdesc12_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set12 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC12_LSB_INDEX) = '1' and halt_free = '1')then
curdesc12_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set12 <= '0';
end if;
end if;
end if;
end process CURDESC12_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC12_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc12_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC12_LSB_INDEX) = '1')then
taildesc12_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC12_LSB_REGISTER;
end generate GEN_DESC12_REG_FOR_SG;
GEN_DESC13_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 13 generate
CURDESC13_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc13_lsb_i <= (others => '0');
error_pointer_set13 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set13 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest13 = '1')then
curdesc13_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set13 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest13 = '1')then
-- curdesc13_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set13 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc13 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest13 = '1')then
curdesc13_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set13 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC13_LSB_INDEX) = '1' and halt_free = '1')then
curdesc13_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set13 <= '0';
end if;
end if;
end if;
end process CURDESC13_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC13_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc13_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC13_LSB_INDEX) = '1')then
taildesc13_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC13_LSB_REGISTER;
end generate GEN_DESC13_REG_FOR_SG;
GEN_DESC14_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 14 generate
CURDESC14_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc14_lsb_i <= (others => '0');
error_pointer_set14 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set14 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest14 = '1')then
curdesc14_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set14 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest14 = '1')then
-- curdesc14_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set14 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc14 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest14 = '1')then
curdesc14_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set14 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC14_LSB_INDEX) = '1' and halt_free = '1')then
curdesc14_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set14 <= '0';
end if;
end if;
end if;
end process CURDESC14_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC14_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc14_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC14_LSB_INDEX) = '1')then
taildesc14_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC14_LSB_REGISTER;
end generate GEN_DESC14_REG_FOR_SG;
GEN_DESC15_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 15 generate
CURDESC15_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc15_lsb_i <= (others => '0');
error_pointer_set15 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set15 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest15 = '1')then
curdesc15_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set15 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest15 = '1')then
-- curdesc15_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set15 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc15 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest15 = '1')then
curdesc15_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set15 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC15_LSB_INDEX) = '1' and halt_free = '1')then
curdesc15_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set15 <= '0';
end if;
end if;
end if;
end process CURDESC15_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC15_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc15_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC15_LSB_INDEX) = '1')then
taildesc15_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC15_LSB_REGISTER;
end generate GEN_DESC15_REG_FOR_SG;
---------------------------------------------------------------------------
-- Current Descriptor MSB Register
---------------------------------------------------------------------------
-- Scatter Gather Interface configured for 64-Bit SG Addresses
GEN_SG_ADDR_EQL64 :if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
CURDESC_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc_msb_i <= (others => '0');
elsif(error_pointer_set = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest0 = '1')then
curdesc_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
elsif(sg_updt_error = '1' and dest0 = '1')then
curdesc_msb_i <= updt_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest0 = '1')then
curdesc_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC_MSB_INDEX) = '1' and halt_free = '1')then
curdesc_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC_MSB_INDEX) = '1')then
taildesc_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC_MSB_REGISTER;
GEN_DESC1_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 1 generate
CURDESC1_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc1_msb_i <= (others => '0');
elsif(error_pointer_set1 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest1 = '1')then
curdesc1_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest1 = '1')then
-- curdesc1_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc1 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest1 = '1')then
curdesc1_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC1_MSB_INDEX) = '1' and halt_free = '1')then
curdesc1_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC1_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC1_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc1_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC1_MSB_INDEX) = '1')then
taildesc1_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC1_MSB_REGISTER;
end generate GEN_DESC1_MSB_FOR_SG;
GEN_DESC2_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 2 generate
CURDESC2_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc2_msb_i <= (others => '0');
elsif(error_pointer_set2 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest2 = '1')then
curdesc2_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest2 = '1')then
-- curdesc2_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc2 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest2 = '1')then
curdesc2_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC2_MSB_INDEX) = '1' and halt_free = '1')then
curdesc2_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC2_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC2_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc2_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC2_MSB_INDEX) = '1')then
taildesc2_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC2_MSB_REGISTER;
end generate GEN_DESC2_MSB_FOR_SG;
GEN_DESC3_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 3 generate
CURDESC3_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc3_msb_i <= (others => '0');
elsif(error_pointer_set3 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest3 = '1')then
curdesc3_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest3 = '1')then
-- curdesc3_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc3 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest3 = '1')then
curdesc3_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC3_MSB_INDEX) = '1' and halt_free = '1')then
curdesc3_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC3_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC3_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc3_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC3_MSB_INDEX) = '1')then
taildesc3_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC3_MSB_REGISTER;
end generate GEN_DESC3_MSB_FOR_SG;
GEN_DESC4_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 4 generate
CURDESC4_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc4_msb_i <= (others => '0');
elsif(error_pointer_set4 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest4 = '1')then
curdesc4_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest4 = '1')then
-- curdesc4_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc4 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest4 = '1')then
curdesc4_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC4_MSB_INDEX) = '1' and halt_free = '1')then
curdesc4_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC4_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC4_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc4_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC4_MSB_INDEX) = '1')then
taildesc4_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC4_MSB_REGISTER;
end generate GEN_DESC4_MSB_FOR_SG;
GEN_DESC5_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 5 generate
CURDESC5_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc5_msb_i <= (others => '0');
elsif(error_pointer_set5 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest5 = '1')then
curdesc5_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest5 = '1')then
-- curdesc5_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc5 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest5 = '1')then
curdesc5_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC5_MSB_INDEX) = '1' and halt_free = '1')then
curdesc5_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC5_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC5_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc5_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC5_MSB_INDEX) = '1')then
taildesc5_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC5_MSB_REGISTER;
end generate GEN_DESC5_MSB_FOR_SG;
GEN_DESC6_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 6 generate
CURDESC6_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc6_msb_i <= (others => '0');
elsif(error_pointer_set6 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest6 = '1')then
curdesc6_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest6 = '1')then
-- curdesc6_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc6 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest6 = '1')then
curdesc6_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC6_MSB_INDEX) = '1' and halt_free = '1')then
curdesc6_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC6_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC6_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc6_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC6_MSB_INDEX) = '1')then
taildesc6_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC6_MSB_REGISTER;
end generate GEN_DESC6_MSB_FOR_SG;
GEN_DESC7_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 7 generate
CURDESC7_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc7_msb_i <= (others => '0');
elsif(error_pointer_set7 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest7 = '1')then
curdesc7_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest7 = '1')then
-- curdesc7_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc7 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest7 = '1')then
curdesc7_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC7_MSB_INDEX) = '1' and halt_free = '1')then
curdesc7_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC7_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC7_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc7_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC7_MSB_INDEX) = '1')then
taildesc7_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC7_MSB_REGISTER;
end generate GEN_DESC7_MSB_FOR_SG;
GEN_DESC8_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 8 generate
CURDESC8_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc8_msb_i <= (others => '0');
elsif(error_pointer_set8 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest8 = '1')then
curdesc8_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest8 = '1')then
-- curdesc8_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc8 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest8 = '1')then
curdesc8_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC8_MSB_INDEX) = '1' and halt_free = '1')then
curdesc8_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC8_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC8_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc8_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC8_MSB_INDEX) = '1')then
taildesc8_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC8_MSB_REGISTER;
end generate GEN_DESC8_MSB_FOR_SG;
GEN_DESC9_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 9 generate
CURDESC9_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc9_msb_i <= (others => '0');
elsif(error_pointer_set9 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest9 = '1')then
curdesc9_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest9 = '1')then
-- curdesc9_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc9 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest9 = '1')then
curdesc9_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC9_MSB_INDEX) = '1' and halt_free = '1')then
curdesc9_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC9_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC9_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc9_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC9_MSB_INDEX) = '1')then
taildesc9_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC9_MSB_REGISTER;
end generate GEN_DESC9_MSB_FOR_SG;
GEN_DESC10_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 10 generate
CURDESC10_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc10_msb_i <= (others => '0');
elsif(error_pointer_set10 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest10 = '1')then
curdesc10_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest10 = '1')then
-- curdesc10_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc10 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest10 = '1')then
curdesc10_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC10_MSB_INDEX) = '1' and halt_free = '1')then
curdesc10_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC10_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC10_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc10_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC10_MSB_INDEX) = '1')then
taildesc10_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC10_MSB_REGISTER;
end generate GEN_DESC10_MSB_FOR_SG;
GEN_DESC11_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 11 generate
CURDESC11_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc11_msb_i <= (others => '0');
elsif(error_pointer_set11 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest11 = '1')then
curdesc11_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest11 = '1')then
-- curdesc11_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc11 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest11 = '1')then
curdesc11_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC11_MSB_INDEX) = '1' and halt_free = '1')then
curdesc11_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC11_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC11_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc11_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC11_MSB_INDEX) = '1')then
taildesc11_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC11_MSB_REGISTER;
end generate GEN_DESC11_MSB_FOR_SG;
GEN_DESC12_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 12 generate
CURDESC12_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc12_msb_i <= (others => '0');
elsif(error_pointer_set12 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest12 = '1')then
curdesc12_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest12 = '1')then
-- curdesc12_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc12 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest12 = '1')then
curdesc12_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC12_MSB_INDEX) = '1' and halt_free = '1')then
curdesc12_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC12_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC12_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc12_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC12_MSB_INDEX) = '1')then
taildesc12_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC12_MSB_REGISTER;
end generate GEN_DESC12_MSB_FOR_SG;
GEN_DESC13_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 13 generate
CURDESC13_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc13_msb_i <= (others => '0');
elsif(error_pointer_set13 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest13 = '1')then
curdesc13_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest13 = '1')then
-- curdesc13_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc13 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest13 = '1')then
curdesc13_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC13_MSB_INDEX) = '1' and halt_free = '1')then
curdesc13_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC13_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC13_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc13_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC13_MSB_INDEX) = '1')then
taildesc13_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC13_MSB_REGISTER;
end generate GEN_DESC13_MSB_FOR_SG;
GEN_DESC14_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 14 generate
CURDESC14_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc14_msb_i <= (others => '0');
elsif(error_pointer_set14 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest14 = '1')then
curdesc14_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest14 = '1')then
-- curdesc14_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc14 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest14 = '1')then
curdesc14_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC14_MSB_INDEX) = '1' and halt_free = '1')then
curdesc14_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC14_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC14_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc14_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC14_MSB_INDEX) = '1')then
taildesc14_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC14_MSB_REGISTER;
end generate GEN_DESC14_MSB_FOR_SG;
GEN_DESC15_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 15 generate
CURDESC15_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc15_msb_i <= (others => '0');
elsif(error_pointer_set15 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest15 = '1')then
curdesc15_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest15 = '1')then
-- curdesc15_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc15 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest15 = '1')then
curdesc15_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC15_MSB_INDEX) = '1' and halt_free = '1')then
curdesc15_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC15_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC15_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc15_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC15_MSB_INDEX) = '1')then
taildesc15_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC15_MSB_REGISTER;
end generate GEN_DESC15_MSB_FOR_SG;
end generate GEN_SG_ADDR_EQL64;
-- Scatter Gather Interface configured for 32-Bit SG Addresses
GEN_SG_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
curdesc_msb_i <= (others => '0');
taildesc_msb_i <= (others => '0');
-- Extending this to the extra registers
curdesc1_msb_i <= (others => '0');
taildesc1_msb_i <= (others => '0');
curdesc2_msb_i <= (others => '0');
taildesc2_msb_i <= (others => '0');
curdesc3_msb_i <= (others => '0');
taildesc3_msb_i <= (others => '0');
curdesc4_msb_i <= (others => '0');
taildesc4_msb_i <= (others => '0');
curdesc5_msb_i <= (others => '0');
taildesc5_msb_i <= (others => '0');
curdesc6_msb_i <= (others => '0');
taildesc6_msb_i <= (others => '0');
curdesc7_msb_i <= (others => '0');
taildesc7_msb_i <= (others => '0');
curdesc8_msb_i <= (others => '0');
taildesc8_msb_i <= (others => '0');
curdesc9_msb_i <= (others => '0');
taildesc9_msb_i <= (others => '0');
curdesc10_msb_i <= (others => '0');
taildesc10_msb_i <= (others => '0');
curdesc11_msb_i <= (others => '0');
taildesc11_msb_i <= (others => '0');
curdesc12_msb_i <= (others => '0');
taildesc12_msb_i <= (others => '0');
curdesc13_msb_i <= (others => '0');
taildesc13_msb_i <= (others => '0');
curdesc14_msb_i <= (others => '0');
taildesc14_msb_i <= (others => '0');
curdesc15_msb_i <= (others => '0');
taildesc15_msb_i <= (others => '0');
end generate GEN_SG_ADDR_EQL32;
-- Scatter Gather Interface configured for 32-Bit SG Addresses
GEN_TAILUPDATE_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-- Added dest so that BD can be dynamically updated
GENERATE_MULTI_CH : if C_ENABLE_MULTI_CHANNEL = 1 generate
tail_update_lsb <= (axi2ip_wrce(TAILDESC_LSB_INDEX) and dest0) or
(axi2ip_wrce(TAILDESC1_LSB_INDEX) and dest1) or
(axi2ip_wrce(TAILDESC2_LSB_INDEX) and dest2) or
(axi2ip_wrce(TAILDESC3_LSB_INDEX) and dest3) or
(axi2ip_wrce(TAILDESC4_LSB_INDEX) and dest4) or
(axi2ip_wrce(TAILDESC5_LSB_INDEX) and dest5) or
(axi2ip_wrce(TAILDESC6_LSB_INDEX) and dest6) or
(axi2ip_wrce(TAILDESC7_LSB_INDEX) and dest7) or
(axi2ip_wrce(TAILDESC8_LSB_INDEX) and dest8) or
(axi2ip_wrce(TAILDESC9_LSB_INDEX) and dest9) or
(axi2ip_wrce(TAILDESC10_LSB_INDEX) and dest10) or
(axi2ip_wrce(TAILDESC11_LSB_INDEX) and dest11) or
(axi2ip_wrce(TAILDESC12_LSB_INDEX) and dest12) or
(axi2ip_wrce(TAILDESC13_LSB_INDEX) and dest13) or
(axi2ip_wrce(TAILDESC14_LSB_INDEX) and dest14) or
(axi2ip_wrce(TAILDESC15_LSB_INDEX) and dest15);
end generate GENERATE_MULTI_CH;
GENERATE_NO_MULTI_CH : if C_ENABLE_MULTI_CHANNEL = 0 generate
tail_update_lsb <= (axi2ip_wrce(TAILDESC_LSB_INDEX) and dest0);
end generate GENERATE_NO_MULTI_CH;
TAILPNTR_UPDT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then
tailpntr_updated_d1 <= '0';
elsif (tail_update_lsb = '1' and tdest_in(5) = '0')then
tailpntr_updated_d1 <= '1';
else
tailpntr_updated_d1 <= '0';
end if;
end if;
end process TAILPNTR_UPDT_PROCESS;
TAILPNTR_UPDT_PROCESS_DEL : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
tailpntr_updated_d2 <= '0';
else
tailpntr_updated_d2 <= tailpntr_updated_d1;
end if;
end if;
end process TAILPNTR_UPDT_PROCESS_DEL;
tailpntr_updated <= tailpntr_updated_d1 and (not tailpntr_updated_d2);
end generate GEN_TAILUPDATE_EQL32;
-- Scatter Gather Interface configured for 64-Bit SG Addresses
GEN_TAILUPDATE_EQL64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
-- Added dest so that BD can be dynamically updated
GENERATE_NO_MULTI_CH1 : if C_ENABLE_MULTI_CHANNEL = 1 generate
tail_update_msb <= (axi2ip_wrce(TAILDESC_MSB_INDEX) and dest0) or
(axi2ip_wrce(TAILDESC1_MSB_INDEX) and dest1) or
(axi2ip_wrce(TAILDESC2_MSB_INDEX) and dest2) or
(axi2ip_wrce(TAILDESC3_MSB_INDEX) and dest3) or
(axi2ip_wrce(TAILDESC4_MSB_INDEX) and dest4) or
(axi2ip_wrce(TAILDESC5_MSB_INDEX) and dest5) or
(axi2ip_wrce(TAILDESC6_MSB_INDEX) and dest6) or
(axi2ip_wrce(TAILDESC7_MSB_INDEX) and dest7) or
(axi2ip_wrce(TAILDESC8_MSB_INDEX) and dest8) or
(axi2ip_wrce(TAILDESC9_MSB_INDEX) and dest9) or
(axi2ip_wrce(TAILDESC10_MSB_INDEX) and dest10) or
(axi2ip_wrce(TAILDESC11_MSB_INDEX) and dest11) or
(axi2ip_wrce(TAILDESC12_MSB_INDEX) and dest12) or
(axi2ip_wrce(TAILDESC13_MSB_INDEX) and dest13) or
(axi2ip_wrce(TAILDESC14_MSB_INDEX) and dest14) or
(axi2ip_wrce(TAILDESC15_MSB_INDEX) and dest15);
end generate GENERATE_NO_MULTI_CH1;
GENERATE_NO_MULTI_CH2 : if C_ENABLE_MULTI_CHANNEL = 0 generate
tail_update_msb <= (axi2ip_wrce(TAILDESC_MSB_INDEX) and dest0);
end generate GENERATE_NO_MULTI_CH2;
TAILPNTR_UPDT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then
tailpntr_updated_d1 <= '0';
elsif (tail_update_msb = '1' and tdest_in(5) = '0')then
tailpntr_updated_d1 <= '1';
else
tailpntr_updated_d1 <= '0';
end if;
end if;
end process TAILPNTR_UPDT_PROCESS;
TAILPNTR_UPDT_PROCESS_DEL : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
tailpntr_updated_d2 <= '0';
else
tailpntr_updated_d2 <= tailpntr_updated_d1;
end if;
end if;
end process TAILPNTR_UPDT_PROCESS_DEL;
tailpntr_updated <= tailpntr_updated_d1 and (not tailpntr_updated_d2);
end generate GEN_TAILUPDATE_EQL64;
end generate GEN_DESC_REG_FOR_SG;
-- Generate Buffer Address and Length Register for Simple DMA Mode
GEN_REG_FOR_SMPL : if C_INCLUDE_SG = 0 generate
begin
-- Signals not used for simple dma mode, only for sg mode
curdesc_lsb_i <= (others => '0');
curdesc_msb_i <= (others => '0');
taildesc_lsb_i <= (others => '0');
taildesc_msb_i <= (others => '0');
-- Extending this to new registers
curdesc1_msb_i <= (others => '0');
taildesc1_msb_i <= (others => '0');
curdesc2_msb_i <= (others => '0');
taildesc2_msb_i <= (others => '0');
curdesc3_msb_i <= (others => '0');
taildesc3_msb_i <= (others => '0');
curdesc4_msb_i <= (others => '0');
taildesc4_msb_i <= (others => '0');
curdesc5_msb_i <= (others => '0');
taildesc5_msb_i <= (others => '0');
curdesc6_msb_i <= (others => '0');
taildesc6_msb_i <= (others => '0');
curdesc7_msb_i <= (others => '0');
taildesc7_msb_i <= (others => '0');
curdesc8_msb_i <= (others => '0');
taildesc8_msb_i <= (others => '0');
curdesc9_msb_i <= (others => '0');
taildesc9_msb_i <= (others => '0');
curdesc10_msb_i <= (others => '0');
taildesc10_msb_i <= (others => '0');
curdesc11_msb_i <= (others => '0');
taildesc11_msb_i <= (others => '0');
curdesc12_msb_i <= (others => '0');
taildesc12_msb_i <= (others => '0');
curdesc13_msb_i <= (others => '0');
taildesc13_msb_i <= (others => '0');
curdesc14_msb_i <= (others => '0');
taildesc14_msb_i <= (others => '0');
curdesc15_msb_i <= (others => '0');
taildesc15_msb_i <= (others => '0');
curdesc1_lsb_i <= (others => '0');
taildesc1_lsb_i <= (others => '0');
curdesc2_lsb_i <= (others => '0');
taildesc2_lsb_i <= (others => '0');
curdesc3_lsb_i <= (others => '0');
taildesc3_lsb_i <= (others => '0');
curdesc4_lsb_i <= (others => '0');
taildesc4_lsb_i <= (others => '0');
curdesc5_lsb_i <= (others => '0');
taildesc5_lsb_i <= (others => '0');
curdesc6_lsb_i <= (others => '0');
taildesc6_lsb_i <= (others => '0');
curdesc7_lsb_i <= (others => '0');
taildesc7_lsb_i <= (others => '0');
curdesc8_lsb_i <= (others => '0');
taildesc8_lsb_i <= (others => '0');
curdesc9_lsb_i <= (others => '0');
taildesc9_lsb_i <= (others => '0');
curdesc10_lsb_i <= (others => '0');
taildesc10_lsb_i <= (others => '0');
curdesc11_lsb_i <= (others => '0');
taildesc11_lsb_i <= (others => '0');
curdesc12_lsb_i <= (others => '0');
taildesc12_lsb_i <= (others => '0');
curdesc13_lsb_i <= (others => '0');
taildesc13_lsb_i <= (others => '0');
curdesc14_lsb_i <= (others => '0');
taildesc14_lsb_i <= (others => '0');
curdesc15_lsb_i <= (others => '0');
taildesc15_lsb_i <= (others => '0');
tailpntr_updated <= '0';
error_pointer_set <= '0';
-- Buffer Address register. Used for Source Address (SA) if MM2S
-- and used for Destination Address (DA) if S2MM
BUFFER_ADDR_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_address_i <= (others => '0');
elsif(axi2ip_wrce(BUFF_ADDRESS_INDEX) = '1')then
buffer_address_i <= axi2ip_wrdata;
end if;
end if;
end process BUFFER_ADDR_REGISTER;
GEN_BUF_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
BUFFER_ADDR_REGISTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_address_64_i <= (others => '0');
elsif(axi2ip_wrce(BUFF_ADDRESS_MSB_INDEX) = '1')then
buffer_address_64_i <= axi2ip_wrdata;
end if;
end if;
end process BUFFER_ADDR_REGISTER1;
end generate GEN_BUF_ADDR_EQL64;
-- Buffer Length register. Used for number of bytes to transfer if MM2S
-- and used for size of receive buffer is S2MM
BUFFER_LNGTH_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_length_i <= (others => '0');
-- Update with actual bytes received (Only for S2MM channel)
elsif(bytes_received_wren = '1' and C_MICRO_DMA = 0)then
buffer_length_i <= bytes_received;
elsif(axi2ip_wrce(BUFF_LENGTH_INDEX) = '1')then
buffer_length_i <= axi2ip_wrdata(C_SG_LENGTH_WIDTH-1 downto 0);
end if;
end if;
end process BUFFER_LNGTH_REGISTER;
-- Buffer Length Write Enable control. Assertion of wren will
-- begin a transfer if channel is Idle.
BUFFER_LNGTH_WRITE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_length_wren <= '0';
-- Non-zero length value written
elsif(axi2ip_wrce(BUFF_LENGTH_INDEX) = '1'
and axi2ip_wrdata(C_SG_LENGTH_WIDTH-1 downto 0) /= ZERO_VALUE(C_SG_LENGTH_WIDTH-1 downto 0))then
buffer_length_wren <= '1';
else
buffer_length_wren <= '0';
end if;
end if;
end process BUFFER_LNGTH_WRITE;
end generate GEN_REG_FOR_SMPL;
end implementation;
| gpl-3.0 | 1ecfd320c2e8c6a3b62f36f5da643e93 | 0.445316 | 4.182627 | false | false | false | false |
tgingold/ghdl | testsuite/synth/mem2d01/tb_memmux04.vhdl | 1 | 1,950 | entity tb_memmux04 is
end tb_memmux04;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_memmux04 is
signal wen : std_logic;
signal waddr : std_logic_vector (3 downto 0);
signal wdat : std_logic_vector (31 downto 0);
signal raddr : std_logic_vector (3 downto 0);
signal rsel : std_logic_vector (1 downto 0);
signal rdat : std_logic_vector (7 downto 0);
signal clk : std_logic;
begin
dut : entity work.memmux04
port map (
wen => wen,
waddr => waddr,
wdat => wdat,
raddr => raddr,
rsel => rsel,
rdat => rdat,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
variable v : std_logic_vector(3 downto 0);
variable s : std_logic_vector(1 downto 0);
begin
wen <= '1';
waddr <= x"0";
wdat <= x"0123_5670";
pulse;
wen <= '1';
waddr <= x"1";
wdat <= x"1234_6781";
raddr <= x"0";
rsel <= "00";
pulse;
assert rdat = x"70" severity failure;
-- Fill the memory.
for i in 0 to 15 loop
wen <= '1';
v := std_logic_vector (to_unsigned (i, 4));
waddr <= v;
wdat (3 downto 0) <= v;
wdat (7 downto 4) <= x"0";
wdat (11 downto 8) <= v;
wdat (15 downto 12) <= x"1";
wdat (19 downto 16) <= v;
wdat (23 downto 20) <= x"2";
wdat (27 downto 24) <= v;
wdat (31 downto 28) <= x"3";
pulse;
end loop;
-- Check the memory.
wen <= '0';
for i in 0 to 15 loop
v := std_logic_vector (to_unsigned (i, 4));
raddr <= v;
for j in 0 to 3 loop
s := std_logic_vector (to_unsigned (j, 2));
rsel <= s;
pulse;
assert rdat (3 downto 0) = v severity failure;
assert rdat (5 downto 4) = s severity failure;
end loop;
end loop;
wait;
end process;
end behav;
| gpl-2.0 | 6810075f6c458349335e48ed6281e1ba | 0.537436 | 3.305085 | false | false | false | false |
tgingold/ghdl | testsuite/synth/dispin01/tb_rec05.vhdl | 1 | 687 | entity tb_rec05 is
end tb_rec05;
library ieee;
use ieee.std_logic_1164.all;
use work.rec05_pkg.all;
architecture behav of tb_rec05 is
signal inp : myrec;
signal r : std_logic;
begin
dut: entity work.rec05
port map (inp => inp, o => r);
process
begin
inp.a <= "0000";
inp.b <= '1';
wait for 1 ns;
assert r = '0' severity failure;
inp.a <= "0010";
inp.b <= '1';
wait for 1 ns;
assert r = '1' severity failure;
inp.a <= "1101";
inp.b <= '0';
wait for 1 ns;
assert r = '1' severity failure;
inp.a <= "1101";
inp.b <= '1';
wait for 1 ns;
assert r = '0' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 30e6376704670af8dc4f1d9ce624dc9f | 0.56623 | 2.974026 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1704.vhd | 4 | 2,663 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1704.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p07n01i01704ent IS
END c09s02b00x00p07n01i01704ent;
ARCHITECTURE c09s02b00x00p07n01i01704arch OF c09s02b00x00p07n01i01704ent IS
signal S : Bit;
BEGIN
TESTING: PROCESS( S )
-- local variables.
variable INITED : BOOLEAN := FALSE;
variable CNT : INTEGER := 0;
variable NEWTIME: TIME;
variable k : integer := 1;
BEGIN
-- Take care of the first run.
if (not( INITED )) then
INITED := TRUE;
CNT := 0;
S <= (not S) after 1 ns;
NEWTIME := NOW + 1 ns;
-- Otherwise, take care of all subsequent runs.
-- NOTE: Take care of the last time we will get awakened.
elsif (NOW /= TIME'HIGH) then
-- Verify that we woke up when S was updated.
if NOT(( S'EVENT ) and ( NEWTIME = NOW )) then
k := 0;
end if;
-- See if we should continue. If so, do it.
CNT := CNT + 1;
if (CNT <= 50) then
S <= (not S) after 1 ns;
NEWTIME := NOW + 1 ns;
end if;
end if;
if (CNT = 50) then
assert NOT( k=1 )
report "***PASSED TEST: c09s02b00x00p07n01i01704"
severity NOTE;
assert ( k=1 )
report "***FAILED TEST: c09s02b00x00p07n01i01704 - The process statement is assumed to contain an implicit wait statement if a sensitivity list appears following the reserved word process."
severity ERROR;
end if;
END PROCESS TESTING;
END c09s02b00x00p07n01i01704arch;
| gpl-2.0 | a596cdfd702f695c03d562226cac2ccf | 0.617724 | 3.76662 | false | true | false | false |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/ghrd_10as066n2_emif_hps_inst.vhd | 1 | 4,198 | component ghrd_10as066n2_emif_hps is
port (
global_reset_n : in std_logic := 'X'; -- reset_n
hps_to_emif : in std_logic_vector(4095 downto 0) := (others => 'X'); -- hps_to_emif
emif_to_hps : out std_logic_vector(4095 downto 0); -- emif_to_hps
hps_to_emif_gp : in std_logic_vector(1 downto 0) := (others => 'X'); -- gp_to_emif
emif_to_hps_gp : out std_logic_vector(0 downto 0); -- emif_to_gp
mem_ck : out std_logic_vector(0 downto 0); -- mem_ck
mem_ck_n : out std_logic_vector(0 downto 0); -- mem_ck_n
mem_a : out std_logic_vector(16 downto 0); -- mem_a
mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
mem_bg : out std_logic_vector(0 downto 0); -- mem_bg
mem_cke : out std_logic_vector(0 downto 0); -- mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n
mem_odt : out std_logic_vector(0 downto 0); -- mem_odt
mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
mem_par : out std_logic_vector(0 downto 0); -- mem_par
mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_alert_n
mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
mem_dbi_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dbi_n
oct_rzqin : in std_logic := 'X'; -- oct_rzqin
pll_ref_clk : in std_logic := 'X' -- clk
);
end component ghrd_10as066n2_emif_hps;
u0 : component ghrd_10as066n2_emif_hps
port map (
global_reset_n => CONNECTED_TO_global_reset_n, -- global_reset_reset_sink.reset_n
hps_to_emif => CONNECTED_TO_hps_to_emif, -- hps_emif_conduit_end.hps_to_emif
emif_to_hps => CONNECTED_TO_emif_to_hps, -- .emif_to_hps
hps_to_emif_gp => CONNECTED_TO_hps_to_emif_gp, -- .gp_to_emif
emif_to_hps_gp => CONNECTED_TO_emif_to_hps_gp, -- .emif_to_gp
mem_ck => CONNECTED_TO_mem_ck, -- mem_conduit_end.mem_ck
mem_ck_n => CONNECTED_TO_mem_ck_n, -- .mem_ck_n
mem_a => CONNECTED_TO_mem_a, -- .mem_a
mem_act_n => CONNECTED_TO_mem_act_n, -- .mem_act_n
mem_ba => CONNECTED_TO_mem_ba, -- .mem_ba
mem_bg => CONNECTED_TO_mem_bg, -- .mem_bg
mem_cke => CONNECTED_TO_mem_cke, -- .mem_cke
mem_cs_n => CONNECTED_TO_mem_cs_n, -- .mem_cs_n
mem_odt => CONNECTED_TO_mem_odt, -- .mem_odt
mem_reset_n => CONNECTED_TO_mem_reset_n, -- .mem_reset_n
mem_par => CONNECTED_TO_mem_par, -- .mem_par
mem_alert_n => CONNECTED_TO_mem_alert_n, -- .mem_alert_n
mem_dqs => CONNECTED_TO_mem_dqs, -- .mem_dqs
mem_dqs_n => CONNECTED_TO_mem_dqs_n, -- .mem_dqs_n
mem_dq => CONNECTED_TO_mem_dq, -- .mem_dq
mem_dbi_n => CONNECTED_TO_mem_dbi_n, -- .mem_dbi_n
oct_rzqin => CONNECTED_TO_oct_rzqin, -- oct_conduit_end.oct_rzqin
pll_ref_clk => CONNECTED_TO_pll_ref_clk -- pll_ref_clk_clock_sink.clk
);
| mit | ecf3a1bf526894d5eb104fa8f7e75d3f | 0.437828 | 3.197258 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug0105/econcat1.vhdl | 1 | 433 | entity econcat1 is
end econcat1;
architecture behav of econcat1 is
constant c1 : string (1 to 5) := "hello";
constant c2 : string (6 downto 1) := " world";
constant r : string := c1 & c2;
begin
process
begin
case True is
when c1 & c2 = "hello world" => null;
when false => null;
end case;
assert r'left = 1 severity failure;
assert r'right = 11 severity failure;
wait;
end process;
end;
| gpl-2.0 | 4a0e010ae2c827c52287edc70f2d3306 | 0.625866 | 3.464 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue713/dma_controller_tb.vhd | 1 | 1,037 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sim_types_pkg.all;
entity dma_controller_tb is
generic (
runner_cfg : string := ""
);
end entity;
architecture bench of dma_controller_tb is
constant num_desc : positive := 4;
subtype num_desc_range is natural range 0 to num_desc-1;
constant MEM_BYTES : positive := 512;
constant MEM_DWORDS : positive := MEM_BYTES/4;
function byte_range (desc : descriptor_t) return bit_vector is
-- Works if 0 to 1
-- variable v : bit_vector(0 to 1);
variable v : bit_vector(desc.address to desc.address + desc.length);
begin
return v;
end function;
begin
mm2s_buffer_destroy: process
variable desc : descriptor_t := (8, 8);
begin
wait for 50 ns;
for i in byte_range(desc)'range loop
call_report(i);
assert i >= 8 and i <= 16 severity failure;
-- Works for below
--for i in 0 to 1 loop
-- set_permissions(mm2s_memory, i, no_access);
end loop;
wait;
end process;
end architecture;
| gpl-2.0 | 8451e89cf4c376b6bdd2b3b327f19795 | 0.659595 | 3.142424 | false | false | false | false |
nickg/nvc | test/regress/proc3.vhd | 2 | 1,531 | package pack is
function func(x : in integer) return integer;
end package;
package body pack is
procedure p5(x : in integer; y : out integer) is
variable k : integer := x + 1;
begin
y := k;
end procedure;
function func(x : in integer) return integer is
variable y : integer;
begin
p5(x, y);
return y;
end function;
end package body;
-------------------------------------------------------------------------------
entity proc3 is
end entity;
use work.pack.all;
architecture test of proc3 is
procedure p1 is
begin
wait for 10 ns;
wait for 5 ns;
end procedure;
procedure p2 is
begin
p1;
p1;
end procedure;
procedure p3(t : in time) is
begin
loop
wait for t;
if now >= 100 ns then
return;
end if;
end loop;
end procedure;
procedure p4(x : in integer; y : out integer) is
variable k : integer;
begin
k := x;
for i in 1 to 5 loop
k := k + 1;
wait for 1 ns;
end loop;
y := k;
end procedure;
begin
process is
variable x : integer;
begin
p1;
assert now = 15 ns;
p2;
assert now = 45 ns;
p3(5 ns);
assert now = 100 ns;
p4(5, x);
assert x = 10;
assert now = 105 ns;
x := func(x);
assert x = 11;
wait;
end process;
end architecture;
| gpl-3.0 | 3557803c4577f4b220551334ada60ff5 | 0.474853 | 4.050265 | false | false | false | false |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeDE1SoC/Video_In_Subsystem/Computer_System_inst.vhd | 1 | 24,866 | component Computer_System is
port (
expansion_jp1_export : inout std_logic_vector(31 downto 0) := (others => 'X'); -- export
expansion_jp2_export : inout std_logic_vector(31 downto 0) := (others => 'X'); -- export
hps_io_hps_io_emac1_inst_TX_CLK : out std_logic; -- hps_io_emac1_inst_TX_CLK
hps_io_hps_io_emac1_inst_TXD0 : out std_logic; -- hps_io_emac1_inst_TXD0
hps_io_hps_io_emac1_inst_TXD1 : out std_logic; -- hps_io_emac1_inst_TXD1
hps_io_hps_io_emac1_inst_TXD2 : out std_logic; -- hps_io_emac1_inst_TXD2
hps_io_hps_io_emac1_inst_TXD3 : out std_logic; -- hps_io_emac1_inst_TXD3
hps_io_hps_io_emac1_inst_RXD0 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD0
hps_io_hps_io_emac1_inst_MDIO : inout std_logic := 'X'; -- hps_io_emac1_inst_MDIO
hps_io_hps_io_emac1_inst_MDC : out std_logic; -- hps_io_emac1_inst_MDC
hps_io_hps_io_emac1_inst_RX_CTL : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CTL
hps_io_hps_io_emac1_inst_TX_CTL : out std_logic; -- hps_io_emac1_inst_TX_CTL
hps_io_hps_io_emac1_inst_RX_CLK : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CLK
hps_io_hps_io_emac1_inst_RXD1 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD1
hps_io_hps_io_emac1_inst_RXD2 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD2
hps_io_hps_io_emac1_inst_RXD3 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD3
hps_io_hps_io_qspi_inst_IO0 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO0
hps_io_hps_io_qspi_inst_IO1 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO1
hps_io_hps_io_qspi_inst_IO2 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO2
hps_io_hps_io_qspi_inst_IO3 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO3
hps_io_hps_io_qspi_inst_SS0 : out std_logic; -- hps_io_qspi_inst_SS0
hps_io_hps_io_qspi_inst_CLK : out std_logic; -- hps_io_qspi_inst_CLK
hps_io_hps_io_sdio_inst_CMD : inout std_logic := 'X'; -- hps_io_sdio_inst_CMD
hps_io_hps_io_sdio_inst_D0 : inout std_logic := 'X'; -- hps_io_sdio_inst_D0
hps_io_hps_io_sdio_inst_D1 : inout std_logic := 'X'; -- hps_io_sdio_inst_D1
hps_io_hps_io_sdio_inst_CLK : out std_logic; -- hps_io_sdio_inst_CLK
hps_io_hps_io_sdio_inst_D2 : inout std_logic := 'X'; -- hps_io_sdio_inst_D2
hps_io_hps_io_sdio_inst_D3 : inout std_logic := 'X'; -- hps_io_sdio_inst_D3
hps_io_hps_io_usb1_inst_D0 : inout std_logic := 'X'; -- hps_io_usb1_inst_D0
hps_io_hps_io_usb1_inst_D1 : inout std_logic := 'X'; -- hps_io_usb1_inst_D1
hps_io_hps_io_usb1_inst_D2 : inout std_logic := 'X'; -- hps_io_usb1_inst_D2
hps_io_hps_io_usb1_inst_D3 : inout std_logic := 'X'; -- hps_io_usb1_inst_D3
hps_io_hps_io_usb1_inst_D4 : inout std_logic := 'X'; -- hps_io_usb1_inst_D4
hps_io_hps_io_usb1_inst_D5 : inout std_logic := 'X'; -- hps_io_usb1_inst_D5
hps_io_hps_io_usb1_inst_D6 : inout std_logic := 'X'; -- hps_io_usb1_inst_D6
hps_io_hps_io_usb1_inst_D7 : inout std_logic := 'X'; -- hps_io_usb1_inst_D7
hps_io_hps_io_usb1_inst_CLK : in std_logic := 'X'; -- hps_io_usb1_inst_CLK
hps_io_hps_io_usb1_inst_STP : out std_logic; -- hps_io_usb1_inst_STP
hps_io_hps_io_usb1_inst_DIR : in std_logic := 'X'; -- hps_io_usb1_inst_DIR
hps_io_hps_io_usb1_inst_NXT : in std_logic := 'X'; -- hps_io_usb1_inst_NXT
hps_io_hps_io_spim1_inst_CLK : out std_logic; -- hps_io_spim1_inst_CLK
hps_io_hps_io_spim1_inst_MOSI : out std_logic; -- hps_io_spim1_inst_MOSI
hps_io_hps_io_spim1_inst_MISO : in std_logic := 'X'; -- hps_io_spim1_inst_MISO
hps_io_hps_io_spim1_inst_SS0 : out std_logic; -- hps_io_spim1_inst_SS0
hps_io_hps_io_uart0_inst_RX : in std_logic := 'X'; -- hps_io_uart0_inst_RX
hps_io_hps_io_uart0_inst_TX : out std_logic; -- hps_io_uart0_inst_TX
hps_io_hps_io_i2c0_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c0_inst_SDA
hps_io_hps_io_i2c0_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c0_inst_SCL
hps_io_hps_io_i2c1_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c1_inst_SDA
hps_io_hps_io_i2c1_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c1_inst_SCL
hps_io_hps_io_gpio_inst_GPIO09 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO09
hps_io_hps_io_gpio_inst_GPIO35 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO35
hps_io_hps_io_gpio_inst_GPIO40 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO40
hps_io_hps_io_gpio_inst_GPIO41 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO41
hps_io_hps_io_gpio_inst_GPIO48 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO48
hps_io_hps_io_gpio_inst_GPIO53 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO53
hps_io_hps_io_gpio_inst_GPIO54 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO54
hps_io_hps_io_gpio_inst_GPIO61 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO61
leds_export : out std_logic_vector(9 downto 0); -- export
memory_mem_a : out std_logic_vector(14 downto 0); -- mem_a
memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
memory_mem_ck : out std_logic; -- mem_ck
memory_mem_ck_n : out std_logic; -- mem_ck_n
memory_mem_cke : out std_logic; -- mem_cke
memory_mem_cs_n : out std_logic; -- mem_cs_n
memory_mem_ras_n : out std_logic; -- mem_ras_n
memory_mem_cas_n : out std_logic; -- mem_cas_n
memory_mem_we_n : out std_logic; -- mem_we_n
memory_mem_reset_n : out std_logic; -- mem_reset_n
memory_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
memory_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
memory_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
memory_mem_odt : out std_logic; -- mem_odt
memory_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
pushbuttons_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
sdram_addr : out std_logic_vector(12 downto 0); -- addr
sdram_ba : out std_logic_vector(1 downto 0); -- ba
sdram_cas_n : out std_logic; -- cas_n
sdram_cke : out std_logic; -- cke
sdram_cs_n : out std_logic; -- cs_n
sdram_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
sdram_dqm : out std_logic_vector(1 downto 0); -- dqm
sdram_ras_n : out std_logic; -- ras_n
sdram_we_n : out std_logic; -- we_n
sdram_clk_clk : out std_logic; -- clk
slider_switches_export : in std_logic_vector(9 downto 0) := (others => 'X'); -- export
system_pll_ref_clk_clk : in std_logic := 'X'; -- clk
system_pll_ref_reset_reset : in std_logic := 'X'; -- reset
vga_CLK : out std_logic; -- CLK
vga_HS : out std_logic; -- HS
vga_VS : out std_logic; -- VS
vga_BLANK : out std_logic; -- BLANK
vga_SYNC : out std_logic; -- SYNC
vga_R : out std_logic_vector(7 downto 0); -- R
vga_G : out std_logic_vector(7 downto 0); -- G
vga_B : out std_logic_vector(7 downto 0); -- B
vga_pll_ref_clk_clk : in std_logic := 'X'; -- clk
vga_pll_ref_reset_reset : in std_logic := 'X'; -- reset
video_in_TD_CLK27 : in std_logic := 'X'; -- TD_CLK27
video_in_TD_DATA : in std_logic_vector(7 downto 0) := (others => 'X'); -- TD_DATA
video_in_TD_HS : in std_logic := 'X'; -- TD_HS
video_in_TD_VS : in std_logic := 'X'; -- TD_VS
video_in_clk27_reset : in std_logic := 'X'; -- clk27_reset
video_in_TD_RESET : out std_logic; -- TD_RESET
video_in_overflow_flag : out std_logic -- overflow_flag
);
end component Computer_System;
u0 : component Computer_System
port map (
expansion_jp1_export => CONNECTED_TO_expansion_jp1_export, -- expansion_jp1.export
expansion_jp2_export => CONNECTED_TO_expansion_jp2_export, -- expansion_jp2.export
hps_io_hps_io_emac1_inst_TX_CLK => CONNECTED_TO_hps_io_hps_io_emac1_inst_TX_CLK, -- hps_io.hps_io_emac1_inst_TX_CLK
hps_io_hps_io_emac1_inst_TXD0 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD0, -- .hps_io_emac1_inst_TXD0
hps_io_hps_io_emac1_inst_TXD1 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD1, -- .hps_io_emac1_inst_TXD1
hps_io_hps_io_emac1_inst_TXD2 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD2, -- .hps_io_emac1_inst_TXD2
hps_io_hps_io_emac1_inst_TXD3 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD3, -- .hps_io_emac1_inst_TXD3
hps_io_hps_io_emac1_inst_RXD0 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD0, -- .hps_io_emac1_inst_RXD0
hps_io_hps_io_emac1_inst_MDIO => CONNECTED_TO_hps_io_hps_io_emac1_inst_MDIO, -- .hps_io_emac1_inst_MDIO
hps_io_hps_io_emac1_inst_MDC => CONNECTED_TO_hps_io_hps_io_emac1_inst_MDC, -- .hps_io_emac1_inst_MDC
hps_io_hps_io_emac1_inst_RX_CTL => CONNECTED_TO_hps_io_hps_io_emac1_inst_RX_CTL, -- .hps_io_emac1_inst_RX_CTL
hps_io_hps_io_emac1_inst_TX_CTL => CONNECTED_TO_hps_io_hps_io_emac1_inst_TX_CTL, -- .hps_io_emac1_inst_TX_CTL
hps_io_hps_io_emac1_inst_RX_CLK => CONNECTED_TO_hps_io_hps_io_emac1_inst_RX_CLK, -- .hps_io_emac1_inst_RX_CLK
hps_io_hps_io_emac1_inst_RXD1 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD1, -- .hps_io_emac1_inst_RXD1
hps_io_hps_io_emac1_inst_RXD2 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD2, -- .hps_io_emac1_inst_RXD2
hps_io_hps_io_emac1_inst_RXD3 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD3, -- .hps_io_emac1_inst_RXD3
hps_io_hps_io_qspi_inst_IO0 => CONNECTED_TO_hps_io_hps_io_qspi_inst_IO0, -- .hps_io_qspi_inst_IO0
hps_io_hps_io_qspi_inst_IO1 => CONNECTED_TO_hps_io_hps_io_qspi_inst_IO1, -- .hps_io_qspi_inst_IO1
hps_io_hps_io_qspi_inst_IO2 => CONNECTED_TO_hps_io_hps_io_qspi_inst_IO2, -- .hps_io_qspi_inst_IO2
hps_io_hps_io_qspi_inst_IO3 => CONNECTED_TO_hps_io_hps_io_qspi_inst_IO3, -- .hps_io_qspi_inst_IO3
hps_io_hps_io_qspi_inst_SS0 => CONNECTED_TO_hps_io_hps_io_qspi_inst_SS0, -- .hps_io_qspi_inst_SS0
hps_io_hps_io_qspi_inst_CLK => CONNECTED_TO_hps_io_hps_io_qspi_inst_CLK, -- .hps_io_qspi_inst_CLK
hps_io_hps_io_sdio_inst_CMD => CONNECTED_TO_hps_io_hps_io_sdio_inst_CMD, -- .hps_io_sdio_inst_CMD
hps_io_hps_io_sdio_inst_D0 => CONNECTED_TO_hps_io_hps_io_sdio_inst_D0, -- .hps_io_sdio_inst_D0
hps_io_hps_io_sdio_inst_D1 => CONNECTED_TO_hps_io_hps_io_sdio_inst_D1, -- .hps_io_sdio_inst_D1
hps_io_hps_io_sdio_inst_CLK => CONNECTED_TO_hps_io_hps_io_sdio_inst_CLK, -- .hps_io_sdio_inst_CLK
hps_io_hps_io_sdio_inst_D2 => CONNECTED_TO_hps_io_hps_io_sdio_inst_D2, -- .hps_io_sdio_inst_D2
hps_io_hps_io_sdio_inst_D3 => CONNECTED_TO_hps_io_hps_io_sdio_inst_D3, -- .hps_io_sdio_inst_D3
hps_io_hps_io_usb1_inst_D0 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D0, -- .hps_io_usb1_inst_D0
hps_io_hps_io_usb1_inst_D1 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D1, -- .hps_io_usb1_inst_D1
hps_io_hps_io_usb1_inst_D2 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D2, -- .hps_io_usb1_inst_D2
hps_io_hps_io_usb1_inst_D3 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D3, -- .hps_io_usb1_inst_D3
hps_io_hps_io_usb1_inst_D4 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D4, -- .hps_io_usb1_inst_D4
hps_io_hps_io_usb1_inst_D5 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D5, -- .hps_io_usb1_inst_D5
hps_io_hps_io_usb1_inst_D6 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D6, -- .hps_io_usb1_inst_D6
hps_io_hps_io_usb1_inst_D7 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D7, -- .hps_io_usb1_inst_D7
hps_io_hps_io_usb1_inst_CLK => CONNECTED_TO_hps_io_hps_io_usb1_inst_CLK, -- .hps_io_usb1_inst_CLK
hps_io_hps_io_usb1_inst_STP => CONNECTED_TO_hps_io_hps_io_usb1_inst_STP, -- .hps_io_usb1_inst_STP
hps_io_hps_io_usb1_inst_DIR => CONNECTED_TO_hps_io_hps_io_usb1_inst_DIR, -- .hps_io_usb1_inst_DIR
hps_io_hps_io_usb1_inst_NXT => CONNECTED_TO_hps_io_hps_io_usb1_inst_NXT, -- .hps_io_usb1_inst_NXT
hps_io_hps_io_spim1_inst_CLK => CONNECTED_TO_hps_io_hps_io_spim1_inst_CLK, -- .hps_io_spim1_inst_CLK
hps_io_hps_io_spim1_inst_MOSI => CONNECTED_TO_hps_io_hps_io_spim1_inst_MOSI, -- .hps_io_spim1_inst_MOSI
hps_io_hps_io_spim1_inst_MISO => CONNECTED_TO_hps_io_hps_io_spim1_inst_MISO, -- .hps_io_spim1_inst_MISO
hps_io_hps_io_spim1_inst_SS0 => CONNECTED_TO_hps_io_hps_io_spim1_inst_SS0, -- .hps_io_spim1_inst_SS0
hps_io_hps_io_uart0_inst_RX => CONNECTED_TO_hps_io_hps_io_uart0_inst_RX, -- .hps_io_uart0_inst_RX
hps_io_hps_io_uart0_inst_TX => CONNECTED_TO_hps_io_hps_io_uart0_inst_TX, -- .hps_io_uart0_inst_TX
hps_io_hps_io_i2c0_inst_SDA => CONNECTED_TO_hps_io_hps_io_i2c0_inst_SDA, -- .hps_io_i2c0_inst_SDA
hps_io_hps_io_i2c0_inst_SCL => CONNECTED_TO_hps_io_hps_io_i2c0_inst_SCL, -- .hps_io_i2c0_inst_SCL
hps_io_hps_io_i2c1_inst_SDA => CONNECTED_TO_hps_io_hps_io_i2c1_inst_SDA, -- .hps_io_i2c1_inst_SDA
hps_io_hps_io_i2c1_inst_SCL => CONNECTED_TO_hps_io_hps_io_i2c1_inst_SCL, -- .hps_io_i2c1_inst_SCL
hps_io_hps_io_gpio_inst_GPIO09 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO09, -- .hps_io_gpio_inst_GPIO09
hps_io_hps_io_gpio_inst_GPIO35 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO35, -- .hps_io_gpio_inst_GPIO35
hps_io_hps_io_gpio_inst_GPIO40 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO40, -- .hps_io_gpio_inst_GPIO40
hps_io_hps_io_gpio_inst_GPIO41 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO41, -- .hps_io_gpio_inst_GPIO41
hps_io_hps_io_gpio_inst_GPIO48 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO48, -- .hps_io_gpio_inst_GPIO48
hps_io_hps_io_gpio_inst_GPIO53 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO53, -- .hps_io_gpio_inst_GPIO53
hps_io_hps_io_gpio_inst_GPIO54 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO54, -- .hps_io_gpio_inst_GPIO54
hps_io_hps_io_gpio_inst_GPIO61 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO61, -- .hps_io_gpio_inst_GPIO61
leds_export => CONNECTED_TO_leds_export, -- leds.export
memory_mem_a => CONNECTED_TO_memory_mem_a, -- memory.mem_a
memory_mem_ba => CONNECTED_TO_memory_mem_ba, -- .mem_ba
memory_mem_ck => CONNECTED_TO_memory_mem_ck, -- .mem_ck
memory_mem_ck_n => CONNECTED_TO_memory_mem_ck_n, -- .mem_ck_n
memory_mem_cke => CONNECTED_TO_memory_mem_cke, -- .mem_cke
memory_mem_cs_n => CONNECTED_TO_memory_mem_cs_n, -- .mem_cs_n
memory_mem_ras_n => CONNECTED_TO_memory_mem_ras_n, -- .mem_ras_n
memory_mem_cas_n => CONNECTED_TO_memory_mem_cas_n, -- .mem_cas_n
memory_mem_we_n => CONNECTED_TO_memory_mem_we_n, -- .mem_we_n
memory_mem_reset_n => CONNECTED_TO_memory_mem_reset_n, -- .mem_reset_n
memory_mem_dq => CONNECTED_TO_memory_mem_dq, -- .mem_dq
memory_mem_dqs => CONNECTED_TO_memory_mem_dqs, -- .mem_dqs
memory_mem_dqs_n => CONNECTED_TO_memory_mem_dqs_n, -- .mem_dqs_n
memory_mem_odt => CONNECTED_TO_memory_mem_odt, -- .mem_odt
memory_mem_dm => CONNECTED_TO_memory_mem_dm, -- .mem_dm
memory_oct_rzqin => CONNECTED_TO_memory_oct_rzqin, -- .oct_rzqin
pushbuttons_export => CONNECTED_TO_pushbuttons_export, -- pushbuttons.export
sdram_addr => CONNECTED_TO_sdram_addr, -- sdram.addr
sdram_ba => CONNECTED_TO_sdram_ba, -- .ba
sdram_cas_n => CONNECTED_TO_sdram_cas_n, -- .cas_n
sdram_cke => CONNECTED_TO_sdram_cke, -- .cke
sdram_cs_n => CONNECTED_TO_sdram_cs_n, -- .cs_n
sdram_dq => CONNECTED_TO_sdram_dq, -- .dq
sdram_dqm => CONNECTED_TO_sdram_dqm, -- .dqm
sdram_ras_n => CONNECTED_TO_sdram_ras_n, -- .ras_n
sdram_we_n => CONNECTED_TO_sdram_we_n, -- .we_n
sdram_clk_clk => CONNECTED_TO_sdram_clk_clk, -- sdram_clk.clk
slider_switches_export => CONNECTED_TO_slider_switches_export, -- slider_switches.export
system_pll_ref_clk_clk => CONNECTED_TO_system_pll_ref_clk_clk, -- system_pll_ref_clk.clk
system_pll_ref_reset_reset => CONNECTED_TO_system_pll_ref_reset_reset, -- system_pll_ref_reset.reset
vga_CLK => CONNECTED_TO_vga_CLK, -- vga.CLK
vga_HS => CONNECTED_TO_vga_HS, -- .HS
vga_VS => CONNECTED_TO_vga_VS, -- .VS
vga_BLANK => CONNECTED_TO_vga_BLANK, -- .BLANK
vga_SYNC => CONNECTED_TO_vga_SYNC, -- .SYNC
vga_R => CONNECTED_TO_vga_R, -- .R
vga_G => CONNECTED_TO_vga_G, -- .G
vga_B => CONNECTED_TO_vga_B, -- .B
vga_pll_ref_clk_clk => CONNECTED_TO_vga_pll_ref_clk_clk, -- vga_pll_ref_clk.clk
vga_pll_ref_reset_reset => CONNECTED_TO_vga_pll_ref_reset_reset, -- vga_pll_ref_reset.reset
video_in_TD_CLK27 => CONNECTED_TO_video_in_TD_CLK27, -- video_in.TD_CLK27
video_in_TD_DATA => CONNECTED_TO_video_in_TD_DATA, -- .TD_DATA
video_in_TD_HS => CONNECTED_TO_video_in_TD_HS, -- .TD_HS
video_in_TD_VS => CONNECTED_TO_video_in_TD_VS, -- .TD_VS
video_in_clk27_reset => CONNECTED_TO_video_in_clk27_reset, -- .clk27_reset
video_in_TD_RESET => CONNECTED_TO_video_in_TD_RESET, -- .TD_RESET
video_in_overflow_flag => CONNECTED_TO_video_in_overflow_flag -- .overflow_flag
);
| mit | d0ca51ce076004453495f0b40fbd9e53 | 0.433604 | 3.213907 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue376/fx3_model_unmodified.vhdl | 1 | 6,850 | -- Copyright (c) 2013 Nuand LLC
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.math_real.all ;
use ieee.math_complex.all ;
library nuand ;
use nuand.util.all ;
entity fx3_model is
port (
fx3_pclk : buffer std_logic := '1' ;
fx3_gpif : inout std_logic_vector(31 downto 0) ;
fx3_ctl : inout std_logic_vector(12 downto 0) ;
fx3_uart_rxd : in std_logic ;
fx3_uart_txd : buffer std_logic ;
fx3_uart_cts : buffer std_logic ;
fx3_rx_en : in std_logic ;
fx3_rx_meta_en : in std_logic ;
fx3_tx_en : in std_logic ;
fx3_tx_meta_en : in std_logic
) ;
end entity ; -- fx3_model
architecture dma of fx3_model is
constant PCLK_HALF_PERIOD : time := 1 sec * (1.0/100.0e6/2.0) ;
-- Control mapping
alias dma0_rx_ack is fx3_ctl( 0) ;
alias dma1_rx_ack is fx3_ctl( 1) ;
alias dma2_tx_ack is fx3_ctl( 2) ;
alias dma3_tx_ack is fx3_ctl( 3) ;
alias dma_rx_enable is fx3_ctl( 4) ;
alias dma_tx_enable is fx3_ctl( 5) ;
alias dma_idle is fx3_ctl( 6) ;
alias system_reset is fx3_ctl( 7) ;
alias dma0_rx_reqx is fx3_ctl( 8) ;
alias dma1_rx_reqx is fx3_ctl(12) ; -- due to 9 being connected to dclk
alias dma2_tx_reqx is fx3_ctl(10) ;
alias dma3_tx_reqx is fx3_ctl(11) ;
type gpif_state_t is (IDLE, TX_SAMPLES, RX_SAMPLES) ;
signal gpif_state : gpif_state_t ;
begin
-- DCLK which isn't used
fx3_ctl(9) <= '0' ;
-- Create a 100MHz clock output
fx3_pclk <= not fx3_pclk after PCLK_HALF_PERIOD ;
rx_sample_stream : process
constant BLOCK_SIZE : natural := 512 ;
variable count : natural := 0 ;
begin
dma0_rx_reqx <= '1' ;
dma1_rx_reqx <= '1' ;
dma_rx_enable <= '0' ;
wait until rising_edge(fx3_pclk) and system_reset = '0' ;
for i in 1 to 10 loop
wait until rising_edge( fx3_pclk ) ;
end loop ;
if( fx3_rx_en = '0' ) then
wait;
end if;
wait for 30 us;
dma_rx_enable <= '1' ;
while true loop
for i in 0 to 2 loop
dma0_rx_reqx <= '0' ;
wait until rising_edge( fx3_pclk ) and dma0_rx_ack = '1' ;
wait until rising_edge( fx3_pclk ) ;
wait until rising_edge( fx3_pclk ) ;
dma0_rx_reqx <= '1' ;
for i in 1 to BLOCK_SIZE loop
wait until rising_edge( fx3_pclk ) ;
end loop ;
end loop ;
dma_rx_enable <= '0' ;
for i in 0 to 5000 loop
wait until rising_edge(fx3_pclk) ;
end loop ;
dma_rx_enable <= '1' ;
for i in 0 to 10 loop
wait until rising_edge(fx3_pclk);
end loop ;
end loop ;
report "Done with RX sample stream" ;
wait ;
end process ;
tx_sample_stream : process
constant BLOCK_SIZE : natural := 512 ;
variable count : natural := 0 ;
variable timestamp_cntr : natural := 80;
variable header_len : natural := 0;
begin
dma2_tx_reqx <= '1' ;
dma3_tx_reqx <= '1' ;
dma_tx_enable <= '0' ;
fx3_gpif <= (others =>'Z') ;
wait until system_reset = '0' ;
for i in 0 to 1000 loop
wait until rising_edge( fx3_pclk ) ;
end loop ;
if( fx3_tx_en = '0' ) then
wait;
end if;
wait for 120 us;
dma_tx_enable <= '1' ;
for i in 0 to 3 loop
dma3_tx_reqx <= '0' ;
wait until rising_edge( fx3_pclk ) and dma3_tx_ack = '1' ;
wait until rising_edge( fx3_pclk ) ;
wait until rising_edge( fx3_pclk ) ;
dma3_tx_reqx <= '1' ;
if( fx3_tx_meta_en = '1') then
for i in 1 to 4 loop
if (i = 1 ) then
fx3_gpif <= x"12341234";
elsif (i = 3 ) then
fx3_gpif <= (others => '0');
elsif(i = 4) then
fx3_gpif <= (others => '1');
elsif (i = 2) then
fx3_gpif(31 downto 0) <= std_logic_vector(to_signed(timestamp_cntr, 32));
timestamp_cntr := timestamp_cntr + 508 * 2;
end if;
wait until rising_edge( fx3_pclk );
end loop;
header_len := 4;
else
header_len := 0;
end if;
for i in 1 to BLOCK_SIZE - header_len loop
fx3_gpif(31 downto 16) <= std_logic_vector(to_signed(count, 16)) ;
fx3_gpif(15 downto 0) <= std_logic_vector(to_signed(-count, 16)) ;
count := (count + 1) mod 2048 ;
wait until rising_edge( fx3_pclk );
end loop ;
fx3_gpif <= (others =>'Z');
for i in 1 to 10 loop
wait until rising_edge( fx3_pclk );
end loop ;
end loop ;
report "Done with TX sample stream" ;
wait ;
end process ;
reset_system : process
begin
system_reset <= '1' ;
dma_idle <= '0' ;
nop( fx3_pclk, 100 ) ;
system_reset <= '0' ;
nop( fx3_pclk, 10 ) ;
dma_idle <= '1' ;
wait ;
end process ;
-- TODO: UART Interface
fx3_uart_txd <= '1' ;
fx3_uart_cts <= '1' ;
end architecture ; -- dma
architecture inband_scheduler of fx3_model is
begin
end architecture ; -- inband_scheduler
| gpl-2.0 | d0d0c64000c2dfbc59891238968b8bc8 | 0.526715 | 3.597689 | false | false | false | false |
nickg/nvc | test/regress/array12.vhd | 1 | 996 | entity array12 is
end entity;
architecture test of array12 is
type rec is record
x : integer_vector;
end record;
type rec_vec is array (natural range <>) of rec;
type rec_vec_vec is array (natural range <>) of rec_vec;
function sum_all (r : rec_vec_vec) return integer is
variable result : integer := 0;
begin
for i in r'range loop
for j in r(i)'range loop
for k in r(i)(j).x'range loop
result := result + r(i)(j).x(k);
end loop;
end loop;
end loop;
return result;
end function;
signal s : rec_vec_vec(1 to 2)(1 to 1)(x(1 to 3));
begin
p1: process is
begin
s <= ( ( 1 => ( x => (1, 2, 3) ) ),
( 1 => ( x => (4, 5, 6) ) ) );
wait for 1 ns;
assert sum_all(s) = 21;
s(1)(1).x(1) <= 5;
wait for 1 ns;
assert sum_all(s) = 25;
wait;
end process;
end architecture;
| gpl-3.0 | d073da32a7bd0a1eb3f5ad868f4cbc2f | 0.48996 | 3.446367 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue216/repro2.vhdl | 2 | 258 | entity repro2 is
end repro2;
architecture behav of repro2 is
constant c : natural := 2;
constant cmap : string (1 to 5) :=
(1 => 'a', 2 => 'b', 3 => 'c', 4 => 'd', 5 => 'e');
begin
assert cmap (c) = 'b';
assert cmap & 'f' = "abcdef";
end behav;
| gpl-2.0 | b288050c3bb5968117cf8e25adab4817 | 0.546512 | 2.744681 | false | false | false | false |
tgingold/ghdl | testsuite/synth/fsm02/recv.vhdl | 1 | 2,276 | library ieee;
use ieee.std_logic_1164.all;
entity recv is
port (
rst : std_logic;
clk : std_logic;
rx : std_logic;
byte : out std_logic_vector (7 downto 0);
b_err : out std_logic;
b_en : out std_logic);
end recv;
architecture behav of recv
is
type state_t is
(s_wait, s0, s1, s2, s3, s4, s5, s6, s7, s_parity, s_stop);
signal state: state_t;
signal parity: std_logic;
signal err : std_logic;
signal en : std_logic;
begin
process (clk) is
begin
if rising_edge(clk) then
if rst = '1' then
state <= s_wait;
err <= '0';
en <= '0';
else
en <= '0';
case state is
when s_wait =>
if rx = '0' then
state <= s0;
err <= '0';
parity <= '0';
end if;
when s0 =>
byte (0) <= rx;
parity <= parity xor rx;
state <= s1;
when s1 =>
byte (1) <= rx;
parity <= parity xor rx;
state <= s2;
when s2 =>
byte (2) <= rx;
parity <= parity xor rx;
state <= s3;
when s3 =>
byte (3) <= rx;
parity <= parity xor rx;
state <= s4;
when s4 =>
byte (4) <= rx;
parity <= parity xor rx;
state <= s5;
when s5 =>
byte (5) <= rx;
parity <= parity xor rx;
state <= s6;
when s6 =>
byte (6) <= rx;
parity <= parity xor rx;
state <= s7;
when s7 =>
byte (7) <= rx;
parity <= parity xor rx;
state <= s_parity;
when s_parity =>
if rx /= parity then
err <= '1';
end if;
state <= s_stop;
when s_stop =>
if rx /= '1' then
err <= '1';
end if;
en <= '1';
state <= s_wait;
end case;
end if;
end if;
end process;
b_en <= en;
b_err <= err;
--psl default clock is rising_edge(clk);
--psl restrict {rst;(not rst)[*]};
assert rst = '1' or err /= '1' report "parity error" severity error;
end behav;
| gpl-2.0 | 1a6c81b1e8e2e2a43163ee6e501f0374 | 0.413445 | 3.694805 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1080/repro3.vhdl | 1 | 777 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity repro3 is
port (
clk : std_logic;
led : out std_logic);
end;
architecture behav of repro3 is
constant LOOKUP_LEN : integer := 6;
constant LOOKUP_TABLE : unsigned(LOOKUP_LEN*8-1 downto 0) :=
x"010205" & x"060708";
signal brt : unsigned(7 downto 0) := (others => '0');
begin
led <= brt (0);
lookup_p : process(Clk)
variable idx : integer range 0 to LOOKUP_LEN-1 := LOOKUP_LEN-1;
begin
if rising_edge(Clk) then
brt <= lookup_table(8*idx+7 downto 8*idx);
if idx /= 0 then
idx := idx - 1;
else
idx := LOOKUP_LEN-1;
end if;
end if;
end process;
end behav;
| gpl-2.0 | 185698d28027d31a11b25fbf8cae9270 | 0.555985 | 3.378261 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/resolution/memory_system.vhd | 4 | 2,336 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
use work.MVL4.all;
entity ROM is
port ( a : in MVL4_ulogic_vector(15 downto 0);
d : inout MVL4_logic_vector(7 downto 0);
rd : in MVL4_ulogic );
end entity ROM;
-- not in book
architecture behavioral of ROM is
begin
end architecture behavioral;
-- end not in book
--------------------------------------------------
use work.MVL4.all;
entity SIMM is
port ( a : in MVL4_ulogic_vector(9 downto 0);
d : inout MVL4_logic_vector(31 downto 0);
ras, cas, we, cs : in MVL4_ulogic );
end entity SIMM;
-- not in book
architecture behavioral of SIMM is
begin
end architecture behavioral;
-- end not in book
--------------------------------------------------
-- not in book
use work.MVL4.all;
entity memory_subsystem is
end entity memory_subsystem;
-- end not in book
architecture detailed of memory_subsystem is
signal internal_data : MVL4_logic_vector(31 downto 0);
-- . . .
-- not in book
signal internal_addr : MVL4_ulogic_vector(31 downto 0);
signal main_mem_addr : MVL4_ulogic_vector(9 downto 0);
signal ROM_select : MVL4_ulogic;
-- end not in book
begin
boot_ROM : entity work.ROM(behavioral)
port map ( a => internal_addr(15 downto 0),
d => internal_data(7 downto 0),
rd => ROM_select );
main_mem : entity work.SIMM(behavioral)
port map ( a => main_mem_addr, d => internal_data, -- . . . );
-- not in book
ras => '0', cas => '0', we => '0', cs => '0' );
-- end not in book
-- . . .
end architecture detailed;
| gpl-2.0 | 64ceb3c2fcd5928d881718590d83a997 | 0.640411 | 3.74359 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue50/vector.d/v_split5.vhd | 2 | 1,357 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity v_split5 is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(7 downto 0);
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic;
wa0_en : in std_logic;
ra0_addr : in std_logic
);
end v_split5;
architecture augh of v_split5 is
-- Embedded RAM
type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 | cb382e69bf851d8dd41b964056b07ce4 | 0.668386 | 2.856842 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug18810/BENCH_OISC_SUBLEQ.vhd | 3 | 6,925 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.OISC_SUBLEQ_PKG.all;
entity BENCH_OISC_SUBLEQ is
begin
end entity BENCH_OISC_SUBLEQ;
architecture BENCH of BENCH_OISC_SUBLEQ is
signal sPCLK : std_logic := '0';
signal sDCLK : std_logic := '0';
signal sCLK : std_logic := '0';
signal sCLR : std_logic := '1';
constant cPCLK_CYCLE : time := 1000.0 ns / 250.0; -- NOTE: 250[MHz]
constant cDCLK_CYCLE : time := 1000.0 ns / 200.0; -- NOTE: 200[MHz]
constant cCLK_CYCLE : time := 1000.0 ns / 150.0; -- NOTE: 150[MHz]
constant cCLR_TIME : time := 10*cCLK_CYCLE;
constant clog2PADDR : integer range 0 to integer'high := 8;
constant clog2DADDR : integer range 0 to integer'high := 4;
constant cDW : integer range 1 to integer'high := 8;
type tPIF is record
OISC_SUBLEQ_oPINST : std_logic_vector(clog2DADDR+clog2DADDR+clog2PADDR-1 downto 0);
end record tPIF;
signal sP : tPIF;
type tP is record
OISC_SUBLEQ_iPWE : std_logic;
OISC_SUBLEQ_iPADDR : integer range 0 to 2**clog2PADDR-1;
OISC_SUBLEQ_iPINST : std_logic_vector(clog2DADDR+clog2DADDR+clog2PADDR-1 downto 0);
DONE : std_logic;
end record tP;
constant cP : tP := (
OISC_SUBLEQ_iPWE => '0',
OISC_SUBLEQ_iPADDR => 0,
OISC_SUBLEQ_iPINST => (clog2DADDR+clog2DADDR+clog2PADDR-1 downto 0 => '0'),
DONE => '0'
);
signal rP : tP := cP;
type tDIF is record
OISC_SUBLEQ_oDDATA : std_logic_vector(cDW-1 downto 0);
end record tDIF;
signal sD : tDIF;
type tD is record
OISC_SUBLEQ_iDWE : std_logic;
OISC_SUBLEQ_iDADDR : integer range 0 to 2**clog2DADDR-1;
OISC_SUBLEQ_iDDATA : std_logic_vector(cDW-1 downto 0);
DONE : std_logic;
end record tD;
constant cD : tD := (
OISC_SUBLEQ_iDWE => '0',
OISC_SUBLEQ_iDADDR => 0,
OISC_SUBLEQ_iDDATA => (cDW-1 downto 0 => '0'),
DONE => '0'
);
signal rD : tD := cD;
type tIF is record
OISC_SUBLEQ_oACT : std_logic;
OISC_SUBLEQ_oPC : integer range 0 to 2**clog2PADDR-1;
OISC_SUBLEQ_oLEQ : std_logic;
end record tIF;
signal s : tIF;
type t is record
ACT : std_logic;
DONE : std_logic;
end record t;
constant c : t := (
ACT => '0',
DONE => '0'
);
signal r : t := c;
begin
P_sPCLK : process
begin
sPCLK <= '0'; wait for cPCLK_CYCLE/2;
sPCLK <= '1'; wait for cPCLK_CYCLE/2;
end process P_sPCLK;
P_sDCLK : process
begin
sDCLK <= '0'; wait for cDCLK_CYCLE/2;
sDCLK <= '1'; wait for cDCLK_CYCLE/2;
end process P_sDCLK;
P_sCLK : process
begin
sCLK <= '0'; wait for cCLK_CYCLE/2;
sCLK <= '1'; wait for cCLK_CYCLE/2;
end process P_sCLK;
P_sCLR : process
begin
sCLR <= '1'; wait for cCLR_TIME;
sCLR <= '0'; wait;
end process P_sCLR;
B_STIM : block is
pure function fINST (
iA : integer range 0 to 2**clog2DADDR-1;
iB : integer range 0 to 2**clog2DADDR-1;
iC : integer range 0 to 2**clog2PADDR-1
) return std_logic_vector is
variable vA : std_logic_vector(clog2DADDR-1 downto 0);
variable vB : std_logic_vector(clog2DADDR-1 downto 0);
variable vC : std_logic_vector(clog2PADDR-1 downto 0);
begin
vA := std_logic_vector(to_unsigned(iA, clog2DADDR));
vB := std_logic_vector(to_unsigned(iB, clog2DADDR));
vC := std_logic_vector(to_unsigned(iC, clog2PADDR));
return vA & vB & vC;
end function fINST;
constant cD_Z : integer range 0 to 2**clog2DADDR-1 := 0;
constant cD_X : integer range 0 to 2**clog2DADDR-1 := 1;
constant cD_Y : integer range 0 to 2**clog2DADDR-1 := 2;
constant cV_Z : std_logic_vector(cDW-1 downto 0) := std_logic_vector(to_signed( 0, cDW));
constant cV_X : std_logic_vector(cDW-1 downto 0) := std_logic_vector(to_signed(12, cDW));
constant cV_Y : std_logic_vector(cDW-1 downto 0) := std_logic_vector(to_signed(34, cDW));
constant cP_ORG : integer range 0 to 2**clog2PADDR-1 := 0;
constant cP_START : integer range 0 to 2**clog2PADDR-1 := cP_ORG+8;
constant cP_STOP : integer range 0 to 2**clog2PADDR-1 := 2**clog2PADDR-1;
begin
P_STIM_P : process
begin
-- ORG: JMP START = ORG: subleq Z, Z, START
rP.OISC_SUBLEQ_iPADDR <= cP_ORG;
rP.OISC_SUBLEQ_iPINST <= fINST(cD_Z, cD_Z, cP_START);
rP.OISC_SUBLEQ_iPWE <= '1';
wait until (rising_edge(sPCLK));
-- START: ADD X, Y = START: subleq X, Z, START+1
-- subleq Z, Y, START+2
-- subleq Z, Z, START+3
rP.OISC_SUBLEQ_iPADDR <= cP_START;
rP.OISC_SUBLEQ_iPINST <= fINST(cD_X, cD_Z, cP_START+1);
rP.OISC_SUBLEQ_iPWE <= '1';
wait until (rising_edge(sPCLK));
rP.OISC_SUBLEQ_iPADDR <= cP_START+1;
rP.OISC_SUBLEQ_iPINST <= fINST(cD_Z, cD_Y, cP_START+2);
rP.OISC_SUBLEQ_iPWE <= '1';
wait until (rising_edge(sPCLK));
rP.OISC_SUBLEQ_iPADDR <= cP_START+2;
rP.OISC_SUBLEQ_iPINST <= fINST(cD_Z, cD_Z, cP_START+3);
rP.OISC_SUBLEQ_iPWE <= '1';
wait until (rising_edge(sPCLK));
-- START+3: JUMP STOP = START+3: subleq Z, Z, STOP
rP.OISC_SUBLEQ_iPADDR <= cP_START+3;
rP.OISC_SUBLEQ_iPINST <= fINST(cD_Z, cD_Z, cP_STOP);
rP.OISC_SUBLEQ_iPWE <= '1';
wait until (rising_edge(sPCLK));
-- STOP: JUMP STOP = STOP: subleq Z, Z, STOP
rP.OISC_SUBLEQ_iPADDR <= cP_STOP;
rP.OISC_SUBLEQ_iPINST <= fINST(cD_Z, cD_Z, cP_STOP);
rP.OISC_SUBLEQ_iPWE <= '1';
wait until (rising_edge(sPCLK));
rP <= cP;
rP.DONE <= '1';
wait;
end process P_STIM_P;
P_STIM_D : process
begin
rD.OISC_SUBLEQ_iDADDR <= cD_Z;
rD.OISC_SUBLEQ_iDDATA <= cV_Z;
rD.OISC_SUBLEQ_iDWE <= '1';
wait until (rising_edge(sDCLK));
rD.OISC_SUBLEQ_iDADDR <= cD_X;
rD.OISC_SUBLEQ_iDDATA <= cV_X;
rD.OISC_SUBLEQ_iDWE <= '1';
wait until (rising_edge(sDCLK));
rD.OISC_SUBLEQ_iDADDR <= cD_Y;
rD.OISC_SUBLEQ_iDDATA <= cV_Y;
rD.OISC_SUBLEQ_iDWE <= '1';
wait until (rising_edge(sDCLK));
rD <= cD;
rD.DONE <= '1';
wait;
end process P_STIM_D;
P_STIM : process
begin
wait until (rP.DONE = '1' and rD.DONE = '1' and sCLR /= '1');
wait until (rising_edge(sCLK));
r.ACT <= '1';
wait until (rising_edge(sCLK));
wait until (s.OISC_SUBLEQ_oPC = cP_STOP);
r.ACT <= '0';
r.DONE <= '1';
wait;
end process P_STIM;
end block B_STIM;
U_OISC_SUBLEQ : OISC_SUBLEQ
generic map (
log2PADDR => clog2PADDR,
log2DADDR => clog2DADDR,
DW => cDW,
ZERO => false,
ASYNC => false
)
port map (
iPCLK => sPCLK,
iPWE => rP.OISC_SUBLEQ_iPWE,
iPADDR => rP.OISC_SUBLEQ_iPADDR,
iPINST => rP.OISC_SUBLEQ_iPINST,
oPINST => sP.OISC_SUBLEQ_oPINST,
iDCLK => sDCLK,
iDWE => rD.OISC_SUBLEQ_iDWE,
iDADDR => rD.OISC_SUBLEQ_iDADDR,
iDDATA => rD.OISC_SUBLEQ_iDDATA,
oDDATA => sD.OISC_SUBLEQ_oDDATA,
iCLR => sCLR,
iCLK => sCLK,
iACT => r.ACT,
oACT => s.OISC_SUBLEQ_oACT,
oPC => s.OISC_SUBLEQ_oPC,
oLEQ => s.OISC_SUBLEQ_oLEQ
);
end architecture BENCH;
| gpl-2.0 | a86dc888facb8f7ce6fc612868ae2974 | 0.618484 | 2.65631 | false | false | false | false |
DE5Amigos/SylvesterTheDE2Bot | DE2Botv3Fall16Main/VEL_CONTROL.vhd | 1 | 11,978 | -- VEL_CONTROL.VHD
-- Based on the velocity controller by Team Flying Robots, Spring 2011
-- Subsequent mods by T. Collins and K. Johnson, including addition of closed-loop control
-- DO NOT ALTER ANYTHING IN THIS FILE.
-- IT IS EASY TO CREATE POSITIVE FEEDBACK,
-- INSTABILITY, AND RUNAWAY ROBOTS!!
LIBRARY IEEE;
LIBRARY LPM;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
USE LPM.LPM_COMPONENTS.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY VEL_CONTROL IS
PORT(PWM_CLK, -- must be a 100 MHz clock signal to get ~25kHz phase frequency
RESETN,
CS, -- chip select, asserted when new speed is input
IO_WRITE : IN STD_LOGIC; -- asserted when being written to
IO_DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- commanded speed from SCOMP (only lower 8 bits used)
POSITION : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- actual position of motor, for closed loop control
CTRL_CLK : IN STD_LOGIC; -- clock that determines control loop sampling rate (64 Hz)
ENABLE : IN STD_LOGIC; -- prevents running control while motors are disabled
SOFT_HALT : IN STD_LOGIC; -- resets desired velocity to 0
MOTOR_PHASE : OUT STD_LOGIC; -- polarity of motor output
MOTOR_EN : OUT STD_LOGIC;
I_WARN : OUT STD_LOGIC; -- integrator warning
WATCHDOG : OUT STD_LOGIC; -- safety feature
I_VAL : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) -- integrator level
);
END VEL_CONTROL;
-- DO NOT ALTER ANYTHING IN THIS FILE.
-- IT IS EASY TO CREATE POSITIVE FEEDBACK,
-- INSTABILITY, AND RUNAWAY ROBOTS!!
ARCHITECTURE a OF VEL_CONTROL IS
SIGNAL COUNT : STD_LOGIC_VECTOR(11 DOWNTO 0); -- counter output
SIGNAL IO_DATA_INT : STD_LOGIC_VECTOR(15 DOWNTO 0); -- internal speed value
SIGNAL POSITION_INT : STD_LOGIC_VECTOR(31 DOWNTO 0); -- internal speed value
SIGNAL LATCH : STD_LOGIC;
SIGNAL PWM_CMD : STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL MOTOR_PHASE_INT : STD_LOGIC;
SIGNAL FIRST_PASS : STD_LOGIC;
SIGNAL SH_ACK, SH_REQ : STD_LOGIC;
SIGNAL I_WARN_INT : STD_LOGIC;
SIGNAL WATCHDOG_INT : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
-- Use LPM counter megafunction to make a divide-by-4096 counter
counter: LPM_COUNTER
GENERIC MAP(
lpm_width => 12,
lpm_direction => "UP"
)
PORT MAP(
clock => PWM_CLK,
q => COUNT
);
-- DO NOT ALTER ANYTHING IN THIS FILE.
-- IT IS EASY TO CREATE POSITIVE FEEDBACK,
-- INSTABILITY, AND RUNAWAY ROBOTS!!
-- Use LPM compare megafunction to produce desired duty cycle
compare: LPM_COMPARE
GENERIC MAP(
lpm_width => 12,
lpm_representation => "UNSIGNED"
)
PORT MAP(
dataa => COUNT,
datab => PWM_CMD(11 DOWNTO 0),
ageb => MOTOR_PHASE_INT
);
-- DO NOT ALTER ANYTHING IN THIS FILE.
-- IT IS EASY TO CREATE POSITIVE FEEDBACK,
-- INSTABILITY, AND RUNAWAY ROBOTS!!
LATCH <= CS AND IO_WRITE; -- part of IO fix (below) -- TRC
I_WARN <= I_WARN_INT; -- output integrator warning
PROCESS (RESETN, LATCH, SOFT_HALT)
BEGIN
-- set speed to 0 after a reset
IF RESETN = '0' THEN
IO_DATA_INT <= x"0000";
MOTOR_EN <= '0';
ELSIF SOFT_HALT = '0' THEN
IO_DATA_INT <= x"0000";
-- keep the IO data (velocity command) from SCOMP in an internal register IO_DATA_INT
ELSIF RISING_EDGE(LATCH) THEN -- fixed unreliable OUT operation - TRC
-- make sure data is within correct range
IF ((IO_DATA(15 DOWNTO 9) = "000000000")
OR ((IO_DATA(15 DOWNTO 9) = "111111111") AND (IO_DATA(8 DOWNTO 0) /= "000000000"))) THEN
IO_DATA_INT <= IO_DATA(15 DOWNTO 0);
ELSE
IO_DATA_INT <= x"0000"; -- behavior for out of range (treat as zero)
END IF;
MOTOR_EN <= '1';
END IF;
END PROCESS;
-- DO NOT ALTER ANYTHING IN THIS FILE.
-- IT IS EASY TO CREATE POSITIVE FEEDBACK,
-- INSTABILITY, AND RUNAWAY ROBOTS!!
-- process to help handle software position resets.
PROCESS (SOFT_HALT, SH_ACK)
BEGIN
IF SH_ACK = '1' THEN
SH_REQ <= '0';
ELSIF RISING_EDGE(SOFT_HALT) THEN
SH_REQ <= '1';
END IF;
END PROCESS;
PROCESS BEGIN -- sample the position
WAIT UNTIL FALLING_EDGE(CTRL_CLK);
POSITION_INT <= POSITION;
END PROCESS;
-- added closed loop control so that motor will try to achieve exactly the value commanded - TRC
PROCESS (CTRL_CLK, RESETN, ENABLE)
VARIABLE IN_VEL, CMD_VEL, VEL_ERR, CUM_VEL_ERR: INTEGER := 0;
VARIABLE LAST_CMD_VEL, LAST_VEL: INTEGER := 0;
VARIABLE CURR_VEL, CURR_POS, LAST_POS: INTEGER := 0;
VARIABLE DERR: INTEGER := 0;
CONSTANT ELIMIT: INTEGER := 500; -- prevents excessive control
CONSTANT ILIMIT: INTEGER := 32767; -- Prevents excessive integral
CONSTANT LIMIT: INTEGER := 6000000; -- prevents excessive speed
CONSTANT DEADZONE: INTEGER := 1600000;
CONSTANT MAX_ACC: INTEGER := 128; -- limit overall acceleration to 1024(tick/s)/s
VARIABLE MOTOR_CMD: INTEGER := 0;
VARIABLE PROP_CTRL, INT_CTRL, DERIV_CTRL, FF_CTRL: INTEGER := 0;
-- DO NOT ALTER ANYTHING IN THIS FILE.
-- IT IS EASY TO CREATE POSITIVE FEEDBACK,
-- INSTABILITY, AND RUNAWAY ROBOTS!!
CONSTANT KP: INTEGER := 2500;--3000;
CONSTANT KI: INTEGER := 52;
CONSTANT KD: INTEGER := 13;
CONSTANT KF: INTEGER := 1600;
BEGIN
I_VAL <= STD_LOGIC_VECTOR(TO_SIGNED((CUM_VEL_ERR), I_VAL'LENGTH));
IF (RESETN = '0') OR (ENABLE = '0') THEN
MOTOR_CMD := 0; -- at startup, motor should be stopped
CUM_VEL_ERR := 0;
LAST_VEL := 0;
CURR_VEL := 0;
DERR := 0;
CURR_POS := 0;
LAST_POS := 0;
IN_VEL := 0;
CMD_VEL := 0;
I_WARN_INT <= '0';
FIRST_PASS <= '1';
SH_ACK <= '0';
CUM_VEL_ERR := 0;
ELSIF RISING_EDGE(CTRL_CLK) THEN -- determine a control signal at each control cycle
IF (FIRST_PASS = '1') OR (SH_REQ = '1') THEN -- avoid jumps when first enabled
CURR_POS := TO_INTEGER(SIGNED(POSITION_INT));
LAST_POS := TO_INTEGER(SIGNED(POSITION_INT));
FIRST_PASS <= '0';
SH_ACK <= '1';
ELSE
SH_ACK <= '0';
-- update the command velocity
-- user control value units are 128ticks/s; control clock here is 32Hz; so there's a factor of 4
IN_VEL := TO_INTEGER(SIGNED(IO_DATA_INT(9 DOWNTO 0)&"00")); -- match magnitudes
-- Control acceleration
IF WATCHDOG_INT = "00000000" THEN
-- If soft watchdog times out, decelerate to 0
IF CMD_VEL > MAX_ACC THEN
CMD_VEL := CMD_VEL - MAX_ACC;
ELSIF CMD_VEL < -MAX_ACC THEN
CMD_VEL := CMD_VEL + MAX_ACC;
ELSE
CMD_VEL := 0;
END IF;
ELSE -- if watchdog active, accelerate normally
IF IN_VEL - CMD_VEL > MAX_ACC THEN
CMD_VEL := CMD_VEL + MAX_ACC;
ELSIF IN_VEL - CMD_VEL < -MAX_ACC THEN
CMD_VEL := CMD_VEL - MAX_ACC;
ELSE
CMD_VEL := IN_VEL;
END IF;
END IF;
-- check current error based on previous interval
CURR_POS := TO_INTEGER(SIGNED(POSITION_INT));
LAST_VEL := CURR_VEL;
CURR_VEL := CURR_POS - LAST_POS;
LAST_POS := CURR_POS;
VEL_ERR := CMD_VEL - CURR_VEL; -- commanded vel should equal measured vel
-- derivative term is calculated as "derivative on measurement" to avoid kick.
DERR := LAST_VEL - CURR_VEL;
DERIV_CTRL := DERR * KD;-- The "D" component
PROP_CTRL := VEL_ERR * KP; -- The "P" component of the PID controller
-- Limit the error going in to the integrator
IF (VEL_ERR > ELIMIT) THEN
VEL_ERR := ELIMIT;
ELSIF (VEL_ERR < -ELIMIT) THEN
VEL_ERR := -ELIMIT;
END IF;
IF (CURR_VEL = 0) AND (CMD_VEL = 0) THEN
CUM_VEL_ERR := 0; -- when stopped, clear the integrator
ELSIF (CUM_VEL_ERR + VEL_ERR) > ILIMIT THEN
-- limit the I term, and set the stall warning if I is too large.
CUM_VEL_ERR := ILIMIT; -- limit integrator when motor is stopped or stalled
I_WARN_INT <= '1';
ELSIF (CUM_VEL_ERR + VEL_ERR) < -ILIMIT THEN
CUM_VEL_ERR := -ILIMIT; -- limit integrator when motor is stopped or stalled
I_WARN_INT <= '1';
ELSE
CUM_VEL_ERR := CUM_VEL_ERR + VEL_ERR; -- perform the integration, if not near setpoint
I_WARN_INT <= '0';
END IF;
INT_CTRL := CUM_VEL_ERR * KI; -- The "I" component
IF CMD_VEL > 0 THEN
FF_CTRL := CMD_VEL * KF + DEADZONE; -- FeedForward component...
ELSIF CMD_VEL < 0 THEN
FF_CTRL := CMD_VEL * KF - DEADZONE; -- FeedForward component...
ELSE
FF_CTRL := 0;
END IF;
MOTOR_CMD := (FF_CTRL) + (PROP_CTRL) + (INT_CTRL) + (DERIV_CTRL);
-- Cap the motor command at its safe limit
IF (MOTOR_CMD > LIMIT) THEN
MOTOR_CMD := LIMIT;
ELSIF (MOTOR_CMD < -LIMIT) THEN
MOTOR_CMD := -LIMIT;
END IF;
END IF;
END IF;
PWM_CMD <= STD_LOGIC_VECTOR(TO_SIGNED((MOTOR_CMD/8192)+2048, PWM_CMD'LENGTH));
END PROCESS;
-- copy internal signal to external
PROCESS BEGIN
WAIT UNTIL RISING_EDGE(PWM_CLK);
MOTOR_PHASE <= MOTOR_PHASE_INT;
END PROCESS;
-- soft watchdog to control hard watchdog
PROCESS (RESETN, LATCH, CTRL_CLK)
BEGIN
IF (RESETN = '0') THEN
WATCHDOG_INT <= "00000000";
ELSIF (LATCH = '1') THEN -- async set when written
WATCHDOG_INT <= "00010000"; -- half a second timeout
ELSIF RISING_EDGE(CTRL_CLK) THEN
IF WATCHDOG_INT /= "00000000" THEN
WATCHDOG_INT <= WATCHDOG_INT - 1;
END IF;
END IF;
END PROCESS;
-- toggle the hard watchdog
WITH WATCHDOG_INT SELECT WATCHDOG <=
'0' WHEN "00000000",
CTRL_CLK WHEN OTHERS;
END a;
-- DO NOT ALTER ANYTHING IN THIS FILE.
-- IT IS EASY TO CREATE POSITIVE FEEDBACK,
-- INSTABILITY, AND RUNAWAY ROBOTS!!
| mit | 0544f4cc5d6311ae14a6c28ec2f6a9a2 | 0.507514 | 3.966225 | false | false | false | false |
nickg/nvc | test/jit/case1.vhd | 1 | 1,241 | package case1 is
type t is (a, b, c);
function test1(x : t) return integer;
function test2(x : bit_vector(1 to 4)) return integer;
end package;
package body case1 is
function test1(x : t) return integer is
begin
case x is
when a => return 10;
when b => return 20;
when c => return 30;
end case;
end function;
function test2(x : bit_vector(1 to 4)) return integer is
variable result : integer := 0;
begin
case x is
when "0000" => result := 0;
when "0001" => result := 1;
when "0010" => result := 2;
when "0011" => result := 3;
when "0100" => result := 4;
when "0101" => result := 5;
when "0110" => result := 6;
when "0111" => result := 7;
when "1000" => result := 8;
when "1001" => result := 9;
when "1010" => result := 10;
when "1011" => result := 11;
when "1100" => result := 12;
when "1101" => result := 13;
when "1110" => result := 14;
when "1111" => result := 15;
end case;
return result;
end function;
end package body;
| gpl-3.0 | 1c83d4488bd36cd9e4f4267c2cfb4d4b | 0.471394 | 3.952229 | false | true | false | false |
nickg/nvc | lib/ieee.08/numeric_std-body.vhdl | 1 | 139,737 | -- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Standard VHDL Synthesis Packages
-- : (NUMERIC_STD package body)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE DASC Synthesis Working Group,
-- : Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNRESOLVED_UNSIGNED: represents an UNSIGNED number
-- : in vector form
-- : -- > UNRESOLVED_SIGNED: represents a SIGNED number
-- : in vector form
-- : The base element type is type STD_ULOGIC.
-- : Aliases U_UNSIGNED and U_SIGNED are defined for the types
-- : UNRESOLVED_UNSIGNED and UNRESOLVED_SIGNED, respectively.
-- : Two numeric subtypes are defined:
-- : -- > UNSIGNED: represents UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The element subtypes are the same subtype as STD_LOGIC.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array
-- : is returned (exceptions, if any, are noted individually).
--
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
library nvc;
use nvc.sim_pkg.ieee_warnings;
package body NUMERIC_STD is
-- null range array constants
constant NAU : UNRESOLVED_UNSIGNED (0 downto 1) := (others => '0');
constant NAS : UNRESOLVED_SIGNED (0 downto 1) := (others => '0');
-- implementation controls
constant NO_WARNING : BOOLEAN := not ieee_warnings;
-- =========================Local Subprograms =================================
function SIGNED_NUM_BITS (ARG : INTEGER) return NATURAL is
variable NBITS : NATURAL;
variable N : NATURAL;
begin
if ARG >= 0 then
N := ARG;
else
N := -(ARG+1);
end if;
NBITS := 1;
while N > 0 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end function SIGNED_NUM_BITS;
function UNSIGNED_NUM_BITS (ARG : NATURAL) return NATURAL is
variable NBITS : NATURAL;
variable N : NATURAL;
begin
N := ARG;
NBITS := 1;
while N > 1 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end function UNSIGNED_NUM_BITS;
------------------------------------------------------------------------
-- this internal function computes the addition of two UNRESOLVED_UNSIGNED
-- with input CARRY
-- * the two arguments are of the same length
function ADD_UNSIGNED (L, R : UNRESOLVED_UNSIGNED; C : STD_LOGIC)
return UNRESOLVED_UNSIGNED
is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is R;
variable RESULT : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable CBIT : STD_LOGIC := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end function ADD_UNSIGNED;
-- this internal function computes the addition of two UNRESOLVED_SIGNED
-- with input CARRY
-- * the two arguments are of the same length
function ADD_SIGNED (L, R : UNRESOLVED_SIGNED; C : STD_LOGIC)
return UNRESOLVED_SIGNED
is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_SIGNED(L_LEFT downto 0) is R;
variable RESULT : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable CBIT : STD_LOGIC := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end function ADD_SIGNED;
-----------------------------------------------------------------------------
-- this internal procedure computes UNSIGNED division
-- giving the quotient and remainder.
procedure DIVMOD (NUM, XDENOM : UNRESOLVED_UNSIGNED;
XQUOT, XREMAIN : out UNRESOLVED_UNSIGNED) is
variable TEMP : UNRESOLVED_UNSIGNED(NUM'length downto 0);
variable QUOT : UNRESOLVED_UNSIGNED(MAXIMUM(NUM'length, XDENOM'length)-1
downto 0);
alias DENOM : UNRESOLVED_UNSIGNED(XDENOM'length-1 downto 0) is XDENOM;
variable TOPBIT : INTEGER;
begin
TEMP := "0"&NUM;
QUOT := (others => '0');
TOPBIT := -1;
for J in DENOM'range loop
if DENOM(J) = '1' then
TOPBIT := J;
exit;
end if;
end loop;
assert TOPBIT >= 0 report "NUMERIC_STD.DIVMOD: DIV, MOD, or REM by zero"
severity error;
for J in NUM'length-(TOPBIT+1) downto 0 loop
if TEMP(TOPBIT+J+1 downto J) >= "0"&DENOM(TOPBIT downto 0) then
TEMP(TOPBIT+J+1 downto J) := (TEMP(TOPBIT+J+1 downto J))
-("0"&DENOM(TOPBIT downto 0));
QUOT(J) := '1';
end if;
assert TEMP(TOPBIT+J+1) = '0'
report "NUMERIC_STD.DIVMOD: internal error in the division algorithm"
severity error;
end loop;
XQUOT := RESIZE(QUOT, XQUOT'length);
XREMAIN := RESIZE(TEMP, XREMAIN'length);
end procedure DIVMOD;
-----------------Local Subprograms - shift/rotate ops-------------------------
function XSLL (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR
is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L downto COUNT) := XARG(ARG_L-COUNT downto 0);
end if;
return RESULT;
end function XSLL;
function XSRL (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR
is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L-COUNT downto 0) := XARG(ARG_L downto COUNT);
end if;
return RESULT;
end function XSRL;
function XSRA (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR
is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0);
variable XCOUNT : NATURAL := COUNT;
begin
if ((ARG'length <= 1) or (XCOUNT = 0)) then return ARG;
else
if (XCOUNT > ARG_L) then XCOUNT := ARG_L;
end if;
RESULT(ARG_L-XCOUNT downto 0) := XARG(ARG_L downto XCOUNT);
RESULT(ARG_L downto (ARG_L - XCOUNT + 1)) := (others => XARG(ARG_L));
end if;
return RESULT;
end function XSRA;
function XROL (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR
is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM : INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L downto COUNTM) := XARG(ARG_L-COUNTM downto 0);
RESULT(COUNTM-1 downto 0) := XARG(ARG_L downto ARG_L-COUNTM+1);
end if;
return RESULT;
end function XROL;
function XROR (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR
is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM : INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L-COUNTM downto 0) := XARG(ARG_L downto COUNTM);
RESULT(ARG_L downto ARG_L-COUNTM+1) := XARG(COUNTM-1 downto 0);
end if;
return RESULT;
end function XROR;
-----------------Local Subprograms - Relational ops---------------------------
--
-- General "=" for UNRESOLVED_UNSIGNED vectors, same length
--
function UNSIGNED_EQUAL (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is
begin
return STD_ULOGIC_VECTOR(L) = STD_ULOGIC_VECTOR(R);
end function UNSIGNED_EQUAL;
--
-- General "=" for UNRESOLVED_SIGNED vectors, same length
--
function SIGNED_EQUAL (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
begin
return STD_ULOGIC_VECTOR(L) = STD_ULOGIC_VECTOR(R);
end function SIGNED_EQUAL;
--
-- General "<" for UNRESOLVED_UNSIGNED vectors, same length
--
function UNSIGNED_LESS (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is
begin
return STD_ULOGIC_VECTOR(L) < STD_ULOGIC_VECTOR(R);
end function UNSIGNED_LESS;
--
-- General "<" function for UNRESOLVED_SIGNED vectors, same length
--
function SIGNED_LESS (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
variable INTERN_L : UNRESOLVED_SIGNED(0 to L'length-1);
variable INTERN_R : UNRESOLVED_SIGNED(0 to R'length-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return STD_ULOGIC_VECTOR(INTERN_L) < STD_ULOGIC_VECTOR(INTERN_R);
end function SIGNED_LESS;
--
-- General "<=" function for UNRESOLVED_UNSIGNED vectors, same length
--
function UNSIGNED_LESS_OR_EQUAL (L, R : UNRESOLVED_UNSIGNED)
return BOOLEAN is
begin
return STD_ULOGIC_VECTOR(L) <= STD_ULOGIC_VECTOR(R);
end function UNSIGNED_LESS_OR_EQUAL;
--
-- General "<=" function for UNRESOLVED_SIGNED vectors, same length
--
function SIGNED_LESS_OR_EQUAL (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
-- Need aliases to assure index direction
variable INTERN_L : UNRESOLVED_SIGNED(0 to L'length-1);
variable INTERN_R : UNRESOLVED_SIGNED(0 to R'length-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return STD_ULOGIC_VECTOR(INTERN_L) <= STD_ULOGIC_VECTOR(INTERN_R);
end function SIGNED_LESS_OR_EQUAL;
-- =========================Exported Functions ==========================
-- Id: A.1
function "abs" (ARG : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNRESOLVED_SIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT : UNRESOLVED_SIGNED(ARG_LEFT downto 0);
begin
if ARG'length < 1 then return NAS;
end if;
RESULT := TO_01(XARG, 'X');
if (RESULT(RESULT'left) = 'X') then return RESULT;
end if;
if RESULT(RESULT'left) = '1' then
RESULT := -RESULT;
end if;
return RESULT;
end function "abs";
-- Id: A.2
function "-" (ARG : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant ARG_LEFT : INTEGER := ARG'length-1;
variable RESULT, XARG01 : UNRESOLVED_SIGNED(ARG_LEFT downto 0);
variable CBIT : STD_LOGIC := '1';
begin
if ARG'length < 1 then return NAS;
end if;
XARG01 := TO_01(ARG, 'X');
if (XARG01(XARG01'left) = 'X') then return XARG01;
end if;
for I in 0 to RESULT'left loop
RESULT(I) := not(XARG01(I)) xor CBIT;
CBIT := CBIT and not(XARG01(I));
end loop;
return RESULT;
end function "-";
-- ============================================================================
-- Id: A.3
function "+" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable R01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
return ADD_UNSIGNED(L01, R01, '0');
end function "+";
-- Id: A.3R
function "+" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC)
return UNRESOLVED_UNSIGNED
is
variable XR : UNRESOLVED_UNSIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L + XR);
end function "+";
-- Id: A.3L
function "+" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED
is
variable XL : UNRESOLVED_UNSIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL + R);
end function "+";
-- Id: A.4
function "+" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(SIZE-1 downto 0);
variable R01 : UNRESOLVED_SIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
return ADD_SIGNED(L01, R01, '0');
end function "+";
-- Id: A.4R
function "+" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC)
return UNRESOLVED_SIGNED
is
variable XR : UNRESOLVED_SIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L + XR);
end function "+";
-- Id: A.4L
function "+" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED
is
variable XL : UNRESOLVED_SIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL + R);
end function "+";
-- Id: A.5
function "+" (L : UNRESOLVED_UNSIGNED; R : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
return L + TO_UNSIGNED(R, L'length);
end function "+";
-- Id: A.6
function "+" (L : NATURAL; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return TO_UNSIGNED(L, R'length) + R;
end function "+";
-- Id: A.7
function "+" (L : UNRESOLVED_SIGNED; R : INTEGER)
return UNRESOLVED_SIGNED is
begin
return L + TO_SIGNED(R, L'length);
end function "+";
-- Id: A.8
function "+" (L : INTEGER; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return TO_SIGNED(L, R'length) + R;
end function "+";
-- ============================================================================
-- Id: A.9
function "-" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable R01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
return ADD_UNSIGNED(L01, not(R01), '1');
end function "-";
-- Id: A.9R
function "-" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC)
return UNRESOLVED_UNSIGNED
is
variable XR : UNRESOLVED_UNSIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L - XR);
end function "-";
-- Id: A.9L
function "-" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED
is
variable XL : UNRESOLVED_UNSIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL - R);
end function "-";
-- Id: A.10
function "-" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(SIZE-1 downto 0);
variable R01 : UNRESOLVED_SIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
return ADD_SIGNED(L01, not(R01), '1');
end function "-";
-- Id: A.10R
function "-" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC)
return UNRESOLVED_SIGNED
is
variable XR : UNRESOLVED_SIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L - XR);
end function "-";
-- Id: A.10L
function "-" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED
is
variable XL : UNRESOLVED_SIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL - R);
end function "-";
-- Id: A.11
function "-" (L : UNRESOLVED_UNSIGNED; R : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
return L - TO_UNSIGNED(R, L'length);
end function "-";
-- Id: A.12
function "-" (L : NATURAL; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return TO_UNSIGNED(L, R'length) - R;
end function "-";
-- Id: A.13
function "-" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is
begin
return L - TO_SIGNED(R, L'length);
end function "-";
-- Id: A.14
function "-" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
begin
return TO_SIGNED(L, R'length) - R;
end function "-";
-- ============================================================================
-- Id: A.15
function "*" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XXL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XXR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
variable RESULT : UNRESOLVED_UNSIGNED((L'length+R'length-1) downto 0) :=
(others => '0');
variable ADVAL : UNRESOLVED_UNSIGNED((L'length+R'length-1) downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then
RESULT := (others => 'X');
return RESULT;
end if;
ADVAL := RESIZE(XR, RESULT'length);
for I in 0 to L_LEFT loop
if XL(I) = '1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
return RESULT;
end function "*";
-- Id: A.16
function "*" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
variable XL : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable XR : UNRESOLVED_SIGNED(R_LEFT downto 0);
variable RESULT : UNRESOLVED_SIGNED((L_LEFT+R_LEFT+1) downto 0) :=
(others => '0');
variable ADVAL : UNRESOLVED_SIGNED((L_LEFT+R_LEFT+1) downto 0);
begin
if ((L_LEFT < 0) or (R_LEFT < 0)) then return NAS;
end if;
XL := TO_01(L, 'X');
XR := TO_01(R, 'X');
if ((XL(L_LEFT) = 'X') or (XR(R_LEFT) = 'X')) then
RESULT := (others => 'X');
return RESULT;
end if;
ADVAL := RESIZE(XR, RESULT'length);
for I in 0 to L_LEFT-1 loop
if XL(I) = '1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
if XL(L_LEFT) = '1' then
RESULT := RESULT - ADVAL;
end if;
return RESULT;
end function "*";
-- Id: A.17
function "*" (L : UNRESOLVED_UNSIGNED; R : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
return L * TO_UNSIGNED(R, L'length);
end function "*";
-- Id: A.18
function "*" (L : NATURAL; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return TO_UNSIGNED(L, R'length) * R;
end function "*";
-- Id: A.19
function "*" (L : UNRESOLVED_SIGNED; R : INTEGER)
return UNRESOLVED_SIGNED is
begin
return L * TO_SIGNED(R, L'length);
end function "*";
-- Id: A.20
function "*" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
begin
return TO_SIGNED(L, R'length) * R;
end function "*";
-- ============================================================================
-- Id: A.21
function "/" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XXL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XXR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then
FQUOT := (others => 'X');
return FQUOT;
end if;
DIVMOD(XL, XR, FQUOT, FREMAIN);
return FQUOT;
end function "/";
-- Id: A.22
function "/" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XXL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XXR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
variable XL : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable XR : UNRESOLVED_SIGNED(R_LEFT downto 0);
variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0);
variable XNUM : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
variable XDENOM : UNRESOLVED_UNSIGNED(R'length-1 downto 0);
variable QNEG : BOOLEAN := false;
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then
FQUOT := (others => 'X');
return UNRESOLVED_SIGNED(FQUOT);
end if;
if XL(XL'left) = '1' then
XNUM := UNRESOLVED_UNSIGNED(-XL);
QNEG := true;
else
XNUM := UNRESOLVED_UNSIGNED(XL);
end if;
if XR(XR'left) = '1' then
XDENOM := UNRESOLVED_UNSIGNED(-XR);
QNEG := not QNEG;
else
XDENOM := UNRESOLVED_UNSIGNED(XR);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if QNEG then FQUOT := "0"-FQUOT;
end if;
return UNRESOLVED_SIGNED(FQUOT);
end function "/";
-- Id: A.23
function "/" (L : UNRESOLVED_UNSIGNED; R : NATURAL)
return UNRESOLVED_UNSIGNED
is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R));
variable XR, QUOT : UNRESOLVED_UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAU;
end if;
if (R_LENGTH > L'length) then
QUOT := (others => '0');
return RESIZE(QUOT, L'length);
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'length);
return RESIZE(QUOT, L'length);
end function "/";
-- Id: A.24
function "/" (L : NATURAL; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED
is
constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length);
variable XL, QUOT : UNRESOLVED_UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'length);
if L_LENGTH > R'length and QUOT(0) /= 'X'
and QUOT(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => '0')
then
assert NO_WARNING report "NUMERIC_STD.""/"": Quotient Truncated"
severity warning;
end if;
return RESIZE(QUOT, R'length);
end function "/";
-- Id: A.25
function "/" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R));
variable XR, QUOT : UNRESOLVED_SIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAS;
end if;
if (R_LENGTH > L'length) then
QUOT := (others => '0');
return RESIZE(QUOT, L'length);
end if;
XR := TO_SIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'length);
return RESIZE(QUOT, L'length);
end function "/";
-- Id: A.26
function "/" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length);
variable XL, QUOT : UNRESOLVED_SIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'length);
if L_LENGTH > R'length and QUOT(0) /= 'X'
and QUOT(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => QUOT(R'length-1))
then
assert NO_WARNING report "NUMERIC_STD.""/"": Quotient Truncated"
severity warning;
end if;
return RESIZE(QUOT, R'length);
end function "/";
-- ============================================================================
-- Id: A.27
function "rem" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XXL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XXR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then
FREMAIN := (others => 'X');
return FREMAIN;
end if;
DIVMOD(XL, XR, FQUOT, FREMAIN);
return FREMAIN;
end function "rem";
-- Id: A.28
function "rem" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XXL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XXR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0);
variable XNUM : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
variable XDENOM : UNRESOLVED_UNSIGNED(R'length-1 downto 0);
variable RNEG : BOOLEAN := false;
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
XNUM := UNRESOLVED_UNSIGNED(TO_01(XXL, 'X'));
XDENOM := UNRESOLVED_UNSIGNED(TO_01(XXR, 'X'));
if ((XNUM(XNUM'left) = 'X') or (XDENOM(XDENOM'left) = 'X')) then
FREMAIN := (others => 'X');
return UNRESOLVED_SIGNED(FREMAIN);
end if;
if XNUM(XNUM'left) = '1' then
XNUM := UNRESOLVED_UNSIGNED(-UNRESOLVED_SIGNED(XNUM));
RNEG := true;
else
XNUM := UNRESOLVED_UNSIGNED(XNUM);
end if;
if XDENOM(XDENOM'left) = '1' then
XDENOM := UNRESOLVED_UNSIGNED(-UNRESOLVED_SIGNED(XDENOM));
else
XDENOM := UNRESOLVED_UNSIGNED(XDENOM);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG then
FREMAIN := "0"-FREMAIN;
end if;
return UNRESOLVED_SIGNED(FREMAIN);
end function "rem";
-- Id: A.29
function "rem" (L : UNRESOLVED_UNSIGNED; R : NATURAL)
return UNRESOLVED_UNSIGNED
is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R));
variable XR, XREM : UNRESOLVED_UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := L rem XR;
if R_LENGTH > L'length and XREM(0) /= 'X'
and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => '0')
then
assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "rem";
-- Id: A.30
function "rem" (L : NATURAL; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED
is
constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length);
variable XL, XREM : UNRESOLVED_UNSIGNED(L_LENGTH-1 downto 0);
begin
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := XL rem R;
if L_LENGTH > R'length and XREM(0) /= 'X'
and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => '0')
then
assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "rem";
-- Id: A.31
function "rem" (L : UNRESOLVED_SIGNED; R : INTEGER)
return UNRESOLVED_SIGNED
is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R));
variable XR, XREM : UNRESOLVED_SIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L rem XR), XREM'length);
if R_LENGTH > L'length and XREM(0) /= 'X'
and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => XREM(L'length-1))
then
assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "rem";
-- Id: A.32
function "rem" (L : INTEGER; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED
is
constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length);
variable XL, XREM : UNRESOLVED_SIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL rem R), XREM'length);
if L_LENGTH > R'length and XREM(0) /= 'X'
and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => XREM(R'length-1))
then
assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "rem";
-- ============================================================================
-- Id: A.33
function "mod" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XXL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XXR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then
FREMAIN := (others => 'X');
return FREMAIN;
end if;
DIVMOD(XL, XR, FQUOT, FREMAIN);
return FREMAIN;
end function "mod";
-- Id: A.34
function "mod" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XXL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XXR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
variable XL : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable XR : UNRESOLVED_SIGNED(R_LEFT downto 0);
variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0);
variable XNUM : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
variable XDENOM : UNRESOLVED_UNSIGNED(R'length-1 downto 0);
variable RNEG : BOOLEAN := false;
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then
FREMAIN := (others => 'X');
return UNRESOLVED_SIGNED(FREMAIN);
end if;
if XL(XL'left) = '1' then
XNUM := UNRESOLVED_UNSIGNED(-XL);
else
XNUM := UNRESOLVED_UNSIGNED(XL);
end if;
if XR(XR'left) = '1' then
XDENOM := UNRESOLVED_UNSIGNED(-XR);
RNEG := true;
else
XDENOM := UNRESOLVED_UNSIGNED(XR);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG and L(L'left) = '1' then
FREMAIN := "0"-FREMAIN;
elsif RNEG and FREMAIN /= "0" then
FREMAIN := FREMAIN-XDENOM;
elsif L(L'left) = '1' and FREMAIN /= "0" then
FREMAIN := XDENOM-FREMAIN;
end if;
return UNRESOLVED_SIGNED(FREMAIN);
end function "mod";
-- Id: A.35
function "mod" (L : UNRESOLVED_UNSIGNED; R : NATURAL)
return UNRESOLVED_UNSIGNED
is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R));
variable XR, XREM : UNRESOLVED_UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'length);
if R_LENGTH > L'length and XREM(0) /= 'X'
and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => '0')
then
assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "mod";
-- Id: A.36
function "mod" (L : NATURAL; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED
is
constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length);
variable XL, XREM : UNRESOLVED_UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'length);
if L_LENGTH > R'length and XREM(0) /= 'X'
and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => '0')
then
assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "mod";
-- Id: A.37
function "mod" (L : UNRESOLVED_SIGNED; R : INTEGER)
return UNRESOLVED_SIGNED
is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R));
variable XR, XREM : UNRESOLVED_SIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'length);
if R_LENGTH > L'length and XREM(0) /= 'X'
and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => XREM(L'length-1))
then
assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "mod";
-- Id: A.38
function "mod" (L : INTEGER; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED
is
constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length);
variable XL, XREM : UNRESOLVED_SIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'length);
if L_LENGTH > R'length and XREM(0) /= 'X'
and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => XREM(R'length-1))
then
assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "mod";
-- ============================================================================
-- Id: A.39
function find_leftmost (ARG : UNRESOLVED_UNSIGNED; Y : STD_ULOGIC)
return INTEGER is
begin
for INDEX in ARG'range loop
if ARG(INDEX) ?= Y then
return INDEX;
end if;
end loop;
return -1;
end function find_leftmost;
-- Id: A.40
function find_leftmost (ARG : UNRESOLVED_SIGNED; Y : STD_ULOGIC)
return INTEGER is
begin
for INDEX in ARG'range loop
if ARG(INDEX) ?= Y then
return INDEX;
end if;
end loop;
return -1;
end function find_leftmost;
-- Id: A.41
function find_rightmost (ARG : UNRESOLVED_UNSIGNED; Y : STD_ULOGIC)
return INTEGER is
begin
for INDEX in ARG'reverse_range loop
if ARG(INDEX) ?= Y then
return INDEX;
end if;
end loop;
return -1;
end function find_rightmost;
-- Id: A.42
function find_rightmost (ARG : UNRESOLVED_SIGNED; Y : STD_ULOGIC)
return INTEGER is
begin
for INDEX in ARG'reverse_range loop
if ARG(INDEX) ?= Y then
return INDEX;
end if;
end loop;
return -1;
end function find_rightmost;
-- ============================================================================
-- Id: C.1
function ">" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return not UNSIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function ">";
-- Id: C.2
function ">" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return not SIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function ">";
-- Id: C.3
function ">" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return true;
end if;
return not UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R01'length), R01);
end function ">";
-- Id: C.4
function ">" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L > 0;
end if;
return not SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R01'length), R01);
end function ">";
-- Id: C.5
function ">" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return false;
end if;
return not UNSIGNED_LESS_OR_EQUAL(L01, TO_UNSIGNED(R, L01'length));
end function ">";
-- Id: C.6
function ">" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 > R;
end if;
return not SIGNED_LESS_OR_EQUAL(L01, TO_SIGNED(R, L01'length));
end function ">";
-- ============================================================================
-- Id: C.7
function "<" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return UNSIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function "<";
-- Id: C.8
function "<" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return SIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function "<";
-- Id: C.9
function "<" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return UNSIGNED_LESS(TO_UNSIGNED(L, R01'length), R01);
end function "<";
-- Id: C.10
function "<" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return SIGNED_LESS(TO_SIGNED(L, R01'length), R01);
end function "<";
-- Id: C.11
function "<" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return UNSIGNED_LESS(L01, TO_UNSIGNED(R, L01'length));
end function "<";
-- Id: C.12
function "<" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return SIGNED_LESS(L01, TO_SIGNED(R, L01'length));
end function "<";
-- ============================================================================
-- Id: C.13
function "<=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return UNSIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function "<=";
-- Id: C.14
function "<=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return SIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function "<=";
-- Id: C.15
function "<=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R01'length), R01);
end function "<=";
-- Id: C.16
function "<=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R01'length), R01);
end function "<=";
-- Id: C.17
function "<=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
begin
if (L_LEFT < 0) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return UNSIGNED_LESS_OR_EQUAL(L01, TO_UNSIGNED(R, L01'length));
end function "<=";
-- Id: C.18
function "<=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
begin
if (L_LEFT < 0) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return SIGNED_LESS_OR_EQUAL(L01, TO_SIGNED(R, L01'length));
end function "<=";
-- ============================================================================
-- Id: C.19
function ">=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return not UNSIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function ">=";
-- Id: C.20
function ">=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return not SIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function ">=";
-- Id: C.21
function ">=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return L > 0;
end if;
return not UNSIGNED_LESS(TO_UNSIGNED(L, R01'length), R01);
end function ">=";
-- Id: C.22
function ">=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L > 0;
end if;
return not SIGNED_LESS(TO_SIGNED(L, R01'length), R01);
end function ">=";
-- Id: C.23
function ">=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return 0 > R;
end if;
return not UNSIGNED_LESS(L01, TO_UNSIGNED(R, L01'length));
end function ">=";
-- Id: C.24
function ">=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 > R;
end if;
return not SIGNED_LESS(L01, TO_SIGNED(R, L01'length));
end function ">=";
-- ============================================================================
-- Id: C.25
function "=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return UNSIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function "=";
-- Id: C.26
function "=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return SIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function "=";
-- Id: C.27
function "=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return false;
end if;
return UNSIGNED_EQUAL(TO_UNSIGNED(L, R01'length), R01);
end function "=";
-- Id: C.28
function "=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return false;
end if;
return SIGNED_EQUAL(TO_SIGNED(L, R01'length), R01);
end function "=";
-- Id: C.29
function "=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return false;
end if;
return UNSIGNED_EQUAL(L01, TO_UNSIGNED(R, L01'length));
end function "=";
-- Id: C.30
function "=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return false;
end if;
return SIGNED_EQUAL(L01, TO_SIGNED(R, L01'length));
end function "=";
-- ============================================================================
-- Id: C.31
function "/=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
return not(UNSIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)));
end function "/=";
-- Id: C.32
function "/=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
return not(SIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)));
end function "/=";
-- Id: C.33
function "/=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return true;
end if;
return not(UNSIGNED_EQUAL(TO_UNSIGNED(L, R01'length), R01));
end function "/=";
-- Id: C.34
function "/=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
if SIGNED_NUM_BITS(L) > R'length then return true;
end if;
return not(SIGNED_EQUAL(TO_SIGNED(L, R01'length), R01));
end function "/=";
-- Id: C.35
function "/=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return true;
end if;
return not(UNSIGNED_EQUAL(L01, TO_UNSIGNED(R, L01'length)));
end function "/=";
-- Id: C.36
function "/=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
if SIGNED_NUM_BITS(R) > L'length then return true;
end if;
return not(SIGNED_EQUAL(L01, TO_SIGNED(R, L01'length)));
end function "/=";
-- ============================================================================
-- Id: C.37
function MINIMUM (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable R01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
if UNSIGNED_LESS(L01, R01) then
return L01;
else
return R01;
end if;
end function MINIMUM;
-- Id: C.38
function MINIMUM (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(SIZE-1 downto 0);
variable R01 : UNRESOLVED_SIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
if SIGNED_LESS(L01, R01) then
return L01;
else
return R01;
end if;
end function MINIMUM;
-- Id: C.39
function MINIMUM (L : NATURAL; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return MINIMUM(TO_UNSIGNED(L, R'length), R);
end function MINIMUM;
-- Id: C.40
function MINIMUM (L : INTEGER; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return MINIMUM(TO_SIGNED(L, R'length), R);
end function MINIMUM;
-- Id: C.41
function MINIMUM (L : UNRESOLVED_UNSIGNED; R : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
return MINIMUM(L, TO_UNSIGNED(R, L'length));
end function MINIMUM;
-- Id: C.42
function MINIMUM (L : UNRESOLVED_SIGNED; R : INTEGER)
return UNRESOLVED_SIGNED is
begin
return MINIMUM(L, TO_SIGNED(R, L'length));
end function MINIMUM;
-- ============================================================================
-- Id: C.43
function MAXIMUM (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable R01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
if UNSIGNED_LESS(L01, R01) then
return R01;
else
return L01;
end if;
end function MAXIMUM;
-- Id: C.44
function MAXIMUM (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(SIZE-1 downto 0);
variable R01 : UNRESOLVED_SIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
if SIGNED_LESS(L01, R01) then
return R01;
else
return L01;
end if;
end function MAXIMUM;
-- Id: C.45
function MAXIMUM (L : NATURAL; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return MAXIMUM(TO_UNSIGNED(L, R'length), R);
end function MAXIMUM;
-- Id: C.46
function MAXIMUM (L : INTEGER; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return MAXIMUM(TO_SIGNED(L, R'length), R);
end function MAXIMUM;
-- Id: C.47
function MAXIMUM (L : UNRESOLVED_UNSIGNED; R : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
return MAXIMUM(L, TO_UNSIGNED(R, L'length));
end function MAXIMUM;
-- Id: C.48
function MAXIMUM (L : UNRESOLVED_SIGNED; R : INTEGER)
return UNRESOLVED_SIGNED is
begin
return MAXIMUM(L, TO_SIGNED(R, L'length));
end function MAXIMUM;
-- ============================================================================
-- Id: C.49
function "?>" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if IS_X(L) or IS_X(R) then
return 'X';
elsif L > R then
return '1';
else
return '0';
end if;
end if;
end function "?>";
-- Id: C.50
function "?>" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if IS_X(L) or IS_X(R) then
return 'X';
elsif L > R then
return '1';
else
return '0';
end if;
end if;
end function "?>";
-- Id: C.51
function "?>" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return TO_UNSIGNED(L, R'length) ?> R;
end function "?>";
-- Id: C.52
function "?>" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return TO_SIGNED(L, R'length) ?> R;
end function "?>";
-- Id: C.53
function "?>" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return L ?> TO_UNSIGNED(R, L'length);
end function "?>";
-- Id: C.54
function "?>" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return L ?> TO_SIGNED(R, L'length);
end function "?>";
-- ============================================================================
-- Id: C.55
function "?<" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if IS_X(L) or IS_X(R) then
return 'X';
elsif L < R then
return '1';
else
return '0';
end if;
end if;
end function "?<";
-- Id: C.56
function "?<" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if IS_X(L) or IS_X(R) then
return 'X';
elsif L < R then
return '1';
else
return '0';
end if;
end if;
end function "?<";
-- Id: C.57
function "?<" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return TO_UNSIGNED(L, R'length) ?< R;
end function "?<";
-- Id: C.58
function "?<" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return TO_SIGNED(L, R'length) ?< R;
end function "?<";
-- Id: C.59
function "?<" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return L ?< TO_UNSIGNED(R, L'length);
end function "?<";
-- Id: C.60
function "?<" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return L ?< TO_SIGNED(R, L'length);
end function "?<";
-- ============================================================================
-- Id: C.61
function "?<=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if IS_X(L) or IS_X(R) then
return 'X';
elsif L <= R then
return '1';
else
return '0';
end if;
end if;
end function "?<=";
-- Id: C.62
function "?<=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if IS_X(L) or IS_X(R) then
return 'X';
elsif L <= R then
return '1';
else
return '0';
end if;
end if;
end function "?<=";
-- Id: C.63
function "?<=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return TO_UNSIGNED(L, R'length) ?<= R;
end function "?<=";
-- Id: C.64
function "?<=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return TO_SIGNED(L, R'length) ?<= R;
end function "?<=";
-- Id: C.65
function "?<=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return L ?<= TO_UNSIGNED(R, L'length);
end function "?<=";
-- Id: C.66
function "?<=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return L ?<= TO_SIGNED(R, L'length);
end function "?<=";
-- ============================================================================
-- Id: C.67
function "?>=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if IS_X(L) or IS_X(R) then
return 'X';
elsif L >= R then
return '1';
else
return '0';
end if;
end if;
end function "?>=";
-- Id: C.68
function "?>=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if IS_X(L) or IS_X(R) then
return 'X';
elsif L >= R then
return '1';
else
return '0';
end if;
end if;
end function "?>=";
-- Id: C.69
function "?>=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return TO_UNSIGNED(L, R'length) ?>= R;
end function "?>=";
-- Id: C.70
function "?>=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return TO_SIGNED(L, R'length) ?>= R;
end function "?>=";
-- Id: C.71
function "?>=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return L ?>= TO_UNSIGNED(R, L'length);
end function "?>=";
-- Id: C.72
function "?>=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return L ?>= TO_SIGNED(R, L'length);
end function "?>=";
-- ============================================================================
-- Id: C.73
function "?=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable LX : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable RX : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin
-- Logically identical to an "=" operator.
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '1';
for i in LX'low to LX'high loop
result1 := LX(i) ?= RX(i);
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function "?=";
-- Id: C.74
function "?=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable LX : UNRESOLVED_SIGNED(SIZE-1 downto 0);
variable RX : UNRESOLVED_SIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '1';
for i in LX'low to LX'high loop
result1 := LX(i) ?= RX(i);
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function "?=";
-- Id: C.75
function "?=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return TO_UNSIGNED(L, R'length) ?= R;
end function "?=";
-- Id: C.76
function "?=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return TO_SIGNED(L, R'length) ?= R;
end function "?=";
-- Id: C.77
function "?=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return L ?= TO_UNSIGNED(R, L'length);
end function "?=";
-- Id: C.78
function "?=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return L ?= TO_SIGNED(R, L'length);
end function "?=";
-- ============================================================================
-- Id: C.79
function "?/=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable LX : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable RX : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?/="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '0';
for i in LX'low to LX'high loop
result1 := LX(i) ?/= RX(i);
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function "?/=";
-- Id: C.80
function "?/=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable LX : UNRESOLVED_SIGNED(SIZE-1 downto 0);
variable RX : UNRESOLVED_SIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?/="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '0';
for i in LX'low to LX'high loop
result1 := LX(i) ?/= RX(i);
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function "?/=";
-- Id: C.81
function "?/=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return TO_UNSIGNED(L, R'length) ?/= R;
end function "?/=";
-- Id: C.82
function "?/=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return TO_SIGNED(L, R'length) ?/= R;
end function "?/=";
-- Id: C.83
function "?/=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return L ?/= TO_UNSIGNED(R, L'length);
end function "?/=";
-- Id: C.84
function "?/=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return L ?/= TO_SIGNED(R, L'length);
end function "?/=";
-- ============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
if (ARG'length < 1) then return NAU;
end if;
return UNRESOLVED_UNSIGNED(XSLL(STD_ULOGIC_VECTOR(ARG), COUNT));
end function SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
if (ARG'length < 1) then return NAU;
end if;
return UNRESOLVED_UNSIGNED(XSRL(STD_ULOGIC_VECTOR(ARG), COUNT));
end function SHIFT_RIGHT;
-- Id: S.3
function SHIFT_LEFT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL)
return UNRESOLVED_SIGNED is
begin
if (ARG'length < 1) then return NAS;
end if;
return UNRESOLVED_SIGNED(XSLL(STD_ULOGIC_VECTOR(ARG), COUNT));
end function SHIFT_LEFT;
-- Id: S.4
function SHIFT_RIGHT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL)
return UNRESOLVED_SIGNED is
begin
if (ARG'length < 1) then return NAS;
end if;
return UNRESOLVED_SIGNED(XSRA(STD_ULOGIC_VECTOR(ARG), COUNT));
end function SHIFT_RIGHT;
-- ============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
if (ARG'length < 1) then return NAU;
end if;
return UNRESOLVED_UNSIGNED(XROL(STD_ULOGIC_VECTOR(ARG), COUNT));
end function ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
if (ARG'length < 1) then return NAU;
end if;
return UNRESOLVED_UNSIGNED(XROR(STD_ULOGIC_VECTOR(ARG), COUNT));
end function ROTATE_RIGHT;
-- Id: S.7
function ROTATE_LEFT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL)
return UNRESOLVED_SIGNED is
begin
if (ARG'length < 1) then return NAS;
end if;
return UNRESOLVED_SIGNED(XROL(STD_ULOGIC_VECTOR(ARG), COUNT));
end function ROTATE_LEFT;
-- Id: S.8
function ROTATE_RIGHT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL)
return UNRESOLVED_SIGNED is
begin
if (ARG'length < 1) then return NAS;
end if;
return UNRESOLVED_SIGNED(XROR(STD_ULOGIC_VECTOR(ARG), COUNT));
end function ROTATE_RIGHT;
-- ============================================================================
------------------------------------------------------------------------------
-- Note: Function S.9 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER)
return UNRESOLVED_UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sll";
------------------------------------------------------------------------------
-- Note: Function S.10 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER)
return UNRESOLVED_SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return UNRESOLVED_SIGNED(SHIFT_RIGHT(UNRESOLVED_UNSIGNED(ARG), -COUNT));
end if;
end function "sll";
------------------------------------------------------------------------------
-- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER)
return UNRESOLVED_UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "srl";
------------------------------------------------------------------------------
-- Note: Function S.12 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER)
return UNRESOLVED_SIGNED is
begin
if (COUNT >= 0) then
return UNRESOLVED_SIGNED(SHIFT_RIGHT(UNRESOLVED_UNSIGNED(ARG), COUNT));
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "srl";
------------------------------------------------------------------------------
-- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER)
return UNRESOLVED_UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end function "rol";
------------------------------------------------------------------------------
-- Note: Function S.14 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER)
return UNRESOLVED_SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end function "rol";
------------------------------------------------------------------------------
-- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER)
return UNRESOLVED_UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end function "ror";
------------------------------------------------------------------------------
-- Note: Function S.16 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER)
return UNRESOLVED_SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end function "ror";
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER)
return UNRESOLVED_UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sla";
------------------------------------------------------------------------------
-- Note: Function S.18 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.18
function "sla" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER)
return UNRESOLVED_SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sla";
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER)
return UNRESOLVED_UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "sra";
------------------------------------------------------------------------------
-- Note: Function S.20 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.20
function "sra" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER)
return UNRESOLVED_SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "sra";
-- ============================================================================
-- Id: D.1
function TO_INTEGER (ARG : UNRESOLVED_UNSIGNED) return NATURAL is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XXARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0) is ARG;
variable XARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0);
variable RESULT : NATURAL := 0;
begin
if (ARG'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: null detected, returning 0"
severity warning;
return 0;
end if;
XARG := TO_01(XXARG, 'X');
if (XARG(XARG'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0"
severity warning;
return 0;
end if;
for I in XARG'range loop
RESULT := RESULT+RESULT;
if XARG(I) = '1' then
RESULT := RESULT + 1;
end if;
end loop;
return RESULT;
end function TO_INTEGER;
-- Id: D.2
function TO_INTEGER (ARG : UNRESOLVED_SIGNED) return INTEGER is
variable XARG : UNRESOLVED_SIGNED(ARG'length-1 downto 0);
begin
if (ARG'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: null detected, returning 0"
severity warning;
return 0;
end if;
XARG := TO_01(ARG, 'X');
if (XARG(XARG'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0"
severity warning;
return 0;
end if;
if XARG(XARG'left) = '0' then
return TO_INTEGER(UNRESOLVED_UNSIGNED(XARG));
else
return (- (TO_INTEGER(UNRESOLVED_UNSIGNED(- (XARG + 1)))) -1);
end if;
end function TO_INTEGER;
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNRESOLVED_UNSIGNED is
variable RESULT : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable I_VAL : NATURAL := ARG;
begin
if (SIZE < 1) then return NAU;
end if;
for I in 0 to RESULT'left loop
if (I_VAL mod 2) = 0 then
RESULT(I) := '0';
else RESULT(I) := '1';
end if;
I_VAL := I_VAL/2;
end loop;
if not(I_VAL = 0) then
assert NO_WARNING
report "NUMERIC_STD.TO_UNSIGNED: vector truncated"
severity warning;
end if;
return RESULT;
end function TO_UNSIGNED;
-- Id: D.4
function TO_SIGNED (ARG : INTEGER; SIZE : NATURAL) return UNRESOLVED_SIGNED is
variable RESULT : UNRESOLVED_SIGNED(SIZE-1 downto 0);
variable B_VAL : STD_LOGIC := '0';
variable I_VAL : INTEGER := ARG;
begin
if (SIZE < 1) then return NAS;
end if;
if (ARG < 0) then
B_VAL := '1';
I_VAL := -(ARG+1);
end if;
for I in 0 to RESULT'left loop
if (I_VAL mod 2) = 0 then
RESULT(I) := B_VAL;
else
RESULT(I) := not B_VAL;
end if;
I_VAL := I_VAL/2;
end loop;
if ((I_VAL /= 0) or (B_VAL /= RESULT(RESULT'left))) then
assert NO_WARNING
report "NUMERIC_STD.TO_SIGNED: vector truncated"
severity warning;
end if;
return RESULT;
end function TO_SIGNED;
function TO_UNSIGNED (ARG : NATURAL; SIZE_RES : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return TO_UNSIGNED (ARG => ARG,
SIZE => SIZE_RES'length);
end function TO_UNSIGNED;
function TO_SIGNED (ARG : INTEGER; SIZE_RES : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return TO_SIGNED (ARG => ARG,
SIZE => SIZE_RES'length);
end function TO_SIGNED;
-- ============================================================================
-- Id: R.1
function RESIZE (ARG : UNRESOLVED_SIGNED; NEW_SIZE : NATURAL)
return UNRESOLVED_SIGNED
is
alias INVEC : UNRESOLVED_SIGNED(ARG'length-1 downto 0) is ARG;
variable RESULT : UNRESOLVED_SIGNED(NEW_SIZE-1 downto 0) :=
(others => '0');
constant BOUND : INTEGER := MINIMUM(ARG'length, RESULT'length)-2;
begin
if (NEW_SIZE < 1) then return NAS;
end if;
if (ARG'length = 0) then return RESULT;
end if;
RESULT := (others => ARG(ARG'left));
if BOUND >= 0 then
RESULT(BOUND downto 0) := INVEC(BOUND downto 0);
end if;
return RESULT;
end function RESIZE;
-- Id: R.2
function RESIZE (ARG : UNRESOLVED_UNSIGNED; NEW_SIZE : NATURAL)
return UNRESOLVED_UNSIGNED
is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT : UNRESOLVED_UNSIGNED(NEW_SIZE-1 downto 0) :=
(others => '0');
begin
if (NEW_SIZE < 1) then return NAU;
end if;
if XARG'length = 0 then return RESULT;
end if;
if (RESULT'length < ARG'length) then
RESULT(RESULT'left downto 0) := XARG(RESULT'left downto 0);
else
RESULT(RESULT'left downto XARG'left+1) := (others => '0');
RESULT(XARG'left downto 0) := XARG;
end if;
return RESULT;
end function RESIZE;
function RESIZE (ARG, SIZE_RES : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return RESIZE (ARG => ARG,
NEW_SIZE => SIZE_RES'length);
end function RESIZE;
function RESIZE (ARG, SIZE_RES : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return RESIZE (ARG => ARG,
NEW_SIZE => SIZE_RES'length);
end function RESIZE;
-- ============================================================================
-- Id: L.1
function "not" (L : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_UNSIGNED(not(STD_ULOGIC_VECTOR(L)));
return RESULT;
end function "not";
-- Id: L.2
function "and" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) and
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "and";
-- Id: L.3
function "or" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) or
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "or";
-- Id: L.4
function "nand" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) nand
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "nand";
-- Id: L.5
function "nor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) nor
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "nor";
-- Id: L.6
function "xor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) xor
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.7 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) xnor
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "xnor";
-- Id: L.8
function "not" (L : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_SIGNED(not(STD_ULOGIC_VECTOR(L)));
return RESULT;
end function "not";
-- Id: L.9
function "and" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) and STD_ULOGIC_VECTOR(R));
return RESULT;
end function "and";
-- Id: L.10
function "or" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) or STD_ULOGIC_VECTOR(R));
return RESULT;
end function "or";
-- Id: L.11
function "nand" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) nand
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "nand";
-- Id: L.12
function "nor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) nor STD_ULOGIC_VECTOR(R));
return RESULT;
end function "nor";
-- Id: L.13
function "xor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) xor STD_ULOGIC_VECTOR(R));
return RESULT;
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.14 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) xnor
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "xnor";
-- Id: L.15
function "and" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (L and STD_ULOGIC_VECTOR(R));
end function "and";
-- Id: L.16
function "and" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) and R);
end function "and";
-- Id: L.17
function "or" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (L or STD_ULOGIC_VECTOR(R));
end function "or";
-- Id: L.18
function "or" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) or R);
end function "or";
-- Id: L.19
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (L nand STD_ULOGIC_VECTOR(R));
end function "nand";
-- Id: L.20
function "nand" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) nand R);
end function "nand";
-- Id: L.21
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (L nor STD_ULOGIC_VECTOR(R));
end function "nor";
-- Id: L.22
function "nor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) nor R);
end function "nor";
-- Id: L.23
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (L xor STD_ULOGIC_VECTOR(R));
end function "xor";
-- Id: L.24
function "xor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) xor R);
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.25 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.25
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (L xnor STD_ULOGIC_VECTOR(R));
end function "xnor";
------------------------------------------------------------------------------
-- Note: Function L.26 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.26
function "xnor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) xnor R);
end function "xnor";
-- Id: L.27
function "and" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (L and STD_ULOGIC_VECTOR(R));
end function "and";
-- Id: L.28
function "and" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) and R);
end function "and";
-- Id: L.29
function "or" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (L or STD_ULOGIC_VECTOR(R));
end function "or";
-- Id: L.30
function "or" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) or R);
end function "or";
-- Id: L.31
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (L nand STD_ULOGIC_VECTOR(R));
end function "nand";
-- Id: L.32
function "nand" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) nand R);
end function "nand";
-- Id: L.33
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (L nor STD_ULOGIC_VECTOR(R));
end function "nor";
-- Id: L.34
function "nor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) nor R);
end function "nor";
-- Id: L.35
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (L xor STD_ULOGIC_VECTOR(R));
end function "xor";
-- Id: L.36
function "xor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) xor R);
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.37 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.37
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (L xnor STD_ULOGIC_VECTOR(R));
end function "xnor";
------------------------------------------------------------------------------
-- Note: Function L.38 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.38
function "xnor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) xnor R);
end function "xnor";
------------------------------------------------------------------------------
-- Note: Function L.39 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.39
function "and" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return and (STD_ULOGIC_VECTOR (L));
end function "and";
------------------------------------------------------------------------------
-- Note: Function L.40 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.40
function "and" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return and (STD_ULOGIC_VECTOR (L));
end function "and";
------------------------------------------------------------------------------
-- Note: Function L.41 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.41
function "nand" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return nand (STD_ULOGIC_VECTOR (L));
end function "nand";
------------------------------------------------------------------------------
-- Note: Function L.42 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.42
function "nand" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return nand (STD_ULOGIC_VECTOR (L));
end function "nand";
------------------------------------------------------------------------------
-- Note: Function L.43 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.43
function "or" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return or (STD_ULOGIC_VECTOR (L));
end function "or";
------------------------------------------------------------------------------
-- Note: Function L.44 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.44
function "or" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return or (STD_ULOGIC_VECTOR (L));
end function "or";
------------------------------------------------------------------------------
-- Note: Function L.45 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.45
function "nor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return nor (STD_ULOGIC_VECTOR (L));
end function "nor";
------------------------------------------------------------------------------
-- Note: Function L.46 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.46
function "nor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return nor (STD_ULOGIC_VECTOR (L));
end function "nor";
------------------------------------------------------------------------------
-- Note: Function L.47 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.47
function "xor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return xor (STD_ULOGIC_VECTOR (L));
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.48 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.48
function "xor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return xor (STD_ULOGIC_VECTOR (L));
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.49 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.49
function "xnor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return xnor (STD_ULOGIC_VECTOR (L));
end function "xnor";
------------------------------------------------------------------------------
-- Note: Function L.50 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.50
function "xnor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return xnor (STD_ULOGIC_VECTOR (L));
end function "xnor";
-- ============================================================================
-- support constants for STD_MATCH:
type BOOLEAN_TABLE is array(STD_ULOGIC, STD_ULOGIC) of BOOLEAN;
constant MATCH_TABLE : BOOLEAN_TABLE := (
--------------------------------------------------------------------------
-- U X 0 1 Z W L H -
--------------------------------------------------------------------------
(false, false, false, false, false, false, false, false, true), -- | U |
(false, false, false, false, false, false, false, false, true), -- | X |
(false, false, true, false, false, false, true, false, true), -- | 0 |
(false, false, false, true, false, false, false, true, true), -- | 1 |
(false, false, false, false, false, false, false, false, true), -- | Z |
(false, false, false, false, false, false, false, false, true), -- | W |
(false, false, true, false, false, false, true, false, true), -- | L |
(false, false, false, true, false, false, false, true, true), -- | H |
(true, true, true, true, true, true, true, true, true) -- | - |
);
-- Id: M.1
function STD_MATCH (L, R : STD_ULOGIC) return BOOLEAN is
begin
return MATCH_TABLE(L, R);
end function STD_MATCH;
-- Id: M.2
function STD_MATCH (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is
alias LV : UNRESOLVED_UNSIGNED(1 to L'length) is L;
alias RV : UNRESOLVED_UNSIGNED(1 to R'length) is R;
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE"
severity warning;
return false;
end if;
if LV'length /= RV'length then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE"
severity warning;
return false;
else
for I in LV'low to LV'high loop
if not (MATCH_TABLE(LV(I), RV(I))) then
return false;
end if;
end loop;
return true;
end if;
end function STD_MATCH;
-- Id: M.3
function STD_MATCH (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
alias LV : UNRESOLVED_SIGNED(1 to L'length) is L;
alias RV : UNRESOLVED_SIGNED(1 to R'length) is R;
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE"
severity warning;
return false;
end if;
if LV'length /= RV'length then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE"
severity warning;
return false;
else
for I in LV'low to LV'high loop
if not (MATCH_TABLE(LV(I), RV(I))) then
return false;
end if;
end loop;
return true;
end if;
end function STD_MATCH;
-- Id: M.5
function STD_MATCH (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
alias LV : STD_ULOGIC_VECTOR(1 to L'length) is L;
alias RV : STD_ULOGIC_VECTOR(1 to R'length) is R;
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE"
severity warning;
return false;
end if;
if LV'length /= RV'length then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE"
severity warning;
return false;
else
for I in LV'low to LV'high loop
if not (MATCH_TABLE(LV(I), RV(I))) then
return false;
end if;
end loop;
return true;
end if;
end function STD_MATCH;
-- ============================================================================
-- function TO_01 is used to convert vectors to the
-- correct form for exported functions,
-- and to report if there is an element which
-- is not in (0, 1, H, L).
-- Id: T.1
function TO_01 (S : UNRESOLVED_UNSIGNED; XMAP : STD_ULOGIC := '0')
return UNRESOLVED_UNSIGNED is
begin
if (S'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.TO_01: null detected, returning NAU"
severity warning;
return NAU;
end if;
return UNRESOLVED_UNSIGNED(TO_01(STD_ULOGIC_VECTOR(S), XMAP));
end function TO_01;
-- Id: T.2
function TO_01 (S : UNRESOLVED_SIGNED; XMAP : STD_ULOGIC := '0')
return UNRESOLVED_SIGNED is
begin
if (S'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.TO_01: null detected, returning NAS"
severity warning;
return NAS;
end if;
return UNRESOLVED_SIGNED(TO_01(STD_ULOGIC_VECTOR(S), XMAP));
end function TO_01;
-- Id: T.3
function TO_X01 (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED(TO_X01(STD_ULOGIC_VECTOR(S)));
end function TO_X01;
-- Id: T.4
function TO_X01 (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED(TO_X01(STD_ULOGIC_VECTOR(S)));
end function TO_X01;
-- Id: T.5
function TO_X01Z (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED(TO_X01Z(STD_ULOGIC_VECTOR(S)));
end function TO_X01Z;
-- Id: T.6
function TO_X01Z (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED(TO_X01Z(STD_ULOGIC_VECTOR(S)));
end function TO_X01Z;
-- Id: T.7
function TO_UX01 (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED(TO_UX01(STD_ULOGIC_VECTOR(S)));
end function TO_UX01;
-- Id: T.8
function TO_UX01 (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED(TO_UX01(STD_ULOGIC_VECTOR(S)));
end function TO_UX01;
-- Id: T.9
function IS_X (S : UNRESOLVED_UNSIGNED) return BOOLEAN is
begin
return IS_X(STD_ULOGIC_VECTOR(S));
end function IS_X;
-- Id: T.10
function IS_X (S : UNRESOLVED_SIGNED) return BOOLEAN is
begin
return IS_X(STD_ULOGIC_VECTOR(S));
end function IS_X;
-- ============================================================================
-- string conversion and write operations
-- ============================================================================
function TO_OSTRING (value : UNRESOLVED_UNSIGNED) return STRING is
begin
return TO_OSTRING(STD_ULOGIC_VECTOR (value));
end function TO_OSTRING;
function TO_OSTRING (value : UNRESOLVED_SIGNED) return STRING is
constant result_length : INTEGER := (value'length+2)/3;
constant pad : STD_ULOGIC_VECTOR(1 to (result_length*3 -
value'length))
:= (others => value (value'left)); -- Extend sign bit
begin
return TO_OSTRING(pad & STD_ULOGIC_VECTOR (value));
end function TO_OSTRING;
function to_hstring (value : UNRESOLVED_UNSIGNED) return STRING is
begin
return to_hstring(STD_ULOGIC_VECTOR (value));
end function to_hstring;
function to_hstring (value : UNRESOLVED_SIGNED) return STRING is
constant result_length : INTEGER := (value'length+3)/4;
constant pad : STD_ULOGIC_VECTOR(1 to (result_length*4 -
value'length))
:= (others => value (value'left)); -- Extend sign bit
begin
return to_hstring(pad & STD_ULOGIC_VECTOR (value));
end function to_hstring;
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
READ (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
READ (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_SIGNED;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
READ (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := SIGNED(ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_SIGNED) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
READ (L => L,
VALUE => ivalue);
VALUE := SIGNED (ivalue);
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
ivalue := STD_ULOGIC_VECTOR (VALUE);
WRITE (L => L,
VALUE => ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure WRITE;
procedure WRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
ivalue := STD_ULOGIC_VECTOR (VALUE);
WRITE (L => L,
VALUE => ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure WRITE;
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
OREAD (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED;
GOOD : out BOOLEAN) is
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3-1);
variable ok : BOOLEAN;
variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);
begin
OREAD (L => L,
VALUE => ivalue, -- Read padded STRING
GOOD => ok);
-- Bail out if there was a bad read
if not ok then
GOOD := false;
return;
end if;
expected_padding := (others => ivalue(pad));
if ivalue(0 to pad-1) /= expected_padding then
GOOD := false;
else
GOOD := true;
VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
OREAD (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED) is
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3-1);
variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);
begin
OREAD (L => L,
VALUE => ivalue); -- Read padded string
expected_padding := (others => ivalue(pad));
if ivalue(0 to pad-1) /= expected_padding then
assert false
report "NUMERIC_STD.OREAD Error: Signed vector truncated"
severity error;
else
VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));
end if;
end procedure OREAD;
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
HREAD (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED;
GOOD : out BOOLEAN) is
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4-1);
variable ok : BOOLEAN;
variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);
begin
HREAD (L => L,
VALUE => ivalue, -- Read padded STRING
GOOD => ok);
if not ok then
GOOD := false;
return;
end if;
expected_padding := (others => ivalue(pad));
if ivalue(0 to pad-1) /= expected_padding then
GOOD := false;
else
GOOD := true;
VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
HREAD (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED) is
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4-1);
variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);
begin
HREAD (L => L,
VALUE => ivalue); -- Read padded string
expected_padding := (others => ivalue(pad));
if ivalue(0 to pad-1) /= expected_padding then
assert false
report "NUMERIC_STD.HREAD Error: Signed vector truncated"
severity error;
else
VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));
end if;
end procedure HREAD;
procedure OWRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
ivalue := STD_ULOGIC_VECTOR (VALUE);
OWRITE (L => L,
VALUE => ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure OWRITE;
procedure OWRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : STD_ULOGIC_VECTOR(0 to (ne*3 - VALUE'length) - 1)
:= (others => VALUE (VALUE'left));
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
ivalue := STD_ULOGIC_VECTOR (VALUE);
OWRITE (L => L,
VALUE => pad & ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure OWRITE;
procedure HWRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
ivalue := STD_ULOGIC_VECTOR (VALUE);
HWRITE (L => L,
VALUE => ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure HWRITE;
procedure HWRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : STD_ULOGIC_VECTOR(0 to (ne*4 - VALUE'length) - 1)
:= (others => VALUE(VALUE'left));
begin
ivalue := STD_ULOGIC_VECTOR (VALUE);
HWRITE (L => L,
VALUE => pad & ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure HWRITE;
end package body NUMERIC_STD;
| gpl-3.0 | ce2e3d4fb8e9b30640c98182f1c694b1 | 0.569176 | 3.852476 | false | false | false | false |
nickg/nvc | test/parse/literal.vhd | 1 | 1,277 | -- -*- coding: latin-1 -*-
entity ee is
end entity;
ARCHITECTURE aa OF ee IS
SIGNAL pos : INTEGER := 64;
SIGNAL neg : INTEGER := -265;
CONSTANT c : INTEGER := 523;
CONSTANT a : STRING := "hel""lo";
CONSTANT b : STRING := """quote""";
CONSTANT d : INTEGER := 1E3; -- Integer not real
CONSTANT e : REAL := 1.234;
CONSTANT f : REAL := 0.21712;
CONSTANT g : REAL := 1.4e6;
CONSTANT h : REAL := 235.1e-2;
CONSTANT i : INTEGER := 1_2_3_4;
CONSTANT j : REAL := 5_6_7.12_3;
type ptr is access integer;
shared variable k : ptr := NULL;
CONSTANT l : STRING := "Setup time is too short";
CONSTANT m : STRING := "";
CONSTANT n : STRING := " ";
CONSTANT o : STRING := "A";
CONSTANT p : STRING := """";
CONSTANT q : STRING := %Setup time is too short%;
CONSTANT r : STRING := %%;
CONSTANT s : STRING := % %;
CONSTANT t : STRING := %A%;
CONSTANT u : STRING := %%%%;
constant v : string := "©";
subtype lowercase is character range 'a' to 'z';
type my_string is array (lowercase range <>) of character;
constant w : my_string := "hello";
constant too_big : integer := 9223372036854775808; -- Error
constant way_too_big : integer := 235423414124e124124; -- Error
BEGIN
END ARCHITECTURE;
| gpl-3.0 | 11fd3007f162b2aa8e0a3c5c78e58120 | 0.591229 | 3.351706 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_17.vhd | 3 | 2,593 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_17.vhd,v 1.5 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.5 $
--
-- ---------------------------------------------------------------------
entity fg_05_17 is
end entity fg_05_17;
library stimulus;
architecture test of fg_05_17 is
use stimulus.stimulus_generators.all;
signal sel0, sel1, d0, d1, d2, d3 : bit := '0';
signal functional_z, equivalent_z : bit;
begin
functional_mux : block is
port ( z : out bit );
port map ( z => functional_z );
begin
-- code from book
zmux : z <= d0 when sel1 = '0' and sel0 = '0' else
d1 when sel1 = '0' and sel0 = '1' else
d2 when sel1 = '1' and sel0 = '0' else
d3 when sel1 = '1' and sel0 = '1';
-- end code from book
end block functional_mux;
equivalent_mux : block is
port ( z : out bit );
port map ( z => equivalent_z );
begin
-- code from book
zmux : process is
begin
if sel1 = '0' and sel0 = '0' then
z <= d0;
elsif sel1 = '0' and sel0 = '1' then
z <= d1;
elsif sel1 = '1' and sel0 = '0' then
z <= d2;
elsif sel1 = '1' and sel0 = '1' then
z <= d3;
end if;
wait on d0, d1, d2, d3, sel0, sel1;
end process zmux;
-- end code from book
end block equivalent_mux;
stimulus_proc :
all_possible_values( bv(0) => sel0, bv(1) => sel1,
bv(2) => d0, bv(3) => d1,
bv(4) => d2, bv(5) => d3,
delay_between_values => 10 ns );
verifier :
assert functional_z = equivalent_z
report "Functional and equivalent models give different results";
end architecture test;
| gpl-2.0 | 4e185b6d0e3be8a64d6ec3532ef99cea | 0.560355 | 3.631653 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc742.vhd | 4 | 3,799 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc742.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p04n01i00742pkg is
type arrtype is array (1 to 5) of integer;
type rectype is record
-- 'a',33,0.1234,TRUE
ch : character;
int : integer;
re : real;
bo : boolean;
end record;
end c01s01b01x01p04n01i00742pkg;
use work.c01s01b01x01p04n01i00742pkg.all;
entity c01s01b01x01p04n01i00742ent_a is
generic (
constant gc1 : arrtype;
constant gc2 : rectype;
constant gc3 : boolean
);
port ( signal cent1 : in bit;
signal cent2 : in bit
);
end c01s01b01x01p04n01i00742ent_a;
architecture c01s01b01x01p04n01i00742arch_a of c01s01b01x01p04n01i00742ent_a is
begin
p0: process
begin
wait for 1 ns;
if (gc1=(1,2,3,4,5)) AND (gc2.ch='a') AND (gc2.int=33) AND (gc2.re=0.1234) AND (gc2.bo) AND (gc3) then
assert FALSE
report "***PASSED TEST: c01s01b01x01p04n01i00742"
severity NOTE;
else
assert FALSE
report "***FAILED TEST: c01s01b01x01p04n01i00742 - Generic association with type conversion in component instantiation failed."
severity ERROR;
end if;
wait;
end process;
end c01s01b01x01p04n01i00742arch_a;
use work.c01s01b01x01p04n01i00742pkg.all;
ENTITY c01s01b01x01p04n01i00742ent IS
generic ( constant gen_con : integer := 7 );
port ( signal ee1 : in bit;
signal ee2 : in bit;
signal eo1 : out bit
);
END c01s01b01x01p04n01i00742ent;
ARCHITECTURE c01s01b01x01p04n01i00742arch OF c01s01b01x01p04n01i00742ent IS
signal s1 : integer;
signal s2 : integer;
signal s3 : integer;
component comp1
generic (
constant dgc1 : arrtype;
constant dgc2 : rectype;
constant dgc3 : boolean
);
port ( signal dcent1 : in bit;
signal dcent2 : in bit
);
end component;
for u1 : comp1 use
entity work.c01s01b01x01p04n01i00742ent_a(c01s01b01x01p04n01i00742arch_a)
generic map (dgc1, dgc2, dgc3)
port map ( dcent1, dcent2 );
function BoolToArr(bin : boolean) return arrtype is
begin
if bin then
return (1,2,3,4,5);
else
return (9,8,7,6,5);
end if;
end;
function IntegerToRec(iin : integer) return rectype is
begin
return ('a',33,0.1234,TRUE);
end;
function BitToBool(bin : bit) return boolean is
begin
if (bin = '1') then
return TRUE;
else
return FALSE;
end if;
end;
BEGIN
u1 : comp1
generic map (BoolToArr(TRUE), IntegerToRec(1234), BitToBool('1'))
port map (ee1,ee2);
END c01s01b01x01p04n01i00742arch;
| gpl-2.0 | 349e9605a82da1476e93b6534ca93830 | 0.639379 | 3.320804 | false | false | false | false |
nickg/nvc | test/regress/arith1.vhd | 1 | 1,051 | entity arith1 is
end entity;
architecture test of arith1 is
begin
proc1: process is
variable x, y : integer;
begin
x := 3;
y := 12;
wait for 1 ns;
assert x + y = 15;
assert x - y = -9;
assert x * y = 36;
assert x / 12 = 0;
assert x = 3;
assert y = 12;
assert x /= y;
assert x < y;
assert y > x;
assert x <= y;
assert y >= x;
assert (- x) = -3;
assert x ** y = 531441;
x := -34;
wait for 1 ns;
assert abs x = 34;
assert abs y = 12;
y := 3;
wait for 1 ns;
assert 5 mod y = 2;
assert 5 rem y = 2;
assert (-5) rem y = -2;
assert (-5) mod 3 = 1;
assert (-5) mod y = 1;
y := -8;
wait for 1 ns;
assert (-512) mod (-8) = 0;
assert (-512) mod y = 0;
assert (-510) mod (-8) = -6;
assert (-510) mod y = -6;
assert x = +x;
wait;
end process;
end architecture;
| gpl-3.0 | 847dab7bdd4d45e7c4d1bebb2b99db83 | 0.415794 | 3.445902 | false | false | false | false |
tgingold/ghdl | testsuite/synth/asgn01/asgn08.vhdl | 1 | 535 | library ieee;
use ieee.std_logic_1164.all;
entity asgn08 is
port (clk : std_logic;
ce : std_logic;
s0 : std_logic;
r : out std_logic_vector (65 downto 0));
end asgn08;
architecture behav of asgn08 is
begin
r (0) <= '1';
process (clk) is
begin
if rising_edge(clk) and ce = '1' then
if s0 = '1' then
r (64 downto 1) <= x"ffff_eeee_dddd_cccc";
r (65) <= '1';
else
r (8 downto 5) <= x"7";
r (65) <= '0';
end if;
end if;
end process;
end behav;
| gpl-2.0 | f8569fa4e1699fc39470f28f29ee523e | 0.527103 | 2.93956 | false | false | false | false |
tgingold/ghdl | testsuite/synth/synth111/rams_sdp_3d.vhd | 1 | 1,964 | -- 3-D Ram Inference Example ( Simple Dual port)
-- Compile this file in VHDL2008 mode
-- File:rams_sdp_3d.vhd
library ieee;
use ieee.std_logic_1164.all;
package mypack is
type myarray_t is array(integer range<>) of std_logic_vector;
type mem_t is array(integer range<>) of myarray_t;
end package;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mypack.all;
entity rams_sdp_3d is generic (
NUM_RAMS : integer := 2;
A_WID : integer := 10;
D_WID : integer := 32
);
port (
clka : in std_logic;
clkb : in std_logic;
wea : in std_logic_vector(NUM_RAMS-1 downto 0);
ena : in std_logic_vector(NUM_RAMS-1 downto 0);
enb : in std_logic_vector(NUM_RAMS-1 downto 0);
addra : in myarray_t(NUM_RAMS-1 downto 0)(A_WID-1 downto 0);
addrb : in myarray_t(NUM_RAMS-1 downto 0)(A_WID-1 downto 0);
dina : in myarray_t(NUM_RAMS-1 downto 0)(D_WID-1 downto 0);
doutb : out myarray_t(NUM_RAMS-1 downto 0)(D_WID-1 downto 0)
);
end rams_sdp_3d;
architecture arch of rams_sdp_3d is
signal mem : mem_t(NUM_RAMS-1 downto 0)(2**A_WID-1 downto 0)(D_WID-1 downto 0);
begin
process(clka)
begin
if(clka'event and clka='1') then
for i in 0 to NUM_RAMS-1 loop
if(ena(i) = '1') then
if(wea(i) = '1') then
mem(i)(to_integer(unsigned(addra(i)))) <= dina(i);
end if;
end if;
end loop;
end if;
end process;
process(clkb)
begin
if(clkb'event and clkb='1') then
for i in 0 to NUM_RAMS-1 loop
if(enb(i) = '1') then
doutb(i) <= mem(i)(to_integer(unsigned(addrb(i))));
end if;
end loop;
end if;
end process;
end arch;
| gpl-2.0 | 3855bf2785463c90014d21d9297bf42f | 0.530041 | 3.323181 | false | false | false | false |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_avlmm_pr_freeze_bridge_1/ghrd_10as066n2_avlmm_pr_freeze_bridge_1_inst.vhd | 1 | 7,590 | component ghrd_10as066n2_avlmm_pr_freeze_bridge_1 is
port (
clock : in std_logic := 'X'; -- clk
freeze_conduit_freeze : in std_logic := 'X'; -- freeze
freeze_conduit_illegal_request : out std_logic; -- illegal_request
mst_bridge_to_pr_read : in std_logic := 'X'; -- read
mst_bridge_to_pr_waitrequest : out std_logic; -- waitrequest
mst_bridge_to_pr_write : in std_logic := 'X'; -- write
mst_bridge_to_pr_address : in std_logic_vector(31 downto 0) := (others => 'X'); -- address
mst_bridge_to_pr_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
mst_bridge_to_pr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
mst_bridge_to_pr_readdata : out std_logic_vector(31 downto 0); -- readdata
mst_bridge_to_pr_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
mst_bridge_to_pr_readdatavalid : out std_logic; -- readdatavalid
mst_bridge_to_pr_beginbursttransfer : in std_logic := 'X'; -- beginbursttransfer
mst_bridge_to_pr_debugaccess : in std_logic := 'X'; -- debugaccess
mst_bridge_to_pr_response : out std_logic_vector(1 downto 0); -- response
mst_bridge_to_pr_lock : in std_logic := 'X'; -- lock
mst_bridge_to_pr_writeresponsevalid : out std_logic; -- writeresponsevalid
mst_bridge_to_sr_read : out std_logic; -- read
mst_bridge_to_sr_waitrequest : in std_logic := 'X'; -- waitrequest
mst_bridge_to_sr_write : out std_logic; -- write
mst_bridge_to_sr_address : out std_logic_vector(31 downto 0); -- address
mst_bridge_to_sr_byteenable : out std_logic_vector(3 downto 0); -- byteenable
mst_bridge_to_sr_writedata : out std_logic_vector(31 downto 0); -- writedata
mst_bridge_to_sr_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
mst_bridge_to_sr_burstcount : out std_logic_vector(2 downto 0); -- burstcount
mst_bridge_to_sr_readdatavalid : in std_logic := 'X'; -- readdatavalid
mst_bridge_to_sr_beginbursttransfer : out std_logic; -- beginbursttransfer
mst_bridge_to_sr_debugaccess : out std_logic; -- debugaccess
mst_bridge_to_sr_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
mst_bridge_to_sr_lock : out std_logic; -- lock
mst_bridge_to_sr_writeresponsevalid : in std_logic := 'X'; -- writeresponsevalid
reset_n : in std_logic := 'X' -- reset_n
);
end component ghrd_10as066n2_avlmm_pr_freeze_bridge_1;
u0 : component ghrd_10as066n2_avlmm_pr_freeze_bridge_1
port map (
clock => CONNECTED_TO_clock, -- clock.clk
freeze_conduit_freeze => CONNECTED_TO_freeze_conduit_freeze, -- freeze_conduit.freeze
freeze_conduit_illegal_request => CONNECTED_TO_freeze_conduit_illegal_request, -- .illegal_request
mst_bridge_to_pr_read => CONNECTED_TO_mst_bridge_to_pr_read, -- mst_bridge_to_pr.read
mst_bridge_to_pr_waitrequest => CONNECTED_TO_mst_bridge_to_pr_waitrequest, -- .waitrequest
mst_bridge_to_pr_write => CONNECTED_TO_mst_bridge_to_pr_write, -- .write
mst_bridge_to_pr_address => CONNECTED_TO_mst_bridge_to_pr_address, -- .address
mst_bridge_to_pr_byteenable => CONNECTED_TO_mst_bridge_to_pr_byteenable, -- .byteenable
mst_bridge_to_pr_writedata => CONNECTED_TO_mst_bridge_to_pr_writedata, -- .writedata
mst_bridge_to_pr_readdata => CONNECTED_TO_mst_bridge_to_pr_readdata, -- .readdata
mst_bridge_to_pr_burstcount => CONNECTED_TO_mst_bridge_to_pr_burstcount, -- .burstcount
mst_bridge_to_pr_readdatavalid => CONNECTED_TO_mst_bridge_to_pr_readdatavalid, -- .readdatavalid
mst_bridge_to_pr_beginbursttransfer => CONNECTED_TO_mst_bridge_to_pr_beginbursttransfer, -- .beginbursttransfer
mst_bridge_to_pr_debugaccess => CONNECTED_TO_mst_bridge_to_pr_debugaccess, -- .debugaccess
mst_bridge_to_pr_response => CONNECTED_TO_mst_bridge_to_pr_response, -- .response
mst_bridge_to_pr_lock => CONNECTED_TO_mst_bridge_to_pr_lock, -- .lock
mst_bridge_to_pr_writeresponsevalid => CONNECTED_TO_mst_bridge_to_pr_writeresponsevalid, -- .writeresponsevalid
mst_bridge_to_sr_read => CONNECTED_TO_mst_bridge_to_sr_read, -- mst_bridge_to_sr.read
mst_bridge_to_sr_waitrequest => CONNECTED_TO_mst_bridge_to_sr_waitrequest, -- .waitrequest
mst_bridge_to_sr_write => CONNECTED_TO_mst_bridge_to_sr_write, -- .write
mst_bridge_to_sr_address => CONNECTED_TO_mst_bridge_to_sr_address, -- .address
mst_bridge_to_sr_byteenable => CONNECTED_TO_mst_bridge_to_sr_byteenable, -- .byteenable
mst_bridge_to_sr_writedata => CONNECTED_TO_mst_bridge_to_sr_writedata, -- .writedata
mst_bridge_to_sr_readdata => CONNECTED_TO_mst_bridge_to_sr_readdata, -- .readdata
mst_bridge_to_sr_burstcount => CONNECTED_TO_mst_bridge_to_sr_burstcount, -- .burstcount
mst_bridge_to_sr_readdatavalid => CONNECTED_TO_mst_bridge_to_sr_readdatavalid, -- .readdatavalid
mst_bridge_to_sr_beginbursttransfer => CONNECTED_TO_mst_bridge_to_sr_beginbursttransfer, -- .beginbursttransfer
mst_bridge_to_sr_debugaccess => CONNECTED_TO_mst_bridge_to_sr_debugaccess, -- .debugaccess
mst_bridge_to_sr_response => CONNECTED_TO_mst_bridge_to_sr_response, -- .response
mst_bridge_to_sr_lock => CONNECTED_TO_mst_bridge_to_sr_lock, -- .lock
mst_bridge_to_sr_writeresponsevalid => CONNECTED_TO_mst_bridge_to_sr_writeresponsevalid, -- .writeresponsevalid
reset_n => CONNECTED_TO_reset_n -- reset_n.reset_n
);
| mit | c0be3bcf23ab5a4dc3d27a15573ce2c7 | 0.499209 | 3.973822 | false | false | false | false |
lfmunoz/vhdl | ip_blocks/sip_toggle_xxbit/src/sip_toggle_4lvds.vhd | 1 | 8,589 |
-------------------------------------------------------------------------------------
-- FILE NAME : sip_lvds_reg.vhd
--
-- AUTHOR : StellarIP (c) 4DSP
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity - sip_lvds_reg
-- architecture - arch_sip_lvds_reg
--
-- LANGUAGE : VHDL
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
-- sip_lvds_reg
-- Notes: sip_lvds_reg
-------------------------------------------------------------------------------------
-- Disclaimer: LIMITED WARRANTY AND DISCLAIMER. These designs are
-- provided to you as is. 4DSP specifically disclaims any
-- implied warranties of merchantability, non-infringement, or
-- fitness for a particular purpose. 4DSP does not warrant that
-- the functions contained in these designs will meet your
-- requirements, or that the operation of these designs will be
-- uninterrupted or error free, or that defects in the Designs
-- will be corrected. Furthermore, 4DSP does not warrant or
-- make any representations regarding use or the results of the
-- use of the designs in terms of correctness, accuracy,
-- reliability, or otherwise.
--
-- LIMITATION OF LIABILITY. In no event will 4DSP or its
-- licensors be liable for any loss of data, lost profits, cost
-- or procurement of substitute goods or services, or for any
-- special, incidental, consequential, or indirect damages
-- arising from the use or operation of the designs or
-- accompanying documentation, however caused and on any theory
-- of liability. This limitation will apply even if 4DSP
-- has been advised of the possibility of such damage. This
-- limitation shall apply not-withstanding the failure of the
-- essential purpose of any limited remedies herein.
--
----------------------------------------------
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
--library declaration
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_misc.all ;
Library UNISIM;
use UNISIM.vcomponents.all;
-------------------------------------------------------------------------------------
--Entity Declaration
-------------------------------------------------------------------------------------
entity sip_toggle_4lvds is
generic (
global_start_addr_gen : std_logic_vector(27 downto 0);
global_stop_addr_gen : std_logic_vector(27 downto 0);
private_start_addr_gen : std_logic_vector(27 downto 0);
private_stop_addr_gen : std_logic_vector(27 downto 0)
);
port (
--Wormhole 'clk' of type 'clkin':
clk_clkin : in std_logic_vector(31 downto 0);
--Wormhole 'rst' of type 'rst_in':
rst_rstin : in std_logic_vector(31 downto 0);
--Wormhole 'cmdclk_in' of type 'cmdclk_in':
cmdclk_in_cmdclk : in std_logic;
--Wormhole 'cmd_in' of type 'cmd_in':
cmd_in_cmdin : in std_logic_vector(63 downto 0);
cmd_in_cmdin_val : in std_logic;
--Wormhole 'cmd_out' of type 'cmd_out':
cmd_out_cmdout : out std_logic_vector(63 downto 0);
cmd_out_cmdout_val : out std_logic;
--Wormhole 'ext_lvds' of type 'ext_lvds':
lvds_in_n : in std_logic_vector(1 downto 0);
lvds_in_p : in std_logic_vector(1 downto 0);
lvds_out_n : out std_logic_vector(1 downto 0);
lvds_out_p : out std_logic_vector(1 downto 0)
);
end entity sip_toggle_4lvds;
-------------------------------------------------------------------------------------
--Architecture declaration
-------------------------------------------------------------------------------------
architecture behav of sip_toggle_4lvds is
-------------------------------------------------------------------------------------
--Constants declaration
-------------------------------------------------------------------------------------
constant WIDTH : natural := 2;
-------------------------------------------------------------------------------------
--Signal declaration
-------------------------------------------------------------------------------------
signal clk : std_logic;
signal rst : std_logic;
signal lvds_in : std_logic_vector(1 downto 0);
signal lvds_out : std_logic_vector(1 downto 0);
signal reg0 : std_logic_vector(31 downto 0);
signal reg1 : std_logic_vector(31 downto 0);
signal reg2 : std_logic_vector(31 downto 0);
--***********************************************************************************
begin
--***********************************************************************************
clk <= cmdclk_in_cmdclk;
-------------------------------------------------------------------------------------
-- Local reset: asynchronous assert, synchronous release
-------------------------------------------------------------------------------------
process(clk, rst_rstin(2))
begin
if rst_rstin(2) = '1' then
rst <= '1';
elsif rising_edge(clk) then
rst <= '0';
end if;
end process;
-------------------------------------------------------------------------------------
-- Command Registers
-------------------------------------------------------------------------------------
ip_block_ctrl_inst0:
entity work.ip_block_ctrl
generic map (
START_ADDR => private_start_addr_gen,
STOP_ADDR => private_stop_addr_gen
)
port map (
rst => rst,
clk_cmd => clk,
in_cmd_val => cmd_in_cmdin_val,
in_cmd => cmd_in_cmdin,
out_cmd_val => cmd_out_cmdout_val,
out_cmd => cmd_out_cmdout,
cmd_busy => open,
reg0 => reg0, --out
reg1 => open, --out
reg2 => reg2, -- in
reg3 => (others=>'0'), -- in
reg4 => (others=>'0'), -- in
reg5 => (others=>'0'), -- in
reg6 => (others=>'0'), -- in
mbx_in_reg => (others=>'0'),
mbx_in_val => '0'
);
--register map
process(clk)
begin
if rising_edge(clk) then
lvds_out(1 downto 0) <= reg0(1 downto 0); -- lvds output out of fpga pin
reg2(1 downto 0) <= lvds_in(1 downto 0); -- lvds input from fpga pin
end if;
end process;
-------------------------------------------------------------------------------------
-- LVDS PHY
-------------------------------------------------------------------------------------
generate_width:
for I in 0 to WIDTH-1 generate
obufds_output : OBUFDS
generic map (
IOSTANDARD => "DEFAULT", -- Specify the output I/O standard
SLEW => "SLOW" -- Specify the output slew rate
)
port map (
O => lvds_out_p(I), -- Diff_p output (connect directly to top-level port)
OB => lvds_out_n(I), -- Diff_n output (connect directly to top-level port)
I => lvds_out(I) -- Buffer input
);
ibufds_input : IBUFDS
generic map (
DIFF_TERM => FALSE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => lvds_in(I), -- Buffer output
I => lvds_in_p(I), -- Diff_p buffer input (connect directly to top-level port)
IB => lvds_in_n(I) -- Diff_n buffer input (connect directly to top-level port)
);
end generate;
--***********************************************************************************
end architecture behav;
--***********************************************************************************
| mit | abe220865a3dffe125f6917d73590e3a | 0.415182 | 4.600428 | false | false | false | false |
tgingold/ghdl | testsuite/synth/asgn01/asgn05.vhdl | 1 | 387 | library ieee;
use ieee.std_logic_1164.all;
entity asgn05 is
port (s0 : std_logic;
s1 : std_logic;
r : out std_logic_vector (5 downto 0));
end asgn05;
architecture behav of asgn05 is
begin
process (s0, s1) is
begin
r <= "000000";
if s0 = '1' then
r (1) <= '1';
r (3) <= '1';
r (4 downto 2) <= "101";
end if;
end process;
end behav;
| gpl-2.0 | 429e81801f4dc0c38c88f1f36f6bbe17 | 0.550388 | 2.824818 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_13.vhd | 4 | 2,073 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_13.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- not in book
entity computer_system is
end entity computer_system;
library stimulus;
use stimulus.stimulus_generators.all;
-- end not in book
architecture structure of computer_system is
component decoder_2_to_4 is
generic ( prop_delay : delay_length );
port ( in0, in1 : in bit;
out0, out1, out2, out3 : out bit );
end component decoder_2_to_4;
-- . . .
-- not in book
signal addr : bit_vector(5 downto 4);
signal interface_a_select, interface_b_select,
interface_c_select, interface_d_select : bit;
-- end not in book
begin
interface_decoder : component decoder_2_to_4
generic map ( prop_delay => 4 ns )
port map ( in0 => addr(4), in1 => addr(5),
out0 => interface_a_select, out1 => interface_b_select,
out2 => interface_c_select, out3 => interface_d_select );
-- . . .
-- not in book
all_possible_values(addr, 10 ns);
-- end not in book
end architecture structure;
| gpl-2.0 | 8bedfb1b1f3a3d6abcd131c3598351c0 | 0.606368 | 3.948571 | false | false | false | false |
nickg/nvc | test/parse/error.vhd | 1 | 1,623 | entity e is end entity;
architecture a of e is
signal x : integer;
begin
bad syntax;
x <= 2; x <= 1 + 2; -- Recovery
some more bad syntax;
x <= 2; x <= 1 + 2; -- Recovery
process
begin
end; -- Missing "process"
x <= 2; x <= 1 + 2; -- Recovery
foo: process is
begin
end process bar; -- Label does not match
process is
begin
end process bar; -- No initial label
b: block is
impure function "+" return boolean is
begin
my_if: if x > 5 then
null;
end if blah; -- Label does not match
x <= 2; x <= 1 + 2; -- Recovery
end function "-"; -- Label does not match
begin
end block;
p1: process is begin end process;
p1: process is begin end process; -- Error, duplicate label
a1: assert x = 1;
a1: assert x = 2; -- Error, duplicate label
s1: x <= 5;
s1: x <= 6; -- Error, duplicate label
b1: block is begin end block;
b1: block is begin end block; -- Error, duplicate label
b2: block is
procedure proc(x : integer) is begin end procedure;
begin
c1: proc(1);
c1: proc(2); -- Error, duplicate label
end block;
c1: not_a_library -- Error
port map ( x => 1 );
end architecture;
architecture bad of not_here is -- Error
begin
end architecture;
| gpl-3.0 | 3e75eeba2ddc88e0167f14d06f1b971f | 0.470117 | 4.316489 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue50/vector.d/v_split0.vhd | 2 | 1,357 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity v_split0 is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(7 downto 0);
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic;
wa0_en : in std_logic;
ra0_addr : in std_logic
);
end v_split0;
architecture augh of v_split0 is
-- Embedded RAM
type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 | 4e2e4576aeb181dbc465a91a9cdfc930 | 0.668386 | 2.856842 | false | false | false | false |
tgingold/ghdl | testsuite/synth/memmux01/memmux03.vhdl | 1 | 726 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memmux03 is
port (
wen : std_logic;
addr : std_logic_vector (3 downto 0);
rdat : out std_logic;
wdat : std_logic_vector (12 downto 0);
clk : std_logic;
rst : std_logic);
end memmux03;
architecture rtl of memmux03 is
begin
process (clk)
is
variable mem : std_logic_vector (12 downto 0);
variable ad : natural range 0 to 12;
begin
if rising_edge(clk) then
if rst = '1' then
mem := (others => '0');
else
ad := to_integer(unsigned(addr));
rdat <= mem (ad);
if wen = '1' then
mem := wdat;
end if;
end if;
end if;
end process;
end rtl;
| gpl-2.0 | 0021c675baa02f9d0f8657c90c97c59f | 0.575758 | 3.345622 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug16096/module.vhd | 3 | 860 | entity module is end entity;
architecture arch of module is
function func(a:natural) return natural is
begin
if a=32 then return 2;
elsif a=16 then return 1;
else return 0;
end if;
end function;
constant DATAPATH :natural := 32;
constant LSLICES :natural := func(DATAPATH);
-- constant LSLICES :natural := 2;
signal a :bit;
signal s :bit_vector(LSLICES-1 downto 0);
begin
DATA8: if DATAPATH=8 generate
a <= '0';
end generate;
-- DATA16: if DATAPATH=16 generate
-- with s select a <=
-- '1' when "0",
-- '0' when others;
-- end generate;
DATA32: if DATAPATH=32 generate
with s select a <=
'1' when "00",
'0' when "01",
'1' when "10",
'0' when others;
end generate;
end architecture;
| gpl-2.0 | 69ecaeccdaf46ca3c9c2992766b6f5bb | 0.555814 | 3.722944 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc537.vhd | 4 | 1,935 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc537.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p05n02i00537ent IS
END c03s03b00x00p05n02i00537ent;
ARCHITECTURE c03s03b00x00p05n02i00537arch OF c03s03b00x00p05n02i00537ent IS
type ARR is access BIT_VECTOR ;
BEGIN
TESTING: PROCESS
variable V1 : ARR := null ;
variable V2 : ARR(0 to 3) := new BIT_VECTOR'("1111") ; -- no_failure_here
BEGIN
V1 := V2;
assert NOT(V1(0 to 3)="1111")
report "***PASSED TEST: c03s03b00x00p05n02i00537"
severity NOTE;
assert (V1(0 to 3)="1111")
report "***FAILED TEST: c03s03b00x00p05n02i00537 - An access value belongs to a corresponding subtype of an access type if the value of the designated object satisfies the constraint."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p05n02i00537arch;
| gpl-2.0 | 819b4cfd134d558a4747158887a29a45 | 0.672868 | 3.699809 | false | true | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_skid2mm_buf.vhd | 7 | 17,071 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_skid2mm_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
-- This Module also provides Write Data Bus Mirroring and WSTRB
-- Demuxing to match a narrow Stream to a wider MMap Write
-- Channel. By doing this in the skid buffer, the resource
-- utilization of the skid buffer can be minimized by only
-- having to buffer/mux the Stream data width, not the MMap
-- Data width.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_wr_demux;
-------------------------------------------------------------------------------
entity axi_sg_skid2mm_buf is
generic (
C_MDATA_WIDTH : INTEGER range 32 to 1024 := 32 ;
-- Width of the MMap Write Data bus (in bits)
C_SDATA_WIDTH : INTEGER range 8 to 1024 := 32 ;
-- Width of the Stream Data bus (in bits)
C_ADDR_LSB_WIDTH : INTEGER range 1 to 8 := 5
-- Width of the LS address bus needed to Demux the WSTRB
);
port (
-- Clock and Reset Inputs -------------------------------------------
--
ACLK : In std_logic ; --
ARST : In std_logic ; --
---------------------------------------------------------------------
-- Slave Side (Wr Data Controller Input Side) -----------------------
--
S_ADDR_LSB : in std_logic_vector(C_ADDR_LSB_WIDTH-1 downto 0); --
S_VALID : In std_logic ; --
S_READY : Out std_logic ; --
S_DATA : In std_logic_vector(C_SDATA_WIDTH-1 downto 0); --
S_STRB : In std_logic_vector((C_SDATA_WIDTH/8)-1 downto 0); --
S_LAST : In std_logic ; --
---------------------------------------------------------------------
-- Master Side (MMap Write Data Output Side) ------------------------
M_VALID : Out std_logic ; --
M_READY : In std_logic ; --
M_DATA : Out std_logic_vector(C_MDATA_WIDTH-1 downto 0); --
M_STRB : Out std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0); --
M_LAST : Out std_logic --
---------------------------------------------------------------------
);
end entity axi_sg_skid2mm_buf;
architecture implementation of axi_sg_skid2mm_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
Constant IN_DATA_WIDTH : integer := C_SDATA_WIDTH;
Constant MM2STRM_WIDTH_RATIO : integer := C_MDATA_WIDTH/C_SDATA_WIDTH;
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_mirror_data_out : std_logic_vector(C_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_wstrb_demux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
M_VALID <= sig_m_valid_out;
S_READY <= sig_s_ready_out;
M_STRB <= sig_strb_reg_out;
M_LAST <= sig_last_reg_out;
M_DATA <= sig_mirror_data_out;
-- Assign the special S_READY FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= M_READY or not(sig_m_valid_dup);
-- Generate the skid inpit register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else S_DATA;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
--Else S_STRB;
Else sig_wstrb_demux_out;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else S_LAST;
-- m_valid combinational logic
sig_m_valid_comb <= S_VALID or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(M_READY)));
-- s_ready combinational logic
sig_s_ready_comb <= M_READY or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(S_VALID)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
sig_reset_reg <= ARST;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_READY_FLOP
--
-- Process Description:
-- Registers S_READY handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
S_READY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process S_READY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: M_VALID_FLOP
--
-- Process Description:
-- Registers M_VALID handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
M_VALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_spcl_s_ready_set = '1') then -- Fix from AXI DMA
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process M_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_DATA_REG
--
-- Process Description:
-- This process implements the Skid register for the
-- Skid Buffer Data signals.
--
-------------------------------------------------------------
SKID_DATA_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_skid_reg_en = '1') then
sig_data_skid_reg <= S_DATA;
else
null; -- hold current state
end if;
end if;
end process SKID_DATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_CNTL_REG
--
-- Process Description:
-- This process implements the Output registers for the
-- Skid Buffer Control signals
--
-------------------------------------------------------------
SKID_CNTL_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_strb_skid_reg <= sig_wstrb_demux_out;
sig_last_skid_reg <= S_LAST;
else
null; -- hold current state
end if;
end if;
end process SKID_CNTL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_DATA_REG
--
-- Process Description:
-- This process implements the Output register for the
-- Data signals.
--
-------------------------------------------------------------
OUTPUT_DATA_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_DATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_CNTL_REG
--
-- Process Description:
-- This process implements the Output registers for the
-- control signals.
--
-------------------------------------------------------------
OUTPUT_CNTL_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_CNTL_REG;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_WR_DATA_MIRROR
--
-- Process Description:
-- Implement the Write Data Mirror structure
--
-- Note that it is required that the Stream Width be less than
-- or equal to the MMap WData width.
--
-------------------------------------------------------------
DO_WR_DATA_MIRROR : process (sig_data_reg_out)
begin
for slice_index in 0 to MM2STRM_WIDTH_RATIO-1 loop
sig_mirror_data_out(((C_SDATA_WIDTH*slice_index)+C_SDATA_WIDTH)-1
downto C_SDATA_WIDTH*slice_index)
<= sig_data_reg_out;
end loop;
end process DO_WR_DATA_MIRROR;
------------------------------------------------------------
-- Instance: I_WSTRB_DEMUX
--
-- Description:
-- Instance for the Write Strobe DeMux.
--
------------------------------------------------------------
I_WSTRB_DEMUX : entity axi_sg_v4_1_2.axi_sg_wr_demux
generic map (
C_SEL_ADDR_WIDTH => C_ADDR_LSB_WIDTH ,
C_MMAP_DWIDTH => C_MDATA_WIDTH ,
C_STREAM_DWIDTH => C_SDATA_WIDTH
)
port map (
wstrb_in => S_STRB ,
demux_wstrb_out => sig_wstrb_demux_out ,
debeat_saddr_lsb => S_ADDR_LSB
);
end implementation;
| gpl-3.0 | 60b96d58780a188607d399d14ecbe9c2 | 0.472614 | 4.442103 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/bfsk_wa.vhd | 4 | 2,172 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee, ieee_proposed;
use ieee_proposed.electrical_systems.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity bfsk_wa is
generic ( fc : real := 455.0e3; -- mean carrier frequency
delta_f : real := 5.0e3; -- difference between low and high
-- carrier frequency
amp : voltage := 1.0; -- amplitude of modulated signal
offset : voltage := 0.0 ); -- output offset voltage
port ( signal d_in : in std_logic; -- digital input
terminal a_out : electrical ); -- output terminal
end entity bfsk_wa;
----------------------------------------------------------------
architecture behavioral of bfsk_wa is
quantity vout across iout through a_out; -- output branch
quantity phi : real; -- free quantity angle in radians
constant wc : real := math_2_pi * fc; -- convert fc to rad/s
constant delta_w : real := math_2_pi * delta_f; -- convert delta_f to rad/s
begin
if To_X01(d_in) = '0' use
phi'dot == wc; -- set to carrier frequency
elsif To_X01(d_in) = '1' use
phi'dot == wc + delta_w; -- set to carrier frequency + delta
else
phi'dot == 0.0;
end use;
vout == offset + amp * sin(phi); -- create sinusoidal output using phi
end architecture behavioral;
| gpl-2.0 | 44c1affbe0543c66eb1b9b753fcc4c15 | 0.626151 | 4.029685 | false | false | false | false |
nickg/nvc | test/regress/conv7.vhd | 1 | 1,420 | package pack is
type rec is record
x, y : natural;
end record;
function rec_to_int (r : rec) return natural;
function int_to_rec (x : natural) return rec;
end package;
package body pack is
function rec_to_int (r : rec) return natural is
begin
return r.x + r.y;
end function;
function int_to_rec (x : natural) return rec is
begin
return (x / 2, x * 2);
end function;
end package body;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port (
i1 : in rec;
i2 : in natural );
end entity;
architecture test of sub is
begin
p1: process is
begin
assert i1 = ( 0, 0 );
assert i2 = 0;
wait for 0 ns;
assert i1 = ( 3, 12 );
assert i2 = 5;
wait for 2 ns;
assert i2 = 8;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
use work.pack.all;
entity conv7 is
end entity;
architecture test of conv7 is
signal s1 : natural;
signal s2 : rec;
begin
uut: entity work.sub
port map (
i1 => int_to_rec(s1),
i2 => rec_to_int(s2) );
main: process is
begin
s1 <= 6;
s2 <= (2, 3);
wait for 1 ns;
s2.y <= 6;
wait;
end process;
end architecture;
| gpl-3.0 | adfc7f81da3dbef55df2454ee4e33632 | 0.478169 | 3.736842 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue563/tb_counter.vhdl | 1 | 1,111 | library ieee;
--library vunit_lib;
--context vunit_lib.vunit_context;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_counter is
generic (runner_cfg : string);
end tb_counter;
architecture arch_tb_counter of tb_counter is
component counter is
port (
key0: in std_logic;
key3: in std_logic;
counter_out: out std_logic_vector(3 downto 0)
);
end component;
signal key0, key3: std_logic;
signal counter_out: std_logic_vector(3 downto 0);
function trigger_rising() return std_logic_vector is
begin
key0 <= '0';
wait for 1 ns;
key0 <= '1';
wait for 1 ns;
end;
begin
uut: counter port map(
key0 => key0,
key3 => key3,
counter_out => counter_out
);
main: process
begin
test_runner_setup(runner, runner_cfg);
for j in 0 to 8 loop
trigger_rising();
check_match(counter_out, (std_logic_vector(to_unsigned(j + 1, 4))));
end loop;
check_match(counter_out, ())))
test_runner_cleanup(runner); -- Simulation ends here
end process;
end arch_tb_counter ; -- arch_tb_counter
| gpl-2.0 | 57203c58372e6083291e3f7487e72eaf | 0.636364 | 3.277286 | false | false | false | false |
mistryalok/FPGA | Xilinx/ISE/Basics/JK_ffviva/JK.vhd | 1 | 1,286 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:40:43 05/22/2013
-- Design Name:
-- Module Name: JK - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity JK is
Port ( JK : in STD_LOGIC_VECTOR (1 downto 0);
Q : inout STD_LOGIC;
Qn : inout STD_LOGIC;
clk : in STD_LOGIC);
end JK;
architecture Behavioral of JK is
begin
process(clk)
begin
if(clk'event and clk='1') then
case JK is
when "00" => null;
when "10" => Q <= '1' ; qn <= '0';
when "01" => q <= '0' ; Qn <= '1';
when "11" => Q <= not q ; Qn <= not Qn;
when others => null;
end case;
end if;
end process;
end Behavioral;
| gpl-3.0 | d7a4ceb7d344be8081355abd2c8ec29e | 0.499222 | 3.475676 | false | false | false | false |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_onchip_memory2_0/pr_region_default_onchip_memory2_0_inst.vhd | 1 | 1,597 | component pr_region_default_onchip_memory2_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
reset_req : in std_logic := 'X'; -- reset_req
address : in std_logic_vector(6 downto 0) := (others => 'X'); -- address
clken : in std_logic := 'X'; -- clken
chipselect : in std_logic := 'X'; -- chipselect
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
byteenable : in std_logic_vector(3 downto 0) := (others => 'X') -- byteenable
);
end component pr_region_default_onchip_memory2_0;
u0 : component pr_region_default_onchip_memory2_0
port map (
clk => CONNECTED_TO_clk, -- clk1.clk
reset => CONNECTED_TO_reset, -- reset1.reset
reset_req => CONNECTED_TO_reset_req, -- .reset_req
address => CONNECTED_TO_address, -- s1.address
clken => CONNECTED_TO_clken, -- .clken
chipselect => CONNECTED_TO_chipselect, -- .chipselect
write => CONNECTED_TO_write, -- .write
readdata => CONNECTED_TO_readdata, -- .readdata
writedata => CONNECTED_TO_writedata, -- .writedata
byteenable => CONNECTED_TO_byteenable -- .byteenable
);
| mit | de9d7363a5fbb5dab3c5ecf7231c6c4a | 0.494678 | 3.604966 | false | false | false | false |
tgingold/ghdl | testsuite/synth/memmux01/tb_memmux04.vhdl | 1 | 927 | entity tb_memmux04 is
end tb_memmux04;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_memmux04 is
signal ad : std_logic_vector (1 downto 0);
signal val : std_logic;
signal dat, res : std_logic_vector (3 downto 0);
begin
dut : entity work.memmux04
port map (
ad => ad,
val => val,
dat => dat,
res => res);
process
begin
dat <= x"e";
ad <= "00";
val <= '0';
wait for 1 ns;
assert res = x"e" severity failure;
ad <= "01";
val <= '0';
wait for 1 ns;
assert res = x"c" severity failure;
ad <= "00";
val <= '1';
wait for 1 ns;
assert res = x"f" severity failure;
ad <= "10";
val <= '0';
wait for 1 ns;
assert res = x"a" severity failure;
ad <= "11";
val <= '0';
wait for 1 ns;
assert res = x"6" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 656d8062608e87eee00898447a7bc539 | 0.550162 | 3.196552 | false | false | false | false |
tgingold/ghdl | testsuite/synth/psl01/assume1.vhdl | 1 | 518 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity assume1 is
port (clk, rst: std_logic;
cnt : out unsigned(3 downto 0));
end assume1;
architecture behav of assume1 is
signal val : unsigned (3 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
val <= (others => '0');
else
val <= val + 1;
end if;
end if;
end process;
cnt <= val;
--psl default clock is rising_edge(clk);
--psl assume always val < 50;
end behav;
| gpl-2.0 | 3a2b56bf3afd2ed654fcdc98edb33f50 | 0.627413 | 3.197531 | false | false | false | false |
tgingold/ghdl | testsuite/synth/dff01/dff12.vhdl | 1 | 441 | library ieee;
use ieee.std_logic_1164.all;
entity dff12 is
port (q : out std_logic;
d : std_logic;
clk : std_logic;
rstn : std_logic);
end dff12;
architecture behav of dff12 is
signal ff : std_logic := '1';
begin
process (clk, rstn) is
begin
if rising_edge (clk) then
if rstn = '0' then
ff <= '0';
else
ff <= d;
end if;
end if;
end process;
q <= ff;
end behav;
| gpl-2.0 | 62525fe3a776fa82641f5caadcb92509 | 0.548753 | 3.15 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado_HLS/image_histogram/solution1/sim/vhdl/AESL_sim_pkg.vhd | 2 | 8,773 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
-- synthesis translate_off
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;
use std.textio.all;
--library work;
--use work.AESL_components.all;
package AESL_sim_components is
-- simulation routines
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING;
token_len: out INTEGER);
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING);
procedure esl_assign_lv (signal LHS : out STD_LOGIC_VECTOR;
variable RHS : in STRING);
procedure esl_assign_l (signal LHS : out STD_LOGIC;
variable RHS : in STRING);
procedure esl_compare_l (signal LHS: in STD_LOGIC;
variable RHS: in STRING;
variable dontcare: in BOOLEAN;
variable isok: out BOOLEAN);
procedure esl_compare_lv (signal LHS: in STD_LOGIC_VECTOR;
variable RHS: in STRING;
variable dontcare: in BOOLEAN;
variable isok: out BOOLEAN);
function esl_conv_string (lv : STD_LOGIC_VECTOR) return STRING;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING;
function esl_conv_lv (str : string; base : integer; len : integer) return STD_LOGIC_VECTOR;
end package;
package body AESL_sim_components is
--simulation routines
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING;
token_len: out INTEGER) is
variable whitespace : CHARACTER;
variable i : INTEGER;
variable ok: BOOLEAN;
variable buff: STRING(1 to token'length);
begin
ok := false;
i := 1;
loop_main: while not endfile(textfile) loop
if textline = null or textline'length = 0 then
readline(textfile, textline);
end if;
loop_remove_whitespace: while textline'length > 0 loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
read(textline, whitespace);
else
exit loop_remove_whitespace;
end if;
end loop;
loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
exit loop_aesl_read_token;
else
read(textline, buff(i));
i := i + 1;
end if;
ok := true;
end loop;
if ok = true then
exit loop_main;
end if;
end loop;
buff(i) := ' ';
token := buff;
token_len:= i-1;
end procedure esl_read_token;
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING) is
variable i : INTEGER;
begin
esl_read_token (textfile, textline, token, i);
end procedure esl_read_token;
procedure esl_assign_lv (signal LHS : out STD_LOGIC_VECTOR;
variable RHS : in STRING) is
variable i : INTEGER;
variable bitwidth : INTEGER;
begin
bitwidth := LHS'length;
for i in 1 to bitwidth loop
if RHS(i) = '1' then
LHS(bitwidth - i) <= '1';
elsif RHS(i) = '0' then
LHS(bitwidth - i) <= '0';
else
LHS(bitwidth - i) <= 'X';
end if;
end loop;
end procedure;
procedure esl_assign_l (signal LHS : out STD_LOGIC;
variable RHS : in STRING) is
begin
if RHS(1) = '1' then
LHS <= '1';
elsif RHS(1) = '0' then
LHS <= '0';
else
LHS <= 'X';
end if;
end procedure;
procedure esl_compare_l (signal LHS: in STD_LOGIC;
variable RHS: in STRING;
variable dontcare: in BOOLEAN;
variable isok: out BOOLEAN) is
begin
if dontcare then
isok := true;
elsif RHS(1) = '1' then
if LHS = '1' then
isok := true;
else
isok := false;
end if;
elsif RHS(1) = '0' then
if LHS = '0' then
isok := true;
else
isok := false;
end if;
else
isok := true;
end if;
end procedure;
procedure esl_compare_lv (signal LHS: in STD_LOGIC_VECTOR;
variable RHS: in STRING;
variable dontcare: in BOOLEAN;
variable isok: out BOOLEAN) is
variable i : INTEGER;
variable bitwidth : INTEGER;
begin
bitwidth := LHS'length;
if dontcare then
isok := true;
else
isok := true;
loop_compare: for i in 1 to bitwidth loop
if RHS(i) = '1' then
if LHS(bitwidth - i) /= '1' then
isok := false;
exit loop_compare;
end if;
elsif RHS(i) = '0' then
if LHS(bitwidth - i) /= '0' then
isok := false;
exit loop_compare;
end if;
end if;
end loop;
end if;
end procedure;
function esl_conv_string (lv : STD_LOGIC_VECTOR) return STRING is
variable ret : STRING (1 to lv'length);
variable i: INTEGER;
begin
for i in 1 to lv'length loop
if lv(lv'length - i) = '1' then
ret(i) := '1';
elsif lv(lv'length - i) = '0' then
ret(i) := '0';
else
ret(i) := 'X';
end if;
end loop;
return ret;
end function;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is
constant LEN : integer := (lv'length + 3)/4;
variable ret : STRING (1 to LEN);
variable i, tmp: INTEGER;
variable normal_lv : STD_LOGIC_VECTOR(LEN * 4 - 1 downto 0);
variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0);
begin
normal_lv := (others => '0');
normal_lv(lv'length - 1 downto 0) := lv;
for i in 0 to LEN - 1 loop
tmp_lv := normal_lv(LEN * 4 - 1 - i * 4 downto LEN * 4 - 4 - i * 4);
case tmp_lv is
when "0000" => ret(i + 1) := '0';
when "0001" => ret(i + 1) := '1';
when "0010" => ret(i + 1) := '2';
when "0011" => ret(i + 1) := '3';
when "0100" => ret(i + 1) := '4';
when "0101" => ret(i + 1) := '5';
when "0110" => ret(i + 1) := '6';
when "0111" => ret(i + 1) := '7';
when "1000" => ret(i + 1) := '8';
when "1001" => ret(i + 1) := '9';
when "1010" => ret(i + 1) := 'a';
when "1011" => ret(i + 1) := 'b';
when "1100" => ret(i + 1) := 'c';
when "1101" => ret(i + 1) := 'd';
when "1110" => ret(i + 1) := 'e';
when "1111" => ret(i + 1) := 'f';
when others => ret(i + 1) := '0';
end case;
end loop;
return ret;
end function;
function esl_conv_lv (str : STRING; base : integer; len : integer) return STD_LOGIC_VECTOR is
variable ret : STD_LOGIC_VECTOR(len - 1 downto 0);
variable val : integer := 0;
variable pos : boolean := true;
variable i : integer;
begin
loop_main: for i in 1 to str'length loop
if str(i) = ' ' or str(i) = HT or str(i) = CR or str(i) = LF then
exit loop_main;
elsif str(i) = '-' then
pos := false;
else
case base is
when 10 =>
if '0' <= str(i) and str(i) <= '9' then
val := val*10 + character'pos(str(i)) - character'pos('0');
else
val := val*10;
end if;
when others =>
val := 0;
end case;
end if;
end loop;
if pos = false then
val := val * (-1);
end if;
ret := conv_std_logic_vector(val, len);
return ret;
end function;
end package body;
-- synthesis translate_on
-- XSIP watermark, do not delete 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
| gpl-3.0 | 2b753fdc6fc2fd872ec9ab83f82de8ba | 0.498005 | 3.953583 | false | false | false | false |
mistryalok/FPGA | Xilinx/ISE/Basics/MUX4x1/MUX4x1.vhd | 1 | 1,132 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:55:43 04/04/2013
-- Design Name:
-- Module Name: MUX4x1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MUX4x1 is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in bit_VECTOR (1 downto 0);
c : out STD_LOGIC);
end MUX4x1;
architecture Behavioral of MUX4x1 is
begin
process(b)
begin
case b is
when "00" => c <= a(0);
when "01" => c <= a(1);
when "10" => c <= a(2);
when "11" => c <= a(3);
end case;
end process;
end Behavioral;
| gpl-3.0 | b080c11c0feeb3fc4f043e897cc2cebc | 0.521201 | 3.430303 | false | false | false | false |
tgingold/ghdl | testsuite/gna/ticket89/project/src93/vhdl_version_layer_pkg.vhd | 3 | 3,783 | --========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation files (for 'Bitvis Utility Library'),
-- to use, copy, modify, merge, publish and/or distribute - subject to the following conditions:
-- - This copyright notice shall be included as is in all copies or substantial portions of the code and documentation
-- - The files included in Bitvis Utility Library may only be used as a part of this library as a whole
-- - The License file may not be modified
-- - The calls in the code to the license file ('show_license') may not be removed or modified.
-- - No other conditions whatsoever may be added to those of this License
-- BITVIS UTILITY LIBRARY AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
-- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH BITVIS UTILITY LIBRARY.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis Utility Library : vhdl_version_layer_pkg
--
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
use ieee_proposed.standard_textio_additions.all;
use work.types_pkg.all;
use work.adaptations_pkg.all;
use work.string_methods_pkg.all;
package vhdl_version_layer_pkg is
impure function get_alert_counter(
alert_level: t_alert_level;
attention : t_attention := REGARD
) return natural;
procedure increment_alert_counter(
alert_level: t_alert_level;
attention : t_attention := REGARD; -- regard, expect, ignore
number : natural := 1
);
procedure report_alert_counters(
order : t_order
);
end package vhdl_version_layer_pkg;
--=============================================================================
--=============================================================================
package body vhdl_version_layer_pkg is
-- Shared variable for all the alert counters for different attention
shared variable shared_alert_attention_counters : t_alert_attention_counters;
impure function get_alert_counter(
alert_level: t_alert_level;
attention : t_attention := REGARD
) return natural is
begin
return shared_alert_attention_counters(alert_level)(attention);
end;
procedure increment_alert_counter(
alert_level: t_alert_level;
attention : t_attention := REGARD; -- regard, expect, ignore
number : natural := 1
) is
begin
shared_alert_attention_counters(alert_level)(attention) :=
shared_alert_attention_counters(alert_level)(attention) + number;
end;
procedure report_alert_counters(
order : t_order
) is
begin
to_string(shared_alert_attention_counters, order);
end;
end package body vhdl_version_layer_pkg;
| gpl-2.0 | da2dce31cb0892eecd457868e26e904b | 0.595823 | 4.630355 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_18.vhd | 4 | 2,398 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_18 is
end entity inline_18;
----------------------------------------------------------------
architecture test of inline_18 is
begin
process_5_a : process is
constant initial_value : natural := 10;
constant max_value : natural := 8;
constant current_character : character := 'A';
constant input_string : string := "012ABC";
constant free_memory : natural := 0;
constant low_water_limit : natural := 1024;
constant packet_length : natural := 0;
constant clock_pulse_width : delay_length := 10 ns;
constant min_clock_width : delay_length := 20 ns;
constant last_position : natural := 10;
constant first_position : natural := 5;
constant number_of_entries : natural := 0;
begin
-- code from book:
assert initial_value <= max_value;
--
assert initial_value <= max_value
report "initial value too large";
--
assert current_character >= '0' and current_character <= '9'
report "Input number " & input_string & " contains a non-digit";
--
assert free_memory >= low_water_limit
report "low on memory, about to start garbage collect"
severity note;
--
assert packet_length /= 0
report "empty network packet received"
severity warning;
--
assert clock_pulse_width >= min_clock_width
severity error;
--
assert (last_position - first_position + 1) = number_of_entries
report "inconsistency in buffer model"
severity failure;
-- end of code from book
wait;
end process process_5_a;
end architecture test;
| gpl-2.0 | 8c5c8fde8e4bbfdad642fbf9ee51355c | 0.656797 | 4.251773 | false | false | false | false |
nickg/nvc | test/regress/case8.vhd | 1 | 1,981 | entity case8 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of case8 is
function toint32(b : std_logic_vector(31 downto 0)) return integer is
begin
-- This uses a non-exact case map as 4*32 > 64
case b is
when X"00000000" => return 0;
when X"00000100" => return 1;
when X"00000101" => return 2;
when X"00000011" => return 3;
when X"00001001" => return 4;
when X"00004141" => return 5;
when X"00002521" => return 6;
when X"10005211" => return 7;
when X"ffff0001" => return 8;
when X"ffff1000" => return 9;
when X"ffff52af" => return 10;
when X"ffffffff" => return 11;
when X"ffffabcd" => return 12;
when X"ffffabed" => return 13;
when X"ffff1415" => return 14;
when X"ffff5252" => return 15;
-- These two have hash collisions
when "LHH-HWUL-LHZ0UHH01WXXWXUUZX-WXUU" => return 555;
when "0X0L0WWUHLX0Z1Z-L---L-LXZ0UHZ-0Z" => return 666;
when others => return -1;
end case;
end function;
begin
process is
variable b : std_logic_vector(31 downto 0);
begin
assert toint32(X"00000000") = 0;
b := X"00004141"; assert toint32(b) = 5;
b := X"00001001"; assert toint32(b) = 4;
b := X"00000101"; assert toint32(b) = 2;
b := X"abab1101"; assert toint32(b) = -1;
b := X"ffff52af"; assert toint32(b) = 10;
b := X"ffff52ae"; assert toint32(b) = -1;
-- The following three cases all hash to the same value
b := "LHH-HWUL-LHZ0UHH01WXXWXUUZX-WXUU";
assert toint32(b) = 555;
b := "0X0L0WWUHLX0Z1Z-L---L-LXZ0UHZ-0Z";
assert toint32(b) = 666;
b := "Z-LXHW0XH-0W1111ZXWW1XLLZULX-HU1";
assert toint32(b) = -1;
wait;
end process;
end architecture;
| gpl-3.0 | b344f12f506fc17c83a59ca548de2aca | 0.54417 | 3.340641 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc607.vhd | 4 | 2,855 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc607.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:42 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:01 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:20 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00607ent IS
END c03s04b01x00p01n01i00607ent;
ARCHITECTURE c03s04b01x00p01n01i00607arch OF c03s04b01x00p01n01i00607ent IS
type positive_cons_vector is array (15 downto 0) of positive;
type positive_cons_vector_file is file of positive_cons_vector;
constant C19 : positive_cons_vector := (others => 3);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : positive_cons_vector_file open read_mode is "iofile.30";
variable v : positive_cons_vector;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C19) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00607"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00607 - File reading operation (positive_cons_vector file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00607arch;
| gpl-2.0 | 25c99d38b51817237aa0aa4b4b694581 | 0.566725 | 3.959778 | false | true | false | false |
tgingold/ghdl | testsuite/synth/arr01/arr06.vhdl | 1 | 922 | library ieee;
use ieee.std_logic_1164.all;
entity arr06 is
port (clk : in std_logic;
val : std_logic_vector(7 downto 0);
res : out std_logic_vector(7 downto 0);
par : out std_logic);
end arr06;
architecture behav of arr06 is
type pipe_el is record
val : std_logic_vector(7 downto 0);
odd : std_logic;
end record;
type pipe_type is array (0 to 4) of pipe_el;
signal mem : pipe_type;
signal n_mem : pipe_type;
signal tick : std_logic := '0';
begin
process(clk)
begin
if rising_edge (clk) then
mem <= n_mem;
tick <= not tick;
end if;
end process;
process(mem, val, tick)
variable v : pipe_type;
begin
for i in 1 to pipe_type'high loop
v (i) := mem (i - 1);
end loop;
v (0).val := val;
v (0).odd := tick;
n_mem <= v;
end process;
res <= mem (pipe_type'high).val;
par <= mem (pipe_type'high).odd;
end behav;
| gpl-2.0 | 7730d337bd81ba38f27550d0b8695217 | 0.590022 | 3.05298 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1155/tb_ent.vhdl | 1 | 1,182 | library ieee;
use ieee.std_logic_1164.all;
entity tb_ent is
end;
architecture a of tb_ent is
component ent is
port (
clk : in std_logic;
write : in std_logic;
addr : in std_logic_vector(1 downto 0);
data_write : in std_logic_vector(3 downto 0);
x0 : out std_logic_vector(3 downto 0);
x1 : out std_logic_vector(3 downto 0);
x2 : out std_logic_vector(3 downto 0);
x3 : out std_logic_vector(3 downto 0)
);
end component;
signal clk, write : std_logic;
signal addr : std_logic_vector(1 downto 0);
signal data_write : std_logic_vector(3 downto 0);
signal x0, x1, x2, x3 : std_logic_vector(3 downto 0);
begin
uut_inst: ent
port map (
clk => clk,
write => write,
addr => addr,
data_write => data_write,
x0 => x0,
x1 => x1,
x2 => x2,
x3 => x3
);
process
procedure pulse is
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end;
begin
write <= '0';
addr <= "00";
pulse;
write <= '1';
data_write <= "1111";
pulse;
assert x0 = "1111";
write <= '0';
data_write <= "0001";
pulse;
assert x0 = "1111";
wait for 20 ns;
wait;
end process;
end;
| gpl-2.0 | da0cfe84abb0157104b897c4c182b0cd | 0.582064 | 2.597802 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue964/ent.vhdl | 1 | 507 | library ieee;
use ieee.std_logic_1164.all;
entity ent is
port (
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
q : out std_logic
);
end;
architecture a of ent is
signal s : std_logic;
begin
process(clk, reset)
begin
if reset = '1' then
s <= '0';
elsif enable /= '1' then
-- [nothing]
elsif rising_edge(clk) then
s <= not s;
end if;
end process;
q <= s;
end;
| gpl-2.0 | f8717ba378692f9b92c2b28dbe8730c5 | 0.495069 | 3.520833 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug040/p_jinfo_dc_dhuff_tbl_mincode.vhd | 2 | 1,457 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity p_jinfo_dc_dhuff_tbl_mincode is
port (
wa0_data : in std_logic_vector(8 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(8 downto 0);
wa0_en : in std_logic
);
end p_jinfo_dc_dhuff_tbl_mincode;
architecture augh of p_jinfo_dc_dhuff_tbl_mincode is
-- Embedded RAM
type ram_type is array (0 to 127) of std_logic_vector(8 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 | 087c2e2962db47282519de9c91dd10c0 | 0.676047 | 2.86811 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug029/repro1.vhdl | 2 | 1,006 | package foo is
function some_foo return integer;
function some_fum return integer;
function some_foe (x, y, w: integer) return integer;
function some_fee (x, y, w: integer) return integer;
end package;
package body foo is
function some_foo return integer is
begin
return -1;
return 0;
end function;
function some_fum return integer is
variable a: integer := -1;
variable b: integer := 0;
begin
return a;
return b;
end function;
function some_foe (x, y, w: integer) return integer is
variable a: integer := -1;
variable b: integer := 0;
begin
return a;
return b;
end function;
function some_fee (x, y, w: integer) return integer is
variable a: integer := -1;
variable b: integer := 0;
begin
a := x + w;
b := y + w;
return a;
return b;
end function;
end package body;
| gpl-2.0 | afdd10218efb836673f7d6cdc1e61361 | 0.548708 | 4.157025 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1251/theunit.vhdl | 1 | 381 | library ieee;
use ieee.std_logic_1164.all;
entity theunit is
-- NOTE: w := 2 prevents bug
generic (w : natural := 1);
port (dout : out std_ulogic);
end;
architecture rtl of theunit is
type selsel_t is array (0 to 1) of natural range 0 to w-1;
signal selsel : selsel_t := (others => 0);
begin
-- NOTE: selsel(0) prevents bug
selsel(1) <= 0;
dout <= '0';
end;
| gpl-2.0 | 5c2ebedf94452cf3709792852428b458 | 0.629921 | 2.930769 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/generics/timer.vhd | 4 | 1,899 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity timer is
generic ( threshold : real;
clamp_on_resistance, clamp_off_resistance : real );
port ( signal trigger_n, reset : in std_ulogic; signal q : out std_ulogic;
terminal rc_ext : electrical );
end entity timer;
----------------------------------------------------------------
architecture behavioral of timer is
quantity v_rc_ext across i_clamp through rc_ext to electrical_ref;
signal q_n : std_ulogic := '1';
begin
if q_n = '1' use
i_clamp == v_rc_ext / clamp_on_resistance;
else
i_clamp == v_rc_ext / clamp_off_resistance;
end use;
timer_state : process ( trigger_n, reset, v_rc_ext'above(threshold) ) is
begin
if reset = '1' or reset = 'H' or v_rc_ext > threshold then
q <= '0'; q_n <= '1';
elsif trigger_n = '0' or trigger_n = 'L' then
q <= '1'; q_n <= '0';
end if;
end process timer_state;
break on q_n;
end architecture behavioral;
| gpl-2.0 | 05ef59eff99fdb0cbab4231b4860a6ad | 0.640337 | 3.805611 | false | false | false | false |
hubertokf/VHDL-Fast-Adders | CLAH/CLA2bits/16bits/CLAH16bits/CLAH16bits.vhd | 1 | 4,196 | LIBRARY Ieee;
USE ieee.std_logic_1164.all;
ENTITY CLAH16bits IS
PORT (
val1,val2: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CarryIn: IN STD_LOGIC;
CarryOut: OUT STD_LOGIC;
clk: IN STD_LOGIC;
rst: IN STD_LOGIC;
SomaResult:OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END CLAH16bits;
ARCHITECTURE strc_CLAH16bits of CLAH16bits is
SIGNAL Cin_sig, Cout_sig: STD_LOGIC;
SIGNAL P0_sig, P1_sig, P2_sig, P3_sig, P4_sig, P5_sig, P6_sig, P7_sig: STD_LOGIC;
SIGNAL G0_sig, G1_sig, G2_sig, G3_sig, G4_sig, G5_sig, G6_sig, G7_sig: STD_LOGIC;
SIGNAL Cout1_temp_sig, Cout2_temp_sig, Cout3_temp_sig, Cout4_temp_sig, Cout5_temp_sig, Cout6_temp_sig, Cout7_temp_sig: STD_LOGIC;
SIGNAL A_sig, B_sig, Out_sig: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL SomaT1,SomaT2,SomaT3,SomaT4,SomaT5,SomaT6,SomaT7,SomaT8:STD_LOGIC_VECTOR(1 DOWNTO 0);
Component CLA2bits
PORT (
val1,val2: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
SomaResult:OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
CarryIn: IN STD_LOGIC;
P, G: OUT STD_LOGIC
);
end component;
Component Reg1Bit
PORT (
valIn: in std_logic;
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic
);
end component;
Component Reg16Bit
PORT (
valIn: in std_logic_vector(15 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(15 downto 0)
);
end component;
Component CLGB
PORT (
P0, P1, G0, G1, Cin: IN STD_LOGIC;
Cout1, Cout2: OUT STD_LOGIC
);
end component;
BEGIN
--registradores--
Reg_CarryIn: Reg1Bit PORT MAP (
valIn=>CarryIn,
clk=>clk,
rst=>rst,
valOut=>Cin_sig
);
Reg_A: Reg16Bit PORT MAP (
valIn=>val1,
clk=>clk,
rst=>rst,
valOut=>A_sig
);
Reg_B: Reg16Bit PORT MAP (
valIn=>val2,
clk=>clk,
rst=>rst,
valOut=>B_sig
);
Reg_CarryOut: Reg1Bit PORT MAP (
valIn=>Cout_sig,
clk=>clk,
rst=>rst,
valOut=>CarryOut
);
Reg_Ssoma: Reg16Bit PORT MAP (
valIn=>Out_sig,
clk=>clk,
rst=>rst,
valOut=>SomaResult
);
Som1: CLA2bits PORT MAP(
val1(1 DOWNTO 0) => A_sig(1 DOWNTO 0),
val2(1 DOWNTO 0) => B_sig(1 DOWNTO 0),
CarryIn=>Cin_sig,
P=>P0_sig,
G=>G0_sig,
SomaResult=>SomaT1
);
CLGB1: CLGB PORT MAP(
P0=>P0_sig,
G0=>G0_sig,
P1=>P1_sig,
G1=>G1_sig,
Cin=>Cin_sig,
Cout1=>Cout1_temp_sig,
Cout2=>Cout2_temp_sig
);
Som2: CLA2bits PORT MAP(
val1(1 DOWNTO 0) => A_sig(3 DOWNTO 2),
val2(1 DOWNTO 0) => B_sig(3 DOWNTO 2),
CarryIn=>Cout1_temp_sig,
P=>P1_sig,
G=>G1_sig,
SomaResult=>SomaT2
);
Som3: CLA2bits PORT MAP(
val1(1 DOWNTO 0) => A_sig(5 DOWNTO 4),
val2(1 DOWNTO 0) => B_sig(5 DOWNTO 4),
CarryIn=>Cout2_temp_sig,
P=>P2_sig,
G=>G2_sig,
SomaResult=>SomaT3
);
CLGB2: CLGB PORT MAP(
P0=>P2_sig,
G0=>G2_sig,
P1=>P3_sig,
G1=>G3_sig,
Cin=>Cout2_temp_sig,
Cout1=>Cout3_temp_sig,
Cout2=>Cout4_temp_sig
);
Som4: CLA2bits PORT MAP(
val1(1 DOWNTO 0) => A_sig(7 DOWNTO 6),
val2(1 DOWNTO 0) => B_sig(7 DOWNTO 6),
CarryIn=>Cout3_temp_sig,
P=>P3_sig,
G=>G3_sig,
SomaResult=>SomaT4
);
--novoooooooo--
Som5: CLA2bits PORT MAP(
val1(1 DOWNTO 0) => A_sig(9 DOWNTO 8),
val2(1 DOWNTO 0) => B_sig(9 DOWNTO 8),
CarryIn=>Cout4_temp_sig,
P=>P4_sig,
G=>G4_sig,
SomaResult=>SomaT5
);
CLGB3: CLGB PORT MAP(
P0=>P4_sig,
G0=>G4_sig,
P1=>P5_sig,
G1=>G5_sig,
Cin=>Cout4_temp_sig,
Cout1=>Cout5_temp_sig,
Cout2=>Cout6_temp_sig
);
Som6: CLA2bits PORT MAP(
val1(1 DOWNTO 0) => A_sig(11 DOWNTO 10),
val2(1 DOWNTO 0) => B_sig(11 DOWNTO 10),
CarryIn=>Cout5_temp_sig,
P=>P5_sig,
G=>G5_sig,
SomaResult=>SomaT6
);
Som7: CLA2bits PORT MAP(
val1(1 DOWNTO 0) => A_sig(13 DOWNTO 12),
val2(1 DOWNTO 0) => B_sig(13 DOWNTO 12),
CarryIn=>Cout6_temp_sig,
P=>P6_sig,
G=>G6_sig,
SomaResult=>SomaT7
);
CLGB4: CLGB PORT MAP(
P0=>P6_sig,
G0=>G6_sig,
P1=>P7_sig,
G1=>G7_sig,
Cin=>Cout6_temp_sig,
Cout1=>Cout7_temp_sig,
Cout2=>Cout_sig
);
Som8: CLA2bits PORT MAP(
val1(1 DOWNTO 0) => A_sig(15 DOWNTO 14),
val2(1 DOWNTO 0) => B_sig(15 DOWNTO 14),
CarryIn=>Cout7_temp_sig,
P=>P7_sig,
G=>G7_sig,
SomaResult=>SomaT8
);
Out_sig <= SomaT8 & SomaT7 & SomaT6 & SomaT5 & SomaT4 & SomaT3 & SomaT2 & SomaT1;
END strc_CLAH16bits; | mit | 11f29f63facd73a1dfba70f60ac13764 | 0.635605 | 2.263215 | false | false | false | false |
nickg/nvc | test/regress/record15.vhd | 1 | 876 | package pack is
type rec is record
x : integer;
y : bit;
end record;
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port (
r : in rec;
x : out integer;
y : out bit );
end entity;
architecture test of sub is
begin
x <= r.x;
y <= r.y;
end architecture;
-------------------------------------------------------------------------------
use work.pack.all;
entity record15 is
end entity;
architecture test of record15 is
signal x : integer;
signal y : bit;
begin
sub_i: entity work.sub
port map (
r => (123, '1'),
x => x,
y => y );
process is
begin
wait for 1 ns;
assert x = 123;
assert y = '1';
wait;
end process;
end architecture;
| gpl-3.0 | 209e8a363394885dd9b36b0730d1e9f3 | 0.422374 | 4.211538 | false | false | false | false |
snow4life/PipelinedDLX | RAM.vhd | 1 | 2,093 | -- Fixed width: 32bit (because of the fixed length of the masks)
-- SIZE = 0 then MASK_32
-- SIZE = 1 then MASK_16
-- SIZE = 2 then MASK_8
-- SIZE = 3 then MASK_32
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity RAM is
generic(RAM_MODULE: integer := 6;
RAM_WIDTH: integer := 32);
port( ADDRESS: in std_logic_vector(RAM_WIDTH - 1 downto 0);
DATA_IN: in std_logic_vector(RAM_WIDTH - 1 downto 0);
RW: in std_logic;
EN: in std_logic;
SIZE: in std_logic_vector(1 downto 0);
DATA_OUT: out std_logic_vector(RAM_WIDTH - 1 downto 0));
end RAM;
architecture BEHAVIORAL of RAM is
constant MASK_8: std_logic_vector(RAM_WIDTH - 1 downto 0) := "00000000000000000000000011111111";
constant MASK_16:std_logic_vector(RAM_WIDTH - 1 downto 0) := "00000000000000001111111111111111";
type RAM_TYPE is array (0 to (2**RAM_MODULE) - 1) of integer;
signal memory : RAM_TYPE;
begin
RAM_PROCESS: process(ADDRESS, DATA_IN, RW, EN, SIZE)
begin
if EN = '1' then
if RW = '1' then
--read
if SIZE = "00" then
DATA_OUT <= conv_std_logic_vector(memory(conv_integer(unsigned(ADDRESS))), RAM_WIDTH);
elsif SIZE = "01" then
DATA_OUT <= (conv_std_logic_vector(memory(conv_integer(unsigned(ADDRESS))), RAM_WIDTH) and MASK_16);
elsif SIZE = "10" then
DATA_OUT <= (conv_std_logic_vector(memory(conv_integer(unsigned(ADDRESS))), RAM_WIDTH) and MASK_8);
elsif SIZE = "11" then
DATA_OUT <= conv_std_logic_vector(memory(conv_integer(unsigned(ADDRESS))), RAM_WIDTH);
end if;
else
--write
if SIZE = "00" then
memory(conv_integer(unsigned(ADDRESS))) <= conv_integer(unsigned(DATA_IN));
elsif SIZE = "01" then
memory(conv_integer(unsigned(ADDRESS))) <= conv_integer(unsigned(DATA_IN and MASK_16));
elsif SIZE = "10" then
memory(conv_integer(unsigned(ADDRESS))) <= conv_integer(unsigned(DATA_IN and MASK_8));
elsif SIZE = "11" then
memory(conv_integer(unsigned(ADDRESS))) <= conv_integer(unsigned(DATA_IN));
end if;
end if;
end if;
end process;
end BEHAVIORAL;
| lgpl-2.1 | c48e5e200f5469c95fe167eb8194a44f | 0.665074 | 3.011511 | false | false | false | false |
lfmunoz/vhdl | ip_blocks/sip_check_data/fifo_64_in_out/synth/fifo_64in_out.vhd | 1 | 38,682 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY fifo_64in_out IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
rd_data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END fifo_64in_out;
ARCHITECTURE fifo_64in_out_arch OF fifo_64in_out IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fifo_64in_out_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF fifo_64in_out_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF fifo_64in_out_arch : ARCHITECTURE IS "fifo_64in_out,fifo_generator_v12_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF fifo_64in_out_arch: ARCHITECTURE IS "fifo_64in_out,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=12,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=64,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=64,C_ENABLE_RLOCS=0,C_FAMILY=virtex7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=1,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=1,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=4kx9,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=4093,C_PROG_FULL_THRESH_NEGATE_VAL=4092,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=12,C_RD_DEPTH=4096,C_RD_FREQ=1,C_RD_PNTR_WIDTH=12,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=12,C_WR_DEPTH=4096,C_WR_FREQ=1,C_WR_PNTR_WIDTH=12,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 12,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 64,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 64,
C_ENABLE_RLOCS => 0,
C_FAMILY => "virtex7",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 1,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 1,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "4kx9",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 4093,
C_PROG_FULL_THRESH_NEGATE_VAL => 4092,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 12,
C_RD_DEPTH => 4096,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 12,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 12,
C_WR_DEPTH => 4096,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 12,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => rst,
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
valid => valid,
rd_data_count => rd_data_count,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END fifo_64in_out_arch;
| mit | 96ad20c66575e70403b1dbb05e2aeaa7 | 0.62807 | 2.916095 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue1051/psi_common_logic_pkg.vhd | 1 | 6,311 | ------------------------------------------------------------------------------
-- Copyright (c) 2018 by Paul Scherrer Institute, Switzerland
-- All rights reserved.
-- Authors: Oliver Bruendler
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Libraries
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.psi_common_math_pkg.all;
------------------------------------------------------------------------------
-- Package Header
------------------------------------------------------------------------------
package psi_common_logic_pkg is
function ZerosVector(size : in natural) return std_logic_vector;
function OnesVector(size : in natural) return std_logic_vector;
function ShiftLeft( arg : in std_logic_vector;
bits : in integer;
fill : in std_logic := '0')
return std_logic_vector;
function ShiftRight(arg : in std_logic_vector;
bits : in integer;
fill : in std_logic := '0')
return std_logic_vector;
function BinaryToGray( binary : in std_logic_vector)
return std_logic_vector;
function GrayToBinary( gray : in std_logic_vector)
return std_logic_vector;
-- Parallel Prefix Computation of the OR function
-- Input --> Output
-- 0100 --> 0111
-- 0101 --> 0111
-- 0011 --> 0011
-- 0010 --> 0011
function PpcOr( inp : in std_logic_vector)
return std_logic_vector;
function IntToStdLogic( int : in integer)
return std_logic;
function ReduceOr( vec : in std_logic_vector)
return std_logic;
function ReduceAnd( vec : in std_logic_vector)
return std_logic;
function To01X( inp : in std_logic)
return std_logic;
function To01X( inp : in std_logic_vector)
return std_logic_vector;
end psi_common_logic_pkg;
------------------------------------------------------------------------------
-- Package Body
------------------------------------------------------------------------------
package body psi_common_logic_pkg is
-- *** ZerosVector ***
function ZerosVector(size : in natural) return std_logic_vector is
constant c : std_logic_vector(size-1 downto 0) := (others => '0');
begin
return c;
end function;
-- *** OnesVector ***
function OnesVector(size : in natural) return std_logic_vector is
constant c : std_logic_vector(size-1 downto 0) := (others => '1');
begin
return c;
end function;
-- *** ShiftLeft ***
function ShiftLeft( arg : in std_logic_vector;
bits : in integer;
fill : in std_logic := '0')
return std_logic_vector is
constant argDt : std_logic_vector(arg'high downto 0) := arg;
variable v : std_logic_vector(argDt'range);
begin
if bits < 0 then
return ShiftRight(argDt, -bits, fill);
else
v(v'left downto bits) := argDt(argDt'left-bits downto 0);
v(bits-1 downto 0) := (others => fill);
return v;
end if;
end function;
-- *** ShiftRight ***
function ShiftRight( arg : in std_logic_vector;
bits : in integer;
fill : in std_logic := '0')
return std_logic_vector is
constant argDt : std_logic_vector(arg'high downto 0) := arg;
variable v : std_logic_vector(argDt'range);
begin
if bits < 0 then
return ShiftLeft(argDt, -bits, fill);
else
v(v'left-bits downto 0) := argDt(argDt'left downto bits);
v(v'left downto v'left-bits+1) := (others => fill);
return v;
end if;
end function;
-- *** BinaryToGray ***
function BinaryToGray( binary : in std_logic_vector)
return std_logic_vector is
variable Gray_v : std_logic_vector(binary'range);
begin
Gray_v := binary xor ('0' & binary(binary'left downto 1));
return Gray_v;
end function;
-- *** GrayToBinary ***
function GrayToBinary( gray : in std_logic_vector)
return std_logic_vector is
variable Binary_v : std_logic_vector(gray'range);
begin
Binary_v(Binary_v'left) := gray(gray'left);
for b in gray'left-1 downto 0 loop
Binary_v(b) := gray(b) xor Binary_v(b+1);
end loop;
return Binary_v;
end function;
-- *** PpcOr ***
function PpcOr( inp : in std_logic_vector)
return std_logic_vector is
constant Stages_c : integer := log2ceil(inp'length);
constant Pwr2Width_c : integer := 2**Stages_c;
type StageOut_t is array (natural range <>) of std_logic_vector(Pwr2Width_c-1 downto 0);
variable StageOut_v : StageOut_t(0 to Stages_c);
variable BinCnt_v : unsigned(Pwr2Width_c-1 downto 0);
begin
StageOut_v(0) := (others => '0');
StageOut_v(0)(inp'length-1 downto 0) := inp;
for stage in 0 to Stages_c-1 loop
BinCnt_v := (others => '0');
for idx in 0 to Pwr2Width_c-1 loop
if BinCnt_v(stage) = '0' then
StageOut_v(stage+1)(idx) := StageOut_v(stage)(idx) or StageOut_v(stage)((idx/(2**stage)+1)*2**stage);
else
StageOut_v(stage+1)(idx) := StageOut_v(stage)(idx);
end if;
BinCnt_v := BinCnt_v+1;
end loop;
end loop;
return StageOut_v(Stages_c)(inp'length-1 downto 0);
end function;
function IntToStdLogic( int : in integer)
return std_logic is
begin
if int = 1 then
return '1';
elsif int = 0 then
return '0';
else
return 'X';
end if;
end function;
function ReduceOr( vec : in std_logic_vector)
return std_logic is
variable tmp : std_logic;
begin
tmp := '0';
for i in 0 to vec'high loop
tmp := tmp or vec(i);
end loop;
return tmp;
end function;
function ReduceAnd( vec : in std_logic_vector)
return std_logic is
variable tmp : std_logic;
begin
tmp := '1';
for i in 0 to vec'high loop
tmp := tmp and vec(i);
end loop;
return tmp;
end function;
function To01X( inp : in std_logic)
return std_logic is
begin
case inp is
when '0' | 'L' => return '0';
when '1' | 'H' => return '1';
when others => return 'X';
end case;
end function;
function To01X( inp : in std_logic_vector)
return std_logic_vector is
variable tmp : std_logic_vector(inp'range);
begin
for i in inp'low to inp'high loop
tmp(i) := to01X(inp(i));
end loop;
return tmp;
end function;
end psi_common_logic_pkg;
| gpl-2.0 | 3308e2056091063ce1c57a6099cbcc93 | 0.575978 | 3.149202 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue672/SQR.vhd | 1 | 3,168 | -------------------------------------------------------------------------------
-- walter d. gallegos
-- www.waltergallegos.com
-- Programable Logic & Software
-- Consultoria y Diseno
--
-- Este archivo y documentacion son propiedad intelectual de Walter D. Gallegos
--
-------------------------------------------------------------------------------
-- Autor : WDG
-- Fecha : 2018-10-04
-- Archivo : SQR.vhd
-- Notas :
--
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL, IEEE.NUMERIC_STD.ALL;
ENTITY SQR IS
PORT(
CLOCK : IN std_logic;
DIN : IN std_logic_vector(31 downto 0);
VIN : IN std_logic;
DOUT : OUT std_logic_vector(31 downto 0);
VOUT : OUT std_logic
);
END ENTITY SQR;
ARCHITECTURE REV0 OF SQR IS
CONSTANT busZero : STD_LOGIC_VECTOR(DIN'RANGE) := (OTHERS => '0');
SIGNAL a : UNSIGNED(DIN'RANGE);
SIGNAL c, sub : UNSIGNED(DIN'LEFT*2+1 DOWNTO 0);
SIGNAL i : INTEGER RANGE a'RANGE;
SIGNAL run : STD_LOGIC;
BEGIN
sub <= c - a * a;
Registers : PROCESS(CLOCK)
BEGIN
IF rising_edge(CLOCK) THEN
IF VIN = '1' THEN
i <= a'LEFT; run <= '1';
a <= (a'LEFT => '1', OTHERS => '0'); c <= UNSIGNED(DIN & busZero);
ELSIF run = '1' THEN
IF i > 0 THEN i <= i - 1;
a(i) <= NOT(sub(sub'LEFT)); a(i-1) <= '1';
ELSE
a(i) <= NOT(sub(sub'LEFT));
run <= '0';
END IF;
END IF;
END IF;
END PROCESS Registers;
DOUT <= STD_LOGIC_VECTOR(a);
VOUT <= NOT(run);
END REV0;
--ARCHITECTURE REV1 OF SQR IS
--
-- CONSTANT busZero : STD_LOGIC_VECTOR(17 DOWNTO 0) := (OTHERS => '0');
-- CONSTANT busZero2: STD_LOGIC_VECTOR(DIN'LEFT-18 DOWNTO 0) := (OTHERS => '0');
--
-- SIGNAL a : UNSIGNED(17 DOWNTO 0);
-- SIGNAL c, sub : UNSIGNED(a'LEFT*2+1 DOWNTO 0);
-- SIGNAL i : INTEGER RANGE a'RANGE;
-- SIGNAL run : STD_LOGIC;
--
--BEGIN
--
-- sub <= c - a * a;
--
-- Registers : PROCESS(CLOCK)
-- BEGIN
-- IF rising_edge(CLOCK) THEN
-- IF VIN = '1' THEN
-- i <= a'LEFT; run <= '1';
-- a <= (a'LEFT => '1', OTHERS => '0'); c <= UNSIGNED(DIN(17 DOWNTO 0) & busZero);
-- ELSIF run = '1' THEN
-- IF i > 0 THEN i <= i - 1;
-- a(i) <= NOT(sub(sub'LEFT)); a(i-1) <= '1';
-- ELSE
-- a(i) <= NOT(sub(sub'LEFT));
-- run <= '0';
-- END IF;
-- END IF;
-- END IF;
-- END PROCESS Registers;
-- DOUT <= busZero2 & STD_LOGIC_VECTOR(a);
-- VOUT <= NOT(run);
--
--END REV1; | gpl-2.0 | f474678160c865660985e1738b97db9e | 0.396149 | 3.84466 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_s2mm_sts_strm.vhd | 3 | 38,431 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_sts_strm.vhd.vhd
-- Description: This entity is the AXI Status Stream Interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
library lib_srl_fifo_v1_0_2;
library lib_cdc_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_sts_strm is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Slave AXI Status Stream Data Width
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_ENABLE_SKID : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex5"
-- Target FPGA Device Family
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
s2mm_stop : in std_logic ; --
--
s2mm_rxlength_valid : out std_logic ; --
s2mm_rxlength_clr : in std_logic ; --
s2mm_rxlength : out std_logic_vector --
(C_SG_LENGTH_WIDTH - 1 downto 0) ; --
--
stsstrm_fifo_rden : in std_logic ; --
stsstrm_fifo_empty : out std_logic ; --
stsstrm_fifo_dout : out std_logic_vector --
(C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0); --
--
-- Stream to Memory Map Status Stream Interface --
s_axis_s2mm_sts_tdata : in std_logic_vector --
(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); --
s_axis_s2mm_sts_tkeep : in std_logic_vector --
((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0); --
s_axis_s2mm_sts_tvalid : in std_logic ; --
s_axis_s2mm_sts_tready : out std_logic ; --
s_axis_s2mm_sts_tlast : in std_logic --
);
end axi_dma_s2mm_sts_strm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_sts_strm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Status Stream FIFO Depth
constant STSSTRM_FIFO_DEPTH : integer := 16;
-- Status Stream FIFO Data Count Width (Unsused)
constant STSSTRM_FIFO_CNT_WIDTH : integer := clog2(STSSTRM_FIFO_DEPTH+1);
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal fifo_full : std_logic := '0';
signal fifo_din : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0) := (others => '0');
signal fifo_wren : std_logic := '0';
signal fifo_sinit : std_logic := '0';
signal rxlength_cdc_from : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal rxlength_valid_cdc_from : std_logic := '0';
signal rxlength_valid_trdy : std_logic := '0';
--signal sts_tvalid_re : std_logic := '0';-- CR565502
--signal sts_tvalid_d1 : std_logic := '0';-- CR565502
signal sts_tvalid : std_logic := '0';
signal sts_tready : std_logic := '0';
signal sts_tdata : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal sts_tkeep : std_logic_vector((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sts_tlast : std_logic := '0';
signal m_tvalid : std_logic := '0';
signal m_tready : std_logic := '0';
signal m_tdata : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_tkeep : std_logic_vector((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_tlast : std_logic := '0';
signal tag_stripped : std_logic := '0';
signal mask_tag_write : std_logic := '0';
--signal mask_tag_hold : std_logic := '0';-- CR565502
signal skid_rst : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Primary Clock is synchronous to Secondary Clock therfore
-- instantiate a sync fifo.
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
signal s2mm_stop_d1 : std_logic := '0';
signal s2mm_stop_re : std_logic := '0';
signal sts_rden : std_logic := '0';
signal follower_empty : std_logic := '0';
signal fifo_empty : std_logic := '0';
signal fifo_out : std_logic_vector (C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0) := (others => '0');
begin
-- Generate Synchronous FIFO
-- I_STSSTRM_FIFO : entity lib_srl_fifo_v1_0_2.sync_fifo_fg
-- generic map (
-- C_FAMILY => C_FAMILY ,
-- C_MEMORY_TYPE => USE_LOGIC_FIFOS,
-- C_WRITE_DATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1,
-- C_WRITE_DEPTH => STSSTRM_FIFO_DEPTH ,
-- C_READ_DATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1,
-- C_READ_DEPTH => STSSTRM_FIFO_DEPTH ,
-- C_PORTS_DIFFER => 0,
-- C_HAS_DCOUNT => 1, --req for proper fifo operation
-- C_DCOUNT_WIDTH => STSSTRM_FIFO_CNT_WIDTH,
-- C_HAS_ALMOST_FULL => 0,
-- C_HAS_RD_ACK => 0,
-- C_HAS_RD_ERR => 0,
-- C_HAS_WR_ACK => 0,
-- C_HAS_WR_ERR => 0,
-- C_RD_ACK_LOW => 0,
-- C_RD_ERR_LOW => 0,
-- C_WR_ACK_LOW => 0,
-- C_WR_ERR_LOW => 0,
-- C_PRELOAD_REGS => 1,-- 1 = first word fall through
-- C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
-- -- C_USE_EMBEDDED_REG => 1 -- 0 ;
-- )
-- port map (
--
-- Clk => m_axi_sg_aclk ,
-- Sinit => fifo_sinit ,
-- Din => fifo_din ,
-- Wr_en => fifo_wren ,
-- Rd_en => stsstrm_fifo_rden ,
-- Dout => stsstrm_fifo_dout ,
-- Full => fifo_full ,
-- Empty => stsstrm_fifo_empty ,
-- Almost_full => open ,
-- Data_count => open ,
-- Rd_ack => open ,
-- Rd_err => open ,
-- Wr_ack => open ,
-- Wr_err => open
--
-- );
I_UPDT_STS_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map (
C_DWIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1,
C_DEPTH => 16 ,
C_FAMILY => C_FAMILY
)
port map (
Clk => m_axi_sg_aclk ,
Reset => fifo_sinit ,
FIFO_Write => fifo_wren ,
Data_In => fifo_din ,
FIFO_Read => sts_rden, --sts_queue_rden ,
Data_Out => fifo_out, --sts_queue_dout ,
FIFO_Empty => fifo_empty, --sts_queue_empty ,
FIFO_Full => fifo_full ,
Addr => open
);
sts_rden <= (not fifo_empty) and follower_empty;
stsstrm_fifo_empty <= follower_empty;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (fifo_sinit = '1' or stsstrm_fifo_rden = '1') then
follower_empty <= '1';
elsif (sts_rden = '1') then
follower_empty <= '0';
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (fifo_sinit = '1') then
stsstrm_fifo_dout <= (others => '0');
elsif (sts_rden = '1') then
stsstrm_fifo_dout <= fifo_out;
end if;
end if;
end process;
fifo_sinit <= not m_axi_sg_aresetn;
fifo_din <= sts_tlast & sts_tdata;
fifo_wren <= sts_tvalid and not fifo_full and not rxlength_valid_cdc_from and not mask_tag_write;
sts_tready <= not fifo_sinit and not fifo_full and not rxlength_valid_cdc_from;
-- CR565502 - particular throttle condition caused masking of tag write to not occur
-- simplified logic will provide more robust handling of tag write mask
-- -- Create register delay of status tvalid in order to create a
-- -- rising edge pulse. note xx_re signal will hold at 1 if
-- -- fifo full on rising edge of tvalid.
-- REG_TVALID : process(axi_prmry_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- sts_tvalid_d1 <= '0';
-- elsif(fifo_full = '0')then
-- sts_tvalid_d1 <= sts_tvalid;
-- end if;
-- end if;
-- end process REG_TVALID;
--
-- -- rising edge on tvalid used to gate off status tag from being
-- -- writen into fifo.
-- sts_tvalid_re <= sts_tvalid and not sts_tvalid_d1;
REG_TAG_STRIPPED : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
tag_stripped <= '0';
-- Reset on write of last word
elsif(fifo_wren = '1' and sts_tlast = '1')then
tag_stripped <= '0';
-- Set on beginning of new status stream
elsif(sts_tready = '1' and sts_tvalid = '1')then
tag_stripped <= '1';
end if;
end if;
end process REG_TAG_STRIPPED;
-- CR565502 - particular throttle condition caused masking of tag write to not occur
-- simplified logic will provide more robust handling of tag write mask
-- REG_MASK_TAG : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- mask_tag_hold <= '0';
-- elsif((sts_tvalid_re = '1' and tag_stripped = '0')
-- or (fifo_wren = '1' and sts_tlast = '1'))then
-- mask_tag_hold <= '1';
-- elsif(tag_stripped = '1')then
-- mask_tag_hold <= '0';
-- end if;
-- end if;
-- end process;
--
-- -- Mask TAG if not already masked and rising edge of tvalid
-- mask_tag_write <= not tag_stripped and (sts_tvalid_re or mask_tag_hold);
mask_tag_write <= not tag_stripped and sts_tready and sts_tvalid;
-- Generate logic to capture receive length when Use Receive Length is
-- enabled
GEN_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate
begin
-- Register receive length on assertion of last and valid
-- Mark rxlength as valid for higher processes
REG_RXLENGTH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_rxlength_clr = '1')then
rxlength_cdc_from <= (others => '0');
rxlength_valid_cdc_from <= '0';
elsif(sts_tlast = '1' and sts_tvalid = '1' and sts_tready = '1')then
rxlength_cdc_from <= sts_tdata(C_SG_LENGTH_WIDTH-1 downto 0);
rxlength_valid_cdc_from <= '1';
end if;
end if;
end process REG_RXLENGTH;
s2mm_rxlength_valid <= rxlength_valid_cdc_from;
s2mm_rxlength <= rxlength_cdc_from;
end generate GEN_STS_APP_LENGTH;
-- Do NOT generate logic to capture receive length when option disabled
GEN_NO_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate
begin
s2mm_rxlength_valid <= '0';
s2mm_rxlength <= (others => '0');
end generate GEN_NO_STS_APP_LENGTH;
-- register stop to create re pulse
REG_STOP : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
s2mm_stop_d1 <= '0';
else
s2mm_stop_d1 <= s2mm_stop;
end if;
end if;
end process REG_STOP;
s2mm_stop_re <= s2mm_stop and not s2mm_stop_d1;
skid_rst <= not m_axi_sg_aresetn;
ENABLE_SKID : if C_ENABLE_SKID = 1 generate
begin
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
STS_SKID_BUF_I : entity axi_dma_v7_1_9.axi_dma_skid_buf
generic map(
C_WDATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => m_axi_sg_aclk ,
ARST => skid_rst ,
skid_stop => s2mm_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => s_axis_s2mm_sts_tvalid ,
S_READY => s_axis_s2mm_sts_tready ,
S_Data => s_axis_s2mm_sts_tdata ,
S_STRB => s_axis_s2mm_sts_tkeep ,
S_Last => s_axis_s2mm_sts_tlast ,
-- Master Side (Stream Data Output
M_VALID => sts_tvalid ,
M_READY => sts_tready ,
M_Data => sts_tdata ,
M_STRB => sts_tkeep ,
M_Last => sts_tlast
);
end generate ENABLE_SKID;
DISABLE_SKID : if C_ENABLE_SKID = 0 generate
begin
sts_tvalid <= s_axis_s2mm_sts_tvalid;
s_axis_s2mm_sts_tready <= sts_tready;
sts_tdata <= s_axis_s2mm_sts_tdata;
sts_tkeep <= s_axis_s2mm_sts_tkeep;
sts_tlast <= s_axis_s2mm_sts_tlast;
end generate DISABLE_SKID;
end generate GEN_SYNC_FIFO;
-- Primary Clock is asynchronous to Secondary Clock therfore
-- instantiate an async fifo.
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
ATTRIBUTE async_reg : STRING;
signal s2mm_stop_reg : std_logic := '0'; -- CR605883
signal p_s2mm_stop_d1_cdc_tig : std_logic := '0';
signal p_s2mm_stop_d2 : std_logic := '0';
signal p_s2mm_stop_d3 : std_logic := '0';
signal p_s2mm_stop_re : std_logic := '0';
--ATTRIBUTE async_reg OF p_s2mm_stop_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_s2mm_stop_d2 : SIGNAL IS "true";
begin
-- Generate Asynchronous FIFO
I_STSSTRM_FIFO : entity axi_dma_v7_1_9.axi_dma_afifo_autord
generic map(
C_DWIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1 ,
-- C_DEPTH => STSSTRM_FIFO_DEPTH ,
-- C_CNT_WIDTH => STSSTRM_FIFO_CNT_WIDTH ,
C_DEPTH => 15 ,
C_CNT_WIDTH => 4 ,
C_USE_BLKMEM => USE_LOGIC_FIFOS ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => fifo_sinit ,
AFIFO_Wr_clk => axi_prmry_aclk ,
AFIFO_Wr_en => fifo_wren ,
AFIFO_Din => fifo_din ,
AFIFO_Rd_clk => m_axi_sg_aclk ,
AFIFO_Rd_en => stsstrm_fifo_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => open ,
AFIFO_Dout => stsstrm_fifo_dout ,
AFIFO_Full => fifo_full ,
AFIFO_Empty => stsstrm_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
fifo_sinit <= not p_reset_n;
fifo_din <= sts_tlast & sts_tdata;
fifo_wren <= sts_tvalid -- valid data
and not fifo_full -- fifo has room
and not rxlength_valid_trdy --rxlength_valid_cdc_from -- not holding a valid length
and not mask_tag_write; -- not masking off tag word
sts_tready <= not fifo_sinit and not fifo_full and not rxlength_valid_trdy; --rxlength_valid_cdc_from;
-- CR565502 - particular throttle condition caused masking of tag write to not occur
-- simplified logic will provide more robust handling of tag write mask
-- -- Create register delay of status tvalid in order to create a
-- -- rising edge pulse. note xx_re signal will hold at 1 if
-- -- fifo full on rising edge of tvalid.
-- REG_TVALID : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- sts_tvalid_d1 <= '0';
-- elsif(fifo_full = '0')then
-- sts_tvalid_d1 <= sts_tvalid;
-- end if;
-- end if;
-- end process REG_TVALID;
-- -- rising edge on tvalid used to gate off status tag from being
-- -- writen into fifo.
-- sts_tvalid_re <= sts_tvalid and not sts_tvalid_d1;
REG_TAG_STRIPPED : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
tag_stripped <= '0';
-- Reset on write of last word
elsif(fifo_wren = '1' and sts_tlast = '1')then
tag_stripped <= '0';
-- Set on beginning of new status stream
elsif(sts_tready = '1' and sts_tvalid = '1')then
tag_stripped <= '1';
end if;
end if;
end process REG_TAG_STRIPPED;
-- CR565502 - particular throttle condition caused masking of tag write to not occur
-- simplified logic will provide more robust handling of tag write mask
-- REG_MASK_TAG : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- mask_tag_hold <= '0';
-- elsif(tag_stripped = '1')then
-- mask_tag_hold <= '0';
--
-- elsif(sts_tvalid_re = '1'
-- or (fifo_wren = '1' and sts_tlast = '1'))then
-- mask_tag_hold <= '1';
-- end if;
-- end if;
-- end process;
--
-- -- Mask TAG if not already masked and rising edge of tvalid
-- mask_tag_write <= not tag_stripped and (sts_tvalid_re or mask_tag_hold);
mask_tag_write <= not tag_stripped and sts_tready and sts_tvalid;
-- Generate logic to capture receive length when Use Receive Length is
-- enabled
GEN_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate
signal rxlength_clr_d1_cdc_tig : std_logic := '0';
signal rxlength_clr_d2 : std_logic := '0';
signal rxlength_d1_cdc_to : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal rxlength_d2 : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal rxlength_valid_d1_cdc_to : std_logic := '0';
signal rxlength_valid_d2_cdc_from : std_logic := '0';
signal rxlength_valid_d3 : std_logic := '0';
signal rxlength_valid_d4 : std_logic := '0';
signal rxlength_valid_d1_back_cdc_to, rxlength_valid_d2_back : std_logic := '0';
ATTRIBUTE async_reg : STRING;
--ATTRIBUTE async_reg OF rxlength_d1_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF rxlength_d2 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF rxlength_valid_d1_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF rxlength_valid_d1_back_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF rxlength_valid_d2_back : SIGNAL IS "true";
begin
-- Double register from secondary clock domain to primary
S2P_CLK_CROSS : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_rxlength_clr,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => rxlength_clr_d2,
scndry_vect_out => open
);
-- S2P_CLK_CROSS : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- if(p_reset_n = '0')then
-- rxlength_clr_d1_cdc_tig <= '0';
-- rxlength_clr_d2 <= '0';
-- else
-- rxlength_clr_d1_cdc_tig <= s2mm_rxlength_clr;
-- rxlength_clr_d2 <= rxlength_clr_d1_cdc_tig;
-- end if;
-- end if;
-- end process S2P_CLK_CROSS;
-- Register receive length on assertion of last and valid
-- Mark rxlength as valid for higher processes
TRDY_RXLENGTH : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0' or rxlength_clr_d2 = '1')then
rxlength_valid_trdy <= '0';
elsif(sts_tlast = '1' and sts_tvalid = '1' and sts_tready = '1')then
rxlength_valid_trdy <= '1';
end if;
end if;
end process TRDY_RXLENGTH;
REG_RXLENGTH : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0') then -- or rxlength_clr_d2 = '1')then
rxlength_cdc_from <= (others => '0');
rxlength_valid_cdc_from <= '0';
elsif(sts_tlast = '1' and sts_tvalid = '1' and sts_tready = '1')then
rxlength_cdc_from <= sts_tdata(C_SG_LENGTH_WIDTH-1 downto 0);
rxlength_valid_cdc_from <= '1';
elsif (rxlength_valid_d2_back = '1') then
rxlength_valid_cdc_from <= '0';
end if;
end if;
end process REG_RXLENGTH;
SYNC_RXLENGTH : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => rxlength_valid_d2_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => rxlength_valid_d2_back,
scndry_vect_out => open
);
-- SYNC_RXLENGTH : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- if(p_reset_n = '0') then -- or rxlength_clr_d2 = '1')then
--
-- rxlength_valid_d1_back_cdc_to <= '0';
-- rxlength_valid_d2_back <= '0';
-- else
-- rxlength_valid_d1_back_cdc_to <= rxlength_valid_d2_cdc_from;
-- rxlength_valid_d2_back <= rxlength_valid_d1_back_cdc_to;
--
-- end if;
-- end if;
-- end process SYNC_RXLENGTH;
-- Double register from primary clock domain to secondary
P2S_CLK_CROSS : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => rxlength_valid_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => rxlength_valid_d2_cdc_from,
scndry_vect_out => open
);
P2S_CLK_CROSS2 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_SG_LENGTH_WIDTH,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => rxlength_cdc_from,
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => rxlength_d2
);
P2S_CLK_CROSS1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0') then -- or s2mm_rxlength_clr = '1') then
-- rxlength_d1_cdc_to <= (others => '0');
-- rxlength_d2 <= (others => '0');
-- rxlength_valid_d1_cdc_to <= '0';
-- rxlength_valid_d2_cdc_from <= '0';
rxlength_valid_d3 <= '0';
else
-- rxlength_d1_cdc_to <= rxlength_cdc_from;
-- rxlength_d2 <= rxlength_d1_cdc_to;
-- rxlength_valid_d1_cdc_to <= rxlength_valid_cdc_from;
-- rxlength_valid_d2_cdc_from <= rxlength_valid_d1_cdc_to;
rxlength_valid_d3 <= rxlength_valid_d2_cdc_from;
end if;
end if;
end process P2S_CLK_CROSS1;
process (m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_rxlength_clr = '1')then
rxlength_valid_d4 <= '0';
elsif (rxlength_valid_d3 = '1' and rxlength_valid_d2_cdc_from = '0') then
rxlength_valid_d4 <= '1';
end if;
end if;
end process;
s2mm_rxlength <= rxlength_d2;
-- s2mm_rxlength_valid <= rxlength_valid_d2;
s2mm_rxlength_valid <= rxlength_valid_d4;
end generate GEN_STS_APP_LENGTH;
-- Do NOT generate logic to capture receive length when option disabled
GEN_NO_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate
s2mm_rxlength_valid <= '0';
s2mm_rxlength <= (others => '0');
end generate GEN_NO_STS_APP_LENGTH;
-- CR605883
-- Register stop to provide pure FF output for synchronizer
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_stop_reg <= '0';
else
s2mm_stop_reg <= s2mm_stop;
end if;
end if;
end process REG_STOP;
-- double register s2mm error into primary clock domain
REG_ERR2PRMRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_stop_reg,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_s2mm_stop_d2,
scndry_vect_out => open
);
REG_ERR2PRMRY1 : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
-- p_s2mm_stop_d1_cdc_tig <= '0';
-- p_s2mm_stop_d2 <= '0';
p_s2mm_stop_d3 <= '0';
else
--p_s2mm_stop_d1_cdc_tig <= s2mm_stop; -- CR605883
-- p_s2mm_stop_d1_cdc_tig <= s2mm_stop_reg;
-- p_s2mm_stop_d2 <= p_s2mm_stop_d1_cdc_tig;
p_s2mm_stop_d3 <= p_s2mm_stop_d2;
end if;
end if;
end process REG_ERR2PRMRY1;
p_s2mm_stop_re <= p_s2mm_stop_d2 and not p_s2mm_stop_d3;
skid_rst <= not p_reset_n;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
STS_SKID_BUF_I : entity axi_dma_v7_1_9.axi_dma_skid_buf
generic map(
C_WDATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => axi_prmry_aclk ,
ARST => skid_rst ,
skid_stop => p_s2mm_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => s_axis_s2mm_sts_tvalid ,
S_READY => s_axis_s2mm_sts_tready ,
S_Data => s_axis_s2mm_sts_tdata ,
S_STRB => s_axis_s2mm_sts_tkeep ,
S_Last => s_axis_s2mm_sts_tlast ,
-- Master Side (Stream Data Output
M_VALID => sts_tvalid ,
M_READY => sts_tready ,
M_Data => sts_tdata ,
M_STRB => sts_tkeep ,
M_Last => sts_tlast
);
end generate GEN_ASYNC_FIFO;
end implementation;
| gpl-3.0 | 198a3481d576c0559176b9de79e73497 | 0.446931 | 3.997815 | false | false | false | false |
tgingold/ghdl | testsuite/synth/psl01/restrict1.vhdl | 1 | 531 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity restrict1 is
port (clk, rst: std_logic;
cnt : out unsigned(3 downto 0));
end restrict1;
architecture behav of restrict1 is
signal val : unsigned (3 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
val <= (others => '0');
else
val <= val + 1;
end if;
end if;
end process;
cnt <= val;
--psl default clock is rising_edge (clk);
--psl restrict {rst; (not rst)[*]};
end behav;
| gpl-2.0 | ae78fe8b38a65d9df09b251e6b9a9f34 | 0.623352 | 3.198795 | false | false | false | false |
nickg/nvc | test/regress/issue467.vhd | 1 | 1,057 | entity issue467 is
end entity;
architecture test of issue467 is
type int_array is array (natural range <>) of integer_vector;
function sum_all (x : int_array) return integer is
variable result : integer := 0;
begin
for i in x'range loop
for j in x(i)'range loop
result := result + x(i)(j);
end loop;
end loop;
return result;
end function;
function get_slice (x : int_array; l, r : natural) return int_array is
begin
return x(l to r);
end function;
signal s1 : int_array(1 to 3)(1 to 2) := ( (1, 2), (3, 4), (5, 6) );
begin
p1: process is
begin
assert sum_all(s1) = 21;
assert get_slice(s1, 1, 2) = ( (1, 2), (3, 4) );
assert get_slice(s1, 3, 3) = ( 0 => (5, 6) );
assert get_slice(s1, 3, 0) = ( 1 to 0 => (1, 1) );
assert get_slice(s1, 1, 2)(2) = ( (3, 4) );
s1(2)(2) <= 10;
wait for 1 ns;
assert sum_all(s1) = 27;
wait;
end process;
end architecture;
| gpl-3.0 | 27e6c10068d13fae29ce11a53af1391d | 0.512772 | 3.155224 | false | false | false | false |
nickg/nvc | test/parse/generate.vhd | 1 | 1,075 | entity gg is end entity;
architecture aa of gg is
constant foo, bar : boolean := false;
signal x, g, f : integer;
constant h : integer := 6;
type text is file of string;
file output : text open WRITE_MODE is "STD_OUTPUT";
begin
g1: if foo generate
signal x : integer;
begin
x <= 5;
end generate;
g2: if bar generate
g2a: if h < 5 generate
g <= 7;
end generate;
end generate;
g3: for i in 1 to 40 generate
signal x : integer;
begin
f <= h;
end generate;
g4: for i in natural'range generate
end generate;
g5: for i in integer'range generate
begin
end generate;
g6: for i in 1 to 3 generate
component sub_ent is
port (val: out natural);
end component sub_ent; -- OK
begin
end generate;
g7: if true generate
procedure doit is -- OK
begin
write(OUTPUT, "OK." & LF);
end procedure doit;
begin
end generate g7;
end architecture;
| gpl-3.0 | 33f82391d5b03533c41f55c4cf341baf | 0.550698 | 4.026217 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue18/fum.vhdl | 2 | 1,689 | package fum is
type fie is protected
impure function foo return integer;
impure function foo(input: real) return integer; -- 4
impure function foo return integer_vector;
impure function foo (input: real) return integer_vector; -- 6
impure function foo (input: integer) return integer;
impure function foo(input: integer) return integer_vector;
end protected fie;
end package;
package body fum is
type fie is protected body
variable answer: integer := 42;
impure function foo return integer is
begin
return answer;
end;
impure function foo(input:real) return integer is
begin
return integer(input) + answer;
end;
impure function foo return integer_vector is
variable conv_vector: integer_vector (0 to 1);
begin
conv_vector(0) := answer;
conv_vector(1) := 0;
return conv_vector;
end;
impure function foo (input: real) return integer_vector is
variable conv_vector: integer_vector (0 to 1);
begin
conv_vector(0) := integer(input) + answer;
conv_vector(1) := 0;
end;
impure function foo (input: integer) return integer is
begin
return answer + input;
end;
impure function foo(input: integer) return integer_vector is
variable conv_vector: integer_vector (0 to 1);
begin
conv_vector(0) := input + answer;
conv_vector(1) := 0;
return conv_vector;
end;
end protected body fie;
end package body;
| gpl-2.0 | a73df8000e8a27697b5275532ae17674 | 0.583185 | 4.691667 | false | false | false | false |
nickg/nvc | test/regress/elab26.vhd | 1 | 1,976 | -- https://github.com/ghdl/ghdl/issues/1842
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
package signal_pkg is
type t_sigs is array (natural range <>) of std_logic_vector(7 downto 0);
type t_signals is record
dta: t_sigs(0 to 7);
end record;
end signal_pkg;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.signal_pkg.all;
entity source is
generic (
instance_number : integer := 0);
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
outs : out t_signals
);
end entity source;
architecture sim of source is
signal toggle : std_logic := '0';
begin -- architecture rtl
process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
outs.dta(instance_number) <= (others => '0');
else
toggle <= not toggle;
if toggle='0' then
outs.dta(instance_number) <= (others => '0');
end if;
outs.dta(instance_number) <= std_logic_vector(to_unsigned(instance_number + 2, 8));
end if;
end if;
end process;
end architecture sim;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.signal_pkg.all;
entity elab26 is
end elab26;
architecture beh1 of elab26 is
signal clk : std_logic := '0';
signal rst_n : std_logic := '0';
signal test : t_signals;
begin -- beh1
clk <= not clk after 10 ns when now < 50 ns;
process
begin
rst_n <= '0';
wait for 30 ns;
rst_n <= '1';
wait;
end process;
g1: for i in 0 to 7 generate
source_1: entity work.source
generic map (
instance_number => i)
port map (
rst_n_i => rst_n,
clk_i => clk,
outs => test);
end generate g1;
check_p: process is
begin
wait for 50 ns;
for i in 0 to 7 loop
assert test.dta(i) = (0 to 7 => 'U');
end loop;
wait;
end process;
end beh1;
| gpl-3.0 | 714b98e491c1996e033ce63798e10c52 | 0.602227 | 3.146497 | false | false | false | false |
nickg/nvc | test/parse/issue458.vhd | 1 | 395 | package test is
constant C_ZERO : bit_vector(4 downto 0) := 5d"0";
constant C_ONE : bit_vector(4 downto 0) := 5d"1";
constant C_TWO : bit_vector(4 downto 0) := 5d"2";
constant C_THREE : bit_vector(4 downto 0) := 5d"3";
constant C_TWENTY : bit_vector(4 downto 0) := 5d"20";
end package test;
| gpl-3.0 | 26d8e6ca085cfdfd7f7338bf15b5603a | 0.491139 | 3.434783 | false | true | false | false |
tgingold/ghdl | testsuite/synth/synth104/tb_case02.vhdl | 1 | 732 | entity tb_case02 is
end tb_case02;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_case02 is
signal sel : unsigned (3 downto 0);
signal det : std_logic_vector (1 downto 0);
begin
dut: entity work.case02
port map (sel, det);
process
begin
sel <= "0000";
wait for 1 ns;
assert det = "00" severity failure;
sel <= "0010";
wait for 1 ns;
assert det = "01" severity failure;
sel <= "0110";
wait for 1 ns;
assert det = "01" severity failure;
sel <= "1010";
wait for 1 ns;
assert det = "10" severity failure;
sel <= "1111";
wait for 1 ns;
assert det = "11" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 1476d1df5fa765ac7f5732fc679b2cce | 0.61612 | 3.357798 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/scalar-data/inline_01a.vhd | 4 | 15,616 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_01a is
end entity inline_01a;
----------------------------------------------------------------
architecture test of inline_01a is
begin
section_1_a : process is
-- code from book:
constant number_of_bytes : integer := 4;
constant number_of_bits : integer := 8 * number_of_bytes;
constant e : real := 2.718281828;
constant prop_delay : time := 3 ns;
constant q : real := 1.60218E-19;
constant resistivity : real := 2.5E5;
--
variable index : integer := 0;
variable temperature : real;
variable start, finish : time := 0 ns;
-- end of code from book
begin
wait;
end process section_1_a;
----------------
section_1_b : process is
-- code from book:
variable start : time := 0 ns;
variable finish : time := 0 ns;
-- end of code from book
variable program_counter : integer;
variable index : integer;
variable resonance_frequency : real;
constant L, C : real := 0.0;
begin
-- code from book:
program_counter := 0;
index := index + 1;
resonance_frequency := L * C;
-- end of code from book
wait;
end process section_1_b;
----------------
section_2_a : process is
-- code from book:
type apples is range 0 to 100;
type oranges is range 0 to 100;
--
type day_of_month is range 0 to 31;
type year is range 0 to 2100;
variable today : day_of_month := 9;
variable start_year : year := 1987;
--
constant number_of_bits : integer := 32;
type bit_index is range 0 to number_of_bits - 1;
--
type set_index_range is range 21 downto 11;
type mode_pos_range is range 5 to 7;
variable set_index : set_index_range;
variable mode_pos : mode_pos_range;
--
type input_level is range -10.0 to +10.0;
type probability is range 0.0 to 1.0;
--
variable input_A : input_level;
-- end of code from book
begin
-- code from book:
-- error: Incompatible types for assignment
-- start_year := today;
-- end of code from book
wait;
end process section_2_a;
----------------
section_2_b : process is
-- code from book:
type resistance is range 0 to 1E9
units
ohm;
end units resistance;
-- end of code from book
begin
wait;
end process section_2_b;
----------------
section_2_c : process is
-- code from book:
type resistance is range 0 to 1E9
units
ohm;
kohm = 1000 ohm;
Mohm = 1000 kohm;
end units resistance;
-- end of code from book
begin
wait;
end process section_2_c;
----------------
section_2_d : process is
-- code from book:
type length is range 0 to 1E9
units
um; -- primary unit: micron
mm = 1000 um; -- metric units
m = 1000 mm;
inch = 25400 um; -- imperial units
foot = 12 inch;
end units length;
-- end of code from book
begin
wait;
end process section_2_d;
----------------
section_2_e : process is
-- code from book:
-- type time is range implementation_defined
type time is range integer'low to integer'high
units
fs;
ps = 1000 fs;
ns = 1000 ps;
us = 1000 ns;
ms = 1000 us;
sec = 1000 ms;
min = 60 sec;
hr = 60 min;
end units;
-- end of code from book
begin
wait;
end process section_2_e;
----------------
section_2_f : process is
-- code from book:
type transistor_region is (linear, saturation);
--
type octal_digit is ('0', '1', '2', '3', '4', '5', '6', '7');
--
variable transistor_state : transistor_region;
variable last_digit : octal_digit := '0';
--
type logic_level is (unknown, low, undriven, high);
variable control : logic_level;
type water_level is (dangerously_low, low, ok);
variable water_sensor : water_level;
-- end of code from book
begin
-- code from book:
transistor_state := linear;
last_digit := '7';
--
control := low;
water_sensor := low;
-- end of code from book
wait;
end process section_2_f;
----------------
section_2_g : process is
-- code from book:
type severity_level is (note, warning, error, failure);
type file_open_status is (open_ok, status_error, name_error, mode_error);
type file_open_kind is (read_mode, write_mode, append_mode);
type domain_type is (quiescent_domain, time_domain, frequency_domain);
-- end of code from book
begin
wait;
end process section_2_g;
----------------
section_2_g1 : process is
-- code from book:
type character is (
nul, soh, stx, etx, eot, enq, ack, bel,
bs, ht, lf, vt, ff, cr, so, si,
dle, dc1, dc2, dc3, dc4, nak, syn, etb,
can, em, sub, esc, fsp, gsp, rsp, usp,
' ', '!', '"', '#', '$', '%', '&', ''',
'(', ')', '*', '+', ',', '-', '.', '/',
'0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', ':', ';', '<', '=', '>', '?',
'@', 'A', 'B', 'C', 'D', 'E', 'F', 'G',
'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O',
'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W',
'X', 'Y', 'Z', '[', '\', ']', '^', '_',
'`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '{', '|', '}', '~', DEL,
c128, c129, c130, c131, c132, c133, c134, c135,
c136, c137, c138, c139, c140, c141, c142, c143,
c144, c145, c146, c147, c148, c149, c150, c151,
c152, c153, c154, c155, c156, c157, c158, c159,
' ', '¡', '¢', '£', '¤', '¥', '¦', '§',
'¨', '©', 'ª', '«', '¬', '', '®', '¯',
'°', '±', '²', '³', '´', 'µ', '¶', '·',
'¸', '¹', 'º', '»', '¼', '½', '¾', '¿',
'À', 'Á', 'Â', 'Ã', 'Ä', 'Å', 'Æ', 'Ç',
'È', 'É', 'Ê', 'Ë', 'Ì', 'Í', 'Î', 'Ï',
'Ð', 'Ñ', 'Ò', 'Ó', 'Ô', 'Õ', 'Ö', '×',
'Ø', 'Ù', 'Ú', 'Û', 'Ü', 'Ý', 'Þ', 'ß',
'à', 'á', 'â', 'ã', 'ä', 'å', 'æ', 'ç',
'è', 'é', 'ê', 'ë', 'ì', 'í', 'î', 'ï',
'ð', 'ñ', 'ò', 'ó', 'ô', 'õ', 'ö', '÷',
'ø', 'ù', 'ú', 'û', 'ü', 'ý', 'þ', 'ÿ');
-- end of code from book
begin
wait;
end process section_2_g1;
----------------
section_2_h : process is
-- code from book:
variable cmd_char, terminator : character;
-- end of code from book
begin
-- code from book:
cmd_char := 'P';
terminator := cr;
-- end of code from book
wait;
end process section_2_h;
----------------
section_2_i : process is
-- code from book:
type boolean is (false, true);
--
type bit is ('0', '1');
-- end of code from book
begin
wait;
end process section_2_i;
----------------
section_2_j : process is
variable write_enable_n, select_reg_n, write_reg_n : bit;
begin
-- code from book:
write_reg_n := not ( not write_enable_n and not select_reg_n );
-- end of code from book
wait;
end process section_2_j;
----------------
section_2_k : process is
-- code from book:
type std_ulogic is ( 'U', -- Uninitialized
'X', -- Forcing Unknown
'0', -- Forcing zero
'1', -- Forcing one
'Z', -- High Impedance
'W', -- Weak Unknown
'L', -- Weak zero
'H', -- Weak one
'-' ); -- Don't care
-- end of code from book
begin
wait;
end process section_2_k;
----------------
section_3_a : process is
-- code from book:
subtype small_int is integer range -128 to 127;
--
variable deviation : small_int;
variable adjustment : integer;
--
subtype bit_index is integer range 31 downto 0;
-- end of code from book
begin
deviation := 0;
adjustment := 0;
-- code from book:
deviation := deviation + adjustment;
-- end of code from book
wait;
end process section_3_a;
----------------
section_3_b : process is
constant highest_integer : integer := integer'high;
constant highest_time : time := time'high;
-- code from book:
subtype pressure is real tolerance "default_pressure";
--
subtype natural is integer range 0 to highest_integer;
subtype positive is integer range 1 to highest_integer;
--
subtype delay_length is time range 0 fs to highest_time;
-- end of code from book
begin
wait;
end process section_3_b;
----------------
section_3_c : process is
-- code from book:
type logic_level is (unknown, low, undriven, high);
type transistor_state is (unknown, unsaturated, saturated);
--
subtype valid_level is logic_level range low to high;
-- end of code from book
begin
wait;
end process section_3_c;
----------------
section_4_a : block is
-- code from book:
subtype voltage is real tolerance "default_voltage";
subtype current is real tolerance "default_current";
nature electrical is
voltage across
current through
electrical_ref reference;
--
terminal in_plus, in_minus, preamp_out : electrical;
--
quantity signal_level across in_plus to in_minus;
quantity output_level across output_current through preamp_out;
-- end of code from book
begin
end block section_4_a;
----------------
section_4_b : block is
-- code from book:
subtype temperature is real tolerance "default_temperature";
subtype heat_flow is real tolerance "default_heat_flow";
subtype cryo_temp is real tolerance "default_temperature";
subtype cryo_flow is real tolerance "default_heat_flow";
nature thermal is
temperature across
heat_flow through
thermal_ref reference;
nature cryogenic is
cryo_temp across
cryo_flow through
cryo_ref reference;
--
subtype illuminance is real tolerance "default_illuminance";
subtype optic_flux is real tolerance "default_optic_flux";
nature radiant is
illuminance across
optic_flux through
radiant_ref reference;
-- end of code from book
begin
end block section_4_b;
----------------
section_4_c : block is
subtype voltage is real tolerance "default_voltage";
subtype current is real tolerance "default_current";
nature electrical is
voltage across
current through
electrical_ref reference;
-- code from book:
subnature coarse_electrical is electrical
tolerance "coarse_voltage" across "coarse_current" through;
terminal supply_plus, supply_minus : coarse_electrical;
terminal bias : electrical;
quantity bias_pullup_v across supply_plus to bias;
quantity bias_pulldown_v across bias to supply_minus;
-- end of code from book
begin
end block section_4_c;
----------------
section_5_a : process is
-- code from book:
type resistance is range 0 to 1E9
units
ohm;
kohm = 1000 ohm;
Mohm = 1000 kohm;
end units resistance;
type set_index_range is range 21 downto 11;
type logic_level is (unknown, low, undriven, high);
-- end of code from book
begin
-- output from vsim: "2000"
report resistance'image(2 kohm);
-- code from book:
assert resistance'left = 0 ohm;
assert resistance'right = 1E9 ohm;
assert resistance'low = 0 ohm;
assert resistance'high = 1E9 ohm;
assert resistance'ascending = true;
assert resistance'image(2 kohm) = "2000 ohm";
assert resistance'value("5 Mohm") = 5_000_000 ohm;
assert set_index_range'left = 21;
assert set_index_range'right = 11;
assert set_index_range'low = 11;
assert set_index_range'high = 21;
assert set_index_range'ascending = false;
assert set_index_range'image(14) = "14";
assert set_index_range'value("20") = 20;
assert logic_level'left = unknown;
assert logic_level'right = high;
assert logic_level'low = unknown;
assert logic_level'high = high;
assert logic_level'ascending = true;
assert logic_level'image(undriven) = "undriven";
assert logic_level'value("Low") = low;
--
assert logic_level'pos(unknown) = 0;
assert logic_level'val(3) = high;
assert logic_level'succ(unknown) = low;
assert logic_level'pred(undriven) = low;
--
assert time'pos(4 ns) = 4_000_000;
-- end of code from book
wait;
end process section_5_a;
----------------
section_5_b : process is
-- code from book:
type length is range integer'low to integer'high
units
mm;
end units length;
type area is range integer'low to integer'high
units
square_mm;
end units area;
--
variable L1, L2 : length;
variable A : area;
-- end of code from book
begin
-- code from book:
-- error: No feasible entries for infix op: "*"
-- A := L1 * L2; -- this is incorrect
--
A := area'val( length'pos(L1) * length'pos(L2) );
-- end of code from book
wait;
end process section_5_b;
----------------
section_5_c : process is
-- code from book:
subtype voltage is real tolerance "default_voltage";
subtype high_current is real tolerance "coarse_current";
--
type gear is (unknown, park, reverse, neutral, first, second, third, fourth, fifth);
subtype forward is gear range first to fifth;
-- end of code from book
begin
-- code from book:
assert voltage'tolerance = "default_voltage";
assert high_current'tolerance = "coarse_current";
--
assert forward'base'left = unknown;
assert forward'base'succ(reverse) = neutral;
-- end of code from book
wait;
end process section_5_c;
----------------
section_5_d : block is
-- code from book:
subtype displacement is real tolerance "default_displacement";
subtype force is real tolerance "default_force";
nature translational is
displacement across
force through
translational_ref reference;
--
quantity qdisp : translational'across; -- declares quantity of type displacement
quantity qforce : translational'through; -- declares quantity of type force
-- end of code from book
begin
end block section_5_d;
end architecture test;
| gpl-2.0 | 4f4922ac74d537b9cf2c665afb922f69 | 0.550397 | 3.56042 | false | false | false | false |
nickg/nvc | test/regress/ieee8.vhd | 1 | 1,001 | entity ieee8 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.float_pkg.all;
use ieee.fixed_pkg.all;
architecture test of ieee8 is
procedure check(value : in float32; expect : in real) is
variable r : real;
begin
r := to_real(value);
assert value > expect - 0.00001;
assert value < expect + 0.00001;
end procedure;
begin
main: process is
subtype ufixed7 is ufixed (3 downto -3); -- 7 bit
variable a, b, c : float32;
variable checknum : float32;
variable check7uf1, check7uf : ufixed7;
begin
a := to_float(2.0);
b := to_float(3.0);
c := a + b;
report to_string(to_real(c));
check(c, 5.0);
c := a * b;
check(c, 6.0);
checknum := "00000000000000000000000000000000"; -- 0
check7uf1 := to_ufixed (checknum, check7uf1'high, check7uf1'low);
check7uf := "0000000";
wait;
end process;
end architecture;
| gpl-3.0 | 934d7279c756dc427dfaf331bd6e313b | 0.573427 | 3.39322 | false | false | false | false |
lfmunoz/vhdl | ip_blocks/sip_spi/amc7823_ctrl.vhd | 1 | 16,859 | -------------------------------------------------------------------------------------
-- FILE NAME :
-- AUTHOR : Luis
-- COMPANY :
-- LANGUAGE : VHDL
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
-- SPI controller for the Texas Instruments AMC7823 analog monitoring and control circuit
--
-- 1-bit R/W, 15-bit Address field, 16-bit Data
-- Clocked in MSB first (R/W), and LSB (D0) last
-- Serial data is clocked in on the rising edge of SCK
--
----------------------------------------------
-------------------------------------------------------------------------------------
-- LIBRARIES
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------------
entity amc7823_ctrl is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";--x"0005400";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF"--x"00073FF"
);
port (
rst : in std_logic;
clk : in std_logic; --serial clock
-- Command Interface
clk_cmd : in std_logic;
in_cmd_val : in std_logic;
in_cmd : in std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
out_cmd : out std_logic_vector(63 downto 0);
-- Spi interface
trig_n_cs : out std_logic;
trig_sclk : out std_logic;
trig_sdo : out std_logic;
trig_clksel0 : in std_logic
);
end amc7823_ctrl;
-------------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------------
architecture Behavioural of amc7823_ctrl is
----------------------------------------------------------------------------------------------------
-- Components
----------------------------------------------------------------------------------------------------
component pulse2pulse
port (
rst : in std_logic;
in_clk : in std_logic;
out_clk : in std_logic;
pulsein : in std_logic;
pulseout : out std_logic;
inbusy : out std_logic
);
end component;
----------------------------------------------------------------------------------------------------
-- Constants
----------------------------------------------------------------------------------------------------
constant ADDR_MAX_WR : std_logic_vector(27 downto 0) := x"0001FFF";
constant ADDR_MAX_RD : std_logic_vector(27 downto 0) := x"0001FFF";
attribute keep : string;
type sh_states is (idle, instruct, data_wait, data_io, data_valid, update, update_instruct, update_data_io);
constant TOTAL_BITS : natural := 32;
constant ADDR_BITS : natural := 15;
constant DATA_BITS : natural := 16;
constant WR_BIT : std_logic := '0'; -- 0 means write
constant RD_BIT : std_logic := '1'; -- 1 means read
----------------------------------------------------------------------------------------------------
-- Signals
----------------------------------------------------------------------------------------------------
signal sh_state : sh_states;
signal out_reg_val : std_logic;
signal out_reg_addr : std_logic_vector(27 downto 0);
signal out_reg : std_logic_vector(31 downto 0);
signal in_reg_req : std_logic;
signal in_reg_addr : std_logic_vector(27 downto 0);
signal in_reg_val : std_logic;
signal in_reg : std_logic_vector(31 downto 0);
signal sclk_prebuf : std_logic;
signal serial_clk : std_logic;
signal sclk_ext : std_logic;
signal trig_sdi : std_logic;
signal trig_sdi_in : std_logic;
signal inst_val : std_logic;
signal inst_reg_val : std_logic;
signal inst_rw : std_logic;
signal inst_reg : std_logic_vector(ADDR_BITS-1 downto 0); --IMPORTANT
signal data_reg : std_logic_vector(DATA_BITS-1 downto 0); -- IMPORTANT
signal shifting : std_logic;
signal shift_reg : std_logic_vector(TOTAL_BITS-1 downto 0); -- IMPORTANT
signal read_byte_val : std_logic;
signal data_read_val : std_logic;
signal data_write_val : std_logic;
signal data_read : std_logic_vector(DATA_BITS-1 downto 0);
signal sh_counter : integer;
signal read_n_write : std_logic;
signal ncs_int : std_logic;
signal ncs_trig : std_logic;
signal busy : std_logic;
--signal ncs_int_w : std_logic;
signal out_mailbox_data_sig : std_logic_vector(31 downto 0);
--------------------------------------------------------------------------------
--debug signals
--------------------------------------------------------------------------------
signal probe0 : std_logic_vector(127 downto 0);
--attribute keep of trig_clksel0 : signal is "true";
--attribute keep of inst_val : signal is "true";
--attribute keep of inst_rw : signal is "true";
--attribute keep of inst_reg : signal is "true";
--attribute keep of data_reg : signal is "true";
signal out_cmd_t :std_logic_vector(63 downto 0);
signal out_cmd_val_t :std_logic;
attribute keep of data_read_val : signal is "true";
attribute keep of data_read : signal is "true";
attribute keep of out_cmd_t : signal is "true";
attribute keep of out_cmd_val_t : signal is "true";
--*****************************************************************************************************
begin
--*****************************************************************************************************
--ila_inst0: entity work.ila_0
--PORT MAP (
-- clk => clk_cmd,
-- probe0 => probe0
--);
--
--
--probe0(63 downto 0) <= out_cmd_t;
--probe0(64) <= out_cmd_val_t;
--probe0(72 downto 65) <= data_read;
--probe0(73) <= data_read_val;
--probe0(127 downto 74) <= (others=>'0');
--probe0(0) <= '1';
--probe0(1) <= inst_val;
--probe0(2) <= inst_rw;
--probe0(15 downto 3) <= inst_reg(12 downto 0);
--probe0(23 downto 16) <= data_reg(7 downto 0);
--probe0(24) <= data_read_val;
----probe0(19 downto 12) <= data_read(7 downto 0);
--probe0(127 downto 25) <= (others=>'0');
--probe0(23 downto 0) <= shift_reg(23 downto 0);
--probe0(24) <= inst_reg_val;
--probe0(25) <= shifting;
--probe0(26) <= read_n_write;
--probe0(27) <= clk;
--probe0(28) <= ncs_int;
--probe0(29) <= trig_sdi_in;
--
--probe0(30) <= inst_val;
--probe0(31) <= inst_rw;
--probe0(44 downto 32) <= inst_reg(12 downto 0);
--probe0(52 downto 45) <= data_reg(7 downto 0);
--probe0(53) <= sdo_0;
--probe0(54) <= data_read_val;
--probe0(62 downto 55) <= data_read;
--probe0(127 downto 63) <= (others=>'0');
--
-- -- Intruction pulse
-- pulse2pulse_inst1120 : pulse2pulse
-- port map
-- (
-- rst => rst,
-- in_clk => serial_clk, --LM clk
-- out_clk => clk_cmd,
-- pulsein => shift_reg(shift_reg'length - 1),
-- pulseout => sdo_0,
-- inbusy => open
-- );
----------------------------------------------------------------------------------------------------
-- Generate serial clock (max 25MHz)
----------------------------------------------------------------------------------------------------
--process (clk)
-- -- Divide by 2^4 = 16, CLKmax = 16 x 25MHz = 400MHz
-- variable clk_div : std_logic_vector(3 downto 0) := (others => '0');
--begin
-- if (rising_edge(clk)) then
-- clk_div := clk_div + '1';
-- -- The slave samples the data on the rising edge of SCLK.
-- -- therefore we make sure the external clock is slightly
-- -- after the internal clock.
-- sclk_ext <= clk_div(clk_div'length-1);
-- sclk_prebuf <= sclk_ext;
-- end if;
--end process;
--bufg_sclk : bufg
--port map (
-- i => sclk_prebuf,
-- o => serial_clk
--);
serial_clk <= clk;
sclk_ext <= serial_clk;
----------------------------------------------------------------------------------------------------
-- Stellar Command Interface
----------------------------------------------------------------------------------------------------
fmc408_stellar_cmd_inst : entity work.fmc408_stellar_cmd
generic map (
START_ADDR => START_ADDR,
STOP_ADDR => STOP_ADDR
)
port map (
reset => rst,
clk_cmd => clk_cmd,
in_cmd_val => in_cmd_val,
in_cmd => in_cmd,
out_cmd_val => out_cmd_val,
out_cmd => out_cmd,
clk_reg => clk_cmd, --LM clk,
out_reg_val => out_reg_val,
out_reg_addr => out_reg_addr,
out_reg => out_reg,
in_reg_req => in_reg_req,
in_reg_addr => in_reg_addr,
in_reg_val => in_reg_val,
in_reg => in_reg,
mbx_out_reg => out_mailbox_data_sig,
mbx_out_val => open,
mbx_in_reg => (others=>'0'),
mbx_in_val => '0'
);
----------------------------------------------------------------------------------------------------
-- Shoot commands to the state machine
----------------------------------------------------------------------------------------------------
process (rst, clk_cmd) --LM clk
begin
if (rst = '1') then
in_reg_val <= '0';
in_reg <= (others => '0');
inst_val <= '0';
inst_rw <= '0';
inst_reg <= (others=> '0');
data_reg <= (others=> '0');
--data_read <= (others=> '0');
elsif (rising_edge(clk_cmd)) then -- LM clk
if (in_reg_addr <= ADDR_MAX_RD) then --(in_reg_req = '1' and in_reg_addr <= ADDR_MAX_RD) then
-- read from serial if when address is within device range
in_reg_val <= data_read_val;
in_reg <= conv_std_logic_vector(0, 32-DATA_BITS) & data_read;
else
in_reg_val <= '0';
in_reg <= in_reg;
end if;
-- Write instruction, only when address is within device range
if (out_reg_val = '1' and out_reg_addr <= ADDR_MAX_WR) then
inst_val <= '1';
inst_rw <= WR_BIT; -- write
inst_reg <= out_reg_addr(ADDR_BITS-1 downto 0);
data_reg <= out_reg(DATA_BITS-1 downto 0);
-- Read instruction, only when address is within LMK04828 range
elsif (in_reg_req = '1' and in_reg_addr <= ADDR_MAX_RD) then
inst_val <= '1';
inst_rw <= RD_BIT; -- read
inst_reg <= in_reg_addr(ADDR_BITS-1 downto 0);
data_reg <= data_reg;
-- No instruction
else
inst_val <= '0';
inst_rw <= inst_rw;
inst_reg <= inst_reg;
data_reg <= data_reg;
end if;
end if;
end process;
----------------------------------------------------------------------------------------------------
-- Serial interface state-machine
----------------------------------------------------------------------------------------------------
process (rst, serial_clk)
begin
if (rst = '1') then
sh_state <= idle;
sh_counter <= 0;
read_n_write <= '0';
--ncs_int_r <= '1';
--ncs_int_w <= '1';
ncs_int <= '1';
shifting <= '0';
elsif (rising_edge(serial_clk)) then
-- Main state machine
case sh_state is
when idle =>
sh_counter <= shift_reg'length-data_reg'length-1; --total length minus data bytes;
-- Accept every instruction
if (inst_reg_val = '1') then
shifting <= '1';
read_n_write <= inst_rw; -- 0 = write, 1 = read
ncs_int <= '0';
sh_state <= instruct;
else
shifting <= '0';
ncs_int <= '1';
end if;
when instruct =>
if (sh_counter = 0) then
sh_counter <= data_reg'length-1;
sh_state <= data_io;
else
sh_counter <= sh_counter - 1;
end if;
when data_io =>
if (sh_counter = 0) then
sh_counter <= shift_reg'length-data_reg'length-1; --total length minus data bytes;
shifting <= '0';
ncs_int <= '1';
if (read_n_write = '1') then
sh_state <= data_valid; -- read
else
sh_state <= data_wait; -- write
end if;
else
sh_counter <= sh_counter - 1;
end if;
when data_valid => -- read
sh_state <= idle;
when data_wait => -- write
sh_state <= idle;
when others =>
sh_state <= idle;
end case;
end if;
end process;
busy <= '0' when (sh_state = idle) else '1';
----------------------------------------------------------------------------------------------------
-- Instruction & data shift register
----------------------------------------------------------------------------------------------------
process (rst, serial_clk)
begin
if (rst = '1') then
shift_reg <= (others => '0');
read_byte_val <= '0';
data_read <= (others => '0');
elsif (rising_edge(serial_clk)) then
if (inst_reg_val = '1' and read_n_write = '0') then -- write
shift_reg <= inst_rw & inst_reg & data_reg;
elsif (inst_reg_val = '1' and read_n_write = '1') then -- read
shift_reg <= inst_rw & inst_reg & data_reg;
end if;
if (shifting = '1') then
shift_reg <= shift_reg(shift_reg'length-2 downto 0) & trig_sdi_in;
end if;
-- Data read from device
if (sh_state = data_valid) then
read_byte_val <= '1';
data_read <= shift_reg(DATA_BITS-1 downto 0);
else
read_byte_val <= '0';
data_read <= data_read;
end if;
end if;
end process;
-- Transfer data valid pulse to other clock domain
pulse2pulse_inst1 : pulse2pulse
port map (
rst => rst,
in_clk => serial_clk,
out_clk => clk_cmd, -- LM clk
pulsein => read_byte_val,
pulseout => data_read_val,
inbusy => open
);
-- Intruction pulse
pulse2pulse_inst0 : pulse2pulse
port map (
rst => rst,
in_clk => clk_cmd, --LM clk
out_clk => serial_clk,
pulsein => inst_val,
pulseout => inst_reg_val,
inbusy => open
);
----------------------------------------------------------------------------------------------------
-- Capture data in on rising edge SCLK
-- therefore freeze the signal on the falling edge of serial clock.
----------------------------------------------------------------------------------------------------
process (serial_clk)
begin
if (falling_edge(serial_clk)) then
trig_sdi_in <= trig_clksel0;
end if;
end process;
--------------------------------------------------------------------------------
-- Outputs
--------------------------------------------------------------------------------
--spi_io_t <= '1' when (sh_state = data_io and read_n_write = '1') else '0'; -- 0 = output, 1 = input
trig_sdo <= 'Z' when (sh_state = data_io and read_n_write = '1') else shift_reg(shift_reg'length - 1);--shift_reg(shift_reg'length - 1) when ncs_int = '0' else 'Z';
trig_n_cs <= ncs_int;
trig_sclk <= not sclk_ext when ncs_int = '0' else '0';
-- ncs_trig <= ncs_int when read_n_write = '0' else ncs_int_w;
--------------------------------------------------------------------------------
-- Output buffer
--------------------------------------------------------------------------------
--iobuf_trig : iobuf
--port map (
-- I => data_write_val,
-- O => trig_sdi,
-- IO => trig_sdo,
-- T => ncs_trig
--);
--********************************************************************************
end Behavioural;
--********************************************************************************
| mit | cc3cd01567a8ce545967278679a2dcca | 0.414319 | 3.885457 | false | false | false | false |
DE5Amigos/SylvesterTheDE2Bot | DE2Botv3Fall16Main/SLCD.vhd | 1 | 5,368 | -- SLCD.VHD (a peripheral module for SCOMP)
-- 2009.10.10
--
-- The simple LCD controller displays a single 16 bit register on the top line
-- of the LCD.
-- It sends an initialization string to the LCD, then repeatedly writes a four-
-- digit hex value to a fixed location in the display. The value is latched
-- whenever the device is selected by CS.
-- See datasheets for the HD44780 or equivalent LCD controller.
LIBRARY IEEE;
LIBRARY LPM;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE LPM.LPM_COMPONENTS.ALL;
ENTITY SLCD IS
PORT(
CLOCK_10KHZ : IN STD_LOGIC;
RESETN : IN STD_LOGIC;
CS : IN STD_LOGIC;
IO_DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
LCD_RS : OUT STD_LOGIC;
LCD_RW : OUT STD_LOGIC;
LCD_E : OUT STD_LOGIC;
LCD_D : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END SLCD;
ARCHITECTURE a OF SLCD IS
TYPE STATE_TYPE IS (
RESET,
INIT,
INIT_CLOCK,
CURPOS,
CURPOS_CLOCK,
SWRITE,
SWRITE_CLOCK
);
TYPE CSTR15_TYPE IS ARRAY (0 TO 15) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
TYPE CSTR08_TYPE IS ARRAY (0 TO 7) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
TYPE CSTR04_TYPE IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL state : STATE_TYPE;
SIGNAL ascii : CSTR15_TYPE;
SIGNAL cstr : CSTR04_TYPE;
SIGNAL istr : CSTR08_TYPE;
SIGNAL count : INTEGER RANGE 0 TO 1000;
SIGNAL delay : INTEGER RANGE 0 TO 100;
SIGNAL data_in : STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
-- LCD initialization string
istr(0) <= x"38"; -- Wakeup
istr(1) <= x"38"; -- Wakeup
istr(2) <= x"38"; -- Wakeup
istr(3) <= x"38"; -- Function set: 2 lines, 5x8 dot font
istr(4) <= x"08"; -- Display off
istr(5) <= x"01"; -- Clear display
istr(6) <= x"0C"; -- Display on
istr(7) <= x"04"; -- Entry mode set (left to right)
ascii( 0) <= x"30"; -- ASCII table values
ascii( 1) <= x"31";
ascii( 2) <= x"32";
ascii( 3) <= x"33";
ascii( 4) <= x"34";
ascii( 5) <= x"35";
ascii( 6) <= x"36";
ascii( 7) <= x"37";
ascii( 8) <= x"38";
ascii( 9) <= x"39";
ascii(10) <= x"41";
ascii(11) <= x"42";
ascii(12) <= x"43";
ascii(13) <= x"44";
ascii(14) <= x"45";
ascii(15) <= x"46";
LCD_RW <= '0';
cstr(0) <= ascii(CONV_INTEGER(data_in( 3 DOWNTO 0)));
cstr(1) <= ascii(CONV_INTEGER(data_in( 7 DOWNTO 4)));
cstr(2) <= ascii(CONV_INTEGER(data_in(11 DOWNTO 8)));
cstr(3) <= ascii(CONV_INTEGER(data_in(15 DOWNTO 12)));
-- This process latches the incoming data value on the rising edge of CS
PROCESS (RESETN, CS)
BEGIN
IF (RESETN = '0') THEN
data_in <= x"0000";
ELSIF (RISING_EDGE(CS)) THEN
data_in <= IO_DATA;
END IF;
END PROCESS;
-- This processes writes the latched data values to the LCD
PROCESS (RESETN, CLOCK_10KHZ)
BEGIN
IF (RESETN = '0') THEN
LCD_D <= x"00";
LCD_RS <= '0';
LCD_E <= '0';
count <= 0;
delay <= 0;
state <= RESET;
ELSIF (RISING_EDGE(CLOCK_10KHZ)) THEN
CASE state IS
WHEN RESET => -- wait about 0.1 sec (exceeds 15 ms requirement)
IF (count > 999) THEN
count <= 0;
state <= INIT;
ELSE
count <= count + 1;
END IF;
WHEN INIT => -- send an init command
LCD_RS <= '0';
LCD_E <= '1';
LCD_D <= istr(count);
count <= count + 1;
delay <= 0;
state <= INIT_CLOCK;
WHEN INIT_CLOCK => -- latch the command and wait
LCD_E <= '0'; -- dropping LCD_E latches
delay <= delay + 1;
IF (delay >= 99) THEN -- wait about 10 ms between init commands
IF (count < 8) THEN
state <= INIT;
ELSE
state <= CURPOS;
END IF;
END IF;
-- all remaining states have no waits. 100 us per state
-- write (enable) states alternate with latching states
WHEN CURPOS => -- Move to 11th character posn on line 1
LCD_RS <= '0';
LCD_E <= '1';
LCD_D <= x"8A";
state <= CURPOS_CLOCK;
WHEN CURPOS_CLOCK =>
LCD_E <= '0';
count <= 0;
state <= SWRITE;
WHEN SWRITE => -- Write (least significant digit first)
LCD_RS <= '1';
LCD_E <= '1';
LCD_D <= cstr(count);
count <= count + 1;
state <= SWRITE_CLOCK;
WHEN SWRITE_CLOCK => -- Finish write (moves left on screen in chosen mode)
LCD_E <= '0';
IF (count >= 4) THEN
state <= CURPOS;
ELSE
state <= SWRITE;
END IF;
END CASE;
END IF;
END PROCESS;
END a;
| mit | 61f30f8409fe14553171666d0c9a6700 | 0.482675 | 3.649218 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1314/issue.vhdl | 1 | 3,983 | library ieee;
use ieee.std_logic_1164.all;
entity sequencer is
generic (
seq : string
);
port (
clk : in std_logic;
data : out std_logic
);
end entity sequencer;
architecture rtl of sequencer is
signal index : natural := seq'low;
function to_bit (a : in character) return std_logic is
variable ret : std_logic;
begin
case a is
when '0' | '_' => ret := '0';
when '1' | '-' => ret := '1';
when others => ret := 'X';
end case;
return ret;
end function to_bit;
begin
process (clk) is
begin
if rising_edge(clk) then
if (index < seq'high) then
index <= index + 1;
end if;
end if;
end process;
data <= to_bit(seq(index));
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
entity hex_sequencer is
generic (
seq : string
);
port (
clk : in std_logic;
data : out std_logic_vector(3 downto 0)
);
end entity hex_sequencer;
architecture rtl of hex_sequencer is
signal index : natural := seq'low;
function to_hex (a : in character) return std_logic_vector is
variable ret : std_logic_vector(3 downto 0);
begin
case a is
when '0' | '_' => ret := x"0";
when '1' => ret := x"1";
when '2' => ret := x"2";
when '3' => ret := x"3";
when '4' => ret := x"4";
when '5' => ret := x"5";
when '6' => ret := x"6";
when '7' => ret := x"7";
when '8' => ret := x"8";
when '9' => ret := x"9";
when 'a' | 'A' => ret := x"A";
when 'b' | 'B' => ret := x"B";
when 'c' | 'C' => ret := x"C";
when 'd' | 'D' => ret := x"D";
when 'e' | 'E' => ret := x"E";
when 'f' | 'F' | '-' => ret := x"F";
when others => ret := x"X";
end case;
return ret;
end function to_hex;
begin
process (clk) is
begin
if rising_edge(clk) then
if (index < seq'high) then
index <= index + 1;
end if;
end if;
end process;
data <= to_hex(seq(index));
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity issue is
port (
clk : in std_logic
);
end entity issue;
architecture psl of issue is
component sequencer is
generic (
seq : string
);
port (
clk : in std_logic;
data : out std_logic
);
end component sequencer;
component hex_sequencer is
generic (
seq : string
);
port (
clk : in std_logic;
data : out std_logic_vector(3 downto 0)
);
end component hex_sequencer;
signal req, ack : std_logic;
signal din, dout : std_logic_vector(3 downto 0);
begin
-- 0123456789
SEQ_REQ : sequencer generic map ("_-______-____") port map (clk, req);
SEQ_DIN : hex_sequencer generic map ("4433344774444") port map (clk, din);
SEQ_ACK : sequencer generic map ("___-______-__") port map (clk, ack);
SEQ_DOUT : hex_sequencer generic map ("2244333447744") port map (clk, dout);
-- All is sensitive to rising edge of clk
default clock is rising_edge(clk);
-- Check for two possible values of din/dout
NEXT_EVENT_0_a : assert always ((req and din = x"4") -> next_event(ack)(dout = x"4"));
NEXT_EVENT_1_a : assert always ((req and din = x"7") -> next_event(ack)(dout = x"7"));
-- Check for all possible values of din/dout
check_transfer : for i in 0 to 15 generate
signal i_slv : std_logic_vector(din'range);
begin
i_slv <= std_logic_vector(to_unsigned(i, 4));
-- Without name it works
assert always ((req and din = i_slv) -> next_event(ack)(dout = i_slv));
-- This errors because of similar names of all asserts
-- ERROR: Assert `count_id(cell->name) == 0' failed in kernel/rtlil.cc:1613.
NEXT_EVENT_a : assert always ((req and din = i_slv) -> next_event(ack)(dout = i_slv));
end generate check_transfer;
end architecture psl;
| gpl-2.0 | c3a1c56564b41f12bfb9340ae1ace283 | 0.554607 | 3.283594 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc53.vhd | 4 | 2,019 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc53.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c04s03b01x01p04n03i00053pkg is
constant C1 : Bit ;
constant C2 : Integer ;
end c04s03b01x01p04n03i00053pkg;
package body c04s03b01x01p04n03i00053pkg is
constant C1 : Bit := '1';
constant C2 : Integer := 20;
end c04s03b01x01p04n03i00053pkg; -- Failure_here
use work.c04s03b01x01p04n03i00053pkg.all;
ENTITY c04s03b01x01p04n03i00053ent IS
END c04s03b01x01p04n03i00053ent;
ARCHITECTURE c04s03b01x01p04n03i00053arch OF c04s03b01x01p04n03i00053ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( C1 = '1' and C2 = 20 )
report "***PASSED TEST:c04s03b01x01p04n03i00053"
severity NOTE;
assert ( C1 = '1' and C2 = 20 )
report "***FAILED TEST: c04s03b01x01p04n03i00053 - Full constant declaration test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x01p04n03i00053arch;
| gpl-2.0 | 2d5fa59fdabfad7b56fcd5bc97535d31 | 0.683507 | 3.370618 | false | true | false | false |
tgingold/ghdl | testsuite/gna/ticket104/bug_tb.vhd | 2 | 837 | library ieee;
use ieee.std_logic_1164.all;
entity bug_tb is
end bug_tb;
-------------------------------------------------------------------------------
architecture test of bug_tb is
type t_test_vec is array (10 downto -1) of std_logic;
signal test_vec : t_test_vec := (others => '0');
-- clock
signal Clk : std_logic := '1';
procedure pr_vec (
vec : in std_logic_vector) is
begin -- procedure pr_vec
for i in vec'range loop
report "bit: " & integer'image(i) & "=" & std_logic'image(vec(i)) severity note;
end loop; -- i
end procedure pr_vec;
begin -- test
-- clock generation
Clk <= not Clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
wait until rising_edge(Clk);
pr_vec(std_logic_vector(test_vec));
wait;
end process WaveGen_Proc;
end test;
| gpl-2.0 | dfe2ed7c51aaa131aaa7e1517dde5279 | 0.572282 | 3.4875 | false | true | false | false |
tgingold/ghdl | testsuite/gna/issue643/repro.vhdl | 1 | 267 | entity repro is
end entity;
architecture a of repro is
constant C_PATTERN_0 : bit_vector(31 downto 0) := (
1 downto 0 => "01",
3 downto 2 => "11",
5 downto 4 => "01",
7 downto 6 => "10",
others => '0'
);
begin
end architecture;
| gpl-2.0 | abf9cc5775dfe25644db5baa85ad8ec4 | 0.546816 | 3.178571 | false | false | false | false |
nickg/nvc | test/regress/signal20.vhd | 1 | 613 | entity signal20 is
end entity;
architecture test of signal20 is
signal x : integer_vector(4 downto 0);
signal y : integer_vector(1 downto 0);
signal z : integer_vector(2 downto 0);
signal i0, i1 : integer;
begin
main: process is
begin
x <= (1, 2, 3, 4, 5);
wait for 1 ns;
(y, z) <= x;
wait for 1 ns;
assert y = (1, 2);
assert z = (3, 4, 5);
wait for 1 ns;
(i0, z, i1) <= x;
wait for 1 ns;
assert i0 = 1;
assert z = (2, 3, 4);
assert i1 = 5;
wait;
end process;
end architecture;
| gpl-3.0 | 0030c8d16c1e37865d7670b9c32e4db8 | 0.502447 | 3.243386 | false | false | false | false |
nickg/nvc | test/regress/file5.vhd | 1 | 690 | entity file5 is
end entity;
architecture test of file5 is
type natural_vector is array (natural range <>) of natural;
type ft is file of natural_vector;
begin
process is
file f : ft;
variable v : natural_vector(1 to 5);
variable len : natural;
begin
file_open(f, "test.bin", WRITE_MODE);
v := (1, 2, 3, 4, 5);
write(f, v);
file_close(f);
v := (others => 0);
file_open(f, "test.bin", READ_MODE);
read(f, v, len);
file_close(f);
assert v = (1, 2, 3, 4, 5);
report integer'image(len);
assert len = 5;
wait;
end process;
end architecture;
| gpl-3.0 | df6a03dc35fc6470a003b1927a7d198d | 0.521739 | 3.467337 | false | true | false | false |
nickg/nvc | test/sem/osvvm2.vhd | 1 | 1,583 | package OsvvmGlobalPkg is
type OsvvmOptionsType is (OPT_INIT_PARM_DETECT, OPT_USE_DEFAULT, DISABLED, FALSE, ENABLED, TRUE) ;
-- Defaults for String values
constant OSVVM_DEFAULT_ALERT_PREFIX : string := "%% Alert" ;
constant OSVVM_DEFAULT_LOG_PREFIX : string := "%% Log " ;
constant OSVVM_DEFAULT_WRITE_PREFIX : string := "%% " ;
constant OSVVM_DEFAULT_DONE_NAME : string := "DONE" ;
constant OSVVM_DEFAULT_PASS_NAME : string := "PASSED" ;
constant OSVVM_DEFAULT_FAIL_NAME : string := "FAILED" ;
constant OSVVM_STRING_INIT_PARM_DETECT : string := NUL & NUL & NUL ;
constant OSVVM_STRING_USE_DEFAULT : string := NUL & "" ;
-- Coverage Settings
constant OSVVM_DEFAULT_WRITE_PASS_FAIL : OsvvmOptionsType := FALSE ;
constant OSVVM_DEFAULT_WRITE_BIN_INFO : OsvvmOptionsType := TRUE ;
constant OSVVM_DEFAULT_WRITE_COUNT : OsvvmOptionsType := TRUE ;
constant OSVVM_DEFAULT_WRITE_ANY_ILLEGAL : OsvvmOptionsType := FALSE ;
end OsvvmGlobalPkg ;
use work.OsvvmGlobalPkg.all ;
package CoveragePkg is
-- type OsvvmOptionsType is (OPT_DEFAULT, FALSE, TRUE) ;
alias CovOptionsType is work.OsvvmGlobalPkg.OsvvmOptionsType ;
constant COV_OPT_INIT_PARM_DETECT : CovOptionsType := work.OsvvmGlobalPkg.OPT_INIT_PARM_DETECT ;
-- For backward compatibility. Don't add to other packages.
alias DISABLED is work.OsvvmGlobalPkg.DISABLED [return work.OsvvmGlobalPkg.OsvvmOptionsType ];
alias ENABLED is work.OsvvmGlobalPkg.ENABLED [return work.OsvvmGlobalPkg.OsvvmOptionsType ];
end package CoveragePkg ;
| gpl-3.0 | 6174f4ab8e696e0211ec2682f504ff9a | 0.715098 | 3.751185 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_22.vhd | 4 | 1,476 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_22.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity S_R_flipflop is
port ( s, r : in bit; q, q_n : out bit );
end entity S_R_flipflop;
--------------------------------------------------
architecture functional of S_R_flipflop is
begin
q <= '1' when s = '1' else
'0' when r = '1';
q_n <= '0' when s = '1' else
'1' when r = '1';
check : assert not (s = '1' and r = '1')
report "Incorrect use of S_R_flip_flop: s and r both '1'";
end architecture functional;
| gpl-2.0 | 712ba7bce1f74b01e5938335c74756b8 | 0.584011 | 3.823834 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue332/irqc_tb.vhd | 1 | 2,962 | --********************************************************************************************************************--
--! @brief Testbench for decoder simulator
--********************************************************************************************************************--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
library STD;
use std.env.all;
use work.irqc_pif_pkg.all;
use work.ilos_sim_pkg.all;
--! Local libraries
library work;
--! Entity/Package Description
entity tb_irqc is
end entity tb_irqc;
architecture tb of tb_irqc is
-- Signal declarations
SIGNAL arst_sig: std_logic;
SIGNAL clk_sig: std_logic;
SIGNAL cs_sig: std_logic;
SIGNAL addr_sig: unsigned(2 DOWNTO 0);
SIGNAL wr_sig: std_logic;
SIGNAL rd_sig: std_logic;
SIGNAL din_sig: std_logic_vector(7 DOWNTO 0);
SIGNAL dout_sig: std_logic_vector(7 DOWNTO 0);
SIGNAL p2c_sig: t_p2c;
SIGNAL c2p_sig: t_c2p;
SIGNAL run_sig: std_logic;
signal sbi_if : t_sbi_if(addr(2 downto 0), wdata(7 downto 0), rdata(7 downto 0)) := init_sbi_if_signals(3, 8);
--! Component declaration for Behavioral Decoder
COMPONENT irqc_pif IS
PORT(
arst : in std_logic;
clk : in std_logic;
-- CPU interface
cs : in std_logic;
addr : in unsigned;
wr : in std_logic;
rd : in std_logic;
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0) := (others => '0');
--
p2c : out t_p2c;
c2p : in t_c2p
);
END COMPONENT irqc_pif;
BEGIN
IRQC: irqc_pif PORT MAP (
arst => arst_sig,
clk => clk_sig,
cs => cs_sig,
addr => addr_sig,
wr => wr_sig,
rd => rd_sig,
din => din_sig,
dout => dout_sig,
p2c => p2c_sig,
c2p => c2p_sig
);
-- Clock generation with concurrent procedure call
clk_gen(clk_sig, 50.0E6, 0 fs, run_sig); -- 50 MHz clock
-- Time resolution show
-- assert FALSE report "Time resolution: " & time'image(time'succ(0 fs)) severity NOTE;
tb: PROCESS
BEGIN
run_sig <= '1';
arst_sig <= '1';
cs_sig <= '0';
addr_sig <= to_unsigned(0, addr_sig'length);
wr_sig <= '0';
rd_sig <= '0';
din_sig <= (others => '0');
c2p_sig.aro_irr <= (others => '0');
c2p_sig.aro_ipr <= (others => '0');
c2p_sig.aro_irq2cpu_allowed <= '0';
wait for 200 ns;
arst_sig <= '0';
wait for 205 nS;
rd_sig <= '1';
cs_sig <= '1';
wait for 20 ns;
addr_sig <= to_unsigned(C_ADDR_IER, addr_sig'length);
wait for 20 nS;
addr_sig <= to_unsigned(C_ADDR_IPR, addr_sig'length);
wait for 20 nS;
addr_sig <= to_unsigned(C_ADDR_IRQ2CPU_ALLOWED, addr_sig'length);
wait for 20 nS;
addr_sig <= to_unsigned(C_ADDR_IER, addr_sig'length);
din_sig <= X"15";
wr_sig <= '1';
rd_sig <= '0';
wait for 20 ns;
cs_sig <= '0';
wr_sig <= '0';
rd_sig <= '1';
cs_sig <= '1';
wait for 80 ns;
cs_sig <= '0';
rd_sig <= '0';
wait for 200 nS;
-- End simulation
run_sig <= '0';
wait for 200 nS;
finish;
END PROCESS tb;
end architecture tb;
| gpl-2.0 | da0ad73af8235f0f04fb8dc929672954 | 0.565496 | 2.71494 | false | false | false | false |
tgingold/ghdl | testsuite/synth/dff02/tb_dff06.vhdl | 1 | 872 | entity tb_dff06 is
end tb_dff06;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff06 is
signal clk : std_logic;
signal rst : std_logic;
signal din : std_logic_vector (7 downto 0);
signal dout : std_logic_vector (7 downto 0);
begin
dut: entity work.dff06
port map (
q => dout,
d => din,
clk => clk,
rst => rst);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rst <= '0';
din <= x"7e";
pulse;
assert dout = x"7e" severity failure;
din <= x"38";
pulse;
assert dout = x"38" severity failure;
rst <= '1';
din <= x"af";
pulse;
assert dout = x"38" severity failure;
rst <= '0';
pulse;
assert dout = x"af" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 1225e777842e79cb5393adc15e5ccd8f | 0.558486 | 3.290566 | false | false | false | false |
tgingold/ghdl | testsuite/gna/ticket89/project/src93/string_methods_pkg.vhd | 3 | 37,715 | --========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation files (for 'Bitvis Utility Library'),
-- to use, copy, modify, merge, publish and/or distribute - subject to the following conditions:
-- - This copyright notice shall be included as is in all copies or substantial portions of the code and documentation
-- - The files included in Bitvis Utility Library may only be used as a part of this library as a whole
-- - The License file may not be modified
-- - The calls in the code to the license file ('show_license') may not be removed or modified.
-- - No other conditions whatsoever may be added to those of this License
-- BITVIS UTILITY LIBRARY AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
-- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH BITVIS UTILITY LIBRARY.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis Utility Library : string_methods_pkg
--
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
use ieee_proposed.std_logic_1164_additions.all;
use ieee_proposed.standard_textio_additions.all;
use work.types_pkg.all;
use work.adaptations_pkg.all;
package string_methods_pkg is
-- Need a low level "alert" in the form of a simple assertion (as string handling may also fail)
procedure bitvis_assert(
val : boolean;
severeness : severity_level;
msg : string;
scope : string
);
function justify(
val : string;
width : natural := 0;
justified : side := RIGHT;
format: t_format_string := AS_IS -- No defaults on 4 first param - to avoid ambiguity with std.textio
) return string;
function pos_of_leftmost(
target : character;
vector : string;
result_if_not_found : natural := 1
) return natural;
function pos_of_rightmost(
target : character;
vector : string;
result_if_not_found : natural := 1
) return natural;
function pos_of_leftmost_non_zero(
vector : string;
result_if_not_found : natural := 1
) return natural;
function get_string_between_delimeters(
val : string;
delim_left : character;
delim_right: character;
start_from : SIDE; -- search from left or right (Only RIGHT implemented so far)
occurrence : positive := 1 -- stop on N'th occurrence of delimeter pair. Default first occurrence
) return string;
function get_procedure_name_from_instance_name(
val : string
) return string;
function get_process_name_from_instance_name(
val : string
) return string;
function get_entity_name_from_instance_name(
val : string
) return string;
function return_string_if_true(
val : string;
return_val : boolean
) return string;
function to_upper(
val : string
) return string;
function fill_string(
val : character;
width : natural
) return string;
function replace_backslash_n_with_lf(
source : string
) return string;
function remove_initial_chars(
source : string;
num : natural
) return string;
function wrap_lines(
constant text_string : string;
constant alignment_pos1 : natural; -- Line position of first aligned character in line 1
constant alignment_pos2 : natural; -- Line position of first aligned character in line 2, etc...
constant line_width : natural
) return string;
procedure wrap_lines(
variable text_lines : inout line;
constant alignment_pos1 : natural; -- Line position prior to first aligned character (incl. Prefix)
constant alignment_pos2 : natural;
constant line_width : natural
);
procedure prefix_lines(
variable text_lines : inout line;
constant prefix : string := C_LOG_PREFIX
);
function replace(
val : string;
target_char : character;
exchange_char : character
) return string;
procedure replace(
variable text_line : inout line;
target_char : character;
exchange_char : character
);
--========================================================
-- Handle missing overloads from 'standard_additions'
--========================================================
function to_string(
val : boolean;
width : natural;
justified : side := right;
format: t_format_string := AS_IS
) return string;
function to_string(
val : integer;
width : natural;
justified : side := right;
format : t_format_string := AS_IS
) return string;
function to_string(
val : std_logic_vector;
radix : t_radix;
format : t_format_zeros := AS_IS; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
function to_string(
val : unsigned;
radix : t_radix;
format : t_format_zeros := AS_IS; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
function to_string(
val : signed;
radix : t_radix;
format : t_format_zeros := AS_IS; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
--========================================================
-- Handle types defined at lower levels
--========================================================
function to_string(
val : t_alert_level;
width : natural := 0;
justified : side := right
) return string;
function to_string(
val : t_msg_id;
width : natural := 0;
justified : side := right
) return string;
function to_string(
val : t_enabled
) return string;
function to_string(
val : t_attention;
width : natural := 0;
justified : side := right
) return string;
procedure to_string(
val : t_alert_attention_counters;
order : t_order := FINAL
);
function ascii_to_char(
ascii_pos : integer range 0 to 255;
ascii_allow : t_ascii_allow := ALLOW_ALL
) return character;
function char_to_ascii(
char : character
) return integer;
-- return string with only valid ascii characters
function to_string(
val : string
) return string;
end package string_methods_pkg;
package body string_methods_pkg is
-- Need a low level "alert" in the form of a simple assertion (as string handling may also fail)
procedure bitvis_assert(
val : boolean;
severeness : severity_level;
msg : string;
scope : string
) is
begin
assert val
report LF & C_LOG_PREFIX & " *** " & to_string(severeness) & "*** caused by Bitvis Util > string handling > "
& scope & LF & C_LOG_PREFIX & " " & msg & LF
severity severeness;
end;
function to_upper(
val : string
) return string is
variable v_result : string (val'range) := val;
variable char : character;
begin
for i in val'range loop
-- NOTE: Illegal characters are allowed and will pass through (check Mentor's std_developers_kit)
if ( v_result(i) >= 'a' and v_result(i) <= 'z') then
v_result(i) := character'val( character'pos(v_result(i)) - character'pos('a') + character'pos('A') );
end if;
end loop;
return v_result;
end to_upper;
function fill_string(
val : character;
width : natural
) return string is
variable v_result : string (1 to maximum(1, width));
begin
if (width = 0) then
return "";
else
for i in 1 to width loop
v_result(i) := val;
end loop;
end if;
return v_result;
end fill_string;
function justify(
val : string;
width : natural := 0;
justified : side := RIGHT;
format : t_format_string := AS_IS -- No defaults on 4 first param - to avoid ambiguity with std.textio
) return string is
constant val_length : natural := val'length;
variable result : string(1 to width) := (others => ' ');
begin
-- return val if width is too small
if val_length >= width then
if (format = TRUNCATE) then
return val(1 to width);
else
return val;
end if;
end if;
if justified = left then
result(1 to val_length) := val;
elsif justified = right then
result(width - val_length + 1 to width) := val;
end if;
return result;
end function;
function pos_of_leftmost(
target : character;
vector : string;
result_if_not_found : natural := 1
) return natural is
alias a_vector : string(1 to vector'length) is vector;
begin
bitvis_assert(vector'length > 0, FAILURE, "String input is empty", "pos_of_leftmost()");
bitvis_assert(vector'ascending, FAILURE, "Only implemented for string(N to M)", "pos_of_rightmost()");
for i in a_vector'left to a_vector'right loop
if (a_vector(i) = target) then
return i;
end if;
end loop;
return result_if_not_found;
end;
function pos_of_rightmost(
target : character;
vector : string;
result_if_not_found : natural := 1
) return natural is
alias a_vector : string(1 to vector'length) is vector;
begin
bitvis_assert(vector'length > 0, FAILURE, "String input is empty", "pos_of_rightmost()");
bitvis_assert(vector'ascending, FAILURE, "Only implemented for string(N to M)", "pos_of_rightmost()");
for i in a_vector'right downto a_vector'left loop
if (a_vector(i) = target) then
return i;
end if;
end loop;
return result_if_not_found;
end;
function pos_of_leftmost_non_zero(
vector : string;
result_if_not_found : natural := 1
) return natural is
alias a_vector : string(1 to vector'length) is vector;
begin
bitvis_assert(vector'length > 0, FAILURE, "String input is empty", "pos_of_leftmost()");
for i in a_vector'left to a_vector'right loop
if (a_vector(i) /= '0' and a_vector(i) /= ' ') then
return i;
end if;
end loop;
return result_if_not_found;
end;
function string_contains_char(
val : string;
char : character
) return boolean is
alias a_val : string(1 to val'length) is val;
begin
if (val'length = 0) then
return false;
else
for i in val'left to val'right loop
if (val(i) = char) then
return true;
end if;
end loop;
-- falls through only if not found
return false;
end if;
end;
-- get_*_name
-- Note: for sub-programs the following is given: library:package:procedure:object
-- Note: for design hierachy the following is given: complete hierarchy from sim-object down to process object
-- e.g. 'sbi_tb:i_test_harness:i2_sbi_vvc:p_constructor:v_msg'
-- Attribute instance_name also gives [procedure signature] or @entity-name(architecture name)
function get_string_between_delimeters(
val : string;
delim_left : character;
delim_right: character;
start_from : SIDE; -- search from left or right (Only RIGHT implemented so far)
occurrence : positive := 1 -- stop on N'th occurrence of delimeter pair. Default first occurrence
) return string is
variable v_left : natural := 0;
variable v_right : natural := 0;
variable v_start : natural := val'length;
variable v_occurrence : natural := 0;
alias a_val : string(1 to val'length) is val;
begin
bitvis_assert(a_val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_string_between_delimeters()");
bitvis_assert(start_from = RIGHT, FAILURE, "Only search from RIGHT is implemented so far", "get_string_between_delimeters()");
loop
-- RIGHT
v_left := 0; -- default
v_right := pos_of_rightmost(delim_right, a_val(1 to v_start), 0);
if v_right > 0 then -- i.e. found
L1: for i in v_right-1 downto 1 loop -- searching backwards for delimeter
if (a_val(i) = delim_left) then
v_left := i;
v_start := i; -- Previous end delimeter could also be a start delimeter for next section
v_occurrence := v_occurrence + 1;
exit L1;
end if;
end loop; -- searching backwards
end if;
if v_right = 0 or v_left = 0 then
return ""; -- No delimeter pair found, and none can be found in the rest (with chars in between)
end if;
if v_occurrence = occurrence then
-- Match
if (v_right - v_left) < 2 then
return ""; -- no chars in between delimeters
else
return a_val(v_left+1 to v_right-1);
end if;
end if;
if v_start < 3 then
return ""; -- No delimeter pair found, and none can be found in the rest (with chars in between)
end if;
end loop; -- Will continue until match or not found
end;
-- ':sbi_tb(func):i_test_harness@test_harness(struct):i2_sbi_vvc@sbi_vvc(struct):p_constructor:instance'
-- ':sbi_tb:i_test_harness:i1_sbi_vvc:p_constructor:instance'
-- - Process name: Search for 2nd last param in path name
-- - Entity name: Search for 3nd last param in path name
--':bitvis_vip_sbi:sbi_bfm_pkg:sbi_write[unsigned,std_logic_vector,string,std_logic,std_logic,unsigned,
-- std_logic,std_logic,std_logic,std_logic_vector,time,string,t_msg_id_panel,t_sbi_config]:msg'
-- - Procedure name: Search for 2nd last param in path name and remove all inside []
function get_procedure_name_from_instance_name(
val : string
) return string is
variable v_line : line;
variable v_msg_line : line;
begin
bitvis_assert(val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_procedure_name_from_instance_name()");
write(v_line, get_string_between_delimeters(val, ':', '[', RIGHT));
if (string_contains_char(val, '@')) then
write(v_msg_line, string'("Must be called with <sub-program object>'instance_name"));
else
write(v_msg_line, string'(" "));
end if;
bitvis_assert(v_line'length > 0, ERROR, "No procedure name found. " & v_msg_line.all, "get_procedure_name_from_instance_name()");
return v_line.all;
end;
function get_process_name_from_instance_name(
val : string
) return string is
variable v_line : line;
variable v_msg_line : line;
begin
bitvis_assert(val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_process_name_from_instance_name()");
write(v_line, get_string_between_delimeters(val, ':', ':', RIGHT));
if (string_contains_char(val, '[')) then
write(v_msg_line, string'("Must be called with <process-local object>'instance_name"));
else
write(v_msg_line, string'(" "));
end if;
bitvis_assert(v_line'length > 0, ERROR, "No process name found", "get_process_name_from_instance_name()");
return v_line.all;
end;
function get_entity_name_from_instance_name(
val : string
) return string is
variable v_line : line;
variable v_msg_line : line;
begin
bitvis_assert(val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_entity_name_from_instance_name()");
if string_contains_char(val, '@') then -- for path with instantiations
write(v_line, get_string_between_delimeters(val, '@', '(', RIGHT));
else -- for path with only a single entity
write(v_line, get_string_between_delimeters(val, ':', '(', RIGHT));
end if;
if (string_contains_char(val, '[')) then
write(v_msg_line, string'("Must be called with <Entity/arch-local object>'instance_name"));
else
write(v_msg_line, string'(" "));
end if;
bitvis_assert(v_line'length > 0, ERROR, "No entity name found", "get_entity_name_from_instance_name()");
return v_line.all;
end;
function adjust_leading_0(
val : string;
format : t_format_zeros := SKIP_LEADING_0
) return string is
alias a_val : string(1 to val'length) is val;
constant leftmost_non_zero : natural := pos_of_leftmost_non_zero(a_val, 1);
begin
if val'length <= 1 then
return val;
end if;
if format = SKIP_LEADING_0 then
return a_val(leftmost_non_zero to val'length);
else
return a_val;
end if;
end function;
function return_string_if_true(
val : string;
return_val : boolean
) return string is
begin
if return_val then
return val;
else
return "";
end if;
end function;
function replace_backslash_n_with_lf(
source : string
) return string is
variable v_source_idx : natural := 0;
variable v_dest_idx : natural := 0;
variable v_dest : string(1 to source'length);
begin
if source'length = 0 then
return "";
else
if C_USE_BACKSLASH_N_AS_LF then
loop
v_source_idx := v_source_idx + 1;
v_dest_idx := v_dest_idx + 1;
if (v_source_idx < source'length) then
if (source(v_source_idx to v_source_idx +1) /= "\n") then
v_dest(v_dest_idx) := source(v_source_idx);
else
v_dest(v_dest_idx) := LF;
v_source_idx := v_source_idx + 1; -- Additional increment as two chars (\n) are consumed
if (v_source_idx = source'length) then
exit;
end if;
end if;
else
-- Final character in string
v_dest(v_dest_idx) := source(v_source_idx);
exit;
end if;
end loop;
else
v_dest := source;
v_dest_idx := source'length;
end if;
return v_dest(1 to v_dest_idx);
end if;
end;
function remove_initial_chars(
source : string;
num : natural
) return string is
begin
if source'length <= num then
return "";
else
return source(1 + num to source'right);
end if;
end;
function wrap_lines(
constant text_string : string;
constant alignment_pos1 : natural; -- Line position of first aligned character in line 1
constant alignment_pos2 : natural; -- Line position of first aligned character in line 2
constant line_width : natural
) return string is
variable v_text_lines : line;
variable v_result : string(1 to 2 * text_string'length + alignment_pos1 + 100); -- Margin for aligns and LF insertions
variable v_result_width : natural;
begin
write(v_text_lines, text_string);
wrap_lines(v_text_lines, alignment_pos1, alignment_pos2, line_width);
v_result_width := v_text_lines'length;
bitvis_assert(v_result_width <= v_result'length, FAILURE,
" String is too long after wrapping. Increase v_result string size.", "wrap_lines()");
v_result(1 to v_result_width) := v_text_lines.all;
deallocate(v_text_lines);
return v_result(1 to v_result_width);
end;
procedure wrap_lines(
variable text_lines : inout line;
constant alignment_pos1 : natural; -- Line position of first aligned character in line 1
constant alignment_pos2 : natural; -- Line position of first aligned character in line 2
constant line_width : natural
) is
variable v_string : string(1 to text_lines'length) := text_lines.all;
variable v_string_width : natural := text_lines'length;
variable v_line_no : natural := 0;
variable v_last_string_wrap : natural := 0;
variable v_min_string_wrap : natural;
variable v_max_string_wrap : natural;
begin
deallocate(text_lines); -- empty the line prior to filling it up again
l_line: loop -- For every tekstline found in text_lines
v_line_no := v_line_no + 1;
-- Find position to wrap in v_string
if (v_line_no = 1) then
v_min_string_wrap := 1; -- Minimum 1 character of input line
v_max_string_wrap := minimum(line_width - alignment_pos1 + 1, v_string_width);
write(text_lines, fill_string(' ', alignment_pos1 - 1));
else
v_min_string_wrap := v_last_string_wrap + 1; -- Minimum 1 character further into the inpit line
v_max_string_wrap := minimum(v_last_string_wrap + (line_width - alignment_pos2 + 1), v_string_width);
write(text_lines, fill_string(' ', alignment_pos2 - 1));
end if;
-- 1. First handle any potential explicit line feed in the current maximum text line
-- Search forward for potential LF
for i in (v_last_string_wrap + 1) to minimum(v_max_string_wrap + 1, v_string_width) loop
if (character(v_string(i)) = LF) then
write(text_lines, v_string((v_last_string_wrap + 1) to i)); -- LF now terminates this part
v_last_string_wrap := i;
next l_line; -- next line
end if;
end loop;
-- 2. Then check if remaining text fits into a single text line
if (v_string_width <= v_max_string_wrap) then
-- No (more) wrapping required
write(text_lines, v_string((v_last_string_wrap + 1) to v_string_width));
exit; -- No more lines
end if;
-- 3. Search for blanks from char after max msg width and downwards (in the left direction)
for i in v_max_string_wrap + 1 downto (v_last_string_wrap + 1) loop
if (character(v_string(i)) = ' ') then
write(text_lines, v_string((v_last_string_wrap + 1) to i-1)); -- Exchange last blank with LF
v_last_string_wrap := i;
if (i = v_string_width ) then
exit l_line;
end if;
-- Skip any potential extra blanks in the string
for j in (i+1) to v_string_width loop
if (v_string(j) = ' ') then
v_last_string_wrap := j;
if (j = v_string_width ) then
exit l_line;
end if;
else
write(text_lines, LF); -- Exchange last blanks with LF, provided not at the end of the string
exit;
end if;
end loop;
next l_line; -- next line
end if;
end loop;
-- 4. At this point no LF or blank is found in the searched section of the string.
-- Hence just break the string - and continue.
write(text_lines, v_string((v_last_string_wrap + 1) to v_max_string_wrap) & LF); -- Added LF termination
v_last_string_wrap := v_max_string_wrap;
end loop;
end;
procedure prefix_lines(
variable text_lines : inout line;
constant prefix : string := C_LOG_PREFIX
) is
variable v_string : string(1 to text_lines'length) := text_lines.all;
variable v_string_width : natural := text_lines'length;
constant prefix_width : natural := prefix'length;
variable v_last_string_wrap : natural := 0;
variable i : natural := 0; -- for indexing v_string
begin
deallocate(text_lines); -- empty the line prior to filling it up again
l_line : loop
-- 1. Write prefix
write(text_lines, prefix);
-- 2. Write rest of text line (or rest of input line if no LF)
l_char: loop
i := i + 1;
if (i < v_string_width) then
if (character(v_string(i)) = LF) then
write(text_lines, v_string((v_last_string_wrap + 1) to i));
v_last_string_wrap := i;
exit l_char;
end if;
else
-- 3. Reached end of string. Hence just write the rest.
write(text_lines, v_string((v_last_string_wrap + 1) to v_string_width));
-- But ensure new line with prefix if ending with LF
if (v_string(i) = LF) then
write(text_lines, prefix);
end if;
exit l_char;
end if;
end loop;
if (i = v_string_width) then
exit;
end if;
end loop;
end;
function replace(
val : string;
target_char : character;
exchange_char : character
) return string is
variable result : string(1 to val'length) := val;
begin
for i in val'range loop
if val(i) = target_char then
result(i) := exchange_char;
end if;
end loop;
return result;
end;
procedure replace(
variable text_line : inout line;
target_char : character;
exchange_char : character
) is
variable v_string : string(1 to text_line'length) := text_line.all;
variable v_string_width : natural := text_line'length;
variable i : natural := 0; -- for indexing v_string
begin
if v_string_width > 0 then
deallocate(text_line); -- empty the line prior to filling it up again
-- 1. Loop through string and replace characters
l_char: loop
i := i + 1;
if (i < v_string_width) then
if (character(v_string(i)) = target_char) then
v_string(i) := exchange_char;
end if;
else
-- 2. Reached end of string. Hence just write the new string.
write(text_line, v_string);
exit l_char;
end if;
end loop;
end if;
end;
--========================================================
-- Handle missing overloads from 'standard_additions' + advanced overloads
--========================================================
function to_string(
val : boolean;
width : natural;
justified : side := right;
format : t_format_string := AS_IS
) return string is
begin
return justify(to_string(val), width, justified, format);
end;
function to_string(
val : integer;
width : natural;
justified : side := right;
format : t_format_string := AS_IS
) return string is
begin
return justify(to_string(val), width, justified, format);
end;
function to_string(
val : std_logic_vector;
radix : t_radix;
format : t_format_zeros := AS_IS; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
variable v_line : line;
alias a_val : std_logic_vector(val'length - 1 downto 0) is val;
variable v_result : string(1 to 10 + 2 * val'length); --
variable v_width : natural;
variable v_use_end_char : boolean := false;
begin
if val'length = 0 then
-- Value length is zero,
-- return empty string.
return "";
end if;
if radix = BIN then
if prefix = INCL_RADIX then
write(v_line, string'("b"""));
v_use_end_char := true;
end if;
write(v_line, adjust_leading_0(to_string(val), format));
elsif radix = HEX then
if prefix = INCL_RADIX then
write(v_line, string'("x"""));
v_use_end_char := true;
end if;
write(v_line, adjust_leading_0(to_hstring(val), format));
elsif radix = DEC then
if prefix = INCL_RADIX then
write(v_line, string'("d"""));
v_use_end_char := true;
end if;
-- Assuming that val is not signed
if (val'length > 31) then
write(v_line, to_hstring(val) & " (too wide to be converted to integer)" );
else
write(v_line, adjust_leading_0(to_string(to_integer(unsigned(val))), format));
end if;
elsif radix = HEX_BIN_IF_INVALID then
if prefix = INCL_RADIX then
write(v_line, string'("x"""));
end if;
if is_x(val) then
write(v_line, adjust_leading_0(to_hstring(val), format));
if prefix = INCL_RADIX then
write(v_line, string'("""")); -- terminate hex value
end if;
write(v_line, string'(" (b"""));
write(v_line, adjust_leading_0(to_string(val), format));
write(v_line, string'(""""));
write(v_line, string'(")"));
else
write(v_line, adjust_leading_0(to_hstring(val), format));
if prefix = INCL_RADIX then
write(v_line, string'(""""));
end if;
end if;
end if;
if v_use_end_char then
write(v_line, string'(""""));
end if;
v_width := v_line'length;
v_result(1 to v_width) := v_line.all;
deallocate(v_line);
return v_result(1 to v_width);
end;
function to_string(
val : unsigned;
radix : t_radix;
format : t_format_zeros := AS_IS; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
begin
return to_string(std_logic_vector(val), radix, format, prefix);
end;
function to_string(
val : signed;
radix : t_radix;
format : t_format_zeros := AS_IS; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
variable v_line : line;
variable v_result : string(1 to 10 + 2 * val'length); --
variable v_width : natural;
variable v_use_end_char : boolean := false;
begin
-- Support negative numbers by _not_ using the slv overload when converting to decimal
if radix = DEC then
if val'length = 0 then
-- Value length is zero,
-- return empty string.
return "";
end if;
if prefix = INCL_RADIX then
write(v_line, string'("d"""));
v_use_end_char := true;
end if;
if (val'length > 32) then
write(v_line, to_string(std_logic_vector(val),radix, format, prefix) & " (too wide to be converted to integer)" );
else
write(v_line, adjust_leading_0(to_string(to_integer(signed(val))), format));
end if;
if v_use_end_char then
write(v_line, string'(""""));
end if;
v_width := v_line'length;
v_result(1 to v_width) := v_line.all;
deallocate(v_line);
return v_result(1 to v_width);
else -- No decimal convertion: May be treated as slv, so use the slv overload
return to_string(std_logic_vector(val), radix, format, prefix);
end if;
end;
--========================================================
-- Handle types defined at lower levels
--========================================================
function to_string(
val : t_alert_level;
width : natural := 0;
justified : side := right
) return string is
constant inner_string : string := t_alert_level'image(val);
begin
return to_upper(justify(inner_string, width, justified));
end function;
function to_string(
val : t_msg_id;
width : natural := 0;
justified : side := right
) return string is
constant inner_string : string := t_msg_id'image(val);
begin
return to_upper(justify(inner_string, width, justified));
end function;
function to_string(
val : t_enabled
) return string is
begin
return to_upper(t_enabled'image(val));
end;
function to_string(
val : t_attention;
width : natural := 0;
justified : side := right
) return string is
begin
return to_upper(justify(t_attention'image(val), width, justified));
end;
procedure to_string(
val : t_alert_attention_counters;
order : t_order := FINAL
) is
variable v_line : line;
variable v_line_copy : line;
variable v_all_ok : boolean := true;
variable v_header : string(1 to 42);
constant prefix : string := C_LOG_PREFIX & " ";
begin
if order = INTERMEDIATE then
v_header := "*** INTERMEDIATE SUMMARY OF ALL ALERTS ***";
else -- order=FINAL
v_header := "*** FINAL SUMMARY OF ALL ALERTS *** ";
end if;
write(v_line,
LF &
fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
v_header & LF &
fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
" REGARDED EXPECTED IGNORED Comment?" & LF);
for i in t_alert_level'left to t_alert_level'right loop
write(v_line, " " & to_upper(to_string(i, 13, LEFT)) & ": "); -- Severity
for j in t_attention'left to t_attention'right loop
write(v_line, to_string(integer'(val(i)(j)), 6, RIGHT) & " ");
end loop;
if (val(i)(REGARD) = val(i)(EXPECT)) then
write(v_line, " ok " & LF);
else
write(v_line, " *** " & to_string(i,0) & " *** " & LF);
if (i > MANUAL_CHECK) then
v_all_ok := false;
end if;
end if;
end loop;
write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF);
-- Print a conclusion when called from the FINAL part of the test sequncer
-- but not when called from in the middle of the test sequence (order=INTERMEDIATE)
if order = FINAL then
if v_all_ok then
write(v_line, ">> Simulation SUCCESS: No mismatch between counted and expected serious alerts" & LF);
else
write(v_line, ">> Simulation FAILED, with unexpected serious alert(s)" & LF);
end if;
write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF & LF);
end if;
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-prefix'length);
prefix_lines(v_line, prefix);
-- Write the info string to the target file
write (v_line_copy, v_line.all & lf); -- copy line
writeline(OUTPUT, v_line);
writeline(LOG_FILE, v_line_copy);
end;
-- Convert from ASCII to character
-- Inputs:
-- ascii_pos (integer) : ASCII number input
-- ascii_allow (t_ascii_allow) : Decide what to do with invisible control characters:
-- - If ascii_allow = ALLOW_ALL (default) : return the character for any ascii_pos
-- - If ascii_allow = ALLOW_PRINTABLE_ONLY : return the character only if it is printable
function ascii_to_char(
ascii_pos : integer range 0 to 255; -- Supporting Extended ASCII
ascii_allow : t_ascii_allow := ALLOW_ALL
) return character is
variable v_printable : boolean := true;
begin
if ascii_pos < 32 or -- NUL, SOH, STX etc
(ascii_pos >= 128 and ascii_pos < 160) then -- C128 to C159
v_printable := false;
end if;
if ascii_allow = ALLOW_ALL or
(ascii_allow = ALLOW_PRINTABLE_ONLY and v_printable) then
return character'val(ascii_pos);
else
return ' '; -- Must return something when invisible control signals
end if;
end;
-- Convert from character to ASCII integer
function char_to_ascii(
char : character
) return integer is
begin
return character'pos(char);
end;
-- return string with only valid ascii characters
function to_string(
val : string
) return string is
variable v_new_string : string(1 to val'length);
variable v_char_idx : natural := 0;
variable v_ascii_pos : natural;
begin
for i in val'range loop
v_ascii_pos := character'pos(val(i));
if v_ascii_pos < 32 or -- NUL, SOH, STX etc
(v_ascii_pos >= 128 and v_ascii_pos < 160) then -- C128 to C159
-- illegal char
null;
else
-- legal char
v_char_idx := v_char_idx + 1;
v_new_string(v_char_idx) := val(i);
end if;
end loop;
if v_char_idx = 0 then
return "";
else
return v_new_string(1 to v_char_idx);
end if;
end;
end package body string_methods_pkg;
| gpl-2.0 | efade94080f043669703706e226b8b0a | 0.568527 | 3.88414 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1374.vhd | 4 | 6,565 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1374.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01374ent IS
END c08s05b00x00p03n01i01374ent;
ARCHITECTURE c08s05b00x00p03n01i01374arch OF c08s05b00x00p03n01i01374ent IS
BEGIN
TESTING: PROCESS
--
-- Define constants for package
--
constant lowb : integer := 1 ;
constant highb : integer := 5 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0 ;
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
variable v_st_arr3 : st_arr3 :=c_st_arr3_1 ;
--
BEGIN
v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) :=
c_st_arr3_2(st_arr3'Right(1),st_arr3'Right(2)) ;
assert NOT(v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2)
report "***PASSED TEST: c08s05b00x00p03n01i01374"
severity NOTE;
assert (v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2)
report "***FAILED TEST: c08s05b00x00p03n01i01374 - The types of the variable and the assigned variable must match."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01374arch;
| gpl-2.0 | 7382441bdd69882f75e173a85f366941 | 0.583549 | 2.933423 | false | false | false | false |
nickg/nvc | test/regress/issue484.vhd | 1 | 887 | library ieee;
use ieee.std_logic_1164.all;
entity issue484 is
end entity;
architecture beh of issue484 is
type t_data is record
sig1 : std_logic;
sig2 : std_logic_vector(7 downto 0);
sig3 : std_logic;
end record;
type t_data_array is array (natural range <>) of t_data;
signal sr : t_data_array(0 to 2) := (others => ('1', x"ff", '1'));
begin
process
begin
for i in 1 to 3 loop
sr <= sr(sr'low + 1 to sr'high) & t_data'('0', x"00", '0');
wait for 1 ns;
end loop;
wait;
end process;
process is
begin
wait for 1 ns;
assert sr(0).sig1 = '1';
assert sr(0).sig2 = x"ff";
assert sr(2).sig1 = '0';
assert sr(2).sig2 = x"00";
wait for 5 ns;
assert sr(0).sig1 = '0';
assert sr(0).sig2 = x"00";
assert sr(2).sig1 = '0';
assert sr(2).sig2 = x"00";
wait;
end process;
end architecture beh;
| gpl-3.0 | 024b05444e77964a5f1d0e1d7973263a | 0.574972 | 2.842949 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue50/vector.d/v_split1.vhd | 2 | 1,357 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity v_split1 is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(7 downto 0);
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic;
wa0_en : in std_logic;
ra0_addr : in std_logic
);
end v_split1;
architecture augh of v_split1 is
-- Embedded RAM
type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 | 57172290ce2c26d03e57092be1940f6b | 0.668386 | 2.856842 | false | false | false | false |
tgingold/ghdl | testsuite/synth/iassoc01/iassoc02.vhdl | 1 | 406 | use work.pkg.all;
entity riassoc02 is
port (v : natural;
res : out nat_rec);
end riassoc02;
architecture behav of riassoc02 is
begin
res.a <= v + 1;
res.b <= v + 2;
end behav;
entity iassoc02 is
port (v : natural;
a, b : out natural);
end iassoc02;
architecture behav of iassoc02 is
begin
inst : entity work.riassoc02
port map (v => v, res.a => a, res.b => b);
end behav;
| gpl-2.0 | 3ea1cc1e6a20f90b1b351f8c43078733 | 0.630542 | 3.007407 | false | false | false | false |
nickg/nvc | test/sem/osvvm5.vhd | 1 | 1,008 | package typepack is
type foo is (A, B, C);
function "=" (l, r : foo) return boolean;
end package;
package body typepack is
function "=" (l, r : foo) return boolean is
begin
return false;
end function;
end package body;
package genpack is
generic ( type t; def : integer );
end package;
package genpack_bitvec is new work.genpack
generic map (t => bit_vector, def => 2);
use work.typepack.all;
package genpack_foo is new work.genpack
generic map (t => foo, def => 2);
use work.genpack_foo.all;
use work.typepack.all;
entity e is
end entity;
architecture test of e is
begin
p1: process is
variable x, y : foo;
begin
assert x = y; -- OK
wait;
end process;
p2: process is
variable x : t; -- OK
variable y : integer := def;
begin
end process;
p3: process is
use work.genpack.all; -- Error
use work.genpack; -- OK
begin
end process;
end architecture;
| gpl-3.0 | a381edbfb2f2d0c329410767229da361 | 0.598214 | 3.512195 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1485.vhd | 4 | 1,925 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1485.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p04n03i01485ent IS
END c08s08b00x00p04n03i01485ent;
ARCHITECTURE c08s08b00x00p04n03i01485arch OF c08s08b00x00p04n03i01485ent IS
BEGIN
TESTING: PROCESS
variable m : severity_level := NOTE;
variable k : integer := 0;
BEGIN
case m is
when severity_level'low | severity_level'high => k := 5;
when others => NULL;
end case;
assert NOT( k = 5 )
report "***PASSED TEST: c08s08b00x00p04n03i01485"
severity NOTE;
assert ( k = 5 )
report "***FAILED TEST: c08s08b00x00p04n03i01485 - Each choice in a case statement alternative must be of the same type as the expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p04n03i01485arch;
| gpl-2.0 | 7bf05c8c09b170fe05102f17bb99fa2e | 0.658182 | 3.716216 | false | true | false | false |
lfmunoz/vhdl | ip_blocks/sip_check_data/tb_sip_check_data.vhd | 1 | 11,837 | -------------------------------------------------------------------------------------
-- FILE NAME : tb_sip_capture_x4.vhd
-- AUTHOR : Luis
-- COMPANY :
-- UNITS : Entity -
-- Architecture - Behavioral
-- LANGUAGE : VHDL
-- DATE : Jan 21, 2015
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
-- Testbench for sip_capture_x4.vhd
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- LIBRARIES
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
Library UNISIM;
use UNISIM.vcomponents.all;
Library xil_defaultlib;
-------------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------------
entity tb_sip_check_data is
end tb_sip_check_data;
-------------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------------
architecture Behavioral of tb_sip_check_data is
-------------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------------
component generic_host_emu is
generic (
global_start_addr_gen : std_logic_vector(27 downto 0);
global_stop_addr_gen : std_logic_vector(27 downto 0);
private_start_addr_gen : std_logic_vector(27 downto 0);
private_stop_addr_gen : std_logic_vector(27 downto 0)
);
port (
--Wormhole 'cmdclk_out' of type 'cmdclk_out':
cmdclk_out_cmdclk : out std_logic;
--Wormhole 'cmd_in' of type 'cmd_in':
cmd_in_cmdin : in std_logic_vector(63 downto 0);
cmd_in_cmdin_val : in std_logic;
--Wormhole 'cmd_out' of type 'cmd_out':
cmd_out_cmdout : out std_logic_vector(63 downto 0);
cmd_out_cmdout_val : out std_logic;
--Wormhole 'ifpga_rst_out' of type 'ifpga_rst_out':
ifpga_rst_out_ifpga_rst : out std_logic;
--Wormhole 'clk' of type 'clkin':
clk_clkin : in std_logic_vector(31 downto 0);
--Wormhole 'rst' of type 'rst_in':
rst_rstin : in std_logic_vector(31 downto 0);
--Wormhole 'ext_vp680_host_if' of type 'ext_vp680_host_if':
sys_clk : in std_logic;
sys_reset_n : in std_logic;
--Wormhole 'in_data' of type 'wh_in':
in_data_in_stop : out std_logic;
in_data_in_dval : in std_logic;
in_data_in_data : in std_logic_vector(63 downto 0);
--Wormhole 'out_data' of type 'wh_out':
out_data_out_stop : in std_logic;
out_data_out_dval : out std_logic;
out_data_out_data : out std_logic_vector(63 downto 0)
);
end component generic_host_emu;
-------------------------------------------------------------------------------------
-- CONSTANTS
-------------------------------------------------------------------------------------
constant CLK_10_MHZ : time := 100 ns;
constant CLK_200_MHZ : time := 5 ns;
constant CLK_125_MHZ : time := 8 ns;
constant CLK_100_MHZ : time := 10 ns;
constant CLK_368_MHZ : time := 2.7126 ns;
constant CLK_25_MHZ : time := 40 ns;
constant CLK_167_MHZ : time := 6 ns;
type bus008 is array(natural range <>) of std_logic_vector(7 downto 0);
type bus064 is array(natural range <>) of std_logic_vector(63 downto 0);
-----------------------------------------------------------------------------------
-- SIGNALS
-----------------------------------------------------------------------------------
signal sysclk_p : std_logic := '1';
signal sysclk_n : std_logic := '0';
signal clk : std_logic := '1';
signal clk200 : std_logic := '1';
signal clk100 : std_logic := '1';
signal rst : std_logic := '1';
signal rst_delay : std_logic := '1';
signal rstn : std_logic := '0';
signal rst_rstin : std_logic_vector(31 downto 0);
signal clk_clkin : std_logic_vector(31 downto 0);
signal in_cmd_val : std_logic;
signal in_cmd : std_logic_vector(63 downto 0);
signal out_cmd_val : std_logic;
signal out_cmd : std_logic_vector(63 downto 0);
signal clk_cmd : std_logic;
signal adc0_out : std_logic_vector(63 downto 0);
signal adc0_val : std_logic;
signal adc0_stop : std_logic;
signal dac0_out : std_logic_vector(63 downto 0);
signal dac0_val : std_logic;
signal dac0_stop : std_logic;
-- data generation
signal lfsr_out : std_logic_vector(2 downto 0);
signal allow : std_logic := '0';
signal samples8bit : bus008(7 downto 0) := (others=>(others=>'0'));
signal base_cnt : std_logic_vector(7 downto 0);
signal data : std_logic_vector(63 downto 0);
signal valid : std_logic;
signal shift_data : std_logic_vector(63 downto 0);
signal shift_valid : std_logic;
signal control : std_logic_vector(31 downto 0);
signal status : std_logic_vector(31 downto 0);
--***********************************************************************************
begin
--***********************************************************************************
-- Clock & reset generation
sysclk_p <= not sysclk_p after CLK_125_MHZ/2;
sysclk_n <= not sysclk_p;
clk <= not clk after CLK_125_MHZ / 2;
clk200 <= not clk200 after CLK_167_MHZ / 2;
clk100 <= not clk100 after CLK_125_MHZ / 2;
rst <= '0' after CLK_167_MHZ * 10;
rstn <= '1' after CLK_167_MHZ * 10;
rst_delay <= '0' after CLK_167_MHZ * 40;
rst_rstin <= (0=>rst, 1 => rst, 2=> rst, others =>'0');
clk_clkin <= (13 => clk200, 14 => clk100, others=>clk);
-----------------------------------------------------------
-- Host Interface
-----------------------------------------------------------
inst0_generic_host: generic_host_emu
generic map (
global_start_addr_gen => x"0000000",
global_stop_addr_gen => x"00000FF",
private_start_addr_gen => x"0000000",
private_stop_addr_gen => x"00000FF"
)
port map (
cmdclk_out_cmdclk => clk_cmd, -- out std_logic;
cmd_in_cmdin => out_cmd , -- in std_logic_vector(63 downto 0);
cmd_in_cmdin_val => out_cmd_val, -- in std_logic;
cmd_out_cmdout => in_cmd, -- out std_logic_vector(63 downto 0);
cmd_out_cmdout_val => in_cmd_val, -- out std_logic;
ifpga_rst_out_ifpga_rst => open, -- out std_logic;
clk_clkin => (others=>'0'),-- in std_logic_vector(31 downto 0);
rst_rstin => (others=>'0'),-- in std_logic_vector(31 downto 0);
sys_clk => clk, -- in std_logic;
sys_reset_n => rstn, -- in std_logic;
in_data_in_stop => adc0_stop, -- out std_logic;
in_data_in_dval => adc0_val, -- in std_logic;
in_data_in_data => adc0_out, -- in std_logic_vector(63 downto 0);
out_data_out_stop => dac0_stop, -- in std_logic;
out_data_out_dval => dac0_val, -- out std_logic;
out_data_out_data => dac0_out -- out std_logic_vector(63 downto 0)
);
IDELAYCTRL_inst : IDELAYCTRL
port map (
RDY => open, -- 1-bit output: Ready output
REFCLK => clk200, -- 1-bit input: Reference clock input
RST => '0' -- 1-bit input: Active high reset input
);
-----------------------------------------------------------
-- Unit under test
-----------------------------------------------------------
sip_capture_x4_0:
entity xil_defaultlib.sip_capture_x4
generic map (
global_start_addr_gen => x"0000000",
global_stop_addr_gen => x"0001FFF",
private_start_addr_gen => x"0000100",
private_stop_addr_gen => x"00001FF"
)
port map (
cmdclk_in_cmdclk => clk_cmd,
cmd_in_cmdin => in_cmd,
cmd_in_cmdin_val => in_cmd_val,
cmd_out_cmdout => out_cmd,
cmd_out_cmdout_val => out_cmd_val,
clk_clkin => clk_clkin,
rst_rstin => rst_rstin,
in0_in_stop => open,
in0_in_dval => shift_valid,
in0_in_data => shift_data,
in1_in_stop => open,
in1_in_dval => shift_valid,
in1_in_data => shift_data,
in2_in_stop => open,
in2_in_dval => shift_valid,
in2_in_data => shift_data,
in3_in_stop => open,
in3_in_dval => shift_valid,
in3_in_data => shift_data,
out0_out_stop => '0',
out0_out_dval => open,
out0_out_data => open,
out1_out_stop => '0',
out1_out_dval => open,
out1_out_data => open,
out2_out_stop => '0',
out2_out_dval => open,
out2_out_data => open,
out3_out_stop => '0',
out3_out_dval => open,
out3_out_data => open
);
--data_check_0:
--entity xil_defaultlib.data_check
--port map (
-- clk_in => clk200,
-- rst_in => rst,
-- data_in => generate_data,
-- valid_in => valid,
-- ctrl_in => control,
-- status_out => status
--);
-----------------------------------------------------------------------------------
-- Stimulus
-----------------------------------------------------------------------------------
process(clk200, rst_delay)
begin
if rising_edge(clk200) then
if rst_delay = '1' then
base_cnt <= (others =>'0');
valid <= '0';
allow <= '0';
else
allow <= lfsr_out(0);
if allow = '1' then
base_cnt <= base_cnt + 2;
valid <= '1';
else
valid <= '0';
end if;
end if;
end if;
end process;
samples8bit(0) <= base_cnt + 0;
samples8bit(1) <= base_cnt + 0;
samples8bit(2) <= base_cnt + 0;
samples8bit(3) <= base_cnt + 0;
samples8bit(4) <= base_cnt + 1;
samples8bit(5) <= base_cnt + 1;
samples8bit(6) <= base_cnt + 1;
samples8bit(7) <= base_cnt + 1;
data <= samples8bit(7) & samples8bit(6) & samples8bit(5) & samples8bit(4) &
samples8bit(3) & samples8bit(2) & samples8bit(1) & samples8bit(0);
shift_bytes_0:
entity work.shift_bytes
port map (
clk_in => clk200,
rst_in => rst,
data_in => data,
valid_in => valid,
data_out => shift_data,
valid_out => shift_valid,
shift_amount_in => "010"
);
-- generate sporadic data
uut: entity work.LFSR_0
generic map (
WIDTH => 3
)
port map (
clk_in => clk200,
rst_in => rst,
reg_out => lfsr_out
);
--***********************************************************************************
end architecture Behavioral;
--***********************************************************************************
| mit | 834fcd39e2e016701297107f56376e19 | 0.431866 | 3.79148 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug040/p_jinfo_comps_info_dc_tbl_no.vhd | 2 | 1,425 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity p_jinfo_comps_info_dc_tbl_no is
port (
wa0_data : in std_logic;
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std_logic;
wa0_en : in std_logic
);
end p_jinfo_comps_info_dc_tbl_no;
architecture augh of p_jinfo_comps_info_dc_tbl_no is
-- Embedded RAM
type ram_type is array (0 to 2) of std_logic;
signal ram : ram_type := (others => '0');
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 3 else '-';
end architecture;
| gpl-2.0 | ce0dfbc89ab934e940adf34220c25e9c | 0.671579 | 2.810651 | false | false | false | false |
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