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JarrettR/FPGA-Cryptoparty | FPGA/hdl/ipcore_dir/fx2_fifo/simulation/fx2_fifo_tb.vhd | 1 | 6,056 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fx2_fifo_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fx2_fifo_pkg.ALL;
ENTITY fx2_fifo_tb IS
END ENTITY;
ARCHITECTURE fx2_fifo_arch OF fx2_fifo_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
CONSTANT rd_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 400 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 200 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fx2_fifo_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fx2_fifo_synth
fx2_fifo_synth_inst:fx2_fifo_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 10
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| gpl-3.0 | ea1c006841e8e92a7be7bf4439448db8 | 0.614102 | 4.091892 | false | false | false | false |
lnls-dig/dsp-cores | hdl/modules/part_delta_sigma/part_delta_sigma.vhd | 1 | 24,542 | -------------------------------------------------------------------------------
-- Title : Partial delta/sigma core
-- Project :
-------------------------------------------------------------------------------
-- File : part_delta_sigma.vhd
-- Author : Vitor Finotti Ferreira <finotti@finotti-Inspiron-7520>
-- Company :
-- Created : 2015-07-15
-- Last update: 2022-10-18
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: This module gets a, b, c and d values and calculates x, y, q
-- and sum using the partial delta/sigma method.
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public License
-- as published by the Free Software Foundation, either version 3 of
-- the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-07-15 1.0 finotti Created
-- 2022-10-21 2.0 guilherme.ricioli Refactored and added offset stage
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dsp_cores_pkg.all;
-- computes partial terms
entity pds_first_stage is
generic (
g_WIDTH : natural := 32
);
port (
clk_i : in std_logic;
a_i : in std_logic_vector(g_WIDTH-1 downto 0);
b_i : in std_logic_vector(g_WIDTH-1 downto 0);
c_i : in std_logic_vector(g_WIDTH-1 downto 0);
d_i : in std_logic_vector(g_WIDTH-1 downto 0);
ce_i : in std_logic;
valid_i : in std_logic;
diff_ac_o : out std_logic_vector(g_WIDTH-1 downto 0);
diff_bd_o : out std_logic_vector(g_WIDTH-1 downto 0);
diff_cd_minus_diff_ba_o : out std_logic_vector(g_WIDTH-1 downto 0);
sum_ac_o : out std_logic_vector(g_WIDTH-1 downto 0);
sum_bd_o : out std_logic_vector(g_WIDTH-1 downto 0);
sum_not_scaled_o : out std_logic_vector(g_WIDTH-1 downto 0);
valid_o : out std_logic
);
end entity pds_first_stage;
architecture arch of pds_first_stage is
-- signals
signal diff_ba, diff_cd, diff_ac, diff_bd : signed(g_WIDTH-1 downto 0);
signal sum_ac, sum_bd : signed(g_WIDTH-1 downto 0);
signal valid_d0 : std_logic := '0';
begin
-- processes
process(clk_i)
variable a, b, c, d : signed(g_WIDTH-1 downto 0);
begin
-- to avoid multiple stages of combinatorial logic, the process was divided
-- into two sequential stages
if rising_edge(clk_i) then
if ce_i = '1' then
a := signed(a_i); b := signed(b_i); c := signed(c_i); d := signed(d_i);
-- first stage
diff_ba <= b - a;
diff_cd <= c - d;
diff_ac <= a - c;
diff_bd <= b - d;
sum_ac <= a + c;
sum_bd <= b + d;
valid_d0 <= valid_i;
-- second stage
diff_ac_o <= std_logic_vector(diff_ac);
diff_bd_o <= std_logic_vector(diff_bd);
sum_ac_o <= std_logic_vector(sum_ac);
sum_bd_o <= std_logic_vector(sum_bd);
sum_not_scaled_o <= std_logic_vector(sum_ac + sum_bd);
diff_cd_minus_diff_ba_o <= std_logic_vector(diff_cd - diff_ba);
valid_o <= valid_d0;
end if;
end if;
end process;
end architecture arch;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dsp_cores_pkg.all;
-- scales x, y and sum (q is just pipelined)
entity pds_scaling_stage is
generic (
g_WIDTH : natural := 32;
g_K_WIDTH : natural := 32
);
port (
clk_i : in std_logic;
diff_ac_over_sum_ac_i : in std_logic_vector(g_WIDTH-1 downto 0);
diff_ac_over_sum_ac_valid_i : in std_logic;
diff_bd_over_sum_bd_i : in std_logic_vector(g_WIDTH-1 downto 0);
diff_bd_over_sum_bd_valid_i : in std_logic;
sum_not_scaled_i : in std_logic_vector(g_WIDTH-1 downto 0);
sum_not_scaled_valid_i : in std_logic;
q_i : in std_logic_vector(g_WIDTH-1 downto 0);
q_valid_i : in std_logic;
kx_i : in std_logic_vector(g_K_WIDTH-1 downto 0);
ky_i : in std_logic_vector(g_K_WIDTH-1 downto 0);
ksum_i : in std_logic_vector(g_K_WIDTH-1 downto 0);
ce_i : in std_logic;
x_scaled_o : out std_logic_vector(g_WIDTH-1 downto 0);
y_scaled_o : out std_logic_vector(g_WIDTH-1 downto 0);
q_o : out std_logic_vector(g_WIDTH-1 downto 0);
sum_scaled_o : out std_logic_vector(g_WIDTH-1 downto 0);
valid_o : out std_logic
);
end entity pds_scaling_stage;
architecture arch of pds_scaling_stage is
-- constants
constant c_LEVELS : natural := 7;
-- signals
signal diff_ac_over_sum_ac : std_logic_vector(g_WIDTH-1 downto 0);
signal diff_bd_over_sum_bd : std_logic_vector(g_WIDTH-1 downto 0);
signal sum_not_scaled : std_logic_vector(g_WIDTH-1 downto 0);
signal q : std_logic_vector(g_WIDTH-1 downto 0);
signal x_not_scaled : std_logic_vector(g_WIDTH-1 downto 0);
signal y_not_scaled : std_logic_vector(g_WIDTH-1 downto 0);
begin
-- registering diff_ac_over_sum_ac_i
cmp_pipeline_diff_ac_over_sum_ac_i : pipeline
generic map (
g_WIDTH => g_WIDTH,
g_DEPTH => 1
)
port map (
data_i => diff_ac_over_sum_ac_i,
clk_i => clk_i,
ce_i => ce_i and diff_ac_over_sum_ac_valid_i,
data_o => diff_ac_over_sum_ac
);
-- registering diff_bd_over_sum_bd_i
cmp_pipeline_diff_bd_over_sum_bd_i : pipeline
generic map (
g_WIDTH => g_WIDTH,
g_DEPTH => 1
)
port map (
data_i => diff_bd_over_sum_bd_i,
clk_i => clk_i,
ce_i => ce_i and diff_bd_over_sum_bd_valid_i,
data_o => diff_bd_over_sum_bd
);
-- registering sum_not_scaled_i
cmp_pipeline_sum_not_scaled_i : pipeline
generic map (
g_WIDTH => g_WIDTH,
g_DEPTH => 1
)
port map (
data_i => sum_not_scaled_i,
clk_i => clk_i,
ce_i => ce_i and sum_not_scaled_valid_i,
data_o => sum_not_scaled
);
-- registering q_i
cmp_pipeline_q_i : pipeline
generic map (
g_WIDTH => g_WIDTH,
g_DEPTH => 1
)
port map (
data_i => q_i,
clk_i => clk_i,
ce_i => ce_i and q_valid_i,
data_o => q
);
-- single stage process to compute {x,y}_not_scaled
process(clk_i)
variable v_half_diff_ac_over_sum_ac : signed(g_WIDTH-1 downto 0);
variable v_half_diff_bd_over_sum_bd : signed(g_WIDTH-1 downto 0);
begin
if rising_edge(clk_i) then
if ce_i = '1' then
v_half_diff_ac_over_sum_ac := -- 0.5[(a - c)/(a + c)]
shift_right(signed(diff_ac_over_sum_ac), 1);
v_half_diff_bd_over_sum_bd := -- 0.5[(b - d)/(b + d)]
shift_right(signed(diff_bd_over_sum_bd), 1);
x_not_scaled <=
std_logic_vector(
v_half_diff_ac_over_sum_ac - v_half_diff_bd_over_sum_bd);
y_not_scaled <=
std_logic_vector(
v_half_diff_ac_over_sum_ac + v_half_diff_bd_over_sum_bd);
end if;
end if;
end process;
-- scaling x
cmp_generic_multiplier_x : generic_multiplier
generic map (
g_A_WIDTH => g_WIDTH,
g_B_WIDTH => g_K_WIDTH,
g_SIGNED => true,
g_P_WIDTH => g_WIDTH,
g_LEVELS => c_LEVELS
)
port map (
a_i => x_not_scaled,
b_i => kx_i,
valid_i => '1',
p_o => x_scaled_o,
ce_i => ce_i,
clk_i => clk_i,
rst_i => '0'
);
-- scaling y
cmp_generic_multiplier_y : generic_multiplier
generic map (
g_A_WIDTH => g_WIDTH,
g_B_WIDTH => g_K_WIDTH,
g_SIGNED => true,
g_P_WIDTH => g_WIDTH,
g_LEVELS => c_LEVELS
)
port map (
a_i => y_not_scaled,
b_i => ky_i,
valid_i => '1',
p_o => y_scaled_o,
ce_i => ce_i,
clk_i => clk_i,
rst_i => '0'
);
-- scaling sum
cmp_generic_multiplier_sum : generic_multiplier
generic map (
g_A_WIDTH => g_WIDTH,
g_B_WIDTH => g_K_WIDTH,
g_SIGNED => true,
g_P_WIDTH => g_WIDTH,
g_LEVELS => c_LEVELS
)
port map (
a_i => sum_not_scaled,
b_i => ksum_i,
valid_i => '1',
p_o => sum_scaled_o,
ce_i => ce_i,
clk_i => clk_i,
rst_i => '0'
);
-- pipelining q to tevel the delay of:
-- {x,y}_not_scaled computation (1 stage);
-- scalings (c_LEVELS + 3 stages)
cmp_pipeline_q : pipeline
generic map (
g_WIDTH => g_WIDTH,
g_DEPTH => c_LEVELS + 4
)
port map (
data_i => q,
clk_i => clk_i,
ce_i => ce_i,
data_o => q_o
);
-- pipelining valid to tevel the delay of:
-- registering (1 stage);
-- {x,y}_not_scaled computation (1 stage);
-- scalings (c_LEVELS + 3 stages)
cmp_pipeline_valid : pipeline
generic map (
g_WIDTH => 1,
g_DEPTH => c_LEVELS + 5
)
port map (
data_i(0) => q_valid_i, -- it could also be diff_{ac,bd}_over_sum_{ac,bd}_valid
clk_i => clk_i,
ce_i => ce_i,
data_o(0) => valid_o
);
end architecture arch;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dsp_cores_pkg.all;
use work.gencores_pkg.all;
-- offsets x and y
entity pds_offset_stage is
generic (
g_WIDTH : natural := 32;
g_PRECISION : natural := 8;
g_OFFSET_WIDTH : natural := 32;
g_OFFSET_PRECISION : natural := 0
);
port (
clk_i : in std_logic;
x_scaled_i : in std_logic_vector(g_WIDTH-1 downto 0);
y_scaled_i : in std_logic_vector(g_WIDTH-1 downto 0);
q_i : in std_logic_vector(g_WIDTH-1 downto 0);
sum_scaled_i : in std_logic_vector(g_WIDTH-1 downto 0);
offset_x_i : in std_logic_vector(g_OFFSET_WIDTH-1 downto 0);
offset_y_i : in std_logic_vector(g_OFFSET_WIDTH-1 downto 0);
ce_i : in std_logic;
valid_i : in std_logic;
x_o : out std_logic_vector(g_WIDTH-1 downto 0);
y_o : out std_logic_vector(g_WIDTH-1 downto 0);
q_o : out std_logic_vector(g_WIDTH-1 downto 0);
sum_o : out std_logic_vector(g_WIDTH-1 downto 0);
valid_o : out std_logic
);
end entity pds_offset_stage;
architecture arch of pds_offset_stage is
-- constants
-- 2 stages for gc_big_adder + 1 stage for registering its output
constant c_LEVELS : natural := 2+1;
-- signals
signal offset_x_n : std_logic_vector(g_WIDTH-1 downto 0);
signal offset_x_shift : std_logic_vector(g_WIDTH-1 downto 0);
signal offset_y_n : std_logic_vector(g_WIDTH-1 downto 0);
signal offset_y_shift : std_logic_vector(g_WIDTH-1 downto 0);
signal x_reg : std_logic_vector(g_WIDTH-1 downto 0);
signal x_valid_reg : std_logic;
signal y_reg : std_logic_vector(g_WIDTH-1 downto 0);
signal x : std_logic_vector(g_WIDTH-1 downto 0);
signal x_valid : std_logic;
signal y : std_logic_vector(g_WIDTH-1 downto 0);
function f_shift_left_gen (arg : signed; count : integer) return signed is
variable v_count : natural := 0;
variable v_ret : signed(arg'range);
begin
if count >= 0 then
v_count := count;
v_ret := shift_left(arg, v_count);
else
v_count := -count;
v_ret := shift_right(arg, v_count);
end if;
return v_ret;
end f_shift_left_gen;
begin
-- align binary points
offset_x_shift <=
std_logic_vector(
f_shift_left_gen(signed(offset_x_i), g_PRECISION - g_OFFSET_PRECISION));
offset_x_n <= not offset_x_shift;
offset_y_shift <=
std_logic_vector(
f_shift_left_gen(signed(offset_y_i), g_PRECISION - g_OFFSET_PRECISION));
offset_y_n <= not offset_y_shift;
-- x offset subtraction
cmp_gc_big_adder2_x_offset : gc_big_adder2
generic map (
g_DATA_BITS => g_WIDTH
)
port map (
clk_i => clk_i,
ce_i => ce_i,
stall_i => '0',
valid_i => valid_i,
a_i => x_scaled_i,
b_i => offset_x_n,
c_i => '1',
x2_o => x,
c2x2_valid_o => x_valid
);
-- gc_big_adder2 outputs are unregistered, so register them
p_x_offset_reg : process(clk_i)
begin
if rising_edge(clk_i) then
if ce_i = '1' then
x_reg <= x;
x_valid_reg <= x_valid;
end if;
end if;
end process;
x_o <= x_reg;
-- y offset subtraction
cmp_gc_big_adder2_y_offset : gc_big_adder2
generic map (
g_DATA_BITS => g_WIDTH
)
port map (
clk_i => clk_i,
ce_i => ce_i,
stall_i => '0',
valid_i => valid_i,
a_i => y_scaled_i,
b_i => offset_y_n,
c_i => '1',
x2_o => y
);
-- gc_big_adder2 outputs are unregistered, so register them
p_y_offset_reg : process(clk_i)
begin
if rising_edge(clk_i) then
if ce_i = '1' then
y_reg <= y;
end if;
end if;
end process;
y_o <= y_reg;
-- pipelining q to tevel the delay of the subtraction (c_LEVELS)
cmp_pipeline_q : pipeline
generic map (
g_WIDTH => g_WIDTH,
g_DEPTH => c_LEVELS
)
port map (
clk_i => clk_i,
ce_i => ce_i,
data_i => q_i,
data_o => q_o
);
-- pipelining sum_scaled to tevel the delay of the subtraction (c_LEVELS)
cmp_pipeline_sum_scaled : pipeline
generic map (
g_WIDTH => g_WIDTH,
g_DEPTH => c_LEVELS
)
port map (
clk_i => clk_i,
ce_i => ce_i,
data_i => sum_scaled_i,
data_o => sum_o
);
valid_o <= x_valid_reg; -- it could be y_valid_reg
end architecture arch;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dsp_cores_pkg.all;
-- main entity
-- NOTE: div_fixedpoint is not pipelined, so its delay dictates the maximum
-- input rate (currently g_WIDTH-1 ce pulses)
entity part_delta_sigma is
generic (
g_WIDTH : natural := 32;
g_K_WIDTH : natural := 24;
g_OFFSET_WIDTH : natural := 32
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
a_i : in std_logic_vector(g_WIDTH-1 downto 0); -- fp: 0
b_i : in std_logic_vector(g_WIDTH-1 downto 0); -- fp: 0
c_i : in std_logic_vector(g_WIDTH-1 downto 0); -- fp: 0
d_i : in std_logic_vector(g_WIDTH-1 downto 0); -- fp: 0
kx_i : in std_logic_vector(g_K_WIDTH-1 downto 0); -- fp: 0
ky_i : in std_logic_vector(g_K_WIDTH-1 downto 0); -- fp: 0
ksum_i : in std_logic_vector(g_K_WIDTH-1 downto 0); -- fp: 0
offset_x_i : in std_logic_vector(g_OFFSET_WIDTH-1 downto 0) := (others => '0'); -- fp: 0
offset_y_i : in std_logic_vector(g_OFFSET_WIDTH-1 downto 0) := (others => '0'); -- fp: 0
ce_i : in std_logic;
valid_i : in std_logic;
x_o : out std_logic_vector(g_WIDTH-1 downto 0); -- fp: g_WIDTH - (1+g_K_WIDTH) + 1
y_o : out std_logic_vector(g_WIDTH-1 downto 0); -- fp: g_WIDTH - (1+g_K_WIDTH) + 1
q_o : out std_logic_vector(g_WIDTH-1 downto 0); -- fp: g_WIDTH-1
sum_o : out std_logic_vector(g_WIDTH-1 downto 0); -- fp: g_WIDTH - (g_WIDTH+g_K_WIDTH) + 1
valid_o : out std_logic
);
end entity part_delta_sigma;
architecture arch of part_delta_sigma is
-- signals
signal diff_ac : std_logic_vector(g_WIDTH-1 downto 0);
signal diff_bd : std_logic_vector(g_WIDTH-1 downto 0);
signal diff_cd_minus_diff_ba : std_logic_vector(g_WIDTH-1 downto 0);
signal sum_ac : std_logic_vector(g_WIDTH-1 downto 0);
signal sum_bd : std_logic_vector(g_WIDTH-1 downto 0);
signal sum_not_scaled : std_logic_vector(g_WIDTH-1 downto 0);
signal pds_first_stage_valid : std_logic;
signal diff_ac_over_sum_ac : std_logic_vector(g_WIDTH-1 downto 0);
signal diff_ac_over_sum_ac_valid : std_logic;
signal diff_bd_over_sum_bd : std_logic_vector(g_WIDTH-1 downto 0);
signal diff_bd_over_sum_bd_valid : std_logic;
signal q_0, q_1 : std_logic_vector(g_WIDTH-1 downto 0);
signal q_valid : std_logic;
signal x_scaled : std_logic_vector(g_WIDTH-1 downto 0);
signal y_scaled : std_logic_vector(g_WIDTH-1 downto 0);
signal sum_scaled : std_logic_vector(g_WIDTH-1 downto 0);
signal pds_scaling_stage_valid : std_logic;
begin
-- components
cmp_pds_first_stage : pds_first_stage
generic map (
g_WIDTH => g_WIDTH
)
port map (
clk_i => clk_i,
a_i => a_i, -- a
b_i => b_i, -- b
c_i => c_i, -- c
d_i => d_i, -- d
ce_i => ce_i,
valid_i => valid_i,
diff_ac_o => diff_ac, -- (a - c)
diff_bd_o => diff_bd, -- (b - d)
diff_cd_minus_diff_ba_o => diff_cd_minus_diff_ba, -- [(c - d) - (b - a)]
sum_ac_o => sum_ac, -- (a + c)
sum_bd_o => sum_bd, -- (b + d)
sum_not_scaled_o => sum_not_scaled, -- (a + b + c + d)
valid_o => pds_first_stage_valid
);
cmp_div_fixedpoint_diff_ac_over_sum_ac : div_fixedpoint
generic map (
g_DATAIN_WIDTH => g_WIDTH,
g_PRECISION => g_WIDTH-1 -- ranges from -1 to "1"
)
port map (
clk_i => clk_i,
rst_i => rst_i,
ce_i => ce_i,
n_i => diff_ac, -- (a - c)
d_i => sum_ac, -- (a + c)
q_o => diff_ac_over_sum_ac, -- (a - c)/(a + c)
r_o => open,
trg_i => pds_first_stage_valid,
rdy_o => diff_ac_over_sum_ac_valid,
err_o => open
);
cmp_div_fixedpoint_diff_bd_over_sum_bd : div_fixedpoint
generic map (
g_DATAIN_WIDTH => g_WIDTH,
g_PRECISION => g_WIDTH-1 -- ranges from -1 to "1"
)
port map (
clk_i => clk_i,
rst_i => rst_i,
ce_i => ce_i,
n_i => diff_bd, -- (b - d)
d_i => sum_bd, -- (b + d)
q_o => diff_bd_over_sum_bd, -- (b - d)/(b + d)
r_o => open,
trg_i => pds_first_stage_valid,
rdy_o => diff_bd_over_sum_bd_valid,
err_o => open
);
cmp_div_fixedpoint_q : div_fixedpoint
generic map (
g_DATAIN_WIDTH => g_WIDTH,
g_PRECISION => g_WIDTH-1 -- ranges from -1 to "1"
)
port map (
clk_i => clk_i,
rst_i => rst_i,
ce_i => ce_i,
n_i => diff_cd_minus_diff_ba, -- [(c - d) - (b - a)]
d_i => sum_not_scaled, -- (a + b + c + d)
q_o => q_0, -- [(c - d) - (b - a)]/(a + b + c + d)
r_o => open,
trg_i => pds_first_stage_valid,
rdy_o => q_valid,
err_o => open
);
cmp_pds_scaling_stage : pds_scaling_stage
generic map (
g_WIDTH => g_WIDTH,
g_K_WIDTH => g_K_WIDTH
)
port map (
clk_i => clk_i,
diff_ac_over_sum_ac_i => diff_ac_over_sum_ac, -- (a - c)/(a + c)
diff_ac_over_sum_ac_valid_i => diff_ac_over_sum_ac_valid,
diff_bd_over_sum_bd_i => diff_bd_over_sum_bd, -- (b - d)/(b + d)
diff_bd_over_sum_bd_valid_i => diff_bd_over_sum_bd_valid,
sum_not_scaled_i => sum_not_scaled, -- (a + b + c + d)
sum_not_scaled_valid_i => pds_first_stage_valid,
q_i => q_0, -- [(c - d) - (b - a)]/(a + b + c + d)
q_valid_i => q_valid,
kx_i => kx_i,
ky_i => ky_i,
ksum_i => ksum_i,
ce_i => ce_i,
x_scaled_o => x_scaled, -- (kx)(0.5)[(a - c)/(a + c) - (b - d)/(b + d)]
y_scaled_o => y_scaled, -- (ky)(0.5)[(a - c)/(a + c) + (b - d)/(b + d)]
q_o => q_1, -- same as q_i
sum_scaled_o => sum_scaled, -- ksum[a + b + c + d]
valid_o => pds_scaling_stage_valid
);
cmp_pds_offset_stage : pds_offset_stage
generic map (
g_WIDTH => g_WIDTH,
g_PRECISION => g_WIDTH-g_K_WIDTH,
g_OFFSET_WIDTH => g_OFFSET_WIDTH,
g_OFFSET_PRECISION => 0
)
port map (
clk_i => clk_i,
ce_i => ce_i,
x_scaled_i => x_scaled, -- (kx)(0.5)[(a - c)/(a + c) - (b - d)/(b + d)]
y_scaled_i => y_scaled, -- (ky)(0.5)[(a - c)/(a + c) + (b - d)/(b + d)]
q_i => q_1, -- [(c - d) - (b - a)]/(a + b + c + d)
sum_scaled_i => sum_scaled, -- ksum[a + b + c + d]
valid_i => pds_scaling_stage_valid,
offset_x_i => offset_x_i,
offset_y_i => offset_y_i,
x_o => x_o, -- (kx)(0.5)[(a - c)/(a + c) - (b - d)/(b + d)] - offset_x
y_o => y_o, -- (ky)(0.5)[(a - c)/(a + c) + (b - d)/(b + d)] - offset_y
q_o => q_o, -- same as q_i
sum_o => sum_o, -- same as sum_scaled_i
valid_o => valid_o
);
end architecture arch;
| lgpl-3.0 | dcaf89ae2d414ce97821752b8def6831 | 0.463206 | 3.261829 | false | false | false | false |
SoCdesign/EHA | Simulation/Credit_Based/TB_Package_32_bit_credit_based.vhd | 1 | 11,497 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_misc.all;
package TB_Package is
function Header_gen(Packet_length, source, destination, packet_id: integer ) return std_logic_vector ;
function Body_gen(Packet_length, Data: integer ) return std_logic_vector ;
function Tail_gen(Packet_length, Data: integer ) return std_logic_vector ;
procedure credit_counter_control(signal clk: in std_logic;
signal credit_in: in std_logic; signal valid_out: in std_logic;
signal credit_counter_out: out std_logic_vector(1 downto 0));
procedure gen_random_packet(frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector);
procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal credit_out: out std_logic; signal valid_in: in std_logic; signal port_in: in std_logic_vector);
procedure gen_fault(signal sta_0, sta_1: out std_logic; signal address: out std_logic_vector; delay, seed_1, seed_2: in integer);
end TB_Package;
package body TB_Package is
constant Header_type : std_logic_vector := "001";
constant Body_type : std_logic_vector := "010";
constant Tail_type : std_logic_vector := "100";
function Header_gen(Packet_length, source, destination, packet_id: integer)
return std_logic_vector is
variable Header_flit: std_logic_vector (31 downto 0);
begin
Header_flit := Header_type & std_logic_vector(to_unsigned(Packet_length, 12)) & std_logic_vector(to_unsigned(destination, 4)) &
std_logic_vector(to_unsigned(source, 4)) & std_logic_vector(to_unsigned(packet_id, 8)) & XOR_REDUCE(Header_type &
std_logic_vector(to_unsigned(Packet_length, 12)) & std_logic_vector(to_unsigned(destination, 4)) &
std_logic_vector(to_unsigned(source, 4)) & std_logic_vector(to_unsigned(packet_id, 8)));
return Header_flit;
end Header_gen;
function Body_gen(Packet_length, Data: integer)
return std_logic_vector is
variable Body_flit: std_logic_vector (31 downto 0);
begin
Body_flit := Body_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Body_type & std_logic_vector(to_unsigned(Data, 28)));
return Body_flit;
end Body_gen;
function Tail_gen(Packet_length, Data: integer)
return std_logic_vector is
variable Tail_flit: std_logic_vector (31 downto 0);
begin
Tail_flit := Tail_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Tail_type & std_logic_vector(to_unsigned(Data, 28)));
return Tail_flit;
end Tail_gen;
procedure credit_counter_control(signal clk: in std_logic;
signal credit_in: in std_logic; signal valid_out: in std_logic;
signal credit_counter_out: out std_logic_vector(1 downto 0)) is
variable credit_counter: std_logic_vector (1 downto 0);
begin
credit_counter := "11";
while true loop
credit_counter_out<= credit_counter;
wait until clk'event and clk ='1';
if valid_out = '1' and credit_in ='1' then
credit_counter := credit_counter;
elsif credit_in = '1' then
credit_counter := credit_counter + 1;
elsif valid_out = '1' and credit_counter > 0 then
credit_counter := credit_counter - 1;
else
credit_counter := credit_counter;
end if;
end loop;
end credit_counter_control;
procedure gen_random_packet(frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector) is
variable seed1 :positive ;
variable seed2 :positive ;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
variable rand : real ;
variable destination_id: integer;
variable id_counter, frame_starting_delay, Packet_length, frame_ending_delay : integer:= 0;
variable credit_counter: std_logic_vector (1 downto 0);
begin
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
valid_out <= '0';
port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ;
wait until clk'event and clk ='1';
for i in 0 to initial_delay loop
wait until clk'event and clk ='1';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
while true loop
--generating the frame initial delay
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - 3*Packet_length)))/100);
--generating the frame ending delay
frame_ending_delay := frame_length - (3*Packet_length+frame_starting_delay);
for k in 0 to frame_starting_delay-1 loop
wait until clk'event and clk ='0';
end loop;
valid_out <= '0';
while credit_counter_in = 0 loop
wait until clk'event and clk ='0';
end loop;
-- generating the packet
id_counter := id_counter + 1;
--------------------------------------
uniform(seed1, seed2, rand);
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
if (Packet_length < min_packet_size) then
Packet_length:=min_packet_size;
end if;
if (Packet_length > max_packet_size) then
Packet_length:=max_packet_size;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
destination_id := integer(rand*3.0);
while (destination_id = source) loop
uniform(seed1, seed2, rand);
destination_id := integer(rand*3.0);
end loop;
--------------------------------------
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(id_counter));
writeline(VEC_FILE, LINEVARIABLE);
wait until clk'event and clk ='0';
port_in <= Header_gen(Packet_length, source, destination_id, id_counter);
valid_out <= '1';
wait until clk'event and clk ='0';
--valid_out <= '0';
--while credit_counter_in = 0 loop
-- wait until clk'event and clk ='1';
--end loop;
for I in 0 to Packet_length-3 loop
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
port_in <= Body_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
--valid_out <= '0';
--while credit_counter_in = 0 loop
-- wait until clk'event and clk ='0';
--end loop;
--wait until clk'event and clk ='1';
end loop;
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
port_in <= Tail_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
valid_out <= '0';
port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ;
for l in 0 to frame_ending_delay-1 loop
wait until clk'event and clk ='0';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
if now > finish_time then
wait;
end if;
end loop;
end gen_random_packet;
procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal credit_out: out std_logic; signal valid_in: in std_logic; signal port_in: in std_logic_vector) is
-- initial_delay: waits for this number of clock cycles before sending the packet!
variable source_node, destination_node, P_length, packet_id, counter: integer;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "received.txt";
begin
credit_out <= '1';
counter := 0;
while true loop
wait until clk'event and clk ='1';
if valid_in = '1' then
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001") then
counter := 1;
P_length := to_integer(unsigned(port_in(28 downto 17)));
destination_node := to_integer(unsigned(port_in(16 downto 13)));
source_node := to_integer(unsigned(port_in(12 downto 9)));
packet_id := to_integer(unsigned(port_in(8 downto 1)));
end if;
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010") then
report "flit type: " &integer'image(to_integer(unsigned(port_in(DATA_WIDTH-1 downto DATA_WIDTH-3)))) ;
report "counter: " & integer'image(counter);
counter := counter+1;
end if;
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100") then
counter := counter+1;
report "Packet received at " & time'image(now) & " From " & integer'image(source_node) & " to " & integer'image(destination_node) & " with length: "& integer'image(P_length) & " counter: "& integer'image(counter);
assert (P_length=counter) report "wrong packet size" severity warning;
assert (Node_ID=destination_node) report "wrong packet destination " severity failure;
write(LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(source_node) & " to: " & integer'image(destination_node) & " length: "& integer'image(P_length) & " actual length: "& integer'image(counter) & " id: "& integer'image(packet_id));
writeline(VEC_FILE, LINEVARIABLE);
counter := 0;
end if;
end if;
end loop;
end get_packet;
procedure gen_fault(signal sta_0, sta_1: out std_logic; signal address: out std_logic_vector; delay, seed_1, seed_2: in integer) is
variable seed1 :positive := seed_1;
variable seed2 :positive := seed_2;
variable rand : real;
variable stuck: integer;
begin
sta_0 <= '0';
sta_1 <= '0';
while true loop
sta_0 <= '0';
sta_1 <= '0';
for I in 0 to delay loop
wait for 1 ns;
end loop;
uniform(seed1, seed2, rand);
address <= std_logic_vector(to_unsigned(integer(rand*31.0), 5));
uniform(seed1, seed2, rand);
stuck := integer(rand*11.0);
if stuck > 5 then
sta_0 <= '1';
sta_1 <= '0';
else
sta_0 <= '0';
sta_1 <= '1';
end if;
wait for 1 ns;
end loop;
end gen_fault;
end TB_Package;
| gpl-3.0 | fba459879d1f87811d8fec6c015e59a9 | 0.594938 | 3.746171 | false | false | false | false |
TUM-LIS/faultify | hardware/testcases/fpu100_div/fpga_sim/xpsLibraryPath/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/vhdl/user_logic.vhd | 1 | 29,243 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Fri May 16 15:25:24 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
faultify_clk_fast : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
component faultify_top
generic (
numInj : integer;
numIn : integer;
numOut : integer);
port (
aclk : in std_logic;
arst_n : in std_logic;
clk : in std_logic;
clk_x32 : in std_logic;
awvalid : in std_logic;
awaddr : in std_logic_vector(31 downto 0);
wvalid : in std_logic;
wdata : in std_logic_vector(31 downto 0);
arvalid : in std_logic;
araddr : in std_logic_vector(31 downto 0);
rvalid : out std_logic;
rdata : out std_logic_vector(31 downto 0));
end component;
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal register_write_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal register_read_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal register_write_address : std_logic_vector(C_NUM_REG-1 downto 0);
signal register_read_address : std_logic_vector(C_NUM_REG-1 downto 0);
signal slv_reg_write_sel : std_logic_vector(31 downto 0);
signal slv_reg_read_sel : std_logic_vector(31 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal faultify_read_valid : std_logic;
signal faultify_read_address_valid : std_logic;
signal faultify_read_address : std_logic_vector(31 downto 0);
signal faultify_write_valid : std_logic;
signal counter, divide : integer := 0;
signal faultify_clk_slow_i : std_logic;
begin
slv_reg_write_sel <= Bus2IP_WrCE(31 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(31 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12) or Bus2IP_WrCE(13) or Bus2IP_WrCE(14) or Bus2IP_WrCE(15) or Bus2IP_WrCE(16) or Bus2IP_WrCE(17) or Bus2IP_WrCE(18) or Bus2IP_WrCE(19) or Bus2IP_WrCE(20) or Bus2IP_WrCE(21) or Bus2IP_WrCE(22) or Bus2IP_WrCE(23) or Bus2IP_WrCE(24) or Bus2IP_WrCE(25) or Bus2IP_WrCE(26) or Bus2IP_WrCE(27) or Bus2IP_WrCE(28) or Bus2IP_WrCE(29) or Bus2IP_WrCE(30) or Bus2IP_WrCE(31);
slv_read_ack <= faultify_read_valid;
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process(Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
register_write_data <= (others => '0');
register_write_address <= (others => '0');
faultify_write_valid <= '0';
else
faultify_write_valid <= slv_write_ack;
case slv_reg_write_sel is
when "10000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(0, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "01000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(1, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00100000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(2, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00010000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(3, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00001000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(4, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000100000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(5, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000010000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(6, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000001000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(7, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000100000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(8, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000010000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(9, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000001000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(10, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000100000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(11, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000010000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(12, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000001000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(13, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000100000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(14, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000010000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(15, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000001000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(16, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000100000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(17, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000010000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(18, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000001000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(19, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000100000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(20, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000010000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(21, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000001000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(22, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000100000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(23, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000010000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(24, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000001000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(25, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(26, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(27, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(28, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(29, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(30, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(31, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process(slv_reg_read_sel, faultify_read_valid) is
begin
faultify_read_address_valid <= '1';
case slv_reg_read_sel is
when "10000000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(0, 32));
when "01000000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(1, 32));
when "00100000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(2, 32));
when "00010000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(3, 32));
when "00001000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(4, 32));
when "00000100000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(5, 32));
when "00000010000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(6, 32));
when "00000001000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(7, 32));
when "00000000100000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(8, 32));
when "00000000010000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(9, 32));
when "00000000001000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(10, 32));
when "00000000000100000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(11, 32));
when "00000000000010000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(12, 32));
when "00000000000001000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(13, 32));
when "00000000000000100000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(14, 32));
when "00000000000000010000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(15, 32));
when "00000000000000001000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(16, 32));
when "00000000000000000100000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(17, 32));
when "00000000000000000010000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(18, 32));
when "00000000000000000001000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(19, 32));
when "00000000000000000000100000000000" => faultify_read_address <= std_logic_vector(to_unsigned(20, 32));
when "00000000000000000000010000000000" => faultify_read_address <= std_logic_vector(to_unsigned(21, 32));
when "00000000000000000000001000000000" => faultify_read_address <= std_logic_vector(to_unsigned(22, 32));
when "00000000000000000000000100000000" => faultify_read_address <= std_logic_vector(to_unsigned(23, 32));
when "00000000000000000000000010000000" => faultify_read_address <= std_logic_vector(to_unsigned(24, 32));
when "00000000000000000000000001000000" => faultify_read_address <= std_logic_vector(to_unsigned(25, 32));
when "00000000000000000000000000100000" => faultify_read_address <= std_logic_vector(to_unsigned(26, 32));
when "00000000000000000000000000010000" => faultify_read_address <= std_logic_vector(to_unsigned(27, 32));
when "00000000000000000000000000001000" => faultify_read_address <= std_logic_vector(to_unsigned(28, 32));
when "00000000000000000000000000000100" => faultify_read_address <= std_logic_vector(to_unsigned(29, 32));
when "00000000000000000000000000000010" => faultify_read_address <= std_logic_vector(to_unsigned(30, 32));
when "00000000000000000000000000000001" => faultify_read_address <= std_logic_vector(to_unsigned(31, 32));
when others => faultify_read_address <= (others => '0');
faultify_read_address_valid <= '0';
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= register_read_data when faultify_read_valid = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
-----------------------------------------------------------------------------
-- clock divider 32 -> 1
-----------------------------------------------------------------------------
divide <= 32;
process(Bus2IP_Clk, Bus2IP_Resetn)
begin
if Bus2IP_Resetn = '0' then
counter <= 0;
faultify_clk_slow_i <= '0';
elsif(rising_edge(Bus2IP_Clk)) then
if(counter < divide/2-1) then
counter <= counter + 1;
faultify_clk_slow_i <= '0';
elsif(counter < divide-1) then
counter <= counter + 1;
faultify_clk_slow_i <= '1';
else
faultify_clk_slow_i <= '0';
counter <= 0;
end if;
end if;
end process;
faultify_top_1 : faultify_top
generic map (
numInj => 268,
numIn => 70,
numOut => 41)
port map (
aclk => Bus2IP_Clk,
arst_n => Bus2IP_Resetn,
clk => faultify_clk_slow_i,
clk_x32 => Bus2IP_Clk,
awvalid => faultify_write_valid,
awaddr => register_write_address,
wvalid => faultify_write_valid,
wdata => register_write_data,
arvalid => faultify_read_address_valid,
araddr => faultify_read_address,
rvalid => faultify_read_valid,
rdata => register_read_data);
end IMP;
| gpl-2.0 | a231480bf5b2e5b367215ef160e2a4d6 | 0.539309 | 4.022974 | false | false | false | false |
JarrettR/FPGA-Cryptoparty | FPGA/hdl/hmac_cache.vhd | 1 | 2,241 | --------------------------------------------------------------------------------
-- hmac_cache.vhd
-- Calculates and caches initial SHA1 H0-H5 vars for HMAC algorithm
-- Copyright (C) 2016 Jarrett Rainier
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.sha1_pkg.all;
entity hmac_cache is
port(
clk_i : in std_ulogic;
rst_i : in std_ulogic;
secret_i : in std_ulogic_vector(0 to 31);
load_i : in std_ulogic;
dat_bi_o : out w_input;
dat_h_o : out w_output;
valid_o : out std_ulogic
);
end hmac_cache;
architecture RTL of hmac_cache is
signal bi: w_input;
signal bo: w_output;
signal i : integer range 0 to 15;
begin
process(clk_i)
begin
if (clk_i'event and clk_i = '1') then
if rst_i = '1' then
i <= 0;
valid_o <= '0';
else
if load_i = '1' then
bi(i) <= X"36363636" xor secret_i;
bo(i) <= X"5c5c5c5c" xor secret_i;
end if;
if i = 15 then
valid_o <= '1';
else
i <= i + 1;
valid_o <= '0';
end if;
end if;
end if;
end process;
dat_bi_o <= bi;
end RTL; | gpl-3.0 | 82721e8dbb836e71a36f0b488cf4c444 | 0.475234 | 3.973404 | false | false | false | false |
SoCdesign/EHA | RTL/Immortal_Chip/Channel_32_bit_with_dominant_checkers_shift_register.vhd | 1 | 17,933 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_misc.all;
entity router_channel is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 5;
Rxy_rst : integer := 60;
Cx_rst : integer := 15;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
DCTS : in std_logic;
DRTS : in std_logic;
RTS : out std_logic;
CTS : out std_logic;
flit_type : in std_logic_vector(2 downto 0);
destination_address : in std_logic_vector(NoC_size-1 downto 0);
Grant_N_in , Grant_E_in , Grant_W_in , Grant_S_in , Grant_L_in : in std_logic;
Req_N_in , Req_E_in , Req_W_in , Req_S_in , Req_L_in :in std_logic;
shift : in std_logic;
Grant_N_out, Grant_E_out, Grant_W_out, Grant_S_out, Grant_L_out: out std_logic;
Req_N_out , Req_E_out, Req_W_out, Req_S_out, Req_L_out:out std_logic;
read_pointer_out, write_pointer_out: out std_logic_vector(3 downto 0);
write_en_out :out std_logic;
Xbar_sel: out std_logic_vector(4 downto 0);
error_signal_sync: out std_logic; -- this is the or of all outputs of the shift register
error_signal_async: out std_logic; -- this is the or of all outputs of the checkers
shift_serial_data: out std_logic
);
end router_channel;
architecture behavior of router_channel is
COMPONENT FIFO is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
DRTS: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
CTS: out std_logic;
empty_out: out std_logic;
read_pointer_out, write_pointer_out: out std_logic_vector(3 downto 0);
write_en_out :out std_logic;
-- Checker outputs
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
--err_CTS_in,
err_write_en,
err_not_CTS_in,
--err_not_write_en,
err_read_en_mismatch : out std_logic
);
end COMPONENT;
COMPONENT Arbiter
port (reset: in std_logic;
clk: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules
DCTS: in std_logic; -- Getting the CTS signal from the input FIFO of the next router/NI (for hand-shaking)
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
Xbar_sel : out std_logic_vector(4 downto 0); -- select lines for XBAR
RTS: out std_logic; -- Valid output which is sent to the next router/NI to specify that the data on the output port is valid
-- Checker outputs
err_state_IDLE_xbar,
err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE,
err_IDLE_Req_L,
err_Local_Req_L,
err_North_Req_N,
err_IDLE_Req_N,
err_Local_Req_N,
err_South_Req_L,
err_West_Req_L,
err_South_Req_N,
err_East_Req_L,
err_West_Req_N,
err_East_Req_N,
err_next_state_onehot,
err_state_in_onehot,
err_state_north_xbar_sel,
err_state_east_xbar_sel,
err_state_west_xbar_sel,
err_state_south_xbar_sel : out std_logic
);
end COMPONENT;
COMPONENT LBDR is
generic (
cur_addr_rst: integer := 5;
Rxy_rst: integer := 60;
Cx_rst: integer := 15;
NoC_size: integer := 4
);
port (reset: in std_logic;
clk: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic;
-- Checker outputs
--err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in : out std_logic
);
end COMPONENT;
COMPONENT shift_register is
generic (
REG_WIDTH: integer := 8
);
port (
clk, reset : in std_logic;
shift: in std_logic;
data_in: in std_logic_vector(REG_WIDTH-1 downto 0);
data_out_parallel: in std_logic_vector(REG_WIDTH-1 downto 0);
data_out_serial: out std_logic
);
end COMPONENT;
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal empty: std_logic;
signal combined_error_signals: std_logic_vector(58 downto 0);
signal shift_parallel_data: std_logic_vector(58 downto 0);
-- Signals related to Checkers
-- LBDR Checkers signals
signal err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in, err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in : std_logic;
-- Arbiter Checkers signals
signal err_state_IDLE_xbar, err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in, err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in, err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in, err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state, err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants, err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot, err_Requests_next_state_IDLE,
err_IDLE_Req_L, err_Local_Req_L, err_North_Req_N, err_IDLE_Req_N, err_Local_Req_N,
err_South_Req_L, err_West_Req_L, err_South_Req_N, err_East_Req_L,
err_West_Req_N, err_East_Req_N, err_next_state_onehot, err_state_in_onehot,
err_state_north_xbar_sel, err_state_east_xbar_sel,
err_state_west_xbar_sel, err_state_south_xbar_sel : std_logic;
-- FIFO Control Part Checkers signals
signal err_write_en_write_pointer, err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full,
err_read_pointer_increment, err_read_pointer_not_increment,
err_write_en, err_not_CTS_in, err_read_en_mismatch : std_logic;
begin
-- OR of checker outputs
error_signal_sync <= OR_REDUCE(shift_parallel_data);
error_signal_async <= OR_REDUCE(combined_error_signals);
-- making the shift register input signal
-- please keep this like this, i use this for counting the number of the signals.
combined_error_signals <= err_header_empty_Requests_FF_Requests_in &
err_tail_Requests_in_all_zero &
err_header_tail_Requests_FF_Requests_in &
err_dst_addr_cur_addr_N1 &
err_dst_addr_cur_addr_not_N1 &
err_dst_addr_cur_addr_E1 &
err_dst_addr_cur_addr_not_E1 &
err_dst_addr_cur_addr_W1 &
err_dst_addr_cur_addr_not_W1 &
err_dst_addr_cur_addr_S1 &
err_dst_addr_cur_addr_not_S1 &
err_dst_addr_cur_addr_not_Req_L_in &
err_dst_addr_cur_addr_Req_L_in &
err_header_not_empty_Req_N_in &
err_header_not_empty_Req_E_in &
err_header_not_empty_Req_W_in &
err_header_not_empty_Req_S_in &
err_state_IDLE_xbar &
err_state_not_IDLE_xbar &
err_state_IDLE_RTS_FF_in &
err_state_not_IDLE_RTS_FF_RTS_FF_in &
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in &
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in &
err_RTS_FF_not_DCTS_state_state_in &
err_not_RTS_FF_state_in_next_state &
err_RTS_FF_DCTS_state_in_next_state &
err_not_DCTS_Grants &
err_DCTS_not_RTS_FF_Grants &
err_DCTS_RTS_FF_IDLE_Grants &
err_DCTS_RTS_FF_not_IDLE_Grants_onehot &
err_Requests_next_state_IDLE &
err_IDLE_Req_L &
err_Local_Req_L &
err_North_Req_N &
err_IDLE_Req_N &
err_Local_Req_N &
err_South_Req_L &
err_West_Req_L &
err_South_Req_N &
err_East_Req_L &
err_West_Req_N &
err_East_Req_N &
err_next_state_onehot &
err_state_in_onehot &
err_state_north_xbar_sel &
err_state_east_xbar_sel &
err_state_west_xbar_sel &
err_state_south_xbar_sel &
err_write_en_write_pointer &
err_not_write_en_write_pointer &
err_read_pointer_write_pointer_not_empty &
err_read_pointer_write_pointer_empty &
err_read_pointer_write_pointer_not_full &
err_read_pointer_write_pointer_full &
err_read_pointer_increment &
err_read_pointer_not_increment &
err_write_en &
err_not_CTS_in &
err_read_en_mismatch;
---------------------------------------------------------------------------------------------------------------------------
FIFO_unit: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, DRTS => DRTS,
read_en_N => Grant_N_in, read_en_E =>Grant_E_in, read_en_W =>Grant_W_in, read_en_S =>Grant_S_in, read_en_L =>Grant_L_in,
CTS => CTS, empty_out => empty,
read_pointer_out => read_pointer_out, write_pointer_out => write_pointer_out,
write_en_out => write_en_out,
err_write_en_write_pointer => err_write_en_write_pointer,
err_not_write_en_write_pointer => err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => err_read_pointer_write_pointer_full,
err_read_pointer_increment => err_read_pointer_increment,
err_read_pointer_not_increment => err_read_pointer_not_increment,
err_write_en => err_write_en,
err_not_CTS_in => err_not_CTS_in,
err_read_en_mismatch => err_read_en_mismatch
);
------------------------------------------------------------------------------------------------------------------------------
LBDR_unit: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty, flit_type => flit_type, dst_addr=> destination_address,
Req_N=> Req_N_out, Req_E=>Req_E_out, Req_W=>Req_W_out, Req_S=>Req_S_out, Req_L=>Req_L_out,
err_header_empty_Requests_FF_Requests_in => err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in => err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => err_header_not_empty_Req_S_in
);
------------------------------------------------------------------------------------------------------------------------------
Arbiter_unit: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_N_in , Req_E => Req_E_in, Req_W => Req_W_in, Req_S => Req_S_in, Req_L => Req_L_in,
DCTS => DCTS, Grant_N => Grant_N_out, Grant_E => Grant_E_out, Grant_W => Grant_W_out, Grant_S => Grant_S_out, Grant_L => Grant_L_out,
Xbar_sel => Xbar_sel,
RTS => RTS,
err_state_IDLE_xbar => err_state_IDLE_xbar ,
err_state_not_IDLE_xbar => err_state_not_IDLE_xbar ,
err_state_IDLE_RTS_FF_in => err_state_IDLE_RTS_FF_in ,
err_state_not_IDLE_RTS_FF_RTS_FF_in => err_state_not_IDLE_RTS_FF_RTS_FF_in ,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in ,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in ,
err_RTS_FF_not_DCTS_state_state_in => err_RTS_FF_not_DCTS_state_state_in ,
err_not_RTS_FF_state_in_next_state => err_not_RTS_FF_state_in_next_state ,
err_RTS_FF_DCTS_state_in_next_state => err_RTS_FF_DCTS_state_in_next_state ,
err_not_DCTS_Grants => err_not_DCTS_Grants ,
err_DCTS_not_RTS_FF_Grants => err_DCTS_not_RTS_FF_Grants ,
err_DCTS_RTS_FF_IDLE_Grants => err_DCTS_RTS_FF_IDLE_Grants ,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => err_DCTS_RTS_FF_not_IDLE_Grants_onehot ,
err_Requests_next_state_IDLE => err_Requests_next_state_IDLE ,
err_IDLE_Req_L => err_IDLE_Req_L ,
err_Local_Req_L => err_Local_Req_L ,
err_North_Req_N => err_North_Req_N ,
err_IDLE_Req_N => err_IDLE_Req_N ,
err_Local_Req_N => err_Local_Req_N ,
err_South_Req_L => err_South_Req_L ,
err_West_Req_L => err_West_Req_L ,
err_South_Req_N => err_South_Req_N ,
err_East_Req_L => err_East_Req_L ,
err_West_Req_N => err_West_Req_N ,
err_East_Req_N => err_East_Req_N ,
err_next_state_onehot => err_next_state_onehot ,
err_state_in_onehot => err_state_in_onehot ,
err_state_north_xbar_sel => err_state_north_xbar_sel ,
err_state_east_xbar_sel => err_state_east_xbar_sel ,
err_state_west_xbar_sel => err_state_west_xbar_sel ,
err_state_south_xbar_sel => err_state_south_xbar_sel
);
checker_shifter: shift_register generic map (REG_WIDTH => 59)
port map (
clk => clk, reset => reset,
shift => shift,
data_in => combined_error_signals,
data_out_parallel => shift_parallel_data,
data_out_serial => shift_serial_data
);
end;
| gpl-3.0 | 5340b4e4133f4fb3da52733312c6ca09 | 0.544415 | 3.259953 | false | false | false | false |
SoCdesign/EHA | RTL/Fault_Management/Fault_management_network/allocator_LV.vhd | 1 | 10,170 | --Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator_LV is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic
);
end allocator_LV;
architecture behavior of allocator_LV is
-- so the idea is that we should have counters that keep track of credit!
signal credit_counter_N_in, credit_counter_N_out: std_logic_vector(1 downto 0);
signal credit_counter_E_in, credit_counter_E_out: std_logic_vector(1 downto 0);
signal credit_counter_W_in, credit_counter_W_out: std_logic_vector(1 downto 0);
signal credit_counter_S_in, credit_counter_S_out: std_logic_vector(1 downto 0);
signal credit_counter_L_in, credit_counter_L_out: std_logic_vector(1 downto 0);
signal grant_N, grant_E, grant_W, grant_S, grant_L: std_logic;
signal grant_N_N_sig, grant_N_E_sig, grant_N_W_sig, grant_N_S_sig, grant_N_L_sig: std_logic;
signal grant_E_N_sig, grant_E_E_sig, grant_E_W_sig, grant_E_S_sig, grant_E_L_sig: std_logic;
signal grant_W_N_sig, grant_W_E_sig, grant_W_W_sig, grant_W_S_sig, grant_W_L_sig: std_logic;
signal grant_S_N_sig, grant_S_E_sig, grant_S_W_sig, grant_S_S_sig, grant_S_L_sig: std_logic;
signal grant_L_N_sig, grant_L_E_sig, grant_L_W_sig, grant_L_S_sig, grant_L_L_sig: std_logic;
component arbiter_out is
port ( reset: in std_logic;
clk: in std_logic;
X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y:in std_logic; -- From LBDR modules
credit: in std_logic_vector(1 downto 0);
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L :out std_logic -- Grants given to LBDR requests (encoded as one-hot)
);
end component;
begin
-- sequential part
process(clk, reset)
begin
if reset = '0' then
-- we start with all full cradit
credit_counter_N_out <= "01";
credit_counter_E_out <= "01";
credit_counter_W_out <= "01";
credit_counter_S_out <= "01";
credit_counter_L_out <= "01";
elsif clk'event and clk = '1' then
credit_counter_N_out <= credit_counter_N_in;
credit_counter_E_out <= credit_counter_E_in;
credit_counter_W_out <= credit_counter_W_in;
credit_counter_S_out <= credit_counter_S_in;
credit_counter_L_out <= credit_counter_L_in;
end if;
end process;
-- The combionational part
grant_N_N <= grant_N_N_sig and not empty_N;
grant_N_E <= grant_N_E_sig and not empty_E;
grant_N_W <= grant_N_W_sig and not empty_W;
grant_N_S <= grant_N_S_sig and not empty_S;
grant_N_L <= grant_N_L_sig and not empty_L;
grant_E_N <= grant_E_N_sig and not empty_N;
grant_E_E <= grant_E_E_sig and not empty_E;
grant_E_W <= grant_E_W_sig and not empty_W;
grant_E_S <= grant_E_S_sig and not empty_S;
grant_E_L <= grant_E_L_sig and not empty_L;
grant_W_N <= grant_W_N_sig and not empty_N;
grant_W_E <= grant_W_E_sig and not empty_E;
grant_W_W <= grant_W_W_sig and not empty_W;
grant_W_S <= grant_W_S_sig and not empty_S;
grant_W_L <= grant_W_L_sig and not empty_L;
grant_S_N <= grant_S_N_sig and not empty_N;
grant_S_E <= grant_S_E_sig and not empty_E;
grant_S_W <= grant_S_W_sig and not empty_W;
grant_S_S <= grant_S_S_sig and not empty_S;
grant_S_L <= grant_S_L_sig and not empty_L;
grant_L_N <= grant_L_N_sig and not empty_N;
grant_L_E <= grant_L_E_sig and not empty_E;
grant_L_W <= grant_L_W_sig and not empty_W;
grant_L_S <= grant_L_S_sig and not empty_S;
grant_L_L <= grant_L_L_sig and not empty_L;
grant_N <= (grant_N_N_sig and not empty_N )or (grant_N_E_sig and not empty_E) or (grant_N_W_sig and not empty_W) or (grant_N_S_sig and not empty_S) or (grant_N_L_sig and not empty_L);
grant_E <= (grant_E_N_sig and not empty_N )or (grant_E_E_sig and not empty_E) or (grant_E_W_sig and not empty_W) or (grant_E_S_sig and not empty_S) or (grant_E_L_sig and not empty_L);
grant_W <= (grant_W_N_sig and not empty_N )or (grant_W_E_sig and not empty_E) or (grant_W_W_sig and not empty_W) or (grant_W_S_sig and not empty_S) or (grant_W_L_sig and not empty_L);
grant_S <= (grant_S_N_sig and not empty_N )or (grant_S_E_sig and not empty_E) or (grant_S_W_sig and not empty_W) or (grant_S_S_sig and not empty_S) or (grant_S_L_sig and not empty_L);
grant_L <= (grant_L_N_sig and not empty_N )or (grant_L_E_sig and not empty_E) or (grant_L_W_sig and not empty_W) or (grant_L_S_sig and not empty_S) or (grant_L_L_sig and not empty_L);
-- this process handels the credit counters!
process(credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L, grant_N, grant_E, grant_W, grant_S, grant_L,
credit_counter_N_out, credit_counter_E_out, credit_counter_W_out, credit_counter_S_out, credit_counter_L_out
)
begin
credit_counter_N_in <= credit_counter_N_out;
credit_counter_E_in <= credit_counter_E_out;
credit_counter_W_in <= credit_counter_W_out;
credit_counter_S_in <= credit_counter_S_out;
credit_counter_L_in <= credit_counter_L_out;
if credit_in_N = '1' and credit_counter_N_out < 1 then
credit_counter_N_in <= credit_counter_N_out + 1;
end if;
if grant_N = '1' then
credit_counter_N_in <= credit_counter_N_out - 1;
end if;
if credit_in_E = '1' and credit_counter_E_out < 1 then
credit_counter_E_in <= credit_counter_E_out + 1;
end if;
if grant_E = '1' then
credit_counter_E_in <= credit_counter_E_out - 1;
end if;
if credit_in_W = '1' and credit_counter_W_out < 1 then
credit_counter_W_in <= credit_counter_W_out + 1;
end if;
if grant_W = '1' then
credit_counter_W_in <= credit_counter_W_out - 1;
end if;
if credit_in_S = '1' and credit_counter_S_out < 1 then
credit_counter_S_in <= credit_counter_S_out + 1;
end if;
if grant_S = '1' then
credit_counter_S_in <= credit_counter_S_out - 1;
end if;
if credit_in_L = '1' and credit_counter_L_out < 1 then
credit_counter_L_in <= credit_counter_L_out + 1;
end if;
if grant_L = '1' then
credit_counter_L_in <= credit_counter_L_out - 1;
end if;
end process;
-- Y is N now
arb_X_N: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => req_N_N, X_E_Y => req_E_N, X_W_Y => req_W_N, X_S_Y => req_S_N, X_L_Y => req_L_N,
credit => credit_counter_N_out,
grant_Y_N => grant_N_N_sig,
grant_Y_E => grant_N_E_sig,
grant_Y_W => grant_N_W_sig,
grant_Y_S => grant_N_S_sig,
grant_Y_L => grant_N_L_sig);
-- Y is E now
arb_X_E: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => req_N_E, X_E_Y => req_E_E, X_W_Y => req_W_E, X_S_Y => req_S_E, X_L_Y => req_L_E,
credit => credit_counter_E_out,
grant_Y_N => grant_E_N_sig,
grant_Y_E => grant_E_E_sig,
grant_Y_W => grant_E_W_sig,
grant_Y_S => grant_E_S_sig,
grant_Y_L => grant_E_L_sig);
-- Y is W now
arb_X_W: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => req_N_W, X_E_Y => req_E_W, X_W_Y => req_W_W, X_S_Y => req_S_W, X_L_Y => req_L_W,
credit => credit_counter_W_out,
grant_Y_N => grant_W_N_sig,
grant_Y_E => grant_W_E_sig,
grant_Y_W => grant_W_W_sig,
grant_Y_S => grant_W_S_sig,
grant_Y_L => grant_W_L_sig);
-- Y is S now
arb_X_S: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => req_N_S, X_E_Y => req_E_S, X_W_Y => req_W_S, X_S_Y => req_S_S, X_L_Y => req_L_S,
credit => credit_counter_S_out,
grant_Y_N => grant_S_N_sig,
grant_Y_E => grant_S_E_sig,
grant_Y_W => grant_S_W_sig,
grant_Y_S => grant_S_S_sig,
grant_Y_L => grant_S_L_sig);
-- Y is L now
arb_X_L: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => req_N_L, X_E_Y => req_E_L, X_W_Y => req_W_L, X_S_Y => req_S_L, X_L_Y => req_L_L,
credit => credit_counter_L_out,
grant_Y_N => grant_L_N_sig,
grant_Y_E => grant_L_E_sig,
grant_Y_W => grant_L_W_sig,
grant_Y_S => grant_L_S_sig,
grant_Y_L => grant_L_L_sig);
valid_N <= grant_N;
valid_E <= grant_E;
valid_W <= grant_W;
valid_S <= grant_S;
valid_L <= grant_L;
END;
| gpl-3.0 | 6f65abcf0becda3c102d8973a90eb9ab | 0.552016 | 2.650508 | false | false | false | false |
JarrettR/FPGA-Cryptoparty | FPGA/hdl/hmac_main.vhd | 1 | 7,424 | --------------------------------------------------------------------------------
-- This is the main HMAC algorithm body
-- Copyright (C) 2016 Jarrett Rainier
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.sha1_pkg.all;
entity hmac_main is
port(
clk_i : in std_ulogic;
rst_i : in std_ulogic;
secret_i : in w_input;
value_i : in w_input;
value_len_i : in std_ulogic_vector(0 to 63);
load_i : in std_ulogic;
dat_o : out w_output;
valid_o : out std_ulogic
);
end hmac_main;
architecture RTL of hmac_main is
component sha1_process_input
port(
clk_i : in std_ulogic;
rst_i : in std_ulogic;
dat_i : in w_input;
load_i : in std_ulogic;
dat_w_o : out w_full;
valid_o : out std_ulogic
);
end component;
component sha1_process_buffer
port(
clk_i : in std_ulogic;
rst_i : in std_ulogic;
dat_i : in w_full;
load_i : in std_ulogic;
new_i : in std_ulogic;
dat_w_i : in w_output;
dat_w_o : out w_output;
valid_o : out std_ulogic
);
end component;
type state_type is (STATE_IDLE,
STATE_BI1_LOAD_ON, STATE_BI1_LOAD_OFF,
STATE_BI1_PROCESS,
STATE_BI2_LOAD_ON, STATE_BI2_LOAD_OFF,
STATE_BI2_PROCESS,
STATE_BO1_LOAD_ON, STATE_BO1_LOAD_OFF,
STATE_BO1_PROCESS,
STATE_BO2_LOAD_ON, STATE_BO2_LOAD_OFF,
STATE_BO2_PROCESS,
STATE_FINISHED);
signal state : state_type := STATE_IDLE;
--signal dat_bi : w_input;
signal bi_buffer_dat : w_output;
signal process_in : w_input;
signal processed_input_load : std_ulogic;
signal processed_input : w_full;
signal processed_valid : std_ulogic;
signal processed_new : std_ulogic;
signal buffer_in : w_output;
signal buffer_dat : w_output;
signal buffer_valid : std_ulogic;
signal i: integer range 0 to 65535;
begin
PINPUT: sha1_process_input port map (clk_i,rst_i,process_in,processed_input_load,processed_input,processed_valid);
PBUFFER: sha1_process_buffer port map (clk_i,rst_i,processed_input,processed_valid,processed_new,buffer_in,buffer_dat,buffer_valid);
process(clk_i)
begin
if (clk_i'event and clk_i = '1') then
if rst_i = '1' then
i <= 0;
state <= STATE_IDLE;
processed_input_load <= '0';
processed_new <= '1';
valid_o <= '0';
elsif load_i = '1' and state = STATE_IDLE then
processed_new <= '1';
for x in 0 to 15 loop
process_in(x) <= X"36363636" xor secret_i(x);
end loop;
state <= STATE_BI1_LOAD_ON;
elsif state = STATE_BI1_LOAD_ON then
processed_input_load <= '1';
state <= STATE_BI1_LOAD_OFF;
elsif state = STATE_BI1_LOAD_OFF then
processed_input_load <= '0';
state <= STATE_BI1_PROCESS;
elsif buffer_valid = '1' and state = STATE_BI1_PROCESS then
processed_new <= '0';
buffer_in <= buffer_dat;
for x in 0 to 13 loop
process_in(x) <= value_i(x);
end loop;
--Todo:
--This is needs the 0x80 frame end flag
process_in(14) <= value_len_i(0 to 31);
process_in(15) <= value_len_i(32 to 63);
state <= STATE_BI2_LOAD_ON;
elsif state = STATE_BI2_LOAD_ON then
processed_input_load <= '1';
state <= STATE_BI2_LOAD_OFF;
elsif state = STATE_BI2_LOAD_OFF then
processed_input_load <= '0';
state <= STATE_BI2_PROCESS;
--Inner done
elsif buffer_valid = '1' and state = STATE_BI2_PROCESS then
processed_input_load <= '0';
processed_new <= '1';
bi_buffer_dat <= buffer_dat;
for x in 0 to 15 loop
process_in(x) <= X"5c5c5c5c" xor secret_i(x);
end loop;
state <= STATE_BO1_LOAD_ON;
elsif state = STATE_BO1_LOAD_ON then
processed_input_load <= '1';
state <= STATE_BO1_LOAD_OFF;
elsif state = STATE_BO1_LOAD_OFF then
processed_input_load <= '0';
state <= STATE_BO1_PROCESS;
elsif buffer_valid = '1' and state = STATE_BO1_PROCESS then
processed_new <= '0';
buffer_in <= buffer_dat;
for x in 0 to 4 loop
process_in(x) <= bi_buffer_dat(x);
end loop;
--0x80 frame end flag is always the same here
process_in(5) <= X"80000000";
for x in 6 to 14 loop
process_in(x) <= X"00000000";
end loop;
process_in(15) <= X"000002A0";
state <= STATE_BO2_LOAD_ON;
elsif state = STATE_BO2_LOAD_ON then
processed_input_load <= '1';
state <= STATE_BO2_LOAD_OFF;
elsif state = STATE_BO2_LOAD_OFF then
processed_input_load <= '0';
state <= STATE_BO2_PROCESS;
elsif buffer_valid = '1' and state = STATE_BO2_PROCESS then
processed_input_load <= '0';
dat_o <= buffer_dat;
valid_o <= '1';
state <= STATE_FINISHED;
elsif state = STATE_FINISHED then
valid_o <= '0';
state <= STATE_IDLE;
--else
-- i <= i + 1;
end if;
i <= i + 1;
end if;
end process;
end RTL; | gpl-3.0 | c5a44826265e6c9231b92d0940a29ae3 | 0.456492 | 4.079121 | false | false | false | false |
SoCdesign/EHA | RTL/Fault_Management/SHMU_prototype/version_2/ParityChecker_packet_detector.vhd | 2 | 2,452 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
entity parity_checker_packet_detector is
generic(DATA_WIDTH : integer := 32);
port(
reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
DRTS: in std_logic;
faulty_packet, healthy_packet: out std_logic
);
end parity_checker_packet_detector;
architecture behavior of parity_checker_packet_detector is
signal xor_all: std_logic;
signal fault_out: std_logic;
alias flit_type : std_logic_vector(2 downto 0) is RX(DATA_WIDTH-1 downto DATA_WIDTH-3);
type state_type IS (Idle, Header_flit, Body_flit, Tail_flit);
SIGNAL state_out, state_in : state_type;
begin
-- sequential process
process(reset, clk)begin
if reset = '0' then
state_out <= Idle;
elsif clk'event and clk = '1' then
state_out <= state_in;
end if;
end process;
--anything bellow this is combinatorial
-- this part is the typical parity
xor_all <= XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
process(DRTS, RX)begin
if DRTS = '1' then
if xor_all = RX(0) then
fault_out <= '0';
else
fault_out <= '1';
end if;
else
fault_out <= '0';
end if;
end process;
-- FSM for packet health detection
process(flit_type, fault_out, state_out, DRTS)
begin
faulty_packet <= '0';
healthy_packet <= '0';
if DRTS = '1' then
case(state_out) is
when Idle =>
if flit_type = "001" then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
when Header_flit =>
if fault_out = '0' then
if flit_type = "010" then
state_in <= Body_flit;
else
state_in <= state_out;
end if;
else
state_in <= Idle;
faulty_packet <= '1';
end if;
when Body_flit =>
if fault_out = '0' then
if flit_type = "100" then
state_in <= Tail_flit;
else
state_in <= state_out;
end if;
else
state_in <= Idle;
faulty_packet <= '1';
end if;
when Tail_flit =>
state_in <= Idle;
if fault_out = '0' then
healthy_packet <= '1';
else
faulty_packet <= '1';
end if;
end case;
else
state_in <= state_out;
end if;
end process;
end;
| gpl-3.0 | b4556083aa0148bd859323a0fe1cdb89 | 0.56199 | 3.172057 | false | false | false | false |
lnls-dig/dsp-cores | hdl/modules/cordic/cordic_core.vhd | 1 | 6,320 | -------------------------------------------------------------------------------
-- Title : Configurable Cordic core
-- Project :
-------------------------------------------------------------------------------
-- File : cordic_core.vhd
-- Author : Aylons <aylons@aylons-yoga2>
-- Company :
-- Created : 2014-05-03
-- Last update: 2015-10-15
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: This CORDIC allow configuration of its number of stages and
-- accepts any bus size for its inputs and ouputs. The calculation to be done
-- is defined by a generic value, and there's no need for external codes due to
-- any parameter change.
-------------------------------------------------------------------------------
-- This file is part of Concordic.
--
-- Concordic is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Concordic is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- Copyright (c) 2014 Aylons Hazzud
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-05-03 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.dsp_cores_pkg.all;
-------------------------------------------------------------------------------
entity cordic_core is
generic (
g_stages : natural := 20;
g_bit_growth : natural := 2;
g_mode : string := "rect_to_polar"
);
-- x represents the x axis in rectangular coordinates or amplitude in polar
-- y represents the y axis in rectangular coordinates
-- z represents phase in polar coordinates
port (
x_i : in signed;
y_i : in signed;
z_i : in signed;
clk_i : in std_logic;
ce_i : in std_logic;
rst_i : in std_logic;
valid_i : in std_logic;
x_o : out signed;
y_o : out signed;
z_o : out signed;
valid_o : out std_logic
);
end entity cordic_core;
-------------------------------------------------------------------------------
architecture str of cordic_core is
constant c_width : natural := x_i'length + g_bit_growth + 2;
type wiring is array (0 to g_stages) of signed(c_width-1 downto 0);
type control_wiring is array (0 to g_stages) of boolean;
type z_wiring is array (0 to g_stages) of signed(x_i'length-1 downto 0);
signal x_inter : wiring := (others => (others => '0'));
signal y_inter : wiring := (others => (others => '0'));
signal z_inter : z_wiring := (others => (others => '0'));
signal x_shifted : wiring := (others => (others => '0'));
signal y_shifted : wiring := (others => (others => '0'));
signal control_x : control_wiring := (others => false);
signal control_y : control_wiring := (others => false);
function stage_constant(mode, stage, width : natural) return signed is
variable const_vector : signed(width-1 downto 0) := (others => '0');
begin
-- Each iteration must sum or subtract arctg(1/(2^(stage-1)))
-- Only works for cordics up to 32 bits. Wider constants require
-- pre-generated tables, due to limitations in most VHDL tool's
const_vector := to_signed(integer(arctan(2.0**(real(1-stage)))/(MATH_2_PI)*(2.0**real(width))), width);
return const_vector;
end function;
begin -- architecture str
--TODO: for now, it only generates a rect_to_polar CORDIC. Adapt so we can
--generate other algorithms while reusing as much code as possible, so it
--will be easy to maintain and evolve - hardware is already hard enough.
x_inter(0) <= resize(x_i, x_i'length+2) & (g_bit_growth-1 downto 0 => '0');
y_inter(0) <= resize(y_i, y_i'length+2) & (g_bit_growth-1 downto 0 => '0');
z_inter(0) <= z_i; -- left aligned
control_x(0) <= y_i(y_i'left) = '1';
control_y(0) <= y_i(y_i'left) = '0';
cmp_valid_pipe : pipeline
generic map (
g_width => 1,
g_depth => g_stages)
port map (
data_i(0) => valid_i,
clk_i => clk_i,
ce_i => ce_i,
data_o(0) => valid_o);
CORE_STAGES : for stage in 1 to g_stages generate
--control_x(stage) <= y_inter(stage-1) < 0;
--control_y(stage) <= y_inter(stage-1) > 0;
x_shifted(stage) <= shift_right(x_inter(stage-1), stage-1);
y_shifted(stage) <= shift_right(y_inter(stage-1), stage-1);
cmp_x_stage : addsub
port map(
a_i => x_inter(stage-1),
b_i => y_shifted(stage),
sub_i => control_x(stage-1),
clk_i => clk_i,
ce_i => ce_i,
rst_i => rst_i,
result_o => x_inter(stage),
positive_o => open,
negative_o => open);
cmp_y_stage : addsub
port map(
a_i => y_inter(stage-1),
b_i => x_shifted(stage),
sub_i => control_y(stage-1),
clk_i => clk_i,
ce_i => ce_i,
rst_i => rst_i,
result_o => y_inter(stage),
positive_o => control_y(stage),
negative_o => control_x(stage));
cmp_z_stage : addsub
port map (
a_i => z_inter(stage-1),
b_i => stage_constant(1, stage, x_i'length),
sub_i => control_x(stage-1),
clk_i => clk_i,
ce_i => ce_i,
rst_i => rst_i,
result_o => z_inter(stage),
positive_o => open,
negative_o => open);
end generate;
--TODO: Round the output
x_o <= x_inter(g_stages)(c_width-1 downto g_bit_growth+2);
y_o <= y_inter(g_stages)(c_width-1 downto g_bit_growth+2);
z_o <= z_inter(g_stages);
end architecture str;
| lgpl-3.0 | b4fcb828bace05285edb6ecd04093485 | 0.534968 | 3.590909 | false | false | false | false |
mgiacomini/mips-pipeline | MAIN_CTTRL.vhd | 1 | 17,843 | -- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- Engineer: Darci Luiz Tomasi Junior
-- E-mail: [email protected]
-- Date : 01/07/2015 - 22:08
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY MAIN_PROCESSOR IS
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC
);
END MAIN_PROCESSOR;
ARCHITECTURE ARC_MAIN_PROCESSOR OF MAIN_PROCESSOR IS
COMPONENT ADD_PC IS
PORT(
IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT ADD IS
PORT(
IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
IN_B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT AND_1 IS
PORT(
Branch : IN STD_LOGIC;
IN_A : IN STD_LOGIC;
OUT_A : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT CONCAT IS
PORT(
IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
IN_B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT CTRL IS
PORT(
OPCode : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
RegDst : OUT STD_LOGIC;
Jump : OUT STD_LOGIC;
Branch : OUT STD_LOGIC;
MemRead : OUT STD_LOGIC;
MemtoReg : OUT STD_LOGIC;
ALUOp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
MemWrite : OUT STD_LOGIC;
ALUSrc : OUT STD_LOGIC;
RegWrite : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT EXTEND_SIGNAL IS
PORT(
IN_A : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT INST IS
PORT(
IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT MEM IS
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
MemWrite : IN STD_LOGIC;
MemRead : IN STD_LOGIC;
IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
IN_B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT MX_1 IS
PORT(
RegDst : IN STD_LOGIC;
IN_A : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
IN_B : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT MX_2 IS
PORT(
AluSrc : IN STD_LOGIC;
IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
IN_B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT MX_3 IS
PORT(
IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
IN_B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
IN_C : IN STD_LOGIC;
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT MX_4 IS
PORT(
Jump : IN STD_LOGIC;
IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
IN_B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT MX_5 IS
PORT(
MemtoReg : IN STD_LOGIC;
IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
IN_B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT PC IS
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT REG IS
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
RegWrite : IN STD_LOGIC;
IN_A : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
IN_B : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
IN_C : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
IN_D : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_B : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT SL_1 IS
PORT(
IN_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT SL_2 IS
PORT(
IN_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT ULA_CTRL IS
PORT (
ALUOp : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
IN_A : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END COMPONENT;
COMPONENT ULA IS
PORT(
IN_A : IN STD_LOGIC_VECTOR (31 downto 0); --RS
IN_B : IN STD_LOGIC_VECTOR (31 downto 0); --RT
IN_C : IN STD_LOGIC_VECTOR (2 downto 0);
OUT_A : OUT STD_LOGIC_VECTOR (31 downto 0);
ZERO : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT IF_ID IS
PORT (
clk : in std_logic;
pcplus4 : in std_logic_vector(31 downto 0);
instruction : in std_logic_vector(31 downto 0);
pc_out : out std_logic_vector(31 downto 0);
instr_out : out std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT ID_EX IS
PORT (
clk : IN STD_LOGIC;
RegDst : IN STD_LOGIC;
Jump : IN STD_LOGIC;
Branch : IN STD_LOGIC;
MemRead : IN STD_LOGIC;
MemtoReg : IN STD_LOGIC;
ALUOp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
MemWrite : IN STD_LOGIC;
ALUSrc : IN STD_LOGIC;
RegWrite : IN STD_LOGIC;
JumpAddr : in std_logic_vector(31 downto 0);
RD1 : in std_logic_vector(31 downto 0);
RD2 : in std_logic_vector(31 downto 0);
RtE : in std_logic_vector(4 downto 0);
RdE : in std_logic_vector(4 downto 0);
SignExt : in std_logic_vector(31 downto 0);
PCPlus4 : in std_logic_vector(31 downto 0);
outRegDst : out std_logic;
outJump : out std_logic;
outBranch : out std_logic;
outMemRead : out std_logic;
outMemtoReg : out std_logic;
outALUOp : out STD_LOGIC_VECTOR(1 DOWNTO 0);
outMemWrite : out std_logic;
outALUSrc : out std_logic;
outRegWrite : out std_logic;
outRD1 : out std_logic_vector(31 downto 0);
outRD2 : out std_logic_vector(31 downto 0);
outRtE : out std_logic_vector(4 downto 0);
outRdE : out std_logic_vector(4 downto 0);
outSignExt : out std_logic_vector(31 downto 0);
outPCPlus4 : out std_logic_vector(31 downto 0);
JumpAddrOut : out std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT EX_MEM IS
PORT (clk : in std_logic;
RegWrite : in std_logic;
MemtoReg : in std_logic;
MemWrite : in std_logic;
MemRead : in std_logic;
Branch : in std_logic;
Jump : IN STD_LOGIC;
ZeroM : in std_logic;
AluOutM : in std_logic_vector(31 downto 0); --SAIDA DA ULA
WriteDataM : in std_logic_vector(31 downto 0); -- VEM DA SAIDA 2 DE REG
WriteRegM : in std_logic_vector(4 downto 0); -- REG DESTINO VEM DO MX_1
PcBranchM : in std_logic_vector(31 downto 0); --ENDERECO DE DESVIO CONDICIONAL
outRegWrite : out std_logic;
outMemtoReg : out std_logic;
outMemWrite : out std_logic;
outMemRead : out std_logic;
outBranch : out std_logic;
outZeroM : out std_logic;
outAluOutM : out std_logic_vector(31 downto 0);
outWriteDataM : out std_logic_vector(31 downto 0);
outWriteRegM : out std_logic_vector(4 downto 0);
outPcBranchM : out std_logic_vector(31 downto 0));
END COMPONENT;
COMPONENT MEM_WB IS
PORT (clk : in std_logic;
RegWrite : in std_logic;
MemtoReg : in std_logic;
ReadDataW : in std_logic_vector(31 downto 0);
AluOutW : in std_logic_vector(31 downto 0);
WriteRegW : in std_logic_vector(4 downto 0);
outRegWrite : out std_logic;
outMemtoReg : out std_logic;
outReadDataW : out std_logic_vector(31 downto 0);
outAluOutW : out std_logic_vector(31 downto 0);
outWriteRegW : out std_logic_vector(4 downto 0)
);
END COMPONENT;
--ADD_PC
SIGNAL S_ADD_PC_OUT_A : STD_LOGIC_VECTOR(31 DOWNTO 0);
--ADD
SIGNAL S_ADD_OUT_A : STD_LOGIC_VECTOR(31 DOWNTO 0);
--AND_1
SIGNAL S_AND_1_OUT_A : STD_LOGIC;
--CONCAT
SIGNAL S_CONCAT_OUT_A : STD_LOGIC_VECTOR(31 DOWNTO 0);
--CTRL
SIGNAL S_CTRL_RegDst : STD_LOGIC;
SIGNAL S_CTRL_Jump : STD_LOGIC;
SIGNAL S_CTRL_Branch : STD_LOGIC;
SIGNAL S_CTRL_MemRead : STD_LOGIC;
SIGNAL S_CTRL_MemtoReg : STD_LOGIC;
SIGNAL S_CTRL_ALUOp : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL S_CTRL_MemWrite : STD_LOGIC;
SIGNAL S_CTRL_ALUSrc : STD_LOGIC;
SIGNAL S_CTRL_RegWrite : STD_LOGIC;
--INST
SIGNAL S_INST_OUT_A : STD_LOGIC_VECTOR(31 DOWNTO 0);
--EXTEND_SIGNAL
SIGNAL S_EXTEND_SIGNAL_OUT_A :STD_LOGIC_VECTOR (31 DOWNTO 0);
--MEM
SIGNAL S_MEM_OUT_A : STD_LOGIC_VECTOR(31 DOWNTO 0);
--MX_1
SIGNAL S_MX_1_OUT_A : STD_LOGIC_VECTOR(4 DOWNTO 0);
--MX_2
SIGNAL S_MX_2_OUT_A : STD_LOGIC_VECTOR(31 DOWNTO 0);
--MX_3
SIGNAL S_MX_3_OUT_A : STD_LOGIC_VECTOR(31 DOWNTO 0);
--MX_4
SIGNAL S_MX_4_OUT_A : STD_LOGIC_VECTOR(31 DOWNTO 0);
--MX_5
SIGNAL S_MX_5_OUT_A : STD_LOGIC_VECTOR(31 DOWNTO 0);
--PC
SIGNAL S_PC_OUT_A : STD_LOGIC_VECTOR(31 DOWNTO 0);
--REG
SIGNAL S_REG_OUT_A : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL S_REG_OUT_B : STD_LOGIC_VECTOR(31 DOWNTO 0);
--SL_1
SIGNAL S_SL_1_OUT_A : STD_LOGIC_VECTOR (31 DOWNTO 0);
--SL_2
SIGNAL S_SL_2_OUT_A : STD_LOGIC_VECTOR (31 DOWNTO 0);
--ULA_CTRL
SIGNAL S_ULA_CTRL_OUT_A : STD_LOGIC_VECTOR (2 DOWNTO 0);
--ULA
SIGNAL S_ULA_OUT_A : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL S_ULA_ZERO : STD_LOGIC;
------------------------ PIPE ----------------------------
--IF_ID
SIGNAL S_PCPlus4_IFID_OUT : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL S_INSTRUCTION_OUT : STD_LOGIC_VECTOR (31 DOWNTO 0);
--ID_EX
SIGNAL S_RegDst_IDEX_OUT : STD_LOGIC;
SIGNAL S_Jump_IDEX_OUT : STD_LOGIC;
SIGNAL S_Branch_IDEX_OUT : STD_LOGIC;
SIGNAL S_MemRead_IDEX_OUT : STD_LOGIC;
SIGNAL S_MemtoReg_IDEX_OUT : STD_LOGIC;
SIGNAL S_ALUOp_IDEX_OUT : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL S_MemWrite_IDEX_OUT : STD_LOGIC;
SIGNAL S_ALUSrc_IDEX_OUT : STD_LOGIC;
SIGNAL S_RegWrite_IDEX_OUT : STD_LOGIC;
SIGNAL S_CONCAT_IDEX_OUT: STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL S_RD1_OUT : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL S_RD2_OUT : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL S_RtE_OUT : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL S_RdE_OUT : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL S_SignExt_OUT : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL S_PCPlus4_IDEX_OUT : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL S_JUMP_ADDR_IDEX_OUT : STD_LOGIC_VECTOR (31 DOWNTO 0);
--EX_MEM
SIGNAL S_RegWrite_EXMEM_OUT : STD_LOGIC;
SIGNAL S_MemtoReg_EXMEM_OUT : STD_LOGIC;
SIGNAL S_MemWrite_EXMEM_OUT : STD_LOGIC;
SIGNAL S_MemRead_EXMEM_OUT : STD_LOGIC;
SIGNAL S_Branch_EXMEM_OUT : STD_LOGIC;
SIGNAL S_ULA_EXMEM_ZERO : STD_LOGIC;
SIGNAL S_ULA_EXMEM_OUT : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL S_REG_EXMEM_OUT : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL S_DSTREG_OUT : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL S_BRANCH_ADDRESS_OUT : STD_LOGIC_VECTOR (31 DOWNTO 0);
--MEM_WB
SIGNAL S_RegWrite_MEMWB_OUT : STD_LOGIC;
SIGNAL S_MemtoReg_MEMWB_OUT : STD_LOGIC;
SIGNAL S_ReadDataW_OUT : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL S_AluOutW_OUT : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL S_WriteRegW_OUT : STD_LOGIC_VECTOR (4 DOWNTO 0);
--DEMAIS SINAIS
SIGNAL S_GERAL_OPCode : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL S_GERAL_RS : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL S_GERAL_RT : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL S_GERAL_RD : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL S_GERAL_I_TYPE : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL S_GERAL_FUNCT : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL S_GERAL_JUMP : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL S_GERAL_PC_4 : STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN
S_GERAL_OPCode <= S_INST_OUT_A(31 DOWNTO 26);
S_GERAL_RS <= S_INST_OUT_A(25 DOWNTO 21);
S_GERAL_RT <= S_INST_OUT_A(20 DOWNTO 16);
S_GERAL_RD <= S_INST_OUT_A(15 DOWNTO 11);
S_GERAL_I_TYPE <= S_INST_OUT_A(15 DOWNTO 0);
S_GERAL_FUNCT <= S_INST_OUT_A(5 DOWNTO 0);
S_GERAL_JUMP <= S_INST_OUT_A(31 DOWNTO 0);
S_GERAL_PC_4 <= S_ADD_PC_OUT_A(31 DOWNTO 0);
C_PC : PC PORT MAP(CLK, RESET, S_MX_4_OUT_A, S_PC_OUT_A);
C_ADD_PC : ADD_PC PORT MAP(S_PC_OUT_A, S_ADD_PC_OUT_A);
C_INST : INST PORT MAP(S_PC_OUT_A, S_INST_OUT_A);
C_SL_1 : SL_1 PORT MAP(S_INSTRUCTION_OUT(31 DOWNTO 0), S_SL_1_OUT_A);
C_CTRL : CTRL PORT MAP(S_INSTRUCTION_OUT(31 DOWNTO 26), S_CTRL_RegDst, S_CTRL_Jump, S_CTRL_Branch, S_CTRL_MemRead, S_CTRL_MemtoReg, S_CTRL_ALUOp, S_CTRL_MemWrite, S_CTRL_ALUSrc, S_CTRL_RegWrite);
C_CONCAT : CONCAT PORT MAP(S_SL_1_OUT_A, S_PCPlus4_IFID_OUT, S_CONCAT_OUT_A);
C_MX_1 : MX_1 PORT MAP(S_CTRL_RegDst, S_RtE_OUT, S_RdE_OUT, S_MX_1_OUT_A);
C_SL_2 : SL_2 PORT MAP(S_SignExt_OUT, S_SL_2_OUT_A);
C_REG : REG PORT MAP(CLK, RESET, S_RegWrite_MEMWB_OUT, S_INSTRUCTION_OUT(25 DOWNTO 21), S_INSTRUCTION_OUT(20 DOWNTO 16), S_WriteRegW_OUT, S_MX_5_OUT_A, S_REG_OUT_A, S_REG_OUT_B);
C_EXTEND_SIGNAL : EXTEND_SIGNAL PORT MAP(S_INSTRUCTION_OUT(15 DOWNTO 0), S_EXTEND_SIGNAL_OUT_A);
C_ADD : ADD PORT MAP(S_PCPlus4_IDEX_OUT, S_SL_2_OUT_A, S_ADD_OUT_A);
C_ULA : ULA PORT MAP(S_RD1_OUT, S_MX_2_OUT_A, S_ULA_CTRL_OUT_A, S_ULA_OUT_A, S_ULA_ZERO);
C_MX_2 : MX_2 PORT MAP(S_ALUSrc_IDEX_OUT, S_RD2_OUT, S_SignExt_OUT, S_MX_2_OUT_A);
C_ULA_CTRL : ULA_CTRL PORT MAP(S_ALUOp_IDEX_OUT, S_SignExt_OUT(5 DOWNTO 0), S_ULA_CTRL_OUT_A);
C_MX_3 : MX_3 PORT MAP(S_ADD_PC_OUT_A, S_ADD_OUT_A, S_AND_1_OUT_A, S_MX_3_OUT_A);
C_AND_1 : AND_1 PORT MAP(S_Branch_EXMEM_OUT, S_ULA_EXMEM_ZERO, S_AND_1_OUT_A);
C_MEM : MEM PORT MAP(CLK, RESET, S_MemWrite_EXMEM_OUT, S_MemRead_EXMEM_OUT, S_ULA_EXMEM_OUT, S_REG_EXMEM_OUT, S_MEM_OUT_A);
C_MX_4 : MX_4 PORT MAP(S_CTRL_Jump, S_CONCAT_OUT_A, S_MX_3_OUT_A, S_MX_4_OUT_A);
C_MX_5 : MX_5 PORT MAP(S_MemtoReg_MEMWB_OUT, S_ReadDataW_OUT, S_AluOutW_OUT, S_MX_5_OUT_A);
--PIPE
C_IF_ID : IF_ID PORT MAP(CLK, S_ADD_PC_OUT_A, S_INST_OUT_A, S_PCPlus4_IFID_OUT, S_INSTRUCTION_OUT);
C_ID_EX : ID_EX PORT MAP(CLK,
S_CTRL_RegDst,
S_CTRL_Jump,
S_CTRL_Branch,
S_CTRL_MemRead,
S_CTRL_MemtoReg,
S_CTRL_ALUOp,
S_CTRL_MemWrite,
S_CTRL_ALUSrc,
S_CTRL_RegWrite,
S_CONCAT_OUT_A,
S_REG_OUT_A,
S_REG_OUT_B,
S_GERAL_RS,
S_GERAL_RT,
S_EXTEND_SIGNAL_OUT_A,
S_PCPlus4_IFID_OUT,
S_RegDst_IDEX_OUT,
S_Jump_IDEX_OUT,
S_Branch_IDEX_OUT,
S_MemRead_IDEX_OUT,
S_MemtoReg_IDEX_OUT,
S_ALUOp_IDEX_OUT,
S_MemWrite_IDEX_OUT,
S_ALUSrc_IDEX_OUT,
S_RegWrite_IDEX_OUT,
S_RD1_OUT,
S_RD2_OUT,
S_RtE_OUT,
S_RdE_OUT,
S_SignExt_OUT,
S_PCPlus4_IDEX_OUT,
S_JUMP_ADDR_IDEX_OUT);
C_EX_MEM : EX_MEM PORT MAP(CLK,
S_RegWrite_IDEX_OUT,
S_MemtoReg_IDEX_OUT,
S_MemWrite_IDEX_OUT,
S_MemRead_IDEX_OUT,
S_Branch_IDEX_OUT,
S_Jump_IDEX_OUT,
S_ULA_ZERO,
S_ULA_OUT_A,
S_REG_OUT_B,
S_MX_1_OUT_A,
S_ADD_OUT_A,
S_RegWrite_EXMEM_OUT,
S_MemtoReg_EXMEM_OUT,
S_MemWrite_EXMEM_OUT,
S_MemRead_EXMEM_OUT,
S_Branch_EXMEM_OUT,
S_ULA_EXMEM_ZERO,
S_ULA_EXMEM_OUT,
S_REG_EXMEM_OUT,
S_DSTREG_OUT,
S_BRANCH_ADDRESS_OUT);
C_MEM_WB : MEM_WB PORT MAP(CLK,
S_RegWrite_EXMEM_OUT,
S_MemtoReg_EXMEM_OUT,
S_MEM_OUT_A,
S_ULA_EXMEM_OUT,
S_DSTREG_OUT,
S_RegWrite_MEMWB_OUT,
S_MemtoReg_MEMWB_OUT,
S_ReadDataW_OUT,
S_AluOutW_OUT,
S_WriteRegW_OUT);
END ARC_MAIN_PROCESSOR;
| gpl-3.0 | e258943821612d024aaabe18bd1339d6 | 0.568738 | 2.756101 | false | false | false | false |
carlosrd/DAS | P5/piano.vhd | 1 | 7,955 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
entity casioTone is
port (
-- Entradas
ps2Clk: in std_logic;
ps2Data: in std_logic;
clk: in std_logic;
rst: in std_logic;
-- Salidas
altavoz: out std_logic
);
end casioTone;
architecture Behavioral of casioTone is
signal musica: std_logic;
-- MEMORIA ROM
signal nota : std_logic_vector(16 downto 0);
signal scanCode : std_logic_vector (7 downto 0);
-- OSCILADOR
signal salidaContOscilador,cs : std_logic_vector(16 downto 0);
-- INTERFAZ TECLADO PS/2
signal data : std_logic_vector (7 DOWNTO 0); -- Salida de datos paralela
signal newData : std_logic; -- Indica la recepción de un nuevo dato por la línea PS2
signal newDataAck : std_logic; -- Reconoce la recepción del nuevo dato
signal ldData, validData, lastBitRcv, ps2ClkSync, ps2ClkFallingEdge: std_logic;
signal ps2DataRegOut: std_logic_vector(10 downto 0);
signal goodParity: std_logic;
-- MAQUINA DE ESTADOS
type ESTADOS is (WAITING_PRESS, WAITING_F0, WAITING_RELEASE, IGNORE_RELEASE);
signal ESTADO, SIG_ESTADO: ESTADOS;
-- REGISTRO SCANCODE
signal loadScanCode, clearScanCode : std_logic;
signal regOut : std_logic_vector (7 downto 0);
begin
-- SALIDA DE AUDIO
-- *******************************************************************************************
altavoz <= musica;
-- TABLA DE NOTAS (ESCALA LA = 440Hz)
-- *******************************************************************************************
-- Calculo del semiperiodo de oscilacion:
-- ( 1 / Frec Nota (Hz) ) / ( 1 / Frec CLK (Hz) )
-- Ej DO: (1 / 261.6 Hz ) / ( 1 / 50 Mhz) = 191131,498 ~ 191132 Ciclos/Perido => Semiperiodo: (Ciclos/Periodo) / 2 = 95566
tablaNotas:
with scanCode select
nota <= "10111010101001110" when "00011100", -- A => DO / 95566 ciclos semiperiodo when A = 1C
"10110000001001100" when "00011101", -- W => DO# / 90188 semiperiodo when W = 1D
"10100110010000001" when "00011011", -- S => RE / 85121 semiperiodo when S = 1B
"10011100111101000" when "00100100", -- E => RE# / 80360 semiperiodo when E = 24
"10010100001001010" when "00100011", -- D => MI / 75850 semiperiodo when D = 23
"10001011110101000" when "00101011", -- F => FA / 71592 semiperiodo when F = 2B
"10000011111110000" when "00101100", -- T => FA# / 67568 semiperiodo when T = 2C
"01111100100100000" when "00110100", -- G => SOL / 63776 semiperiodo when G = 34
"01110101100100101" when "00110101", -- Y => SOL# / 60197 semiperiodo when Y = 35
"01101110111110010" when "00110011", -- H => LA / 56818 semiperiodo when H = 33
"01101000101111001" when "00111100", -- U => LA# / 53625 semiperiodo when U = 3C
"01100010110111010" when "00111011", -- J => SI / 50618 semiperiodo when J = 3B
"01011101010011110" when "01000010", -- K => DO / 47774 semiperiodo when K = 42
"00000000000000000" when others;
-- OSCILADOR
-- *******************************************************************************************
oscilador:
process( clk, rst )
begin
salidaContOscilador <= cs;
if rst = '0' then
cs <= conv_std_logic_vector( 0 , 17 );
musica <= '0';
elsif clk'event and clk = '1' then
if salidaContOscilador = nota then
cs <= conv_std_logic_vector( 0 , 17 );
musica <= not (musica);
elsif cs = conv_std_logic_vector( 131071 , 17 ) then
cs <= conv_std_logic_vector( 0 , 17 );
else
cs <= cs + 1;
end if;
end if;
end process;
-- INTERFAZ TECLADO PS/2
-- *******************************************************************************************
synchronizer:
PROCESS (rst, clk)
VARIABLE aux1: std_logic;
BEGIN
IF (rst='0') THEN
aux1 := '1';
ps2ClkSync <= '1';
ELSIF (clk'EVENT AND clk='1') THEN
ps2ClkSync <= aux1;
aux1 := ps2Clk;
END IF;
END PROCESS synchronizer;
edgeDetector:
PROCESS (rst, clk)
VARIABLE aux1, aux2: std_logic;
BEGIN
ps2ClkFallingEdge <= (NOT aux1) AND aux2;
IF (rst='0') THEN
aux1 := '1';
aux2 := '1';
ELSIF (clk'EVENT AND clk='1') THEN
aux2 := aux1;
aux1 := ps2ClkSync;
END IF;
END PROCESS edgeDetector;
ps2DataReg:
PROCESS (rst, clk)
BEGIN
IF (rst='0') THEN
ps2DataRegOut <= (OTHERS =>'1');
ELSIF (clk'EVENT AND clk='1') THEN
IF (lastBitRcv='1') THEN
ps2DataRegOut <= (OTHERS=>'1');
ELSIF (ps2ClkFallingEdge='1') THEN
ps2DataRegOut <= ps2Data & ps2DataRegOut(10 downto 1);
END IF;
END IF;
END PROCESS ps2DataReg;
oddParityCheker:
goodParity <=
((ps2DataRegOut(9) XOR ps2DataRegOut(8)) XOR (ps2DataRegOut(7) XOR ps2DataRegOut(6)))
XOR ((ps2DataRegOut(5) XOR ps2DataRegOut(4)) XOR (ps2DataRegOut(3) XOR ps2DataRegOut(2)))
XOR ps2DataRegOut(1);
lastBitRcv <= NOT ps2DataRegOut(0);
validData <= lastBitRcv AND goodParity;
dataReg:
PROCESS (rst, clk)
BEGIN
IF (rst='0') THEN
data <= (OTHERS=>'0');
ELSIF (clk'EVENT AND clk='1') THEN
IF (ldData='1') THEN
data <= ps2DataRegOut(8 downto 1);
END IF;
END IF;
END PROCESS dataReg;
controller:
PROCESS (validData, rst, clk)
TYPE states IS (waitingData, waitingNewDataAck);
VARIABLE state: states;
BEGIN
ldData <= '0';
newData <= '0';
CASE state IS
WHEN waitingData =>
IF (validData='1') THEN
ldData <= '1';
END IF;
WHEN waitingNewDataAck =>
newData <= '1';
WHEN OTHERS => NULL;
END CASE;
IF (rst='0') THEN
state := waitingData;
ELSIF (clk'EVENT AND clk='1') THEN
CASE state IS
WHEN waitingData =>
IF (validData='1') THEN
state := waitingNewDataAck;
END IF;
WHEN waitingNewDataAck =>
IF (newDataAck='1') THEN
state := waitingData;
END IF;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS controller;
-- MAQUINA DE ESTADOS PARA DETECCION DE TECLAS (TECLADO PS/2)
-- *******************************************************************************************
-- MAQUINA ESTADOS: SINCRONO
maqEstadosSyn:
process(clk,rst)
begin
if rst ='0' then
ESTADO <= WAITING_PRESS;
elsif clk'event and clk='1' then
ESTADO <= SIG_ESTADO;
end if;
end process;
-- MAQUINA ESTADOS: COMBINACIONAL
maqEstadosComb:
process(ESTADO,rst,newData,data,scanCode)
begin
SIG_ESTADO <= ESTADO;
loadScanCode <= '0';
clearScanCode <= '0';
case ESTADO is
when WAITING_PRESS =>
newDataAck <= '1';
if newData = '1' then
if data /= "11110000" then
loadScanCode <= '1';
SIG_ESTADO <= WAITING_F0;
else
SIG_ESTADO <= IGNORE_RELEASE;
end if;
end if;
when WAITING_F0 =>
newDataAck <= '1';
if newData = '1' then
if data = "11110000" then
SIG_ESTADO <= WAITING_RELEASE;
end if;
end if;
when WAITING_RELEASE =>
newDataAck <= '1';
if newData = '1' then
if scanCode = data then
clearScanCode <= '1';
SIG_ESTADO <= WAITING_PRESS;
else
SIG_ESTADO <= WAITING_F0;
end if;
end if;
when IGNORE_RELEASE =>
newDataAck <= '1';
if newData = '1' then
SIG_ESTADO <= WAITING_PRESS;
end if;
end case;
end process;
-- REGISTRO SCANCODE
-- *******************************************************************************************
registroScanCode:
process( clk, rst , loadScanCode, clearScanCode)
begin
scanCode <= regOut;
if rst = '0' then
regOut <= (others=>'0');
elsif clk'event and clk = '1' then
if loadScanCode = '1' then
regOut <= data;
elsif clearScanCode = '1' then
regOut <= (others=>'0');
end if;
end if;
end process;
end Behavioral;
| mit | 50b2d085964c60cf182d4e117f4b27af | 0.56983 | 3.431838 | false | false | false | false |
bruskajp/EE-316 | Project4/Vivado_NexysBoard/craddockEE316/craddockEE316.srcs/sources_1/imports/testFolder/math_real.vhd | 1 | 51,266 | ------------------------------------------------------------------------
--
-- This source file may be used and distributed without restriction.
-- No declarations or definitions shall be added to this package.
-- This package cannot be sold or distributed for profit.
--
-- ****************************************************************
-- * *
-- * W A R N I N G *
-- * *
-- * This DRAFT version IS NOT endorsed or approved by IEEE *
-- * *
-- ****************************************************************
--
-- Title: PACKAGE MATH_REAL
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Purpose: VHDL declarations for mathematical package MATH_REAL
-- which contains common real constants, common real
-- functions, and real trascendental functions.
--
-- Author: IEEE VHDL Math Package Study Group
--
-- Notes:
-- The package body shall be considered the formal definition of
-- the semantics of this package. Tool developers may choose to implement
-- the package body in the most efficient manner available to them.
--
-- History:
-- Version 0.1 (Strawman) Jose A. Torres 6/22/92
-- Version 0.2 Jose A. Torres 1/15/93
-- Version 0.3 Jose A. Torres 4/13/93
-- Version 0.4 Jose A. Torres 4/19/93
-- Version 0.5 Jose A. Torres 4/20/93 Added RANDOM()
-- Version 0.6 Jose A. Torres 4/23/93 Renamed RANDOM as
-- UNIFORM. Modified
-- rights banner.
-- Version 0.7 Jose A. Torres 5/28/93 Rev up for compatibility
-- with package body.
-------------------------------------------------------------
Library IEEE;
Package MATH_REAL is
--
-- commonly used constants
--
constant MATH_E : real := 2.71828_18284_59045_23536;
-- value of e
constant MATH_1_E: real := 0.36787_94411_71442_32160;
-- value of 1/e
constant MATH_PI : real := 3.14159_26535_89793_23846;
-- value of pi
constant MATH_1_PI : real := 0.31830_98861_83790_67154;
-- value of 1/pi
constant MATH_LOG_OF_2: real := 0.69314_71805_59945_30942;
-- natural log of 2
constant MATH_LOG_OF_10: real := 2.30258_50929_94045_68402;
-- natural log of10
constant MATH_LOG2_OF_E: real := 1.44269_50408_88963_4074;
-- log base 2 of e
constant MATH_LOG10_OF_E: real := 0.43429_44819_03251_82765;
-- log base 10 of e
constant MATH_SQRT2: real := 1.41421_35623_73095_04880;
-- sqrt of 2
constant MATH_SQRT1_2: real := 0.70710_67811_86547_52440;
-- sqrt of 1/2
constant MATH_SQRT_PI: real := 1.77245_38509_05516_02730;
-- sqrt of pi
constant MATH_DEG_TO_RAD: real := 0.01745_32925_19943_29577;
-- conversion factor from degree to radian
constant MATH_RAD_TO_DEG: real := 57.29577_95130_82320_87685;
-- conversion factor from radian to degree
--
-- attribute for functions whose implementation is foreign (C native)
--
attribute FOREIGN : string; -- predefined attribute in VHDL-1992
--
-- function declarations
--
function SIGN (X: real ) return real;
-- returns 1.0 if X > 0.0; 0.0 if X == 0.0; -1.0 if X < 0.0
function CEIL (X : real ) return real;
-- returns smallest integer value (as real) not less than X
function FLOOR (X : real ) return real;
-- returns largest integer value (as real) not greater than X
function ROUND (X : real ) return real;
-- returns integer FLOOR(X + 0.5) if X > 0;
-- return integer CEIL(X - 0.5) if X < 0
function FMAX (X, Y : real ) return real;
-- returns the algebraically larger of X and Y
function FMIN (X, Y : real ) return real;
-- returns the algebraically smaller of X and Y
procedure UNIFORM (variable Seed1,Seed2:inout integer; variable X:out real);
-- returns a pseudo-random number with uniform distribution in the
-- interval (0.0, 1.0).
-- Before the first call to UNIFORM, the seed values (Seed1, Seed2) must
-- be initialized to values in the range [1, 2147483562] and
-- [1, 2147483398] respectively. The seed values are modified after
-- each call to UNIFORM.
-- This random number generator is portable for 32-bit computers, and
-- it has period ~2.30584*(10**18) for each set of seed values.
--
-- For VHDL-1992, the seeds will be global variables, functions to
-- initialize their values (INIT_SEED) will be provided, and the UNIFORM
-- procedure call will be modified accordingly.
function SRAND (seed: in integer ) return integer;
--
-- sets value of seed for sequence of
-- pseudo-random numbers.
-- It uses the foreign native C function srand().
attribute FOREIGN of SRAND : function is "C_NATIVE";
function RAND return integer;
--
-- returns an integer pseudo-random number with uniform distribution.
-- It uses the foreign native C function rand().
-- Seed for the sequence is initialized with the
-- SRAND() function and value of the seed is changed every
-- time SRAND() is called, but it is not visible.
-- The range of generated values is platform dependent.
attribute FOREIGN of RAND : function is "C_NATIVE";
function GET_RAND_MAX return integer;
--
-- returns the upper bound of the range of the
-- pseudo-random numbers generated by RAND().
-- The support for this function is platform dependent, and
-- it uses foreign native C functions or constants.
-- It may not be available in some platforms.
-- Note: the value of (RAND() / GET_RAND_MAX()) is a
-- pseudo-random number distributed between 0 & 1.
attribute FOREIGN of GET_RAND_MAX : function is "C_NATIVE";
function SQRT (X : real ) return real;
-- returns square root of X; X >= 0
function CBRT (X : real ) return real;
-- returns cube root of X
function "**" (X : integer; Y : real) return real;
-- returns Y power of X ==> X**Y;
-- error if X = 0 and Y <= 0.0
-- error if X < 0 and Y does not have an integer value
function "**" (X : real; Y : real) return real;
-- returns Y power of X ==> X**Y;
-- error if X = 0.0 and Y <= 0.0
-- error if X < 0.0 and Y does not have an integer value
function EXP (X : real ) return real;
-- returns e**X; where e = MATH_E
function LOG (X : real ) return real;
-- returns natural logarithm of X; X > 0
function LOG (BASE: positive; X : real) return real;
-- returns logarithm base BASE of X; X > 0
function SIN (X : real ) return real;
-- returns sin X; X in radians
function COS ( X : real ) return real;
-- returns cos X; X in radians
function TAN (X : real ) return real;
-- returns tan X; X in radians
-- X /= ((2k+1) * PI/2), where k is an integer
function ASIN (X : real ) return real;
-- returns -PI/2 < asin X < PI/2; | X | <= 1
function ACOS (X : real ) return real;
-- returns 0 < acos X < PI; | X | <= 1
function ATAN (X : real) return real;
-- returns -PI/2 < atan X < PI/2
function ATAN2 (X : real; Y : real) return real;
-- returns atan (X/Y); -PI < atan2(X,Y) < PI; Y /= 0.0
function SINH (X : real) return real;
-- hyperbolic sine; returns (e**X - e**(-X))/2
function COSH (X : real) return real;
-- hyperbolic cosine; returns (e**X + e**(-X))/2
function TANH (X : real) return real;
-- hyperbolic tangent; -- returns (e**X - e**(-X))/(e**X + e**(-X))
function ASINH (X : real) return real;
-- returns ln( X + sqrt( X**2 + 1))
function ACOSH (X : real) return real;
-- returns ln( X + sqrt( X**2 - 1)); X >= 1
function ATANH (X : real) return real;
-- returns (ln( (1 + X)/(1 - X)))/2 ; | X | < 1
end MATH_REAL;
---------------------------------------------------------------
--
-- This source file may be used and distributed without restriction.
-- No declarations or definitions shall be included in this package.
-- This package cannot be sold or distributed for profit.
--
-- ****************************************************************
-- * *
-- * W A R N I N G *
-- * *
-- * This DRAFT version IS NOT endorsed or approved by IEEE *
-- * *
-- ****************************************************************
--
-- Title: PACKAGE MATH_COMPLEX
--
-- Purpose: VHDL declarations for mathematical package MATH_COMPLEX
-- which contains common complex constants and basic complex
-- functions and operations.
--
-- Author: IEEE VHDL Math Package Study Group
--
-- Notes:
-- The package body uses package IEEE.MATH_REAL
--
-- The package body shall be considered the formal definition of
-- the semantics of this package. Tool developers may choose to implement
-- the package body in the most efficient manner available to them.
--
-- History:
-- Version 0.1 (Strawman) Jose A. Torres 6/22/92
-- Version 0.2 Jose A. Torres 1/15/93
-- Version 0.3 Jose A. Torres 4/13/93
-- Version 0.4 Jose A. Torres 4/19/93
-- Version 0.5 Jose A. Torres 4/20/93
-- Version 0.6 Jose A. Torres 4/23/93 Added unary minus
-- and CONJ for polar
-- Version 0.7 Jose A. Torres 5/28/93 Rev up for compatibility
-- with package body.
-------------------------------------------------------------
Library IEEE;
Package MATH_COMPLEX is
type COMPLEX is record RE, IM: real; end record;
type COMPLEX_VECTOR is array (integer range <>) of COMPLEX;
type COMPLEX_POLAR is record MAG: real; ARG: real; end record;
constant CBASE_1: complex := COMPLEX'(1.0, 0.0);
constant CBASE_j: complex := COMPLEX'(0.0, 1.0);
constant CZERO: complex := COMPLEX'(0.0, 0.0);
function CABS(Z: in complex ) return real;
-- returns absolute value (magnitude) of Z
function CARG(Z: in complex ) return real;
-- returns argument (angle) in radians of a complex number
function CMPLX(X: in real; Y: in real:= 0.0 ) return complex;
-- returns complex number X + iY
function "-" (Z: in complex ) return complex;
-- unary minus
function "-" (Z: in complex_polar ) return complex_polar;
-- unary minus
function CONJ (Z: in complex) return complex;
-- returns complex conjugate
function CONJ (Z: in complex_polar) return complex_polar;
-- returns complex conjugate
function CSQRT(Z: in complex ) return complex_vector;
-- returns square root of Z; 2 values
function CEXP(Z: in complex ) return complex;
-- returns e**Z
function COMPLEX_TO_POLAR(Z: in complex ) return complex_polar;
-- converts complex to complex_polar
function POLAR_TO_COMPLEX(Z: in complex_polar ) return complex;
-- converts complex_polar to complex
-- arithmetic operators
function "+" ( L: in complex; R: in complex ) return complex;
function "+" ( L: in complex_polar; R: in complex_polar) return complex;
function "+" ( L: in complex_polar; R: in complex ) return complex;
function "+" ( L: in complex; R: in complex_polar) return complex;
function "+" ( L: in real; R: in complex ) return complex;
function "+" ( L: in complex; R: in real ) return complex;
function "+" ( L: in real; R: in complex_polar) return complex;
function "+" ( L: in complex_polar; R: in real) return complex;
function "-" ( L: in complex; R: in complex ) return complex;
function "-" ( L: in complex_polar; R: in complex_polar) return complex;
function "-" ( L: in complex_polar; R: in complex ) return complex;
function "-" ( L: in complex; R: in complex_polar) return complex;
function "-" ( L: in real; R: in complex ) return complex;
function "-" ( L: in complex; R: in real ) return complex;
function "-" ( L: in real; R: in complex_polar) return complex;
function "-" ( L: in complex_polar; R: in real) return complex;
function "*" ( L: in complex; R: in complex ) return complex;
function "*" ( L: in complex_polar; R: in complex_polar) return complex;
function "*" ( L: in complex_polar; R: in complex ) return complex;
function "*" ( L: in complex; R: in complex_polar) return complex;
function "*" ( L: in real; R: in complex ) return complex;
function "*" ( L: in complex; R: in real ) return complex;
function "*" ( L: in real; R: in complex_polar) return complex;
function "*" ( L: in complex_polar; R: in real) return complex;
function "/" ( L: in complex; R: in complex ) return complex;
function "/" ( L: in complex_polar; R: in complex_polar) return complex;
function "/" ( L: in complex_polar; R: in complex ) return complex;
function "/" ( L: in complex; R: in complex_polar) return complex;
function "/" ( L: in real; R: in complex ) return complex;
function "/" ( L: in complex; R: in real ) return complex;
function "/" ( L: in real; R: in complex_polar) return complex;
function "/" ( L: in complex_polar; R: in real) return complex;
end MATH_COMPLEX;
---------------------------------------------------------------
--
-- This source file may be used and distributed without restriction.
-- No declarations or definitions shall be added to this package.
-- This package cannot be sold or distributed for profit.
--
-- ****************************************************************
-- * *
-- * W A R N I N G *
-- * *
-- * This DRAFT version IS NOT endorsed or approved by IEEE *
-- * *
-- ****************************************************************
--
-- Title: PACKAGE BODY MATH_REAL
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Purpose: VHDL declarations for mathematical package MATH_REAL
-- which contains common real constants, common real
-- functions, and real trascendental functions.
--
-- Author: IEEE VHDL Math Package Study Group
--
-- Notes:
-- The package body shall be considered the formal definition of
-- the semantics of this package. Tool developers may choose to implement
-- the package body in the most efficient manner available to them.
--
-- Source code and algorithms for this package body comes from the
-- following sources:
-- IEEE VHDL Math Package Study Group participants,
-- U. of Mississippi, Mentor Graphics, Synopsys,
-- Viewlogic/Vantage, Communications of the ACM (June 1988, Vol
-- 31, Number 6, pp. 747, Pierre L'Ecuyer, Efficient and Portable
-- Random Number Generators), Handbook of Mathematical Functions
-- by Milton Abramowitz and Irene A. Stegun (Dover).
--
-- History:
-- Version 0.1 Jose A. Torres 4/23/93 First draft
-- Version 0.2 Jose A. Torres 5/28/93 Fixed potentially illegal code
-------------------------------------------------------------
Library IEEE;
Package body MATH_REAL is
--
-- some constants for use in the package body only
--
constant Q_PI : real := MATH_PI/4.0;
constant HALF_PI : real := MATH_PI/2.0;
constant TWO_PI : real := MATH_PI*2.0;
constant MAX_ITER: integer := 27; -- max precision factor for cordic
--
-- some type declarations for cordic operations
--
constant KC : REAL := 6.0725293500888142e-01; -- constant for cordic
type REAL_VECTOR is array (NATURAL range <>) of REAL;
type NATURAL_VECTOR is array (NATURAL range <>) of NATURAL;
subtype REAL_VECTOR_N is REAL_VECTOR (0 to max_iter);
subtype REAL_ARR_2 is REAL_VECTOR (0 to 1);
subtype REAL_ARR_3 is REAL_VECTOR (0 to 2);
subtype QUADRANT is INTEGER range 0 to 3;
type CORDIC_MODE_TYPE is (ROTATION, VECTORING);
--
-- auxiliary functions for cordic algorithms
--
function POWER_OF_2_SERIES (d : NATURAL_VECTOR; initial_value : REAL;
number_of_values : NATURAL) return REAL_VECTOR is
variable v : REAL_VECTOR (0 to number_of_values);
variable temp : REAL := initial_value;
variable flag : boolean := true;
begin
for i in 0 to number_of_values loop
v(i) := temp;
for p in d'range loop
if i = d(p) then
flag := false;
end if;
end loop;
if flag then
temp := temp/2.0;
end if;
flag := true;
end loop;
return v;
end POWER_OF_2_SERIES;
constant two_at_minus : REAL_VECTOR := POWER_OF_2_SERIES(
NATURAL_VECTOR'(100, 90),1.0,
MAX_ITER);
constant epsilon : REAL_VECTOR_N := (
7.8539816339744827e-01,
4.6364760900080606e-01,
2.4497866312686413e-01,
1.2435499454676144e-01,
6.2418809995957351e-02,
3.1239833430268277e-02,
1.5623728620476830e-02,
7.8123410601011116e-03,
3.9062301319669717e-03,
1.9531225164788189e-03,
9.7656218955931937e-04,
4.8828121119489829e-04,
2.4414062014936175e-04,
1.2207031189367021e-04,
6.1035156174208768e-05,
3.0517578115526093e-05,
1.5258789061315760e-05,
7.6293945311019699e-06,
3.8146972656064960e-06,
1.9073486328101870e-06,
9.5367431640596080e-07,
4.7683715820308876e-07,
2.3841857910155801e-07,
1.1920928955078067e-07,
5.9604644775390553e-08,
2.9802322387695303e-08,
1.4901161193847654e-08,
7.4505805969238281e-09
);
function CORDIC ( x0 : REAL;
y0 : REAL;
z0 : REAL;
n : NATURAL; -- precision factor
CORDIC_MODE : CORDIC_MODE_TYPE -- rotation (z -> 0)
-- or vectoring (y -> 0)
) return REAL_ARR_3 is
variable x : REAL := x0;
variable y : REAL := y0;
variable z : REAL := z0;
variable x_temp : REAL;
begin
if CORDIC_MODE = ROTATION then
for k in 0 to n loop
x_temp := x;
if ( z >= 0.0) then
x := x - y * two_at_minus(k);
y := y + x_temp * two_at_minus(k);
z := z - epsilon(k);
else
x := x + y * two_at_minus(k);
y := y - x_temp * two_at_minus(k);
z := z + epsilon(k);
end if;
end loop;
else
for k in 0 to n loop
x_temp := x;
if ( y < 0.0) then
x := x - y * two_at_minus(k);
y := y + x_temp * two_at_minus(k);
z := z - epsilon(k);
else
x := x + y * two_at_minus(k);
y := y - x_temp * two_at_minus(k);
z := z + epsilon(k);
end if;
end loop;
end if;
return REAL_ARR_3'(x, y, z);
end CORDIC;
--
-- non-trascendental functions
--
function SIGN (X: real ) return real is
-- returns 1.0 if X > 0.0; 0.0 if X == 0.0; -1.0 if X < 0.0
begin
if ( X > 0.0 ) then
return 1.0;
elsif ( X < 0.0 ) then
return -1.0;
else
return 0.0;
end if;
end SIGN;
function CEIL (X : real ) return real is
-- returns smallest integer value (as real) not less than X
-- No conversion to an integer type is expected, so truncate cannot
-- overflow for large arguments.
variable large: real := 1073741824.0;
type long is range -1073741824 to 1073741824;
-- 2**30 is longer than any single-precision mantissa
variable rd: real;
begin
if abs( X) >= large then
return X;
else
rd := real ( long( X));
if X > 0.0 then
if rd >= X then
return rd;
else
return rd + 1.0;
end if;
elsif X = 0.0 then
return 0.0;
else
if rd <= X then
return rd;
else
return rd - 1.0;
end if;
end if;
end if;
end CEIL;
function FLOOR (X : real ) return real is
-- returns largest integer value (as real) not greater than X
-- No conversion to an integer type is expected, so truncate
-- cannot overflow for large arguments.
--
variable large: real := 1073741824.0;
type long is range -1073741824 to 1073741824;
-- 2**30 is longer than any single-precision mantissa
variable rd: real;
begin
if abs( X ) >= large then
return X;
else
rd := real ( long( X));
if X > 0.0 then
if rd <= X then
return rd;
else
return rd - 1.0;
end if;
elsif X = 0.0 then
return 0.0;
else
if rd >= X then
return rd;
else
return rd + 1.0;
end if;
end if;
end if;
end FLOOR;
function ROUND (X : real ) return real is
-- returns integer FLOOR(X + 0.5) if X > 0;
-- return integer CEIL(X - 0.5) if X < 0
begin
if X > 0.0 then
return FLOOR(X + 0.5);
elsif X < 0.0 then
return CEIL( X - 0.5);
else
return 0.0;
end if;
end ROUND;
function FMAX (X, Y : real ) return real is
-- returns the algebraically larger of X and Y
begin
if X > Y then
return X;
else
return Y;
end if;
end FMAX;
function FMIN (X, Y : real ) return real is
-- returns the algebraically smaller of X and Y
begin
if X < Y then
return X;
else
return Y;
end if;
end FMIN;
--
-- Pseudo-random number generators
--
procedure UNIFORM(variable Seed1,Seed2:inout integer;variable X:out real) is
-- returns a pseudo-random number with uniform distribution in the
-- interval (0.0, 1.0).
-- Before the first call to UNIFORM, the seed values (Seed1, Seed2) must
-- be initialized to values in the range [1, 2147483562] and
-- [1, 2147483398] respectively. The seed values are modified after
-- each call to UNIFORM.
-- This random number generator is portable for 32-bit computers, and
-- it has period ~2.30584*(10**18) for each set of seed values.
--
-- For VHDL-1992, the seeds will be global variables, functions to
-- initialize their values (INIT_SEED) will be provided, and the UNIFORM
-- procedure call will be modified accordingly.
variable z, k: integer;
begin
k := Seed1/53668;
Seed1 := 40014 * (Seed1 - k * 53668) - k * 12211;
if Seed1 < 0 then
Seed1 := Seed1 + 2147483563;
end if;
k := Seed2/52774;
Seed2 := 40692 * (Seed2 - k * 52774) - k * 3791;
if Seed2 < 0 then
Seed2 := Seed2 + 2147483399;
end if;
z := Seed1 - Seed2;
if z < 1 then
z := z + 2147483562;
end if;
X := REAL(Z)*4.656613e-10;
end UNIFORM;
function SRAND (seed: in integer ) return integer is
--
-- sets value of seed for sequence of
-- pseudo-random numbers.
-- Returns the value of the seed.
-- It uses the foreign native C function srand().
begin
end SRAND;
function RAND return integer is
--
-- returns an integer pseudo-random number with uniform distribution.
-- It uses the foreign native C function rand().
-- Seed for the sequence is initialized with the
-- SRAND() function and value of the seed is changed every
-- time SRAND() is called, but it is not visible.
-- The range of generated values is platform dependent.
begin
end RAND;
function GET_RAND_MAX return integer is
--
-- returns the upper bound of the range of the
-- pseudo-random numbers generated by RAND().
-- The support for this function is platform dependent, and
-- it uses foreign native C functions or constants.
-- It may not be available in some platforms.
-- Note: the value of (RAND / GET_RAND_MAX) is a
-- pseudo-random number distributed between 0 & 1.
begin
end GET_RAND_MAX;
--
-- trascendental and trigonometric functions
--
function SQRT (X : real ) return real is
-- returns square root of X; X >= 0
--
-- Computes square root using the Newton-Raphson approximation:
-- F(n+1) = 0.5*[F(n) + x/F(n)];
--
constant inival: real := 1.5;
constant eps : real := 0.000001;
constant relative_err : real := eps*X;
variable oldval : real ;
variable newval : real ;
begin
-- check validity of argument
if ( X < 0.0 ) then
assert false report "X < 0 in SQRT(X)"
severity ERROR;
return (0.0);
end if;
-- get the square root for special cases
if X = 0.0 then
return 0.0;
else
if ( X = 1.0 ) then
return 1.0; -- return exact value
end if;
end if;
-- get the square root for general cases
oldval := inival;
newval := (X/oldval + oldval)/2.0;
while ( abs(newval -oldval) > relative_err ) loop
oldval := newval;
newval := (X/oldval + oldval)/2.0;
end loop;
return newval;
end SQRT;
function CBRT (X : real ) return real is
-- returns cube root of X
-- Computes square root using the Newton-Raphson approximation:
-- F(n+1) = (1/3)*[2*F(n) + x/F(n)**2];
--
constant inival: real := 1.5;
constant eps : real := 0.000001;
constant relative_err : real := eps*abs(X);
variable xlocal : real := X;
variable negative : boolean := X < 0.0;
variable oldval : real ;
variable newval : real ;
begin
-- compute root for special cases
if X = 0.0 then
return 0.0;
elsif ( X = 1.0 ) then
return 1.0;
else
if X = -1.0 then
return -1.0;
end if;
end if;
-- compute root for general cases
if negative then
xlocal := -X;
end if;
oldval := inival;
newval := (xlocal/(oldval*oldval) + 2.0*oldval)/3.0;
while ( abs(newval -oldval) > relative_err ) loop
oldval := newval;
newval :=(xlocal/(oldval*oldval) + 2.0*oldval)/3.0;
end loop;
if negative then
newval := -newval;
end if;
return newval;
end CBRT;
function "**" (X : integer; Y : real) return real is
-- returns Y power of X ==> X**Y;
-- error if X = 0 and Y <= 0.0
-- error if X < 0 and Y does not have an integer value
begin
-- check validity of argument
if ( X = 0 ) and ( Y <= 0.0 ) then
assert false report "X = 0 and Y <= 0.0 in X**Y"
severity ERROR;
return (0.0);
end if;
if ( X < 0 ) and ( Y /= REAL(INTEGER(Y)) ) then
assert false report "X < 0 and Y \= integer in X**Y"
severity ERROR;
return (0.0);
end if;
-- compute the result
return EXP (Y * LOG (REAL(X)));
end "**";
function "**" (X : real; Y : real) return real is
-- returns Y power of X ==> X**Y;
-- error if X = 0.0 and Y <= 0.0
-- error if X < 0.0 and Y does not have an integer value
begin
-- check validity of argument
if ( X = 0.0 ) and ( Y <= 0.0 ) then
assert false report "X = 0.0 and Y <= 0.0 in X**Y"
severity ERROR;
return (0.0);
end if;
if ( X < 0.0 ) and ( Y /= REAL(INTEGER(Y)) ) then
assert false report "X < 0.0 and Y \= integer in X**Y"
severity ERROR;
return (0.0);
end if;
-- compute the result
return EXP (Y * LOG (X));
end "**";
function EXP (X : real ) return real is
-- returns e**X; where e = MATH_E
--
-- This function computes the exponential using the following series:
-- exp(x) = 1 + x + x**2/2! + x**3/3! + ... ; x > 0
--
constant eps : real := 0.000001; -- precision criteria
variable reciprocal: boolean := x < 0.0;-- check sign of argument
variable xlocal : real := abs(x); -- use positive value
variable oldval: real ; -- following variables are
variable num: real ; -- used for series evaluation
variable count: integer ;
variable denom: real ;
variable newval: real ;
begin
-- compute value for special cases
if X = 0.0 then
return 1.0;
else
if X = 1.0 then
return MATH_E;
end if;
end if;
-- compute value for general cases
oldval := 1.0;
num := xlocal;
count := 1;
denom := 1.0;
newval:= oldval + num/denom;
while ( abs(newval - oldval) > eps ) loop
oldval := newval;
num := num*xlocal;
count := count +1;
denom := denom*(real(count));
newval := oldval + num/denom;
end loop;
if reciprocal then
newval := 1.0/newval;
end if;
return newval;
end EXP;
function LOG (X : real ) return real is
-- returns natural logarithm of X; X > 0
--
-- This function computes the exponential using the following series:
-- log(x) = 2[ (x-1)/(x+1) + (((x-1)/(x+1))**3)/3.0 + ...] ; x > 0
--
constant eps : real := 0.000001; -- precision criteria
variable xlocal: real ; -- following variables are
variable oldval: real ; -- used to evaluate the series
variable xlocalsqr: real ;
variable factor : real ;
variable count: integer ;
variable newval: real ;
begin
-- check validity of argument
if ( x <= 0.0 ) then
assert false report "X <= 0 in LOG(X)"
severity ERROR;
return(REAL'LOW);
end if;
-- compute value for special cases
if ( X = 1.0 ) then
return 0.0;
else
if ( X = MATH_E ) then
return 1.0;
end if;
end if;
-- compute value for general cases
xlocal := (X - 1.0)/(X + 1.0);
oldval := xlocal;
xlocalsqr := xlocal*xlocal;
factor := xlocal*xlocalsqr;
count := 3;
newval := oldval + (factor/real(count));
while ( abs(newval - oldval) > eps ) loop
oldval := newval;
count := count +2;
factor := factor * xlocalsqr;
newval := oldval + factor/real(count);
end loop;
newval := newval * 2.0;
return newval;
end LOG;
function LOG (BASE: positive; X : real) return real is
-- returns logarithm base BASE of X; X > 0
begin
-- check validity of argument
if ( BASE <= 0 ) or ( x <= 0.0 ) then
assert false report "BASE <= 0 or X <= 0.0 in LOG(BASE, X)"
severity ERROR;
return(REAL'LOW);
end if;
-- compute the value
return ( LOG(X)/LOG(REAL(BASE)));
end LOG;
function SIN (X : real ) return real is
-- returns sin X; X in radians
variable n : INTEGER;
begin
if (x < 1.6 ) and (x > -1.6) then
return CORDIC( KC, 0.0, x, 27, ROTATION)(1);
end if;
n := INTEGER( x / HALF_PI );
case QUADRANT( n mod 4 ) is
when 0 =>
return CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(1);
when 1 =>
return CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(0);
when 2 =>
return -CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(1);
when 3 =>
return -CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(0);
end case;
end SIN;
function COS (x : REAL) return REAL is
-- returns cos X; X in radians
variable n : INTEGER;
begin
if (x < 1.6 ) and (x > -1.6) then
return CORDIC( KC, 0.0, x, 27, ROTATION)(0);
end if;
n := INTEGER( x / HALF_PI );
case QUADRANT( n mod 4 ) is
when 0 =>
return CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(0);
when 1 =>
return -CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(1);
when 2 =>
return -CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(0);
when 3 =>
return CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(1);
end case;
end COS;
function TAN (x : REAL) return REAL is
-- returns tan X; X in radians
-- X /= ((2k+1) * PI/2), where k is an integer
variable n : INTEGER := INTEGER( x / HALF_PI );
variable v : REAL_ARR_3 :=
CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION);
begin
if n mod 2 = 0 then
return v(1)/v(0);
else
return -v(0)/v(1);
end if;
end TAN;
function ASIN (x : real ) return real is
-- returns -PI/2 < asin X < PI/2; | X | <= 1
begin
if abs x > 1.0 then
assert false report "Out of range parameter passed to ASIN"
severity ERROR;
return x;
elsif abs x < 0.9 then
return atan(x/(sqrt(1.0 - x*x)));
elsif x > 0.0 then
return HALF_PI - atan(sqrt(1.0 - x*x)/x);
else
return - HALF_PI + atan((sqrt(1.0 - x*x))/x);
end if;
end ASIN;
function ACOS (x : REAL) return REAL is
-- returns 0 < acos X < PI; | X | <= 1
begin
if abs x > 1.0 then
assert false report "Out of range parameter passed to ACOS"
severity ERROR;
return x;
elsif abs x > 0.9 then
if x > 0.0 then
return atan(sqrt(1.0 - x*x)/x);
else
return MATH_PI - atan(sqrt(1.0 - x*x)/x);
end if;
else
return HALF_PI - atan(x/sqrt(1.0 - x*x));
end if;
end ACOS;
function ATAN (x : REAL) return REAL is
-- returns -PI/2 < atan X < PI/2
begin
return CORDIC( 1.0, x, 0.0, 27, VECTORING )(2);
end ATAN;
function ATAN2 (x : REAL; y : REAL) return REAL is
-- returns atan (X/Y); -PI < atan2(X,Y) < PI; Y /= 0.0
begin
if y = 0.0 then
if x = 0.0 then
assert false report "atan2(0.0, 0.0) is undetermined, returned 0,0"
severity NOTE;
return 0.0;
elsif x > 0.0 then
return 0.0;
else
return MATH_PI;
end if;
elsif x > 0.0 then
return CORDIC( x, y, 0.0, 27, VECTORING )(2);
else
return MATH_PI + CORDIC( x, y, 0.0, 27, VECTORING )(2);
end if;
end ATAN2;
function SINH (X : real) return real is
-- hyperbolic sine; returns (e**X - e**(-X))/2
begin
return ( (EXP(X) - EXP(-X))/2.0 );
end SINH;
function COSH (X : real) return real is
-- hyperbolic cosine; returns (e**X + e**(-X))/2
begin
return ( (EXP(X) + EXP(-X))/2.0 );
end COSH;
function TANH (X : real) return real is
-- hyperbolic tangent; -- returns (e**X - e**(-X))/(e**X + e**(-X))
begin
return ( (EXP(X) - EXP(-X))/(EXP(X) + EXP(-X)) );
end TANH;
function ASINH (X : real) return real is
-- returns ln( X + sqrt( X**2 + 1))
begin
return ( LOG( X + SQRT( X**2 + 1.0)) );
end ASINH;
function ACOSH (X : real) return real is
-- returns ln( X + sqrt( X**2 - 1)); X >= 1
begin
if abs x >= 1.0 then
assert false report "Out of range parameter passed to ACOSH"
severity ERROR;
return x;
end if;
return ( LOG( X + SQRT( X**2 - 1.0)) );
end ACOSH;
function ATANH (X : real) return real is
-- returns (ln( (1 + X)/(1 - X)))/2 ; | X | < 1
begin
if abs x < 1.0 then
assert false report "Out of range parameter passed to ATANH"
severity ERROR;
return x;
end if;
return( LOG( (1.0+X)/(1.0-X) )/2.0 );
end ATANH;
end MATH_REAL;
---------------------------------------------------------------
--
-- This source file may be used and distributed without restriction.
-- No declarations or definitions shall be included in this package.
-- This package cannot be sold or distributed for profit.
--
-- ****************************************************************
-- * *
-- * W A R N I N G *
-- * *
-- * This DRAFT version IS NOT endorsed or approved by IEEE *
-- * *
-- ****************************************************************
--
-- Title: PACKAGE BODY MATH_COMPLEX
--
-- Purpose: VHDL declarations for mathematical package MATH_COMPLEX
-- which contains common complex constants and basic complex
-- functions and operations.
--
-- Author: IEEE VHDL Math Package Study Group
--
-- Notes:
-- The package body uses package IEEE.MATH_REAL
--
-- The package body shall be considered the formal definition of
-- the semantics of this package. Tool developers may choose to implement
-- the package body in the most efficient manner available to them.
--
-- Source code for this package body comes from the following
-- following sources:
-- IEEE VHDL Math Package Study Group participants,
-- U. of Mississippi, Mentor Graphics, Synopsys,
-- Viewlogic/Vantage, Communications of the ACM (June 1988, Vol
-- 31, Number 6, pp. 747, Pierre L'Ecuyer, Efficient and Portable
-- Random Number Generators, Handbook of Mathematical Functions
-- by Milton Abramowitz and Irene A. Stegun (Dover).
--
-- History:
-- Version 0.1 Jose A. Torres 4/23/93 First draft
-- Version 0.2 Jose A. Torres 5/28/93 Fixed potentially illegal code
--
-------------------------------------------------------------
----use MATH_REAL.all; -- real trascendental operations
--Package body MATH_COMPLEX is
-- function CABS(Z: in complex ) return real is
-- -- returns absolute value (magnitude) of Z
-- variable ztemp : complex_polar;
-- begin
-- ztemp := COMPLEX_TO_POLAR(Z);
-- return ztemp.mag;
-- end CABS;
-- function CARG(Z: in complex ) return real is
-- -- returns argument (angle) in radians of a complex number
-- variable ztemp : complex_polar;
-- begin
-- ztemp := COMPLEX_TO_POLAR(Z);
-- return ztemp.arg;
-- end CARG;
-- function CMPLX(X: in real; Y: in real := 0.0 ) return complex is
-- -- returns complex number X + iY
-- begin
-- return COMPLEX'(X, Y);
-- end CMPLX;
-- function "-" (Z: in complex ) return complex is
-- -- unary minus; returns -x -jy for z= x + jy
-- begin
-- return COMPLEX'(-z.Re, -z.Im);
-- end "-";
-- function "-" (Z: in complex_polar ) return complex_polar is
-- -- unary minus; returns (z.mag, z.arg + MATH_PI)
-- begin
-- return COMPLEX_POLAR'(z.mag, z.arg + MATH_PI);
-- end "-";
-- function CONJ (Z: in complex) return complex is
-- -- returns complex conjugate (x-jy for z = x+ jy)
-- begin
-- return COMPLEX'(z.Re, -z.Im);
-- end CONJ;
-- function CONJ (Z: in complex_polar) return complex_polar is
-- -- returns complex conjugate (z.mag, -z.arg)
-- begin
-- return COMPLEX_POLAR'(z.mag, -z.arg);
-- end CONJ;
-- function CSQRT(Z: in complex ) return complex_vector is
-- -- returns square root of Z; 2 values
-- variable ztemp : complex_polar;
-- variable zout : complex_vector (0 to 1);
-- variable temp : real;
-- begin
-- ztemp := COMPLEX_TO_POLAR(Z);
-- temp := SQRT(ztemp.mag);
-- zout(0).re := temp*COS(ztemp.arg/2.0);
-- zout(0).im := temp*SIN(ztemp.arg/2.0);
-- zout(1).re := temp*COS(ztemp.arg/2.0 + MATH_PI);
-- zout(1).im := temp*SIN(ztemp.arg/2.0 + MATH_PI);
-- return zout;
-- end CSQRT;
-- function CEXP(Z: in complex ) return complex is
-- -- returns e**Z
-- begin
-- return COMPLEX'(EXP(Z.re)*COS(Z.im), EXP(Z.re)*SIN(Z.im));
-- end CEXP;
-- function COMPLEX_TO_POLAR(Z: in complex ) return complex_polar is
-- -- converts complex to complex_polar
-- begin
-- return COMPLEX_POLAR'(sqrt(z.re**2 + z.im**2),atan2(z.re,z.im));
-- end COMPLEX_TO_POLAR;
-- function POLAR_TO_COMPLEX(Z: in complex_polar ) return complex is
-- -- converts complex_polar to complex
-- begin
-- return COMPLEX'( z.mag*cos(z.arg), z.mag*sin(z.arg) );
-- end POLAR_TO_COMPLEX;
-- --
-- -- arithmetic operators
-- --
-- function "+" ( L: in complex; R: in complex ) return complex is
-- begin
-- return COMPLEX'(L.Re + R.Re, L.Im + R.Im);
-- end "+";
-- function "+" (L: in complex_polar; R: in complex_polar) return complex is
-- variable zL, zR : complex;
-- begin
-- zL := POLAR_TO_COMPLEX( L );
-- zR := POLAR_TO_COMPLEX( R );
-- return COMPLEX'(zL.Re + zR.Re, zL.Im + zR.Im);
-- end "+";
-- function "+" ( L: in complex_polar; R: in complex ) return complex is
-- variable zL : complex;
-- begin
-- zL := POLAR_TO_COMPLEX( L );
-- return COMPLEX'(zL.Re + R.Re, zL.Im + R.Im);
-- end "+";
-- function "+" ( L: in complex; R: in complex_polar) return complex is
-- variable zR : complex;
-- begin
-- zR := POLAR_TO_COMPLEX( R );
-- return COMPLEX'(L.Re + zR.Re, L.Im + zR.Im);
-- end "+";
-- function "+" ( L: in real; R: in complex ) return complex is
-- begin
-- return COMPLEX'(L + R.Re, R.Im);
-- end "+";
-- function "+" ( L: in complex; R: in real ) return complex is
-- begin
-- return COMPLEX'(L.Re + R, L.Im);
-- end "+";
-- function "+" ( L: in real; R: in complex_polar) return complex is
-- variable zR : complex;
-- begin
-- zR := POLAR_TO_COMPLEX( R );
-- return COMPLEX'(L + zR.Re, zR.Im);
-- end "+";
-- function "+" ( L: in complex_polar; R: in real) return complex is
-- variable zL : complex;
-- begin
-- zL := POLAR_TO_COMPLEX( L );
-- return COMPLEX'(zL.Re + R, zL.Im);
-- end "+";
-- function "-" ( L: in complex; R: in complex ) return complex is
-- begin
-- return COMPLEX'(L.Re - R.Re, L.Im - R.Im);
-- end "-";
-- function "-" ( L: in complex_polar; R: in complex_polar) return complex is
-- variable zL, zR : complex;
-- begin
-- zL := POLAR_TO_COMPLEX( L );
-- zR := POLAR_TO_COMPLEX( R );
-- return COMPLEX'(zL.Re - zR.Re, zL.Im - zR.Im);
-- end "-";
-- function "-" ( L: in complex_polar; R: in complex ) return complex is
-- variable zL : complex;
-- begin
-- zL := POLAR_TO_COMPLEX( L );
-- return COMPLEX'(zL.Re - R.Re, zL.Im - R.Im);
-- end "-";
-- function "-" ( L: in complex; R: in complex_polar) return complex is
-- variable zR : complex;
-- begin
-- zR := POLAR_TO_COMPLEX( R );
-- return COMPLEX'(L.Re - zR.Re, L.Im - zR.Im);
-- end "-";
-- function "-" ( L: in real; R: in complex ) return complex is
-- begin
-- return COMPLEX'(L - R.Re, -1.0 * R.Im);
-- end "-";
-- function "-" ( L: in complex; R: in real ) return complex is
-- begin
-- return COMPLEX'(L.Re - R, L.Im);
-- end "-";
-- function "-" ( L: in real; R: in complex_polar) return complex is
-- variable zR : complex;
-- begin
-- zR := POLAR_TO_COMPLEX( R );
-- return COMPLEX'(L - zR.Re, -1.0*zR.Im);
-- end "-";
-- function "-" ( L: in complex_polar; R: in real) return complex is
-- variable zL : complex;
-- begin
-- zL := POLAR_TO_COMPLEX( L );
-- return COMPLEX'(zL.Re - R, zL.Im);
-- end "-";
-- function "*" ( L: in complex; R: in complex ) return complex is
-- begin
-- return COMPLEX'(L.Re * R.Re - L.Im * R.Im, L.Re * R.Im + L.Im * R.Re);
-- end "*";
-- function "*" ( L: in complex_polar; R: in complex_polar) return complex is
-- variable zout : complex_polar;
-- begin
-- zout.mag := L.mag * R.mag;
-- zout.arg := L.arg + R.arg;
-- return POLAR_TO_COMPLEX(zout);
-- end "*";
-- function "*" ( L: in complex_polar; R: in complex ) return complex is
-- variable zL : complex;
-- begin
-- zL := POLAR_TO_COMPLEX( L );
-- return COMPLEX'(zL.Re*R.Re - zL.Im * R.Im, zL.Re * R.Im + zL.Im*R.Re);
-- end "*";
-- function "*" ( L: in complex; R: in complex_polar) return complex is
-- variable zR : complex;
-- begin
-- zR := POLAR_TO_COMPLEX( R );
-- return COMPLEX'(L.Re*zR.Re - L.Im * zR.Im, L.Re * zR.Im + L.Im*zR.Re);
-- end "*";
-- function "*" ( L: in real; R: in complex ) return complex is
-- begin
-- return COMPLEX'(L * R.Re, L * R.Im);
-- end "*";
-- function "*" ( L: in complex; R: in real ) return complex is
-- begin
-- return COMPLEX'(L.Re * R, L.Im * R);
-- end "*";
-- function "*" ( L: in real; R: in complex_polar) return complex is
-- variable zR : complex;
-- begin
-- zR := POLAR_TO_COMPLEX( R );
-- return COMPLEX'(L * zR.Re, L * zR.Im);
-- end "*";
-- function "*" ( L: in complex_polar; R: in real) return complex is
-- variable zL : complex;
-- begin
-- zL := POLAR_TO_COMPLEX( L );
-- return COMPLEX'(zL.Re * R, zL.Im * R);
-- end "*";
-- function "/" ( L: in complex; R: in complex ) return complex is
-- variable magrsq : REAL := R.Re ** 2 + R.Im ** 2;
-- begin
-- if (magrsq = 0.0) then
-- assert FALSE report "Attempt to divide by (0,0)"
-- severity ERROR;
-- return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
-- else
-- return COMPLEX'( (L.Re * R.Re + L.Im * R.Im) / magrsq,
-- (L.Im * R.Re - L.Re * R.Im) / magrsq);
-- end if;
-- end "/";
-- function "/" ( L: in complex_polar; R: in complex_polar) return complex is
-- variable zout : complex_polar;
-- begin
-- if (R.mag = 0.0) then
-- assert FALSE report "Attempt to divide by (0,0)"
-- severity ERROR;
-- return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
-- else
-- zout.mag := L.mag/R.mag;
-- zout.arg := L.arg - R.arg;
-- return POLAR_TO_COMPLEX(zout);
-- end if;
-- end "/";
-- function "/" ( L: in complex_polar; R: in complex ) return complex is
-- variable zL : complex;
-- variable temp : REAL := R.Re ** 2 + R.Im ** 2;
-- begin
-- if (temp = 0.0) then
-- assert FALSE report "Attempt to divide by (0.0,0.0)"
-- severity ERROR;
-- return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
-- else
-- zL := POLAR_TO_COMPLEX( L );
-- return COMPLEX'( (zL.Re * R.Re + zL.Im * R.Im) / temp,
-- (zL.Im * R.Re - zL.Re * R.Im) / temp);
-- end if;
-- end "/";
-- function "/" ( L: in complex; R: in complex_polar) return complex is
-- variable zR : complex := POLAR_TO_COMPLEX( R );
-- variable temp : REAL := zR.Re ** 2 + zR.Im ** 2;
-- begin
-- if (R.mag = 0.0) or (temp = 0.0) then
-- assert FALSE report "Attempt to divide by (0.0,0.0)"
-- severity ERROR;
-- return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
-- else
-- return COMPLEX'( (L.Re * zR.Re + L.Im * zR.Im) / temp,
-- (L.Im * zR.Re - L.Re * zR.Im) / temp);
-- end if;
-- end "/";
-- function "/" ( L: in real; R: in complex ) return complex is
-- variable temp : REAL := R.Re ** 2 + R.Im ** 2;
-- begin
-- if (temp = 0.0) then
-- assert FALSE report "Attempt to divide by (0.0,0.0)"
-- severity ERROR;
-- return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
-- else
-- temp := L / temp;
-- return COMPLEX'( temp * R.Re, -temp * R.Im );
-- end if;
-- end "/";
-- function "/" ( L: in complex; R: in real ) return complex is
-- begin
-- if (R = 0.0) then
-- assert FALSE report "Attempt to divide by (0.0,0.0)"
-- severity ERROR;
-- return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
-- else
-- return COMPLEX'(L.Re / R, L.Im / R);
-- end if;
-- end "/";
-- function "/" ( L: in real; R: in complex_polar) return complex is
-- variable zR : complex := POLAR_TO_COMPLEX( R );
-- variable temp : REAL := zR.Re ** 2 + zR.Im ** 2;
-- begin
-- if (R.mag = 0.0) or (temp = 0.0) then
-- assert FALSE report "Attempt to divide by (0.0,0.0)"
-- severity ERROR;
-- return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
-- else
-- temp := L / temp;
-- return COMPLEX'( temp * zR.Re, -temp * zR.Im );
-- end if;
-- end "/";
-- function "/" ( L: in complex_polar; R: in real) return complex is
-- variable zL : complex := POLAR_TO_COMPLEX( L );
-- begin
-- if (R = 0.0) then
-- assert FALSE report "Attempt to divide by (0.0,0.0)"
-- severity ERROR;
-- return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
-- else
-- return COMPLEX'(zL.Re / R, zL.Im / R);
-- end if;
-- end "/";
--end MATH_COMPLEX;
| gpl-3.0 | 679acb554fa53bce9da8e36a3703fe97 | 0.524753 | 3.409324 | false | false | false | false |
TUM-LIS/faultify | hardware/testcases/fpu100_mul/fpga_sim/xpsLibraryPath_asic_400_631/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/vhdl/faultify_simulator.vhd | 1 | 5,578 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity faultify_simulator is
generic (
numInj : integer := 56;
numIn : integer := 10;
numOut : integer := 10);
port (
clk : in std_logic;
clk_m : in std_logic;
circ_ce : in std_logic;
circ_rst : in std_logic;
test : out std_logic_vector(31 downto 0);
testvector : in std_logic_vector(numIn-1 downto 0);
resultvector_o : out std_logic_vector(numOut-1 downto 0);
resultvector_f : out std_logic_vector(numOut-1 downto 0);
seed_in_en : in std_logic;
seed_in : in std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
shift_en : in std_logic;
rst_n : in std_logic);
end faultify_simulator;
-- 866:0
architecture behav of faultify_simulator is
component faultify_binomial_gen
generic (
width : integer);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : out std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
prob_out_c : out std_logic;
shift_en : in std_logic;
data_out : out std_logic;
data_out_valid : out std_logic);
end component;
component circuit_under_test
port (
clk : in std_logic;
rst : in std_logic;
testvector : in std_logic_vector(numIn-1 downto 0);
resultvector : out std_logic_vector(numOut-1 downto 0);
injectionvector : in std_logic_vector(621-1 downto 0));
end component;
component golden_circuit
port (
clk : in std_logic;
rst : in std_logic;
testvector : in std_logic_vector(numIn-1 downto 0);
resultvector : out std_logic_vector(numOut-1 downto 0));
end component;
signal injectionvector : std_logic_vector(numInj-1 downto 0);
signal injectionvector_reg : std_logic_vector(numInj-1 downto 0);
signal injectionvector_reg_o : std_logic_vector(numInj-1 downto 0);
signal seed_chain : std_logic_vector(numInj downto 0);
signal prob_chain : std_logic_vector(numInj downto 0);
signal rst : std_logic;
signal clk_ce_m : std_logic;
signal testvector_reg : std_logic_vector(numIn-1 downto 0);
attribute syn_noprune : boolean;
attribute syn_noprune of circuit_under_test_inst : label is true;
attribute syn_noprune of golden_circuit_inst : label is true;
attribute xc_props : string;
attribute xc_props of circuit_under_test_inst : label is "KEEP_HIERARCHY=TRUE";
attribute xc_props of golden_circuit_inst : label is "KEEP_HIERARCHY=TRUE";
signal inj_vec_total : std_logic_vector(621-1 downto 0);
begin -- behav
rst <= not rst_n;
-----------------------------------------------------------------------------
-- debug...
-----------------------------------------------------------------------------
-- resultvector_f <= (others => '1');
-- resultvector_o <= (others => '1');
cgate : bufgce
port map (
I => clk_m,
O => clk_ce_m,
CE => circ_ce);
process (clk_ce_m, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
testvector_reg <= (others => '0');
elsif clk_ce_m'event and clk_ce_m = '1' then -- rising clock edge
testvector_reg <= testvector;
end if;
end process;
circuit_under_test_inst : circuit_under_test
port map (
clk => clk_ce_m,
rst => circ_rst,
testvector => testvector_reg,
resultvector => resultvector_f,
injectionvector => inj_vec_total);
inj_vec_total(299 downto 0) <= (others => '0');
inj_vec_total(621-1 downto 300) <= injectionvector_reg;
golden_circuit_inst : golden_circuit
port map (
clk => clk_ce_m,
rst => circ_rst,
testvector => testvector_reg,
resultvector => resultvector_o
);
seed_chain(0) <= seed_in;
prob_chain(0) <= prob_in;
prsn_loop : for i in 0 to numInj-1 generate
prsn_top_1 : faultify_binomial_gen
generic map (
width => 32)
port map (
clk => clk,
rst_n => rst_n,
seed_in_en => seed_in_en,
seed_in => seed_chain(i),
seed_out_c => seed_chain(i+1),
prob_in_en => prob_in_en,
prob_in => prob_chain(i),
prob_out_c => prob_chain(i+1),
shift_en => shift_en,
data_out => injectionvector(i),
data_out_valid => open);
end generate prsn_loop;
reg : process (clk_ce_m, rst_n)
begin -- process reg
if rst_n = '0' then -- asynchronous reset (active low)
injectionvector_reg <= (others => '0');
--injectionvector_reg_o <= (others => '0');
--test <= (others => '0');
elsif clk_ce_m'event and clk_ce_m = '1' then -- rising clock edge
injectionvector_reg <= injectionvector;
--injectionvector_reg <= (others => '0');
--test <= injectionvector_reg_o(31 downto 0);
--injectionvector_reg_o(31 downto 0) <= injectionvector_reg_o(31 downto 0) or (resultvector_f(31 downto 0) xor resultvector_o(31 downto 0));
end if;
end process reg;
end behav;
| gpl-2.0 | dbdd0785f2166a70eb3e85ed138a1a6f | 0.547867 | 3.610356 | false | true | false | false |
jhoward321/pacman | usb_system/usb_system_inst.vhd | 1 | 3,574 | component usb_system is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
sdram_wire_addr : out std_logic_vector(12 downto 0); -- addr
sdram_wire_ba : out std_logic_vector(1 downto 0); -- ba
sdram_wire_cas_n : out std_logic; -- cas_n
sdram_wire_cke : out std_logic; -- cke
sdram_wire_cs_n : out std_logic; -- cs_n
sdram_wire_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- dq
sdram_wire_dqm : out std_logic_vector(3 downto 0); -- dqm
sdram_wire_ras_n : out std_logic; -- ras_n
sdram_wire_we_n : out std_logic; -- we_n
keycode_export : out std_logic_vector(7 downto 0); -- export
usb_DATA : inout std_logic_vector(15 downto 0) := (others => 'X'); -- DATA
usb_ADDR : out std_logic_vector(1 downto 0); -- ADDR
usb_RD_N : out std_logic; -- RD_N
usb_WR_N : out std_logic; -- WR_N
usb_CS_N : out std_logic; -- CS_N
usb_RST_N : out std_logic; -- RST_N
usb_INT : in std_logic := 'X'; -- INT
sdram_out_clk_clk : out std_logic; -- clk
usb_out_clk_clk : out std_logic -- clk
);
end component usb_system;
u0 : component usb_system
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
sdram_wire_addr => CONNECTED_TO_sdram_wire_addr, -- sdram_wire.addr
sdram_wire_ba => CONNECTED_TO_sdram_wire_ba, -- .ba
sdram_wire_cas_n => CONNECTED_TO_sdram_wire_cas_n, -- .cas_n
sdram_wire_cke => CONNECTED_TO_sdram_wire_cke, -- .cke
sdram_wire_cs_n => CONNECTED_TO_sdram_wire_cs_n, -- .cs_n
sdram_wire_dq => CONNECTED_TO_sdram_wire_dq, -- .dq
sdram_wire_dqm => CONNECTED_TO_sdram_wire_dqm, -- .dqm
sdram_wire_ras_n => CONNECTED_TO_sdram_wire_ras_n, -- .ras_n
sdram_wire_we_n => CONNECTED_TO_sdram_wire_we_n, -- .we_n
keycode_export => CONNECTED_TO_keycode_export, -- keycode.export
usb_DATA => CONNECTED_TO_usb_DATA, -- usb.DATA
usb_ADDR => CONNECTED_TO_usb_ADDR, -- .ADDR
usb_RD_N => CONNECTED_TO_usb_RD_N, -- .RD_N
usb_WR_N => CONNECTED_TO_usb_WR_N, -- .WR_N
usb_CS_N => CONNECTED_TO_usb_CS_N, -- .CS_N
usb_RST_N => CONNECTED_TO_usb_RST_N, -- .RST_N
usb_INT => CONNECTED_TO_usb_INT, -- .INT
sdram_out_clk_clk => CONNECTED_TO_sdram_out_clk_clk, -- sdram_out_clk.clk
usb_out_clk_clk => CONNECTED_TO_usb_out_clk_clk -- usb_out_clk.clk
);
| mit | bf8e2e80d965d08dad94ff2ae4feb5f7 | 0.412983 | 3.44316 | false | false | false | false |
lnls-dig/dsp-cores | hdl/testbench/multiplier/multiplier_bench.vhd | 1 | 2,866 | -------------------------------------------------------------------------------
-- Title : Multiplier testbench
-- Project :
-------------------------------------------------------------------------------
-- File : multiplier_bench.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-02-01
-- Last update: 2015-03-11
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Multiplier testbench
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-02-01 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
use std.textio.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity multiplier_bench is
end entity multiplier_bench;
architecture test of multiplier_bench is
constant input_freq : real := 120.0e6;
constant clock_period : time := 1.0 sec /(2.0*input_freq);
signal clock : std_logic := '0';
signal endoffile : bit := '0';
signal a1 : std_logic_vector(15 downto 0);
signal b1 : std_logic_vector(15 downto 0);
signal p1 : std_logic_vector(15 downto 0);
component generic_multiplier is
generic (
g_a_width : natural;
g_b_width : natural;
g_signed : boolean;
g_p_width : natural);
port (
a_i : in std_logic_vector(g_a_width-1 downto 0);
b_i : in std_logic_vector(g_b_width-1 downto 0);
p_o : out std_logic_vector(g_p_width-1 downto 0);
ce_i : in std_logic;
clk_i : in std_logic;
rst_i : in std_logic);
end component generic_multiplier;
begin -- architecture test
clk_gen : process
begin
clock <= '0';
wait for clock_period;
clock <= '1';
wait for clock_period;
end process;
uut : generic_multiplier
generic map(
g_a_width => 16,
g_b_width => 16,
g_signed => true,
g_p_width => 16)
port map(
a_i => a1,
b_i => b1,
p_o => p1,
ce_i => '1',
clk_i => clock,
rst_i => '0');
b1 <= X"FFFF";
-- FIXME: too simple of a test, requiring manual inspection. Improve it.
single_test : process(clock)
variable a_test : integer := -1000;
begin
if rising_edge(clock) then
a1 <= std_logic_vector(to_signed(a_test, 16));
a_test := a_test + 20;
if a_test = 1000 then
assert(false) report "Input file finished." severity failure;
end if;
end if;
end process;
end architecture test;
| lgpl-3.0 | 2ab8cdaba4f9edc40d24758b675d8600 | 0.49023 | 3.771053 | false | true | false | false |
SoCdesign/EHA | RTL/Hand_Shaking/Checkers/Control_part_checkers/Handshaking_FC/Arbiter_checkers/RTL_and_Synthesis/Arbiter_with_checkers_top.vhd | 1 | 14,258 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Arbiter_with_checkers_top is
port ( Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules
DCTS: in std_logic; -- Getting the CTS signal from the input FIFO of the next router/NI (for hand-shaking)
RTS_FF: in std_logic;
state: in std_logic_vector (5 downto 0); -- 6 states for Arbiter's FSM
-- Arbiter outputs
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
Xbar_sel : out std_logic_vector(4 downto 0); -- select lines for XBAR
RTS_FF_in: out std_logic; -- Valid output which is sent to the next router/NI to specify that the data on the output port is valid
state_in: out std_logic_vector (5 downto 0); -- 6 states for Arbiter's FSM
next_state_out: out std_logic_vector (5 downto 0); -- 6 states for Arbiter's FSM
-- Checker outputs
err_state_IDLE_xbar,
err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE,
err_IDLE_Req_L,
err_Local_Req_L,
err_North_Req_N,
err_East_Req_E,
err_West_Req_W,
err_South_Req_S,
err_IDLE_Req_N,
err_Local_Req_N,
err_North_Req_E,
err_East_Req_W,
err_West_Req_S,
err_South_Req_L,
err_IDLE_Req_E,
err_Local_Req_E,
err_North_Req_W,
err_East_Req_S,
err_West_Req_L,
err_South_Req_N,
err_IDLE_Req_W,
err_Local_Req_W,
err_North_Req_S,
err_East_Req_L,
err_West_Req_N,
err_South_Req_E,
err_IDLE_Req_S,
err_Local_Req_S,
err_North_Req_L,
err_East_Req_N,
err_West_Req_E,
err_South_Req_W,
err_next_state_onehot,
err_state_in_onehot,
err_DCTS_RTS_FF_state_Grant_L,
err_DCTS_RTS_FF_state_Grant_N,
err_DCTS_RTS_FF_state_Grant_E,
err_DCTS_RTS_FF_state_Grant_W,
err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel,
err_state_east_xbar_sel,
err_state_west_xbar_sel,
err_state_south_xbar_sel,
err_state_local_xbar_sel : out std_logic
);
end Arbiter_with_checkers_top;
architecture behavior of Arbiter_with_checkers_top is
component Arbiter_pseudo is
port (
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules
DCTS: in std_logic; -- Getting the CTS signal from the input FIFO of the next router/NI (for hand-shaking)
RTS_FF: in std_logic;
state: in std_logic_vector (5 downto 0); -- 6 states for Arbiter's FSM
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
Xbar_sel : out std_logic_vector (4 downto 0); -- select lines for XBAR
RTS_FF_in: out std_logic; -- Valid output which is sent to the next router/NI to specify that the data on the output port is valid
state_in: out std_logic_vector (5 downto 0); -- 6 states for Arbiter's FSM
next_state_out: out std_logic_vector (5 downto 0) -- 6 states for Arbiter's FSM
);
end component;
component Arbiter_checkers is
port (
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic;
DCTS: in std_logic;
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L: in std_logic;
Xbar_sel : in std_logic_vector(4 downto 0);
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
next_state_out: in std_logic_vector (5 downto 0);
RTS_FF: in std_logic;
RTS_FF_in: in std_logic;
-- Checker outputs
err_state_IDLE_xbar,
err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE,
err_IDLE_Req_L,
err_Local_Req_L,
err_North_Req_N,
err_East_Req_E,
err_West_Req_W,
err_South_Req_S,
err_IDLE_Req_N,
err_Local_Req_N,
err_North_Req_E,
err_East_Req_W,
err_West_Req_S,
err_South_Req_L,
err_IDLE_Req_E,
err_Local_Req_E,
err_North_Req_W,
err_East_Req_S,
err_West_Req_L,
err_South_Req_N,
err_IDLE_Req_W,
err_Local_Req_W,
err_North_Req_S,
err_East_Req_L,
err_West_Req_N,
err_South_Req_E,
err_IDLE_Req_S,
err_Local_Req_S,
err_North_Req_L,
err_East_Req_N,
err_West_Req_E,
err_South_Req_W,
err_next_state_onehot,
err_state_in_onehot,
err_DCTS_RTS_FF_state_Grant_L,
err_DCTS_RTS_FF_state_Grant_N,
err_DCTS_RTS_FF_state_Grant_E,
err_DCTS_RTS_FF_state_Grant_W,
err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel,
err_state_east_xbar_sel,
err_state_west_xbar_sel,
err_state_south_xbar_sel,
err_state_local_xbar_sel : out std_logic
);
end component;
signal Grant_N_sig, Grant_E_sig, Grant_W_sig, Grant_S_sig, Grant_L_sig: std_logic;
signal Xbar_sel_sig: std_logic_vector(4 downto 0);
signal state_in_sig: std_logic_vector (5 downto 0);
signal next_state_out_sig: std_logic_vector (5 downto 0);
signal RTS_FF_in_sig: std_logic;
begin
Grant_N <= Grant_N_sig;
Grant_E <= Grant_E_sig;
Grant_W <= Grant_W_sig;
Grant_S <= Grant_S_sig;
Grant_L <= Grant_L_sig;
Xbar_sel <= Xbar_sel_sig;
state_in <= state_in_sig;
RTS_FF_in <= RTS_FF_in_sig;
next_state_out <= next_state_out_sig;
-- Arbiter instantiation
ARBITER: Arbiter_pseudo port map (
Req_N=>Req_N,
Req_E=>Req_E,
Req_W=>Req_W,
Req_S=>Req_S,
Req_L=>Req_L,
DCTS => DCTS,
RTS_FF => RTS_FF,
state=>state,
Grant_N => Grant_N_sig,
Grant_E => Grant_E_sig,
Grant_W => Grant_W_sig,
Grant_S => Grant_S_sig,
Grant_L => Grant_L_sig,
Xbar_sel => Xbar_sel_sig,
RTS_FF_in => RTS_FF_in,
state_in => state_in_sig,
next_state_out => next_state_out_sig
);
-- Checkers instantiation
CHECKERS: Arbiter_checkers port map (
Req_N => Req_N,
Req_E => Req_E,
Req_W => Req_W,
Req_S => Req_S,
Req_L => Req_L,
DCTS => DCTS,
RTS_FF => RTS_FF,
state => state,
Grant_N => Grant_N_sig,
Grant_E => Grant_E_sig,
Grant_W => Grant_W_sig,
Grant_S => Grant_S_sig,
Grant_L => Grant_L_sig,
Xbar_sel=>Xbar_sel_sig,
state_in => state_in_sig,
next_state_out => next_state_out_sig,
RTS_FF_in => RTS_FF_in_sig,
err_state_IDLE_xbar => err_state_IDLE_xbar,
err_state_not_IDLE_xbar => err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in => err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in => err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in => err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state => err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state => err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants => err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants => err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants => err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE => err_Requests_next_state_IDLE,
err_IDLE_Req_L => err_IDLE_Req_L,
err_Local_Req_L => err_Local_Req_L,
err_North_Req_N => err_North_Req_N,
err_East_Req_E => err_East_Req_E,
err_West_Req_W => err_West_Req_W,
err_South_Req_S => err_South_Req_S,
err_IDLE_Req_N => err_IDLE_Req_N,
err_Local_Req_N => err_Local_Req_N,
err_North_Req_E => err_North_Req_E,
err_East_Req_W => err_East_Req_W,
err_West_Req_S => err_West_Req_S,
err_South_Req_L => err_South_Req_L,
err_IDLE_Req_E => err_IDLE_Req_E,
err_Local_Req_E => err_Local_Req_E,
err_North_Req_W => err_North_Req_W,
err_East_Req_S => err_East_Req_S,
err_West_Req_L => err_West_Req_L,
err_South_Req_N => err_South_Req_N,
err_IDLE_Req_W => err_IDLE_Req_W,
err_Local_Req_W => err_Local_Req_W,
err_North_Req_S => err_North_Req_S,
err_East_Req_L => err_East_Req_L,
err_West_Req_N => err_West_Req_N,
err_South_Req_E => err_South_Req_E,
err_IDLE_Req_S => err_IDLE_Req_S,
err_Local_Req_S => err_Local_Req_S,
err_North_Req_L => err_North_Req_L,
err_East_Req_N => err_East_Req_N,
err_West_Req_E => err_West_Req_E,
err_South_Req_W => err_South_Req_W,
err_next_state_onehot => err_next_state_onehot,
err_state_in_onehot => err_state_in_onehot,
err_DCTS_RTS_FF_state_Grant_L => err_DCTS_RTS_FF_state_Grant_L,
err_DCTS_RTS_FF_state_Grant_N => err_DCTS_RTS_FF_state_Grant_N,
err_DCTS_RTS_FF_state_Grant_E => err_DCTS_RTS_FF_state_Grant_E,
err_DCTS_RTS_FF_state_Grant_W => err_DCTS_RTS_FF_state_Grant_W,
err_DCTS_RTS_FF_state_Grant_S => err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel => err_state_north_xbar_sel,
err_state_east_xbar_sel => err_state_east_xbar_sel,
err_state_west_xbar_sel => err_state_west_xbar_sel,
err_state_south_xbar_sel => err_state_south_xbar_sel,
err_state_local_xbar_sel => err_state_local_xbar_sel
);
end behavior; | gpl-3.0 | 3932f4fdc23d7f2e3955d213d8b67dee | 0.44326 | 3.733438 | false | false | false | false |
Ana06/function-graphing-FPGA | vga.vhd | 2 | 25,666 | ----------------------------------------------------------------------------------
-- Company: Nameless2
-- Engineer: Ana María Martínez Gómez, Aitor Alonso Lorenzo, Víctor Adolfo Gallego Alcalá
--
-- Create Date: 12:10:21 11/10/2013
-- Design Name:
-- Module Name: vga - Behavioral
-- Project Name: Representación gráfica de funciones
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use std.textio.all;
--pantalla debe ser top
entity project is
port
( resetN: in std_logic; -- reset
clk: in std_logic;
ps2data: inout std_logic;
ps2clk: inout std_logic;
hsyncb: inout std_logic; -- horizontal (line) sync
vsyncb: out std_logic; -- vertical (frame) sync
rgb: out std_logic_vector(8 downto 0); -- red,green,blue colors
fin_principal: out std_logic;
escalay: out std_logic_vector(4 downto 0); --Conectada a barra de leds
escalax: out std_logic_vector(7 downto 0)); -- Conectada a los 7 segmentos
end project;
architecture project_arch of project is
component puntos_muestra is
Port ( caso : in std_logic_vector(1 downto 0);
numPuntos : in std_logic_vector( 6 downto 0);
enable, retro_muestra : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
fin : out STD_LOGIC;
entradaTeclado: in std_logic_vector(49 downto 0);
punto_o : out STD_LOGIC_VECTOR(20 downto 0);
count_o: out std_logic_vector(3 downto 0));-- Para mostrar en el display de 7 segmentos
end component puntos_muestra;
component calculo is
port(reset, clk, enable, integral: in std_logic;
num: in std_logic_vector(20 downto 0);
c: in std_logic_vector(49 downto 0);
s: out std_logic_vector(20 downto 0);
ready: out std_logic);
end component calculo;
component conversor is
port( caso : in std_logic_vector(1 downto 0);
numPuntos : in std_logic_vector(6 downto 0);
fin_pantalla: in std_logic;
avanza: in std_logic;
punto: in std_logic_vector(20 downto 0);
reset, clk:in std_logic;
punto1X, punto1Y, punto2X, punto2Y: out std_logic_vector(6 downto 0);
enable_pantalla, fin_conv, inf: out std_logic;
indice_o: out std_logic_vector(4 downto 0)); -- Para mostrarlo en la barra de LEDs
end component conversor;
component divisor is
port (
reset: in STD_LOGIC;
clk_entrada: in STD_LOGIC; -- reloj de entrada de la entity superior
clk_salida: out STD_LOGIC -- reloj que se utiliza en los process del programa principal
);
end component;
component rams_2p is
port (clk : in std_logic;
we : in std_logic;
addr1 : in std_logic_vector(6 downto 0);
addr2 : in std_logic_vector(6 downto 0);
di : in std_logic_vector(0 to 127);
do1 : out std_logic_vector(0 to 127);
do2 : out std_logic_vector(0 to 127)
);
end component;
component reconocedor is
port(ps2data: inout std_logic;
ps2clk: inout std_logic;
reset: in std_logic;
clk: in std_logic;
fin : out std_logic;
fin_coef: out std_logic_vector(15 downto 0);
salida: out std_logic_vector(49 downto 0));
end component reconocedor;
component expresion is
port(
clk: in std_logic;
salida_teclado: in std_logic_vector(49 downto 0);
addr : in std_logic_vector(7 downto 0);
do : out std_logic_vector(0 to 10)
);
end component;
component numero is
port(
clk: in std_logic;
s: in std_logic_vector(20 downto 0);
addr : in std_logic_vector(5 downto 0);
do : out std_logic_vector(0 to 9)
);
end component;
type ESTADOS is (S1, S2, S3); --ESTADOS DE LA PANTALLA
signal ESTADO, SIG_ESTADO: ESTADOS;
type ESTADOSG is (inicial, leer, calc, a_memoria, integrar1, integrar2); --ESTADOS DEL CONTROLADOR PRINCIPAL
signal estadoGen, estadoGen_sig: ESTADOSG;
-- En la representación en coma fija
-- DEC es el número de bits reservados a la parte decimal (contando el signo, pues representamos en C2)
-- ENT es el número de bits reservados a la parte entera
constant ENT : integer := 11;
constant DEC : integer := 10;
constant nB : integer := 6; --nBits-1
constant nF : integer := 127; --nF-1
constant nC : integer := 255; --nC-1
constant hInf : integer := 63;
constant hSup : integer := hInf + nF + 2;
constant vInf : integer := 63;
constant vSup : integer := vInf + nC + 2;
constant numPuntos : integer := 2;
signal clock, reset: std_logic;
--Señales de la pantalla
signal hcnt, fila, filaExp: std_logic_vector(9 downto 0); -- horizontal pixel counter
signal vcnt, auxColumna: std_logic_vector(8 downto 0); -- vertical line counter
signal columna: std_logic_vector(6 downto 0);
signal data: std_logic_vector(0 to nF);
signal data_particular,data_particularExp, data_particularNum, we: std_logic;
signal addr1, addr2, puntos1X, puntos1Y, puntos2X, puntos2Y: std_logic_vector(6 downto 0);
signal di, do1, do2, vAux, v: std_logic_vector(0 to 127);
signal b, j, jAux, a, i, iAux: std_logic_vector(nB downto 0);
signal aj, bi, biAux, ajAux: std_logic_vector(11 downto 0);
signal pinta_funcion, pinta_ejes, pinta_fondo, pinta_expresion, pinta_expY, pinta_expB, pinta_num:std_logic;
signal addrExp: std_logic_vector(7 downto 0);
signal addrNum: std_logic_vector(5 downto 0);
signal doExp: std_logic_vector(0 to 10);
signal doNum: std_logic_vector(0 to 9);
signal dataExp, dataNum: std_logic_vector(0 to 15);
signal columnaExp, columnaNum: std_logic_vector(3 downto 0);
signal fin_coef: std_logic_vector(15 downto 0);
signal noPintes, noPintesAux: std_logic;
--señales del controlador principal
signal caso: std_logic_vector(1 downto 0);
signal salida_teclado: std_logic_vector(49 downto 0);
signal integral, solo_positivos, solo_positivosAux, fin_muestra, fin_teclado, ready_calculo, enable_muestra, retro_muestra, fin_puntos, enable_calculo, fin_pantalla,enable_pantalla, avanza_conv, inf, inf1, inf2, puntos_centrales, x1, x2, x3, x4, x5, xl: std_logic;
signal punto, s, limite1, limite1Aux, limite2, limite2Aux, valorIntegral, valorIntegralAux: std_logic_vector(DEC+ENT-1 downto 0);
signal numPuntos2 : std_logic_vector(6 downto 0);
signal count: std_logic_vector(3 downto 0);
signal indice: std_logic_vector(4 downto 0);
begin
calcExp: expresion port map (clock, salida_teclado, addrExp, doExp);
calInt: numero port map (clock, valorIntegral, addrNum,doNum);
muestra: puntos_muestra port map(caso, numPuntos2, enable_muestra, retro_muestra, clock, reset, fin_muestra, salida_teclado,punto, count);
calculador: calculo port map(reset, clock, enable_calculo,integral, punto, salida_teclado, s, ready_calculo);
--Por comodidad las componentes de los puntos están intercambiadas
conver: conversor port map(caso, numPuntos2, fin_pantalla, avanza_conv, s, reset, clock, puntos1Y, puntos1X, puntos2Y, puntos2X, enable_pantalla, fin_puntos, puntos_centrales,indice);
reco: reconocedor port map(ps2data, ps2clk, reset, clock, fin_teclado, fin_coef, salida_teclado);
divisor1: divisor port map (reset, clk, clock);
ram: rams_2p port map(clock, we, addr1, addr2, di, do1, do2);
--PANTALLA
reset<= resetN;
a<=puntos2Y-puntos1Y;
b<=puntos2X-puntos1X when puntos2X>puntos1X else
puntos1X-puntos2X;
auxColumna <= vcnt - (vInf+1);
columna<= auxColumna(nB+1 downto 1);
fila<= hcnt - (hInf+1);
addr2 <=fila(nB downto 0)+1;
data(0 to 127) <=do2;
data_particular <=data(conv_integer(columna));
columnaExp<= auxColumna(3 downto 0);
filaExp<= hcnt - (32);
addrExp <=filaExp(7 downto 0);
dataExp(0 to 10) <=doExp;
--Al resto de pos de dataExp le ponemos ceros
dataExp(11 to 15)<=(others=>'0');
data_particularExp <=dataExp(conv_integer(columnaExp));
columnaNum<= auxColumna(3 downto 0);
addrNum <=fila(5 downto 0);
dataNum(0 to 9) <=doNum;
--Al resto de pos de dataNum le ponemos ceros
dataNum(10 to 15)<=(others=>'0');
data_particularNum <=dataNum(conv_integer(columnaNum));
colorear: process(hcnt, vcnt, pinta_funcion, pinta_ejes, pinta_fondo, pinta_expresion, pinta_num, pinta_expY, pinta_expB)
begin
if pinta_num = '1' or pinta_expY ='1' then
rgb<="111111000";
elsif pinta_expB ='1' then
rgb<="001011110";
elsif pinta_expresion = '1' then
rgb<="111111111";
elsif pinta_funcion ='1' then
rgb<="111001011";
elsif pinta_ejes = '1' then
rgb<="000000100";
elsif pinta_fondo = '1' then
rgb<="111111111";
else rgb<="000000000";
end if;
end process colorear;
pintar_fondo: process(hcnt, vcnt)
begin
pinta_fondo<='0';
if hcnt > hInf and hcnt < hSup then
if vcnt > vInf and vcnt < vSup then
pinta_fondo<='1';
end if;
end if;
end process pintar_fondo;
pintar_ejes: process(hcnt, vcnt, solo_positivos)
begin
pinta_ejes<='0';
if hcnt > hInf and hcnt < hSup then
if vcnt > vInf and vcnt < vSup then
if (vcnt=192 or vcnt=193) then pinta_ejes <= '1';
elsif solo_positivos ='0' and hcnt=128 then pinta_ejes <= '1';
elsif solo_positivos ='1' and hcnt=(vInf+1) then pinta_ejes <= '1';
--escala horizontal
elsif vcnt =194 and hcnt(2 downto 0)="000" then pinta_ejes <='1';
--escala vertical
elsif solo_positivos ='0' and hcnt=129 and (vcnt(3 downto 0) ="0000" or vcnt(3 downto 0) ="0001") then pinta_ejes <='1';
elsif solo_positivos ='1' and hcnt=vInf+2 and (vcnt(3 downto 0) ="0000" or vcnt(3 downto 0) ="0001") then pinta_ejes <='1';
end if;
end if;
end if;
end process pintar_ejes;
pintar_funcion: process(hcnt, vcnt, data_particular, noPintes)
begin
pinta_funcion <= '0';
if hcnt > hInf and hcnt < hSup then
if vcnt > vInf and vcnt < vSup then
if data_particular='1' and noPintes = '1' then pinta_funcion <= '1';
end if;
end if;
end if;
end process pintar_funcion;
pintar_expresion: process(hcnt, vcnt, data_particularExp, fin_coef)
begin
pinta_expresion <= '0';
pinta_expB <='0';
pinta_expY <='0';
if vcnt > vSup +15 and vcnt < (vSup+11)+15 then
if (hcnt > 32 and hcnt < 42) then
if data_particularExp='1' and fin_coef(0) ='0' then pinta_expB <='1';
elsif data_particularExp='1' and fin_coef(0) ='1' then pinta_expY <='1';
end if;
elsif (hcnt > 53 and hcnt < 65) then
if data_particularExp='1' and fin_coef(1) ='0' then pinta_expB <='1';
elsif data_particularExp='1' and fin_coef(1) ='1' then pinta_expY <='1';
end if;
elsif (hcnt > 82 and hcnt < 94) then
if data_particularExp='1' and fin_coef(2) ='0' then pinta_expB <='1';
elsif data_particularExp='1' and fin_coef(2) ='1' then pinta_expY <='1';
end if;
elsif (hcnt > 111 and hcnt < 123) then
if data_particularExp='1' and fin_coef(3) ='0' then pinta_expB <='1';
elsif data_particularExp='1' and fin_coef(3) ='1' then pinta_expY <='1';
end if;
elsif (hcnt > 132 and hcnt < 144) then
if data_particularExp='1' and fin_coef(4) ='0' then pinta_expB <='1';
elsif data_particularExp='1' and fin_coef(4) ='1' then pinta_expY <='1';
end if;
elsif (hcnt > 153 and hcnt < 165) then
if data_particularExp='1' and fin_coef(5) ='0' then pinta_expB <='1';
elsif data_particularExp='1' and fin_coef(5) ='1' then pinta_expY <='1';
end if;
elsif (hcnt > 170 and hcnt <= 182) then
if data_particularExp='1' and fin_coef(6) ='0' then pinta_expB <='1';
elsif data_particularExp='1' and fin_coef(6) ='1' then pinta_expY <='1';
end if;
elsif (hcnt > 181 and hcnt < 193) then
if data_particularExp='1' and fin_coef(7) ='0' then pinta_expB <='1';
elsif data_particularExp='1' and fin_coef(7) ='1' then pinta_expY <='1';
end if;
elsif (hcnt > 202 and hcnt < 214) then
if data_particularExp='1' and fin_coef(8) ='0' then pinta_expB <='1';
elsif data_particularExp='1' and fin_coef(8) ='1' then pinta_expY <='1';
end if;
elsif (hcnt > 225 and hcnt < 237) then
if data_particularExp='1' and fin_coef(9) ='0' then pinta_expB <='1';
elsif data_particularExp='1' and fin_coef(9) ='1' then pinta_expY <='1';
end if;
elsif (hcnt >= 43 and hcnt <= 53) or (hcnt >= 65 and hcnt <= 82) or (hcnt >= 94 and hcnt <=111) or (hcnt >= 123 and hcnt <= 132) or (hcnt >= 144 and hcnt <=153) or (hcnt >= 165 and hcnt <=170) or (hcnt >= 193 and hcnt <=202)or (hcnt >= 214 and hcnt <=225) or (hcnt >= 237 and hcnt < 32+217)then
if data_particularExp='1' then pinta_expresion <= '1';
end if;
end if;
end if;
end process pintar_expresion;
pintar_integral: process(hcnt, vcnt, data_particularNum)
begin
pinta_num <= '0';
if hcnt > hInf and hcnt < hInf+64 then
if vcnt >= vInf -15 and vcnt < (vInf+10)-15 then
if data_particularNum='1' then pinta_num <= '1';
end if;
end if;
end if;
end process pintar_integral;
combinacional_pantalla: process(ESTADO, enable_pantalla, j, i, v, aj, bi, puntos1X, puntos1Y, puntos2X, puntos2Y, fin_puntos, vAux, inf, inf1, inf2, a, b,solo_positivos)
begin
di<=(others=>'0');
addr1<=(others=>'0');
biAux<=(others=>'0');
ajAux<=(others=>'0');
iAux<=(others=>'0');
jAux<=(others=>'0');
--vAux<=(others=>'0');
-- si lo pones por alguna razon deja de sintetizar, pero habria que ponerlo porque si no xilinx no
-- entiende las declaraciones parciales y pone latches
we<='0';
fin_pantalla<='0';
-- para quitar latches, cuando queramos usarlo lo pondremos explicitamente
case ESTADO is
when S1 =>
if inf = '0' then
di<=(others=>'0');
addr1<=(others=>'0');
biAux<=(others=>'0');
ajAux<=(others=>'0');
iAux<=(others=>'0');
jAux<=(others=>'0');
we<='0';
fin_pantalla<='1';
if fin_puntos = '1' then
vAux<= (others =>'0');
else
vAux<=v;
end if;
if enable_pantalla ='1' then
vAux(conv_integer(puntos1X))<= '1';
SIG_ESTADO <= S2;
else SIG_ESTADO <= S1;
end if;
else
if solo_positivos = '1' then
we <= '0';
fin_pantalla <= '0';
SIG_ESTADO <= S2;
iAux <= (others=>'0');
vAux<=(others=>'0');
else
we <= '1';
fin_pantalla <= '0';
if inf1 = '1' then --bit + sig bit + abajo
vAux(conv_integer(puntos1X) to 127) <= (others=>'1');
vAux(0 to conv_integer(puntos1X)-1) <= (others=>'0');
else
vAux(conv_integer(puntos1X)+1 to 127) <= (others=>'0');
vAux(0 to conv_integer(puntos1X)) <= (others=>'1');
end if;
di <= v or vAux;
addr1 <= puntos1Y;
iAux(nB downto 1) <= (others=>'0');
iAux(0) <= '1';
SIG_ESTADO <= S2;
end if;
end if;
when S2 =>
if inf = '0' then
fin_pantalla<='0';
ajAux<=aj;
biAux<=bi;
iAux<=i;
di<=(others=>'0');
addr1<=(others=>'0');
we<='0';
vAux <= v;
if a(nB downto 1) +aj <bi and j < b then
if puntos2X>puntos1X then
vAux(conv_integer(j+1+puntos1X))<= '1';
else
vAux(conv_integer(puntos1X-j-1))<= '1';
end if;
jAux<=j+1;
ajAux <= aj+a;
SIG_ESTADO <= S2;
else
di<=v;
we<='1';
addr1<=i+puntos1Y;
iAux <= i+1;
biAux <= bi+b;
jAux <= j;
vAux<=(others=>'0');
if i < a then
if a(nB downto 1) +aj >=bi+b then
if puntos2X>puntos1X then
vAux(conv_integer(j+puntos1X))<=v(conv_integer(j+puntos1X));
else
vAux(conv_integer(puntos1X-j))<= v(conv_integer(puntos1X-j));
end if;
end if;
SIG_ESTADO <= S2;
else
SIG_ESTADO <= S1;
vAux<=v;
end if;
end if;
else
we <= '1';
fin_pantalla <= '0';
di <= (others=>'0');
addr1 <= puntos1Y+i;
iAux <= i+1;
vAux <= (others=>'0');
if puntos1Y+iAux = puntos2Y then
SIG_ESTADO <= S3;
else
SIG_ESTADO <= S2;
end if;
end if;
when S3 =>
we <= '1';
fin_pantalla <= '1';
if inf2 = '1' then --bit + sig bit + abajo
vAux(conv_integer(puntos2X) to 127) <= (others=>'1');
vAux(0 to conv_integer(puntos2X)-1) <= (others=>'0');
else
vAux(conv_integer(puntos2X)+1 to 127) <= (others=>'0');
vAux(0 to conv_integer(puntos2X)) <= (others=>'1');
end if;
di <= vAux;
addr1 <= puntos2Y;
iAux <= (others=>'0');
SIG_ESTADO <= S1;
end case;
end process combinacional_pantalla;
sincrono: process(clock, reset)
begin
-- Reset asincrono
if reset = '1' then
ESTADO <= S1;
elsif clock'event and clock = '1' then
ESTADO <= SIG_ESTADO;
end if;
end process sincrono;
registros_clock: process(vAux, clock, reset, jAux, iAux, ajAux, biAux, noPintesAux)
begin
if reset = '1' then
v<=(others=>'0');
j<=(others=>'0');
i<=(others=>'0');
aj<=(others =>'0');
bi<=(others =>'0');
noPintes <='0';
elsif clock'event and clock='1' then
v<=vAux;
j<=jAux;
i<=iAux;
aj<=ajAux;
bi<=biAux;
noPintes <=noPintesAux;
end if;
end process registros_clock;
pA: process(clock,reset)
begin
-- reset asynchronously clears pixel counter
if reset='1' then
hcnt <= "0000000000";
-- horiz. pixel counter increments on rising edge of dot clock
elsif (clock'event and clock='1') then
-- horiz. pixel counter rolls-over after 381 pixels
if hcnt<380 then
hcnt <= hcnt + 1;
else
hcnt <= "0000000000";
end if;
end if;
end process pA;
pB: process(hsyncb,reset)
begin
-- reset asynchronously clears line counter
if reset='1' then
vcnt <= "000000000";
-- vert. line counter increments after every horiz. line
elsif (hsyncb'event and hsyncb='1') then
-- vert. line counter rolls-over after 528 lines
if vcnt<527 then
vcnt <= vcnt + 1;
else
vcnt <= "000000000";
end if;
end if;
end process pB;
C: process(clock,reset)
begin
-- reset asynchronously sets horizontal sync to inactive
if reset='1' then
hsyncb <= '1';
-- horizontal sync is recomputed on the rising edge of every dot clock
elsif (clock'event and clock='1') then
-- horiz. sync is low in this interval to signal start of a new line
if (hcnt>=291 and hcnt<337) then
hsyncb <= '0';
else
hsyncb <= '1';
end if;
end if;
end process;
D: process(hsyncb,reset)
begin
-- reset asynchronously sets vertical sync to inactive
if reset='1' then
vsyncb <= '1';
-- vertical sync is recomputed at the end of every line of pixels
elsif (hsyncb'event and hsyncb='1') then
-- vert. sync is low in this interval to signal start of a new frame
if (vcnt>=490 and vcnt<492) then
vsyncb <= '0';
else
vsyncb <= '1';
end if;
end if;
end process;
--CONTROLADOR PRINCIPAL
with salida_teclado(4 downto 0) select
x3 <= '0' when "00000",
'1' when others;
with salida_teclado(9 downto 5) select
x2 <= '0' when "00000",
'1' when others;
with salida_teclado(14 downto 10) select
x1 <= '0' when "00000",
'1' when others;
with salida_teclado(49 downto 45) select
xl <= '0' when "00000",
'1' when others;
x4 <= x1 or x2 or x3;
x5 <= x4 or xl;
inf <= puntos_centrales and x5;
--'0' es positivo, '1' es negativo
pinf1y2: process(salida_teclado, x1, x2, x3)
begin
if salida_teclado(4) = '1' then
inf1 <= '0';
inf2 <= '1';
elsif x3 = '1' then
inf1 <= '1';
inf2 <= '0';
elsif salida_teclado(9) = '1' then
inf1 <= '1';
inf2 <= '1';
elsif x2 = '1' then
inf1 <= '0';
inf2 <= '0';
elsif salida_teclado(14) = '1' then
inf1 <= '0';
inf2 <= '1';
elsif x1 = '1' then
inf1 <= '1';
inf2 <= '0';
elsif salida_teclado(49) = '1' then -- a partir de aqui el limite lo domina el logaritmo
inf1 <= '0'; -- para quitar latches
inf2 <= '0';
else -- o el caso de que no usemos los inf
inf1 <= '0'; -- para quitar latches
inf2 <= '1';
end if;
end process pinf1y2;
sincronoGen: process(clock, reset)
begin
if reset = '1' then
estadoGen <= inicial;
elsif clock'event and clock = '1' then
estadoGen <= estadoGen_sig;
end if;
end process sincronoGen;
--En función de si hay potencias negativas o solo evaluamos en puntos negativos (como en el caso del logaritmo
--elegimos un caso u otro: ver puntos_muestra.vhd y conversor.vhd)
p_numero: process(x4, solo_positivos)
begin
if solo_positivos = '0' then
caso <= "10";
numPuntos2 <= "0100000";
else
if x4 = '0' then
caso <= "00";
numPuntos2 <= "0100001";
else
caso <= "01";
numPuntos2 <= "0100000";
end if;
end if;
end process p_numero;
maquina_estadoGens: process(estadoGen, enable_muestra, enable_calculo, ready_calculo, fin_puntos, fin_teclado, fin_muestra, salida_teclado, solo_positivos, valorIntegral, limite1, limite2, noPintes, s)
begin
valorIntegralAux <= valorIntegral;
solo_positivosAux <= solo_positivos;
retro_muestra <= '0';
limite1Aux <= limite1;
limite2Aux <= limite2;
noPintesAux<=noPintes;
case estadoGen is
-- estadoGen de inicio
when inicial =>
integral <= '1';
enable_muestra <= '0'; -- Cuando está a 1, la salida devuelve el siguiente punto de muestra a ser evaluado.
enable_calculo <= '0';
avanza_conv <= '0'; -- Avanza el conversor al siguiente estadoGen. En cada estadoGen con el prefijo S, se guarda
-- cada punto obtenido de calculo.vhd, con el fin de aplicar la conversión a coordenadas
-- en memoria/pantalla.
solo_positivosAux <= solo_positivos;
estadoGen_sig <= leer;
-- Criterio de divergencia de la integral
if solo_positivos = '0' then
if salida_teclado(9 downto 5) /= "00000" then
if salida_teclado(9) = '0' then
valorIntegralAux <= "011111111111111111111";
else
valorIntegralAux <= "100000000000000000000";
end if;
else valorIntegralAux <= limite2 - limite1;
end if;
else
if salida_teclado(4 downto 0) /= "00000" then
if salida_teclado(4) = '0' then
valorIntegralAux <= "011111111111111111111";
else
valorIntegralAux <= "100000000000000000000";
end if;
elsif salida_teclado(9 downto 5) /= "00000" then
if salida_teclado(9) = '0' then
valorIntegralAux <= "011111111111111111111";
else
valorIntegralAux <= "100000000000000000000";
end if;
elsif salida_teclado(14 downto 10) /= "00000" then
if salida_teclado(14) = '0' then
valorIntegralAux <= "011111111111111111111";
else
valorIntegralAux <= "100000000000000000000";
end if;
else
valorIntegralAux <= limite2 - limite1;
end if;
end if;
when leer =>
integral <= '0';
enable_muestra <= '0';
enable_calculo <= '0';
avanza_conv <= '0';
if fin_teclado = '0' then
solo_positivosAux <= solo_positivos;
estadoGen_sig <= leer; -- fin_teclado indica el momento en el que salida_teclado tiene
else
estadoGen_sig <= calc; -- la información adecuada (los coeficientes del polinomio)
if salida_teclado(49 downto 45) = "00000" then
solo_positivosAux <= '0';
else solo_positivosAux <= '1';
end if;
avanza_conv <= '1';
end if;
-- calc: estadoGen de cálculo de la imagen de un punto muestra. Hay 14 puntos a calcular, por tanto antes de pasar al
-- siguiente estadoGen, a_memoria, volvemos a pasar 13 veces a este estadoGen (cuando ready_calculo = 1, por tanto, se ha
-- calculado la imagen del punto. En este caso, avanzamos el conversor y el módulo muestra)
when calc =>
integral <= '0';
solo_positivosAux <= solo_positivos;
avanza_conv <= '0';
enable_calculo <= '1';
if ready_calculo = '0' then
estadoGen_sig <= calc;
enable_muestra <= '0';
else enable_muestra <= '1';
avanza_conv <= '1';
if fin_muestra = '0' then
estadoGen_sig <= calc;
else
estadoGen_sig <= a_memoria;
end if;
end if;
-- estadoGen de transferencia a memoria/pantalla. En el módulo conversor, corresponde a los estadoGens con prefijo
when a_memoria =>
integral <= '0';
solo_positivosAux <= solo_positivos;
avanza_conv <= '0';
enable_muestra <= '0';
enable_calculo <= '0';
noPintesAux<='1';
if fin_puntos = '1' then
estadoGen_sig <= integrar1;
integral <= '1';
else
estadoGen_sig <= a_memoria;
end if;
when integrar1 =>
integral <= '1';
solo_positivosAux <= solo_positivos;
avanza_conv <= '0';
enable_calculo <= '1';
enable_muestra <= '0';
if ready_calculo = '0' then
estadoGen_sig <= integrar1;
else retro_muestra <= '1';
estadoGen_sig <= integrar2;
limite1Aux <= s;
end if;
when integrar2 =>
integral <= '1';
solo_positivosAux <= solo_positivos;
avanza_conv <= '0';
enable_calculo <= '1';
enable_muestra <= '0';
retro_muestra <= '0';
if ready_calculo = '0' then
estadoGen_sig <= integrar2;
else enable_muestra <= '1';
estadoGen_sig <= inicial;
limite2Aux <= s;
end if;
end case;
end process maquina_estadoGens;
fin_principal <= fin_puntos;
escalay <= indice;
with count select
escalax <= "11101101" when "1011",
"11100110" when "1100",
"11001111" when "1101",
"11011011" when "1110",
"10000110" when "1111",
"00111111" when "0000",
"00000110" when "0001",
"11111111" when others;
registros_controlador: process (clock, estadoGen, solo_positivosAux, limite1Aux, limite2Aux, valorIntegralAux, reset)
begin
if reset = '1' then
valorIntegral <= (others => '0');
solo_positivos <= '0';
limite1 <= (others => '0');
limite2 <= (others => '0');
elsif clock'event and clock = '1' then
solo_positivos <= solo_positivosAux;
limite1 <= limite1Aux;
limite2 <= limite2Aux;
valorIntegral <= valorIntegralAux;
end if;
end process registros_controlador;
end project_arch; | gpl-3.0 | 3f530e10eaad9507be15f9b77836276c | 0.636523 | 3.064597 | false | false | false | false |
TUM-LIS/faultify | hardware/testcases/fpu100_mul/fpga_sim/xpsLibraryPath_asic/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/vhdl/user_logic.vhd | 1 | 29,249 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Fri May 16 15:25:24 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
faultify_clk_fast : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
component faultify_top
generic (
numInj : integer;
numIn : integer;
numOut : integer);
port (
aclk : in std_logic;
arst_n : in std_logic;
clk : in std_logic;
clk_x32 : in std_logic;
awvalid : in std_logic;
awaddr : in std_logic_vector(31 downto 0);
wvalid : in std_logic;
wdata : in std_logic_vector(31 downto 0);
arvalid : in std_logic;
araddr : in std_logic_vector(31 downto 0);
rvalid : out std_logic;
rdata : out std_logic_vector(31 downto 0));
end component;
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal register_write_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal register_read_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal register_write_address : std_logic_vector(C_NUM_REG-1 downto 0);
signal register_read_address : std_logic_vector(C_NUM_REG-1 downto 0);
signal slv_reg_write_sel : std_logic_vector(31 downto 0);
signal slv_reg_read_sel : std_logic_vector(31 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal faultify_read_valid : std_logic;
signal faultify_read_address_valid : std_logic;
signal faultify_read_address : std_logic_vector(31 downto 0);
signal faultify_write_valid : std_logic;
signal counter, divide : integer := 0;
signal faultify_clk_slow_i : std_logic;
begin
slv_reg_write_sel <= Bus2IP_WrCE(31 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(31 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12) or Bus2IP_WrCE(13) or Bus2IP_WrCE(14) or Bus2IP_WrCE(15) or Bus2IP_WrCE(16) or Bus2IP_WrCE(17) or Bus2IP_WrCE(18) or Bus2IP_WrCE(19) or Bus2IP_WrCE(20) or Bus2IP_WrCE(21) or Bus2IP_WrCE(22) or Bus2IP_WrCE(23) or Bus2IP_WrCE(24) or Bus2IP_WrCE(25) or Bus2IP_WrCE(26) or Bus2IP_WrCE(27) or Bus2IP_WrCE(28) or Bus2IP_WrCE(29) or Bus2IP_WrCE(30) or Bus2IP_WrCE(31);
slv_read_ack <= faultify_read_valid;
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process(Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
register_write_data <= (others => '0');
register_write_address <= (others => '0');
faultify_write_valid <= '0';
else
faultify_write_valid <= slv_write_ack;
case slv_reg_write_sel is
when "10000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(0, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "01000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(1, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00100000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(2, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00010000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(3, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00001000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(4, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000100000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(5, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000010000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(6, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000001000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(7, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000100000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(8, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000010000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(9, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000001000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(10, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000100000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(11, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000010000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(12, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000001000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(13, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000100000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(14, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000010000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(15, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000001000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(16, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000100000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(17, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000010000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(18, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000001000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(19, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000100000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(20, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000010000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(21, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000001000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(22, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000100000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(23, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000010000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(24, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000001000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(25, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(26, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(27, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(28, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(29, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(30, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(31, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process(slv_reg_read_sel, faultify_read_valid) is
begin
faultify_read_address_valid <= '1';
case slv_reg_read_sel is
when "10000000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(0, 32));
when "01000000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(1, 32));
when "00100000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(2, 32));
when "00010000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(3, 32));
when "00001000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(4, 32));
when "00000100000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(5, 32));
when "00000010000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(6, 32));
when "00000001000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(7, 32));
when "00000000100000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(8, 32));
when "00000000010000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(9, 32));
when "00000000001000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(10, 32));
when "00000000000100000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(11, 32));
when "00000000000010000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(12, 32));
when "00000000000001000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(13, 32));
when "00000000000000100000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(14, 32));
when "00000000000000010000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(15, 32));
when "00000000000000001000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(16, 32));
when "00000000000000000100000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(17, 32));
when "00000000000000000010000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(18, 32));
when "00000000000000000001000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(19, 32));
when "00000000000000000000100000000000" => faultify_read_address <= std_logic_vector(to_unsigned(20, 32));
when "00000000000000000000010000000000" => faultify_read_address <= std_logic_vector(to_unsigned(21, 32));
when "00000000000000000000001000000000" => faultify_read_address <= std_logic_vector(to_unsigned(22, 32));
when "00000000000000000000000100000000" => faultify_read_address <= std_logic_vector(to_unsigned(23, 32));
when "00000000000000000000000010000000" => faultify_read_address <= std_logic_vector(to_unsigned(24, 32));
when "00000000000000000000000001000000" => faultify_read_address <= std_logic_vector(to_unsigned(25, 32));
when "00000000000000000000000000100000" => faultify_read_address <= std_logic_vector(to_unsigned(26, 32));
when "00000000000000000000000000010000" => faultify_read_address <= std_logic_vector(to_unsigned(27, 32));
when "00000000000000000000000000001000" => faultify_read_address <= std_logic_vector(to_unsigned(28, 32));
when "00000000000000000000000000000100" => faultify_read_address <= std_logic_vector(to_unsigned(29, 32));
when "00000000000000000000000000000010" => faultify_read_address <= std_logic_vector(to_unsigned(30, 32));
when "00000000000000000000000000000001" => faultify_read_address <= std_logic_vector(to_unsigned(31, 32));
when others => faultify_read_address <= (others => '0');
faultify_read_address_valid <= '0';
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= register_read_data when faultify_read_valid = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
-----------------------------------------------------------------------------
-- clock divider 32 -> 1
-----------------------------------------------------------------------------
divide <= 32;
process(Bus2IP_Clk, Bus2IP_Resetn)
begin
if Bus2IP_Resetn = '0' then
counter <= 0;
faultify_clk_slow_i <= '0';
elsif(rising_edge(Bus2IP_Clk)) then
if(counter < divide/2-1) then
counter <= counter + 1;
faultify_clk_slow_i <= '0';
elsif(counter < divide-1) then
counter <= counter + 1;
faultify_clk_slow_i <= '1';
else
faultify_clk_slow_i <= '0';
counter <= 0;
end if;
end if;
end process;
faultify_top_1 : faultify_top
generic map (
numInj => 300, --631
numIn => 70,
numOut => 41)
port map (
aclk => Bus2IP_Clk,
arst_n => Bus2IP_Resetn,
clk => faultify_clk_slow_i,
clk_x32 => Bus2IP_Clk,
awvalid => faultify_write_valid,
awaddr => register_write_address,
wvalid => faultify_write_valid,
wdata => register_write_data,
arvalid => faultify_read_address_valid,
araddr => faultify_read_address,
rvalid => faultify_read_valid,
rdata => register_read_data);
end IMP;
| gpl-2.0 | c8520e2df91ed2dd584c525cf969ea9e | 0.5393 | 4.022693 | false | false | false | false |
bruskajp/EE-316 | Project2/Quartus_DE2Board/DE2.vhd | 1 | 9,506 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY DE2 IS
PORT (
-- Clock Input
CLOCK_27 : IN STD_LOGIC; -- On Board 27 MHz
CLOCK_50 : IN STD_LOGIC; -- On Board 50 MHz
EXT_CLOCK : IN STD_LOGIC; -- External Clock
-- Push Button
KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- Pushbutton[3:0]
-- DPDT Switch
SW : IN STD_LOGIC_VECTOR(17 DOWNTO 0); -- Toggle Switch[17:0]
-- 7-SEG Dispaly
HEX0 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); -- Seven Segment Digit 0
HEX1 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); -- Seven Segment Digit 1
HEX2 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); -- Seven Segment Digit 2
HEX3 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); -- Seven Segment Digit 3
HEX4 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); -- Seven Segment Digit 4
HEX5 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); -- Seven Segment Digit 5
HEX6 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); -- Seven Segment Digit 6
HEX7 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); -- Seven Segment Digit 7
-- LED
LEDG : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); -- LED Green[8:0]
LEDR : OUT STD_LOGIC_VECTOR(17 DOWNTO 0); -- LED Red[17:0]
-- UART
UART_TXD : OUT STD_LOGIC; -- UART Transmitter
UART_RXD : IN STD_LOGIC; -- UART Receiver
-- IRDA
-- IRDA_TXD : OUT STD_LOGIC; -- IRDA Transmitter
-- IRDA_RXD : IN STD_LOGIC; -- IRDA Receiver
-- SDRAM Interface
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- SDRAM Data bus 16 Bits
DRAM_ADDR : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); -- SDRAM Address bus 12 Bits
DRAM_LDQM : OUT STD_LOGIC; -- SDRAM Low-byte Data Mask
DRAM_UDQM : OUT STD_LOGIC; -- SDRAM High-byte Data Mask
DRAM_WE_N : OUT STD_LOGIC; -- SDRAM Write Enable
DRAM_CAS_N : OUT STD_LOGIC; -- SDRAM Column Address Strobe
DRAM_RAS_N : OUT STD_LOGIC; -- SDRAM Row Address Strobe
DRAM_CS_N : OUT STD_LOGIC; -- SDRAM Chip Select
DRAM_BA_0 : OUT STD_LOGIC; -- SDRAM Bank Address 0
DRAM_BA_1 : OUT STD_LOGIC; -- SDRAM Bank Address 1
DRAM_CLK : OUT STD_LOGIC; -- SDRAM Clock
DRAM_CKE : OUT STD_LOGIC; -- SDRAM Clock Enable
-- Flash Interface
FL_DQ : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- FLASH Data bus 8 Bits
FL_ADDR : OUT STD_LOGIC_VECTOR(21 DOWNTO 0); -- FLASH Address bus 20 Bits
FL_WE_N : OUT STD_LOGIC; -- FLASH Write Enable
FL_RST_N : OUT STD_LOGIC; -- FLASH Reset
FL_OE_N : OUT STD_LOGIC; -- FLASH Output Enable
FL_CE_N : OUT STD_LOGIC; -- FLASH Chip Enable
-- SRAM Interface
SRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- SRAM Data bus 16 Bits
SRAM_ADDR : OUT STD_LOGIC_VECTOR(17 DOWNTO 0); -- SRAM Address bus 18 Bits
SRAM_UB_N : OUT STD_LOGIC; -- SRAM High-byte Data Mask
SRAM_LB_N : OUT STD_LOGIC; -- SRAM Low-byte Data Mask
SRAM_WE_N : OUT STD_LOGIC; -- SRAM Write Enable
SRAM_CE_N : OUT STD_LOGIC; -- SRAM Chip Enable
SRAM_OE_N : OUT STD_LOGIC; -- SRAM Output Enable
-- ISP1362 Interface
OTG_DATA : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- ISP1362 Data bus 16 Bits
OTG_ADDR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- ISP1362 Address 2 Bits
OTG_CS_N : OUT STD_LOGIC; -- ISP1362 Chip Select
OTG_RD_N : OUT STD_LOGIC; -- ISP1362 Read
OTG_WR_N : OUT STD_LOGIC; -- ISP1362 Write
OTG_RST_N : OUT STD_LOGIC; -- ISP1362 Reset
OTG_FSPEED : OUT STD_LOGIC; -- USB Full Speed, 0 = Enable, Z = Disable
OTG_LSPEED : OUT STD_LOGIC; -- USB Low Speed, 0 = Enable, Z = Disable
OTG_INT0 : IN STD_LOGIC; -- ISP1362 Interrupt 0
OTG_INT1 : IN STD_LOGIC; -- ISP1362 Interrupt 1
OTG_DREQ0 : IN STD_LOGIC; -- ISP1362 DMA Request 0
OTG_DREQ1 : IN STD_LOGIC; -- ISP1362 DMA Request 1
OTG_DACK0_N : OUT STD_LOGIC; -- ISP1362 DMA Acknowledge 0
OTG_DACK1_N : OUT STD_LOGIC; -- ISP1362 DMA Acknowledge 1
-- LCD Module 16X2
LCD_ON : OUT STD_LOGIC; -- LCD Power ON/OFF
LCD_BLON : OUT STD_LOGIC; -- LCD Back Light ON/OFF
LCD_RW : OUT STD_LOGIC; -- LCD Read/Write Select, 0 = Write, 1 = Read
LCD_EN : OUT STD_LOGIC; -- LCD Enable
LCD_RS : OUT STD_LOGIC; -- LCD Command/Data Select, 0 = Command, 1 = Data
LCD_DATA : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- LCD Data bus 8 bits
-- SD_Card Interface
SD_DAT : INOUT STD_LOGIC; -- SD Card Data
SD_DAT3 : INOUT STD_LOGIC; -- SD Card Data 3
SD_CMD : INOUT STD_LOGIC; -- SD Card Command Signal
SD_CLK : OUT STD_LOGIC; -- SD Card Clock
-- USB JTAG link
TDI : IN STD_LOGIC; -- CPLD -> FPGA (Data in)
TCK : IN STD_LOGIC; -- CPLD -> FPGA (Clock)
TCS : IN STD_LOGIC; -- CPLD -> FPGA (CS)
TDO : OUT STD_LOGIC; -- FPGA -> CPLD (Data out)
-- I2C
I2C_SDAT : INOUT STD_LOGIC; -- I2C Data
I2C_SCLK : OUT STD_LOGIC; -- I2C Clock
-- PS2
PS2_DAT : IN STD_LOGIC; -- PS2 Data
PS2_CLK : IN STD_LOGIC; -- PS2 Clock
-- VGA
VGA_CLK : OUT STD_LOGIC; -- VGA Clock
VGA_HS : OUT STD_LOGIC; -- VGA H_SYNC
VGA_VS : OUT STD_LOGIC; -- VGA V_SYNC
VGA_BLANK : OUT STD_LOGIC; -- VGA BLANK
VGA_SYNC : OUT STD_LOGIC; -- VGA SYNC
VGA_R : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); -- VGA Red[9:0]
VGA_G : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); -- VGA Green[9:0]
VGA_B : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); -- VGA Blue[9:0]
-- Ethernet Interface
ENET_DATA : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);-- DM9000A DATA bus 16Bits
ENET_CMD : OUT STD_LOGIC; -- DM9000A Command/Data Select, 0 = Command, 1 = Data
ENET_CS_N : OUT STD_LOGIC; -- DM9000A Chip Select
ENET_WR_N : OUT STD_LOGIC; -- DM9000A Write
ENET_RD_N : OUT STD_LOGIC; -- DM9000A Read
ENET_RST_N : OUT STD_LOGIC; -- DM9000A Reset
ENET_INT : IN STD_LOGIC; -- DM9000A Interrupt
ENET_CLK : OUT STD_LOGIC; -- DM9000A Clock 25 MHz
-- Audio CODEC
AUD_ADCLRCK : INOUT STD_LOGIC; -- Audio CODEC ADC LR Clock
AUD_ADCDAT : IN STD_LOGIC; -- Audio CODEC ADC Data
AUD_DACLRCK : INOUT STD_LOGIC; -- Audio CODEC DAC LR Clock
AUD_DACDAT : OUT STD_LOGIC; -- Audio CODEC DAC Data
AUD_BCLK : INOUT STD_LOGIC; -- Audio CODEC Bit-Stream Clock
AUD_XCK : OUT STD_LOGIC; -- Audio CODEC Chip Clock
-- TV Decoder
TD_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- TV Decoder Data bus 8 bits
TD_HS : IN STD_LOGIC; -- TV Decoder H_SYNC
TD_VS : IN STD_LOGIC; -- TV Decoder V_SYNC
TD_RESET : OUT STD_LOGIC; -- TV Decoder Reset
-- GPIO
GPIO_0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);-- GPIO Connection 0
GPIO_1 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0) -- GPIO Connection 1
);
END DE2;
ARCHITECTURE structural OF DE2 IS
component top_level is
generic (constant divisor : integer := 83333);
Port (
iClk : in std_logic;
iReset : in std_logic;
F_B : in std_logic;
E_D : in std_logic;
HEX0 : out std_logic_vector(6 downto 0);
HEX1 : out std_logic_vector(6 downto 0);
HEX2 : out std_logic_vector(6 downto 0);
HEX3 : out std_logic_vector(6 downto 0);
HEX4 : out std_logic_vector(6 downto 0);
HEX5 : out std_logic_vector(6 downto 0);
HEX6 : out std_logic_vector(6 downto 0);
HEX7 : out std_logic_vector(6 downto 0);
Tx : out std_logic;
MOSI : out std_logic;
CSN : out std_logic;
SCK : out std_logic;
sda : inout std_logic;
scl : inout std_logic
);
end component;
begin
Inst_top_level: top_level
generic map (divisor => 83333)
port map (
iClk => CLOCK_50,
iReset => not KEY(0),
F_B => not KEY(1),
E_D => not KEY(2),
HEX0 => HEX0,
HEX1 => HEX1,
HEX2 => HEX2,
HEX3 => HEX3,
HEX4 => HEX4,
HEX5 => HEX5,
HEX6 => HEX6,
HEX7 => HEX7,
Tx => GPIO_0(0),
MOSI => GPIO_0(1),
CSN => GPIO_0(2),
SCK => GPIO_0(3),
sda => GPIO_1(0),
scl => GPIO_1(1)
);
END structural;
| gpl-3.0 | f25c9950f673ef734f4d57846e0eeb97 | 0.503787 | 3.343651 | false | false | false | false |
Ana06/function-graphing-FPGA | conversor.vhd | 2 | 11,053 | ----------------------------------------------------------------------------------
-- Company: Nameless2
-- Engineer: Ana María Martínez Gómez, Aitor Alonso Lorenzo, Víctor Adolfo Gallego Alcalá
--
-- Create Date: 12:15:23 11/18/2013
-- Design Name:
-- Module Name: conversor - Behavioral
-- Project Name: Representación gráfica de funciones
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
entity conversor is
port( caso : in std_logic_vector(1 downto 0);
numPuntos : in std_logic_vector(6 downto 0);
fin_pantalla: in std_logic;
avanza: in std_logic;
punto: in std_logic_vector(20 downto 0);
reset, clk: in std_logic;
punto1X, punto2X, punto1Y, punto2Y: out std_logic_vector(6 downto 0);
enable_pantalla, fin_conv, inf: out std_logic;
indice_o: out std_logic_vector(4 downto 0)); -- Para mostrarlo en la barra de LEDs
end conversor;
architecture Behavioral of conversor is
constant ENT : integer := 11;
constant DEC : integer := 10;
constant nB: integer := 6;
type matrizPuntos is array(0 to 31) of std_logic_vector(31 downto 0);
signal puntos, puntosAux: matrizPuntos;
signal indice, indice3: std_logic_vector(4 downto 0);
signal salida1Y, salida2Y: std_logic_vector(6 downto 0);
signal estado, estado_sig: std_logic_vector(6 downto 0);
signal estado2, estado2_sig: std_logic_vector(1 downto 0);
signal vAcc, vAccAux: std_logic_vector(DEC+ENT-1 downto 6);
type matrizX is array(0 to 32) of std_logic_vector(6 downto 0);
signal puntos1X: matrizX;
type matrizX2 is array(0 to 31) of std_logic_vector(6 downto 0);
signal puntos2X, puntos3X : matrizX2;
begin
puntos1X(0) <= "0000000";
puntos1X(1) <= "0000100";
puntos1X(2) <= "0001000";
puntos1X(3) <= "0001100";
puntos1X(4) <= "0010000";
puntos1X(5) <= "0010100";
puntos1X(6) <= "0011000";
puntos1X(7) <= "0011100";
puntos1X(8) <= "0100000";
puntos1X(9) <= "0100100";
puntos1X(10) <= "0101000";
puntos1X(11) <= "0101100";
puntos1X(12) <= "0110000";
puntos1X(13) <= "0110100";
puntos1X(14) <= "0111000";
puntos1X(15) <= "0111100";
puntos1X(16) <= "1000000";
puntos1X(17) <= "1000100";
puntos1X(18) <= "1001000";
puntos1X(19) <= "1001100";
puntos1X(20) <= "1010000";
puntos1X(21) <= "1010100";
puntos1X(22) <= "1011000";
puntos1X(23) <= "1011100";
puntos1X(24) <= "1100000";
puntos1X(25) <= "1100100";
puntos1X(26) <= "1101000";
puntos1X(27) <= "1101100";
puntos1X(28) <= "1110000";
puntos1X(29) <= "1110100";
puntos1X(30) <= "1111000";
puntos1X(31) <= "1111100";
puntos1X(32) <= "1111111";
puntos2X(0) <= "0000000";
puntos2X(1) <= "0001000";
puntos2X(2) <= "0001100";
puntos2X(3) <= "0010000";
puntos2X(4) <= "0010100";
puntos2X(5) <= "0011000";
puntos2X(6) <= "0011100";
puntos2X(7) <= "0100000";
puntos2X(8) <= "0100100";
puntos2X(9) <= "0101000";
puntos2X(10) <= "0101100";
puntos2X(11) <= "0110000";
puntos2X(12) <= "0110100";
puntos2X(13) <= "0111000";
puntos2X(14) <= "0111100";
puntos2X(15) <= "1000000";
puntos2X(16) <= "1000100";
puntos2X(17) <= "1001000";
puntos2X(18) <= "1001100";
puntos2X(19) <= "1010000";
puntos2X(20) <= "1010100";
puntos2X(21) <= "1011000";
puntos2X(22) <= "1011100";
puntos2X(23) <= "1100000";
puntos2X(24) <= "1100100";
puntos2X(25) <= "1101000";
puntos2X(26) <= "1101100";
puntos2X(27) <= "1110000";
puntos2X(28) <= "1110100";
puntos2X(29) <= "1111000";
puntos2X(30) <= "1111100";
puntos2X(31) <= "1111111";
puntos3X(0) <= "0000000";
puntos3X(1) <= "0000100";
puntos3X(2) <= "0001000";
puntos3X(3) <= "0001100";
puntos3X(4) <= "0010000";
puntos3X(5) <= "0010100";
puntos3X(6) <= "0011000";
puntos3X(7) <= "0011100";
puntos3X(8) <= "0100000";
puntos3X(9) <= "0100100";
puntos3X(10) <= "0101000";
puntos3X(11) <= "0101100";
puntos3X(12) <= "0110000";
puntos3X(13) <= "0110100";
puntos3X(14) <= "0111000";
puntos3X(15) <= "0111100";
puntos3X(16) <= "1000100";
puntos3X(17) <= "1001000";
puntos3X(18) <= "1001100";
puntos3X(19) <= "1010000";
puntos3X(20) <= "1010100";
puntos3X(21) <= "1011000";
puntos3X(22) <= "1011100";
puntos3X(23) <= "1100000";
puntos3X(24) <= "1100100";
puntos3X(25) <= "1101000";
puntos3X(26) <= "1101100";
puntos3X(27) <= "1110000";
puntos3X(28) <= "1110100";
puntos3X(29) <= "1111000";
puntos3X(30) <= "1111100";
puntos3X(31) <= "1111111";
index: process(vAcc, estado2)
begin
-- En función del bit más significativo a 1 (permanece en todo a 1 tras realizar las or(ver el estado "10"), una posición a la izquierda
-- de ese bit será el índice. La conversión a coordenadas de pantalla consiste en, a partir de ese bit y hacia
-- la derecha, tomar 7 bits (un punto de la pantalla)
indice <= "00110";
bucle1: for i in 6 to 20 loop
if estado2 = "01" or estado2 = "10" or estado2 = "11" then
if vAcc(i) = '1' then
indice <= conv_std_logic_vector(i+1, 5);
end if;
end if;
end loop bucle1;
end process index;
sincrono: process(clk, reset, estado2_sig, estado_sig)
begin
if reset = '1' then
estado2 <= ( others => '0');
estado <= ( others => '0');
elsif clk'event and clk = '1' then
estado2 <= estado2_sig;
estado <= estado_sig;
end if;
end process sincrono;
maquina: process(estado2, fin_pantalla, punto, avanza, puntos, estado, vAcc, numPuntos, caso)
begin
inf <= '0';
puntosAux <= puntos;
vAccAux <= vAcc;
salida1Y <= (others=>'0');
salida2Y <= (others=>'0');
case estado2 is
-- Estado de inicio
when "00" =>
vAccAux <= (others => '0');
fin_conv <= '1';
enable_pantalla <= '0';
estado_sig <= estado;
if avanza = '1' then
estado2_sig <= "01";
else
estado2_sig <= "00";
end if;
-- Estado 01: de guardado de puntos. Se guardan en puntos, y vAcc (en este último, como valor absoluto,
-- con el fin de poder obtener el índice necesario realizar el reescalado a coordenadas de pantalla, basándonos
-- en realizar sucesivas OR lógicas con el fin de obtener el índice (factor para la escala vertical).
when "01" =>
fin_conv <= '0';
enable_pantalla <= '0';
if punto(20)='1' then
puntosAux(conv_integer(unsigned(estado))) <= "11111111111" & punto;
vAccAux <= vAcc or ("000000000000" - punto(DEC+ENT-1 downto 6));
else
vAccAux <= vAcc or punto(DEC+ENT-1 downto 6);
puntosAux(conv_integer(unsigned(estado))) <= "00000000000" & punto;
end if;
estado_sig <= estado;
if avanza ='1' then
if estado = numPuntos-1 then
estado2_sig <= "10";
estado_sig <= (others => '0');
else
estado_sig <= estado +1;
estado2_sig <= "01";
end if;
else
estado_sig <= estado;
estado2_sig <= estado2;
end if;
-- En el siguiente estado se manda un par de puntos a la pantalla. Los puntos han sigo guardados en los estados
-- anteriores, por tanto la señal indice tiene el valor correcto con el fin de tomar el subvector para realizar
-- el reescalado.
-- Debido a las características de la algoritmia de la pantalla, estado 10 y 11 son iguales, salvo que en el primero
-- únicamente estamos un ciclo con enable_pantalla a 1.
when "10" =>
if estado = "0000000" and caso(1)='0' then
inf <= '1';
elsif estado = numPuntos(6 downto 1) -1 and caso = "10" then
inf <= '1';
else
inf <= '0';
end if;
enable_pantalla <= '1';
fin_conv <= '0';
salida1Y <= puntos(conv_integer(unsigned(estado)))(conv_integer(unsigned(indice)) downto conv_integer(unsigned(indice))-6);
salida2Y <= puntos(conv_integer(unsigned(estado))+1)(conv_integer(unsigned(indice)) downto conv_integer(unsigned(indice))-6);
estado2_sig <= "11";
estado_sig <= estado;
when "11" =>
if estado = "0000000" and caso(1)='0' then
inf <= '1';
elsif estado = numPuntos(6 downto 1) -1 and caso = "10" then
inf <= '1';
else
inf <= '0';
end if;
fin_conv <= '0';
salida1Y <= puntos(conv_integer(unsigned(estado)))(conv_integer(unsigned(indice)) downto conv_integer(unsigned(indice))-6);
salida2Y <= puntos(conv_integer(unsigned(estado))+1)(conv_integer(unsigned(indice)) downto conv_integer(unsigned(indice))-6);
enable_pantalla <= '0';
if fin_pantalla = '1' then
if estado = numPuntos-2 then
estado_sig <= (others => '0');
estado2_sig <= "00";
else
estado_sig <= estado +1;
estado2_sig <= "10";
end if;
else
estado2_sig <= estado2;
estado_sig <= estado;
end if;
-- Una vez hemos obtenido el subvector de longitud 7 usando el indice, hacemos 64 - eso, con el fin
-- de ajustar a las coordenadas en la pantalla.
--Ejemplo: las coordenadas verticales de la pantalla son de esta manera
--
-- 0 (lim. sup)
--
--
-- 64 (eje horizontal)
--
--
-- 127 (lim.inf).
-- Así, si por ejemplo tenemos los f(x) = 2, f(y) = 3, al tomar con el índice teniendo en cuenta las
-- or anteriores quedarían 0100000 (=32) (para el 2) y 0110000 (=48) (para el 3). Realizando 64 - lo anterior, quedarían
-- las coordenadas 32 y 16, respectivamente. De forma similar, si f(x) fuera negativo, su coordenada sería mayor
-- que 64, quedando por debajo del eje horizontal.
when others =>
end case;
end process maquina;
process(clk)
begin
if clk'event and clk = '1' then
if estado2 = "11" then
indice3 <= indice;
else
indice3 <= indice3;
end if;
end if;
end process;
p_outX: process(puntos1X, puntos2X, estado, estado2, caso, puntos3X)
begin
if estado2 = "10" or estado2 = "11" then
if caso = "00" then
punto1X <= puntos1X(conv_integer(unsigned(estado)));
punto2X <= puntos1X(conv_integer(unsigned(estado))+1);
elsif caso = "01" then
punto1X <= puntos2X(conv_integer(unsigned(estado)));
punto2X <= puntos2X(conv_integer(unsigned(estado))+1);
else
punto1X <= puntos3X(conv_integer(unsigned(estado)));
punto2X <= puntos3X(conv_integer(unsigned(estado))+1);
end if;
else
punto1X <= (others => '1');
punto2X <= (others => '1');
end if;
end process p_outX;
registros: process (clk, reset, vAccAux, puntosAux, estado2_sig, estado_sig)
begin
if reset = '1' then
puntos <= (others => "00000000000000000000000000000000");
vAcc <= (others => '0');
estado2 <= (others => '0');
estado <= (others => '0');
elsif clk'event and clk = '1' then
puntos <= puntosAux;
vAcc <= vAccAux;
estado <= estado_sig;
estado2 <= estado2_sig;
end if;
end process registros;
punto1Y <= 64 - salida1Y;
punto2Y <= 64 - salida2Y;
-- Escala y: 1 unidad equivale a 2^(indice-13), por lo que indice_o representará este exponente
indice_o <= unsigned(indice3)-13 ;
end Behavioral;
| gpl-3.0 | 71038b79d96e14e18308a182d9f21b6f | 0.622908 | 2.876887 | false | false | false | false |
SoCdesign/EHA | RTL/Immortal_Chip/modules_with_fault_injectors/FIFO_one_hot_with_checkers.vhd | 1 | 8,591 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.math_real."ceil";
use IEEE.math_real."log2";
entity FIFO is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
DRTS: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
CTS: out std_logic;
empty_out: out std_logic;
read_pointer_out, write_pointer_out: out std_logic_vector(3 downto 0);
write_en_out :out std_logic;
-- fault injector signals
shift: in std_logic;
fault_clk: in std_logic;
data_in_serial: in std_logic;
data_out_serial: out std_logic;
-- Checker outputs
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
--err_CTS_in,
err_write_en,
err_not_CTS_in,
--err_not_write_en,
err_read_en_mismatch : out std_logic
);
end FIFO;
architecture behavior of FIFO is
signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(3 downto 0);
signal full, empty: std_logic;
signal read_en, write_en: std_logic;
signal CTS_in, CTS_out: std_logic;
component FIFO_control_part_checkers is
port ( DRTS: in std_logic;
CTS_out: in std_logic;
CTS_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
read_pointer_in: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
write_pointer_in: in std_logic_vector(3 downto 0);
empty_out: in std_logic;
full_out: in std_logic;
read_en_out: in std_logic;
write_en_out: in std_logic;
-- Checker outputs
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
--err_CTS_in,
err_write_en,
err_not_CTS_in,
--err_not_write_en,
err_read_en_mismatch : out std_logic
);
end component;
component fault_injector is
generic(DATA_WIDTH : integer := 32);
port(
data_in: in std_logic_vector (DATA_WIDTH-1 downto 0);
address: in std_logic_vector(integer(ceil(log2(real(DATA_WIDTH))))-1 downto 0);
sta_0: in std_logic;
sta_1: in std_logic;
data_out: out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end component;
component shift_register_serial_in is
generic (
REG_WIDTH: integer := 8
);
port (
clk, reset : in std_logic;
shift: in std_logic;
data_in_serial: in std_logic;
data_out_parallel: out std_logic_vector(REG_WIDTH-1 downto 0);
data_out_serial: out std_logic
);
end component;
signal FI_add_sta: std_logic_vector(?? downto 0);
begin
FI: fault_injector generic map(DATA_WIDTH => ??)
port map (data_in=> ?? , address=> FI_add_sta(?? downto 2), sta_0=> FI_add_sta(1), sta_1=> FI_add_sta(0), data_out=>??
);
SR: shift_register_serial_in generic map(REG_WIDTH => )
port map( clk=> fault_clk, reset=>reset, shift=> shift,data_in_serial=> data_in_serial,
data_out_parallel=> FI_add_sta, data_out_serial=> data_out_serial
);
-- FIFO Control Part checkers instantiation
FIFOCONTROLPARTCHECKERS: FIFO_control_part_checkers port map (
DRTS => DRTS,
CTS_out => CTS_out, CTS_in => CTS_in,
read_en_N => read_en_N, read_en_E => read_en_E, read_en_W => read_en_W, read_en_S => read_en_S, read_en_L => read_en_L,
read_pointer => read_pointer, read_pointer_in => read_pointer_in,
write_pointer => write_pointer, write_pointer_in => write_pointer_in,
empty_out => empty, full_out => full,
read_en_out => read_en, write_en_out => write_en,
err_write_en_write_pointer => err_write_en_write_pointer,
err_not_write_en_write_pointer => err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => err_read_pointer_write_pointer_full,
err_read_pointer_increment => err_read_pointer_increment,
err_read_pointer_not_increment => err_read_pointer_not_increment,
err_write_en => err_write_en,
err_not_CTS_in => err_not_CTS_in,
err_read_en_mismatch => err_read_en_mismatch
);
process (clk, reset)begin
if reset = '0' then
read_pointer <= "0001";
write_pointer <= "0001";
CTS_out<='0';
elsif clk'event and clk = '1' then
write_pointer <= write_pointer_in;
read_pointer <= read_pointer_in;
CTS_out<=CTS_in;
end if;
end process;
-- anything below here is pure combinational
-- combinatorial part
write_pointer_out <= write_pointer;
read_pointer_out <= read_pointer;
write_en_out <= write_en;
read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty;
empty_out <= empty;
CTS <= CTS_out;
process(write_en, write_pointer)begin
if write_en = '1'then
write_pointer_in <= write_pointer(2 downto 0)&write_pointer(3);
else
write_pointer_in <= write_pointer;
end if;
end process;
process(read_en, empty, read_pointer)begin
if (read_en = '1' and empty = '0') then
read_pointer_in <= read_pointer(2 downto 0)&read_pointer(3);
else
read_pointer_in <= read_pointer;
end if;
end process;
process(full, DRTS, CTS_out) begin
if CTS_out = '0' and DRTS = '1' and full ='0' then
CTS_in <= '1';
write_en <= '1';
else
CTS_in <= '0';
write_en <= '0';
end if;
end process;
process(write_pointer, read_pointer) begin
if read_pointer = write_pointer then
empty <= '1';
else
empty <= '0';
end if;
-- if write_pointer = read_pointer>>1 then
if write_pointer = read_pointer(0)&read_pointer(3 downto 1) then
full <= '1';
else
full <= '0';
end if;
end process;
end;
| gpl-3.0 | a7ad3cde88ed99efc1ec5b616ebcfbca | 0.497963 | 3.922831 | false | false | false | false |
bruskajp/EE-316 | Project1/input_handler.vhd | 1 | 3,328 | -- Author: Zander Blasingame
-- Class: EE 316 Spring 2017
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity input_handler is
generic (
COUNT_MAX : integer := 250000
);
port (
row_sel : in std_logic_vector(4 downto 0);
clk : in std_logic;
reset : in std_logic;
key_out : out std_logic_vector(7 downto 0);
col_sel : out std_logic_vector(3 downto 0);
keypress_out : out std_logic
);
end input_handler;
architecture input_handler of input_handler is
signal counter : integer range 0 to COUNT_MAX - 1 := 0;
signal clk_en : std_logic := '0';
signal keypress : std_logic := '0';
signal buf_col_sel : std_logic_vector(3 downto 0);
signal rev_row_sel : std_logic_vector(4 downto 0);
signal rev_col_sel : std_logic_vector(3 downto 0);
signal internal_state_sel : integer range 0 to 3 := 0;
signal key_address : std_logic_vector(8 downto 0);
begin
-- Clock Enabler
process(clk, reset)
begin
if reset = '1' then
counter <= 0;
elsif rising_edge(clk) then
if counter < COUNT_MAX then
counter <= counter + 1;
clk_en <= '0';
else
counter <= 0;
clk_en <= '1';
end if;
end if;
end process;
-- col_sel selection clock
process(clk, clk_en, reset, keypress)
begin
if reset = '1' then
internal_state_sel <= 0;
elsif rising_edge(clk) and keypress = '0' and clk_en = '1' then
if internal_state_sel < 3 then
internal_state_sel <= internal_state_sel + 1;
else
internal_state_sel <= 0;
end if;
end if;
end process;
-- Keypress
process(row_sel, clk, clk_en, reset, keypress)
begin
if reset = '1' then
keypress <= '0';
else
keypress <= not(row_sel(4) and row_sel(3) and row_sel(2)
and row_sel(1) and row_sel(0));
end if;
keypress_out <= keypress;
end process;
-- Mux for col_sel
process(internal_state_sel, buf_col_sel)
begin
case internal_state_sel is
when 0 => buf_col_sel <= "0111";
when 1 => buf_col_sel <= "1011";
when 2 => buf_col_sel <= "1101";
when 3 => buf_col_sel <= "1110";
when others => buf_col_sel <= "1111";
end case;
col_sel <= buf_col_sel;
end process;
-- LUT selection
process(row_sel, buf_col_sel, key_address)
begin
key_address <= buf_col_sel & row_sel;
case key_address is
when "111011110" => key_out <= x"0A";
when "110111110" => key_out <= x"0B";
when "101111110" => key_out <= x"0C";
when "011111110" => key_out <= x"0D";
when "111011101" => key_out <= x"01";
when "110111101" => key_out <= x"02";
when "101111101" => key_out <= x"03";
when "011111101" => key_out <= x"0E";
when "111011011" => key_out <= x"04";
when "110111011" => key_out <= x"05";
when "101111011" => key_out <= x"06";
when "011111011" => key_out <= x"0F";
when "111010111" => key_out <= x"07";
when "110110111" => key_out <= x"08";
when "101110111" => key_out <= x"09";
when "011110111" => key_out <= x"F0"; -- Shift
when "110101111" => key_out <= x"00";
when "101101111" => key_out <= x"F1"; -- H
when "011101111" => key_out <= x"F2"; -- L
when others => key_out <= x"FF"; -- Error code
end case;
end process;
end input_handler;
| gpl-3.0 | 5686909aee90a1fc1fdd0cb8e04d367c | 0.580228 | 2.827528 | false | false | false | false |
SoCdesign/EHA | RTL/Fault_Management/Fault_management_network/TB_Package_LV_CB_multi_flit.vhd | 1 | 9,283 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_misc.all;
package TB_Package is
function Header_gen(Packet_length, source, destination, packet_id: integer ) return std_logic_vector ;
function Body_gen(Packet_length, Data: integer ) return std_logic_vector ;
function Tail_gen(Packet_length, Data: integer ) return std_logic_vector ;
procedure credit_counter_control(signal clk: in std_logic;
signal credit_in: in std_logic; signal valid_out: in std_logic;
signal credit_counter_out: out std_logic_vector(1 downto 0));
procedure gen_random_packet(SHMU_ID, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector);
procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal credit_out: out std_logic; signal valid_in: in std_logic; signal port_in: in std_logic_vector);
end TB_Package;
package body TB_Package is
constant Header_type : std_logic_vector := "001";
constant Body_type : std_logic_vector := "010";
constant Tail_type : std_logic_vector := "100";
function Header_gen(Packet_length, source, destination, packet_id: integer)
return std_logic_vector is
variable Header_flit: std_logic_vector (10 downto 0);
variable faulty_healhty: integer;
variable seed1 :positive ;
variable seed2 :positive ;
variable rand : real ;
begin
uniform(seed1, seed2, rand);
faulty_healhty := integer(rand*100.0);
if faulty_healhty > 50 then
Header_flit := std_logic_vector(to_unsigned(source, 4)) & std_logic_vector(to_unsigned(destination, 4)) & Header_type;
else
Header_flit := std_logic_vector(to_unsigned(source, 4)) & std_logic_vector(to_unsigned(destination, 4)) & Header_type;
end if;
return Header_flit;
end Header_gen;
function Body_gen(Packet_length, Data: integer)
return std_logic_vector is
variable Body_flit: std_logic_vector (10 downto 0);
begin
Body_flit := std_logic_vector(to_unsigned(Data, 8)) & Body_type;
return Body_flit;
end Body_gen;
function Tail_gen(Packet_length, Data: integer)
return std_logic_vector is
variable Tail_flit: std_logic_vector (10 downto 0);
begin
Tail_flit := std_logic_vector(to_unsigned(Data, 8)) & Tail_type;
return Tail_flit;
end Tail_gen;
procedure credit_counter_control(signal clk: in std_logic;
signal credit_in: in std_logic; signal valid_out: in std_logic;
signal credit_counter_out: out std_logic_vector(1 downto 0)) is
variable credit_counter: std_logic_vector (1 downto 0);
begin
credit_counter := "11";
while true loop
credit_counter_out<= credit_counter;
wait until clk'event and clk ='1';
if credit_in = '1' then
credit_counter := credit_counter + 1;
end if;
if valid_out = '1' and credit_counter > 0 then
credit_counter := credit_counter - 1;
end if;
end loop;
end credit_counter_control;
procedure gen_random_packet(SHMU_ID, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector) is
variable seed1 :positive ;
variable seed2 :positive ;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
variable rand : real ;
variable destination_id: integer;
variable id_counter, frame_starting_delay, Packet_length, frame_ending_delay : integer:= 0;
variable credit_counter: std_logic_vector (1 downto 0);
begin
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
valid_out <= '0';
port_in <= "XXXXXXXXXXX" ;
wait until clk'event and clk ='1';
for i in 0 to initial_delay loop
wait until clk'event and clk ='1';
end loop;
port_in <= "UUUUUUUUUUU" ;
while true loop
--generating the frame initial delay
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*((2*frame_length/3) - Packet_length)))/100);
--generating the frame ending delay
frame_ending_delay := frame_length - (Packet_length+frame_starting_delay);
for k in 0 to frame_starting_delay-1 loop
wait until clk'event and clk ='0';
end loop;
valid_out <= '0';
while credit_counter_in = 0 loop
wait until clk'event and clk ='0';
end loop;
-- generating the packet
id_counter := id_counter + 1;
--------------------------------------
uniform(seed1, seed2, rand);
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
if (Packet_length < min_packet_size) then
Packet_length:=min_packet_size;
end if;
if (Packet_length > max_packet_size) then
Packet_length:=max_packet_size;
end if;
--------------------------------------
--uniform(seed1, seed2, rand);
--destination_id := integer(rand*3.0);
--while (destination_id = source) loop
-- uniform(seed1, seed2, rand);
-- destination_id := integer(rand*3.0);
--end loop;
destination_id := SHMU_ID;
--------------------------------------
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id) & " with length: "& integer'image(Packet_length));
writeline(VEC_FILE, LINEVARIABLE);
wait until clk'event and clk ='0';
port_in <= Header_gen(Packet_length, source, destination_id, id_counter);
valid_out <= '1';
wait until clk'event and clk ='0';
--valid_out <= '0';
--while credit_counter_in = 0 loop
-- wait until clk'event and clk ='1';
--end loop;
for I in 0 to Packet_length-3 loop
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
port_in <= Body_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
--valid_out <= '0';
--while credit_counter_in = 0 loop
-- wait until clk'event and clk ='0';
--end loop;
--wait until clk'event and clk ='1';
end loop;
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
port_in <= Tail_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
valid_out <= '0';
port_in <= "ZZZZZZZZZZZ" ;
for l in 0 to frame_ending_delay-1 loop
wait until clk'event and clk ='0';
end loop;
port_in <= "UUUUUUUUUUU" ;
if now > finish_time then
wait;
end if;
end loop;
end gen_random_packet;
procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal credit_out: out std_logic; signal valid_in: in std_logic; signal port_in: in std_logic_vector) is
-- initial_delay: waits for this number of clock cycles before sending the packet!
variable source_node, destination_node, P_length, packet_id, counter: integer;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "received.txt";
begin
credit_out <= '1';
while true loop
wait until clk'event and clk ='1';
if valid_in = '1' then
if (port_in(2 downto 0) = "001") then
destination_node := to_integer(unsigned(port_in(6 downto 3)));
source_node := to_integer(unsigned(port_in(10 downto 7)));
end if;
if (port_in(2 downto 0) = "100") then
report "Packet received at " & time'image(now) & " From " & integer'image(source_node) & " to " & integer'image(destination_node) ;
write(LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(source_node) & " to: " & integer'image(destination_node) );
writeline(VEC_FILE, LINEVARIABLE);
end if;
end if;
end loop;
end get_packet;
end TB_Package;
| gpl-3.0 | 1a3654cc92399b88db09728f28a2b95d | 0.591835 | 3.785889 | false | false | false | false |
TUM-LIS/faultify | hardware/testcases/viterbi/fpga_sim/xpsLibraryPath_viterbi_400_578/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/vhdl/user_logic.vhd | 3 | 30,363 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Fri May 16 15:25:24 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
numInj : integer := 56;
numIn : integer := 10;
numOut : integer := 10;
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
faultify_clk_fast : in std_logic;
faultify_clk_slow_out : out std_logic;
s_axis_aresetn : in std_logic;
-- AXI IFACE
resultvector_o : out std_logic_vector(numOut-1 downto 0);
resultvector_f : out std_logic_vector(numOut-1 downto 0);
testvector : in std_logic_vector(numIn-1 downto 0);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
component faultify_top is
generic (
numInj : integer;
numIn : integer;
numOut : integer);
port (
aclk : in std_logic;
arst_n : in std_logic;
clk : in std_logic;
clk_x32 : in std_logic;
awvalid : in std_logic;
awaddr : in std_logic_vector(31 downto 0);
wvalid : in std_logic;
wdata : in std_logic_vector(31 downto 0);
arvalid : in std_logic;
araddr : in std_logic_vector(31 downto 0);
rvalid : out std_logic;
rdata : out std_logic_vector(31 downto 0);
resultvector_o_p : out std_logic_vector(numOut-1 downto 0);
resultvector_f_p : out std_logic_vector(numOut-1 downto 0);
testvector : in std_logic_vector(numIn-1 downto 0);
s_axis_aresetn : in std_logic
);
end component faultify_top;
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal register_write_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal register_read_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal register_write_address : std_logic_vector(C_NUM_REG-1 downto 0);
signal register_read_address : std_logic_vector(C_NUM_REG-1 downto 0);
signal slv_reg_write_sel : std_logic_vector(31 downto 0);
signal slv_reg_read_sel : std_logic_vector(31 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal faultify_read_valid : std_logic;
signal faultify_read_address_valid : std_logic;
signal faultify_read_address : std_logic_vector(31 downto 0);
signal faultify_write_valid : std_logic;
signal counter, divide : integer := 0;
signal faultify_clk_slow_i : std_logic;
begin
slv_reg_write_sel <= Bus2IP_WrCE(31 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(31 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12) or Bus2IP_WrCE(13) or Bus2IP_WrCE(14) or Bus2IP_WrCE(15) or Bus2IP_WrCE(16) or Bus2IP_WrCE(17) or Bus2IP_WrCE(18) or Bus2IP_WrCE(19) or Bus2IP_WrCE(20) or Bus2IP_WrCE(21) or Bus2IP_WrCE(22) or Bus2IP_WrCE(23) or Bus2IP_WrCE(24) or Bus2IP_WrCE(25) or Bus2IP_WrCE(26) or Bus2IP_WrCE(27) or Bus2IP_WrCE(28) or Bus2IP_WrCE(29) or Bus2IP_WrCE(30) or Bus2IP_WrCE(31);
slv_read_ack <= faultify_read_valid;
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process(Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
register_write_data <= (others => '0');
register_write_address <= (others => '0');
faultify_write_valid <= '0';
else
faultify_write_valid <= slv_write_ack;
case slv_reg_write_sel is
when "10000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(0, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "01000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(1, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00100000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(2, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00010000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(3, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00001000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(4, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000100000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(5, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000010000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(6, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000001000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(7, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000100000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(8, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000010000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(9, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000001000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(10, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000100000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(11, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000010000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(12, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000001000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(13, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000100000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(14, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000010000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(15, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000001000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(16, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000100000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(17, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000010000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(18, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000001000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(19, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000100000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(20, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000010000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(21, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000001000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(22, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000100000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(23, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000010000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(24, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000001000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(25, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(26, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(27, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(28, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(29, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(30, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(31, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process(slv_reg_read_sel, faultify_read_valid) is
begin
faultify_read_address_valid <= '1';
case slv_reg_read_sel is
when "10000000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(0, 32));
when "01000000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(1, 32));
when "00100000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(2, 32));
when "00010000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(3, 32));
when "00001000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(4, 32));
when "00000100000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(5, 32));
when "00000010000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(6, 32));
when "00000001000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(7, 32));
when "00000000100000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(8, 32));
when "00000000010000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(9, 32));
when "00000000001000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(10, 32));
when "00000000000100000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(11, 32));
when "00000000000010000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(12, 32));
when "00000000000001000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(13, 32));
when "00000000000000100000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(14, 32));
when "00000000000000010000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(15, 32));
when "00000000000000001000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(16, 32));
when "00000000000000000100000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(17, 32));
when "00000000000000000010000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(18, 32));
when "00000000000000000001000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(19, 32));
when "00000000000000000000100000000000" => faultify_read_address <= std_logic_vector(to_unsigned(20, 32));
when "00000000000000000000010000000000" => faultify_read_address <= std_logic_vector(to_unsigned(21, 32));
when "00000000000000000000001000000000" => faultify_read_address <= std_logic_vector(to_unsigned(22, 32));
when "00000000000000000000000100000000" => faultify_read_address <= std_logic_vector(to_unsigned(23, 32));
when "00000000000000000000000010000000" => faultify_read_address <= std_logic_vector(to_unsigned(24, 32));
when "00000000000000000000000001000000" => faultify_read_address <= std_logic_vector(to_unsigned(25, 32));
when "00000000000000000000000000100000" => faultify_read_address <= std_logic_vector(to_unsigned(26, 32));
when "00000000000000000000000000010000" => faultify_read_address <= std_logic_vector(to_unsigned(27, 32));
when "00000000000000000000000000001000" => faultify_read_address <= std_logic_vector(to_unsigned(28, 32));
when "00000000000000000000000000000100" => faultify_read_address <= std_logic_vector(to_unsigned(29, 32));
when "00000000000000000000000000000010" => faultify_read_address <= std_logic_vector(to_unsigned(30, 32));
when "00000000000000000000000000000001" => faultify_read_address <= std_logic_vector(to_unsigned(31, 32));
when others => faultify_read_address <= (others => '0');
faultify_read_address_valid <= '0';
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= register_read_data when faultify_read_valid = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
-----------------------------------------------------------------------------
-- clock divider 32 -> 1
-----------------------------------------------------------------------------
divide <= 32;
process(Bus2IP_Clk, Bus2IP_Resetn)
begin
if Bus2IP_Resetn = '0' then
counter <= 0;
faultify_clk_slow_i <= '0';
elsif(rising_edge(Bus2IP_Clk)) then
if(counter < divide/2-1) then
counter <= counter + 1;
faultify_clk_slow_i <= '0';
elsif(counter < divide-1) then
counter <= counter + 1;
faultify_clk_slow_i <= '1';
else
faultify_clk_slow_i <= '0';
counter <= 0;
end if;
end if;
end process;
faultify_clk_slow_out <= faultify_clk_slow_i;
faultify_top_1 : faultify_top
generic map (
numInj => numInj,
numIn => numIn,
numOut => numOut)
port map (
aclk => Bus2IP_Clk,
arst_n => Bus2IP_Resetn,
clk => faultify_clk_slow_i,
clk_x32 => Bus2IP_Clk,
awvalid => faultify_write_valid,
awaddr => register_write_address,
wvalid => faultify_write_valid,
wdata => register_write_data,
arvalid => faultify_read_address_valid,
araddr => faultify_read_address,
rvalid => faultify_read_valid,
rdata => register_read_data,
resultvector_o_p => resultvector_o,
resultvector_f_p => resultvector_f,
testvector => testvector,
s_axis_aresetn => s_axis_aresetn
);
end IMP;
| gpl-2.0 | 308e94aaa1671e4ac91efc37c4c67aa4 | 0.537068 | 4.03495 | false | false | false | false |
TUM-LIS/faultify | hardware/testcases/viterbi/fpga_sim/xpsLibraryPath_viterbi_400_578/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/vhdl/faultify_axi_wrapper.vhd | 1 | 19,307 | ------------------------------------------------------------------------------
-- faultify_axi_wrapper.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: faultify_axi_wrapper.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Fri May 16 15:25:24 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
use proc_common_v3_00_a.soft_reset;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library faultify_axi_wrapper_v1_00_a;
use faultify_axi_wrapper_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity faultify_axi_wrapper is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
numInj : integer := 178;
numIn : integer := 69;
numOut : integer := 5;
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
faultify_clk_fast : in std_logic;
faultify_clk_slow_out : out std_logic;
s_axis_aresetn : in std_logic;
s_axis_input_tvalid : in std_logic;
s_axis_input_tdata : in std_logic_vector(31 downto 0);
s_axis_input_tlast : in std_logic;
s_axis_input_tready : out std_logic;
m_axis_output_tvalid : out std_logic;
m_axis_output_tdata : out std_logic_vector(31 downto 0);
m_axis_output_tlast : out std_logic;
m_axis_output_tready : in std_logic;
s_axis_ctrl_tvalid : in std_logic;
s_axis_ctrl_tdata : in std_logic_vector(31 downto 0);
s_axis_ctrl_tlast : in std_logic;
s_axis_ctrl_tready : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity faultify_axi_wrapper;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of faultify_axi_wrapper is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant RST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
constant RST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
constant USER_SLV_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & RST_BASEADDR, -- soft reset space base address
ZERO_ADDR_PAD & RST_HIGHADDR, -- soft reset space high address
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant RST_NUM_CE : integer := 1;
constant USER_SLV_NUM_REG : integer := 32;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG + RST_NUM_CE;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (RST_NUM_CE), -- number of ce for soft reset space
1 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Width of triggered reset in bus clocks
------------------------------------------
constant RESET_WIDTH : integer := 8;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant RST_CS_INDEX : integer := 0;
constant RST_CE_INDEX : integer := USER_NUM_REG;
constant USER_SLV_CS_INDEX : integer := 1;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_Bus2IP_Reset : std_logic;
signal rst_Bus2IP_Reset : std_logic;
signal rst_IP2Bus_WrAck : std_logic;
signal rst_IP2Bus_Error : std_logic;
signal rst_Bus2IP_Reset_tmp : std_logic;
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
signal testvector : std_logic_vector(numIn-1 downto 0);
signal resultvector_o : std_logic_vector(numOut-1 downto 0);
signal resultvector_f : std_logic_vector(numOut-1 downto 0);
begin
testvector(0) <= s_axis_input_tvalid;
testvector(32 downto 1) <= s_axis_input_tdata;
testvector(33) <= s_axis_input_tlast;
s_axis_input_tready <= resultvector_o(0);
m_axis_output_tvalid <= resultvector_o(1);
m_axis_output_tdata(0) <= resultvector_o(2);
m_axis_output_tdata(1) <= resultvector_f(2);
m_axis_output_tdata(31 downto 2) <= (others => '0');
m_axis_output_tlast <= resultvector_o(3);
testvector(34) <= m_axis_output_tready;
testvector(35) <= s_axis_ctrl_tvalid;
testvector(67 downto 36) <= s_axis_ctrl_tdata;
testvector(68) <= s_axis_ctrl_tlast;
s_axis_ctrl_tready <= resultvector_o(4);
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate soft_reset
------------------------------------------
SOFT_RESET_I : entity proc_common_v3_00_a.soft_reset
generic map
(
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_RESET_WIDTH => RESET_WIDTH
)
port map
(
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_WrCE => ipif_Bus2IP_WrCE(RST_CE_INDEX),
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Reset2IP_Reset => rst_Bus2IP_Reset,
Reset2Bus_WrAck => rst_IP2Bus_WrAck,
Reset2Bus_Error => rst_IP2Bus_Error,
Reset2Bus_ToutSup => open
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity faultify_axi_wrapper_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
numInj => numInj,
numIn => numIn,
numOut => numOut,
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
faultify_clk_fast => faultify_clk_fast,
faultify_clk_slow_out => faultify_clk_slow_out,
s_axis_aresetn => s_axis_aresetn,
resultvector_o => resultvector_o,
resultvector_f => resultvector_f,
testvector => testvector,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => rst_Bus2IP_Reset_tmp,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
IP2BUS_DATA_MUX_PROC : process(ipif_Bus2IP_CS, user_IP2Bus_Data) is
begin
case ipif_Bus2IP_CS (1 downto 0) is
when "01" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when "10" => ipif_IP2Bus_Data <= (others => '0');
when others => ipif_IP2Bus_Data <= (others => '0');
end case;
end process IP2BUS_DATA_MUX_PROC;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck or rst_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error or rst_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
ipif_Bus2IP_Reset <= not ipif_Bus2IP_Resetn;
rst_Bus2IP_Reset_tmp <= not rst_Bus2IP_Reset;
end IMP;
| gpl-2.0 | 629c51be9fa6fbcb33a6aa4090c7d6ff | 0.524628 | 3.683839 | false | false | false | false |
lnls-dig/dsp-cores | hdl/modules/ce_synch/ce_synch.vhd | 1 | 3,097 | -------------------------------------------------------------------------------
-- Title : Clock Enable synchronizer for data/valid signals
-- Project :
-------------------------------------------------------------------------------
-- File : ce_synch.vhd
-- Author : Lucas Russo <[email protected]>
-- Company :
-- Created : 2016-05-02
-- Last update: 2016-05-02
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Clock Enable synchronizer for data/valid signals. This modules basically,
-- synchronizes data/valid signals between two clock enable signals.
-- WARNING: This only works if the destination CE signal is slower
-- than the source CE signal
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-05-02 1.0 lerwys Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ce_synch is
generic (
g_data_width : natural := 16
);
port (
clk_i : in std_logic := '0';
rst_i : in std_logic := '0';
ce_in_i : in std_logic := '0';
valid_i : in std_logic := '1';
data_i : in std_logic_vector(g_data_width-1 downto 0) := (others => '0');
ce_out_i : in std_logic := '0';
data_o : out std_logic_vector(g_data_width-1 downto 0) := (others => '0');
valid_o : out std_logic := '0'
);
end entity ce_synch;
architecture rtl of ce_synch is
signal data_int : std_logic_vector(g_data_width-1 downto 0) := (others => '0');
signal valid_int : std_logic := '0';
begin
p_in : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
data_int <= (others => '0');
valid_int <= '0';
else
if ce_in_i = '1' then
-- if valid_i = '1' or ack_out = '1' then
if valid_i = '1' or ce_out_i = '1' then
data_int <= data_i;
valid_int <= valid_i;
end if;
-- elsif ack_out = '1' then
elsif ce_out_i = '1' then
data_int <= (others => '0');
valid_int <= '0';
end if;
end if;
end if;
end process;
-- p_out : process (clk_i)
-- begin
-- if rising_edge(clk_i) then
-- if rst_i = '1' then
-- ack_out <= '0';
-- else
-- if ce_out_i = '1' then
-- ack_out <= '1';
-- else
-- ack_out <= '0';
-- end if;
-- end if;
-- end if;
-- end process;
data_o <= data_int;
valid_o <= valid_int;
end architecture rtl;
| lgpl-3.0 | 3ae2fae8008d3e7edc35d1280a4e36ca | 0.405231 | 3.876095 | false | false | false | false |
SoCdesign/EHA | RTL/Immortal_Chip/modules_with_fault_injectors/to_be_tested/Arbiter_one_hot_with_checkers_with_FI.vhd | 1 | 19,331 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Arbiter is
port ( reset: in std_logic;
clk: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules
DCTS: in std_logic; -- Getting the CTS signal from the input FIFO of the next router/NI (for hand-shaking)
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
Xbar_sel : out std_logic_vector(4 downto 0); -- select lines for XBAR
RTS: out std_logic; -- Valid output which is sent to the next router/NI to specify that the data on the output port is valid
-- fault injector signals
shift: in std_logic;
fault_clk: in std_logic;
data_in_serial: in std_logic;
data_out_serial: out std_logic;
-- Checker outputs
err_state_IDLE_xbar,
err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE,
err_IDLE_Req_L,
err_Local_Req_L,
err_North_Req_N,
--err_East_Req_E,
--err_West_Req_W,
--err_South_Req_S,
err_IDLE_Req_N,
err_Local_Req_N,
--err_North_Req_E,
--err_East_Req_W,
--err_West_Req_S,
err_South_Req_L,
--err_IDLE_Req_E,
--err_Local_Req_E,
--err_North_Req_W,
--err_East_Req_S,
err_West_Req_L,
err_South_Req_N,
--err_IDLE_Req_W,
--err_Local_Req_W,
--err_North_Req_S,
err_East_Req_L,
err_West_Req_N,
--err_South_Req_E,
--err_IDLE_Req_S,
--err_Local_Req_S,
--err_North_Req_L,
err_East_Req_N,
--err_West_Req_E,
--err_South_Req_W,
err_next_state_onehot,
err_state_in_onehot,
--err_DCTS_RTS_FF_state_Grant_L,
--err_DCTS_RTS_FF_state_Grant_N,
--err_DCTS_RTS_FF_state_Grant_E,
--err_DCTS_RTS_FF_state_Grant_W,
--err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel,
err_state_east_xbar_sel,
err_state_west_xbar_sel,
err_state_south_xbar_sel : out std_logic
--err_state_local_xbar_sel : out std_logic
);
end;
architecture behavior of Arbiter is
-- TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SUBTYPE STATE_TYPE IS STD_LOGIC_VECTOR (5 downto 0);
CONSTANT IDLE: STATE_TYPE := "000001";
CONSTANT Local: STATE_TYPE := "000010";
CONSTANT North: STATE_TYPE := "000100";
CONSTANT East: STATE_TYPE := "001000";
CONSTANT West: STATE_TYPE := "010000";
CONSTANT South: STATE_TYPE := "100000";
SIGNAL state, state_in, next_state : STATE_TYPE := IDLE;
SIGNAL RTS_FF, RTS_FF_in: std_logic;
signal Grant_N_sig, Grant_E_sig, Grant_W_sig, Grant_S_sig, Grant_L_sig: std_logic;
signal Xbar_sel_sig: std_logic_vector(4 downto 0);
-- New signals used for integration of FI(s) in LBDR module
signal Req_N_faulty, Req_E_faulty, Req_W_faulty, Req_S_faulty, Req_L_faulty : std_logic;
signal DCTS_faulty : std_logic;
SIGNAL state_faulty, state_in_faulty, next_state_faulty : STATE_TYPE := IDLE;
SIGNAL RTS_FF_faulty, RTS_FF_in_faulty: std_logic;
signal Grant_N_sig_faulty, Grant_E_sig_faulty, Grant_W_sig_faulty, Grant_S_sig_faulty, Grant_L_sig_faulty: std_logic;
signal Xbar_sel_sig_faulty: std_logic_vector(4 downto 0);
component Arbiter_checkers is
port (
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic;
DCTS: in std_logic;
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L: in std_logic;
Xbar_sel : in std_logic_vector(4 downto 0);
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
next_state_out: in std_logic_vector (5 downto 0);
RTS_FF: in std_logic;
RTS_FF_in: in std_logic;
-- Checker outputs
err_state_IDLE_xbar,
err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE,
err_IDLE_Req_L,
err_Local_Req_L,
err_North_Req_N,
--err_East_Req_E,
--err_West_Req_W,
--err_South_Req_S,
err_IDLE_Req_N,
err_Local_Req_N,
--err_North_Req_E,
--err_East_Req_W,
--err_West_Req_S,
err_South_Req_L,
--err_IDLE_Req_E,
--err_Local_Req_E,
--err_North_Req_W,
--err_East_Req_S,
err_West_Req_L,
err_South_Req_N,
--err_IDLE_Req_W,
--err_Local_Req_W,
--err_North_Req_S,
err_East_Req_L,
err_West_Req_N,
--err_South_Req_E,
--err_IDLE_Req_S,
--err_Local_Req_S,
--err_North_Req_L,
err_East_Req_N,
--err_West_Req_E,
--err_South_Req_W,
err_next_state_onehot,
err_state_in_onehot,
--err_DCTS_RTS_FF_state_Grant_L,
--err_DCTS_RTS_FF_state_Grant_N,
--err_DCTS_RTS_FF_state_Grant_E,
--err_DCTS_RTS_FF_state_Grant_W,
--err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel,
err_state_east_xbar_sel,
err_state_west_xbar_sel,
err_state_south_xbar_sel : out std_logic
--err_state_local_xbar_sel : out std_logic
);
end component;
component fault_injector is
generic(DATA_WIDTH : integer := 32;
ADDRESS_WIDTH : integer := 5);
port(
data_in: in std_logic_vector (DATA_WIDTH-1 downto 0);
address: in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
sta_0: in std_logic;
sta_1: in std_logic;
data_out: out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end component;
component shift_register_serial_in is
generic (
REG_WIDTH: integer := 44
);
port (
clk, reset : in std_logic;
shift: in std_logic;
data_in_serial: in std_logic;
data_out_parallel: out std_logic_vector(REG_WIDTH-1 downto 0);
data_out_serial: out std_logic
);
end component;
signal FI_add_sta: std_logic_vector(43 downto 0); -- 36 bits for inputs and internal signals
-- 6 bits for fault injection location address (ceil of log2(36) = 6)
-- 2 bits for type of fault (SA0 or SA1)
signal non_faulty_signals: std_logic_vector (35 downto 0);
signal faulty_signals: std_logic_vector(35 downto 0); -- 36 bits for inputs, internal and output signals (with one fault injected in one of them)
begin
non_faulty_signals <= Req_N & Req_E & Req_W & Req_S & Req_L &
DCTS &
state & state_in & next_state &
RTS_FF & RTS_FF_in &
Grant_N_sig & Grant_E_sig & Grant_W_sig & Grant_S_sig & Grant_L_sig &
Xbar_sel_sig;
FI: fault_injector generic map(DATA_WIDTH => 36, ADDRESS_WIDTH => 6)
port map (data_in=> non_faulty_signals , address=> FI_add_sta(7 downto 2), sta_0=> FI_add_sta(1), sta_1=> FI_add_sta(0), data_out=> faulty_signals
);
-- Extracting faulty values for input, internal and output signals
Req_N_faulty <= faulty_signals(35);
Req_E_faulty <= faulty_signals(34);
Req_W_faulty <= faulty_signals(33);
Req_S_faulty <= faulty_signals(32);
Req_L_faulty <= faulty_signals(31);
DCTS_faulty <= faulty_signals(30);
state_faulty <= faulty_signals(29 downto 24);
state_in_faulty <= faulty_signals(23 downto 18);
next_state_faulty <= faulty_signals(17 downto 12);
RTS_FF_faulty <= faulty_signals(11);
RTS_FF_in_faulty <= faulty_signals(10);
Grant_N_sig_faulty <= faulty_signals(9);
Grant_E_sig_faulty <= faulty_signals(8);
Grant_W_sig_faulty <= faulty_signals(7);
Grant_S_sig_faulty <= faulty_signals(6);
Grant_L_sig_faulty <= faulty_signals(5);
Xbar_sel_sig_faulty <= faulty_signals(4 downto 0);
SR: shift_register_serial_in generic map(REG_WIDTH => 44)
port map( clk=> fault_clk, reset=>reset, shift=> shift,data_in_serial=> data_in_serial,
data_out_parallel=> FI_add_sta, data_out_serial=> data_out_serial
);
-- Arbiter checkers instantiation
ARBITERCHECKERS: Arbiter_checkers port map (
Req_N => Req_N,
Req_E => Req_E,
Req_W => Req_W,
Req_S => Req_S,
Req_L => Req_L,
DCTS => DCTS,
Grant_N => Grant_N_sig,
Grant_E => Grant_E_sig,
Grant_W => Grant_W_sig,
Grant_S => Grant_S_sig,
Grant_L => Grant_L_sig,
Xbar_sel=>Xbar_sel_sig,
state => state,
state_in => state_in,
next_state_out => next_state,
RTS_FF => RTS_FF,
RTS_FF_in => RTS_FF_in,
err_state_IDLE_xbar => err_state_IDLE_xbar,
err_state_not_IDLE_xbar => err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in => err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in => err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in => err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state => err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state => err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants => err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants => err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants => err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE => err_Requests_next_state_IDLE,
err_IDLE_Req_L => err_IDLE_Req_L,
err_Local_Req_L => err_Local_Req_L,
err_North_Req_N => err_North_Req_N,
err_IDLE_Req_N => err_IDLE_Req_N,
err_Local_Req_N => err_Local_Req_N,
err_South_Req_L => err_South_Req_L,
err_West_Req_L => err_West_Req_L,
err_South_Req_N => err_South_Req_N,
err_East_Req_L => err_East_Req_L,
err_West_Req_N => err_West_Req_N,
err_East_Req_N => err_East_Req_N,
err_next_state_onehot => err_next_state_onehot,
err_state_in_onehot => err_state_in_onehot,
err_state_north_xbar_sel => err_state_north_xbar_sel,
err_state_east_xbar_sel => err_state_east_xbar_sel,
err_state_west_xbar_sel => err_state_west_xbar_sel,
err_state_south_xbar_sel => err_state_south_xbar_sel
);
-- process for updating the state of arbiter's FSM, also setting RTS based on the state (if Grant is given or not)
process(clk, reset)begin
if reset = '0' then
state<=IDLE;
RTS_FF <= '0';
elsif clk'event and clk = '1' then
-- no grant given yet, it might be that there is no request to
-- arbiter or request is there, but the next router's/NI's FIFO is full
state <= state_in_faulty;
RTS_FF <= RTS_FF_in_faulty;
end if;
end process;
-- anything below here is pure combinational
RTS <= RTS_FF;
-- Becuase of checkers we did this!
Grant_N <= Grant_N_sig;
Grant_E <= Grant_E_sig;
Grant_W <= Grant_W_sig;
Grant_S <= Grant_S_sig;
Grant_L <= Grant_L_sig;
Xbar_sel <= Xbar_sel_sig;
process(RTS_FF_faulty, DCTS_faulty, state_faulty, next_state_faulty)begin
if RTS_FF_faulty = '1' and DCTS_faulty = '0' then
state_in <= state_faulty;
else
state_in <= next_state_faulty;
end if;
end process;
process(state_faulty, RTS_FF_faulty, DCTS_faulty)begin
if state_faulty = IDLE then
RTS_FF_in <= '0';
-- if there was a grant given to one of the inputs,
-- tell the next router/NI that the output data is valid
else
if RTS_FF_faulty = '1' and DCTS_faulty = '1' then
RTS_FF_in <= '0';
else
RTS_FF_in <= '1';
end if;
end if ;
end process;
-- sets the grants using round robin
-- the order is L --> N --> E --> W --> S and then back to L
process(state_faulty, Req_N_faulty, Req_E_faulty, Req_W_faulty, Req_S_faulty, Req_L_faulty, DCTS_faulty, RTS_FF_faulty)begin
Grant_N_sig <= '0';
Grant_E_sig <= '0';
Grant_W_sig <= '0';
Grant_S_sig <= '0';
Grant_L_sig <= '0';
Xbar_sel_sig <= "00000";
case(state_faulty) is
when IDLE =>
Xbar_sel_sig <= "00000";
If Req_L_faulty = '1' then
next_state <= Local;
elsif Req_N_faulty = '1' then
next_state <= North;
elsif Req_E_faulty = '1' then
next_state <= East;
elsif Req_W_faulty = '1' then
next_state <= West;
elsif Req_S_faulty = '1' then
next_state <= South;
else
next_state <= IDLE;
end if;
when North =>
Grant_N_sig <= DCTS_faulty and RTS_FF_faulty ;
Xbar_sel_sig <= "00001";
If Req_N_faulty = '1' then
next_state <= North;
elsif Req_E_faulty = '1' then
next_state <= East;
elsif Req_W_faulty = '1' then
next_state <= West;
elsif Req_S_faulty = '1' then
next_state <= South;
elsif Req_L_faulty = '1' then
next_state <= Local;
else
next_state <= IDLE;
end if;
when East =>
Grant_E_sig <= DCTS_faulty and RTS_FF_faulty;
Xbar_sel_sig <= "00010";
If Req_E_faulty = '1' then
next_state <= East;
elsif Req_W_faulty = '1' then
next_state <= West;
elsif Req_S_faulty = '1' then
next_state <= South;
elsif Req_L_faulty = '1' then
next_state <= Local;
elsif Req_N_faulty = '1' then
next_state <= North;
else
next_state <= IDLE;
end if;
when West =>
Grant_W_sig <= DCTS_faulty and RTS_FF_faulty;
Xbar_sel_sig <= "00100";
If Req_W_faulty = '1' then
next_state <= West;
elsif Req_S_faulty = '1' then
next_state <= South;
elsif Req_L_faulty = '1' then
next_state <= Local;
elsif Req_N_faulty = '1' then
next_state <= North;
elsif Req_E_faulty = '1' then
next_state <= East;
else
next_state <= IDLE;
end if;
when South =>
Grant_S_sig <= DCTS_faulty and RTS_FF_faulty;
Xbar_sel_sig <= "01000";
If Req_S_faulty = '1' then
next_state <= South;
elsif Req_L_faulty = '1' then
next_state <= Local;
elsif Req_N_faulty = '1' then
next_state <= North;
elsif Req_E_faulty = '1' then
next_state <= East;
elsif Req_W_faulty = '1' then
next_state <= West;
else
next_state <= IDLE;
end if;
when others => -- Local
Grant_L_sig <= DCTS_faulty and RTS_FF_faulty;
Xbar_sel_sig <= "10000";
If Req_L_faulty = '1' then
next_state <= Local;
elsif Req_N_faulty = '1' then
next_state <= North;
elsif Req_E_faulty = '1' then
next_state <= East;
elsif Req_W_faulty = '1' then
next_state <= West;
elsif Req_S_faulty = '1' then
next_state <= South;
else
next_state <= IDLE;
end if;
end case ;
end process;
end;
| gpl-3.0 | 5dc80fdc9ad734ac793ba68f3c0b11ee | 0.482903 | 3.650803 | false | false | false | false |
SoCdesign/EHA | RTL/Credit_Based/Credit_Based_FC/Router_32_bit_credit_based.vhd | 1 | 14,457 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_credit_based is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 60;
Cx_rst : integer := 10;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end router_credit_based;
architecture behavior of router_credit_based is
COMPONENT FIFO_credit_based
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
COMPONENT allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic
);
end COMPONENT;
COMPONENT LBDR is
generic (
cur_addr_rst: integer := 0;
Rxy_rst: integer := 60;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
begin
-- all the FIFOs
FIFO_N: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_N, valid_in => valid_in_N,
read_en_N => '0', read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
credit_out => credit_out_N, empty_out => empty_N, Data_out => FIFO_D_out_N);
FIFO_E: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_E, valid_in => valid_in_E,
read_en_N => Grant_NE, read_en_E =>'0', read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
credit_out => credit_out_E, empty_out => empty_E, Data_out => FIFO_D_out_E);
FIFO_W: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_W, valid_in => valid_in_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>'0', read_en_S =>Grant_SW, read_en_L =>Grant_LW,
credit_out => credit_out_W, empty_out => empty_W, Data_out => FIFO_D_out_W);
FIFO_S: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_S, valid_in => valid_in_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>'0', read_en_L =>Grant_LS,
credit_out => credit_out_S, empty_out => empty_S, Data_out => FIFO_D_out_S);
FIFO_L: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_L, valid_in => valid_in_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>'0',
credit_out => credit_out_L, empty_out => empty_L, Data_out => FIFO_D_out_L);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the LBDRs
LBDR_N: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N, flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
grant_N => '0', grant_E =>Grant_EN, grant_W => Grant_WN, grant_S=>Grant_SN, grant_L =>Grant_LN,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL);
LBDR_E: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E, flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
grant_N => Grant_NE, grant_E =>'0', grant_W => Grant_WE, grant_S=>Grant_SE, grant_L =>Grant_LE,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL);
LBDR_W: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W, flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
grant_N => Grant_NW, grant_E =>Grant_EW, grant_W =>'0' ,grant_S=>Grant_SW, grant_L =>Grant_LW,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL);
LBDR_S: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S, flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
grant_N => Grant_NS, grant_E =>Grant_ES, grant_W =>Grant_WS ,grant_S=>'0', grant_L =>Grant_LS,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL);
LBDR_L: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L, flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
grant_N => Grant_NL, grant_E =>Grant_EL, grant_W => Grant_WL,grant_S=>Grant_SL, grant_L =>'0',
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- switch allocator
allocator_unit: allocator port map ( reset => reset, clk => clk,
-- flow control
credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L,
-- requests from the LBDRS
req_N_N => '0', req_N_E => Req_NE, req_N_W => Req_NW, req_N_S => Req_NS, req_N_L => Req_NL,
req_E_N => Req_EN, req_E_E => '0', req_E_W => Req_EW, req_E_S => Req_ES, req_E_L => Req_EL,
req_W_N => Req_WN, req_W_E => Req_WE, req_W_W => '0', req_W_S => Req_WS, req_W_L => Req_WL,
req_S_N => Req_SN, req_S_E => Req_SE, req_S_W => Req_SW, req_S_S => '0', req_S_L => Req_SL,
req_L_N => Req_LN, req_L_E => Req_LE, req_L_W => Req_LW, req_L_S => Req_LS, req_L_L => '0',
empty_N => empty_N, empty_E => empty_E, empty_w => empty_W, empty_S => empty_S, empty_L => empty_L,
valid_N => valid_out_N, valid_E => valid_out_E, valid_W => valid_out_W, valid_S => valid_out_S, valid_L => valid_out_L,
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
grant_N_N => Grant_NN, grant_N_E => Grant_NE, grant_N_W => Grant_NW, grant_N_S => Grant_NS, grant_N_L => Grant_NL,
grant_E_N => Grant_EN, grant_E_E => Grant_EE, grant_E_W => Grant_EW, grant_E_S => Grant_ES, grant_E_L => Grant_EL,
grant_W_N => Grant_WN, grant_W_E => Grant_WE, grant_W_W => Grant_WW, grant_W_S => Grant_WS, grant_W_L => Grant_WL,
grant_S_N => Grant_SN, grant_S_E => Grant_SE, grant_S_W => Grant_SW, grant_S_S => Grant_SS, grant_S_L => Grant_SL,
grant_L_N => Grant_LN, grant_L_E => Grant_LE, grant_L_W => Grant_LW, grant_L_S => Grant_LS, grant_L_L => Grant_LL
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbar select_signals
Xbar_sel_N <= '0' & Grant_NE & Grant_NW & Grant_NS & Grant_NL;
Xbar_sel_E <= Grant_EN & '0' & Grant_EW & Grant_ES & Grant_EL;
Xbar_sel_W <= Grant_WN & Grant_WE & '0' & Grant_WS & Grant_WL;
Xbar_sel_S <= Grant_SN & Grant_SE & Grant_SW & '0' & Grant_SL;
Xbar_sel_L <= Grant_LN & Grant_LE & Grant_LW & Grant_LS & '0';
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
end;
| gpl-3.0 | c8250a81d9593d4e29136478c2ade062 | 0.518918 | 2.951613 | false | false | false | false |
lnls-dig/dsp-cores | hdl/modules/clock_driver/xlclockdriver.vhd | 1 | 18,016 |
-------------------------------------------------------------------
-- System Generator version 13.4 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity single_reg_w_init is
generic (
width: integer := 8;
init_index: integer := 0;
init_value: bit_vector := b"0000"
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end single_reg_w_init;
architecture structural of single_reg_w_init is
function build_init_const(width: integer;
init_index: integer;
init_value: bit_vector)
return std_logic_vector
is
variable result: std_logic_vector(width - 1 downto 0);
begin
if init_index = 0 then
result := (others => '0');
elsif init_index = 1 then
result := (others => '0');
result(0) := '1';
else
result := to_stdlogicvector(init_value);
end if;
return result;
end;
component fdre
port (
q: out std_ulogic;
d: in std_ulogic;
c: in std_ulogic;
ce: in std_ulogic;
r: in std_ulogic
);
end component;
attribute syn_black_box of fdre: component is true;
attribute fpga_dont_touch of fdre: component is "true";
component fdse
port (
q: out std_ulogic;
d: in std_ulogic;
c: in std_ulogic;
ce: in std_ulogic;
s: in std_ulogic
);
end component;
attribute syn_black_box of fdse: component is true;
attribute fpga_dont_touch of fdse: component is "true";
constant init_const: std_logic_vector(width - 1 downto 0)
:= build_init_const(width, init_index, init_value);
begin
fd_prim_array: for index in 0 to width - 1 generate
bit_is_0: if (init_const(index) = '0') generate
fdre_comp: fdre
port map (
c => clk,
d => i(index),
q => o(index),
ce => ce,
r => clr
);
end generate;
bit_is_1: if (init_const(index) = '1') generate
fdse_comp: fdse
port map (
c => clk,
d => i(index),
q => o(index),
ce => ce,
s => clr
);
end generate;
end generate;
end architecture structural;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg_w_init is
generic (
width: integer := 8;
init_index: integer := 0;
init_value: bit_vector := b"0000";
latency: integer := 1
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end synth_reg_w_init;
architecture structural of synth_reg_w_init is
component single_reg_w_init
generic (
width: integer := 8;
init_index: integer := 0;
init_value: bit_vector := b"0000"
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0);
signal dly_clr: std_logic;
begin
latency_eq_0: if (latency = 0) generate
o <= i;
end generate;
latency_gt_0: if (latency >= 1) generate
dly_i((latency + 1) * width - 1 downto latency * width) <= i
after 200 ps;
dly_clr <= clr after 200 ps;
fd_array: for index in latency downto 1 generate
reg_comp: single_reg_w_init
generic map (
width => width,
init_index => init_index,
init_value => init_value
)
port map (
clk => clk,
i => dly_i((index + 1) * width - 1 downto index * width),
o => dly_i(index * width - 1 downto (index - 1) * width),
ce => ce,
clr => dly_clr
);
end generate;
o <= dly_i(width - 1 downto 0);
end generate;
end structural;
-------------------------------------------------------------------
-- System Generator version 13.4 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-------------------------------------------------------------------
-- System Generator version 13.4 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
entity xlclockdriver is
generic (
period: integer := 2;
log_2_period: integer := 0;
pipeline_regs: integer := 5;
use_bufg: integer := 0
);
port (
sysclk: in std_logic;
sysclr: in std_logic;
sysce: in std_logic;
clk: out std_logic;
clr: out std_logic;
ce: out std_logic;
ce_logic: out std_logic
);
end xlclockdriver;
architecture behavior of xlclockdriver is
component bufg
port (
i: in std_logic;
o: out std_logic
);
end component;
component synth_reg_w_init
generic (
width: integer;
init_index: integer;
init_value: bit_vector;
latency: integer
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
function size_of_uint(inp: integer; power_of_2: boolean)
return integer
is
constant inp_vec: std_logic_vector(31 downto 0) :=
integer_to_std_logic_vector(inp,32, xlUnsigned);
variable result: integer;
begin
result := 32;
for i in 0 to 31 loop
if inp_vec(i) = '1' then
result := i;
end if;
end loop;
if power_of_2 then
return result;
else
return result+1;
end if;
end;
function is_power_of_2(inp: std_logic_vector)
return boolean
is
constant width: integer := inp'length;
variable vec: std_logic_vector(width - 1 downto 0);
variable single_bit_set: boolean;
variable more_than_one_bit_set: boolean;
variable result: boolean;
begin
vec := inp;
single_bit_set := false;
more_than_one_bit_set := false;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if width > 0 then
for i in 0 to width - 1 loop
if vec(i) = '1' then
if single_bit_set then
more_than_one_bit_set := true;
end if;
single_bit_set := true;
end if;
end loop;
end if;
if (single_bit_set and not(more_than_one_bit_set)) then
result := true;
else
result := false;
end if;
return result;
end;
function ce_reg_init_val(index, period : integer)
return integer
is
variable result: integer;
begin
result := 0;
if ((index mod period) = 0) then
result := 1;
end if;
return result;
end;
function remaining_pipe_regs(num_pipeline_regs, period : integer)
return integer
is
variable factor, result: integer;
begin
factor := (num_pipeline_regs / period);
result := num_pipeline_regs - (period * factor) + 1;
return result;
end;
function sg_min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
constant max_pipeline_regs : integer := 8;
constant pipe_regs : integer := 5;
constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs);
constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period);
constant period_floor: integer := max(2, period);
constant power_of_2_counter: boolean :=
is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned));
constant cnt_width: integer :=
size_of_uint(period_floor, power_of_2_counter);
constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned);
constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned);
constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned);
signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0');
signal ce_vec : std_logic_vector(num_pipeline_regs downto 0);
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of ce_vec:signal is "REDUCE";
signal ce_vec_logic : std_logic_vector(num_pipeline_regs downto 0);
attribute MAX_FANOUT of ce_vec_logic:signal is "REDUCE";
signal internal_ce: std_logic_vector(0 downto 0);
signal internal_ce_logic: std_logic_vector(0 downto 0);
signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0);
begin
clk <= sysclk;
clr <= sysclr;
cntr_gen: process(sysclk)
begin
if sysclk'event and sysclk = '1' then
if (sysce = '1') then
if ((cnt_clr_dly(0) = '1') or (sysclr = '1')) then
clk_num <= (others => '0');
else
clk_num <= clk_num + 1;
end if;
end if;
end if;
end process;
clr_gen: process(clk_num, sysclr)
begin
if power_of_2_counter then
cnt_clr(0) <= sysclr;
else
if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1
or sysclr = '1') then
cnt_clr(0) <= '1';
else
cnt_clr(0) <= '0';
end if;
end if;
end process;
clr_reg: synth_reg_w_init
generic map (
width => 1,
init_index => 0,
init_value => b"0000",
latency => 1
)
port map (
i => cnt_clr,
ce => sysce,
clr => sysclr,
clk => sysclk,
o => cnt_clr_dly
);
pipelined_ce : if period > 1 generate
ce_gen: process(clk_num)
begin
if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then
ce_vec(num_pipeline_regs) <= '1';
else
ce_vec(num_pipeline_regs) <= '0';
end if;
end process;
ce_pipeline: for index in num_pipeline_regs downto 1 generate
ce_reg : synth_reg_w_init
generic map (
width => 1,
init_index => ce_reg_init_val(index, period),
init_value => b"0000",
latency => 1
)
port map (
i => ce_vec(index downto index),
ce => sysce,
clr => sysclr,
clk => sysclk,
o => ce_vec(index-1 downto index-1)
);
end generate;
internal_ce <= ce_vec(0 downto 0);
end generate;
pipelined_ce_logic: if period > 1 generate
ce_gen_logic: process(clk_num)
begin
if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then
ce_vec_logic(num_pipeline_regs) <= '1';
else
ce_vec_logic(num_pipeline_regs) <= '0';
end if;
end process;
ce_logic_pipeline: for index in num_pipeline_regs downto 1 generate
ce_logic_reg : synth_reg_w_init
generic map (
width => 1,
init_index => ce_reg_init_val(index, period),
init_value => b"0000",
latency => 1
)
port map (
i => ce_vec_logic(index downto index),
ce => sysce,
clr => sysclr,
clk => sysclk,
o => ce_vec_logic(index-1 downto index-1)
);
end generate;
internal_ce_logic <= ce_vec_logic(0 downto 0);
end generate;
use_bufg_true: if period > 1 and use_bufg = 1 generate
ce_bufg_inst: bufg
port map (
i => internal_ce(0),
o => ce
);
ce_bufg_inst_logic: bufg
port map (
i => internal_ce_logic(0),
o => ce_logic
);
end generate;
use_bufg_false: if period > 1 and (use_bufg = 0) generate
ce <= internal_ce(0);
ce_logic <= internal_ce_logic(0);
end generate;
generate_system_clk: if period = 1 generate
ce <= sysce;
ce_logic <= sysce;
end generate;
end architecture behavior;
| lgpl-3.0 | a00ce8cc9093250cf22cd327aa66f8cb | 0.617895 | 3.861951 | false | false | false | false |
SoCdesign/EHA | RTL/Hand_Shaking/Checkers/Control_part_checkers/Handshaking_FC/LBDR_checkers/RTL_and_Synthesis/LBDR_with_checkers_top.vhd | 1 | 7,834 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_with_checkers_top is
generic (
cur_addr_rst: integer := 5;
Rxy_rst: integer := 60;
Cx_rst: integer := 15;
NoC_size: integer := 4
);
port ( empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
-- LBDR outputs
N1_out, E1_out, W1_out, S1_out: out std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: out std_logic;
-- Checker outputs
err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in : out std_logic
);
end LBDR_with_checkers_top;
architecture behavior of LBDR_with_checkers_top is
component LBDR_pseudo is
generic (
cur_addr_rst: integer := 5;
Rxy_rst: integer := 60;
Cx_rst: integer := 15;
NoC_size: integer := 4
);
port ( empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
N1_out, E1_out, W1_out, S1_out: out std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: out std_logic
);
end component;
component LBDR_checkers is
generic (
cur_addr_rst: integer := 5;
NoC_size: integer := 4
);
port ( empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic;
N1_out, E1_out, W1_out, S1_out: in std_logic;
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
-- Checker outputs
err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in : out std_logic
);
end component;
signal Req_N_in_sig, Req_E_in_sig, Req_W_in_sig, Req_S_in_sig, Req_L_in_sig: std_logic;
signal N1_out_sig, E1_out_sig, W1_out_sig, S1_out_sig: std_logic;
begin
Req_N_in <= Req_N_in_sig;
Req_E_in <= Req_E_in_sig;
Req_W_in <= Req_W_in_sig;
Req_S_in <= Req_S_in_sig;
Req_L_in <= Req_L_in_sig;
N1_out <= N1_out_sig;
E1_out <= E1_out_sig;
W1_out <= W1_out_sig;
S1_out <= S1_out_sig;
-- LBDR instantiation
LBDR: LBDR_pseudo generic map (cur_addr_rst => 5, Rxy_rst => 60, Cx_rst => 15, NoC_size => 4)
port map (
empty=>empty,
flit_type=>flit_type,
dst_addr=>dst_addr,
Req_N_FF=>Req_N_FF,
Req_E_FF=>Req_E_FF,
Req_W_FF=>Req_W_FF,
Req_S_FF=>Req_S_FF,
Req_L_FF=>Req_L_FF,
N1_out => N1_out_sig,
E1_out => E1_out_sig,
W1_out => W1_out_sig,
S1_out => S1_out_sig,
Req_N_in=>Req_N_in_sig,
Req_E_in=>Req_E_in_sig,
Req_W_in=>Req_W_in_sig,
Req_S_in=>Req_S_in_sig,
Req_L_in=>Req_L_in_sig
);
-- Checkers instantiation
CHECKERS: LBDR_checkers generic map (cur_addr_rst => 5, NoC_size => 4)
port map (empty=>empty, flit_type=>flit_type,
Req_N_FF=>Req_N_FF,
Req_E_FF=>Req_E_FF,
Req_W_FF=>Req_W_FF,
Req_S_FF=>Req_S_FF,
Req_L_FF=>Req_L_FF,
Req_N_in=>Req_N_in_sig,
Req_E_in=>Req_E_in_sig,
Req_W_in=>Req_W_in_sig,
Req_S_in=>Req_S_in_sig,
Req_L_in=>Req_L_in_sig,
N1_out => N1_out_sig,
E1_out => E1_out_sig,
W1_out => W1_out_sig,
S1_out => S1_out_sig,
dst_addr => dst_addr,
err_header_not_empty_Requests_in_onehot => err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in => err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in => err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => err_header_not_empty_Req_S_in
);
end behavior; | gpl-3.0 | b029f83c58cb4a2712dff913c95f4c69 | 0.471917 | 3.13988 | false | false | false | false |
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| gpl-3.0 | 10cea5f4c94848826e22f1a4407b70e9 | 0.953963 | 1.831086 | false | false | false | false |
Hyvok/HardHeat | sim/ds18b20/ds18b20_tb.vhd | 1 | 4,871 | library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.utils_pkg.all;
entity ds18b20_tb is
end entity;
architecture rtl of ds18b20_tb is
-- Main clock frequency 100 MHz
constant CLK_PERIOD : time := 1 sec / 10e7;
-- Conversion interval in clock cycles
constant CONV_INTERVAL : natural := 750000;
constant TEST_TEMP : std_logic_vector(15 downto 0) := x"0031";
type data_t is array(natural range <>) of std_logic_vector(8 - 1 downto 0);
constant TEST_DATA : data_t(9 - 1 downto 0) :=
(x"31", x"00", x"4B", x"46", x"FF", x"FF", x"02", x"10", x"72");
signal clk : std_logic := '0';
signal reset : std_logic;
signal reset_ow : std_logic;
signal ow_in : std_logic;
signal ow_out : std_logic;
signal data_in : std_logic_vector(8 - 1 downto 0);
signal data_in_f : std_logic;
signal receive_data_f : std_logic;
signal busy : std_logic;
signal data_out : std_logic_vector(8 - 1 downto 0);
signal data_out_f : std_logic;
signal err : std_logic;
signal err_id : unsigned(1 downto 0);
signal temp : signed(16 - 1 downto 0);
signal temp_f : std_logic;
signal temp_error : std_logic;
signal crc : std_logic_vector(8 - 1 downto 0);
signal pullup : std_logic;
-- Signals internal to the test bench
signal conv : std_logic;
begin
reset <= '1', '0' after 500 ns;
clk_gen: process(clk)
begin
clk <= not clk after CLK_PERIOD / 2;
end process;
-- Perform temperature reading at predefined intervals
conv_p: process(clk, reset)
variable timer : unsigned(ceil_log2(CONV_INTERVAL) downto 0);
begin
if reset = '1' then
timer := to_unsigned(CONV_INTERVAL, timer'length);
conv <= '0';
elsif rising_edge(clk) then
conv <= '0';
if timer < CONV_INTERVAL then
timer := timer + 1;
else
conv <= '1';
timer := (others => '0');
end if;
end if;
end process;
-- Verify CRC after doing one full conversion
assert_crc: process(temp_f)
begin
if rising_edge(temp_f) then
assert crc = x"00" report "CRC error!" severity failure;
end if;
end process;
-- Verify we do not encounter a temp error
process(clk, reset)
begin
if rising_edge(clk) and not reset = '1' then
assert temp_error = '0' report "Temp error!" severity failure;
end if;
end process;
DUT_inst: entity work.ds18b20(rtl)
generic map
(
-- Use a small 1ms conversion delay to not make simulation take long
CONV_DELAY_VAL => 100000
)
port map
(
clk => clk,
reset => reset,
conv_in_f => conv,
data_in => data_out,
data_in_f => data_out_f,
busy_in => busy,
error_in => err,
error_id_in => err_id,
reset_ow_out => reset_ow,
data_out => data_in,
data_out_f => data_in_f,
receive_data_out_f => receive_data_f,
temp_out => temp,
temp_out_f => temp_f,
crc_in => crc,
temp_error_out => temp_error,
pullup_out => pullup
);
ow_p: entity work.one_wire(rtl)
generic map
(
US_D => 100
)
port map
(
clk => clk,
reset => reset,
reset_ow => reset_ow,
ow_in => ow_in,
data_in => data_in,
data_in_f => data_in_f,
receive_data_f => receive_data_f,
ow_out => ow_out,
error_out => err,
error_id_out => err_id,
busy_out => busy,
data_out => data_out,
data_out_f => data_out_f,
crc_out => crc
);
data_gen: entity work.ds18b20_data_gen(rtl)
generic map
(
MICROSECOND_D => 100
)
port map
(
clk => clk,
reset => reset,
ow_in => ow_in,
ow_out => ow_out,
temp_in => signed(TEST_TEMP),
temp_in_f => '0'
);
-- Make sure pullup is not active when bus is pulled low
assert not (ow_out = '0' and pullup = '0')
report "Pullup active when bus pulled down!" severity warning;
end;
| mit | d4136a11cbba260ff4e094a747db4074 | 0.476494 | 3.796571 | false | false | false | false |
iamllama/EE2020 | ee2020.ip_user_files/ipstatic/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd | 1 | 94,635 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 67920)
`protect data_block
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`protect end_protected
| gpl-3.0 | 12b2048efcd90d3ecc3a61e17acc0108 | 0.951889 | 1.839645 | false | false | false | false |
Hyvok/HardHeat | sim/lock_detector/lock_detector_tb.vhd | 1 | 847 | library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lock_detector_tb is
end entity;
architecture rtl of lock_detector_tb is
-- Clock frequency 100 MHz
constant CLK_PERIOD : time := 1 sec / 10e7;
signal clk : std_logic := '0';
signal reset : std_logic;
begin
DUT_inst: entity work.lock_detector(rtl)
generic map
(
PHASE_TIME_IN_N => 12,
LOCK_COUNT_N => 8,
ULOCK_COUNT_N => 8,
LOCK_LIMIT => 100
)
port map
(
clk => clk,
reset => reset,
phase_time_in => to_signed(0, 13)
);
reset <= '1', '0' after 500 ns;
clk_gen: process(clk)
begin
clk <= not clk after CLK_PERIOD / 2;
end process;
end;
| mit | c7d4afd3c3315343881c0a5038a2f73b | 0.507674 | 3.529167 | false | false | false | false |
cafe-alpha/wasca | fpga_firmware/sniff_fifo.vhd | 1 | 7,068 | -- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: scfifo
-- ============================================================
-- File Name: sniff_fifo.vhd
-- Megafunction Name(s):
-- scfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 15.1.0 Build 185 10/21/2015 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus Prime License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY sniff_fifo IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
usedw : OUT STD_LOGIC_VECTOR (10 DOWNTO 0)
);
END sniff_fifo;
ARCHITECTURE SYN OF sniff_fifo IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (10 DOWNTO 0);
COMPONENT scfifo
GENERIC (
add_ram_output_register : STRING;
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
underflow_checking : STRING;
use_eab : STRING
);
PORT (
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
usedw : OUT STD_LOGIC_VECTOR (10 DOWNTO 0)
);
END COMPONENT;
BEGIN
empty <= sub_wire0;
full <= sub_wire1;
q <= sub_wire2(15 DOWNTO 0);
usedw <= sub_wire3(10 DOWNTO 0);
scfifo_component : scfifo
GENERIC MAP (
add_ram_output_register => "OFF",
intended_device_family => "MAX 10",
lpm_numwords => 2048,
lpm_showahead => "ON",
lpm_type => "scfifo",
lpm_width => 16,
lpm_widthu => 11,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
PORT MAP (
clock => clock,
data => data,
rdreq => rdreq,
wrreq => wrreq,
empty => sub_wire0,
full => sub_wire1,
q => sub_wire2,
usedw => sub_wire3
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Depth NUMERIC "2048"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: Width NUMERIC "16"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "16"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
-- Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
-- Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: usedw 0 0 11 0 OUTPUT NODEFVAL "usedw[10..0]"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
-- Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
-- Retrieval info: CONNECT: usedw 0 0 11 0 @usedw 0 0 11 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL sniff_fifo.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sniff_fifo.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sniff_fifo.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sniff_fifo.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sniff_fifo_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-2.0 | f5730cd54434b6f1961f79f5e1cdf67d | 0.666242 | 3.534 | false | false | false | false |
Hyvok/HardHeat | src/rpm_counter.vhd | 1 | 2,028 | library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rpm_counter is
generic
(
BITS_N : positive;
MIN_RPM_LIM : natural;
DEBOUNCE_D : natural
);
port
(
clk : in std_logic;
reset : in std_logic;
rpm_in : in std_logic;
rpm_out : out unsigned(BITS_N - 1 downto 0);
rpm_out_f : out std_logic;
fault_out : out std_logic
);
end entity;
architecture rtl of rpm_counter is
signal rpm : std_logic;
begin
debounce_p: entity work.debounce(rtl)
generic map
(
DEBOUNCE_D => DEBOUNCE_D,
FLIPFLOPS_N => 5
)
port map
(
clk => clk,
reset => reset,
sig_in => rpm_in,
sig_out => rpm
);
rpm_p: process(clk, reset)
variable counter : unsigned(BITS_N - 1 downto 0);
variable last_state : std_logic;
begin
if reset = '1' then
rpm_out <= (others => '0');
fault_out <= '0';
rpm_out_f <= '0';
counter := (others => '0');
last_state := '0';
elsif rising_edge(clk) then
rpm_out_f <= '0';
-- Indicate a fault if counter reaches maximum value
if counter = 2**counter'length - 1 then
fault_out <= '1';
else
counter := counter + 1;
end if;
if not rpm = last_state and rpm = '1' then
if counter > MIN_RPM_LIM then
fault_out <= '1';
else
fault_out <= '0';
end if;
rpm_out <= counter;
rpm_out_f <= '1';
counter := (others => '0');
end if;
last_state := rpm;
end if;
end process;
end;
| mit | c077fa8a7c851401c11c462f639beac6 | 0.419132 | 4.047904 | false | false | false | false |
JeremySavonet/Eurobot-2017-Moon-Village | software/HPS_FPGA_LED/fpga/robot_layer_2.vhd | 1 | 14,902 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.types_pkg.all;
use work.robot_layer_2_pkg.all;
entity robot_layer_2 is
generic (
CLK_FREQUENCY_HZ : positive;
RegCnt : positive
);
port (
clk : in std_logic;
reset : in std_logic;
regs_data_in_value : out std_logic_vector(RegCnt*32-1 downto 0) := (others => '0');
regs_data_in_read : in std_logic_vector(RegCnt-1 downto 0);
regs_data_out_value : in std_logic_vector(RegCnt*32-1 downto 0);
regs_data_out_write : in std_logic_vector(RegCnt-1 downto 0);
---------------------------------
-------- TO/FROM LAYER 1 --------
---------------------------------
--------- UART ----------
uart_tx : out std_logic_vector(4-1 downto 0);
uart_rx : in std_logic_vector(4-1 downto 0);
motor_value : out int16_t(MOTOR_COUNT-1 downto 0);
motor_current : in int24_t(MOTOR_COUNT-1 downto 0);
motor_fault : in std_logic_vector(MOTOR_COUNT-1 downto 0);
qei_value : in int16_t(QEI_COUNT-1 downto 0);
qei_ref : in std_logic_vector(QEI_COUNT-1 downto 0);
---------------------------------
-------- TO/FROM LAYER 3 --------
---------------------------------
sum_m_dist : out std_logic_vector(32-1 downto 0);
sum_m_angle : out std_logic_vector(32-1 downto 0);
sum_c_dist : out std_logic_vector(32-1 downto 0);
sum_c_angle : out std_logic_vector(32-1 downto 0);
pos_valid : out std_logic;
pos_id : out std_logic_vector(8-1 downto 0);
pos_teta : out std_logic_vector(16-1 downto 0);
pos_x : out std_logic_vector(16-1 downto 0);
pos_y : out std_logic_vector(16-1 downto 0);
pos_sum_dist : out std_logic_vector(32-1 downto 0);
pos_sum_angle : out std_logic_vector(32-1 downto 0);
dist_en : in std_logic;
dist_acc : in std_logic_vector(32-1 downto 0);
dist_speed : in std_logic_vector(32-1 downto 0);
dist_target : in std_logic_vector(32-1 downto 0);
angle_en : in std_logic;
angle_acc : in std_logic_vector(32-1 downto 0);
angle_speed : in std_logic_vector(32-1 downto 0);
angle_target : in std_logic_vector(32-1 downto 0)
);
end entity;
architecture rtl of robot_layer_2 is
component system is
port (
clk_clk : in std_logic := 'X'; -- clk
pio_data_in_value : in std_logic_vector(511 downto 0) := (others => 'X'); -- data_in_value
pio_data_in_read : out std_logic_vector(15 downto 0); -- data_in_read
pio_data_out_value : out std_logic_vector(511 downto 0); -- data_out_value
pio_data_out_write : out std_logic_vector(15 downto 0); -- data_out_write
reset_reset_n : in std_logic := 'X'; -- reset_n
uart_0_external_rxd : in std_logic := 'X'; -- rxd
uart_0_external_txd : out std_logic -- txd
);
end component system;
signal w_reset_n : std_logic;
signal w_regs_data_in_value : std_logic_vector(RegCnt*32-1 downto 0);
signal w_regs_data_in_value_mask : std_logic_vector(RegCnt*4-1 downto 0) := (others=>'0');
-- constant MSG_SIZE : natural := 1+2+4*2+2+2;
-- signal r_uart_tx_data : std_logic_vector(MSG_SIZE*8-1 downto 0);
-- signal w_uart_tx_valid : std_logic;
-- signal w_uart_tx_busy : std_logic;
signal w_odo_output : int32_t(2-1 downto 0);
constant PID_COUNT : natural := 3;
signal w_pid_en : std_logic_vector(PID_COUNT-1 downto 0);
signal w_pid_acc : int32_t(PID_COUNT-1 downto 0);
signal w_pid_speed : int32_t(PID_COUNT-1 downto 0);
signal w_pid_target : int32_t(PID_COUNT-1 downto 0);
signal w_pid_measure : int32_t(PID_COUNT-1 downto 0);
signal w_pid_output : int32_t(PID_COUNT-1 downto 0);
begin
w_reset_n <= not reset;
--! we return for read the same written data, expect for some bytes (noted masked) where we compute the value internally
g_reg: for i in 0 to w_regs_data_in_value_mask'length-1 generate
regs_data_in_value((i+1)*8-1 downto i*8) <= regs_data_out_value((i+1)*8-1 downto i*8) when w_regs_data_in_value_mask(i) = '0' else w_regs_data_in_value((i+1)*8-1 downto i*8);
end generate;
b_odometry: block
signal w_pio_data_in_value : std_logic_vector(511 downto 0) := (others=>'0');
signal w_pio_data_in_read : std_logic_vector(15 downto 0);
signal w_pio_data_out_value : std_logic_vector(511 downto 0);
signal w_pio_data_out_write : std_logic_vector(15 downto 0);
constant REGS_ODO_OUT_OFFSET : natural := 8;
begin
w_regs_data_in_value_mask((1+2)*4-1 downto (0+2)*4) <= "0011";
w_regs_data_in_value_mask((6+9)*4-1 downto (0+9)*4) <= (others=>'1');
p_async: process(regs_data_out_value,w_pio_data_out_value,qei_value) is
begin
w_pio_data_in_value(1*32-1 downto 0*32) <= X"00000000";
w_pio_data_in_value((1+13)*32-1 downto 1*32) <= regs_data_out_value((2+13)*32-1 downto 2*32);
--! we override the values for register 9 & 10 to give QEI inputs
w_pio_data_in_value((8+2)*32-1 downto 8*32) <= qei_value(3) & qei_value(2) & qei_value(1) & qei_value(0);
w_regs_data_in_value((8+8)*32-1 downto (0+8)*32) <= w_pio_data_out_value((8+7)*32-1 downto (0+7)*32);
end process;
w_odo_output(0) <= w_pio_data_out_value((1+REGS_ODO_OUT_OFFSET)*32-1 downto (0+REGS_ODO_OUT_OFFSET)*32); --! distance
w_odo_output(1) <= w_pio_data_out_value((2+REGS_ODO_OUT_OFFSET)*32-1 downto (1+REGS_ODO_OUT_OFFSET)*32); --! angle
sum_m_dist <= w_pio_data_out_value((1+REGS_ODO_OUT_OFFSET)*32-1 downto (0+REGS_ODO_OUT_OFFSET)*32);
sum_m_angle <= w_pio_data_out_value((2+REGS_ODO_OUT_OFFSET)*32-1 downto (1+REGS_ODO_OUT_OFFSET)*32);
sum_c_dist <= w_pio_data_out_value((3+REGS_ODO_OUT_OFFSET)*32-1 downto (2+REGS_ODO_OUT_OFFSET)*32);
sum_c_angle <= w_pio_data_out_value((4+REGS_ODO_OUT_OFFSET)*32-1 downto (3+REGS_ODO_OUT_OFFSET)*32);
pos_valid <= std_norm_range(w_pio_data_out_value((5+REGS_ODO_OUT_OFFSET)*32-1 downto (4+REGS_ODO_OUT_OFFSET)*32))(0);
pos_id <= std_norm_range(w_pio_data_out_value((5+REGS_ODO_OUT_OFFSET)*32-1 downto (4+REGS_ODO_OUT_OFFSET)*32))(16-1 downto 8);
pos_teta <= std_norm_range(w_pio_data_out_value((5+REGS_ODO_OUT_OFFSET)*32-1 downto (4+REGS_ODO_OUT_OFFSET)*32))(32-1 downto 16);
pos_x <= std_norm_range(w_pio_data_out_value((6+REGS_ODO_OUT_OFFSET)*32-1 downto (5+REGS_ODO_OUT_OFFSET)*32))(16-1 downto 0);
pos_y <= std_norm_range(w_pio_data_out_value((6+REGS_ODO_OUT_OFFSET)*32-1 downto (5+REGS_ODO_OUT_OFFSET)*32))(32-1 downto 16);
pos_sum_dist <= w_pio_data_out_value((7+REGS_ODO_OUT_OFFSET)*32-1 downto (6+REGS_ODO_OUT_OFFSET)*32);
pos_sum_angle <= w_pio_data_out_value((8+REGS_ODO_OUT_OFFSET)*32-1 downto (7+REGS_ODO_OUT_OFFSET)*32);
--! disable warnings
assert w_pio_data_in_read = w_pio_data_in_read;
assert w_pio_data_out_write = w_pio_data_out_write;
inst_odometry_rv : component system
port map (
clk_clk => clk,
reset_reset_n => w_reset_n,
pio_data_in_value => w_pio_data_in_value,
pio_data_in_read => w_pio_data_in_read,
pio_data_out_value => w_pio_data_out_value,
pio_data_out_write => w_pio_data_out_write,
uart_0_external_rxd => uart_rx(0),
uart_0_external_txd => uart_tx(0)
);
end block;
b_carroussel: block
signal r_position : std_logic_vector(32-1 downto 0);
signal r_ref : std_logic_vector(32-1 downto 0);
signal r_qei_last : std_logic_vector(16-1 downto 0);
constant REGS_CARROUSSEL_REF_OFFSET : natural := 48;
begin
w_regs_data_in_value_mask((REGS_CARROUSSEL_REF_OFFSET+1)*4-1 downto (REGS_CARROUSSEL_REF_OFFSET)*4) <= (others=>'1');
w_regs_data_in_value((REGS_CARROUSSEL_REF_OFFSET+1)*32-1 downto (REGS_CARROUSSEL_REF_OFFSET)*32) <= r_ref;
p_sync: process(clk,reset) is
variable v_diff : integer;
begin
if reset = '1' then
r_position <= (others=>'0');
r_ref <= (others=>'0');
r_qei_last <= (others=>'0');
elsif rising_edge(clk) then
r_qei_last <= qei_value(4);
if qei_value(4) /= r_qei_last then
v_diff := to_integer(unsigned(qei_value(4)))-to_integer(unsigned(r_qei_last));
if v_diff >= 2**15 then
v_diff := v_diff - 2**16;
end if;
if v_diff <= -2**15 then
v_diff := v_diff + 2**16;
end if;
r_position <= std_logic_vector(signed(r_position)+to_signed(v_diff,32));
end if;
if qei_ref(4) = '1' then
r_ref <= r_position;
end if;
end if;
end process;
w_pid_measure(2) <= r_position;
end block;
w_pid_measure(0) <= w_odo_output(0);
w_pid_measure(1) <= w_odo_output(1);
w_pid_en(0) <= dist_en;
w_pid_acc(0) <= dist_acc;
w_pid_speed(0) <= dist_speed;
w_pid_target(0) <= dist_target;
w_pid_en(1) <= angle_en;
w_pid_acc(1) <= angle_acc;
w_pid_speed(1) <= angle_speed;
w_pid_target(1) <= angle_target;
--! not used from Layer 3, override from sw needed to control it
w_pid_en(2) <= '0';
w_pid_acc(2) <= (others=>'0');
w_pid_speed(2) <= (others=>'0');
w_pid_target(2) <= (others=>'0');
b_motor_pid: block
begin
g_motor: for i in 0 to PID_COUNT-1 generate
constant REG_COUNT : natural := 11;
constant REG_INDEX : natural := 15+REG_COUNT*i;
constant REG_MEASURE_INDEX : natural := 9;
constant REG_OUTPUT_INDEX : natural := 11;
signal w_pio_data_in_value : std_logic_vector(511 downto 0) := (others=>'0');
signal w_pio_data_in_read : std_logic_vector(15 downto 0);
signal w_pio_data_out_value : std_logic_vector(511 downto 0);
signal w_pio_data_out_write : std_logic_vector(15 downto 0);
signal w_pid_override : std_logic;
begin
w_regs_data_in_value_mask((1+REG_INDEX)*4-1 downto (REG_INDEX)*4) <= "0011";
w_regs_data_in_value_mask((REG_COUNT+REG_INDEX)*4-1 downto (1+REG_INDEX)*4) <= (others=>'1');
w_pid_override <= std_norm_range(regs_data_out_value((REG_INDEX+2)*32-1 downto (REG_INDEX+1)*32))(8);
p_async: process(regs_data_out_value,w_pio_data_out_value,w_pid_measure,w_pid_override) is
begin
--! in the case the measure is uint32_t instead of float, arg[0] = 1
if i /= 3-1 then
w_pio_data_in_value(1*32-1 downto 0*32) <= X"00000100";
else
w_pio_data_in_value(1*32-1 downto 0*32) <= X"00010100";
end if;
w_pio_data_in_value((1+REG_COUNT)*32-1 downto 1*32) <= regs_data_out_value((REG_INDEX+REG_COUNT)*32-1 downto REG_INDEX*32);
if w_pid_override = '0' then
w_pio_data_in_value(2*32+8-1 downto 2*32) <= "0000000" & w_pid_en(i);
w_pio_data_in_value(7*32-1 downto 6*32) <= w_pid_speed(i);
w_pio_data_in_value(8*32-1 downto 7*32) <= w_pid_acc(i);
w_pio_data_in_value(11*32-1 downto 10*32) <= w_pid_target(i);
end if;
w_pio_data_in_value((REG_MEASURE_INDEX+1)*32-1 downto REG_MEASURE_INDEX*32) <= w_pid_measure(i);
w_regs_data_in_value((REG_INDEX+REG_MEASURE_INDEX)*32-1 downto (REG_INDEX+REG_MEASURE_INDEX-1)*32) <= w_pid_measure(i);
end process;
w_pid_output(i) <= w_pio_data_out_value((REG_OUTPUT_INDEX+1)*32-1 downto REG_OUTPUT_INDEX*32);
--! disable warnings
assert w_pio_data_in_read = w_pio_data_in_read;
assert w_pio_data_out_write = w_pio_data_out_write;
inst_motor_pid_rv : component system
port map (
clk_clk => clk,
reset_reset_n => w_reset_n,
pio_data_in_value => w_pio_data_in_value,
pio_data_in_read => w_pio_data_in_read,
pio_data_out_value => w_pio_data_out_value,
pio_data_out_write => w_pio_data_out_write,
uart_0_external_rxd => uart_rx(i+1),
uart_0_external_txd => uart_tx(i+1)
);
end generate;
end block;
p_async: process(w_pid_output) is
variable v_left,v_right : signed(16+1-1 downto 0);
begin
v_left := signed(w_pid_output(0)(31) & w_pid_output(0)(16-1 downto 0)) + signed(w_pid_output(1)(31) & w_pid_output(1)(16-1 downto 0));
v_right := signed(w_pid_output(0)(31) & w_pid_output(0)(16-1 downto 0)) - signed(w_pid_output(1)(31) & w_pid_output(1)(16-1 downto 0));
motor_value(0) <= std_logic_vector(v_left(16-1 downto 0));
motor_value(1) <= std_logic_vector(v_right(16-1 downto 0));
if v_left > 2**15-1 then
motor_value(0) <= std_logic_vector(to_signed(2**15-1,16));
end if;
if v_left < -2**15 then
motor_value(0) <= std_logic_vector(to_signed(-2**15-1,16));
end if;
if v_right > 2**15-1 then
motor_value(1) <= std_logic_vector(to_signed(2**15-1,16));
end if;
if v_right < -2**15 then
motor_value(1) <= std_logic_vector(to_signed(-2**15-1,16));
end if;
end process;
motor_value(2) <= w_pid_output(2)(31) & w_pid_output(2)(15-1 downto 0);
motor_value(3) <= (others=>'0');
motor_value(4) <= (others=>'0');
motor_value(5) <= (others=>'0');
end architecture;
| gpl-3.0 | 6ae0ec1cc715e701f0331254e5561bb9 | 0.526372 | 3.097485 | false | false | false | false |
summershrimp/VHDLClock | VHDLClock.vhd | 1 | 2,576 | Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
Library work;
use work.all;
Entity VHDLClock is
Port(
clk, ch, seth, setm:in std_logic;
houth, mouth:out std_logic_vector(2 downto 0);
houtl, moutl:out std_logic_vector(3 downto 0);
sout, bout, cstat:out std_logic
);
End Entity VHDLClock;
Architecture ArchVHDLClock of VHDLClock is
Component c42to1
Port(
A,B:in std_logic_vector(3 downto 0);
O: out std_logic_vector(3 downto 0);
en, ch: in std_logic
);
End Component;
Component c32to1
Port(
A,B:in std_logic_vector(2 downto 0);
O: out std_logic_vector(2 downto 0);
en, ch: in std_logic
);
End Component;
Component Alarm
Port(
hlow, mlow: out std_logic_vector(3 downto 0);
hhigh,mhigh: out std_logic_vector(2 downto 0);
en, hadd, madd: in std_logic
);
End Component;
Component Timer
Port(
clk, seth, setm: in std_logic;
ssig: out std_logic;
hsigh, msigh: out std_logic_vector(2 downto 0);
hsigl, msigl: out std_logic_vector(3 downto 0)
);
End Component;
Signal choice, tseth, tsetm, aseth, asetm:std_logic;
Signal thsigh, tmsigh, ahsigh, amsigh:std_logic_vector(2 downto 0);
Signal thsigl, tmsigl, ahsigl, amsigl:std_logic_vector(3 downto 0);
Signal en :std_logic;
Begin
en <= '1';
TT: Timer
Port Map(clk, tseth, tsetm ,sout, thsigh, tmsigh, thsigl, tmsigl);
AA: Alarm
Port Map(ahsigl, amsigl, ahsigh, amsigh, en, aseth, asetm);
Chlow: c42to1
Port Map(thsigl, ahsigl, houtl, en, choice);
Cmlow: c42to1
Port Map(tmsigl, amsigl, moutl, en, choice);
Chhigh: c32to1
Port Map(thsigh, ahsigh, houth, en, choice);
Cmhigh: c32to1
Port Map(tmsigh, amsigh, mouth, en, choice);
Process(clk, thsigh, tmsigh, ahsigh, amsigh, thsigl, tmsigl, ahsigl, amsigl)
Variable beepcount:integer range 0 to 31 :=0;
Variable bstat:std_logic := '0';
Begin
If clk'event and clk = '1' Then
If thsigh = ahsigh And thsigl = ahsigl And tmsigh = amsigh And tmsigl = amsigl And choice = '0'Then
beepcount := 30;
End If;
If beepcount > 0 Then
beepcount:= beepcount - 1;
bstat := not bstat;
End If;
If beepcount = 0 and bstat /= '0' Then
bstat := '0';
End If;
End If;
bout <= bstat;
End Process;
Process(clk, ch, seth, setm)
Begin
If ch'event and ch='0' Then
choice <= not choice;
End If;
If choice = '1' Then
aseth <= seth;
asetm <= setm;
Else
tseth <=seth;
tsetm <=setm;
End if;
cstat <= choice;
End Process;
End Architecture;
| gpl-2.0 | 32160f1d3c24883f7d96a2bc35647bbe | 0.648292 | 2.642051 | false | false | false | false |
zhlinh/vhdl_course | Assignment/IMG_LSB/IMG_LSB.vhd | 1 | 6,094 | --Top-Level Entity
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--使用自定义程序包
USE WORK.MYTYPE.ALL;
ENTITY IMG_LSB IS
PORT(CLK: IN STD_LOGIC;
RESET: IN STD_LOGIC;
R_IN: IN COLOR;
G_IN: IN COLOR;
B_IN: IN COLOR;
SEL: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
A_COL: IN COLOR;
A_ROW: IN COLOR;
B_COL: IN COLOR;
B_ROW: IN COLOR;
C_COL: IN COLOR;
C_ROW: IN COLOR;
R_OUT: OUT COLOR;
G_OUT: OUT COLOR;
B_OUT: OUT COLOR;
DETECT_RESULT: OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
XX: IN COLOR;
YY: IN COLOR;
ZZ: IN INTEGER RANGE 0 TO 2;
STR: IN STRING(1 TO 20);
HR_OUT: OUT COLOR;
HG_OUT: OUT COLOR;
HB_OUT: OUT COLOR;
STR_LEN: IN INTEGER RANGE 0 TO 8192;
CHAR_OUT: OUT CHARACTER);
END ENTITY IMG_LSB;
ARCHITECTURE ART OF IMG_LSB IS
COMPONENT CHOOSE
PORT(RESET: IN STD_LOGIC;
CLK: IN STD_LOGIC;
SEL: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
TO_TRANS: OUT STD_LOGIC;
TO_INSERT: OUT STD_LOGIC;
TO_DETECT: OUT STD_LOGIC;
TO_HIDE: OUT STD_LOGIC;
TO_UNHIDE: OUT STD_LOGIC);
END COMPONENT;
COMPONENT RGB2YUV
PORT(RESET: IN STD_LOGIC;
CLK: IN STD_LOGIC;
ENABLE: IN STD_LOGIC;
R_IN: IN COLOR;
G_IN: IN COLOR;
B_IN: IN COLOR;
Y_OUT: OUT COLOR;
U_OUT: OUT COLOR;
V_OUT: OUT COLOR);
END COMPONENT;
COMPONENT LSB_INSERT
PORT(ENABLE: IN STD_LOGIC;
CLK: IN STD_LOGIC;
RESET: IN STD_LOGIC;
Y_IN: IN COLOR;
U_IN: IN COLOR;
V_IN: IN COLOR;
A_COL: IN COLOR;
A_ROW: IN COLOR;
B_COL: IN COLOR;
B_ROW: IN COLOR;
C_COL: IN COLOR;
C_ROW: IN COLOR;
FIXED_Y_OUT: OUT COLOR;
U_OUT: OUT COLOR;
V_OUT: OUT COLOR);
END COMPONENT;
COMPONENT YUV2RGB
PORT(CLK: IN STD_LOGIC;
RESET: IN STD_LOGIC;
FIXED_Y_IN: IN COLOR;
U_IN: IN COLOR;
V_IN: IN COLOR;
R_OUT: OUT COLOR;
G_OUT: OUT COLOR;
B_OUT: OUT COLOR);
END COMPONENT;
COMPONENT LSB_DETECT
PORT(ENABLE: IN STD_LOGIC;
CLK: IN STD_LOGIC;
RESET: IN STD_LOGIC;
Y_IN: IN COLOR;
RESULT: OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END COMPONENT;
COMPONENT HIDE_STR
PORT(CLK: IN STD_LOGIC;
RESET: IN STD_LOGIC;
ENABLE: IN STD_LOGIC;
R_IN: IN COLOR;
G_IN: IN COLOR;
B_IN: IN COLOR;
XX: IN COLOR;
YY: IN COLOR;
ZZ: IN INTEGER RANGE 0 TO 2;
STR: IN STRING;
HR_OUT: OUT COLOR;
HG_OUT: OUT COLOR;
HB_OUT: OUT COLOR);
END COMPONENT;
COMPONENT UNHIDE_STR
PORT(CLK: IN STD_LOGIC;
RESET: IN STD_LOGIC;
ENABLE: IN STD_LOGIC;
R_IN: IN COLOR;
G_IN: IN COLOR;
B_IN: IN COLOR;
XX: IN COLOR;
YY: IN COLOR;
ZZ: IN INTEGER RANGE 0 TO 2;
STR_LEN: IN INTEGER RANGE 0 TO 8192;
CHAR_OUT: OUT CHARACTER);
END COMPONENT;
SIGNAL TOIN_MID1: STD_LOGIC;
SIGNAL TODE_MID1: STD_LOGIC;
SIGNAL TOTR_MID1: STD_LOGIC;
SIGNAL TOHI_MID1: STD_LOGIC;
SIGNAL TOUN_MID1: STD_LOGIC;
SIGNAL Y_MID2: COLOR;
SIGNAL U_MID2: COLOR;
SIGNAL V_MID2: COLOR;
SIGNAL FIX_Y_MID3: COLOR;
SIGNAL U_MID3: COLOR;
SIGNAL V_MID3: COLOR;
BEGIN
INST_CHOOSE: CHOOSE PORT MAP(
CLK=>CLK,
RESET=>RESET,
SEL=>SEL,
TO_INSERT=>TOIN_MID1,
TO_DETECT=>TODE_MID1,
TO_TRANS=>TOTR_MID1,
TO_HIDE=>TOHI_MID1,
TO_UNHIDE=>TOUN_MID1
);
INST_RGB2YUV: RGB2YUV PORT MAP(
CLK=>CLK,
RESET=>RESET,
ENABLE=>TOTR_MID1,
R_IN=>R_IN,
B_IN=>B_IN,
G_IN=>G_IN,
Y_OUT=>Y_MID2,
U_OUT=>U_MID2,
V_OUT=>V_MID2
);
INST_LSB_INSERT: LSB_INSERT PORT MAP(
CLK=>CLK,
RESET=>RESET,
ENABLE=>TOIN_MID1,
Y_IN=>Y_MID2,
U_IN=>U_MID2,
V_IN=>V_MID2,
A_COL=>A_COL,
A_ROW=>A_ROW,
B_COL=>B_COL,
B_ROW=>B_ROW,
C_COL=>C_COL,
C_ROW=>C_ROW,
FIXED_Y_OUT=>FIX_Y_MID3,
U_OUT=>U_MID3,
V_OUT=>V_MID3
);
INST_YUV2RGB: YUV2RGB PORT MAP(
CLK=>CLK,
RESET=>RESET,
FIXED_Y_IN=>FIX_Y_MID3,
U_IN=>U_MID3,
V_IN=>V_MID3,
R_OUT=>R_OUT,
G_OUT=>G_OUT,
B_OUT=>B_OUT
);
INST_LSB_DETECT: LSB_DETECT PORT MAP(
CLK=>CLK,
RESET=>RESET,
ENABLE=>TODE_MID1,
Y_IN=>Y_MID2,
RESULT=>DETECT_RESULT
);
INST_HIDE_STR: HIDE_STR PORT MAP(
CLK=>CLK,
RESET=>RESET,
ENABLE=>TOHI_MID1,
R_IN=>R_IN,
G_IN=>G_IN,
B_IN=>B_IN,
XX=>XX,
YY=>YY,
ZZ=>ZZ,
STR=>STR,
HR_OUT=>HR_OUT,
HG_OUT=>HG_OUT,
HB_OUT=>HB_OUT
);
INST_UNHIDE_STR: UNHIDE_STR PORT MAP(
CLK=>CLK,
RESET=>RESET,
ENABLE=>TOUN_MID1,
R_IN=>R_IN,
G_IN=>G_IN,
B_IN=>B_IN,
XX=>XX,
YY=>YY,
ZZ=>ZZ,
STR_LEN=>STR_LEN,
CHAR_OUT=>CHAR_OUT
);
END ARCHITECTURE ART;
| apache-2.0 | 8a716cd5044c6c91bc4c7ad1f7dd88f8 | 0.448667 | 3.501152 | false | false | false | false |
upci/upci | Simulações/testes_memoria/memory.vhd | 1 | 2,972 | ---- Memory ------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.processor_functions.all;
------------------------------------------------------------------------------------------------------------------
ENTITY memory IS
PORT (clk, nrst: IN STD_LOGIC; -- reset ativo em zero
MDR_load: IN STD_LOGIC; -- sinal de carregamento do BUS para MDR
MAR_load: IN STD_LOGIC; -- sinal de carregamento do BUS para MAR
MEM_valid: IN STD_LOGIC; -- sinal que indica que o resultado da MDR deve ser colocado em MEM_bus (ou Z se 0)
MEM_en: IN STD_LOGIC; -- ativacao da memorica para operacoes de leitura e escrita
MEM_rw: IN STD_LOGIC; -- flag que indica se a operacao a ser realizada eh de leitura ou escrita
MEM_bus: INOUT STD_LOGIC_VECTOR(n-1 DOWNTO 0)); -- barramento de entrada/saida
END ENTITY memory;
------------------------------------------------------------------------------------------------------------------
ARCHITECTURE rtl OF memory IS
SIGNAL mdr: STD_LOGIC_VECTOR(wordlen-1 DOWNTO 0); -- registrador de dados
SIGNAL mar: UNSIGNED(wordlen-oplen-1 DOWNTO 0); -- registrador de enderecos
BEGIN
-- Se o MEM_valid = '1', manda o valor do resultado do MDR pro barramento. Caso contrario, manda Z.
MEM_bus <= mdr
WHEN MEM_valid = '1'
ELSE (others => 'Z');
PROCESS (clk, nrst) IS
VARIABLE contents: memory_array; -- conteudo da memoria
-- Definicao do valor padrao da memoria (para simular ROM com programa)
CONSTANT program: memory_array := (0 => "000000000011",
1 => "001000000100",
2 => "000100000101",
3 => "000000001100",
4 => "000000000011",
5 => "000000000000" ,
OTHERS => (OTHERS => '0'));
BEGIN
-- De forma assincrona, se o reset ficar em nivel 0, reseta os registradores e conteudo da memoria
IF nrst = '0' THEN
mdr <= (OTHERS => '0');
mar <= (OTHERS => '0');
contents := program;
-- Se teve uma borda de subida no clock, faz as outras coisas
ELSIF (clk'EVENT AND clk='1') THEN
-- A ordem de prioridade eh: Carregamento do MAR, Carregamento do MDR e leitura/escrita
IF MAR_load = '1' THEN
mar <= UNSIGNED(MEM_bus(n-oplen-1 DOWNTO 0)); -- Para carregar MAR, basta ler o endereco do que tem no BUS (desconsidera o OPCODE)
ELSIF MDR_load = '1' THEN
mdr <= MEM_bus; -- Para carregar MDR, basta ler direto do BUS
ELSIF MEM_en = '1' THEN
IF MEM_rw = '0' THEN
mdr <= contents(to_integer(mar)); -- Se for leitura, pega o conteudo do endereco salvo em MAR e manda para MDR
ELSE
contents(to_integer(mar)) := mdr; -- Se for escrita, escreve MDR no endereco salvo em MAR
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE rtl;
------------------------------------------------------------------------------------------------------------------ | gpl-2.0 | 4ebe331e820ef89f5b616eb07b23bbdf | 0.55821 | 4.021651 | false | false | false | false |
cafe-alpha/wasca | fpga_firmware/wasca/wasca_inst.vhd | 1 | 13,620 | component wasca is
port (
abus_avalon_sdram_bridge_0_abus_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
abus_avalon_sdram_bridge_0_abus_read : in std_logic := 'X'; -- read
abus_avalon_sdram_bridge_0_abus_waitrequest : out std_logic; -- waitrequest
abus_avalon_sdram_bridge_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => 'X'); -- addressdata
abus_avalon_sdram_bridge_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => 'X'); -- chipselect
abus_avalon_sdram_bridge_0_abus_direction : out std_logic; -- direction
abus_avalon_sdram_bridge_0_abus_disable_out : out std_logic; -- disable_out
abus_avalon_sdram_bridge_0_abus_interrupt : out std_logic; -- interrupt
abus_avalon_sdram_bridge_0_abus_muxing : out std_logic_vector(1 downto 0); -- muxing
abus_avalon_sdram_bridge_0_abus_writebyteenable_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- writebyteenable_n
abus_avalon_sdram_bridge_0_abus_reset : in std_logic := 'X'; -- reset
abus_avalon_sdram_bridge_0_sdram_addr : out std_logic_vector(12 downto 0); -- addr
abus_avalon_sdram_bridge_0_sdram_ba : out std_logic_vector(1 downto 0); -- ba
abus_avalon_sdram_bridge_0_sdram_cas_n : out std_logic; -- cas_n
abus_avalon_sdram_bridge_0_sdram_cke : out std_logic; -- cke
abus_avalon_sdram_bridge_0_sdram_cs_n : out std_logic; -- cs_n
abus_avalon_sdram_bridge_0_sdram_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
abus_avalon_sdram_bridge_0_sdram_dqm : out std_logic_vector(1 downto 0); -- dqm
abus_avalon_sdram_bridge_0_sdram_ras_n : out std_logic; -- ras_n
abus_avalon_sdram_bridge_0_sdram_we_n : out std_logic; -- we_n
abus_avalon_sdram_bridge_0_sdram_clk : out std_logic; -- clk
altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_cmd : inout std_logic := 'X'; -- b_SD_cmd
altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat : inout std_logic := 'X'; -- b_SD_dat
altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat3 : inout std_logic := 'X'; -- b_SD_dat3
altera_up_sd_card_avalon_interface_0_conduit_end_o_SD_clock : out std_logic; -- o_SD_clock
altpll_1_areset_conduit_export : in std_logic := 'X'; -- export
altpll_1_locked_conduit_export : out std_logic; -- export
altpll_1_phasedone_conduit_export : out std_logic; -- export
audio_out_BCLK : in std_logic := 'X'; -- BCLK
audio_out_DACDAT : out std_logic; -- DACDAT
audio_out_DACLRCK : in std_logic := 'X'; -- DACLRCK
buffered_spi_mosi : out std_logic; -- mosi
buffered_spi_clk : out std_logic; -- clk
buffered_spi_miso : in std_logic := 'X'; -- miso
buffered_spi_cs : out std_logic; -- cs
clk_clk : in std_logic := 'X'; -- clk
clock_116_mhz_clk : out std_logic; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
reset_controller_0_reset_in1_reset : in std_logic := 'X'; -- reset
uart_0_external_connection_rxd : in std_logic := 'X'; -- rxd
uart_0_external_connection_txd : out std_logic -- txd
);
end component wasca;
u0 : component wasca
port map (
abus_avalon_sdram_bridge_0_abus_address => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_address, -- abus_avalon_sdram_bridge_0_abus.address
abus_avalon_sdram_bridge_0_abus_read => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_read, -- .read
abus_avalon_sdram_bridge_0_abus_waitrequest => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_waitrequest, -- .waitrequest
abus_avalon_sdram_bridge_0_abus_addressdata => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_addressdata, -- .addressdata
abus_avalon_sdram_bridge_0_abus_chipselect => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_chipselect, -- .chipselect
abus_avalon_sdram_bridge_0_abus_direction => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_direction, -- .direction
abus_avalon_sdram_bridge_0_abus_disable_out => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_disable_out, -- .disable_out
abus_avalon_sdram_bridge_0_abus_interrupt => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_interrupt, -- .interrupt
abus_avalon_sdram_bridge_0_abus_muxing => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_muxing, -- .muxing
abus_avalon_sdram_bridge_0_abus_writebyteenable_n => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_writebyteenable_n, -- .writebyteenable_n
abus_avalon_sdram_bridge_0_abus_reset => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_reset, -- .reset
abus_avalon_sdram_bridge_0_sdram_addr => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_addr, -- abus_avalon_sdram_bridge_0_sdram.addr
abus_avalon_sdram_bridge_0_sdram_ba => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_ba, -- .ba
abus_avalon_sdram_bridge_0_sdram_cas_n => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_cas_n, -- .cas_n
abus_avalon_sdram_bridge_0_sdram_cke => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_cke, -- .cke
abus_avalon_sdram_bridge_0_sdram_cs_n => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_cs_n, -- .cs_n
abus_avalon_sdram_bridge_0_sdram_dq => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_dq, -- .dq
abus_avalon_sdram_bridge_0_sdram_dqm => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_dqm, -- .dqm
abus_avalon_sdram_bridge_0_sdram_ras_n => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_ras_n, -- .ras_n
abus_avalon_sdram_bridge_0_sdram_we_n => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_we_n, -- .we_n
abus_avalon_sdram_bridge_0_sdram_clk => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_clk, -- .clk
altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_cmd => CONNECTED_TO_altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_cmd, -- altera_up_sd_card_avalon_interface_0_conduit_end.b_SD_cmd
altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat => CONNECTED_TO_altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat, -- .b_SD_dat
altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat3 => CONNECTED_TO_altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat3, -- .b_SD_dat3
altera_up_sd_card_avalon_interface_0_conduit_end_o_SD_clock => CONNECTED_TO_altera_up_sd_card_avalon_interface_0_conduit_end_o_SD_clock, -- .o_SD_clock
altpll_1_areset_conduit_export => CONNECTED_TO_altpll_1_areset_conduit_export, -- altpll_1_areset_conduit.export
altpll_1_locked_conduit_export => CONNECTED_TO_altpll_1_locked_conduit_export, -- altpll_1_locked_conduit.export
altpll_1_phasedone_conduit_export => CONNECTED_TO_altpll_1_phasedone_conduit_export, -- altpll_1_phasedone_conduit.export
audio_out_BCLK => CONNECTED_TO_audio_out_BCLK, -- audio_out.BCLK
audio_out_DACDAT => CONNECTED_TO_audio_out_DACDAT, -- .DACDAT
audio_out_DACLRCK => CONNECTED_TO_audio_out_DACLRCK, -- .DACLRCK
buffered_spi_mosi => CONNECTED_TO_buffered_spi_mosi, -- buffered_spi.mosi
buffered_spi_clk => CONNECTED_TO_buffered_spi_clk, -- .clk
buffered_spi_miso => CONNECTED_TO_buffered_spi_miso, -- .miso
buffered_spi_cs => CONNECTED_TO_buffered_spi_cs, -- .cs
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
clock_116_mhz_clk => CONNECTED_TO_clock_116_mhz_clk, -- clock_116_mhz.clk
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
reset_controller_0_reset_in1_reset => CONNECTED_TO_reset_controller_0_reset_in1_reset, -- reset_controller_0_reset_in1.reset
uart_0_external_connection_rxd => CONNECTED_TO_uart_0_external_connection_rxd, -- uart_0_external_connection.rxd
uart_0_external_connection_txd => CONNECTED_TO_uart_0_external_connection_txd -- .txd
);
| gpl-2.0 | f264088cc6de5620f40252862317731c | 0.390602 | 4.734098 | false | false | false | false |
sudov/options-accel | vhls-dut-template/fifo.prj/sol/syn/vhdl/dut.vhd | 2 | 4,070 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2012.3
-- Copyright (C) 2012 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity dut is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
in_fifo_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
in_fifo_V_empty_n : IN STD_LOGIC;
in_fifo_V_read : OUT STD_LOGIC;
out_fifo_V_din : OUT STD_LOGIC_VECTOR (31 downto 0);
out_fifo_V_full_n : IN STD_LOGIC;
out_fifo_V_write : OUT STD_LOGIC );
end;
architecture behav of dut is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"dut_inst,dut,{component_name=dut_inst,HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=4.352000,HLS_SYN_LAT=0,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=33,HLS_SYN_LUT=34}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_FFFFFFFF : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111111";
signal cnt : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal ap_sig_bdd_24 : BOOLEAN;
signal tmp_fu_49_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- cnt assign process. --
cnt_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
cnt <= ap_const_lv32_0;
else
if (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not(ap_sig_bdd_24))) then
cnt <= tmp_fu_49_p2;
end if;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process(ap_CS_fsm, ap_sig_bdd_24)
begin
if (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not(ap_sig_bdd_24))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_CS_fsm;
end if;
end process;
-- ap_sig_bdd_24 assign process. --
ap_sig_bdd_24_assign_proc : process(in_fifo_V_empty_n, out_fifo_V_full_n)
begin
ap_sig_bdd_24 <= ((in_fifo_V_empty_n = ap_const_logic_0) or (out_fifo_V_full_n = ap_const_logic_0));
end process;
-- in_fifo_V_read assign process. --
in_fifo_V_read_assign_proc : process(ap_CS_fsm, ap_sig_bdd_24)
begin
if (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not(ap_sig_bdd_24))) then
in_fifo_V_read <= ap_const_logic_1;
else
in_fifo_V_read <= ap_const_logic_0;
end if;
end process;
out_fifo_V_din <= std_logic_vector(unsigned(cnt) + unsigned(ap_const_lv32_FFFFFFFF));
-- out_fifo_V_write assign process. --
out_fifo_V_write_assign_proc : process(ap_CS_fsm, ap_sig_bdd_24)
begin
if (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not(ap_sig_bdd_24))) then
out_fifo_V_write <= ap_const_logic_1;
else
out_fifo_V_write <= ap_const_logic_0;
end if;
end process;
tmp_fu_49_p2 <= std_logic_vector(unsigned(cnt) + unsigned(ap_const_lv32_FFFFFFFF));
end behav;
| apache-2.0 | e7981d14aeb7d191cd36ce7e2f5f5291 | 0.574201 | 3.035048 | false | false | false | false |
zhlinh/vhdl_course | Assignment/CHKSEQ/simulation/modelsim/TB_CHKSEQ.vhd | 1 | 1,134 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TB_CHKSEQ IS
END ENTITY TB_CHKSEQ;
ARCHITECTURE DIRECT_WAY OF TB_CHKSEQ IS
COMPONENT CHKSEQ
PORT(CLK,RESET,DIN:IN STD_LOGIC;
DOUT:OUT STD_LOGIC);
END COMPONENT;
SIGNAL CLK,RESET,DIN:STD_LOGIC:='0';
SIGNAL DOUT:STD_LOGIC;
SIGNAL GIVEN_SEQ:STD_LOGIC_VECTOR(48 DOWNTO 0)
:="0111110010010110111011011101110111111100101110010";
CONSTANT CLK_PERIOD:TIME:=10 NS;
BEGIN
-- DUT = DEVICE UNDER TEST
DUT:CHKSEQ PORT MAP(
CLK=>CLK,
RESET=>RESET,
DIN=>DIN,
DOUT=>DOUT);
--CLOCK PROCESS
CLK_PROCESS:PROCESS
BEGIN
CLK<='0';
WAIT FOR CLK_PERIOD/2;
CLK<='1';
WAIT FOR CLK_PERIOD/2;
END PROCESS;
--GIVEN SEQUENCE PROCESS
GIVEN_SEQ_PROCESS:PROCESS(CLK)
BEGIN
IF(CLK'EVENT AND CLK='1') THEN
GIVEN_SEQ<=GIVEN_SEQ(47 DOWNTO 0) & '0';
DIN<=GIVEN_SEQ(48);
END IF;
END PROCESS;
--SET UP THE RESET SIGNAL
STIMULIS_PROCESS:PROCESS
BEGIN
RESET<='1';
WAIT FOR CLK_PERIOD;
RESET<='0';
WAIT FOR CLK_PERIOD*8;
RESET<='1';
WAIT FOR CLK_PERIOD/2;
RESET<='0';
WAIT;
END PROCESS;
END ARCHITECTURE DIRECT_WAY;
| apache-2.0 | 12d1831a17a54476916dd1a18d179fbb | 0.69224 | 2.779412 | false | false | false | false |
JeremySavonet/Eurobot-2017-Moon-Village | software/HPS_FPGA_LED/fpga/robot_layer_3.vhd | 1 | 8,087 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.types_pkg.all;
use work.robot_layer_3_pkg.all;
entity robot_layer_3 is
generic (
CLK_FREQUENCY_HZ : positive;
RegCnt : positive
);
port (
clk : in std_logic;
reset : in std_logic;
regs_data_in_value : out std_logic_vector(RegCnt*32-1 downto 0) := (others => '0');
regs_data_in_read : in std_logic_vector(RegCnt-1 downto 0);
regs_data_out_value : in std_logic_vector(RegCnt*32-1 downto 0);
regs_data_out_write : in std_logic_vector(RegCnt-1 downto 0);
---------------------------------
-------- TO/FROM LAYER 2 --------
---------------------------------
sum_m_dist : in std_logic_vector(32-1 downto 0);
sum_m_angle : in std_logic_vector(32-1 downto 0);
sum_c_dist : in std_logic_vector(32-1 downto 0);
sum_c_angle : in std_logic_vector(32-1 downto 0);
pos_valid : in std_logic;
pos_id : in std_logic_vector(8-1 downto 0);
pos_teta : in std_logic_vector(16-1 downto 0);
pos_x : in std_logic_vector(16-1 downto 0);
pos_y : in std_logic_vector(16-1 downto 0);
pos_sum_dist : in std_logic_vector(32-1 downto 0);
pos_sum_angle : in std_logic_vector(32-1 downto 0);
dist_en : out std_logic;
dist_acc : out std_logic_vector(32-1 downto 0);
dist_speed : out std_logic_vector(32-1 downto 0);
dist_target : out std_logic_vector(32-1 downto 0);
angle_en : out std_logic;
angle_acc : out std_logic_vector(32-1 downto 0);
angle_speed : out std_logic_vector(32-1 downto 0);
angle_target : out std_logic_vector(32-1 downto 0)
);
end entity;
architecture rtl of robot_layer_3 is
component system is
port (
clk_clk : in std_logic := 'X'; -- clk
pio_data_in_value : in std_logic_vector(511 downto 0) := (others => 'X'); -- data_in_value
pio_data_in_read : out std_logic_vector(15 downto 0); -- data_in_read
pio_data_out_value : out std_logic_vector(511 downto 0); -- data_out_value
pio_data_out_write : out std_logic_vector(15 downto 0); -- data_out_write
reset_reset_n : in std_logic := 'X' -- reset_n
);
end component system;
signal w_reset_n : std_logic;
signal w_regs_data_in_value : std_logic_vector(RegCnt*32-1 downto 0);
signal w_regs_data_in_value_mask : std_logic_vector(RegCnt*4-1 downto 0) := (others=>'0');
begin
w_reset_n <= not reset;
--! we return for read the same written data, expect for some bytes (noted masked) where we compute the value internally
g_reg: for i in 0 to w_regs_data_in_value_mask'length-1 generate
regs_data_in_value((i+1)*8-1 downto i*8) <= regs_data_out_value((i+1)*8-1 downto i*8) when w_regs_data_in_value_mask(i) = '0' else w_regs_data_in_value((i+1)*8-1 downto i*8);
end generate;
b_trajectory: block
signal w_pio_data_in_value : std_logic_vector(511 downto 0) := (others=>'0');
signal w_pio_data_in_read : std_logic_vector(15 downto 0);
signal w_pio_data_out_value : std_logic_vector(511 downto 0);
signal w_pio_data_out_write : std_logic_vector(15 downto 0);
--! difference between external MM and CPU regs
constant REGS_ORIGIN : natural := 2;
constant REGS_PID_DISTANCE_OFFSET : natural := 2;
constant REGS_PID_ANGLE_OFFSET : natural := REGS_PID_DISTANCE_OFFSET+4;
constant REGS_ODO_OFFSET : natural := 2;
constant REGS_TRAJ_OUT_OFFSET : natural := 14;
begin
w_regs_data_in_value_mask((2+REGS_ORIGIN)*4-1 downto (1+REGS_ORIGIN)*4) <= "0011";
w_regs_data_in_value_mask((REGS_ORIGIN+REGS_TRAJ_OUT_OFFSET+2-1)*4-1 downto (REGS_ORIGIN+REGS_TRAJ_OUT_OFFSET-1)*4) <= (others=>'1');
p_async: process(regs_data_out_value,w_pio_data_out_value,
sum_m_dist,sum_m_angle,sum_c_dist,sum_c_angle,pos_valid,pos_id,pos_teta,pos_x,pos_y,pos_sum_dist,pos_sum_angle
) is
begin
w_pio_data_in_value(1*32-1 downto 0*32) <= X"00000200";
w_pio_data_in_value((16)*32-1 downto 1*32) <= regs_data_out_value((REGS_ORIGIN+15)*32-1 downto REGS_ORIGIN*32);
--! we override the values for odometry data
w_pio_data_in_value((REGS_ODO_OFFSET+8)*32-1 downto REGS_ODO_OFFSET*32) <= pos_sum_angle &
pos_sum_dist &
pos_y &
pos_x &
pos_teta &
pos_id &
"0000000" & pos_valid &
sum_c_angle &
sum_c_dist &
sum_m_angle &
sum_m_dist;
w_regs_data_in_value((2+REGS_ORIGIN)*32-1 downto (1+REGS_ORIGIN)*32) <= w_pio_data_out_value((2)*32-1 downto (1)*32);
w_regs_data_in_value((REGS_TRAJ_OUT_OFFSET+REGS_ORIGIN+2-1)*32-1 downto (REGS_TRAJ_OUT_OFFSET+REGS_ORIGIN-1)*32) <= w_pio_data_out_value((REGS_TRAJ_OUT_OFFSET+2)*32-1 downto (REGS_TRAJ_OUT_OFFSET)*32);
end process;
--w_odo_output(0) <= w_pio_data_out_value((1+8)*32-1 downto (0+8)*32); --! distance
--w_odo_output(1) <= w_pio_data_out_value((2+8)*32-1 downto (1+8)*32); --! angle
dist_en <= w_pio_data_out_value((1+REGS_PID_DISTANCE_OFFSET)*32-1 downto (0+REGS_PID_DISTANCE_OFFSET)*32)((0+REGS_PID_DISTANCE_OFFSET)*32);
dist_speed <= w_pio_data_out_value((2+REGS_PID_DISTANCE_OFFSET)*32-1 downto (1+REGS_PID_DISTANCE_OFFSET)*32);
dist_acc <= w_pio_data_out_value((3+REGS_PID_DISTANCE_OFFSET)*32-1 downto (2+REGS_PID_DISTANCE_OFFSET)*32);
dist_target <= w_pio_data_out_value((4+REGS_PID_DISTANCE_OFFSET)*32-1 downto (3+REGS_PID_DISTANCE_OFFSET)*32);
angle_en <= w_pio_data_out_value((1+REGS_PID_ANGLE_OFFSET)*32-1 downto (0+REGS_PID_ANGLE_OFFSET)*32)((0+REGS_PID_ANGLE_OFFSET)*32);
angle_speed <= w_pio_data_out_value((2+REGS_PID_ANGLE_OFFSET)*32-1 downto (1+REGS_PID_ANGLE_OFFSET)*32);
angle_acc <= w_pio_data_out_value((3+REGS_PID_ANGLE_OFFSET)*32-1 downto (2+REGS_PID_ANGLE_OFFSET)*32);
angle_target <= w_pio_data_out_value((4+REGS_PID_ANGLE_OFFSET)*32-1 downto (3+REGS_PID_ANGLE_OFFSET)*32);
--! disable warnings
assert w_pio_data_in_read = w_pio_data_in_read;
assert w_pio_data_out_write = w_pio_data_out_write;
inst_trajectory_rv : component system
port map (
clk_clk => clk,
reset_reset_n => w_reset_n,
pio_data_in_value => w_pio_data_in_value,
pio_data_in_read => w_pio_data_in_read,
pio_data_out_value => w_pio_data_out_value,
pio_data_out_write => w_pio_data_out_write
);
end block;
end architecture;
| gpl-3.0 | de63d5835b45e4f3043588890bf0bc62 | 0.500927 | 3.499351 | false | false | false | false |
cafe-alpha/wasca | v12/fpga_firmware/wasca/wasca_inst.vhd | 2 | 10,448 | component wasca is
port (
altpll_0_areset_conduit_export : in std_logic := 'X'; -- export
altpll_0_locked_conduit_export : out std_logic; -- export
altpll_0_phasedone_conduit_export : out std_logic; -- export
audio_out_BCLK : in std_logic := 'X'; -- BCLK
audio_out_DACDAT : out std_logic; -- DACDAT
audio_out_DACLRCK : in std_logic := 'X'; -- DACLRCK
clk_clk : in std_logic := 'X'; -- clk
clock_116_mhz_clk : out std_logic; -- clk
external_sdram_controller_wire_addr : out std_logic_vector(12 downto 0); -- addr
external_sdram_controller_wire_ba : out std_logic_vector(1 downto 0); -- ba
external_sdram_controller_wire_cas_n : out std_logic; -- cas_n
external_sdram_controller_wire_cke : out std_logic; -- cke
external_sdram_controller_wire_cs_n : out std_logic; -- cs_n
external_sdram_controller_wire_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
external_sdram_controller_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
external_sdram_controller_wire_ras_n : out std_logic; -- ras_n
external_sdram_controller_wire_we_n : out std_logic; -- we_n
sega_saturn_abus_slave_0_abus_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
sega_saturn_abus_slave_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => 'X'); -- chipselect
sega_saturn_abus_slave_0_abus_read : in std_logic := 'X'; -- read
sega_saturn_abus_slave_0_abus_write : in std_logic_vector(1 downto 0) := (others => 'X'); -- write
sega_saturn_abus_slave_0_abus_waitrequest : out std_logic; -- waitrequest
sega_saturn_abus_slave_0_abus_interrupt : out std_logic; -- interrupt
sega_saturn_abus_slave_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => 'X'); -- addressdata
sega_saturn_abus_slave_0_abus_direction : out std_logic; -- direction
sega_saturn_abus_slave_0_abus_muxing : out std_logic_vector(1 downto 0); -- muxing
sega_saturn_abus_slave_0_abus_disableout : out std_logic; -- disableout
sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset : in std_logic := 'X'; -- saturn_reset
spi_sd_card_MISO : in std_logic := 'X'; -- MISO
spi_sd_card_MOSI : out std_logic; -- MOSI
spi_sd_card_SCLK : out std_logic; -- SCLK
spi_sd_card_SS_n : out std_logic -- SS_n
);
end component wasca;
u0 : component wasca
port map (
altpll_0_areset_conduit_export => CONNECTED_TO_altpll_0_areset_conduit_export, -- altpll_0_areset_conduit.export
altpll_0_locked_conduit_export => CONNECTED_TO_altpll_0_locked_conduit_export, -- altpll_0_locked_conduit.export
altpll_0_phasedone_conduit_export => CONNECTED_TO_altpll_0_phasedone_conduit_export, -- altpll_0_phasedone_conduit.export
audio_out_BCLK => CONNECTED_TO_audio_out_BCLK, -- audio_out.BCLK
audio_out_DACDAT => CONNECTED_TO_audio_out_DACDAT, -- .DACDAT
audio_out_DACLRCK => CONNECTED_TO_audio_out_DACLRCK, -- .DACLRCK
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
clock_116_mhz_clk => CONNECTED_TO_clock_116_mhz_clk, -- clock_116_mhz.clk
external_sdram_controller_wire_addr => CONNECTED_TO_external_sdram_controller_wire_addr, -- external_sdram_controller_wire.addr
external_sdram_controller_wire_ba => CONNECTED_TO_external_sdram_controller_wire_ba, -- .ba
external_sdram_controller_wire_cas_n => CONNECTED_TO_external_sdram_controller_wire_cas_n, -- .cas_n
external_sdram_controller_wire_cke => CONNECTED_TO_external_sdram_controller_wire_cke, -- .cke
external_sdram_controller_wire_cs_n => CONNECTED_TO_external_sdram_controller_wire_cs_n, -- .cs_n
external_sdram_controller_wire_dq => CONNECTED_TO_external_sdram_controller_wire_dq, -- .dq
external_sdram_controller_wire_dqm => CONNECTED_TO_external_sdram_controller_wire_dqm, -- .dqm
external_sdram_controller_wire_ras_n => CONNECTED_TO_external_sdram_controller_wire_ras_n, -- .ras_n
external_sdram_controller_wire_we_n => CONNECTED_TO_external_sdram_controller_wire_we_n, -- .we_n
sega_saturn_abus_slave_0_abus_address => CONNECTED_TO_sega_saturn_abus_slave_0_abus_address, -- sega_saturn_abus_slave_0_abus.address
sega_saturn_abus_slave_0_abus_chipselect => CONNECTED_TO_sega_saturn_abus_slave_0_abus_chipselect, -- .chipselect
sega_saturn_abus_slave_0_abus_read => CONNECTED_TO_sega_saturn_abus_slave_0_abus_read, -- .read
sega_saturn_abus_slave_0_abus_write => CONNECTED_TO_sega_saturn_abus_slave_0_abus_write, -- .write
sega_saturn_abus_slave_0_abus_waitrequest => CONNECTED_TO_sega_saturn_abus_slave_0_abus_waitrequest, -- .waitrequest
sega_saturn_abus_slave_0_abus_interrupt => CONNECTED_TO_sega_saturn_abus_slave_0_abus_interrupt, -- .interrupt
sega_saturn_abus_slave_0_abus_addressdata => CONNECTED_TO_sega_saturn_abus_slave_0_abus_addressdata, -- .addressdata
sega_saturn_abus_slave_0_abus_direction => CONNECTED_TO_sega_saturn_abus_slave_0_abus_direction, -- .direction
sega_saturn_abus_slave_0_abus_muxing => CONNECTED_TO_sega_saturn_abus_slave_0_abus_muxing, -- .muxing
sega_saturn_abus_slave_0_abus_disableout => CONNECTED_TO_sega_saturn_abus_slave_0_abus_disableout, -- .disableout
sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset => CONNECTED_TO_sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset, -- sega_saturn_abus_slave_0_conduit_saturn_reset.saturn_reset
spi_sd_card_MISO => CONNECTED_TO_spi_sd_card_MISO, -- spi_sd_card.MISO
spi_sd_card_MOSI => CONNECTED_TO_spi_sd_card_MOSI, -- .MOSI
spi_sd_card_SCLK => CONNECTED_TO_spi_sd_card_SCLK, -- .SCLK
spi_sd_card_SS_n => CONNECTED_TO_spi_sd_card_SS_n -- .SS_n
);
| gpl-2.0 | a1f9fc9ec0f0f64a21536f566cdfe4cb | 0.380073 | 5.074308 | false | false | false | false |
zhlinh/vhdl_course | Assignment/LED_CNT/LED_DEC.vhd | 1 | 813 | --LED Decoder Entity
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY LED_DEC IS
PORT ( NUM : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END ENTITY LED_DEC;
ARCHITECTURE ART1 OF LED_DEC IS
BEGIN
PROCESS(NUM)
BEGIN
CASE(NUM) IS
WHEN "0000" =>
DOUT <= "1111110";
WHEN "0001" =>
DOUT <= "0110000";
WHEN "0010" =>
DOUT <= "1101101";
WHEN "0011" =>
DOUT <= "1111001";
WHEN "0100" =>
DOUT <= "0110011";
WHEN "0101" =>
DOUT <= "1011011";
WHEN "0110" =>
DOUT <= "1011111";
WHEN "0111" =>
DOUT <= "1110000";
WHEN "1000" =>
DOUT <= "1111111";
WHEN "1001" =>
DOUT <= "1111011";
WHEN OTHERS =>
DOUT <= (OTHERS=> '0');
END CASE;
END PROCESS;
END ARCHITECTURE ART1; | apache-2.0 | 36e53589f16917f88f8c93d1e12d9dc0 | 0.573186 | 2.882979 | false | false | false | false |
iamllama/EE2020 | ee2020.srcs/sources_1/imports/Downloads/DA2RefComp.vhd | 1 | 9,889 | --------------------------------------------------------------------------------
-- DA2 Reference Component
--------------------------------------------------------------------------------
-- Author : Ioana Dabacan
-- CopyRight 2008 Digilent Ro.
--------------------------------------------------------------------------------
-- Desription : This file is the VHDL code for a PMOD-DA2 controller.
--
--------------------------------------------------------------------------------
-- Revision History:
-- Feb/29/2008 (Created) Ioana Dabacan
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--------------------------------------------------------------------------------
--
-- Title : DA1 controller entity
--
-- Inputs : 5
-- Outputs : 5
--
-- Description: This is the DA2 Reference Component entity. The input ports are
-- a 50MHz clock and and an asynchronous reset button along with the
-- data to be serially shifted in the 2 DAC121S101 chips on a DA2
-- Pmod on each clock cycle.There is also a signal to start a
-- conversion.
-- The outputs of this entity are: a output clock signal, two serial
-- output signals D1 and D2, a sync signal to synchronize the data
-- in the DAC121S101 chip, a done signal to tell that the chip is
-- done converting the data and another set of data can be sent.
--
---------------------------------------------------------------------------------
entity DA2RefComp is
Port (
--General usage
CLK : in std_logic; -- System Clock (50MHz)
RST : in std_logic;
--Pmod interface signals
D1 : out std_logic;
D2 : out std_logic;
CLK_OUT : out std_logic;
nSYNC : out std_logic;
--User interface signals
DATA1 : in std_logic_vector(11 downto 0);
DATA2 : in std_logic_vector(11 downto 0);
START : in std_logic;
DONE : out std_logic
);
end DA2RefComp ;
architecture DA2 of DA2RefComp is
-- control constant: Normal Operation
constant control : std_logic_vector(3 downto 0) := "0000";
------------------------------------------------------------------------------------
-- Title : signal assignments
--
-- Description: The following signals are enumerated signals for the
-- finite state machine,2 temporary vectors to be shifted out to the
-- DAC121S101 chips, a divided clock signal to drive the DAC121S101 chips,
-- a counter to divide the internal 50 MHz clock signal,
-- a 4-bit counter to be used to shift out the 16-bit register,
-- and 2 enable signals for the paralel load and shift of the
-- shift register.
--
------------------------------------------------------------------------------------
type states is (Idle,
ShiftOut,
SyncData);
signal current_state : states;
signal next_state : states;
signal temp1 : std_logic_vector(15 downto 0);
signal temp2 : std_logic_vector(15 downto 0);
signal clk_div : std_logic;
signal clk_counter : std_logic_vector(27 downto 0);
signal shiftCounter : std_logic_vector(3 downto 0);
signal enShiftCounter: std_logic;
signal enParalelLoad : std_logic;
begin
------------------------------------------------------------------------------------
--
-- Title : Clock Divider
--
-- Description: The following process takes a 50 MHz clock and divides it down to a
-- 25 MHz clock signal by assigning the signals clk_out and clk_div
-- to the 2nd bit of the clk_counter vector. clk_div is used by
-- the Finite State Machine and clk_out is used by the DAC121S101 chips.
--
------------------------------------------------------------------------------------
clock_divide : process(rst,clk)
begin
if rst = '1' then
clk_counter <= "0000000000000000000000000000";
elsif (clk = '1' and clk'event) then
clk_counter <= clk_counter + '1';
end if;
end process;
clk_div <= clk_counter(0);
clk_out <= clk_counter(0);
-----------------------------------------------------------------------------------
--
-- Title : counter
--
-- Description: This is the process were the teporary registers will be loaded and
-- shifted.When the enParalelLoad signal is generated inside the state
-- the temp1 and temp2 registers will be loaded with the 8 bits of control
-- concatenated with the 8 bits of data. When the enShiftCounter is
-- activated, the 16-bits of data inside the temporary registers will be
-- shifted. A 4-bit counter is used to keep shifting the data
-- inside temp1 and temp 2 for 16 clock cycles.
--
-----------------------------------------------------------------------------------
counter : process(clk_div, enParalelLoad, enShiftCounter)
begin
if (clk_div = '1' and clk_div'event) then
if enParalelLoad = '1' then
shiftCounter <= "0000";
temp1 <= control & DATA1;
temp2 <= control & DATA2;
elsif (enShiftCounter = '1') then
temp1 <= temp1(14 downto 0)&temp1(15);
temp2 <= temp2(14 downto 0)&temp2(15);
shiftCounter <= shiftCounter + '1';
end if;
end if;
end process;
D1 <= temp1(15);
D2 <= temp2(15);
---------------------------------------------------------------------------------
--
-- Title : Finite State Machine
--
-- Description: This 3 processes represent the FSM that contains three states.
-- First one is the Idle state in which the temporary registers are
-- assigned the updated value of the input "DATA1" and "DATA2".
-- The next state is the ShiftOut state which is the state where the
-- 16-bits of temporary registers are shifted out left from the MSB
-- to the two serial outputs, D1 and D2. Immediately following the
-- second state is the third state SyncData. This state drives the
-- output signal sync high for2 clock signals telling the DAC121S101
-- to latch the 16-bit data it just recieved in the previous state.
-- Notes: The data will change on the upper edge of the clock signal. Their
-- is also an asynchronous reset that will reset all signals to their
-- original state.
--
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
--
-- Title : SYNC_PROC
--
-- Description: This is the process were the states are changed synchronously. At
-- reset the current state becomes Idle state.
--
-----------------------------------------------------------------------------------
SYNC_PROC: process (clk_div, rst)
begin
if (clk_div'event and clk_div = '1') then
if (rst = '1') then
current_state <= Idle;
else
current_state <= next_state;
end if;
end if;
end process;
-----------------------------------------------------------------------------------
--
-- Title : OUTPUT_DECODE
--
-- Description: This is the process were the output signals are generated
-- unsynchronously based on the state only (Moore State Machine).
--
-----------------------------------------------------------------------------------
OUTPUT_DECODE: process (current_state)
begin
if current_state = Idle then
enShiftCounter <='0';
DONE <='1';
nSYNC <='1';
enParalelLoad <= '1';
elsif current_state = ShiftOut then
enShiftCounter <='1';
DONE <='0';
nSYNC <='0';
enParalelLoad <= '0';
else --if current_state = SyncData then
enShiftCounter <='0';
DONE <='0';
nSYNC <='1';
enParalelLoad <= '0';
end if;
end process;
-----------------------------------------------------------------------------------
--
-- Title : NEXT_STATE_DECODE
--
-- Description: This is the process were the next state logic is generated
-- depending on the current state and the input signals.
--
-----------------------------------------------------------------------------------
NEXT_STATE_DECODE: process (current_state, START, shiftCounter)
begin
next_state <= current_state; --default is to stay in current state
case (current_state) is
when Idle =>
if START = '1' then
next_state <= ShiftOut;
end if;
when ShiftOut =>
if shiftCounter = x"F" then
next_state <= SyncData;
end if;
when SyncData =>
if START = '0' then
next_state <= Idle;
end if;
when others =>
next_state <= Idle;
end case;
end process;
end DA2; | gpl-3.0 | 9ce82680eac9fe9e7350f6868287db1d | 0.45313 | 5.068683 | false | false | false | false |
aylons/concordic | hdl/testbench/simple/simple_tb.vhd | 1 | 3,653 | -------------------------------------------------------------------------------
-- Title : Simple testbench
-- Project :
-------------------------------------------------------------------------------te
-- File : simple_tb.vhd
-- Author : Aylons <aylons@aylons-yoga2>
-- Company :
-- Created : 2014-05-04
-- Last update: 2014-05-04
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: SImplest testbench, just to see if code sinthesizes.
-------------------------------------------------------------------------------
-- This file is part of Concordic.
--
-- Concordic is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Concordic is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-05-04 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity simple_tb is end entity simple_tb;
architecture test of simple_tb is
constant c_clk_freq : real := 100.0e6;
constant c_input_width : natural := 24;
constant c_output_width : natural := 24;
constant c_number_of_stages : natural := 20;
signal x_input : signed(c_input_width-1 downto 0) := x"010000";
signal y_input : signed(c_input_width-1 downto 0) := x"010000";
signal z_input : signed(c_input_width-1 downto 0) := x"000000";
signal x_output : signed(c_output_width-1 downto 0);
signal y_output : signed(c_output_width-1 downto 0);
signal z_output : signed(c_output_width-1 downto 0);
signal clk : std_logic := '0';
-- Procedure for clock generation
procedure clk_gen(signal clk : out std_logic; constant FREQ : real) is
constant PERIOD : time := 1 sec / FREQ; -- Full period
constant HIGH_TIME : time := PERIOD / 2; -- High time
constant LOW_TIME : time := PERIOD - HIGH_TIME; -- Low time; always >= HIGH_TIME
begin
-- Check the arguments
assert (HIGH_TIME /= 0 fs) report "clk_plain: High time is zero; time resolution to large for frequency" severity failure;
-- Generate a clock cycle
loop
clk <= '1';
wait for HIGH_TIME;
clk <= '0';
wait for LOW_TIME;
end loop;
end procedure;
component concordic is
generic (
g_stages : natural;
g_mode : string);
port (
x_i : in signed;
y_i : in signed;
z_i : in signed;
clk_i : in std_logic;
x_o : out signed;
y_o : out signed;
z_o : out signed);
end component concordic;
begin
clk_gen(clk, c_clk_freq);
concordic_1 : entity work.concordic
generic map (
g_stages => c_number_of_stages,
g_mode => "rect_to_polar")
port map (
x_i => x_input,
y_i => y_input,
z_i => z_input,
clk_i => clk,
x_o => x_output,
y_o => y_output,
z_o => z_output);
end architecture test;
| gpl-3.0 | 757893927ba46c57f7ece631924ac2d8 | 0.548316 | 3.88204 | false | false | false | false |
Hyvok/HardHeat | src/pwm.vhd | 1 | 2,811 | library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.utils_pkg.all;
entity pwm is
generic
(
-- Number of bits in the PWM counter
COUNTER_N : positive;
-- Minimum modulation level (to ensure for example fans stay running)
MIN_MOD_LVL : positive;
-- Number of PWM cycles (full timer) the PWM is disabled on enable
ENABLE_ON_D : natural
);
port
(
clk : in std_logic;
reset : in std_logic;
enable_in : in std_logic;
mod_lvl_in : in unsigned(COUNTER_N - 1 downto 0);
mod_lvl_f_in : in std_logic;
pwm_out : out std_logic
);
end entity;
architecture rtl of pwm is
begin
pwm_p: process(clk, reset)
type pwm_state is (idle, enable_on_delay, pwm);
variable state : pwm_state;
variable timer : unsigned(COUNTER_N - 1 downto 0);
variable cycles : unsigned(ceil_log2(ENABLE_ON_D) downto 0);
variable mod_lvl : unsigned(COUNTER_N - 1 downto 0);
begin
if reset = '1' then
state := idle;
timer := (others => '0');
cycles := (others => '0');
mod_lvl := to_unsigned(MIN_MOD_LVL, mod_lvl'length);
pwm_out <= '0';
elsif rising_edge(clk) then
if state = idle then
pwm_out <= '0';
if enable_in = '1' then
state := enable_on_delay;
timer := (others => '0');
cycles := (others => '0');
pwm_out <= '1';
end if;
elsif state = enable_on_delay then
if timer = 2**COUNTER_N - 1 then
cycles := cycles + 1;
if cycles >= ENABLE_ON_D then
state := pwm;
timer := (others => '0');
end if;
end if;
elsif state = pwm then
if timer <= mod_lvl then
pwm_out <= '1';
else
pwm_out <= '0';
end if;
end if;
if enable_in = '0' then
state := idle;
timer := (others => '0');
else
timer := timer + 1;
end if;
if mod_lvl_f_in = '1' then
if mod_lvl_in < MIN_MOD_LVL then
mod_lvl := to_unsigned(MIN_MOD_LVL, mod_lvl'length);
else
mod_lvl := mod_lvl_in;
end if;
end if;
end if;
end process;
end;
| mit | 9c011a67a54d7ef950d02adc4540df69 | 0.424404 | 4.298165 | false | false | false | false |
Hyvok/HardHeat | src/resonant_pfd.vhd | 1 | 1,423 | library ieee;
use ieee.std_logic_1164.all;
entity resonant_pfd is
port
(
-- Inputs
clk : in std_logic;
reset : in std_logic;
sig_in : in std_logic;
ref_in : in std_logic;
-- Outputs
up_out : out std_logic;
down_out : out std_logic
);
end resonant_pfd;
architecture rtl of resonant_pfd is
signal ff : std_logic;
begin
-- D-type flip-flop
ff_p: process(clk, reset)
variable last_sig : std_logic;
begin
if reset = '1' then
ff <= '0';
last_sig := '0';
-- FF is synchronous so we do not have to synchronize the output after
elsif rising_edge(clk) then
if not sig_in = last_sig and sig_in = '1' then
ff <= ref_in;
end if;
last_sig := sig_in;
end if;
end process;
-- Actual phase-frequency detector
pfd_p: process(clk, reset)
variable sig_ref_xor : std_logic;
begin
if reset = '1' then
up_out <= '0';
down_out <= '0';
sig_ref_xor := '0';
elsif rising_edge(clk) then
sig_ref_xor := sig_in xor ref_in;
up_out <= sig_ref_xor and ff;
down_out <= sig_ref_xor and not ff;
end if;
end process;
end;
| mit | ab5d594ae62237d713da3aeb10a24798 | 0.472242 | 3.734908 | false | false | false | false |
upci/upci | Projeto/memory.vhd | 1 | 3,279 | ---- Memory ------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.processor_functions.all;
------------------------------------------------------------------------------------------------------------------
ENTITY memory IS
PORT (clk, nrst: IN STD_LOGIC; -- reset ativo em zero
MDR_load: IN STD_LOGIC; -- sinal de carregamento do BUS para MDR
MAR_load: IN STD_LOGIC; -- sinal de carregamento do BUS para MAR
MEM_valid: IN STD_LOGIC; -- sinal que indica que o resultado da MDR deve ser colocado em MEM_bus (ou Z se 0)
MEM_en: IN STD_LOGIC; -- ativacao da memoria para operacoes de leitura e escrita
MEM_rw: IN STD_LOGIC; -- flag que indica se a operacao a ser realizada eh de leitura ou escrita
MEM_bus: INOUT STD_LOGIC_VECTOR(n-1 DOWNTO 0)); -- barramento de entrada/saida
END ENTITY memory;
------------------------------------------------------------------------------------------------------------------
ARCHITECTURE rtl OF memory IS
SIGNAL mdr: STD_LOGIC_VECTOR(wordlen-1 DOWNTO 0); -- registrador de dados
SIGNAL mar: UNSIGNED(wordlen-oplen-1 DOWNTO 0); -- registrador de enderecos
BEGIN
-- Se o MEM_valid = '1', manda o valor do resultado do MDR pro barramento. Caso contrario, manda Z.
MEM_bus <= mdr
WHEN MEM_valid = '1' AND mar(7) = '0'
ELSE (others => 'Z');
PROCESS (clk, nrst) IS
VARIABLE contents: memory_array; -- conteudo da memoria
-- Definicao do valor padrao da memoria (para simular ROM com programa)
CONSTANT program: memory_array := (0 => "000000010001",
1 => "000100010100",
2 => "000100010101",
3 => "000000010011",
4 => "000100010100",
5 => "000000010100",
6 => "101100001110",
7 => "000000010101",
8 => "001000010010",
9 => "000100010101",
10 => "000000010100",
11 => "010100000000",
12 => "000100010100",
13 => "101000000101",
14 => "000000010101",
15 => "000110000001",
16 => "101000000000",
17 => "000000000000",
18 => "000000000011",
19 => "000000000111",
20 => "000000000000",
21 => "000000000000",
OTHERS => (OTHERS => '0'));
BEGIN
-- De forma assincrona, se o reset ficar em nivel 0, reseta os registradores e conteudo da memoria
IF nrst = '0' THEN
mdr <= (OTHERS => '0');
mar <= (OTHERS => '0');
contents := program;
-- Se teve uma borda de subida no clock, faz as outras coisas
ELSIF rising_edge(clk) THEN
-- A ordem de prioridade eh: Carregamento do MAR, Carregamento do MDR e leitura/escrita
IF MAR_load = '1' THEN
mar <= UNSIGNED(MEM_bus(n-oplen-1 DOWNTO 0)); -- Para carregar MAR, basta ler o endereco do que tem no BUS (desconsidera o OPCODE)
ELSIF MDR_load = '1' THEN
mdr <= MEM_bus; -- Para carregar MDR, basta ler direto do BUS
ELSIF MEM_en = '1' AND mar < mem_limit THEN
IF MEM_rw = '0' THEN
mdr <= contents(to_integer(mar)); -- Se for leitura, pega o conteudo do endereco salvo em MAR e manda para MDR
ELSE
contents(to_integer(mar)) := mdr; -- Se for escrita, escreve MDR no endereco salvo em MAR
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE rtl;
------------------------------------------------------------------------------------------------------------------ | gpl-2.0 | b8c7255db5918248ae432308206e7b24 | 0.578835 | 3.866745 | false | false | false | false |
albayaty/Video-Game-Engine | EDK/VGA/40x30/vgatimehelper.vhd | 1 | 4,696 | -- ==============================================
-- Copyright © 2014 Ali M. Al-Bayaty
--
-- Video-Game-Engine is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- any later version.
--
-- Video-Game-Engine is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- ==============================================
--
-- Video Game Engine Project
-- ( EDK: VGA 40x30 Resolution, Timer Helper VHDL )
--
-- MSEE student: Ali M. Al-Bayaty
-- EE659: System-On-Chip
-- Personal website: <http://albayaty.github.io/>
-- Source code link: <https://github.com/albayaty/Video-Game-Engine.git>
--
-- ==============================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vgatimehelper is
port(
clk, reset: in std_logic; --send in 50mhz clock
hsync, vsync: out std_logic;
video_on, p_tick: out std_logic; --p_tick is the 25mhz clock you will
--not need to use, video_on is when you
--can display a pixel
pixel_x, pixel_y: out std_logic_vector (9 downto 0)
);
end vgatimehelper;
architecture arch of vgatimehelper is
-- VGA 640-by-480 sync parameters
constant HD: integer:=640; --horizontal display area
constant HF: integer:=16 ; --h. front porch
constant HB: integer:=48 ; --h. back porch
constant HR: integer:=96 ; --h. retrace
constant VD: integer:=480; --vertical display area
constant VF: integer:=10; --v. front porch
constant VB: integer:=33; --v. back porch
constant VR: integer:=2; --v. retrace
-- mod-2 counter
signal mod2_reg, mod2_next: std_logic;
-- sync counters
signal v_count_reg, v_count_next: unsigned(9 downto 0);
signal h_count_reg, h_count_next: unsigned(9 downto 0);
-- output buffer
signal v_sync_reg, h_sync_reg: std_logic;
signal v_sync_next, h_sync_next: std_logic;
-- status signal
signal h_end, v_end, pixel_tick: std_logic;
begin
-- registers
process (clk,reset)
begin
if reset='1' then
mod2_reg <= '0';
v_count_reg <= (others=>'0');
h_count_reg <= (others=>'0');
v_sync_reg <= '0';
h_sync_reg <= '0';
elsif (clk'event and clk='1') then
mod2_reg <= mod2_next;
v_count_reg <= v_count_next;
h_count_reg <= h_count_next;
v_sync_reg <= v_sync_next;
h_sync_reg <= h_sync_next;
end if;
end process;
-- mod-2 circuit to generate 25 MHz enable tick
mod2_next <= not mod2_reg;
-- 25 MHz pixel tick
pixel_tick <= '1' when mod2_reg='1' else '0';
-- status
h_end <= -- end of horizontal counter
'1' when h_count_reg=(HD+HF+HB+HR-1) else --799
'0';
v_end <= -- end of vertical counter
'1' when v_count_reg=(VD+VF+VB+VR-1) else --524
'0';
-- mod-800 horizontal sync counter
process (h_count_reg,h_end,pixel_tick)
begin
if pixel_tick='1' then -- 25 MHz tick
if h_end='1' then
h_count_next <= (others=>'0');
else
h_count_next <= h_count_reg + 1;
end if;
else
h_count_next <= h_count_reg;
end if;
end process;
-- mod-525 vertical sync counter
process (v_count_reg,h_end,v_end,pixel_tick)
begin
if pixel_tick='1' and h_end='1' then
if (v_end='1') then
v_count_next <= (others=>'0');
else
v_count_next <= v_count_reg + 1;
end if;
else
v_count_next <= v_count_reg;
end if;
end process;
-- horizontal and vertical sync, buffered to avoid glitch
h_sync_next <=
'1' when (h_count_reg>=(HD+HF)) --656
and (h_count_reg<=(HD+HF+HR-1)) else --751
'0';
v_sync_next <=
'1' when (v_count_reg>=(VD+VF)) --490
and (v_count_reg<=(VD+VF+VR-1)) else --491
'0';
-- video on/off
video_on <=
'1' when (h_count_reg<HD) and (v_count_reg<VD) else
'0';
-- output signal
hsync <= h_sync_reg;
vsync <= v_sync_reg;
pixel_x <= std_logic_vector(h_count_reg);
pixel_y <= std_logic_vector(v_count_reg);
p_tick <= pixel_tick;
end arch;
| gpl-3.0 | 2f45acf1f93c88c8c0b54cc7909c3cc2 | 0.568477 | 3.39971 | false | false | false | false |
Hyvok/HardHeat | src/phase_accumulator.vhd | 1 | 976 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity phase_accumulator is
generic
(
-- Number of bits in the accumulator
ACCUM_BITS_N : positive;
-- Number of bits in the tuning word (unsigned)
TUNING_WORD_N : positive
);
port
(
clk : in std_logic;
reset : in std_logic;
tuning_word_in : in unsigned(TUNING_WORD_N - 1 downto 0);
sig_out : out std_logic
);
end entity;
architecture rtl of phase_accumulator is
signal accumulator : unsigned (ACCUM_BITS_N - 1 downto 0);
begin
accumulate: process(clk, reset)
begin
if reset = '1' then
accumulator <= to_unsigned(0, ACCUM_BITS_N);
sig_out <= '0';
elsif rising_edge(clk) then
accumulator <= accumulator + tuning_word_in;
sig_out <= accumulator(accumulator'high);
end if;
end process;
end;
| mit | 73bb3e80927665cc24088b5c3476478e | 0.566598 | 3.873016 | false | false | false | false |
zhlinh/vhdl_course | Assignment/FREQ_CNT/DIV_FREQ.vhd | 1 | 624 | --Frequency Divider
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DIV_FREQ IS
PORT( CLK_IN_1HZ :IN STD_LOGIC;
RST :IN STD_LOGIC;
CLK_OUT_05HZ:OUT STD_LOGIC);
END ENTITY DIV_FREQ;
ARCHITECTURE ART1 OF DIV_FREQ IS
BEGIN
PROCESS (CLK_IN_1HZ,RST)
VARIABLE CLK_OUT_TEMP:STD_LOGIC_VECTOR (1 DOWNTO 0):="00";
BEGIN
IF(RST='1')THEN
CLK_OUT_TEMP:="00";
ELSE IF(CLK_IN_1HZ 'EVENT AND CLK_IN_1HZ='1')THEN
CLK_OUT_TEMP := CLK_OUT_TEMP + "01";
END IF;
END IF;
CLK_OUT_05HZ <= CLK_OUT_TEMP(0);
END PROCESS;
END ARCHITECTURE ART1;
| apache-2.0 | c9b1351d0ef2faea3eb71feb3f20dd55 | 0.674679 | 2.486056 | false | false | false | false |
cafe-alpha/wasca | fpga_firmware/wasca/synthesis/submodules/abus_avalon_sdram_bridge.vhd | 2 | 57,235 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity abus_avalon_sdram_bridge is
port (
clock : in std_logic := '0'; -- clock.clk
abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
abus_waitrequest : out std_logic := '1'; -- .waitrequest
abus_interrupt : out std_logic := '1'; -- .interrupt
abus_direction : out std_logic := '0'; -- .direction
abus_muxing : out std_logic_vector(1 downto 0) := "01"; -- .muxing
abus_disable_out : out std_logic := '0'; -- .disableout
sdram_addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
sdram_ba : out std_logic_vector(1 downto 0); -- .ba
sdram_cas_n : out std_logic; -- .cas_n
sdram_cke : out std_logic; -- .cke
sdram_cs_n : out std_logic; -- .cs_n
sdram_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
sdram_dqm : out std_logic_vector(1 downto 0) := (others => '1'); -- .dqm
sdram_ras_n : out std_logic; -- .ras_n
sdram_we_n : out std_logic; -- .we_n
sdram_clk : out std_logic;
avalon_sdram_read : in std_logic := '0'; -- avalon_master.read
avalon_sdram_write : in std_logic := '0'; -- .write
avalon_sdram_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_sdram_address : in std_logic_vector(25 downto 0) := (others => '0'); -- .address
avalon_sdram_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_sdram_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_sdram_readdatavalid : out std_logic := '0'; -- .readdatavalid
avalon_sdram_byteenable : in std_logic_vector(1 downto 0) := (others => '0'); -- .readdata
avalon_regs_read : in std_logic := '0'; -- avalon_master.read
avalon_regs_write : in std_logic := '0'; -- .write
avalon_regs_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_regs_address : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
avalon_regs_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_regs_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_regs_readdatavalid : out std_logic := '0'; -- .readdatavalid
saturn_reset : in std_logic := '0'; -- .saturn_reset
reset : in std_logic := '0' -- reset.reset
);
end entity abus_avalon_sdram_bridge;
architecture rtl of abus_avalon_sdram_bridge is
component sniff_fifo
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
usedw : OUT STD_LOGIC_VECTOR (10 DOWNTO 0)
);
end component;
--xilinx mode
--component sniff_fifo
-- PORT
-- (
-- clk : IN STD_LOGIC;
-- srst : IN STD_LOGIC;
-- din : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
-- wr_en : IN STD_LOGIC;
-- rd_en : IN STD_LOGIC;
-- dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
-- full : OUT STD_LOGIC;
-- empty : OUT STD_LOGIC;
-- data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
-- );
--end component;
signal abus_address_ms : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_address_buf : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_addressdata_ms : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_addressdata_buf : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_chipselect_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_chipselect_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_ms : std_logic := '0'; -- .read
signal abus_read_buf : std_logic := '0'; -- .read
signal abus_write_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_write_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_read_buf2 : std_logic := '0'; -- .read
signal abus_read_buf3 : std_logic := '0'; -- .read
signal abus_read_buf4 : std_logic := '0'; -- .read
signal abus_read_buf5 : std_logic := '0'; -- .read
signal abus_read_buf6 : std_logic := '0'; -- .read
signal abus_read_buf7 : std_logic := '0'; -- .read
signal abus_write_buf2 : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_buf2 : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse : std_logic := '0'; -- .read
signal abus_write_pulse : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse_off : std_logic := '0'; -- .read
signal abus_write_pulse_off : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse_off : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_anypulse : std_logic := '0';
signal abus_anypulse2 : std_logic := '0';
signal abus_anypulse3 : std_logic := '0';
signal abus_anypulse_off : std_logic := '0';
signal abus_cspulse : std_logic := '0';
signal abus_cspulse2 : std_logic := '0';
signal abus_cspulse3 : std_logic := '0';
signal abus_cspulse4 : std_logic := '0';
signal abus_cspulse5 : std_logic := '0';
signal abus_cspulse6 : std_logic := '0';
signal abus_cspulse7 : std_logic := '0';
signal abus_cspulse_off : std_logic := '0';
signal abus_address_latched_prepatch : std_logic_vector(25 downto 0) := (others => '0'); -- abus.address prior to patching
signal abus_address_latched : std_logic_vector(25 downto 0) := (others => '0'); -- abus.address
signal abus_chipselect_latched : std_logic_vector(1 downto 0) := (others => '1'); -- abus.address
signal abus_direction_internal : std_logic := '0';
signal abus_muxing_internal : std_logic_vector(1 downto 0) := (others => '0'); -- abus.address
signal abus_data_out : std_logic_vector(15 downto 0) := (others => '0');
signal abus_data_in : std_logic_vector(15 downto 0) := (others => '0');
--signal abus_waitrequest_read : std_logic := '0';
--signal abus_waitrequest_write : std_logic := '0';
--signal abus_waitrequest_read2 : std_logic := '0';
--signal abus_waitrequest_write2 : std_logic := '0';
--signal abus_waitrequest_read3 : std_logic := '0';
--signal abus_waitrequest_write3 : std_logic := '0';
--signal abus_waitrequest_read4 : std_logic := '0';
--signal abus_waitrequest_write4 : std_logic := '0';
--signal abus_waitrequest_read_off : std_logic := '0';
--signal abus_waitrequest_write_off : std_logic := '0';
signal REG_PCNTR : std_logic_vector(15 downto 0) := (others => '0');
signal REG_STATUS : std_logic_vector(15 downto 0) := (others => '0');
signal REG_MODE : std_logic_vector(15 downto 0) := (others => '0');
signal REG_HWVER : std_logic_vector(15 downto 0) := X"0002";
signal REG_SWVER : std_logic_vector(15 downto 0) := (others => '0');
signal REG_MAPPER_READ : std_logic_vector(63 downto 0) := (others => '1');
signal REG_MAPPER_WRITE : std_logic_vector(63 downto 0) := (others => '1');
--signal sdram_read : std_logic;
--signal sdram_write : std_logic;
-- avalon_waitrequest : in std_logic := '0'; -- .waitrequest
-- avalon_address : out std_logic_vector(27 downto 0); -- .address
-- avalon_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
-- avalon_writedata : out std_logic_vector(15 downto 0); -- .writedata
-- avalon_readdatavalid : in std_logic
------------------- sdram signals ---------------
signal sdram_abus_pending : std_logic := '0'; --abus request is detected and should be parsed
signal sdram_abus_complete : std_logic := '0';
signal sdram_wait_counter : unsigned(3 downto 0) := (others => '0');
--refresh interval should be no bigger than 7.8us = 906 clock cycles
--to keep things simple, perfrorm autorefresh at 512 cycles
signal sdram_init_counter : unsigned(15 downto 0) := (others => '0');
signal sdram_autorefresh_counter : unsigned(9 downto 0) := (others => '1');
signal sdram_datain_latched : std_logic_vector(15 downto 0) := (others => '0');
signal avalon_sdram_complete : std_logic := '0';
signal avalon_sdram_reset_pending : std_logic := '0';
signal avalon_sdram_read_pending : std_logic := '0';
signal avalon_sdram_read_pending_f1 : std_logic := '0';
signal avalon_sdram_write_pending : std_logic := '0';
signal avalon_sdram_pending_address : std_logic_vector(25 downto 0) := (others => '0');
signal avalon_sdram_pending_data : std_logic_vector(15 downto 0) := (others => '0');
signal avalon_sdram_readdata_latched : std_logic_vector(15 downto 0) := (others => '0');
--signal avalon_regs_address_latched : std_logic_vector(7 downto 0) := (others => '0');
signal counter_filter_control : std_logic_vector(7 downto 0) := (others => '0');
signal counter_reset : std_logic := '0';
signal counter_count_read : std_logic := '0';
signal counter_count_write : std_logic := '0';
signal counter_value : unsigned(31 downto 0) := (others => '0');
signal sniffer_filter_control : std_logic_vector(7 downto 0) := (others => '0');
signal sniffer_data_in : std_logic_vector(15 downto 0) := (others => '0');
signal sniffer_data_in_p1 : std_logic_vector(15 downto 0) := (others => '0');
signal sniffer_data_out : std_logic_vector(15 downto 0) := (others => '0');
--signal sniffer_data_write_p1 : std_logic := '0';
signal sniffer_data_write : std_logic := '0';
signal sniffer_data_ack : std_logic := '0';
signal sniffer_fifo_content_size : std_logic_vector(10 downto 0) := (others => '0');
signal sniffer_fifo_empty : std_logic := '0';
signal sniffer_fifo_full : std_logic := '0';
signal sniffer_last_active_block : std_logic_vector(15 downto 0) := (others => '1');
signal sniffer_pending_set : std_logic := '0';
signal sniffer_pending_reset : std_logic := '0';
signal sniffer_pending_flag : std_logic := '0';
signal sniffer_pending_block : std_logic_vector(15 downto 0) := (others => '0');
signal sniffer_pending_timeout : std_logic := '0';
signal sniffer_pending_timeout_counter : std_logic_vector(31 downto 0) := (others => '0');
signal mapper_write_enable : std_logic := '1';
signal mapper_read_enable : std_logic := '1';
TYPE transaction_dir IS (DIR_NONE,DIR_WRITE,DIR_READ);
SIGNAL my_little_transaction_dir : transaction_dir := DIR_NONE;
TYPE wasca_mode_type IS (MODE_INIT,
MODE_POWER_MEMORY_05M, MODE_POWER_MEMORY_1M, MODE_POWER_MEMORY_2M, MODE_POWER_MEMORY_4M,
MODE_RAM_1M, MODE_RAM_4M,
MODE_ROM_KOF95,
MODE_ROM_ULTRAMAN,
MODE_BOOT);
SIGNAL wasca_mode : wasca_mode_type := MODE_INIT;
TYPE sdram_mode_type IS (
SDRAM_INIT0,
SDRAM_INIT1,
SDRAM_INIT2,
SDRAM_INIT3,
SDRAM_INIT4,
SDRAM_INIT5,
SDRAM_IDLE,
SDRAM_AUTOREFRESH,
SDRAM_AUTOREFRESH2,
SDRAM_ABUS_ACTIVATE,
SDRAM_ABUS_READ_AND_PRECHARGE,
SDRAM_ABUS_WRITE_AND_PRECHARGE,
SDRAM_AVALON_ACTIVATE,
SDRAM_AVALON_READ_AND_PRECHARGE,
SDRAM_AVALON_WRITE_AND_PRECHARGE
);
SIGNAL sdram_mode : sdram_mode_type := SDRAM_INIT0;
begin
abus_direction <= abus_direction_internal;
abus_muxing <= not abus_muxing_internal;
--we won't be aserting interrupt and waitrequest. because we can. can we?
abus_interrupt <= '1';
abus_waitrequest <= '1';
abus_disable_out <= '1'; --dasbling waitrequest & int outputs, so they're tristate
--ignoring functioncode, timing and addressstrobe for now
--abus transactions are async, so first we must latch incoming signals
--to get rid of metastability
process (clock)
begin
if rising_edge(clock) then
--1st stage
abus_address_ms <= abus_address;
abus_addressdata_ms <= abus_addressdata;
abus_chipselect_ms <= abus_chipselect; --work only with CS1 for now
abus_read_ms <= abus_read;
abus_write_ms <= abus_write;
--2nd stage
abus_address_buf <= abus_address_ms;
abus_addressdata_buf <= abus_addressdata_ms;
abus_chipselect_buf <= abus_chipselect_ms;
abus_read_buf <= abus_read_ms;
abus_write_buf <= abus_write_ms;
end if;
end process;
--excluding metastability protection is a bad behavior
--but it looks like we're out of more options to optimize read pipeline
--abus_read_ms <= abus_read;
--abus_read_buf <= abus_read_ms;
--abus read/write latch
process (clock)
begin
if rising_edge(clock) then
abus_write_buf2 <= abus_write_buf;
abus_read_buf2 <= abus_read_buf;
abus_read_buf3 <= abus_read_buf2;
abus_read_buf4 <= abus_read_buf3;
abus_read_buf5 <= abus_read_buf4;
abus_read_buf6 <= abus_read_buf5;
abus_read_buf7 <= abus_read_buf6;
abus_chipselect_buf2 <= abus_chipselect_buf;
abus_anypulse2 <= abus_anypulse;
abus_anypulse3 <= abus_anypulse2;
abus_cspulse2 <= abus_cspulse;
abus_cspulse3 <= abus_cspulse2;
abus_cspulse4 <= abus_cspulse3;
abus_cspulse5 <= abus_cspulse4;
abus_cspulse6 <= abus_cspulse5;
abus_cspulse7 <= abus_cspulse6;
end if;
end process;
--abus write/read pulse is a falling edge since read and write signals are negative polarity
--abus_write_pulse <= abus_write_buf2 and not abus_write_buf;
abus_write_pulse <= abus_write_buf and not abus_write_ms;
--abus_read_pulse <= abus_read_buf2 and not abus_read_buf;
abus_read_pulse <= abus_read_buf and not abus_read_ms;
abus_chipselect_pulse <= abus_chipselect_buf and not abus_chipselect_ms;
--abus_write_pulse_off <= abus_write_buf and not abus_write_buf2;
abus_write_pulse_off <= abus_write_ms and not abus_write_buf;
--abus_read_pulse_off <= abus_read_buf and not abus_read_buf2;
abus_read_pulse_off <= abus_read_ms and not abus_read_buf;
--abus_chipselect_pulse_off <= abus_chipselect_buf and not abus_chipselect_buf2;
abus_chipselect_pulse_off <= abus_chipselect_ms and not abus_chipselect_buf;
abus_anypulse <= abus_write_pulse(0) or abus_write_pulse(1) or abus_read_pulse or
abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_anypulse_off <= abus_write_pulse_off(0) or abus_write_pulse_off(1) or abus_read_pulse_off or
abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
abus_cspulse <= abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_cspulse_off <= abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
--whatever pulse we've got, latch address
--it might be latched twice per transaction, but it's not a problem
--multiplexer was switched to address after previous transaction or after boot,
--so we have address ready to latch
process (clock)
begin
if rising_edge(clock) then
if abus_cspulse = '1' then
abus_address_latched_prepatch <= abus_address & abus_addressdata_buf(11) & abus_addressdata_buf(12) & abus_addressdata_buf(9) & abus_addressdata_buf(10)
& abus_addressdata_buf(2) & abus_addressdata_buf(1) & abus_addressdata_buf(3) & abus_addressdata_buf(8)
& abus_addressdata_buf(13) & abus_addressdata_buf(14) & abus_addressdata_buf(15) & abus_addressdata_buf(4)
& abus_addressdata_buf(5) & abus_addressdata_buf(6) & abus_addressdata_buf(0) & abus_addressdata_buf(7);
end if;
end if;
end process;
--patching abus_address_latched : for RAM 1M mode A19 and A20 should be set to zero
--trying to do this asynchronously
abus_address_latched <= abus_address_latched_prepatch(25 downto 21)&"00"&abus_address_latched_prepatch(18 downto 0) when wasca_mode = MODE_RAM_1M and abus_address_latched_prepatch(24 downto 21) = "0010"
else abus_address_latched_prepatch;
--mapper write enable decode
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_buf(0) = '0' then
mapper_write_enable <= REG_MAPPER_WRITE(to_integer(unsigned(abus_address_latched(24 downto 20))));
elsif abus_chipselect_buf(1) = '0' then
mapper_write_enable <= REG_MAPPER_WRITE(32+to_integer(unsigned(abus_address_latched(23 downto 20))));
elsif abus_chipselect_buf(2) = '0' then
mapper_write_enable <= REG_MAPPER_WRITE(48);
end if;
end if;
end process;
--mapper read enable decode
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_buf(0) = '0' then
mapper_read_enable <= REG_MAPPER_READ(to_integer(unsigned(abus_address_latched(24 downto 20))));
elsif abus_chipselect_buf(1) = '0' then
mapper_read_enable <= REG_MAPPER_READ(32+to_integer(unsigned(abus_address_latched(23 downto 20))));
elsif abus_chipselect_buf(2) = '0' then
mapper_read_enable <= REG_MAPPER_READ(48);
end if;
end if;
end process;
--latch transaction direction
process (clock)
begin
if rising_edge(clock) then
if abus_write_pulse(0) = '1' or abus_write_pulse(1) = '1' then
my_little_transaction_dir <= DIR_WRITE;
elsif abus_read_pulse = '1' then
my_little_transaction_dir <= DIR_READ;
elsif abus_anypulse_off = '1' and abus_cspulse_off = '0' then --ending anything but not cs
my_little_transaction_dir <= DIR_NONE;
end if;
end if;
end process;
--latch chipselect number
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_pulse(0) = '1' then
abus_chipselect_latched <= "00";
elsif abus_chipselect_pulse(1) = '1' then
abus_chipselect_latched <= "01";
elsif abus_chipselect_pulse(2) = '1' then
abus_chipselect_latched <= "10";
elsif abus_cspulse_off = '1' then
abus_chipselect_latched <= "11";
end if;
end if;
end process;
--if valid transaction captured, switch to corresponding multiplex mode
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_latched = "11" then
--chipselect deasserted
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "01"; --address
else
--chipselect asserted
case (my_little_transaction_dir) is
when DIR_NONE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
when DIR_READ =>
abus_direction_internal <= mapper_read_enable;--'1'; --active
abus_muxing_internal <= "10"; --data
when DIR_WRITE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
end case;
end if;
end if;
end process;
--abus_disable_out <= '1' when abus_chipselect_latched(1) = '1' else
-- '0';
--sync mux for abus read requests
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_latched = "00" then
--CS0 access
if abus_address_latched(24 downto 0) = "1"&X"FF0FFE" then
--wasca specific SD card control register
abus_data_out <= X"CDCD";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF0" then
--wasca prepare counter
abus_data_out <= REG_PCNTR;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF2" then
--wasca status register
abus_data_out <= REG_STATUS;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF4" then
--wasca mode register
abus_data_out <= REG_MODE;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF6" then
--wasca hwver register
abus_data_out <= REG_HWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF8" then
--wasca swver register
abus_data_out <= REG_SWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFA" then
--wasca signature "wa"
abus_data_out <= X"7761";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFC" then
--wasca signature "sc"
abus_data_out <= X"7363";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFE" then
--wasca signature "a "
abus_data_out <= X"6120";
else
--normal CS0 read access
case wasca_mode is
when MODE_INIT => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_1M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_2M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_4M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_RAM_1M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_RAM_4M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_ROM_KOF95 => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_ROM_ULTRAMAN => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_BOOT => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
end case;
end if;
elsif abus_chipselect_latched = "01" then
--CS1 access
if ( abus_address_latched(23 downto 0) = X"FFFFFE" or abus_address_latched(23 downto 0) = X"FFFFFC" ) then
--saturn cart id register
case wasca_mode is
when MODE_INIT => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FF21";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FF22";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FF23";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FF24";
when MODE_RAM_1M => abus_data_out <= X"FF5A";
when MODE_RAM_4M => abus_data_out <= X"FF5C";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
else
--normal CS1 access
case wasca_mode is
when MODE_INIT => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_1M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_2M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_4M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_RAM_1M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_RAM_4M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_ROM_KOF95 => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_ROM_ULTRAMAN => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_BOOT => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
end case;
end if;
else
--CS2 access
abus_data_out <= X"EEEE";
end if;
end if;
end process;
--if abus write access is detected, disable abus wait immediately
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched /= "11" and abus_cspulse7 = '1' then
-- abus_waitrequest_write <= '1';
-- else
-- abus_waitrequest_write <= '0';
-- end if;
-- end if;
-- end process;
--wasca mode register write
--reset
process (clock)
begin
if rising_edge(clock) then
--if saturn_reset='0' then wasca_mode <= MODE_INIT;
--els
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched = "00" and abus_cspulse7 = '1' and
abus_address_latched(23 downto 0) = X"FFFFF4" then
--wasca mode register
REG_MODE <= abus_data_in;
case (abus_data_in (3 downto 0)) is
when X"1" => wasca_mode <= MODE_POWER_MEMORY_05M;
when X"2" => wasca_mode <= MODE_POWER_MEMORY_1M;
when X"3" => wasca_mode <= MODE_POWER_MEMORY_2M;
when X"4" => wasca_mode <= MODE_POWER_MEMORY_4M;
when others =>
case (abus_data_in (7 downto 4)) is
when X"1" => wasca_mode <= MODE_RAM_1M;
when X"2" => wasca_mode <= MODE_RAM_4M;
when others =>
case (abus_data_in (11 downto 8)) is
when X"1" => wasca_mode <= MODE_ROM_KOF95;
when X"2" => wasca_mode <= MODE_ROM_ULTRAMAN;
when others => null;-- wasca_mode <= MODE_INIT;
end case;
end case;
end case;
end if;
end if;
end process;
abus_data_in <= abus_addressdata_buf;
--working only if direction is 1
abus_addressdata <= (others => 'Z') when abus_direction_internal='0' else
abus_data_out;
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- abus_waitrequest_read2 <= abus_waitrequest_read;
-- --abus_waitrequest_read3 <= abus_waitrequest_read2;
-- --abus_waitrequest_read4 <= abus_waitrequest_read3;
-- abus_waitrequest_write2 <= abus_waitrequest_write;
-- --abus_waitrequest_write3 <= abus_waitrequest_write3;
-- --abus_waitrequest_write4 <= abus_waitrequest_write4;
-- end if;
-- end process;
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- abus_waitrequest_read_off <= '0';
-- abus_waitrequest_write_off <= '0';
-- if abus_waitrequest_read = '0' and abus_waitrequest_read2 = '1' then
-- abus_waitrequest_read_off <= '1';
-- end if;
-- if abus_waitrequest_write = '0' and abus_waitrequest_write2 = '1' then
-- abus_waitrequest_write_off <= '1';
-- end if;
-- end if;
-- end process;
--process (clock)
--begin
-- if rising_edge(clock) then
-- --if abus_read_pulse='1' or abus_write_pulse(0)='1' or abus_write_pulse(1)='1' then
-- --if abus_anypulse = '1' then
-- if abus_chipselect_pulse(0) = '1' or abus_chipselect_pulse(1) = '1' then
-- abus_waitrequest <= '0';
-- elsif abus_waitrequest_read_off='1' or abus_waitrequest_write_off='1' then
-- abus_waitrequest <= '1';
-- end if;
-- end if;
--end process;
--abus_waitrequest <= not (abus_waitrequest_read or abus_waitrequest_write);
--Avalon regs read interface
process (clock)
begin
if rising_edge(clock) then
avalon_regs_readdatavalid <= '0';
sniffer_data_ack <= '0';
if avalon_regs_read = '1' then
avalon_regs_readdatavalid <= '1';
case avalon_regs_address(7 downto 0) is
when X"C0" =>
avalon_regs_readdata <= REG_MAPPER_READ(15 downto 0);
when X"C2" =>
avalon_regs_readdata <= REG_MAPPER_READ(31 downto 16);
when X"C4" =>
avalon_regs_readdata <= REG_MAPPER_READ(47 downto 32);
when X"C6" =>
avalon_regs_readdata <= REG_MAPPER_READ(63 downto 48);
when X"C8" =>
avalon_regs_readdata <= REG_MAPPER_WRITE(15 downto 0);
when X"CA" =>
avalon_regs_readdata <= REG_MAPPER_WRITE(31 downto 16);
when X"CC" =>
avalon_regs_readdata <= REG_MAPPER_WRITE(47 downto 32);
when X"CE" =>
avalon_regs_readdata <= REG_MAPPER_WRITE(63 downto 48);
when X"D0" =>
avalon_regs_readdata <= std_logic_vector(counter_value(15 downto 0));
when X"D2" =>
avalon_regs_readdata <= std_logic_vector(counter_value(31 downto 16));
when X"D4" =>
avalon_regs_readdata(15 downto 8) <= X"00";
avalon_regs_readdata(7 downto 0) <= counter_filter_control;
--D6 is a reset, writeonly
--D8 to DE are reserved
when X"E0" =>
avalon_regs_readdata <= sniffer_data_out;
sniffer_data_ack <= '1';
--E2 to E6 are reserved
when X"E8" =>
avalon_regs_readdata(15 downto 8) <= X"00";
avalon_regs_readdata(7 downto 0) <= sniffer_filter_control;
when X"EA" =>
avalon_regs_readdata(15 downto 12) <= "0000";
avalon_regs_readdata(11) <= sniffer_fifo_full;
avalon_regs_readdata(10 downto 0) <= sniffer_fifo_content_size;
--EC to EE are reserved
when X"F0" =>
avalon_regs_readdata <= REG_PCNTR;
when X"F2" =>
avalon_regs_readdata <= REG_STATUS;
when X"F4" =>
avalon_regs_readdata <= REG_MODE;
when X"F6" =>
avalon_regs_readdata <= REG_HWVER;
when X"F8" =>
avalon_regs_readdata <= REG_SWVER;
when X"FA" =>
avalon_regs_readdata <= X"ABCD"; --for debug, remove later
when others =>
avalon_regs_readdata <= REG_HWVER; --to simplify mux
end case;
end if;
end if;
end process;
--Avalon regs write interface
process (clock)
begin
if rising_edge(clock) then
counter_reset <= '0';
if avalon_regs_write= '1' then
case avalon_regs_address(7 downto 0) is
when X"C0" =>
REG_MAPPER_READ(15 downto 0) <= avalon_regs_writedata;
when X"C2" =>
REG_MAPPER_READ(31 downto 16) <= avalon_regs_writedata;
when X"C4" =>
REG_MAPPER_READ(47 downto 32) <= avalon_regs_writedata;
when X"C6" =>
REG_MAPPER_READ(63 downto 48) <= avalon_regs_writedata;
when X"C8" =>
REG_MAPPER_WRITE(15 downto 0) <= avalon_regs_writedata;
when X"CA" =>
REG_MAPPER_WRITE(31 downto 16) <= avalon_regs_writedata;
when X"CC" =>
REG_MAPPER_WRITE(47 downto 32) <= avalon_regs_writedata;
when X"CE" =>
REG_MAPPER_WRITE(63 downto 48) <= avalon_regs_writedata;
when X"D0" =>
null;
when X"D2" =>
null;
when X"D4" =>
counter_filter_control <= avalon_regs_writedata(7 downto 0);
when X"D6" =>
counter_reset <= '1';
--D8 to DE are reserved
when X"E0" =>
null;
--E2 to E6 are reserved
when X"E8" =>
sniffer_filter_control <= avalon_regs_writedata(7 downto 0);
when X"EA" =>
null;
--EC to EE are reserved
when X"F0" =>
REG_PCNTR <= avalon_regs_writedata;
when X"F2" =>
REG_STATUS <= avalon_regs_writedata;
when X"F4" =>
null;
when X"F6" =>
null;
when X"F8" =>
REG_SWVER <= avalon_regs_writedata;
when others =>
null;
end case;
end if;
end if;
end process;
--Avalon regs interface is only regs, so always ready to write.
avalon_regs_waitrequest <= '0';
---------------------- sdram avalon interface -------------------
--waitrequest should be issued as long as we received some command from avalon
--keep it until the command is processed
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (avalon_sdram_read = '1' or avalon_sdram_write = '1') and avalon_sdram_read_pending = '0' and avalon_sdram_write_pending = '0' then
-- avalon_sdram_waitrequest <= '1';
-- elsif avalon_sdram_complete = '1' then
-- avalon_sdram_waitrequest <= '0';
-- end if;
-- end if;
-- end process;
--to talk to sdram interface, avalon requests are latched until sdram is ready to process them
process (clock)
begin
if rising_edge(clock) then
if avalon_sdram_reset_pending = '1' then
avalon_sdram_read_pending <= '0';
avalon_sdram_write_pending <= '0';
elsif avalon_sdram_read = '1' then
avalon_sdram_read_pending <= '1';
avalon_sdram_pending_address <= avalon_sdram_address;
elsif avalon_sdram_write = '1' then
avalon_sdram_write_pending <= '1';
avalon_sdram_pending_address <= avalon_sdram_address;
avalon_sdram_pending_data<= avalon_sdram_writedata;
end if;
end if;
end process;
avalon_sdram_read_pending_f1 <= avalon_sdram_read_pending when rising_edge(clock);
--avalon_sdram_readdatavalid <= avalon_sdram_complete and avalon_sdram_read_pending_f1;
avalon_sdram_readdata <= avalon_sdram_readdata_latched;
--avalon_sdram_readdata_latched should be set by sdram interface directly
------------------------------ SDRAM stuff ---------------------------------------
-- abus pending flag.
-- abus_anypulse might appear up to 3-4 times at transaction start, so we shouldn't issue ack until at least 3-4 cycles from the start
process (clock)
begin
if rising_edge(clock) then
if abus_cspulse2 = '1' then
sdram_abus_pending <= '1';
elsif sdram_abus_complete = '1' then
sdram_abus_pending <= '0';
end if;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
sdram_autorefresh_counter <= sdram_autorefresh_counter + 1;
case sdram_mode is
when SDRAM_INIT0 =>
--first stage init. cke off, dqm high, others Z
sdram_addr <= (others => 'Z');
sdram_ba <= "ZZ";
sdram_cas_n <= 'Z';
sdram_cke <= '0';
sdram_cs_n <= 'Z';
sdram_dq <= (others => 'Z');
sdram_ras_n <= 'Z';
sdram_we_n <= 'Z';
sdram_dqm <= "11";
sdram_init_counter <= sdram_init_counter + 1;
avalon_sdram_readdatavalid <= '0';
if sdram_init_counter(15) = '1' then
-- 282 us from the start elapsed, moving to next init
sdram_init_counter <= (others => '0');
sdram_mode <= SDRAM_INIT1;
end if;
when SDRAM_INIT1 =>
--another stage init. cke on, dqm high, set other pin
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_cke <= '1';
sdram_cs_n <= '0';
sdram_dq <= (others => 'Z');
sdram_ras_n <= '1';
sdram_we_n <= '1';
sdram_dqm <= "11";
sdram_init_counter <= sdram_init_counter + 1;
if sdram_init_counter(10) = '1' then
-- some smaller time elapsed, moving to next init - issue "precharge all"
sdram_mode <= SDRAM_INIT2;
sdram_ras_n <= '0';
sdram_we_n <= '0';
sdram_addr(10) <= '1';
sdram_wait_counter <= to_unsigned(1,4);
end if;
when SDRAM_INIT2 =>
--move on with init
sdram_ras_n <= '1';
sdram_we_n <= '1';
sdram_addr(10) <= '0';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
-- issue "auto refresh"
sdram_mode <= SDRAM_INIT3;
sdram_ras_n <= '0';
sdram_cas_n <= '0';
sdram_wait_counter <= to_unsigned(7,4);
end if;
when SDRAM_INIT3 =>
--move on with init
sdram_ras_n <= '1';
sdram_cas_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
-- issue "auto refresh"
sdram_mode <= SDRAM_INIT4;
sdram_ras_n <= '0';
sdram_cas_n <= '0';
sdram_wait_counter <= to_unsigned(7,4);
end if;
when SDRAM_INIT4 =>
--move on with init
sdram_ras_n <= '1';
sdram_cas_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
-- issue "mode register set command"
sdram_mode <= SDRAM_INIT5;
sdram_ras_n <= '0';
sdram_cas_n <= '0';
sdram_we_n <= '0';
sdram_addr <= "0001000110000"; --write single, no testmode, cas 3, burst seq, burst len 1
sdram_wait_counter <= to_unsigned(10,4);
end if;
when SDRAM_INIT5 =>
--move on with init
sdram_ras_n <= '1';
sdram_cas_n <= '1';
sdram_we_n <= '1';
sdram_addr <= (others => '0');
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
-- init done, switching to working mode
sdram_mode <= SDRAM_IDLE;
end if;
when SDRAM_IDLE =>
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_cke <= '1';
sdram_cs_n <= '0';
sdram_dq <= (others => 'Z');
sdram_ras_n <= '1';
sdram_we_n <= '1';
sdram_dqm <= "11";
sdram_abus_complete <= '0';
avalon_sdram_complete <= '0';
avalon_sdram_readdatavalid <= '0';
avalon_sdram_waitrequest <= '1';
avalon_sdram_reset_pending <= '0';
-- in idle mode we should check if any of the events occured:
-- 1) abus transaction detected - priority 0
-- 2) avalon transaction detected - priority 1
-- 3) autorefresh counter exceeded threshold - priority 2
-- if none of these events occur, we keep staying in the idle mode
if sdram_abus_pending = '1' and sdram_abus_complete = '0' then
sdram_mode <= SDRAM_ABUS_ACTIVATE;
--something on abus, address should be stable already (is it???), so we activate row now
sdram_ras_n <= '0';
sdram_addr <= abus_address_latched(23 downto 11);
sdram_ba(0) <= abus_address_latched(24);
sdram_ba(1) <= abus_chipselect_buf(0); --if CS0 is active, it's 0, else it's 1
if abus_write_buf = "11" then
sdram_dqm <= "00"; --it's a read
sdram_wait_counter <= to_unsigned(3,4); -- tRCD = 21ns min ; 3 cycles @ 116mhz = 25ns
else
sdram_dqm(0) <= abus_write_buf(1); --it's a write
sdram_dqm(1) <= abus_write_buf(0); --it's a write
sdram_wait_counter <= to_unsigned(5,4); -- for writing we use a little longer activate delay, so that the data at the a-bus will become ready
end if;
elsif (avalon_sdram_read_pending = '1' or avalon_sdram_write_pending = '1') and avalon_sdram_complete = '0' then
sdram_mode <= SDRAM_AVALON_ACTIVATE;
--something on avalon, activating!
sdram_ras_n <= '0';
sdram_addr <= avalon_sdram_pending_address(23 downto 11);
sdram_ba <= avalon_sdram_pending_address(25 downto 24);
sdram_wait_counter <= to_unsigned(2,4); -- tRCD = 21ns min ; 3 cycles @ 116mhz = 25ns
if avalon_sdram_read_pending = '1' then
sdram_dqm <= "00";
else
sdram_dqm(0) <= not avalon_sdram_byteenable(0);
sdram_dqm(1) <= not avalon_sdram_byteenable(1);
end if;
elsif sdram_autorefresh_counter(9) = '1' then --512 cycles
sdram_mode <= SDRAM_AUTOREFRESH;
--first stage of autorefresh issues "precharge all" command
sdram_ras_n <= '0';
sdram_we_n <= '0';
sdram_addr(10) <= '1';
sdram_autorefresh_counter <= (others => '0');
sdram_wait_counter <= to_unsigned(1,4); -- precharge all is fast
end if;
when SDRAM_AUTOREFRESH =>
sdram_ras_n <= '1';
sdram_we_n <= '1';
sdram_addr(10) <= '0';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
--switching to ABUS in case of ABUS request caught us between refresh stages
if sdram_abus_pending = '1' then
sdram_mode <= SDRAM_ABUS_ACTIVATE;
--something on abus, address should be stable already (is it???), so we activate row now
sdram_ras_n <= '0';
sdram_addr <= abus_address_latched(23 downto 11);
sdram_ba(0) <= abus_address_latched(24);
sdram_ba(1) <= abus_chipselect_buf(0); --if CS0 is active, it's 0, else it's 1
sdram_wait_counter <= to_unsigned(3,4); -- tRCD = 21ns min ; 3 cycles @ 116mhz = 25ns
if abus_write_buf = "11" then
sdram_dqm <= "00"; --it's a read
else
sdram_dqm(0) <= abus_write_buf(1); --it's a write
sdram_dqm(1) <= abus_write_buf(0); --it's a write
end if;
else
-- second autorefresh stage - autorefresh command
sdram_cas_n <= '0';
sdram_ras_n <= '0';
sdram_wait_counter <= to_unsigned(7,4); --7 cut to 6 -- tRC = 63ns min ; 8 cycles @ 116mhz = 67ns
sdram_mode <= SDRAM_AUTOREFRESH2;
end if;
end if;
when SDRAM_AUTOREFRESH2 =>
--here we wait for autorefresh to end and move on to idle state
sdram_cas_n <= '1';
sdram_ras_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
end if;
when SDRAM_ABUS_ACTIVATE =>
--while waiting for row to be activated, we choose where to switch to - read or write
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_ras_n <= '1';
--we keep updating dqm in activate stage, because it could change after abus pending
if abus_write_buf = "11" then
sdram_dqm <= "00"; --it's a read
else
sdram_dqm(0) <= abus_write_buf(1); --it's a write
sdram_dqm(1) <= abus_write_buf(0); --it's a write
end if;
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
if my_little_transaction_dir = DIR_WRITE and mapper_write_enable = '1' then --if mapper write is not enabled, doing read instead
sdram_mode <= SDRAM_ABUS_WRITE_AND_PRECHARGE;
counter_count_write <= '1';
sdram_cas_n <= '0';
sdram_we_n <= '0';
sdram_dq <= abus_data_in(7 downto 0)&abus_data_in(15 downto 8);
sdram_addr <= "001"&abus_address_latched(10 downto 1);
sdram_ba(0) <= abus_address_latched(24);
sdram_ba(1) <= abus_chipselect_buf(0); --if CS0 is active, it's 0, else it's 1
sdram_wait_counter <= to_unsigned(4,4); -- tRP = 21ns min ; 3 cycles @ 116mhz = 25ns
else --if my_little_transaction_dir = DIR_READ then
sdram_mode <= SDRAM_ABUS_READ_AND_PRECHARGE;
counter_count_read <= '1';
sdram_cas_n <= '0';
sdram_addr <= "001"&abus_address_latched(10 downto 1);
sdram_ba(0) <= abus_address_latched(24);
sdram_ba(1) <= abus_chipselect_buf(0); --if CS0 is active, it's 0, else it's 1
sdram_wait_counter <= to_unsigned(4,4); --5 cut to 4 -- tRP = 21ns min ; 3 cycles @ 116mhz = 25ns
--else
-- this is an invalid transaction - either it's for CS2 or from an unmapped range
-- but the bank is already prepared, and we need to precharge it
-- we can issue a precharge command, but read&precharge command will have the same effect, so we use that one
end if;
end if;
when SDRAM_ABUS_READ_AND_PRECHARGE =>
--move on with reading, bus is a Z after idle
--data should be latched at 2nd or 3rd clock (cas=2 or cas=3)
counter_count_read <= '0';
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 1 then
sdram_datain_latched <= sdram_dq;
end if;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
sdram_abus_complete <= '1';
sdram_dqm <= "11";
end if;
when SDRAM_ABUS_WRITE_AND_PRECHARGE =>
--move on with writing
counter_count_write <= '0';
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_we_n <= '1';
sdram_dq <= (others => 'Z');
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
sdram_abus_complete <= '1';
sdram_dqm <= "11";
end if;
when SDRAM_AVALON_ACTIVATE =>
--while waiting for row to be activated, we choose where to switch to - read or write
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_ras_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
if avalon_sdram_read_pending = '1' then
sdram_mode <= SDRAM_AVALON_READ_AND_PRECHARGE;
sdram_ba <= avalon_sdram_pending_address(25 downto 24);
sdram_cas_n <= '0';
sdram_addr <= "001"&avalon_sdram_pending_address(10 downto 1);
sdram_wait_counter <= to_unsigned(4,4); -- tRP = 21ns min ; 3 cycles @ 116mhz = 25ns
else
sdram_mode <= SDRAM_AVALON_WRITE_AND_PRECHARGE;
sdram_cas_n <= '0';
sdram_we_n <= '0';
sdram_ba <= avalon_sdram_pending_address(25 downto 24);
sdram_dq <= avalon_sdram_pending_data;
sdram_addr <= "001"&avalon_sdram_pending_address(10 downto 1);
sdram_wait_counter <= to_unsigned(4,4); -- tRP = 21ns min ; 3 cycles @ 116mhz = 25ns
end if;
end if;
when SDRAM_AVALON_READ_AND_PRECHARGE =>
--move on with reading, bus is a Z after idle
--data should be latched at 2nd or 3rd clock (cas=2 or cas=3)
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 1 then
avalon_sdram_readdata_latched <= sdram_dq;
avalon_sdram_waitrequest <= '0';
end if;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
avalon_sdram_complete <= '1';
sdram_dqm <= "11";
avalon_sdram_waitrequest <= '1';
avalon_sdram_reset_pending <= '1';
avalon_sdram_readdatavalid <= '1';--'0';
end if;
when SDRAM_AVALON_WRITE_AND_PRECHARGE =>
--move on with writing
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_we_n <= '1';
sdram_dq <= (others => 'Z');
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 1 then
avalon_sdram_reset_pending <= '1';
avalon_sdram_waitrequest <= '0';
end if;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
avalon_sdram_complete <= '1';
sdram_dqm <= "11";
avalon_sdram_waitrequest <= '1';
avalon_sdram_reset_pending <= '0';
end if;
end case;
end if;
end process;
sdram_clk <= clock;
------------------------------ A-bus transactions counter ---------------------------------------
-- counter filters transactions transferred over a-bus and counts them
-- for writes, 8-bit transactions are counted as 1 byte, 16-bit as 2 bytes
-- for reads, every access is counted as 2 bytes
-- filter control :
-- bit 0 - read
-- bit 1 - write
-- bit 2 - CS0
-- bit 3 - CS1
-- bit 4 - CS2
process (clock)
begin
if rising_edge(clock) then
if counter_reset = '1' then
counter_value <= (others =>'0');
elsif counter_count_write='1' and counter_filter_control(1) = '1' then
--write detected, checking state
if abus_chipselect_buf(0) = '0' and counter_filter_control(2) = '1' then
if abus_write_buf="00" then
counter_value <= counter_value + 2;
else
counter_value <= counter_value + 1;
end if;
elsif abus_chipselect_buf(1) = '0' and counter_filter_control(3) = '1' then
if abus_write_buf="00" then
counter_value <= counter_value + 2;
else
counter_value <= counter_value + 1;
end if;
elsif abus_chipselect_buf(2) = '0' and counter_filter_control(4) = '1' then
if abus_write_buf="00" then
counter_value <= counter_value + 2;
else
counter_value <= counter_value + 1;
end if;
end if;
elsif counter_count_read='1' and counter_filter_control(0) = '1' then
--read detected, checking state
if abus_chipselect_buf(0) = '0' and counter_filter_control(2) = '1' then
counter_value <= counter_value + 2;
elsif abus_chipselect_buf(1) = '0' and counter_filter_control(3) = '1' then
counter_value <= counter_value + 2;
elsif abus_chipselect_buf(2) = '0' and counter_filter_control(4) = '1' then
counter_value <= counter_value + 2;
end if;
end if;
end if;
end process;
------------------------------ A-bus sniffer ---------------------------------------
--fifo should be written in 2 cases
-- 1) write was done to a different block
-- 2) no write within 10 ms
process (clock)
begin
if rising_edge(clock) then
sniffer_pending_set <= '0';
if counter_count_write='1' and sniffer_filter_control(1) = '1' then
--write detected, checking state
if abus_chipselect_buf(0) = '0' and sniffer_filter_control(2) = '1' then
sniffer_pending_set <= '1';
elsif abus_chipselect_buf(1) = '0' and sniffer_filter_control(3) = '1' then
sniffer_pending_set <= '1';
elsif abus_chipselect_buf(2) = '0' and sniffer_filter_control(4) = '1' then
sniffer_pending_set <= '1';
end if;
elsif counter_count_read='1' and sniffer_filter_control(0) = '1' then
--read detected, checking state
if abus_chipselect_buf(0) = '0' and sniffer_filter_control(2) = '1' then
sniffer_pending_set <= '1';
elsif abus_chipselect_buf(1) = '0' and sniffer_filter_control(3) = '1' then
sniffer_pending_set <= '1';
elsif abus_chipselect_buf(2) = '0' and sniffer_filter_control(4) = '1' then
sniffer_pending_set <= '1';
end if;
end if;
end if;
end process;
--if an access passed thru filter, set the request as pending
process (clock)
begin
if rising_edge(clock) then
if sniffer_pending_set = '1' then
sniffer_pending_flag <= '1';
sniffer_pending_block <= abus_address_latched(24 downto 9);
elsif sniffer_pending_reset = '1' then
sniffer_pending_flag <= '0';
end if;
end if;
end process;
--if we have a pending request, and it's for a different block, issue write
--if we don't have eny requests, but the timeout fired, issue write as well
process (clock)
begin
if rising_edge(clock) then
sniffer_pending_reset <= '0';
sniffer_data_write <= '0';
if sniffer_pending_flag = '1' and sniffer_pending_block /= sniffer_last_active_block then
sniffer_data_write <= '1';
sniffer_last_active_block <= sniffer_pending_block;
sniffer_pending_reset <= '1';
elsif sniffer_pending_timeout = '1' then
sniffer_data_write <= '1';
sniffer_last_active_block <= sniffer_pending_block;
sniffer_pending_reset <= '1';
end if;
end if;
end process;
--timeout counter. resets when another pending is set
process (clock)
begin
if rising_edge(clock) then
if sniffer_pending_set = '1' then
sniffer_pending_timeout_counter <= (others => '0');
elsif sniffer_pending_timeout_counter < std_logic_vector(to_unsigned(134217728,32)) then
sniffer_pending_timeout_counter <= std_logic_vector(unsigned(sniffer_pending_timeout_counter) + 1);
end if;
end if;
end process;
--timeout comparator @ 10ms = 1160000
process (clock)
begin
if rising_edge(clock) then
sniffer_pending_timeout <= '0';
if sniffer_pending_timeout_counter = std_logic_vector(to_unsigned(1160000,32)) then
sniffer_pending_timeout <= '1';
end if;
end if;
end process;
sniffer_data_in_p1(15 downto 0) <= sniffer_last_active_block when rising_edge(clock);
sniffer_data_in <= sniffer_data_in_p1 when rising_edge(clock);
--sniffer_data_write <= sniffer_data_write_p1 when rising_edge(clock);
sniff_fifo_inst : sniff_fifo PORT MAP (
clock => clock,
data => sniffer_data_in,
rdreq => sniffer_data_ack,
wrreq => sniffer_data_write,
empty => sniffer_fifo_empty,
full => sniffer_fifo_full,
q => sniffer_data_out,
usedw => sniffer_fifo_content_size
);
-- --xilinx mode
-- sniff_fifo_inst : sniff_fifo PORT MAP (
-- clk => clock,
-- srst => '0',
-- din => sniffer_data_in,
-- rd_en => sniffer_data_ack,
-- wr_en => sniffer_data_write,
-- empty => sniffer_fifo_empty,
-- full => sniffer_fifo_full,
-- dout => sniffer_data_out,
-- data_count => sniffer_fifo_content_size
-- );
end architecture rtl; -- of sega_saturn_abus_slave
| gpl-2.0 | a91e1872a1275622aa49e171701abb02 | 0.559221 | 3.402997 | false | false | false | false |
jz0229/open-ephys-pcie | oepcie_host_firmware/HDLs/TB_hs_com_control.vhd | 1 | 2,083 | --------------------------------------------------------------------------------
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
use work.myDeclare.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TB_hs_com_control IS
END TB_hs_com_control;
ARCHITECTURE behavior OF TB_hs_com_control IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT hs_com_control
PORT(
bus_clk : IN std_logic;
global_reset : IN std_logic;
hs_com_fifo_data : OUT std_logic_vector(31 downto 0);
dev_reset_in : in std_logic;
hs_com_fifo_enb : OUT std_logic
);
END COMPONENT;
--Inputs
signal bus_clk : std_logic := '0';
signal global_reset : std_logic := '0';
signal dev_reset_in : std_logic := '0';
--Outputs
signal hs_com_fifo_data : std_logic_vector(31 downto 0);
signal hs_com_fifo_enb : std_logic;
-- Clock period definitions
constant bus_clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: hs_com_control PORT MAP (
bus_clk => bus_clk,
global_reset => global_reset,
dev_reset_in => dev_reset_in,
hs_com_fifo_data => hs_com_fifo_data,
hs_com_fifo_enb => hs_com_fifo_enb
);
-- Clock process definitions
bus_clk_process :process
begin
bus_clk <= '0';
wait for bus_clk_period/2;
bus_clk <= '1';
wait for bus_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
global_reset <= '1';
dev_reset_in <= '1';
wait for 100 ns;
global_reset <= '0';
dev_reset_in <= '0';
wait for 5 ms;
global_reset <= '1';
wait for 100 ns;
global_reset <= '0';
wait;
end process;
END;
| mit | 9b30ea0c8d93eb19df6eca4debcfc32e | 0.533845 | 3.673721 | false | false | false | false |
albayaty/Video-Game-Engine | EDK/NES-Controller/user_logic.vhd | 1 | 11,238 | -- ==============================================
-- Copyright © 2014 Ali M. Al-Bayaty
--
-- Video-Game-Engine is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- any later version.
--
-- Video-Game-Engine is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- ==============================================
--
-- Video Game Engine Project
-- ( EDK: NES User Logic VHDL )
--
-- MSEE student: Ali M. Al-Bayaty
-- EE659: System-On-Chip
-- Personal website: <http://albayaty.github.io/>
-- Source code link: <https://github.com/albayaty/Video-Game-Engine.git>
--
-- ==============================================
--
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Sun Oct 16 17:16:09 2011 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 1
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
reset : in STD_LOGIC;
led : out STD_LOGIC_VECTOR(0 to 7);
nes_latch : out STD_LOGIC;
nes_clk : out STD_LOGIC;
nes_data : in STD_LOGIC;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
component nes_controller
Port ( reset : in STD_LOGIC;
clk_50 : in STD_LOGIC;
led : out STD_LOGIC_VECTOR(0 to 7);
nes_latch : out STD_LOGIC;
nes_clk : out STD_LOGIC;
nes_data : in STD_LOGIC );
end component;
signal led_buf: STD_LOGIC_VECTOR(0 to 31);
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg_write_sel : std_logic_vector(0 to 0);
signal slv_reg_read_sel : std_logic_vector(0 to 0);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
nesmodule: nes_controller port map (
reset => reset,
clk_50 => Bus2IP_Clk,
led => led_buf(24 to 31),
nes_latch => nes_latch,
nes_clk => nes_clk,
nes_data => nes_data );
led <= led_buf(24 to 31);
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(0 to 0);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 0);
slv_write_ack <= Bus2IP_WrCE(0);
slv_read_ack <= Bus2IP_RdCE(0);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
else
case slv_reg_write_sel is
when "1" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0 ) is
begin
case slv_reg_read_sel is
when "1" => slv_ip2bus_data <= led_buf; --slv_reg0;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
| gpl-3.0 | 327524da1aa02a9c417c82a405c68af0 | 0.486696 | 4.340286 | false | false | false | false |
samrose3/trex-runner | BinHexDecoder.vhd | 1 | 901 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity BcdSegDecoder is
Port ( clk : in std_logic;
bcd : in std_logic_vector(3 downto 0);
segment7 : out std_logic_vector(6 downto 0));
end BcdSegDecoder;
architecture Behavioral of BcdSegDecoder is
begin
process (clk,bcd)
begin
if (clk'event and clk='1') then
case bcd is
when "0000"=> segment7 <="0000001"; -- '0'
when "0001"=> segment7 <="1001111"; -- '1'
when "0010"=> segment7 <="0010010"; -- '2'
when "0011"=> segment7 <="0000110"; -- '3'
when "0100"=> segment7 <="1001100"; -- '4'
when "0101"=> segment7 <="0100100"; -- '5'
when "0110"=> segment7 <="0100000"; -- '6'
when "0111"=> segment7 <="0001111"; -- '7'
when "1000"=> segment7 <="0000000"; -- '8'
when "1001"=> segment7 <="0000100"; -- '9'
when others=> segment7 <="1111111";
end case;
end if;
end process;
end Behavioral; | mit | 3893ef26e4b27d7b137e064ad09a40fe | 0.598224 | 3.043919 | false | false | false | false |
thequbit/af_paper | code/xilinx/color_space_converter.vhd | 1 | 2,076 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity color_space_converter is
Port ( i_clk : in STD_LOGIC;
i_reset : in STD_LOGIC;
i_R : in STD_LOGIC_VECTOR (7 downto 0);
i_G : in STD_LOGIC_VECTOR (7 downto 0);
i_B : in STD_LOGIC_VECTOR (7 downto 0);
i_framevalid: in STD_LOGIC;
i_linevalid: in STD_LOGIC;
o_Y : out STD_LOGIC_VECTOR (7 downto 0);
o_framevalid : out STD_LOGIC;
o_linevalid : out STD_LOGIC
);
end color_space_converter;
architecture Behavioral of color_space_converter is
signal r_y : STD_LOGIC_VECTOR(8 downto 0);
signal r_r : STD_LOGIC_VECTOR(7 downto 0);
signal r_g : STD_LOGIC_VECTOR(7 downto 0);
signal r_b : STD_LOGIC_VECTOR(7 downto 0);
signal r_framevalid : STD_LOGIC;
signal r_framevalidout : STD_LOGIC;
signal r_linevalid : STD_LOGIC;
signal r_linevalidout : STD_LOGIC;
begin
o_Y <= r_y(7 downto 0) when r_y < "100000000" else X"FF";
o_framevalid <= r_framevalidout;
o_linevalid <= r_linevalidout;
process( i_clk )
begin
if ( rising_edge( i_clk ) ) then
if ( i_reset = '1' ) then
r_r <= (others => '0');
r_g <= (others => '0');
r_b <= (others => '0');
r_y <= (others => '0');
else
-- 1/4th + 1/8th = 3/8ths, or 37.5% of value
r_r <= ("00" & i_R(7 downto 2)) + ("000" & i_R(7 downto 3));
r_g <= ("00" & i_G(7 downto 2)) + ("000" & i_G(7 downto 3));
r_b <= ("00" & i_B(7 downto 2)) + ("000" & i_B(7 downto 3));
r_y <= ("0" & r_r) + ("0" & r_g) + ("0" & r_b);
end if;
end if;
end process;
process( i_clk )
begin
if ( rising_edge( i_clk ) ) then
if ( i_reset = '1' ) then
r_framevalid <= '0';
r_framevalidout <= '0';
r_linevalid <= '0';
r_linevalidout <= '0';
else
r_framevalid <= i_framevalid;
r_framevalidout <= r_framevalid;
r_linevalid <= i_linevalid;
r_linevalidout <= r_linevalid;
end if;
end if;
end process;
end Behavioral; | gpl-3.0 | 1fc4f66a0cc0f7f2ec2ac8315c1aff72 | 0.559249 | 2.731579 | false | false | false | false |
samrose3/trex-runner | counter.vhd | 1 | 1,735 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
entity Counter is
port(clk : in std_logic;
countup: in std_logic;
reset: in std_logic;
d0: out std_logic_vector(3 downto 0);
d10: out std_logic_vector(3 downto 0);
d100: out std_logic_vector(3 downto 0));
--d1000: out std_logic_vector(3 downto 0));
end Counter;
architecture Behavioral of Counter is
signal t0: integer := 0;
signal t10: integer := 0;
signal t100: integer := 0;
--signal t1000: integer := 0;
begin
process(clk)
variable prescalerCount: integer := 0;
variable prescaler: integer := 25000000;
begin
if (reset = '1') then
t0 <= 0;
t10 <= 0;
t100 <= 0;
--t1000 <= 0;
elsif(clk = '1' and clk'event) then
if prescalerCount >= prescaler then
if countup='1' then
if t100 >= 9 then
t0 <= 0;
t10 <= 0;
t100 <= 0;
--t1000 <= 0;
else
t0 <= t0 + 1;
if t0 >= 9 then
t10 <= t10 + 1;
t0 <= 0;
if t10 >= 9 then
t100 <= t100 + 1;
t10 <= 0;
--if t100 >= 9 then
-- t1000 <= t1000 + 1;
-- t100 <= 0;
--end if;
end if;
end if;
end if;
end if;
prescalerCount := 0;
end if;
prescalerCount := prescalerCount + 1;
end if;
end process;
d0 <= std_logic_vector(to_unsigned(t0, d0'length));
d10 <= std_logic_vector(to_unsigned(t10, d10'length));
d100 <= std_logic_vector(to_unsigned(t100, d100'length));
--d1000 <= std_logic_vector(to_unsigned(t1000, d1000'length));
end Behavioral; | mit | 745990f04ecf86e327ab779a5afd7b4a | 0.543516 | 2.991379 | false | false | false | false |
samrose3/trex-runner | DeBounce.vhd | 1 | 703 | -- Pushbutton Debounce Module
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.all;
USE ieee.STD_LOGIC_UNSIGNED.all;
ENTITY Debo IS
PORT (
clk: IN STD_LOGIC; ---make it a low frequency Clock input
key: IN STD_LOGIC; -- active low input
pulse: OUT STD_LOGIC);
END Debo;
ARCHITECTURE onepulse OF Debo IS
SIGNAL cnt: STD_LOGIC_VECTOR (1 DOWNTO 0);
BEGIN
PROCESS (clk,key)
BEGIN
IF (key = '1') THEN
cnt <= "00";
ELSIF (clk'EVENT AND clk= '1') THEN
IF (cnt /= "11") THEN cnt <= cnt + 1; END IF;
END IF;
IF (cnt = "10") AND (key = '0') THEN
pulse <= '1';
ELSE pulse <= '0';
END IF;
END PROCESS; --You must BEGIN and END a PROCESS in VHDL.
END onepulse;
| mit | cef54c6e621c97fe5479fde3016d6e51 | 0.614509 | 3.152466 | false | false | false | false |
JeremySavonet/Eurobot-2017-Moon-Village | software/HPS_FPGA_LED/fpga/robot_layer_1.vhd | 1 | 43,415 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.uart_pkg.all;
use work.spi_master_pkg.all;
use work.qei_pkg.all;
use work.pwm_pkg.all;
use work.debounce_pkg.all;
use work.types_pkg.all;
use work.robot_layer_1_pkg.all;
entity robot_layer_1 is
generic (
CLK_FREQUENCY_HZ : positive;
RegCnt : positive
);
port (
clk : in std_logic;
reset : in std_logic;
regs_data_in_value : out std_logic_vector(RegCnt*32-1 downto 0) := (others => '0');
regs_data_in_read : in std_logic_vector(RegCnt-1 downto 0);
regs_data_out_value : in std_logic_vector(RegCnt*32-1 downto 0);
regs_data_out_write : in std_logic_vector(RegCnt-1 downto 0);
----------- ADC (//) ---------
ad0_sclk : out std_logic;
ad0_miso : in std_logic;
ad0_drdy : in std_logic;
ad0_sync : out std_logic;
ad0_clk : out std_logic;
--------- ADC (muxed) --------
ad1_sclk : out std_logic;
ad1_mosi : out std_logic;
ad1_miso : in std_logic;
ad1_ss : out std_logic;
ad1_drdy : in std_logic;
ad1_rst : out std_logic;
---------- H BRIDGE ----------
m0_pwma : out std_logic;
m0_pwmb : out std_logic;
m01_fault: in std_logic; --m01_fault
m1_pwma : out std_logic;
m1_pwmb : out std_logic;
m01_resetn: out std_logic; --m01_resetn
m2_pwma : out std_logic;
m2_pwmb : out std_logic;
m3_pwma : out std_logic;
m3_pwmb : out std_logic;
m2345_fault: in std_logic; --m2345_fault
m4_pwma : out std_logic;
m4_pwmb : out std_logic;
m5_pwma : out std_logic;
m5_pwmb : out std_logic;
m2345_resetn: out std_logic; --m2345_resetn
---------- QEI ----------
qei0_a : in std_logic;
qei0_b : in std_logic;
qei1_a : in std_logic;
qei1_b : in std_logic;
qei2_a : in std_logic;
qei2_b : in std_logic;
qei2_z : in std_logic;
qei3_a : in std_logic;
qei3_b : in std_logic;
qei3_z : in std_logic;
---------- ESC ----------
esc0_pwm : out std_logic;
esc0_dir : out std_logic;
esc1_pwm : out std_logic;
esc1_dir : out std_logic;
------- PWM (Servos) ------
s : out std_logic_vector(8-1 downto 0);
--------- IOs ----------
io_0 : inout std_logic;
io_1 : inout std_logic;
io_2 : inout std_logic;
io_3 : inout std_logic;
io_4 : inout std_logic;
io_5 : inout std_logic;
io_6 : inout std_logic;
io_7 : inout std_logic;
--------- UART ----------
uart0_rx : in std_logic;
uart0_tx : out std_logic;
uart1_rx : in std_logic;
uart1_tx : out std_logic;
uart2_rx : in std_logic;
uart2_tx : out std_logic;
uart2_custom : out std_logic;
uart3_rx : in std_logic;
uart3_tx : out std_logic;
uart3_custom : out std_logic;
--------- I2C ----------
i2c0_scl : inout std_logic;
i2c0_sda : inout std_logic;
i2c0_reset : out std_logic;
i2c1_scl : inout std_logic;
i2c1_sda : inout std_logic;
i2c1_reset : out std_logic;
--------- SPI ----------
spi0_sclk : in std_logic;
spi0_mosi : in std_logic;
spi0_miso : in std_logic;
spi0_ss : in std_logic;
spi1_sclk : out std_logic;
spi1_mosi : out std_logic;
spi1_miso : in std_logic;
spi1_ss : out std_logic;
--! Use SPI1
imu_ss : out std_logic;
imu_drdy : in std_logic;
imu_fsync : in std_logic;
---------- LED -----------
led_green : out std_logic;
led_red : out std_logic;
--------- MGMT -----------
lv_mux : out std_logic_vector(2-1 downto 0);
buzzer : out std_logic;
----------/ NANO SOC LED --------/
LED : out std_logic_vector(8-1 downto 0);
----------/ NANO SOC SW --------/
SW : in std_logic_vector(4-1 downto 0);
---------------------------------
-------- TO/FROM LAYER 2 --------
---------------------------------
--------- UART ----------
uart_tx : in std_logic_vector(4-1 downto 0);
uart_rx : out std_logic_vector(4-1 downto 0);
motor_value : in int16_t(MOTOR_COUNT-1 downto 0);
motor_current : out int24_t(MOTOR_COUNT-1 downto 0);
motor_fault : out std_logic_vector(MOTOR_COUNT-1 downto 0);
qei_value : out int16_t(QEI_COUNT-1 downto 0);
qei_ref : out std_logic_vector(QEI_COUNT-1 downto 0)
);
end entity;
architecture rtl of robot_layer_1 is
component system_ll is
port (
clk_clk : in std_logic := 'X'; -- clk
i2c_master_serial_0_sda_in : in std_logic := 'X'; -- sda_in
i2c_master_serial_0_scl_in : in std_logic := 'X'; -- scl_in
i2c_master_serial_0_sda_oe : out std_logic; -- sda_oe
i2c_master_serial_0_scl_oe : out std_logic; -- scl_oe
i2c_master_serial_1_sda_in : in std_logic := 'X'; -- sda_in
i2c_master_serial_1_scl_in : in std_logic := 'X'; -- scl_in
i2c_master_serial_1_sda_oe : out std_logic; -- sda_oe
i2c_master_serial_1_scl_oe : out std_logic; -- scl_oe
pio_data_in_value : in std_logic_vector(511 downto 0) := (others => 'X'); -- data_in_value
pio_data_in_read : out std_logic_vector(15 downto 0); -- data_in_read
pio_data_out_value : out std_logic_vector(511 downto 0); -- data_out_value
pio_data_out_write : out std_logic_vector(15 downto 0); -- data_out_write
reset_reset_n : in std_logic := 'X'; -- reset_n
uart_0_external_rxd : in std_logic := 'X'; -- rxd
uart_0_external_txd : out std_logic
);
end component system_ll;
signal w_reset_n : std_logic;
signal w_regs_data_in_value : std_logic_vector(RegCnt*32-1 downto 0);
signal w_regs_data_in_value_mask : std_logic_vector(RegCnt*4-1 downto 0) := (others=>'0');
constant REG_MOTOR_OFFSET : natural := 12;
constant REG_MOTOR_CURRENT_OFFSET : natural := REG_MOTOR_OFFSET+MOTOR_COUNT;
signal w_motor_value : int16_t(MOTOR_COUNT-1 downto 0);
signal w_motor_invert : std_logic_vector(MOTOR_COUNT-1 downto 0);
signal w_motor_override : std_logic_vector(MOTOR_COUNT-1 downto 0);
signal w_motor_current : int24_t(MOTOR_COUNT-1 downto 0);
signal w_motor_out : std_logic_vector(MOTOR_COUNT-1 downto 0);
signal w_motor_dir : std_logic_vector(MOTOR_COUNT-1 downto 0);
constant REG_SERVO_OFFSET : natural := 30;
constant SERVO_COUNT : natural := 8;
signal w_servo_value : int16_t(SERVO_COUNT-1 downto 0);
signal w_servo_enabled : std_logic_vector(SERVO_COUNT-1 downto 0);
signal w_servo_full_range : std_logic_vector(SERVO_COUNT-1 downto 0);
signal w_servo_override : std_logic_vector(SERVO_COUNT-1 downto 0);
signal w_servo_current : int24_t(SERVO_COUNT-1 downto 0);
signal w_servo_out : std_logic_vector(SERVO_COUNT-1 downto 0);
constant REG_ESC_OFFSET : natural := 46;
constant ESC_COUNT : natural := 2;
signal w_esc_value : int16_t(ESC_COUNT-1 downto 0);
signal w_esc_enabled : std_logic_vector(ESC_COUNT-1 downto 0);
signal w_esc_override : std_logic_vector(ESC_COUNT-1 downto 0);
signal w_esc_current : int24_t(ESC_COUNT-1 downto 0);
signal w_esc_out : std_logic_vector(ESC_COUNT-1 downto 0);
signal w_esc_dir : std_logic_vector(ESC_COUNT-1 downto 0);
constant REG_QEI_OFFSET : natural := 24;
signal w_qei_a : std_logic_vector(QEI_COUNT-1 downto 0);
signal w_qei_b : std_logic_vector(QEI_COUNT-1 downto 0);
signal w_qei_z : std_logic_vector(QEI_COUNT-1 downto 0);
signal w_qei_override : std_logic_vector(QEI_COUNT-1 downto 0);
signal w_qei_value : int16_t(QEI_COUNT-1 downto 0);
signal w_qei_ref : std_logic_vector(QEI_COUNT-1 downto 0);
signal r_led_red : std_logic;
signal w_ad0_rx_data : std_logic_vector(192-1 downto 0);
constant VOLTAGE_COUNT : natural := 4;
constant REG_VOLTAGE_OFFSET : natural := 2;
signal r_voltage : int24_t(VOLTAGE_COUNT-1 downto 0);
signal r_lv_mux : std_logic_vector(2-1 downto 0);
signal r_voltage_cnt : std_logic_vector(7-1 downto 0);
constant REG_BUZZER_OFFSET : natural := 6;
signal r_buzzer : std_logic;
signal w_buzzer_override : std_logic;
signal w_buzzer_out : std_logic;
constant REG_IO_OFFSET : natural := 7;
constant IO_COUNT : natural := 4;
signal w_input_in : std_logic_vector(IO_COUNT-1 downto 0);
signal w_input_override: std_logic_vector(IO_COUNT-1 downto 0);
signal w_input_value : std_logic_vector(IO_COUNT-1 downto 0);
signal w_output_value : std_logic_vector(IO_COUNT-1 downto 0);
signal w_output_override: std_logic_vector(IO_COUNT-1 downto 0);
signal w_output_out : std_logic_vector(IO_COUNT-1 downto 0);
constant REG_STATE_CONFIG_OFFSET : natural := 1;
signal w_sim_mode : std_logic;
signal w_i2c_0_scl : std_logic;
signal w_i2c_0_sda : std_logic;
signal w_i2c_0_scl_oe : std_logic;
signal w_i2c_0_sda_oe : std_logic;
signal w_i2c_0_reset : std_logic;
signal w_i2c_1_scl : std_logic;
signal w_i2c_1_sda : std_logic;
signal w_i2c_1_scl_oe : std_logic;
signal w_i2c_1_sda_oe : std_logic;
signal w_i2c_1_reset : std_logic;
begin
w_reset_n <= not reset;
imu_ss <= '1';
--! we return for read the same written data, expect for some bytes (noted masked) where we compute the value internally
g_reg: for i in 0 to w_regs_data_in_value_mask'length-1 generate
regs_data_in_value((i+1)*8-1 downto i*8) <= regs_data_out_value((i+1)*8-1 downto i*8) when w_regs_data_in_value_mask(i) = '0' else w_regs_data_in_value((i+1)*8-1 downto i*8);
end generate;
b_ads1278: block
signal r_clk_25mhz : std_logic;
signal r_clk_12mhz : std_logic;
signal r_ad_drdy : std_logic;
signal r_ad_en : std_logic;
signal w_ad_rx_busy : std_logic;
signal r_ad_rx_busy : std_logic;
signal w_ad_rx_data : std_logic_vector(192-1 downto 0);
signal r_ad_rx_valid : std_logic;
begin
p_sync_spi: process(clk) is
begin
if rising_edge(clk) then
r_clk_25mhz <= not r_clk_25mhz;
r_ad_drdy <= ad0_drdy;
if r_clk_25mhz = '1' then
r_clk_12mhz <= not r_clk_12mhz;
end if;
r_ad_en <= '0';
if ad0_drdy = '0' and r_ad_drdy = '1' then
r_ad_en <= '1';
end if;
end if;
end process;
ad0_clk <= r_clk_12mhz;
ad0_sync <= '1';
inst_spi_ad: spi_master
generic map(
slaves => 1,
d_width => w_ad_rx_data'length
)
port map (
clock => clk,
reset_n => w_reset_n,
enable => r_ad_en,
cpol => '0',
cpha => '0',
cont => '0',
clk_div => 2,
addr => 0,
tx_data => (others=>'0'),
miso => ad0_miso,
sclk => ad0_sclk,
ss_n => open,
mosi => open,
ss_n => open,
busy => w_ad_rx_busy,
rx_data => w_ad_rx_data
);
p_sync_ad_output: process(clk,reset) is
begin
if reset = '1' then
r_ad_rx_valid <= '0';
r_ad_rx_busy <= '0';
elsif rising_edge(clk) then
r_ad_rx_busy <= w_ad_rx_busy;
r_ad_rx_valid<= '0';
if w_ad_rx_busy = '0' and r_ad_rx_busy = '1' then
r_ad_rx_valid <= '1';
end if;
end if;
end process;
p_sync_voltage_mux: process(clk,reset) is
begin
if reset = '1' then
r_voltage_cnt <= (others=>'0');
r_lv_mux <= (others=>'0');
r_buzzer <= '0';
elsif rising_edge(clk) then
if r_ad_rx_valid = '1' then
r_voltage_cnt <= std_logic_vector(unsigned(r_voltage_cnt)+1);
if r_voltage_cnt = (r_voltage_cnt'range=>'1') then
r_lv_mux <= std_logic_vector(unsigned(r_lv_mux)+1);
r_voltage(to_integer(unsigned(r_lv_mux))) <= w_ad_rx_data(8*24-1 downto 7*24);
end if;
end if;
r_buzzer <= '0';
for i in 0 to VOLTAGE_COUNT-1 loop
if unsigned(w_regs_data_in_value(((i+1)+REG_VOLTAGE_OFFSET)*32-1 downto (i+REG_VOLTAGE_OFFSET)*32)) < unsigned(regs_data_out_value(((i+1)+REG_VOLTAGE_OFFSET)*32-1 downto (i+REG_VOLTAGE_OFFSET)*32)) then
r_buzzer <= '1';
end if;
end loop;
end if;
end process;
b_buzzer: block
signal w_reg : std_logic_vector(32-1 downto 0);
begin
w_reg <= regs_data_out_value((REG_BUZZER_OFFSET+1)*32-1 downto REG_BUZZER_OFFSET*32);
w_buzzer_override <= w_reg(8);
w_buzzer_out <= r_buzzer when w_buzzer_override = '0' else w_reg(0);
w_regs_data_in_value((REG_BUZZER_OFFSET+1)*32-1 downto REG_BUZZER_OFFSET*32) <= X"0000" & X"00" & "0000000" & w_buzzer_out;
w_regs_data_in_value_mask((REG_BUZZER_OFFSET+1)*4-1 downto REG_BUZZER_OFFSET*4) <= "0001";
g_voltage_mux: for i in 0 to VOLTAGE_COUNT-1 generate
begin
w_regs_data_in_value(((i+1)+REG_VOLTAGE_OFFSET)*32-1 downto (i+REG_VOLTAGE_OFFSET)*32) <= (8-1 downto 0=>r_voltage(i)(r_voltage(i)'high)) & r_voltage(i);
w_regs_data_in_value_mask(((i+1)+REG_VOLTAGE_OFFSET)*4-1 downto (i+REG_VOLTAGE_OFFSET)*4) <= (others=>'1');
end generate;
end block;
buzzer <= w_buzzer_out;
w_ad0_rx_data <= w_ad_rx_data;
end block;
-- spi_master_0_MISO => ad1_miso, -- spi_master_0.MISO
-- spi_master_0_MOSI => ad1_mosi, -- .MOSI
-- spi_master_0_SCLK => ad1_sclk , -- .SCLK
-- spi_master_0_SS_n => ad1_ss --
-- ad1_sclk : out std_logic;
-- ad1_mosi : out std_logic;
-- ad1_miso : in std_logic;
-- ad1_ss : out std_logic;
-- ad1_drdy : in std_logic;
-- ad1_rst : out std_logic;
b_ads1258: block
signal r_ad_drdy : std_logic;
signal r_ad_en : std_logic;
signal w_ad_rx_busy : std_logic;
signal r_ad_rx_busy : std_logic;
signal r_ad_tx_data : std_logic_vector(8*4-1 downto 0);
signal w_ad_rx_data : std_logic_vector(8*4-1 downto 0);
signal r_ad_rx_valid : std_logic;
constant ADC_COUNT : natural := 8;
signal r_adc_values : int24_t(ADC_COUNT-1 downto 0);
constant REGS_ADC_SERVO_OFFSET : natural := 38;
signal r_state : std_logic_vector(2-1 downto 0);
signal r_cnt : natural;
begin
--uint8_t spi_buf1[2] = {0x60, 0x18};
--uint8_t spi_buf2[2] = {0x61, 0x70};
p_sync_spi: process(clk,reset) is
begin
if (reset = '1') then
ad1_rst <= '0';
r_ad_drdy <= '0';
r_ad_en <= '0';
r_ad_tx_data <= (others=>'0');
r_state <= "00";
r_cnt <= 0;
elsif rising_edge(clk) then
r_ad_en <= '0';
case r_state is
when "00" =>
ad1_rst <= '1';
r_state <= "01";
when "01" =>
r_cnt <= r_cnt + 1;
if w_ad_rx_busy = '0' and r_cnt = 250000000 then
r_ad_tx_data <= X"60" & X"1A" & X"60" & X"1A";
r_ad_en <= '1';
r_state <= "10";
end if;
when "10" =>
if r_ad_rx_valid = '1' then
r_ad_tx_data <= X"61" & X"70" & X"61" & X"70";
r_ad_en <= '1';
r_state <= "11";
end if;
when "11" =>
r_ad_drdy <= ad1_drdy;
if ad1_drdy = '0' and r_ad_drdy = '1' and w_ad_rx_busy = '0' then
r_ad_tx_data <= (others=>'0');
r_ad_en <= '1';
end if;
end case;
end if;
end process;
inst_spi_ad: spi_master
generic map(
slaves => 1,
d_width => w_ad_rx_data'length
)
port map (
clock => clk,
reset_n => w_reset_n,
enable => r_ad_en,
cpol => '0',
cpha => '0',
cont => '0',
clk_div => 8,
addr => 0,
tx_data => r_ad_tx_data,
miso => ad1_miso,
mosi => ad1_mosi,
sclk => ad1_sclk,
ss_n(0) => ad1_ss,
busy => w_ad_rx_busy,
rx_data => w_ad_rx_data
);
--spi1_ss <= '0';
--ad1_ss <= '0';
p_sync_ad_output: process(clk,reset) is
begin
if reset = '1' then
r_ad_rx_valid <= '0';
r_ad_rx_busy <= '0';
elsif rising_edge(clk) then
r_ad_rx_busy <= w_ad_rx_busy;
r_ad_rx_valid<= '0';
if w_ad_rx_busy = '0' and r_ad_rx_busy = '1' then
r_ad_rx_valid <= '1';
end if;
end if;
end process;
p_ad_read: process(clk,reset) is
begin
if reset = '1' then
r_adc_values <= (others=>(others=>'0'));
elsif rising_edge(clk) then
if r_ad_rx_valid = '1' then
if unsigned(w_ad_rx_data(32-3-1 downto 32-8)) >= 16 and unsigned(w_ad_rx_data(32-3-1 downto 32-8)) <= 23 then
r_adc_values(to_integer(unsigned(w_ad_rx_data(32-3-1 downto 32-8)))-16) <= w_ad_rx_data(3*8-1 downto 0);
end if;
end if;
end if;
end process;
b_adc_regs: block
begin
g_mux: for i in 0 to ADC_COUNT-1 generate
begin
w_regs_data_in_value(((i+1)+REGS_ADC_SERVO_OFFSET)*32-1 downto (i+REGS_ADC_SERVO_OFFSET)*32) <= (8-1 downto 0=>r_adc_values(i)(r_adc_values(i)'high)) & r_adc_values(i);
w_regs_data_in_value_mask(((i+1)+REGS_ADC_SERVO_OFFSET)*4-1 downto (i+REGS_ADC_SERVO_OFFSET)*4) <= (others=>'1');
end generate;
end block;
end block;
w_input_in(0) <= io_0 when w_sim_mode = '0' else SW(0);
w_input_in(1) <= io_2 when w_sim_mode = '0' else SW(1);
w_input_in(2) <= io_3 when w_sim_mode = '0' else SW(2);
w_input_in(3) <= io_4 when w_sim_mode = '0' else SW(3);
io_0 <= 'Z';
io_2 <= 'Z';
io_3 <= 'Z';
io_4 <= 'Z';
b_io: block
signal w_input_in_filtered : std_logic_vector(IO_COUNT-1 downto 0);
signal w_input_value_reg : std_logic_vector(32-1 downto 0);
signal w_input_override_reg : std_logic_vector(32-1 downto 0);
signal w_output_value_reg : std_logic_vector(32-1 downto 0);
signal w_output_override_reg : std_logic_vector(32-1 downto 0);
begin
w_input_value_reg <= regs_data_out_value(((0+1)+REG_IO_OFFSET)*32-1 downto (0+REG_IO_OFFSET)*32);
w_input_override_reg <= regs_data_out_value(((1+1)+REG_IO_OFFSET)*32-1 downto (1+REG_IO_OFFSET)*32);
w_output_value_reg <= regs_data_out_value(((2+1)+REG_IO_OFFSET)*32-1 downto (2+REG_IO_OFFSET)*32);
w_output_override_reg <= regs_data_out_value(((3+1)+REG_IO_OFFSET)*32-1 downto (3+REG_IO_OFFSET)*32);
w_regs_data_in_value_mask(((0+1)+REG_IO_OFFSET)*4-1 downto (0+REG_IO_OFFSET)*4) <= (others=>'1');
w_regs_data_in_value_mask(((2+1)+REG_IO_OFFSET)*4-1 downto (2+REG_IO_OFFSET)*4) <= (others=>'1');
g_io: for i in 0 to IO_COUNT-1 generate
begin
inst_in_filter: debounce
generic map(
counter_size => 19 --counter size (19 bits gives 10.5ms with 50MHz clock)
)
port map(
clk => clk,
button => w_input_in(i),
result => w_input_in_filtered(i)
);
w_input_override(i) <= w_input_override_reg(i*8);
w_input_value(i) <= w_input_in_filtered(i) when w_input_override(i) = '0' else w_input_value_reg(i*8);
--! to be completed by Layer 2 signals
w_output_value(i) <= '0';
w_output_override(i) <= w_output_override_reg(i*8);
w_output_out(i) <= w_output_value(i) when w_output_override(i) = '0' else w_output_value_reg(i*8);
w_regs_data_in_value((0+REG_IO_OFFSET)*32+(i+1)*8-1 downto (0+REG_IO_OFFSET)*32+i*8) <= "0000000" & w_input_value(i);
w_regs_data_in_value((2+REG_IO_OFFSET)*32+(i+1)*8-1 downto (2+REG_IO_OFFSET)*32+i*8) <= "0000000" & w_output_value(i);
end generate;
end block;
io_1 <= w_output_out(0);
io_6 <= w_output_out(1);
io_7 <= w_output_out(2);
--io_? <= w_output_out(3);
b_state_config: block
signal w_reg : std_logic_vector(32-1 downto 0);
begin
w_reg <= regs_data_out_value(((0+1)+REG_STATE_CONFIG_OFFSET)*32-1 downto (0+REG_STATE_CONFIG_OFFSET)*32);
w_sim_mode <= w_reg(8);
end block;
w_motor_current(0) <= w_ad0_rx_data(1*24-1 downto 0*24);
w_motor_current(1) <= w_ad0_rx_data(2*24-1 downto 1*24);
w_motor_current(2) <= w_ad0_rx_data(3*24-1 downto 2*24);
w_motor_current(3) <= w_ad0_rx_data(4*24-1 downto 3*24);
w_motor_current(4) <= w_ad0_rx_data(5*24-1 downto 4*24);
w_motor_current(5) <= w_ad0_rx_data(6*24-1 downto 5*24);
motor_current <= w_motor_current;
motor_fault(0) <= m01_fault;
motor_fault(1) <= m01_fault;
motor_fault(2) <= m2345_fault;
motor_fault(3) <= m2345_fault;
motor_fault(4) <= m2345_fault;
motor_fault(5) <= m2345_fault;
w_regs_data_in_value(((0+1)+REG_MOTOR_OFFSET-1)*32-1 downto (0+REG_MOTOR_OFFSET-1)*32) <= X"0000" & "0000000" & m2345_fault & "0000000" & m01_fault;
w_regs_data_in_value_mask(((0+1)+REG_MOTOR_OFFSET-1)*4-1 downto (0+REG_MOTOR_OFFSET-1)*4) <= (others=>'1');
g_motor: for i in 0 to MOTOR_COUNT-1 generate
signal w_duty : std_logic_vector(15-1 downto 0);
signal w_reg : std_logic_vector(32-1 downto 0);
begin
w_regs_data_in_value(((i+1)+REG_MOTOR_CURRENT_OFFSET)*32-1 downto (i+REG_MOTOR_CURRENT_OFFSET)*32) <= (8-1 downto 0=>w_motor_current(i)(w_motor_current(i)'high)) & w_motor_current(i);
w_regs_data_in_value_mask(((i+1)+REG_MOTOR_CURRENT_OFFSET)*4-1 downto (i+REG_MOTOR_CURRENT_OFFSET)*4) <= (others=>'1');
w_reg <= regs_data_out_value(((i+1)+REG_MOTOR_OFFSET)*32-1 downto (i+REG_MOTOR_OFFSET)*32);
w_motor_invert(i) <= w_reg(16);
w_motor_override(i) <= w_reg(24);
w_motor_value(i) <= w_reg(16-1 downto 0) when w_motor_override(i) = '1' else motor_value(i);
w_duty <= std_logic_vector(abs(signed(w_motor_value(i))))(w_duty'range);
inst_pwm_motor: pwm
generic map(
sys_clk => CLK_FREQUENCY_HZ, --system clock frequency in Hz
pwm_freq => 20_000, --PWM switching frequency in Hz
bits_resolution => w_duty'length, --bits of resolution setting the duty cycle
phases => 1 --number of out : pwms and phases
)
port map (
clk => clk,
reset_n => w_reset_n,
ena => '1',
duty => w_duty,
pwm_out(0)=> w_motor_out(i)
);
w_motor_dir(i) <= w_motor_value(i)(w_motor_value(i)'high) when w_motor_invert(i) = '0' else not w_motor_value(i)(w_motor_value(i)'high);
end generate;
LED(0) <= w_motor_out(0) when w_motor_dir(0) = '0' else not w_motor_out(0);
LED(1) <= w_motor_out(1) when w_motor_dir(1) = '0' else not w_motor_out(1);
LED(2) <= w_motor_out(2) when w_motor_dir(2) = '0' else not w_motor_out(2);
LED(3) <= w_motor_out(3) when w_motor_dir(3) = '0' else not w_motor_out(3);
LED(4) <= w_output_out(0);
LED(5) <= w_output_out(1);
LED(6) <= w_output_out(2);
LED(7) <= w_output_out(3);
m0_pwma <= w_motor_out(0) and not w_motor_dir(0);
m0_pwmb <= w_motor_out(0) and w_motor_dir(0);
m1_pwma <= w_motor_out(1) and not w_motor_dir(1);
m1_pwmb <= w_motor_out(1) and w_motor_dir(1);
m2_pwma <= w_motor_out(2) and not w_motor_dir(2);
m2_pwmb <= w_motor_out(2) and w_motor_dir(2);
m3_pwma <= w_motor_out(3) and not w_motor_dir(3);
m3_pwmb <= w_motor_out(3) and w_motor_dir(3);
m4_pwma <= w_motor_out(4) and not w_motor_dir(4);
m4_pwmb <= w_motor_out(4) and w_motor_dir(4);
m5_pwma <= w_motor_out(5) and not w_motor_dir(5);
m5_pwmb <= w_motor_out(5) and w_motor_dir(5);
uart2_custom <= w_motor_out(5);
--uart3_custom <= w_motor_out(5);
b_blk_motor: block
signal w_reg : std_logic_vector(32-1 downto 0);
begin
w_reg <= regs_data_out_value(((0+1)+REG_MOTOR_OFFSET-1)*32-1 downto (0+REG_MOTOR_OFFSET-1)*32);
p_sync_reset: process(clk, w_reset_n) is
begin
if (w_reset_n = '0') then
m01_resetn <= '0';
m2345_resetn <= '0';
elsif rising_edge(clk) then
m01_resetn <= '1' and not w_reg(0);
m2345_resetn <= '1' and not w_reg(8);
end if;
end process;
end block;
g_servo: for i in 0 to SERVO_COUNT-1 generate
signal w_duty : std_logic_vector(16-1 downto 0);
signal w_reg : std_logic_vector(32-1 downto 0);
begin
w_reg <= regs_data_out_value(((i+1)+REG_SERVO_OFFSET)*32-1 downto (i+REG_SERVO_OFFSET)*32);
w_servo_enabled(i) <= w_reg(16);
w_servo_full_range(i) <= w_reg(17);
w_servo_override(i) <= w_reg(24);
w_servo_value(i) <= w_reg(16-1 downto 0) when w_servo_override(i) = '1' else (others=>'0');
w_duty <= std_logic_vector(to_unsigned(2**16/5,w_duty'length)+unsigned(w_servo_value(i))*52)(w_duty'range) when w_servo_enabled(i) = '1' and w_servo_full_range(i) = '0'
else w_servo_value(i) when w_servo_enabled(i) = '1' and w_servo_full_range(i) = '1'
else (others=>'0');
inst_pwm_servo: pwm
generic map(
sys_clk => CLK_FREQUENCY_HZ, --system clock frequency in Hz
pwm_freq => 200, --PWM switching frequency in Hz
bits_resolution => w_duty'length, --bits of resolution setting the duty cycle
phases => 1 --number of out : pwms and phases
)
port map (
clk => clk,
reset_n => w_reset_n,
ena => '1',
duty => w_duty,
pwm_out(0)=> w_servo_out(i)
);
end generate;
s <= w_servo_out;
g_esc: for i in 0 to ESC_COUNT-1 generate
signal w_duty : std_logic_vector(12-1 downto 0);
signal w_reg : std_logic_vector(32-1 downto 0);
begin
w_reg <= regs_data_out_value(((i+1)+REG_ESC_OFFSET)*32-1 downto (i+REG_ESC_OFFSET)*32);
w_esc_enabled(i) <= w_reg(16);
w_esc_override(i) <= w_reg(24);
w_esc_value(i) <= w_reg(16-1 downto 0) when w_esc_override(i) = '1' else (others=>'0');
w_duty <= std_logic_vector(to_unsigned(256,w_duty'length)+unsigned(abs(signed(w_esc_value(i)))))(w_duty'range) when w_esc_enabled(i) = '1' else (others=>'0');
inst_pwm_esc: pwm
generic map(
sys_clk => CLK_FREQUENCY_HZ*2, --system clock frequency in Hz
pwm_freq => 625*2/10, --PWM switching frequency in Hz
bits_resolution => w_duty'length, --bits of resolution setting the duty cycle
phases => 1 --number of out : pwms and phases
)
port map (
clk => clk,
reset_n => w_reset_n,
ena => '1',
duty => w_duty,
pwm_out(0)=> w_esc_out(i)
);
w_esc_dir(i) <= w_esc_value(i)(w_esc_value(i)'high);
end generate;
lv_mux <= r_lv_mux;
esc0_pwm <= w_esc_out(0);
esc1_pwm <= w_esc_out(1);
esc0_dir <= w_esc_dir(0);
esc1_dir <= w_esc_dir(1);
w_qei_a(0) <= qei0_a;
w_qei_b(0) <= qei0_b;
w_qei_z(0) <= '0';
w_qei_a(1) <= qei1_a;
w_qei_b(1) <= qei1_b;
w_qei_z(1) <= '0';
w_qei_a(2) <= qei2_a;
w_qei_b(2) <= qei2_b;
w_qei_z(2) <= qei2_z;
w_qei_a(3) <= qei3_a;
w_qei_b(3) <= qei3_b;
w_qei_z(3) <= qei3_z;
w_qei_a(4) <= spi0_sclk;
w_qei_b(4) <= spi0_ss;
w_qei_z(4) <= not spi0_mosi;
qei_value <= w_qei_value;
qei_ref <= w_qei_ref;
g_qei: for i in 0 to QEI_COUNT-1 generate
signal w_reg : std_logic_vector(32-1 downto 0);
signal w_cnt : std_logic_vector(16-1 downto 0);
signal r_qei_z : std_logic;
signal r2_qei_z : std_logic;
signal r_ref : std_logic;
signal r_qei_value_simu : std_logic_vector(16-1 downto 0);
function get_id_motor(qei_id : natural) return natural is
begin
if qei_id = 0 or qei_id = 2 then
return 0;
end if;
if qei_id = 1 or qei_id = 3 then
return 1;
end if;
return 2;
end function;
constant SIMU_ID_MOTOR : natural := get_id_motor(i);
constant SIMU_REF_COUNT : natural := 8192;
signal r_ref_cnt : integer range -(SIMU_REF_COUNT+1) to SIMU_REF_COUNT+1;
signal w_qei_z_local : std_logic;
signal r_qei_z_simu : std_logic;
begin
w_regs_data_in_value(((i+1)+REG_QEI_OFFSET)*32-1 downto (i+REG_QEI_OFFSET)*32) <= "0000000" & w_qei_override(i) & "0000000" & w_qei_ref(i) & w_qei_value(i);
w_regs_data_in_value_mask(((i+1)+REG_QEI_OFFSET)*4-1 downto (i+REG_QEI_OFFSET)*4) <= (others=>'1');
w_reg <= regs_data_out_value(((i+1)+REG_QEI_OFFSET)*32-1 downto (i+REG_QEI_OFFSET)*32);
w_qei_override(i) <= w_reg(24);
inst_qei: QuadratureCounterPorts
port map (
clock => clk,
QuadA => w_qei_a(i),
QuadB => w_qei_b(i),
CounterValue => w_cnt
);
p_async: process(w_sim_mode,r_qei_value_simu,w_cnt,w_qei_override,w_reg) is
begin
if w_sim_mode = '0' then
if w_qei_override(i) = '0' then
w_qei_value(i) <= w_cnt;
else
w_qei_value(i) <= w_reg(16-1 downto 0);
end if;
else
if w_qei_override(i) = '0' then
w_qei_value(i) <= r_qei_value_simu;
else
w_qei_value(i) <= w_reg(16-1 downto 0);
end if;
end if;
end process;
p_sync_simu: process(clk,reset) is
begin
if reset = '1' then
r_qei_value_simu <= (others=>'0');
r_ref_cnt <= 0;
elsif rising_edge(clk) then
if unsigned(abs(signed(w_motor_value(SIMU_ID_MOTOR)))) >= 10000 then
if w_motor_dir(SIMU_ID_MOTOR) = '0' then
r_qei_value_simu <= std_logic_vector(unsigned(r_qei_value_simu)+1);
r_ref_cnt <= r_ref_cnt+1;
else
r_qei_value_simu <= std_logic_vector(unsigned(r_qei_value_simu)-1);
r_ref_cnt <= r_ref_cnt-1;
end if;
end if;
r_qei_z_simu <= '0';
if r_ref_cnt = SIMU_REF_COUNT or r_ref_cnt = -SIMU_REF_COUNT then
r_ref_cnt <= 0;
r_qei_z_simu <= '1';
end if;
if w_sim_mode = '0' then
r_qei_value_simu <= (others=>'0');
r_ref_cnt <= 0;
end if;
end if;
end process;
w_qei_z_local <= w_qei_z(i) when w_sim_mode = '0' else r_qei_z_simu;
p_sync: process(clk,reset) is
begin
if reset = '1' then
r_ref <= '0';
r_qei_z <= '0';
elsif rising_edge(clk) then
r_qei_z <= w_qei_z_local;
r2_qei_z <= r_qei_z;
r_ref <= '0';
if r_qei_z = '1' and r2_qei_z = '0' then
r_ref <= '1';
end if;
--if r_qei_z = '0' and r2_qei_z = '1' then
-- r_ref <= '0';
--end if;
end if;
end process;
w_qei_ref(i) <= r_ref when w_qei_override(i) = '0' else w_reg(16);
end generate;
uart0_tx <= uart_tx(0);
uart1_tx <= uart_tx(1);
uart2_tx <= uart_tx(2);
uart3_tx <= uart_tx(3);
uart_rx(0) <= uart_tx(0);--uart0_rx;
uart_rx(1) <= uart1_rx;
uart_rx(2) <= uart2_rx;
uart_rx(3) <= uart3_rx;
i2c0_scl <= 'Z' when w_i2c_0_scl_oe = '0' else '0';
i2c0_sda <= 'Z' when w_i2c_0_sda_oe = '0' else '0';
i2c0_reset <= '0';
i2c1_scl <= 'Z' when w_i2c_1_scl_oe = '0' else '0';
i2c1_sda <= 'Z' when w_i2c_1_sda_oe = '0' else '0';
b_orca_low_level: block
--uint8_t reset;
--uint8_t pgm_id;
--uint8_t arg[2];
--// ADC 1278 Muxed
--uint8_t adc_drdy; // in // 1
--uint8_t adc_reset; // out
--uint8_t adc_valid; //
--uint8_t adc_id;
--uint32_t adc_value; // 2
--// Color Sensor
--uint8_t color_valid; // 3
--uint8_t reserved2[3];
--uint16_t R; //4
--uint16_t G;
--uint16_t B; //5
--uint16_t C;
--// Distance sensors
--uint8_t dist_valid; // 6
--uint8_t dist_id;
--uint8_t reserved3[2];
--uint32_t dist_value; // 7
signal w_pio_data_in_value : std_logic_vector(511 downto 0) := (others=>'0');
signal w_pio_data_out_value : std_logic_vector(511 downto 0);
constant REGS_ADC_SERVO_OFFSET : natural := 38;
constant REGS_COLOR_VALID_OFFSET : natural := 50;
constant REGS_COLOR_RG_OFFSET : natural := 51;
constant REGS_COLOR_BC_OFFSET : natural := 52;
constant REGS_DISTANCE_OFFSET : natural := 53;
constant ORCA_REGS_ADC_CFG_OFFSET : natural := 1;
constant ORCA_REGS_ADC_VALUE_OFFSET : natural := 2;
constant ORCA_REGS_COLOR_CFG_OFFSET : natural := 3;
constant ORCA_REGS_COLOR_RG_OFFSET : natural := 4;
constant ORCA_REGS_COLOR_BC_OFFSET : natural := 5;
constant ORCA_REGS_DIST_CFG_OFFSET : natural := 6;
constant ORCA_REGS_DIST_VALUE_OFFSET : natural := 7;
signal w_adc_muxed_id : std_logic_vector(8-1 downto 0);
signal w_adc_muxed_valid : std_logic;
signal w_adc_muxed_data : std_logic_vector(32-1 downto 0);
signal r_adc_muxed_data : int32_t(8-1 downto 0);
signal w_dist_id : std_logic_vector(8-1 downto 0);
signal w_dist_valid : std_logic;
signal w_dist_data : std_logic_vector(32-1 downto 0);
signal r_distance : int32_t(8-1 downto 0);
begin
--w_regs_data_in_value_mask((1+8+REGS_ADC_SERVO_OFFSET)*4-1 downto (0+REGS_ADC_SERVO_OFFSET)*4) <= (others=>'1');
w_regs_data_in_value_mask((1+REGS_COLOR_VALID_OFFSET)*4-1 downto (0+REGS_COLOR_VALID_OFFSET)*4) <= "1111";
w_regs_data_in_value_mask((1+REGS_COLOR_RG_OFFSET)*4-1 downto (0+REGS_COLOR_RG_OFFSET)*4) <= "1111";
w_regs_data_in_value_mask((1+REGS_COLOR_BC_OFFSET)*4-1 downto (0+REGS_COLOR_BC_OFFSET)*4) <= "1111";
w_regs_data_in_value_mask((1+8+REGS_DISTANCE_OFFSET)*4-1 downto (0+REGS_DISTANCE_OFFSET)*4) <= (others=>'1');
p_async: process(regs_data_out_value,w_pio_data_out_value,r_distance) is
begin
w_pio_data_in_value(1*32-1 downto 0*32) <= X"00000000";
w_pio_data_in_value((1+ORCA_REGS_ADC_CFG_OFFSET)*32-1 downto (0+ORCA_REGS_ADC_CFG_OFFSET)*32) <= X"0000000" & "000" & regs_data_out_value(8);
w_pio_data_in_value((1+ORCA_REGS_ADC_VALUE_OFFSET)*32-1 downto (0+ORCA_REGS_ADC_VALUE_OFFSET)*32) <= X"0000000" & "000" & regs_data_out_value(8);
--w_pio_data_in_value((1+ORCA_REGS_ADC_CFG_OFFSET)*32-1 downto (0+ORCA_REGS_ADC_CFG_OFFSET)*32)(0) <= regs_data_out_value(8);
for i in 0 to r_distance'length-1 loop
w_regs_data_in_value((1+i+REGS_DISTANCE_OFFSET)*32-1 downto (0+i+REGS_DISTANCE_OFFSET)*32) <= r_distance(i);
end loop;
end process;
w_regs_data_in_value((1+REGS_COLOR_VALID_OFFSET)*32-1 downto (0+REGS_COLOR_VALID_OFFSET)*32) <= X"0000000" & "000" & std_norm_range(w_pio_data_out_value((1+ORCA_REGS_COLOR_CFG_OFFSET)*32-1 downto (0+ORCA_REGS_COLOR_CFG_OFFSET)*32))(0);
w_regs_data_in_value((1+REGS_COLOR_RG_OFFSET)*32-1 downto (0+REGS_COLOR_RG_OFFSET)*32) <= w_pio_data_out_value((1+ORCA_REGS_COLOR_RG_OFFSET)*32-1 downto (0+ORCA_REGS_COLOR_RG_OFFSET)*32);
w_regs_data_in_value((1+REGS_COLOR_BC_OFFSET)*32-1 downto (0+REGS_COLOR_BC_OFFSET)*32) <= w_pio_data_out_value((1+ORCA_REGS_COLOR_BC_OFFSET)*32-1 downto (0+ORCA_REGS_COLOR_BC_OFFSET)*32);
i2c1_reset <= std_norm_range(w_pio_data_out_value((1+ORCA_REGS_ADC_CFG_OFFSET)*32-1 downto (0+ORCA_REGS_ADC_CFG_OFFSET)*32))(8);
w_adc_muxed_id <= std_norm_range(w_pio_data_out_value((1+ORCA_REGS_ADC_CFG_OFFSET)*32-1 downto (0+ORCA_REGS_ADC_CFG_OFFSET)*32))(32-1 downto 24);
w_adc_muxed_valid <= std_norm_range(w_pio_data_out_value((1+ORCA_REGS_ADC_CFG_OFFSET)*32-1 downto (0+ORCA_REGS_ADC_CFG_OFFSET)*32))(16);
w_adc_muxed_data <= w_pio_data_out_value((1+ORCA_REGS_ADC_VALUE_OFFSET)*32-1 downto (0+ORCA_REGS_ADC_VALUE_OFFSET)*32);
w_dist_id <= std_norm_range(w_pio_data_out_value((1+ORCA_REGS_DIST_CFG_OFFSET)*32-1 downto (0+ORCA_REGS_DIST_CFG_OFFSET)*32))(16-1 downto 8);
w_dist_valid <= std_norm_range(w_pio_data_out_value((1+ORCA_REGS_DIST_CFG_OFFSET)*32-1 downto (0+ORCA_REGS_DIST_CFG_OFFSET)*32))(0);
w_dist_data <= w_pio_data_out_value((1+ORCA_REGS_DIST_VALUE_OFFSET)*32-1 downto (0+ORCA_REGS_DIST_VALUE_OFFSET)*32);
p_sync: process(clk,reset) is
begin
if reset = '1' then
r_adc_muxed_data <= (others=>(others=>'0'));
r_distance <= (others=>(others=>'0'));
elsif rising_edge(clk) then
if w_adc_muxed_valid = '1' then
for i in 0 to r_adc_muxed_data'length-1 loop
if i = unsigned(w_adc_muxed_id) then
r_adc_muxed_data(i) <= w_adc_muxed_data;
end if;
end loop;
end if;
if w_dist_valid = '1' then
for i in 0 to r_distance'length-1 loop
if i = unsigned(w_dist_id) then
r_distance(i) <= w_dist_data;
end if;
end loop;
end if;
end if;
end process;
inst_orca_low_level : component system_ll
port map (
clk_clk => clk, -- clk.clk
i2c_master_serial_0_sda_in => i2c0_sda, -- i2c_master_serial_0.sda_in
i2c_master_serial_0_scl_in => i2c0_scl, -- .scl_in
i2c_master_serial_0_sda_oe => w_i2c_0_sda_oe, -- .sda_oe
i2c_master_serial_0_scl_oe => w_i2c_0_scl_oe, -- .scl_oe
i2c_master_serial_1_sda_in => i2c1_sda, -- i2c_master_serial_1.sda_in
i2c_master_serial_1_scl_in => i2c1_scl, -- .scl_in
i2c_master_serial_1_sda_oe => w_i2c_1_sda_oe, -- .sda_oe
i2c_master_serial_1_scl_oe => w_i2c_1_scl_oe, -- .scl_oe
pio_data_in_value => w_pio_data_in_value, -- pio.data_in_value
pio_data_in_read => open, -- .data_in_read
pio_data_out_value => w_pio_data_out_value, -- .data_out_value
pio_data_out_write => open, -- .data_out_write
reset_reset_n => not reset -- reset.reset_n
--uart_0_external_rxd => CONNECTED_TO_uart_0_external_rxd, -- uart_0_external.rxd
--uart_0_external_txd => CONNECTED_TO_uart_0_external_txd, -- .txd
);
end block;
end architecture;
| gpl-3.0 | 223c76531d40868b4cc4f74acd652c3c | 0.491282 | 3.103066 | false | false | false | false |
zhlinh/vhdl_course | Assignment/IMG_LSB/UNHIDE_STR.vhd | 1 | 2,348 | --UNHIDE_STR entity
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE WORK.MYTYPE.ALL;
ENTITY UNHIDE_STR IS
PORT(CLK: IN STD_LOGIC;
RESET: IN STD_LOGIC;
ENABLE: IN STD_LOGIC;
R_IN: IN COLOR;
G_IN: IN COLOR;
B_IN: IN COLOR;
XX: IN COLOR;
YY: IN COLOR;
ZZ: IN INTEGER RANGE 0 TO 2;
STR_LEN: IN INTEGER RANGE 0 TO 8192;
CHAR_OUT: OUT CHARACTER);
END ENTITY UNHIDE_STR;
ARCHITECTURE ART1 OF UNHIDE_STR IS
SIGNAL INDEX: INTEGER RANGE 0 TO 65535;
SIGNAL LEN: INTEGER RANGE 0 TO 65535;
BEGIN
COMPUTE: PROCESS(XX,YY,STR_LEN)
BEGIN
INDEX<=256*XX+YY+1;
LEN<= 8 * STR_LEN;
END PROCESS;
CLOCK: PROCESS(CLK,RESET,ENABLE)
VARIABLE FIXED_REM: COLOR;
VARIABLE COLOR_REM: STD_LOGIC_VECTOR(7 DOWNTO 0);
--COUNT的范围是256*256
VARIABLE COUNT: INTEGER RANGE 0 TO 65536;
VARIABLE CHAR_I: INTEGER RANGE 0 TO 8;
--STR_I的范围65535/8
VARIABLE CHAR_REM: STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
IF(RESET='1' OR ENABLE='0') THEN
CHAR_OUT<=CHARACTER'VAL(0);
COUNT:=0;
CHAR_I:=0;
ELSIF(COUNT=65536) THEN
CHAR_OUT<=CHARACTER'VAL(0);
ELSIF(CLK'EVENT AND CLK='1') THEN
COUNT:=COUNT+1;
IF( (COUNT>=INDEX) AND (COUNT<INDEX+LEN)) THEN
-- 取出8 bit 数据
IF(ZZ=0) THEN
COLOR_REM := CONV_STD_LOGIC_VECTOR(R_IN, 8);
ELSIF(ZZ=1) THEN
COLOR_REM := CONV_STD_LOGIC_VECTOR(G_IN, 8);
ELSE
COLOR_REM := CONV_STD_LOGIC_VECTOR(B_IN, 8);
END IF;
-- 取出LSB位
CHAR_REM(CHAR_I):=COLOR_REM(0);
IF(CHAR_I=7) THEN
-- 将CHAR输出
CHAR_OUT<=CONV_TO_CHAR(CHAR_REM);
END IF;
IF(CHAR_I<=7) THEN
CHAR_I:=CHAR_I+1;
END IF;
IF(CHAR_I=8) THEN
CHAR_I:=0;
END IF;
ELSE
CHAR_OUT<=CHARACTER'VAL(0);
END IF;
END IF;
END PROCESS;
END ARCHITECTURE ART1;
| apache-2.0 | 4cc70b9ff955747b869e10140215882b | 0.500864 | 3.604361 | false | false | false | false |
jz0229/open-ephys-pcie | serdes-interface/firmware/TB_i2c.vhd | 2 | 7,595 | <<<<<<< HEAD
--Test bench for i2c interface
--by: Jie (Jack) Zhang MWL-MIT
=======
--------------------------------------------------------------------------------
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
<<<<<<< HEAD
=======
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
ENTITY TB_i2c IS
END TB_i2c;
ARCHITECTURE behavior OF TB_i2c IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT i2c_master
generic(
input_clk : INTEGER := 50_000_000; --input clock speed from user logic in Hz
bus_clk : INTEGER := 500_000); --speed the i2c bus (scl) will run at in Hz
port(
clk : IN std_logic;
reset : IN std_logic;
ena : IN std_logic;
devid : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --device id of target slave
addr : IN std_logic_vector(7 downto 0);
rw : IN std_logic;
data_wr : IN std_logic_vector(7 downto 0);
busy : OUT std_logic;
data_rd : OUT std_logic_vector(7 downto 0);
ack_error : BUFFER std_logic;
<<<<<<< HEAD
rd_from_remote : in std_logic;
=======
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
sda : INOUT std_logic;
scl : INOUT std_logic
);
END COMPONENT;
--slave device
component i2c_slave is
generic(
input_clk : INTEGER := 50_000_000; --input clock speed from user logic in Hz
<<<<<<< HEAD
bus_clk : INTEGER := 500_000; --speed the i2c bus (scl) will run at in Hz
ID : std_logic_vector(6 downto 0) := "1010101"); --Device specific ID
=======
bus_clk : INTEGER := 500_000); --speed the i2c bus (scl) will run at in Hz
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
port (
clk : IN STD_LOGIC; --system clock
reset : IN STD_LOGIC; --active high reset
sda : INOUT STD_LOGIC; --serial data i2c bus
scl : INOUT STD_LOGIC; --serial clock i2c bus
wr_enb : out std_logic; --0: write to slave 1: read from slave
rd_enb : out std_logic;
addrout : out std_logic_vector(7 downto 0);
regin : in std_logic_vector(7 downto 0); --register values to send through i2c
regout : out std_logic_vector(7 downto 0)
);
end component;
<<<<<<< HEAD
component i2c_master_init is
port(
clk : in std_logic; --same clock for the i2c interface
reset : in std_logic;
busy : in std_logic;
ack_error : in std_logic;
i2c_ena_o : out std_logic;
rw_o : out std_logic;
device_id_o : out std_logic_vector(6 downto 0);
addr_o : out std_logic_vector(7 downto 0);
value_o : out std_logic_vector(7 downto 0);
user_rw : in std_logic;
user_device_id : in std_logic_vector(6 downto 0);
user_addr : in std_logic_vector(7 downto 0);
user_value : in std_logic_vector(7 downto 0)
);
end component;
=======
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal ena : std_logic := '0';
signal devid : std_logic_vector(6 downto 0) := (others => '0');
signal addr : std_logic_vector(7 downto 0) := (others => '0');
signal rw : std_logic := '0';
signal data_wr : std_logic_vector(7 downto 0) := (others => '0');
signal wr_enb : std_logic; --0: write to slave 1: read from slave
signal rd_enb : std_logic;
signal addrout : std_logic_vector(7 downto 0);
signal regin : std_logic_vector(7 downto 0); --register values to send through i2c
signal regout : std_logic_vector(7 downto 0);
--BiDirs
signal sda : std_logic;
signal scl : std_logic;
--Outputs
signal busy : std_logic;
signal data_rd : std_logic_vector(7 downto 0);
signal ack_error : std_logic;
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut_i2c_master: i2c_master PORT MAP (
clk => clk,
reset => reset,
ena => ena,
devid => devid,
addr => addr,
rw => rw,
data_wr => data_wr,
busy => busy,
data_rd => data_rd,
ack_error => ack_error,
<<<<<<< HEAD
rd_from_remote => '0',
=======
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
sda => sda,
scl => scl
);
-- slave module
<<<<<<< HEAD
uut_i2c_slave_des : i2c_slave generic map (
ID => "1100000"
)port map (
clk => clk,
reset => reset, --active high reset
sda => sda, --serial data i2c bus
scl => scl, --serial clock i2c bus
wr_enb => wr_enb,
rd_enb => rd_enb,
addrout => open,
regin => "10111001",
regout => open
);
uut_i2c_slave_ser : i2c_slave generic map (
ID => "1011000"
)port map (
clk => clk,
reset => reset, --active high reset
sda => sda, --serial data i2c bus
scl => scl, --serial clock i2c bus
wr_enb => wr_enb,
rd_enb => rd_enb,
addrout => open,
regin => regin,
regout => open
);
uut_i2c_slave_remote : i2c_slave generic map (
ID => "1010000"
)port map (
=======
uut_i2c_slave : i2c_slave port map (
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
clk => clk,
reset => reset, --active high reset
sda => sda, --serial data i2c bus
scl => scl, --serial clock i2c bus
wr_enb => wr_enb,
rd_enb => rd_enb,
addrout => addrout,
<<<<<<< HEAD
regin => "10111001",
regout => regout
);
control_init : i2c_master_init port map(
clk => clk,
reset => reset,
busy => busy,
ack_error => ack_error,
i2c_ena_o => ena,
rw_o => rw,
device_id_o => devid,
addr_o => addr,
value_o => data_wr,
user_rw => '1',
user_device_id => "1010000",
user_addr => "00110110",
user_value => "01110100"
);
=======
regin => regin,
regout => regout
);
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
scl <= 'H';
sda <= 'H';
reset <= '1';
<<<<<<< HEAD
wait for 100 ns;
reset <= '0';
regin <= "10101100";
wait for clk_period*10;
wait for clk_period*100;
-- insert stimulus here
wait for 200 us;
scl <= '0';
wait for 200 us;
scl <= 'H';
=======
addr <= "11001011";
devid <= "1010101";
data_wr <= "01011100";
ena <= '0';
wait for 100 ns;
reset <= '0';
wait for clk_period*10;
ena <= '1';
wait for clk_period*100;
ena <= '0';
-- insert stimulus here
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
wait;
end process;
END;
| mit | 7966b61f6787bf291226f7ad46ca2fab | 0.526136 | 3.124229 | false | false | false | false |
jz0229/open-ephys-pcie | serdes-interface/firmware/TB_SPI_module.vhd | 2 | 2,783 | --------------------------------------------------------------------------------
--Test bench for the SPI_module
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TB_SPI_module IS
END TB_SPI_module;
ARCHITECTURE behavior OF TB_SPI_module IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SPI_module
PORT(
clk_spi : IN std_logic;
reset : IN std_logic;
spi_start : IN std_logic;
command_in : in std_logic_vector(15 downto 0);
miso_i : in std_logic;
cs_o : OUT std_logic;
sclk_o : OUT std_logic;
mosi_o : OUT std_logic;
data_lclk_o : out std_logic
);
END COMPONENT;
--Inputs
signal clk_spi : std_logic := '0';
signal reset : std_logic := '0';
signal spi_start : std_logic := '0';
signal command_in : std_logic_vector(15 downto 0);
signal miso_i : std_logic;
--Outputs
signal cs_o : std_logic;
signal sclk_o : std_logic;
signal mosi_o : std_logic;
signal data_lclk_o : std_logic;
-- Clock period definitions
constant clk_spi_period : time := 10 ns;
constant spi_start_period : time := 1 us;
BEGIN
-- output SPI module
uut_output: SPI_module PORT MAP (
clk_spi => clk_spi,
reset => reset,
spi_start => spi_start,
command_in => command_in,
miso_i => miso_i,
cs_o => cs_o,
sclk_o => sclk_o,
mosi_o => mosi_o,
data_lclk_o => data_lclk_o
);
-- Instantiate the Unit Under Test (UUT)
uut_input: SPI_module PORT MAP (
clk_spi => clk_spi,
reset => reset,
spi_start => spi_start,
command_in => command_in,
miso_i => mosi_o,
cs_o => open,
sclk_o => open,
mosi_o => open,
data_lclk_o => open
);
-- Clock process definitions
clk_spi_process :process
begin
clk_spi <= '0';
wait for clk_spi_period/2;
clk_spi <= '1';
wait for clk_spi_period/2;
end process;
spi_start_process :process
begin
spi_start <= '1';
wait for spi_start_period;
spi_start <= '1';
wait for 40 ns;
end process;
-- Stimulus process
stim_proc: process
begin
command_in <= "1000000001011011";
miso_i <= '1';
-- hold reset state for 100 ns.
reset <= '1';
wait for 100 ns;
reset <= '0';
wait for clk_spi_period*10;
-- insert stimulus here
wait;
end process;
END;
| mit | cbbd94e1a5811829776a5796f65833ba | 0.519943 | 3.633159 | false | false | false | false |
upci/upci | Simulações/testes_memoria_16bits/processor_functions.vhd | 1 | 1,325 | LIBRARY ieee;
USE ieee.numeric_std.all;
USE ieee.std_logic_1164.all;
PACKAGE processor_functions IS
TYPE opcode IS (load, store, add, nott, andd, orr, xorr, inc, sub, branch);
FUNCTION Decode (word: STD_LOGIC_VECTOR) RETURN opcode;
CONSTANT n: integer := 16;
CONSTANT wordlen: integer := 16;
CONSTANT oplen: integer := 4;
TYPE memory_array IS ARRAY (0 to 2**(n-oplen-1)) of STD_LOGIC_VECTOR(n-1 DOWNTO 0);
CONSTANT reg_zero: unsigned (n-1 DOWNTO 0) := (OTHERS => '0');
END PACKAGE processor_functions;
PACKAGE BODY processor_functions IS
FUNCTION Decode (word: STD_LOGIC_VECTOR) return opcode IS
VARIABLE opcode_out: opcode;
BEGIN
CASE word(n-1 DOWNTO n-oplen) IS
WHEN "0000" => opcode_out := load;
WHEN "0001" => opcode_out := store;
WHEN "0010" => opcode_out := add;
WHEN "0011" => opcode_out := nott;
WHEN "0100" => opcode_out := andd;
WHEN "0101" => opcode_out := orr;
WHEN "0110" => opcode_out := xorr;
WHEN "0111" => opcode_out := inc;
WHEN "1000" => opcode_out := sub;
WHEN "1001" => opcode_out := branch;
WHEN OTHERS => null;
END CASE;
RETURN opcode_out;
END FUNCTION decode;
END PACKAGE BODY processor_functions; | gpl-2.0 | 05b2e85010463a4aae90dc5638372b92 | 0.593208 | 3.701117 | false | false | false | false |
zhlinh/vhdl_course | Assignment/LED_CNT/LED_CNT.vhd | 1 | 1,341 | --Top-Level Entity
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY LED_CNT IS
PORT (
CLK : IN STD_LOGIC; ---THE CLK OF CNT
CLKDSP : IN STD_LOGIC; ---THE CLK OF SACN
RESET : IN STD_LOGIC;
DOUT : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
SEL : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END ENTITY LED_CNT;
ARCHITECTURE ART OF LED_CNT IS
COMPONENT BCD_CNT
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
DOUT12 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT;
COMPONENT SCANNER
PORT(
CLK_SCAN : IN STD_LOGIC;
RESET : IN STD_LOGIC;
DIN12 : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
NUM : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT;
COMPONENT LED_DEC
PORT(
NUM : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END COMPONENT;
SIGNAL BCD_CNT_MID1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL SCAN_MID2 : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
INST_BCD_CNT : BCD_CNT PORT MAP(
CLK => CLK,
RESET => RESET,
DOUT12 => BCD_CNT_MID1
);
INST_SCANNER : SCANNER PORT MAP(
CLK_SCAN => CLKDSP,
RESET => RESET,
DIN12 => BCD_CNT_MID1,
NUM => SCAN_MID2,
SEL => SEL
);
INST_LED_DEC: LED_DEC PORT MAP(
NUM => SCAN_MID2,
DOUT => DOUT
);
END ARCHITECTURE ART; | apache-2.0 | ebf6b0a4f2ce44ece3b5f0ed62686052 | 0.639821 | 2.747951 | false | false | false | false |
jz0229/open-ephys-pcie | serdes-interface/firmware/data_split.vhd | 3 | 6,099 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:56:40 05/16/2017
-- Design Name:
-- Module Name: data_split - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity data_split is
port(
pclk : in std_logic;
reset : in std_logic;
vsync : in std_logic;
din : in std_logic_vector(7 downto 0);
stream1_o : out std_logic_vector(15 downto 0);
stream2_o : out std_logic_vector(15 downto 0);
stream3_o : out std_logic_vector(15 downto 0);
stream4_o : out std_logic_vector(15 downto 0);
vsync_pcie_o : out std_logic
);
end data_split;
architecture Behavioral of data_split is
type split_state_type is (IDLE, S1MSB, S1LSB, S2MSB, S2LSB, S3MSB, S3LSB, S4MSB, S4LSB, LATCHDATA, WAITLOW); --state machine definition
signal split_state, split_state_next : split_state_type;
signal stream1, stream1_next: std_logic_vector(15 downto 0);
signal stream2, stream2_next: std_logic_vector(15 downto 0);
signal stream3, stream3_next: std_logic_vector(15 downto 0);
signal stream4, stream4_next: std_logic_vector(15 downto 0);
signal stream1_masked : std_logic_vector(15 downto 0);
signal stream2_masked : std_logic_vector(15 downto 0);
signal stream3_masked : std_logic_vector(15 downto 0);
signal stream4_masked : std_logic_vector(15 downto 0);
signal vsync_pcie : std_logic;
begin
--signal mapping
vsync_pcie_o <= vsync_pcie;
stream1_o <= stream1_masked;
stream2_o <= stream2_masked;
stream3_o <= stream3_masked;
stream4_o <= stream4_masked;
--vsync triggers the data spliting process
process(reset, split_state, pclk, stream1, stream2, stream3, stream4, stream1_masked, stream2_masked, stream3_masked, stream3_masked)
begin
if (reset='1') then
split_state <= IDLE;
stream1 <= (others=>'0');
stream2 <= (others=>'0');
stream3 <= (others=>'0');
stream4 <= (others=>'0');
stream1_masked <= (others=>'0');
stream2_masked <= (others=>'0');
stream3_masked <= (others=>'0');
stream4_masked <= (others=>'0');
vsync_pcie <= '0';
elsif (rising_edge(pclk)) then
split_state <= split_state_next;
stream1 <= stream1_next;
stream2 <= stream2_next;
stream3 <= stream3_next;
stream4 <= stream4_next;
if split_state = WAITLOW then
vsync_pcie <= '1';
else
vsync_pcie <= '0';
end if;
if split_state = LATCHDATA then
stream1_masked <= stream1;
stream2_masked <= stream2;
stream3_masked <= stream3;
stream4_masked <= stream4;
else
stream1_masked <= stream1_masked;
stream2_masked <= stream2_masked;
stream3_masked <= stream3_masked;
stream4_masked <= stream4_masked;
end if;
end if;
end process;
--next process
process(reset, split_state, vsync, pclk, stream1, stream2, stream3, stream4, din)
begin
case split_state is
when IDLE =>
if (vsync = '1') then
split_state_next <= S1MSB;
stream1_next(15 downto 8) <= din;
stream1_next(7 downto 0) <= stream1(7 downto 0);
else
split_state_next <= IDLE;
stream1_next <= stream1;
end if;
--2,3,4 unchanged
stream2_next <= stream2;
stream3_next <= stream3;
stream4_next <= stream4;
when S1MSB =>
stream1_next(15 downto 8) <= stream1(15 downto 8);
stream1_next(7 downto 0) <= din;
split_state_next <= S1LSB;
--2,3,4 unchanged
stream2_next <= stream2;
stream3_next <= stream3;
stream4_next <= stream4;
when S1LSB =>
split_state_next <= S2MSB;
--2 MSB
stream2_next(15 downto 8) <= din;
stream2_next(7 downto 0) <= stream2(7 downto 0);
--1,3,4 unchanged
stream1_next <= stream1;
stream3_next <= stream3;
stream4_next <= stream4;
when S2MSB =>
split_state_next <= S2LSB;
--2 LSB
stream2_next(15 downto 8) <= stream2(15 downto 8);
stream2_next(7 downto 0) <= din;
--1,3,4 unchanged
stream1_next <= stream1;
stream3_next <= stream3;
stream4_next <= stream4;
when S2LSB =>
split_state_next <= S3MSB;
--3 MSB
stream3_next(15 downto 8) <= din;
stream3_next(7 downto 0) <= stream3(7 downto 0);
--1,2,4 unchanged
stream1_next <= stream1;
stream2_next <= stream2;
stream4_next <= stream4;
when S3MSB =>
split_state_next <= S3LSB;
--3 LSB
stream3_next(15 downto 8) <= stream3(15 downto 8);
stream3_next(7 downto 0) <= din;
--1,2,4 unchanged
stream1_next <= stream1;
stream2_next <= stream2;
stream4_next <= stream4;
when S3LSB =>
split_state_next <= S4MSB;
--4 MSB
stream4_next(15 downto 8) <= din;
stream4_next(7 downto 0) <= stream4(7 downto 0);
--1,2,3 unchanged
stream1_next <= stream1;
stream2_next <= stream2;
stream3_next <= stream3;
when S4MSB =>
split_state_next <= S4LSB;
--4 LSB
stream4_next(15 downto 8) <= stream4(15 downto 8);
stream4_next(7 downto 0) <= din;
--1,2,3 unchanged
stream1_next <= stream1;
stream2_next <= stream2;
stream3_next <= stream3;
when S4LSB =>
split_state_next <= LATCHDATA;
stream1_next <= stream1;
stream2_next <= stream2;
stream3_next <= stream3;
stream4_next <= stream4;
when LATCHDATA =>
stream1_next <= stream1;
split_state_next <= WAITLOW;
stream1_next <= stream1;
stream2_next <= stream2;
stream3_next <= stream3;
stream4_next <= stream4;
when WAITLOW =>
if (vsync = '0') then
split_state_next <= IDLE;
else
split_state_next <= WAITLOW;
end if;
stream1_next <= stream1;
stream2_next <= stream2;
stream3_next <= stream3;
stream4_next <= stream4;
end case;
end process;
end Behavioral;
| mit | 94c7f70d47fde6fcba2bc493739cc1f1 | 0.604853 | 2.976574 | false | false | false | false |
Hyvok/HardHeat | src/temp_controller.vhd | 1 | 5,655 | library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.utils_pkg.all;
entity temp_controller is
generic
(
CONV_D : natural;
CONV_CMD_D : natural;
OW_US_D : positive;
PWM_N : positive;
PWM_MIN_LVL : positive;
PWM_EN_ON_D : natural;
P_SHIFT_N : integer;
I_SHIFT_N : integer;
TEMP_SETPOINT : integer
);
port
(
clk : in std_logic;
reset : in std_logic;
ow_in : in std_logic;
enable_in : in std_logic;
ow_out : out std_logic;
temp_out : out signed(16 - 1 downto 0);
temp_out_f : out std_logic;
temp_error_out : out std_logic;
pwm_out : out std_logic;
ow_pullup_out : out std_logic
);
end entity;
architecture rtl of temp_controller is
signal reset_ow : std_logic;
signal data_in : std_logic_vector(8 - 1 downto 0);
signal data_in_f : std_logic;
signal receive_data_f : std_logic;
signal busy : std_logic;
signal data_out : std_logic_vector(8 - 1 downto 0);
signal data_out_f : std_logic;
signal err : std_logic;
signal err_id : unsigned(1 downto 0);
signal crc : std_logic_vector(8 - 1 downto 0);
signal pwm_enable : std_logic;
signal temp : signed(16 - 1 downto 0);
signal temp_f : std_logic;
signal pid_out : signed(temp'range);
signal mod_lvl : unsigned(PWM_N - 1 downto 0);
signal mod_lvl_f : std_logic;
signal conv : std_logic;
function trunc_to_unsigned(arg : signed) return unsigned is
begin
return unsigned(std_logic_vector(arg));
end function;
function clamp_to_unsigned(arg : signed) return unsigned is
variable res : unsigned(arg'high - 1 downto 0);
begin
-- Shift value so it is always positive
res := trunc_to_unsigned(resize(arg + to_signed(2**(arg'length - 1) - 1
, arg'length)
, res'length));
return res;
end function;
begin
temp_out <= temp;
temp_out_f <= temp_f;
-- Perform temperature reading at predefined intervals
conv_p: process(clk, reset)
variable timer : unsigned(ceil_log2(CONV_D) downto 0);
begin
if reset = '1' then
timer := to_unsigned(CONV_D, timer'length);
conv <= '0';
elsif rising_edge(clk) then
conv <= '0';
if timer < CONV_D then
timer := timer + 1;
else
conv <= '1';
timer := (others => '0');
end if;
end if;
end process;
ds18b20_p: entity work.ds18b20(rtl)
generic map
(
CONV_DELAY_VAL => CONV_CMD_D
)
port map
(
clk => clk,
reset => reset,
conv_in_f => conv,
data_in => data_out,
data_in_f => data_out_f,
busy_in => busy,
error_in => err,
error_id_in => err_id,
reset_ow_out => reset_ow,
data_out => data_in,
data_out_f => data_in_f,
receive_data_out_f => receive_data_f,
temp_out => temp,
temp_out_f => temp_f,
crc_in => crc,
temp_error_out => temp_error_out,
pullup_out => ow_pullup_out
);
ow_p: entity work.one_wire(rtl)
generic map
(
US_D => OW_US_D
)
port map
(
clk => clk,
reset => reset,
reset_ow => reset_ow,
ow_in => ow_in,
data_in => data_in,
data_in_f => data_in_f,
receive_data_f => receive_data_f,
ow_out => ow_out,
error_out => err,
error_id_out => err_id,
busy_out => busy,
data_out => data_out,
data_out_f => data_out_f,
crc_out => crc
);
pid_p: entity work.pid(rtl)
generic map
(
P_SHIFT_N => P_SHIFT_N,
I_SHIFT_N => I_SHIFT_N,
BITS_N => temp'length,
INIT_OUT_VAL => 0
)
port map
(
clk => clk,
reset => reset,
upd_clk_in => temp_f,
setpoint_in => to_signed(TEMP_SETPOINT, temp'length),
pid_in => temp,
pid_out => pid_out
);
-- Invert, clamp and scale PID output for PWM controller input
mod_lvl <= resize(shift_right(clamp_to_unsigned(-pid_out)
, pid_out'length - mod_lvl'length)
, mod_lvl'length);
pwm_p: entity work.pwm(rtl)
generic map
(
COUNTER_N => PWM_N,
MIN_MOD_LVL => PWM_MIN_LVL,
ENABLE_ON_D => PWM_EN_ON_D
)
port map
(
clk => clk,
reset => reset,
enable_in => enable_in,
mod_lvl_in => mod_lvl,
mod_lvl_f_in => temp_f,
pwm_out => pwm_out
);
end;
| mit | 2496111723eee0cbbac350998146d8c1 | 0.435897 | 3.818366 | false | false | false | false |
sudov/options-accel | final_design/verilog/ieee_FP_pkg/fixed_pkg_c.vhd | 2 | 302,591 | -- --------------------------------------------------------------------
-- "fixed_pkg_c.vhdl" package contains functions for fixed point math.
-- Please see the documentation for the fixed point package.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
-- use ieee_proposed.fixed_float_types.all;
-- use ieee_proposed.fixed_pkg.all;
--
-- This verison is designed to work with the VHDL-93 compilers
-- synthesis tools. Please note the "%%%" comments. These are where we
-- diverge from the VHDL-200X LRM.
-- --------------------------------------------------------------------
-- Version : $Revision: 1.22 $
-- Date : $Date: 2010/09/22 18:34:14 $
-- --------------------------------------------------------------------
use STD.TEXTIO.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library IEEE_PROPOSED;
use IEEE_PROPOSED.fixed_float_types.all;
package fixed_pkg is
-- generic (
-- Rounding routine to use in fixed point, fixed_round or fixed_truncate
constant fixed_round_style : fixed_round_style_type := fixed_round;
-- Overflow routine to use in fixed point, fixed_saturate or fixed_wrap
constant fixed_overflow_style : fixed_overflow_style_type := fixed_saturate;
-- Extra bits used in divide routines
constant fixed_guard_bits : NATURAL := 3;
-- If TRUE, then turn off warnings on "X" propagation
constant no_warning : BOOLEAN := (false
);
-- Author David Bishop ([email protected])
-- base Unsigned fixed point type, downto direction assumed
type UNRESOLVED_ufixed is array (INTEGER range <>) of STD_ULOGIC;
-- base Signed fixed point type, downto direction assumed
type UNRESOLVED_sfixed is array (INTEGER range <>) of STD_ULOGIC;
subtype U_ufixed is UNRESOLVED_ufixed;
subtype U_sfixed is UNRESOLVED_sfixed;
subtype ufixed is UNRESOLVED_ufixed;
subtype sfixed is UNRESOLVED_sfixed;
--===========================================================================
-- Arithmetic Operators:
--===========================================================================
-- Absolute value, 2's complement
-- abs sfixed(a downto b) = sfixed(a+1 downto b)
function "abs" (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Negation, 2's complement
-- - sfixed(a downto b) = sfixed(a+1 downto b)
function "-" (arg : UNRESOLVED_sfixed)return UNRESOLVED_sfixed;
-- Addition
-- ufixed(a downto b) + ufixed(c downto d)
-- = ufixed(maximum(a,c)+1 downto minimum(b,d))
function "+" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) + sfixed(c downto d)
-- = sfixed(maximum(a,c)+1 downto minimum(b,d))
function "+" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Subtraction
-- ufixed(a downto b) - ufixed(c downto d)
-- = ufixed(maximum(a,c)+1 downto minimum(b,d))
function "-" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) - sfixed(c downto d)
-- = sfixed(maximum(a,c)+1 downto minimum(b,d))
function "-" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Multiplication
-- ufixed(a downto b) * ufixed(c downto d) = ufixed(a+c+1 downto b+d)
function "*" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) * sfixed(c downto d) = sfixed(a+c+1 downto b+d)
function "*" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Division
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function "/" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function "/" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Remainder
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b,d))
function "rem" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (minimum(a,c) downto minimum(b,d))
function "rem" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b, d))
function "mod" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto minimum(b, d))
function "mod" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- In these routines the "real" or "natural" (integer)
-- are converted into a fixed point number and then the operation is
-- performed. It is assumed that the array will be large enough.
-- If the input is "real" then the real number is converted into a fixed of
-- the same size as the fixed point input. If the number is an "integer"
-- then it is converted into fixed with the range (l'high downto 0).
----------------------------------------------------------------------------
-- ufixed(a downto b) + ufixed(a downto b) = ufixed(a+1 downto b)
function "+" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(c downto d) + ufixed(c downto d) = ufixed(c+1 downto d)
function "+" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) + ufixed(a downto 0) = ufixed(a+1 downto minimum(0,b))
function "+" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto minimum(0,d))
function "+" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) - ufixed(a downto b) = ufixed(a+1 downto b)
function "-" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(c downto d) - ufixed(c downto d) = ufixed(c+1 downto d)
function "-" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) - ufixed(a downto 0) = ufixed(a+1 downto minimum(0,b))
function "-" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto minimum(0,d))
function "-" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) * ufixed(a downto b) = ufixed(2a+1 downto 2b)
function "*" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(c downto d) * ufixed(c downto d) = ufixed(2c+1 downto 2d)
function "*" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
function "*" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
function "*" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
function "/" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
function "/" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) / ufixed(a downto 0) = ufixed(a downto b-a-1)
function "/" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed(c downto 0) / ufixed(c downto d) = ufixed(c-d downto -c-1)
function "/" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) rem ufixed (a downto b) = ufixed (a downto b)
function "rem" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed (c downto d) rem ufixed (c downto d) = ufixed (c downto d)
function "rem" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) rem ufixed (a downto 0) = ufixed (a downto minimum(b,0))
function "rem" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed (c downto 0) rem ufixed (c downto d) = ufixed (c downto minimum(d,0))
function "rem" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) mod ufixed (a downto b) = ufixed (a downto b)
function "mod" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed (c downto d) mod ufixed (c downto d) = ufixed (c downto d)
function "mod" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) mod ufixed (a downto 0) = ufixed (a downto minimum(b,0))
function "mod" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed (c downto 0) mod ufixed (c downto d) = ufixed (c downto minimum(d,0))
function "mod" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) + sfixed(a downto b) = sfixed(a+1 downto b)
function "+" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) + sfixed(c downto d) = sfixed(c+1 downto d)
function "+" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) + sfixed(a downto 0) = sfixed(a+1 downto minimum(0,b))
function "+" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) + sfixed(c downto d) = sfixed(c+1 downto minimum(0,d))
function "+" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) - sfixed(a downto b) = sfixed(a+1 downto b)
function "-" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) - sfixed(c downto d) = sfixed(c+1 downto d)
function "-" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) - sfixed(a downto 0) = sfixed(a+1 downto minimum(0,b))
function "-" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) - sfixed(c downto d) = sfixed(c+1 downto minimum(0,d))
function "-" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) * sfixed(a downto b) = sfixed(2a+1 downto 2b)
function "*" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) * sfixed(c downto d) = sfixed(2c+1 downto 2d)
function "*" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) * sfixed(a downto 0) = sfixed(2a+1 downto b)
function "*" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) * sfixed(c downto d) = sfixed(2c+1 downto d)
function "*" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) / sfixed(a downto b) = sfixed(a-b+1 downto b-a)
function "/" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) / sfixed(c downto d) = sfixed(c-d+1 downto d-c)
function "/" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) / sfixed(a downto 0) = sfixed(a+1 downto b-a)
function "/" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) / sfixed(c downto d) = sfixed(c-d+1 downto -c)
function "/" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) rem sfixed (a downto b) = sfixed (a downto b)
function "rem" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed (c downto d) rem sfixed (c downto d) = sfixed (c downto d)
function "rem" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) rem sfixed (a downto 0) = sfixed (a downto minimum(b,0))
function "rem" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed (c downto 0) rem sfixed (c downto d) = sfixed (c downto minimum(d,0))
function "rem" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) mod sfixed (a downto b) = sfixed (a downto b)
function "mod" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed (c downto d) mod sfixed (c downto d) = sfixed (c downto d)
function "mod" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) mod sfixed (a downto 0) = sfixed (a downto minimum(b,0))
function "mod" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed (c downto 0) mod sfixed (c downto d) = sfixed (c downto minimum(d,0))
function "mod" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- This version of divide gives the user more control
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function divide (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- This version of divide gives the user more control
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function divide (
l, r : UNRESOLVED_sfixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- These functions return 1/X
-- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
function reciprocal (
arg : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
function reciprocal (
arg : UNRESOLVED_sfixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- REM function
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b,d))
function remainder (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (minimum(a,c) downto minimum(b,d))
function remainder (
l, r : UNRESOLVED_sfixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- mod function
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b, d))
function modulo (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto minimum(b, d))
function modulo (
l, r : UNRESOLVED_sfixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- Procedure for those who need an "accumulator" function.
-- add_carry (ufixed(a downto b), ufixed (c downto d))
-- = ufixed (maximum(a,c) downto minimum(b,d))
procedure add_carry (
L, R : in UNRESOLVED_ufixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_ufixed;
c_out : out STD_ULOGIC);
-- add_carry (sfixed(a downto b), sfixed (c downto d))
-- = sfixed (maximum(a,c) downto minimum(b,d))
procedure add_carry (
L, R : in UNRESOLVED_sfixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_sfixed;
c_out : out STD_ULOGIC);
-- Scales the result by a power of 2. Width of input = width of output with
-- the binary point moved.
function scalb (y : UNRESOLVED_ufixed; N : INTEGER) return UNRESOLVED_ufixed;
function scalb (y : UNRESOLVED_ufixed; N : SIGNED) return UNRESOLVED_ufixed;
function scalb (y : UNRESOLVED_sfixed; N : INTEGER) return UNRESOLVED_sfixed;
function scalb (y : UNRESOLVED_sfixed; N : SIGNED) return UNRESOLVED_sfixed;
function Is_Negative (arg : UNRESOLVED_sfixed) return BOOLEAN;
--===========================================================================
-- Comparison Operators
--===========================================================================
function ">" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function ">" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "<" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "<" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "<=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "<=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function ">=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function ">=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "/=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "/=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function \?=\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?/=\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>=\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<=\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?=\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?/=\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>=\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<=\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function std_match (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function std_match (l, r : UNRESOLVED_sfixed) return BOOLEAN;
-- Overloads the default "maximum" and "minimum" function
function maximum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function minimum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function maximum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function minimum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- In these compare functions a natural is converted into a
-- fixed point number of the bounds "maximum(l'high,0) downto 0"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function ">" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "<" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "/=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function \?=\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?=\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?/=\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>=\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<=\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_ufixed; r : NATURAL)
return UNRESOLVED_ufixed;
function minimum (l : UNRESOLVED_ufixed; r : NATURAL)
return UNRESOLVED_ufixed;
function maximum (l : NATURAL; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function minimum (l : NATURAL; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
----------------------------------------------------------------------------
-- In these compare functions a real is converted into a
-- fixed point number of the bounds "l'high+1 downto l'low"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function ">" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "<" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "/=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function \?=\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?=\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?/=\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>=\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<=\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
function maximum (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function minimum (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
function minimum (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
----------------------------------------------------------------------------
-- In these compare functions an integer is converted into a
-- fixed point number of the bounds "maximum(l'high,1) downto 0"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "/=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function ">=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "<=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function ">" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "<" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "/=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function \?=\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?=\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?/=\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>=\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<=\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_sfixed; r : INTEGER)
return UNRESOLVED_sfixed;
function maximum (l : INTEGER; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function minimum (l : UNRESOLVED_sfixed; r : INTEGER)
return UNRESOLVED_sfixed;
function minimum (l : INTEGER; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- In these compare functions a real is converted into a
-- fixed point number of the bounds "l'high+1 downto l'low"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function ">" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "<" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "/=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function \?=\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?=\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?/=\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>=\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<=\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
function maximum (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function minimum (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
function minimum (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
--===========================================================================
-- Shift and Rotate Functions.
-- Note that sra and sla are not the same as the BIT_VECTOR version
--===========================================================================
function "sll" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "srl" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "rol" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "ror" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "sla" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "sra" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "sll" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "srl" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "rol" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "ror" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "sla" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "sra" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function SHIFT_LEFT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed;
function SHIFT_RIGHT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed;
function SHIFT_LEFT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed;
function SHIFT_RIGHT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (l : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "and" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "or" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "nand" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "nor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "xor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "xnor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "not" (l : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "and" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "or" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "nand" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "nor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "xor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "xnor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "and" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "or" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "or" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "nand" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "nand" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "nor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "nor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "xor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "xor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "xnor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "and" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "and" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "or" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "or" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "nand" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "nand" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "nor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "nor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "xor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "xor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "xnor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
-- Reduction operators, same as numeric_std functions
function and_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function nand_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function or_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function nor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function xor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function xnor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function and_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function nand_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function or_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function nor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function xor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function xnor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
-- returns arg'low-1 if not found
function find_leftmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER;
function find_leftmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER;
-- returns arg'high+1 if not found
function find_rightmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER;
function find_rightmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER;
--===========================================================================
-- RESIZE Functions
--===========================================================================
-- resizes the number (larger or smaller)
-- The returned result will be ufixed (left_index downto right_index)
-- If "round_style" is fixed_round, then the result will be rounded.
-- If the MSB of the remainder is a "1" AND the LSB of the unrounded result
-- is a '1' or the lower bits of the remainder include a '1' then the result
-- will be increased by the smallest representable number for that type.
-- "overflow_style" can be fixed_saturate or fixed_wrap.
-- In saturate mode, if the number overflows then the largest possible
-- representable number is returned. If wrap mode, then the upper bits
-- of the number are truncated.
function resize (
arg : UNRESOLVED_ufixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- "size_res" functions create the size of the output from the indices
-- of the "size_res" input. The actual value of "size_res" is not used.
function resize (
arg : UNRESOLVED_ufixed; -- input
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- Note that in "wrap" mode the sign bit is not replicated. Thus the
-- resize of a negative number can have a positive result in wrap mode.
function resize (
arg : UNRESOLVED_sfixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
function resize (
arg : UNRESOLVED_sfixed; -- input
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
--===========================================================================
-- Conversion Functions
--===========================================================================
-- integer (natural) to unsigned fixed point.
-- arguments are the upper and lower bounds of the number, thus
-- ufixed (7 downto -3) <= to_ufixed (int, 7, -3);
function to_ufixed (
arg : NATURAL; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : NATURAL; -- integer
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- real to unsigned fixed point
function to_ufixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : REAL; -- real
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- unsigned to unsigned fixed point
function to_ufixed (
arg : UNSIGNED; -- unsigned
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- Performs a conversion. ufixed (arg'range) is returned
function to_ufixed (
arg : UNSIGNED) -- unsigned
return UNRESOLVED_ufixed;
-- unsigned fixed point to unsigned
function to_unsigned (
arg : UNRESOLVED_ufixed; -- fixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNSIGNED;
-- unsigned fixed point to unsigned
function to_unsigned (
arg : UNRESOLVED_ufixed; -- fixed point input
size_res : UNSIGNED; -- used for length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNSIGNED;
-- unsigned fixed point to real
function to_real (
arg : UNRESOLVED_ufixed) -- fixed point input
return REAL;
-- unsigned fixed point to integer
function to_integer (
arg : UNRESOLVED_ufixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return NATURAL;
-- Integer to UNRESOLVED_sfixed
function to_sfixed (
arg : INTEGER; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : INTEGER; -- integer
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
-- Real to sfixed
function to_sfixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : REAL; -- real
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- signed to sfixed
function to_sfixed (
arg : SIGNED; -- signed
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : SIGNED; -- signed
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
-- signed to sfixed (output assumed to be size of signed input)
function to_sfixed (
arg : SIGNED) -- signed
return UNRESOLVED_sfixed;
-- Conversion from ufixed to sfixed
function to_sfixed (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_sfixed;
-- signed fixed point to signed
function to_signed (
arg : UNRESOLVED_sfixed; -- fixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return SIGNED;
-- signed fixed point to signed
function to_signed (
arg : UNRESOLVED_sfixed; -- fixed point input
size_res : SIGNED; -- used for length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return SIGNED;
-- signed fixed point to real
function to_real (
arg : UNRESOLVED_sfixed) -- fixed point input
return REAL;
-- signed fixed point to integer
function to_integer (
arg : UNRESOLVED_sfixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return INTEGER;
-- Because of the fairly complicated sizing rules in the fixed point
-- packages these functions are provided to compute the result ranges
-- Example:
-- signal uf1 : ufixed (3 downto -3);
-- signal uf2 : ufixed (4 downto -2);
-- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
-- ufixed_low (3, -3, '*', 4, -2));
-- uf1multuf2 <= uf1 * uf2;
-- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod),
-- '1' (reciprocal), 'a' or 'A' (abs), 'n' or 'N' (unary -)
function ufixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function ufixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function sfixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function sfixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
-- Same as above, but using the "size_res" input only for their ranges:
-- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
-- ufixed_low (uf1, '*', uf2));
-- uf1multuf2 <= uf1 * uf2;
--
function ufixed_high (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER;
function ufixed_low (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER;
function sfixed_high (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER;
function sfixed_low (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
function saturate (
size_res : UNRESOLVED_ufixed) -- only the size of this is used
return UNRESOLVED_ufixed;
function saturate (
size_res : UNRESOLVED_sfixed) -- only the size of this is used
return UNRESOLVED_sfixed;
--===========================================================================
-- Translation Functions
--===========================================================================
-- maps meta-logical values
function to_01 (
s : UNRESOLVED_ufixed; -- fixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_ufixed;
-- maps meta-logical values
function to_01 (
s : UNRESOLVED_sfixed; -- fixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_sfixed;
function Is_X (arg : UNRESOLVED_ufixed) return BOOLEAN;
function Is_X (arg : UNRESOLVED_sfixed) return BOOLEAN;
function to_X01 (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function to_X01 (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function to_X01Z (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function to_X01Z (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function to_UX01 (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function to_UX01 (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- straight vector conversion routines, needed for synthesis.
-- These functions are here so that a std_logic_vector can be
-- converted to and from sfixed and ufixed. Note that you can
-- not convert these vectors because of their negative index.
function to_slv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_LOGIC_VECTOR;
alias to_StdLogicVector is to_slv [UNRESOLVED_ufixed
return STD_LOGIC_VECTOR];
alias to_Std_Logic_Vector is to_slv [UNRESOLVED_ufixed
return STD_LOGIC_VECTOR];
function to_slv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_LOGIC_VECTOR;
alias to_StdLogicVector is to_slv [UNRESOLVED_sfixed
return STD_LOGIC_VECTOR];
alias to_Std_Logic_Vector is to_slv [UNRESOLVED_sfixed
return STD_LOGIC_VECTOR];
function to_sulv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_ULOGIC_VECTOR;
alias to_StdULogicVector is to_sulv [UNRESOLVED_ufixed
return STD_ULOGIC_VECTOR];
alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_ufixed
return STD_ULOGIC_VECTOR];
function to_sulv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_ULOGIC_VECTOR;
alias to_StdULogicVector is to_sulv [UNRESOLVED_sfixed
return STD_ULOGIC_VECTOR];
alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_sfixed
return STD_ULOGIC_VECTOR];
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed;
-- As a concession to those who use a graphical DSP environment,
-- these functions take parameters in those tools format and create
-- fixed point numbers. These functions are designed to convert from
-- a std_logic_vector to the VHDL fixed point format using the conventions
-- of these packages. In a pure VHDL environment you should use the
-- "to_ufixed" and "to_sfixed" routines.
-- unsigned fixed point
function to_UFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed;
-- signed fixed point
function to_SFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed;
-- finding the bounds of a number. These functions can be used like this:
-- signal xxx : ufixed (7 downto -3);
-- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
-- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
-- downto UFix_low(11, 3, "+", 11, 3));
-- Where "11" is the width of xxx (xxx'length),
-- and 3 is the lower bound (abs (xxx'low))
-- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
function UFix_high (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
function UFix_low (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
-- Same as above but for signed fixed point. Note that the width
-- of a signed fixed point number ignores the sign bit, thus
-- width = sxxx'length-1
function SFix_high (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
function SFix_low (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
-- rtl_synthesis off
-- pragma synthesis_off
--===========================================================================
-- string and textio Functions
--===========================================================================
-- purpose: writes fixed point into a line
procedure WRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
-- purpose: writes fixed point into a line
procedure WRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN);
alias bwrite is WRITE [LINE, UNRESOLVED_ufixed, SIDE, width];
alias bwrite is WRITE [LINE, UNRESOLVED_sfixed, SIDE, width];
alias bread is READ [LINE, UNRESOLVED_ufixed];
alias bread is READ [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias bread is READ [LINE, UNRESOLVED_sfixed];
alias bread is READ [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_ufixed, SIDE, width];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_sfixed, SIDE, width];
alias BINARY_READ is READ [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_ufixed];
alias BINARY_READ is READ [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_sfixed];
-- octal read and write
procedure OWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure OWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN);
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_ufixed];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_sfixed];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_ufixed, SIDE, WIDTH];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_sfixed, SIDE, WIDTH];
-- hex read and write
procedure HWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
-- purpose: writes fixed point into a line
procedure HWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN);
alias HEX_READ is HREAD [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_ufixed];
alias HEX_READ is HREAD [LINE, UNRESOLVED_sfixed];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_ufixed, SIDE, WIDTH];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_sfixed, SIDE, WIDTH];
-- returns a string, useful for:
-- assert (x = y) report "error found " & to_string(x) severity error;
function to_string (value : UNRESOLVED_ufixed) return STRING;
alias to_bstring is to_string [UNRESOLVED_ufixed return STRING];
alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_ufixed return STRING];
function to_ostring (value : UNRESOLVED_ufixed) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_ufixed return STRING];
function to_hstring (value : UNRESOLVED_ufixed) return STRING;
alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_ufixed return STRING];
function to_string (value : UNRESOLVED_sfixed) return STRING;
alias to_bstring is to_string [UNRESOLVED_sfixed return STRING];
alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_sfixed return STRING];
function to_ostring (value : UNRESOLVED_sfixed) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_sfixed return STRING];
function to_hstring (value : UNRESOLVED_sfixed) return STRING;
alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_sfixed return STRING];
-- From string functions allow you to convert a string into a fixed
-- point number. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
-- The "." is optional in this syntax, however it exist and is
-- in the wrong location an error is produced. Overflow will
-- result in saturation.
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
alias from_bstring is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
alias from_binary_string is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
-- Octal and hex conversions work as follows:
-- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
-- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
alias from_octal_string is from_ostring [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
alias from_hex_string is from_hstring [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
alias from_bstring is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
alias from_binary_string is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
alias from_octal_string is from_ostring [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
alias from_hex_string is from_hstring [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
-- Same as above, "size_res" is used for it's range only.
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
alias from_bstring is from_string [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
alias from_binary_string is from_string [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
alias from_octal_string is from_ostring [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
alias from_hex_string is from_hstring [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
alias from_bstring is from_string [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
alias from_binary_string is from_string [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
alias from_octal_string is from_ostring [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
alias from_hex_string is from_hstring [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
-- Direct conversion functions. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100"); -- 6.5
-- In this case the "." is not optional, and the size of
-- the output must match exactly.
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_ufixed;
alias from_bstring is from_string [STRING return UNRESOLVED_ufixed];
alias from_binary_string is from_string [STRING return UNRESOLVED_ufixed];
-- Direct octal and hex conversion functions. In this case
-- the string lengths must match. Example:
-- signal sf1 := sfixed (5 downto -3);
-- sf1 <= from_ostring ("71.4") -- -6.5
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_ufixed;
alias from_octal_string is from_ostring [STRING return UNRESOLVED_ufixed];
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_ufixed;
alias from_hex_string is from_hstring [STRING return UNRESOLVED_ufixed];
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_sfixed;
alias from_bstring is from_string [STRING return UNRESOLVED_sfixed];
alias from_binary_string is from_string [STRING return UNRESOLVED_sfixed];
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_sfixed;
alias from_octal_string is from_ostring [STRING return UNRESOLVED_sfixed];
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_sfixed;
alias from_hex_string is from_hstring [STRING return UNRESOLVED_sfixed];
-- rtl_synthesis on
-- pragma synthesis_on
-- IN VHDL-2006 std_logic_vector is a subtype of std_ulogic_vector, so these
-- extra functions are needed for compatability.
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed;
-- unsigned fixed point
function to_UFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed;
-- signed fixed point
function to_SFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed;
end package fixed_pkg;
-------------------------------------------------------------------------------
-- Proposed package body for the VHDL-200x-FT fixed_pkg package
-- (Fixed point math package)
-- This package body supplies a recommended implementation of these functions
-- Version : $Revision: 1.22 $
-- Date : $Date: 2010/09/22 18:34:14 $
--
-- Created for VHDL-200X-ft, David Bishop ([email protected])
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
package body fixed_pkg is
-- Author David Bishop ([email protected])
-- Other contributers: Jim Lewis, Yannick Grugni, Ryan W. Hilton
-- null array constants
constant NAUF : UNRESOLVED_ufixed (0 downto 1) := (others => '0');
constant NASF : UNRESOLVED_sfixed (0 downto 1) := (others => '0');
constant NSLV : STD_ULOGIC_VECTOR (0 downto 1) := (others => '0');
-- This differed constant will tell you if the package body is synthesizable
-- or implemented as real numbers, set to "true" if synthesizable.
constant fixedsynth_or_real : BOOLEAN := true;
-- %%% Replicated functions
function maximum (
l, r : integer) -- inputs
return integer is
begin -- function max
if l > r then return l;
else return r;
end if;
end function maximum;
function minimum (
l, r : integer) -- inputs
return integer is
begin -- function min
if l > r then return r;
else return l;
end if;
end function minimum;
function "sra" (arg : SIGNED; count : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(arg, count);
else
return SHIFT_LEFT(arg, -count);
end if;
end function "sra";
function or_reduce (arg : STD_ULOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '0';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) or BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := or_reduce (BUS_int (BUS_int'left downto Half));
Lower := or_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper or Lower;
end if;
end if;
return Result;
end function or_reduce;
-- purpose: AND all of the bits in a vector together
-- This is a copy of the proposed "and_reduce" from 1076.3
function and_reduce (arg : STD_ULOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '1';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) and BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := and_reduce (BUS_int (BUS_int'left downto Half));
Lower := and_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper and Lower;
end if;
end if;
return Result;
end function and_reduce;
function xor_reduce (arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range
begin
if (arg'length >= 1) then
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int(BUS_int'right) xor BUS_int(BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := xor_reduce (BUS_int (BUS_int'left downto Half));
Lower := xor_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper xor Lower;
end if;
end if;
return Result;
end function xor_reduce;
function nand_reduce(arg : std_ulogic_vector) return STD_ULOGIC is
begin
return not and_reduce (arg);
end function nand_reduce;
function nor_reduce(arg : std_ulogic_vector) return STD_ULOGIC is
begin
return not or_reduce (arg);
end function nor_reduce;
function xnor_reduce(arg : std_ulogic_vector) return STD_ULOGIC is
begin
return not xor_reduce (arg);
end function xnor_reduce;
-- Match table, copied form new std_logic_1164
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
constant match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |
('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |
);
-------------------------------------------------------------------
-- ?= functions, Similar to "std_match", but returns "std_ulogic".
-------------------------------------------------------------------
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return match_logic_table (l, r);
end function \?=\;
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return not match_logic_table (l, r);
end function \?/=\;
-- "?=" operator is similar to "std_match", but returns a std_ulogic..
-- Id: M.2B
function \?=\ (L, R: UNSIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'LENGTH-1;
constant R_LEFT : INTEGER := R'LENGTH-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'LENGTH, R'LENGTH);
variable LX : UNSIGNED(SIZE-1 downto 0);
variable RX : UNSIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin
-- Logically identical to an "=" operator.
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '1';
for i in LX'low to LX'high loop
result1 := \?=\(LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- Id: M.3B
function \?=\ (L, R: SIGNED) return std_ulogic is
constant L_LEFT : INTEGER := L'LENGTH-1;
constant R_LEFT : INTEGER := R'LENGTH-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'LENGTH, R'LENGTH);
variable LX : SIGNED(SIZE-1 downto 0);
variable RX : SIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '1';
for i in LX'low to LX'high loop
result1 := \?=\ (LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
function \?/=\ (L, R : UNSIGNED) return std_ulogic is
constant L_LEFT : INTEGER := L'LENGTH-1;
constant R_LEFT : INTEGER := R'LENGTH-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'LENGTH, R'LENGTH);
variable LX : UNSIGNED(SIZE-1 downto 0);
variable RX : UNSIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?/="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '0';
for i in LX'low to LX'high loop
result1 := \?/=\ (LX(i), RX(i));
if result1 = 'U' then
result := 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
function \?/=\ (L, R : SIGNED) return std_ulogic is
constant L_LEFT : INTEGER := L'LENGTH-1;
constant R_LEFT : INTEGER := R'LENGTH-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'LENGTH, R'LENGTH);
variable LX : SIGNED(SIZE-1 downto 0);
variable RX : SIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?/="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '0';
for i in LX'low to LX'high loop
result1 := \?/=\ (LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
function Is_X ( s : UNSIGNED ) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
function Is_X ( s : SIGNED ) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
function \?>\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- %%% function "?>" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?>"\;
function \?>\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
function \?>=\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- %%% function "?>=" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?>=";
function \?>=\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
function \?<\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- %%% function "?<" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?<";
function \?<\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
function \?<=\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- %%% function "?<=" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?<=";
function \?<=\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- %%% END replicated functions
-- Special version of "minimum" to do some boundary checking without errors
function mins (l, r : INTEGER)
return INTEGER is
begin -- function mins
if (L = INTEGER'low or R = INTEGER'low) then
return 0; -- error condition, silent
end if;
return minimum (L, R);
end function mins;
-- Special version of "minimum" to do some boundary checking with errors
function mine (l, r : INTEGER)
return INTEGER is
begin -- function mine
if (L = INTEGER'low or R = INTEGER'low) then
report fixed_pkg'instance_name
& " Unbounded number passed, was a literal used?"
severity error;
return 0;
end if;
return minimum (L, R);
end function mine;
-- The following functions are used only internally. Every function
-- calls "cleanvec" either directly or indirectly.
-- purpose: Fixes "downto" problem and resolves meta states
function cleanvec (
arg : UNRESOLVED_sfixed) -- input
return UNRESOLVED_sfixed is
constant left_index : INTEGER := maximum(arg'left, arg'right);
constant right_index : INTEGER := mins(arg'left, arg'right);
variable result : UNRESOLVED_sfixed (arg'range);
begin -- function cleanvec
assert not (arg'ascending and (arg'low /= INTEGER'low))
report fixed_pkg'instance_name
& " Vector passed using a ""to"" range, expected is ""downto"""
severity error;
return arg;
end function cleanvec;
-- purpose: Fixes "downto" problem and resolves meta states
function cleanvec (
arg : UNRESOLVED_ufixed) -- input
return UNRESOLVED_ufixed is
constant left_index : INTEGER := maximum(arg'left, arg'right);
constant right_index : INTEGER := mins(arg'left, arg'right);
variable result : UNRESOLVED_ufixed (arg'range);
begin -- function cleanvec
assert not (arg'ascending and (arg'low /= INTEGER'low))
report fixed_pkg'instance_name
& " Vector passed using a ""to"" range, expected is ""downto"""
severity error;
return arg;
end function cleanvec;
-- Type convert a "unsigned" into a "ufixed", used internally
function to_fixed (
arg : UNSIGNED; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
begin -- function to_fixed
result := UNRESOLVED_ufixed(arg);
return result;
end function to_fixed;
-- Type convert a "signed" into an "sfixed", used internally
function to_fixed (
arg : SIGNED; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin -- function to_fixed
result := UNRESOLVED_sfixed(arg);
return result;
end function to_fixed;
-- Type convert a "ufixed" into an "unsigned", used internally
function to_uns (
arg : UNRESOLVED_ufixed) -- fp vector
return UNSIGNED is
subtype t is UNSIGNED(arg'high - arg'low downto 0);
variable slv : t;
begin -- function to_uns
slv := t(arg);
return slv;
end function to_uns;
-- Type convert an "sfixed" into a "signed", used internally
function to_s (
arg : UNRESOLVED_sfixed) -- fp vector
return SIGNED is
subtype t is SIGNED(arg'high - arg'low downto 0);
variable slv : t;
begin -- function to_s
slv := t(arg);
return slv;
end function to_s;
-- adds 1 to the LSB of the number
procedure round_up (arg : in UNRESOLVED_ufixed;
result : out UNRESOLVED_ufixed;
overflowx : out BOOLEAN) is
variable arguns, resuns : UNSIGNED (arg'high-arg'low+1 downto 0)
:= (others => '0');
begin -- round_up
arguns (arguns'high-1 downto 0) := to_uns (arg);
resuns := arguns + 1;
result := to_fixed(resuns(arg'high-arg'low
downto 0), arg'high, arg'low);
overflowx := (resuns(resuns'high) = '1');
end procedure round_up;
-- adds 1 to the LSB of the number
procedure round_up (arg : in UNRESOLVED_sfixed;
result : out UNRESOLVED_sfixed;
overflowx : out BOOLEAN) is
variable args, ress : SIGNED (arg'high-arg'low+1 downto 0);
begin -- round_up
args (args'high-1 downto 0) := to_s (arg);
args(args'high) := arg(arg'high); -- sign extend
ress := args + 1;
result := to_fixed(ress (ress'high-1
downto 0), arg'high, arg'low);
overflowx := ((arg(arg'high) /= ress(ress'high-1))
and (or_reduce (STD_ULOGIC_VECTOR(ress)) /= '0'));
end procedure round_up;
-- Rounding - Performs a "round_nearest" (IEEE 754) which rounds up
-- when the remainder is > 0.5. If the remainder IS 0.5 then if the
-- bottom bit is a "1" it is rounded, otherwise it remains the same.
function round_fixed (arg : UNRESOLVED_ufixed;
remainder : UNRESOLVED_ufixed;
overflow_style : fixed_overflow_style_type := fixed_overflow_style)
return UNRESOLVED_ufixed is
variable rounds : BOOLEAN;
variable round_overflow : BOOLEAN;
variable result : UNRESOLVED_ufixed (arg'range);
begin
rounds := false;
if (remainder'length > 1) then
if (remainder (remainder'high) = '1') then
rounds := (arg(arg'low) = '1')
or (or_reduce (to_sulv(remainder(remainder'high-1 downto
remainder'low))) = '1');
end if;
else
rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');
end if;
if rounds then
round_up(arg => arg,
result => result,
overflowx => round_overflow);
else
result := arg;
end if;
if (overflow_style = fixed_saturate) and round_overflow then
result := saturate (result'high, result'low);
end if;
return result;
end function round_fixed;
-- Rounding case statement
function round_fixed (arg : UNRESOLVED_sfixed;
remainder : UNRESOLVED_sfixed;
overflow_style : fixed_overflow_style_type := fixed_overflow_style)
return UNRESOLVED_sfixed is
variable rounds : BOOLEAN;
variable round_overflow : BOOLEAN;
variable result : UNRESOLVED_sfixed (arg'range);
begin
rounds := false;
if (remainder'length > 1) then
if (remainder (remainder'high) = '1') then
rounds := (arg(arg'low) = '1')
or (or_reduce (to_sulv(remainder(remainder'high-1 downto
remainder'low))) = '1');
end if;
else
rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');
end if;
if rounds then
round_up(arg => arg,
result => result,
overflowx => round_overflow);
else
result := arg;
end if;
if round_overflow then
if (overflow_style = fixed_saturate) then
if arg(arg'high) = '0' then
result := saturate (result'high, result'low);
else
result := not saturate (result'high, result'low);
end if;
-- Sign bit not fixed when wrapping
end if;
end if;
return result;
end function round_fixed;
-- converts an sfixed into a ufixed. The output is the same length as the
-- input, because abs("1000") = "1000" = 8.
function to_ufixed (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_ufixed
is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable xarg : UNRESOLVED_sfixed(left_index+1 downto right_index);
variable result : UNRESOLVED_ufixed(left_index downto right_index);
begin
if arg'length < 1 then
return NAUF;
end if;
xarg := abs(arg);
result := UNRESOLVED_ufixed (xarg (left_index downto right_index));
return result;
end function to_ufixed;
-----------------------------------------------------------------------------
-- Visible functions
-----------------------------------------------------------------------------
-- Conversion functions. These are needed for synthesis where typically
-- the only input and output type is a std_logic_vector.
function to_sulv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_ULOGIC_VECTOR is
variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0);
begin
if arg'length < 1 then
return NSLV;
end if;
result := STD_ULOGIC_VECTOR (arg);
return result;
end function to_sulv;
function to_sulv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_ULOGIC_VECTOR is
variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0);
begin
if arg'length < 1 then
return NSLV;
end if;
result := STD_ULOGIC_VECTOR (arg);
return result;
end function to_sulv;
function to_slv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_LOGIC_VECTOR is
begin
return to_stdlogicvector(to_sulv(arg));
end function to_slv;
function to_slv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_LOGIC_VECTOR is
begin
return to_stdlogicvector(to_sulv(arg));
end function to_slv;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return unresolved_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (arg'length < 1 or right_index > left_index) then
return NAUF;
end if;
if (arg'length /= result'length) then
report fixed_pkg'instance_name & "TO_UFIXED(SLV) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NAUF;
else
result := to_fixed (arg => UNSIGNED(arg),
left_index => left_index,
right_index => right_index);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return unresolved_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (arg'length < 1 or right_index > left_index) then
return NASF;
end if;
if (arg'length /= result'length) then
report fixed_pkg'instance_name & "TO_SFIXED(SLV) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NASF;
else
result := to_fixed (arg => SIGNED(arg),
left_index => left_index,
right_index => right_index);
return result;
end if;
end function to_sfixed;
-- Two's complement number, Grows the vector by 1 bit.
-- because "abs (1000.000) = 01000.000" or abs(-16) = 16.
function "abs" (
arg : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable ressns : SIGNED (arg'length downto 0);
variable result : UNRESOLVED_sfixed (left_index+1 downto right_index);
begin
if (arg'length < 1 or result'length < 1) then
return NASF;
end if;
ressns (arg'length-1 downto 0) := to_s (cleanvec (arg));
ressns (arg'length) := ressns (arg'length-1); -- expand sign bit
result := to_fixed (abs(ressns), left_index+1, right_index);
return result;
end function "abs";
-- also grows the vector by 1 bit.
function "-" (
arg : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
constant left_index : INTEGER := arg'high+1;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable ressns : SIGNED (arg'length downto 0);
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (arg'length < 1 or result'length < 1) then
return NASF;
end if;
ressns (arg'length-1 downto 0) := to_s (cleanvec(arg));
ressns (arg'length) := ressns (arg'length-1); -- expand sign bit
result := to_fixed (-ressns, left_index, right_index);
return result;
end function "-";
-- Addition
function "+" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) + ufixed(c downto d) =
return UNRESOLVED_ufixed is -- ufixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv + rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "+";
function "+" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) + sfixed(c downto d) =
return UNRESOLVED_sfixed is -- sfixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index downto 0);
variable result_slv : SIGNED (left_index-right_index downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv + rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "+";
-- Subtraction
function "-" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) - ufixed(c downto d) =
return UNRESOLVED_ufixed is -- ufixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv - rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "-";
function "-" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) - sfixed(c downto d) =
return UNRESOLVED_sfixed is -- sfixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index downto 0);
variable result_slv : SIGNED (left_index-right_index downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv - rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "-";
function "*" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) * ufixed(c downto d) =
return UNRESOLVED_ufixed is -- ufixed(a+c+1 downto b+d)
variable lslv : UNSIGNED (l'length-1 downto 0);
variable rslv : UNSIGNED (r'length-1 downto 0);
variable result_slv : UNSIGNED (r'length+l'length-1 downto 0);
variable result : UNRESOLVED_ufixed (l'high + r'high+1 downto
mine(l'low, l'low) + mine(r'low, r'low));
begin
if (l'length < 1 or r'length < 1 or
result'length /= result_slv'length) then
return NAUF;
end if;
lslv := to_uns (cleanvec(l));
rslv := to_uns (cleanvec(r));
result_slv := lslv * rslv;
result := to_fixed (result_slv, result'high, result'low);
return result;
end function "*";
function "*" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) * sfixed(c downto d) =
return UNRESOLVED_sfixed is -- sfixed(a+c+1 downto b+d)
variable lslv : SIGNED (l'length-1 downto 0);
variable rslv : SIGNED (r'length-1 downto 0);
variable result_slv : SIGNED (r'length+l'length-1 downto 0);
variable result : UNRESOLVED_sfixed (l'high + r'high+1 downto
mine(l'low, l'low) + mine(r'low, r'low));
begin
if (l'length < 1 or r'length < 1 or
result'length /= result_slv'length) then
return NASF;
end if;
lslv := to_s (cleanvec(l));
rslv := to_s (cleanvec(r));
result_slv := lslv * rslv;
result := to_fixed (result_slv, result'high, result'low);
return result;
end function "*";
function "/" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) / ufixed(c downto d) =
return UNRESOLVED_ufixed is -- ufixed(a-d downto b-c-1)
begin
return divide (l, r);
end function "/";
function "/" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) / sfixed(c downto d) =
return UNRESOLVED_sfixed is -- sfixed(a-d+1 downto b-c)
begin
return divide (l, r);
end function "/";
-- This version of divide gives the user more control
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function divide (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (l'high - mine(r'low, r'low) downto
mine (l'low, l'low) - r'high -1);
variable dresult : UNRESOLVED_ufixed (result'high downto result'low -guard_bits);
variable lresize : UNRESOLVED_ufixed (l'high downto l'high - dresult'length+1);
variable lslv : UNSIGNED (lresize'length-1 downto 0);
variable rslv : UNSIGNED (r'length-1 downto 0);
variable result_slv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NAUF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_uns (cleanvec (lresize));
rslv := to_uns (cleanvec (r));
if (rslv = 0) then
report fixed_pkg'instance_name
& "DIVIDE(ufixed) Division by zero" severity error;
result := saturate (result'high, result'low); -- saturate
else
result_slv := lslv / rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap, -- overflow impossible
round_style => round_style);
end if;
return result;
end function divide;
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function divide (
l, r : UNRESOLVED_sfixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (l'high - mine(r'low, r'low) + 1 downto
mine (l'low, l'low) - r'high);
variable dresult : UNRESOLVED_sfixed (result'high downto result'low-guard_bits);
variable lresize : UNRESOLVED_sfixed (l'high+1 downto l'high+1 -dresult'length+1);
variable lslv : SIGNED (lresize'length-1 downto 0);
variable rslv : SIGNED (r'length-1 downto 0);
variable result_slv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_s (cleanvec (lresize));
rslv := to_s (cleanvec (r));
if (rslv = 0) then
report fixed_pkg'instance_name
& "DIVIDE(sfixed) Division by zero" severity error;
result := saturate (result'high, result'low);
else
result_slv := lslv / rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap, -- overflow impossible
round_style => round_style);
end if;
return result;
end function divide;
-- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
function reciprocal (
arg : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed is
constant one : UNRESOLVED_ufixed (0 downto 0) := "1";
begin
return divide (l => one,
r => arg,
round_style => round_style,
guard_bits => guard_bits);
end function reciprocal;
-- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
function reciprocal (
arg : UNRESOLVED_sfixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed is
constant one : UNRESOLVED_sfixed (1 downto 0) := "01"; -- extra bit.
variable resultx : UNRESOLVED_sfixed (-mine(arg'low, arg'low)+2 downto -arg'high);
begin
if (arg'length < 1 or resultx'length < 1) then
return NASF;
else
resultx := divide (l => one,
r => arg,
round_style => round_style,
guard_bits => guard_bits);
return resultx (resultx'high-1 downto resultx'low); -- remove extra bit
end if;
end function reciprocal;
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function "rem" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return remainder (l, r);
end function "rem";
-- remainder
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function "rem" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return remainder (l, r);
end function "rem";
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function remainder (
l, r : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (minimum(l'high, r'high) downto
mine(l'low, r'low));
variable lresize : UNRESOLVED_ufixed (maximum(l'high, r'low) downto
mins(r'low, r'low)-guard_bits);
variable rresize : UNRESOLVED_ufixed (r'high downto r'low-guard_bits);
variable dresult : UNRESOLVED_ufixed (rresize'range);
variable lslv : UNSIGNED (lresize'length-1 downto 0);
variable rslv : UNSIGNED (rresize'length-1 downto 0);
variable result_slv : UNSIGNED (rslv'range);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NAUF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_uns (lresize);
rresize := resize (arg => r,
left_index => rresize'high,
right_index => rresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
rslv := to_uns (rresize);
if (rslv = 0) then
report fixed_pkg'instance_name
& "remainder(ufixed) Division by zero" severity error;
result := saturate (result'high, result'low); -- saturate
else
if (r'low <= l'high) then
result_slv := lslv rem rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap, -- can't overflow
round_style => round_style);
end if;
if l'low < r'low then
result(mins(r'low-1, l'high) downto l'low) :=
cleanvec(l(mins(r'low-1, l'high) downto l'low));
end if;
end if;
return result;
end function remainder;
-- remainder
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function remainder (
l, r : UNRESOLVED_sfixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed is
variable l_abs : UNRESOLVED_ufixed (l'range);
variable r_abs : UNRESOLVED_ufixed (r'range);
variable result : UNRESOLVED_sfixed (minimum(r'high, l'high) downto
mine(r'low, l'low));
variable neg_result : UNRESOLVED_sfixed (minimum(r'high, l'high)+1 downto
mins(r'low, l'low));
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
l_abs := to_ufixed (l);
r_abs := to_ufixed (r);
result := UNRESOLVED_sfixed (remainder (
l => l_abs,
r => r_abs,
round_style => round_style));
neg_result := -result;
if l(l'high) = '1' then
result := neg_result(result'range);
end if;
return result;
end function remainder;
-- modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function "mod" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return modulo (l, r);
end function "mod";
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function "mod" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return modulo(l, r);
end function "mod";
-- modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function modulo (
l, r : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed is
begin
return remainder(l => l,
r => r,
round_style => round_style,
guard_bits => guard_bits);
end function modulo;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function modulo (
l, r : UNRESOLVED_sfixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed is
variable l_abs : UNRESOLVED_ufixed (l'range);
variable r_abs : UNRESOLVED_ufixed (r'range);
variable result : UNRESOLVED_sfixed (r'high downto
mine(r'low, l'low));
variable dresult : UNRESOLVED_sfixed (minimum(r'high, l'high)+1 downto
mins(r'low, l'low));
variable dresult_not_zero : BOOLEAN;
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
l_abs := to_ufixed (l);
r_abs := to_ufixed (r);
dresult := "0" & UNRESOLVED_sfixed(remainder (l => l_abs,
r => r_abs,
round_style => round_style));
if (to_s(dresult) = 0) then
dresult_not_zero := false;
else
dresult_not_zero := true;
end if;
if to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '0'
and dresult_not_zero then
result := resize (arg => r - dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
elsif to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '1' then
result := resize (arg => -dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
elsif to_x01(l(l'high)) = '0' and to_x01(r(r'high)) = '1'
and dresult_not_zero then
result := resize (arg => dresult + r,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
else
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
end if;
return result;
end function modulo;
-- Procedure for those who need an "accumulator" function
procedure add_carry (
L, R : in UNRESOLVED_ufixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_ufixed;
c_out : out STD_ULOGIC) is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
variable cx : UNSIGNED (0 downto 0); -- Carry in
begin
if (l'length < 1 or r'length < 1) then
result := NAUF;
c_out := '0';
else
cx (0) := c_in;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv + rslv + cx;
c_out := result_slv(left_index);
result := to_fixed(result_slv (left_index-right_index-1 downto 0),
left_index-1, right_index);
end if;
end procedure add_carry;
procedure add_carry (
L, R : in UNRESOLVED_sfixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_sfixed;
c_out : out STD_ULOGIC) is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index
downto 0);
variable result_slv : SIGNED (left_index-right_index
downto 0);
variable cx : SIGNED (1 downto 0); -- Carry in
begin
if (l'length < 1 or r'length < 1) then
result := NASF;
c_out := '0';
else
cx (1) := '0';
cx (0) := c_in;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv + rslv + cx;
c_out := result_slv(left_index);
result := to_fixed(result_slv (left_index-right_index-1 downto 0),
left_index-1, right_index);
end if;
end procedure add_carry;
-- Scales the result by a power of 2. Width of input = width of output with
-- the decimal point moved.
function scalb (y : UNRESOLVED_ufixed; N : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (y'high+N downto y'low+N);
begin
if y'length < 1 then
return NAUF;
else
result := y;
return result;
end if;
end function scalb;
function scalb (y : UNRESOLVED_ufixed; N : SIGNED)
return UNRESOLVED_ufixed is
begin
return scalb (y => y,
N => to_integer(N));
end function scalb;
function scalb (y : UNRESOLVED_sfixed; N : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (y'high+N downto y'low+N);
begin
if y'length < 1 then
return NASF;
else
result := y;
return result;
end if;
end function scalb;
function scalb (y : UNRESOLVED_sfixed; N : SIGNED)
return UNRESOLVED_sfixed is
begin
return scalb (y => y,
N => to_integer(N));
end function scalb;
function Is_Negative (arg : UNRESOLVED_sfixed) return BOOLEAN is
begin
if to_X01(arg(arg'high)) = '1' then
return true;
else
return false;
end if;
end function Is_Negative;
function find_rightmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'reverse_range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_rightmost;
function find_leftmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_leftmost;
function find_rightmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'reverse_range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_rightmost;
function find_leftmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_leftmost;
function "sll" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sll";
function "srl" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "srl";
function "rol" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv rol COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "rol";
function "ror" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv ror COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "ror";
function "sla" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
-- Arithmetic shift on an unsigned is a logical shift
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sla";
function "sra" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
-- Arithmetic shift on an unsigned is a logical shift
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sra";
function "sll" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sll";
function "srl" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "srl";
function "rol" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv rol COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "rol";
function "ror" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv ror COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "ror";
function "sla" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
if COUNT > 0 then
-- Arithmetic shift left on a 2's complement number is a logic shift
argslv := argslv sll COUNT;
else
argslv := argslv sra -COUNT;
end if;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sla";
function "sra" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
if COUNT > 0 then
argslv := argslv sra COUNT;
else
-- Arithmetic shift left on a 2's complement number is a logic shift
argslv := argslv sll -COUNT;
end if;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sra";
-- Because some people want the older functions.
function SHIFT_LEFT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed is
begin
if (ARG'length < 1) then
return NAUF;
end if;
return ARG sla COUNT;
end function SHIFT_LEFT;
function SHIFT_RIGHT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed is
begin
if (ARG'length < 1) then
return NAUF;
end if;
return ARG sra COUNT;
end function SHIFT_RIGHT;
function SHIFT_LEFT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed is
begin
if (ARG'length < 1) then
return NASF;
end if;
return ARG sla COUNT;
end function SHIFT_LEFT;
function SHIFT_RIGHT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed is
begin
if (ARG'length < 1) then
return NASF;
end if;
return ARG sra COUNT;
end function SHIFT_RIGHT;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (L : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_sulv(L);
return to_ufixed(RESULT, L'high, L'low);
end function "not";
function "and" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) and to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "and";
function "or" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) or to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "or";
function "nand" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nand to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "nand";
function "nor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nor to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "nor";
function "xor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xor to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "xor";
function "xnor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xnor to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "xnor";
function "not" (L : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_sulv(L);
return to_sfixed(RESULT, L'high, L'low);
end function "not";
function "and" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) and to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "and";
function "or" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) or to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "or";
function "nand" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nand to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "nand";
function "nor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nor to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "nor";
function "xor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xor to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "xor";
function "xnor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xnor to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "xnor";
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
function "and" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
-- Reduction operator_reduces
function and_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return and_reduce (to_sulv(l));
end function and_reduce;
function nand_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return nand_reduce (to_sulv(l));
end function nand_reduce;
function or_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return or_reduce (to_sulv(l));
end function or_reduce;
function nor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return nor_reduce (to_sulv(l));
end function nor_reduce;
function xor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return xor_reduce (to_sulv(l));
end function xor_reduce;
function xnor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return xnor_reduce (to_sulv(l));
end function xnor_reduce;
function and_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return and_reduce (to_sulv(l));
end function and_reduce;
function nand_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return nand_reduce (to_sulv(l));
end function nand_reduce;
function or_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return or_reduce (to_sulv(l));
end function or_reduce;
function nor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return nor_reduce (to_sulv(l));
end function nor_reduce;
function xor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return xor_reduce (to_sulv(l));
end function xor_reduce;
function xnor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return xnor_reduce (to_sulv(l));
end function xnor_reduce;
-- End reduction operator_reduces
function \?=\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?=\ (lslv, rslv);
end if;
end function \?=\;
function \?/=\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?/=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?/="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?/=\ (lslv, rslv);
end if;
end function \?/=\;
function \?>\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?>
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?>"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?>\ (lslv, rslv);
end if;
end function \?>\;
function \?>=\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?>=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?>="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?>=\ (lslv, rslv);
end if;
end function \?>=\;
function \?<\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?<
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?<"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?<\ (lslv, rslv);
end if;
end function \?<\;
function \?<=\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?<=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?<="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?<=\ (lslv, rslv);
end if;
end function \?<=\;
function \?=\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?=\ (lslv, rslv);
end if;
end function \?=\;
function \?/=\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?/=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?/="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?/=\ (lslv, rslv);
end if;
end function \?/=\;
function \?>\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?>
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?>"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?>\ (lslv, rslv);
end if;
end function \?>\;
function \?>=\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?>=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?>="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?>=\ (lslv, rslv);
end if;
end function \?>=\;
function \?<\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?<
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?<"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?<\ (lslv, rslv);
end if;
end function \?<\;
function \?<=\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?<=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?<="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?<=\ (lslv, rslv);
end if;
end function \?<=\;
-- Match function, similar to "std_match" from numeric_std
function std_match (L, R : UNRESOLVED_ufixed) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_sulv(L), to_sulv(R));
else
assert NO_WARNING
report fixed_pkg'instance_name
& "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
function std_match (L, R : UNRESOLVED_sfixed) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_sulv(L), to_sulv(R));
else
assert NO_WARNING
report fixed_pkg'instance_name
& "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
-- compare functions
function "=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv = rslv;
end function "=";
function "=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv = rslv;
end function "=";
function "/=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """/="": null argument detected, returning TRUE"
severity warning;
return true;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv /= rslv;
end function "/=";
function "/=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """/="": null argument detected, returning TRUE"
severity warning;
return true;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv /= rslv;
end function "/=";
function ">" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv > rslv;
end function ">";
function ">" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv > rslv;
end function ">";
function "<" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv < rslv;
end function "<";
function "<" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv < rslv;
end function "<";
function ">=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv >= rslv;
end function ">=";
function ">=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv >= rslv;
end function ">=";
function "<=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv <= rslv;
end function "<=";
function "<=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv <= rslv;
end function "<=";
-- overloads of the default maximum and minimum functions
function maximum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
if lresize > rresize then return lresize;
else return rresize;
end if;
end function maximum;
function maximum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
if lresize > rresize then return lresize;
else return rresize;
end if;
end function maximum;
function minimum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
if lresize > rresize then return rresize;
else return lresize;
end if;
end function minimum;
function minimum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
if lresize > rresize then return rresize;
else return lresize;
end if;
end function minimum;
function to_ufixed (
arg : NATURAL; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_ufixed (left_index downto fw);
variable sresult : UNRESOLVED_ufixed (left_index downto 0) :=
(others => '0'); -- integer portion
variable argx : NATURAL; -- internal version of arg
begin
if (result'length < 1) then
return NAUF;
end if;
if arg /= 0 then
argx := arg;
for I in 0 to sresult'left loop
if (argx mod 2) = 0 then
sresult(I) := '0';
else
sresult(I) := '1';
end if;
argx := argx/2;
end loop;
if argx /= 0 then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_UFIXED(NATURAL): vector truncated"
severity warning;
if overflow_style = fixed_saturate then
return saturate (left_index, right_index);
end if;
end if;
result := resize (arg => sresult,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
else
result := (others => '0');
end if;
return result;
end function to_ufixed;
function to_sfixed (
arg : INTEGER; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_sfixed (left_index downto fw);
variable sresult : UNRESOLVED_sfixed (left_index downto 0) :=
(others => '0'); -- integer portion
variable argx : INTEGER; -- internal version of arg
variable sign : STD_ULOGIC; -- sign of input
begin
if (result'length < 1) then -- null range
return NASF;
end if;
if arg /= 0 then
if (arg < 0) then
sign := '1';
argx := -(arg + 1);
else
sign := '0';
argx := arg;
end if;
for I in 0 to sresult'left loop
if (argx mod 2) = 0 then
sresult(I) := sign;
else
sresult(I) := not sign;
end if;
argx := argx/2;
end loop;
if argx /= 0 or left_index < 0 or sign /= sresult(sresult'left) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_SFIXED(INTEGER): vector truncated"
severity warning;
if overflow_style = fixed_saturate then -- saturate
if arg < 0 then
result := not saturate (result'high, result'low); -- underflow
else
result := saturate (result'high, result'low); -- overflow
end if;
return result;
end if;
end if;
result := resize (arg => sresult,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
else
result := (others => '0');
end if;
return result;
end function to_sfixed;
function to_ufixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_ufixed is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_ufixed (left_index downto fw) :=
(others => '0');
variable Xresult : UNRESOLVED_ufixed (left_index downto
fw-guard_bits) :=
(others => '0');
variable presult : REAL;
-- variable overflow_needed : BOOLEAN;
begin
-- If negative or null range, return.
if (left_index < fw) then
return NAUF;
end if;
if (arg < 0.0) then
report fixed_pkg'instance_name
& "TO_UFIXED: Negative argument passed "
& REAL'image(arg) severity error;
return result;
end if;
presult := arg;
if presult >= (2.0**(left_index+1)) then
assert NO_WARNING report fixed_pkg'instance_name
& "TO_UFIXED(REAL): vector truncated"
severity warning;
if overflow_style = fixed_wrap then
presult := presult mod (2.0**(left_index+1)); -- wrap
else
return saturate (result'high, result'low);
end if;
end if;
for i in Xresult'range loop
if presult >= 2.0**i then
Xresult(i) := '1';
presult := presult - 2.0**i;
else
Xresult(i) := '0';
end if;
end loop;
if guard_bits > 0 and round_style = fixed_round then
result := round_fixed (arg => Xresult (left_index
downto right_index),
remainder => Xresult (right_index-1 downto
right_index-guard_bits),
overflow_style => overflow_style);
else
result := Xresult (result'range);
end if;
return result;
end function to_ufixed;
function to_sfixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_sfixed is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_sfixed (left_index downto fw) :=
(others => '0');
variable Xresult : UNRESOLVED_sfixed (left_index+1 downto fw-guard_bits) :=
(others => '0');
variable presult : REAL;
begin
if (left_index < fw) then -- null range
return NASF;
end if;
if (arg >= (2.0**left_index) or arg < -(2.0**left_index)) then
assert NO_WARNING report fixed_pkg'instance_name
& "TO_SFIXED(REAL): vector truncated"
severity warning;
if overflow_style = fixed_saturate then
if arg < 0.0 then -- saturate
result := not saturate (result'high, result'low); -- underflow
else
result := saturate (result'high, result'low); -- overflow
end if;
return result;
else
presult := abs(arg) mod (2.0**(left_index+1)); -- wrap
end if;
else
presult := abs(arg);
end if;
for i in Xresult'range loop
if presult >= 2.0**i then
Xresult(i) := '1';
presult := presult - 2.0**i;
else
Xresult(i) := '0';
end if;
end loop;
if arg < 0.0 then
Xresult := to_fixed(-to_s(Xresult), Xresult'high, Xresult'low);
end if;
if guard_bits > 0 and round_style = fixed_round then
result := round_fixed (arg => Xresult (left_index
downto right_index),
remainder => Xresult (right_index-1 downto
right_index-guard_bits),
overflow_style => overflow_style);
else
result := Xresult (result'range);
end if;
return result;
end function to_sfixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
variable result : UNRESOLVED_ufixed (left_index downto right_index);
begin
if arg'length < 1 or (left_index < right_index) then
return NAUF;
end if;
result := resize (arg => UNRESOLVED_ufixed (XARG),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_ufixed;
-- converted version
function to_ufixed (
arg : UNSIGNED) -- unsigned
return UNRESOLVED_ufixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
begin
if arg'length < 1 then
return NAUF;
end if;
return UNRESOLVED_ufixed(xarg);
end function to_ufixed;
function to_sfixed (
arg : SIGNED; -- signed
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin
if arg'length < 1 or (left_index < right_index) then
return NASF;
end if;
result := resize (arg => UNRESOLVED_sfixed (XARG),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_sfixed;
-- converted version
function to_sfixed (
arg : SIGNED) -- signed
return UNRESOLVED_sfixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
begin
if arg'length < 1 then
return NASF;
end if;
return UNRESOLVED_sfixed(xarg);
end function to_sfixed;
function to_sfixed (arg : UNRESOLVED_ufixed) return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (arg'high+1 downto arg'low);
begin
if arg'length < 1 then
return NASF;
end if;
result (arg'high downto arg'low) := UNRESOLVED_sfixed(cleanvec(arg));
result (arg'high+1) := '0';
return result;
end function to_sfixed;
-- Because of the fairly complicated sizing rules in the fixed point
-- packages these functions are provided to compute the result ranges
-- Example:
-- signal uf1 : ufixed (3 downto -3);
-- signal uf2 : ufixed (4 downto -2);
-- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
-- ufixed_low (3, -3, '*', 4, -2));
-- uf1multuf2 <= uf1 * uf2;
-- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod),
-- '1' (reciprocal), 'A', 'a' (abs), 'N', 'n' (-sfixed)
function ufixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return maximum (left_index, left_index2) + 1;
when '*' => return left_index + left_index2 + 1;
when '/' => return left_index - right_index2;
when '1' => return -right_index; -- reciprocal
when 'R'|'r' => return mins (left_index, left_index2); -- "rem"
when 'M'|'m' => return mins (left_index, left_index2); -- "mod"
when others => return left_index; -- For abs and default
end case;
end function ufixed_high;
function ufixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return mins (right_index, right_index2);
when '*' => return right_index + right_index2;
when '/' => return right_index - left_index2 - 1;
when '1' => return -left_index - 1; -- reciprocal
when 'R'|'r' => return mins (right_index, right_index2); -- "rem"
when 'M'|'m' => return mins (right_index, right_index2); -- "mod"
when others => return right_index; -- for abs and default
end case;
end function ufixed_low;
function sfixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return maximum (left_index, left_index2) + 1;
when '*' => return left_index + left_index2 + 1;
when '/' => return left_index - right_index2 + 1;
when '1' => return -right_index + 1; -- reciprocal
when 'R'|'r' => return mins (left_index, left_index2); -- "rem"
when 'M'|'m' => return left_index2; -- "mod"
when 'A'|'a' => return left_index + 1; -- "abs"
when 'N'|'n' => return left_index + 1; -- -sfixed
when others => return left_index;
end case;
end function sfixed_high;
function sfixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return mins (right_index, right_index2);
when '*' => return right_index + right_index2;
when '/' => return right_index - left_index2;
when '1' => return -left_index; -- reciprocal
when 'R'|'r' => return mins (right_index, right_index2); -- "rem"
when 'M'|'m' => return mins (right_index, right_index2); -- "mod"
when others => return right_index; -- default for abs, neg and default
end case;
end function sfixed_low;
-- Same as above, but using the "size_res" input only for their ranges:
-- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
-- ufixed_low (uf1, '*', uf2));
-- uf1multuf2 <= uf1 * uf2;
function ufixed_high (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER is
begin
return ufixed_high (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function ufixed_high;
function ufixed_low (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER is
begin
return ufixed_low (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function ufixed_low;
function sfixed_high (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER is
begin
return sfixed_high (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function sfixed_high;
function sfixed_low (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER is
begin
return sfixed_low (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function sfixed_low;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
constant sat : UNRESOLVED_ufixed (left_index downto right_index) :=
(others => '1');
begin
return sat;
end function saturate;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable sat : UNRESOLVED_sfixed (left_index downto right_index) :=
(others => '1');
begin
-- saturate positive, to saturate negative, just do "not saturate()"
sat (left_index) := '0';
return sat;
end function saturate;
function saturate (
size_res : UNRESOLVED_ufixed) -- only the size of this is used
return UNRESOLVED_ufixed is
begin
return saturate (size_res'high, size_res'low);
end function saturate;
function saturate (
size_res : UNRESOLVED_sfixed) -- only the size of this is used
return UNRESOLVED_sfixed is
begin
return saturate (size_res'high, size_res'low);
end function saturate;
-- As a concession to those who use a graphical DSP environment,
-- these functions take parameters in those tools format and create
-- fixed point numbers. These functions are designed to convert from
-- a std_logic_vector to the VHDL fixed point format using the conventions
-- of these packages. In a pure VHDL environment you should use the
-- "to_ufixed" and "to_sfixed" routines.
-- Unsigned fixed point
function to_UFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (width-fraction-1 downto -fraction);
begin
if (arg'length /= result'length) then
report fixed_pkg'instance_name
& "TO_UFIX (STD_ULOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NAUF;
else
result := to_ufixed (arg, result'high, result'low);
return result;
end if;
end function to_UFix;
-- signed fixed point
function to_SFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (width-fraction-1 downto -fraction);
begin
if (arg'length /= result'length) then
report fixed_pkg'instance_name
& "TO_SFIX (STD_ULOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NASF;
else
result := to_sfixed (arg, result'high, result'low);
return result;
end if;
end function to_SFix;
-- finding the bounds of a number. These functions can be used like this:
-- signal xxx : ufixed (7 downto -3);
-- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
-- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
-- downto UFix_low(11, 3, "+", 11, 3));
-- Where "11" is the width of xxx (xxx'length),
-- and 3 is the lower bound (abs (xxx'low))
-- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
function ufix_high (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return ufixed_high (left_index => width - 1 - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - 1 - fraction2,
right_index2 => -fraction2);
end function ufix_high;
function ufix_low (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return ufixed_low (left_index => width - 1 - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - 1 - fraction2,
right_index2 => -fraction2);
end function ufix_low;
function sfix_high (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return sfixed_high (left_index => width - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - fraction2,
right_index2 => -fraction2);
end function sfix_high;
function sfix_low (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return sfixed_low (left_index => width - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - fraction2,
right_index2 => -fraction2);
end function sfix_low;
function to_unsigned (
arg : UNRESOLVED_ufixed; -- ufixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNSIGNED is
begin
return to_uns(resize (arg => arg,
left_index => size-1,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
end function to_unsigned;
function to_unsigned (
arg : UNRESOLVED_ufixed; -- ufixed point input
size_res : UNSIGNED; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNSIGNED is
begin
return to_unsigned (arg => arg,
size => size_res'length,
round_style => round_style,
overflow_style => overflow_style);
end function to_unsigned;
function to_signed (
arg : UNRESOLVED_sfixed; -- sfixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return SIGNED is
begin
return to_s(resize (arg => arg,
left_index => size-1,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
end function to_signed;
function to_signed (
arg : UNRESOLVED_sfixed; -- sfixed point input
size_res : SIGNED; -- used for length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return SIGNED is
begin
return to_signed (arg => arg,
size => size_res'length,
round_style => round_style,
overflow_style => overflow_style);
end function to_signed;
function to_real (
arg : UNRESOLVED_ufixed) -- ufixed point input
return REAL is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable result : REAL; -- result
variable arg_int : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (arg'length < 1) then
return 0.0;
end if;
arg_int := to_x01(cleanvec(arg));
if (Is_X(arg_int)) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_REAL (ufixed): metavalue detected, returning 0.0"
severity warning;
return 0.0;
end if;
result := 0.0;
for i in arg_int'range loop
if (arg_int(i) = '1') then
result := result + (2.0**i);
end if;
end loop;
return result;
end function to_real;
function to_real (
arg : UNRESOLVED_sfixed) -- ufixed point input
return REAL is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable result : REAL; -- result
variable arg_int : UNRESOLVED_sfixed (left_index downto right_index);
-- unsigned version of argument
variable arg_uns : UNRESOLVED_ufixed (left_index downto right_index);
-- absolute of argument
begin
if (arg'length < 1) then
return 0.0;
end if;
arg_int := to_x01(cleanvec(arg));
if (Is_X(arg_int)) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_REAL (sfixed): metavalue detected, returning 0.0"
severity warning;
return 0.0;
end if;
arg_uns := to_ufixed (arg_int);
result := to_real (arg_uns);
if (arg_int(arg_int'high) = '1') then
result := -result;
end if;
return result;
end function to_real;
function to_integer (
arg : UNRESOLVED_ufixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return NATURAL is
constant left_index : INTEGER := arg'high;
variable arg_uns : UNSIGNED (left_index+1 downto 0)
:= (others => '0');
begin
if (arg'length < 1) then
return 0;
end if;
if (Is_X (arg)) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_INTEGER (ufixed): metavalue detected, returning 0"
severity warning;
return 0;
end if;
if (left_index < -1) then
return 0;
end if;
arg_uns := to_uns(resize (arg => arg,
left_index => arg_uns'high,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
return to_integer (arg_uns);
end function to_integer;
function to_integer (
arg : UNRESOLVED_sfixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return INTEGER is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable arg_s : SIGNED (left_index+1 downto 0);
begin
if (arg'length < 1) then
return 0;
end if;
if (Is_X (arg)) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_INTEGER (sfixed): metavalue detected, returning 0"
severity warning;
return 0;
end if;
if (left_index < -1) then
return 0;
end if;
arg_s := to_s(resize (arg => arg,
left_index => arg_s'high,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
return to_integer (arg_s);
end function to_integer;
function to_01 (
s : UNRESOLVED_ufixed; -- ufixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (s'range); -- result
begin
if (s'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_01(ufixed): null detected, returning NULL"
severity warning;
return NAUF;
end if;
return to_fixed (to_01(to_uns(s), XMAP), s'high, s'low);
end function to_01;
function to_01 (
s : UNRESOLVED_sfixed; -- sfixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (s'range);
begin
if (s'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_01(sfixed): null detected, returning NULL"
severity warning;
return NASF;
end if;
return to_fixed (to_01(to_s(s), XMAP), s'high, s'low);
end function to_01;
function Is_X (
arg : UNRESOLVED_ufixed)
return BOOLEAN is
variable argslv : STD_ULOGIC_VECTOR (arg'length-1 downto 0); -- slv
begin
argslv := to_sulv(arg);
return Is_X (argslv);
end function Is_X;
function Is_X (
arg : UNRESOLVED_sfixed)
return BOOLEAN is
variable argslv : STD_ULOGIC_VECTOR (arg'length-1 downto 0); -- slv
begin
argslv := to_sulv(arg);
return Is_X (argslv);
end function Is_X;
function To_X01 (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return to_ufixed (To_X01(to_sulv(arg)), arg'high, arg'low);
end function To_X01;
function to_X01 (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return to_sfixed (To_X01(to_sulv(arg)), arg'high, arg'low);
end function To_X01;
function To_X01Z (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return to_ufixed (To_X01Z(to_sulv(arg)), arg'high, arg'low);
end function To_X01Z;
function to_X01Z (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return to_sfixed (To_X01Z(to_sulv(arg)), arg'high, arg'low);
end function To_X01Z;
function To_UX01 (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return to_ufixed (To_UX01(to_sulv(arg)), arg'high, arg'low);
end function To_UX01;
function to_UX01 (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return to_sfixed (To_UX01(to_sulv(arg)), arg'high, arg'low);
end function To_UX01;
function resize (
arg : UNRESOLVED_ufixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant arghigh : INTEGER := maximum (arg'high, arg'low);
constant arglow : INTEGER := mine (arg'high, arg'low);
variable invec : UNRESOLVED_ufixed (arghigh downto arglow);
variable result : UNRESOLVED_ufixed(left_index downto right_index) :=
(others => '0');
variable needs_rounding : BOOLEAN := false;
begin -- resize
if (arg'length < 1) or (result'length < 1) then
return NAUF;
elsif (invec'length < 1) then
return result; -- string literal value
else
invec := cleanvec(arg);
if (right_index > arghigh) then -- return top zeros
needs_rounding := (round_style = fixed_round) and
(right_index = arghigh+1);
elsif (left_index < arglow) then -- return overflow
if (overflow_style = fixed_saturate) and
(or_reduce(to_sulv(invec)) = '1') then
result := saturate (result'high, result'low); -- saturate
end if;
elsif (arghigh > left_index) then
-- wrap or saturate?
if (overflow_style = fixed_saturate and
or_reduce (to_sulv(invec(arghigh downto left_index+1))) = '1')
then
result := saturate (result'high, result'low); -- saturate
else
if (arglow >= right_index) then
result (left_index downto arglow) :=
invec(left_index downto arglow);
else
result (left_index downto right_index) :=
invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
end if;
else -- arghigh <= integer width
if (arglow >= right_index) then
result (arghigh downto arglow) := invec;
else
result (arghigh downto right_index) :=
invec (arghigh downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
end if;
-- Round result
if needs_rounding then
result := round_fixed (arg => result,
remainder => invec (right_index-1
downto arglow),
overflow_style => overflow_style);
end if;
return result;
end if;
end function resize;
function resize (
arg : UNRESOLVED_sfixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant arghigh : INTEGER := maximum (arg'high, arg'low);
constant arglow : INTEGER := mine (arg'high, arg'low);
variable invec : UNRESOLVED_sfixed (arghigh downto arglow);
variable result : UNRESOLVED_sfixed(left_index downto right_index) :=
(others => '0');
variable reduced : STD_ULOGIC;
variable needs_rounding : BOOLEAN := false; -- rounding
begin -- resize
if (arg'length < 1) or (result'length < 1) then
return NASF;
elsif (invec'length < 1) then
return result; -- string literal value
else
invec := cleanvec(arg);
if (right_index > arghigh) then -- return top zeros
if (arg'low /= INTEGER'low) then -- check for a literal
result := (others => arg(arghigh)); -- sign extend
end if;
needs_rounding := (round_style = fixed_round) and
(right_index = arghigh+1);
elsif (left_index < arglow) then -- return overflow
if (overflow_style = fixed_saturate) then
reduced := or_reduce (to_sulv(invec));
if (reduced = '1') then
if (invec(arghigh) = '0') then
-- saturate POSITIVE
result := saturate (result'high, result'low);
else
-- saturate negative
result := not saturate (result'high, result'low);
end if;
-- else return 0 (input was 0)
end if;
-- else return 0 (wrap)
end if;
elsif (arghigh > left_index) then
if (invec(arghigh) = '0') then
reduced := or_reduce (to_sulv(invec(arghigh-1 downto
left_index)));
if overflow_style = fixed_saturate and reduced = '1' then
-- saturate positive
result := saturate (result'high, result'low);
else
if (right_index > arglow) then
result := invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round);
else
result (left_index downto arglow) :=
invec (left_index downto arglow);
end if;
end if;
else
reduced := and_reduce (to_sulv(invec(arghigh-1 downto
left_index)));
if overflow_style = fixed_saturate and reduced = '0' then
result := not saturate (result'high, result'low);
else
if (right_index > arglow) then
result := invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round);
else
result (left_index downto arglow) :=
invec (left_index downto arglow);
end if;
end if;
end if;
else -- arghigh <= integer width
if (arglow >= right_index) then
result (arghigh downto arglow) := invec;
else
result (arghigh downto right_index) :=
invec (arghigh downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
if (left_index > arghigh) then -- sign extend
result(left_index downto arghigh+1) := (others => invec(arghigh));
end if;
end if;
-- Round result
if (needs_rounding) then
result := round_fixed (arg => result,
remainder => invec (right_index-1
downto arglow),
overflow_style => overflow_style);
end if;
return result;
end if;
end function resize;
-- size_res functions
-- These functions compute the size from a passed variable named "size_res"
-- The only part of this variable used it it's size, it is never passed
-- to a lower level routine.
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : NATURAL; -- integer
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : INTEGER; -- integer
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : REAL; -- real
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
guard_bits => guard_bits,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : REAL; -- real
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
guard_bits => guard_bits,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : SIGNED; -- signed
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function resize (
arg : UNRESOLVED_ufixed; -- input
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'high downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NAUF;
else
result := resize (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function resize;
function resize (
arg : UNRESOLVED_sfixed; -- input
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'high downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NASF;
else
result := resize (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function resize;
-- Overloaded math functions for real
function "+" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l + to_ufixed (r, l'high, l'low));
end function "+";
function "+" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) + r);
end function "+";
function "+" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l + to_sfixed (r, l'high, l'low));
end function "+";
function "+" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) + r);
end function "+";
function "-" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l - to_ufixed (r, l'high, l'low));
end function "-";
function "-" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) - r);
end function "-";
function "-" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l - to_sfixed (r, l'high, l'low));
end function "-";
function "-" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) - r);
end function "-";
function "*" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l * to_ufixed (r, l'high, l'low));
end function "*";
function "*" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) * r);
end function "*";
function "*" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l * to_sfixed (r, l'high, l'low));
end function "*";
function "*" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) * r);
end function "*";
function "/" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l / to_ufixed (r, l'high, l'low));
end function "/";
function "/" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) / r);
end function "/";
function "/" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l / to_sfixed (r, l'high, l'low));
end function "/";
function "/" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) / r);
end function "/";
function "rem" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l rem to_ufixed (r, l'high, l'low));
end function "rem";
function "rem" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) rem r);
end function "rem";
function "rem" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l rem to_sfixed (r, l'high, l'low));
end function "rem";
function "rem" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) rem r);
end function "rem";
function "mod" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l mod to_ufixed (r, l'high, l'low));
end function "mod";
function "mod" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) mod r);
end function "mod";
function "mod" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l mod to_sfixed (r, l'high, l'low));
end function "mod";
function "mod" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) mod r);
end function "mod";
-- Overloaded math functions for integers
function "+" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l + to_ufixed (r, l'high, 0));
end function "+";
function "+" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) + r);
end function "+";
function "+" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l + to_sfixed (r, l'high, 0));
end function "+";
function "+" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) + r);
end function "+";
-- Overloaded functions
function "-" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l - to_ufixed (r, l'high, 0));
end function "-";
function "-" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) - r);
end function "-";
function "-" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l - to_sfixed (r, l'high, 0));
end function "-";
function "-" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) - r);
end function "-";
-- Overloaded functions
function "*" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l * to_ufixed (r, l'high, 0));
end function "*";
function "*" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) * r);
end function "*";
function "*" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l * to_sfixed (r, l'high, 0));
end function "*";
function "*" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) * r);
end function "*";
-- Overloaded functions
function "/" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l / to_ufixed (r, l'high, 0));
end function "/";
function "/" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) / r);
end function "/";
function "/" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l / to_sfixed (r, l'high, 0));
end function "/";
function "/" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) / r);
end function "/";
function "rem" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l rem to_ufixed (r, l'high, 0));
end function "rem";
function "rem" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) rem r);
end function "rem";
function "rem" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l rem to_sfixed (r, l'high, 0));
end function "rem";
function "rem" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) rem r);
end function "rem";
function "mod" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l mod to_ufixed (r, l'high, 0));
end function "mod";
function "mod" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) mod r);
end function "mod";
function "mod" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l mod to_sfixed (r, l'high, 0));
end function "mod";
function "mod" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) mod r);
end function "mod";
-- overloaded ufixed compare functions with integer
function "=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l = to_ufixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l /= to_ufixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l >= to_ufixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l <= to_ufixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l > to_ufixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l < to_ufixed (r, l'high, l'low));
end function "<";
function \?=\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (l, to_ufixed (r, l'high, l'low));
end function \?=\;
function \?/=\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (l, to_ufixed (r, l'high, l'low));
end function \?/=\;
function \?>=\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (l, to_ufixed (r, l'high, l'low));
end function \?>=\;
function \?<=\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (l, to_ufixed (r, l'high, l'low));
end function \?<=\;
function \?>\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (l, to_ufixed (r, l'high, l'low));
end function \?>\;
function \?<\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (l, to_ufixed (r, l'high, l'low));
end function \?<\;
function maximum (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return maximum (l, to_ufixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return minimum (l, to_ufixed (r, l'high, l'low));
end function minimum;
-- NATURAL to ufixed
function "=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) < r);
end function "<";
function \?=\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (to_ufixed (l, r'high, r'low), r);
end function \?=\;
function \?/=\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (to_ufixed (l, r'high, r'low), r);
end function \?/=\;
function \?>=\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (to_ufixed (l, r'high, r'low), r);
end function \?>=\;
function \?<=\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (to_ufixed (l, r'high, r'low), r);
end function \?<=\;
function \?>\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (to_ufixed (l, r'high, r'low), r);
end function \?>\;
function \?<\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (to_ufixed (l, r'high, r'low), r);
end function \?<\;
function maximum (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return maximum (to_ufixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return minimum (to_ufixed (l, r'high, r'low), r);
end function minimum;
-- overloaded ufixed compare functions with real
function "=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l = to_ufixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l /= to_ufixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l >= to_ufixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l <= to_ufixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l > to_ufixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l < to_ufixed (r, l'high, l'low));
end function "<";
function \?=\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?=\ (l, to_ufixed (r, l'high, l'low));
end function \?=\;
function \?/=\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?/=\ (l, to_ufixed (r, l'high, l'low));
end function \?/=\;
function \?>=\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?>=\ (l, to_ufixed (r, l'high, l'low));
end function \?>=\;
function \?<=\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?<=\ (l, to_ufixed (r, l'high, l'low));
end function \?<=\;
function \?>\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?>\ (l, to_ufixed (r, l'high, l'low));
end function \?>\;
function \?<\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?<\ (l, to_ufixed (r, l'high, l'low));
end function \?<\;
function maximum (
l : UNRESOLVED_ufixed;
r : REAL)
return UNRESOLVED_ufixed is
begin
return maximum (l, to_ufixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_ufixed;
r : REAL)
return UNRESOLVED_ufixed is
begin
return minimum (l, to_ufixed (r, l'high, l'low));
end function minimum;
-- real and ufixed
function "=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) < r);
end function "<";
function \?=\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (to_ufixed (l, r'high, r'low), r);
end function \?=\;
function \?/=\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (to_ufixed (l, r'high, r'low), r);
end function \?/=\;
function \?>=\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (to_ufixed (l, r'high, r'low), r);
end function \?>=\;
function \?<=\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (to_ufixed (l, r'high, r'low), r);
end function \?<=\;
function \?>\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (to_ufixed (l, r'high, r'low), r);
end function \?>\;
function \?<\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (to_ufixed (l, r'high, r'low), r);
end function \?<\;
function maximum (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return maximum (to_ufixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return minimum (to_ufixed (l, r'high, r'low), r);
end function minimum;
-- overloaded sfixed compare functions with integer
function "=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l = to_sfixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l /= to_sfixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l >= to_sfixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l <= to_sfixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l > to_sfixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l < to_sfixed (r, l'high, l'low));
end function "<";
function \?=\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?=\ (l, to_sfixed (r, l'high, l'low));
end function \?=\;
function \?/=\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?/=\ (l, to_sfixed (r, l'high, l'low));
end function \?/=\;
function \?>=\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?>=\ (l, to_sfixed (r, l'high, l'low));
end function \?>=\;
function \?<=\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?<=\ (l, to_sfixed (r, l'high, l'low));
end function \?<=\;
function \?>\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?>\ (l, to_sfixed (r, l'high, l'low));
end function \?>\;
function \?<\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?<\ (l, to_sfixed (r, l'high, l'low));
end function \?<\;
function maximum (
l : UNRESOLVED_sfixed;
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return maximum (l, to_sfixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_sfixed;
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return minimum (l, to_sfixed (r, l'high, l'low));
end function minimum;
-- integer and sfixed
function "=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) < r);
end function "<";
function \?=\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (to_sfixed (l, r'high, r'low), r);
end function \?=\;
function \?/=\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (to_sfixed (l, r'high, r'low), r);
end function \?/=\;
function \?>=\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (to_sfixed (l, r'high, r'low), r);
end function \?>=\;
function \?<=\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (to_sfixed (l, r'high, r'low), r);
end function \?<=\;
function \?>\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (to_sfixed (l, r'high, r'low), r);
end function \?>\;
function \?<\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (to_sfixed (l, r'high, r'low), r);
end function \?<\;
function maximum (
l : INTEGER;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return maximum (to_sfixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : INTEGER;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return minimum (to_sfixed (l, r'high, r'low), r);
end function minimum;
-- overloaded sfixed compare functions with real
function "=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l = to_sfixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l /= to_sfixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l >= to_sfixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l <= to_sfixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l > to_sfixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l < to_sfixed (r, l'high, l'low));
end function "<";
function \?=\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?=\ (l, to_sfixed (r, l'high, l'low));
end function \?=\;
function \?/=\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?/=\ (l, to_sfixed (r, l'high, l'low));
end function \?/=\;
function \?>=\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?>=\ (l, to_sfixed (r, l'high, l'low));
end function \?>=\;
function \?<=\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?<=\ (l, to_sfixed (r, l'high, l'low));
end function \?<=\;
function \?>\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?>\ (l, to_sfixed (r, l'high, l'low));
end function \?>\;
function \?<\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?<\ (l, to_sfixed (r, l'high, l'low));
end function \?<\;
function maximum (
l : UNRESOLVED_sfixed;
r : REAL)
return UNRESOLVED_sfixed is
begin
return maximum (l, to_sfixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_sfixed;
r : REAL)
return UNRESOLVED_sfixed is
begin
return minimum (l, to_sfixed (r, l'high, l'low));
end function minimum;
-- REAL and sfixed
function "=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) < r);
end function "<";
function \?=\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (to_sfixed (l, r'high, r'low), r);
end function \?=\;
function \?/=\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (to_sfixed (l, r'high, r'low), r);
end function \?/=\;
function \?>=\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (to_sfixed (l, r'high, r'low), r);
end function \?>=\;
function \?<=\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (to_sfixed (l, r'high, r'low), r);
end function \?<=\;
function \?>\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (to_sfixed (l, r'high, r'low), r);
end function \?>\;
function \?<\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (to_sfixed (l, r'high, r'low), r);
end function \?<\;
function maximum (
l : REAL;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return maximum (to_sfixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : REAL;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return minimum (to_sfixed (l, r'high, r'low), r);
end function minimum;
-- rtl_synthesis off
-- pragma synthesis_off
-- copied from std_logic_textio
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant NUS : STRING(2 to 1) := (others => ' ');
-- %%% Replicated Textio functions
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report fixed_pkg'instance_name
& "OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
result := "UUU";
good := false;
end case;
end procedure Char2TriBits;
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report fixed_pkg'instance_name
& "HREAD Error: Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
result := "UUUU";
good := false;
end case;
end procedure Char2QuadBits;
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
function to_ostring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_ULOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
-------------------------------------------------------------------
function to_hstring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_ULOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
-- %%% END replicated textio functions
-- purpose: writes fixed point into a line
procedure write (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'length +1) := (others => ' ');
variable sindx : INTEGER;
begin -- function write Example: 0011.1100
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
write(l, s, justified, field);
end procedure write;
-- purpose: writes fixed point into a line
procedure write (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'length +1);
variable sindx : INTEGER;
begin -- function write Example: 0011.1100
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
write(l, s, justified, field);
end procedure write;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable i : INTEGER; -- index variable
variable mv : ufixed (VALUE'range);
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a "."
begin -- READ
VALUE := (VALUE'range => 'U');
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := value'high;
while i >= VALUE'low loop
if readOk = false then -- Bail out if there was a bad read
report fixed_pkg'instance_name & "READ(ufixed) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = value'high then
report fixed_pkg'instance_name & "READ(ufixed) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report fixed_pkg'instance_name & "READ(ufixed) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = '.' then -- binary point
if founddot then
report fixed_pkg'instance_name & "READ(ufixed) "
& "Two binary points found in input string" severity error;
return;
elsif i /= -1 then -- Seperator in the wrong spot
report fixed_pkg'instance_name & "READ(ufixed) "
& "Decimal point does not match number format "
severity error;
return;
end if;
founddot := true;
lastu := false;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
report fixed_pkg'instance_name & "READ(ufixed) "
& "Short read, Space encounted in input string"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report fixed_pkg'instance_name & "READ(ufixed) "
& "Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i - 1;
if i < mv'low then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable mv : ufixed (VALUE'range);
variable i : INTEGER; -- index variable
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a "."
begin -- READ
VALUE := (VALUE'range => 'U');
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, readOk);
i := value'high;
GOOD := false;
while i >= VALUE'low loop
if not readOk then -- Bail out if there was a bad read
return;
elsif c = '_' then
if i = value'high then -- Begins with an "_"
return;
elsif lastu then -- "__" detected
return;
else
lastu := true;
end if;
elsif c = '.' then -- binary point
if founddot then
return;
elsif i /= -1 then -- Seperator in the wrong spot
return;
end if;
founddot := true;
lastu := false;
elsif (char_to_MVL9plus(c) = error) then -- Illegal character/short read
return;
else
mv(i) := char_to_MVL9(c);
i := i - 1;
if i < mv'low then -- reading done
GOOD := true;
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
else
GOOD := true; -- read into a null array
end if;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable i : INTEGER; -- index variable
variable mv : sfixed (VALUE'range);
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a "."
begin -- READ
VALUE := (VALUE'range => 'U');
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := value'high;
while i >= VALUE'low loop
if readOk = false then -- Bail out if there was a bad read
report fixed_pkg'instance_name & "READ(sfixed) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = value'high then
report fixed_pkg'instance_name & "READ(sfixed) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report fixed_pkg'instance_name & "READ(sfixed) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = '.' then -- binary point
if founddot then
report fixed_pkg'instance_name & "READ(sfixed) "
& "Two binary points found in input string" severity error;
return;
elsif i /= -1 then -- Seperator in the wrong spot
report fixed_pkg'instance_name & "READ(sfixed) "
& "Decimal point does not match number format "
severity error;
return;
end if;
founddot := true;
lastu := false;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
report fixed_pkg'instance_name & "READ(sfixed) "
& "Short read, Space encounted in input string"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report fixed_pkg'instance_name & "READ(sfixed) "
& "Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i - 1;
if i < mv'low then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN) is
variable value_ufixed : UNRESOLVED_ufixed (VALUE'range);
begin -- READ
READ (L => L, VALUE => value_ufixed, GOOD => GOOD);
VALUE := UNRESOLVED_sfixed (value_ufixed);
end procedure READ;
-- octal read and write
procedure owrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_ostring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure owrite;
procedure owrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_ostring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure owrite;
-- purpose: Routines common to the OREAD routines
procedure OREAD_common (
L : inout LINE;
slv : out STD_ULOGIC_VECTOR;
igood : out BOOLEAN;
idex : out INTEGER;
constant bpoint : in INTEGER; -- binary point
constant message : in BOOLEAN;
constant smath : in BOOLEAN) is
-- purpose: error message routine
procedure errmes (
constant mess : in STRING) is -- error message
begin
if message then
if smath then
report fixed_pkg'instance_name
& "OREAD(sfixed) "
& mess
severity error;
else
report fixed_pkg'instance_name
& "OREAD(ufixed) "
& mess
severity error;
end if;
end if;
end procedure errmes;
variable xgood : BOOLEAN;
variable nybble : STD_ULOGIC_VECTOR (2 downto 0); -- 3 bits
variable c : CHARACTER;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a dot.
begin
Skip_whitespace (L);
if slv'length > 0 then
i := slv'high;
read (l, c, xgood);
while i > 0 loop
if xgood = false then
errmes ("Error: end of string encountered");
exit;
elsif c = '_' then
if i = slv'length then
errmes ("Error: String begins with an ""_""");
xgood := false;
exit;
elsif lastu then
errmes ("Error: Two underscores detected in input string ""__""");
xgood := false;
exit;
else
lastu := true;
end if;
elsif (c = '.') then
if (i + 1 /= bpoint) then
errmes ("encountered ""."" at wrong index");
xgood := false;
exit;
elsif i = slv'length then
errmes ("encounted a ""."" at the beginning of the line");
xgood := false;
exit;
elsif founddot then
errmes ("Two ""."" encounted in input string");
xgood := false;
exit;
end if;
founddot := true;
lastu := false;
else
Char2triBits(c, nybble, xgood, message);
if not xgood then
exit;
end if;
slv (i downto i-2) := nybble;
i := i - 3;
lastu := false;
end if;
if i > 0 then
read (L, c, xgood);
end if;
end loop;
idex := i;
igood := xgood;
else
igood := true; -- read into a null array
idex := -1;
end if;
end procedure OREAD_common;
-- Note that for Octal and Hex read, you can not start with a ".",
-- the read is for numbers formatted "A.BC". These routines go to
-- the nearest bounds, so "F.E" will fit into an sfixed (2 downto -3).
procedure OREAD (L : inout LINE;
VALUE : out UNRESOLVED_ufixed) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => true,
smath => false);
if igood then -- We did not get another error
if not ((i = -1) and -- We read everything, and high bits 0
(or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
report fixed_pkg'instance_name
& "OREAD(ufixed): Vector truncated."
severity error;
else
if (or_reduce (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report fixed_pkg'instance_name
& "OREAD(ufixed): Vector truncated"
severity warning;
end if;
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => false);
if (igood and -- We did not get another error
(i = -1) and -- We read everything, and high bits 0
(or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => true,
smath => true);
if igood then -- We did not get another error
if not ((i = -1) and -- We read everything
((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
report fixed_pkg'instance_name
& "OREAD(sfixed): Vector truncated."
severity error;
else
if (or_reduce (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report fixed_pkg'instance_name
& "OREAD(sfixed): Vector truncated"
severity warning;
end if;
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => true);
if (igood -- We did not get another error
and (i = -1) -- We read everything
and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure OREAD;
-- hex read and write
procedure hwrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_hstring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure hwrite;
-- purpose: writes fixed point into a line
procedure hwrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_hstring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure hwrite;
-- purpose: Routines common to the OREAD routines
procedure HREAD_common (
L : inout LINE;
slv : out STD_ULOGIC_VECTOR;
igood : out BOOLEAN;
idex : out INTEGER;
constant bpoint : in INTEGER; -- binary point
constant message : in BOOLEAN;
constant smath : in BOOLEAN) is
-- purpose: error message routine
procedure errmes (
constant mess : in STRING) is -- error message
begin
if message then
if smath then
report fixed_pkg'instance_name
& "HREAD(sfixed) "
& mess
severity error;
else
report fixed_pkg'instance_name
& "HREAD(ufixed) "
& mess
severity error;
end if;
end if;
end procedure errmes;
variable xgood : BOOLEAN;
variable nybble : STD_ULOGIC_VECTOR (3 downto 0); -- 4 bits
variable c : CHARACTER;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a dot.
begin
Skip_whitespace (L);
if slv'length > 0 then
i := slv'high;
read (l, c, xgood);
while i > 0 loop
if xgood = false then
errmes ("Error: end of string encountered");
exit;
elsif c = '_' then
if i = slv'length then
errmes ("Error: String begins with an ""_""");
xgood := false;
exit;
elsif lastu then
errmes ("Error: Two underscores detected in input string ""__""");
xgood := false;
exit;
else
lastu := true;
end if;
elsif (c = '.') then
if (i + 1 /= bpoint) then
errmes ("encountered ""."" at wrong index");
xgood := false;
exit;
elsif i = slv'length then
errmes ("encounted a ""."" at the beginning of the line");
xgood := false;
exit;
elsif founddot then
errmes ("Two ""."" encounted in input string");
xgood := false;
exit;
end if;
founddot := true;
lastu := false;
else
Char2QuadBits(c, nybble, xgood, message);
if not xgood then
exit;
end if;
slv (i downto i-3) := nybble;
i := i - 4;
lastu := false;
end if;
if i > 0 then
read (L, c, xgood);
end if;
end loop;
idex := i;
igood := xgood;
else
idex := -1;
igood := true; -- read null string
end if;
end procedure HREAD_common;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => false);
if igood then
if not ((i = -1) and -- We read everything, and high bits 0
(or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
report fixed_pkg'instance_name
& "HREAD(ufixed): Vector truncated."
severity error;
else
if (or_reduce (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report fixed_pkg'instance_name
& "HREAD(ufixed): Vector truncated"
severity warning;
end if;
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => false);
if (igood and -- We did not get another error
(i = -1) and -- We read everything, and high bits 0
(or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => true,
smath => true);
if igood then -- We did not get another error
if not ((i = -1) -- We read everything
and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
report fixed_pkg'instance_name
& "HREAD(sfixed): Vector truncated."
severity error;
else
if (or_reduce (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report fixed_pkg'instance_name
& "HREAD(sfixed): Vector truncated"
severity warning;
end if;
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => true);
if (igood and -- We did not get another error
(i = -1) and -- We read everything
((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure HREAD;
function to_string (value : UNRESOLVED_ufixed) return STRING is
variable s : STRING(1 to value'length +1) := (others => ' ');
variable subval : UNRESOLVED_ufixed (value'high downto -1);
variable sindx : INTEGER;
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
if value(value'high) = 'Z' then
return to_string (resize (sfixed(value), 0, value'low));
else
return to_string (resize (value, 0, value'low));
end if;
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_string(subval);
else
return to_string (resize (value, value'high, -1));
end if;
else
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
return s;
end if;
end if;
end function to_string;
function to_string (value : UNRESOLVED_sfixed) return STRING is
variable s : STRING(1 to value'length + 1) := (others => ' ');
variable subval : UNRESOLVED_sfixed (value'high downto -1);
variable sindx : INTEGER;
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_string (resize (value, 0, value'low));
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_string(subval);
else
return to_string (resize (value, value'high, -1));
end if;
else
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
return s;
end if;
end if;
end function to_string;
function to_ostring (value : UNRESOLVED_ufixed) return STRING is
constant lne : INTEGER := (-VALUE'low+2)/3;
variable subval : UNRESOLVED_ufixed (value'high downto -3);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
if value(value'high) = 'Z' then
return to_ostring (resize (sfixed(value), 2, value'low));
else
return to_ostring (resize (value, 2, value'low));
end if;
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_ostring(subval);
else
return to_ostring (resize (value, value'high, -3));
end if;
else
slv := to_sulv (value);
if Is_X (value (value'low)) then
lpad := (others => value (value'low));
else
lpad := (others => '0');
end if;
return to_ostring(slv(slv'high downto slv'high-VALUE'high))
& "."
& to_ostring(slv(slv'high-VALUE'high-1 downto 0) & lpad);
end if;
end if;
end function to_ostring;
function to_hstring (value : UNRESOLVED_ufixed) return STRING is
constant lne : INTEGER := (-VALUE'low+3)/4;
variable subval : UNRESOLVED_ufixed (value'high downto -4);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
if value(value'high) = 'Z' then
return to_hstring (resize (sfixed(value), 3, value'low));
else
return to_hstring (resize (value, 3, value'low));
end if;
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_hstring(subval);
else
return to_hstring (resize (value, value'high, -4));
end if;
else
slv := to_sulv (value);
if Is_X (value (value'low)) then
lpad := (others => value(value'low));
else
lpad := (others => '0');
end if;
return to_hstring(slv(slv'high downto slv'high-VALUE'high))
& "."
& to_hstring(slv(slv'high-VALUE'high-1 downto 0)&lpad);
end if;
end if;
end function to_hstring;
function to_ostring (value : UNRESOLVED_sfixed) return STRING is
constant ne : INTEGER := ((value'high+1)+2)/3;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - (value'high+1)) - 1);
constant lne : INTEGER := (-VALUE'low+2)/3;
variable subval : UNRESOLVED_sfixed (value'high downto -3);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (VALUE'high - VALUE'low downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_ostring (resize (value, 2, value'low));
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_ostring(subval);
else
return to_ostring (resize (value, value'high, -3));
end if;
else
pad := (others => value(value'high));
slv := to_sulv (value);
if Is_X (value (value'low)) then
lpad := (others => value(value'low));
else
lpad := (others => '0');
end if;
return to_ostring(pad & slv(slv'high downto slv'high-VALUE'high))
& "."
& to_ostring(slv(slv'high-VALUE'high-1 downto 0) & lpad);
end if;
end if;
end function to_ostring;
function to_hstring (value : UNRESOLVED_sfixed) return STRING is
constant ne : INTEGER := ((value'high+1)+3)/4;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - (value'high+1)) - 1);
constant lne : INTEGER := (-VALUE'low+3)/4;
variable subval : UNRESOLVED_sfixed (value'high downto -4);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_hstring (resize (value, 3, value'low));
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_hstring(subval);
else
return to_hstring (resize (value, value'high, -4));
end if;
else
slv := to_sulv (value);
pad := (others => value(value'high));
if Is_X (value (value'low)) then
lpad := (others => value(value'low));
else
lpad := (others => '0');
end if;
return to_hstring(pad & slv(slv'high downto slv'high-VALUE'high))
& "."
& to_hstring(slv(slv'high-VALUE'high-1 downto 0) & lpad);
end if;
end if;
end function to_hstring;
-- From string functions allow you to convert a string into a fixed
-- point number. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
-- The "." is optional in this syntax, however it exist and is
-- in the wrong location an error is produced. Overflow will
-- result in saturation.
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_string: Bad string "& bstring severity error;
return result;
end function from_string;
-- Octal and hex conversions work as follows:
-- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
-- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_string: Bad string "& bstring severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
-- Same as above, "size_res" is used for it's range only.
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return from_string (bstring, size_res'high, size_res'low);
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return from_ostring (ostring, size_res'high, size_res'low);
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return from_hstring(hstring, size_res'high, size_res'low);
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return from_string (bstring, size_res'high, size_res'low);
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return from_ostring (ostring, size_res'high, size_res'low);
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return from_hstring (hstring, size_res'high, size_res'low);
end function from_hstring;
-- purpose: Calculate the string boundaries
procedure calculate_string_boundry (
arg : in STRING; -- input string
left_index : out INTEGER; -- left
right_index : out INTEGER) is -- right
-- examples "10001.111" would return +4, -3
-- "07X.44" would return +2, -2 (then the octal routine would multiply)
-- "A_B_._C" would return +1, -1 (then the hex routine would multiply)
alias xarg : STRING (arg'length downto 1) is arg; -- make it downto range
variable l, r : INTEGER; -- internal indexes
variable founddot : BOOLEAN := false;
begin
if arg'length > 0 then
l := xarg'high - 1;
r := 0;
for i in xarg'range loop
if xarg(i) = '_' then
if r = 0 then
l := l - 1;
else
r := r + 1;
end if;
elsif xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT then
report fixed_pkg'instance_name
& "Found a space in the input STRING " & xarg
severity error;
elsif xarg(i) = '.' then
if founddot then
report fixed_pkg'instance_name
& "Found two binary points in input string " & xarg
severity error;
else
l := l - i;
r := -i + 1;
founddot := true;
end if;
end if;
end loop;
left_index := l;
right_index := r;
else
left_index := 0;
right_index := 0;
end if;
end procedure calculate_string_boundry;
-- Direct conversion functions. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100"); -- 6.5
-- In this case the "." is not optional, and the size of
-- the output must match exactly.
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_ufixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (bstring, left_index, right_index);
return from_string (bstring, left_index, right_index);
end function from_string;
-- Direct octal and hex conversion functions. In this case
-- the string lengths must match. Example:
-- signal sf1 := sfixed (5 downto -3);
-- sf1 <= from_ostring ("71.4") -- -6.5
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_ufixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (ostring, left_index, right_index);
return from_ostring (ostring, ((left_index+1)*3)-1, right_index*3);
end function from_ostring;
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_ufixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (hstring, left_index, right_index);
return from_hstring (hstring, ((left_index+1)*4)-1, right_index*4);
end function from_hstring;
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_sfixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (bstring, left_index, right_index);
return from_string (bstring, left_index, right_index);
end function from_string;
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_sfixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (ostring, left_index, right_index);
return from_ostring (ostring, ((left_index+1)*3)-1, right_index*3);
end function from_ostring;
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_sfixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (hstring, left_index, right_index);
return from_hstring (hstring, ((left_index+1)*4)-1, right_index*4);
end function from_hstring;
-- pragma synthesis_on
-- rtl_synthesis on
-- IN VHDL-2006 std_logic_vector is a subtype of std_ulogic_vector, so these
-- extra functions are needed for compatability.
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
begin
return to_ufixed (
arg => to_stdulogicvector (arg),
left_index => left_index,
right_index => right_index);
end function to_ufixed;
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed is
begin
return to_ufixed (
arg => to_stdulogicvector (arg),
size_res => size_res);
end function to_ufixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
begin
return to_sfixed (
arg => to_stdulogicvector (arg),
left_index => left_index,
right_index => right_index);
end function to_sfixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed is
begin
return to_sfixed (
arg => to_stdulogicvector (arg),
size_res => size_res);
end function to_sfixed;
-- unsigned fixed point
function to_UFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed is
begin
return to_UFix (
arg => to_stdulogicvector (arg),
width => width,
fraction => fraction);
end function to_UFix;
-- signed fixed point
function to_SFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed is
begin
return to_SFix (
arg => to_stdulogicvector (arg),
width => width,
fraction => fraction);
end function to_SFix;
end package body fixed_pkg;
| apache-2.0 | ef711cf72ad8abbdbcef7569eaef4685 | 0.569273 | 3.985131 | false | false | false | false |
JeremySavonet/Eurobot-2017-Moon-Village | software/HPS_FPGA_LED/fpga/HPSFPGA.vhd | 1 | 38,578 | --=================================
-- Hello world
-- Author: J.Savonet
--=================================
--`define ENABLE_HPS
----`define ENABLE_CLK
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.types_pkg.all;
use work.robot_layer_1_pkg.all;
use work.robot_layer_2_pkg.all;
use work.robot_layer_3_pkg.all;
entity hpsfpga is
port (
----------/ ADC --------/
ADC_CONVST : out std_logic;
ADC_SCK : out std_logic;
ADC_SDI : out std_logic;
ADC_SDO : in std_logic;
----------/ ARDUINO --------/
--ARDUINO_IO : inout std_logic_vector(16-1 downto 0);
--ARDUINO_RESET_N : inout std_logic;
--`ifdef ENABLE_CLK
-- --------/ CLK --------/
-- out : CLK_I2C_SCL,
-- inout : CLK_I2C_SDA,
--`endif /*ENABLE_CLK*/
----------/ FPGA --------/
FPGA_CLK1_50 : in std_logic;
FPGA_CLK2_50 : in std_logic;
FPGA_CLK3_50 : in std_logic;
----------/ GPIO --------/
--GPIO_0 : inout std_logic_vector(36-1 downto 0);
--GPIO_1 : inout std_logic_vector(36-1 downto 0);
----------- ADC (//) ---------
ad0_sclk : out std_logic;
ad0_miso : in std_logic;
ad0_drdy : in std_logic;
ad0_sync : out std_logic;
ad0_clk : out std_logic;
--------- ADC (muxed) --------
ad1_sclk : out std_logic;
ad1_mosi : out std_logic;
ad1_miso : in std_logic;
ad1_ss : out std_logic;
ad1_drdy : in std_logic;
ad1_rst : out std_logic;
---------- H BRIDGE ----------
m0_pwma : out std_logic;
m0_pwmb : out std_logic;
m01_fault: in std_logic; --m01_fault
m1_pwma : out std_logic;
m1_pwmb : out std_logic;
m01_resetn: out std_logic; --m01_resetn
m2_pwma : out std_logic;
m2_pwmb : out std_logic;
m3_pwma : out std_logic;
m3_pwmb : out std_logic;
m2345_fault: in std_logic; --m2345_fault
m4_pwma : out std_logic;
m4_pwmb : out std_logic;
m5_pwma : out std_logic;
m5_pwmb : out std_logic;
m2345_resetn: out std_logic; --m2345_resetn
---------- QEI ----------
qei0_a : in std_logic;
qei0_b : in std_logic;
qei1_a : in std_logic;
qei1_b : in std_logic;
qei2_a : in std_logic;
qei2_b : in std_logic;
qei2_z : in std_logic;
qei3_a : in std_logic;
qei3_b : in std_logic;
qei3_z : in std_logic;
---------- ESC ----------
esc0_pwm : out std_logic;
esc0_dir : out std_logic;
esc1_pwm : out std_logic;
esc1_dir : out std_logic;
------- PWM (Servos) ------
s : out std_logic_vector(8-1 downto 0);
--------- IOs ----------
io_0 : inout std_logic;
io_1 : inout std_logic;
io_2 : inout std_logic;
io_3 : inout std_logic;
io_4 : inout std_logic;
io_5 : inout std_logic;
io_6 : inout std_logic;
io_7 : inout std_logic;
--------- UART ----------
uart0_rx : in std_logic;
uart0_tx : out std_logic;
uart1_rx : in std_logic;
uart1_tx : out std_logic;
uart2_rx : in std_logic;
uart2_tx : out std_logic;
uart2_custom : out std_logic;
uart3_rx : in std_logic;
uart3_tx : out std_logic;
uart3_custom : out std_logic;
--------- I2C ----------
i2c0_scl : inout std_logic;
i2c0_sda : inout std_logic;
i2c0_reset : out std_logic;
i2c1_scl : inout std_logic;
i2c1_sda : inout std_logic;
i2c1_reset : out std_logic;
--------- SPI ----------
spi0_sclk : in std_logic;
spi0_mosi : in std_logic;
spi0_miso : in std_logic;
spi0_ss : in std_logic;
spi1_sclk : out std_logic;
spi1_mosi : out std_logic;
spi1_miso : in std_logic;
spi1_ss : out std_logic;
--! Use SPI1
imu_ss : out std_logic;
imu_drdy : in std_logic;
imu_fsync : in std_logic;
---------- LED -----------
led_green : out std_logic;
led_red : out std_logic;
--------- MGMT -----------
lv_mux : out std_logic_vector(2-1 downto 0);
buzzer : out std_logic;
--`ifdef ENABLE_HPS
----------/ HPS --------/
HPS_CONV_USB_N : inout std_logic;
HPS_DDR3_ADDR : out std_logic_vector(15-1 downto 0);
HPS_DDR3_BA : out std_logic_vector(3-1 downto 0);
HPS_DDR3_CAS_N : out std_logic;
HPS_DDR3_CKE : out std_logic;
HPS_DDR3_CK_N : out std_logic;
HPS_DDR3_CK_P : out std_logic;
HPS_DDR3_CS_N : out std_logic;
HPS_DDR3_DM : out std_logic_vector(4-1 downto 0);
HPS_DDR3_DQ : inout std_logic_vector(32-1 downto 0);
HPS_DDR3_DQS_N : inout std_logic_vector(4-1 downto 0);
HPS_DDR3_DQS_P : inout std_logic_vector(4-1 downto 0);
HPS_DDR3_ODT : out std_logic;
HPS_DDR3_RAS_N : out std_logic;
HPS_DDR3_RESET_N : out std_logic;
HPS_DDR3_RZQ : in std_logic;
HPS_DDR3_WE_N : out std_logic;
HPS_ENET_GTX_CLK : out std_logic;
HPS_ENET_INT_N : inout std_logic;
HPS_ENET_MDC : out std_logic;
HPS_ENET_MDIO : inout std_logic;
HPS_ENET_RX_CLK : in std_logic;
HPS_ENET_RX_DATA : in std_logic_vector(4-1 downto 0);
HPS_ENET_RX_DV : in std_logic;
HPS_ENET_TX_DATA : out std_logic_vector(4-1 downto 0);
HPS_ENET_TX_EN : out std_logic;
HPS_GSENSOR_INT : inout std_logic;
HPS_I2C0_SCLK : inout std_logic;
HPS_I2C0_SDAT : inout std_logic;
HPS_I2C1_SCLK : inout std_logic;
HPS_I2C1_SDAT : inout std_logic;
HPS_KEY : inout std_logic;
HPS_LED : inout std_logic;
HPS_LTC_GPIO : inout std_logic;
HPS_SD_CLK : out std_logic;
HPS_SD_CMD : inout std_logic;
HPS_SD_DATA : inout std_logic_vector(4-1 downto 0);
HPS_SPIM_CLK : out std_logic;
HPS_SPIM_MISO : in std_logic;
HPS_SPIM_MOSI : out std_logic;
HPS_SPIM_SS : inout std_logic;
HPS_UART_RX : in std_logic;
HPS_UART_TX : out std_logic;
HPS_USB_CLKOUT : in std_logic;
HPS_USB_DATA : inout std_logic_vector(8-1 downto 0);
HPS_USB_DIR : in std_logic;
HPS_USB_NXT : in std_logic;
HPS_USB_STP : out std_logic;
--`endif /*ENABLE_HPS*/
----------/ KEY --------/
KEY : in std_logic_vector(2-1 downto 0);
----------/ LED --------/
LED : out std_logic_vector(8-1 downto 0);
----------/ SW --------/
SW : in std_logic_vector(4-1 downto 0)
);
end entity;
architecture hpsfpga_arch of hpsfpga is
component hps_fpga is
port (
clk_clk : in std_logic := 'X'; -- clk
hps_arm_h2f_reset_reset_n : out std_logic; -- reset_n
hps_arm_hps_io_hps_io_emac1_inst_TX_CLK : out std_logic; -- hps_io_emac1_inst_TX_CLK
hps_arm_hps_io_hps_io_emac1_inst_TXD0 : out std_logic; -- hps_io_emac1_inst_TXD0
hps_arm_hps_io_hps_io_emac1_inst_TXD1 : out std_logic; -- hps_io_emac1_inst_TXD1
hps_arm_hps_io_hps_io_emac1_inst_TXD2 : out std_logic; -- hps_io_emac1_inst_TXD2
hps_arm_hps_io_hps_io_emac1_inst_TXD3 : out std_logic; -- hps_io_emac1_inst_TXD3
hps_arm_hps_io_hps_io_emac1_inst_RXD0 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD0
hps_arm_hps_io_hps_io_emac1_inst_MDIO : inout std_logic := 'X'; -- hps_io_emac1_inst_MDIO
hps_arm_hps_io_hps_io_emac1_inst_MDC : out std_logic; -- hps_io_emac1_inst_MDC
hps_arm_hps_io_hps_io_emac1_inst_RX_CTL : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CTL
hps_arm_hps_io_hps_io_emac1_inst_TX_CTL : out std_logic; -- hps_io_emac1_inst_TX_CTL
hps_arm_hps_io_hps_io_emac1_inst_RX_CLK : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CLK
hps_arm_hps_io_hps_io_emac1_inst_RXD1 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD1
hps_arm_hps_io_hps_io_emac1_inst_RXD2 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD2
hps_arm_hps_io_hps_io_emac1_inst_RXD3 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD3
hps_arm_hps_io_hps_io_sdio_inst_CMD : inout std_logic := 'X'; -- hps_io_sdio_inst_CMD
hps_arm_hps_io_hps_io_sdio_inst_D0 : inout std_logic := 'X'; -- hps_io_sdio_inst_D0
hps_arm_hps_io_hps_io_sdio_inst_D1 : inout std_logic := 'X'; -- hps_io_sdio_inst_D1
hps_arm_hps_io_hps_io_sdio_inst_CLK : out std_logic; -- hps_io_sdio_inst_CLK
hps_arm_hps_io_hps_io_sdio_inst_D2 : inout std_logic := 'X'; -- hps_io_sdio_inst_D2
hps_arm_hps_io_hps_io_sdio_inst_D3 : inout std_logic := 'X'; -- hps_io_sdio_inst_D3
hps_arm_hps_io_hps_io_usb1_inst_D0 : inout std_logic := 'X'; -- hps_io_usb1_inst_D0
hps_arm_hps_io_hps_io_usb1_inst_D1 : inout std_logic := 'X'; -- hps_io_usb1_inst_D1
hps_arm_hps_io_hps_io_usb1_inst_D2 : inout std_logic := 'X'; -- hps_io_usb1_inst_D2
hps_arm_hps_io_hps_io_usb1_inst_D3 : inout std_logic := 'X'; -- hps_io_usb1_inst_D3
hps_arm_hps_io_hps_io_usb1_inst_D4 : inout std_logic := 'X'; -- hps_io_usb1_inst_D4
hps_arm_hps_io_hps_io_usb1_inst_D5 : inout std_logic := 'X'; -- hps_io_usb1_inst_D5
hps_arm_hps_io_hps_io_usb1_inst_D6 : inout std_logic := 'X'; -- hps_io_usb1_inst_D6
hps_arm_hps_io_hps_io_usb1_inst_D7 : inout std_logic := 'X'; -- hps_io_usb1_inst_D7
hps_arm_hps_io_hps_io_usb1_inst_CLK : in std_logic := 'X'; -- hps_io_usb1_inst_CLK
hps_arm_hps_io_hps_io_usb1_inst_STP : out std_logic; -- hps_io_usb1_inst_STP
hps_arm_hps_io_hps_io_usb1_inst_DIR : in std_logic := 'X'; -- hps_io_usb1_inst_DIR
hps_arm_hps_io_hps_io_usb1_inst_NXT : in std_logic := 'X'; -- hps_io_usb1_inst_NXT
hps_arm_hps_io_hps_io_spim1_inst_CLK : out std_logic; -- hps_io_spim1_inst_CLK
hps_arm_hps_io_hps_io_spim1_inst_MOSI : out std_logic; -- hps_io_spim1_inst_MOSI
hps_arm_hps_io_hps_io_spim1_inst_MISO : in std_logic := 'X'; -- hps_io_spim1_inst_MISO
hps_arm_hps_io_hps_io_spim1_inst_SS0 : out std_logic; -- hps_io_spim1_inst_SS0
hps_arm_hps_io_hps_io_uart0_inst_RX : in std_logic := 'X'; -- hps_io_uart0_inst_RX
hps_arm_hps_io_hps_io_uart0_inst_TX : out std_logic; -- hps_io_uart0_inst_TX
hps_arm_hps_io_hps_io_i2c0_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c0_inst_SDA
hps_arm_hps_io_hps_io_i2c0_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c0_inst_SCL
hps_arm_hps_io_hps_io_i2c1_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c1_inst_SDA
hps_arm_hps_io_hps_io_i2c1_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c1_inst_SCL
memory_mem_a : out std_logic_vector(14 downto 0); -- mem_a
memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
memory_mem_ck : out std_logic; -- mem_ck
memory_mem_ck_n : out std_logic; -- mem_ck_n
memory_mem_cke : out std_logic; -- mem_cke
memory_mem_cs_n : out std_logic; -- mem_cs_n
memory_mem_ras_n : out std_logic; -- mem_ras_n
memory_mem_cas_n : out std_logic; -- mem_cas_n
memory_mem_we_n : out std_logic; -- mem_we_n
memory_mem_reset_n : out std_logic; -- mem_reset_n
memory_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
memory_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
memory_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
memory_mem_odt : out std_logic; -- mem_odt
memory_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
reset_reset_n : in std_logic := 'X'; -- reset_n
pio_n_layer1_data_in_value : in std_logic_vector(2048-1 downto 0) := (others => 'X'); -- data_in_value
pio_n_layer1_data_in_read : out std_logic_vector(64-1 downto 0); -- data_in_read
pio_n_layer1_data_out_value : out std_logic_vector(2048-1 downto 0); -- data_out_value
pio_n_layer1_data_out_write : out std_logic_vector(64-1 downto 0); -- data_out_write
pio_n_layer2_data_in_value : in std_logic_vector(2048-1 downto 0) := (others => 'X'); -- data_in_value
pio_n_layer2_data_in_read : out std_logic_vector(64-1 downto 0); -- data_in_read
pio_n_layer2_data_out_value : out std_logic_vector(2048-1 downto 0); -- data_out_value
pio_n_layer2_data_out_write : out std_logic_vector(64-1 downto 0); -- data_out_write
pio_n_layer3_data_in_value : in std_logic_vector(2048-1 downto 0) := (others => 'X'); -- data_in_value
pio_n_layer3_data_in_read : out std_logic_vector(64-1 downto 0); -- data_in_read
pio_n_layer3_data_out_value : out std_logic_vector(2048-1 downto 0); -- data_out_value
pio_n_layer3_data_out_write : out std_logic_vector(64-1 downto 0); -- data_out_write
uart_0_rxd : in std_logic := 'X'; -- rxd
uart_0_txd : out std_logic; -- txd
uart_1_rxd : in std_logic := 'X'; -- rxd
uart_1_txd : out std_logic; -- txd
uart_2_rxd : in std_logic := 'X'; -- rxd
uart_2_txd : out std_logic; -- txd
uart_3_rxd : in std_logic := 'X'; -- rxd
uart_3_txd : out std_logic; -- txd
uart_4_rxd : in std_logic := 'X'; -- rxd
uart_4_txd : out std_logic; -- txd
uart_5_rxd : in std_logic := 'X'; -- rxd
uart_5_txd : out std_logic -- txd
--uart_6_rxd : in std_logic := 'X'; -- rxd
--uart_6_txd : out std_logic; -- txd
--uart_7_rxd : in std_logic := 'X'; -- rxd
--uart_7_txd : out std_logic -- txd
);
end component hps_fpga;
----=======================================================
---- REG/WIRE declarations
----=======================================================
signal hps_fpga_reset_n : std_logic;
signal w_pio_n_layer1_data_in_value : std_logic_vector(2048-1 downto 0) := (others => 'X'); -- data_in_value
signal w_pio_n_layer1_data_in_read : std_logic_vector(64-1 downto 0); -- data_in_read
signal w_pio_n_layer1_data_out_value : std_logic_vector(2048-1 downto 0); -- data_out_value
signal w_pio_n_layer1_data_out_write : std_logic_vector(64-1 downto 0); -- data_out_write
signal w_pio_n_layer2_data_in_value : std_logic_vector(2048-1 downto 0) := (others => 'X'); -- data_in_value
signal w_pio_n_layer2_data_in_read : std_logic_vector(64-1 downto 0); -- data_in_read
signal w_pio_n_layer2_data_out_value : std_logic_vector(2048-1 downto 0); -- data_out_value
signal w_pio_n_layer2_data_out_write : std_logic_vector(64-1 downto 0); -- data_out_write
signal w_pio_n_layer3_data_in_value : std_logic_vector(2048-1 downto 0) := (others => 'X'); -- data_in_value
signal w_pio_n_layer3_data_in_read : std_logic_vector(64-1 downto 0); -- data_in_read
signal w_pio_n_layer3_data_out_value : std_logic_vector(2048-1 downto 0); -- data_out_value
signal w_pio_n_layer3_data_out_write : std_logic_vector(64-1 downto 0); -- data_out_write
--------- UART ----------
signal w_uart_tx : std_logic_vector(4-1 downto 0);
signal w_uart_rx : std_logic_vector(4-1 downto 0);
signal w_motor_value : int16_t(6-1 downto 0);
signal w_motor_current : int24_t(6-1 downto 0);
signal w_motor_fault : std_logic_vector(6-1 downto 0);
signal w_qei_value : int16_t(5-1 downto 0);
signal w_qei_ref : std_logic_vector(5-1 downto 0);
signal w_sum_m_dist : std_logic_vector(32-1 downto 0);
signal w_sum_m_angle : std_logic_vector(32-1 downto 0);
signal w_sum_c_dist : std_logic_vector(32-1 downto 0);
signal w_sum_c_angle : std_logic_vector(32-1 downto 0);
signal w_pos_valid : std_logic;
signal w_pos_id : std_logic_vector(8-1 downto 0);
signal w_pos_teta : std_logic_vector(16-1 downto 0);
signal w_pos_x : std_logic_vector(16-1 downto 0);
signal w_pos_y : std_logic_vector(16-1 downto 0);
signal w_pos_sum_dist : std_logic_vector(32-1 downto 0);
signal w_pos_sum_angle : std_logic_vector(32-1 downto 0);
signal w_dist_en : std_logic;
signal w_dist_acc : std_logic_vector(32-1 downto 0);
signal w_dist_speed : std_logic_vector(32-1 downto 0);
signal w_dist_target : std_logic_vector(32-1 downto 0);
signal w_angle_en : std_logic;
signal w_angle_acc : std_logic_vector(32-1 downto 0);
signal w_angle_speed : std_logic_vector(32-1 downto 0);
signal w_angle_target : std_logic_vector(32-1 downto 0);
signal r_reset : std_logic;
--signal r_cnt : natural := 0;
signal w_uart_loop : std_logic;
begin
p_sync: process(FPGA_CLK1_50)
begin
if rising_edge(FPGA_CLK1_50) then
r_reset <= not hps_fpga_reset_n or w_pio_n_layer1_data_out_value(0);
end if;
end process;
--led(8-1 downto 4) <= w_ledg_out(4-1 downto 0);
buzzer <= '0';
inst_layer_1: robot_layer_1
generic map (
CLK_FREQUENCY_HZ => 50_000_000,
RegCnt => 64
)
port map (
clk => FPGA_CLK1_50,
reset => r_reset,
regs_data_in_value => w_pio_n_layer1_data_in_value,
regs_data_in_read => w_pio_n_layer1_data_in_read,
regs_data_out_value => w_pio_n_layer1_data_out_value,
regs_data_out_write => w_pio_n_layer1_data_out_write,
----------- ADC (//) ---------
ad0_sclk => ad0_sclk,
ad0_miso => ad0_miso,
ad0_drdy => ad0_drdy,
ad0_sync => ad0_sync,
ad0_clk => ad0_clk ,
--------- ADC (muxed) --------
ad1_sclk => ad1_sclk,
ad1_mosi => ad1_mosi,
ad1_miso => ad1_miso,
ad1_ss => ad1_ss,
ad1_drdy => ad1_drdy,
ad1_rst => ad1_rst,
---------- H BRIDGE ----------
m0_pwma => m0_pwma,
m0_pwmb => m0_pwmb,
m01_fault=> m01_fault,
m1_pwma => m1_pwma,
m1_pwmb => m1_pwmb,
m01_resetn=> m01_resetn,
m2_pwma => m2_pwma,
m2_pwmb => m2_pwmb,
m3_pwma => m3_pwma,
m3_pwmb => m3_pwmb,
m2345_fault=> m2345_fault,
m4_pwma => m4_pwma,
m4_pwmb => m4_pwmb,
m5_pwma => m5_pwma,
m5_pwmb => m5_pwmb,
m2345_resetn=> m2345_resetn,
---------- QEI ----------
qei0_a => qei0_a,
qei0_b => qei0_b,
qei1_a => qei1_a,
qei1_b => qei1_b,
qei2_a => qei2_a,
qei2_b => qei2_b,
qei2_z => qei2_z,
qei3_a => qei3_a,
qei3_b => qei3_b,
qei3_z => qei3_z,
---------- ESC ----------
esc0_pwm => esc0_pwm,
esc0_dir => esc0_dir,
esc1_pwm => esc1_pwm,
esc1_dir => esc1_dir,
------- PWM (Servos) ------
s => s,
--------- IOs ----------
io_0 => io_0,
io_1 => io_1,
io_2 => io_2,
io_3 => io_3,
io_4 => io_4,
io_5 => io_5,
io_6 => io_6,
io_7 => io_7,
--------- UART ----------
uart0_rx => uart0_rx,
uart0_tx => uart0_tx,
uart1_rx => uart1_rx,
uart1_tx => uart1_tx,
uart2_rx => uart2_rx,
uart2_tx => uart2_tx,
uart2_custom => uart2_custom,
uart3_rx => uart3_rx,
uart3_tx => uart3_tx,
uart3_custom => uart3_custom,
--------- I2C ----------
i2c0_scl => i2c0_scl,
i2c0_sda => i2c0_sda,
i2c0_reset => i2c0_reset,
i2c1_scl => i2c1_scl,
i2c1_sda => i2c1_sda,
i2c1_reset => i2c1_reset,
--------- SPI ----------
spi0_sclk => spi0_sclk,
spi0_mosi => spi0_mosi,
spi0_miso => spi0_miso,
spi0_ss => spi0_ss,
spi1_sclk => spi1_sclk,
spi1_mosi => spi1_mosi,
spi1_miso => spi1_miso,
spi1_ss => spi1_ss,
--! Use SPI1
imu_ss => imu_ss,
imu_drdy => imu_drdy,
imu_fsync => imu_fsync,
---------- LED -----------
led_green => led_green,
led_red => led_red,
--------- MGMT -----------
lv_mux => lv_mux,
buzzer => open,
----------/ NANO SOC LED --------/
LED => LED,
----------/ NANO SOC SW --------/
SW => SW,
---------------------------------
-------- TO/FROM LAYER 2 --------
---------------------------------
--------- UART ----------
uart_tx => w_uart_tx,
uart_rx => w_uart_rx,
motor_value => w_motor_value,
motor_current => w_motor_current,
motor_fault => w_motor_fault,
qei_value => w_qei_value,
qei_ref => w_qei_ref
);
inst_layer_2: robot_layer_2
generic map (
CLK_FREQUENCY_HZ => 50_000_000,
RegCnt => 64
)
port map (
clk => FPGA_CLK1_50,
reset => r_reset,
regs_data_in_value => w_pio_n_layer2_data_in_value,
regs_data_in_read => w_pio_n_layer2_data_in_read,
regs_data_out_value => w_pio_n_layer2_data_out_value,
regs_data_out_write => w_pio_n_layer2_data_out_write,
---------------------------------
-------- TO/FROM LAYER 1 --------
---------------------------------
--------- UART ----------
uart_tx => w_uart_tx,
uart_rx => w_uart_rx,
motor_value => w_motor_value,
motor_current => w_motor_current,
motor_fault => w_motor_fault,
qei_value => w_qei_value,
qei_ref => w_qei_ref,
---------------------------------
-------- TO/FROM LAYER 3 --------
---------------------------------
sum_m_dist => w_sum_m_dist,
sum_m_angle => w_sum_m_angle,
sum_c_dist => w_sum_c_dist,
sum_c_angle => w_sum_c_angle,
pos_valid => w_pos_valid,
pos_id => w_pos_id,
pos_teta => w_pos_teta,
pos_x => w_pos_x,
pos_y => w_pos_y,
pos_sum_dist => w_pos_sum_dist,
pos_sum_angle => w_pos_sum_angle,
dist_en => w_dist_en,
dist_acc => w_dist_acc,
dist_speed => w_dist_speed,
dist_target => w_dist_target,
angle_en => w_angle_en,
angle_acc => w_angle_acc,
angle_speed => w_angle_speed,
angle_target => w_angle_target
);
inst_layer_3: robot_layer_3
generic map (
CLK_FREQUENCY_HZ => 50_000_000,
RegCnt => 64
)
port map (
clk => FPGA_CLK1_50,
reset => r_reset,
regs_data_in_value => w_pio_n_layer3_data_in_value,
regs_data_in_read => w_pio_n_layer3_data_in_read,
regs_data_out_value => w_pio_n_layer3_data_out_value,
regs_data_out_write => w_pio_n_layer3_data_out_write,
---------------------------------
-------- TO/FROM LAYER 2 --------
---------------------------------
sum_m_dist => w_sum_m_dist,
sum_m_angle => w_sum_m_angle,
sum_c_dist => w_sum_c_dist,
sum_c_angle => w_sum_c_angle,
pos_valid => w_pos_valid,
pos_id => w_pos_id,
pos_teta => w_pos_teta,
pos_x => w_pos_x,
pos_y => w_pos_y,
pos_sum_dist => w_pos_sum_dist,
pos_sum_angle => w_pos_sum_angle,
dist_en => w_dist_en,
dist_acc => w_dist_acc,
dist_speed => w_dist_speed,
dist_target => w_dist_target,
angle_en => w_angle_en,
angle_acc => w_angle_acc,
angle_speed => w_angle_speed,
angle_target => w_angle_target
);
----=======================================================
---- Structural coding
----=======================================================
inst_hps: hps_fpga
port map(
-- CLK & RESET
clk_clk => FPGA_CLK1_50 , -- clkclk
reset_reset_n => '1' , -- resetreset_n
hps_arm_h2f_reset_reset_n => hps_fpga_reset_n,
pio_n_layer1_data_in_value => w_pio_n_layer1_data_in_value, -- pio_n_layer1.data_in_value
pio_n_layer1_data_in_read => w_pio_n_layer1_data_in_read, -- .data_in_read
pio_n_layer1_data_out_value => w_pio_n_layer1_data_out_value, -- .data_out_value
pio_n_layer1_data_out_write => w_pio_n_layer1_data_out_write, -- .data_out_write
pio_n_layer2_data_in_value => w_pio_n_layer2_data_in_value, -- pio_n_layer2.data_in_value
pio_n_layer2_data_in_read => w_pio_n_layer2_data_in_read, -- .data_in_read
pio_n_layer2_data_out_value => w_pio_n_layer2_data_out_value, -- .data_out_value
pio_n_layer2_data_out_write => w_pio_n_layer2_data_out_write, -- .data_out_write
pio_n_layer3_data_in_value => w_pio_n_layer3_data_in_value, -- pio_n_layer3.data_in_value
pio_n_layer3_data_in_read => w_pio_n_layer3_data_in_read, -- .data_in_read
pio_n_layer3_data_out_value => w_pio_n_layer3_data_out_value, -- .data_out_value
pio_n_layer3_data_out_write => w_pio_n_layer3_data_out_write, -- .data_out_write
-- HPS ETHERNET
hps_arm_hps_io_hps_io_emac1_inst_TX_CLK => HPS_ENET_GTX_CLK , -- hps_arm_hps_iohps_io_emac1_inst_TX_CLK
hps_arm_hps_io_hps_io_emac1_inst_TXD0 => HPS_ENET_TX_DATA(0) , -- hps_io_emac1_inst_TXD0
hps_arm_hps_io_hps_io_emac1_inst_TXD1 => HPS_ENET_TX_DATA(1) , -- hps_io_emac1_inst_TXD1
hps_arm_hps_io_hps_io_emac1_inst_TXD2 => HPS_ENET_TX_DATA(2), -- hps_io_emac1_inst_TXD2
hps_arm_hps_io_hps_io_emac1_inst_TXD3 => HPS_ENET_TX_DATA(3), -- hps_io_emac1_inst_TXD3
hps_arm_hps_io_hps_io_emac1_inst_RXD0 => HPS_ENET_RX_DATA(0), -- hps_io_emac1_inst_RXD0
hps_arm_hps_io_hps_io_emac1_inst_MDIO => HPS_ENET_MDIO , -- hps_io_emac1_inst_MDIO
hps_arm_hps_io_hps_io_emac1_inst_MDC => HPS_ENET_MDC , -- hps_io_emac1_inst_MDC
hps_arm_hps_io_hps_io_emac1_inst_RX_CTL => HPS_ENET_RX_DV , -- hps_io_emac1_inst_RX_CTL
hps_arm_hps_io_hps_io_emac1_inst_TX_CTL => HPS_ENET_TX_EN , -- hps_io_emac1_inst_TX_CTL
hps_arm_hps_io_hps_io_emac1_inst_RX_CLK => HPS_ENET_RX_CLK , -- hps_io_emac1_inst_RX_CLK
hps_arm_hps_io_hps_io_emac1_inst_RXD1 => HPS_ENET_RX_DATA(1), -- hps_io_emac1_inst_RXD1
hps_arm_hps_io_hps_io_emac1_inst_RXD2 => HPS_ENET_RX_DATA(2), -- hps_io_emac1_inst_RXD2
hps_arm_hps_io_hps_io_emac1_inst_RXD3 => HPS_ENET_RX_DATA(3), -- hps_io_emac1_inst_RXD3
-- HPS SD CARD
hps_arm_hps_io_hps_io_sdio_inst_CMD => HPS_SD_CMD , -- hps_io_sdio_inst_CMD
hps_arm_hps_io_hps_io_sdio_inst_D0 => HPS_SD_DATA(0), -- hps_io_sdio_inst_D0
hps_arm_hps_io_hps_io_sdio_inst_D1 => HPS_SD_DATA(1), -- hps_io_sdio_inst_D1
hps_arm_hps_io_hps_io_sdio_inst_CLK => HPS_SD_CLK , -- hps_io_sdio_inst_CLK
hps_arm_hps_io_hps_io_sdio_inst_D2 => HPS_SD_DATA(2), -- hps_io_sdio_inst_D2
hps_arm_hps_io_hps_io_sdio_inst_D3 => HPS_SD_DATA(3), -- hps_io_sdio_inst_D3
-- HPS USB
hps_arm_hps_io_hps_io_usb1_inst_D0 => HPS_USB_DATA(0), -- hps_io_usb1_inst_D0
hps_arm_hps_io_hps_io_usb1_inst_D1 => HPS_USB_DATA(1), -- hps_io_usb1_inst_D1
hps_arm_hps_io_hps_io_usb1_inst_D2 => HPS_USB_DATA(2), -- hps_io_usb1_inst_D2
hps_arm_hps_io_hps_io_usb1_inst_D3 => HPS_USB_DATA(3), -- hps_io_usb1_inst_D3
hps_arm_hps_io_hps_io_usb1_inst_D4 => HPS_USB_DATA(4), -- hps_io_usb1_inst_D4
hps_arm_hps_io_hps_io_usb1_inst_D5 => HPS_USB_DATA(5), -- hps_io_usb1_inst_D5
hps_arm_hps_io_hps_io_usb1_inst_D6 => HPS_USB_DATA(6), -- hps_io_usb1_inst_D6
hps_arm_hps_io_hps_io_usb1_inst_D7 => HPS_USB_DATA(7), -- hps_io_usb1_inst_D7
hps_arm_hps_io_hps_io_usb1_inst_CLK => HPS_USB_CLKOUT , -- hps_io_usb1_inst_CLK
hps_arm_hps_io_hps_io_usb1_inst_STP => HPS_USB_STP , -- hps_io_usb1_inst_STP
hps_arm_hps_io_hps_io_usb1_inst_DIR => HPS_USB_DIR , -- hps_io_usb1_inst_DIR
hps_arm_hps_io_hps_io_usb1_inst_NXT => HPS_USB_NXT , -- hps_io_usb1_inst_NXT
-- HPS SPI
hps_arm_hps_io_hps_io_spim1_inst_CLK => HPS_SPIM_CLK , -- hps_io_spim1_inst_CLK
hps_arm_hps_io_hps_io_spim1_inst_MOSI => HPS_SPIM_MOSI , -- hps_io_spim1_inst_MOSI
hps_arm_hps_io_hps_io_spim1_inst_MISO => HPS_SPIM_MISO , -- hps_io_spim1_inst_MISO
hps_arm_hps_io_hps_io_spim1_inst_SS0 => HPS_SPIM_SS , -- hps_io_spim1_inst_SS0
-- HPS UART
hps_arm_hps_io_hps_io_uart0_inst_RX => HPS_UART_RX , -- hps_io_uart0_inst_RX
hps_arm_hps_io_hps_io_uart0_inst_TX => HPS_UART_TX , -- hps_io_uart0_inst_TX
hps_arm_hps_io_hps_io_i2c0_inst_SDA => HPS_I2C0_SDAT , -- hps_io_i2c0_inst_SDA
hps_arm_hps_io_hps_io_i2c0_inst_SCL => HPS_I2C0_SCLK , -- hps_io_i2c0_inst_SCL
-- HPS I2C1
hps_arm_hps_io_hps_io_i2c1_inst_SDA => HPS_I2C1_SDAT , -- hps_io_i2c1_inst_SDA
hps_arm_hps_io_hps_io_i2c1_inst_SCL => HPS_I2C1_SCLK , -- hps_io_i2c1_inst_SCL
uart_0_rxd => w_uart_tx(0),
uart_0_txd => open,
uart_1_rxd => w_uart_tx(1),
uart_1_txd => open,
uart_2_rxd => w_uart_tx(2),
uart_2_txd => open,
uart_3_rxd => w_uart_tx(3),
uart_3_txd => open,
uart_4_rxd => w_uart_tx(3),
uart_4_txd => open,
uart_5_rxd => w_uart_loop,
uart_5_txd => w_uart_loop,
--uart_6_rxd => '0',
--uart_6_txd => open,
--uart_7_rxd => '0',
--uart_7_txd => open,
-- HPS DDR3
memory_mem_a => HPS_DDR3_ADDR , -- memorymem_a
memory_mem_ba => HPS_DDR3_BA , -- mem_ba
memory_mem_ck => HPS_DDR3_CK_P , -- mem_ck
memory_mem_ck_n => HPS_DDR3_CK_N , -- mem_ck_n
memory_mem_cke => HPS_DDR3_CKE , -- mem_cke
memory_mem_cs_n => HPS_DDR3_CS_N , -- mem_cs_n
memory_mem_ras_n => HPS_DDR3_RAS_N , -- mem_ras_n
memory_mem_cas_n => HPS_DDR3_CAS_N , -- mem_cas_n
memory_mem_we_n => HPS_DDR3_WE_N , -- mem_we_n
memory_mem_reset_n => HPS_DDR3_RESET_N , -- mem_reset_n
memory_mem_dq => HPS_DDR3_DQ , -- mem_dq
memory_mem_dqs => HPS_DDR3_DQS_P , -- mem_dqs
memory_mem_dqs_n => HPS_DDR3_DQS_N , -- mem_dqs_n
memory_mem_odt => HPS_DDR3_ODT , -- mem_odt
memory_mem_dm => HPS_DDR3_DM , -- mem_dm
memory_oct_rzqin => HPS_DDR3_RZQ -- .oct_rzqin
);
end architecture;
| gpl-3.0 | a4fa7525e26ab9bd8bf5f86c9270d419 | 0.422806 | 3.238855 | false | false | false | false |
Hyvok/HardHeat | sim/phase_accumulator/phase_accumulator_tb.vhd | 1 | 1,325 | library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity phase_accumulator_tb is
generic
(
ACCUM_BITS_N : positive := 32;
TUNING_WORD_N : positive := 22
);
end entity;
architecture rtl of phase_accumulator_tb is
-- Clock frequency is 100 MHz
constant CLK_PERIOD : time := 1 sec / 10e8;
signal clk : std_logic := '0';
signal reset : std_logic;
signal tuning_word_in : unsigned(TUNING_WORD_N - 1 downto 0);
signal sig_out : std_logic;
begin
DUT_inst: entity work.phase_accumulator(rtl)
generic map
(
ACCUM_BITS_N => ACCUM_BITS_N,
TUNING_WORD_N => TUNING_WORD_N
)
port map
(
clk => clk,
reset => reset,
tuning_word_in => tuning_word_in,
sig_out => sig_out
);
reset <= '1', '0' after 500 ns;
clk_gen: process(clk)
begin
clk <= not clk after CLK_PERIOD / 2;
end process;
tuning_word_gen: process(clk)
begin
if reset = '1' then
tuning_word_in <= to_unsigned(2**TUNING_WORD_N - 1, TUNING_WORD_N);
elsif rising_edge(clk) then
tuning_word_in <= tuning_word_in - 1;
end if;
end process;
end;
| mit | 9a7cbdfb36ce01223ff6a39a227aedf3 | 0.537358 | 3.505291 | false | false | false | false |
jz0229/open-ephys-pcie | serdes-interface/firmware/TB_SPI_LEDdriver.vhd | 2 | 2,341 | --------------------------------------------------------------------------------
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TB_SPI_LEDdriver IS
END TB_SPI_LEDdriver;
ARCHITECTURE behavior OF TB_SPI_LEDdriver IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SPI_LEDdriver
PORT(
clk_spi : IN std_logic;
reset : IN std_logic;
write_start : IN std_logic;
command_in : IN std_logic_vector(15 downto 0);
led_clk_o : OUT std_logic;
led_data_o : OUT std_logic;
led_latch_o : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk_spi : std_logic := '0';
signal reset : std_logic := '0';
signal write_start : std_logic := '0';
signal command_in : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal led_clk_o : std_logic;
signal led_data_o : std_logic;
signal led_latch_o : std_logic;
-- Clock period definitions
constant clk_spi_period : time := 10 ns;
constant write_start_period : time := 1 us;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: SPI_LEDdriver PORT MAP (
clk_spi => clk_spi,
reset => reset,
write_start => write_start,
command_in => command_in,
led_clk_o => led_clk_o,
led_data_o => led_data_o,
led_latch_o => led_latch_o
);
-- Clock process definitions
clk_spi_process :process
begin
clk_spi <= '0';
wait for clk_spi_period/2;
clk_spi <= '1';
wait for clk_spi_period/2;
end process;
write_start_process :process
begin
write_start <= '0';
wait for write_start_period;
write_start <= '1';
wait for 40 ns;
end process;
-- Stimulus process
stim_proc: process
begin
command_in <= "1000000001011011";
-- hold reset state for 100 ns.
reset <= '1';
wait for 100 ns;
reset <= '0';
wait for clk_spi_period*10;
-- insert stimulus here
wait;
end process;
END;
| mit | 0e0b8f3b36d3f5635a09cce637ec7ec4 | 0.532678 | 3.812704 | false | false | false | false |
kjellhar/ArtixPi | spi_test/src/hdl/ocore/spi_slave.vhd | 1 | 33,688 | ----------------------------------------------------------------------------------
-- Author: Jonny Doin, [email protected]
--
-- Create Date: 15:36:20 05/15/2011
-- Module Name: SPI_SLAVE - RTL
-- Project Name: SPI INTERFACE
-- Target Devices: Spartan-6
-- Tool versions: ISE 13.1
-- Description:
--
-- This block is the SPI slave interface, implemented in one single entity.
-- All internal core operations are synchronous to the external SPI clock, and follows the general SPI de-facto standard.
-- The parallel read/write interface is synchronous to a supplied system master clock, 'clk_i'.
-- Synchronization for the parallel ports is provided by input data request and write enable lines, and output data valid line.
-- Fully pipelined cross-clock circuitry guarantees that no setup artifacts occur on the buffers that are accessed by the two
-- clock domains.
--
-- The block is very simple to use, and has parallel inputs and outputs that behave like a synchronous memory i/o.
-- It is parameterizable via generics for the data width ('N'), SPI mode (CPHA and CPOL), and lookahead prefetch
-- signaling ('PREFETCH').
--
-- PARALLEL WRITE INTERFACE
-- The parallel interface has a input port 'di_i' and an output port 'do_o'.
-- Parallel load is controlled using 3 signals: 'di_i', 'di_req_o' and 'wren_i'.
-- When the core needs input data, a look ahead data request strobe , 'di_req_o' is pulsed 'PREFETCH' 'spi_sck_i'
-- cycles in advance to synchronize a user pipelined memory or fifo to present the next input data at 'di_i'
-- in time to have continuous clock at the spi bus, to allow back-to-back continuous load.
-- The data request strobe on 'di_req_o' is 2 'clk_i' clock cycles long.
-- The write to 'di_i' must occur at most one 'spi_sck_i' cycle before actual load to the core shift register, to avoid
-- race conditions at the register transfer.
-- The user circuit places data at the 'di_i' port and strobes the 'wren_i' line for one rising edge of 'clk_i'.
-- For a pipelined sync RAM, a PREFETCH of 3 cycles allows an address generator to present the new adress to the RAM in one
-- cycle, and the RAM to respond in one more cycle, in time for 'di_i' to be latched by the interface one clock before transfer.
-- If the user sequencer needs a different value for PREFETCH, the generic can be altered at instantiation time.
-- The 'wren_i' write enable strobe must be valid at least one setup time before the rising edge of the last clock cycle,
-- if continuous transmission is intended.
-- When the interface is idle ('spi_ssel_i' is HIGH), the top bit of the latched 'di_i' port is presented at port 'spi_miso_o'.
--
-- PARALLEL WRITE PIPELINED SEQUENCE
-- =================================
-- __ __ __ __ __ __ __
-- clk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \... -- parallel interface clock
-- ___________
-- di_req_o ________/ \_____________________... -- 'di_req_o' asserted on rising edge of 'clk_i'
-- ______________ ___________________________...
-- di_i __old_data____X______new_data_____________... -- user circuit loads data on 'di_i' at next 'clk_i' rising edge
-- ________
-- wren_i __________________________/ \______... -- 'wren_i' enables latch on rising edge of 'clk_i'
--
--
-- PARALLEL READ INTERFACE
-- An internal buffer is used to copy the internal shift register data to drive the 'do_o' port. When a complete
-- word is received, the core shift register is transferred to the buffer, at the rising edge of the spi clock, 'spi_sck_i'.
-- The signal 'do_valid_o' is strobed 3 'clk_i' clocks after, to directly drive a synchronous memory or fifo write enable.
-- 'do_valid_o' is synchronous to the parallel interface clock, and changes only on rising edges of 'clk_i'.
-- When the interface is idle, data at the 'do_o' port holds the last word received.
--
-- PARALLEL READ PIPELINED SEQUENCE
-- ================================
-- ______ ______ ______ ______
-- clk_spi_i ___/ bit1 \______/ bitN \______/bitN-1\______/bitN-2\__... -- spi base clock
-- __ __ __ __ __ __ __ __ __
-- clk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \_... -- parallel interface clock
-- _________________ _____________________________________... -- 1) received data is transferred to 'do_buffer_reg'
-- do_o __old_data_______X__________new_data___________________... -- after last bit received, at next shift clock.
-- ____________
-- do_valid_o ________________________________/ \_________... -- 2) 'do_valid_o' strobed for 2 'clk_i' cycles
-- -- on the 3rd 'clk_i' rising edge.
--
--
-- This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints.
--
------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
--
-- This file is part of the SPI MASTER/SLAVE INTERFACE project http://opencores.org/project,spi_master_slave
--
-- Author(s): Jonny Doin, [email protected], [email protected]
--
-- Copyright (C) 2011 Jonny Doin
-- -----------------------------
--
-- This source file may be used and distributed without restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains the original copyright notice and the associated
-- disclaimer.
--
-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser
-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download
-- it from http://www.gnu.org/licenses/lgpl.txt
--
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
--
-- 2011/05/15 v0.10.0050 [JD] created the slave logic, with 2 clock domains, from SPI_MASTER module.
-- 2011/05/15 v0.15.0055 [JD] fixed logic for starting state when CPHA='1'.
-- 2011/05/17 v0.80.0049 [JD] added explicit clock synchronization circuitry across clock boundaries.
-- 2011/05/18 v0.95.0050 [JD] clock generation circuitry, with generators for all-rising-edge clock core.
-- 2011/06/05 v0.96.0053 [JD] changed async clear to sync resets.
-- 2011/06/07 v0.97.0065 [JD] added cross-clock buffers, fixed fsm async glitches.
-- 2011/06/09 v0.97.0068 [JD] reduced control sets (resets, CE, presets) to the absolute minimum to operate, to reduce
-- synthesis LUT overhead in Spartan-6 architecture.
-- 2011/06/11 v0.97.0075 [JD] redesigned all parallel data interfacing ports, and implemented cross-clock strobe logic.
-- 2011/06/12 v0.97.0079 [JD] implemented wr_ack and di_req logic for state 0, and eliminated unnecessary registers reset.
-- 2011/06/17 v0.97.0079 [JD] implemented wr_ack and di_req logic for state 0, and eliminated unnecessary registers reset.
-- 2011/07/16 v1.11.0080 [JD] verified both spi_master and spi_slave in loopback at 50MHz SPI clock.
-- 2011/07/29 v2.00.0110 [JD] FIX: CPHA bugs:
-- - redesigned core clocking to address all CPOL and CPHA configurations.
-- - added CHANGE_EDGE to the FSM register transfer logic, to have MISO change at opposite
-- clock phases from SHIFT_EDGE.
-- Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions
-- for each state, to avoid reported inference problems in some synthesis engines.
-- Streamlined port names and indentation blocks.
-- 2011/08/01 v2.01.0115 [JD] Adjusted 'do_valid_o' pulse width to be 2 'clk_i', as in the master core.
-- Simulated in iSim with the master core for continuous transmission mode.
-- 2011/08/02 v2.02.0120 [JD] Added mux for MISO at reset state, to output di(N-1) at start. This fixed a bug in first bit.
-- The master and slave cores were verified in FPGA with continuous transmission, for all SPI modes.
-- 2011/08/04 v2.02.0121 [JD] Changed minor comment bugs in the combinatorial fsm logic.
-- 2011/08/08 v2.02.0122 [JD] FIX: continuous transfer mode bug. When wren_i is not strobed prior to state 1 (last bit), the
-- sequencer goes to state 0, and then to state 'N' again. This produces a wrong bit-shift for received
-- data. The fix consists in engaging continuous transfer regardless of the user strobing write enable, and
-- sequencing from state 1 to N as long as the master clock is present. If the user does not write new
-- data, the last data word is repeated.
-- 2011/08/08 v2.02.0123 [JD] ISSUE: continuous transfer mode bug, for ignored 'di_req' cycles. Instead of repeating the last data word,
-- the slave will send (others => '0') instead.
-- 2011/08/28 v2.02.0126 [JD] ISSUE: the miso_o MUX that preloads tx_bit when slave is desselected will glitch for CPHA='1'.
-- FIX: added a registered drive for the MUX select that will transfer the tx_reg only after the first tx_reg update.
--
-----------------------------------------------------------------------------------------------------------------------
-- TODO
-- ====
--
-----------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity spi_slave is
Generic (
N : positive := 32; -- 32bit serial word length is default
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
CPHA : std_logic := '0'; -- CPOL = clock polarity, CPHA = clock phase.
PREFETCH : positive := 3); -- prefetch lookahead cycles
Port (
clk_i : in std_logic := 'X'; -- internal interface clock (clocks di/do registers)
spi_ssel_i : in std_logic := 'X'; -- spi bus slave select line
spi_sck_i : in std_logic := 'X'; -- spi bus sck clock (clocks the shift register core)
spi_mosi_i : in std_logic := 'X'; -- spi bus mosi input
spi_miso_o : out std_logic := 'X'; -- spi bus spi_miso_o output
di_req_o : out std_logic; -- preload lookahead data request line
di_i : in std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel load data in (clocked in on rising edge of clk_i)
wren_i : in std_logic := 'X'; -- user data write enable
wr_ack_o : out std_logic; -- write acknowledge
do_valid_o : out std_logic; -- do_o data valid strobe, valid during one clk_i rising edge.
do_o : out std_logic_vector (N-1 downto 0); -- parallel output (clocked out on falling clk_i)
--- debug ports: can be removed for the application circuit ---
do_transfer_o : out std_logic; -- debug: internal transfer driver
wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher
rx_bit_next_o : out std_logic; -- debug: internal rx bit
state_dbg_o : out std_logic_vector (3 downto 0); -- debug: internal state register
sh_reg_dbg_o : out std_logic_vector (N-1 downto 0) -- debug: internal shift register
);
end spi_slave;
--================================================================================================================
-- SYNTHESIS CONSIDERATIONS
-- ========================
-- There are several output ports that are used to simulate and verify the core operation.
-- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing
-- circuitry.
-- The same is valid for the transmit and receive ports. If the receive ports are not mapped, the
-- synthesis tool will remove the receive logic from the generated circuitry.
-- Alternatively, you can remove these ports and related circuitry once the core is verified and
-- integrated to your circuit.
--================================================================================================================
architecture rtl of spi_slave is
-- constants to control FlipFlop synthesis
constant SHIFT_EDGE : std_logic := (CPOL xnor CPHA); -- MOSI data is captured and shifted at this SCK edge
constant CHANGE_EDGE : std_logic := (CPOL xor CPHA); -- MISO data is updated at this SCK edge
------------------------------------------------------------------------------------------
-- GLOBAL RESET:
-- all signals are initialized to zero at GSR (global set/reset) by giving explicit
-- initialization values at declaration. This is needed for all Xilinx FPGAs, and
-- especially for the Spartan-6 and newer CLB architectures, where a local reset can
-- reduce the usability of the slice registers, due to the need to share the control
-- set (RESET/PRESET, CLOCK ENABLE and CLOCK) by all 8 registers in a slice.
-- By using GSR for the initialization, and reducing RESET local init to the really
-- essential, the model achieves better LUT/FF packing and CLB usability.
------------------------------------------------------------------------------------------
-- internal state signals for register and combinatorial stages
signal state_next : natural range N downto 0 := 0; -- state 0 is idle state
signal state_reg : natural range N downto 0 := 0; -- state 0 is idle state
-- shifter signals for register and combinatorial stages
signal sh_next : std_logic_vector (N-1 downto 0);
signal sh_reg : std_logic_vector (N-1 downto 0);
-- mosi and miso connections
signal rx_bit_next : std_logic; -- sample of MOSI input
signal tx_bit_next : std_logic;
signal tx_bit_reg : std_logic; -- drives MISO during sequential logic
signal preload_miso : std_logic; -- controls the MISO MUX
-- buffered di_i data signals for register and combinatorial stages
signal di_reg : std_logic_vector (N-1 downto 0);
-- internal wren_i stretcher for fsm combinatorial stage
signal wren : std_logic;
signal wr_ack_next : std_logic := '0';
signal wr_ack_reg : std_logic := '0';
-- buffered do_o data signals for register and combinatorial stages
signal do_buffer_next : std_logic_vector (N-1 downto 0);
signal do_buffer_reg : std_logic_vector (N-1 downto 0);
-- internal signal to flag transfer to do_buffer_reg
signal do_transfer_next : std_logic := '0';
signal do_transfer_reg : std_logic := '0';
-- internal input data request signal
signal di_req_next : std_logic := '0';
signal di_req_reg : std_logic := '0';
-- cross-clock do_valid_o logic
signal do_valid_next : std_logic := '0';
signal do_valid_A : std_logic := '0';
signal do_valid_B : std_logic := '0';
signal do_valid_C : std_logic := '0';
signal do_valid_D : std_logic := '0';
signal do_valid_o_reg : std_logic := '0';
-- cross-clock di_req_o logic
signal di_req_o_next : std_logic := '0';
signal di_req_o_A : std_logic := '0';
signal di_req_o_B : std_logic := '0';
signal di_req_o_C : std_logic := '0';
signal di_req_o_D : std_logic := '0';
signal di_req_o_reg : std_logic := '0';
begin
--=============================================================================================
-- GENERICS CONSTRAINTS CHECKING
--=============================================================================================
-- minimum word width is 8 bits
assert N >= 8
report "Generic parameter 'N' error: SPI shift register size needs to be 8 bits minimum"
severity FAILURE;
-- maximum prefetch lookahead check
assert PREFETCH <= N-5
report "Generic parameter 'PREFETCH' error: lookahead count out of range, needs to be N-5 maximum"
severity FAILURE;
--=============================================================================================
-- GENERATE BLOCKS
--=============================================================================================
--=============================================================================================
-- DATA INPUTS
--=============================================================================================
-- connect rx bit input
rx_bit_proc : rx_bit_next <= spi_mosi_i;
--=============================================================================================
-- CROSS-CLOCK PIPELINE TRANSFER LOGIC
--=============================================================================================
-- do_valid_o and di_req_o strobe output logic
-- this is a delayed pulse generator with a ripple-transfer FFD pipeline, that generates a
-- fixed-length delayed pulse for the output flags, at the parallel clock domain
out_transfer_proc : process ( clk_i, do_transfer_reg, di_req_reg,
do_valid_A, do_valid_B, do_valid_D,
di_req_o_A, di_req_o_B, di_req_o_D) is
begin
if clk_i'event and clk_i = '1' then -- clock at parallel port clock
-- do_transfer_reg -> do_valid_o_reg
do_valid_A <= do_transfer_reg; -- the input signal must be at least 2 clocks long
do_valid_B <= do_valid_A; -- feed it to a ripple chain of FFDs
do_valid_C <= do_valid_B;
do_valid_D <= do_valid_C;
do_valid_o_reg <= do_valid_next; -- registered output pulse
--------------------------------
-- di_req_reg -> di_req_o_reg
di_req_o_A <= di_req_reg; -- the input signal must be at least 2 clocks long
di_req_o_B <= di_req_o_A; -- feed it to a ripple chain of FFDs
di_req_o_C <= di_req_o_B;
di_req_o_D <= di_req_o_C;
di_req_o_reg <= di_req_o_next; -- registered output pulse
end if;
-- generate a 2-clocks pulse at the 3rd clock cycle
do_valid_next <= do_valid_A and do_valid_B and not do_valid_D;
di_req_o_next <= di_req_o_A and di_req_o_B and not di_req_o_D;
end process out_transfer_proc;
-- parallel load input registers: data register and write enable
in_transfer_proc: process (clk_i, wren_i, wr_ack_reg) is
begin
-- registered data input, input register with clock enable
if clk_i'event and clk_i = '1' then
if wren_i = '1' then
di_reg <= di_i; -- parallel data input buffer register
end if;
end if;
-- stretch wren pulse to be detected by spi fsm (ffd with sync preset and sync reset)
if clk_i'event and clk_i = '1' then
if wren_i = '1' then -- wren_i is the sync preset for wren
wren <= '1';
elsif wr_ack_reg = '1' then -- wr_ack is the sync reset for wren
wren <= '0';
end if;
end if;
end process in_transfer_proc;
--=============================================================================================
-- REGISTER TRANSFER PROCESSES
--=============================================================================================
-- fsm state and data registers change on spi SHIFT_EDGE
core_reg_proc : process (spi_sck_i, spi_ssel_i) is
begin
-- FFD registers clocked on SHIFT edge and cleared on idle (spi_ssel_i = 1)
-- state fsm register (fdr)
if spi_ssel_i = '1' then -- async clr
state_reg <= 0; -- state falls back to idle when slave not selected
elsif spi_sck_i'event and spi_sck_i = SHIFT_EDGE then -- on SHIFT edge, update state register
state_reg <= state_next; -- core fsm changes state with spi SHIFT clock
end if;
-- FFD registers clocked on SHIFT edge
-- rtl core registers (fd)
if spi_sck_i'event and spi_sck_i = SHIFT_EDGE then -- on fsm state change, update all core registers
sh_reg <= sh_next; -- core shift register
do_buffer_reg <= do_buffer_next; -- registered data output
do_transfer_reg <= do_transfer_next; -- cross-clock transfer flag
di_req_reg <= di_req_next; -- input data request
wr_ack_reg <= wr_ack_next; -- wren ack for data load synchronization
end if;
-- FFD registers clocked on CHANGE edge and cleared on idle (spi_ssel_i = 1)
-- miso MUX preload control register (fdp)
if spi_ssel_i = '1' then -- async preset
preload_miso <= '1'; -- miso MUX sees top bit of parallel input when slave not selected
elsif spi_sck_i'event and spi_sck_i = CHANGE_EDGE then -- on CHANGE edge, change to tx_reg output
preload_miso <= spi_ssel_i; -- miso MUX sees tx_bit_reg when it is driven by SCK
end if;
-- FFD registers clocked on CHANGE edge
-- tx_bit register (fd)
if spi_sck_i'event and spi_sck_i = CHANGE_EDGE then
tx_bit_reg <= tx_bit_next; -- update MISO driver from the MSb
end if;
end process core_reg_proc;
--=============================================================================================
-- COMBINATORIAL LOGIC PROCESSES
--=============================================================================================
-- state and datapath combinatorial logic
core_combi_proc : process ( sh_reg, sh_next, state_reg, tx_bit_reg, rx_bit_next, do_buffer_reg,
do_transfer_reg, di_reg, di_req_reg, wren, wr_ack_reg) is
begin
-- all output signals are assigned to (avoid latches)
sh_next <= sh_reg; -- shift register
tx_bit_next <= tx_bit_reg; -- MISO driver
do_buffer_next <= do_buffer_reg; -- output data buffer
do_transfer_next <= do_transfer_reg; -- output data flag
wr_ack_next <= wr_ack_reg; -- write enable acknowledge
di_req_next <= di_req_reg; -- data input request
state_next <= state_reg; -- fsm control state
case state_reg is
when (N) => -- deassert 'di_rdy' and stretch do_valid
wr_ack_next <= '0'; -- acknowledge data in transfer
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
tx_bit_next <= sh_reg(N-1); -- output next MSbit
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
state_next <= state_reg - 1; -- update next state at each sck pulse
when (N-1) downto (PREFETCH+3) => -- remove 'do_transfer' and shift bits
do_transfer_next <= '0'; -- reset 'do_valid' transfer signal
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
wr_ack_next <= '0'; -- remove data load ack for all but the load stages
tx_bit_next <= sh_reg(N-1); -- output next MSbit
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
state_next <= state_reg - 1; -- update next state at each sck pulse
when (PREFETCH+2) downto 3 => -- raise prefetch 'di_req_o' signal
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
wr_ack_next <= '0'; -- remove data load ack for all but the load stages
tx_bit_next <= sh_reg(N-1); -- output next MSbit
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
state_next <= state_reg - 1; -- update next state at each sck pulse
when 2 => -- transfer received data to do_buffer_reg on next cycle
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
wr_ack_next <= '0'; -- remove data load ack for all but the load stages
tx_bit_next <= sh_reg(N-1); -- output next MSbit
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
do_transfer_next <= '1'; -- signal transfer to do_buffer on next cycle
do_buffer_next <= sh_next; -- get next data directly into rx buffer
state_next <= state_reg - 1; -- update next state at each sck pulse
when 1 => -- transfer rx data to do_buffer and restart if new data is written
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
state_next <= N; -- next state is top bit of new data
if wren = '1' then -- load tx register if valid data present at di_reg
wr_ack_next <= '1'; -- acknowledge data in transfer
sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits
tx_bit_next <= di_reg(N-1); -- first output bit comes from the MSb of parallel data
else
wr_ack_next <= '0'; -- no data reload for continuous transfer mode
sh_next(N-1 downto 1) <= (others => '0'); -- clear transmit shift register
tx_bit_next <= '0'; -- send ZERO
end if;
when 0 => -- idle state: start and end of transmission
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits
tx_bit_next <= di_reg(N-1); -- first output bit comes from the MSb of parallel data
wr_ack_next <= '1'; -- acknowledge data in transfer
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
do_transfer_next <= '0'; -- clear signal transfer to do_buffer
state_next <= N; -- next state is top bit of new data
when others =>
state_next <= 0; -- safe state
end case;
end process core_combi_proc;
--=============================================================================================
-- OUTPUT LOGIC PROCESSES
--=============================================================================================
-- data output processes
do_o_proc : do_o <= do_buffer_reg; -- do_o always available
do_valid_o_proc: do_valid_o <= do_valid_o_reg; -- copy registered do_valid_o to output
di_req_o_proc: di_req_o <= di_req_o_reg; -- copy registered di_req_o to output
wr_ack_o_proc: wr_ack_o <= wr_ack_reg; -- copy registered wr_ack_o to output
-----------------------------------------------------------------------------------------------
-- MISO driver process: preload top bit of parallel data to MOSI at reset
-----------------------------------------------------------------------------------------------
-- this is a MUX that selects the combinatorial next tx bit at reset, and the registered tx bit
-- at sequential operation. The mux gives us a preload of the first bit, simplifying the shifter logic.
spi_miso_o_proc: process (preload_miso, tx_bit_reg, di_reg) is
begin
if preload_miso = '1' then
spi_miso_o <= di_reg(N-1); -- copy top bit of parallel data at reset
else
spi_miso_o <= tx_bit_reg; -- copy top bit of shifter at sequential operation
end if;
end process spi_miso_o_proc;
--=============================================================================================
-- DEBUG LOGIC PROCESSES
--=============================================================================================
-- these signals are useful for verification, and can be deleted after debug.
do_transfer_proc: do_transfer_o <= do_transfer_reg;
state_debug_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 4)); -- export internal state to debug
rx_bit_next_proc: rx_bit_next_o <= rx_bit_next;
wren_o_proc: wren_o <= wren;
sh_reg_debug_proc: sh_reg_dbg_o <= sh_reg; -- export sh_reg to debug
end architecture rtl;
| gpl-3.0 | 0354bd42747e1c76f3021913c78813cb | 0.478598 | 4.756177 | false | false | false | false |
albayaty/Video-Game-Engine | EDK/NES-Controller/nes_controller.vhd | 1 | 5,138 | -- ==============================================
-- Copyright © 2014 Ali M. Al-Bayaty
--
-- Video-Game-Engine is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- any later version.
--
-- Video-Game-Engine is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- ==============================================
--
-- Video Game Engine Project
-- ( EDK: NES Controller VHDL )
--
-- MSEE student: Ali M. Al-Bayaty
-- EE659: System-On-Chip
-- Personal website: <http://albayaty.github.io/>
-- Source code link: <https://github.com/albayaty/Video-Game-Engine.git>
--
-- ==============================================
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity nes_controller is
Port ( reset : in STD_LOGIC;
clk_50 : in STD_LOGIC;
led : out STD_LOGIC_VECTOR (7 downto 0):= "00000000";
--nes_latch : inout STD_LOGIC;
nes_latch : out STD_LOGIC;
--nes_clk : inout STD_LOGIC;
nes_clk : out STD_LOGIC;
nes_data : in STD_LOGIC);
end nes_controller;
architecture Behavioral of nes_controller is
signal pulses: integer := 1;
signal neslatch, nesclk: std_logic;
type statetype is (state1, state2);
signal currentstate, nextstate : statetype;
begin
-- Generating 12us width signal (nes_latch), and 6us duty cycle (nes_clk)
-- Sys clk= 50mhz = 20ns = 0.02 us
-- Latch clk = sys clk * 600 iterations (for high)
-- Pulses clk = sys clk * 300 and another 300 iterations (for high and low)
process(clk_50, reset)
variable counter: integer;
variable nes_latch_gen: std_logic;
variable nes_clk_gen: std_logic;
begin
if ( reset = '1') then
nes_latch <= '0';
neslatch <= '0';
nes_latch_gen := '1';
nes_clk <= '0';
nesclk <= '0';
nes_clk_gen := '0';
counter := 1;
pulses <= 1;
elsif (rising_edge(clk_50)) then
-- Generating the nes_latch:
if ( nes_latch_gen = '1' ) then
if ( counter <= 600 ) then
nes_latch <= '1';
neslatch <= '1';
counter := counter + 1;
elsif ( counter > 600 and counter <= 900 ) then
nes_latch <= '0';
neslatch <= '0';
counter := counter + 1;
elsif ( counter > 900 ) then
nes_latch <= '0';
neslatch <= '0';
nes_latch_gen := '0';
nes_clk_gen := '1';
counter := 1;
--pulses <= 1;
end if;
-- Generating the nes_clk:
elsif ( nes_clk_gen = '1' ) then
if ( counter <= 300 ) then
nes_clk <= '1';
nesclk <= '1';
counter := counter + 1;
elsif ( counter > 300 and counter <= 600 ) then
nes_clk <= '0';
nesclk <= '0';
counter := counter + 1;
elsif ( counter > 600 and pulses <= 7 ) then
counter := 1;
pulses <= pulses + 1;
elsif ( pulses > 7 ) then
nes_clk <= '0';
nesclk <= '0';
nes_latch_gen := '1';
nes_clk_gen := '0';
counter := 1;
pulses <= 1;
end if;
end if;
end if;
end process;
-- Starting of the FSM:
cst: process(clk_50, reset)
begin
if ( reset = '1') then
currentstate <= state1;
elsif (rising_edge(clk_50)) then
currentstate <= nextstate;
end if;
end process;
nst: process(currentstate, nes_data, neslatch, nesclk, pulses)
begin
case currentstate is
when state1 =>
if ( neslatch = '1' ) then
led(7) <= not nes_data;
nextstate <= state2;
else
led(7) <= '0';
nextstate <= state2;
end if;
--nextstate <= state2;
when state2 =>
--nextstate <= state2;
if ( nesclk = '1' and pulses = 1 ) then
led(6) <= not nes_data;
nextstate <= state2;
elsif ( nesclk = '1' and pulses = 2 ) then
led(5) <= not nes_data;
nextstate <= state2;
elsif ( nesclk = '1' and pulses = 3 ) then
led(4) <= not nes_data;
nextstate <= state2;
elsif ( nesclk = '1' and pulses = 4 ) then
led(3) <= not nes_data;
nextstate <= state2;
elsif ( nesclk = '1' and pulses = 5 ) then
led(2) <= not nes_data;
nextstate <= state2;
elsif ( nesclk = '1' and pulses = 6 ) then
led(1) <= not nes_data;
nextstate <= state2;
elsif ( nesclk = '1' and pulses = 7 ) then
led(0) <= not nes_data;
nextstate <= state1;
end if;
end case;
end process;
end Behavioral;
| gpl-3.0 | e2fe423ec522281eccf026c67af59552 | 0.581857 | 3.282428 | false | false | false | false |
zhlinh/vhdl_course | Assignment/FREQ_CNT/FREQ_CNT.vhd | 1 | 4,754 | --Top Entity
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY FREQ_CNT IS
PORT(
RST: IN STD_LOGIC;
CLK_IN_1HZ: IN STD_LOGIC;
CLK_DISP: IN STD_LOGIC;
TEST_CLK: IN STD_LOGIC;
MEASURE_CLK: IN STD_LOGIC;
CHOOSE: IN STD_LOGIC;
DATA_RANGE: IN STD_LOGIC;
BEEP: OUT STD_LOGIC;
RANGE_DISP: OUT STD_LOGIC;
DATA2LED: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
SEL2LED: OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END ENTITY FREQ_CNT;
ARCHITECTURE ART OF FREQ_CNT IS
COMPONENT DIV_FREQ IS
PORT( CLK_IN_1HZ: IN STD_LOGIC;
RST: IN STD_LOGIC;
CLK_OUT_05HZ: OUT STD_LOGIC);
END COMPONENT;
COMPONENT SEL_SIGNAL IS
PORT( TEST_CLK: IN STD_LOGIC;
MEASURE_CLK: IN STD_LOGIC;
CHOOSE: IN STD_LOGIC;
CLK: OUT STD_LOGIC);
END COMPONENT;
COMPONENT COUNT IS
PORT( CLK: IN STD_LOGIC;
CLK_OUT_05HZ: IN STD_LOGIC;
RST: IN STD_LOGIC;
D1: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
D2: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
D3: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
D4: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CARRY: OUT STD_LOGIC;
READ_EN: OUT STD_LOGIC);
END COMPONENT;
COMPONENT ALERT IS
PORT( DATA_RANGE: IN STD_LOGIC;
CARRY_LABEL: IN STD_LOGIC;
D1_IN: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
D2_IN: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
D3_IN: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
D4_IN: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
D1_OUT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
D2_OUT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
D3_OUT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
BEEP: OUT STD_LOGIC;
RANGE_DISP: OUT STD_LOGIC);
END COMPONENT;
COMPONENT D_LATCH IS
PORT( LATCH_EN: IN STD_LOGIC;
D1_IN: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
D2_IN: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
D3_IN: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
D1_OUT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
D2_OUT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
D3_OUT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
COMPONENT LED_DISP IS
PORT( CLK_DISP: IN STD_LOGIC;
DATA_IN_1: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DATA_IN_2: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DATA_IN_3: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DATA2LED: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
SEL2LED: OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END COMPONENT;
SIGNAL WIRE1: STD_LOGIC;
SIGNAL WIRE2: STD_LOGIC;
SIGNAL WIRE3: STD_LOGIC;
SIGNAL WIRE4: STD_LOGIC;
SIGNAL WIRE_C_D1: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL WIRE_C_D2: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL WIRE_C_D3: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL WIRE_C_D4: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL WIRE_A_D1: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL WIRE_A_D2: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL WIRE_A_D3: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL WIRE_L_D1: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL WIRE_L_D2: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL WIRE_L_D3: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
INST_DIV_FREQ: DIV_FREQ
PORT MAP(CLK_IN_1HZ => CLK_IN_1HZ,
RST => RST,
CLK_OUT_05HZ => WIRE1);
INST_SEL_SIGNAL: SEL_SIGNAL
PORT MAP(TEST_CLK => TEST_CLK,
MEASURE_CLK => MEASURE_CLK,
CHOOSE => CHOOSE,
CLK => WIRE2);
INST_COUNT: COUNT
PORT MAP(CLK => WIRE2,
CLK_OUT_05HZ => WIRE1,
RST => RST,
D1 => WIRE_C_D1,
D2 => WIRE_C_D2,
D3 => WIRE_C_D3,
D4 => WIRE_C_D4,
CARRY => WIRE3,
READ_EN => WIRE4);
INST_ALERT: ALERT
PORT MAP(DATA_RANGE => DATA_RANGE,
CARRY_LABEL => WIRE3,
D1_IN => WIRE_C_D1,
D2_IN => WIRE_C_D2,
D3_IN => WIRE_C_D3,
D4_IN => WIRE_C_D4,
D1_OUT => WIRE_A_D1,
D2_OUT => WIRE_A_D2,
D3_OUT => WIRE_A_D3,
BEEP => BEEP,
RANGE_DISP => RANGE_DISP);
INST_D_LATCH: D_LATCH
PORT MAP(LATCH_EN => WIRE4,
D1_IN => WIRE_A_D1,
D2_IN => WIRE_A_D2,
D3_IN => WIRE_A_D3,
D1_OUT => WIRE_L_D1,
D2_OUT => WIRE_L_D2,
D3_OUT => WIRE_L_D3);
INST_LED_DISP: LED_DISP
PORT MAP(CLK_DISP => CLK_DISP,
DATA_IN_1 => WIRE_L_D1,
DATA_IN_2 => WIRE_L_D2,
DATA_IN_3 => WIRE_L_D3,
DATA2LED => DATA2LED,
SEL2LED => SEL2LED);
END ARCHITECTURE ART;
| apache-2.0 | 1501780ef8dfc11bfc7614f7e12db78b | 0.546277 | 2.667789 | false | false | false | false |
jz0229/open-ephys-pcie | serdes-interface/firmware/ipcore_dir/pll.vhd | 2 | 6,491 | -- file: pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____84.000______0.000______50.0______438.095____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity pll is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end pll;
architecture xilinx of pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "pll,clk_wiz_v3_6,{component_name=pll,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 25,
CLKFX_MULTIPLY => 21,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 10.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => RESET,
-- Unused pin, tie low
DSSEN => '0');
LOCKED <= locked_internal;
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfb,
I => clk0);
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkfx);
end xilinx;
| mit | 5b4321eac61f1cac35d5f7a3a31d5ecc | 0.554922 | 4.264783 | false | false | false | false |
aylons/concordic | hdl/modules/cordic_vectoring/cordic_vectoring_wb.vhd | 1 | 9,110 | -------------------------------------------------------------------------------
-- Title : Wishbonized vectoring CORDIC
-- Project :
-------------------------------------------------------------------------------
-- File : cordic_vectoring_wb.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-09-03
-- Last update: 2014-11-19
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Wishbonized version of the CORDIC in vectoring mode. This
-- module is transparent for both TGD and ADR, but to reduce area use, it may
-- me set to only accept a maximum number of simultaneous data points being
-- calculated. It may also accept parallel or serial I/Q data.
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-09-03 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
use work.wb_stream_pkg.all;
-------------------------------------------------------------------------------
-- Input data structure:
-- I = (g_width*2)-1 downto g_width
-- Q = g_width-1 downto 0;
-- Output data structure:
-- mag = (g_width*2)-1 downto g_width
-- phase = g_width-1 downto 0
entity cordic_vectoring_wb is
generic (
g_stages : natural := 32;
g_width : natural := 32;
g_simultaneous : natural := 4;
g_parallel : boolean := true;
g_tgd_width : natural := 4;
g_adr_width : natural := 3;
g_input_buffer : natural := 4;
g_output_buffer : natural := 2
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
ce_i : in std_logic;
snk_i : in t_wbs_sink_in;
snk_o : out t_wbs_sink_out;
src_i : in t_wbs_source_in;
src_o : out t_wbs_source_out
);
end entity cordic_vectoring_wb;
-------------------------------------------------------------------------------
architecture str of cordic_vectoring_wb is
signal data_sink, data_source : std_logic_vector(g_width*2-1 downto 0) := (others => '0');
signal metadata_sink, metadata_source : std_logic_vector(g_tgd_width + g_adr_width - 1 downto 0);
signal I : std_logic_vector(g_width-1 downto 0) := (others => '0');
signal Q : std_logic_vector(g_width-1 downto 0) := (others => '0');
signal mag : std_logic_vector(g_width-1 downto 0) := (others => '0');
signal phase : std_logic_vector(g_width-1 downto 0) := (others => '0');
signal tgd_sink : std_logic_vector(g_tgd_width-1 downto 0) := (others => '0');
signal adr_sink : std_logic_vector(g_adr_width-1 downto 0) := (others => '0');
signal valid_sink : std_logic := '0';
signal tgd_source : std_logic_vector(g_tgd_width-1 downto 0) := (others => '0');
signal adr_source : std_logic_vector(g_adr_width-1 downto 0) := (others => '0');
signal valid_source : std_logic := '0';
signal source_req : std_logic;
signal ack_sink : std_logic;
signal ack_source : std_logic;
signal full_meta : std_logic;
signal rst_n : std_logic;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
component cordic_vectoring_slv is
generic (
g_stages : natural;
g_width : natural);
port (
x_i : in std_logic_vector(g_width-1 downto 0) := (others => '0');
y_i : in std_logic_vector(g_width-1 downto 0) := (others => '0');
clk_i : in std_logic;
ce_i : in std_logic;
valid_i : in std_logic;
rst_i : in std_logic;
mag_o : out std_logic_vector(g_width-1 downto 0) := (others => '0');
phase_o : out std_logic_vector(g_width-1 downto 0) := (others => '0');
valid_o : out std_logic);
end component cordic_vectoring_slv;
component decoupled_fifo is
generic (
g_fifo_width : natural;
g_fifo_depth : natural);
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
d_i : in std_logic_vector(g_fifo_width-1 downto 0);
we_i : in std_logic;
rd_i : in std_logic;
full_o : out std_logic;
d_o : out std_logic_vector(g_fifo_width-1 downto 0);
valid_o : out std_logic);
end component decoupled_fifo;
component generic_shiftreg_fifo is
generic (
g_data_width : integer;
g_size : integer);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
full_o : out std_logic;
almost_full_o : out std_logic;
q_valid_o : out std_logic);
end component generic_shiftreg_fifo;
component xwb_stream_sink is
generic (
g_data_width : natural;
g_addr_width : natural;
g_tgd_width : natural;
g_buffer_depth : natural);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
snk_i : in t_wbs_sink_in;
snk_o : out t_wbs_sink_out;
addr_o : out std_logic_vector(g_adr_width-1 downto 0);
data_o : out std_logic_vector(g_data_width-1 downto 0);
tgd_o : out std_logic_vector(g_tgd_width-1 downto 0);
error_o : out std_logic;
dvalid_o : out std_logic;
dreq_i : in std_logic);
end component xwb_stream_sink;
component xwb_stream_source is
generic (
g_data_width : natural;
g_addr_width : natural;
g_tgd_width : natural;
g_buffer_depth : natural);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
src_i : in t_wbs_source_in;
src_o : out t_wbs_source_out;
addr_i : in std_logic_vector(g_adr_width-1 downto 0);
data_i : in std_logic_vector(g_data_width-1 downto 0);
tgd_i : in std_logic_vector(g_tgd_width-1 downto 0);
dvalid_i : in std_logic;
error_i : in std_logic;
dreq_o : out std_logic);
end component xwb_stream_source;
begin -- architecture str
rst_n <= not(rst_i);
cmp_wb_sink : xwb_stream_sink
generic map (
g_data_width => g_width*2,
g_addr_width => g_adr_width,
g_tgd_width => g_tgd_width,
g_buffer_depth => g_input_buffer)
port map (
clk_i => clk_i,
rst_n_i => rst_n,
snk_i => snk_i,
snk_o => snk_o,
addr_o => adr_sink,
data_o => data_sink,
tgd_o => tgd_sink,
error_o => open, -- no error treatment
dvalid_o => valid_sink,
dreq_i => ack_sink);
I <= data_sink(g_width*2-1 downto g_width);
Q <= data_sink(g_width-1 downto 0);
cmp_cordic : cordic_vectoring_slv
generic map (
g_stages => g_stages,
g_width => g_width)
port map (
x_i => I,
y_i => Q,
clk_i => clk_i,
ce_i => ce_i,
valid_i => ack_sink,
rst_i => rst_i,
mag_o => mag,
phase_o => phase,
valid_o => valid_source);
data_source(g_width*2-1 downto g_width) <= mag;
data_source(g_width-1 downto 0) <= phase;
-- Metadata
metadata_sink <= tgd_sink & adr_sink;
ack_sink <= not(full_meta) and ce_i and valid_sink;
ack_source <= source_req and ce_i and valid_source;
-- Stop accepting new data if full
cmp_metadata : decoupled_fifo
generic map(
g_fifo_width => g_adr_width + g_tgd_width,
g_fifo_depth => g_simultaneous)
port map (
rst_n_i => rst_n,
clk_i => clk_i,
d_i => metadata_sink,
we_i => ack_sink,
rd_i => ack_source,
d_o => metadata_source,
full_o => full_meta);
tgd_source <= metadata_source(g_tgd_width + g_adr_width - 1 downto g_adr_width);
adr_source <= metadata_source(g_adr_width - 1 downto 0);
cmp_wb_source : xwb_stream_source
generic map (
g_data_width => g_width*2,
g_addr_width => g_adr_width,
g_tgd_width => g_tgd_width,
g_buffer_depth => g_output_buffer)
port map (
clk_i => clk_i,
rst_n_i => rst_n,
src_i => src_i,
src_o => src_o,
addr_i => adr_source,
data_i => data_source,
tgd_i => tgd_source,
dvalid_i => ack_source,
error_i => '0', --error is only forwarded through TGD
dreq_o => source_req);
end architecture str;
-------------------------------------------------------------------------------
| gpl-3.0 | f32bf5cb9be0392cab46580b00677286 | 0.497036 | 3.351729 | false | false | false | false |
albayaty/Video-Game-Engine | EDK/VGA/20x15/main.vhd | 1 | 4,630 | -- ==============================================
-- Copyright © 2014 Ali M. Al-Bayaty
--
-- Video-Game-Engine is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- any later version.
--
-- Video-Game-Engine is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- ==============================================
--
-- Video Game Engine Project
-- ( EDK: VGA 20x15 Resolution, Main VHDL )
--
-- MSEE student: Ali M. Al-Bayaty
-- EE659: System-On-Chip
-- Personal website: <http://albayaty.github.io/>
-- Source code link: <https://github.com/albayaty/Video-Game-Engine.git>
--
-- ==============================================
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity vga is
port (
clk: in std_logic;
--reset: in std_logic;
hsync, vsync: out std_logic;
rgb: out std_logic_vector(2 downto 0);
we: in std_logic;
--sel: in std_logic_vector(1 downto 0);
add_bus1: in std_logic_vector(8 downto 0);
add_bus2: in std_logic_vector(8 downto 0);
add_bus3: in std_logic_vector(10 downto 0);
data_bus1: in std_logic_vector(4 downto 0);
data_bus2: in std_logic_vector(4 downto 0);
data_bus3: in std_logic_vector(3 downto 0)
);
end vga;
architecture Behavioral of vga is
signal rgb_reg: std_logic_vector(2 downto 0);
signal video_on: std_logic;
signal pixel_x, pixel_y : std_logic_vector(9 downto 0);
-- Foreground Tile-map : 20x15
Type tile_map is array(0 to 299) of std_logic_vector(4 downto 0);
signal fore_map : tile_map; --(RAM 1)
-- Background Tile-map : 20x15
signal back_map : tile_map; --(RAM 2)
-- Sprites-map of 64x32
Type sprites_map is array(0 to 2047) of std_logic_vector(3 downto 0);
signal sprites : sprites_map; -- (RAM 3)
component vgatimehelper
port (
clk, reset : in std_logic;
hsync, vsync : out std_logic;
video_on, p_tick : out std_logic;
pixel_x, pixel_y : out std_logic_vector(9 downto 0));
end component;
signal index, index1, index2: integer;
signal reset: std_logic := '0';
--signal data_buf1: std_logic_vector(4 downto 0);
--signal data_buf2: std_logic_vector(4 downto 0);
--signal data_buf3: std_logic_vector(3 downto 0);
begin
-- instantiate VGA sync circuit
vga_unit: vgatimehelper
port map(clk=>clk, reset=>reset, hsync=>hsync,
vsync=>vsync, video_on=>video_on,
p_tick=>open, pixel_x=>pixel_x, pixel_y=>pixel_y);
-- Creating, reading, and writing RAM 1:
ram1: process
begin
if rising_edge(clk) then
-- write:
if( we = '1' ) then
--fore_map(conv_integer(add_bus1)) <= data_buf1;
fore_map(conv_integer(add_bus1)) <= data_bus1;
end if;
end if;
end process;
-- Creating, reading, and writing RAM 2:
ram2: process
begin
if rising_edge(clk) then
-- write:
if( we = '1' ) then
--back_map(conv_integer(add_bus2)) <= data_buf2;
back_map(conv_integer(add_bus2)) <= data_bus2;
end if;
end if;
end process;
-- Creating, reading, and writing RAM 3:
ram3: process
begin
if rising_edge(clk) then
-- write:
if( we = '1' ) then
--sprites(conv_integer(add_bus3)) <= data_buf3;
sprites(conv_integer(add_bus3)) <= data_bus3;
end if;
end if;
end process;
--data_buf1 <= data_bus1;
--data_buf2 <= data_bus2;
--data_buf3 <= data_bus3;
-- Draw on the LCD screen:
-- Conversion from 640x480 scale to 20x15 scale:
-- from screen to foreground tile-map:
index <= conv_integer(pixel_y(9 downto 5))*20 + conv_integer(pixel_x(9 downto 5));
index1 <= (conv_integer(pixel_y(4 downto 2)))*8 + (conv_integer(pixel_x(4 downto 2))) +
(conv_integer(fore_map(index))*64);
index2 <= (conv_integer(pixel_y(4 downto 2)))*8 + (conv_integer(pixel_x(4 downto 2))) +
(conv_integer(back_map(index))*64);
-- rgb_reg1 <= sprites(index1);
-- rgb_reg2 <= sprites(index2);
rgb_reg <= sprites(index1)(2 downto 0) when sprites(index1)(3) = '0' else sprites(index2)(2 downto 0);
rgb <= rgb_reg when video_on='1' else "000";
end Behavioral;
| gpl-3.0 | 210fde4bcaedfc89359f1fd4c15517b0 | 0.628429 | 3.05343 | false | false | false | false |
Hyvok/HardHeat | sim/rpm_counter/rpm_counter_tb.vhd | 1 | 1,796 | library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rpm_counter_tb is
generic
(
BITS_N : natural := 20;
MIN_RPM_LIM : natural := 2**18;
TEST_RPM : natural := 2**16
);
end entity;
architecture rtl of rpm_counter_tb is
-- Main clock frequency 100 MHz
constant CLK_PERIOD : time := 1 sec / 10e7;
signal clk : std_logic := '0';
signal reset : std_logic;
signal rpm : std_logic;
signal fault : std_logic;
begin
reset <= '1', '0' after 500 ns;
clk_gen: process(clk)
begin
clk <= not clk after CLK_PERIOD / 2;
end process;
DUT_inst: entity work.rpm_counter(rtl)
generic map
(
BITS_N => BITS_N,
MIN_RPM_LIM => 2**18,
DEBOUNCE_D => 10000
)
port map
(
clk => clk,
reset => reset,
rpm_in => rpm,
fault_out => fault
);
rpm_gen: process(clk, reset)
variable counter : unsigned(BITS_N - 1 downto 0);
variable start_done : boolean;
begin
if reset = '1' then
counter := (others => '0');
rpm <= '1';
start_done := false;
elsif rising_edge(clk) then
if start_done then
counter := counter + 1;
-- Wait until we get fault indication for no RPM
elsif fault = '1' then
start_done := true;
end if;
if counter > TEST_RPM then
rpm <= not rpm;
counter := (others => '0');
end if;
end if;
end process;
end;
| mit | 5ddf9ff765ec6e983ae17f397b8c4207 | 0.457684 | 4.035955 | false | false | false | false |
jz0229/open-ephys-pcie | serdes-interface/firmware/ipcore_dir/pll/simulation/pll_tb.vhd | 2 | 6,625 | -- file: pll_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity pll_tb is
end pll_tb;
architecture test of pll_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 10.0 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bit of the sampling counter
signal COUNT : std_logic;
-- Status and control signals
signal RESET : std_logic := '0';
signal LOCKED : std_logic;
signal COUNTER_RESET : std_logic := '0';
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(1 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component pll_exdes
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
RESET <= '1';
wait for (PER1*6);
RESET <= '0';
wait until LOCKED = '1';
COUNTER_RESET <= '1';
wait for (PER1*20);
COUNTER_RESET <= '0';
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : pll_exdes
generic map (
TCQ => TCQ)
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT,
-- Status and control signals
RESET => RESET,
LOCKED => LOCKED);
-- Freq Check
end test;
| mit | 7995769aac067c86fb14d70f7cb68bd4 | 0.608755 | 4.254978 | false | false | false | false |
cafe-alpha/wasca | fpga_firmware/abus_avalon_sdram_bridge_tb.vhd | 1 | 20,973 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity abus_avalon_sdram_bridge_tb is
end abus_avalon_sdram_bridge_tb;
architecture Behavioral of abus_avalon_sdram_bridge_tb is
component abus_avalon_sdram_bridge is
port (
clock : in std_logic := '0'; -- clock.clk
abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
abus_waitrequest : out std_logic := '1'; -- .waitrequest
abus_interrupt : out std_logic := '0'; -- .interrupt
abus_direction : out std_logic := '0'; -- .direction
abus_muxing : out std_logic_vector(1 downto 0) := "01"; -- .muxing
abus_disable_out : out std_logic := '0'; -- .disableout
sdram_addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
sdram_ba : out std_logic_vector(1 downto 0); -- .ba
sdram_cas_n : out std_logic; -- .cas_n
sdram_cke : out std_logic; -- .cke
sdram_cs_n : out std_logic; -- .cs_n
sdram_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
sdram_dqm : out std_logic_vector(1 downto 0); -- .dqm
sdram_ras_n : out std_logic; -- .ras_n
sdram_we_n : out std_logic; -- .we_n
sdram_clk : out std_logic;
avalon_sdram_read : in std_logic := '0'; -- avalon_master.read
avalon_sdram_write : in std_logic := '0'; -- .write
avalon_sdram_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_sdram_address : in std_logic_vector(24 downto 0) := (others => '0'); -- .address
avalon_sdram_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_sdram_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_sdram_readdatavalid : out std_logic := '0'; -- .readdatavalid
avalon_regs_read : in std_logic := '0'; -- avalon_master.read
avalon_regs_write : in std_logic := '0'; -- .write
avalon_regs_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_regs_address : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
avalon_regs_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_regs_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_regs_readdatavalid : out std_logic := '0'; -- .readdatavalid
saturn_reset : in std_logic := '0'; -- .saturn_reset
reset : in std_logic := '0' -- reset.reset
);
end component;
component sdram_controller is
port(
-- HOST INTERFACE
wr_addr: in std_logic_vector(23 downto 0);
wr_data: in std_logic_vector(15 downto 0);
wr_enable: in std_logic;
rd_addr: in std_logic_vector(23 downto 0);
rd_data: out std_logic_vector(15 downto 0);
rd_ready: out std_logic;
rd_enable: in std_logic;
busy: out std_logic;
rst_n: in std_logic;
clk: in std_logic;
-- SDRAM SIDE
addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
bank_addr : out std_logic_vector(1 downto 0); -- .ba
cas_n : out std_logic; -- .cas_n
clock_enable : out std_logic; -- .cke
cs_n : out std_logic; -- .cs_n
data : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
data_mask_low: out std_logic;
data_mask_high: out std_logic;
ras_n : out std_logic; -- .ras_n
we_n : out std_logic
);
end component;
----------------------ins
signal clock : std_logic := '0'; -- clock.clk
signal abus_address : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_chipselect : std_logic_vector(2 downto 0) := (others => '1'); -- .chipselect
signal abus_read : std_logic := '1'; -- .read
signal abus_write : std_logic_vector(1 downto 0) := (others => '1'); -- .write
signal avalon_sdram_read : std_logic := '0'; -- avalon_master.read
signal avalon_sdram_write : std_logic := '0'; -- .write
signal avalon_sdram_address : std_logic_vector(24 downto 0) := (others => '0'); -- .address
signal avalon_sdram_writedata : std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
signal avalon_regs_read : std_logic := '0'; -- avalon_master.read
signal avalon_regs_write : std_logic := '0'; -- .write
signal avalon_regs_address : std_logic_vector(7 downto 0) := (others => '0'); -- .address
signal avalon_regs_writedata : std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
signal saturn_reset : std_logic := '0'; -- .saturn_reset
signal reset : std_logic := '0'; -- reset.reset
----------------------outs
signal abus_waitrequest : std_logic := '1'; -- .waitrequest
signal abus_interrupt : std_logic := '0'; -- .interrupt
signal abus_direction : std_logic := '0'; -- .direction
signal abus_muxing : std_logic_vector(1 downto 0) := "01"; -- .muxing
signal abus_disable_out : std_logic := '0'; -- .disableout
signal sdram_addr : std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
signal sdram_ba : std_logic_vector(1 downto 0); -- .ba
signal sdram_cas_n : std_logic; -- .cas_n
signal sdram_cke : std_logic; -- .cke
signal sdram_cs_n : std_logic;
signal sdram_dqm : std_logic_vector(1 downto 0); -- .dqm
signal sdram_ras_n : std_logic; -- .ras_n
signal sdram_we_n : std_logic; -- .we_n
signal sdram_clk : std_logic;
signal avalon_sdram_waitrequest : std_logic := '0'; -- .waitrequest
signal avalon_sdram_readdata : std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
signal avalon_sdram_readdatavalid : std_logic := '0'; -- .readdatavalid
signal avalon_regs_waitrequest : std_logic := '0'; -- .waitrequest
signal avalon_regs_readdata : std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
signal avalon_regs_readdatavalid : std_logic := '0'; -- .readdatavalid
----------------------inouts
signal abus_addressdata : std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
signal sdram_dq : std_logic_vector(15 downto 0) := (others => '0'); -- .dq
signal abus_full_address : std_logic_vector(25 downto 0) := (others => '0');
signal abus_data_in : std_logic_vector(15 downto 0) := (others => '0');
------------- reference controller
signal refer_wr_addr: std_logic_vector(23 downto 0) := (others => '0');
signal refer_wr_data: std_logic_vector(15 downto 0) := (others => '0');
signal refer_wr_enable: std_logic;
signal refer_rd_addr: std_logic_vector(23 downto 0) := (others => '0');
signal refer_rd_data: std_logic_vector(15 downto 0) := (others => '0');
signal refer_rd_ready: std_logic;
signal refer_rd_enable: std_logic := '0';
signal refer_busy: std_logic;
signal refer_rst_n: std_logic := '1';
procedure write_abus_16 (addry : in std_logic_vector(25 downto 0);
datty : in std_logic_vector(15 downto 0);
csy : in std_logic_vector(2 downto 0);
wry : in std_logic_vector(1 downto 0);
signal Abus_Ad : out std_logic_vector(25 downto 0);
signal Abus_Da : out std_logic_vector(15 downto 0);
signal Abus_CS : out std_logic_vector(2 downto 0);
signal Abus_Wri : out std_logic_vector(1 downto 0);
signal Ref_Ad : out std_logic_vector(23 downto 0);
signal Ref_Da : out std_logic_vector(15 downto 0);
signal Ref_Wri : out std_logic
) is
begin
Abus_Ad <= addry;
Ref_Ad <= addry(24 downto 1);
Ref_Da <= datty;
wait for 8620 ps;
Abus_Da <= datty;
wait for 8620 ps;
Abus_CS <= csy;
wait for 8620 ps;
Abus_Wri <= wry;
wait for 4310 ps;
Ref_Wri <= '1';
wait for 8620 ps;
Ref_Wri <= '0';
wait for 159470 ps;
Abus_CS <= "111";
wait for 8620 ps;
Abus_Wri <= "11";
wait for 8620 ps;
end write_abus_16;
procedure read_abus_16 (addry : in std_logic_vector(25 downto 0);
csy : in std_logic_vector(2 downto 0);
signal Abus_Ad : out std_logic_vector(25 downto 0);
signal Abus_CS : out std_logic_vector(2 downto 0);
signal Abus_Re : out std_logic;
signal Ref_Ad : out std_logic_vector(23 downto 0);
signal Ref_Re : out std_logic
) is
begin
Abus_Ad <= addry;
Ref_Ad <= addry(24 downto 1);
wait for 8620 ps;
Abus_CS <= csy;
wait for 8620 ps;
Abus_Re <= '0';
wait for 8620 ps;
Ref_Re <= '1';
wait for 8620 ps;
Ref_Re <= '0';
wait for 172400 ps;
Abus_CS <= "111";
wait for 8620 ps;
Abus_Re <= '1';
wait for 8620 ps;
end read_abus_16;
procedure write_avalon_16 (addry : in std_logic_vector(25 downto 0);
datty : in std_logic_vector(15 downto 0);
signal Ava_Ad : out std_logic_vector(24 downto 0);
signal Ava_Da : out std_logic_vector(15 downto 0);
signal Ava_Wri : out std_logic;
signal Ref_Ad : out std_logic_vector(23 downto 0);
signal Ref_Da : out std_logic_vector(15 downto 0);
signal Ref_Wri : out std_logic
) is
begin
Ava_Ad <= addry(24 downto 0);
Ref_Ad <= addry(24 downto 1);
Ref_Da <= datty;
Ava_Da <= datty;
wait for 8620 ps;
Ava_Wri <= '1';
wait for 8620 ps;
Ref_Wri <= '1';
Ava_Wri <= '0';
wait for 8620 ps;
Ref_Wri <= '0';
end write_avalon_16;
procedure write_avalon_16_regs (addry : in std_logic_vector(7 downto 0);
datty : in std_logic_vector(15 downto 0);
signal Ava_Ad : out std_logic_vector(7 downto 0);
signal Ava_Da : out std_logic_vector(15 downto 0);
signal Ava_Wri : out std_logic
) is
begin
Ava_Ad <= addry;
Ava_Da <= datty;
wait for 8620 ps;
Ava_Wri <= '1';
wait for 8620 ps;
Ava_Wri <= '0';
wait for 8620 ps;
end write_avalon_16_regs;
procedure read_avalon_16 (addry : in std_logic_vector(25 downto 0);
signal Ava_Ad : out std_logic_vector(24 downto 0);
signal Ava_Re : out std_logic;
signal Ref_Ad : out std_logic_vector(23 downto 0);
signal Ref_Re : out std_logic
) is
begin
Ava_Ad <= addry(24 downto 0);
Ref_Ad <= addry(24 downto 1);
wait for 8620 ps;
Ava_Re <= '1';
wait for 8620 ps;
Ref_Re <= '1';
Ava_Re <= '0';
wait for 8620 ps;
Ref_Re <= '0';
end read_avalon_16;
procedure read_avalon_16_regs (addry : in std_logic_vector(7 downto 0);
signal Ava_Ad : out std_logic_vector(7 downto 0);
signal Ava_Re : out std_logic
) is
begin
Ava_Ad <= addry;
wait for 8620 ps;
Ava_Re <= '1';
wait for 8620 ps;
Ava_Re <= '0';
wait for 8620 ps;
end read_avalon_16_regs;
begin
clock <= not clock after 4310 ps; --116 MHz clock
--address/data mux
abus_addressdata <= abus_full_address(5) & abus_full_address(6) & abus_full_address(7) & abus_full_address(14) &
abus_full_address(15) & abus_full_address(12) & abus_full_address(13) & abus_full_address(8) &
abus_full_address(0) & abus_full_address(2) & abus_full_address(3) & abus_full_address(4) &
abus_full_address(9) & abus_full_address(11) & abus_full_address(10) & abus_full_address(1)
when abus_muxing = "10" else
abus_data_in when abus_direction = '0' else
(others => 'Z');
abus_address <= abus_full_address(25 downto 16);
UUT: abus_avalon_sdram_bridge
port map(
clock => clock,
abus_address => abus_address,
abus_addressdata => abus_addressdata,
abus_chipselect => abus_chipselect,
abus_read => abus_read,
abus_write => abus_write,
abus_waitrequest => abus_waitrequest,
abus_interrupt => abus_interrupt,
abus_direction => abus_direction,
abus_muxing => abus_muxing,
abus_disable_out => abus_disable_out,
sdram_addr => sdram_addr,
sdram_ba => sdram_ba,
sdram_cas_n => sdram_cas_n,
sdram_cke => sdram_cke,
sdram_cs_n => sdram_cs_n,
sdram_dq => sdram_dq,
sdram_dqm => sdram_dqm,
sdram_ras_n => sdram_ras_n,
sdram_we_n => sdram_we_n,
sdram_clk => sdram_clk,
avalon_sdram_read => avalon_sdram_read,
avalon_sdram_write => avalon_sdram_write,
avalon_sdram_waitrequest => avalon_sdram_waitrequest,
avalon_sdram_address => avalon_sdram_address,
avalon_sdram_writedata => avalon_sdram_writedata,
avalon_sdram_readdata => avalon_sdram_readdata,
avalon_sdram_readdatavalid => avalon_sdram_readdatavalid,
avalon_regs_read => avalon_regs_read,
avalon_regs_write => avalon_regs_write,
avalon_regs_waitrequest => avalon_regs_waitrequest,
avalon_regs_address => avalon_regs_address,
avalon_regs_writedata => avalon_regs_writedata,
avalon_regs_readdata => avalon_regs_readdata,
avalon_regs_readdatavalid => avalon_regs_readdatavalid,
saturn_reset => saturn_reset,
reset => reset
);
REFER: sdram_controller
port map(
clk => clock,
rst_n => refer_rst_n,
busy => open,
wr_addr => refer_wr_addr,
wr_data => refer_wr_data,
wr_enable => refer_wr_enable,
rd_addr => refer_rd_addr,
rd_data => refer_rd_data,
rd_ready => refer_rd_ready,
rd_enable => refer_rd_enable,
addr => open,
bank_addr => open,
cas_n => open,
clock_enable => open,
cs_n => open,
data => open,
data_mask_low => open,
data_mask_high => open,
ras_n => open,
we_n => open
);
process
begin
refer_rst_n <= '1';
wait for 100ns;
refer_rst_n <= '0';
wait for 100ns;
refer_rst_n <= '1';
wait for 800ns;
wait for 300us; --sdram init time
--setup sniff fifo - only writes on cs1
write_avalon_16_regs(X"E8",X"000A",avalon_regs_address,avalon_regs_writedata,avalon_regs_write); --filter - only write on cs1
--abus normal read
read_abus_16("00"&X"EFAFAE","101",abus_full_address,abus_chipselect,abus_read,refer_rd_addr,refer_rd_enable);
--abus read while autorefresh
wait for 3150ns;
read_abus_16("00"&X"EFAFAE","101",abus_full_address,abus_chipselect,abus_read,refer_rd_addr,refer_rd_enable);
--abus pack write
for w in 0 to 1025 loop
wait for 1 us;
write_abus_16(std_logic_vector(to_unsigned(w*2,26)),X"DADA","101","00",abus_full_address,abus_data_in,abus_chipselect,abus_write,refer_wr_addr,refer_wr_data,refer_wr_enable);
end loop;
wait for 100 us;
--pack read fifo
for w in 0 to 1025 loop
wait for 1 us;
read_avalon_16_regs(X"E0",avalon_regs_address,avalon_regs_read);
--write_avalon_16_regs(X"E6",X"0000",avalon_regs_address,avalon_regs_writedata,avalon_regs_write); --filter - only write on cs1
end loop;
wait for 10ms;
--abus pack write
for w in 0 to 1025 loop
wait for 1 us;
write_abus_16(std_logic_vector(to_unsigned(w*512,26)),X"DADA","101","00",abus_full_address,abus_data_in,abus_chipselect,abus_write,refer_wr_addr,refer_wr_data,refer_wr_enable);
end loop;
wait for 100 us;
--pack read fifo
for w in 0 to 1025 loop
wait for 1 us;
read_avalon_16_regs(X"E0",avalon_regs_address,avalon_regs_read);
--write_avalon_16_regs(X"E6",X"0000",avalon_regs_address,avalon_regs_writedata,avalon_regs_write); --filter - only write on cs1
end loop;
-- --avalon normal write
-- wait for 500ns;
-- write_avalon_16("00"&X"EEE312",X"DADA",avalon_sdram_address,avalon_sdram_writedata,avalon_sdram_write,refer_wr_addr,refer_wr_data,refer_wr_enable);
-- wait for 500ns;
-- --avalon normal read
-- wait for 500ns;
-- read_avalon_16("00"&X"EEE312",avalon_sdram_address,avalon_sdram_read,refer_rd_addr,refer_rd_enable);
-- wait for 500ns;
wait;
end process;
end Behavioral;
| gpl-2.0 | 8485c61a363a75db002bea5098d3a58d | 0.477852 | 3.804281 | false | false | false | false |
suoto/hdlcc | .ci/test_support/test_project/basic_library/clk_en_generator.vhd | 1 | 1,114 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.very_common_pkg.all;
entity clk_en_generator is
generic (
DIVIDER : integer := 10
);
port (
reset : in std_logic;
clk_input : in std_logic;
clk_en : out std_logic
);
end clk_en_generator;
architecture clk_en_generator of clk_en_generator is
signal clk_divided : std_logic;
signal clk_divided0 : std_logic;
begin
clk_divider_u : clock_divider
generic map (
DIVIDER => DIVIDER
)
port map (
reset => reset,
clk_input => clk_input,
clk_output => clk_divided
);
process(clk_input)
begin
if clk_input'event and clk_input = '1' then
clk_divided0 <= clk_divided0;
clk_en <= '0';
if clk_divided = '1' and clk_divided0 = '0' then
clk_en <= '1';
end if;
if reset = '1' then
clk_en <= '0';
end if;
end if;
end process;
end clk_en_generator;
| gpl-3.0 | c0f8c924be761d3aec7c30aa894c7daa | 0.507181 | 3.652459 | false | false | false | false |
jz0229/open-ephys-pcie | oepcie_host_firmware/HDLs/TB_mem_conf_control.vhd | 1 | 4,416 |
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
use work.myDeclare.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TB_mem_conf_control IS
END TB_mem_conf_control;
ARCHITECTURE behavior OF TB_mem_conf_control IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mem_conf_control
PORT(
bus_clk : IN std_logic;
reset : IN std_logic;
user_mem_32_addr : IN std_logic_vector(2 downto 0);
user_w_mem_32_wren : IN std_logic;
user_r_mem_32_rden : IN std_logic;
user_w_mem_32_data : IN std_logic_vector(31 downto 0);
user_r_mem_32_data : OUT std_logic_vector(31 downto 0);
dev_reset_out : out std_logic;
conf_ack : OUT std_logic;
conf_nack : OUT std_logic;
mem_out : out mem_type
);
END COMPONENT;
COMPONENT async_com_control
PORT(
bus_clk : IN std_logic;
reset : IN std_logic;
dev_reset_in : in std_logic;
conf_ack : IN std_logic;
conf_nack : IN std_logic;
conf_done : IN std_logic;
conf_mem_in : in mem_type;
async_fifo_wr_enb : out std_logic;
async_fifo_wr_data : out std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal bus_clk : std_logic := '0';
signal reset : std_logic := '0';
signal user_mem_32_addr : std_logic_vector(2 downto 0) := (others => '0');
signal user_w_mem_32_wren : std_logic := '0';
signal user_r_mem_32_rden : std_logic := '0';
signal user_w_mem_32_data : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal user_r_mem_32_data : std_logic_vector(31 downto 0);
signal conf_ack : std_logic;
signal conf_nack : std_logic;
signal hs_start : std_logic := '0';
signal conf_done : std_logic := '0';
signal async_fifo_wr_enb : std_logic;
signal async_fifo_wr_data : std_logic_vector(7 downto 0);
signal conf_mem : mem_type;
signal dev_reset : std_logic;
-- Clock period definitions
constant bus_clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: mem_conf_control PORT MAP (
bus_clk => bus_clk,
reset => reset,
user_mem_32_addr => user_mem_32_addr,
user_w_mem_32_wren => user_w_mem_32_wren,
user_r_mem_32_rden => user_r_mem_32_rden,
user_w_mem_32_data => user_w_mem_32_data,
user_r_mem_32_data => user_r_mem_32_data,
dev_reset_out => dev_reset,
conf_ack => conf_ack,
conf_nack => conf_nack,
mem_out => conf_mem
);
uut2: async_com_control PORT MAP (
bus_clk => bus_clk,
reset => reset,
dev_reset_in => dev_reset,
conf_ack => conf_ack,
conf_nack => conf_nack,
conf_done => conf_done,
conf_mem_in => conf_mem,
async_fifo_wr_enb => async_fifo_wr_enb,
async_fifo_wr_data => async_fifo_wr_data
);
-- Clock process definitions
bus_clk_process :process
begin
bus_clk <= '0';
wait for bus_clk_period/2;
bus_clk <= '1';
wait for bus_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
user_w_mem_32_wren <= '1';
user_mem_32_addr <= std_logic_vector(to_unsigned(2, 3));
user_w_mem_32_data <= std_logic_vector(to_unsigned(134, 32));
reset <= '1';
-- hold reset state for 100 ns.
wait for 100 ns;
reset <= '0';
user_w_mem_32_wren <= '1';
user_mem_32_addr <= std_logic_vector(to_unsigned(2, 3));
user_w_mem_32_data <= std_logic_vector(to_unsigned(134, 32));
wait for 50 ns;
user_w_mem_32_wren <= '1';
user_mem_32_addr <= std_logic_vector(to_unsigned(1, 3));
user_w_mem_32_data <= std_logic_vector(to_unsigned(152, 32));
wait for 50 ns;
user_w_mem_32_wren <= '1';
user_mem_32_addr <= std_logic_vector(to_unsigned(4, 3));
user_w_mem_32_data <= std_logic_vector(to_unsigned(1, 32));
wait for bus_clk_period*10;
-- insert stimulus here
wait;
end process;
END;
| mit | 105c36cef9b11146eb018187821271f2 | 0.559783 | 3.158798 | false | false | false | false |
Hyvok/HardHeat | sim/adpll/adpll_tb.vhd | 1 | 1,381 | library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adpll_tb is
end entity;
architecture rtl of adpll_tb is
-- Clock frequency 100 MHz
constant CLK_PERIOD : time := 1 sec / 10e7;
-- Reference signal frequency 50 kHz
constant REF_PERIOD : time := 1 sec / 90e3;
signal clk : std_logic := '0';
signal reset : std_logic;
signal ref : std_logic := '0';
begin
DUT_inst: entity work.adpll(rtl)
generic map
(
TDC_N => 13,
FILT_P_SHIFT_N => 0,
FILT_I_SHIFT_N => -5,
ACCUM_BITS_N => 32,
ACCUM_WORD_N => 23,
FILT_INIT_OUT_VAL => 2**11,
FILT_OUT_OFFSET => 2**21,
FILT_OUT_LIMIT => 2**22,
LD_LOCK_N => 20,
LD_ULOCK_N => 16,
LD_LOCK_LIMIT => 100
)
port map
(
clk => clk,
reset => reset,
ref_in => ref
);
reset <= '1', '0' after 500 ns;
clk_gen: process(clk)
begin
clk <= not clk after CLK_PERIOD / 2;
end process;
ref_gen: process(ref)
begin
ref <= not ref after REF_PERIOD / 2;
end process;
end;
| mit | bd61e63092e1c4bd06e0c749321b08ec | 0.443157 | 3.732432 | false | false | false | false |
Hyvok/HardHeat | sim/pid/pid_tb.vhd | 1 | 1,199 | library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pid_tb is
end entity;
architecture rtl of pid_tb is
-- Clock frequency 100 MHz
constant CLK_PERIOD : time := 1 sec / 10e7;
-- Run the filter at 50 kHz
constant UPD_PERIOD : time := 1 sec / 50e3;
signal clk : std_logic := '0';
signal upd : std_logic := '0';
signal reset : std_logic;
signal filt_in : std_logic;
begin
DUT_inst: entity work.pid(rtl)
generic map
(
P_SHIFT_N => 4,
I_SHIFT_N => -2,
BITS_N => 16,
INIT_OUT_VAL => 0
)
port map
(
clk => clk,
reset => reset,
upd_clk_in => upd,
setpoint_in => to_signed(0, 16),
pid_in => to_signed(100, 16)
);
reset <= '1', '0' after 500 ns;
clk_gen: process(clk)
begin
clk <= not clk after CLK_PERIOD / 2;
end process;
upd_gen: process(upd)
begin
upd <= not upd after UPD_PERIOD / 2;
end process;
end;
| mit | 2d7c8d78460196cdd2a5ec6399eb0ff1 | 0.464554 | 3.655488 | false | false | false | false |
kjellhar/ArtixPi | spi_test/src/hdl/spi_slave.vhd | 1 | 4,197 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06/16/2016 04:17:04 AM
-- Design Name:
-- Module Name: spi_slave - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity spi_slave is
Generic (
N : positive := 8
);
Port ( clk : in STD_LOGIC;
-- External SPI signals
spi_ss_n : in STD_LOGIC;
spi_clk : in STD_LOGIC;
spi_mosi : in STD_LOGIC;
spi_miso : out STD_LOGIC;
-- Internal data signals
di : out STD_LOGIC_VECTOR (N-1 downto 0); -- Data received from SPI
do : in STD_LOGIC_VECTOR (N-1 downto 0); -- Data to be transmitted over SPI
data_valid : out std_logic; -- High for one clock cycle to indicate a new word is present
do_wren : in std_logic; -- Write a data word to the transmit register
data_busy : out std_logic); -- High for one clock cycle when the transmission starts.
-- The next data word can be written as soon as this signal goes low.
end spi_slave;
architecture Behavioral of spi_slave is
signal do_buf : std_logic_vector(N-1 downto 0);
signal do_i : std_logic_vector(N-1 downto 0);
-- Signals used in the spi_clk domain
signal di_reg : std_logic_vector(N-1 downto 0);
signal di_buf : std_logic_vector(N-1 downto 0);
signal in_count : integer range 0 to N-1 := 0;
signal di_valid : std_logic;
signal do_reg : std_logic_vector(N-1 downto 0);
signal out_count : integer range 0 to N-1 := 0;
signal do_busy : std_logic;
-- Signals used to sync between spi_clk and clk
signal di_valid_sr : std_logic_vector (0 to 1);
signal do_busy_sr : std_logic_vector (0 to 1);
begin
-- output data buffer
process
begin
wait until rising_edge (clk);
if do_wren='1' then
do_buf <= do;
end if;
end process;
-- Input shift register
process (spi_clk, spi_ss_n)
begin
if spi_ss_n = '1' then
in_count <= 0;
elsif rising_edge(spi_clk) then
in_count <= in_count + 1;
if in_count=7 then
di_buf <= di_reg(N-2 downto 0) & spi_mosi;
else
di_reg <= di_reg(N-2 downto 0) & spi_mosi;
end if;
end if;
end process;
di_valid <= '1' when in_count=7 else '0';
-- output shift register
process (spi_clk, spi_ss_n)
begin
if spi_ss_n = '1' then
out_count <= 0;
elsif falling_edge(spi_clk) then
out_count <= out_count + 1;
if out_count = 0 then
do_reg <= do_buf(N-2 downto 0) & '0';
else
do_reg <= do_reg(N-2 downto 0) & '0';
end if;
end if;
end process;
spi_miso <= do_buf(N-1) when out_count=0 else do_reg(N-1);
do_busy <= '1' when out_count=7 else
'1' when out_count=7 and spi_ss_n='0' else
'0';
-- Sync spi_clk -> clk
process
begin
wait until rising_edge(clk);
di_valid_sr <= di_valid & di_valid_sr(0 to 0);
do_busy_sr <= do_busy & do_busy_sr(0 to 0);
end process;
di <= di_buf;
data_valid <= di_valid_sr(1);
data_busy <= do_busy_sr(1);
end Behavioral;
| gpl-3.0 | 6b61bfc68e9ea4bd24eba551941af224 | 0.508935 | 3.850459 | false | false | false | false |
iamllama/EE2020 | ee2020.ip_user_files/ip/dds_compiler_0/demo_tb/tb_dds_compiler_0.vhd | 1 | 8,589 | --------------------------------------------------------------------------------
-- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Description:
-- This is an example testbench for the DDS Compiler IP core.
-- The testbench has been generated by Vivado to accompany the IP core
-- instance you have generated.
--
-- This testbench is for demonstration purposes only. See note below for
-- instructions on how to use it with your core.
--
-- See the DDS Compiler product guide for further information
-- about this core.
--
--------------------------------------------------------------------------------
-- Using this testbench
--
-- This testbench instantiates your generated DDS Compiler core
-- instance named "dds_compiler_0".
--
-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado
-- documentation for details.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity tb_dds_compiler_0 is
end tb_dds_compiler_0;
architecture tb of tb_dds_compiler_0 is
-----------------------------------------------------------------------
-- Timing constants
-----------------------------------------------------------------------
constant CLOCK_PERIOD : time := 100 ns;
constant T_HOLD : time := 10 ns;
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
-----------------------------------------------------------------------
-- DUT input signals
-----------------------------------------------------------------------
-- General inputs
signal aclk : std_logic := '0'; -- the master clock
-- Phase slave channel signals
signal s_axis_phase_tvalid : std_logic := '0'; -- payload is valid
signal s_axis_phase_tdata : std_logic_vector(23 downto 0) := (others => '0'); -- data payload
-- Data master channel signals
signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal m_axis_data_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- data payload
-----------------------------------------------------------------------
-- Aliases for AXI channel TDATA and TUSER fields
-- These are a convenience for viewing data in a simulator waveform viewer.
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
-- to prevent the simulator optimizing away these signals.
-----------------------------------------------------------------------
-- Phase slave channel alias signals
signal s_axis_phase_tdata_inc : std_logic_vector(21 downto 0) := (others => '0');
-- Data master channel alias signals
signal m_axis_data_tdata_sine : std_logic_vector(11 downto 0) := (others => '0');
signal end_of_simulation : boolean := false;
begin
-----------------------------------------------------------------------
-- Instantiate the DUT
-----------------------------------------------------------------------
dut : entity work.dds_compiler_0
port map (
aclk => aclk
,s_axis_phase_tvalid => s_axis_phase_tvalid
,s_axis_phase_tdata => s_axis_phase_tdata
,m_axis_data_tvalid => m_axis_data_tvalid
,m_axis_data_tdata => m_axis_data_tdata
);
-----------------------------------------------------------------------
-- Generate clock
-----------------------------------------------------------------------
clock_gen : process
begin
aclk <= '0';
if (end_of_simulation) then
wait;
else
wait for CLOCK_PERIOD;
loop
aclk <= '0';
wait for CLOCK_PERIOD/2;
aclk <= '1';
wait for CLOCK_PERIOD/2;
end loop;
end if;
end process clock_gen;
-----------------------------------------------------------------------
-- Generate inputs
-----------------------------------------------------------------------
stimuli : process
begin
-- Drive inputs T_HOLD time after rising edge of clock
wait until rising_edge(aclk);
wait for T_HOLD;
-- Input a constant phase increment each cycle, and run for long enough to produce 5 periods of outputs
for cycle in 0 to 159 loop
s_axis_phase_tvalid <= '1';
s_axis_phase_tdata <= (others => '0'); -- set unused TDATA bits to zero
s_axis_phase_tdata(21 downto 0) <= "0000000000000000000000"; -- constant phase increment
wait for CLOCK_PERIOD;
end loop;
s_axis_phase_tvalid <= '0';
-- End of test
end_of_simulation <= true;
report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
wait;
end process stimuli;
-----------------------------------------------------------------------
-- Check outputs
-----------------------------------------------------------------------
check_outputs : process
variable check_ok : boolean := true;
begin
-- Check outputs T_STROBE time after rising edge of clock
wait until rising_edge(aclk);
wait for T_STROBE;
-- Do not check the output payload values, as this requires the behavioral model
-- which would make this demonstration testbench unwieldy.
-- Instead, check the protocol of the data master channel:
-- check that the payload is valid (not X) when TVALID is high
if m_axis_data_tvalid = '1' then
if is_x(m_axis_data_tdata) then
report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error;
check_ok := false;
end if;
end if;
assert check_ok
report "ERROR: terminating test with failures." severity failure;
end process check_outputs;
-----------------------------------------------------------------------
-- Assign TDATA fields to aliases, for easy simulator waveform viewing
-----------------------------------------------------------------------
-- Phase slave channel alias signals
s_axis_phase_tdata_inc <= s_axis_phase_tdata(21 downto 0);
-- Data master channel alias signals: update these only when they are valid
m_axis_data_tdata_sine <= m_axis_data_tdata(11 downto 0) when m_axis_data_tvalid = '1';
end tb;
| gpl-3.0 | f1648e804502924b86aa20315bb4d93f | 0.561649 | 4.894017 | false | false | false | false |
jz0229/open-ephys-pcie | oepcie_host_firmware/HDLs/TB_async_com_control.vhd | 1 | 2,264 | --------------------------------------------------------------------------------
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.myDeclare.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TB_async_com_control IS
END TB_async_com_control;
ARCHITECTURE behavior OF TB_async_com_control IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT async_com_control
PORT(
bus_clk : IN std_logic;
reset : IN std_logic;
conf_ack : IN std_logic;
conf_nack : IN std_logic;
conf_done : IN std_logic;
async_fifo_wr_enb : out std_logic;
async_fifo_wr_data : out std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal bus_clk : std_logic := '0';
signal reset : std_logic := '0';
signal hs_start : std_logic := '0';
signal conf_ack : std_logic := '0';
signal conf_nack : std_logic := '0';
signal conf_done : std_logic := '0';
signal async_fifo_wr_enb : std_logic;
signal async_fifo_wr_data : std_logic_vector(7 downto 0);
-- Clock period definitions
constant bus_clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: async_com_control PORT MAP (
bus_clk => bus_clk,
reset => reset,
hs_start => hs_start,
conf_ack => conf_ack,
conf_nack => conf_nack,
conf_done => conf_done,
async_fifo_wr_enb => async_fifo_wr_enb,
async_fifo_wr_data => async_fifo_wr_data
);
-- Clock process definitions
bus_clk_process :process
begin
bus_clk <= '0';
wait for bus_clk_period/2;
bus_clk <= '1';
wait for bus_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
wait for 100 ns;
reset <= '0';
wait for bus_clk_period*10;
-- insert stimulus here
wait;
end process;
END;
| mit | 3f3649bca831a54ef0e0eb5355b95a8a | 0.537986 | 3.748344 | false | false | false | false |
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| gpl-3.0 | 011b3382c2d99caabd98c5846e7784ff | 0.945731 | 1.853919 | false | false | false | false |
Hyvok/HardHeat | src/hardheat.vhd | 1 | 4,948 | library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.utils_pkg.all;
entity hardheat is
generic
(
TDC_N : positive;
FILT_P_SHIFT_N : integer;
FILT_I_SHIFT_N : integer;
FILT_INIT_OUT_VAL : positive;
FILT_OUT_OFFSET : natural;
FILT_OUT_LIM : positive;
ACCUM_BITS_N : positive;
ACCUM_WORD_N : positive;
DT_N : positive;
DT_VAL : natural;
LD_LOCK_N : positive;
LD_ULOCK_N : positive;
LD_LOCK_LIMIT : natural;
TEMP_CONV_D : natural;
TEMP_CONV_CMD_D : natural;
TEMP_OW_US_D : positive;
TEMP_PWM_N : positive;
TEMP_PWM_MIN_LVL : natural;
TEMP_PWM_EN_ON_D : natural;
TEMP_P_SHIFT_N : integer;
TEMP_I_SHIFT_N : integer;
TEMP_SETPOINT : integer
);
port
(
clk : in std_logic;
reset : in std_logic;
ref_in : in std_logic;
sig_in : in std_logic;
mod_lvl_in : in unsigned(2 downto 0);
mod_lvl_in_f : in std_logic;
ow_in : in std_logic;
ow_out : out std_logic;
ow_pullup_out : out std_logic;
sig_out : out std_logic;
sig_lh_out : out std_logic;
sig_ll_out : out std_logic;
sig_rh_out : out std_logic;
sig_rl_out : out std_logic;
lock_out : out std_logic;
temp_out : out signed(16 - 1 downto 0);
temp_out_f : out std_logic;
temp_err_out : out std_logic;
pwm_out : out std_logic
);
end entity;
architecture rtl of hardheat is
signal sig : std_logic;
signal deadtime : std_logic;
signal deadtime_n : std_logic;
signal sig_lh : std_logic;
signal sig_ll : std_logic;
signal sig_rh : std_logic;
signal sig_rl : std_logic;
begin
adpll_p: entity work.adpll(rtl)
generic map
(
TDC_N => TDC_N,
FILT_P_SHIFT_N => FILT_P_SHIFT_N,
FILT_I_SHIFT_N => FILT_I_SHIFT_N,
FILT_INIT_OUT_VAL => FILT_INIT_OUT_VAL,
FILT_OUT_OFFSET => FILT_OUT_OFFSET,
FILT_OUT_LIMIT => FILT_OUT_LIM,
ACCUM_BITS_N => ACCUM_BITS_N,
ACCUM_WORD_N => ACCUM_WORD_N,
LD_LOCK_N => LD_LOCK_N,
LD_ULOCK_N => LD_ULOCK_N,
LD_LOCK_LIMIT => LD_LOCK_LIMIT
)
port map
(
clk => clk,
reset => reset,
ref_in => ref_in,
sig_out => sig,
lock_out => lock_out
);
epdm_p: entity work.epdm(rtl)
port map
(
clk => clk,
reset => reset,
mod_lvl_in => mod_lvl_in,
mod_lvl_in_f => mod_lvl_in_f,
sig_in => sig,
sig_lh_out => sig_lh,
sig_ll_out => sig_ll,
sig_rh_out => sig_rh,
sig_rl_out => sig_rl
);
deadtime_gen_p: entity work.deadtime_gen(rtl)
generic map
(
DT_N => DT_N,
DT_VAL => DT_VAL
)
port map
(
clk => clk,
reset => reset,
sig_in => sig,
sig_out => deadtime,
sig_n_out => deadtime_n
);
temp_controller_p: entity work.temp_controller(rtl)
generic map
(
CONV_D => TEMP_CONV_D,
CONV_CMD_D => TEMP_CONV_CMD_D,
OW_US_D => TEMP_OW_US_D,
PWM_N => TEMP_PWM_N,
PWM_MIN_LVL => TEMP_PWM_MIN_LVL,
PWM_EN_ON_D => TEMP_PWM_EN_ON_D,
P_SHIFT_N => TEMP_P_SHIFT_N,
I_SHIFT_N => TEMP_I_SHIFT_N,
TEMP_SETPOINT => TEMP_SETPOINT
)
port map
(
clk => clk,
reset => reset,
ow_in => ow_in,
ow_out => ow_out,
temp_out => temp_out,
temp_out_f => temp_out_f,
pwm_out => pwm_out,
enable_in => '1',
temp_error_out => temp_err_out,
ow_pullup_out => ow_pullup_out
);
sig_lh_out <= sig_lh and not deadtime;
sig_ll_out <= sig_ll and not deadtime_n;
sig_rh_out <= sig_rh and not deadtime_n;
sig_rl_out <= sig_rl and not deadtime;
sig_out <= sig;
end;
| mit | 66a824af10aa2a68ed0e66977f4bbf93 | 0.416128 | 3.585507 | false | false | false | false |
albayaty/Video-Game-Engine | EDK/VGA/40x30/user_logic.vhd | 1 | 14,477 | -- ==============================================
-- Copyright © 2014 Ali M. Al-Bayaty
--
-- Video-Game-Engine is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- any later version.
--
-- Video-Game-Engine is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- ==============================================
--
-- Video Game Engine Project
-- ( EDK: VGA 40x30 Resolution, User Logic VHDL )
--
-- MSEE student: Ali M. Al-Bayaty
-- EE659: System-On-Chip
-- Personal website: <http://albayaty.github.io/>
-- Source code link: <https://github.com/albayaty/Video-Game-Engine.git>
--
-- ==============================================
--
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Wed Oct 19 14:01:59 2011 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 7
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
hsync: out std_logic;
vsync: out std_logic;
rgb: out std_logic_vector(0 to 2);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
component vga
port (
clk: in std_logic;
hsync, vsync: out std_logic;
rgb: out std_logic_vector(0 to 2);
we: in std_logic;
add_bus1: in std_logic_vector(0 to 10);
add_bus2: in std_logic_vector(0 to 10);
add_bus3: in std_logic_vector(0 to 10);
data_bus1: in std_logic_vector(0 to 4);
data_bus2: in std_logic_vector(0 to 4);
data_bus3: in std_logic_vector(0 to 3) );
end component;
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg2 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg3 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg4 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg5 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg6 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg_write_sel : std_logic_vector(0 to 6);
signal slv_reg_read_sel : std_logic_vector(0 to 6);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
vgamodule: vga port map(
clk => Bus2IP_Clk,
hsync => hsync,
vsync => vsync,
rgb => rgb,
we => slv_reg0(31),
add_bus1 => slv_reg1(21 to 31),
add_bus2 => slv_reg2(21 to 31),
add_bus3 => slv_reg3(21 to 31),
data_bus1 => slv_reg4(27 to 31),
data_bus2 => slv_reg5(27 to 31),
data_bus3 => slv_reg6(28 to 31)
);
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(0 to 6);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 6);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5) or Bus2IP_RdCE(6);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
else
case slv_reg_write_sel is
when "1000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg4(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg5(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg6(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6 ) is
begin
case slv_reg_read_sel is
when "1000000" => slv_ip2bus_data <= slv_reg0;
when "0100000" => slv_ip2bus_data <= slv_reg1;
when "0010000" => slv_ip2bus_data <= slv_reg2;
when "0001000" => slv_ip2bus_data <= slv_reg3;
when "0000100" => slv_ip2bus_data <= slv_reg4;
when "0000010" => slv_ip2bus_data <= slv_reg5;
when "0000001" => slv_ip2bus_data <= slv_reg6;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
| gpl-3.0 | b67f260b66cc5a0c1763f111480b0af2 | 0.496132 | 3.894539 | false | false | false | false |
zhlinh/vhdl_course | Assignment/IMG_LSB/MYTYPE.vhd | 1 | 1,359 | --MYTYPE package
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--自定义程序包
PACKAGE MYTYPE IS
SUBTYPE COLOR IS INTEGER RANGE 0 TO 255;
FUNCTION CONV_TO_CHAR (SLV8 :STD_LOGIC_VECTOR (7 DOWNTO 0)) RETURN CHARACTER;
FUNCTION CONV_TO_VECTOR (CHAR :CHARACTER) RETURN STD_LOGIC_VECTOR;
END PACKAGE MYTYPE;
PACKAGE BODY MYTYPE IS
FUNCTION CONV_TO_CHAR (SLV8 :STD_LOGIC_VECTOR (7 DOWNTO 0)) RETURN CHARACTER IS
CONSTANT XMAP :INTEGER :=0;
VARIABLE TEMP :INTEGER :=0;
BEGIN
FOR I IN SLV8'RANGE LOOP
TEMP:=TEMP*2;
CASE SLV8(I) IS
WHEN '0' => NULL;
WHEN '1' => TEMP :=TEMP+1;
WHEN OTHERS => TEMP :=TEMP+XMAP;
END CASE;
END LOOP;
RETURN CHARACTER'VAL(TEMP);
END CONV_TO_CHAR;
FUNCTION CONV_TO_VECTOR (CHAR :CHARACTER) RETURN STD_LOGIC_VECTOR IS
VARIABLE SLV8 :STD_LOGIC_VECTOR (7 DOWNTO 0);
VARIABLE TEMP :INTEGER :=CHARACTER'POS(CHAR);
BEGIN
FOR I IN SLV8'REVERSE_RANGE LOOP
CASE TEMP MOD 2 IS
WHEN 0 => SLV8(I):='0';
WHEN 1 => SLV8(I):='1';
WHEN OTHERS => NULL;
END CASE;
TEMP:=TEMP/2;
END LOOP;
RETURN SLV8;
END CONV_TO_VECTOR;
END MYTYPE;
| apache-2.0 | 88c1f4145cca62bcf6c8b85205f5efd8 | 0.573868 | 3.640541 | false | false | false | false |
sudov/options-accel | final_design/fifo.prj/sol/syn/vhdl/dut_dmul_64ns_64ns_64_6_max_dsp.vhd | 2 | 3,326 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.2
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity dut_dmul_64ns_64ns_64_6_max_dsp is
generic (
ID : integer := 1;
NUM_STAGE : integer := 6;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of dut_dmul_64ns_64ns_64_6_max_dsp is
--------------------- Component ---------------------
component dut_ap_dmul_4_max_dsp is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
dut_ap_dmul_4_max_dsp_u : component dut_ap_dmul_4_max_dsp
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| apache-2.0 | 318e5fc2b2923c44e4355c8ab6fb0257 | 0.483163 | 3.482723 | false | false | false | false |
aylons/concordic | hdl/testbench/mode1/cordic_bench.vhd | 1 | 4,835 | -------------------------------------------------------------------------------
-- Title : Testbench for CORDIC module
-- Project :
-------------------------------------------------------------------------------
-- File : cordic_bench.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-03-21
-- Last update: 2014-07-28
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-03-21 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
use std.textio.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity cordic_bench is
end entity cordic_bench;
architecture test of cordic_bench is
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
constant c_input_freq : real := 100.0e6;
constant c_clock_period : time := 1.0 sec /(2.0*c_input_freq);
constant c_cycles_to_reset : natural := 4;
signal clock : std_logic := '0';
signal reset_n : std_logic := '0';
constant c_width : natural := 24;
constant c_stages : natural := 24;
constant c_cordic_delay : natural := c_stages+1;
signal I_in : std_logic_vector(c_width-1 downto 0) := (others => '0');
signal Q_in : std_logic_vector(c_width-1 downto 0) := (others => '0');
signal mag_out : std_logic_vector(c_width-1 downto 0);
signal phase_out : std_logic_vector(c_width-1 downto 0);
signal valid : std_logic;
signal endoffile : std_logic := '0';
component cordic_vectoring_slv is
generic (
g_stages : natural;
g_width : natural);
port (
x_i : in std_logic_vector(g_width-1 downto 0) := (others => '0');
y_i : in std_logic_vector(g_width-1 downto 0) := (others => '0');
clk_i : in std_logic;
ce_i : in std_logic;
valid_i : in std_logic;
rst_i : in std_logic;
mag_o : out std_logic_vector(g_width-1 downto 0) := (others => '0');
phase_o : out std_logic_vector(g_width-1 downto 0) := (others => '0');
valid_o : out std_logic);
end component cordic_vectoring_slv;
begin
clk_gen : process
begin
clock <= '0';
wait for c_clock_period;
clock <= '1';
wait for c_clock_period;
end process;
rst_gen : process(clock)
variable clock_count : natural := c_cycles_to_reset;
begin
if rising_edge(clock) and clock_count /= 0 then
clock_count := clock_count - 1;
if clock_count = 0 then
reset_n <= '1';
end if;
end if;
end process;
uut : cordic_vectoring_slv
generic map (
g_stages => c_stages,
g_width => c_width)
port map (
x_i => I_in,
y_i => Q_in,
clk_i => clock,
valid_i => '1',
ce_i => '1',
rst_i => '0',
mag_o => mag_out,
phase_o => phase_out,
valid_o => valid);
sample_read : process(clock)
file vect_file : text open read_mode is "vectoring_in.dat";
variable cur_line : line;
variable datain1, datain2 : real;
begin
if rising_edge(clock) then
--Pick samples for vectoring mode
if not endfile(vect_file) then
readline(vect_file, cur_line);
read(cur_line, datain1);
I_in <= std_logic_vector(to_signed(integer(datain1*(2.0**(c_width-1))), c_width));
read(cur_line, datain2);
Q_in <= std_logic_vector(to_signed(integer(datain2*(2.0**(c_width-1))), c_width));
else
endoffile <= '1';
end if;
end if; -- rising_edge
end process sample_read;
signal_write : process(clock)
file vect_file : text open write_mode is "vectoring_out.dat";
variable cur_line : line;
variable mag, phase : integer;
-- variable counter : natural = cordic_delay;
begin
if rising_edge(clock) then
if(endoffile = '0' and valid = '1') then
mag := to_integer(unsigned(mag_out));
write(cur_line, mag);
write(cur_line, string'(" "));
phase := to_integer(signed(phase_out));
write(cur_line, phase);
writeline(vect_file, cur_line);
else
assert (false) report "Input file finished." severity failure;
end if;
end if;
end process signal_write;
end architecture test;
| gpl-3.0 | c7af8a26c7522e519c441691827c14ae | 0.504654 | 3.704981 | false | false | false | false |
zhlinh/vhdl_course | Assignment/LED_CNT/BCD_CNT.vhd | 1 | 1,837 | --BCD Counter Entity
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY BCD_CNT IS
PORT ( CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
DOUT12 : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
);
END ENTITY BCD_CNT;
ARCHITECTURE ART1 OF BCD_CNT IS
SIGNAL BCD_CNT_REG : STD_LOGIC_VECTOR(11 DOWNTO 0);
BEGIN
PROCESS(CLK)
BEGIN
IF(CLK'EVENT AND CLK='1') THEN
DOUT12 <= BCD_CNT_REG;
END IF;
END PROCESS;
PROCESS(CLK,RESET)
BEGIN
IF RESET = '0' THEN
BCD_CNT_REG(3 DOWNTO 0) <= (OTHERS=> '0');
ELSIF(CLK'EVENT AND CLK='1') THEN
--低4位遇9变0
IF (BCD_CNT_REG(3 DOWNTO 0) = "1001") THEN
BCD_CNT_REG(3 DOWNTO 0) <= (OTHERS=> '0');
ELSE
BCD_CNT_REG(3 DOWNTO 0) <= BCD_CNT_REG(3 DOWNTO 0) + 1;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RESET)
BEGIN
IF RESET = '0' THEN
BCD_CNT_REG(7 DOWNTO 4) <= (OTHERS=> '0');
ELSIF(CLK'EVENT AND CLK='1') THEN
--中间4位先判断是否有低4位的进位，有才会计数
IF (BCD_CNT_REG(3 DOWNTO 0) = "1001") THEN
IF (BCD_CNT_REG(7 DOWNTO 4) = "1001") THEN
BCD_CNT_REG(7 DOWNTO 4) <= (OTHERS=> '0');
ELSE
BCD_CNT_REG(7 DOWNTO 4) <= BCD_CNT_REG(7 DOWNTO 4) + 1;
END IF;
ELSE
BCD_CNT_REG(7 DOWNTO 4) <= BCD_CNT_REG(7 DOWNTO 4);
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RESET)
BEGIN
IF RESET = '0' THEN
BCD_CNT_REG(11 DOWNTO 8) <= (OTHERS=> '0');
ELSIF(CLK'EVENT AND CLK='1') THEN
--高4位先判断是否有来自中间4位的进位
IF (BCD_CNT_REG(7 DOWNTO 4) = "1001") THEN
IF (BCD_CNT_REG(11 DOWNTO 8) = "1001") THEN
BCD_CNT_REG(11 DOWNTO 8) <= (OTHERS=> '0');
ELSE
BCD_CNT_REG(11 DOWNTO 8) <= BCD_CNT_REG(11 DOWNTO 8) + 1;
END IF;
ELSE
BCD_CNT_REG(11 DOWNTO 8) <= BCD_CNT_REG(11 DOWNTO 8);
END IF;
END IF;
END PROCESS;
END ARCHITECTURE ART1; | apache-2.0 | ff44179716b9614a5517aec7c3cc3aad | 0.61753 | 2.342667 | false | false | false | false |
jz0229/open-ephys-pcie | oepcie_host_firmware/HDLs/com_scheduler.vhd | 1 | 6,322 | --serialized communication scheduler
--Jie Zhang, MWL MIT
--Description: This headstage scheduler takes an array of 16 bits data and converts into a 12 bits stream for the serilizer
--The length of the 16bits array depends on the number of devices avaliable on the headstage.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.myDeclare.all;
entity com_scheduler is
Port (
clk : in std_logic;
reset : in std_logic;
device_data_array : in device_data_array_type; -- Array of dimension (No. of device x 16bits) data, each 16bits corresponds to 1 device input stream
device_flag_array : in std_logic_vector(0 to NUMBEROFDEVICE-1);
serdes_data_out : out std_logic_vector(11 downto 0);
serdes_valid_out : out std_logic
);
end com_scheduler;
architecture Behavioral of com_scheduler is
--state machines
type schstate_type is (IDLE, CONV_P1, CONV_P2, CONV_P3, CONV_P4); --state machine definition
signal schstate : schstate_type;
signal sample_cnt : unsigned(LOG2MAXSAMPLES-1 downto 0); --keeping track of the current number of sample.
signal device_id_cnt : unsigned(LOG2NUMBEROFDEVICE-1 downto 0); --keeping track of the current device.
signal data_reminder : std_logic_vector(11 downto 0);
signal serdes_data : std_logic_vector(11 downto 0);
signal serdes_valid : std_logic;
begin
--output mapping
serdes_data_out <= serdes_data;
serdes_valid_out <= serdes_valid;
sch_proc : process(clk, reset)
begin
if (reset = '1') then
schstate <= IDLE;
sample_cnt <= (others=>'0');
device_id_cnt <= (others=>'0');
data_reminder <= (others=>'0');
serdes_data <= (others=>'0');
serdes_valid <= '0';
elsif (rising_edge(clk)) then
case schstate is
when IDLE =>
if device_flag_array(0) = '1' then
schstate <= CONV_P1;
else
schstate <= IDLE;
end if;
device_id_cnt <= (others=>'0');
sample_cnt <= (others=>'0');
serdes_valid <= '0';
when CONV_P1 => --16 into 12 with 4 as reminder
if device_id_cnt >= NUMBEROFDEVICE-1 then --if device id reach the max then go to IDLE state
schstate <= IDLE;
else
if device_flag_array(to_integer(device_id_cnt)) = '1' then --check device data avaliable flag
if sample_cnt <= data_length_array(to_integer(device_id_cnt)) then --there is still samples
sample_cnt <= sample_cnt + 1;
else
sample_cnt <= (others=>'0');
device_id_cnt <= device_id_cnt + 1;
end if;
schstate <= CONV_P2;
------ Take new data / rise valie flag ------
data_reminder(3 downto 0) <= device_data_array(to_integer(device_id_cnt))(3 downto 0);
serdes_data <= device_data_array(to_integer(device_id_cnt))(15 downto 4);
serdes_valid <= '1';
---------------------------------------------
else --halt and wait for device data avaliable flag to go high
schstate <= CONV_P1;
serdes_valid <= '0';
end if;
end if;
when CONV_P2 => --4+16 into 12 with 8 as reminder
if device_id_cnt >= NUMBEROFDEVICE-1 then --if device id reach the max then go to IDLE state
schstate <= IDLE; --here need to send the left over 4 bits
serdes_data(11 downto 8) <= data_reminder(3 downto 0);
serdes_data(7 downto 0) <= (others=>'0');
serdes_valid <= '1';
else
if device_flag_array(to_integer(device_id_cnt)) = '1' then --check device data avaliable flag
if sample_cnt <= data_length_array(to_integer(device_id_cnt)) then --there is still samples
sample_cnt <= sample_cnt + 1;
else
sample_cnt <= sample_cnt + 1;
device_id_cnt <= device_id_cnt + 1;
end if;
schstate <= CONV_P3;
------ Take new data / rise valie flag ------
data_reminder(7 downto 0) <= device_data_array(to_integer(device_id_cnt))(7 downto 0);
serdes_data <= device_data_array(to_integer(device_id_cnt))(15 downto 8) & data_reminder(3 downto 0);
serdes_valid <= '1';
---------------------------------------------
else --halt and wait for device data avaliable flag to go high
schstate <= CONV_P2;
end if;
end if;
when CONV_P3 => --8+16 into 12 with 12 as reminder
if device_id_cnt >= NUMBEROFDEVICE-1 then --if device id reach the max then go to IDLE state
schstate <= IDLE; --here need to send the left over 8 bits
serdes_data(11 downto 4) <= data_reminder(7 downto 0);
serdes_data(3 downto 0) <= (others=>'0');
serdes_valid <= '1';
else
if device_flag_array(to_integer(device_id_cnt)) = '1' then --check device data avaliable flag
if sample_cnt <= data_length_array(to_integer(device_id_cnt)) then --there is still samples
sample_cnt <= sample_cnt + 1;
else
sample_cnt <= sample_cnt + 1;
device_id_cnt <= device_id_cnt + 1;
end if;
schstate <= CONV_P4;
------ Take new data / rise valie flag ------
data_reminder(11 downto 0) <= device_data_array(to_integer(device_id_cnt))(11 downto 0);
serdes_data <= device_data_array(to_integer(device_id_cnt))(15 downto 12) & data_reminder(7 downto 0);
serdes_valid <= '1';
---------------------------------------------
else --halt and wait for device data avaliable flag to go high
schstate <= CONV_P3;
end if;
end if;
when CONV_P4 => --12 into 12 with 0 as reminder
if device_id_cnt >= NUMBEROFDEVICE-1 then --if device id reach the max then go to IDLE state
schstate <= IDLE;
else
schstate <= CONV_P1;
end if;
--Do not need to check if the flag is high because we don't take new data at this state
--We also do not need to increase the sample cnt and deivce_id_cnt
------ send the data in the reminder registers ------
data_reminder <= (others=>'0');
serdes_data <= data_reminder(11 downto 0);
serdes_valid <= '1';
-----------------------------------------------------
end case;
end if;
end process;
end Behavioral;
| mit | 8077bde80293da4331ffae559164f0a0 | 0.585891 | 3.610508 | false | false | false | false |
Hyvok/HardHeat | sim/resonant_pfd/resonant_pfd_tb.vhd | 1 | 1,207 | library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity resonant_pfd_tb is
end entity;
architecture rtl of resonant_pfd_tb is
-- Clock frequency 100 MHz
constant CLK_PERIOD : time := 1 sec / 10e7;
-- Reference signal frequency 40 kHz
constant REF_PERIOD : time := 1 sec / 40e3;
-- Output signal frequency 50 kHz
constant SIG_PERIOD : time := 1 sec / 50e3;
signal clk : std_logic := '0';
signal reset : std_logic;
signal ref : std_logic := '0';
signal sig : std_logic := '0';
begin
DUT_inst: entity work.resonant_pfd(rtl)
port map
(
clk => clk,
reset => reset,
ref_in => ref,
sig_in => sig
);
reset <= '1' , '0' after 500 ns;
clk_gen: process(clk)
begin
clk <= not clk after CLK_PERIOD / 2;
end process;
ref_gen: process(ref)
begin
ref <= not ref after REF_PERIOD / 2;
end process;
sig_gen: process(sig)
begin
sig <= not sig after SIG_PERIOD / 2;
end process;
end;
| mit | f208dea2011060ab5e7d1ff2b338f0c3 | 0.514499 | 3.771875 | false | false | false | false |
upci/upci | Projeto/io.vhd | 1 | 3,391 | ---- IO ------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.processor_functions.all;
------------------------------------------------------------------------------------------------------------------
ENTITY io IS
PORT (clk, nrst: IN STD_LOGIC; -- reset ativo em zero
IODR_load: IN STD_LOGIC; -- sinal de carregamento do BUS para IODR
IOAR_load: IN STD_LOGIC; -- sinal de carregamento do BUS para IOAR
IO_valid: IN STD_LOGIC; -- sinal que indica que o resultado da IODR deve ser colocado em IO_bus (ou Z se 0)
IO_en: IN STD_LOGIC; -- ativacao do componente para operacoes de leitura e escrita
IO_rw: IN STD_LOGIC; -- flag que indica se a operacao a ser realizada eh de leitura ou escrita
IO_bus: INOUT STD_LOGIC_VECTOR(n-1 DOWNTO 0); -- barramento de entrada/saida
-- Switches
switches: IN std_logic_vector(17 downto 0);
-- Displays
hex3: OUT std_logic_vector(0 TO 7);
hex2: OUT std_logic_vector(0 TO 7);
hex1: OUT std_logic_vector(0 TO 7);
hex0: OUT std_logic_vector(0 TO 7));
END ENTITY io;
ARCHITECTURE processor_io OF io IS
SIGNAL iodr: STD_LOGIC_VECTOR(wordlen-1 DOWNTO 0); -- registrador de dados
SIGNAL ioar: UNSIGNED(wordlen-oplen-1 downto 0); -- registrador de enderecos
SIGNAL bcd0: STD_LOGIC_VECTOR(3 downto 0);
SIGNAL bcd1: STD_LOGIC_VECTOR(3 downto 0);
SIGNAL bcd2: STD_LOGIC_VECTOR(3 downto 0);
SIGNAL bcd3: STD_LOGIC_VECTOR(3 downto 0);
SIGNAL bcd_en: STD_LOGIC;
COMPONENT bcd_to_7seg IS
PORT (bcd: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
en: IN std_logic;
output: OUT STD_LOGIC_VECTOR (0 TO 7));
END COMPONENT;
BEGIN
-- Se o IO_valid = '1', manda o valor do resultado do iodr pro barramento. Caso contrario, manda Z.
IO_bus <= iodr
WHEN IO_valid = '1' AND ioar(7) = '1'
ELSE (others => 'Z');
-- Gera a visualizacao 7seg
bcd0_7seg: bcd_to_7seg PORT MAP(bcd0, seg_en, hex0);
bcd1_7seg: bcd_to_7seg PORT MAP(bcd1, seg_en, hex1);
bcd2_7seg: bcd_to_7seg PORT MAP(bcd2, seg_en, hex2);
bcd3_7seg: bcd_to_7seg PORT MAP(bcd3, seg_en, hex3);
PROCESS (clk, nrst) IS
BEGIN
-- De forma assincrona, se o reset ficar em nivel 0, reseta os registradores e conteudo da memoria
IF nrst = '0' THEN
iodr <= (OTHERS => '0');
ioar <= (OTHERS => '0');
bcd0 <= "0000";
bcd1 <= "0000";
bcd2 <= "0000";
bcd3 <= "0000";
-- Se teve uma borda de subida no clock, faz as outras coisas
ELSIF rising_edge(clk) THEN
IF IOAR_load = '1' THEN
ioar <= UNSIGNED(IO_bus(n-oplen-1 DOWNTO 0)); -- Para carregar IOAR, basta ler o endereco do que tem no BUS (desconsidera o OPCODE)
ELSIF IODR_load = '1' THEN
iodr <= IO_BUS; -- Para carregar IODR, basta ler direto do BUS
ELSIF IO_en = '1' THEN
IF IO_rw = '0' THEN
-- Porta '0' de IO é de leitura (switches)
IF to_integer(ioar) = mem_limit + 0 THEN
iodr <= switches(11 downto 0);
END IF;
ELSE
-- Porta '1' de IO é de saída.
IF ioar = mem_limit + 1 THEN
bcd0 <= iodr(3 downto 0);
bcd1 <= iodr(7 downto 4);
-- Porta '2' de IO é de saída.
ELSIF ioar = mem_limit + 2 THEN
bcd2 <= iodr(3 downto 0);
bcd3 <= iodr(7 downto 4);
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE processor_io; | gpl-2.0 | db893dda2874d54de28b29c97912f738 | 0.60632 | 3.0866 | false | false | false | false |
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