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TanND/Electronic | VHDL/D8_C1.vhd | 1 | 892 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D8_C1 is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR(7 downto 0)
);
end D8_C1;
architecture D8_C1 of D8_C1 is
begin
process(rst,clk)
variable dem:integer range 0 to 9;
begin
if (rst='1') then dem:=0;
elsif (rising_edge(clk)) then
if (dem=9) then dem:=0;
else dem:=dem+1;
end if;
end if;
case dem is
when 0 => seg<= x"C0";
when 1 => seg<= x"F9";
when 2 => seg<= x"A4";
when 3 => seg<= x"B0";
when 4 => seg<= x"99";
when 5 => seg<= x"92";
when 6 => seg<= x"82";
when 7 => seg<= x"F8";
when 8 => seg<= x"80";
when 9 => seg<= x"90";
when others =>NULL;
end case;
end process;
end D8_C1;
-- rst= 100Khz; clk=10Mhz; | apache-2.0 | 1c1ce16e9bbf0011efa7fb0b9ccf8265 | 0.480942 | 2.877419 | false | false | false | false |
SoCdesign/EHA | RTL/Credit_Based/Checkers/Control_Part_Checkers/LBDR_credit_based_checkers/RTL_and_Synthesis/LBDR_credit_based_checkers.vhd | 1 | 9,006 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_credit_based_checkers is
generic (
cur_addr_rst: integer := 5;
NoC_size: integer := 4
);
port ( empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic;
N1_out, E1_out, W1_out, S1_out: in std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
grants: in std_logic;
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
-- Checker outputs
err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot,
err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in : out std_logic
);
end LBDR_credit_based_checkers;
architecture behavior of LBDR_credit_based_checkers is
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal Requests_FF: std_logic_vector(4 downto 0);
signal Requests_in: std_logic_vector(4 downto 0);
signal grant_signals: std_logic_vector(4 downto 0);
begin
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
Requests_FF <= Req_N_FF & Req_E_FF & Req_W_FF & Req_S_FF & Req_L_FF;
Requests_in <= Req_N_in & Req_E_in & Req_W_in & Req_S_in & Req_L_in;
grant_signals <= grant_N & grant_E & grant_W & grant_S & grant_L;
-- Implementing checkers in form of concurrent assignments (combinational assertions)
process (flit_type, empty, Requests_in)
begin
if (flit_type = "001" and empty = '0' and Requests_in /= "00001" and Requests_in /= "00010" and Requests_in /= "00100" and
Requests_in /= "01000" and Requests_in /= "10000") then
err_header_not_empty_Requests_in_onehot <= '1';
else
err_header_not_empty_Requests_in_onehot <= '0';
end if;
end process;
process (flit_type, empty, Requests_FF, Requests_in)
begin
if (flit_type = "001" and empty = '1' and Requests_FF /= Requests_in) then
err_header_empty_Requests_FF_Requests_in <= '1';
else
err_header_empty_Requests_FF_Requests_in <= '0';
end if;
end process;
process (flit_type, empty, grants, Requests_in)
begin
if (flit_type = "100" and empty = '0' and grants = '1' and Requests_in /= "00000") then
err_tail_Requests_in_all_zero <= '1';
else
err_tail_Requests_in_all_zero <= '0';
end if;
end process;
process (flit_type, empty, Requests_FF, Requests_in)
begin
if (flit_type = "100" and empty = '1' and Requests_FF /= Requests_in) then
err_tail_empty_Requests_FF_Requests_in <= '1';
else
err_tail_empty_Requests_FF_Requests_in <= '0';
end if;
end process;
process (flit_type, empty, grants, Requests_FF, Requests_in)
begin
if (flit_type = "100" and empty = '0' and grants = '0' and Requests_FF /= Requests_in) then
err_tail_not_empty_not_grants_Requests_FF_Requests_in <= '1';
else
err_tail_not_empty_not_grants_Requests_FF_Requests_in <= '0';
end if;
end process;
process (grant_signals, grants)
begin
if ( (grant_signals = "00001" or grant_signals = "00010" or grant_signals = "00100" or
grant_signals = "01000" or grant_signals = "10000") and grants = '0') then
err_grants_onehot <= '1';
else
err_grants_onehot <= '0';
end if;
end process;
process (grant_signals, grants)
begin
if ( grant_signals = "00000" and grants = '1') then
err_grants_mismatch <= '1';
else
err_grants_mismatch <= '0';
end if;
end process;
process (flit_type, Requests_FF, Requests_FF, Requests_in)
begin
if (flit_type /= "001" and flit_type /= "100" and Requests_FF /= Requests_in) then
err_header_tail_Requests_FF_Requests_in <= '1';
else
err_header_tail_Requests_FF_Requests_in <= '0';
end if;
end process;
process (cur_addr, dst_addr, N1_out)
begin
if ( dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) and N1_out = '0') then
err_dst_addr_cur_addr_N1 <= '1';
else
err_dst_addr_cur_addr_N1 <= '0';
end if;
end process;
process (cur_addr, dst_addr, N1_out)
begin
if ( dst_addr(NoC_size-1 downto NoC_size/2) >= cur_addr(NoC_size-1 downto NoC_size/2) and N1_out = '1') then
err_dst_addr_cur_addr_not_N1 <= '1';
else
err_dst_addr_cur_addr_not_N1 <= '0';
end if;
end process;
process (cur_addr, dst_addr, E1_out)
begin
if ( cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) and E1_out = '0') then
err_dst_addr_cur_addr_E1 <= '1';
else
err_dst_addr_cur_addr_E1 <= '0';
end if;
end process;
process (cur_addr, dst_addr, E1_out)
begin
if ( cur_addr((NoC_size/2)-1 downto 0) >= dst_addr((NoC_size/2)-1 downto 0) and E1_out = '1') then
err_dst_addr_cur_addr_not_E1 <= '1';
else
err_dst_addr_cur_addr_not_E1 <= '0';
end if;
end process;
process (cur_addr, dst_addr, W1_out)
begin
if ( dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) and W1_out = '0') then
err_dst_addr_cur_addr_W1 <= '1';
else
err_dst_addr_cur_addr_W1 <= '0';
end if;
end process;
process (cur_addr, dst_addr, W1_out)
begin
if ( dst_addr((NoC_size/2)-1 downto 0) >= cur_addr((NoC_size/2)-1 downto 0) and W1_out = '1') then
err_dst_addr_cur_addr_not_W1 <= '1';
else
err_dst_addr_cur_addr_not_W1 <= '0';
end if;
end process;
process (cur_addr, dst_addr, S1_out)
begin
if ( cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) and S1_out = '0') then
err_dst_addr_cur_addr_S1 <= '1';
else
err_dst_addr_cur_addr_S1 <= '0';
end if;
end process;
process (cur_addr, dst_addr, S1_out)
begin
if ( cur_addr(NoC_size-1 downto NoC_size/2) >= dst_addr(NoC_size-1 downto NoC_size/2) and S1_out = '1') then
err_dst_addr_cur_addr_not_S1 <= '1';
else
err_dst_addr_cur_addr_not_S1 <= '0';
end if;
end process;
process (flit_type, empty, N1_out, E1_out, W1_out, S1_out, Req_L_in)
begin
if ( flit_type = "001" and empty = '0' and Req_L_in /= (not N1_out and not E1_out and not W1_out and not S1_out) ) then
err_dst_addr_cur_addr_not_Req_L_in <= '1';
else
err_dst_addr_cur_addr_not_Req_L_in <= '0';
end if;
end process;
process (flit_type, empty, cur_addr, dst_addr, Req_L_in)
begin
if ( flit_type = "001" and empty = '0' and cur_addr /= dst_addr and Req_L_in = '1') then
err_dst_addr_cur_addr_Req_L_in <= '1';
else
err_dst_addr_cur_addr_Req_L_in <= '0';
end if;
end process;
process (flit_type, empty, Req_N_in, N1_out, E1_out, W1_out)
begin
if ( flit_type = "001" and empty = '0' and Req_N_in /= (N1_out and not E1_out and not W1_out) ) then
err_header_not_empty_Req_N_in <= '1';
else
err_header_not_empty_Req_N_in <= '0';
end if;
end process;
process (flit_type, empty, Req_E_in, N1_out, E1_out, S1_out)
begin
if ( flit_type = "001" and empty = '0' and Req_E_in /= ((E1_out and not N1_out and not S1_out) or
(E1_out and N1_out) or (E1_out and S1_out)) ) then
err_header_not_empty_Req_E_in <= '1';
else
err_header_not_empty_Req_E_in <= '0';
end if;
end process;
process (flit_type, empty, Req_W_in, N1_out, W1_out, S1_out)
begin
if ( flit_type = "001" and empty = '0' and Req_W_in /= ((W1_out and not N1_out and not S1_out) or
(W1_out and N1_out) or (W1_out and S1_out)) ) then
err_header_not_empty_Req_W_in <= '1';
else
err_header_not_empty_Req_W_in <= '0';
end if;
end process;
process (flit_type, empty, Req_S_in, E1_out, W1_out, S1_out)
begin
if ( flit_type = "001" and empty = '0' and Req_S_in /= (S1_out and not E1_out and not W1_out) ) then
err_header_not_empty_Req_S_in <= '1';
else
err_header_not_empty_Req_S_in <= '0';
end if;
end process;
end behavior; | gpl-3.0 | 509f4432cdd6c71f65e40140f28c7068 | 0.59849 | 2.758346 | false | false | false | false |
SoCdesign/EHA | RTL/Hand_Shaking/Hand_Shaking_FC/Router_32_bit_parity.vhd | 1 | 14,318 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_parity is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 60;
Cx_rst : integer := 10;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
DCTS_N, DCTS_E, DCTS_w, DCTS_S, DCTS_L: in std_logic;
DRTS_N, DRTS_E, DRTS_W, DRTS_S, DRTS_L: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
RTS_N, RTS_E, RTS_W, RTS_S, RTS_L: out std_logic;
CTS_N, CTS_E, CTS_w, CTS_S, CTS_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
fault_out_N, fault_out_E, fault_out_W, fault_out_S, fault_out_L:out std_logic
);
end router_parity;
architecture behavior of router_parity is
COMPONENT parity_checker is
generic(DATA_WIDTH : integer := 32);
port(
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
DRTS: in std_logic;
fault_out: out std_logic
);
end COMPONENT;
COMPONENT FIFO
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector (DATA_WIDTH-1 downto 0);
DRTS: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
CTS: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
COMPONENT Arbiter
port ( reset: in std_logic;
clk: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic;
DCTS: in std_logic;
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic;
Xbar_sel : out std_logic_vector(4 downto 0);
RTS: out std_logic
);
end COMPONENT;
COMPONENT LBDR is
generic (
cur_addr_rst: integer := 0;
Rxy_rst: integer := 60;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
begin
------------------------------------------------------------------------------------------------------------------------------
-- block diagram of one channel
--
-- .____________grant_________
-- | ▲
-- | _______ __|_______
-- | | | | |
-- | | LBDR |---req--->| Arbiter | <--handshake-->
-- | |_______| |__________| signals
-- | ▲ |
-- __▼___ | flit ___▼__
-- RX ----->| | | type | |
-- <-handshake->| FIFO |---o------------->| |-----> TX
-- signals |______| ------>| |
-- ------>| XBAR |
-- ------>| |
-- ------>| |
-- |______|
--
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the parity_checkers
PC_N: parity_checker generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(RX => RX_N, DRTS =>DRTS_N, fault_out => fault_out_N);
PC_E: parity_checker generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(RX => RX_E, DRTS =>DRTS_E, fault_out => fault_out_E);
PC_W: parity_checker generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(RX => RX_W, DRTS =>DRTS_W, fault_out => fault_out_W);
PC_S: parity_checker generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(RX => RX_S, DRTS =>DRTS_S, fault_out => fault_out_S);
PC_L: parity_checker generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(RX => RX_L, DRTS =>DRTS_L, fault_out => fault_out_L);
-- all the FIFOs
FIFO_N: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_N, DRTS => DRTS_N,
read_en_N => '0', read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
CTS => CTS_N, empty_out => empty_N, Data_out => FIFO_D_out_N);
FIFO_E: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_E, DRTS => DRTS_E,
read_en_N => Grant_NE, read_en_E =>'0', read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
CTS => CTS_E, empty_out => empty_E, Data_out => FIFO_D_out_E);
FIFO_W: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_W, DRTS => DRTS_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>'0', read_en_S =>Grant_SW, read_en_L =>Grant_LW,
CTS => CTS_W, empty_out => empty_W, Data_out => FIFO_D_out_W);
FIFO_S: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_S, DRTS => DRTS_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>'0', read_en_L =>Grant_LS,
CTS => CTS_S, empty_out => empty_S, Data_out => FIFO_D_out_S);
FIFO_L: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_L, DRTS => DRTS_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>'0',
CTS => CTS_L, empty_out => empty_L, Data_out => FIFO_D_out_L);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the LBDRs
LBDR_N: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N, flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL);
LBDR_E: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E, flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL);
LBDR_W: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W, flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL);
LBDR_S: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S, flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL);
LBDR_L: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L, flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Arbiters
Arbiter_N: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => '0' , Req_E => Req_EN, Req_W => Req_WN, Req_S => Req_SN, Req_L => Req_LN,
DCTS => DCTS_N, Grant_N => Grant_NN, Grant_E => Grant_NE, Grant_W => Grant_NW, Grant_S => Grant_NS, Grant_L => Grant_NL,
Xbar_sel => Xbar_sel_N,
RTS => RTS_N
);
Arbiter_E: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NE , Req_E => '0', Req_W => Req_WE, Req_S => Req_SE, Req_L => Req_LE,
DCTS => DCTS_E, Grant_N => Grant_EN, Grant_E => Grant_EE, Grant_W => Grant_EW, Grant_S => Grant_ES, Grant_L => Grant_EL,
Xbar_sel => Xbar_sel_E,
RTS => RTS_E
);
Arbiter_W: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NW , Req_E => Req_EW, Req_W => '0', Req_S => Req_SW, Req_L => Req_LW,
DCTS => DCTS_W, Grant_N => Grant_WN, Grant_E => Grant_WE, Grant_W => Grant_WW, Grant_S => Grant_WS, Grant_L => Grant_WL,
Xbar_sel => Xbar_sel_W,
RTS => RTS_W
);
Arbiter_S: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NS , Req_E => Req_ES, Req_W => Req_WS, Req_S => '0', Req_L => Req_LS,
DCTS => DCTS_S, Grant_N => Grant_SN, Grant_E => Grant_SE, Grant_W => Grant_SW, Grant_S => Grant_SS, Grant_L => Grant_SL,
Xbar_sel => Xbar_sel_S,
RTS => RTS_S
);
Arbiter_L: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NL , Req_E => Req_EL, Req_W => Req_WL, Req_S => Req_SL, Req_L => '0',
DCTS => DCTS_L, Grant_N => Grant_LN, Grant_E => Grant_LE, Grant_W => Grant_LW, Grant_S => Grant_LS, Grant_L => Grant_LL,
Xbar_sel => Xbar_sel_L,
RTS => RTS_L
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
end;
| gpl-3.0 | 8652a7cfe69411a5316f91e0441dfdd8 | 0.473795 | 3.250057 | false | false | false | false |
carlosrd/DAS | P4/Parte B (Opcional 1)/cronometro.vhd | 1 | 5,446 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
entity cronometro is
port (
-- Entradas
startStop: in std_logic;
puestaCero: in std_logic;
clk: in std_logic;
rst: in std_logic;
-- Salidas
rightSegs: out std_logic_vector(7 downto 0);
leftSegs: out std_logic_vector(7 downto 0);
decimasSegs: out std_logic_vector(7 downto 0);
puntoDec: out std_logic
);
end cronometro;
architecture Behavioral of cronometro is
signal ssDebounced,ssDebFallEdge,ssDebRiseEdge: std_logic;
signal pODebounced,pODebFallEdge,pODebRiseEdge: std_logic;
signal t: std_logic;
signal salidaCont5kk: std_logic_vector(22 downto 0);
signal salidaContDecimas, salidaContUnidades,salidaContDecenas: std_logic_vector(3 downto 0);
signal cuentaDecimas, cuentaUnidades, cuentaDecenas: std_logic;
signal cs1 : std_logic_vector( 22 downto 0 );
signal cs2,cs3,cs4 : std_logic_vector( 3 downto 0 );
signal lit1,lit2,lit3: std_logic;
component debouncer
port(rst: in std_logic;
clk: in std_logic;
x: in std_logic;
xDeb: out std_logic;
xDebFallingEdge: out std_logic;
xDebRisingEdge: out std_logic);
end component;
component binToSeg is
port (
bin: in std_logic_vector(3 downto 0);
displaySeg: out std_logic_vector(7 downto 0) -- 7 = A / 6 = B / ... / 0 = H
);
end component;
begin
-- ELIMINACION DE REBOTES EN LOS PUSHBUTTONS
debouncerStartStop: debouncer port map (rst,clk,startStop,ssDebounced,ssDebFallEdge,ssDebRiseEdge);
debouncerPuestaCero: debouncer port map (rst,clk,puestaCero,pODebounced,pODebFallEdge,pODebRiseEdge);
-- CONTADORES
contMod5kk:
process( clk, cs1, rst, pODebFallEdge, ssDebFallEdge )
begin
salidaCont5kk <= cs1;
if rst = '0' then
cs1 <= conv_std_logic_vector( 0 , 23 );
elsif clk'event and clk = '1' then
if pODebFallEdge = '1' then
cs1 <= conv_std_logic_vector( 0 , 23 );
elsif t = '1' then
if cs1 = conv_std_logic_vector( 4999999 , 23 ) then
cs1 <= conv_std_logic_vector( 0 , 23 );
else
cs1 <= cs1 + 1;
end if;
end if;
end if;
end process;
-- contDecimas cuenta cuando se tenga 4.999.999 = 10011000100101100111111 en cont5Millones
cuentaDecimas <= salidaCont5kk(22) and salidaCont5kk(19) and salidaCont5kk(18) and salidaCont5kk(14) and salidaCont5kk(11) and
salidaCont5kk(9) and salidaCont5kk(8) and salidaCont5kk(5) and salidaCont5kk(4) and salidaCont5kk(3) and
salidaCont5kk(2) and salidaCont5kk(1) and salidaCont5kk(0);
contDecimas:
process( clk, cs2, rst, pODebFallEdge, cuentaDecimas )
begin
salidaContDecimas <= cs2;
if rst = '0' then
cs2 <= conv_std_logic_vector( 0 , 4 );
elsif clk'event and clk = '1' then
if pODebFallEdge = '1' then
cs2 <= conv_std_logic_vector( 0 , 4 );
elsif cuentaDecimas = '1' then
if cs2 = conv_std_logic_vector( 9 , 4 ) then
cs2 <= conv_std_logic_vector( 0 , 4 );
else
cs2 <= cs2 + 1;
end if;
end if;
end if;
end process;
-- contUnidades cuenta cuando se tenga 9 = 1001 en contDecimas
cuentaUnidades <= (salidaContDecimas(3) and salidaContDecimas(0)) and cuentaDecimas;
contUnidades:
process( clk, cs3, rst, pODebFallEdge, cuentaUnidades )
begin
salidaContUnidades <= cs3;
if rst = '0' then
cs3 <= conv_std_logic_vector( 0 , 4 );
elsif clk'event and clk = '1' then
if pODebFallEdge = '1' then
cs3 <= conv_std_logic_vector( 0 , 4 );
elsif cuentaUnidades = '1' then
if cs3 = conv_std_logic_vector( 9 , 4 ) then
cs3 <= conv_std_logic_vector( 0 , 4 );
else
cs3 <= cs3 + 1;
end if;
end if;
end if;
end process;
cuentaDecenas <= (salidaContUnidades(3) and salidaContUnidades(0)) and (cuentaDecimas and cuentaUnidades);
contDecenas:
process( clk, cs4, rst, pODebFallEdge, cuentaDecenas )
begin
salidaContDecenas <= cs4;
if rst = '0' then
cs4 <= conv_std_logic_vector( 0 , 4 );
elsif clk'event and clk = '1' then
if pODebFallEdge = '1' then
cs4 <= conv_std_logic_vector( 0 , 4 );
elsif cuentaDecenas = '1' then
if cs4 = conv_std_logic_vector( 5 , 4 ) then
cs4 <= conv_std_logic_vector( 0 , 4 );
else
cs4 <= cs4 + 1;
end if;
end if;
end if;
end process;
-- BIESTABLE T
-- Usamos el flanco de bajada (fall) porque la placa tiene logica negativa
biestableT:
process(clk)
begin
if (rst = '0') then
t <= '0';
elsif (clk'event and clk='1') then
if (ssDebFallEdge = '1') then
t <= not (t);
end if;
end if;
end process;
parpadeoPuntoDecimal:
process(salidaContDecimas)
begin
lit1 <= not salidaContDecimas(3) and not salidaContDecimas(2);
lit2 <= not salidaContDecimas(3) and not salidaContDecimas(1) and not salidaContDecimas(0);
lit3 <= lit1 or lit2;
if (lit3 = '1') then
puntoDec <= '1';
else
puntoDec <= '0';
end if;
end process;
-- DISPLAYS 8 SEGMENTOS
decenasSeg: binToSeg port map (salidaContDecenas,leftSegs);
unidadesSeg: binToSeg port map (salidaContUnidades,rightSegs);
deciSeg: binToSeg port map (salidaContDecimas,decimasSegs);
end Behavioral;
-- x3 x2 x1 x0 z
--------------------
--0 0 0 0 0 1
--1 0 0 0 1 1
--2 0 0 1 0 1
--3 0 0 1 1 1
--4 0 1 0 0 1
--5 0 1 0 1 0
--6 0 1 1 0 0
--7 0 1 1 1 0
--8 1 0 0 0 0
--9 1 0 0 1 0
-- Mapa de Karnaugh ==> FLASH = (¬ x3)(¬ x2) + (¬ x3)(¬ x1)(¬ x0)
| mit | 3106f8f10e739efed3d862560c429eb0 | 0.659438 | 2.936319 | false | false | false | false |
bruskajp/EE-316 | Project4/Vivado_NexysBoard/craddockEE316/craddockEE316.srcs/sources_1/imports/testFolder/top_level.vhd | 1 | 16,075 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03/09/2017 12:40:24 PM
-- Design Name:
-- Module Name: top_level - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top_level is
port(
iCLK : in std_logic;
--iPCsel : in std_logic_vector(1 downto 0); -- testing
iPCsel : in std_logic;
iEOC : in std_logic;
SW : in std_logic;
--idata_valid : in std_logic; -- testing
iReset : in std_logic; -- BTNC
inData0 : in std_logic; -- PIN D14 JB[1]
inData1 : in std_logic; -- PIN F16 JB[2]
inData2 : in std_logic; -- PIN G16 JB[3]
inData3 : in std_logic; -- PIN H14 JB[4]
inData4 : in std_logic; -- PIN E16 JB[5]
inData5 : in std_logic; -- PIN F13 JB[6]
inData6 : in std_logic; -- PIN G13 JB[7]
inData7 : in std_logic; -- PIN H16 JB[8]
--iadc_dataReady : in std_logic; -- PIN E17 JA[6]
inStartOutput : in std_logic;
oALE : out std_logic;
sysPWMout : out std_logic_vector(0 downto 0); -- PIN K1 JC[1]
sysPWM_nout : out std_logic_vector(0 downto 0); -- PIN F6 JC[2]
oadc_select : out std_logic; -- PIN F18 JA[1]
oadc_clock : out std_logic; -- PIN D18 JA[2]
oadc_loadAddressStart : out std_logic; -- PIN E7 JA[3]
oadc_outputEnable : out std_logic; -- PIN G17 JA[4]
odata_valid : buffer std_logic; -- PIN D17 JA[5]
otx_ready : out std_logic; -- PIN J2 JC[3]
outData : out std_logic -- data to PC -- PIN G6 JC[4]
);
end top_level;
architecture Structural of top_level is
--component basic_uart is
-- port(
-- clk: in std_logic; -- clock
-- reset: in std_logic; -- reset
-- -- Client interface
-- rx_data: out std_logic_vector(7 downto 0); -- received byte
-- rx_enable: out std_logic; -- validates received byte (1 system clock spike)
-- tx_data: in std_logic_vector(7 downto 0); -- byte to send
-- tx_enable: in std_logic; -- validates byte to send if tx_ready is '1'
-- tx_ready: out std_logic; -- if '1', we can send a new byte, otherwise we won't take it
-- -- Physical interface
-- rx: in std_logic;
-- tx: out std_logic
-- );
--end component;
component uart is
port (
reset :in std_logic;
txclk :in std_logic;
ld_tx_data :in std_logic;
tx_data :in std_logic_vector (7 downto 0);
tx_enable :in std_logic;
selCheck :in std_logic_vector(1 downto 0);
tx_out :out std_logic;
tx_empty :out std_logic;
rxclk :in std_logic;
uld_rx_data :in std_logic;
rx_data :out std_logic_vector (7 downto 0);
rx_enable :in std_logic;
rx_in :in std_logic;
rx_empty :out std_logic
);
end component;
--component ad_converter is
-- port (from_adc : in std_logic_vector(7 downto 0);
-- adc_dataReady, slow_clk, reset, enable : in std_logic;
-- adc_select : out std_logic_vector(1 downto 0);
-- adc_output00FL, adc_output01FR, adc_output10BL, adc_output11BR
-- : out std_logic_vector(7 downto 0);
-- adc_clock, adc_loadAddressStart, adc_outputEnable, data_valid
-- : out std_logic);
-- end component;
component ADC_Controller is
generic(samples : integer :=128);
Port ( iclk : in STD_LOGIC;
reset : in STD_LOGIC;
EOC : in STD_LOGIC;
oStart : out STD_LOGIC;
ALE : out std_logic;
oOE : out std_logic;
sel : buffer std_logic := '0';
oWriteReady : buffer std_logic;
oClk_en : out std_logic
);
end component;
--component PWM_Controller is
-- port(
-- iadc_sel : in std_logic;
-- iSW : in std_logic;
-- iData : in std_logic_vector(7 downto 0);
-- --iData2 : in std_logic_vector(7 downto 0);
-- oData : out std_logic_vector(7 downto 0)
-- );
--end component;
component RAM_Controller is
generic( constant samples : integer := 128);
Port ( clk11kHz : in STD_LOGIC;
clk : in std_logic;
clk500kHz : in STD_LOGIC;
idata_valid : in std_logic;
sel : in STD_LOGIC_vector(1 downto 0);
ointernalCount : out std_logic;
iadcsel : in std_logic;
reset : in std_logic;
ena1 : out std_logic;
enb1 : out std_logic;
ena2 : out std_logic;
enb2 : out std_logic;
wea : out std_logic_vector(0 downto 0);
UARTen : out std_logic;
ocount1 : out std_logic_vector(13 downto 0);
ocount4 : out std_logic_vector(13 downto 0);
ocount2 : out std_logic_vector(13 downto 0);
ocount3 : out std_logic_vector(13 downto 0));
end component;
component multiplex_UART is
generic (data_width : positive := 8);
port(select_line: in std_logic;
in_a, in_b: in std_logic_vector(data_width-1 downto 0);
--UARTen : out std_logic;
output : out std_logic_vector(data_width-1 downto 0));
end component;
component pwm IS
GENERIC(
sys_clk : INTEGER := 100_000_000; --system clock frequency in Hz
pwm_freq : INTEGER := 500_000; --PWM switching frequency in Hz
bits_resolution : INTEGER := 64; --bits of resolution setting the duty cycle
phases : INTEGER := 1); --number of output pwms and phases
PORT(
clk : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --asynchronous reset
ena : IN STD_LOGIC; --latches in new duty cycle
duty : IN STD_LOGIC_VECTOR(bits_resolution-1 DOWNTO 0); --duty cycle
pwm_out : OUT STD_LOGIC_VECTOR(phases-1 DOWNTO 0); --pwm outputs
pwm_n_out : OUT STD_LOGIC_VECTOR(phases-1 DOWNTO 0)); --pwm inverse outputs
END component;
--component pwm_prog is
--generic(
-- N : integer := 8); -- number of bit of PWM counter
--port (
-- i_clk : in std_logic;
-- i_rstb : in std_logic;
-- i_sync_reset : in std_logic;
-- i_pwm_module : in std_logic_vector(N-1 downto 0); -- PWM Freq = clock freq/ (i_pwm_module+1); max value = 2^N-1
-- i_pwm_width : in std_logic_vector(N-1 downto 0); -- PWM width = (others=>0)=> OFF; i_pwm_module => MAX ON
-- o_pwm : out std_logic);
--end component;
component clk1Mhz IS
PORT (
SIGNAL samplingFreq : INOUT std_logic;
signal baudRate : INOUT std_logic;
signal rx_clk : inout std_logic;
signal tx_clk : inout std_logic;
SIGNAL iCLK : IN std_logic);
END component;
COMPONENT sig1dualRAM
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
component btn_debounce_toggle is
GENERIC (
CONSTANT CNTR_MAX : std_logic_vector(15 downto 0) := X"FFFF");
Port ( BTN_I : in STD_LOGIC;
CLK : in STD_LOGIC;
BTN_O : out STD_LOGIC;
TOGGLE_O : out STD_LOGIC);
end component;
-- component adc_parse is
-- Port ( iData : in STD_LOGIC_vector(7 downto 0);
-- oData1 : out STD_LOGIC_vector(7 downto 0);
-- oData2 : out STD_LOGIC_vector(7 downto 0);
-- iadc_sel : in STD_LOGIC);
-- end component;
signal rx_en: std_logic:= '1';
signal tx_en: std_logic:= '1';
signal txs: std_logic;
signal rxs: std_logic;
signal sreset_n: std_logic;
signal Sreset: std_logic;
--signal adc_1: std_logic_vector(7 downto 0);
--signal adc_2: std_logic_vector(7 downto 0);
--signal adc00: std_logic_vector(7 downto 0);
--signal adc01: std_logic_vector(7 downto 0);
--signal adc10: std_logic_vector(7 downto 0);
--signal adc11: std_logic_vector(7 downto 0);
signal rx_ld: std_logic;
signal Sclk500kHZ: std_logic;
signal Sclk11kHz: std_logic;
signal RAMout1: std_logic_vector(7 downto 0);
signal RAMout2: std_logic_vector(7 downto 0);
signal RAMout3: std_logic_vector(7 downto 0);
signal UARTdata: std_logic_vector(7 downto 0);
signal RAMUARTen: std_logic;
--signal MUXUARTen: std_logic;
signal RAMena1: std_logic;
signal RAMenb1: std_logic;
signal RAMena2: std_logic;
signal RAMenb2: std_logic;
signal RAMwea: std_logic_vector(0 downto 0);
signal RAMaddra1: std_logic_vector(13 downto 0);
signal RAMaddra2: std_logic_vector(13 downto 0);
signal RAMaddrb1: std_logic_vector(13 downto 0);
signal RAMaddrb2: std_logic_vector(13 downto 0);
signal inData : std_logic_vector(7 downto 0);
signal PCsel : std_logic_vector(1 downto 0);
signal rxSel : std_logic_vector(7 downto 0);
signal stx_ready: std_logic:= '1';
signal adcsel : std_logic;
signal adcsel_n : std_logic;
signal Spwm_out : std_logic;
signal Srx_clk : std_logic;
signal Stx_clk : std_logic;
signal data_valid : std_logic;
signal RAM_count : std_logic;
signal PWMdata : std_logic_vector(7 downto 0);
signal sig1 : std_logic_vector(7 downto 0);
signal sig2 : std_logic_vector(7 downto 0);
begin
--adc_1 <= adc00 or adc01;
--adc_2 <= adc10 or adc11;
RAMout3 <= RAMout1 or RAMout2;
sreset_n <= not iReset;
--inData <= inData0 & inData1 & inData2 & inData3 & inData4 & inData5 & inData6 & inData7;
inData <= inData7 & inData6 & inData5 & inData4 & inData3 & inData2 & inData1 & inData0;
PCsel <= rxSel(1 downto 0);
oadc_select <= adcsel;
adcsel_n <= not adcsel;
--sysPWM_nout <= not(Spwm_out);
--sysPWMout <= Spwm_out;
odata_valid <= data_valid;
rx_ld <= not(RAM_count) and rx_en;
Inst_sys_clk: clk1Mhz
port map(
iCLK => iCLK,
samplingFreq => Sclk500kHz,
rx_clk => Srx_clk,
tx_clk => Stx_clk,
baudRate => Sclk11kHz
);
Inst_ResetDeb: btn_debounce_toggle
GENERIC map ( CNTR_MAX => X"FFFF")
Port map ( BTN_I => iReset,
CLK => iCLK,
BTN_O => Sreset,
TOGGLE_O => open
);
--Inst_ADC_Parse: adc_parse
-- Port map
-- ( iData => inData,
-- oData1 => sig1,
-- oData2 => sig2,
-- iadc_sel => adcsel
-- );
--Inst_ADC: ad_converter
-- port map(
-- from_adc => inData,
-- adc_dataReady => iadc_dataReady,
-- slow_clk => Sclk500kHz,
-- reset => iReset,
-- enable => en,
-- adc_select => oadc_select,
-- adc_output00FL => adc00,
-- adc_output01FR => adc01,
-- adc_output10BL => adc10,
-- adc_output11BR => adc11,
-- adc_clock => oadc_clock,
-- adc_loadAddressStart => oadc_loadAddressStart,
-- adc_outputEnable => oadc_outputEnable,
-- data_valid => odata_valid
-- );
--Inst_PWM_Controller: PWM_Controller
-- port map(
-- iadc_sel => adcsel,
-- iSW => SW,
-- iData => inData,
-- --iData2 => sig2,
-- oData => pwmData
-- );
Inst_ADC: ADC_Controller
generic map(samples => 128)
port map(
iclk => iCLK,
reset => Sreset,
EOC => iEOC,
oStart => oadc_loadAddressStart,
ALE => oALE,
oOE => oadc_outputEnable,
sel => adcsel,
oWriteReady => data_valid,
oClk_en => oadc_clock
);
Inst_RAM_Controller: RAM_Controller
generic map(samples => 128)
port map(
clk => iCLK,
clk11kHz => Sclk11kHz,
idata_valid => data_valid,
clk500kHz => Sclk500kHz,
iadcsel => adcsel,
reset => Sreset,
sel => PCsel,
ointernalCount => RAM_count,
ena1 => RAMena1,
enb1 => RAMenb1,
ena2 => RAMena2,
enb2 => RAMenb2,
wea => RAMwea,
UARTen => RAMUARTen,
ocount1 => RAMaddra1,
ocount4 => RAMaddra2,
ocount2 => RAMaddrb1,
ocount3 => RAMaddrb2
);
Inst_RAM1: sig1dualRAM
port map(
clka => iCLK,
ena => adcsel_n,
wea => RAMwea,
addra => RAMaddra1,
dina => inData,
clkb => iCLK,
enb => RAMenb1,
addrb => RAMaddrb1,
doutb => RAMout1
);
Inst_RAM2: sig1dualRAM
port map(
clka => iCLK,
ena => adcsel,
wea => RAMwea,
addra => RAMaddra2,
dina => inData,
clkb => iCLK,
enb => RAMenb2,
addrb => RAMaddrb2,
doutb => RAMout2
);
Inst_Mux: multiplex_UART
generic map (data_width => 8)
port map(
-- inputs
select_line => RAMenb2,
--UARTen => MUXUARTen,
in_a => RAMout1,
in_b => RAMout2,
-- outputs
output => UARTdata
);
Inst_PWM: pwm
generic map(
sys_clk => 100_000_000,
pwm_freq => 500_000,
bits_resolution => 8,
phases => 1)
port map(
clk => iCLK,
reset_n => sreset_n,
ena => rx_en,
duty => inData,
pwm_out => sysPWMout,
pwm_n_out => sysPWM_nout
);
--Inst_PWM: pwm_prog
-- generic map( N => 8)
-- port map(
-- i_clk => iCLK,
-- i_rstb => Sreset,
-- i_sync_reset => Sreset,
-- i_pwm_module => "01000000",
-- i_pwm_width => UARTdata,
-- o_pwm => Spwm_out
-- );
--Inst_UART: basic_uart
-- port map(
-- clk => iCLK,
-- reset => iReset,
-- rx_data => rxSel,
-- tx_data => RAMout3,
-- rx_enable => rx_en,
-- tx_enable => tx_en,
-- rx => iPCsel,
-- tx => outData,
-- tx_ready => otx_ready
-- );
Inst_UART: uart
port map(
reset => Sreset,
txclk => Stx_clk,
ld_tx_data => RAM_count,
tx_data => UARTdata,
selCheck => PCsel,
tx_enable => tx_en,
tx_out => outData,
tx_empty => open,
rxclk => Srx_clk,
uld_rx_data => rx_ld,
rx_data => rxSel,
rx_enable => rx_en,
rx_in => iPCsel,
rx_empty => open
);
end Structural;
| gpl-3.0 | 531f6c2f6d8f9d24ba7158d1a9eaeeb9 | 0.516765 | 3.525219 | false | false | false | false |
TanND/Electronic | VHDL/D1_C1.vhd | 1 | 1,266 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity D1_C1 is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
sel : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR (7 downto 0));
end D1_C1;
architecture D1_C1 of D1_C1 is
signal temp:STD_LOGIC_VECTOR (3 downto 0);
begin
process(clk,rst)
begin
if(rst='1') then
temp<="0000";
elsif(rising_edge(clk)) then
if(sel='1') then
if temp="1001" then
temp<="0000";
else temp<=temp+1;
end if;
else
if temp="0000" then
temp<="1001";
else temp<=temp-1;
end if;
end if;
end if;
end process;
process(clk,temp)
begin
case temp is
when "0000" => seg<= x"C0";
when "0001" => seg<= x"F9";
when "0010" => seg<= x"A4";
when "0011" => seg<= x"B0";
when "0100" => seg<= x"99";
when "0101" => seg<= x"92";
when "0110" => seg<= x"82";
when "0111" => seg<= x"F8";
when "1000" => seg<= x"80";
when "1001" => seg<= x"90";
when others =>NULL;
end case;
end process;
end D1_C1;
-- rst =100khz, sel=0.5Mhz, clk=20Mhz.
| apache-2.0 | 0ce951427fbc0fae735f5e7f4c336b2d | 0.50316 | 2.910345 | false | false | false | false |
SoCdesign/EHA | RTL/Immortal_Chip/modules_with_fault_injectors/shift_register_serial_in.vhd | 1 | 972 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity shift_register_serial_in is
generic (
REG_WIDTH: integer := 8
);
port (
clk, reset : in std_logic;
shift: in std_logic;
data_in_serial: in std_logic;
data_out_parallel: out std_logic_vector(REG_WIDTH-1 downto 0);
data_out_serial: out std_logic
);
end;
architecture behavior of shift_register_serial_in is
signal shift_register_mem_out : std_logic_vector(REG_WIDTH-1 downto 0);
begin
process (clk, reset)
begin
if reset = '0' then
shift_register_mem_out <= (others => '0');
elsif clk'event and clk = '1' then
if shift = '1' then
shift_register_mem_out <= shift_register_mem_out (REG_WIDTH-2 downto 0) & data_in_serial;
end if;
end if;
end process;
data_out_parallel <= shift_register_mem_out;
data_out_serial <= shift_register_mem_out (REG_WIDTH-2);
end; | gpl-3.0 | 4331a7f7d43ff1127233072266b2dd73 | 0.633745 | 3.218543 | false | false | false | false |
bruskajp/EE-316 | Project2/Quartus_DE2Board/Reset_Delay.vhd | 1 | 634 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.numeric_std.ALL;
use IEEE.STD_LOGIC_ARITH;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY Reset_Delay IS
PORT (
SIGNAL iCLK : IN std_logic;
SIGNAL oRESET : OUT std_logic
);
END Reset_Delay;
ARCHITECTURE Arch OF Reset_Delay IS
SIGNAL Cont : std_logic_vector(19 DOWNTO 0):=X"00000";
BEGIN
PROCESS
BEGIN
WAIT UNTIL rising_edge (iCLK);
-- IF Cont /= X"FFFFF" THEN
IF Cont /= X"0000F" THEN --changed
Cont <= Cont + '1';
oRESET <= '1';
ELSE
oRESET <= '0';
END IF;
END PROCESS;
END Arch; | gpl-3.0 | 9f920fa6e77aebafab6da5e96a4f5948 | 0.589905 | 3.268041 | false | false | false | false |
hanyazou/vivado-ws | playpen/dvi2vga_nofilter/dvi2vga_nofilter.srcs/sources_1/bd/design_1/ip/design_1_rgb2vga_0_0/sim/design_1_rgb2vga_0_0.vhd | 2 | 4,708 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: digilentinc.com:ip:rgb2vga:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_rgb2vga_0_0 IS
PORT (
rgb_pData : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_pVDE : IN STD_LOGIC;
rgb_pHSync : IN STD_LOGIC;
rgb_pVSync : IN STD_LOGIC;
PixelClk : IN STD_LOGIC;
vga_pRed : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
vga_pGreen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
vga_pBlue : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
vga_pHSync : OUT STD_LOGIC;
vga_pVSync : OUT STD_LOGIC
);
END design_1_rgb2vga_0_0;
ARCHITECTURE design_1_rgb2vga_0_0_arch OF design_1_rgb2vga_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_rgb2vga_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT rgb2vga IS
GENERIC (
VID_IN_DATA_WIDTH : INTEGER;
kRedDepth : INTEGER;
kGreenDepth : INTEGER;
kBlueDepth : INTEGER
);
PORT (
rgb_pData : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_pVDE : IN STD_LOGIC;
rgb_pHSync : IN STD_LOGIC;
rgb_pVSync : IN STD_LOGIC;
PixelClk : IN STD_LOGIC;
vga_pRed : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
vga_pGreen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
vga_pBlue : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
vga_pHSync : OUT STD_LOGIC;
vga_pVSync : OUT STD_LOGIC
);
END COMPONENT rgb2vga;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF rgb_pData: SIGNAL IS "xilinx.com:interface:vid_io:1.0 vid_in DATA";
ATTRIBUTE X_INTERFACE_INFO OF rgb_pVDE: SIGNAL IS "xilinx.com:interface:vid_io:1.0 vid_in ACTIVE_VIDEO";
ATTRIBUTE X_INTERFACE_INFO OF rgb_pHSync: SIGNAL IS "xilinx.com:interface:vid_io:1.0 vid_in HSYNC";
ATTRIBUTE X_INTERFACE_INFO OF rgb_pVSync: SIGNAL IS "xilinx.com:interface:vid_io:1.0 vid_in VSYNC";
ATTRIBUTE X_INTERFACE_INFO OF PixelClk: SIGNAL IS "xilinx.com:signal:clock:1.0 signal_clock CLK";
BEGIN
U0 : rgb2vga
GENERIC MAP (
VID_IN_DATA_WIDTH => 24,
kRedDepth => 5,
kGreenDepth => 6,
kBlueDepth => 5
)
PORT MAP (
rgb_pData => rgb_pData,
rgb_pVDE => rgb_pVDE,
rgb_pHSync => rgb_pHSync,
rgb_pVSync => rgb_pVSync,
PixelClk => PixelClk,
vga_pRed => vga_pRed,
vga_pGreen => vga_pGreen,
vga_pBlue => vga_pBlue,
vga_pHSync => vga_pHSync,
vga_pVSync => vga_pVSync
);
END design_1_rgb2vga_0_0_arch;
| mit | 258dc055114261d86f52991675226078 | 0.705395 | 3.769416 | false | false | false | false |
bruskajp/EE-316 | Project1/seven_seg_driver.vhd | 1 | 1,927 | -- Author: Zander Blasingame
-- Class: EE 316 Spring 2017
-- Description: Seven Segment Display driver
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity seven_seg_driver is
port(
data : in std_logic_vector(15 downto 0);
address : in std_logic_vector(7 downto 0);
hex0 : out std_logic_vector(7 downto 0);
hex1 : out std_logic_vector(7 downto 0);
hex2 : out std_logic_vector(7 downto 0);
hex3 : out std_logic_vector(7 downto 0);
hex4 : out std_logic_vector(7 downto 0);
hex5 : out std_logic_vector(7 downto 0)
);
end seven_seg_driver;
architecture Behavioral of seven_seg_driver is
-- Function to convert hex into seven seg
function hex_to_seven(hex_code : std_logic_vector(3 downto 0))
return std_logic_vector is
variable output : std_logic_vector(7 downto 0) := x"00";
begin
-- Character Lookup table
case hex_code is
when x"0" => output := "00111111";
when x"1" => output := "00000110";
when x"2" => output := "01011011";
when x"3" => output := "01001111";
when x"4" => output := "01100110";
when x"5" => output := "01101101";
when x"6" => output := "01111101";
when x"7" => output := "00000111";
when x"8" => output := "01111111";
when x"9" => output := "01100111";
when x"A" => output := "01110111";
when x"B" => output := "01111100";
when x"C" => output := "00111001";
when x"D" => output := "01011110";
when x"E" => output := "01111001";
when x"F" => output := "01110001";
when others => output := "00000000";
end case;
return not output;
end hex_to_seven;
begin
hex5 <= hex_to_seven(address(7 downto 4));
hex4 <= hex_to_seven(address(3 downto 0));
hex3 <= hex_to_seven(data(15 downto 12));
hex2 <= hex_to_seven(data(11 downto 8));
hex1 <= hex_to_seven(data(7 downto 4));
hex0 <= hex_to_seven(data(3 downto 0));
end Behavioral; | gpl-3.0 | d197e5b903158ff34b550f50fcc32e88 | 0.616502 | 3.001558 | false | false | false | false |
carlosrd/DAS | P7/tronLegacy.vhd | 1 | 27,225 | -------------------------------------------------------------------
--
-- Fichero:
-- damero.vhd 12/7/2013
--
-- (c) J.M. Mendias
-- Diseño Automático de Sistemas
-- Facultad de Informática. Universidad Complutense de Madrid
--
-- Propósito:
-- Muestra un damero sobre un monitor compatible VGA
--
-- Notas de diseño:
-- La sincronización con la pantalla VGA presupone que la
-- frecuencia de reloj del sistema es de 50 MHz
--
-------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
library UNISIM;
use UNISIM.vcomponents.all;
ENTITY tron IS
PORT (
rst: IN std_logic;
clk: IN std_logic;
ps2Data : IN std_logic;
ps2Clk : IN std_logic;
hSyncQ : OUT std_logic;
vSyncQ : OUT std_logic;
RGBQ : OUT std_logic_vector(8 DOWNTO 0)
);
END tron;
ARCHITECTURE tronArch OF tron IS
-- MEMORIA DE REFRESCO
component RAMB16_S1_s1
generic(
WRITE_MODE_A : string := "READ_FIRST";
WRITE_MODE_B : string := "READ_FIRST"
);
port(
DOA0: out std_logic; -- Salida de datos
DOB0: out std_logic;
ADDRA: in std_logic_vector(13 downto 0); -- Direccion
ADDRB: in std_logic_vector(13 downto 0);
CLKA: in std_ulogic; -- Reloj
CLKB: in std_ulogic;
DIA0: in std_logic; -- Entrada de datos
DIB0: in std_logic;
ENA: in std_ulogic; -- Entrada capacitacion
ENB: in std_ulogic;
SSRA: in std_ulogic; -- Inicializacion sincrona para los latches de salida
SSRB: in std_ulogic;
WEA: in std_ulogic; -- Entrada capacitacion escritura
WEB: in std_ulogic
);
end component;
-- SEÑALES VGA
signal pixelCntOut: std_logic_vector(10 downto 0);
signal lineCntOut: std_logic_vector(9 downto 0);
signal blanking, valor: std_logic;
-- SEÑALES PARA PINTAR
signal hSync, vSync : std_logic;
signal RGB : std_logic_vector(8 downto 0);
signal salidaRojo, salidaAzul : std_logic;
signal motoAzul, estelaAzul, motoRoja, estelaRoja : std_logic;
-- MEMORIA DE REFRESCO
signal dirRefrescoVGA, dirEscrituraAzul, dirTrayectoAzul, dirEscrituraRoja, dirTrayectoRoja: std_logic_vector(14 downto 0);
signal readFirstAzul1,DOB0,readFirstAzul2,DOB1,readFirstRoja1,DOB2,readFirstRoja2,DOB3 : std_logic;
signal valorEscritura , enableEscritura: std_logic;
-- LIMPIEZA DE LA MEMORIA
signal limpiarMemoria,limpiezaCompletada : std_logic;
signal csCiclosLimpieza: std_logic_vector(22 downto 0);
-- CONTADORES MOTOS: PELOTA
signal csMotoAzulY: std_logic_vector(6 downto 0); -- 7 bits
signal csMotoAzulX: std_logic_vector(7 downto 0); -- 8 bits
signal csMotoRojaY: std_logic_vector(6 downto 0);
signal csMotoRojaX: std_logic_vector(7 downto 0);
-- CONTROL DIRECCION DE LAS MOTOS
type DIR_MOTO is (ARRIBA, ABAJO, IZQUIERDA, DERECHA);
signal dirMotoAzul, dirMotoAzulNext, dirMotoRoja, dirMotoRojaNext: DIR_MOTO;
-- RALENTIZADOR
signal csRalentizador : std_logic_vector(22 downto 0);
signal mueve : std_logic;
-- VARIABLES DE JUEGO
signal hayGanador, partidaEnCurso, iniciarMotos : std_logic;
signal choqueContrario, choquePropioAzul, choquePropioRoja : std_logic;
-- INTERFAZ TECLADO PS/2
signal data : std_logic_vector (7 DOWNTO 0); -- Salida de datos paralela
signal newData : std_logic; -- Indica la recepción de un nuevo dato por la línea PS2
signal newDataAck : std_logic; -- Reconoce la recepción del nuevo dato
signal ldData, validData, lastBitRcv, ps2ClkSync, ps2ClkFallingEdge: std_logic;
signal ps2DataRegOut: std_logic_vector(10 downto 0);
signal goodParity: std_logic;
-- MAQUINA DE ESTADOS PARA EL CONTROL DE TECLAS
type ESTADOS is (WAITING_PRESS, RELEASE_BUTTON);
signal ESTADO, SIG_ESTADO: ESTADOS;
signal flagSPC, flagSPCnext : std_logic;
-- MAQUINA DE ESTADOS PARA EL CONTROL DEL JUEGO
type GAME_STATES is (WAITING_SPACE, INITIALIZING_GAME, WAITING_WINNER);
signal GAME, NEXT_GAME: GAME_STATES;
BEGIN
pixelCnt:
PROCESS( rst, clk )
BEGIN
IF (rst='0') THEN
pixelCntOut <= (OTHERS=>'0');
ELSIF(clk'EVENT AND clk='1') THEN
IF (pixelCntOut=1588) THEN
pixelCntOut <= (OTHERS=>'0');
ELSE
pixelCntOut <= pixelCntOut+1;
END IF;
END IF;
END PROCESS pixelCnt;
lineCnt:
PROCESS( rst, clk )
BEGIN
IF (rst='0') THEN
lineCntOut <= (OTHERS=>'0');
ELSIF (clk'EVENT AND clk='1') THEN
IF (pixelCntOut=1588) THEN
IF (lineCntOut=527) THEN
lineCntOut <= (others=>'0');
ELSE
lineCntOut <= lineCntOut+1;
END IF;
END IF;
END IF;
END PROCESS lineCnt;
hSync <= '0' WHEN (pixelCntOut > 1304) AND (pixelCntOut <= 1493) ELSE '1';
vSync <= '0' WHEN (lineCntOut > 493) AND (lineCntOut <= 495) ELSE '1';
blanking <= '1' WHEN (pixelCntOut > 1257) OR (lineCntOut > 479) ELSE '0';
--RGB <= salidaRojo & salidaRojo & salidaRojo & '0' & '0' & '0' & salidaAzul & salidaAzul & salidaAzul;
RGB <= salidaAzul & salidaAzul & salidaAzul & '0' & '0' & '0' & salidaRojo & salidaRojo & salidaRojo;
-------------------------------------------------------------------------------------
-- INTRODUCIR CODIGO DESDE AQUI
-- | | | | |
-- v v v v v
-- COMO VA EL LINECOUNT PARA HACER LINEAS MAS GORDAS:
-- 0100
-- 0101
-- 0110
-- 0111
-- 1100 -> Hay que fijarse cuales son los bits comunes para ir
-- 1101 diviendo entre 2. (Con esto, son numeros modulo 2, 4, 8 .. etc)
-- 1110
-- 1111
-- INSTACIAMOS MEMORIA REFRESCO
-- *******************************************************************************
-- Usar una memoria de doble puerto:
-- * los coches almacenan su estela por un puerto (úsese también para borrar estelas)
-- * el refresco se realiza leyendo desde el otro => (Escritura => A y Lectura => B)
-- * para evitar conflictos de lectura y escritura simultánea configurarla en modo READ_FIRST
-- Para simplificar la lógica de direccionamiento (a costa de desperdiciar memoria) usar
-- una de 32Kx2b organizada en 2 slices: uno para el coche rojo y otro para el azul
-- * la dirección de un pixel se obtiene concatenado parte de lineCnt con parte de pixelCnt
-- * usar 4 RAM Blocks de 16 K×1b
-- * Usaremos 2 memorias para cada moto para poder direccionar toda la pantalla.
-- * PxCountMax => 152 px = 8 bits / LineCountMax => 119 px = 7 bits ==> 15 bits
-- * Direccionamos hasta la linea 63 en la primera memoria y de la 64 a la 119 en la segunda memoria
-- * Para distinguir la primera memoria de la segunda usamos bit mas significativo (el de la pos 14 que indica el 64)
-- Para el refresco de la pantalla, leeremos por el puerto B la direccion resultante de
-- concatenar una parte de lineCnt con parte de PixelCnt
dirRefrescoVGA <= lineCntOut(8 downto 2) & pixelCntOut(10 downto 3);
-- Para guardar en memoria la estela azul, usamos como direccion la concatenacion de la
-- coordenada Y (lineCnt) y la X (pixelCnt)
dirTrayectoAzul <= csMotoAzulY & csMotoAzulX;
dirTrayectoRoja <= csMotoRojaY & csMotoRojaX;
-- MEMORIAS MOTO AZUL
-- ···········································································
enableEscritura <= mueve OR limpiarMemoria;
memAzul_1: RAMB16_S1_s1
port map(
readFirstAzul1, -- Salida de Datos (A - Escritura) - Sirve para saber si chocamos contra nuestra propia estela.
DOB0, -- Salida de Datos (B - Lectura)
dirEscrituraAzul(13 downto 0), -- Direccion de escritura (A): Durante el juego es la posicion de la moto y durante la limpieza el Px/ln count
dirRefrescoVGA(13 downto 0), -- Direccion de lectura (B)
clk, -- Mismo reloj para ambos puertos
clk,
valorEscritura, -- Sera 1 durante el juego y 0 durante la limpieza de la memoria
'0', -- Nunca escribimos por el puerto B, asi que ponemos 0 como valor Din por poner algo
not dirEscrituraAzul(14), -- ENABLE A: El modulo de escritura estara activo cuando el lineCnt sea menor que 64
not dirRefrescoVGA(14), -- ENABLE B: El modulo de lectura estara activo cuando el lineCnt sea menor que 64
'0', -- Desactivamos la limpieza de los latches de salida
'0',
enableEscritura, -- Escritura habilitada en puerto A cuando se ha realizado movimiento o durante limpieza
'0' -- Escritura NO habilitada en puerto B
);
memAzul_2: RAMB16_S1_s1
port map(
readFirstAzul2, -- Salida de Datos (A - Escritura) - Sirve para saber si chocamos contra nuestra propia estela.
DOB1, -- Salida de Datos (B - Lectura)
dirEscrituraAzul(13 downto 0),-- Direccion de escritura (A): Durante el juego es la posicion de la moto y durante la limpieza el Px/ln count
dirRefrescoVGA(13 downto 0), -- Direccion de lectura (B)
clk, -- Mismo reloj para ambos puertos
clk,
valorEscritura, -- Sera 1 durante el juego y 0 durante la limpieza de la memoria
'0', -- Nunca escribimos por el puerto B, asi que ponemos 0 como valor Din por poner algo
dirEscrituraAzul(14), -- ENABLE A: El modulo de escritura estara activo cuando el lineCnt sea mayor o igual que 64
dirRefrescoVGA(14), -- ENABLE B: El modulo de lectura estara activo cuando el lineCnt sea mayor o igual que 64
'0', -- Desactivamos la limpieza de los latches de salida
'0',
enableEscritura, -- Escritura habilitada en puerto A cuando se ha realizado movimiento o durante limpieza
'0' -- Escritura NO habilitada en puerto B
);
estelaAzul <= DOB0 OR DOB1;
-- MEMORIAS MOTO ROJA
-- ···········································································
memRoja_1: RAMB16_S1_s1
port map(
readFirstRoja1, -- Salida de Datos (A - Escritura) - Sirve para saber si chocamos contra nuestra propia estela.
DOB2, -- Salida de Datos (B - Lectura)
dirEscrituraRoja(13 downto 0),-- Direccion de escritura (A): Durante el juego es la posicion de la moto y durante la limpieza el Px/ln count
dirRefrescoVGA(13 downto 0), -- Direccion de lectura (B)
clk, -- Mismo reloj para ambos puertos
clk,
valorEscritura, -- Sera 1 durante el juego y 0 durante la limpieza de la memoria
'0', -- Nunca escribimos por el puerto B, asi que ponemos 0 como valor Din por poner algo
not dirEscrituraRoja(14), -- ENABLE A: El modulo de escritura estara activo cuando el lineCnt sea menor que 64
not dirRefrescoVGA(14), -- ENABLE B: El modulo de lectura estara activo cuando el lineCnt sea menor que 64
'0', -- Desactivamos la limpieza de los latches de salida
'0',
enableEscritura, -- Escritura habilitada en puerto A cuando se ha realizado movimiento o durante limpieza
'0' -- Escritura NO habilitada en puerto B
);
memRoja_2: RAMB16_S1_s1
port map(
readFirstRoja2, -- Salida de Datos (A - Escritura) - Sirve para saber si chocamos contra nuestra propia estela.
DOB3, -- Salida de Datos (B - Lectura)
dirEscrituraRoja(13 downto 0),-- Direccion de escritura (A): Durante el juego es la posicion de la moto y durante la limpieza el Px/ln count
dirRefrescoVGA(13 downto 0), -- Direccion de lectura (B)
clk, -- Mismo reloj para ambos puertos
clk,
valorEscritura, -- Sera 1 durante el juego y 0 durante la limpieza de la memoria
'0', -- Nunca escribimos por el puerto B, asi que ponemos 0 como valor Din por poner algo
dirEscrituraRoja(14), -- ENABLE A: El modulo de escritura estara activo cuando el lineCnt sea mayor o igual que 64
dirRefrescoVGA(14), -- ENABLE B: El modulo de lectura estara activo cuando el lineCnt sea mayor o igual que 64
'0', -- Desactivamos la limpieza de los latches de salida
'0',
enableEscritura, -- Escritura habilitada en puerto A cuando se ha realizado movimiento o durante limpieza
'0' -- Escritura NO habilitada en puerto B
);
estelaRoja <= DOB2 OR DOB3;
-- LIMPIEZA DE LA MEMORIA: Contador para esperar durante la limpieza. Cuando el contador finalice la memoria estará limpia.
-- *******************************************************************************
ciclosLimpiezaCnt:
process( clk, rst, csCiclosLimpieza, limpiarMemoria)
begin
if rst = '0' then
limpiezaCompletada <= '0';
csCiclosLimpieza <= (others => '0');
elsif clk'event and clk = '1' then
if limpiarMemoria = '1' then
if csCiclosLimpieza = 5000000 then
limpiezaCompletada <= '1';
else
csCiclosLimpieza <= csCiclosLimpieza + 1;
limpiezaCompletada <= '0';
end if;
else
csCiclosLimpieza <= (others => '0');
limpiezaCompletada <= '0';
end if;
end if;
end process;
-- Durante la limpieza la direccion de escritura es la de refrescoVGA para limpiar (valor 0) toda la pantalla
-- Durante el juego la direccion de escritura es la de los contadores de posicion (valor 1) de las motos.
dirEscrituraAzul <= dirRefrescoVGA WHEN limpiarMemoria = '1' ELSE dirTrayectoAzul;
dirEscrituraRoja <= dirRefrescoVGA WHEN limpiarMemoria = '1' ELSE dirTrayectoRoja;
valorEscritura <= '0' WHEN limpiarMemoria = '1' ELSE '1';
-- DETECTOR DE COLISIONES
-- *******************************************************************************
choqueContrario <= '1' WHEN (DOB0 = '1' AND DOB2 = '1') OR (DOB1 = '1' AND DOB3 = '1') ELSE '0';
choquePropioRoja <= '1' WHEN ((readFirstRoja1 = '1' AND dirEscrituraRoja(14) = '0') OR
(readFirstRoja2 = '1' AND dirEscrituraRoja(14) = '1')) AND
csRalentizador = 0 ELSE '0';
choquePropioAzul <= '1' WHEN ((readFirstAzul1 = '1' AND dirEscrituraAzul(14) = '0') OR
(readFirstAzul2 = '1' AND dirEscrituraAzul(14) = '1')) AND
csRalentizador = 0 ELSE '0';
hayGanador <= choqueContrario OR choquePropioRoja OR choquePropioAzul;
-- PINTAR MOTO AZUL
-- *******************************************************************************
motoAzulY:
process( clk, rst, csMotoAzulY, mueve, dirMotoAzul, iniciarMotos)
begin
if rst = '0' then
csMotoAzulY <= conv_std_logic_vector( 111 , 7 ); -- Abajo de la pantalla (7 bits)
elsif clk'event and clk='1' then
if iniciarMotos = '1' then
csMotoAzulY <= conv_std_logic_vector( 111 , 7 );
elsif mueve = '1' then
-- Ajustar conteo en funcion de la direccion
if dirMotoAzul = ARRIBA then
csMotoAzulY <= csMotoAzulY - 1;
elsif dirMotoAzul = ABAJO then
csMotoAzulY <= csMotoAzulY + 1;
end if;
-- Si se sale por el borde de arriba (0 px) o el de abajo (119 px) aparecer por el contrario
if csMotoAzulY = 0 and dirMotoAzul = ARRIBA then
csMotoAzulY <= conv_std_logic_vector( 119 , 7 );
elsif csMotoAzulY = 119 and dirMotoAzul = ABAJO then
csMotoAzulY <= conv_std_logic_vector( 0 , 7 );
end if;
end if;
end if;
end process;
motoAzulX:
process( clk, rst , csMotoAzulX, mueve, dirMotoAzul, iniciarMotos)
begin
if rst = '0' then
csMotoAzulX <= conv_std_logic_vector( 152 , 8 );
elsif clk'event and clk='1' then
if iniciarMotos = '1' then
csMotoAzulX <= conv_std_logic_vector( 152 , 8 );
elsif mueve = '1' then
-- Ajustar conteo en funcion de la direccion
if dirMotoAzul = IZQUIERDA then
csMotoAzulX <= csMotoAzulX - 1;
elsif dirMotoAzul = DERECHA then
csMotoAzulX <= csMotoAzulX + 1;
end if;
-- Si se sale por el borde de arriba (0 px) o el de abajo (119 px) aparecer por el contrario
if csMotoAzulX = 0 and dirMotoAzul = IZQUIERDA then
csMotoAzulX <= conv_std_logic_vector( 152 , 8 );
elsif csMotoAzulX = 152 and dirMotoAzul = DERECHA then
csMotoAzulX <= conv_std_logic_vector( 0 , 8 );
end if;
end if;
end if;
end process;
-- La moto azul se pinta donde marquen los contadores de los ejes X e Y
motoAzul <= '1' WHEN (pixelCntOut(10 downto 3) > csMotoAzulX-2) AND (pixelCntOut(10 downto 3) < csMotoAzulX+2) AND
(lineCntOut(8 downto 2) > csMotoAzulY-2) AND (lineCntOut(8 downto 2) < csMotoAzulY+2) ELSE '0';
-- PINTAR MOTO ROJA
-- *******************************************************************************
motoRojaY:
process( clk, rst , mueve, csMotoRojaY, mueve, dirMotoRoja, iniciarMotos)
begin
if rst = '0' then
csMotoRojaY <= conv_std_logic_vector( 7, 7 );
elsif clk'event and clk='1' then
if iniciarMotos = '1' then
csMotoRojaY <= conv_std_logic_vector( 7 , 7 );
elsif mueve = '1' then
-- Ajustar conteo en funcion de la direccion
if dirMotoRoja = ARRIBA then
csMotoRojaY <= csMotoRojaY - 1;
elsif dirMotoRoja = ABAJO then
csMotoRojaY <= csMotoRojaY + 1;
end if;
-- Si se sale por el borde de arriba (0 px) o el de abajo (119 px) aparecer por el contrario
if csMotoRojaY = 0 and dirMotoRoja = ARRIBA then
csMotoRojaY <= conv_std_logic_vector( 119 , 7 );
elsif csMotoRojaY = 119 and dirMotoRoja = ABAJO then
csMotoRojaY <= conv_std_logic_vector( 0 , 7 );
end if;
end if;
end if;
end process;
motoRojaX:
process( clk, rst , csMotoRojaX, mueve, dirMotoRoja, iniciarMotos)
begin
if rst = '0' then
csMotoRojaX <= conv_std_logic_vector( 2 , 8 );
elsif clk'event and clk='1' then
if iniciarMotos = '1' then
csMotoRojaX <= conv_std_logic_vector( 2 , 8 );
elsif mueve = '1' then
-- Ajustar conteo en funcion de la direccion
if dirMotoRoja = IZQUIERDA then
csMotoRojaX <= csMotoRojaX - 1;
elsif dirMotoRoja = DERECHA then
csMotoRojaX <= csMotoRojaX + 1;
end if;
-- Si se sale por el borde de arriba (0 px) o el de abajo (119 px) aparecer por el contrario
if csMotoRojaX = 0 and dirMotoRoja = IZQUIERDA then
csMotoRojaX <= conv_std_logic_vector( 152 , 8 );
elsif csMotoRojaX = 152 and dirMotoRoja = DERECHA then
csMotoRojaX <= conv_std_logic_vector( 0 , 8 );
end if;
end if;
end if;
end process;
-- La moto roja se pinta donde marquen los contadores de los ejes X e Y
motoRoja <= '1' WHEN (pixelCntOut(10 downto 3) > csMotoRojaX-2) AND (pixelCntOut(10 downto 3) < csMotoRojaX+2) AND
(lineCntOut(8 downto 2) > csMotoRojaY-2) AND (lineCntOut(8 downto 2) < csMotoRojaY+2) ELSE '0';
-- RALENTIZADOR DE MOVIMIENTO: Evita que las motos se muevan demasiado deprisa
-- *******************************************************************************
ralentizador:
process( clk, rst, csRalentizador, partidaEnCurso)
begin
if rst = '0' then
mueve <= '0';
csRalentizador <= conv_std_logic_vector( 0, 23 );
elsif clk'event and clk = '1' then
if partidaEnCurso = '1' then
if csRalentizador = 2000000 then
mueve <= '1';
csRalentizador <= conv_std_logic_vector( 0, 23 );
else
csRalentizador <= csRalentizador + 1;
mueve <= '0';
end if;
end if;
end if;
end process;
-- RESULTADO FINAL EN MONITOR VGA
-- *******************************************************************************
valor <= NOT blanking;
salidaRojo <= (motoRoja OR estelaRoja) AND NOT blanking;
salidaAzul <= (motoAzul OR estelaAzul) AND NOT blanking;
-- Este biestable evita los glitches en la salida VGA
biestableVGASync:
process(rst, clk)
begin
if rst = '0' then
hSyncQ <= '0';
vSyncQ <= '0';
RGBQ <= valor & valor & valor & valor & valor & valor & valor & valor & valor;
elsif clk'event and clk = '1' then
hSyncQ <= hSync;
vSyncQ <= vSync;
RGBQ <= RGB;
end if;
end process;
-- INTERFAZ TECLADO PS/2
-- *******************************************************************************************
synchronizer:
PROCESS (rst, clk)
VARIABLE aux1: std_logic;
BEGIN
IF (rst='0') THEN
aux1 := '1';
ps2ClkSync <= '1';
ELSIF (clk'EVENT AND clk='1') THEN
ps2ClkSync <= aux1;
aux1 := ps2Clk;
END IF;
END PROCESS synchronizer;
edgeDetector:
PROCESS (rst, clk)
VARIABLE aux1, aux2: std_logic;
BEGIN
ps2ClkFallingEdge <= (NOT aux1) AND aux2;
IF (rst='0') THEN
aux1 := '1';
aux2 := '1';
ELSIF (clk'EVENT AND clk='1') THEN
aux2 := aux1;
aux1 := ps2ClkSync;
END IF;
END PROCESS edgeDetector;
ps2DataReg:
PROCESS (rst, clk)
BEGIN
IF (rst='0') THEN
ps2DataRegOut <= (OTHERS =>'1');
ELSIF (clk'EVENT AND clk='1') THEN
IF (lastBitRcv='1') THEN
ps2DataRegOut <= (OTHERS=>'1');
ELSIF (ps2ClkFallingEdge='1') THEN
ps2DataRegOut <= ps2Data & ps2DataRegOut(10 downto 1);
END IF;
END IF;
END PROCESS ps2DataReg;
oddParityCheker:
goodParity <=
((ps2DataRegOut(9) XOR ps2DataRegOut(8)) XOR (ps2DataRegOut(7) XOR ps2DataRegOut(6)))
XOR ((ps2DataRegOut(5) XOR ps2DataRegOut(4)) XOR (ps2DataRegOut(3) XOR ps2DataRegOut(2)))
XOR ps2DataRegOut(1);
lastBitRcv <= NOT ps2DataRegOut(0);
validData <= lastBitRcv AND goodParity;
dataReg:
PROCESS (rst, clk)
BEGIN
IF (rst='0') THEN
data <= (OTHERS=>'0');
ELSIF (clk'EVENT AND clk='1') THEN
IF (ldData='1') THEN
data <= ps2DataRegOut(8 downto 1);
END IF;
END IF;
END PROCESS dataReg;
controller:
PROCESS (validData, rst, clk)
TYPE states IS (waitingData, waitingNewDataAck);
VARIABLE state: states;
BEGIN
ldData <= '0';
newData <= '0';
CASE state IS
WHEN waitingData =>
IF (validData='1') THEN
ldData <= '1';
END IF;
WHEN waitingNewDataAck =>
newData <= '1';
WHEN OTHERS => NULL;
END CASE;
IF (rst='0') THEN
state := waitingData;
ELSIF (clk'EVENT AND clk='1') THEN
CASE state IS
WHEN waitingData =>
IF (validData='1') THEN
state := waitingNewDataAck;
END IF;
WHEN waitingNewDataAck =>
IF (newDataAck='1') THEN
state := waitingData;
END IF;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS controller;
-- MAQUINA DE ESTADOS PARA DETECCION DE TECLAS (TECLADO PS/2)
-- *******************************************************************************************
-- MAQUINA ESTADOS: SINCRONO
maqEstadosTecladoSyn:
process(clk,rst)
begin
if rst ='0' then
dirMotoAzul <= IZQUIERDA;
dirMotoRoja <= DERECHA;
flagSPC <= '0';
ESTADO <= WAITING_PRESS;
elsif clk'event and clk='1' then
dirMotoAzul <= dirMotoAzulNext;
dirMotoRoja <= dirMotoRojaNext;
flagSPC <= flagSPCnext;
ESTADO <= SIG_ESTADO;
end if;
end process;
-- MAQUINA ESTADOS: COMBINACIONAL
maqEstadosTecladoComb:
process(ESTADO, newData, data, dirMotoAzul, dirMotoRoja)
begin
dirMotoAzulNext <= dirMotoAzul;
dirMotoRojaNext <= dirMotoRoja;
flagSPCnext <= flagSPC;
SIG_ESTADO <= ESTADO;
case ESTADO is
when WAITING_PRESS =>
newDataAck <= '1';
if newData = '1' then
case data is
-- Si es F0, es una liberacion de tecla
when "11110000" => SIG_ESTADO <= RELEASE_BUTTON;
-- CONTROL MOTO ROJA
-- ···········································································
-- Si es Q = 15 (hex) y NO va hacia abajo
when "00010101" => if dirMotoRoja = IZQUIERDA OR dirMotoRoja = DERECHA then
dirMotoRojaNext <= ARRIBA;
end if;
-- Si es A = 1C (hex) y NO va hacia arriba
when "00011100" => if dirMotoRoja = IZQUIERDA OR dirMotoRoja = DERECHA then
dirMotoRojaNext <= ABAJO;
end if;
-- Si es Z = 1A (hex) y NO va hacia la derecha
when "00011010" => if dirMotoRoja = ARRIBA OR dirMotoRoja = ABAJO then
dirMotoRojaNext <= IZQUIERDA;
end if;
-- Si es X = 22 (hex) y NO va hacia izquierda
when "00100010" => if dirMotoRoja = ARRIBA OR dirMotoRoja = ABAJO then
dirMotoRojaNext <= DERECHA;
end if;
-- CONTROL MOTO AZUL
-- ···········································································
-- Si es P = 4D (hex) y NO va hacia abajo
when "01001101" => if dirMotoAzul = IZQUIERDA OR dirMotoAzul = DERECHA then
dirMotoAzulNext <= ARRIBA;
end if;
-- Si es L = 4B (hex) y NO va hacia arriba
when "01001011" => if dirMotoAzul = IZQUIERDA OR dirMotoAzul = DERECHA then
dirMotoAzulNext <= ABAJO;
end if;
-- Si es N = 31 (hex) y NO va hacia la derecha
when "00110001" => if dirMotoAzul = ARRIBA OR dirMotoAzul = ABAJO then
dirMotoAzulNext <= IZQUIERDA;
end if;
-- Si es M = 3A (hex) y NO va hacia izquierda
when "00111010" => if dirMotoAzul = ARRIBA OR dirMotoAzul = ABAJO then
dirMotoAzulNext <= DERECHA;
end if;
when "00101001" => flagSPCnext <= '1'; -- Si es SPACE = 29 (hex), activamos flag de SPACE
when others => SIG_ESTADO <= WAITING_PRESS;
end case;
end if;
when RELEASE_BUTTON =>
newDataAck <= '1';
flagSPCnext <= '0';
-- No hacemos nada; consumimos liberacion de tecla para no confundirla con una pulsacion
if newData = '1' then
-- Si es el SPC y antes de empezar la partida
if data = "00101001" AND partidaEnCurso = '0' then
dirMotoAzulNext <= IZQUIERDA;
dirMotoRojaNext <= DERECHA;
end if;
SIG_ESTADO <= WAITING_PRESS;
end if;
end case;
end process;
-- MAQUINA DE ESTADOS PARA EL JUEGO
-- *******************************************************************************************
-- MAQUINA ESTADOS: SINCRONO
maqEstadosJuegoSyn:
process(clk,rst)
begin
if rst ='0' then
GAME <= WAITING_SPACE;
elsif clk'event and clk='1' then
GAME <= NEXT_GAME;
end if;
end process;
-- MAQUINA ESTADOS: COMBINACIONAL
maqEstadosJuegoComb:
process(GAME, flagSPC, hayGanador, limpiezaCompletada)
begin
case GAME is
when WAITING_SPACE =>
partidaEnCurso <= '0';
iniciarMotos <= '0';
limpiarMemoria <= '0';
NEXT_GAME <= WAITING_SPACE;
if flagSPC = '1' then
limpiarMemoria <= '1';
NEXT_GAME <= INITIALIZING_GAME;
end if;
when INITIALIZING_GAME =>
partidaEnCurso <= '0';
iniciarMotos <= '1';
limpiarMemoria <= '1';
NEXT_GAME <= INITIALIZING_GAME;
if limpiezaCompletada = '1' then
limpiarMemoria <= '0';
NEXT_GAME <= WAITING_WINNER;
end if;
when WAITING_WINNER =>
partidaEnCurso <= '1';
iniciarMotos <= '0';
limpiarMemoria <= '0';
NEXT_GAME <= WAITING_WINNER;
if hayGanador = '1'then
NEXT_GAME <= WAITING_SPACE;
end if;
end case;
end process;
END tronArch;
| mit | 6314688ed8a6434344e0f6246545e0db | 0.607456 | 3.645554 | false | false | false | false |
SoCdesign/EHA | RTL/Fault_Management/SHMU_prototype/version_2/counter_threshold.vhd | 3 | 3,488 | --Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, Intermittent, Faulty:out std_logic
);
end counter_threshold_classifier;
architecture behavior of counter_threshold_classifier is
signal faulty_counter_in, faulty_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal healthy_counter_in, healthy_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal NET: std_logic; --no error threshold
signal DET: std_logic; --detected error threshold
signal reset_counters: std_logic;
TYPE STATE_TYPE IS (Healthy_state, Intermittent_state, Faulty_state);
SIGNAL state, next_state : STATE_TYPE := Healthy_state;
begin
process(clk, reset)begin
if reset = '0' then
faulty_counter_out <= (others => '0');
healthy_counter_out <= (others => '0');
state <= Healthy_state;
elsif clk'event and clk = '1' then
faulty_counter_out <= faulty_counter_in;
healthy_counter_out <= healthy_counter_in;
state <= next_state;
end if;
end process;
process(faulty_packet, reset_counters, faulty_counter_out)begin
if reset_counters = '1' then
faulty_counter_in <= (others => '0');
elsif faulty_packet = '1' then
faulty_counter_in <= faulty_counter_out + 1;
else
faulty_counter_in <= faulty_counter_out;
end if;
end process;
process(Healthy_packet, reset_counters, healthy_counter_out)begin
if reset_counters = '1' then
healthy_counter_in <= (others => '0');
elsif Healthy_packet = '1' then
healthy_counter_in <= healthy_counter_out + 1;
else
healthy_counter_in <= healthy_counter_out;
end if;
end process;
process(healthy_counter_out, faulty_counter_out) begin
reset_counters <= '0';
DET <= '0';
NET <= '0';
if healthy_counter_out = std_logic_vector(to_unsigned(healthy_counter_threshold, healthy_counter_out'length)) then
NET <= '1';
reset_counters <= '1';
end if;
if faulty_counter_out = std_logic_vector(to_unsigned(faulty_counter_threshold, faulty_counter_out'length)) then
DET <= '1';
reset_counters <= '1';
end if;
end process;
process (NET, DET, state)begin
Healthy <= '0';
Intermittent <= '0';
Faulty <= '0';
case state is
when Healthy_state =>
Healthy <= '1';
if NET = '1' then
next_state <= Healthy_state;
elsif DET = '1' then
next_state <= Intermittent_state;
else
next_state <= Healthy_state;
end if;
when Intermittent_state =>
Intermittent <= '1';
if NET = '1' then
next_state <= Healthy_state;
elsif DET = '1' then
next_state <= Faulty_state;
else
next_state <= Intermittent_state;
end if;
when Faulty_state =>
Faulty <= '1';
next_state <= Faulty_state;
when others =>
next_state <= Healthy_state;
end case;
end process;
END; | gpl-3.0 | c5f47ae1debb0b9b117332aeefc614f8 | 0.617259 | 3.68321 | false | false | false | false |
SoCdesign/EHA | RTL/Fault_Management/Fault_management_network/FIFO_one_hot_LV_CB.vhd | 1 | 5,348 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_LV is
generic (
DATA_WIDTH: integer := 11
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end FIFO_LV;
architecture behavior of FIFO_LV is
signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(1 downto 0);
signal full, empty: std_logic;
signal read_en, write_en: std_logic;
signal FIFO_MEM_1, FIFO_MEM_1_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_2, FIFO_MEM_2_in : std_logic_vector(DATA_WIDTH-1 downto 0);
--signal FIFO_MEM_3, FIFO_MEM_3_in : std_logic_vector(DATA_WIDTH-1 downto 0);
--signal FIFO_MEM_4, FIFO_MEM_4_in : std_logic_vector(DATA_WIDTH-1 downto 0);
begin
--------------------------------------------------------------------------------------------
-- block diagram of the FIFO!
--------------------------------------------------------------------------------------------
-- circular buffer structure
-- <--- WriteP
-- ---------------------------------
-- | 3 | 2 | 1 | 0 |
-- ---------------------------------
-- <--- readP
--------------------------------------------------------------------------------------------
process (clk, reset)begin
if reset = '0' then
read_pointer <= "01";
write_pointer <= "01";
FIFO_MEM_1 <= (others=>'0');
FIFO_MEM_2 <= (others=>'0');
--FIFO_MEM_3 <= (others=>'0');
--FIFO_MEM_4 <= (others=>'0');
credit_out <= '0';
elsif clk'event and clk = '1' then
write_pointer <= write_pointer_in;
credit_out <= '0';
if write_en = '1' then
--write into the memory
FIFO_MEM_1 <= FIFO_MEM_1_in;
FIFO_MEM_2 <= FIFO_MEM_2_in;
--FIFO_MEM_3 <= FIFO_MEM_3_in;
--FIFO_MEM_4 <= FIFO_MEM_4_in;
end if;
if read_en = '1' then
credit_out <= '1';
end if;
read_pointer <= read_pointer_in;
end if;
end process;
-- anything below here is pure combinational
-- combinatorial part
process(RX, write_pointer, FIFO_MEM_1, FIFO_MEM_2--, FIFO_MEM_3, FIFO_MEM_4
)begin
case( write_pointer ) is
when "01" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; --FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "10" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; --FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
--when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
--when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; -- FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
end process;
process(read_pointer, FIFO_MEM_1, FIFO_MEM_2 --, FIFO_MEM_3, FIFO_MEM_4
)begin
case( read_pointer ) is
when "01" => Data_out <= FIFO_MEM_1;
when "10" => Data_out <= FIFO_MEM_2;
--when "0100" => Data_out <= FIFO_MEM_3;
--when "1000" => Data_out <= FIFO_MEM_4;
when others => Data_out <= FIFO_MEM_1;
end case ;
end process;
read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty;
empty_out <= empty;
process(write_en, write_pointer)begin
if write_en = '1'then
write_pointer_in <= write_pointer(0)&write_pointer(1);
else
write_pointer_in <= write_pointer;
end if;
end process;
process(read_en, empty, read_pointer)begin
if (read_en = '1' and empty = '0') then
read_pointer_in <= read_pointer(0)&read_pointer(1);
else
read_pointer_in <= read_pointer;
end if;
end process;
process(full, valid_in) begin
if valid_in = '1' and full ='0' then
write_en <= '1';
else
write_en <= '0';
end if;
end process;
process(write_pointer, read_pointer) begin
if read_pointer = write_pointer then
empty <= '1';
else
empty <= '0';
end if;
-- if write_pointer = read_pointer>>1 then
if write_pointer = read_pointer(0)&read_pointer(1) then
full <= '1';
else
full <= '0';
end if;
end process;
end;
| gpl-3.0 | 678d6086958756eae71c5e3891bc95ad | 0.476814 | 3.45255 | false | false | false | false |
SoCdesign/EHA | RTL/Immortal_Chip/shift_register.vhd | 1 | 1,051 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity shift_register is
generic (
REG_WIDTH: integer := 8
);
port (
clk, reset : in std_logic;
shift: in std_logic;
data_in: in std_logic_vector(REG_WIDTH-1 downto 0);
data_out_parallel: out std_logic_vector(REG_WIDTH-1 downto 0);
data_out_serial: out std_logic
);
end;
architecture behavior of shift_register is
signal shift_register_mem_out : std_logic_vector(REG_WIDTH-1 downto 0);
begin
process (clk, reset)
begin
if reset = '0' then
shift_register_mem_out <= (others => '0');
elsif clk'event and clk = '1' then
if shift = '1' then
shift_register_mem_out <= shift_register_mem_out (REG_WIDTH-2 downto 0) & '0';
else
shift_register_mem_out <= data_in or shift_register_mem_out;
end if;
end if;
end process;
data_out_parallel <= shift_register_mem_out;
data_out_serial <= shift_register_mem_out (REG_WIDTH-2);
end; | gpl-3.0 | 875bf9966abb4ed4b1dc8108dddad9c7 | 0.623216 | 3.263975 | false | false | false | false |
lnls-dig/dsp-cores | hdl/testbench/cordic_iter/cordic_tb2.vhd | 1 | 6,081 | -------------------------------------------------------------------------------
-- Title : Testbench for design "cordic_iter_slv"
-- Project :
-------------------------------------------------------------------------------
-- File : cordic_iter_slv_tb.vhd
-- Author : Vitor Finotti Ferreira <vfinotti@finotti-Inspiron-7520>
-- Company : Brazilian Synchrotron Light Laboratory, LNLS/CNPEM
-- Created : 2015-11-23
-- Last update: 2015-11-25
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2015 Brazilian Synchrotron Light Laboratory, LNLS/CNPEM
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public License
-- as published by the Free Software Foundation, either version 3 of
-- the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-11-23 1.0 vfinotti Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
use std.textio.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
use work.test_pkg.all;
library work;
use work.dsp_cores_pkg.all;
-------------------------------------------------------------------------------
entity cordic_tb2 is
end entity cordic_tb2;
-------------------------------------------------------------------------------
architecture behav of cordic_tb2 is
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
constant c_CLK_FREQ : real := 100.0e6;
constant c_CYCLES_TO_CE : natural := 4;
constant c_CYCLES_TO_CE_DATA : natural := 8;
constant c_INPUT_FILE : string := "vectoring_in.samples";
constant c_INPUT_WIDTH : natural := 32;
constant c_OUTPUT_FILE : string := "vectoring_out.samples";
constant c_OUTPUT_WIDTH : natural := 32;
signal end_of_file : std_logic := '0';
-- component generics
constant c_input_width1 : positive := 32;
constant c_stages : positive := 15;
constant c_xy_calc_width : positive := 32 + natural(ceil(log2(real(4))));
constant c_x_output_width : positive := 32;
constant c_phase_calc_width : positive := c_input_width1 + natural(ceil(log2(real(c_stages))))+2;
constant c_phase_output_width : positive := 32;
constant c_iter_per_clk : positive := 3;
constant c_rounding : boolean := true;
-- component ports
signal s_clk : std_logic;
signal s_rst : std_logic;
signal s_ce_data_i : std_logic;
signal s_valid_i : std_logic;
signal s_ce : std_logic;
signal s_valid_o : std_logic;
signal s_stall : std_logic := '0';
signal s_req : std_logic := '0';
signal s_x_i_s : signed(c_input_width1-1 downto 0);
signal s_y_i_s : signed(c_input_width1-1 downto 0);
signal s_mag_o_s : signed(c_x_output_width-1 downto 0);
signal s_phase_o_S : signed(c_phase_output_width-1 downto 0);
begin -- architecture behav
p_clk_gen (
clk => s_clk,
c_FREQ => c_CLK_FREQ);
p_rst_gen (
clk => s_clk,
rst => s_rst,
c_CYCLES => 2);
p_ce_gen (
clk => s_clk,
ce => s_ce,
rst => s_rst,
c_CYCLES => c_CYCLES_TO_CE);
p_ce_gen (
clk => s_clk,
ce => s_ce_data_i,
rst => s_rst,
c_CYCLES => c_CYCLES_TO_CE_DATA);
-- component instantiation
DUT : cordic
generic map (
XY_CALC_WID => c_xy_calc_width,
XY_IN_WID => c_input_width1,
X_OUT_WID => c_x_output_width,
PH_CALC_WID => c_phase_calc_width,
PH_OUT_WID => c_phase_output_width,
NUM_ITER => c_stages,
ITER_PER_CLK => c_iter_per_clk,
USE_INREG => false,
USE_CE => true,
ROUNDING => true)
port map (
clk => s_clk,
ce => s_ce,
b_start_in => s_valid_i,
s_x_in => s_x_i_s,
s_y_in => s_y_i_s,
s_x_o => s_mag_o_s,
s_ph_o => s_phase_o_s,
b_rdy_o => s_valid_o,
b_busy_o => s_stall);
p_read_tsv_file_signed (
c_INPUT_FILE_NAME => c_INPUT_FILE,
c_SAMPLES_PER_LINE => 2,
c_OUTPUT_WIDTH => c_INPUT_WIDTH, --input for the testbench, output for
--the procedure
clk => s_clk,
rst => s_rst,
ce => s_ce,
req => s_req,
sample(0) => s_x_i_s,
sample(1) => s_y_i_s,
valid => s_valid_i,
end_of_file => end_of_file);
p_write_tsv_file_signed (
c_OUTPUT_FILE_NAME => c_OUTPUT_FILE,
c_SAMPLES_PER_LINE => 2,
c_OUTPUT_WIDTH => c_OUTPUT_WIDTH,
clk => s_clk,
rst => s_rst,
ce => s_ce,
sample(0) => s_mag_o_s,
sample(1) => s_phase_o_s,
valid => s_valid_o,
end_of_file => end_of_file);
s_req <= not(s_stall);
end architecture behav;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
| lgpl-3.0 | 53d235b39cf879967a3aa5854fccba46 | 0.479855 | 3.67432 | false | false | false | false |
SoCdesign/EHA | RTL/Immortal_Chip/Fault_injector.vhd | 2 | 1,183 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
use IEEE.math_real."ceil";
use IEEE.math_real."log2";
entity fault_injector is
generic(DATA_WIDTH : integer := 32);
port(
data_in: in std_logic_vector (DATA_WIDTH-1 downto 0);
address: in std_logic_vector(integer(ceil(log2(real(DATA_WIDTH))))-1 downto 0);
sta_0: in std_logic;
sta_1: in std_logic;
data_out: out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end fault_injector;
architecture behavior of fault_injector is
signal mask: std_logic_vector (DATA_WIDTH-1 downto 0);
begin
-- data_in | sta_0 | sta_1 | data_out
-- --------|--------|--------|----------
-- 0 | 0 | 0 | 0
-- 1 | 0 | 0 | 1
-- X | 0 | 1 | 1
-- X | 1 | 0 | 0
process (address) begin
mask <= (others => '0');
mask(to_integer(unsigned(address))) <= '1';
end process;
Gen_faulty:
for i in 0 to DATA_WIDTH-1 generate
data_out(i) <= (data_in(i) and not sta_1 and not sta_0) or (mask(i) and sta_1);
end generate;
end; | gpl-3.0 | 6789b195a6f5fa028e57c0bbb3419e52 | 0.546069 | 2.892421 | false | false | false | false |
bruskajp/EE-316 | Project2/Vivado_NexysBoard/project_2b/project_2b.srcs/sources_1/imports/Downloads/clk_enabler.vhd | 1 | 786 | library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use ieee.std_logic_unsigned.all;
entity clk_enabler is
GENERIC (
CONSTANT cnt_max : integer := 99999999);
port(
clock: in std_logic;
reset: in std_logic;
clk_en: out std_logic
);
end clk_enabler;
----------------------------------------------------
architecture behv of clk_enabler is
signal clk_cnt: integer range 0 to cnt_max;
begin
process(clock)
begin
if (reset = '1') then
clk_cnt <= 0;
clk_en <= '0';
elsif (rising_edge(clock)) then
-- if (clk_cnt = 99999) then
if (clk_cnt = cnt_max) then
clk_cnt <= 0;
clk_en <= '1';
else
clk_cnt <= clk_cnt + 1;
clk_en <= '0';
end if;
end if;
end process;
end behv;
| gpl-3.0 | c9f2001340e427a505fdd1074a90e942 | 0.573791 | 2.777385 | false | false | false | false |
TUM-LIS/faultify | hardware/testcases/QR/fpga_sim/xpsLibraryPath/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/vhdl/user_logic.vhd | 1 | 29,245 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Fri May 16 15:25:24 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
faultify_clk_fast : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
component faultify_top
generic (
numInj : integer;
numIn : integer;
numOut : integer);
port (
aclk : in std_logic;
arst_n : in std_logic;
clk : in std_logic;
clk_x32 : in std_logic;
awvalid : in std_logic;
awaddr : in std_logic_vector(31 downto 0);
wvalid : in std_logic;
wdata : in std_logic_vector(31 downto 0);
arvalid : in std_logic;
araddr : in std_logic_vector(31 downto 0);
rvalid : out std_logic;
rdata : out std_logic_vector(31 downto 0));
end component;
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal register_write_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal register_read_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal register_write_address : std_logic_vector(C_NUM_REG-1 downto 0);
signal register_read_address : std_logic_vector(C_NUM_REG-1 downto 0);
signal slv_reg_write_sel : std_logic_vector(31 downto 0);
signal slv_reg_read_sel : std_logic_vector(31 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal faultify_read_valid : std_logic;
signal faultify_read_address_valid : std_logic;
signal faultify_read_address : std_logic_vector(31 downto 0);
signal faultify_write_valid : std_logic;
signal counter, divide : integer := 0;
signal faultify_clk_slow_i : std_logic;
begin
slv_reg_write_sel <= Bus2IP_WrCE(31 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(31 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12) or Bus2IP_WrCE(13) or Bus2IP_WrCE(14) or Bus2IP_WrCE(15) or Bus2IP_WrCE(16) or Bus2IP_WrCE(17) or Bus2IP_WrCE(18) or Bus2IP_WrCE(19) or Bus2IP_WrCE(20) or Bus2IP_WrCE(21) or Bus2IP_WrCE(22) or Bus2IP_WrCE(23) or Bus2IP_WrCE(24) or Bus2IP_WrCE(25) or Bus2IP_WrCE(26) or Bus2IP_WrCE(27) or Bus2IP_WrCE(28) or Bus2IP_WrCE(29) or Bus2IP_WrCE(30) or Bus2IP_WrCE(31);
slv_read_ack <= faultify_read_valid;
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process(Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
register_write_data <= (others => '0');
register_write_address <= (others => '0');
faultify_write_valid <= '0';
else
faultify_write_valid <= slv_write_ack;
case slv_reg_write_sel is
when "10000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(0, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "01000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(1, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00100000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(2, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00010000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(3, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00001000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(4, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000100000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(5, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000010000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(6, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000001000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(7, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000100000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(8, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000010000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(9, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000001000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(10, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000100000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(11, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000010000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(12, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000001000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(13, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000100000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(14, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000010000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(15, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000001000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(16, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000100000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(17, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000010000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(18, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000001000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(19, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000100000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(20, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000010000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(21, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000001000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(22, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000100000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(23, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000010000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(24, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000001000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(25, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(26, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(27, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(28, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(29, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(30, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(31, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process(slv_reg_read_sel, faultify_read_valid) is
begin
faultify_read_address_valid <= '1';
case slv_reg_read_sel is
when "10000000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(0, 32));
when "01000000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(1, 32));
when "00100000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(2, 32));
when "00010000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(3, 32));
when "00001000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(4, 32));
when "00000100000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(5, 32));
when "00000010000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(6, 32));
when "00000001000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(7, 32));
when "00000000100000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(8, 32));
when "00000000010000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(9, 32));
when "00000000001000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(10, 32));
when "00000000000100000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(11, 32));
when "00000000000010000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(12, 32));
when "00000000000001000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(13, 32));
when "00000000000000100000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(14, 32));
when "00000000000000010000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(15, 32));
when "00000000000000001000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(16, 32));
when "00000000000000000100000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(17, 32));
when "00000000000000000010000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(18, 32));
when "00000000000000000001000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(19, 32));
when "00000000000000000000100000000000" => faultify_read_address <= std_logic_vector(to_unsigned(20, 32));
when "00000000000000000000010000000000" => faultify_read_address <= std_logic_vector(to_unsigned(21, 32));
when "00000000000000000000001000000000" => faultify_read_address <= std_logic_vector(to_unsigned(22, 32));
when "00000000000000000000000100000000" => faultify_read_address <= std_logic_vector(to_unsigned(23, 32));
when "00000000000000000000000010000000" => faultify_read_address <= std_logic_vector(to_unsigned(24, 32));
when "00000000000000000000000001000000" => faultify_read_address <= std_logic_vector(to_unsigned(25, 32));
when "00000000000000000000000000100000" => faultify_read_address <= std_logic_vector(to_unsigned(26, 32));
when "00000000000000000000000000010000" => faultify_read_address <= std_logic_vector(to_unsigned(27, 32));
when "00000000000000000000000000001000" => faultify_read_address <= std_logic_vector(to_unsigned(28, 32));
when "00000000000000000000000000000100" => faultify_read_address <= std_logic_vector(to_unsigned(29, 32));
when "00000000000000000000000000000010" => faultify_read_address <= std_logic_vector(to_unsigned(30, 32));
when "00000000000000000000000000000001" => faultify_read_address <= std_logic_vector(to_unsigned(31, 32));
when others => faultify_read_address <= (others => '0');
faultify_read_address_valid <= '0';
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= register_read_data when faultify_read_valid = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
-----------------------------------------------------------------------------
-- clock divider 32 -> 1
-----------------------------------------------------------------------------
divide <= 32;
process(Bus2IP_Clk, Bus2IP_Resetn)
begin
if Bus2IP_Resetn = '0' then
counter <= 0;
faultify_clk_slow_i <= '0';
elsif(rising_edge(Bus2IP_Clk)) then
if(counter < divide/2-1) then
counter <= counter + 1;
faultify_clk_slow_i <= '0';
elsif(counter < divide-1) then
counter <= counter + 1;
faultify_clk_slow_i <= '1';
else
faultify_clk_slow_i <= '0';
counter <= 0;
end if;
end if;
end process;
faultify_top_1 : faultify_top
generic map (
numInj => 414,
numIn => 111,
numOut => 202)
port map (
aclk => Bus2IP_Clk,
arst_n => Bus2IP_Resetn,
clk => faultify_clk_slow_i,
clk_x32 => Bus2IP_Clk,
awvalid => faultify_write_valid,
awaddr => register_write_address,
wvalid => faultify_write_valid,
wdata => register_write_data,
arvalid => faultify_read_address_valid,
araddr => faultify_read_address,
rvalid => faultify_read_valid,
rdata => register_read_data);
end IMP;
| gpl-2.0 | 645e8578bce0e8595f90cb159216b002 | 0.53934 | 4.023249 | false | false | false | false |
SoCdesign/EHA | RTL/Hand_Shaking/Checkers/Modules_with_checkers_integrated/All_checkers/FIFO_one_hot_with_checkers/FIFO_one_hot_with_checkers.vhd | 1 | 9,658 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
DRTS: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
CTS: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
-- Checker outputs
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_CTS_in,
err_write_en,
err_not_CTS_in,
err_not_write_en,
err_read_en_mismatch : out std_logic
);
end FIFO;
architecture behavior of FIFO is
signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(3 downto 0);
signal full, empty: std_logic;
signal read_en, write_en: std_logic;
signal CTS_in, CTS_out: std_logic;
signal FIFO_MEM_1, FIFO_MEM_1_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_2, FIFO_MEM_2_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_3, FIFO_MEM_3_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_4, FIFO_MEM_4_in : std_logic_vector(DATA_WIDTH-1 downto 0);
component FIFO_control_part_checkers is
port ( DRTS: in std_logic;
CTS_out: in std_logic;
CTS_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
read_pointer_in: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
write_pointer_in: in std_logic_vector(3 downto 0);
empty_out: in std_logic;
full_out: in std_logic;
read_en_out: in std_logic;
write_en_out: in std_logic;
-- Checker outputs
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_CTS_in,
err_write_en,
err_not_CTS_in,
err_not_write_en,
err_read_en_mismatch : out std_logic
);
end component;
begin
--------------------------------------------------------------------------------------------
-- block diagram of the FIFO!
-- previous
-- router
-- -- ------------------------------------------
-- | | |
-- TX|--------->| RX Data_out|----> goes to Xbar and LBDR
-- | | |
-- RTS|--------->| DRTS FIFO read_en|<---- Comes from Arbiters (N,E,W,S,L)
-- | | (N,E,W,S,L)|
-- DCTS|<---------| CTS |
-- -- ------------------------------------------
--------------------------------------------------------------------------------------------
-- Hand shake protocol!
--
-- |<-Valid->|
-- | Data |
-- _____ _________ ______
-- RX _____X_________X______
-- DRTS _____|'''''''''|_____
-- CTS __________|''''|_______
--
--------------------------------------------------------------------------------------------
-- circular buffer structure
-- <--- WriteP
-- ---------------------------------
-- | 3 | 2 | 1 | 0 |
-- ---------------------------------
-- <--- readP
--------------------------------------------------------------------------------------------
-- FIFO Control Part checkers instantiation
FIFOCONTROLPARTCHECKERS: FIFO_control_part_checkers port map (
DRTS => DRTS,
CTS_out => CTS_out, CTS_in => CTS_in,
read_en_N => read_en_N, read_en_E => read_en_E, read_en_W => read_en_W, read_en_S => read_en_S, read_en_L => read_en_L,
read_pointer => read_pointer, read_pointer_in => read_pointer_in,
write_pointer => write_pointer, write_pointer_in => write_pointer_in,
empty_out => empty, full_out => full,
read_en_out => read_en, write_en_out => write_en,
err_write_en_write_pointer => err_write_en_write_pointer,
err_not_write_en_write_pointer => err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => err_read_pointer_write_pointer_full,
err_read_pointer_increment => err_read_pointer_increment,
err_read_pointer_not_increment => err_read_pointer_not_increment,
err_CTS_in => err_CTS_in,
err_write_en => err_write_en,
err_not_CTS_in => err_not_CTS_in,
err_not_write_en => err_not_write_en,
err_read_en_mismatch => err_read_en_mismatch
);
process (clk, reset)begin
if reset = '0' then
read_pointer <= "0001";
write_pointer <= "0001";
CTS_out<='0';
FIFO_MEM_1 <= (others=>'0');
FIFO_MEM_2 <= (others=>'0');
FIFO_MEM_3 <= (others=>'0');
FIFO_MEM_4 <= (others=>'0');
elsif clk'event and clk = '1' then
write_pointer <= write_pointer_in;
if write_en = '1' then
--write into the memory
FIFO_MEM_1 <= FIFO_MEM_1_in;
FIFO_MEM_2 <= FIFO_MEM_2_in;
FIFO_MEM_3 <= FIFO_MEM_3_in;
FIFO_MEM_4 <= FIFO_MEM_4_in;
end if;
read_pointer <= read_pointer_in;
CTS_out<=CTS_in;
end if;
end process;
-- anything below here is pure combinational
-- combinatorial part
process(RX, write_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
end process;
process(read_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( read_pointer ) is
when "0001" => Data_out <= FIFO_MEM_1;
when "0010" => Data_out <= FIFO_MEM_2;
when "0100" => Data_out <= FIFO_MEM_3;
when "1000" => Data_out <= FIFO_MEM_4;
when others => Data_out <= FIFO_MEM_1;
end case ;
end process;
read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty;
empty_out <= empty;
CTS <= CTS_out;
process(write_en, write_pointer)begin
if write_en = '1'then
write_pointer_in <= write_pointer(2 downto 0)&write_pointer(3);
else
write_pointer_in <= write_pointer;
end if;
end process;
process(read_en, empty, read_pointer)begin
if (read_en = '1' and empty = '0') then
read_pointer_in <= read_pointer(2 downto 0)&read_pointer(3);
else
read_pointer_in <= read_pointer;
end if;
end process;
process(full, DRTS, CTS_out) begin
if CTS_out = '0' and DRTS = '1' and full ='0' then
CTS_in <= '1';
write_en <= '1';
else
CTS_in <= '0';
write_en <= '0';
end if;
end process;
process(write_pointer, read_pointer) begin
if read_pointer = write_pointer then
empty <= '1';
else
empty <= '0';
end if;
-- if write_pointer = read_pointer>>1 then
if write_pointer = read_pointer(0)&read_pointer(3 downto 1) then
full <= '1';
else
full <= '0';
end if;
end process;
end;
| gpl-3.0 | 4b192168aec6e2c8dc294ccc51c7fbd3 | 0.48157 | 3.582344 | false | false | false | false |
SoCdesign/EHA | RTL/Immortal_Chip/modules_with_fault_injectors/LBDR_with_checkers.vhd | 1 | 9,652 | --Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR is
generic (
cur_addr_rst: integer := 5;
Rxy_rst: integer := 60;
Cx_rst: integer := 15;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic;
-- fault injector signals
shift: in std_logic;
fault_clk: in std_logic;
data_in_serial: in std_logic;
data_out_serial: out std_logic;
-- Checker outputs
--err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in : out std_logic
);
end LBDR;
architecture behavior of LBDR is
signal Cx: std_logic_vector(3 downto 0);
signal Rxy: std_logic_vector(7 downto 0);
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal N1, E1, W1, S1 :std_logic := '0';
signal Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: std_logic;
signal Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: std_logic;
component LBDR_checkers is
generic (
cur_addr_rst: integer := 5;
NoC_size: integer := 4
);
port ( empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic;
N1_out, E1_out, W1_out, S1_out: in std_logic;
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
-- Checker outputs
--err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in : out std_logic
);
end component;
component fault_injector is
generic(DATA_WIDTH : integer := 32);
port(
data_in: in std_logic_vector (DATA_WIDTH-1 downto 0);
address: in std_logic_vector(integer(ceil(log2(real(DATA_WIDTH))))-1 downto 0);
sta_0: in std_logic;
sta_1: in std_logic;
data_out: out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end component;
component shift_register_serial_in is
generic (
REG_WIDTH: integer := 8
);
port (
clk, reset : in std_logic;
shift: in std_logic;
data_in_serial: in std_logic;
data_out_parallel: out std_logic_vector(REG_WIDTH-1 downto 0);
data_out_serial: out std_logic
);
end component;
signal FI_add_sta: std_logic_vector(?? downto 0);
begin
FI: fault_injector generic map(DATA_WIDTH => ??)
port map (data_in=> ?? , address=> FI_add_sta(?? downto 2), sta_0=> FI_add_sta(1), sta_1=> FI_add_sta(0), data_out=>??
);
SR: shift_register_serial_in generic map(REG_WIDTH => )
port map( clk=> fault_clk, reset=>reset, shift=> shift,data_in_serial=> data_in_serial,
data_out_parallel=> FI_add_sta, data_out_serial=> data_out_serial
);
Cx <= std_logic_vector(to_unsigned(Cx_rst, Cx'length));
Rxy <= std_logic_vector(to_unsigned(Rxy_rst, Rxy'length));
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
N1 <= '1' when dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) else '0';
E1 <= '1' when cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) else '0';
W1 <= '1' when dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) else '0';
S1 <= '1' when cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) else '0';
LBDRCHECKERS: LBDR_checkers generic map (cur_addr_rst => cur_addr_rst, NoC_size => NoC_size)
port map (
empty => empty,
flit_type => flit_type,
Req_N_FF => Req_N_FF,
Req_E_FF => Req_E_FF,
Req_W_FF => Req_W_FF,
Req_S_FF => Req_S_FF,
Req_L_FF => Req_L_FF,
Req_N_in => Req_N_in,
Req_E_in => Req_E_in,
Req_W_in => Req_W_in,
Req_S_in => Req_S_in,
Req_L_in => Req_L_in,
N1_out => N1,
E1_out => E1,
W1_out => W1,
S1_out => S1,
dst_addr => dst_addr,
err_header_empty_Requests_FF_Requests_in => err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in => err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => err_header_not_empty_Req_S_in
);
process(clk, reset)
begin
if reset = '0' then
Req_N_FF <= '0';
Req_E_FF <= '0';
Req_W_FF <= '0';
Req_S_FF <= '0';
Req_L_FF <= '0';
elsif clk'event and clk = '1' then
Req_N_FF <= Req_N_in;
Req_E_FF <= Req_E_in;
Req_W_FF <= Req_W_in;
Req_S_FF <= Req_S_in;
Req_L_FF <= Req_L_in;
end if;
end process;
-- The combionational part
Req_N <= Req_N_FF;
Req_E <= Req_E_FF;
Req_W <= Req_W_FF;
Req_S <= Req_S_FF;
Req_L <= Req_L_FF;
process(N1, E1, W1, S1, Rxy, Cx, flit_type, empty, Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF) begin
if flit_type = "001" and empty = '0' then
Req_N_in <= ((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0);
Req_E_in <= ((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1);
Req_W_in <= ((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2);
Req_S_in <= ((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3);
Req_L_in <= not N1 and not E1 and not W1 and not S1;
elsif flit_type = "100" then
Req_N_in <= '0';
Req_E_in <= '0';
Req_W_in <= '0';
Req_S_in <= '0';
Req_L_in <= '0';
else
Req_N_in <= Req_N_FF;
Req_E_in <= Req_E_FF;
Req_W_in <= Req_W_FF;
Req_S_in <= Req_S_FF;
Req_L_in <= Req_L_FF;
end if;
end process;
END; | gpl-3.0 | dbb3fe16a180aaee24c9f0ba9c2975b7 | 0.502279 | 3.042875 | false | false | false | false |
TanND/Electronic | VHDL/D6_C2.vhd | 1 | 520 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D6_C2 is
port(
nut : in STD_LOGIC_VECTOR(3 downto 0);
seg : out STD_LOGIC_VECTOR(3 downto 0)
);
end D6_C2;
architecture D6_C2 of D6_C2 is
begin
process(nut)
begin
case nut is
when "0000" =>seg<="0000";
when "0001" =>seg<="0001";
when "0010" =>seg<="0010";
when "0100" =>seg<="0100";
when "1000" =>seg<="1000";
when others =>null;
end case;
end process;
end D6_C2;
-- nut = random 0000=>11111 uniform 100ns; chi dung khi mo phong | apache-2.0 | 2df7438afdec889171c3eb380baa6a04 | 0.623077 | 2.6 | false | false | false | false |
Ana06/function-graphing-FPGA | expresion.vhd | 2 | 40,130 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ana María Martínez Gómez, Aitor Alonso Lorenzo, Víctor Adolfo Gallego Alcalá
--
-- Create Date: 16:17:24 02/22/2014
-- Design Name:
-- Module Name: expresion - Behavioral
-- Project Name: Representación gráfica de funciones
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use std.textio.all;
entity expresion is
port(
clk: in std_logic;
salida_teclado: in std_logic_vector(49 downto 0);
addr : in std_logic_vector(7 downto 0);
do : out std_logic_vector(0 to 10)
);
end expresion;
architecture Behavioral of expresion is
constant anchoExp: integer:=216;
type matriz is array(0 to 255) of std_logic_vector(10 downto 0);
signal expMatematica: matriz;
type coeficiente is array (0 to 5) of std_logic_vector(10 downto 0);
constant cero: coeficiente:= ("01111111111", "01111111111", "01100000011", "01100000011", "01111111111", "01111111111");
constant uno: coeficiente:= ((others=>'0'), (others=>'0'), "01111111111", "01111111111", (others=>'0'), (others=>'0'));
constant dos: coeficiente:= ("01111110011", "01111110011", "01100110011", "01100110011", "01100111111", "01100111111");
constant tres: coeficiente:= ("01111111111", "01111111111", "01100110011", "01100110011", "01100110011", "01100000011");
constant cuatro: coeficiente:=("01111111111", "01111111111", "00000110000", "00000110000", "01111110000", "01111110000");
constant cinco: coeficiente:= ("01100111111", "01100111111", "01100110011", "01100110011", "01111110011", "01111110011");
constant seis: coeficiente:= ("01100111111", "01100111111", "01100110011", "01100110011", "01111111111", "01111111111");
constant siete: coeficiente:= ("00000110000", "01111111111", "01111111111", "01100110000", "01100000000", "01100000000");
constant ocho: coeficiente:= ("01111111111", "01111111111", "01100110011", "01100110011", "01111111111", "01111111111");
constant nueve: coeficiente:= ("01111111111", "01111111111", "01100110000", "01100110000", "01111110000", "01111110000");
type caracter5Lineas is array (0 to 4) of std_logic_vector(10 downto 0);
constant X: caracter5Lineas:= ("01100000011", "00011001100", "00000110000", "00011001100", "01100000011");
constant sen: caracter5Lineas:= ("00111100011", "01111110011", "01100110011", "01100111111", "01100011110");
constant cos: caracter5Lineas:= ("01111111111", "01111111111", "11000000011", "11000000011", "11000000011");
constant log: caracter5Lineas:= ("00000000011", "00000000011", "00000000011", "01111111111", "01111111111");
constant pi: caracter5Lineas:= ("01111111111", "01111111111", "01100000000", "01111111111", "01111111111");
constant Xpequeña: caracter5Lineas:= ("00110000011", "00001101100", "00000010000", "00001101100", "00110000011");
type signo is array (0 to 2) of std_logic_vector(10 downto 0);
constant mas: signo:= ("00000110000", "00011111100", "00000110000");
constant menos: signo:= ("00000110000", "00000110000", "00000110000");
begin
--OBTENER TROZO DE LA EXPRESIÓN PEDIDO
expPedida: process (clk)
begin
if rising_edge(clk) then
do <= expMatematica(anchoExp-1-conv_integer(addr));
end if;
end process expPedida;
--EXPRESION MATEMÁTICA
--ExpMatematica tiene algunos valores fijos
--Xs (5 columnas cada una)
--6-10
expMatematica(6)<=X(0);
expMatematica(7)<=X(1);
expMatematica(8)<=X(2);
expMatematica(9)<=X(3);
expMatematica(10)<=X(4);
--29-33
expMatematica(29)<=X(0);
expMatematica(30)<=X(1);
expMatematica(31)<=X(2);
expMatematica(32)<=X(3);
expMatematica(33)<=X(4);
--50-54
expMatematica(50)<=X(0);
expMatematica(51)<=X(1);
expMatematica(52)<=X(2);
expMatematica(53)<=X(3);
expMatematica(54)<=X(4);
--78-82
expMatematica(78)<=X(0);
expMatematica(79)<=X(1);
expMatematica(80)<=X(2);
expMatematica(81)<=X(3);
expMatematica(82)<=X(4);
--99-103
expMatematica(99)<=X(0);
expMatematica(100)<=X(1);
expMatematica(101)<=X(2);
expMatematica(102)<=X(3);
expMatematica(103)<=X(4);
--120-124
expMatematica(120)<=X(0);
expMatematica(121)<=X(1);
expMatematica(122)<=X(2);
expMatematica(123)<=X(3);
expMatematica(124)<=X(4);
--S de sen (5 columnas)
expMatematica(182)<=sen(0);
expMatematica(181)<=sen(1);
expMatematica(180)<=sen(2);
expMatematica(179)<=sen(3);
expMatematica(178)<=sen(4);
--C de cos(5 columnas)
expMatematica(153)<=cos(0);
expMatematica(152)<=cos(1);
expMatematica(151)<=cos(2);
expMatematica(150)<=cos(3);
expMatematica(149)<=cos(4);
--L de log(5 columnas)
expMatematica(201)<=log(0);
expMatematica(202)<=log(1);
expMatematica(203)<=log(2);
expMatematica(204)<=log(3);
expMatematica(205)<=log(4);
-- Lo de dentro del Sen y Cos: pi
expMatematica(176)<= pi(0);
expMatematica(175)<= pi(1);
expMatematica(174)<= pi(2);
expMatematica(173)<= pi(3);
expMatematica(172)<= pi(4);
expMatematica(147)<= pi(0);
expMatematica(146)<= pi(1);
expMatematica(145)<= pi(2);
expMatematica(144)<= pi(3);
expMatematica(143)<= pi(4);
-- Lo de dentro del Sen, Cos y log: x
expMatematica(170)<= Xpequeña(0);
expMatematica(169)<= Xpequeña(1);
expMatematica(168)<= Xpequeña(2);
expMatematica(167)<= Xpequeña(3);
expMatematica(166)<= Xpequeña(4);
expMatematica(141)<= Xpequeña(0);
expMatematica(140)<= Xpequeña(1);
expMatematica(139)<= Xpequeña(2);
expMatematica(138)<= Xpequeña(3);
expMatematica(137)<= Xpequeña(4);
expMatematica(195)<= Xpequeña(0);
expMatematica(196)<= Xpequeña(1);
expMatematica(197)<= Xpequeña(2);
expMatematica(198)<= Xpequeña(3);
expMatematica(199)<= Xpequeña(4);
--EXPONENTE 3 (3 columnas)
expMatematica(2)<="10001000000";
expMatematica(1)<="10101000000";
expMatematica(0)<="11111000000";
expMatematica(118)<="10001000000";
expMatematica(117)<="10101000000";
expMatematica(116)<="11111000000";
--EXPONENTE 2 (3 columnas)
expMatematica(23)<="11101000000";
expMatematica(24)<="10101000000";
expMatematica(25)<="10111000000";
expMatematica(95)<="11101000000";
expMatematica(96)<="10101000000";
expMatematica(97)<="10111000000";
--EXPONENTE 1 (1 columna)
expMatematica(46)<="11111000000";
--EXPONENTE - (1 columna)
expMatematica(4)<="00100000000";
expMatematica(27)<="00100000000";
expMatematica(48)<="00100000000";
--Los coeficientes son variables y dependen de salida_teclado
expMatCal: process(salida_teclado)
begin
--signo de coeficiente de x^-3
if salida_teclado(4) = '0' then -- signo +
expMatematica(19)<= mas(0);
expMatematica(20)<= mas(1);
expMatematica(21)<= mas(2);
else -- signo -
expMatematica(19)<= menos(0);
expMatematica(20)<= menos(1);
expMatematica(21)<= menos(2);
end if;
--signo de coeficiente de x^-2
if salida_teclado(9) = '0' then -- signo +
expMatematica(42)<= mas(0);
expMatematica(43)<= mas(1);
expMatematica(44)<= mas(2);
else -- signo -
expMatematica(42)<= menos(0);
expMatematica(43)<= menos(1);
expMatematica(44)<= menos(2);
end if;
--signo de coeficiente de x^-1
if salida_teclado(14) = '0' then -- signo +
expMatematica(63)<= mas(0);
expMatematica(64)<= mas(1);
expMatematica(65)<= mas(2);
else -- signo -
expMatematica(63)<= menos(0);
expMatematica(64)<= menos(1);
expMatematica(65)<= menos(2);
end if;
--signo de coeficiente de la constante
if salida_teclado(19) = '0' then -- signo +
expMatematica(74)<= mas(0);
expMatematica(75)<= mas(1);
expMatematica(76)<= mas(2);
else -- signo -
expMatematica(74)<= menos(0);
expMatematica(75)<= menos(1);
expMatematica(76)<= menos(2);
end if;
--signo de coeficiente de x
if salida_teclado(24) = '0' then -- signo +
expMatematica(91)<= mas(0);
expMatematica(92)<= mas(1);
expMatematica(93)<= mas(2);
else -- signo -
expMatematica(91)<= menos(0);
expMatematica(92)<= menos(1);
expMatematica(93)<= menos(2);
end if;
--signo de coeficiente de x^2
if salida_teclado(29) = '0' then -- signo +
expMatematica(112)<= mas(0);
expMatematica(113)<= mas(1);
expMatematica(114)<= mas(2);
else -- signo -
expMatematica(112)<= menos(0);
expMatematica(113)<= menos(1);
expMatematica(114)<= menos(2);
end if;
--signo de coeficiente de x^3
if salida_teclado(34) = '0' then -- signo +
expMatematica(133)<= mas(0);
expMatematica(134)<= mas(1);
expMatematica(135)<= mas(2);
else -- signo -
expMatematica(133)<= menos(0);
expMatematica(134)<= menos(1);
expMatematica(135)<= menos(2);
end if;
--signo de coeficiente de cos
if salida_teclado(39) = '0' then -- signo +
expMatematica(162)<= mas(0);
expMatematica(163)<= mas(1);
expMatematica(164)<= mas(2);
else -- signo -
expMatematica(162)<= menos(0);
expMatematica(163)<= menos(1);
expMatematica(164)<= menos(2);
end if;
--signo de coeficiente de sen
if salida_teclado(44) = '0' then -- signo +
expMatematica(191)<= mas(0);
expMatematica(192)<= mas(1);
expMatematica(193)<= mas(2);
else -- signo -
expMatematica(191)<= menos(0);
expMatematica(192)<= menos(1);
expMatematica(193)<= menos(2);
end if;
--signo de coeficiente de log
if salida_teclado(49) = '0' then -- si es + no se muestra nada pues es el primer sumando
expMatematica(214)<=(others=>'0');
expMatematica(215)<=(others=>'0');
expMatematica(216)<=(others=>'0');
else -- signo -
expMatematica(214)<= menos(0);
expMatematica(215)<= menos(1);
expMatematica(216)<= menos(2);
end if;
--coeficiente de x^-3 (posiciones de 12 a 17)
if salida_teclado(4 downto 0) = "00001" or salida_teclado(4 downto 0) = "11111" then --1
expMatematica(12)<= uno(0);
expMatematica(13)<= uno(1);
expMatematica(14)<= uno(2);
expMatematica(15)<= uno(3);
expMatematica(16)<= uno(4);
expMatematica(17)<= uno(5);
elsif salida_teclado(4 downto 0) = "00010" or salida_teclado(4 downto 0) = "11110" then --2
expMatematica(12)<= dos(0);
expMatematica(13)<= dos(1);
expMatematica(14)<= dos(2);
expMatematica(15)<= dos(3);
expMatematica(16)<= dos(4);
expMatematica(17)<= dos(5);
elsif salida_teclado(4 downto 0) = "00011" or salida_teclado(4 downto 0) = "11101" then --3
expMatematica(12)<= tres(0);
expMatematica(13)<= tres(1);
expMatematica(14)<= tres(2);
expMatematica(15)<= tres(3);
expMatematica(16)<= tres(4);
expMatematica(17)<= tres(5);
elsif salida_teclado(4 downto 0) = "00100" or salida_teclado(4 downto 0) = "11100" then --4
expMatematica(12)<= cuatro(0);
expMatematica(13)<= cuatro(1);
expMatematica(14)<= cuatro(2);
expMatematica(15)<= cuatro(3);
expMatematica(16)<= cuatro(4);
expMatematica(17)<= cuatro(5);
elsif salida_teclado(4 downto 0) = "00101" or salida_teclado(4 downto 0) = "11011" then --5
expMatematica(12)<= cinco(0);
expMatematica(13)<= cinco(1);
expMatematica(14)<= cinco(2);
expMatematica(15)<= cinco(3);
expMatematica(16)<= cinco(4);
expMatematica(17)<= cinco(5);
elsif salida_teclado(4 downto 0) = "00110" or salida_teclado(4 downto 0) = "11010" then --6
expMatematica(12)<= seis(0);
expMatematica(13)<= seis(1);
expMatematica(14)<= seis(2);
expMatematica(15)<= seis(3);
expMatematica(16)<= seis(4);
expMatematica(17)<= seis(5);
elsif salida_teclado(4 downto 0) = "00111" or salida_teclado(4 downto 0) = "11001" then --7
expMatematica(12)<= siete(0);
expMatematica(13)<= siete(1);
expMatematica(14)<= siete(2);
expMatematica(15)<= siete(3);
expMatematica(16)<= siete(4);
expMatematica(17)<= siete(5);
elsif salida_teclado(4 downto 0) = "01000" or salida_teclado(4 downto 0) = "11000" then --8
expMatematica(12)<= ocho(0);
expMatematica(13)<= ocho(1);
expMatematica(14)<= ocho(2);
expMatematica(15)<= ocho(3);
expMatematica(16)<= ocho(4);
expMatematica(17)<= ocho(5);
elsif salida_teclado(4 downto 0) = "01001" or salida_teclado(4 downto 0) = "10111" then --9
expMatematica(12)<= nueve(0);
expMatematica(13)<= nueve(1);
expMatematica(14)<= nueve(2);
expMatematica(15)<= nueve(3);
expMatematica(16)<= nueve(4);
expMatematica(17)<= nueve(5);
else -- 0
expMatematica(12)<= cero(0);
expMatematica(13)<= cero(1);
expMatematica(14)<= cero(2);
expMatematica(15)<= cero(3);
expMatematica(16)<= cero(4);
expMatematica(17)<= cero(5);
end if;
--coeficiente de x^-2 (posiciones de 35 a 40)
if salida_teclado(9 downto 5) = "00001" or salida_teclado(9 downto 5) = "11111" then --1
expMatematica(35)<= uno(0);
expMatematica(36)<= uno(1);
expMatematica(37)<= uno(2);
expMatematica(38)<= uno(3);
expMatematica(39)<= uno(4);
expMatematica(40)<= uno(5);
elsif salida_teclado(9 downto 5) = "00010" or salida_teclado(9 downto 5) = "11110" then --2
expMatematica(35)<= dos(0);
expMatematica(36)<= dos(1);
expMatematica(37)<= dos(2);
expMatematica(38)<= dos(3);
expMatematica(39)<= dos(4);
expMatematica(40)<= dos(5);
elsif salida_teclado(9 downto 5) = "00011" or salida_teclado(9 downto 5) = "11101" then --3
expMatematica(35)<= tres(0);
expMatematica(36)<= tres(1);
expMatematica(37)<= tres(2);
expMatematica(38)<= tres(3);
expMatematica(39)<= tres(4);
expMatematica(40)<= tres(5);
elsif salida_teclado(9 downto 5) = "00100" or salida_teclado(9 downto 5) = "11100" then --4
expMatematica(35)<= cuatro(0);
expMatematica(36)<= cuatro(1);
expMatematica(37)<= cuatro(2);
expMatematica(38)<= cuatro(3);
expMatematica(39)<= cuatro(4);
expMatematica(40)<= cuatro(5);
elsif salida_teclado(9 downto 5) = "00101" or salida_teclado(9 downto 5) = "11011" then --5
expMatematica(35)<= cinco(0);
expMatematica(36)<= cinco(1);
expMatematica(37)<= cinco(2);
expMatematica(38)<= cinco(3);
expMatematica(39)<= cinco(4);
expMatematica(40)<= cinco(5);
elsif salida_teclado(9 downto 5) = "00110" or salida_teclado(9 downto 5) = "11010" then --6
expMatematica(35)<= seis(0);
expMatematica(36)<= seis(1);
expMatematica(37)<= seis(2);
expMatematica(38)<= seis(3);
expMatematica(39)<= seis(4);
expMatematica(40)<= seis(5);
elsif salida_teclado(9 downto 5) = "00111" or salida_teclado(9 downto 5) = "11001" then --7
expMatematica(35)<= siete(0);
expMatematica(36)<= siete(1);
expMatematica(37)<= siete(2);
expMatematica(38)<= siete(3);
expMatematica(39)<= siete(4);
expMatematica(40)<= siete(5);
elsif salida_teclado(9 downto 5) = "01000" or salida_teclado(9 downto 5) = "11000" then --8
expMatematica(35)<= ocho(0);
expMatematica(36)<= ocho(1);
expMatematica(37)<= ocho(2);
expMatematica(38)<= ocho(3);
expMatematica(39)<= ocho(4);
expMatematica(40)<= ocho(5);
elsif salida_teclado(9 downto 5) = "01001" or salida_teclado(9 downto 5) = "10111" then --9
expMatematica(35)<= nueve(0);
expMatematica(36)<= nueve(1);
expMatematica(37)<= nueve(2);
expMatematica(38)<= nueve(3);
expMatematica(39)<= nueve(4);
expMatematica(40)<= nueve(5);
else -- 0
expMatematica(35)<= cero(0);
expMatematica(36)<= cero(1);
expMatematica(37)<= cero(2);
expMatematica(38)<= cero(3);
expMatematica(39)<= cero(4);
expMatematica(40)<= cero(5);
end if;
--coeficiente de x^-1 (posiciones de 56 a 61)
if salida_teclado(14 downto 10) = "00001" or salida_teclado(14 downto 10) = "11111" then --1
expMatematica(56)<= uno(0);
expMatematica(57)<= uno(1);
expMatematica(58)<= uno(2);
expMatematica(59)<= uno(3);
expMatematica(60)<= uno(4);
expMatematica(61)<= uno(5);
elsif salida_teclado(14 downto 10) = "00010" or salida_teclado(14 downto 10) = "11110" then --2
expMatematica(56)<= dos(0);
expMatematica(57)<= dos(1);
expMatematica(58)<= dos(2);
expMatematica(59)<= dos(3);
expMatematica(60)<= dos(4);
expMatematica(61)<= dos(5);
elsif salida_teclado(14 downto 10) = "00011" or salida_teclado(14 downto 10) = "11101" then --3
expMatematica(56)<= tres(0);
expMatematica(57)<= tres(1);
expMatematica(58)<= tres(2);
expMatematica(59)<= tres(3);
expMatematica(60)<= tres(4);
expMatematica(61)<= tres(5);
elsif salida_teclado(14 downto 10) = "00100" or salida_teclado(14 downto 10) = "11100" then --4
expMatematica(56)<= cuatro(0);
expMatematica(57)<= cuatro(1);
expMatematica(58)<= cuatro(2);
expMatematica(59)<= cuatro(3);
expMatematica(60)<= cuatro(4);
expMatematica(61)<= cuatro(5);
elsif salida_teclado(14 downto 10) = "00101" or salida_teclado(14 downto 10) = "11011" then --5
expMatematica(56)<= cinco(0);
expMatematica(57)<= cinco(1);
expMatematica(58)<= cinco(2);
expMatematica(59)<= cinco(3);
expMatematica(60)<= cinco(4);
expMatematica(61)<= cinco(5);
elsif salida_teclado(14 downto 10) = "00110" or salida_teclado(14 downto 10) = "11010" then --6
expMatematica(56)<= seis(0);
expMatematica(57)<= seis(1);
expMatematica(58)<= seis(2);
expMatematica(59)<= seis(3);
expMatematica(60)<= seis(4);
expMatematica(61)<= seis(5);
elsif salida_teclado(14 downto 10) = "00111" or salida_teclado(14 downto 10) = "11001" then --7
expMatematica(56)<= siete(0);
expMatematica(57)<= siete(1);
expMatematica(58)<= siete(2);
expMatematica(59)<= siete(3);
expMatematica(60)<= siete(4);
expMatematica(61)<= siete(5);
elsif salida_teclado(14 downto 10) = "01000" or salida_teclado(14 downto 10) = "11000" then --8
expMatematica(56)<= ocho(0);
expMatematica(57)<= ocho(1);
expMatematica(58)<= ocho(2);
expMatematica(59)<= ocho(3);
expMatematica(60)<= ocho(4);
expMatematica(61)<= ocho(5);
elsif salida_teclado(14 downto 10) = "01001" or salida_teclado(14 downto 10) = "10111" then --9
expMatematica(56)<= nueve(0);
expMatematica(57)<= nueve(1);
expMatematica(58)<= nueve(2);
expMatematica(59)<= nueve(3);
expMatematica(60)<= nueve(4);
expMatematica(61)<= nueve(5);
else -- 0
expMatematica(56)<= cero(0);
expMatematica(57)<= cero(1);
expMatematica(58)<= cero(2);
expMatematica(59)<= cero(3);
expMatematica(60)<= cero(4);
expMatematica(61)<= cero(5);
end if;
--coeficiente de constante(posiciones de 67 a 72)
if salida_teclado(19 downto 15) = "00001" or salida_teclado(19 downto 15) = "11111" then --1
expMatematica(67)<= uno(0);
expMatematica(68)<= uno(1);
expMatematica(69)<= uno(2);
expMatematica(70)<= uno(3);
expMatematica(71)<= uno(4);
expMatematica(72)<= uno(5);
elsif salida_teclado(19 downto 15) = "00010" or salida_teclado(19 downto 15) = "11110" then --2
expMatematica(67)<= dos(0);
expMatematica(68)<= dos(1);
expMatematica(69)<= dos(2);
expMatematica(70)<= dos(3);
expMatematica(71)<= dos(4);
expMatematica(72)<= dos(5);
elsif salida_teclado(19 downto 15) = "00011" or salida_teclado(19 downto 15) = "11101" then --3
expMatematica(67)<= tres(0);
expMatematica(68)<= tres(1);
expMatematica(69)<= tres(2);
expMatematica(70)<= tres(3);
expMatematica(71)<= tres(4);
expMatematica(72)<= tres(5);
elsif salida_teclado(19 downto 15) = "00100" or salida_teclado(19 downto 15) = "11100" then --4
expMatematica(67)<= cuatro(0);
expMatematica(68)<= cuatro(1);
expMatematica(69)<= cuatro(2);
expMatematica(70)<= cuatro(3);
expMatematica(71)<= cuatro(4);
expMatematica(72)<= cuatro(5);
elsif salida_teclado(19 downto 15) = "00101" or salida_teclado(19 downto 15) = "11011" then --5
expMatematica(67)<= cinco(0);
expMatematica(68)<= cinco(1);
expMatematica(69)<= cinco(2);
expMatematica(70)<= cinco(3);
expMatematica(71)<= cinco(4);
expMatematica(72)<= cinco(5);
elsif salida_teclado(19 downto 15) = "00110" or salida_teclado(19 downto 15) = "11010" then --6
expMatematica(67)<= seis(0);
expMatematica(68)<= seis(1);
expMatematica(69)<= seis(2);
expMatematica(70)<= seis(3);
expMatematica(71)<= seis(4);
expMatematica(72)<= seis(5);
elsif salida_teclado(19 downto 15) = "00111" or salida_teclado(19 downto 15) = "11001" then --7
expMatematica(67)<= siete(0);
expMatematica(68)<= siete(1);
expMatematica(69)<= siete(2);
expMatematica(70)<= siete(3);
expMatematica(71)<= siete(4);
expMatematica(72)<= siete(5);
elsif salida_teclado(19 downto 15) = "01000" or salida_teclado(19 downto 15) = "11000" then --8
expMatematica(67)<= ocho(0);
expMatematica(68)<= ocho(1);
expMatematica(69)<= ocho(2);
expMatematica(70)<= ocho(3);
expMatematica(71)<= ocho(4);
expMatematica(72)<= ocho(5);
elsif salida_teclado(19 downto 15) = "01001" or salida_teclado(19 downto 15) = "10111" then --9
expMatematica(67)<= nueve(0);
expMatematica(68)<= nueve(1);
expMatematica(69)<= nueve(2);
expMatematica(70)<= nueve(3);
expMatematica(71)<= nueve(4);
expMatematica(72)<= nueve(5);
else -- 0
expMatematica(67)<= cero(0);
expMatematica(68)<= cero(1);
expMatematica(69)<= cero(2);
expMatematica(70)<= cero(3);
expMatematica(71)<= cero(4);
expMatematica(72)<= cero(5);
end if;
--coeficiente de x(posiciones de 84 a 89)
if salida_teclado(24 downto 20) = "00001" or salida_teclado(24 downto 20) = "11111" then --1
expMatematica(84)<= uno(0);
expMatematica(85)<= uno(1);
expMatematica(86)<= uno(2);
expMatematica(87)<= uno(3);
expMatematica(88)<= uno(4);
expMatematica(89)<= uno(5);
elsif salida_teclado(24 downto 20) = "00010" or salida_teclado(24 downto 20) = "11110" then --2
expMatematica(84)<= dos(0);
expMatematica(85)<= dos(1);
expMatematica(86)<= dos(2);
expMatematica(87)<= dos(3);
expMatematica(88)<= dos(4);
expMatematica(89)<= dos(5);
elsif salida_teclado(24 downto 20) = "00011" or salida_teclado(24 downto 20) = "11101" then --3
expMatematica(84)<= tres(0);
expMatematica(85)<= tres(1);
expMatematica(86)<= tres(2);
expMatematica(87)<= tres(3);
expMatematica(88)<= tres(4);
expMatematica(89)<= tres(5);
elsif salida_teclado(24 downto 20) = "00100" or salida_teclado(24 downto 20) = "11100" then --4
expMatematica(84)<= cuatro(0);
expMatematica(85)<= cuatro(1);
expMatematica(86)<= cuatro(2);
expMatematica(87)<= cuatro(3);
expMatematica(88)<= cuatro(4);
expMatematica(89)<= cuatro(5);
elsif salida_teclado(24 downto 20) = "00101" or salida_teclado(24 downto 20) = "11011" then --5
expMatematica(84)<= cinco(0);
expMatematica(85)<= cinco(1);
expMatematica(86)<= cinco(2);
expMatematica(87)<= cinco(3);
expMatematica(88)<= cinco(4);
expMatematica(89)<= cinco(5);
elsif salida_teclado(24 downto 20) = "00110" or salida_teclado(24 downto 20) = "11010" then --6
expMatematica(84)<= seis(0);
expMatematica(85)<= seis(1);
expMatematica(86)<= seis(2);
expMatematica(87)<= seis(3);
expMatematica(88)<= seis(4);
expMatematica(89)<= seis(5);
elsif salida_teclado(24 downto 20) = "00111" or salida_teclado(24 downto 20) = "11001" then --7
expMatematica(84)<= siete(0);
expMatematica(85)<= siete(1);
expMatematica(86)<= siete(2);
expMatematica(87)<= siete(3);
expMatematica(88)<= siete(4);
expMatematica(89)<= siete(5);
elsif salida_teclado(24 downto 20) = "01000" or salida_teclado(24 downto 20) = "11000" then --8
expMatematica(84)<= ocho(0);
expMatematica(85)<= ocho(1);
expMatematica(86)<= ocho(2);
expMatematica(87)<= ocho(3);
expMatematica(88)<= ocho(4);
expMatematica(89)<= ocho(5);
elsif salida_teclado(24 downto 20) = "01001" or salida_teclado(24 downto 20) = "10111" then --9
expMatematica(84)<= nueve(0);
expMatematica(85)<= nueve(1);
expMatematica(86)<= nueve(2);
expMatematica(87)<= nueve(3);
expMatematica(88)<= nueve(4);
expMatematica(89)<= nueve(5);
else -- 0
expMatematica(84)<= cero(0);
expMatematica(85)<= cero(1);
expMatematica(86)<= cero(2);
expMatematica(87)<= cero(3);
expMatematica(88)<= cero(4);
expMatematica(89)<= cero(5);
end if;
--coeficiente de x^2(posiciones de 105 a 110)
if salida_teclado(29 downto 25) = "00001" or salida_teclado(29 downto 25) = "11111" then --1
expMatematica(105)<= uno(0);
expMatematica(106)<= uno(1);
expMatematica(107)<= uno(2);
expMatematica(108)<= uno(3);
expMatematica(109)<= uno(4);
expMatematica(110)<= uno(5);
elsif salida_teclado(29 downto 25) = "00010" or salida_teclado(29 downto 25) = "11110" then --2
expMatematica(105)<= dos(0);
expMatematica(106)<= dos(1);
expMatematica(107)<= dos(2);
expMatematica(108)<= dos(3);
expMatematica(109)<= dos(4);
expMatematica(110)<= dos(5);
elsif salida_teclado(29 downto 25) = "00011" or salida_teclado(29 downto 25) = "11101" then --3
expMatematica(105)<= tres(0);
expMatematica(106)<= tres(1);
expMatematica(107)<= tres(2);
expMatematica(108)<= tres(3);
expMatematica(109)<= tres(4);
expMatematica(110)<= tres(5);
elsif salida_teclado(29 downto 25) = "00100" or salida_teclado(29 downto 25) = "11100" then --4
expMatematica(105)<= cuatro(0);
expMatematica(106)<= cuatro(1);
expMatematica(107)<= cuatro(2);
expMatematica(108)<= cuatro(3);
expMatematica(109)<= cuatro(4);
expMatematica(110)<= cuatro(5);
elsif salida_teclado(29 downto 25) = "00101" or salida_teclado(29 downto 25) = "11011" then --5
expMatematica(105)<= cinco(0);
expMatematica(106)<= cinco(1);
expMatematica(107)<= cinco(2);
expMatematica(108)<= cinco(3);
expMatematica(109)<= cinco(4);
expMatematica(110)<= cinco(5);
elsif salida_teclado(29 downto 25) = "00110" or salida_teclado(29 downto 25) = "11010" then --6
expMatematica(105)<= seis(0);
expMatematica(106)<= seis(1);
expMatematica(107)<= seis(2);
expMatematica(108)<= seis(3);
expMatematica(109)<= seis(4);
expMatematica(110)<= seis(5);
elsif salida_teclado(29 downto 25) = "00111" or salida_teclado(29 downto 25) = "11001" then --7
expMatematica(105)<= siete(0);
expMatematica(106)<= siete(1);
expMatematica(107)<= siete(2);
expMatematica(108)<= siete(3);
expMatematica(109)<= siete(4);
expMatematica(110)<= siete(5);
elsif salida_teclado(29 downto 25) = "01000" or salida_teclado(29 downto 25) = "11000" then --8
expMatematica(105)<= ocho(0);
expMatematica(106)<= ocho(1);
expMatematica(107)<= ocho(2);
expMatematica(108)<= ocho(3);
expMatematica(109)<= ocho(4);
expMatematica(110)<= ocho(5);
elsif salida_teclado(29 downto 25) = "01001" or salida_teclado(29 downto 25) = "10111" then --9
expMatematica(105)<= nueve(0);
expMatematica(106)<= nueve(1);
expMatematica(107)<= nueve(2);
expMatematica(108)<= nueve(3);
expMatematica(109)<= nueve(4);
expMatematica(110)<= nueve(5);
else -- 0
expMatematica(105)<= cero(0);
expMatematica(106)<= cero(1);
expMatematica(107)<= cero(2);
expMatematica(108)<= cero(3);
expMatematica(109)<= cero(4);
expMatematica(110)<= cero(5);
end if;
--coeficiente de x^3 (posiciones de 126 a 131)
if salida_teclado(34 downto 30) = "00001" or salida_teclado(34 downto 30) = "11111" then --1
expMatematica(126)<= uno(0);
expMatematica(127)<= uno(1);
expMatematica(128)<= uno(2);
expMatematica(129)<= uno(3);
expMatematica(130)<= uno(4);
expMatematica(131)<= uno(5);
elsif salida_teclado(34 downto 30) = "00010" or salida_teclado(34 downto 30) = "11110" then --2
expMatematica(126)<= dos(0);
expMatematica(127)<= dos(1);
expMatematica(128)<= dos(2);
expMatematica(129)<= dos(3);
expMatematica(130)<= dos(4);
expMatematica(131)<= dos(5);
elsif salida_teclado(34 downto 30) = "00011" or salida_teclado(34 downto 30) = "11101" then --3
expMatematica(126)<= tres(0);
expMatematica(127)<= tres(1);
expMatematica(128)<= tres(2);
expMatematica(129)<= tres(3);
expMatematica(130)<= tres(4);
expMatematica(131)<= tres(5);
elsif salida_teclado(34 downto 30) = "00100" or salida_teclado(34 downto 30) = "11100" then --4
expMatematica(126)<= cuatro(0);
expMatematica(127)<= cuatro(1);
expMatematica(128)<= cuatro(2);
expMatematica(129)<= cuatro(3);
expMatematica(130)<= cuatro(4);
expMatematica(131)<= cuatro(5);
elsif salida_teclado(34 downto 30) = "00101" or salida_teclado(34 downto 30) = "11011" then --5
expMatematica(126)<= cinco(0);
expMatematica(127)<= cinco(1);
expMatematica(128)<= cinco(2);
expMatematica(129)<= cinco(3);
expMatematica(130)<= cinco(4);
expMatematica(131)<= cinco(5);
elsif salida_teclado(34 downto 30) = "00110" or salida_teclado(34 downto 30) = "11010" then --6
expMatematica(126)<= seis(0);
expMatematica(127)<= seis(1);
expMatematica(128)<= seis(2);
expMatematica(129)<= seis(3);
expMatematica(130)<= seis(4);
expMatematica(131)<= seis(5);
elsif salida_teclado(34 downto 30) = "00111" or salida_teclado(34 downto 30) = "11001" then --7
expMatematica(126)<= siete(0);
expMatematica(127)<= siete(1);
expMatematica(128)<= siete(2);
expMatematica(129)<= siete(3);
expMatematica(130)<= siete(4);
expMatematica(131)<= siete(5);
elsif salida_teclado(34 downto 30) = "01000" or salida_teclado(34 downto 30) = "11000" then --8
expMatematica(126)<= ocho(0);
expMatematica(127)<= ocho(1);
expMatematica(128)<= ocho(2);
expMatematica(129)<= ocho(3);
expMatematica(130)<= ocho(4);
expMatematica(131)<= ocho(5);
elsif salida_teclado(34 downto 30) = "01001" or salida_teclado(34 downto 30) = "10111" then --9
expMatematica(126)<= nueve(0);
expMatematica(127)<= nueve(1);
expMatematica(128)<= nueve(2);
expMatematica(129)<= nueve(3);
expMatematica(130)<= nueve(4);
expMatematica(131)<= nueve(5);
else -- 0
expMatematica(126)<= cero(0);
expMatematica(127)<= cero(1);
expMatematica(128)<= cero(2);
expMatematica(129)<= cero(3);
expMatematica(130)<= cero(4);
expMatematica(131)<= cero(5);
end if;
--coeficiente de cos(posiciones de 155 a 160)
if salida_teclado(39 downto 35) = "00001" or salida_teclado(39 downto 35) = "11111" then --1
expMatematica(155)<= uno(0);
expMatematica(156)<= uno(1);
expMatematica(157)<= uno(2);
expMatematica(158)<= uno(3);
expMatematica(159)<= uno(4);
expMatematica(160)<= uno(5);
elsif salida_teclado(39 downto 35) = "00010" or salida_teclado(39 downto 35) = "11110" then --2
expMatematica(155)<= dos(0);
expMatematica(156)<= dos(1);
expMatematica(157)<= dos(2);
expMatematica(158)<= dos(3);
expMatematica(159)<= dos(4);
expMatematica(160)<= dos(5);
elsif salida_teclado(39 downto 35) = "00011" or salida_teclado(39 downto 35) = "11101" then --3
expMatematica(155)<= tres(0);
expMatematica(156)<= tres(1);
expMatematica(157)<= tres(2);
expMatematica(158)<= tres(3);
expMatematica(159)<= tres(4);
expMatematica(160)<= tres(5);
elsif salida_teclado(39 downto 35) = "00100" or salida_teclado(39 downto 35) = "11100" then --4
expMatematica(155)<= cuatro(0);
expMatematica(156)<= cuatro(1);
expMatematica(157)<= cuatro(2);
expMatematica(158)<= cuatro(3);
expMatematica(159)<= cuatro(4);
expMatematica(160)<= cuatro(5);
elsif salida_teclado(39 downto 35) = "00101" or salida_teclado(39 downto 35) = "11011" then --5
expMatematica(155)<= cinco(0);
expMatematica(156)<= cinco(1);
expMatematica(157)<= cinco(2);
expMatematica(158)<= cinco(3);
expMatematica(159)<= cinco(4);
expMatematica(160)<= cinco(5);
elsif salida_teclado(39 downto 35) = "00110" or salida_teclado(39 downto 35) = "11010" then --6
expMatematica(155)<= seis(0);
expMatematica(156)<= seis(1);
expMatematica(157)<= seis(2);
expMatematica(158)<= seis(3);
expMatematica(159)<= seis(4);
expMatematica(160)<= seis(5);
elsif salida_teclado(39 downto 35) = "00111" or salida_teclado(39 downto 35) = "11001" then --7
expMatematica(155)<= siete(0);
expMatematica(156)<= siete(1);
expMatematica(157)<= siete(2);
expMatematica(158)<= siete(3);
expMatematica(159)<= siete(4);
expMatematica(160)<= siete(5);
elsif salida_teclado(39 downto 35) = "01000" or salida_teclado(39 downto 35) = "11000" then --8
expMatematica(155)<= ocho(0);
expMatematica(156)<= ocho(1);
expMatematica(157)<= ocho(2);
expMatematica(158)<= ocho(3);
expMatematica(159)<= ocho(4);
expMatematica(160)<= ocho(5);
elsif salida_teclado(39 downto 35) = "01001" or salida_teclado(39 downto 35) = "10111" then --9
expMatematica(155)<= nueve(0);
expMatematica(156)<= nueve(1);
expMatematica(157)<= nueve(2);
expMatematica(158)<= nueve(3);
expMatematica(159)<= nueve(4);
expMatematica(160)<= nueve(5);
else -- 0
expMatematica(155)<= cero(0);
expMatematica(156)<= cero(1);
expMatematica(157)<= cero(2);
expMatematica(158)<= cero(3);
expMatematica(159)<= cero(4);
expMatematica(160)<= cero(5);
end if;
--coeficiente de sen(posiciones de 184 a 189)
if salida_teclado(44 downto 40) = "00001" or salida_teclado(44 downto 40) = "11111" then --1
expMatematica(184)<= uno(0);
expMatematica(185)<= uno(1);
expMatematica(186)<= uno(2);
expMatematica(187)<= uno(3);
expMatematica(188)<= uno(4);
expMatematica(189)<= uno(5);
elsif salida_teclado(44 downto 40) = "00010" or salida_teclado(44 downto 40) = "11110" then --2
expMatematica(184)<= dos(0);
expMatematica(185)<= dos(1);
expMatematica(186)<= dos(2);
expMatematica(187)<= dos(3);
expMatematica(188)<= dos(4);
expMatematica(189)<= dos(5);
elsif salida_teclado(44 downto 40) = "00011" or salida_teclado(44 downto 40) = "11101" then --3
expMatematica(184)<= tres(0);
expMatematica(185)<= tres(1);
expMatematica(186)<= tres(2);
expMatematica(187)<= tres(3);
expMatematica(188)<= tres(4);
expMatematica(189)<= tres(5);
elsif salida_teclado(44 downto 40) = "00100" or salida_teclado(44 downto 40) = "11100" then --4
expMatematica(184)<= cuatro(0);
expMatematica(185)<= cuatro(1);
expMatematica(186)<= cuatro(2);
expMatematica(187)<= cuatro(3);
expMatematica(188)<= cuatro(4);
expMatematica(189)<= cuatro(5);
elsif salida_teclado(44 downto 40) = "00101" or salida_teclado(44 downto 40) = "11011" then --5
expMatematica(184)<= cinco(0);
expMatematica(185)<= cinco(1);
expMatematica(186)<= cinco(2);
expMatematica(187)<= cinco(3);
expMatematica(188)<= cinco(4);
expMatematica(189)<= cinco(5);
elsif salida_teclado(44 downto 40) = "00110" or salida_teclado(44 downto 40) = "11010" then --6
expMatematica(184)<= seis(0);
expMatematica(185)<= seis(1);
expMatematica(186)<= seis(2);
expMatematica(187)<= seis(3);
expMatematica(188)<= seis(4);
expMatematica(189)<= seis(5);
elsif salida_teclado(44 downto 40) = "00111" or salida_teclado(44 downto 40) = "11001" then --7
expMatematica(184)<= siete(0);
expMatematica(185)<= siete(1);
expMatematica(186)<= siete(2);
expMatematica(187)<= siete(3);
expMatematica(188)<= siete(4);
expMatematica(189)<= siete(5);
elsif salida_teclado(44 downto 40) = "01000" or salida_teclado(44 downto 40) = "11000" then --8
expMatematica(184)<= ocho(0);
expMatematica(185)<= ocho(1);
expMatematica(186)<= ocho(2);
expMatematica(187)<= ocho(3);
expMatematica(188)<= ocho(4);
expMatematica(189)<= ocho(5);
elsif salida_teclado(44 downto 40) = "01001" or salida_teclado(44 downto 40) = "10111" then --9
expMatematica(184)<= nueve(0);
expMatematica(185)<= nueve(1);
expMatematica(186)<= nueve(2);
expMatematica(187)<= nueve(3);
expMatematica(188)<= nueve(4);
expMatematica(189)<= nueve(5);
else -- 0
expMatematica(184)<= cero(0);
expMatematica(185)<= cero(1);
expMatematica(186)<= cero(2);
expMatematica(187)<= cero(3);
expMatematica(188)<= cero(4);
expMatematica(189)<= cero(5);
end if;
--coeficiente de log(posiciones de 207 a 212)
if salida_teclado(49 downto 45) = "00001" or salida_teclado(49 downto 45) = "11111" then --1
expMatematica(207)<= uno(0);
expMatematica(208)<= uno(1);
expMatematica(209)<= uno(2);
expMatematica(210)<= uno(3);
expMatematica(211)<= uno(4);
expMatematica(212)<= uno(5);
elsif salida_teclado(49 downto 45) = "00010" or salida_teclado(49 downto 45) = "11110" then --2
expMatematica(207)<= dos(0);
expMatematica(208)<= dos(1);
expMatematica(209)<= dos(2);
expMatematica(210)<= dos(3);
expMatematica(211)<= dos(4);
expMatematica(212)<= dos(5);
elsif salida_teclado(49 downto 45) = "00011" or salida_teclado(49 downto 45) = "11101" then --3
expMatematica(207)<= tres(0);
expMatematica(208)<= tres(1);
expMatematica(209)<= tres(2);
expMatematica(210)<= tres(3);
expMatematica(211)<= tres(4);
expMatematica(212)<= tres(5);
elsif salida_teclado(49 downto 45) = "00100" or salida_teclado(49 downto 45) = "11100" then --4
expMatematica(207)<= cuatro(0);
expMatematica(208)<= cuatro(1);
expMatematica(209)<= cuatro(2);
expMatematica(210)<= cuatro(3);
expMatematica(211)<= cuatro(4);
expMatematica(212)<= cuatro(5);
elsif salida_teclado(49 downto 45) = "00101" or salida_teclado(49 downto 45) = "11011" then --5
expMatematica(207)<= cinco(0);
expMatematica(208)<= cinco(1);
expMatematica(209)<= cinco(2);
expMatematica(210)<= cinco(3);
expMatematica(211)<= cinco(4);
expMatematica(212)<= cinco(5);
elsif salida_teclado(49 downto 45) = "00110" or salida_teclado(49 downto 45) = "11010" then --6
expMatematica(207)<= seis(0);
expMatematica(208)<= seis(1);
expMatematica(209)<= seis(2);
expMatematica(210)<= seis(3);
expMatematica(211)<= seis(4);
expMatematica(212)<= seis(5);
elsif salida_teclado(49 downto 45) = "00111" or salida_teclado(49 downto 45) = "11001" then --7
expMatematica(207)<= siete(0);
expMatematica(208)<= siete(1);
expMatematica(209)<= siete(2);
expMatematica(210)<= siete(3);
expMatematica(211)<= siete(4);
expMatematica(212)<= siete(5);
elsif salida_teclado(49 downto 45) = "01000" or salida_teclado(49 downto 45) = "11000" then --8
expMatematica(207)<= ocho(0);
expMatematica(208)<= ocho(1);
expMatematica(209)<= ocho(2);
expMatematica(210)<= ocho(3);
expMatematica(211)<= ocho(4);
expMatematica(212)<= ocho(5);
elsif salida_teclado(49 downto 45) = "01001" or salida_teclado(49 downto 45) = "10111" then --9
expMatematica(207)<= nueve(0);
expMatematica(208)<= nueve(1);
expMatematica(209)<= nueve(2);
expMatematica(210)<= nueve(3);
expMatematica(211)<= nueve(4);
expMatematica(212)<= nueve(5);
else -- 0
expMatematica(207)<= cero(0);
expMatematica(208)<= cero(1);
expMatematica(209)<= cero(2);
expMatematica(210)<= cero(3);
expMatematica(211)<= cero(4);
expMatematica(212)<= cero(5);
end if;
end process expMatCal;
--ESPACIOS (1 columnas de ceros)
--antes de la X o el sen o cos
expMatematica(11)<=(others=>'0');
expMatematica(34)<=(others=>'0');
expMatematica(55)<=(others=>'0');
expMatematica(83)<=(others=>'0');
expMatematica(104)<=(others=>'0');
expMatematica(125)<=(others=>'0');
expMatematica(154)<=(others=>'0');
expMatematica(183)<=(others=>'0');
--antes del número
expMatematica(18)<=(others=>'0');
expMatematica(41)<=(others=>'0');
expMatematica(62)<=(others=>'0');
expMatematica(73)<=(others=>'0');
expMatematica(90)<=(others=>'0');
expMatematica(111)<=(others=>'0');
expMatematica(132)<=(others=>'0');
expMatematica(161)<=(others=>'0');
expMatematica(190)<=(others=>'0');
--antes del signo (menos en el primero)
expMatematica(22)<=(others=>'0');
expMatematica(45)<=(others=>'0');
expMatematica(66)<=(others=>'0');
expMatematica(77)<=(others=>'0');
expMatematica(94)<=(others=>'0');
expMatematica(115)<=(others=>'0');
expMatematica(136)<=(others=>'0');
expMatematica(165)<=(others=>'0');
--para el exponente
expMatematica(3)<=(others=>'0');
expMatematica(5)<=(others=>'0');
expMatematica(26)<=(others=>'0');
expMatematica(28)<=(others=>'0');
expMatematica(47)<=(others=>'0');
expMatematica(49)<=(others=>'0');
expMatematica(98)<=(others=>'0');
expMatematica(119)<=(others=>'0');
--dentro del sen y cos
expMatematica(142)<=(others=>'0');
expMatematica(171)<=(others=>'0');
expMatematica(148)<=(others=>'0');
expMatematica(177)<=(others=>'0');
--del log
expMatematica(194)<=(others=>'0');
expMatematica(200)<=(others=>'0');
expMatematica(206)<=(others=>'0');
expMatematica(213)<=(others=>'0');
-- Las posiciones mayores que anchoExp no se usan
expMatematica(anchoExp+1 to 255)<=(others=>"00000000000");
end Behavioral;
| gpl-3.0 | c18b5292399151367f99b64e777b316e | 0.661824 | 3.217607 | false | false | false | false |
hanyazou/vivado-ws | playpen/dvi2vga_nofilter/dvi2vga_nofilter.srcs/sources_1/ipshared/digilentinc.com/dvi2rgb_v1_5/a3d4f4cf/src/dvi2rgb.vhd | 1 | 11,028 | -------------------------------------------------------------------------------
--
-- File: dvi2rgb.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 24 July 2015
--
-------------------------------------------------------------------------------
-- (c) 2015 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module connects to a top level DVI 1.0 sink interface comprised of three
-- TMDS data channels and one TMDS clock channel. It includes the necessary
-- clock infrastructure, deserialization, phase alignment, channel deskew and
-- decode logic. It outputs 24-bit RGB video data along with pixel clock and
-- synchronization signals.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dvi2rgb is
Generic (
kEmulateDDC : boolean := true; --will emulate a DDC EEPROM with basic EDID, if set to yes
kRstActiveHigh : boolean := true; --true, if active-high; false, if active-low
kAddBUFG : boolean := true; --true, if PixelClk should be re-buffered with BUFG
kClkRange : natural := 1; -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3)
-- 7-series specific
kIDLY_TapValuePs : natural := 78; --delay in ps per tap
kIDLY_TapWidth : natural := 5); --number of bits for IDELAYE2 tap counter
Port (
-- DVI 1.0 TMDS video interface
TMDS_Clk_p : in std_logic;
TMDS_Clk_n : in std_logic;
TMDS_Data_p : in std_logic_vector(2 downto 0);
TMDS_Data_n : in std_logic_vector(2 downto 0);
-- Auxiliary signals
RefClk : in std_logic; --200 MHz reference clock for IDELAYCTRL, reset, lock monitoring etc.
aRst : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
aRst_n : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
-- Video out
vid_pData : out std_logic_vector(23 downto 0);
vid_pVDE : out std_logic;
vid_pHSync : out std_logic;
vid_pVSync : out std_logic;
PixelClk : out std_logic; --pixel-clock recovered from the DVI interface
SerialClk : out std_logic; -- advanced use only; 5x PixelClk
aPixelClkLckd : out std_logic; -- advanced use only; PixelClk and SerialClk stable
-- Optional DDC port
DDC_SDA_I : in std_logic;
DDC_SDA_O : out std_logic;
DDC_SDA_T : out std_logic;
DDC_SCL_I : in std_logic;
DDC_SCL_O : out std_logic;
DDC_SCL_T : out std_logic;
pRst : in std_logic; -- synchronous reset; will restart locking procedure
pRst_n : in std_logic -- synchronous reset; will restart locking procedure
);
end dvi2rgb;
architecture Behavioral of dvi2rgb is
type dataIn_t is array (2 downto 0) of std_logic_vector(7 downto 0);
type eyeSize_t is array (2 downto 0) of std_logic_vector(kIDLY_TapWidth-1 downto 0);
signal aLocked, SerialClk_int, PixelClk_int, pLockLostRst: std_logic;
signal pRdy, pVld, pDE, pAlignErr, pC0, pC1 : std_logic_vector(2 downto 0);
signal pDataIn : dataIn_t;
signal pEyeSize : eyeSize_t;
signal aRst_int, pRst_int : std_logic;
signal pData : std_logic_vector(23 downto 0);
signal pVDE, pHSync, pVSync : std_logic;
begin
ResetActiveLow: if not kRstActiveHigh generate
aRst_int <= not aRst_n;
pRst_int <= not pRst_n;
end generate ResetActiveLow;
ResetActiveHigh: if kRstActiveHigh generate
aRst_int <= aRst;
pRst_int <= pRst;
end generate ResetActiveHigh;
-- Clocking infrastructure to obtain a usable fast serial clock and a slow parallel clock
TMDS_ClockingX: entity work.TMDS_Clocking
generic map (
kClkRange => kClkRange)
port map (
aRst => aRst_int,
RefClk => RefClk,
TMDS_Clk_p => TMDS_Clk_p,
TMDS_Clk_n => TMDS_Clk_n,
aLocked => aLocked,
PixelClk => PixelClk_int, -- slow parallel clock
SerialClk => SerialClk_int -- fast serial clock
);
-- We need a reset bridge to use the asynchronous aLocked signal to reset our circuitry
-- and decrease the chance of metastability. The signal pLockLostRst can be used as
-- asynchronous reset for any flip-flop in the PixelClk domain, since it will be de-asserted
-- synchronously.
LockLostReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => not aLocked,
OutClk => PixelClk_int,
oRst => pLockLostRst);
-- Three data channel decoders
DataDecoders: for iCh in 2 downto 0 generate
DecoderX: entity work.TMDS_Decoder
generic map (
kCtlTknCount => kMinTknCntForBlank, --how many subsequent control tokens make a valid blank detection (DVI spec)
kTimeoutMs => kBlankTimeoutMs, --what is the maximum time interval for a blank to be detected (DVI spec)
kRefClkFrqMHz => 200, --what is the RefClk frequency
kIDLY_TapValuePs => kIDLY_TapValuePs, --delay in ps per tap
kIDLY_TapWidth => kIDLY_TapWidth) --number of bits for IDELAYE2 tap counter
port map (
aRst => pLockLostRst,
PixelClk => PixelClk_int,
SerialClk => SerialClk_int,
RefClk => RefClk,
pRst => pRst_int,
sDataIn_p => TMDS_Data_p(iCh),
sDataIn_n => TMDS_Data_n(iCh),
pOtherChRdy(1 downto 0) => pRdy((iCh+1) mod 3) & pRdy((iCh+2) mod 3), -- tie channels together for channel de-skew
pOtherChVld(1 downto 0) => pVld((iCh+1) mod 3) & pVld((iCh+2) mod 3), -- tie channels together for channel de-skew
pAlignErr => pAlignErr(iCh),
pC0 => pC0(iCh),
pC1 => pC1(iCh),
pMeRdy => pRdy(iCh),
pMeVld => pVld(iCh),
pVde => pDE(iCh),
pDataIn(7 downto 0) => pDataIn(iCh),
pEyeSize => pEyeSize(iCh)
);
end generate DataDecoders;
-- RGB Output conform DVI 1.0
-- except that it sends blank pixel during blanking
-- for some reason video_data uses RBG packing
pData(23 downto 16) <= pDataIn(2); -- red is channel 2
pData(7 downto 0) <= pDataIn(1); -- green is channel 1
pData(15 downto 8) <= pDataIn(0); -- blue is channel 0
pHSync <= pC0(0); -- channel 0 carries control signals too
pVSync <= pC1(0); -- channel 0 carries control signals too
pVDE <= pDE(0); -- since channels are aligned, all of them are either active or blanking at once
-- Clock outputs
SerialClk <= SerialClk_int; -- fast 5x pixel clock for advanced use only
aPixelClkLckd <= aLocked;
----------------------------------------------------------------------------------
-- Re-buffer PixelClk with a BUFG so that it can reach the whole device, unlike
-- through a BUFR. Since BUFG introduces a delay on the clock path, pixel data is
-- re-registered here.
----------------------------------------------------------------------------------
GenerateBUFG: if kAddBUFG generate
ResyncToBUFG_X: entity work.ResyncToBUFG
port map (
-- Video in
piData => pData,
piVDE => pVDE,
piHSync => pHSync,
piVSync => pVSync,
PixelClkIn => PixelClk_int,
-- Video out
poData => vid_pData,
poVDE => vid_pVDE,
poHSync => vid_pHSync,
poVSync => vid_pVSync,
PixelClkOut => PixelClk
);
end generate GenerateBUFG;
DontGenerateBUFG: if not kAddBUFG generate
vid_pData <= pData;
vid_pVDE <= pVDE;
vid_pHSync <= pHSync;
vid_pVSync <= pVSync;
PixelClk <= PixelClk_int;
end generate DontGenerateBUFG;
----------------------------------------------------------------------------------
-- Optional DDC EEPROM Display Data Channel - Bi-directional (DDC2B)
-- The EDID will be loaded from the file specified below in kInitFileName.
----------------------------------------------------------------------------------
GenerateDDC: if kEmulateDDC generate
DDC_EEPROM: entity work.EEPROM_8b
generic map (
kSampleClkFreqInMHz => 200,
kSlaveAddress => "1010000",
kAddrBits => 7, -- 128 byte EDID 1.x data
kWritable => false,
kInitFileName => "dgl_dvi_edid.txt") -- name of file containing init values
port map(
SampleClk => RefClk,
sRst => '0',
aSDA_I => DDC_SDA_I,
aSDA_O => DDC_SDA_O,
aSDA_T => DDC_SDA_T,
aSCL_I => DDC_SCL_I,
aSCL_O => DDC_SCL_O,
aSCL_T => DDC_SCL_T);
end generate GenerateDDC;
end Behavioral;
| mit | e15dbf3010bfc8982b396fee75f6d30a | 0.607091 | 4.54201 | false | false | false | false |
lnls-dig/dsp-cores | hdl/testbench/cic/cic_bench.vhd | 1 | 11,021 | -------------------------------------------------------------------------------
-- Title : CIC testbench
-- Project :
-------------------------------------------------------------------------------
-- File : cic_bench.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-03-10
-- Last update: 2016-05-06
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Testbench for generic CIC filter
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-03-10 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
use std.textio.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
use work.swap_pkg.all;
-------------------------------------------------------------------------------
entity cic_bench is
end entity cic_bench;
architecture str of cic_bench is
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
constant c_input_freq : real := 100.0e6;
constant c_clock_period : time := 1.0 sec /(2.0*c_input_freq);
constant c_delay_period : time := c_clock_period;
constant c_cycles_to_reset : natural := 4;
signal clock : std_logic := '0';
signal reset : std_logic := '1';
signal reset_n : std_logic := '0';
signal ce : std_logic := '1';
signal ce_out : std_logic := '1';
signal sw_out : std_logic := '0';
signal data_tag : std_logic_vector(0 downto 0) := "0";
signal data_tag_en : std_logic := '0';
signal valid : std_logic := '0';
signal freqgen_en : std_logic := '0';
constant c_input_width : natural := 24;
constant c_output_width : natural := c_input_width + 9;
constant c_diff_delay : natural := 1;
constant c_stages : natural := 1;
constant c_decimation_rate : natural := 32;
constant c_decimation_rate_log2 : natural := natural(ceil(log2(real(c_decimation_rate+1))));
constant c_bus_width : natural := natural(ceil(log2(real(c_decimation_rate))))+2;
constant c_data_mask_width : natural := 10;
signal data_mask_beg_num_samples : unsigned(c_data_mask_width-1 downto 0) := to_unsigned(10, c_data_mask_width);
signal data_mask_end_num_samples : unsigned(c_data_mask_width-1 downto 0) := to_unsigned(10, c_data_mask_width);
--signal data_mask_end_num_samples : unsigned(c_data_mask_width-1 downto 0) := to_unsigned(2, c_data_mask_width);
signal data_mask_en : std_logic := '0';
signal data_in : std_logic_vector(c_input_width-1 downto 0) := (others => '0');
signal data_out : std_logic_vector(c_output_width-1 downto 0);
signal cic_valid : std_logic;
signal valid_tr : std_logic;
signal sync_trig : std_logic := '0';
signal endoffile : std_logic := '0';
component cic_dyn is
generic (
g_input_width : natural := 16;
g_output_width : natural := 16;
g_stages : natural := 1; -- aka "N"
g_delay : natural := 1; -- aka "M"
g_max_rate : natural := 2048; -- Max decimation rate
g_bus_width : natural := 11; -- Decimation ratio bus width.
g_with_ce_synch : boolean := false;
g_tag_width : natural := 1; -- Input data tag width
g_data_mask_width : natural := 10; -- Input data mask width
g_round_convergent : natural := 0
);
port (
clk_i : in std_logic := '0';
rst_i : in std_logic := '0';
ce_i : in std_logic := '0';
ce_out_i : in std_logic := '0';
valid_i : in std_logic := '0';
data_i : in std_logic_vector(g_input_width-1 downto 0) := (others => '0');
data_tag_i : in std_logic_vector(g_tag_width-1 downto 0) := (others => '0');
data_tag_en_i : in std_logic := '0';
data_mask_num_samples_beg_i : in unsigned(g_data_mask_width-1 downto 0) := (others => '0');
data_mask_num_samples_end_i : in unsigned(g_data_mask_width-1 downto 0) := (others => '0');
data_mask_en_i : in std_logic := '0';
ratio_i : in std_logic_vector(g_bus_width-1 downto 0) := (others => '0');
data_o : out std_logic_vector(g_output_width-1 downto 0) := (others => '0');
valid_o : out std_logic := '0'
);
end component cic_dyn;
begin -- architecture str
clk_gen : process
begin
clock <= '1';
wait for c_clock_period/2;
clock <= '0';
wait for c_clock_period/2;
end process;
ce_gen : process
begin
if reset = '0' then
ce_out <= '0';
ce <= '0';
wait for 3*c_clock_period;
ce_out <= '1';
ce <= '1';
wait for c_clock_period;
else
ce_out <= '0';
ce <= '0';
wait for c_clock_period;
end if;
end process;
valid_tr_gen : process
begin
if reset = '0' then
valid_tr <= '0';
wait for 11*c_clock_period;
valid_tr <= '1';
wait for c_clock_period;
else
valid_tr <= '0';
wait for c_clock_period;
end if;
end process;
sync_trig_gen : process
begin
if reset = '0' then
wait for (12*c_decimation_rate-1)*c_clock_period;
sync_trig <= '1';
wait for c_clock_period;
sync_trig <= '0';
else
sync_trig <= '0';
wait for (4043+5)*c_delay_period;
end if;
end process;
cmp_tag : entity work.swap_freqgen
generic map (
g_delay_vec_width => 10,
g_swap_div_freq_vec_width => c_decimation_rate_log2
)
port map (
clk_i => clock,
rst_n_i => reset_n,
en_i => ce,
sync_trig_i => sync_trig,
-- Swap and de-swap signals
swap_o => open,
deswap_o => sw_out,
swap_mode_i => c_swmode_swap_deswap,
swap_div_f_i => std_logic_vector(to_unsigned(c_decimation_rate,
c_decimation_rate_log2)),
swap_div_f_cnt_en_i => valid,
deswap_delay_i => (others => '0')
);
--sw_gen : process
--begin
-- if reset = '0' then
-- sw_out <= '1';
-- wait for c_decimation_rate*c_clock_period;
-- sw_out <= '0';
-- wait for c_decimation_rate*c_clock_period;
-- else
-- sw_out <= '0';
-- wait for 3*c_clock_period;
-- end if;
--end process;
data_tag(0) <= sw_out;
data_tag_en_gen : process
begin
data_tag_en <= '0';
wait for 200*c_clock_period;
data_tag_en <= '1';
wait;
end process;
mask_gen : process
begin
data_mask_en <= '0';
wait for 10*c_clock_period;
data_mask_en <= '0';
wait for 1000*c_clock_period;
data_mask_en <= '1';
wait;
end process;
rst_gen : process(clock)
variable clock_count : natural := c_cycles_to_reset;
begin
if rising_edge(clock) and clock_count /= 0 then
clock_count := clock_count - 1;
if clock_count = 0 then
reset <= '0';
end if;
end if;
end process;
reset_n <= not reset;
--input_read : process(clock)
-- file data_file : text open read_mode is "cic.samples";
-- variable cur_line : line;
-- variable datain : integer;
--begin
-- if rising_edge(clock) and reset = '0' then
-- if not endfile(data_file) and valid_tr = '1' then
-- readline(data_file, cur_line);
-- read(cur_line, datain);
-- data_in <= std_logic_vector(to_signed(datain, c_input_width));
-- valid <= '1';
-- --else
-- elsif ce = '1' then
-- --endoffile <= '1';
-- valid <= '0';
-- end if;
-- end if;
--end process input_read;
input_read : process(clock)
file data_file : text open read_mode is "cic.samples";
variable cur_line : line;
variable datain : integer;
begin
if rising_edge(clock) and reset = '0' and ce = '1' then
if not endfile(data_file) and valid_tr = '1' then
readline(data_file, cur_line);
read(cur_line, datain);
data_in <= std_logic_vector(to_signed(datain, c_input_width));
valid <= '1';
else
--endoffile <= '1';
valid <= '0';
end if;
end if;
end process input_read;
uut : cic_dyn
generic map (
g_input_width => c_input_width,
g_output_width => c_output_width,
g_stages => c_stages,
g_delay => c_diff_delay,
g_max_rate => c_decimation_rate,
g_with_ce_synch => true,
g_bus_width => c_bus_width,
g_round_convergent => 1)
port map (
clk_i => clock,
rst_i => reset,
ce_i => ce,
ce_out_i => ce_out,
valid_i => valid,
data_i => data_in,
data_tag_i => data_tag,
data_tag_en_i => data_tag_en,
data_mask_num_samples_beg_i => data_mask_beg_num_samples,
data_mask_num_samples_end_i => data_mask_end_num_samples,
data_mask_en_i => data_mask_en,
ratio_i => std_logic_vector(to_unsigned(c_decimation_rate, c_bus_width)),
data_o => data_out,
valid_o => cic_valid);
output_write : process(cic_valid)
file ouput_file : text open write_mode is "cic_out.samples";
variable cur_line : line;
variable data : integer;
begin
if rising_edge(cic_valid) then
if(endoffile = '0') then
data := to_integer(signed(data_out));
write(cur_line, data);
writeline(ouput_file, cur_line);
else
assert (false) report "Input file finished." severity failure;
end if;
end if;
end process output_write;
end architecture str;
-------------------------------------------------------------------------------
| lgpl-3.0 | 06133d0832c9935a0393b0642e4682d8 | 0.469921 | 3.643306 | false | false | false | false |
bruskajp/EE-316 | Project2/Quartus_DE2Board/display_driver.vhd | 1 | 6,458 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity display_driver is
port( Input : in std_logic_vector(15 downto 0);
--clk : in std_logic;
HEX0 : out std_logic_vector(6 downto 0);
HEX1 : out std_logic_vector(6 downto 0);
HEX2 : out std_logic_vector(6 downto 0);
HEX3 : out std_logic_vector(6 downto 0);
HEX4 : out std_logic_vector(6 downto 0);
HEX5 : out std_logic_vector(6 downto 0);
HEX6 : out std_logic_vector(6 downto 0);
HEX7 : out std_logic_vector(6 downto 0)
);
end display_driver;
architecture behavior of display_driver is
signal H0 : std_logic_vector(3 downto 0);
signal H1 : std_logic_vector(3 downto 0);
signal H2 : std_logic_vector(3 downto 0);
signal H3 : std_logic_vector(3 downto 0);
--signal Sel : std_logic_vector(1 downto 0);
--signal clk_cnt : integer range 0 to 9;
--signal clk_en : std_logic;
begin
H0 <= Input(3 downto 0);
H1 <= Input(7 downto 4);
H2 <= Input(11 downto 8);
H3 <= Input(15 downto 12);
HEX4 <= "1111111";
HEX5 <= "1111111";
HEX6 <= "1111111";
HEX7 <= "1111111";
-- begin
-- if rising_edge(clk) and clk_en='1' then
-- Sel <= Sel + 1;
-- end if;
-- end process;
--
-- process(clk)
-- begin
-- if rising_edge(clk) then
-- if (clk_cnt = 9) then
-- clk_cnt <= 0;
-- clk_en <= '1';
-- else
-- clk_cnt <= clk_cnt + 1;
-- clk_en <= '0';
-- end if;
-- end if;
-- end process;
--
-- process(Sel)
-- begin
-- case Sel is
-- when "00" => H0 <= Input(3 downto 0);
-- when "01" => H1 <= Input(7 downto 4);
-- when "10" => H2 <= Input(11 downto 8);
-- when "11" => H3 <= Input(15 downto 12);
-- when others => H0 <= "1111"; H1 <= "1111"; H2 <= "1111"; H3 <= "1111";
-- end case;
-- end process;
process(H0)
begin
case H0 is
when "0000" => HEX0 <="1000000"; -- 0 shown on display
when "0001" => HEX0 <="1111001"; -- 1 shown on display
when "0010" => HEX0 <="0100100"; -- 2 shown on display
when "0011" => HEX0 <="0110000"; -- 3 shown on display
when "0100" => HEX0 <="0011001"; -- 4 shown on display
when "0101" => HEX0 <="0010010"; -- 5 shown on display
when "0110" => HEX0 <="0000010"; -- 6 shown on display
when "0111" => HEX0 <="1111000"; -- 7 shown on display
when "1000" => HEX0 <="0000000"; -- 8 shown on display
when "1001" => HEX0 <="0010000"; -- 9 shown on display
when "1010" => HEX0 <="0001000"; -- A shown on display
when "1011" => HEX0 <="0000011"; -- b shown on display
when "1100" => HEX0 <="1000110"; -- C shown on display
when "1101" => HEX0 <="0100001"; -- d shown on display
when "1110" => HEX0 <="0000110"; -- E shown on display
when "1111" => HEX0 <="0001110"; -- F shown on display
when others => HEX0 <="0001110"; -- F shown on display
end case;
end process;
process(H1)
begin
case H1 is
when "0000" => HEX1 <="1000000"; -- 0 shown on display
when "0001" => HEX1 <="1111001"; -- 1 shown on display
when "0010" => HEX1 <="0100100"; -- 2 shown on display
when "0011" => HEX1 <="0110000"; -- 3 shown on display
when "0100" => HEX1 <="0011001"; -- 4 shown on display
when "0101" => HEX1 <="0010010"; -- 5 shown on display
when "0110" => HEX1 <="0000010"; -- 6 shown on display
when "0111" => HEX1 <="1111000"; -- 7 shown on display
when "1000" => HEX1 <="0000000"; -- 8 shown on display
when "1001" => HEX1 <="0010000"; -- 9 shown on display
when "1010" => HEX1 <="0001000"; -- A shown on display
when "1011" => HEX1 <="0000011"; -- b shown on display
when "1100" => HEX1 <="1000110"; -- C shown on display
when "1101" => HEX1 <="0100001"; -- d shown on display
when "1110" => HEX1 <="0000110"; -- E shown on display
when "1111" => HEX1 <="0001110"; -- F shown on display
when others => HEX1 <="0001110"; -- F shown on display
end case;
end process;
process(H2)
begin
case H2 is
when "0000" => HEX2 <="1000000"; -- 0 shown on display
when "0001" => HEX2 <="1111001"; -- 1 shown on display
when "0010" => HEX2 <="0100100"; -- 2 shown on display
when "0011" => HEX2 <="0110000"; -- 3 shown on display
when "0100" => HEX2 <="0011001"; -- 4 shown on display
when "0101" => HEX2 <="0010010"; -- 5 shown on display
when "0110" => HEX2 <="0000010"; -- 6 shown on display
when "0111" => HEX2 <="1111000"; -- 7 shown on display
when "1000" => HEX2 <="0000000"; -- 8 shown on display
when "1001" => HEX2 <="0010000"; -- 9 shown on display
when "1010" => HEX2 <="0001000"; -- A shown on display
when "1011" => HEX2 <="0000011"; -- b shown on display
when "1100" => HEX2 <="1000110"; -- C shown on display
when "1101" => HEX2 <="0100001"; -- d shown on display
when "1110" => HEX2 <="0000110"; -- E shown on display
when "1111" => HEX2 <="0001110"; -- F shown on display
when others => HEX2 <="0001110"; -- F shown on display
end case;
end process;
process(H3)
begin
case H3 is
when "0000" => HEX3 <="1000000"; -- 0 shown on display
when "0001" => HEX3 <="1111001"; -- 1 shown on display
when "0010" => HEX3 <="0100100"; -- 2 shown on display
when "0011" => HEX3 <="0110000"; -- 3 shown on display
when "0100" => HEX3 <="0011001"; -- 4 shown on display
when "0101" => HEX3 <="0010010"; -- 5 shown on display
when "0110" => HEX3 <="0000010"; -- 6 shown on display
when "0111" => HEX3 <="1111000"; -- 7 shown on display
when "1000" => HEX3 <="0000000"; -- 8 shown on display
when "1001" => HEX3 <="0010000"; -- 9 shown on display
when "1010" => HEX3 <="0001000"; -- A shown on display
when "1011" => HEX3 <="0000011"; -- b shown on display
when "1100" => HEX3 <="1000110"; -- C shown on display
when "1101" => HEX3 <="0100001"; -- d shown on display
when "1110" => HEX3 <="0000110"; -- E shown on display
when "1111" => HEX3 <="0001110"; -- F shown on display
when others => HEX3 <="0001110"; -- F shown on display
end case;
end process;
end behavior;
| gpl-3.0 | 7dfc1c91f410439fd65850c6c9e40dd2 | 0.546454 | 3.472043 | false | false | false | false |
Ana06/function-graphing-FPGA | KbdTxData.vhd | 2 | 10,141 | ----------------------------------------------------------------------------------
-- Company:
-- EngINeer: Ali Diouri
--
-- Create Date: 20:59:21 05/03/2012
-- Design Name:
-- Module Name: KbdCore - Behavioral
-- Project Name: KbdTxData
-- Target Devices:
-- Tool versions: XilINx ISE 14.4
-- Description:
-- http://www.computer-engINeerINg.org/ps2protocol/
--
-- 1) BrINg the Clock lINe low for at least 100 microseconds.
-- 2) BrINg the Data lINe low.
-- 3) Release the Clock lINe.
-- 4) Wait for the device to brINg the Clock lINe low.
-- 5) Set/reset the Data lINe to Tx_en the first data bit
-- 6) Wait for the device to brINg Clock high.
-- 7) Wait for the device to brINg Clock low.
-- 8) Repeat steps 5-7 for the other seven data bits and the parity bit
-- 9) Release the Data lINe.
-- 10) Wait for the device to brINg Data low.
-- 11) Wait for the device to brINg Clock low.
-- 12) Wait for the device to release Data and Clock
-- DepENDencies:
--
-- RevISion:
-- RevISion 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
entity KbdTxData IS
Port (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
Tx_en : IN STD_LOGIC;
kbd_dataf : IN STD_LOGIC;
kbd_clkf : IN STD_LOGIC;
Data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
busy : OUT STD_LOGIC;
T_Data : OUT STD_LOGIC; --WHEN T=0, IO = OUT; WHEN T=1, IO = IN;
T_Clk : OUT STD_LOGIC; --WHEN T=0, IO = OUT; WHEN T=1, IO = IN;
KbdData : OUT STD_LOGIC;
KbdClk : OUT STD_LOGIC
);
END KbdTxData;
ARCHITECTURE Behavioral OF KbdTxData IS
TYPE state_type IS (reset,INit, clkLow,
startSEND,startbit,
bitshIFt,bitsEND,
parity,tempo_parity,
stopbit,akn,
DevRelease,ENDFSM);
SIGNAL state, next_state: state_type ;
SIGNAL cnt : std_logic_vector(12 DOWNTO 0):=(OTHERS=>'0');
SIGNAL startCount : std_logic:='0';
SIGNAL ENDCount : std_logic:='0';
SIGNAL shIFt : std_logic:='0';
SIGNAL ENDshIFt : std_logic:='0';
SIGNAL shIFtcnt : std_logic_vector(2 DOWNTO 0):=(OTHERS=>'0');
SIGNAL dataReg : std_logic_vector(7 DOWNTO 0):=(OTHERS=>'0');
SIGNAL INt_busy : std_logic;
SIGNAL INt_T_Clk : std_logic;
SIGNAL INt_T_Data : std_logic;
SIGNAL INt_KbdData : std_logic;
SIGNAL INt_KbdClk : std_logic;
BEGIN
Sequential: PROCESS (clk,rst)
BEGIN
IF (rst = '1') THEN
state <= INit;
ELSIF (clk='1' and clk'Event) THEN
state <= next_state;
END IF;
END PROCESS;
-- Counter
PROCESS (clk,rst)
BEGIN
IF (rst = '1') THEN
cnt <= (OTHERS=>'0');
ENDCount <= '0';
ELSIF (clk = '1' and clk'Event) THEN
ENDCount <= '0';
cnt <= (OTHERS=>'0');
IF(startCount = '1') THEN
cnt <= cnt+'1';
IF (cnt = X"1388") THEN -- 100 us
cnt <= (OTHERS=>'0');
ENDCount <= '1';
END IF;
END IF;
END IF;
END PROCESS;
Dataproc:PROCESS(clk,rst)
BEGIN
IF (rst = '1') THEN
dataReg <= X"FF";
shIFtcnt <= "000";
ENDshIFt <= '0';
ELSIF (clk = '1' and clk'Event) THEN
IF (state = INit) THEN
dataReg <= data;
shIFtcnt <= "000";
ENDshIFt <= '0';
ELSIF (shIFtcnt = "111") THEN
shIFtcnt <= "000";
ENDshIFt <= '1';
ELSIF (shIFt = '1') THEN
ENDshIFt <= '0';
shIFtcnt <= shIFtcnt + '1';
dataReg <= dataReg(0) & dataReg(7 DOWNTO 1);
END IF;
END IF;
END PROCESS;
CntrlFSM : PROCESS (state, kbd_clkf, kbd_dataf,ENDCount,Tx_en,ENDshIFt)
BEGIN
CASE state IS
WHEN reset =>
INt_busy <= '0';
INt_T_Clk <= '1';
INt_T_Data <= '1';
shIFt <= '0';
startCount <= '0';
INt_KbdData <= '1';
INt_KbdClk <= '1';
next_state <= clkLow;
WHEN INit =>
INt_busy <= '0';
INt_T_Clk <= '1';
INt_T_Data <= '1';
shIFt <= '0';
startCount <= '0';
INt_KbdData <= '1';
INt_KbdClk <= '1';
IF (Tx_en = '1') THEN
next_state <= clkLow;
ELSIF (Tx_en='0') THEN
next_state <= INit;
END IF;
WHEN clkLow =>
INt_busy <= '1';
INt_T_Clk <= '0';
INt_T_Data <= '1';
shIFt <= '0';
INt_KbdData <= '1';
INt_KbdClk <= '0';
IF (ENDCount = '1') THEN
startCount <= '0';
next_state <= startSEND;
ELSE
startCount <= '1';
next_state <= clkLow;
END IF;
WHEN startSEND =>
INt_busy <= '1';
INt_T_Clk <= '1';
INt_T_Data <= '0';
shIFt <= '0';
INt_KbdClk <= '1';
INt_KbdData <= '0';
startCount <= '0';
IF (kbd_clkf = '1') THEN
next_state <= startbit;
ELSE
next_state <= startSEND;
END IF;
WHEN startbit =>
INt_busy <= '1';
INt_T_Clk <= '1';
INt_T_Data <= '0';
shIFt <= '0';
INt_KbdClk <= '1';
INt_KbdData <= '0';
startCount <= '0';
IF (kbd_clkf = '0') THEN
next_state <= bitshIFt;
ELSE
next_state <= startbit;
END IF;
WHEN bitshIFt =>
INt_busy <= '1';
INt_T_Clk <= '1';
INt_T_Data <= '0';
shIFt <= '0';
INt_KbdClk <= '1';
INt_KbdData <= dataReg(0);
startCount <='0';
IF (kbd_clkf = '1') THEN
next_state <= bitsEND;
ELSE
next_state <= bitshIFt;
END IF;
WHEN bitsEND =>
INt_busy <= '1';
INt_T_Clk <= '1';
INt_T_Data <= '0';
INt_KbdClk <= '1';
INt_KbdData <= dataReg(0);
startCount <= '0';
IF (kbd_clkf = '1') THEN
shIFt <= '0';
next_state <= bitsEND;
ELSIF (ENDshIFt = '1') THEN
shIFt <= '0';
next_state <= parity;
ELSE
shIFt <= '1';
next_state <= bitshIFt;
END IF;
WHEN parity =>
INt_busy <= '1';
INt_T_Clk <= '1';
INt_T_Data <= '0';
shIFt <= '0';
INt_KbdClk <= '1';
INt_KbdData <= not(DataReg(7) xor DataReg(6) xor DataReg(5) xor DataReg(4) xor DataReg(3) xor DataReg(2) xor DataReg(1) xor DataReg(0));
startCount <= '0';
IF (kbd_clkf = '1') THEN
next_state <= tempo_parity;
ELSE
next_state <= parity;
END IF;
WHEN tempo_parity =>
INt_busy <= '1';
INt_T_Clk <= '1';
INt_T_Data <= '0';
shIFt <= '0';
INt_KbdClk <= '1';
INt_KbdData <= not(DataReg(7) xor DataReg(6) xor DataReg(5) xor DataReg(4) xor DataReg(3) xor DataReg(2) xor DataReg(1) xor DataReg(0));
startCount <= '0';
IF (kbd_clkf = '0') THEN
next_state <= stopbit;
ELSE
next_state <= tempo_parity;
END IF;
WHEN stopbit =>
INt_busy <= '1';
INt_T_Clk <= '1';
INt_T_Data <= '0';
shIFt <= '0';
INt_KbdClk <= '1';
INt_KbdData <= '1';
startCount <= '0';
IF kbd_clkf = '1' THEN
next_state <= akn;
ELSE
next_state <= stopbit;
END IF;
WHEN Akn =>
INt_busy <= '1';
INt_T_Clk <= '1';
INt_T_Data <= '1';
shIFt <= '0';
INt_KbdClk <= '1';
INt_KbdData <= '1';
startCount <= '0';
IF (kbd_dataf = '0') THEN
next_state <= DevRelease;
ELSE
next_state <= Akn;
END IF;
WHEN DevRelease =>
INt_busy <= '1';
INt_T_Clk <= '1';
INt_T_Data <= '1';
shIFt <= '0';
startCount <= '0';
INt_KbdData <= '1';
INt_KbdClk <= '1';
IF (kbd_dataf = '1') THEN
next_state <= ENDFSM;
ELSE
next_state <= DevRelease;
END IF;
WHEN ENDFSM =>
INt_busy <= '0';
INt_T_Clk <= '1';
INt_T_Data <= '1';
shIFt <= '0';
startCount <= '0';
INt_KbdData <= '1';
INt_KbdClk <= '1';
next_state <= INit;
END case;
END PROCESS;
OUTput: PROCESS (clk,rst)
BEGIN
IF (rst = '1') THEN
busy <= '0';
T_Clk <= '1';
T_Data <= '1';
KbdData <= '1';
KbdClk <= '1';
ELSIF (clk='1' and clk'Event) THEN
busy <= INt_busy;
T_Clk <= INt_T_Clk;
T_Data <= INt_T_Data;
KbdData <= INt_KbdData;
KbdClk <= INt_KbdClk;
END IF;
END PROCESS;
END Behavioral;
| gpl-3.0 | a548a21098c7cbabaf7b684c2ef9792e | 0.411892 | 3.72968 | false | false | false | false |
hanyazou/vivado-ws | playpen/dvi2vga_nofilter/dvi2vga_nofilter.srcs/sources_1/ipshared/digilentinc.com/rgb2vga_v1_0/910567e3/src/rgb2vga.vhd | 6 | 4,009 | -------------------------------------------------------------------------------
--
-- File: rgb2vga.vhd
-- Author: Elod Gyorgy
-- Original Project: Genesys 2 demo project
-- Date: 20 March 2015
--
-------------------------------------------------------------------------------
-- (c) 2015 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- To provide a properly blanked vga signal from an rgb interface
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rgb2vga is
Generic (
VID_IN_DATA_WIDTH : natural := 24;
kRedDepth : natural := 5;
kGreenDepth : natural := 6;
kBlueDepth : natural := 5
);
Port (
rgb_pData : in std_logic_vector(VID_IN_DATA_WIDTH-1 downto 0);
rgb_pVDE : in std_logic;
rgb_pHSync : in std_logic;
rgb_pVSync : in std_logic;
PixelClk : in std_logic; --pixel clock
vga_pRed : out std_logic_vector(kRedDepth-1 downto 0);
vga_pGreen : out std_logic_vector(kGreenDepth-1 downto 0);
vga_pBlue : out std_logic_vector(kBlueDepth-1 downto 0);
vga_pHSync : out std_logic;
vga_pVSync : out std_logic
);
end rgb2vga;
architecture Behavioral of rgb2vga is
signal int_pData : std_logic_vector(VID_IN_DATA_WIDTH-1 downto 0);
begin
Blanking: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (rgb_pVDE = '1') then
int_pData <= rgb_pData;
else
int_pData <= (others => '0');
end if;
vga_pHSync <= rgb_pHSync;
vga_pVSync <= rgb_pVSync;
end if;
end process Blanking;
vga_pRed <= int_pData(VID_IN_DATA_WIDTH-1 downto VID_IN_DATA_WIDTH - kRedDepth);
vga_pBlue <= int_pData(VID_IN_DATA_WIDTH/3*2-1 downto VID_IN_DATA_WIDTH/3*2 - kBlueDepth);
vga_pGreen <= int_pData(VID_IN_DATA_WIDTH/3-1 downto VID_IN_DATA_WIDTH/3 - kGreenDepth);
end Behavioral;
| mit | 4566d9df8f5b2a43bde00d501e3b4ea7 | 0.652781 | 4.202306 | false | false | false | false |
TanND/Electronic | VHDL/alu8bit.vhd | 1 | 2,280 | -------------------------------------------------------------------------------
--
-- Title : ALU_procedure
-- Design : de1
-- Author : [email protected]
-- Company : homes
--
-------------------------------------------------------------------------------
--
-- File : ALU_procedure.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU_procedure is
port(
cin : in STD_LOGIC;
a : in STD_LOGIC_VECTOR(7 downto 0);
b : in STD_LOGIC_VECTOR(7 downto 0);
sel : in STD_LOGIC_VECTOR(3 downto 0);
y : out STD_LOGIC_VECTOR(7 downto 0)
);
end ALU_procedure;
--}} End of automatically maintained section
architecture ALU_procedure of ALU_procedure is
procedure hamlogic
(
signal x1,x2: in std_logic_vector(7 downto 0);
signal sel : in STD_LOGIC_VECTOR(2 downto 0);
signal y1: out std_logic_vector(7 downto 0)
) is
begin
if sel = "000" then y1<= not x1;
elsif sel ="001" then y1<= not x2;
elsif sel ="010" then y1<= x1 and x2;
elsif sel ="011" then y1<= x1 or x2;
elsif sel ="100" then y1<= x1 nand x2;
elsif sel ="101" then y1<= x1 nor x2;
elsif sel ="110" then y1<= x1 xor x2;
elsif sel ="111" then y1<= x1 xnor x2;
end if ;
end hamlogic;
procedure hamsohoc
(
signal x1,x2: in std_logic_vector(7 downto 0) ;
signal sel : in STD_LOGIC_VECTOR(2 downto 0);
signal cin: in std_logic;
signal y2: out std_logic_vector(7 downto 0)
) is
begin
if sel ="000" then y2<= a;
elsif sel ="001" then y2<=a+1;
elsif sel ="010" then y2<=a-1;
elsif sel ="011" then y2<=b;
elsif sel ="100" then y2<=b+1;
elsif sel ="101" then y2<=b-1;
elsif sel ="110" then y2<=a+b;
elsif sel ="111" then y2<=a+b+cin;
end if;
end hamsohoc;
procedure hammux
(
signal y1: in std_logic_vector(7 downto 0) ;
signal y2: in std_logic_vector(7 downto 0);
signal sel : in STD_LOGIC;
signal y: out std_logic_vector(7 downto 0)
) is
begin
if sel='0'then y<=y1;
else y<=y2;
end if;
end hammux;
signal w1,w2: std_logic_vector (7 downto 0);
begin
process(sel,a,b,cin)
begin
hamlogic(a,b,sel(2 downto 0),w1);
hamsohoc(a,b,sel(2 downto 0),cin,w2);
hammux(w1,w2,sel(3),y);
end process;
end ALU_procedure;
| apache-2.0 | e563370f7dc4a578d3563877af37ade7 | 0.592105 | 2.770352 | false | false | false | false |
bruskajp/EE-316 | Project4/Vivado_NexysBoard/craddockEE316/craddockEE316.srcs/sources_1/imports/testFolder/nregister.vhd | 1 | 1,237 | -- file: nregister.vhd
-------------------------------------
-- n bit register for use in carry save counter
-- Shauna Rae
-- October 4, 1999
library ieee;
use ieee.std_logic_1164.all;
-- component nregister is
-- generic (data_width : positive := 16);
--- port(clock, reset : in std_logic;
-- register_in: in std_logic_vector(data_width-1 downto 0);
-- register_out : out std_logic_vector(data_width-1 downto 0));
-- end component nregister;
--define the entity of nregister
entity nregister is
generic (data_width : positive := 16);
port(clock, reset: in std_logic;
register_in: in std_logic_vector(data_width-1 downto 0);
register_out: out std_logic_vector(data_width-1 downto 0));
end nregister;
architecture basic of nregister is
begin
--define a process that is dependent on reset and a clock
register_behaviour: process(clock, reset) is
begin
if reset = '0' then -- on reset zero the output
register_out <= (others => '0');
--on rising edge of clock set output to input
elsif rising_edge(clock) then
register_out <= register_in;
end if;
end process register_behaviour;
end basic; | gpl-3.0 | fcca5189de7f6beffa5268b45ecbbc25 | 0.621665 | 3.606414 | false | false | false | false |
JarrettR/FPGA-Cryptoparty | FPGA/hdl/sha1_process_buffer.vhd | 1 | 9,744 | --------------------------------------------------------------------------------
-- Final stage of SHA1 algorithm - process existing buffer and calc outputs
-- Copyright (C) 2016 Jarrett Rainier
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sha1_pkg.all;
entity sha1_process_buffer is
port(
clk_i : in std_ulogic;
rst_i : in std_ulogic;
dat_i : in w_full;
load_i : in std_ulogic;
new_i : in std_ulogic;
dat_w_i : in w_output;
dat_w_o : out w_output;
valid_o : out std_ulogic
);
end sha1_process_buffer;
architecture RTL of sha1_process_buffer is
signal w: w_full;
--signal w_con: w_full;
signal w_hold: w_full;
signal running: std_ulogic;
-- synthesis translate_off
signal test_word_1: std_ulogic_vector(0 to 31);
signal test_word_2: std_ulogic_vector(0 to 31);
signal test_word_3: std_ulogic_vector(0 to 31);
signal test_word_4: std_ulogic_vector(0 to 31);
signal test_word_5: std_ulogic_vector(0 to 31);
-- synthesis translate_on
signal i : integer range 0 to 79;
signal a: unsigned(0 to 31);
signal b: unsigned(0 to 31);
signal c: unsigned(0 to 31);
signal d: unsigned(0 to 31);
signal e: unsigned(0 to 31);
signal a_con: std_ulogic_vector(0 to 31);
signal b_con: std_ulogic_vector(0 to 31);
signal c_con: std_ulogic_vector(0 to 31);
signal d_con: std_ulogic_vector(0 to 31);
signal e_con: std_ulogic_vector(0 to 31);
--Algorithm variables
constant h0i : std_ulogic_vector(0 to 31) := X"67452301"; -- H0 (a)
constant h1i : std_ulogic_vector(0 to 31) := X"EFCDAB89"; -- H1 (b)
constant h2i : std_ulogic_vector(0 to 31) := X"98BADCFE"; -- H2 (c)
constant h3i : std_ulogic_vector(0 to 31) := X"10325476"; -- H3 (d)
constant h4i : std_ulogic_vector(0 to 31) := X"C3D2E1F0"; -- H4 (e)
constant k0 : std_ulogic_vector(0 to 31) := X"5A827999"; -- ( 0 <= t <= 19)
constant k1 : std_ulogic_vector(0 to 31) := X"6ED9EBA1"; -- (20 <= t <= 39)
constant k2 : std_ulogic_vector(0 to 31) := X"8F1BBCDC"; -- (40 <= t <= 59)
constant k3 : std_ulogic_vector(0 to 31) := X"CA62C1D6"; -- (60 <= t <= 79)
signal h0 : std_ulogic_vector(0 to 31) := h0i;
signal h1 : std_ulogic_vector(0 to 31) := h1i;
signal h2 : std_ulogic_vector(0 to 31) := h2i;
signal h3 : std_ulogic_vector(0 to 31) := h3i;
signal h4 : std_ulogic_vector(0 to 31) := h4i;
signal h0out : unsigned(0 to 31);
signal h1out : unsigned(0 to 31);
signal h2out : unsigned(0 to 31);
signal h3out : unsigned(0 to 31);
signal h4out : unsigned(0 to 31);
begin
process(clk_i)
begin
if (clk_i'event and clk_i = '1') then
if rst_i = '1' then
i <= 0;
--running <= '0';
--Todo: Reset input too, if needed
--for x in 0 to 79 loop
-- w_hold(x) <= "00000000000000000000000000000000";
--end loop;
h0 <= h0i;
h1 <= h1i;
h2 <= h2i;
h3 <= h3i;
h4 <= h4i;
else
if load_i = '1' then
if new_i = '1' then
h0 <= h0i;
h1 <= h1i;
h2 <= h2i;
h3 <= h3i;
h4 <= h4i;
a <= unsigned((h1i and h2i) or ((not h1i) and h3i)) +
rotate_left(unsigned(h0i), 5) +
unsigned(h4i) +
unsigned(dat_i(0)) +
unsigned(k0);
b <= unsigned(h0i);
c <= rotate_left(unsigned(h1i), 30);
d <= unsigned(h2i);
e <= unsigned(h3i);
else
h0 <= dat_w_i(0);
h1 <= dat_w_i(1);
h2 <= dat_w_i(2);
h3 <= dat_w_i(3);
h4 <= dat_w_i(4);
a <= unsigned((dat_w_i(1) and dat_w_i(2)) or ((not dat_w_i(1)) and dat_w_i(3))) +
rotate_left(unsigned(dat_w_i(0)), 5) +
unsigned(dat_w_i(4)) +
unsigned(dat_i(0)) +
unsigned(k0);
b <= unsigned(dat_w_i(0));
c <= rotate_left(unsigned(dat_w_i(1)), 30);
d <= unsigned(dat_w_i(2));
e <= unsigned(dat_w_i(3));
end if;
i <= 0;
else
--TEMP = S^5(A) + f(t;B,C,D) + E + W(t) + K(t);
--Alt: gotta be better way!
case i is
--f(t;B,C,D) = (B AND C) OR ((NOT B) AND D)
when 0 to 18 => a <= unsigned((b_con and c_con) or ((not b_con) and d_con)) +
rotate_left(unsigned(a_con), 5) +
unsigned(e_con) +
unsigned(w(i + 1)) +
unsigned(k0);
--f(t;B,C,D) = B XOR C XOR D
when 19 to 38 => a <= unsigned(b_con xor c_con xor d_con) +
rotate_left(unsigned(a_con), 5) +
unsigned(e_con) +
unsigned(w(i + 1)) +
unsigned(k1);
--f(t;B,C,D) = (B AND C) OR (B AND D) OR (C AND D)
when 39 to 58 => a <= unsigned((b_con and c_con) or (b_con and d_con) or (c_con and d_con)) +
rotate_left(unsigned(a_con), 5) +
unsigned(e_con) +
unsigned(w(i + 1)) +
unsigned(k2);
--f(t;B,C,D) = B XOR C XOR D
when 59 to 78 => a <= unsigned(b_con xor c_con xor d_con) +
rotate_left(unsigned(a_con), 5) +
unsigned(e_con) +
unsigned(w(i + 1)) +
unsigned(k3);
when 79 => a <= unsigned(b_con xor c_con xor d_con) +
rotate_left(unsigned(a_con), 5) +
unsigned(e_con) +
unsigned(w(i)) +
unsigned(k3);
end case;
--E = D; D = C; C = S^30(B); B = A; A = TEMP;
e <= unsigned(d_con);
d <= unsigned(c_con);
c <= rotate_left(unsigned(b_con), 30);
b <= unsigned(a_con);
i <= i + 1;
end if;
if i = 79 then
--i <= 0;
--Todo: AND 'running' signal with i = 79 to stop incorrect 'valid_o' outputs
valid_o <= '1';
h0out <= unsigned(h0) + a;
h1out <= unsigned(h1) + b;
h2out <= unsigned(h2) + c;
h3out <= unsigned(h3) + d;
h4out <= unsigned(h4) + e;
else
valid_o <= '0';
end if;
end if;
end if;
end process;
dat_w_o(0) <= std_ulogic_vector(h0out);
dat_w_o(1) <= std_ulogic_vector(h1out);
dat_w_o(2) <= std_ulogic_vector(h2out);
dat_w_o(3) <= std_ulogic_vector(h3out);
dat_w_o(4) <= std_ulogic_vector(h4out);
w <= dat_i;
--w_con <= w;
a_con <= std_ulogic_vector(a);
b_con <= std_ulogic_vector(b);
c_con <= std_ulogic_vector(c);
d_con <= std_ulogic_vector(d);
e_con <= std_ulogic_vector(e);
-- synthesis translate_off
test_word_1 <= w(0);
test_word_2 <= w(79);
test_word_3 <= h0;
test_word_4 <= std_ulogic_vector(h0out);
test_word_5 <= std_ulogic_vector(h1out);
-- synthesis translate_on
end RTL; | gpl-3.0 | fae726c3adda703c41e539704dee7ee6 | 0.406301 | 3.736196 | false | false | false | false |
TanND/Electronic | VHDL/D14_C1.vhd | 1 | 1,179 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity D14_C1 is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR(6 downto 0)
);
end D14_C1;
architecture D14_C1 of D14_C1 is
signal temp:STD_Logic_vector (3 downto 0);
begin
process (clk,rst)
begin
if(rst='1') then
temp<="0000";
elsif (rising_edge(clk)) then
if(temp="1111") then temp<="0000";
else temp <= temp+1;
end if;
end if;
end process;
process(temp)
begin
case temp is
WHEN "0000"=>seg<="1111110";
WHEN "0001"=>seg<="0110000";
WHEN "0010"=>seg<="1101101";
WHEN "0011"=>seg<="1111001";
WHEN "0100"=>seg<="0110011";
WHEN "0101"=>seg<="1011011";
WHEN "0110"=>seg<="1011111";
WHEN "0111"=>seg<="1110000";
WHEN "1000"=>seg<="1111111";
WHEN "1001"=>seg<="1111011";
WHEN "1010"=>seg<="1110111";
WHEN "1011"=>seg<="0011111";
WHEN "1100"=>seg<="1001110";
WHEN "1101"=>seg<="0111101";
WHEN "1110"=>seg<="1001111";
WHEN "1111"=>seg<="1000111";
WHEN OTHERS=>seg<="XXXXXXX";
end case;
end process;
end D14_C1;
-- rst=500khz; clk=20Mhz; | apache-2.0 | 3c3f763875d731b596ddfe3b867b9d50 | 0.60475 | 2.889706 | false | false | false | false |
lnls-dig/dsp-cores | hdl/modules/cic/cic_dyn.vhd | 1 | 12,052 | -------------------------------------------------------------------------------
-- Title : CIC with dynamically-adjustable decimator
-- Project :
-------------------------------------------------------------------------------
-- File : cic.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-03-11
-- Last update: 2016-05-02
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: CIC with dinamically adjustable decimation rate
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-03-11 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
use work.dsp_cores_pkg.all;
-------------------------------------------------------------------------------
entity cic_dyn is
generic (
g_input_width : natural := 16;
g_output_width : natural := 16;
g_stages : natural := 1; -- aka "N"
g_delay : natural := 1; -- aka "M"
g_max_rate : natural := 2048; -- Max decimation rate
g_tag_desync_cnt_width : natural := 14;
g_bus_width : natural := 11; -- Decimation ratio bus width.
g_with_ce_synch : boolean := false;
g_tag_width : natural := 1; -- Input data tag width
g_data_mask_width : natural := 16; -- Input data mask width
g_round_convergent : natural := 0
);
port (
clk_i : in std_logic := '0';
rst_i : in std_logic := '0';
ce_i : in std_logic := '0';
ce_out_i : in std_logic := '0';
valid_i : in std_logic := '0';
data_i : in std_logic_vector(g_input_width-1 downto 0) := (others => '0');
data_tag_i : in std_logic_vector(g_tag_width-1 downto 0) := (others => '0');
data_tag_en_i : in std_logic := '0';
data_tag_desync_cnt_rst_i : in std_logic := '0';
data_tag_desync_cnt_o : out std_logic_vector(g_tag_desync_cnt_width-1 downto 0);
data_mask_num_samples_beg_i : in unsigned(g_data_mask_width-1 downto 0) := (others => '0');
data_mask_num_samples_end_i : in unsigned(g_data_mask_width-1 downto 0) := (others => '0');
data_mask_en_i : in std_logic := '0';
ratio_i : in std_logic_vector(g_bus_width-1 downto 0) := (others => '0');
data_o : out std_logic_vector(g_output_width-1 downto 0) := (others => '0');
valid_o : out std_logic := '0'
);
end entity cic_dyn;
-------------------------------------------------------------------------------
architecture str of cic_dyn is
signal decimation_strobe : std_logic := '0';
signal decimation_strobe_d0 : std_logic := '0';
signal data_out : std_logic_vector(g_output_width-1 downto 0) := (others => '0');
signal valid_out : std_logic := '0';
signal synch_int : std_logic := '0';
signal desync_cnt : unsigned(g_tag_desync_cnt_width-1 downto 0) := (others => '0');
type t_fsm_cic_sync_state is (IDLE, CHECK_SYNC, START_SYNC, SYNCHING);
signal fsm_cic_sync_current_state : t_fsm_cic_sync_state := IDLE;
signal data_mask_en_d0 : std_logic := '0';
signal data_mask_beg_idx : unsigned(g_data_mask_width-1 downto 0) :=
to_unsigned(0, g_data_mask_width);
signal data_mask_end_idx : unsigned(g_data_mask_width-1 downto 0) :=
to_unsigned(0, g_data_mask_width);
signal data_mask_counter : unsigned(g_data_mask_width-1 downto 0) :=
to_unsigned(0, g_data_mask_width);
signal valid_d0 : std_logic := '0';
signal data_d0 : std_logic_vector(g_input_width-1 downto 0) := (others => '0');
signal data_tag_input : std_logic_vector(g_tag_width-1 downto 0) := (others => '0');
signal data_tag_d0 : std_logic_vector(g_tag_width-1 downto 0) := (others => '0');
signal data_tag_d1 : std_logic_vector(g_tag_width-1 downto 0) := (others => '0');
signal rst_modules : std_logic := '0';
signal rst_int : std_logic := '0';
signal rst_n_int : std_logic := '0';
signal data_tag_change : std_logic := '0';
signal data_tag_change_d0 : std_logic := '0';
component decimation_strober
generic (
g_maxrate : natural := 2048;
g_bus_width : natural := 11);
port (
clk_i : in std_logic;
rst_i : in std_logic;
ce_i : in std_logic;
valid_i : in std_logic;
ratio_i : in std_logic_vector(g_bus_width-1 downto 0);
strobe_o : out std_logic);
end component;
begin -- architecture str
-- We don't need CE here as these are user configurable registers. We will have
-- lots of clock cycles anyway
p_data_mask_limits : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
data_mask_beg_idx <= (others => '0');
data_mask_end_idx <= (others => '0');
else
-- Set beginning counter index
data_mask_beg_idx <= data_mask_num_samples_beg_i;
if data_mask_num_samples_beg_i > g_max_rate then
data_mask_beg_idx <= to_unsigned(g_max_rate, data_mask_beg_idx'length);
end if;
-- Set ending counter index
data_mask_end_idx <= g_max_rate - data_mask_num_samples_end_i;
if data_mask_num_samples_end_i > g_max_rate then
data_mask_end_idx <= to_unsigned(0, data_mask_end_idx'length);
end if;
end if;
end if;
end process;
-- Data masking logic
p_data_mask : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
data_mask_counter <= (others => '0');
valid_d0 <= '0';
data_d0 <= (others => '0');
data_mask_en_d0 <= '0';
else
if ce_i = '1' then
if valid_i = '1' then
data_mask_counter <= data_mask_counter + 1;
-- decimation_strobe always happens at g_max_rate clock
-- cycles
if decimation_strobe = '1' then
data_mask_counter <= (others => '0');
data_mask_en_d0 <= data_mask_en_i;
end if;
if data_mask_en_d0 = '1' and
(data_mask_counter < data_mask_beg_idx or
data_mask_counter >= data_mask_end_idx) then
data_d0 <= (others => '0');
else
data_d0 <= data_i;
end if;
end if;
-- We take one clock cycle to detect a transition and act on it.
-- so, delay everyone by this same amount
valid_d0 <= valid_i;
decimation_strobe_d0 <= decimation_strobe;
end if;
end if;
end if;
end process;
data_tag_change <= '1' when data_tag_i /= data_tag_d0 else '0';
data_tag_change_d0 <= '1' when data_tag_d0 /= data_tag_d1 else '0';
p_sync_cic_fsm : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
fsm_cic_sync_current_state <= IDLE;
rst_modules <= '0';
desync_cnt <= (others => '0');
data_tag_d0 <= (others => '0');
data_tag_d1 <= (others => '0');
else
if ce_i = '1' then
data_tag_d0 <= data_tag_i;
-- To check for a transition we need another clock cycle. So, use a
-- delayed version of data_tag
data_tag_d1 <= data_tag_d0;
-- Desync clear
if data_tag_desync_cnt_rst_i = '1' then
desync_cnt <= (others => '0');
end if;
-- FSM transitions
case fsm_cic_sync_current_state is
when IDLE =>
-- passthrough
rst_modules <= '0';
-- CIC synchronization is disabled
if data_tag_en_i = '0' then
fsm_cic_sync_current_state <= IDLE;
else
fsm_cic_sync_current_state <= CHECK_SYNC;
end if;
when CHECK_SYNC =>
if data_tag_en_i = '0' then
fsm_cic_sync_current_state <= IDLE;
else
-- when we decimate the CIC, check if the next sample
-- belongs to the next tag. This means that the CIC decimation
-- cycle is synched with the tag
if decimation_strobe = '1' then
-- tag transition
if data_tag_change_d0 = '1' then
-- CIC is synched with tag
fsm_cic_sync_current_state <= CHECK_SYNC;
else
fsm_cic_sync_current_state <= START_SYNC;
end if;
end if;
end if;
when START_SYNC =>
if data_tag_en_i = '0' then
fsm_cic_sync_current_state <= IDLE;
else
rst_modules <= '1';
fsm_cic_sync_current_state <= SYNCHING;
-- count desync occurence
desync_cnt <= desync_cnt + 1;
end if;
when SYNCHING =>
if data_tag_en_i = '0' then
fsm_cic_sync_current_state <= IDLE;
else
-- tag transition
if data_tag_change = '1' then
rst_modules <= '0';
fsm_cic_sync_current_state <= CHECK_SYNC;
end if;
end if;
when others =>
fsm_cic_sync_current_state <= IDLE;
end case;
end if;
end if;
end if;
end process;
data_tag_desync_cnt_o <= std_logic_vector(desync_cnt);
rst_int <= rst_i or rst_modules;
cmp_decimation_strober : decimation_strober
generic map (
g_maxrate => g_max_rate,
g_bus_width => g_bus_width)
port map (
clk_i => clk_i,
rst_i => rst_int,
ce_i => ce_i,
valid_i => valid_d0,
ratio_i => ratio_i,
strobe_o => decimation_strobe);
cmp_cic_decim : cic_decim
generic map (
DATAIN_WIDTH => g_input_width,
DATAOUT_WIDTH => g_output_width,
M => g_delay,
N => g_stages,
MAXRATE => g_max_rate,
BITGROWTH => integer(ceil(real(g_stages)*log2(real(g_delay)*real(g_max_rate)))),
ROUND_CONVERGENT => g_round_convergent)
port map (
clk_i => clk_i,
rst_i => rst_int,
en_i => ce_i,
data_i => data_d0,
data_o => data_out,
act_i => valid_d0,
act_out_i => decimation_strobe_d0,
val_o => valid_out);
gen_with_ce_sync : if g_with_ce_synch generate
cmp_ce_synch : ce_synch
generic map (
g_data_width => g_output_width)
port map (
clk_i => clk_i,
rst_i => rst_i,
ce_in_i => ce_i,
data_i => data_out,
valid_i => valid_out,
ce_out_i => ce_out_i,
data_o => data_o,
valid_o => valid_o);
end generate;
gen_without_ce_sync : if not(g_with_ce_synch) generate
data_o <= data_out;
valid_o <=valid_out;
end generate;
end architecture str;
-------------------------------------------------------------------------------
| lgpl-3.0 | 7b612fbdeec3cb12e2ea23915820c412 | 0.469051 | 3.66545 | false | false | false | false |
bruskajp/EE-316 | Project4/Vivado_NexysBoard/craddockEE316/craddockEE316.srcs/sources_1/imports/testFolder/pwm.vhd | 1 | 7,744 | --------------------------------------------------------------------------------
--
-- FileName: pwm.vhd
-- Dependencies: none
-- Design Software: Quartus II 64-bit Version 12.1 Build 177 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 8/1/2013 Scott Larson
-- Initial Public Release
-- Version 2.0 1/9/2015 Scott Larson
-- Transistion between duty cycles always starts at center of pulse to avoid
-- anomalies in pulse shapes
--
--------------------------------------------------------------------------------
-- PWM code taken from IEEE wiki - https://eewiki.net/pages/viewpage.action?pageId=20939345#PWMGenerator(VHDL)-CodeDownload
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY pwm IS
GENERIC(
sys_clk : INTEGER := 100_000_000; --system clock frequency in Hz
pwm_freq : INTEGER := 500_000; --PWM switching frequency in Hz
bits_resolution : INTEGER := 64; --bits of resolution setting the duty cycle
phases : INTEGER := 1); --number of output pwms and phases
PORT(
clk : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --asynchronous reset
ena : IN STD_LOGIC; --latches in new duty cycle
duty : IN STD_LOGIC_VECTOR(bits_resolution-1 DOWNTO 0); --duty cycle
pwm_out : OUT STD_LOGIC_VECTOR(phases-1 DOWNTO 0); --pwm outputs
pwm_n_out : OUT STD_LOGIC_VECTOR(phases-1 DOWNTO 0)); --pwm inverse outputs
END pwm;
ARCHITECTURE logic OF pwm IS
CONSTANT period : INTEGER := sys_clk/pwm_freq; --number of clocks in one pwm period
TYPE counters IS ARRAY (0 TO phases-1) OF INTEGER RANGE 0 TO period - 1; --data type for array of period counters
SIGNAL count : counters := (OTHERS => 0); --array of period counters
SIGNAL half_duty_new : INTEGER RANGE 0 TO period/2 := 0; --number of clocks in 1/2 duty cycle
TYPE half_duties IS ARRAY (0 TO phases-1) OF INTEGER RANGE 0 TO period/2; --data type for array of half duty values
SIGNAL half_duty : half_duties := (OTHERS => 0); --array of half duty values (for each phase)
BEGIN
PROCESS(clk, reset_n)
BEGIN
IF(reset_n = '0') THEN --asynchronous reset
count <= (OTHERS => 0); --clear counter
pwm_out <= (OTHERS => '0'); --clear pwm outputs
pwm_n_out <= (OTHERS => '0'); --clear pwm inverse outputs
ELSIF((clk'EVENT AND clk = '1')) THEN --rising system clock edge
IF(ena = '1') THEN --latch in new duty cycle
half_duty_new <= conv_integer(duty)*period/(2**bits_resolution)/2; --determine clocks in 1/2 duty cycle
END IF;
FOR i IN 0 to phases-1 LOOP --create a counter for each phase
IF(count(0) = period - 1 - i*period/phases) THEN --end of period reached
count(i) <= 0; --reset counter
half_duty(i) <= half_duty_new; --set most recent duty cycle value
ELSE --end of period not reached
count(i) <= count(i) + 1; --increment counter
END IF;
END LOOP;
FOR i IN 0 to phases-1 LOOP --control outputs for each phase
IF(count(i) = half_duty(i)) THEN --phase's falling edge reached
pwm_out(i) <= '0'; --deassert the pwm output
pwm_n_out(i) <= '1'; --assert the pwm inverse output
ELSIF(count(i) = period - half_duty(i)) THEN --phase's rising edge reached
pwm_out(i) <= '1'; --assert the pwm output
pwm_n_out(i) <= '0'; --deassert the pwm inverse output
END IF;
END LOOP;
END IF;
END PROCESS;
END logic;
--library ieee;
--use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
--entity pwm_prog is
--generic(
-- N : integer := 8); -- number of bit of PWM counter
--port (
-- i_clk : in std_logic;
-- i_rstb : in std_logic;
-- i_sync_reset : in std_logic;
-- i_pwm_module : in std_logic_vector(N-1 downto 0); -- PWM Freq = clock freq/ (i_pwm_module+1); max value = 2^N-1
-- i_pwm_width : in std_logic_vector(N-1 downto 0); -- PWM width = (others=>0)=> OFF; i_pwm_module => MAX ON
-- o_pwm : out std_logic);
--end pwm_prog;
--architecture rtl of pwm_prog is
--signal r_max_count : unsigned(N-1 downto 0);
--signal r_pwm_counter : unsigned(N-1 downto 0);
--signal r_pwm_width : unsigned(N-1 downto 0);
--signal w_tc_pwm_counter : std_logic;
--begin
--w_tc_pwm_counter <= '0' when(r_pwm_counter<r_max_count) else '1'; -- use to strobe new word
----------------------------------------------------------------------
--p_state_out : process(i_clk,i_rstb)
--begin
-- if(i_rstb='0') then
-- r_max_count <= (others=>'0');
-- r_pwm_width <= (others=>'0');
-- r_pwm_counter <= (others=>'0');
-- o_pwm <= '0';
-- elsif(rising_edge(i_clk)) then
-- r_max_count <= unsigned(i_pwm_module);
-- if(i_sync_reset='1') then
-- r_pwm_width <= unsigned(i_pwm_width);
-- r_pwm_counter <= to_unsigned(0,N);
-- o_pwm <= '0';
-- else
-- if(r_pwm_counter=0) and (r_pwm_width/=r_max_count) then
-- o_pwm <= '0';
-- elsif(r_pwm_counter<=r_pwm_width) then
-- o_pwm <= '1';
-- else
-- o_pwm <= '0';
-- end if;
-- if(w_tc_pwm_counter='1') then
-- r_pwm_width <= unsigned(i_pwm_width);
-- end if;
-- if(r_pwm_counter=r_max_count) then
-- r_pwm_counter <= to_unsigned(0,N);
-- else
-- r_pwm_counter <= r_pwm_counter + 1;
-- end if;
-- end if;
-- end if;
--end process p_state_out;
--end rtl; | gpl-3.0 | 568acbc0e5bf1d54dcc57f7a087e6c2e | 0.472237 | 3.953037 | false | false | false | false |
SoCdesign/EHA | RTL/Hand_Shaking/Hand_Shaking_FC/LBDR.vhd | 3 | 3,137 | --Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic
);
end LBDR;
architecture behavior of LBDR is
signal Cx: std_logic_vector(3 downto 0);
signal Rxy: std_logic_vector(7 downto 0);
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal N1, E1, W1, S1 :std_logic :='0';
signal Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: std_logic;
signal Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: std_logic;
begin
Cx <= std_logic_vector(to_unsigned(Cx_rst, Cx'length));
Rxy <= std_logic_vector(to_unsigned(Rxy_rst, Rxy'length));
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
N1 <= '1' when dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) else '0';
E1 <= '1' when cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) else '0';
W1 <= '1' when dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) else '0';
S1 <= '1' when cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) else '0';
process(clk, reset)
begin
if reset = '0' then
Req_N_FF <= '0';
Req_E_FF <= '0';
Req_W_FF <= '0';
Req_S_FF <= '0';
Req_L_FF <= '0';
elsif clk'event and clk = '1' then
Req_N_FF <= Req_N_in;
Req_E_FF <= Req_E_in;
Req_W_FF <= Req_W_in;
Req_S_FF <= Req_S_in;
Req_L_FF <= Req_L_in;
end if;
end process;
-- The combionational part
Req_N <= Req_N_FF;
Req_E <= Req_E_FF;
Req_W <= Req_W_FF;
Req_S <= Req_S_FF;
Req_L <= Req_L_FF;
process(N1, E1, W1, S1, Rxy, Cx, flit_type, empty, Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF) begin
if flit_type = "001" and empty = '0' then
Req_N_in <= ((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0);
Req_E_in <= ((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1);
Req_W_in <= ((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2);
Req_S_in <= ((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3);
Req_L_in <= not N1 and not E1 and not W1 and not S1;
elsif flit_type = "100" then
Req_N_in <= '0';
Req_E_in <= '0';
Req_W_in <= '0';
Req_S_in <= '0';
Req_L_in <= '0';
else
Req_N_in <= Req_N_FF;
Req_E_in <= Req_E_FF;
Req_W_in <= Req_W_FF;
Req_S_in <= Req_S_FF;
Req_L_in <= Req_L_FF;
end if;
end process;
END; | gpl-3.0 | a49e4dac9d1c7850ac4529fe1311a858 | 0.570928 | 2.487708 | false | false | false | false |
bruskajp/EE-316 | Project5/game_logic_3.vhd | 1 | 21,733 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04/05/2017 02:01:44 PM
-- Design Name:
-- Module Name: game_logic - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity game_logic is
port(
clk : in STD_LOGIC;
usb_bt_clk : in STD_LOGIC;
save_button_input : in STD_LOGIC;
keyboard_input : in STD_LOGIC_VECTOR(7 downto 0);
x_pos_input : in STD_LOGIC_VECTOR(7 downto 0);
y_pos_input : in STD_LOGIC_VECTOR(7 downto 0);
usb_bt_input : in STD_LOGIC_VECTOR(7 downto 0);
reset_output : out STD_LOGIC;
screen_size_output : out STD_LOGIC;
pen_width_output : out STD_LOGIC_VECTOR(2 downto 0);
x_pos_output : out STD_LOGIC_VECTOR(7 downto 0);
y_pos_output : out STD_LOGIC_VECTOR(7 downto 0);
tricolor_led_output : out STD_LOGIC_VECTOR(11 downto 0);
usb_bt_output : out STD_LOGIC_VECTOR(15 downto 0);
color_output : out STD_LOGIC_VECTOR(23 downto 0);
ram_we_output : out STD_LOGIC_VECTOR(0 downto 0);
ram_val_output : out STD_LOGIC_VECTOR(11 downto 0);
ram_addr_output : out STD_LOGIC_VECTOR(16 downto 0)
);
end game_logic;
architecture Behavioral of game_logic is
-- Font ROM component
component font_rom is
port(
clk : in STD_LOGIC;
addr : in STD_LOGIC_VECTOR(10 downto 0);
data : out STD_LOGIC_VECTOR(7 downto 0)
);
end component;
-- RAM clock divider component
component clock_divider is
generic(count_max : INTEGER := 8); -- FIX THIS?
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
clk_output : out STD_LOGIC
);
end component;
-- System properties
signal pc_connected : STD_LOGIC := '0';
signal screen_size : STD_LOGIC := '0';
signal reset : STD_LOGIC := '0';
signal pen_width : STD_LOGIC_VECTOR(2 downto 0) := "000";
signal ascii_char : STD_LOGIC_VECTOR(7 downto 0) := x"00";
signal color : STD_LOGIC_VECTOR(23 downto 0) := x"000000";
--USB/bluetooth control send signals
signal prev_screen_size : STD_LOGIC := '0';
signal prev_save : STD_LOGIC := '0';
signal prev_reset : STD_LOGIC := '0';
signal prev_pen_width : STD_LOGIC_VECTOR(2 downto 0):= "000";
signal prev_ascii_char : STD_LOGIC_VECTOR(7 downto 0):= x"00";
signal prev_x_pos, prev_y_pos : STD_LOGIC_VECTOR(7 downto 0):= x"00";
signal prev_color : STD_LOGIC_VECTOR(23 downto 0):= x"000000";
--USB/Bluetooth control receive signals
signal prev_connections : STD_LOGIC_VECTOR(7 downto 0);
-- Keyboard control signals
signal num_values_input : INTEGER := 0;
signal prev_pc_connected : STD_LOGIC := '0';
signal changing_item : STD_LOGIC_VECTOR(2 downto 0) := "000"; -- [color, pen_width, screen_size]
signal hex_input : STD_LOGIC_VECTOR(3 downto 0) := x"0";
signal temp_hex_input : STD_LOGIC_VECTOR(7 downto 0) := x"00";
signal input_values : STD_LOGIC_VECTOR(23 downto 0) := x"000000";
-- Font Rom signals
signal font_rom_addr : UNSIGNED(10 downto 0) := x"00" & "000";
signal font_rom_data : STD_LOGIC_VECTOR(7 downto 0) := x"00";
-- RAM clock divider signals
signal ram_divider_counter : INTEGER := 0;
signal ram_clk : STD_LOGIC := '0';
-- RAM Signals
signal x_pos_int : INTEGER := 0;
signal y_pos_int : INTEGER := 0;
-- RAM fast update signals
signal ram_update_count : INTEGER := 0;
signal ram_update_x_count : INTEGER := 0;
signal ram_update_y_count : INTEGER := 0;
signal ram_update_slow_int : INTEGER := 0;
signal ram_update : STD_LOGIC_VECTOR(2 downto 0) := "000"; -- [pos, sys_text, user_text]
signal ram_update_slow : STD_LOGIC_VECTOR(2 downto 0) := "000";
signal ram_update_pos_slow : STD_LOGIC_VECTOR(7 downto 0) := x"00";
signal ram_update_sys_text_slow : STD_LOGIC_VECTOR(7 downto 0) := x"00";
signal ram_update_user_text_slow : STD_LOGIC_VECTOR(7 downto 0) := x"00";
-- RAM slow control signals
signal x_addr_count, y_addr_count : INTEGER := 0;
-- RAM reset signals
signal ram_reset : STD_LOGIC := '0';
signal ram_reset_slow : STD_LOGIC := '0';
signal ram_reset_count : UNSIGNED(15 downto 0) := x"0000";
signal prev_ram_resets : STD_LOGIC_VECTOR(7 downto 0) := x"00";
begin
screen_size_output <= screen_size;
pen_width_output <= pen_width;
x_pos_output <= x_pos_input;
y_pos_output <= y_pos_input;
tricolor_led_output <= color(11 downto 0);
color_output <= color;
ram_we_output <= "1";
--ram_we_output <= "0";
reset_output <= reset;
-- Previous signal generation process
process(clk)
begin
prev_pc_connected <= pc_connected;
prev_x_pos <= x_pos_input;
prev_y_pos <= y_pos_input;
prev_color <= color;
prev_ascii_char <= ascii_char;
prev_screen_size <= screen_size;
prev_pen_width <= pen_width;
prev_save <= save_button_input;
prev_reset <= reset;
end process;
-- USB/Bluetooth control process
process(clk, usb_bt_clk, prev_x_pos, prev_y_pos) -- FIX THIS (add update method)
begin
-- Sending Data
if rising_edge(clk) then
if reset /= prev_reset then
usb_bt_output(15 downto 12) <= "1111";
usb_bt_output(1) <= save_button_input;
usb_bt_output(0) <= reset;
elsif prev_x_pos /= x_pos_input then
usb_bt_output(15 downto 14) <= "10";
usb_bt_output(8) <= '0';
usb_bt_output(7 downto 0) <= x_pos_input;
elsif prev_y_pos /= y_pos_input then
usb_bt_output(15 downto 14) <= "10";
usb_bt_output(8) <= '1';
usb_bt_output(7 downto 0) <= y_pos_input;
elsif prev_color /= color then
usb_bt_output(15 downto 12) <= "1100";
usb_bt_output(11 downto 0) <= color(11 downto 0); -- change to 24 bit?
elsif prev_screen_size /= screen_size or prev_pen_width /= pen_width then
usb_bt_output(15 downto 12) <= "1110";
usb_bt_output(3) <= screen_size;
usb_bt_output(2 downto 0) <= pen_width;
elsif prev_ascii_char /= ascii_char then
usb_bt_output(15 downto 12) <= "1101";
usb_bt_output(7 downto 0) <= ascii_char;
elsif prev_save /= save_button_input then
usb_bt_output(15 downto 12) <= "1111";
usb_bt_output(1) <= save_button_input;
usb_bt_output(0) <= reset;
else
usb_bt_output <= x"0000";
end if;
end if;
-- Recieving Data
if rising_edge(usb_bt_clk) then
prev_connections <= prev_connections(6 downto 0) & usb_bt_input(0);
if prev_connections = x"00" then
pc_connected <= '0';
else
pc_connected <= '1';
end if;
end if;
end process;
-- Keyboard control process
hex_input <= temp_hex_input(3 downto 0);
process(clk)
begin
-- Keyboard control
if rising_edge(clk) then
if reset = '0' then
if keyboard_input = x"77" and changing_item = "000" then -- input w and changing color
ascii_char <= x"77";
changing_item <= "100";
num_values_input <= 1;
elsif keyboard_input = x"63" and changing_item = "000" then -- input c and changing pen_width
ascii_char <= x"63";
changing_item <= "010";
num_values_input <= 1;
elsif keyboard_input = x"73" and changing_item = "000" then -- input s and changing screen_size
ascii_char <= x"73";
changing_item <= "001";
num_values_input <= 1;
elsif keyboard_input = x"72" and changing_item = "000" then -- input r
reset <= '1';
color <= x"FFFFFF";
pen_width <= "000";
screen_size <= '0';
elsif keyboard_input = x"71" and changing_item /= "000" then -- input q and exit command
ascii_char <= x"71";
-- FIX THIS
elsif keyboard_input = x"08" and num_values_input = 1 then -- input backspace
ascii_char <= x"08";
num_values_input <= 0;
changing_item <= "000";
elsif changing_item /= "000" then
-- Ascii to hex converter
if (keyboard_input >= x"30" and keyboard_input <= x"39") then
temp_hex_input <= std_logic_vector(unsigned(keyboard_input) - x"30");
elsif (keyboard_input >= x"61" and keyboard_input <= x"66") then
temp_hex_input <= std_logic_vector(unsigned(keyboard_input) - x"57");
else
temp_hex_input <= x"FF";
end if;
-- User keyboard input restrictions
if changing_item = "100" and hex_input <= x"F" then -- Limit color
input_values(((num_values_input * 4)-1) downto ((num_values_input-1) * 4)) <= hex_input;
num_values_input <= num_values_input + 1;
elsif changing_item = "010" and hex_input >= x"1" and hex_input <= x"7" then -- Limit pen_width
input_values(3 downto 0) <= hex_input;
num_values_input <= num_values_input + 1;
elsif changing_item = "001" and hex_input <= x"1" then -- Limit screen_size
input_values(3 downto 0) <= hex_input;
num_values_input <= num_values_input + 1;
end if;
elsif keyboard_input = x"0A" then -- input enter
ascii_char <= x"0A";
if changing_item = "100" and num_values_input = 7 then -- new color
color <= input_values;
changing_item <= "000";
elsif changing_item = "010" and num_values_input = 1 then -- new pen_width
pen_width <= input_values(2 downto 0);
changing_item <= "000";
elsif changing_item = "001" and num_values_input = 1 then -- new screen_size
screen_size <= input_values(0);
changing_item <= "000";
end if;
end if;
end if;
-- Reset handling
if reset = '1' and prev_reset = '1' and ram_reset = '0' then
reset <= '0';
color <= x"000000";
end if;
end if;
end process;
-- Font ROM port map
ram_font_rom : font_rom
port map(
clk => clk,
addr => std_logic_vector(font_rom_addr),
data => font_rom_data
);
-- RAM clock divider port map
ram_clock_divider : clock_divider
generic map(count_max => 2) -- CHANGE VALUE
port map(
clk => clk,
reset => '0',
clk_output => ram_clk
);
x_pos_int <= to_integer(unsigned(x_pos_input));
y_pos_int <= to_integer(unsigned(y_pos_input));
-- RAM control process
process(clk, ram_clk)
begin
-- When to update RAM
if rising_edge(clk) then
-- ram_update_pos_slow <= ram_update_pos_slow(6 downto 0) & ram_update_slow(2);
-- ram_update_pos_slow <= ram_update_pos_slow(6 downto 0) & ram_update_slow(2);
-- ram_update_pos_slow <= ram_update_pos_slow(6 downto 0) & ram_update_slow(2);
if (x_pos_input /= prev_x_pos or y_pos_input /= prev_y_pos) then
ram_update(2) <= '1'; -- pos
ram_update_slow_int <= 1;
elsif ram_update_slow = std_logic_vector(to_unsigned(2048, 17)) then
ram_update(2) <= '0';
-- elsif (color /= prev_color or pen_width /= prev_pen_width
-- or pc_connected /= prev_pc_connected) then
-- ram_update(1) <= '1'; -- sys_text
-- elsif (ascii_char /= prev_ascii_char) then
-- ram_update(0) <= '1'; -- user_text
end if;
if ram_update_slow_int = std_logic_vector(to_unsigned(2048, 17)) then
ram_update_slow_int <= 0;
elsif ram_update_slow_int > 0 then
ram_update_slow_int <= ram_update_slow_int + 1;
end if;
-- if ram_update_pos_slow = x"00" then
-- ram_update(2) <= '0';
-- end if;
-- if ram_update_sys_text_slow = x"00" then
-- ram_update(1) <= '0';
-- end if;
-- if ram_update_user_text_slow = x"00" then
-- ram_update(0) <= '0';
-- end if;
-- if reset = '1' and ram_reset = '0' then
-- ram_reset <= '1';
-- prev_ram_resets <= prev_ram_resets(6 downto 0) & ram_reset;
-- end if;
--
-- if ram_reset_slow = '0' and prev_ram_resets = x"FF" then
-- ram_reset <= '0';
-- end if;
-- end if;
-- Draw to RAM
--if rising_edge(ram_clk) then
--if rising_edge(clk) then
--if ram_reset = '0' then
if ram_update(2) = '1' then -- pos
--if(true) then
--ram_we_output <= "1";
ram_val_output <= color(23 downto 20) & color(15 downto 12) & color(7 downto 4);
--ram_update_slow(2) <= '1';
--ram_update(2) <= '0';
-- if (y_addr_count < unsigned(pen_width)) and
-- ((y_pos_int + y_addr_count) < 256) and
-- ((y_pos_int + y_addr_count) >= 0) then
-- if (x_addr_count < unsigned(pen_width)) and
-- ((x_pos_int + x_addr_count) < 256) and
-- ((x_pos_int + x_addr_count) >= 0) then
ram_addr_output <= std_logic_vector(to_unsigned( ((x_pos_int+x_addr_count) + ((y_pos_int+y_addr_count) * 256)) , 17));
else
ram_val_output <= x"F00";
ram_addr_output <= std_logic_vector(to_unsigned(66666, 17));
--ram_update(2) <= '1';
-- else
-- x_addr_count <= 0;
-- end if;
-- y_addr_count <= y_addr_count + 1;
-- else
-- y_addr_count <= 0;
-- end if;
--elsif prev_x_pos /= x_pos_input and prev_y_pos /= y_pos_input then --Not needed?
--ram_update(1) <= '0';
--ram_we_output <= "0"; --Not needed?
--ram_update(2) <= '0'; --Not needed?
-- elsif ram_update(2 downto 1) = "01" then -- sys_text
-- ram_update_slow(2 downto 1) <= "01";
-- if ram_update_count < 3 then
-- if ram_update_y_count < 16 then
-- if ram_update_x_count < 8 then
-- if ram_update_count = 1 then -- Update color
-- ram_addr_output <= std_logic_vector(to_unsigned(65618 + ram_update_x_count
-- + (ram_update_y_count * 384), 17));
-- ram_val_output <= color(11 downto 0);
-- elsif ram_update_count = 2 then -- Update pen_width
-- ram_addr_output <= std_logic_vector(to_unsigned(65768 + ram_update_x_count
-- + (ram_update_y_count * 384), 17));
-- font_rom_addr <= "000" & (x"30" + unsigned("0000" & pen_width)); -- FIX THIS (concurency)
-- if font_rom_data(ram_update_x_count) = '1' then
-- ram_val_output <= x"000";
-- else
-- ram_val_output <= x"FFF";
-- end if;
-- else -- Update pc_connnection
-- ram_addr_output <= std_logic_vector(to_unsigned(65888 + ram_update_x_count
-- + (ram_update_count * 10)
-- + (ram_update_y_count * 384), 17));
-- font_rom_addr <= "00" & (x"30" + "0000000" & pc_connected); -- FIX THIS (concurency)
-- if font_rom_data(ram_update_x_count) = '1' then
-- ram_val_output <= x"000";
-- else
-- ram_val_output <= x"FFF";
-- end if;
-- end if;
-- ram_update_x_count <= ram_update_x_count + 1;
-- else
-- ram_update_x_count <= 0;
-- end if;
-- ram_update_y_count <= ram_update_x_count + 1;
-- else
-- ram_update_y_count <= 0;
-- end if;
-- ram_update_count <= ram_update_count + 1;
-- else
-- ram_update_slow(1) <= '0';
-- ram_update_count <= 0;
-- end if;
-- elsif ram_update = "001" then -- user_text
-- ram_update_slow <= "001";
-- if ram_update_count < 8 then
-- if ram_update_y_count < 16 then
-- if ram_update_x_count < 8 then
-- ram_addr_output <= std_logic_vector(to_unsigned(66102 + ram_update_x_count
-- + (ram_update_y_count * 384), 17));
-- font_rom_addr <= unsigned("000" & ascii_char); -- FIX THIS (concurency)
-- if font_rom_data(ram_update_x_count) = '1' then
-- ram_val_output <= x"000";
-- else
-- ram_val_output <= x"FFF";
-- end if;
-- ram_update_x_count <= ram_update_x_count + 1;
-- else
-- ram_update_x_count <= 0;
-- end if;
-- ram_update_y_count <= ram_update_x_count + 1;
-- else
-- ram_update_y_count <= 0;
-- end if;
-- ram_update_count <= ram_update_count + 1;
-- else
-- ram_update_slow(0) <= '0';
-- ram_update_count <= 0;
-- end if;
-- else
-- ram_update_slow <= "000";
--end if;
---- else -- ram_reset = 1
---- -- Drawing Screen (sys_text and user_text update automatically)
---- if ram_reset_count < 65536 then
---- ram_reset_slow <= '1';
---- ram_reset_count <= ram_reset_count + 1;
---- ram_addr_output <= "0" & std_logic_vector(ram_reset_count);
---- else
---- ram_reset_slow <= '0';
---- ram_reset_count <= x"0000";
---- end if;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 29377053ff472bbe9b3e8f907a9b258f | 0.44743 | 3.979674 | false | false | false | false |
lnls-dig/dsp-cores | hdl/modules/multiplier/generic_multiplier.vhd | 1 | 10,287 | -------------------------------------------------------------------------------
-- Title : Generic Multiplier
-- Project :
-------------------------------------------------------------------------------
-- File : generic_multiplier.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-02-25
-- Last update: 2015-10-15
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: A multiplier where each input and output widths are determined
-- by generics. The inputs may be both unsigned, one signed or both signed, and
-- the ouput always have only one sign bit + MSBs.
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-02-25 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
-------------------------------------------------------------------------------
entity generic_multiplier is
generic (
g_a_width : natural := 16; -- width for each input.
g_b_width : natural := 16;
g_signed : boolean := true; -- signed or unsigned multiplication? Signed
-- multiplication will have only one sign bit
-- at the output
g_tag_width : natural := 1; -- Input data tag width
g_p_width : natural := 16; -- width for output. Must be less than
-- g_a_width + g_b_width if unsigned,
-- g_a_width+g_b_width-1 if signed.
-- use round convergent or not
g_round_convergent : natural := 0;
g_levels : natural := 7); -- Just multiplier pipeline. Total
-- delay is levels +2
port (
a_i : in std_logic_vector(g_a_width-1 downto 0);
b_i : in std_logic_vector(g_b_width-1 downto 0);
valid_i : in std_logic;
tag_i : in std_logic_vector(g_tag_width-1 downto 0) := (others => '0');
p_o : out std_logic_vector(g_p_width-1 downto 0);
valid_o : out std_logic;
tag_o : out std_logic_vector(g_tag_width-1 downto 0);
ce_i : in std_logic;
clk_i : in std_logic;
rst_i : in std_logic);
attribute mult_style : string;
attribute mult_style of generic_multiplier : entity is "pipe_block";
end entity generic_multiplier;
-------------------------------------------------------------------------------
architecture behavioural of generic_multiplier is
constant c_product_width : natural := g_a_width + g_b_width;
constant c_product_extra_bits : natural := c_product_width - g_p_width;
constant c_zeros_extra_bits_m1 : std_logic_vector(c_product_extra_bits-2 downto 0) := (others => '0');
constant c_product_extra_bits_mid : std_logic_vector(c_product_extra_bits-1 downto 0) := '1' & c_zeros_extra_bits_m1;
constant c_zeros_extra_bits_m2 : std_logic_vector(c_product_extra_bits-3 downto 0) := (others => '0');
constant c_product_extra_bits_mid_m1 : std_logic_vector(c_product_extra_bits-2 downto 0) := '1' & c_zeros_extra_bits_m2;
type pipe is array(g_levels-1 downto 0) of std_logic_vector(c_product_width-1 downto 0);
type pipe_valid is array(g_levels-1 downto 0) of std_logic;
type pipe_tag is array(g_levels-1 downto 0) of std_logic_vector(g_tag_width-1 downto 0);
signal a : std_logic_vector(g_a_width-1 downto 0) := (others => '0');
signal b : std_logic_vector(g_b_width-1 downto 0) := (others => '0');
signal valid_in : std_logic := '0';
signal tag_in : std_logic_vector(g_tag_width-1 downto 0) := (others => '0');
signal product : pipe := (others => (others => '0'));
signal product_full : std_logic_vector(c_product_width-1 downto 0) := (others => '0');
signal valid : pipe_valid := (others => '0');
signal valid_full : std_logic := '0';
signal tag : pipe_tag := (others => (others => '0'));
signal tag_full : std_logic_vector(g_tag_width-1 downto 0) := (others => '0');
signal product_int : std_logic_vector(c_product_width-1 downto 0) := (others => '0');
signal product_out : std_logic_vector(g_p_width-1 downto 0) := (others => '0');
signal valid_int : std_logic := '0';
signal valid_out : std_logic := '0';
signal tag_int : std_logic_vector(g_tag_width-1 downto 0) := (others => '0');
signal tag_out : std_logic_vector(g_tag_width-1 downto 0) := (others => '0');
begin -- architecture str
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
-- Last stage of multiplication pipeline
product_full <= product(g_levels-1);
valid_full <= valid(g_levels-1);
tag_full <= tag(g_levels-1);
multiplication : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
product_int <= (others => '0');
valid_int <= '0';
tag_int <= (others => '0');
elsif ce_i = '1' then
-- Instantiate a register before multiplier to improve speed
a <= a_i;
b <= b_i;
valid_in <= valid_i;
tag_in <= tag_i;
-- If both are signed, there are two signals. Drop the redundancy.
if g_signed = true then
product(0) <= std_logic_vector(signed(a) * signed(b));
valid(0) <= valid_in;
tag(0) <= tag_in;
for n in 1 to g_levels-1 loop
product(n) <= product(n-1);
valid(n) <= valid(n-1);
tag(n) <= tag(n-1);
end loop;
if g_p_width < c_product_width then
product_int <= product_full;
-- Keep "valid_int" grouped with "product_int" so we don't forget to keep them synchronized
valid_int <= valid_full;
tag_int <= tag_full;
-- Output stage. Generate convergent rounding or not
if (g_round_convergent = 1) then
if (unsigned(product_int(c_product_extra_bits-1 -1 downto 0)) = unsigned(c_product_extra_bits_mid_m1)) then
product_out <= std_logic_vector(unsigned(product_int(c_product_width-2 downto c_product_extra_bits-1)) +
unsigned'("" & product_int(c_product_extra_bits-1)));
else
product_out <= std_logic_vector(unsigned(product_int(c_product_width-2 downto c_product_extra_bits-1)) +
unsigned'("" & product_int(c_product_extra_bits-1 -1)));
end if;
valid_out <= valid_int;
tag_out <= tag_int;
else
product_out <= product_int(c_product_width-2 downto c_product_extra_bits - 1);
-- Keep "valid_int" grouped with "product_int" so we don't forget to keep them synchronized
valid_out <= valid_int;
tag_out <= tag_int;
end if;
else
product_int <= std_logic_vector(resize(signed(product_full), g_p_width));
-- Keep "valid_int" grouped with "product_int" so we don't forget to keep them synchronized
valid_int <= valid_full;
tag_int <= tag_full;
-- Output stage
product_out <= product_int;
valid_out <= valid_int;
tag_out <= tag_int;
end if;
else
product(0) <= std_logic_vector(unsigned(a) * unsigned(b));
valid(0) <= valid_in;
tag(0) <= tag_in;
for n in 1 to g_levels-1 loop
product(n) <= product(n-1);
valid(n) <= valid(n-1);
tag(n) <= tag(n-1);
end loop;
if g_p_width < c_product_width then
product_int <= product_full(c_product_width-1 downto c_product_extra_bits);
-- Keep "valid_int" grouped with "product_int" so we don't forget to keep them synchronized
valid_int <= valid_full;
tag_int <= tag_full;
-- Output stage. Generate convergent rounding or not
if (g_round_convergent = 1) then
if (unsigned(product_int(c_product_extra_bits-1 downto 0)) = unsigned(c_product_extra_bits_mid)) then
product_out <= std_logic_vector(unsigned(product_int(c_product_width-1 downto c_product_extra_bits)) +
unsigned'("" & product_int(c_product_extra_bits)));
else
product_out <= std_logic_vector(unsigned(product_int(c_product_width-1 downto c_product_extra_bits)) +
unsigned'("" & product_int(c_product_extra_bits-1)));
end if;
valid_out <= valid_int;
tag_out <= tag_int;
else
product_out <= product_int(c_product_width-1 downto c_product_extra_bits);
valid_out <= valid_int;
tag_out <= tag_int;
end if;
else
product_int <= std_logic_vector(resize(signed(product_full), g_p_width));
-- Keep "valid_int" grouped with "product_int" so we don't forget to keep them synchronized
valid_int <= valid_full;
tag_int <= tag_full;
-- Output stage
product_out <= product_int;
valid_out <= valid_int;
tag_out <= tag_int;
end if;
end if;
end if; -- reset
end if; -- clk
end process multiplication;
p_o <= product_out;
valid_o <= valid_out;
tag_o <= tag_out;
end architecture behavioural;
-------------------------------------------------------------------------------
| lgpl-3.0 | 4e4af4637177b0853d153a57cd0d4c87 | 0.496063 | 3.920351 | false | false | false | false |
TUM-LIS/faultify | hardware/testcases/fpu100_mul/fpga_sim/xpsLibraryPath_asic_400_631/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/vhdl/user_logic.vhd | 1 | 29,249 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Fri May 16 15:25:24 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
faultify_clk_fast : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
component faultify_top
generic (
numInj : integer;
numIn : integer;
numOut : integer);
port (
aclk : in std_logic;
arst_n : in std_logic;
clk : in std_logic;
clk_x32 : in std_logic;
awvalid : in std_logic;
awaddr : in std_logic_vector(31 downto 0);
wvalid : in std_logic;
wdata : in std_logic_vector(31 downto 0);
arvalid : in std_logic;
araddr : in std_logic_vector(31 downto 0);
rvalid : out std_logic;
rdata : out std_logic_vector(31 downto 0));
end component;
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal register_write_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal register_read_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal register_write_address : std_logic_vector(C_NUM_REG-1 downto 0);
signal register_read_address : std_logic_vector(C_NUM_REG-1 downto 0);
signal slv_reg_write_sel : std_logic_vector(31 downto 0);
signal slv_reg_read_sel : std_logic_vector(31 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal faultify_read_valid : std_logic;
signal faultify_read_address_valid : std_logic;
signal faultify_read_address : std_logic_vector(31 downto 0);
signal faultify_write_valid : std_logic;
signal counter, divide : integer := 0;
signal faultify_clk_slow_i : std_logic;
begin
slv_reg_write_sel <= Bus2IP_WrCE(31 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(31 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12) or Bus2IP_WrCE(13) or Bus2IP_WrCE(14) or Bus2IP_WrCE(15) or Bus2IP_WrCE(16) or Bus2IP_WrCE(17) or Bus2IP_WrCE(18) or Bus2IP_WrCE(19) or Bus2IP_WrCE(20) or Bus2IP_WrCE(21) or Bus2IP_WrCE(22) or Bus2IP_WrCE(23) or Bus2IP_WrCE(24) or Bus2IP_WrCE(25) or Bus2IP_WrCE(26) or Bus2IP_WrCE(27) or Bus2IP_WrCE(28) or Bus2IP_WrCE(29) or Bus2IP_WrCE(30) or Bus2IP_WrCE(31);
slv_read_ack <= faultify_read_valid;
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process(Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
register_write_data <= (others => '0');
register_write_address <= (others => '0');
faultify_write_valid <= '0';
else
faultify_write_valid <= slv_write_ack;
case slv_reg_write_sel is
when "10000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(0, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "01000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(1, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00100000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(2, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00010000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(3, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00001000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(4, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000100000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(5, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000010000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(6, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000001000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(7, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000100000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(8, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000010000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(9, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000001000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(10, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000100000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(11, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000010000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(12, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000001000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(13, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000100000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(14, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000010000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(15, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000001000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(16, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000100000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(17, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000010000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(18, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000001000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(19, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000100000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(20, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000010000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(21, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000001000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(22, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000100000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(23, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000010000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(24, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000001000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(25, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(26, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(27, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(28, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(29, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(30, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(31, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process(slv_reg_read_sel, faultify_read_valid) is
begin
faultify_read_address_valid <= '1';
case slv_reg_read_sel is
when "10000000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(0, 32));
when "01000000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(1, 32));
when "00100000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(2, 32));
when "00010000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(3, 32));
when "00001000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(4, 32));
when "00000100000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(5, 32));
when "00000010000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(6, 32));
when "00000001000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(7, 32));
when "00000000100000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(8, 32));
when "00000000010000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(9, 32));
when "00000000001000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(10, 32));
when "00000000000100000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(11, 32));
when "00000000000010000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(12, 32));
when "00000000000001000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(13, 32));
when "00000000000000100000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(14, 32));
when "00000000000000010000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(15, 32));
when "00000000000000001000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(16, 32));
when "00000000000000000100000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(17, 32));
when "00000000000000000010000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(18, 32));
when "00000000000000000001000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(19, 32));
when "00000000000000000000100000000000" => faultify_read_address <= std_logic_vector(to_unsigned(20, 32));
when "00000000000000000000010000000000" => faultify_read_address <= std_logic_vector(to_unsigned(21, 32));
when "00000000000000000000001000000000" => faultify_read_address <= std_logic_vector(to_unsigned(22, 32));
when "00000000000000000000000100000000" => faultify_read_address <= std_logic_vector(to_unsigned(23, 32));
when "00000000000000000000000010000000" => faultify_read_address <= std_logic_vector(to_unsigned(24, 32));
when "00000000000000000000000001000000" => faultify_read_address <= std_logic_vector(to_unsigned(25, 32));
when "00000000000000000000000000100000" => faultify_read_address <= std_logic_vector(to_unsigned(26, 32));
when "00000000000000000000000000010000" => faultify_read_address <= std_logic_vector(to_unsigned(27, 32));
when "00000000000000000000000000001000" => faultify_read_address <= std_logic_vector(to_unsigned(28, 32));
when "00000000000000000000000000000100" => faultify_read_address <= std_logic_vector(to_unsigned(29, 32));
when "00000000000000000000000000000010" => faultify_read_address <= std_logic_vector(to_unsigned(30, 32));
when "00000000000000000000000000000001" => faultify_read_address <= std_logic_vector(to_unsigned(31, 32));
when others => faultify_read_address <= (others => '0');
faultify_read_address_valid <= '0';
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= register_read_data when faultify_read_valid = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
-----------------------------------------------------------------------------
-- clock divider 32 -> 1
-----------------------------------------------------------------------------
divide <= 32;
process(Bus2IP_Clk, Bus2IP_Resetn)
begin
if Bus2IP_Resetn = '0' then
counter <= 0;
faultify_clk_slow_i <= '0';
elsif(rising_edge(Bus2IP_Clk)) then
if(counter < divide/2-1) then
counter <= counter + 1;
faultify_clk_slow_i <= '0';
elsif(counter < divide-1) then
counter <= counter + 1;
faultify_clk_slow_i <= '1';
else
faultify_clk_slow_i <= '0';
counter <= 0;
end if;
end if;
end process;
faultify_top_1 : faultify_top
generic map (
numInj => 321, --631
numIn => 70,
numOut => 41)
port map (
aclk => Bus2IP_Clk,
arst_n => Bus2IP_Resetn,
clk => faultify_clk_slow_i,
clk_x32 => Bus2IP_Clk,
awvalid => faultify_write_valid,
awaddr => register_write_address,
wvalid => faultify_write_valid,
wdata => register_write_data,
arvalid => faultify_read_address_valid,
araddr => faultify_read_address,
rvalid => faultify_read_valid,
rdata => register_read_data);
end IMP;
| gpl-2.0 | e52a49b375781ff1fde05f0553895ef8 | 0.5393 | 4.022693 | false | false | false | false |
SoCdesign/EHA | RTL/Immortal_Chip/Arbiter_one_hot_with_checkers.vhd | 2 | 16,687 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Arbiter is
port ( reset: in std_logic;
clk: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules
DCTS: in std_logic; -- Getting the CTS signal from the input FIFO of the next router/NI (for hand-shaking)
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
Xbar_sel : out std_logic_vector(4 downto 0); -- select lines for XBAR
RTS: out std_logic; -- Valid output which is sent to the next router/NI to specify that the data on the output port is valid
-- Checker outputs
err_state_IDLE_xbar,
err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE,
err_IDLE_Req_L,
err_Local_Req_L,
err_North_Req_N,
--err_East_Req_E,
--err_West_Req_W,
--err_South_Req_S,
err_IDLE_Req_N,
err_Local_Req_N,
--err_North_Req_E,
--err_East_Req_W,
--err_West_Req_S,
err_South_Req_L,
--err_IDLE_Req_E,
--err_Local_Req_E,
--err_North_Req_W,
--err_East_Req_S,
err_West_Req_L,
err_South_Req_N,
--err_IDLE_Req_W,
--err_Local_Req_W,
--err_North_Req_S,
err_East_Req_L,
err_West_Req_N,
--err_South_Req_E,
--err_IDLE_Req_S,
--err_Local_Req_S,
--err_North_Req_L,
err_East_Req_N,
--err_West_Req_E,
--err_South_Req_W,
err_next_state_onehot,
err_state_in_onehot,
--err_DCTS_RTS_FF_state_Grant_L,
--err_DCTS_RTS_FF_state_Grant_N,
--err_DCTS_RTS_FF_state_Grant_E,
--err_DCTS_RTS_FF_state_Grant_W,
--err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel,
err_state_east_xbar_sel,
err_state_west_xbar_sel,
err_state_south_xbar_sel : out std_logic
--err_state_local_xbar_sel : out std_logic
);
end;
architecture behavior of Arbiter is
-- next
-- Arbiter router or NI
-- ------------------------------------- ----
-- from LBDR ---> |Req(s) RTS | -----> |DRTS
-- To FIFO <--- |Grant(s) DCTS| <----- |CTS
-- to XBAR <--- |Xbar_sel | |
-- ------------------------------------- ----
--------------------------------------------------------------------------------------------
-- an example of a request/grant + handshake process with next router or NI
--CLK _|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|__
-- Req _____|'''''''''''''''''''''''''''''''''''''''''''|________
-- _________ ___________________ _______ _______ _______ ____
-- TX _________X_______HEADER______X_Body__X_Body__X__Tail_X____
-- Grant _________________________|'''|___|'''|___|'''|____________
-- RTs _________|'''''''''''''''''''|___|'''''''|___|'''''''|____
-- DCTS _________________________|'''|_______|'''|_______|'''|____
-- |<---------clear----------->|
-- | to send |
--------------------------------------------------------------------------------------------
-- TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SUBTYPE STATE_TYPE IS STD_LOGIC_VECTOR (5 downto 0);
CONSTANT IDLE: STATE_TYPE := "000001";
CONSTANT Local: STATE_TYPE := "000010";
CONSTANT North: STATE_TYPE := "000100";
CONSTANT East: STATE_TYPE := "001000";
CONSTANT West: STATE_TYPE := "010000";
CONSTANT South: STATE_TYPE := "100000";
SIGNAL state, state_in, next_state : STATE_TYPE := IDLE;
SIGNAL RTS_FF, RTS_FF_in: std_logic;
signal Grant_N_sig, Grant_E_sig, Grant_W_sig, Grant_S_sig, Grant_L_sig: std_logic;
signal Xbar_sel_sig: std_logic_vector(4 downto 0);
component Arbiter_checkers is
port (
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic;
DCTS: in std_logic;
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L: in std_logic;
Xbar_sel : in std_logic_vector(4 downto 0);
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
next_state_out: in std_logic_vector (5 downto 0);
RTS_FF: in std_logic;
RTS_FF_in: in std_logic;
-- Checker outputs
err_state_IDLE_xbar,
err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE,
err_IDLE_Req_L,
err_Local_Req_L,
err_North_Req_N,
--err_East_Req_E,
--err_West_Req_W,
--err_South_Req_S,
err_IDLE_Req_N,
err_Local_Req_N,
--err_North_Req_E,
--err_East_Req_W,
--err_West_Req_S,
err_South_Req_L,
--err_IDLE_Req_E,
--err_Local_Req_E,
--err_North_Req_W,
--err_East_Req_S,
err_West_Req_L,
err_South_Req_N,
--err_IDLE_Req_W,
--err_Local_Req_W,
--err_North_Req_S,
err_East_Req_L,
err_West_Req_N,
--err_South_Req_E,
--err_IDLE_Req_S,
--err_Local_Req_S,
--err_North_Req_L,
err_East_Req_N,
--err_West_Req_E,
--err_South_Req_W,
err_next_state_onehot,
err_state_in_onehot,
--err_DCTS_RTS_FF_state_Grant_L,
--err_DCTS_RTS_FF_state_Grant_N,
--err_DCTS_RTS_FF_state_Grant_E,
--err_DCTS_RTS_FF_state_Grant_W,
--err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel,
err_state_east_xbar_sel,
err_state_west_xbar_sel,
err_state_south_xbar_sel : out std_logic
--err_state_local_xbar_sel : out std_logic
);
end component;
begin
-- Arbiter checkers instantiation
ARBITERCHECKERS: Arbiter_checkers port map (
Req_N => Req_N,
Req_E => Req_E,
Req_W => Req_W,
Req_S => Req_S,
Req_L => Req_L,
DCTS => DCTS,
Grant_N => Grant_N_sig,
Grant_E => Grant_E_sig,
Grant_W => Grant_W_sig,
Grant_S => Grant_S_sig,
Grant_L => Grant_L_sig,
Xbar_sel=>Xbar_sel_sig,
state => state,
state_in => state_in,
next_state_out => next_state,
RTS_FF => RTS_FF,
RTS_FF_in => RTS_FF_in,
err_state_IDLE_xbar => err_state_IDLE_xbar,
err_state_not_IDLE_xbar => err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in => err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in => err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in => err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state => err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state => err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants => err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants => err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants => err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE => err_Requests_next_state_IDLE,
err_IDLE_Req_L => err_IDLE_Req_L,
err_Local_Req_L => err_Local_Req_L,
err_North_Req_N => err_North_Req_N,
err_IDLE_Req_N => err_IDLE_Req_N,
err_Local_Req_N => err_Local_Req_N,
err_South_Req_L => err_South_Req_L,
err_West_Req_L => err_West_Req_L,
err_South_Req_N => err_South_Req_N,
err_East_Req_L => err_East_Req_L,
err_West_Req_N => err_West_Req_N,
err_East_Req_N => err_East_Req_N,
err_next_state_onehot => err_next_state_onehot,
err_state_in_onehot => err_state_in_onehot,
err_state_north_xbar_sel => err_state_north_xbar_sel,
err_state_east_xbar_sel => err_state_east_xbar_sel,
err_state_west_xbar_sel => err_state_west_xbar_sel,
err_state_south_xbar_sel => err_state_south_xbar_sel
);
-- process for updating the state of arbiter's FSM, also setting RTS based on the state (if Grant is given or not)
process(clk, reset)begin
if reset = '0' then
state<=IDLE;
RTS_FF <= '0';
elsif clk'event and clk = '1' then
-- no grant given yet, it might be that there is no request to
-- arbiter or request is there, but the next router's/NI's FIFO is full
state <= state_in;
RTS_FF <= RTS_FF_in;
end if;
end process;
-- anything below here is pure combinational
RTS <= RTS_FF;
-- Becuase of checkers we did this!
Grant_N <= Grant_N_sig;
Grant_E <= Grant_E_sig;
Grant_W <= Grant_W_sig;
Grant_S <= Grant_S_sig;
Grant_L <= Grant_L_sig;
Xbar_sel <= Xbar_sel_sig;
process(RTS_FF, DCTS, state, next_state)begin
if RTS_FF = '1' and DCTS = '0' then
state_in <= state;
else
state_in <= next_state;
end if;
end process;
process(state, RTS_FF, DCTS)begin
if state = IDLE then
RTS_FF_in <= '0';
-- if there was a grant given to one of the inputs,
-- tell the next router/NI that the output data is valid
else
if RTS_FF = '1' and DCTS = '1' then
RTS_FF_in <= '0';
else
RTS_FF_in <= '1';
end if;
end if ;
end process;
-- sets the grants using round robin
-- the order is L --> N --> E --> W --> S and then back to L
process(state, Req_N, Req_E, Req_W, Req_S, Req_L, DCTS, RTS_FF)begin
Grant_N_sig <= '0';
Grant_E_sig <= '0';
Grant_W_sig <= '0';
Grant_S_sig <= '0';
Grant_L_sig <= '0';
Xbar_sel_sig <= "00000";
case(state) is
when IDLE =>
Xbar_sel_sig <= "00000";
If Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
else
next_state <= IDLE;
end if;
when North =>
Grant_N_sig <= DCTS and RTS_FF ;
Xbar_sel_sig <= "00001";
If Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
else
next_state <= IDLE;
end if;
when East =>
Grant_E_sig <= DCTS and RTS_FF;
Xbar_sel_sig <= "00010";
If Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
else
next_state <= IDLE;
end if;
when West =>
Grant_W_sig <= DCTS and RTS_FF;
Xbar_sel_sig <= "00100";
If Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
else
next_state <= IDLE;
end if;
when South =>
Grant_S_sig <= DCTS and RTS_FF;
Xbar_sel_sig <= "01000";
If Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
else
next_state <= IDLE;
end if;
when others => -- Local
Grant_L_sig <= DCTS and RTS_FF;
Xbar_sel_sig <= "10000";
If Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
else
next_state <= IDLE;
end if;
end case ;
end process;
end;
| gpl-3.0 | 1b251602774f96512d07cd5fa08237f1 | 0.416612 | 3.878894 | false | false | false | false |
JarrettR/FPGA-Cryptoparty | sdk/examples/usb-fpga-1.15y/ucecho/fpga/ucecho.vhd | 6 | 737 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out std_logic_vector(7 downto 0);
CS : in std_logic;
CLK : in std_logic
-- SCL : in std_logic;
-- SDA : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
pb <= std_logic_vector( pb_buf ) when CS = '1' else (others => 'Z');
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
end if;
end process dpUCECHO;
end RTL;
| gpl-3.0 | e5672d3b4cc516f620f5ad1fee165f6a | 0.552239 | 3.070833 | false | false | false | false |
TUM-LIS/faultify | hardware/testcases/viterbi/fpga_sim/xpsLibraryPath_viterbi_400_578/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/vhdl/faultify_simulator.vhd | 1 | 5,686 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity faultify_simulator is
generic (
numInj : integer := 56;
numIn : integer := 10;
numOut : integer := 10);
port (
clk : in std_logic;
clk_m : in std_logic;
circ_ce : in std_logic;
circ_rst : in std_logic;
test : out std_logic_vector(31 downto 0);
testvector : in std_logic_vector(numIn-1 downto 0);
resultvector_o : out std_logic_vector(numOut-1 downto 0);
resultvector_f : out std_logic_vector(numOut-1 downto 0);
seed_in_en : in std_logic;
seed_in : in std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
shift_en : in std_logic;
rst_n : in std_logic);
end faultify_simulator;
-- 866:0
architecture behav of faultify_simulator is
component faultify_binomial_gen
generic (
width : integer);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : out std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
prob_out_c : out std_logic;
shift_en : in std_logic;
data_out : out std_logic;
data_out_valid : out std_logic);
end component;
component circuit_under_test
port (
clk : in std_logic;
rst : in std_logic;
testvector : in std_logic_vector(numIn-1 downto 0);
resultvector : out std_logic_vector(numOut-1 downto 0);
injectionvector : in std_logic_vector(578-1 downto 0));
end component;
component golden_circuit
port (
clk : in std_logic;
rst : in std_logic;
testvector : in std_logic_vector(numIn-1 downto 0);
resultvector : out std_logic_vector(numOut-1 downto 0));
end component;
signal injectionvector : std_logic_vector(numInj-1 downto 0);
signal injectionvector_reg : std_logic_vector(numInj-1 downto 0);
signal injectionvector_reg_o : std_logic_vector(numInj-1 downto 0);
signal seed_chain : std_logic_vector(numInj downto 0);
signal prob_chain : std_logic_vector(numInj downto 0);
signal rst : std_logic;
signal clk_ce_m : std_logic;
signal testvector_reg : std_logic_vector(numIn-1 downto 0);
attribute syn_noprune : boolean;
attribute syn_noprune of circuit_under_test_inst : label is true;
attribute syn_noprune of golden_circuit_inst : label is true;
attribute xc_props : string;
attribute xc_props of circuit_under_test_inst : label is "KEEP_HIERARCHY=TRUE";
attribute xc_props of golden_circuit_inst : label is "KEEP_HIERARCHY=TRUE";
signal injectionvector_reg_cat : std_logic_vector(578-1 downto 0);
begin -- behav
rst <= not rst_n;
-----------------------------------------------------------------------------
-- debug...
-----------------------------------------------------------------------------
-- resultvector_f <= (others => '1');
-- resultvector_o <= (others => '1');
cgate : bufgce
port map (
I => clk_m,
O => clk_ce_m,
CE => '1');
process (clk_ce_m, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
testvector_reg <= (others => '0');
elsif clk_ce_m'event and clk_ce_m = '1' then -- rising clock edge
testvector_reg <= testvector;
end if;
end process;
circuit_under_test_inst : circuit_under_test
port map (
clk => clk_ce_m,
rst => circ_rst,
testvector => testvector_reg,
resultvector => resultvector_f,
injectionvector => injectionvector_reg_cat);
injectionvector_reg_cat(199 downto 0) <= (others => '0');
injectionvector_reg_cat(399 downto 200) <= (others => '0');
injectionvector_reg_cat(578-1 downto 400) <= injectionvector_reg;
golden_circuit_inst : golden_circuit
port map (
clk => clk_ce_m,
rst => circ_rst,
testvector => testvector_reg,
resultvector => resultvector_o
);
seed_chain(0) <= seed_in;
prob_chain(0) <= prob_in;
prsn_loop : for i in 0 to numInj-1 generate
prsn_top_1 : faultify_binomial_gen
generic map (
width => 32)
port map (
clk => clk,
rst_n => rst_n,
seed_in_en => seed_in_en,
seed_in => seed_chain(i),
seed_out_c => seed_chain(i+1),
prob_in_en => prob_in_en,
prob_in => prob_chain(i),
prob_out_c => prob_chain(i+1),
shift_en => shift_en,
data_out => injectionvector(i),
data_out_valid => open);
end generate prsn_loop;
reg : process (clk_ce_m, rst_n)
begin -- process reg
if rst_n = '0' then -- asynchronous reset (active low)
injectionvector_reg <= (others => '0');
--injectionvector_reg_o <= (others => '0');
--test <= (others => '0');
elsif clk_ce_m'event and clk_ce_m = '1' then -- rising clock edge
injectionvector_reg <= injectionvector;
--injectionvector_reg <= (others => '0');
--test <= injectionvector_reg_o(31 downto 0);
--injectionvector_reg_o(31 downto 0) <= injectionvector_reg_o(31 downto 0) or (resultvector_f(31 downto 0) xor resultvector_o(31 downto 0));
end if;
end process reg;
end behav;
| gpl-2.0 | 54b56a807a58b08fa2ffbe1fe0551eeb | 0.550651 | 3.642537 | false | true | false | false |
lnls-dig/dsp-cores | hdl/modules/cordic/cordic_vectoring_slv.vhd | 1 | 4,385 | -------------------------------------------------------------------------------
-- Title : Vectoring-mode cordic, slv version
-- Project :
-------------------------------------------------------------------------------
-- File : cordic_vectoring_slv.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-05-13
-- Last update: 2015-11-25
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: This is a top-block for vectoring mode using concordic,
-- constrained standard_logic_vector version.
-------------------------------------------------------------------------------
-- This file is part of Concordic.
--
-- Concordic is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Concordic is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- Copyright (c) 2014 Aylons Hazzud
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-05-13 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.dsp_cores_pkg.all;
-------------------------------------------------------------------------------
entity cordic_vectoring_slv is
generic (
g_stages : natural := 20;
g_width : natural := 32
);
port (
x_i : in std_logic_vector(g_width-1 downto 0) := (others => '0');
y_i : in std_logic_vector(g_width-1 downto 0) := (others => '0');
clk_i : in std_logic;
ce_i : in std_logic;
valid_i : in std_logic;
rst_i : in std_logic;
mag_o : out std_logic_vector(g_width-1 downto 0) := (others => '0');
phase_o : out std_logic_vector(g_width-1 downto 0) := (others => '0');
valid_o : out std_logic
);
end entity cordic_vectoring_slv;
-------------------------------------------------------------------------------
architecture str of cordic_vectoring_slv is
signal adjusted_x : signed(g_width-1 downto 0) := (others => '0');
signal adjusted_y : signed(g_width-1 downto 0) := (others => '0');
signal adjusted_z : signed(g_width-1 downto 0) := (others => '0');
signal mag_temp : signed(g_width-1 downto 0) := (others => '0');
signal phase_temp : signed(g_width-1 downto 0) := (others => '0');
signal y_temp : signed(g_width-1 downto 0) := (others => '0');
signal x_i_signed : signed(g_width-1 downto 0);
signal y_i_signed : signed(g_width-1 downto 0);
signal valid_temp : std_logic := '0';
begin -- architecture str
x_i_signed <= signed(x_i);
y_i_signed <= signed(y_i);
cmp_inversion : inversion_stage
generic map (
g_mode => "rect_to_polar")
port map (
x_i => x_i_signed,
y_i => y_i_signed,
z_i => (g_width-1 downto 0 => '0'),
clk_i => clk_i,
ce_i => ce_i,
rst_i => rst_i,
valid_i => valid_i,
x_o => adjusted_x,
y_o => adjusted_y,
z_o => adjusted_z,
valid_o => valid_temp);
cmp_core : cordic_core
generic map (
g_stages => g_stages,
g_mode => "rect_to_polar",
g_bit_growth => natural(ceil(log2(real(g_stages)))))
port map (
x_i => adjusted_x,
y_i => adjusted_y,
z_i => adjusted_z,
clk_i => clk_i,
ce_i => ce_i,
rst_i => rst_i,
valid_i => valid_temp,
x_o => mag_temp,
y_o => y_temp,
z_o => phase_temp,
valid_o => valid_o);
mag_o <= std_logic_vector(mag_temp);
phase_o <= std_logic_vector(phase_temp);
end architecture str;
-------------------------------------------------------------------------------
| lgpl-3.0 | a61fe48707fdbb57ccbc1e929e3bc331 | 0.492132 | 3.722411 | false | false | false | false |
lnls-dig/dsp-cores | hdl/testbench/daphine/daphine_tb.vhd | 1 | 7,797 | -------------------------------------------------------------------------------
-- Title : Daphine Testbench
-- Project :
-------------------------------------------------------------------------------
-- File : daphine_tb.vhd
-- Author : vfinotti
-- Company :
-- Created : 2015-07-01
-- Last update: 2015-07-01
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Tests daphine algorithm
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-07-01 1.0 vfinotti Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
use std.textio.all;
--use work.arith_dsp48e.all;
--use work.utilities.all;
-------------------------------------------------------------------------------
entity daphine_tb is
end entity daphine_tb;
-------------------------------------------------------------------------------
architecture str of daphine_tb is
constant c_input_freq : real := 120.0e6;
constant c_half_period : time := 1.0 sec / (2.0 * c_input_freq);
constant c_ce_period : natural := 2; -- in number of clock cycles
constant c_valid_period : natural := 100; -- in number of ce cycles
constant c_output_file : string := "./delta_sigma.samples";
constant c_width : natural := 32;
constant c_k : real := 2.0**real(c_width-2);
constant c_k_width : natural := 24;
-- Signals
signal clock : std_logic := '0';
signal endoffile : bit := '0';
signal ce : std_logic := '0';
signal reset : std_logic := '0';
signal valid : std_logic := '0';
signal valid_out : std_logic := '0';
signal a, b, c, d : std_logic_vector(c_width-1 downto 0);
-- signal x_in, y_in, q_in, sum_in : real;
signal x_in, y_in : real;
-- signal x_out, y_out, q_out, sum_out : std_logic_vector(c_width-1 downto 0);
signal x_out, y_out, sum_ac_out,sum_db_out : std_logic_vector(c_width-1 downto 0);
constant c_kx : std_logic_vector(c_k_width-1 downto 0) := "011111111111111111111111";
constant c_ky : std_logic_vector(c_k_width-1 downto 0) := "011111111111111111111111";
-- constant c_ksum : std_logic_vector(c_k_width-1 downto 0) := "011111111111111111111111";
component daphine is
generic (
g_width : natural;
g_k_width : natural);
port (
a_i : in std_logic_vector(g_width-1 downto 0);
b_i : in std_logic_vector(g_width-1 downto 0);
c_i : in std_logic_vector(g_width-1 downto 0);
d_i : in std_logic_vector(g_width-1 downto 0);
kx_i : in std_logic_vector(g_k_width-1 downto 0);
ky_i : in std_logic_vector(g_k_width-1 downto 0);
-- ksum_i : in std_logic_vector(g_k_width-1 downto 0);
clk_i : in std_logic;
ce_i : in std_logic;
valid_i : in std_logic;
valid_o : out std_logic;
rst_i : in std_logic;
x_o : out std_logic_vector(g_width-1 downto 0);
y_o : out std_logic_vector(g_width-1 downto 0);
-- q_o : out std_logic_vector(g_width-1 downto 0);
-- sum_o : out std_logic_vector(g_width-1 downto 0));
sum_ac_o : out std_logic_vector(g_width-1 downto 0);
sum_db_o : out std_logic_vector(g_width-1 downto 0));
end component daphine;
begin -- architecture str
clk_gen : process
begin
clock <= '0';
wait for c_half_period;
clock <= '1';
wait for c_half_period;
end process;
rst_gen : process(clock)
constant clocks_to_reset : natural := 1;
variable reset_count : natural := 0;
begin
if rising_edge(clock) then
if reset_count = 0 then
reset <= '1';
reset_count := reset_count + 1;
elsif reset_count = clocks_to_reset then
reset <= '0';
else
reset_count := reset_count +1;
end if;
end if;
end process;
ce_gen : process(clock)
variable ce_count : natural := 0;
begin
if rising_edge(clock) then
ce_count := ce_count + 1;
if ce_count = c_ce_period then
ce <= '1';
ce_count := 0;
else
ce <= '0';
end if;
end if;
end process;
valid_gen : process(clock)
variable valid_count : natural := 0;
begin
if rising_edge(clock) and ce = '1' then
valid_count := valid_count + 1;
if valid_count = c_valid_period then
valid <= '1';
valid_count := 0;
else
valid <= '0';
end if;
end if;
end process;
data_gen : process
variable x_temp, y_temp : real;
begin
wait until valid = '1';
for x_int in -999 to 999 loop --avoid extremes because the math is
--not defined for them
x_temp := real(x_int)/1000.0;
x_in <= x_temp;
for y_int in -99 to 99 loop
y_temp := real(y_int)/100.0;
y_in <= y_temp;
a <= std_logic_vector(to_signed(integer(
0.25*c_k*(-x_temp + y_temp + 1.0)),c_width));
b <= std_logic_vector(to_signed(integer(
0.25*c_k*(x_temp + y_temp + 1.0)),c_width));
c <= std_logic_vector(to_signed(integer(
0.25*c_k*(x_temp - y_temp + 1.0)),c_width));
d <= std_logic_vector(to_signed(integer(
0.25*c_k*(-x_temp - y_temp + 1.0)),c_width));
wait until valid = '1';
end loop;
end loop;
assert(false) report "end of input stream" severity failure;
end process;
output_check : process(clock)
file samples_file : text open write_mode is "daphine.samples";
variable cur_line : line;
-- variable x_diff, y_diff, sum_diff : real;
variable x_diff, y_diff : real;
begin
if rising_edge(clock) and ce = '1' and valid_out = '1' then
write(cur_line, x_in);
write(cur_line, ht);
write(cur_line, y_in);
write(cur_line, ht);
write(cur_line, to_integer(signed(x_out)));
write(cur_line, ht);
write(cur_line, to_integer(signed(y_out)));
write(cur_line, ht);
-- write(cur_line, to_integer(signed(q_out)));
-- write(cur_line, ht);
-- write(cur_line, to_integer(signed(sum_out)));
-- write(cur_line, ht);
writeline(samples_file, cur_line);
-- compare results directly
x_diff := real(to_integer(signed(x_out)))/2.0**31.0 - x_in;
y_diff := real(to_integer(signed(y_out)))/2.0**31.0 - y_in;
-- sum_diff := real(to_integer(signed(sum_out)))/2.0**31.0 - sum_in;
--assert x_diff < x_in/(10.0**5.0)
-- report "x difference too big"
-- severity failure;
end if;
end process;
uut : daphine
generic map (
g_width => c_width,
g_k_width => c_k_width)
port map (
a_i => a,
b_i => b,
c_i => c,
d_i => d,
kx_i => c_kx,
ky_i => c_ky,
-- ksum_i => c_ksum,
clk_i => clock,
rst_i => reset,
ce_i => ce,
valid_i => valid,
valid_o => valid_out,
x_o => x_out,
y_o => y_out,
-- q_o => q_out,
-- sum_o => sum_out);
sum_ac_o => sum_ac_out,
sum_db_o => sum_db_out);
end architecture str;
-------------------------------------------------------------------------------
| lgpl-3.0 | e02dbfc000cd37b5f41ba6abcabe8e86 | 0.487623 | 3.357881 | false | false | false | false |
TUM-LIS/faultify | hardware/testcases/viterbi/fpga_sim/xpsLibraryPath/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/vhdl/faultify_axi_wrapper.vhd | 14 | 17,300 | ------------------------------------------------------------------------------
-- faultify_axi_wrapper.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: faultify_axi_wrapper.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Fri May 16 15:25:24 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
use proc_common_v3_00_a.soft_reset;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library faultify_axi_wrapper_v1_00_a;
use faultify_axi_wrapper_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity faultify_axi_wrapper is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
faultify_clk_fast : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity faultify_axi_wrapper;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of faultify_axi_wrapper is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant RST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
constant RST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
constant USER_SLV_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & RST_BASEADDR, -- soft reset space base address
ZERO_ADDR_PAD & RST_HIGHADDR, -- soft reset space high address
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant RST_NUM_CE : integer := 1;
constant USER_SLV_NUM_REG : integer := 32;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG + RST_NUM_CE;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (RST_NUM_CE), -- number of ce for soft reset space
1 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Width of triggered reset in bus clocks
------------------------------------------
constant RESET_WIDTH : integer := 8;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant RST_CS_INDEX : integer := 0;
constant RST_CE_INDEX : integer := USER_NUM_REG;
constant USER_SLV_CS_INDEX : integer := 1;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_Bus2IP_Reset : std_logic;
signal rst_Bus2IP_Reset : std_logic;
signal rst_IP2Bus_WrAck : std_logic;
signal rst_IP2Bus_Error : std_logic;
signal rst_Bus2IP_Reset_tmp : std_logic;
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate soft_reset
------------------------------------------
SOFT_RESET_I : entity proc_common_v3_00_a.soft_reset
generic map
(
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_RESET_WIDTH => RESET_WIDTH
)
port map
(
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_WrCE => ipif_Bus2IP_WrCE(RST_CE_INDEX),
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Reset2IP_Reset => rst_Bus2IP_Reset,
Reset2Bus_WrAck => rst_IP2Bus_WrAck,
Reset2Bus_Error => rst_IP2Bus_Error,
Reset2Bus_ToutSup => open
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity faultify_axi_wrapper_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
faultify_clk_fast => faultify_clk_fast,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => rst_Bus2IP_Reset_tmp,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
IP2BUS_DATA_MUX_PROC : process(ipif_Bus2IP_CS, user_IP2Bus_Data) is
begin
case ipif_Bus2IP_CS (1 downto 0) is
when "01" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when "10" => ipif_IP2Bus_Data <= (others => '0');
when others => ipif_IP2Bus_Data <= (others => '0');
end case;
end process IP2BUS_DATA_MUX_PROC;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck or rst_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error or rst_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
ipif_Bus2IP_Reset <= not ipif_Bus2IP_Resetn;
rst_Bus2IP_Reset_tmp <= not rst_Bus2IP_Reset;
end IMP;
| gpl-2.0 | 7df10ac950e5d6393c0d7015d88bfc8e | 0.517746 | 3.735694 | false | false | false | false |
TUM-LIS/faultify | hardware/testcases/QR/fpga_sim/ml605_asic_400_599/faultify_top.vhd | 4 | 21,421 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.qr_pack.all;
entity faultify_top is
generic (
numInj : integer := 56;
numIn : integer := 10;
numOut : integer := 10);
port (
aclk : in std_logic; -- interface clock
arst_n : in std_logic; -- interface reset
clk : in std_logic; -- simulation clock (slow)
clk_x32 : in std_logic; -- prng clock (fast)
-- Write channel
awvalid : in std_logic;
awaddr : in std_logic_vector(31 downto 0);
wvalid : in std_logic;
wdata : in std_logic_vector(31 downto 0);
-- Read channel
arvalid : in std_logic;
araddr : in std_logic_vector(31 downto 0);
rvalid : out std_logic;
rdata : out std_logic_vector(31 downto 0)
);
attribute syn_hier : string;
attribute syn_hier of faultify_top : entity is "hard";
end faultify_top;
architecture behav of faultify_top is
component qr_wrapper_wrapper_stimuli
port (
clk : in std_logic;
rst_n : in std_logic;
reduced_matrix : out std_logic;
start : out std_logic;
request_out : out std_logic;
valid_out : in std_logic;
ready : in std_logic;
in_A_r : out std_logic_vector(N_G*WORD_WIDTH_G - 1 downto 0);
in_A_i : out std_logic_vector(N_G*WORD_WIDTH_G - 1 downto 0));
end component;
component flag_cdc
port (
clkA : in std_logic;
clkB : in std_logic;
FlagIn_clkA : in std_logic;
FlagOut_clkB : out std_logic;
rst_n : in std_logic);
end component;
component faultify_simulator
generic (
numInj : integer;
numIn : integer;
numOut : integer);
port (
clk : in std_logic;
clk_m : in std_logic;
circ_ce : in std_logic;
circ_rst : in std_logic;
test : out std_logic_vector(31 downto 0);
testvector : in std_logic_vector(numIn-1 downto 0);
resultvector_o : out std_logic_vector(numOut-1 downto 0);
resultvector_f : out std_logic_vector(numOut-1 downto 0);
seed_in_en : in std_logic;
seed_in : in std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
shift_en : in std_logic;
rst_n : in std_logic);
end component;
component lfsr
generic (
width : integer;
seed : integer);
port (
clk : in std_logic;
rand_out : out std_logic_vector(width-1 downto 0));
end component;
type vector is array (0 to numOut-1) of std_logic_vector(31 downto 0);
signal errorSum : vector;
signal errorSumReg : vector;
signal errorSumReg_cdc_0 : vector;
signal errorSumReg_cdc_1 : vector;
signal errorVec : std_logic_vector(numOut-1 downto 0);
signal cnt : integer;
signal cnt_cdc_0 : integer;
signal cnt_cdc_1 : integer;
-- Asymmetric ram larger than 36 bit not supported in synplify I-2013
--type seed_ram_matr is array (0 to numInj-1) of std_logic_vector(63 downto 0);
--signal seed_ram : seed_ram_matr;
-- workaround 2 32-bit rams
type seed_ram_matr is array (0 to numInj-1) of std_logic_vector(31 downto 0);
signal seed_ram_low : seed_ram_matr;
signal seed_ram_high : seed_ram_matr;
--subtype seed_ram_matr_word_t is std_logic_vector(63 downto 0);
--type seed_ram_matr_memory_t is array (0 to numInj-1) of seed_ram_matr_word_t;
--signal seed_ram : seed_ram_matr_memory_t;
type prob_ram_matr is array (0 to numInj-1) of std_logic_vector(31 downto 0);
signal prob_ram : prob_ram_matr;
type reg_type is record
control : std_logic_vector(31 downto 0);
status : std_logic_vector(31 downto 0);
pe_location : std_logic_vector(31 downto 0);
pe_seed_low : std_logic_vector(31 downto 0);
pe_seed_high : std_logic_vector(31 downto 0);
pe_probability : std_logic_vector(31 downto 0);
output : std_logic_vector(31 downto 0);
ovalid : std_logic;
simtime : std_logic_vector(31 downto 0);
sel_soe : std_logic_vector(31 downto 0);
adr_soe : std_logic_vector(31 downto 0);
awaddr : std_logic_vector(31 downto 0);
test : std_logic_vector(31 downto 0);
circreset : std_logic_vector(31 downto 0);
cnt_tmp : std_logic_vector(31 downto 0);
sumoferrors : vector;
end record;
signal busy_loading : std_logic;
signal busy_simulating : std_logic;
signal busy_loading_reg : std_logic_vector(1 downto 0);
signal busy_simulating_reg : std_logic_vector(1 downto 0);
signal sim_done : std_logic;
signal r : reg_type;
type load_fsm_states is (IDLE, LOADSEED, LOADPROB);
signal l_state : load_fsm_states;
type sim_states is (IDLE, DELAY_Z, DELAY, SIMULATION, DELAY2, DELAY3, DELAY4, FREE_SIMULATION);
signal s_state : sim_states;
signal testvector : std_logic_vector(numIn-1 downto 0);
signal resultvector_o : std_logic_vector(numOut-1 downto 0);
signal resultvector_f : std_logic_vector(numOut-1 downto 0);
signal seed_in_en : std_logic;
signal seed_in : std_logic;
signal prob_in_en : std_logic;
signal prob_in : std_logic;
signal shift_en : std_logic;
signal shift_en_l : std_logic;
signal shift_en_s : std_logic;
signal load_seed_prob : std_logic;
signal start_simulation : std_logic;
signal start_free_simulation : std_logic;
signal stop_simulation : std_logic;
signal circ_ce, circ_rst, circ_rst_sim : std_logic;
signal tvec : std_logic_vector(127 downto 0);
signal test : std_logic_vector(31 downto 0);
signal rst_cdc, rst_cdc_n : std_logic;
begin -- behav
-----------------------------------------------------------------------------
-- PRNG shifting
-----------------------------------------------------------------------------
shift_en <= shift_en_l or shift_en_s;
-----------------------------------------------------------------------------
-- Testvector
-----------------------------------------------------------------------------
--testvector <= (others => '0');
--lfsr_1 : lfsr
-- generic map (
-- width => 128,
-- seed => 3498327)
-- port map (
-- clk => clk,
-- rand_out => tvec);
qr_wrapper_wrapper_stimuli_1: qr_wrapper_wrapper_stimuli
port map (
clk => clk,
rst_n => not circ_rst,
reduced_matrix => testvector(0),
start => testvector(1),
request_out => testvector(2),
valid_out => resultvector_o(0),
ready => resultvector_o(1),
in_A_r => testvector(50 downto 3),
in_A_i => testvector(98 downto 51));
testvector(110 downto 99) <= (others => '0');
--testvector <= tvec(numIn-1 downto 0);
-----------------------------------------------------------------------------
-- Simulator
-----------------------------------------------------------------------------
circ_rst <= circ_rst_sim when r.circreset(0) = '1' else '0';
faultify_simulator_1 : faultify_simulator
generic map (
numInj => numInj,
numIn => numIn,
numOut => numOut)
port map (
clk => clk_x32,
clk_m => clk,
circ_ce => circ_ce,
circ_rst => circ_rst,
test => test,
testvector => testvector,
resultvector_o => resultvector_o,
resultvector_f => resultvector_f,
seed_in_en => seed_in_en,
seed_in => seed_in,
prob_in_en => prob_in_en,
prob_in => prob_in,
shift_en => shift_en,
rst_n => arst_n);
-------------------------------------------------------------------------------
-- One Process Flow
-------------------------------------------------------------------------------
register_process : process (aclk, arst_n)
begin -- process register_process
if arst_n = '0' then -- asynchronous reset (active low)
r.control <= (others => '0');
r.status <= (others => '0');
r.pe_probability <= (others => '0');
r.pe_seed_high <= (others => '0');
r.pe_seed_low <= (others => '0');
r.pe_location <= (others => '0');
r.ovalid <= '0';
r.simtime <= (others => '0');
r.sel_soe <= (others => '0');
r.adr_soe <= (others => '0');
r.sumoferrors <= (others => (others => '0'));
r.output <= (others => '0');
elsif aclk'event and aclk = '1' then -- rising clock edge
r.control <= (others => '0');
if awvalid = '1' then
r.awaddr <= awaddr;
end if;
if wvalid = '1' then
if r.awaddr = x"00000000" then
r.control <= wdata;
elsif r.awaddr = x"00000001" then
r.pe_location <= wdata;
elsif r.awaddr = x"00000002" then
r.pe_seed_low <= wdata;
elsif r.awaddr = x"00000003" then
r.pe_seed_high <= wdata;
elsif r.awaddr = x"00000004" then
r.pe_probability <= wdata;
elsif r.awaddr = x"00000005" then
r.cnt_tmp <= std_logic_vector(to_unsigned(cnt_cdc_1, 32));
r.adr_soe <= wdata;
elsif r.awaddr = x"00000007" then
r.simtime <= wdata;
elsif r.awaddr = x"00000009" then
r.circreset <= wdata;
end if;
end if;
if arvalid = '1' then
if araddr = x"0000000F" then
r.output <= r.status;
elsif araddr = x"00000001" then
r.output <= r.pe_location;
elsif araddr = x"00000002" then
r.output <= r.pe_seed_low;
elsif araddr = x"00000003" then
r.output <= r.pe_seed_high;
elsif araddr = x"00000004" then
r.output <= r.pe_probability;
elsif araddr = x"00000006" then
r.output <= r.sel_soe;
elsif araddr = x"00000008" then
r.output <= r.test;
elsif araddr = x"0000000A" then
r.output <= r.cnt_tmp;
end if;
r.ovalid <= '1';
else
r.ovalid <= '0';
end if;
if busy_loading_reg(1) = '1' then
r.status(0) <= '1';
else
r.status(0) <= '0';
end if;
if busy_simulating_reg(1) = '1' then
r.status(1) <= '1';
else
r.status(1) <= '0';
end if;
r.sel_soe <= r.sumoferrors(to_integer(unsigned(r.adr_soe)));
rdata <= r.output;
rvalid <= r.ovalid;
r.sumoferrors <= errorSumReg_cdc_1;
r.test <= errorSum(0);
end if;
end process register_process;
-----------------------------------------------------------------------------
-- simple clock domain crossing
-----------------------------------------------------------------------------
process (aclk, arst_n)
begin -- process
if arst_n = '0' then -- asynchronous reset (active low)
busy_simulating_reg <= (others => '0');
busy_loading_reg <= (others => '0');
elsif aclk'event and aclk = '1' then -- rising clock edge
busy_simulating_reg(0) <= busy_simulating;
busy_loading_reg(0) <= busy_loading;
busy_simulating_reg(1) <= busy_simulating_reg(0);
busy_loading_reg(1) <= busy_loading_reg(0);
cnt_cdc_0 <= cnt;
cnt_cdc_1 <= cnt_cdc_0;
errorSumReg_cdc_0 <= errorSumReg;
errorSumReg_cdc_1 <= errorSumReg_cdc_0;
end if;
end process;
-------------------------------------------------------------------------------
-- Store seeed/prob
-------------------------------------------------------------------------------
store_seed : process (aclk, arst_n)
begin -- process store_seed
if arst_n = '0' then -- asynchronous reset (active low)
elsif aclk'event and aclk = '1' then -- rising clock edge
if r.control(0) = '1' then
-- Synplify bug workaround
--seed_ram(to_integer(unsigned(r.pe_location))) <= r.pe_seed_high & r.pe_seed_low;
seed_ram_low(to_integer(unsigned(r.pe_location))) <= r.pe_seed_low;
seed_ram_high(to_integer(unsigned(r.pe_location))) <= r.pe_seed_high;
prob_ram(to_integer(unsigned(r.pe_location))) <= r.pe_probability;
end if;
end if;
end process store_seed;
-----------------------------------------------------------------------------
-- Seed/prob loading FSM
-----------------------------------------------------------------------------
flag_cdc_1 : flag_cdc
port map (
clkA => aclk,
clkB => clk_x32,
FlagIn_clkA => r.control(1),
FlagOut_clkB => load_seed_prob,
rst_n => arst_n);
seed_prob_loading : process (clk_x32, arst_n)
variable cnt_seed : integer range 0 to 64;
variable cnt_inj : integer range 0 to numInj;
variable cnt_prob : integer range 0 to 32;
begin -- process seed_prob_loading
if arst_n = '0' then -- asynchronous reset (active low)
l_state <= IDLE;
seed_in <= '0';
seed_in_en <= '0';
prob_in <= '0';
prob_in_en <= '0';
shift_en_l <= '0';
busy_loading <= '0';
elsif clk_x32'event and clk_x32 = '1' then -- rising clock edge
case l_state is
when IDLE =>
cnt_seed := 0;
cnt_inj := 0;
cnt_prob := 0;
busy_loading <= '0';
seed_in_en <= '0';
prob_in_en <= '0';
shift_en_l <= '0';
if load_seed_prob = '1' then
busy_loading <= '1';
l_state <= LOADSEED;
end if;
when LOADSEED =>
if cnt_seed < 64 then
shift_en_l <= '1';
seed_in_en <= '1';
-- not working in synplify I-2013
--seed_in <= seed_ram(cnt_inj)(cnt_seed);
--
if cnt_seed < 32 then
seed_in <= seed_ram_low(cnt_inj)(cnt_seed);
else
seed_in <= seed_ram_high(cnt_inj)(cnt_seed-32);
end if;
cnt_seed := cnt_seed + 1;
end if;
if cnt_seed = 64 then
cnt_seed := 0;
cnt_inj := cnt_inj + 1;
end if;
if cnt_inj = numInj then
l_state <= LOADPROB;
--seed_in_en <= '0';
cnt_inj := 0;
end if;
when LOADPROB =>
seed_in_en <= '0';
if cnt_prob < 32 then
prob_in_en <= '1';
prob_in <= prob_ram(cnt_inj)(cnt_prob);
cnt_prob := cnt_prob + 1;
end if;
if cnt_prob = 32 then
cnt_prob := 0;
cnt_inj := cnt_inj + 1;
end if;
if cnt_inj = numInj then
l_state <= IDLE;
cnt_inj := 0;
--prob_in_en <= '0';
end if;
end case;
end if;
end process seed_prob_loading;
-----------------------------------------------------------------------------
-- Simulation FSM
-----------------------------------------------------------------------------
flag_cdc_2 : flag_cdc
port map (
clkA => aclk,
clkB => clk,
FlagIn_clkA => r.control(2),
FlagOut_clkB => start_simulation,
rst_n => arst_n);
flag_cdc_3 : flag_cdc
port map (
clkA => aclk,
clkB => clk,
FlagIn_clkA => r.control(3),
FlagOut_clkB => start_free_simulation,
rst_n => arst_n);
flag_cdc_4 : flag_cdc
port map (
clkA => aclk,
clkB => clk,
FlagIn_clkA => r.control(4),
FlagOut_clkB => stop_simulation,
rst_n => arst_n);
rst_cdc : flag_cdc
port map (
clkA => aclk,
clkB => clk,
FlagIn_clkA => not arst_n,
FlagOut_clkB => rst_cdc,
rst_n => open);
rst_cdc_n <= not rst_cdc;
process (clk, rst_cdc_n)
variable simtime : integer;
--variable cnt : integer;
variable cnt_delay : integer range 0 to 9;
begin -- process
if clk'event and clk = '1' then -- rising clock edge
--resultvector_f_reg <= resultvector_f;
--resultvector_o_reg <= resultvector_o;
if rst_cdc_n = '0' then -- asynchronous reset (active low)
s_state <= IDLE;
errorVec <= (others => '0');
errorSum <= (others => (others => '0'));
circ_ce <= '0';
circ_rst_sim <= '1';
shift_en_s <= '0';
busy_simulating <= '0';
sim_done <= '0';
errorSumReg <= (others => (others => '0'));
else
case s_state is
when IDLE =>
sim_done <= '0';
circ_ce <= '0';
circ_rst_sim <= '1';
shift_en_s <= '0';
errorVec <= (others => '0');
--errorSum <= errorSum;
errorSum <= (others => (others => '0'));
--cnt := 0;
busy_simulating <= '0';
cnt_delay := 0;
if start_simulation = '1' then
cnt <= 0;
busy_simulating <= '1';
errorSum <= (others => (others => '0'));
errorSumReg <= (others => (others => '0'));
simtime := to_integer(unsigned(r.simtime));
s_state <= DELAY_Z;
circ_ce <= '1';
circ_rst_sim <= '0';
shift_en_s <= '1';
end if;
if start_free_simulation = '1' then
cnt <= 0;
busy_simulating <= '1';
errorSum <= (others => (others => '0'));
errorSumReg <= (others => (others => '0'));
s_state <= FREE_SIMULATION;
circ_ce <= '1';
circ_rst_sim <= '0';
shift_en_s <= '1';
end if;
when DELAY_z =>
cnt_delay := cnt_delay + 1;
if cnt_delay = 9 then
s_state <= DELAY;
end if;
when DELAY =>
--circ_ce <= '1';
s_state <= SIMULATION;
errorVec <= (others => '0');
errorSum <= (others => (others => '0'));
when SIMULATION =>
--circ_ce <= '1';
circ_rst_sim <= '0';
shift_en_s <= '1';
-- collect errors
errorVec <= resultvector_o xor resultvector_f;
for i in 0 to (numOut-1) loop
if (errorVec(i) = '1') then
errorSum(i) <= std_logic_vector(unsigned(errorSum(i)) + 1);
end if;
end loop;
if cnt = simtime-1 then
s_state <= DELAY2;
--sim_done <= '1';
circ_ce <= '0';
circ_rst_sim <= '1';
shift_en_s <= '0';
end if;
cnt <= cnt +1;
when DELAY2 =>
errorVec <= resultvector_o xor resultvector_f;
for i in 0 to (numOut-1) loop
if (errorVec(i) = '1') then
errorSum(i) <= std_logic_vector(unsigned(errorSum(i)) + 1);
end if;
end loop;
s_state <= DELAY3;
when DELAY3 =>
--errorVec <= resultvector_o xor resultvector_f;
--for i in 0 to (numOut-1) loop
-- if (errorVec(i) = '1') then
-- errorSum(i) <= std_logic_vector(unsigned(errorSum(i)) + 1);
-- end if;
--end loop;
s_state <= DELAY4;
errorSumReg <= errorSum;
errorSum <= (others => (others => '0'));
when DELAY4 =>
--errorVec <= resultvector_o xor resultvector_f;
--for i in 0 to (numOut-1) loop
-- if (errorVec(i) = '1') then
-- errorSum(i) <= std_logic_vector(unsigned(errorSum(i)) + 1);
-- end if;
--end loop;
s_state <= IDLE;
sim_done <= '1';
--errorSumReg <= errorSum;
when FREE_SIMULATION =>
circ_rst_sim <= '0';
shift_en_s <= '1';
-- collect errors
errorVec <= resultvector_o xor resultvector_f;
for i in 0 to (numOut-1) loop
if (errorVec(i) = '1') then
errorSum(i) <= std_logic_vector(unsigned(errorSum(i)) + 1);
end if;
end loop;
--
errorSumReg <= errorSum;
if stop_simulation = '1' then
s_state <= IDLE;
sim_done <= '1';
circ_ce <= '0';
circ_rst_sim <= '1';
shift_en_s <= '0';
end if;
cnt <= cnt +1;
when others =>
s_state <= IDLE;
end case;
end if;
end if;
end process;
end behav; | gpl-2.0 | 4ee4dc351abb409ba9c306af5701baf6 | 0.463984 | 3.814281 | false | false | false | false |
SoCdesign/EHA | RTL/Credit_Based/Credit_Based_FC/SHMU.vhd | 1 | 8,540 | --Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity SHMU is
generic (
router_fault_info_width: integer := 5;
network_size: integer := 2
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet_N_0, healthy_packet_N_0, faulty_packet_E_0, healthy_packet_E_0, faulty_packet_W_0, healthy_packet_W_0, faulty_packet_S_0, healthy_packet_S_0, faulty_packet_L_0, healthy_packet_L_0: in std_logic;
faulty_packet_N_1, healthy_packet_N_1, faulty_packet_E_1, healthy_packet_E_1, faulty_packet_W_1, healthy_packet_W_1, faulty_packet_S_1, healthy_packet_S_1, faulty_packet_L_1, healthy_packet_L_1: in std_logic;
faulty_packet_N_2, healthy_packet_N_2, faulty_packet_E_2, healthy_packet_E_2, faulty_packet_W_2, healthy_packet_W_2, faulty_packet_S_2, healthy_packet_S_2, faulty_packet_L_2, healthy_packet_L_2: in std_logic;
faulty_packet_N_3, healthy_packet_N_3, faulty_packet_E_3, healthy_packet_E_3, faulty_packet_W_3, healthy_packet_W_3, faulty_packet_S_3, healthy_packet_S_3, faulty_packet_L_3, healthy_packet_L_3: in std_logic );
end SHMU;
architecture behavior of SHMU is
type SHM_type is array (0 to network_size*network_size-1) of std_logic_vector(router_fault_info_width-1 downto 0); --memory
signal SHM : SHM_type ;
signal Healthy_N_0, Healthy_E_0, Healthy_W_0, Healthy_S_0, Healthy_L_0: std_logic;
signal Healthy_N_1, Healthy_E_1, Healthy_W_1, Healthy_S_1, Healthy_L_1: std_logic;
signal Healthy_N_2, Healthy_E_2, Healthy_W_2, Healthy_S_2, Healthy_L_2: std_logic;
signal Healthy_N_3, Healthy_E_3, Healthy_W_3, Healthy_S_3, Healthy_L_3: std_logic;
signal Intermittent_N_0, Intermittent_E_0, Intermittent_W_0, Intermittent_S_0, Intermittent_L_0: std_logic;
signal Intermittent_N_1, Intermittent_E_1, Intermittent_W_1, Intermittent_S_1, Intermittent_L_1: std_logic;
signal Intermittent_N_2, Intermittent_E_2, Intermittent_W_2, Intermittent_S_2, Intermittent_L_2: std_logic;
signal Intermittent_N_3, Intermittent_E_3, Intermittent_W_3, Intermittent_S_3, Intermittent_L_3: std_logic;
signal Faulty_N_0, Faulty_E_0, Faulty_W_0, Faulty_S_0, Faulty_L_0: std_logic;
signal Faulty_N_1, Faulty_E_1, Faulty_W_1, Faulty_S_1, Faulty_L_1: std_logic;
signal Faulty_N_2, Faulty_E_2, Faulty_W_2, Faulty_S_2, Faulty_L_2: std_logic;
signal Faulty_N_3, Faulty_E_3, Faulty_W_3, Faulty_S_3, Faulty_L_3: std_logic;
component counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, Intermittent, Faulty:out std_logic
);
end component;
begin
-- these are the signals that do not actually exist because of the topology
Faulty_N_0 <= '0';
Faulty_W_0 <= '0';
Faulty_N_1 <= '0';
Faulty_E_1 <= '0';
Faulty_S_2 <= '0';
Faulty_W_2 <= '0';
Faulty_S_3 <= '0';
Faulty_E_3 <= '0';
CT_0_E: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map( reset => reset,
clk => clk,
faulty_packet => faulty_packet_E_0, Healthy_packet => healthy_packet_E_0,
Healthy => Healthy_E_0, Intermittent => Intermittent_E_0, Faulty => Faulty_E_0);
CT_0_S: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map( reset => reset,
clk => clk,
faulty_packet => faulty_packet_S_0, Healthy_packet => healthy_packet_S_0,
Healthy => Healthy_S_0, Intermittent => Intermittent_S_0, Faulty => Faulty_S_0);
CT_0_L: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map( reset => reset,
clk => clk,
faulty_packet => faulty_packet_L_0, Healthy_packet => healthy_packet_L_0,
Healthy => Healthy_L_0, Intermittent => Intermittent_L_0, Faulty => Faulty_L_0);
------------------------------------------------------------------------------------------------------------
CT_1_W: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_W_1, Healthy_packet => healthy_packet_W_1,
Healthy => Healthy_W_1, Intermittent => Intermittent_W_1, Faulty => Faulty_W_1);
CT_1_S: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_S_1, Healthy_packet => healthy_packet_S_1,
Healthy => Healthy_S_1, Intermittent => Intermittent_S_1, Faulty => Faulty_S_1);
CT_1_L: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_L_1, Healthy_packet => healthy_packet_L_1,
Healthy => Healthy_L_1, Intermittent => Intermittent_L_1, Faulty => Faulty_L_1);
------------------------------------------------------------------------------------------------------------
CT_2_N: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_N_2, Healthy_packet => healthy_packet_N_2,
Healthy => Healthy_N_2, Intermittent => Intermittent_N_2, Faulty => Faulty_N_2);
CT_2_E: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_E_2, Healthy_packet => healthy_packet_E_2,
Healthy => Healthy_E_2, Intermittent => Intermittent_E_2, Faulty => Faulty_E_2);
CT_2_L: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_L_2, Healthy_packet => healthy_packet_L_2,
Healthy => Healthy_L_2, Intermittent => Intermittent_L_2, Faulty => Faulty_L_2);
------------------------------------------------------------------------------------------------------------
CT_3_N: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_N_3, Healthy_packet => healthy_packet_N_3,
Healthy => Healthy_N_3, Intermittent => Intermittent_N_3, Faulty => Faulty_N_3);
CT_3_W: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_W_3, Healthy_packet => healthy_packet_W_3,
Healthy => Healthy_W_3, Intermittent => Intermittent_W_3, Faulty => Faulty_W_3);
CT_3_L: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_L_3, Healthy_packet => healthy_packet_L_3,
Healthy => Healthy_L_3, Intermittent => Intermittent_L_3, Faulty => Faulty_L_3);
process(clk, reset)begin
if reset = '0' then
SHM <= (others => (others => '0'));
elsif clk'event and clk = '1' then
SHM(0) <= Faulty_N_0 & Faulty_E_0 & Faulty_W_0 & Faulty_S_0 & Faulty_L_0;
SHM(1) <= Faulty_N_1 & Faulty_E_1 & Faulty_W_1 & Faulty_S_1 & Faulty_L_1;
SHM(2) <= Faulty_N_2 & Faulty_E_2 & Faulty_W_2 & Faulty_S_2 & Faulty_L_2;
SHM(3) <= Faulty_N_3 & Faulty_E_3 & Faulty_W_3 & Faulty_S_3 & Faulty_L_3;
end if;
end process;
END; | gpl-3.0 | d23e07416eebc6c90fe8022c49507eed | 0.617096 | 3.28841 | false | false | false | false |
SoCdesign/EHA | RTL/Hand_Shaking/Hand_Shaking_FC/Arbiter_one_hot.vhd | 1 | 7,624 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Arbiter is
port ( reset: in std_logic;
clk: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules
DCTS: in std_logic; -- Getting the CTS signal from the input FIFO of the next router/NI (for hand-shaking)
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
Xbar_sel : out std_logic_vector(4 downto 0); -- select lines for XBAR
RTS: out std_logic -- Valid output which is sent to the next router/NI to specify that the data on the output port is valid
);
end;
architecture behavior of Arbiter is
-- next
-- Arbiter router or NI
-- --- ---------------------------- ---- ----
-- from LBDR ---> |Req(s) RTS | -----> |DRTS
-- To FIFO <--- |Grant(s) DCTS| <----- |CTS
-- to XBAR <--- |Xbar_sel | |
-- --- ---------------------------- ---- ----
--------------------------------------------------------------------------------------------
-- an example of a request/grant + handshake process with next router or NI
--CLK _|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|__
-- Req _____|'''''''''''''''''''''''''''''''''''''''''''|________
-- _________ ___________________ _______ _______ _______ ____
-- TX _________X_______HEADER______X_Body__X_Body__X__Tail_X____
-- Grant _________________________|'''|___|'''|___|'''|____________
-- RTS _________|'''''''''''''''''''|___|'''''''|___|'''''''|____
-- DCTS _________________________|'''|_______|'''|_______|'''|____ (CTS (DCTS) is always maximum 1 clock cycle!)
-- |<---------clear----------->|
-- | to send |
--------------------------------------------------------------------------------------------
--TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SUBTYPE STATE_TYPE IS STD_LOGIC_VECTOR (5 downto 0);
CONSTANT IDLE: STATE_TYPE := "000001";
CONSTANT Local: STATE_TYPE := "000010";
CONSTANT North: STATE_TYPE := "000100";
CONSTANT East: STATE_TYPE := "001000";
CONSTANT West: STATE_TYPE := "010000";
CONSTANT South: STATE_TYPE := "100000";
SIGNAL state, state_in, next_state : STATE_TYPE := IDLE;
SIGNAL RTS_FF, RTS_FF_in: std_logic;
begin
-- process for updating the state of arbiter's FSM, also setting RTS based on the state (if Grant is given or not)
process(clk, reset)begin
if reset = '0' then
state<=IDLE;
RTS_FF <= '0';
elsif clk'event and clk = '1' then
-- no grant given yet, it might be that there is no request to
-- arbiter or request is there, but the next router's/NI's FIFO is full
state <= state_in;
RTS_FF <= RTS_FF_in;
end if;
end process;
-- anything below here is pure combinational
RTS <= RTS_FF;
process(RTS_FF, DCTS, state, next_state)begin
if RTS_FF = '1' and DCTS = '0' then
state_in <= state;
else
state_in <= next_state;
end if;
end process;
process(state, RTS_FF, DCTS)begin
if state = IDLE then
RTS_FF_in <= '0';
-- if there was a grant given to one of the inputs,
-- tell the next router/NI that the output data is valid
else
if RTS_FF = '1' and DCTS = '1' then
RTS_FF_in <= '0';
else
RTS_FF_in <= '1';
end if;
end if ;
end process;
-- sets the grants using round robin
-- the order is L --> N --> E --> W --> S and then back to L
process(state, Req_N, Req_E, Req_W, Req_S, Req_L, DCTS, RTS_FF)begin
Grant_N <= '0';
Grant_E <= '0';
Grant_W <= '0';
Grant_S <= '0';
Grant_L <= '0';
Xbar_sel<= "00000";
case(state) is
when IDLE =>
Xbar_sel<= "00000";
If Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
else
next_state <= IDLE;
end if;
when North =>
Grant_N <= DCTS and RTS_FF ;
Xbar_sel<= "00001";
If Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
else
next_state <= IDLE;
end if;
when East =>
Grant_E <= DCTS and RTS_FF;
Xbar_sel<= "00010";
If Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
else
next_state <= IDLE;
end if;
when West =>
Grant_W <= DCTS and RTS_FF;
Xbar_sel<= "00100";
If Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
else
next_state <= IDLE;
end if;
when South =>
Grant_S <= DCTS and RTS_FF;
Xbar_sel<= "01000";
If Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
else
next_state <= IDLE;
end if;
when others => -- Local
Grant_L <= DCTS and RTS_FF;
Xbar_sel<= "10000";
If Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
else
next_state <= IDLE;
end if;
end case ;
end process;
end;
| gpl-3.0 | e9d0338955d9b152bd56166f66b75fb1 | 0.401364 | 4.317101 | false | false | false | false |
bruskajp/EE-316 | Project2/Vivado_NexysBoard/project_2b/project_2b.srcs/sources_1/imports/Downloads/reset_delay.vhd | 1 | 624 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.numeric_std.ALL;
use IEEE.STD_LOGIC_ARITH;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY Reset_Delay IS
PORT (
SIGNAL iCLK : IN std_logic;
SIGNAL oRESET : OUT std_logic
);
END Reset_Delay;
ARCHITECTURE Arch OF Reset_Delay IS
SIGNAL Cont : std_logic_vector(19 DOWNTO 0):=X"00000";
BEGIN
PROCESS
BEGIN
WAIT UNTIL rising_edge (iCLK);
IF Cont /= X"FFFFF" THEN
-- IF Cont /= X"0000F" THEN
Cont <= Cont + '1';
oRESET <= '1';
ELSE
oRESET <= '0';
END IF;
END PROCESS;
END Arch; | gpl-3.0 | 926d306a225047e354d2f0d7677b6669 | 0.588141 | 3.25 | false | false | false | false |
carlosrd/DAS | P4/Parte C (Opcional 2)/binToSeg.vhd | 5 | 1,631 | ----------------------------------------------------------------------------------
-- ESQUEMA LEDS 8 SEGMENTOS:
--
-- A
-- ---
-- F | | B
-- -G-
-- E | | C
-- --- . DP
-- D
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity binToSeg is
port (
bin: in std_logic_vector(3 downto 0);
displaySeg: out std_logic_vector(7 downto 0) -- 7 = A / 6 = B / ... / 0 = H
);
end binToSeg;
architecture Converter of binToSeg is
begin
with bin select
displaySeg <= "11111100" when "0000", -- 0 => Leds: A,B,C,D,E,F
"01100000" when "0001", -- 1 => Leds: B,C
"11011010" when "0010", -- 2 => Leds: A,B,G,E,D
"11110010" when "0011", -- 3 => Leds: A,B,C,D,G
"01100110" when "0100", -- 4 => Leds: B,C,F,G
"10110110" when "0101", -- 5 => Leds: A,C,D,F,G
"10111110" when "0110", -- 6 => Leds: A,C,D,E,F,G
"11100000" when "0111", -- 7 => Leds: A,B,C
"11111110" when "1000", -- 8 => Leds: A,B,C,D,E,F,G
"11110110" when "1001", -- 9 => Leds: A,B,C,D,F,G
"11101110" when "1010", -- A(10) => Leds: A,B,C,E,F,G
"00111110" when "1011", -- B(11) => Leds: A,B,C,D,E,F,G
"10011100" when "1100", -- C(12) => Leds: A,D,E,F
"01111010" when "1101", -- D(13) => Leds: A,B,C,D,E,F
"10011110" when "1110", -- E(14) => Leds: A,D,E,F,G
"10001110" when "1111", -- F(15) => Leds: A,E,F,G
"00000001" when others; -- En cualquier otro caso encendemos el "."
end Converter;
| mit | e0a94cfb83a2582b0b75db7ac649f107 | 0.437155 | 2.764407 | false | false | false | false |
TUM-LIS/faultify | hardware/testcases/viterbi/fpga_sim/xpsLibraryPath_viterbi_200_399/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/vhdl/faultify_axi_wrapper.vhd | 2 | 19,307 | ------------------------------------------------------------------------------
-- faultify_axi_wrapper.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: faultify_axi_wrapper.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Fri May 16 15:25:24 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
use proc_common_v3_00_a.soft_reset;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library faultify_axi_wrapper_v1_00_a;
use faultify_axi_wrapper_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity faultify_axi_wrapper is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
numInj : integer := 200;
numIn : integer := 69;
numOut : integer := 5;
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
faultify_clk_fast : in std_logic;
faultify_clk_slow_out : out std_logic;
s_axis_aresetn : in std_logic;
s_axis_input_tvalid : in std_logic;
s_axis_input_tdata : in std_logic_vector(31 downto 0);
s_axis_input_tlast : in std_logic;
s_axis_input_tready : out std_logic;
m_axis_output_tvalid : out std_logic;
m_axis_output_tdata : out std_logic_vector(31 downto 0);
m_axis_output_tlast : out std_logic;
m_axis_output_tready : in std_logic;
s_axis_ctrl_tvalid : in std_logic;
s_axis_ctrl_tdata : in std_logic_vector(31 downto 0);
s_axis_ctrl_tlast : in std_logic;
s_axis_ctrl_tready : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity faultify_axi_wrapper;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of faultify_axi_wrapper is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant RST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
constant RST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
constant USER_SLV_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & RST_BASEADDR, -- soft reset space base address
ZERO_ADDR_PAD & RST_HIGHADDR, -- soft reset space high address
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant RST_NUM_CE : integer := 1;
constant USER_SLV_NUM_REG : integer := 32;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG + RST_NUM_CE;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (RST_NUM_CE), -- number of ce for soft reset space
1 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Width of triggered reset in bus clocks
------------------------------------------
constant RESET_WIDTH : integer := 8;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant RST_CS_INDEX : integer := 0;
constant RST_CE_INDEX : integer := USER_NUM_REG;
constant USER_SLV_CS_INDEX : integer := 1;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_Bus2IP_Reset : std_logic;
signal rst_Bus2IP_Reset : std_logic;
signal rst_IP2Bus_WrAck : std_logic;
signal rst_IP2Bus_Error : std_logic;
signal rst_Bus2IP_Reset_tmp : std_logic;
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
signal testvector : std_logic_vector(numIn-1 downto 0);
signal resultvector_o : std_logic_vector(numOut-1 downto 0);
signal resultvector_f : std_logic_vector(numOut-1 downto 0);
begin
testvector(0) <= s_axis_input_tvalid;
testvector(32 downto 1) <= s_axis_input_tdata;
testvector(33) <= s_axis_input_tlast;
s_axis_input_tready <= resultvector_o(0);
m_axis_output_tvalid <= resultvector_o(1);
m_axis_output_tdata(0) <= resultvector_o(2);
m_axis_output_tdata(1) <= resultvector_f(2);
m_axis_output_tdata(31 downto 2) <= (others => '0');
m_axis_output_tlast <= resultvector_o(3);
testvector(34) <= m_axis_output_tready;
testvector(35) <= s_axis_ctrl_tvalid;
testvector(67 downto 36) <= s_axis_ctrl_tdata;
testvector(68) <= s_axis_ctrl_tlast;
s_axis_ctrl_tready <= resultvector_o(4);
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate soft_reset
------------------------------------------
SOFT_RESET_I : entity proc_common_v3_00_a.soft_reset
generic map
(
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_RESET_WIDTH => RESET_WIDTH
)
port map
(
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_WrCE => ipif_Bus2IP_WrCE(RST_CE_INDEX),
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Reset2IP_Reset => rst_Bus2IP_Reset,
Reset2Bus_WrAck => rst_IP2Bus_WrAck,
Reset2Bus_Error => rst_IP2Bus_Error,
Reset2Bus_ToutSup => open
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity faultify_axi_wrapper_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
numInj => numInj,
numIn => numIn,
numOut => numOut,
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
faultify_clk_fast => faultify_clk_fast,
faultify_clk_slow_out => faultify_clk_slow_out,
s_axis_aresetn => s_axis_aresetn,
resultvector_o => resultvector_o,
resultvector_f => resultvector_f,
testvector => testvector,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => rst_Bus2IP_Reset_tmp,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
IP2BUS_DATA_MUX_PROC : process(ipif_Bus2IP_CS, user_IP2Bus_Data) is
begin
case ipif_Bus2IP_CS (1 downto 0) is
when "01" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when "10" => ipif_IP2Bus_Data <= (others => '0');
when others => ipif_IP2Bus_Data <= (others => '0');
end case;
end process IP2BUS_DATA_MUX_PROC;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck or rst_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error or rst_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
ipif_Bus2IP_Reset <= not ipif_Bus2IP_Resetn;
rst_Bus2IP_Reset_tmp <= not rst_Bus2IP_Reset;
end IMP;
| gpl-2.0 | c780d5ae7c3a5bde3ded309273f03a7e | 0.524628 | 3.683839 | false | false | false | false |
SoCdesign/EHA | RTL/Fault_Management/Error_Detection_Correction/hamming_decoder.vhd | 1 | 5,641 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_misc.all;
Entity hamming_decoder is
port
(hamming_in : in std_logic_vector(38 downto 0); --d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 --d26 d27 p0 p1 p2 p3 p4 p5 p6
dataout : out std_logic_vector(31 downto 0); --d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 --d26 d27
s_err_corr : out std_logic; --diagnostic outputs
d_err_det : out std_logic; --diagnostic outputs
no_error : out std_logic); --diagnostic outputs
end hamming_decoder;
architecture beh OF hamming_decoder is
Signal syndrome : std_logic_vector (6 downto 0);
begin
syndrome(0) <= hamming_in(0) xor hamming_in(1) xor hamming_in(3) xor hamming_in(4) xor hamming_in(6) xor
hamming_in(8) xor hamming_in(10) xor hamming_in(11) xor hamming_in(13) xor hamming_in(15) xor
hamming_in(17) xor hamming_in(19) xor hamming_in(21) xor hamming_in(23) xor hamming_in(25) xor hamming_in(26) xor hamming_in(28) xor hamming_in(30) xor hamming_in(32);
syndrome(1) <= hamming_in(0) xor hamming_in(2) xor hamming_in(3) xor hamming_in(5) xor hamming_in(6) xor
hamming_in(9) xor hamming_in(10) xor hamming_in(12) xor hamming_in(13) xor hamming_in(16) xor
hamming_in(17) xor hamming_in(20) xor hamming_in(21) xor hamming_in(24) xor hamming_in(25) xor hamming_in(27) xor hamming_in(28) xor hamming_in(31) xor hamming_in(33);
syndrome(2) <= XOR_REDUCE(hamming_in(3 downto 1)) xor XOR_REDUCE(hamming_in(10 downto 7)) xor XOR_REDUCE(hamming_in(17 downto 14)) xor
XOR_REDUCE(hamming_in(25 downto 22)) xor XOR_REDUCE(hamming_in(31 downto 29)) xor hamming_in(34);
syndrome(3) <= XOR_REDUCE(hamming_in(10 downto 4)) xor XOR_REDUCE(hamming_in(25 downto 18)) xor hamming_in(35);
syndrome(4) <= XOR_REDUCE(hamming_in(25 downto 11)) xor hamming_in(36);
syndrome(5) <= XOR_REDUCE(hamming_in(31 downto 26)) xor hamming_in(37);
syndrome(6) <= XOR_REDUCE(hamming_in(38 downto 0));
PROCESS(hamming_in, syndrome)
BEGIN
if syndrome(6) = '0' then
s_err_corr <= '0';
if (syndrome = "0000000") then -------no errors
no_error <= '1';
d_err_det <= '0';
dataout <= hamming_in(31 downto 0);
else -- (syndrome(5 downto 0) /= "000000")
no_error <= '0';
d_err_det <= '1';
dataout <= (others=> '0');
end if;
else -----------------------------------------------single bit error syndrome(6) = '1'
no_error <= '0';
d_err_det <= '0';
s_err_corr <= '1';
dataout <= hamming_in(31 downto 0); -- to cover all the bits
Case syndrome(5 downto 0) is
when "000000"|"000001"|"000010"|"000100"|"001000"|"010000"|"100000" => ------ this implies the error is only in parity bits, not data.
dataout <= hamming_in(31 downto 0);
when "000011" => dataout(0) <= not hamming_in(0);
when "000101" => dataout(1) <= not hamming_in(1);
when "000110" => dataout(2) <= not hamming_in(2);
when "000111" => dataout(3) <= not hamming_in(3);
when "001001" => dataout(4) <= not hamming_in(4);
when "001010" => dataout(5) <= not hamming_in(5);
when "001011" => dataout(6) <= not hamming_in(6);
when "001100" => dataout(7) <= not hamming_in(7);
when "001101" => dataout(8) <= not hamming_in(8);
when "001110" => dataout(9) <= not hamming_in(9);
when "001111" => dataout(10) <= not hamming_in(10);
when "010001" => dataout(11) <= not hamming_in(11);
when "010010" => dataout(12) <= not hamming_in(12);
when "010011" => dataout(13) <= not hamming_in(13);
when "010100" => dataout(14) <= not hamming_in(14);
when "010101" => dataout(15) <= not hamming_in(15);
when "010110" => dataout(16) <= not hamming_in(16);
when "010111" => dataout(17) <= not hamming_in(17);
when "011000" => dataout(18) <= not hamming_in(18);
when "011001" => dataout(19) <= not hamming_in(19);
when "011010" => dataout(20) <= not hamming_in(20);
when "011011" => dataout(21) <= not hamming_in(21);
when "011100" => dataout(22) <= not hamming_in(22);
when "011101" => dataout(23) <= not hamming_in(23);
when "011110" => dataout(24) <= not hamming_in(24);
when "011111" => dataout(25) <= not hamming_in(25);
when "100001" => dataout(26) <= not hamming_in(26);
when "100010" => dataout(27) <= not hamming_in(27);
when "100011" => dataout(28) <= not hamming_in(28);
when "100100" => dataout(29) <= not hamming_in(29);
when "100101" => dataout(30) <= not hamming_in(30);
when "100110" => dataout(31) <= not hamming_in(31);
when others=> dataout <= (others=> '0');
END Case;
END if;
END process;
END beh; | gpl-3.0 | f2d65c3d7f5e971dc1acc9ed91d2c8ea | 0.528984 | 3.464988 | false | false | false | false |
Ana06/function-graphing-FPGA | mem_2.vhd | 2 | 18,873 | ----------------------------------------------------------------------------------
-- Company: Universidad Complutense de Madrid
-- Engineer: Marcos Sanchez-Elez
--
-- Create Date: 15:52:19 12/04/2013
-- Module Name: rams_2p - circuito
-- Target Devices: Spartan 3
-- Tool versions:
-- Description:
-- Memoria síncrona de doble puerto de lectura y un único puerto de escritura
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity rams_2p is
port (clk : in std_logic;
we : in std_logic;
addr1 : in std_logic_vector(6 downto 0);
addr2 : in std_logic_vector(6 downto 0);
di : in std_logic_vector(0 to 127);
do1 : out std_logic_vector(0 to 127);
do2 : out std_logic_vector(0 to 127)
);
end rams_2p;
architecture circuito of rams_2p is
type ram_type is array (0 to 127) of std_logic_vector (0 to 127);
signal RAM : ram_type:=(
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begin
puerto1: process (clk)
begin
if rising_edge(clk) then
if we = '1' then
RAM(conv_integer(addr1)) <= di;
end if;
do1 <= RAM(conv_integer(addr1));
end if;
end process puerto1;
puerto2: process (clk)
begin
if rising_edge(clk) then
do2 <= RAM(conv_integer(addr2));
end if;
end process puerto2;
end circuito;
| gpl-3.0 | 15ec5a7c5760230d824811ce47c35dbc | 0.912891 | 17.507421 | false | false | false | false |
bruskajp/EE-316 | Project2/Quartus_DE2Board/top_level.vhd | 1 | 7,456 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_level is
generic (constant divisor : integer := 83333); -- want the effective clock to be 600Hz, input clock is 50MHz, div by 83.3k
Port ( iClk : in std_logic;
iReset : in std_logic; -- KEY0
F_B : in std_logic; -- KEY1
E_D : in std_logic; -- KEY2
HEX0 : out std_logic_vector(6 downto 0);
HEX1 : out std_logic_vector(6 downto 0);
HEX2 : out std_logic_vector(6 downto 0);
HEX3 : out std_logic_vector(6 downto 0);
HEX4 : out std_logic_vector(6 downto 0);
HEX5 : out std_logic_vector(6 downto 0);
HEX6 : out std_logic_vector(6 downto 0);
HEX7 : out std_logic_vector(6 downto 0);
Tx : out std_logic;
MOSI : out std_logic;
CSN : out std_logic;
SCK : out std_logic;
scl : inout std_logic;
sda : inout std_logic;
clk_t : inout std_logic := '0'
);
end top_level;
architecture Structural of top_level is
---------------------------Components-----------------------
component Reset_Delay is
PORT (
SIGNAL iCLK : in std_logic;
SIGNAL oRESET : out std_logic
);
end component;
component clk_enabler is
port (
clock : in std_logic;
clk_en : out std_logic
);
end component;
component btn_debounce_toggle is
GENERIC (CONSTANT CNTR_MAX : std_logic_vector(15 downto 0) := X"FFFF");
Port (
BTN_I : in std_logic;
CLK : in std_logic;
BTN_O : out std_logic;
TOGGLE_O : out std_logic
);
end component;
component univ_bin_counter is
generic (N: natural := 8);
port (
clk : in std_logic;
syn_clr, en, up : in std_logic;
clk_en : in std_logic := '1';
qo : out std_logic_vector(N-1 downto 0)
);
end component;
component Hex_ROM is
port (
address : in std_logic_vector(7 downto 0);
clock : in std_logic;
q : out std_logic_vector(15 downto 0)
);
end component;
component display_driver is
port (
Input : in std_logic_vector(15 downto 0);
--clk : in std_logic;
HEX0 : out std_logic_vector(6 downto 0);
HEX1 : out std_logic_vector(6 downto 0);
HEX2 : out std_logic_vector(6 downto 0);
HEX3 : out std_logic_vector(6 downto 0);
HEX4 : out std_logic_vector(6 downto 0);
HEX5 : out std_logic_vector(6 downto 0);
HEX6 : out std_logic_vector(6 downto 0);
HEX7 : out std_logic_vector(6 downto 0)
);
end component;
component TTL_Serial_Display is
port (
Hex_IN : in std_logic_vector (15 downto 0);
iCLK : in std_logic;
Tx : out std_logic);
end component;
component SPI_Display is
port (
Hex_IN : in std_logic_vector (15 downto 0);
iCLK : in std_logic;
MOSI : out std_logic;
CSN : out std_logic;
SCK : out std_logic
);
end component;
component Interfacer is
PORT(
CLK : in std_logic;
data_in : in std_logic_vector(15 downto 0) := x"0000";
sda : inout std_logic;
scl : inout std_logic
);
end component;
-----------------------------Signals---------------------------------
signal r_reg : unsigned(3 downto 0);
signal reset : std_logic;
signal clk_en : std_logic;
signal clk_cnt : integer range 0 to divisor:= 0;
signal output : integer range 0 to 15:= 0;
signal iReset_deb : std_logic;
signal iCnt_en_deb, iF_B_deb : std_logic;
signal TOGGLE_up : std_logic;
signal TOGGLE_en : std_logic;
signal reset_on : std_logic;
signal TOGGLE_Forward : std_logic;
---------------------------------------------------------------------
signal iROM : std_logic_vector(7 downto 0);
signal oROM : std_logic_vector(15 downto 0);
---------------------------------------------------------------------
constant cnt_max2 : integer :=19999999;
signal clk_cnt2 : integer range 0 to cnt_max2;
signal clk_en2 : std_logic;
-----------------------------Buttons---------------------------------
signal clk_counter : integer range 0 to 3999999;
signal clk_counter2 : integer range 0 to 3999999;
begin
-- process(iClk)
-- begin
-- if rising_edge(iClk) then
-- if (clk_cnt2 = cnt_max2) then
-- clk_cnt2 <= 0;
-- clk_en2 <= '1';
-- else
-- clk_cnt2 <= clk_cnt2 + 1;
-- clk_en2 <= '0';
-- end if;
-- end if;
-- end process;
process(iClk)
begin
if rising_edge(iClk) then
if (clk_counter = 50) then
clk_t <= not clk_t;
clk_counter <= 0;
else
clk_counter <= clk_counter + 1;
end if;
end if;
end process;
process(iClk)
begin
if rising_edge(iClk) then
if (clk_t = '0') then
clk_counter2 <= clk_counter2 +1;
end if;
end if;
end process;
Inst_clk_Reset_Delay: Reset_Delay
port map(
iCLK => iClk,
oRESET => reset
);
Inst_clk_enabler: clk_enabler
port map(
clock => iClk,
clk_en => clk_en
);
Inst_iReset_debounce: btn_debounce_toggle
generic map(CNTR_MAX => X"FFFF") -- For simulation: use CNTR_MAX => X"0009", else use X"FFFF""
port map(
BTN_I => iReset,
CLK => iClk,
BTN_O => iReset_deb,
TOGGLE_O => open -- Toggle output is not used in this design
);
Inst_iCnt_en_debounce: btn_debounce_toggle
generic map(CNTR_MAX => X"FFFF") -- For simulation: use CNTR_MAX => X"0009", else use X"FFFF"
port map(
BTN_I => E_D,
CLK => iClk,
BTN_O => open,
TOGGLE_O => TOGGLE_en
);
Inst_iF_B_debounce: btn_debounce_toggle
generic map(CNTR_MAX => X"FFFF") -- For simulation: use CNTR_MAX => X"0009", else use X"FFFF""
port map(
BTN_I => F_B,
CLK => iClk,
BTN_O => open,
TOGGLE_O => TOGGLE_up
);
-------------------------Component Definitions-----------------------
Inst_univ_bin_counter: univ_bin_counter
generic map(N => 8)
port map(
clk => clk_en,
qo => iROM,
en => TOGGLE_en,
up => TOGGLE_up,
syn_clr => iReset_deb
);
Inst_Hex_ROM: Hex_ROM
port map(
clock => iClk,
address => iROM,
q => oROM
);
Inst_display_driver: display_driver
port map(
Input => oROM,
--clk => clk_en,
HEX0 => HEX0,
HEX1 => HEX1,
HEX2 => HEX2,
HEX3 => HEX3,
HEX4 => HEX4,
HEX5 => HEX5,
HEX6 => HEX6,
HEX7 => HEX7
);
Inst_TTL_Serial_Display: TTL_Serial_Display
port map(
Hex_IN => oROM,
iClk => clk_en,
Tx => Tx
);
Inst_SPI_Display: SPI_Display
port map(
Hex_IN => oROM,
iClk => clk_en,
MOSI => MOSI,
CSN => CSN,
SCK => SCK
);
Inst_Interfacer: Interfacer
port map(
CLK => iClk,
data_in => oROM,
sda => sda,
scl => scl
);
end Structural;
| gpl-3.0 | 6970986f3b7a580bd909b7d0a842b545 | 0.498793 | 3.115754 | false | false | false | false |
carlosrd/DAS | P3/cerrojoElectronico.vhd | 1 | 3,858 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:13:29 11/08/2013
-- Design Name:
-- Module Name: cerrojoElectronico - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cerrojoElectronico is
port (
-- Entradas
intro: in std_logic; -- Boton para confirmar la introduccion de clave
switch: in std_logic_vector(7 downto 0); -- Switches para escribir la clave
clk: in std_logic; -- Reloj
rst: in std_logic; -- Reset
-- Salidas
segs: out std_logic_vector(7 downto 0); -- Display 8-Segmentos para visualizar numero de intentos restantes
lock: out std_logic -- Encederemos el primer LED para indicar que esta LOCK
);
end cerrojoElectronico;
architecture Behavioral of cerrojoElectronico is
-- CERROJO ELECTRONICO
signal xDebounced,xDebRiseEdge,xDebFallingEdge: std_logic;
signal load: std_logic;
signal salidaRegistro: std_logic_vector(7 downto 0);
signal rightSeg: std_logic_vector(7 downto 0);
-- MAQUINA DE ESTADOS
type ESTADOS is (INICIAL,S0, S1, S2, S3);
signal ESTADO, SIG_ESTADO: ESTADOS;
signal st: std_logic_vector(3 downto 0);
--
signal clave: std_logic_vector(7 downto 0);
component debouncer
port(rst: in std_logic;
clk: in std_logic;
x: in std_logic;
xDeb: out std_logic;
xDebFallingEdge: out std_logic;
xDebRisingEdge: out std_logic);
end component;
component binToSeg
port (
bin: in std_logic_vector(3 downto 0);
displaySeg: out std_logic_vector(7 downto 0) -- 7 = A / 6 = B / ... / 0 = H
);
end component;
begin
segs <= rightSeg;
clave <= switch;
button: debouncer port map (rst,clk,intro,xDebounced,xDebFallingEdge,xDebRiseEdge);
registro:
process (clk, rst)
begin
-- Los Push Buttons, como los Switches, tienen logica negativa, es decir, es al reves.
if rst='0' then
salidaRegistro <= (others=>'0');
elsif (clk'event and clk='1') then
if load='1' then
salidaRegistro <= switch;
end if;
end if;
end process;
-- MAQUINA ESTADOS: SINCRONO
maqEstadosSyn:
process(clk,rst)
begin
if rst ='0' then
ESTADO <= INICIAL;
elsif clk'event and clk='1' then
ESTADO <= SIG_ESTADO;
end if;
end process;
-- MAQUINA ESTADOS: COMBINACIONAL
maqEstadosComb:
process(ESTADO,rst,xDebFallingEdge,salidaRegistro,clave)
begin
SIG_ESTADO <= ESTADO;
load <= '0';
lock <= '1';
case ESTADO is
when INICIAL =>
lock <= '0';
st <= "1010";
if xDebFallingEdge = '1' then
load <= '1';
SIG_ESTADO <= S3;
end if;
when S3 =>
st <= "0011";
if xDebFallingEdge = '1' and (salidaRegistro = clave) then
SIG_ESTADO <= INICIAL;
elsif xDebFallingEdge = '1' and (salidaRegistro /= clave) then
SIG_ESTADO <= S2;
end if;
when S2 =>
st <= "0010";
if xDebFallingEdge = '1' and (salidaRegistro = clave) then
SIG_ESTADO <= INICIAL;
elsif xDebFallingEdge = '1' and (salidaRegistro /= clave) then
SIG_ESTADO <= S1;
end if;
when S1 =>
st <= "0001";
if xDebFallingEdge = '1' and (salidaRegistro = clave) then
SIG_ESTADO <= INICIAL;
elsif xDebFallingEdge = '1' and (salidaRegistro /= clave) then
SIG_ESTADO <= S0;
end if;
when S0 =>
st <= "0000";
end case;
end process;
displayCuenta: binToSeg port map (st,rightSeg);
end Behavioral;
| mit | a9ad7e168aa8dab53d6d8b74a9fd063b | 0.589425 | 3.562327 | false | false | false | false |
carlosrd/DAS | P2/Parte A/switchToSeg.vhd | 1 | 3,313 | ----------------------------------------------------------------------------------
-- ESQUEMA LEDS 8 SEGMENTOS:
--
-- A
-- ---
-- F | | B
-- -G-
-- E | | C
-- --- . DP
-- D
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity switchToSeg is
port (
switch: in std_logic_vector(7 downto 0);
rightSeg: out std_logic_vector(7 downto 0);
leftSeg: out std_logic_vector(7 downto 0) -- 7 = A / 6 = B / ... / 0 = H
);
end switchToSeg;
architecture Behavioral of switchToSeg is
signal rightSwitch: std_logic_vector(3 downto 0);
signal leftSwitch: std_logic_vector(3 downto 0);
begin
-- Partimos los 8 switch en 2 bloques de 4.
-- Recordamos de la practica anterior que es necesario usar
-- un negador con los switch para que funcionen de la manera esperada
leftSwitch(3) <= not(switch(0));
leftSwitch(2) <= not(switch(1));
leftSwitch(1) <= not(switch(2));
leftSwitch(0) <= not(switch(3));
rightSwitch(3) <= not(switch(4));
rightSwitch(2) <= not(switch(5));
rightSwitch(1) <= not(switch(6));
rightSwitch(0) <= not(switch(7));
with leftSwitch select
leftSeg <= "11111100" when "0000", -- 0 => Leds: A,B,C,D,E,F
"01100000" when "0001", -- 1 => Leds: B,C
"11011010" when "0010", -- 2 => Leds: A,B,G,E,D
"11110010" when "0011", -- 3 => Leds: A,B,C,D,G
"01100110" when "0100", -- 4 => Leds: B,C,F,G
"10110110" when "0101", -- 5 => Leds: A,C,D,F,G
"10111110" when "0110", -- 6 => Leds: A,C,D,E,F,G
"11100000" when "0111", -- 7 => Leds: A,B,C
"11111110" when "1000", -- 8 => Leds: A,B,C,D,E,F,G
"11110110" when "1001", -- 9 => Leds: A,B,C,D,F,G
"11101110" when "1010", -- A(10) => Leds: A,B,C,E,F,G
"00111110" when "1011", -- B(11) => Leds: A,B,C,D,E,F,G
"10011100" when "1100", -- C(12) => Leds: A,D,E,F
"01111010" when "1101", -- D(13) => Leds: A,B,C,D,E,F
"10011110" when "1110", -- E(14) => Leds: A,D,E,F,G
"10001110" when "1111", -- F(15) => Leds: A,E,F,G
"00000001" when others; -- En cualquier otro caso encendemos el "."
with rightSwitch select
rightSeg <= "11111100" when "0000", -- 0 => Leds: A,B,C,D,E,F
"01100000" when "0001", -- 1 => Leds: B,C
"11011010" when "0010", -- 2 => Leds: A,B,G,E,D
"11110010" when "0011", -- 3 => Leds: A,B,C,D,G
"01100110" when "0100", -- 4 => Leds: B,C,F,G
"10110110" when "0101", -- 5 => Leds: A,C,D,F,G
"10111110" when "0110", -- 6 => Leds: A,C,D,E,F,G
"11100000" when "0111", -- 7 => Leds: A,B,C
"11111110" when "1000", -- 8 => Leds: A,B,C,D,E,F,G
"11110110" when "1001", -- 9 => Leds: A,B,C,D,F,G
"11101110" when "1010", -- A(10) => Leds: A,B,C,E,F,G
"00111110" when "1011", -- B(11) => Leds: A,B,C,D,E,F,G
"10011100" when "1100", -- C(12) => Leds: A,D,E,F
"01111010" when "1101", -- D(13) => Leds: A,B,C,D,E,F
"10011110" when "1110", -- E(14) => Leds: A,D,E,F,G
"10001110" when "1111", -- F(15) => Leds: A,E,F,G
"00000001" when others; -- En cualquier otro caso encendemos el "."
end Behavioral;
| mit | 68e90d3165f75da06ddf41a0b6767042 | 0.49834 | 2.680421 | false | false | false | false |
JarrettR/FPGA-Cryptoparty | FPGA/hdl/sha1_load.vhd | 1 | 2,323 | --------------------------------------------------------------------------------
-- This code serial loads and pads message for SHA1 calculation
-- Copyright (C) 2016 Jarrett Rainier
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.sha1_pkg.all;
entity sha1_load is
port(
clk_i : in std_ulogic;
rst_i : in std_ulogic;
dat_i : in std_ulogic_vector(0 to 31);
sot_in : in std_ulogic;
dat_w_o : out w_input
);
end sha1_load;
architecture RTL of sha1_load is
signal w: w_input;
signal w_temp: w_input;
begin
process(clk_i)
begin
if (clk_i'event and clk_i = '1') then
if rst_i = '1' then
for i in 0 to 15 loop
w(i) <= "00000000000000000000000000000000";
end loop;
else
for i in 1 to 15 loop
w(i) <= w_temp(i - 1);
end loop;
end if;
end if;
end process;
dat_w_o <= w_temp;
--Alt: Use a generate statement
w_temp(0) <= dat_i;
w_temp(1) <= w(1);
w_temp(2) <= w(2);
w_temp(3) <= w(3);
w_temp(4) <= w(4);
w_temp(5) <= w(5);
w_temp(6) <= w(6);
w_temp(7) <= w(7);
w_temp(8) <= w(8);
w_temp(9) <= w(9);
w_temp(10) <= w(10);
w_temp(11) <= w(11);
w_temp(12) <= w(12);
w_temp(13) <= w(13);
w_temp(14) <= w(14);
w_temp(15) <= w(15);
end RTL; | gpl-3.0 | deabb229cb129bd314ad7a4bda993068 | 0.489453 | 3.472347 | false | false | false | false |
SoCdesign/EHA | RTL/Immortal_Chip/FIFO_one_hot_with_checkers.vhd | 1 | 8,761 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
DRTS: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
CTS: out std_logic;
empty_out: out std_logic;
read_pointer_out, write_pointer_out: out std_logic_vector(3 downto 0);
write_en_out :out std_logic;
-- Checker outputs
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
--err_CTS_in,
err_write_en,
err_not_CTS_in,
--err_not_write_en,
err_read_en_mismatch : out std_logic
);
end FIFO;
architecture behavior of FIFO is
signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(3 downto 0);
signal full, empty: std_logic;
signal read_en, write_en: std_logic;
signal CTS_in, CTS_out: std_logic;
component FIFO_control_part_checkers is
port ( DRTS: in std_logic;
CTS_out: in std_logic;
CTS_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
read_pointer_in: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
write_pointer_in: in std_logic_vector(3 downto 0);
empty_out: in std_logic;
full_out: in std_logic;
read_en_out: in std_logic;
write_en_out: in std_logic;
-- Checker outputs
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
--err_CTS_in,
err_write_en,
err_not_CTS_in,
--err_not_write_en,
err_read_en_mismatch : out std_logic
);
end component;
begin
--------------------------------------------------------------------------------------------
-- block diagram of the FIFO!
-- previous
-- router
-- -- ------------------------------------------
-- | | |
-- TX|--------->| RX Data_out|----> goes to Xbar and LBDR
-- | | |
-- RTS|--------->| DRTS FIFO read_en|<---- Comes from Arbiters (N,E,W,S,L)
-- | | (N,E,W,S,L)|
-- DCTS|<---------| CTS |
-- -- ------------------------------------------
--------------------------------------------------------------------------------------------
-- Hand shake protocol!
--
-- |<-Valid->|
-- | Data |
-- _____ _________ ______
-- RX _____X_________X______
-- DRTS _____|'''''''''|_____
-- CTS __________|''''|_______
--
--------------------------------------------------------------------------------------------
-- circular buffer structure
-- <--- WriteP
-- ---------------------------------
-- | 3 | 2 | 1 | 0 |
-- ---------------------------------
-- <--- readP
--------------------------------------------------------------------------------------------
-- FIFO Control Part checkers instantiation
FIFOCONTROLPARTCHECKERS: FIFO_control_part_checkers port map (
DRTS => DRTS,
CTS_out => CTS_out, CTS_in => CTS_in,
read_en_N => read_en_N, read_en_E => read_en_E, read_en_W => read_en_W, read_en_S => read_en_S, read_en_L => read_en_L,
read_pointer => read_pointer, read_pointer_in => read_pointer_in,
write_pointer => write_pointer, write_pointer_in => write_pointer_in,
empty_out => empty, full_out => full,
read_en_out => read_en, write_en_out => write_en,
err_write_en_write_pointer => err_write_en_write_pointer,
err_not_write_en_write_pointer => err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => err_read_pointer_write_pointer_full,
err_read_pointer_increment => err_read_pointer_increment,
err_read_pointer_not_increment => err_read_pointer_not_increment,
err_write_en => err_write_en,
err_not_CTS_in => err_not_CTS_in,
err_read_en_mismatch => err_read_en_mismatch
);
process (clk, reset)begin
if reset = '0' then
read_pointer <= "0001";
write_pointer <= "0001";
CTS_out<='0';
elsif clk'event and clk = '1' then
write_pointer <= write_pointer_in;
read_pointer <= read_pointer_in;
CTS_out<=CTS_in;
end if;
end process;
-- anything below here is pure combinational
-- combinatorial part
write_pointer_out <= write_pointer;
read_pointer_out <= read_pointer;
write_en_out <= write_en;
read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty;
empty_out <= empty;
CTS <= CTS_out;
process(write_en, write_pointer)begin
if write_en = '1'then
write_pointer_in <= write_pointer(2 downto 0)&write_pointer(3);
else
write_pointer_in <= write_pointer;
end if;
end process;
process(read_en, empty, read_pointer)begin
if (read_en = '1' and empty = '0') then
read_pointer_in <= read_pointer(2 downto 0)&read_pointer(3);
else
read_pointer_in <= read_pointer;
end if;
end process;
process(full, DRTS, CTS_out) begin
if CTS_out = '0' and DRTS = '1' and full ='0' then
CTS_in <= '1';
write_en <= '1';
else
CTS_in <= '0';
write_en <= '0';
end if;
end process;
process(write_pointer, read_pointer) begin
if read_pointer = write_pointer then
empty <= '1';
else
empty <= '0';
end if;
-- if write_pointer = read_pointer>>1 then
if write_pointer = read_pointer(0)&read_pointer(3 downto 1) then
full <= '1';
else
full <= '0';
end if;
end process;
end;
| gpl-3.0 | 659ac5c86f6163c8d7c0f8b5fa05784f | 0.412168 | 4.418053 | false | false | false | false |
bruskajp/EE-316 | Project2/Quartus_DE2Board/SPI_Display.vhd | 1 | 4,156 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SPI_Display is
Port (
Hex_IN : in STD_LOGIC_VECTOR (15 downto 0);
iCLK : in STD_LOGIC;
MOSI : out STD_LOGIC;
CSN : out STD_LOGIC;
SCK : out STD_LOGIC);
end SPI_Display;
architecture Behavioral of SPI_Display is
signal DIV : unsigned(15 DOWNTO 0) :=X"0000";
--Signals for StateMachine:
type stateType is range 0 to 18;
Signal Sel : integer range 0 to 11;
Signal Q : std_logic;
signal CS : stateType;
signal X1,X2,X3,X4 : std_logic_vector (3 downto 0);
signal extend : std_logic_vector (3 downto 0);
signal clk_en : std_logic;
signal HEX2_Data1 : std_logic_vector (7 downto 0);
signal HEX2_Data2 : std_logic_vector (7 downto 0);
signal HEX2_Data3 : std_logic_vector (7 downto 0);
signal HEX2_Data4 : std_logic_vector (7 downto 0);
signal LUT_Data : std_logic_vector (7 downto 0);
signal sCSN : std_logic := '1';
signal sSCK : std_logic := '0';
BEGIN
LUTConversion:
Process(Hex_IN)
begin
X1 <= Hex_IN(15 downto 12);
X2 <= Hex_IN(11 downto 8);
X3 <= Hex_IN(7 downto 4);
X4 <= Hex_IN(3 downto 0);
extend <= "0000";
end process;
Process(X1, X2, X3, X4)
begin
HEX2_Data1 <= extend & X1;
HEX2_Data2 <= extend & X2;
HEX2_Data3 <= extend & X3;
HEX2_Data4 <= extend & X4;
end process;
LUTMux:
process (Sel)
begin
if (Sel = 0) then
LUT_Data <= X"76";
elsif (Sel = 1) then
LUT_Data <= X"76";
elsif (Sel = 2) then
LUT_Data <= X"76";
elsif (Sel = 3) then
LUT_Data <= X"76";
elsif (Sel = 4) then
LUT_Data <= X"79";
elsif (Sel = 5) then
LUT_Data <= X"00";
elsif (Sel = 6) then
LUT_Data <= X"7A";
elsif (Sel = 7) then
LUT_Data <= X"FF";
elsif (Sel = 8) then
LUT_Data <= HEX2_Data1;
elsif (Sel = 9) then
LUT_Data <= HEX2_Data2;
elsif (Sel = 10) then
LUT_Data <= HEX2_Data3;
elsif (Sel = 11) then
LUT_Data <= HEX2_Data4;
end if;
end process;
StateMachine:
--code pulled from Ring_Counter.vhd
process(iCLK)
begin
if rising_edge(iCLK) then
if DIV >= X"0018" then
DIV <= X"0000";
clk_en <= '1';
else
DIV <= DIV +1;
clk_en <= '0';
end if;
end if;
end process;
process (CS, iCLK, clk_en)
begin
if rising_edge(iCLK) and clk_en = '1' then
case CS is
when 0 =>
CS <= 1;
sSCK <= '0';
sCSN <= '0';
Q <= LUT_Data(7);
when 1 =>
CS <= 2;
sSCK <= '1';
Q <= LUT_Data(7);
when 2 =>
Q <= LUT_Data(6);
CS <= 3;
sSCK <= '0';
when 3 =>
Q <= LUT_Data(6);
CS <= 4;
sSCK <= '1';
when 4 =>
Q <= LUT_Data(5);
CS <= 5;
sSCK <= '0';
when 5 =>
Q <= LUT_Data(5);
CS <= 6;
sSCK <= '1';
when 6 =>
Q <= LUT_Data(4);
CS <= 7;
sSCK <= '0';
when 7 =>
Q <= LUT_Data(4);
CS <= 8;
sSCK <= '1';
when 8 =>
Q <= LUT_Data(3);
CS <= 9;
sSCK <= '0';
when 9 =>
Q <= LUT_Data(3);
CS <= 10;
sSCK <= '1';
when 10 =>
Q <= LUT_Data(2);
CS <= 11;
sSCK <= '0';
when 11 =>
Q <= LUT_Data(2);
CS <= 12;
sSCK <= '1';
when 12 =>
Q <= LUT_Data(1);
CS <= 13;
sSCK <= '0';
when 13 =>
Q <= LUT_Data(1);
CS <= 14;
sSCK <= '1';
when 14 =>
Q <= LUT_Data(0);
CS <= 15;
sSCK <= '0';
when 15 =>
Q <= LUT_Data(0);
CS <= 16;
sSCK <= '1';
when 16 =>
Q <= '0';
CS <= 17;
sSCK <= '0';
when 17 =>
Q <= '0';
CS <= 18;
sSCK <= '0';
sCSN <= '1';
if (Sel < 11) then
Sel <= Sel+1;
else
Sel <= 8;
end if;
when 18 =>
Q <= '0';
CS <= 1;
sSCK <= '0';
sCSN <= '0';
end case;
end if;
end process;
MOSI <= Q;
CSN <= sCSN;
SCK <= sSCK;
end Behavioral;
| gpl-3.0 | 30117e3f52577415ffcd3ffbb86b531f | 0.462945 | 2.727034 | false | false | false | false |
TanND/Electronic | VHDL/D8_C2.vhd | 1 | 549 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
entity D8_C2 is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR(7 downto 0)
);
end D8_C2;
architecture D8_C2 of D8_C2 is
begin
process(rst,clk)
variable dem:integer range 0 to 127;
begin
if (rst='1') then dem:=0;
else
if (rising_edge(clk)) then
if(dem=0) then dem:=127;
else dem:=dem-1;
end if;
end if;
end if;
seg<=conv_std_logic_vector(dem,8);
end process;
end D8_C2;
-- rst=0 or 78Khz; clk=25Mhz; | apache-2.0 | 98fee6428a4bd87244a3b5601b0aa0d5 | 0.635701 | 2.44 | false | false | false | false |
SoCdesign/EHA | RTL/Fault_Management/SHMU_prototype/version_2/Router_32_bit_parity.vhd | 2 | 14,978 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_parity is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 60;
Cx_rst : integer := 10;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
DCTS_N, DCTS_E, DCTS_w, DCTS_S, DCTS_L: in std_logic;
DRTS_N, DRTS_E, DRTS_W, DRTS_S, DRTS_L: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
RTS_N, RTS_E, RTS_W, RTS_S, RTS_L: out std_logic;
CTS_N, CTS_E, CTS_w, CTS_S, CTS_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L:out std_logic;
healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L:out std_logic
);
end router_parity;
architecture behavior of router_parity is
COMPONENT parity_checker_packet_detector is
generic(DATA_WIDTH : integer := 32);
port(
reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
DRTS: in std_logic;
faulty_packet, healthy_packet: out std_logic
);
end COMPONENT;
COMPONENT FIFO
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector (DATA_WIDTH-1 downto 0);
DRTS: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
CTS: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
COMPONENT Arbiter
port ( reset: in std_logic;
clk: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic;
DCTS: in std_logic;
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic;
Xbar_sel : out std_logic_vector(4 downto 0);
RTS: out std_logic
);
end COMPONENT;
COMPONENT LBDR is
generic (
cur_addr_rst: integer := 0;
Rxy_rst: integer := 60;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
begin
------------------------------------------------------------------------------------------------------------------------------
-- block diagram of one channel
--
-- .____________grant_________
-- | ▲
-- | _______ __|_______
-- | | | | |
-- | | LBDR |---req--->| Arbiter | <--handshake-->
-- | |_______| |__________| signals
-- | ▲ |
-- __▼___ | flit ___▼__
-- RX ----->| | | type | |
-- <-handshake->| FIFO |---o------------->| |-----> TX
-- signals |______| ------>| |
-- ------>| XBAR |
-- ------>| |
-- ------>| |
-- |______|
--
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the parity_checkers
PC_N: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_N, DRTS =>DRTS_N, faulty_packet => faulty_packet_N , healthy_packet => healthy_packet_N);
PC_E: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_E, DRTS =>DRTS_E, faulty_packet => faulty_packet_E , healthy_packet => healthy_packet_E);
PC_W: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_W, DRTS =>DRTS_W, faulty_packet => faulty_packet_W , healthy_packet => healthy_packet_W);
PC_S: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_S, DRTS =>DRTS_S, faulty_packet => faulty_packet_S , healthy_packet => healthy_packet_S);
PC_L: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_L, DRTS =>DRTS_L, faulty_packet => faulty_packet_L , healthy_packet => healthy_packet_L);
-- all the FIFOs
FIFO_N: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_N, DRTS => DRTS_N,
read_en_N => '0', read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
CTS => CTS_N, empty_out => empty_N, Data_out => FIFO_D_out_N);
FIFO_E: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_E, DRTS => DRTS_E,
read_en_N => Grant_NE, read_en_E =>'0', read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
CTS => CTS_E, empty_out => empty_E, Data_out => FIFO_D_out_E);
FIFO_W: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_W, DRTS => DRTS_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>'0', read_en_S =>Grant_SW, read_en_L =>Grant_LW,
CTS => CTS_W, empty_out => empty_W, Data_out => FIFO_D_out_W);
FIFO_S: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_S, DRTS => DRTS_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>'0', read_en_L =>Grant_LS,
CTS => CTS_S, empty_out => empty_S, Data_out => FIFO_D_out_S);
FIFO_L: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_L, DRTS => DRTS_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>'0',
CTS => CTS_L, empty_out => empty_L, Data_out => FIFO_D_out_L);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the LBDRs
LBDR_N: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N, flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL);
LBDR_E: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E, flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL);
LBDR_W: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W, flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL);
LBDR_S: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S, flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL);
LBDR_L: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L, flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Arbiters
Arbiter_N: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => '0' , Req_E => Req_EN, Req_W => Req_WN, Req_S => Req_SN, Req_L => Req_LN,
DCTS => DCTS_N, Grant_N => Grant_NN, Grant_E => Grant_NE, Grant_W => Grant_NW, Grant_S => Grant_NS, Grant_L => Grant_NL,
Xbar_sel => Xbar_sel_N,
RTS => RTS_N
);
Arbiter_E: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NE , Req_E => '0', Req_W => Req_WE, Req_S => Req_SE, Req_L => Req_LE,
DCTS => DCTS_E, Grant_N => Grant_EN, Grant_E => Grant_EE, Grant_W => Grant_EW, Grant_S => Grant_ES, Grant_L => Grant_EL,
Xbar_sel => Xbar_sel_E,
RTS => RTS_E
);
Arbiter_W: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NW , Req_E => Req_EW, Req_W => '0', Req_S => Req_SW, Req_L => Req_LW,
DCTS => DCTS_W, Grant_N => Grant_WN, Grant_E => Grant_WE, Grant_W => Grant_WW, Grant_S => Grant_WS, Grant_L => Grant_WL,
Xbar_sel => Xbar_sel_W,
RTS => RTS_W
);
Arbiter_S: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NS , Req_E => Req_ES, Req_W => Req_WS, Req_S => '0', Req_L => Req_LS,
DCTS => DCTS_S, Grant_N => Grant_SN, Grant_E => Grant_SE, Grant_W => Grant_SW, Grant_S => Grant_SS, Grant_L => Grant_SL,
Xbar_sel => Xbar_sel_S,
RTS => RTS_S
);
Arbiter_L: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NL , Req_E => Req_EL, Req_W => Req_WL, Req_S => Req_SL, Req_L => '0',
DCTS => DCTS_L, Grant_N => Grant_LN, Grant_E => Grant_LE, Grant_W => Grant_LW, Grant_S => Grant_LS, Grant_L => Grant_LL,
Xbar_sel => Xbar_sel_L,
RTS => RTS_L
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
end;
| gpl-3.0 | 3a942967b20b2861e7fb350ac7a116fe | 0.485304 | 3.267845 | false | false | false | false |
SoCdesign/EHA | RTL/Hand_Shaking/Checkers/Control_part_checkers/Handshaking_FC/FIFO_control_part_checkers/RTL_and_Synthesis/FIFO_control_part_with_checkers_top.vhd | 1 | 6,575 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity FIFO_control_part_with_checkers_top is
port ( DRTS: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
CTS_out: in std_logic;
CTS_in: out std_logic;
empty_out: out std_logic;
full_out: out std_logic;
read_pointer_in: out std_logic_vector(3 downto 0);
write_pointer_in: out std_logic_vector(3 downto 0);
read_en_out: out std_logic;
write_en_out: out std_logic;
-- Checker outputs
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_CTS_in,
err_write_en,
err_not_CTS_in,
err_not_write_en,
err_read_en_mismatch : out std_logic
);
end FIFO_control_part_with_checkers_top;
architecture behavior of FIFO_control_part_with_checkers_top is
component FIFO_control_part_pseudo is
port ( DRTS: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
CTS_out: in std_logic;
CTS_in: out std_logic;
empty_out: out std_logic;
full_out: out std_logic;
read_pointer_in: out std_logic_vector(3 downto 0);
write_pointer_in: out std_logic_vector(3 downto 0);
read_en_out: out std_logic;
write_en_out: out std_logic
);
end component;
component FIFO_control_part_checkers is
port ( DRTS: in std_logic;
CTS_out: in std_logic;
CTS_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
read_pointer_in: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
write_pointer_in: in std_logic_vector(3 downto 0);
empty_out: in std_logic;
full_out: in std_logic;
read_en_out: in std_logic;
write_en_out: in std_logic;
-- Checker outputs
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_CTS_in,
err_write_en,
err_not_CTS_in,
err_not_write_en,
err_read_en_mismatch : out std_logic
);
end component;
signal CTS_in_sig, empty_out_sig, full_out_sig, read_en_out_sig, write_en_out_sig: std_logic;
signal read_pointer_in_sig, write_pointer_in_sig: std_logic_vector(3 downto 0);
begin
CTS_in <= CTS_in_sig;
read_pointer_in <= read_pointer_in_sig;
write_pointer_in <= write_pointer_in_sig;
empty_out <= empty_out_sig;
full_out <= full_out_sig;
read_en_out <= read_en_out_sig;
write_en_out <= write_en_out_sig;
-- FEIFO Control Part instantiation
FIFO_CONTROL_PART: FIFO_control_part_pseudo port map (DRTS => DRTS,
read_en_N => read_en_N, read_en_E => read_en_E, read_en_W => read_en_W, read_en_S => read_en_S, read_en_L => read_en_L,
CTS_out => CTS_out,
read_pointer => read_pointer, write_pointer => write_pointer,
CTS_in => CTS_in_sig, read_pointer_in => read_pointer_in_sig, write_pointer_in => write_pointer_in_sig,
empty_out => empty_out_sig, full_out => full_out_sig,
read_en_out => read_en_out_sig, write_en_out => write_en_out_sig
);
-- Checkers instantiation
CHECKERS: FIFO_control_part_checkers port map (DRTS => DRTS,
CTS_in => CTS_in_sig, CTS_out => CTS_out,
read_en_N => read_en_N, read_en_E => read_en_E, read_en_W => read_en_W, read_en_S => read_en_S, read_en_L => read_en_L,
read_pointer => read_pointer, read_pointer_in => read_pointer_in_sig, write_pointer => write_pointer, write_pointer_in => write_pointer_in_sig,
empty_out => empty_out_sig, full_out => full_out_sig,
read_en_out => read_en_out_sig, write_en_out => write_en_out_sig,
err_write_en_write_pointer => err_write_en_write_pointer,
err_not_write_en_write_pointer => err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => err_read_pointer_write_pointer_full,
err_read_pointer_increment => err_read_pointer_increment,
err_read_pointer_not_increment => err_read_pointer_not_increment,
err_CTS_in => err_CTS_in,
err_write_en => err_write_en,
err_not_CTS_in => err_not_CTS_in,
err_not_write_en => err_not_write_en,
err_read_en_mismatch => err_read_en_mismatch
);
end behavior; | gpl-3.0 | a5088e307e3aeaa5c1580e0e9f3c83da | 0.547529 | 3.420916 | false | false | false | false |
JarrettR/FPGA-Cryptoparty | FPGA/hdl/ipcore_dir/fx2_fifo/simulation/fx2_fifo_pctrl.vhd | 1 | 18,277 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fx2_fifo_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fx2_fifo_pkg.ALL;
ENTITY fx2_fifo_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fx2_fifo_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 100 ns;
PRC_RD_EN <= prc_re_i AFTER 50 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fx2_fifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fx2_fifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
| gpl-3.0 | e91ba324e13e8b18ba2a07afd80babec | 0.508836 | 3.246359 | false | false | false | false |
lnls-dig/dsp-cores | hdl/modules/cordic/addsub.vhd | 1 | 3,341 | -------------------------------------------------------------------------------
-- Title : Dynamic adder/subtractor
-- Project :
-------------------------------------------------------------------------------
-- File : addsub.vhd
-- Author : Aylons <[email protected]>
-- Company :
-- Created : 2014-05-03
-- Last update: 2015-10-15
-- Platform :
-- Standard : VHDL'93/02/08
-------------------------------------------------------------------------------
-- Description: Depening on sub_i, result_o may be a_i + b_i or a_i - b_i.
-- The three widths must all be the same.
-------------------------------------------------------------------------------
-- This file is part of Concordic.
--
-- Concordic is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Concordic is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-05-03 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity addsub is
port (
a_i : in signed;
b_i : in signed;
sub_i : in boolean;
clk_i : in std_logic;
ce_i : in std_logic;
rst_i : in std_logic;
result_o : out signed;
positive_o : out boolean;
negative_o : out boolean
);
end entity addsub;
-------------------------------------------------------------------------------
architecture str of addsub is
constant width : natural := a_i'length;
signal a_1, b_1 : signed(width-1 downto 0) := (others => '0');
signal mux_result : signed (width-1 downto 0) := (others => '0');
begin -- architecture str
assert a_i'length = b_i'length
report "a_i and b_i have different widths"
severity error;
assert a_i'length = result_o'length
report "invalid result_o width"
severity error;
process(clk_i) is
variable result : signed(width-1 downto 0) := (others => '0');
begin
if rising_edge(clk_i) then
if rst_i = '1' then
result_o <= (width-1 downto 0 => '0');
positive_o <= true;
negative_o <= false;
else
if ce_i = '1' then
result := mux_result;
positive_o <= result(result'left) = '0';
negative_o <= result(result'left) = '1';
result_o <= result;
end if;
end if;
end if;
end process;
mux_result <= a_i + b_i when (not sub_i) else a_i - b_i;
end architecture str;
-------------------------------------------------------------------------------
| lgpl-3.0 | b7263e920bc4408b947a441dfd9616b2 | 0.4783 | 4.245235 | false | false | false | false |
SoCdesign/EHA | RTL/Fault_Management/SHMU_prototype/version_2/FIFO_one_hot.vhd | 2 | 6,389 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
DRTS: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
CTS: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end;
architecture behavior of FIFO is
signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(3 downto 0);
signal full, empty: std_logic;
signal read_en, write_en: std_logic;
signal CTS_in, CTS_out: std_logic;
signal FIFO_MEM_1, FIFO_MEM_1_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_2, FIFO_MEM_2_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_3, FIFO_MEM_3_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_4, FIFO_MEM_4_in : std_logic_vector(DATA_WIDTH-1 downto 0);
begin
--------------------------------------------------------------------------------------------
-- block diagram of the FIFO!
-- previous
-- router
-- -- ------------------------------------------
-- | | |
-- TX|--------->| RX Data_out|----> goes to Xbar and LBDR
-- | | |
-- RTS|--------->| DRTS FIFO read_en|<---- Comes from Arbiters (N,E,W,S,L)
-- | | (N,E,W,S,L)|
-- DCTS|<---------| CTS |
-- -- ------------------------------------------
--------------------------------------------------------------------------------------------
-- Hand shake protocol!
--
-- |<-Valid->|
-- | Data |
-- _____ _________ ______
-- RX _____X_________X______
-- DRTS _____|'''''''''|_____
-- CTS __________|''''|_______
--
--------------------------------------------------------------------------------------------
-- circular buffer structure
-- <--- WriteP
-- ---------------------------------
-- | 3 | 2 | 1 | 0 |
-- ---------------------------------
-- <--- readP
--------------------------------------------------------------------------------------------
process (clk, reset)begin
if reset = '0' then
read_pointer <= "0001";
write_pointer <= "0001";
CTS_out<='0';
FIFO_MEM_1 <= (others=>'0');
FIFO_MEM_2 <= (others=>'0');
FIFO_MEM_3 <= (others=>'0');
FIFO_MEM_4 <= (others=>'0');
elsif clk'event and clk = '1' then
write_pointer <= write_pointer_in;
if write_en = '1' then
--write into the memory
FIFO_MEM_1 <= FIFO_MEM_1_in;
FIFO_MEM_2 <= FIFO_MEM_2_in;
FIFO_MEM_3 <= FIFO_MEM_3_in;
FIFO_MEM_4 <= FIFO_MEM_4_in;
end if;
read_pointer <= read_pointer_in;
CTS_out<=CTS_in;
end if;
end process;
-- anything below here is pure combinational
-- combinatorial part
process(RX, write_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
end process;
process(read_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( read_pointer ) is
when "0001" => Data_out <= FIFO_MEM_1;
when "0010" => Data_out <= FIFO_MEM_2;
when "0100" => Data_out <= FIFO_MEM_3;
when "1000" => Data_out <= FIFO_MEM_4;
when others => Data_out <= FIFO_MEM_1;
end case ;
end process;
read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty;
empty_out <= empty;
CTS <= CTS_out;
process(write_en, write_pointer)begin
if write_en = '1'then
write_pointer_in <= write_pointer(2 downto 0)&write_pointer(3);
else
write_pointer_in <= write_pointer;
end if;
end process;
process(read_en, empty, read_pointer)begin
if (read_en = '1' and empty = '0') then
read_pointer_in <= read_pointer(2 downto 0)&read_pointer(3);
else
read_pointer_in <= read_pointer;
end if;
end process;
process(full, DRTS, CTS_out) begin
if CTS_out = '0' and DRTS = '1' and full ='0' then
CTS_in <= '1';
write_en <= '1';
else
CTS_in <= '0';
write_en <= '0';
end if;
end process;
process(write_pointer, read_pointer) begin
if read_pointer = write_pointer then
empty <= '1';
else
empty <= '0';
end if;
-- if write_pointer = read_pointer>>1 then
if write_pointer = read_pointer(0)&read_pointer(3 downto 1) then
full <= '1';
else
full <= '0';
end if;
end process;
end;
| gpl-3.0 | 451cedb10390baa9e7f859cd2c14db7e | 0.425732 | 3.703768 | false | false | false | false |
lnls-dig/dsp-cores | hdl/testbench/part_delta_sigma/part_delta_sigma_tb.vhd | 1 | 12,024 | -------------------------------------------------------------------------------
-- Title : Partial delta/sigma core testbench
-- Project :
-------------------------------------------------------------------------------
-- File : part_delta_sigma_tb.vhd
-- Author : Vitor Finotti Ferreira <finotti@finotti-Inspiron-7520>
-- Company :
-- Created : 2015-07-15
-- Last update: 2022-10-21
-- Platform : Simulation
-- Standard : VHDL 2008
-------------------------------------------------------------------------------
-- Description: Reads BPM antennas' data from file, drives part_delta_sigma
-- core checks its outputs against expected values.
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-07-15 1.0 finotti Created
-- 2022-10-21 2.0 guilherme.ricioli Rewriten
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
use std.env.finish;
use std.textio.all;
entity part_delta_sigma_tb is
generic (
g_BPM_ANTENNAS_FILE : string := "../bpm_a_b_c_d_readings.dat";
g_KX : natural := 1000;
g_KY : natural := 1000;
g_KSUM : natural := 1000;
g_OFFSET_X : integer := 10000;
g_OFFSET_Y : integer := 10000
);
end entity part_delta_sigma_tb;
architecture part_delta_sigma_tb_arch of part_delta_sigma_tb is
-- constants
constant c_SYS_CLOCK_FREQ : natural := 100_000_000;
constant c_WIDTH : natural := 32;
constant c_K_WIDTH : natural := 24;
constant c_OFFSET_WIDTH : natural := 32;
constant c_KX :
std_logic_vector(c_K_WIDTH-1 downto 0) :=
std_logic_vector(to_unsigned(g_KX, c_K_WIDTH));
constant c_KY :
std_logic_vector(c_K_WIDTH-1 downto 0) :=
std_logic_vector(to_unsigned(g_KY, c_K_WIDTH));
constant c_KSUM :
std_logic_vector(c_K_WIDTH-1 downto 0) :=
std_logic_vector(to_unsigned(g_KSUM, c_K_WIDTH));
constant c_OFFSET_X :
std_logic_vector(c_OFFSET_WIDTH-1 downto 0) :=
std_logic_vector(to_unsigned(g_OFFSET_X, c_OFFSET_WIDTH));
constant c_OFFSET_Y :
std_logic_vector(c_OFFSET_WIDTH-1 downto 0) :=
std_logic_vector(to_unsigned(g_OFFSET_Y, c_OFFSET_WIDTH));
-- part_delta_sigma internal div_fixedpoint cores aren't pipelined, so we must
-- wait for its delay to feed another reading
constant c_PDS_HARD_INP_DELAY : natural := 33;
-- signals
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal ce : std_logic := '0';
signal a_b_c_d_valid : std_logic := '0';
signal x_y_q_sum_valid : std_logic := '0';
signal a, b, c, d : std_logic_vector(c_WIDTH-1 downto 0);
signal x, y, q, sum : std_logic_vector(c_WIDTH-1 downto 0);
component part_delta_sigma is
generic (
g_WIDTH : natural;
g_K_WIDTH : natural;
g_OFFSET_WIDTH : natural
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
a_i : in std_logic_vector(g_WIDTH-1 downto 0);
b_i : in std_logic_vector(g_WIDTH-1 downto 0);
c_i : in std_logic_vector(g_WIDTH-1 downto 0);
d_i : in std_logic_vector(g_WIDTH-1 downto 0);
kx_i : in std_logic_vector(g_K_WIDTH-1 downto 0);
ky_i : in std_logic_vector(g_K_WIDTH-1 downto 0);
ksum_i : in std_logic_vector(g_K_WIDTH-1 downto 0);
offset_x_i : in std_logic_vector(g_OFFSET_WIDTH-1 downto 0);
offset_y_i : in std_logic_vector(g_OFFSET_WIDTH-1 downto 0);
ce_i : in std_logic;
valid_i : in std_logic;
x_o : out std_logic_vector(g_WIDTH-1 downto 0);
y_o : out std_logic_vector(g_WIDTH-1 downto 0);
q_o : out std_logic_vector(g_WIDTH-1 downto 0);
sum_o : out std_logic_vector(g_WIDTH-1 downto 0);
valid_o : out std_logic
);
end component part_delta_sigma;
-- procedures
procedure f_gen_clk(constant freq : in natural;
signal clk : inout std_logic) is
begin
loop
wait for (0.5 / real(freq)) * 1 sec;
clk <= not clk;
end loop;
end procedure f_gen_clk;
procedure f_wait_cycles(signal clk : in std_logic;
constant cycles : natural) is
begin
for i in 1 to cycles loop
wait until rising_edge(clk);
end loop;
end procedure f_wait_cycles;
procedure f_wait_clocked_signal(signal clk : in std_logic;
signal sig : in std_logic;
val : in std_logic;
timeout : in natural := 2147483647) is
variable cnt : natural := timeout;
begin
while sig /= val and cnt > 0 loop
wait until rising_edge(clk);
cnt := cnt - 1;
end loop;
end procedure f_wait_clocked_signal;
-- functions
-- calculates fixed point position based on pds_scaling_stage internal
-- multiplications
function f_calc_fp_pos (a_int_width : natural;
b_int_width : natural;
p_width : natural)
return integer is
variable v_mult_int_width : natural := a_int_width + b_int_width;
variable v_ret : integer;
begin
v_ret := (p_width - v_mult_int_width) + 1;
return v_ret;
end f_calc_fp_pos;
function f_fp_to_real (arg : std_logic_vector; fp_pos : integer)
return real is
variable v_ret : real := real(to_integer(signed(arg)));
begin
v_ret := v_ret/(2.0**(fp_pos));
return v_ret;
end f_fp_to_real;
begin
f_gen_clk(c_SYS_CLOCK_FREQ, clk);
-- main process
process
file fin : text;
variable lin : line;
variable meas_idx : natural := 0;
variable v_a, v_b, v_c, v_d : integer;
begin
-- resetting cores
report "resetting cores"
severity note;
rst <= '1';
f_wait_cycles(clk, 1);
rst <= '0';
f_wait_cycles(clk, 10);
file_open(fin, g_BPM_ANTENNAS_FILE, read_mode);
f_wait_clocked_signal(clk, ce, '0');
while not endfile(fin)
loop
readline(fin, lin); read(lin, v_a);
readline(fin, lin); read(lin, v_b);
readline(fin, lin); read(lin, v_c);
readline(fin, lin); read(lin, v_d);
-- driving a, b, c and d
a <= std_logic_vector(to_signed(v_a, c_WIDTH));
b <= std_logic_vector(to_signed(v_b, c_WIDTH));
c <= std_logic_vector(to_signed(v_c, c_WIDTH));
d <= std_logic_vector(to_signed(v_d, c_WIDTH));
a_b_c_d_valid <= '1';
-- waiting for a ce pulse
f_wait_clocked_signal(clk, ce, '1');
f_wait_clocked_signal(clk, ce, '0');
a_b_c_d_valid <= '0';
f_wait_cycles(ce, c_PDS_HARD_INP_DELAY);
meas_idx := meas_idx + 1;
end loop;
f_wait_cycles(ce, c_PDS_HARD_INP_DELAY);
report "all good!"
severity note;
finish;
end process;
-- process to check outputs
check: process
file fin : text;
variable lin : line;
variable v_a, v_b, v_c, v_d : real := 0.0;
variable meas_idx : natural := 0;
variable v_kx : real := real(to_integer(unsigned(c_KX)));
variable v_ky : real := real(to_integer(unsigned(c_KY)));
variable v_ksum : real := real(to_integer(unsigned(c_KSUM)));
variable v_offset_x : real := real(to_integer(signed(c_OFFSET_X)));
variable v_offset_y : real := real(to_integer(signed(c_OFFSET_Y)));
variable v_sum_ac, v_sum_bd, v_diff_ac_over_sum_ac, v_diff_bd_over_sum_bd,
v_sum_not_scaled : real := 0.0;
variable v_x, v_y, v_q, v_sum : real := 0.0;
variable v_x_y_fp_pos : integer := f_calc_fp_pos(1, c_K_WIDTH, c_WIDTH);
variable v_q_fp_pos : integer := c_WIDTH-1;
variable v_sum_fp_pos : integer := f_calc_fp_pos(c_WIDTH, c_K_WIDTH, c_WIDTH);
variable v_expec_x, v_expec_y, v_expec_q, v_expec_sum : real := 0.0;
variable v_err_x, v_err_y, v_err_q, v_err_sum : real := 0.0;
begin
file_open(fin, g_BPM_ANTENNAS_FILE, read_mode);
f_wait_clocked_signal(clk, x_y_q_sum_valid, '0');
loop
-- waiting for x, y, q and sum valid pulse
f_wait_clocked_signal(clk, x_y_q_sum_valid, '1');
f_wait_clocked_signal(clk, x_y_q_sum_valid, '0');
v_x := f_fp_to_real(x, v_x_y_fp_pos);
v_y := f_fp_to_real(y, v_x_y_fp_pos);
v_q := f_fp_to_real(q, v_q_fp_pos);
v_sum := f_fp_to_real(sum, v_sum_fp_pos);
readline(fin, lin); read(lin, v_a);
readline(fin, lin); read(lin, v_b);
readline(fin, lin); read(lin, v_c);
readline(fin, lin); read(lin, v_d);
v_sum_ac := (v_a + v_c);
v_sum_bd := (v_b + v_d);
v_diff_ac_over_sum_ac := (v_a - v_c)/(v_a + v_c);
v_diff_bd_over_sum_bd := (v_b - v_d)/(v_b + v_d);
v_sum_not_scaled := (v_a + v_b + v_c + v_d);
-- computing expected values
v_expec_x := v_kx*(0.5*v_diff_ac_over_sum_ac - 0.5*v_diff_bd_over_sum_bd);
v_expec_x := v_expec_x - v_offset_x;
v_expec_y := v_ky*(0.5*v_diff_ac_over_sum_ac + 0.5*v_diff_bd_over_sum_bd);
v_expec_y := v_expec_y - v_offset_y;
v_expec_q := (v_sum_ac - v_sum_bd)/v_sum_not_scaled;
v_expec_sum := v_ksum*v_sum_not_scaled;
v_expec_sum := v_ksum*v_sum_not_scaled;
-- checking x, y, q and sum against expected values
v_err_x := abs(v_x/v_expec_x - 1.0);
v_err_y := abs(v_y/v_expec_y - 1.0);
v_err_q := abs(v_q/v_expec_q - 1.0);
v_err_sum := abs(v_sum/v_expec_sum - 1.0);
if v_err_x > 0.01 then
report "wrong x: " & to_string(v_x) & " (expected: " &
to_string(v_expec_x) & ") on measurement " & natural'image(meas_idx)
severity error;
elsif v_err_y > 0.01 then
report "wrong y: " & to_string(v_y) & " (expected: " &
to_string(v_expec_y) & ") on measurement " & natural'image(meas_idx)
severity error;
-- TODO: sum has its 23 lsbs discarded; how to properly check it?
--elsif v_err_sum > 0.1 then
-- report "wrong sum: " & to_string(v_sum) & " (expected: " &
-- to_string(v_expec_sum) & ") on measurement " & natural'image(meas_idx) & " " & to_string(v_err_sum)
-- severity note;
elsif v_err_q > 0.01 then
report "wrong q: " & to_string(v_q) & " (expected: " &
to_string(v_expec_q) & ") on measurement " & natural'image(meas_idx)
severity error;
end if;
f_wait_cycles(clk, 1);
meas_idx := meas_idx + 1;
end loop;
end process check;
-- process to pulse ce
p_ce_gen: process
begin
f_wait_cycles(clk, 10);
ce <= '1';
f_wait_cycles(clk, 1);
ce <= '0';
end process p_ce_gen;
-- components
cmp_part_delta_sigma : part_delta_sigma
generic map (
g_WIDTH => c_WIDTH,
g_K_WIDTH => c_K_WIDTH,
g_OFFSET_WIDTH => c_OFFSET_WIDTH
)
port map (
clk_i => clk,
rst_i => rst,
a_i => a,
b_i => b,
c_i => c,
d_i => d,
kx_i => c_KX,
ky_i => c_KY,
ksum_i => c_KSUM,
offset_x_i => c_OFFSET_X,
offset_y_i => c_OFFSET_Y,
ce_i => ce,
valid_i => a_b_c_d_valid,
x_o => x,
y_o => y,
q_o => q,
sum_o => sum,
valid_o => x_y_q_sum_valid
);
end architecture part_delta_sigma_tb_arch;
| lgpl-3.0 | 51bf4f95b922358fa6588822a88c6c5c | 0.51655 | 3.108583 | false | false | false | false |
SoCdesign/EHA | RTL/Credit_Based/Credit_Based_FC/Router_32_bit_credit_based_parity_LV_compatible.vhd | 1 | 17,781 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_credit_based_parity_lv is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 60;
Cx_rst : integer := 10;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
------------------------- lV network port
-- the router just sends the packets out. no need for any incomming packets support.
-- the output of the LV network will be connected to the PEs
credit_in_LV : in std_logic;
valid_out_LV : out std_logic;
TX_LV: out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end router_credit_based_parity_lv;
architecture behavior of router_credit_based_parity_lv is
COMPONENT PACKETIZER_LV is
generic (
DATA_WIDTH: integer := 13;
current_address : integer := 0;
SHMU_address : integer := 0
);
port (
reset, clk: in std_logic;
faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L: in std_logic;
healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L: in std_logic;
credit_in_LV: in std_logic;
valid_out_LV : out std_logic;
TX_LV: out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end COMPONENT;
COMPONENT parity_checker_packet_detector is
generic(DATA_WIDTH : integer := 32
);
port(
reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
faulty_packet, healthy_packet: out std_logic
);
end COMPONENT;
COMPONENT FIFO_credit_based
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
COMPONENT allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic
);
end COMPONENT;
COMPONENT LBDR is
generic (
cur_addr_rst: integer := 0;
Rxy_rst: integer := 60;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
signal faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L: std_logic;
signal healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L: std_logic;
begin
-- packetizer for LV network
packetizer: PACKETIZER_LV generic map(DATA_WIDTH => 13, current_address => current_address, SHMU_address => 0)
port map (reset => reset, clk => clk,
faulty_packet_N => faulty_packet_N, faulty_packet_E => faulty_packet_E, faulty_packet_W => faulty_packet_W,
faulty_packet_S => faulty_packet_S, faulty_packet_L => faulty_packet_L,
healthy_packet_N => healthy_packet_N, healthy_packet_E => healthy_packet_E, healthy_packet_W => healthy_packet_W,
healthy_packet_S => healthy_packet_S, healthy_packet_L => healthy_packet_L,
credit_in_LV => credit_in_LV,
valid_out_LV => valid_out_LV,
TX_LV => TX_LV);
-- all the parity_checkers
PC_N: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_N, valid_in =>valid_in_N, faulty_packet => faulty_packet_N , healthy_packet => healthy_packet_N);
PC_E: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_E, valid_in =>valid_in_E, faulty_packet => faulty_packet_E , healthy_packet => healthy_packet_E);
PC_W: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_W, valid_in =>valid_in_W, faulty_packet => faulty_packet_W , healthy_packet => healthy_packet_W);
PC_S: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_S, valid_in =>valid_in_S, faulty_packet => faulty_packet_S , healthy_packet => healthy_packet_S);
PC_L: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_L, valid_in =>valid_in_L, faulty_packet => faulty_packet_L , healthy_packet => healthy_packet_L);
-- all the FIFOs
FIFO_N: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_N, valid_in => valid_in_N,
read_en_N => '0', read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
credit_out => credit_out_N, empty_out => empty_N, Data_out => FIFO_D_out_N);
FIFO_E: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_E, valid_in => valid_in_E,
read_en_N => Grant_NE, read_en_E =>'0', read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
credit_out => credit_out_E, empty_out => empty_E, Data_out => FIFO_D_out_E);
FIFO_W: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_W, valid_in => valid_in_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>'0', read_en_S =>Grant_SW, read_en_L =>Grant_LW,
credit_out => credit_out_W, empty_out => empty_W, Data_out => FIFO_D_out_W);
FIFO_S: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_S, valid_in => valid_in_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>'0', read_en_L =>Grant_LS,
credit_out => credit_out_S, empty_out => empty_S, Data_out => FIFO_D_out_S);
FIFO_L: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_L, valid_in => valid_in_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>'0',
credit_out => credit_out_L, empty_out => empty_L, Data_out => FIFO_D_out_L);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the LBDRs
LBDR_N: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N, flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
grant_N => '0', grant_E =>Grant_EN, grant_W => Grant_WN, grant_S=>Grant_SN, grant_L =>Grant_LN,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL);
LBDR_E: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E, flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
grant_N => Grant_NE, grant_E =>'0', grant_W => Grant_WE, grant_S=>Grant_SE, grant_L =>Grant_LE,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL);
LBDR_W: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W, flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
grant_N => Grant_NW, grant_E =>Grant_EW, grant_W =>'0' ,grant_S=>Grant_SW, grant_L =>Grant_LW,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL);
LBDR_S: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S, flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
grant_N => Grant_NS, grant_E =>Grant_ES, grant_W =>Grant_WS ,grant_S=>'0', grant_L =>Grant_LS,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL);
LBDR_L: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L, flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
grant_N => Grant_NL, grant_E =>Grant_EL, grant_W => Grant_WL,grant_S=>Grant_SL, grant_L =>'0',
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- switch allocator
allocator_unit: allocator port map ( reset => reset, clk => clk,
-- flow control
credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L,
-- requests from the LBDRS
req_N_N => '0', req_N_E => Req_NE, req_N_W => Req_NW, req_N_S => Req_NS, req_N_L => Req_NL,
req_E_N => Req_EN, req_E_E => '0', req_E_W => Req_EW, req_E_S => Req_ES, req_E_L => Req_EL,
req_W_N => Req_WN, req_W_E => Req_WE, req_W_W => '0', req_W_S => Req_WS, req_W_L => Req_WL,
req_S_N => Req_SN, req_S_E => Req_SE, req_S_W => Req_SW, req_S_S => '0', req_S_L => Req_SL,
req_L_N => Req_LN, req_L_E => Req_LE, req_L_W => Req_LW, req_L_S => Req_LS, req_L_L => '0',
empty_N => empty_N, empty_E => empty_E, empty_w => empty_W, empty_S => empty_S, empty_L => empty_L,
valid_N => valid_out_N, valid_E => valid_out_E, valid_W => valid_out_W, valid_S => valid_out_S, valid_L => valid_out_L,
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
grant_N_N => Grant_NN, grant_N_E => Grant_NE, grant_N_W => Grant_NW, grant_N_S => Grant_NS, grant_N_L => Grant_NL,
grant_E_N => Grant_EN, grant_E_E => Grant_EE, grant_E_W => Grant_EW, grant_E_S => Grant_ES, grant_E_L => Grant_EL,
grant_W_N => Grant_WN, grant_W_E => Grant_WE, grant_W_W => Grant_WW, grant_W_S => Grant_WS, grant_W_L => Grant_WL,
grant_S_N => Grant_SN, grant_S_E => Grant_SE, grant_S_W => Grant_SW, grant_S_S => Grant_SS, grant_S_L => Grant_SL,
grant_L_N => Grant_LN, grant_L_E => Grant_LE, grant_L_W => Grant_LW, grant_L_S => Grant_LS, grant_L_L => Grant_LL
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbar select_signals
Xbar_sel_N <= '0' & Grant_NE & Grant_NW & Grant_NS & Grant_NL;
Xbar_sel_E <= Grant_EN & '0' & Grant_EW & Grant_ES & Grant_EL;
Xbar_sel_W <= Grant_WN & Grant_WE & '0' & Grant_WS & Grant_WL;
Xbar_sel_S <= Grant_SN & Grant_SE & Grant_SW & '0' & Grant_SL;
Xbar_sel_L <= Grant_LN & Grant_LE & Grant_LW & Grant_LS & '0';
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
end;
| gpl-3.0 | 7dc940da9af6fe2cdd737abbfcdab15f | 0.544176 | 3.00304 | false | false | false | false |
hanyazou/vivado-ws | playpen/dvi2vga_nofilter/dvi2vga_nofilter.srcs/sources_1/bd/design_1/ip/design_1_dvi2rgb_0_1/synth/design_1_dvi2rgb_0_1.vhd | 1 | 7,287 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: digilentinc.com:ip:dvi2rgb:1.5
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_dvi2rgb_0_1 IS
PORT (
TMDS_Clk_p : IN STD_LOGIC;
TMDS_Clk_n : IN STD_LOGIC;
TMDS_Data_p : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
TMDS_Data_n : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
RefClk : IN STD_LOGIC;
aRst_n : IN STD_LOGIC;
vid_pData : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
vid_pVDE : OUT STD_LOGIC;
vid_pHSync : OUT STD_LOGIC;
vid_pVSync : OUT STD_LOGIC;
PixelClk : OUT STD_LOGIC;
aPixelClkLckd : OUT STD_LOGIC;
DDC_SDA_I : IN STD_LOGIC;
DDC_SDA_O : OUT STD_LOGIC;
DDC_SDA_T : OUT STD_LOGIC;
DDC_SCL_I : IN STD_LOGIC;
DDC_SCL_O : OUT STD_LOGIC;
DDC_SCL_T : OUT STD_LOGIC;
pRst_n : IN STD_LOGIC
);
END design_1_dvi2rgb_0_1;
ARCHITECTURE design_1_dvi2rgb_0_1_arch OF design_1_dvi2rgb_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_dvi2rgb_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT dvi2rgb IS
GENERIC (
kEmulateDDC : BOOLEAN;
kRstActiveHigh : BOOLEAN;
kClkRange : INTEGER;
kIDLY_TapValuePs : INTEGER;
kIDLY_TapWidth : INTEGER;
kAddBUFG : BOOLEAN
);
PORT (
TMDS_Clk_p : IN STD_LOGIC;
TMDS_Clk_n : IN STD_LOGIC;
TMDS_Data_p : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
TMDS_Data_n : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
RefClk : IN STD_LOGIC;
aRst : IN STD_LOGIC;
aRst_n : IN STD_LOGIC;
vid_pData : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
vid_pVDE : OUT STD_LOGIC;
vid_pHSync : OUT STD_LOGIC;
vid_pVSync : OUT STD_LOGIC;
PixelClk : OUT STD_LOGIC;
SerialClk : OUT STD_LOGIC;
aPixelClkLckd : OUT STD_LOGIC;
DDC_SDA_I : IN STD_LOGIC;
DDC_SDA_O : OUT STD_LOGIC;
DDC_SDA_T : OUT STD_LOGIC;
DDC_SCL_I : IN STD_LOGIC;
DDC_SCL_O : OUT STD_LOGIC;
DDC_SCL_T : OUT STD_LOGIC;
pRst : IN STD_LOGIC;
pRst_n : IN STD_LOGIC
);
END COMPONENT dvi2rgb;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_dvi2rgb_0_1_arch: ARCHITECTURE IS "dvi2rgb,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_dvi2rgb_0_1_arch : ARCHITECTURE IS "design_1_dvi2rgb_0_1,dvi2rgb,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF TMDS_Clk_p: SIGNAL IS "digilentinc.com:interface:tmds:1.0 TMDS CLK_P";
ATTRIBUTE X_INTERFACE_INFO OF TMDS_Clk_n: SIGNAL IS "digilentinc.com:interface:tmds:1.0 TMDS CLK_N";
ATTRIBUTE X_INTERFACE_INFO OF TMDS_Data_p: SIGNAL IS "digilentinc.com:interface:tmds:1.0 TMDS DATA_P";
ATTRIBUTE X_INTERFACE_INFO OF TMDS_Data_n: SIGNAL IS "digilentinc.com:interface:tmds:1.0 TMDS DATA_N";
ATTRIBUTE X_INTERFACE_INFO OF RefClk: SIGNAL IS "xilinx.com:signal:clock:1.0 RefClk CLK";
ATTRIBUTE X_INTERFACE_INFO OF aRst_n: SIGNAL IS "xilinx.com:signal:reset:1.0 AsyncRst_n RST";
ATTRIBUTE X_INTERFACE_INFO OF vid_pData: SIGNAL IS "xilinx.com:interface:vid_io:1.0 RGB DATA";
ATTRIBUTE X_INTERFACE_INFO OF vid_pVDE: SIGNAL IS "xilinx.com:interface:vid_io:1.0 RGB ACTIVE_VIDEO";
ATTRIBUTE X_INTERFACE_INFO OF vid_pHSync: SIGNAL IS "xilinx.com:interface:vid_io:1.0 RGB HSYNC";
ATTRIBUTE X_INTERFACE_INFO OF vid_pVSync: SIGNAL IS "xilinx.com:interface:vid_io:1.0 RGB VSYNC";
ATTRIBUTE X_INTERFACE_INFO OF PixelClk: SIGNAL IS "xilinx.com:signal:clock:1.0 PixelClk CLK";
ATTRIBUTE X_INTERFACE_INFO OF DDC_SDA_I: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SDA_I";
ATTRIBUTE X_INTERFACE_INFO OF DDC_SDA_O: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SDA_O";
ATTRIBUTE X_INTERFACE_INFO OF DDC_SDA_T: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SDA_T";
ATTRIBUTE X_INTERFACE_INFO OF DDC_SCL_I: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SCL_I";
ATTRIBUTE X_INTERFACE_INFO OF DDC_SCL_O: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SCL_O";
ATTRIBUTE X_INTERFACE_INFO OF DDC_SCL_T: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SCL_T";
ATTRIBUTE X_INTERFACE_INFO OF pRst_n: SIGNAL IS "xilinx.com:signal:reset:1.0 SyncRst_n RST";
BEGIN
U0 : dvi2rgb
GENERIC MAP (
kEmulateDDC => true,
kRstActiveHigh => false,
kClkRange => 2,
kIDLY_TapValuePs => 78,
kIDLY_TapWidth => 5,
kAddBUFG => true
)
PORT MAP (
TMDS_Clk_p => TMDS_Clk_p,
TMDS_Clk_n => TMDS_Clk_n,
TMDS_Data_p => TMDS_Data_p,
TMDS_Data_n => TMDS_Data_n,
RefClk => RefClk,
aRst => '0',
aRst_n => aRst_n,
vid_pData => vid_pData,
vid_pVDE => vid_pVDE,
vid_pHSync => vid_pHSync,
vid_pVSync => vid_pVSync,
PixelClk => PixelClk,
aPixelClkLckd => aPixelClkLckd,
DDC_SDA_I => DDC_SDA_I,
DDC_SDA_O => DDC_SDA_O,
DDC_SDA_T => DDC_SDA_T,
DDC_SCL_I => DDC_SCL_I,
DDC_SCL_O => DDC_SCL_O,
DDC_SCL_T => DDC_SCL_T,
pRst => '0',
pRst_n => pRst_n
);
END design_1_dvi2rgb_0_1_arch;
| mit | a86bf480aa376aae9fdd16c1bda8d3b2 | 0.688898 | 3.44051 | false | false | false | false |
SoCdesign/EHA | RTL/Fault_Management/Fault_management_network/arbiter_out.vhd | 1 | 3,929 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity arbiter_out is
port (
reset: in std_logic;
clk: in std_logic;
X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y :in std_logic; -- From LBDR modules
credit: in std_logic_vector(1 downto 0);
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : out std_logic -- Grants given to LBDR requests (encoded as one-hot)
);
end;
architecture behavior of arbiter_out is
TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SIGNAL state, state_in : STATE_TYPE := IDLE;
begin
process (clk, reset)begin
if reset = '0' then
state <= IDLE;
elsif clk'event and clk ='1'then
state <= state_in;
end if;
end process;
-- anything below here is pure combinational
process(state, X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y, credit) begin
grant_Y_N <= '0';
grant_Y_E <= '0';
grant_Y_W <= '0';
grant_Y_S <= '0';
grant_Y_L <= '0';
case state is
when IDLE =>
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when North =>
if credit /= "00" then
grant_Y_N <= '1';
end if;
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when East =>
if credit /= "00" then
grant_Y_E <= '1';
end if;
if X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
else
state_in <= IDLE;
end if;
when West =>
if credit /= "00" then
grant_Y_W <= '1';
end if;
if X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
else
state_in <= IDLE;
end if;
when South =>
if credit /= "00" then
grant_Y_S <= '1';
end if;
if X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
else
state_in <= IDLE;
end if;
when others =>
if credit /= "00" then
grant_Y_L <= '1';
end if;
if X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
else
state_in <= IDLE;
end if;
end case;
end process;
end;
| gpl-3.0 | 7b30ba9568e68bdb9d5d15b9e745f0bc | 0.420463 | 3.416522 | false | false | false | false |
TUM-LIS/faultify | hardware/testcases/FIR/fpga_sim/xpsLibraryPath/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/vhdl/user_logic.vhd | 1 | 29,241 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Fri May 16 15:25:24 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
faultify_clk_fast : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
component faultify_top
generic (
numInj : integer;
numIn : integer;
numOut : integer);
port (
aclk : in std_logic;
arst_n : in std_logic;
clk : in std_logic;
clk_x32 : in std_logic;
awvalid : in std_logic;
awaddr : in std_logic_vector(31 downto 0);
wvalid : in std_logic;
wdata : in std_logic_vector(31 downto 0);
arvalid : in std_logic;
araddr : in std_logic_vector(31 downto 0);
rvalid : out std_logic;
rdata : out std_logic_vector(31 downto 0));
end component;
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal register_write_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal register_read_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal register_write_address : std_logic_vector(C_NUM_REG-1 downto 0);
signal register_read_address : std_logic_vector(C_NUM_REG-1 downto 0);
signal slv_reg_write_sel : std_logic_vector(31 downto 0);
signal slv_reg_read_sel : std_logic_vector(31 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal faultify_read_valid : std_logic;
signal faultify_read_address_valid : std_logic;
signal faultify_read_address : std_logic_vector(31 downto 0);
signal faultify_write_valid : std_logic;
signal counter, divide : integer := 0;
signal faultify_clk_slow_i : std_logic;
begin
slv_reg_write_sel <= Bus2IP_WrCE(31 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(31 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12) or Bus2IP_WrCE(13) or Bus2IP_WrCE(14) or Bus2IP_WrCE(15) or Bus2IP_WrCE(16) or Bus2IP_WrCE(17) or Bus2IP_WrCE(18) or Bus2IP_WrCE(19) or Bus2IP_WrCE(20) or Bus2IP_WrCE(21) or Bus2IP_WrCE(22) or Bus2IP_WrCE(23) or Bus2IP_WrCE(24) or Bus2IP_WrCE(25) or Bus2IP_WrCE(26) or Bus2IP_WrCE(27) or Bus2IP_WrCE(28) or Bus2IP_WrCE(29) or Bus2IP_WrCE(30) or Bus2IP_WrCE(31);
slv_read_ack <= faultify_read_valid;
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process(Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
register_write_data <= (others => '0');
register_write_address <= (others => '0');
faultify_write_valid <= '0';
else
faultify_write_valid <= slv_write_ack;
case slv_reg_write_sel is
when "10000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(0, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "01000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(1, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00100000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(2, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00010000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(3, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00001000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(4, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000100000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(5, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000010000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(6, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000001000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(7, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000100000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(8, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000010000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(9, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000001000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(10, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000100000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(11, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000010000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(12, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000001000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(13, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000100000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(14, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000010000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(15, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000001000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(16, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000100000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(17, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000010000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(18, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000001000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(19, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000100000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(20, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000010000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(21, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000001000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(22, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000100000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(23, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000010000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(24, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000001000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(25, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(26, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(27, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(28, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(29, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(30, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(31, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process(slv_reg_read_sel, faultify_read_valid) is
begin
faultify_read_address_valid <= '1';
case slv_reg_read_sel is
when "10000000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(0, 32));
when "01000000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(1, 32));
when "00100000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(2, 32));
when "00010000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(3, 32));
when "00001000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(4, 32));
when "00000100000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(5, 32));
when "00000010000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(6, 32));
when "00000001000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(7, 32));
when "00000000100000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(8, 32));
when "00000000010000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(9, 32));
when "00000000001000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(10, 32));
when "00000000000100000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(11, 32));
when "00000000000010000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(12, 32));
when "00000000000001000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(13, 32));
when "00000000000000100000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(14, 32));
when "00000000000000010000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(15, 32));
when "00000000000000001000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(16, 32));
when "00000000000000000100000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(17, 32));
when "00000000000000000010000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(18, 32));
when "00000000000000000001000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(19, 32));
when "00000000000000000000100000000000" => faultify_read_address <= std_logic_vector(to_unsigned(20, 32));
when "00000000000000000000010000000000" => faultify_read_address <= std_logic_vector(to_unsigned(21, 32));
when "00000000000000000000001000000000" => faultify_read_address <= std_logic_vector(to_unsigned(22, 32));
when "00000000000000000000000100000000" => faultify_read_address <= std_logic_vector(to_unsigned(23, 32));
when "00000000000000000000000010000000" => faultify_read_address <= std_logic_vector(to_unsigned(24, 32));
when "00000000000000000000000001000000" => faultify_read_address <= std_logic_vector(to_unsigned(25, 32));
when "00000000000000000000000000100000" => faultify_read_address <= std_logic_vector(to_unsigned(26, 32));
when "00000000000000000000000000010000" => faultify_read_address <= std_logic_vector(to_unsigned(27, 32));
when "00000000000000000000000000001000" => faultify_read_address <= std_logic_vector(to_unsigned(28, 32));
when "00000000000000000000000000000100" => faultify_read_address <= std_logic_vector(to_unsigned(29, 32));
when "00000000000000000000000000000010" => faultify_read_address <= std_logic_vector(to_unsigned(30, 32));
when "00000000000000000000000000000001" => faultify_read_address <= std_logic_vector(to_unsigned(31, 32));
when others => faultify_read_address <= (others => '0');
faultify_read_address_valid <= '0';
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= register_read_data when faultify_read_valid = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
-----------------------------------------------------------------------------
-- clock divider 32 -> 1
-----------------------------------------------------------------------------
divide <= 32;
process(Bus2IP_Clk, Bus2IP_Resetn)
begin
if Bus2IP_Resetn = '0' then
counter <= 0;
faultify_clk_slow_i <= '0';
elsif(rising_edge(Bus2IP_Clk)) then
if(counter < divide/2-1) then
counter <= counter + 1;
faultify_clk_slow_i <= '0';
elsif(counter < divide-1) then
counter <= counter + 1;
faultify_clk_slow_i <= '1';
else
faultify_clk_slow_i <= '0';
counter <= 0;
end if;
end if;
end process;
faultify_top_1 : faultify_top
generic map (
numInj => 105,
numIn => 8,
numOut => 8)
port map (
aclk => Bus2IP_Clk,
arst_n => Bus2IP_Resetn,
clk => faultify_clk_slow_i,
clk_x32 => Bus2IP_Clk,
awvalid => faultify_write_valid,
awaddr => register_write_address,
wvalid => faultify_write_valid,
wdata => register_write_data,
arvalid => faultify_read_address_valid,
araddr => faultify_read_address,
rvalid => faultify_read_valid,
rdata => register_read_data);
end IMP;
| gpl-2.0 | 87cd1fe6b66125682261f75561128901 | 0.539277 | 4.022699 | false | false | false | false |
SoCdesign/EHA | RTL/Fault_Management/Fault_management_network/Router_LV_CB.vhd | 1 | 15,055 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_LV is
generic (
DATA_WIDTH: integer := 11;
current_address : integer := 0;
Rxy_rst : integer := 60;
Cx_rst : integer := 10;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end router_LV;
architecture behavior of router_LV is
COMPONENT FIFO_LV
generic (
DATA_WIDTH: integer := 11
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
COMPONENT allocator_LV is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic
);
end COMPONENT;
COMPONENT LBDR_LV is
generic (
cur_addr_rst: integer := 0;
Rxy_rst: integer := 60;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
empty: in std_logic;
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
packet_info: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic
);
end COMPONENT;
COMPONENT XBAR_LV is
generic (
DATA_WIDTH: integer := 11
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
begin
-------------------------------------------------------------------------------------------
--Packet format
-- packet info__ __________flit type
-- ______________________________________________|____|__
-- |________4_________|__________4__________|_1_|_1_|__3__|
-- source address destination |
-- address |____healthy/faulty
--
-------------------------------------------------------------------------------------------
-- all the FIFOs
FIFO_N: FIFO_LV
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_N, valid_in => valid_in_N,
read_en_N => '0', read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
credit_out => credit_out_N, empty_out => empty_N, Data_out => FIFO_D_out_N);
FIFO_E: FIFO_LV
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_E, valid_in => valid_in_E,
read_en_N => Grant_NE, read_en_E =>'0', read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
credit_out => credit_out_E, empty_out => empty_E, Data_out => FIFO_D_out_E);
FIFO_W: FIFO_LV
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_W, valid_in => valid_in_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>'0', read_en_S =>Grant_SW, read_en_L =>Grant_LW,
credit_out => credit_out_W, empty_out => empty_W, Data_out => FIFO_D_out_W);
FIFO_S: FIFO_LV
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_S, valid_in => valid_in_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>'0', read_en_L =>Grant_LS,
credit_out => credit_out_S, empty_out => empty_S, Data_out => FIFO_D_out_S);
FIFO_L: FIFO_LV
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_L, valid_in => valid_in_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L => Grant_LL,
credit_out => credit_out_L, empty_out => empty_L, Data_out => FIFO_D_out_L);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the LBDRs
LBDR_N: LBDR_LV generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N, dst_addr=> FIFO_D_out_N(3+NoC_size-1 downto 3) , packet_info => FIFO_D_out_N(3), flit_type=> FIFO_D_out_N(2 downto 0),
grant_N => '0', grant_E =>Grant_EN, grant_W => Grant_WN, grant_S=>Grant_SN, grant_L =>Grant_LN,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL);
LBDR_E: LBDR_LV generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E, dst_addr=> FIFO_D_out_E(3+NoC_size-1 downto 3) , packet_info => FIFO_D_out_E(3), flit_type=> FIFO_D_out_E(2 downto 0),
grant_N => Grant_NE, grant_E =>'0', grant_W => Grant_WE, grant_S=>Grant_SE, grant_L =>Grant_LE,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL);
LBDR_W: LBDR_LV generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W, dst_addr=> FIFO_D_out_W(3+NoC_size-1 downto 3) , packet_info => FIFO_D_out_W(3), flit_type=> FIFO_D_out_W(2 downto 0),
grant_N => Grant_NW, grant_E =>Grant_EW, grant_W =>'0' ,grant_S=>Grant_SW, grant_L =>Grant_LW,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL);
LBDR_S: LBDR_LV generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S, dst_addr=> FIFO_D_out_S(3+NoC_size-1 downto 3) , packet_info => FIFO_D_out_S(3), flit_type=> FIFO_D_out_S(2 downto 0),
grant_N => Grant_NS, grant_E =>Grant_ES, grant_W =>Grant_WS ,grant_S=>'0', grant_L =>Grant_LS,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL);
LBDR_L: LBDR_LV generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L, dst_addr=> FIFO_D_out_L(3+NoC_size-1 downto 3) , packet_info => FIFO_D_out_L(3), flit_type=> FIFO_D_out_L(2 downto 0),
grant_N => Grant_NL, grant_E =>Grant_EL, grant_W => Grant_WL,grant_S=>Grant_SL, grant_L => Grant_LL,
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- switch allocator
allocator_unit: allocator_LV port map ( reset => reset, clk => clk,
-- flow control
credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L,
-- requests from the LBDRS
req_N_N => '0', req_N_E => Req_NE, req_N_W => Req_NW, req_N_S => Req_NS, req_N_L => Req_NL,
req_E_N => Req_EN, req_E_E => '0', req_E_W => Req_EW, req_E_S => Req_ES, req_E_L => Req_EL,
req_W_N => Req_WN, req_W_E => Req_WE, req_W_W => '0', req_W_S => Req_WS, req_W_L => Req_WL,
req_S_N => Req_SN, req_S_E => Req_SE, req_S_W => Req_SW, req_S_S => '0', req_S_L => Req_SL,
req_L_N => Req_LN, req_L_E => Req_LE, req_L_W => Req_LW, req_L_S => Req_LS, req_L_L => Req_LL,
empty_N => empty_N, empty_E => empty_E, empty_w => empty_W, empty_S => empty_S, empty_L => empty_L,
valid_N => valid_out_N, valid_E => valid_out_E, valid_W => valid_out_W, valid_S => valid_out_S, valid_L => valid_out_L,
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
grant_N_N => Grant_NN, grant_N_E => Grant_NE, grant_N_W => Grant_NW, grant_N_S => Grant_NS, grant_N_L => Grant_NL,
grant_E_N => Grant_EN, grant_E_E => Grant_EE, grant_E_W => Grant_EW, grant_E_S => Grant_ES, grant_E_L => Grant_EL,
grant_W_N => Grant_WN, grant_W_E => Grant_WE, grant_W_W => Grant_WW, grant_W_S => Grant_WS, grant_W_L => Grant_WL,
grant_S_N => Grant_SN, grant_S_E => Grant_SE, grant_S_W => Grant_SW, grant_S_S => Grant_SS, grant_S_L => Grant_SL,
grant_L_N => Grant_LN, grant_L_E => Grant_LE, grant_L_W => Grant_LW, grant_L_S => Grant_LS, grant_L_L => Grant_LL
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbar select_signals
Xbar_sel_N <= '0' & Grant_NE & Grant_NW & Grant_NS & Grant_NL;
Xbar_sel_E <= Grant_EN & '0' & Grant_EW & Grant_ES & Grant_EL;
Xbar_sel_W <= Grant_WN & Grant_WE & '0' & Grant_WS & Grant_WL;
Xbar_sel_S <= Grant_SN & Grant_SE & Grant_SW & '0' & Grant_SL;
Xbar_sel_L <= Grant_LN & Grant_LE & Grant_LW & Grant_LS & Grant_LL;
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR_LV generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR_LV generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR_LV generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR_LV generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR_LV generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
end;
| gpl-3.0 | b124f32c31e65de090df2c86bf5acf81 | 0.496845 | 3.025523 | false | false | false | false |
bruskajp/EE-316 | Project2/Vivado_NexysBoard/project_2b/project_2b.srcs/sources_1/imports/Downloads/Interfacer.vhd | 2 | 5,195 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY Interfacer IS
PORT(
CLK : in std_logic;
data_in : in std_logic_vector(15 downto 0) := x"0000";
sda : inout std_logic;
scl : inout std_logic);
END Interfacer;
architecture behavioural of Interfacer is
component i2c_master is
PORT(
clk : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --active low reset
ena : IN STD_LOGIC; --latch in command
addr : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave
rw : IN STD_LOGIC; --'0' is write, '1' is read
data_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --data to write to slave
busy : OUT STD_LOGIC; --indicates transaction in progress
data_rd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave
ack_error : BUFFER STD_LOGIC; --flag if improper acknowledge from slave
sda : INOUT STD_LOGIC; --serial data output of i2c bus
scl : INOUT STD_LOGIC); --serial clock output of i2c bus
end component;
type state_type is (initial, wait_i2c, send_addr, send_data_1, send_data_2, send_data_3, send_data_4, stop);
signal state : state_type := initial;
signal data_sec : std_logic_vector(7 downto 0);
signal address : std_logic_vector(6 downto 0):= "1110001";
signal read_write : std_logic := '0';
signal reset : std_logic;
signal enable : std_logic;
signal busy : std_logic;
signal error : std_logic;
signal busy_prev : std_logic;
signal data_prev : std_logic_vector(15 downto 0);
signal counter : integer := 0;
signal byteSel : std_logic_vector(7 downto 0);
signal transmitted : boolean;
begin
I2CMaster : i2c_master
port map(
clk => CLK,
reset_n => reset,
ena => enable,
addr => address,
rw => read_write,
data_wr => data_sec,
busy => busy,
ack_error => error,
sda => sda,
scl => scl);
process(CLK, state, busy, error)
begin
if rising_edge(CLK) then
data_prev <= data_in;
case state is
when initial =>
reset <= '1';
enable <= '1';
if counter <= 12 then
--enable <= '1';
data_sec <= byteSel;
busy_prev <= busy;
if busy = '0' and busy_prev = '1' then
transmitted <= True;
else
transmitted <= false;
end if;
if transmitted then
counter <= counter + 1;
transmitted <= false;
else
counter <= counter;
end if;
elsif counter > 12 then
enable <= '0';
counter <= 0;
state <= wait_i2c;
end if;
when wait_i2c =>
if data_in /= data_prev then
state <= send_addr;
reset <= '0';
else
state <= wait_i2c;
end if;
when send_addr =>
enable <= '1';
reset <= '1';
state <= send_data_1;
when send_data_1 =>
data_sec <= "0000" & data_in(15 downto 12);
busy_prev <= busy;
if busy = '0' and busy_prev = '1' then
transmitted <= True;
else
transmitted <= false;
end if;
if transmitted then
state <= send_data_2;
transmitted <= false;
else
state <= send_data_1;
end if;
when send_data_2 =>
data_sec <= "0000" & data_in(11 downto 8);
busy_prev <= busy;
if busy = '0' and busy_prev = '1' then
transmitted <= True;
else
transmitted <= false;
end if;
if transmitted then
state <= send_data_3;
transmitted <= false;
else
state <= send_data_2;
end if;
when send_data_3 =>
data_sec <= "0000" & data_in(7 downto 4);
busy_prev <= busy;
if busy = '0' and busy_prev = '1' then
transmitted <= True;
else
transmitted <= false;
end if;
if transmitted then
state <= send_data_4;
transmitted <= false;
else
state <= send_data_3;
end if;
when send_data_4 =>
data_sec <= "0000" & data_in(3 downto 0);
busy_prev <= busy;
if busy = '0' and busy_prev = '1' then
transmitted <= True;
else
transmitted <= false;
end if;
if transmitted then
state <= stop;
transmitted <= false;
else
state <= send_data_4;
end if;
when stop =>
enable <= '0';
state <= wait_i2c;
when others =>
state <= wait_i2c;
end case;
end if;
end process;
process(counter)
begin
case (counter) is
when 0 => byteSel <= x"76"; -- board initialization sequence
when 1 => byteSel <= x"76";
when 2 => byteSel <= x"76";
when 3 => byteSel <= x"7A";
when 4 => byteSel <= x"FF";
when 5 => byteSel <= x"77";
when 6 => byteSel <= x"00";
when 7 => byteSel <= x"79";
when 8 => byteSel <= x"00";
when 9 => byteSel <= x"00"; -- initial data
when 10 => byteSel <= x"00";
when 11 => byteSel <= x"00";
when 12 => byteSel <= x"00";
when others => byteSel <= x"00";
end case;
end process;
end behavioural; | gpl-3.0 | 1e69ab7a8c272bad00f4a0747b8b8a98 | 0.536092 | 3.165753 | false | false | false | false |
TUM-LIS/faultify | hardware/testcases/QR/fpga_sim/xpsLibraryPath_asic_400_599/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/vhdl/user_logic.vhd | 3 | 29,245 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Fri May 16 15:25:24 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
faultify_clk_fast : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
component faultify_top
generic (
numInj : integer;
numIn : integer;
numOut : integer);
port (
aclk : in std_logic;
arst_n : in std_logic;
clk : in std_logic;
clk_x32 : in std_logic;
awvalid : in std_logic;
awaddr : in std_logic_vector(31 downto 0);
wvalid : in std_logic;
wdata : in std_logic_vector(31 downto 0);
arvalid : in std_logic;
araddr : in std_logic_vector(31 downto 0);
rvalid : out std_logic;
rdata : out std_logic_vector(31 downto 0));
end component;
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal register_write_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal register_read_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal register_write_address : std_logic_vector(C_NUM_REG-1 downto 0);
signal register_read_address : std_logic_vector(C_NUM_REG-1 downto 0);
signal slv_reg_write_sel : std_logic_vector(31 downto 0);
signal slv_reg_read_sel : std_logic_vector(31 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal faultify_read_valid : std_logic;
signal faultify_read_address_valid : std_logic;
signal faultify_read_address : std_logic_vector(31 downto 0);
signal faultify_write_valid : std_logic;
signal counter, divide : integer := 0;
signal faultify_clk_slow_i : std_logic;
begin
slv_reg_write_sel <= Bus2IP_WrCE(31 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(31 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12) or Bus2IP_WrCE(13) or Bus2IP_WrCE(14) or Bus2IP_WrCE(15) or Bus2IP_WrCE(16) or Bus2IP_WrCE(17) or Bus2IP_WrCE(18) or Bus2IP_WrCE(19) or Bus2IP_WrCE(20) or Bus2IP_WrCE(21) or Bus2IP_WrCE(22) or Bus2IP_WrCE(23) or Bus2IP_WrCE(24) or Bus2IP_WrCE(25) or Bus2IP_WrCE(26) or Bus2IP_WrCE(27) or Bus2IP_WrCE(28) or Bus2IP_WrCE(29) or Bus2IP_WrCE(30) or Bus2IP_WrCE(31);
slv_read_ack <= faultify_read_valid;
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process(Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
register_write_data <= (others => '0');
register_write_address <= (others => '0');
faultify_write_valid <= '0';
else
faultify_write_valid <= slv_write_ack;
case slv_reg_write_sel is
when "10000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(0, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "01000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(1, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00100000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(2, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00010000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(3, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00001000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(4, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000100000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(5, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000010000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(6, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000001000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(7, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000100000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(8, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000010000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(9, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000001000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(10, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000100000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(11, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000010000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(12, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000001000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(13, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000100000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(14, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000010000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(15, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000001000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(16, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000100000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(17, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000010000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(18, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000001000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(19, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000100000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(20, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000010000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(21, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000001000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(22, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000100000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(23, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000010000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(24, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000001000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(25, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(26, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(27, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(28, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(29, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(30, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(31, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process(slv_reg_read_sel, faultify_read_valid) is
begin
faultify_read_address_valid <= '1';
case slv_reg_read_sel is
when "10000000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(0, 32));
when "01000000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(1, 32));
when "00100000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(2, 32));
when "00010000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(3, 32));
when "00001000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(4, 32));
when "00000100000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(5, 32));
when "00000010000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(6, 32));
when "00000001000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(7, 32));
when "00000000100000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(8, 32));
when "00000000010000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(9, 32));
when "00000000001000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(10, 32));
when "00000000000100000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(11, 32));
when "00000000000010000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(12, 32));
when "00000000000001000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(13, 32));
when "00000000000000100000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(14, 32));
when "00000000000000010000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(15, 32));
when "00000000000000001000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(16, 32));
when "00000000000000000100000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(17, 32));
when "00000000000000000010000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(18, 32));
when "00000000000000000001000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(19, 32));
when "00000000000000000000100000000000" => faultify_read_address <= std_logic_vector(to_unsigned(20, 32));
when "00000000000000000000010000000000" => faultify_read_address <= std_logic_vector(to_unsigned(21, 32));
when "00000000000000000000001000000000" => faultify_read_address <= std_logic_vector(to_unsigned(22, 32));
when "00000000000000000000000100000000" => faultify_read_address <= std_logic_vector(to_unsigned(23, 32));
when "00000000000000000000000010000000" => faultify_read_address <= std_logic_vector(to_unsigned(24, 32));
when "00000000000000000000000001000000" => faultify_read_address <= std_logic_vector(to_unsigned(25, 32));
when "00000000000000000000000000100000" => faultify_read_address <= std_logic_vector(to_unsigned(26, 32));
when "00000000000000000000000000010000" => faultify_read_address <= std_logic_vector(to_unsigned(27, 32));
when "00000000000000000000000000001000" => faultify_read_address <= std_logic_vector(to_unsigned(28, 32));
when "00000000000000000000000000000100" => faultify_read_address <= std_logic_vector(to_unsigned(29, 32));
when "00000000000000000000000000000010" => faultify_read_address <= std_logic_vector(to_unsigned(30, 32));
when "00000000000000000000000000000001" => faultify_read_address <= std_logic_vector(to_unsigned(31, 32));
when others => faultify_read_address <= (others => '0');
faultify_read_address_valid <= '0';
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= register_read_data when faultify_read_valid = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
-----------------------------------------------------------------------------
-- clock divider 32 -> 1
-----------------------------------------------------------------------------
divide <= 32;
process(Bus2IP_Clk, Bus2IP_Resetn)
begin
if Bus2IP_Resetn = '0' then
counter <= 0;
faultify_clk_slow_i <= '0';
elsif(rising_edge(Bus2IP_Clk)) then
if(counter < divide/2-1) then
counter <= counter + 1;
faultify_clk_slow_i <= '0';
elsif(counter < divide-1) then
counter <= counter + 1;
faultify_clk_slow_i <= '1';
else
faultify_clk_slow_i <= '0';
counter <= 0;
end if;
end if;
end process;
faultify_top_1 : faultify_top
generic map (
numInj => 200,
numIn => 111,
numOut => 202)
port map (
aclk => Bus2IP_Clk,
arst_n => Bus2IP_Resetn,
clk => faultify_clk_slow_i,
clk_x32 => Bus2IP_Clk,
awvalid => faultify_write_valid,
awaddr => register_write_address,
wvalid => faultify_write_valid,
wdata => register_write_data,
arvalid => faultify_read_address_valid,
araddr => faultify_read_address,
rvalid => faultify_read_valid,
rdata => register_read_data);
end IMP;
| gpl-2.0 | bdc2f9f5ffb0706d056e016392565539 | 0.53934 | 4.023249 | false | false | false | false |
SoCdesign/EHA | RTL/Hand_Shaking/Checkers/Control_part_checkers/Handshaking_FC/LBDR_checkers/RTL_and_Synthesis/LBDR_pseudo.vhd | 1 | 2,839 | -- Copyright (C) 2016 Siavoosh Payandeh, Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_pseudo is
generic (
cur_addr_rst: integer := 5;
Rxy_rst: integer := 60;
Cx_rst: integer := 15;
NoC_size: integer := 4
);
port ( empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
N1_out, E1_out, W1_out, S1_out: out std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: out std_logic
);
end LBDR_pseudo;
architecture behavior of LBDR_pseudo is
signal Cx: std_logic_vector(3 downto 0);
signal Rxy: std_logic_vector(7 downto 0);
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal N1, E1, W1, S1: std_logic;
begin
Cx <= std_logic_vector(to_unsigned(Cx_rst, Cx'length));
Rxy <= std_logic_vector(to_unsigned(Rxy_rst, Rxy'length));
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
N1 <= '1' when dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) else '0';
E1 <= '1' when cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) else '0';
W1 <= '1' when dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) else '0';
S1 <= '1' when cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) else '0';
-- Taking X1 signals to the output interface for checking with checkers
N1_out <= N1;
E1_out <= E1;
W1_out <= W1;
S1_out <= S1;
-- The combionational part
process(N1, E1, W1, S1, Rxy, Cx, flit_type, empty, Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF) begin
if flit_type = "001" and empty = '0' then
Req_N_in <= ((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0);
Req_E_in <= ((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1);
Req_W_in <= ((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2);
Req_S_in <= ((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3);
Req_L_in <= not N1 and not E1 and not W1 and not S1;
elsif flit_type = "100" then
Req_N_in <= '0';
Req_E_in <= '0';
Req_W_in <= '0';
Req_S_in <= '0';
Req_L_in <= '0';
else -- Body flit
Req_N_in <= Req_N_FF;
Req_E_in <= Req_E_FF;
Req_W_in <= Req_W_FF;
Req_S_in <= Req_S_FF;
Req_L_in <= Req_L_FF;
end if;
end process;
END; | gpl-3.0 | 7578d0ea4e9f7babe504908720dfe71b | 0.582247 | 2.6022 | false | false | false | false |
JarrettR/FPGA-Cryptoparty | FPGA/hdl/ipcore_dir/fx2_fifo/simulation/fx2_fifo_rng.vhd | 1 | 3,887 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fx2_fifo_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fx2_fifo_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fx2_fifo_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
| gpl-3.0 | 25bef24beb2007f13de330930b748416 | 0.637252 | 4.33817 | false | false | false | false |
bruskajp/EE-316 | Project2/Vivado_NexysBoard/project_2b/project_2b.srcs/sources_1/imports/Downloads/sys_clk.vhd | 1 | 803 | LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY sys_clk IS
GENERIC (
CONSTANT REF_CLK : integer := 50000000; -- 50.0 MHz
CONSTANT OUT_CLK : integer := 10000000); -- 10.0 MHz
PORT (
SIGNAL oCLK : INOUT std_logic;
SIGNAL iCLK : IN std_logic;
SIGNAL iRST_N : IN std_logic);
END sys_clk;
ARCHITECTURE Arch OF sys_clk IS
SIGNAL DIV : std_logic_vector (25 DOWNTO 0):="00"&X"000000";
BEGIN
PROCESS(iCLK, iRST_N)
BEGIN
IF (iRST_N='0') THEN
DIV <= "00"&X"000000";
oCLK <= '0';
ELSIF rising_edge(iCLK) THEN
IF DIV >= REF_CLK/OUT_CLK/2 - 1 THEN
DIV <= "00"&X"000000";
oCLK <= NOT oCLK;
ELSE
DIV <= DIV + '1';
END IF;
END IF;
END PROCESS;
END Arch;
| gpl-3.0 | 3ad5b89b65bbbd1f03a81d69b6f34dab | 0.592777 | 2.90942 | false | false | false | false |
TUM-LIS/faultify | hardware/testcases/DCT4/fpga_sim/xpsLibraryPath/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/vhdl/user_logic.vhd | 1 | 29,242 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Fri May 16 15:25:24 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
faultify_clk_fast : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
component faultify_top
generic (
numInj : integer;
numIn : integer;
numOut : integer);
port (
aclk : in std_logic;
arst_n : in std_logic;
clk : in std_logic;
clk_x32 : in std_logic;
awvalid : in std_logic;
awaddr : in std_logic_vector(31 downto 0);
wvalid : in std_logic;
wdata : in std_logic_vector(31 downto 0);
arvalid : in std_logic;
araddr : in std_logic_vector(31 downto 0);
rvalid : out std_logic;
rdata : out std_logic_vector(31 downto 0));
end component;
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal register_write_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal register_read_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal register_write_address : std_logic_vector(C_NUM_REG-1 downto 0);
signal register_read_address : std_logic_vector(C_NUM_REG-1 downto 0);
signal slv_reg_write_sel : std_logic_vector(31 downto 0);
signal slv_reg_read_sel : std_logic_vector(31 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal faultify_read_valid : std_logic;
signal faultify_read_address_valid : std_logic;
signal faultify_read_address : std_logic_vector(31 downto 0);
signal faultify_write_valid : std_logic;
signal counter, divide : integer := 0;
signal faultify_clk_slow_i : std_logic;
begin
slv_reg_write_sel <= Bus2IP_WrCE(31 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(31 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12) or Bus2IP_WrCE(13) or Bus2IP_WrCE(14) or Bus2IP_WrCE(15) or Bus2IP_WrCE(16) or Bus2IP_WrCE(17) or Bus2IP_WrCE(18) or Bus2IP_WrCE(19) or Bus2IP_WrCE(20) or Bus2IP_WrCE(21) or Bus2IP_WrCE(22) or Bus2IP_WrCE(23) or Bus2IP_WrCE(24) or Bus2IP_WrCE(25) or Bus2IP_WrCE(26) or Bus2IP_WrCE(27) or Bus2IP_WrCE(28) or Bus2IP_WrCE(29) or Bus2IP_WrCE(30) or Bus2IP_WrCE(31);
slv_read_ack <= faultify_read_valid;
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process(Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
register_write_data <= (others => '0');
register_write_address <= (others => '0');
faultify_write_valid <= '0';
else
faultify_write_valid <= slv_write_ack;
case slv_reg_write_sel is
when "10000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(0, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "01000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(1, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00100000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(2, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00010000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(3, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00001000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(4, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000100000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(5, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000010000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(6, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000001000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(7, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000100000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(8, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000010000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(9, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000001000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(10, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000100000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(11, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000010000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(12, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000001000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(13, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000100000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(14, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000010000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(15, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000001000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(16, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000100000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(17, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000010000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(18, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000001000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(19, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000100000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(20, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000010000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(21, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000001000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(22, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000100000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(23, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000010000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(24, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000001000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(25, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(26, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(27, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(28, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(29, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(30, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(31, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process(slv_reg_read_sel, faultify_read_valid) is
begin
faultify_read_address_valid <= '1';
case slv_reg_read_sel is
when "10000000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(0, 32));
when "01000000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(1, 32));
when "00100000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(2, 32));
when "00010000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(3, 32));
when "00001000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(4, 32));
when "00000100000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(5, 32));
when "00000010000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(6, 32));
when "00000001000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(7, 32));
when "00000000100000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(8, 32));
when "00000000010000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(9, 32));
when "00000000001000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(10, 32));
when "00000000000100000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(11, 32));
when "00000000000010000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(12, 32));
when "00000000000001000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(13, 32));
when "00000000000000100000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(14, 32));
when "00000000000000010000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(15, 32));
when "00000000000000001000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(16, 32));
when "00000000000000000100000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(17, 32));
when "00000000000000000010000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(18, 32));
when "00000000000000000001000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(19, 32));
when "00000000000000000000100000000000" => faultify_read_address <= std_logic_vector(to_unsigned(20, 32));
when "00000000000000000000010000000000" => faultify_read_address <= std_logic_vector(to_unsigned(21, 32));
when "00000000000000000000001000000000" => faultify_read_address <= std_logic_vector(to_unsigned(22, 32));
when "00000000000000000000000100000000" => faultify_read_address <= std_logic_vector(to_unsigned(23, 32));
when "00000000000000000000000010000000" => faultify_read_address <= std_logic_vector(to_unsigned(24, 32));
when "00000000000000000000000001000000" => faultify_read_address <= std_logic_vector(to_unsigned(25, 32));
when "00000000000000000000000000100000" => faultify_read_address <= std_logic_vector(to_unsigned(26, 32));
when "00000000000000000000000000010000" => faultify_read_address <= std_logic_vector(to_unsigned(27, 32));
when "00000000000000000000000000001000" => faultify_read_address <= std_logic_vector(to_unsigned(28, 32));
when "00000000000000000000000000000100" => faultify_read_address <= std_logic_vector(to_unsigned(29, 32));
when "00000000000000000000000000000010" => faultify_read_address <= std_logic_vector(to_unsigned(30, 32));
when "00000000000000000000000000000001" => faultify_read_address <= std_logic_vector(to_unsigned(31, 32));
when others => faultify_read_address <= (others => '0');
faultify_read_address_valid <= '0';
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= register_read_data when faultify_read_valid = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
-----------------------------------------------------------------------------
-- clock divider 32 -> 1
-----------------------------------------------------------------------------
divide <= 32;
process(Bus2IP_Clk, Bus2IP_Resetn)
begin
if Bus2IP_Resetn = '0' then
counter <= 0;
faultify_clk_slow_i <= '0';
elsif(rising_edge(Bus2IP_Clk)) then
if(counter < divide/2-1) then
counter <= counter + 1;
faultify_clk_slow_i <= '0';
elsif(counter < divide-1) then
counter <= counter + 1;
faultify_clk_slow_i <= '1';
else
faultify_clk_slow_i <= '0';
counter <= 0;
end if;
end if;
end process;
faultify_top_1 : faultify_top
generic map (
numInj => 13,
numIn => 64,
numOut => 23)
port map (
aclk => Bus2IP_Clk,
arst_n => Bus2IP_Resetn,
clk => faultify_clk_slow_i,
clk_x32 => Bus2IP_Clk,
awvalid => faultify_write_valid,
awaddr => register_write_address,
wvalid => faultify_write_valid,
wdata => register_write_data,
arvalid => faultify_read_address_valid,
araddr => faultify_read_address,
rvalid => faultify_read_valid,
rdata => register_read_data);
end IMP;
| gpl-2.0 | 25e4bfec46083fe44b38e868f1d6b317 | 0.539293 | 4.022837 | false | false | false | false |
JarrettR/FPGA-Cryptoparty | FPGA/hdl/ipcore_dir/fx2_fifo.vhd | 1 | 10,274 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2017 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file fx2_fifo.vhd when simulating
-- the core, fx2_fifo. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY fx2_fifo IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC
);
END fx2_fifo;
ARCHITECTURE fx2_fifo_a OF fx2_fifo IS
-- synthesis translate_off
COMPONENT wrapped_fx2_fifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_fx2_fifo USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 10,
c_default_value => "BlankString",
c_din_width => 16,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 16,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 0,
c_has_almost_empty => 1,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 2,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 2,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 2,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "1kx18",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 1023,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 1022,
c_prog_full_type => 0,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 10,
c_rd_depth => 1024,
c_rd_freq => 1,
c_rd_pntr_width => 10,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 10,
c_wr_depth => 1024,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 10,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fx2_fifo
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty,
almost_empty => almost_empty
);
-- synthesis translate_on
END fx2_fifo_a;
| gpl-3.0 | 8b8f3c8ce578c005de872686e0c8f484 | 0.536695 | 3.323843 | false | false | false | false |
TanND/Electronic | VHDL/D1_C2.vhd | 1 | 672 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D1_C2 is
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
q0 : out STD_LOGIC;
q1 : out STD_LOGIC
);
end D1_C2;
--}} End of automatically maintained section
architecture D1_C2 of D1_C2 is
signal j : integer:=1;
begin
process(clk,rst)
begin
if rst ='0' then j<=0;
else
if rising_edge(clk) then
if j=3 then j<=0;
else
j<=j+1;
end if;
end if;
end if;
end process;
process(rst,j)
begin
if rst ='0' then q0<='0';q1<='0';
else
if j=1 then q0<='1';q1<='1'; end if;
if j=3 then q0<='0';q1<='0'; end if ;
end if;
end process;
end led;
-- clk =2hz
| apache-2.0 | a1bf6dba4bfc57968701a69f1e1225fd | 0.56994 | 2.434783 | false | false | false | false |
SoCdesign/EHA | RTL/Credit_Based/Checkers/Control_Part_Checkers/outdated/FIFO_one_hot_credit_based_control_part_checkers/RTL_and_Synthesis/FIFO_one_hot_credit_based_control_part_with_checkers_top.vhd | 1 | 8,758 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity FIFO_credit_based_control_part_with_checkers_top is
port ( valid_in : in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
credit_out: out std_logic;
empty_out: out std_logic;
full_out: out std_logic;
read_pointer_in: out std_logic_vector(3 downto 0);
write_pointer_in: out std_logic_vector(3 downto 0);
read_en_out: out std_logic;
write_en_out: out std_logic;
-- Checker outputs
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_read_en_credit_out,
err_not_read_en_credit_out,
err_write_en,
err_not_write_en,
err_read_en_mismatch : out std_logic
);
end FIFO_credit_based_control_part_with_checkers_top;
architecture behavior of FIFO_credit_based_control_part_with_checkers_top is
component FIFO_credit_based_control_part_pseudo is
port ( valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
credit_out: out std_logic;
empty_out: out std_logic;
full_out: out std_logic;
read_pointer_in: out std_logic_vector(3 downto 0);
write_pointer_in: out std_logic_vector(3 downto 0);
read_en_out: out std_logic;
write_en_out: out std_logic
);
end component;
component FIFO_credit_based_control_part_checkers is
port ( valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
read_pointer_in: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
write_pointer_in: in std_logic_vector(3 downto 0);
credit_out: in std_logic;
empty_out: in std_logic;
full_out: in std_logic;
read_en_out: in std_logic;
write_en_out: in std_logic;
-- Checker outputs
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_read_en_credit_out,
err_not_read_en_credit_out,
err_write_en,
err_not_write_en,
err_read_en_mismatch : out std_logic
);
end component;
signal credit_out_sig: std_logic;
signal empty_out_sig, full_out_sig, read_en_out_sig, write_en_out_sig: std_logic;
signal read_pointer_in_sig, write_pointer_in_sig: std_logic_vector(3 downto 0);
begin
credit_out <= credit_out_sig;
read_pointer_in <= read_pointer_in_sig;
write_pointer_in <= write_pointer_in_sig;
empty_out <= empty_out_sig;
full_out <= full_out_sig;
read_en_out <= read_en_out_sig;
write_en_out <= write_en_out_sig;
-- Credit-Based FIFO Control Part instantiation
FIFO_CREDIT_BASED_CONTROL_PART: FIFO_credit_based_control_part_pseudo port map
(valid_in => valid_in,
read_en_N => read_en_N,
read_en_E => read_en_E,
read_en_W => read_en_W,
read_en_S => read_en_S,
read_en_L => read_en_L,
read_pointer => read_pointer,
write_pointer => write_pointer,
credit_out => credit_out_sig,
empty_out => empty_out_sig,
full_out => full_out_sig,
read_pointer_in => read_pointer_in_sig,
write_pointer_in => write_pointer_in_sig,
read_en_out => read_en_out_sig,
write_en_out => write_en_out_sig
);
-- Checkers instantiation
CHECKERS: FIFO_credit_based_control_part_checkers port map (valid_in => valid_in,
read_en_N => read_en_N,
read_en_E => read_en_E,
read_en_W => read_en_W,
read_en_S => read_en_S,
read_en_L => read_en_L,
read_pointer => read_pointer,
read_pointer_in => read_pointer_in_sig,
write_pointer => write_pointer,
write_pointer_in => write_pointer_in_sig,
credit_out => credit_out_sig,
empty_out => empty_out_sig,
full_out => full_out_sig,
read_en_out => read_en_out_sig,
write_en_out => write_en_out_sig,
err_write_en_write_pointer => err_write_en_write_pointer,
err_not_write_en_write_pointer => err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => err_read_pointer_write_pointer_full,
err_read_pointer_increment => err_read_pointer_increment,
err_read_pointer_not_increment => err_read_pointer_not_increment,
err_read_en_credit_out => err_read_en_credit_out,
err_not_read_en_credit_out => err_not_read_en_credit_out,
err_write_en => err_write_en,
err_not_write_en => err_not_write_en,
err_read_en_mismatch => err_read_en_mismatch
);
end behavior; | gpl-3.0 | 5f1970c800e8c3a02486709c642ea991 | 0.43172 | 4.468367 | false | false | false | false |
bruskajp/EE-316 | Project4/Vivado_NexysBoard/craddockEE316/craddockEE316.srcs/sources_1/imports/testFolder/RAM_Controller.vhd | 1 | 8,058 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03/12/2017 06:15:00 PM
-- Design Name:
-- Module Name: RAM_Controller - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RAM_Controller is
generic( constant samples : integer := 128);
Port ( clk11kHz : in STD_LOGIC;
clk : in std_logic;
clk500kHz : in STD_LOGIC;
idata_valid : in std_logic;
sel : in STD_LOGIC_vector(1 downto 0);
reset : in std_logic;
iadcsel : in std_logic;
ointernalCount : out std_logic;
ena1 : out std_logic;
enb1 : out std_logic;
ena2 : out std_logic;
enb2 : out std_logic;
wea : out std_logic_vector(0 downto 0);
UARTen : out std_logic;
ocount1 : out std_logic_vector(13 downto 0);
ocount2 : out std_logic_vector(13 downto 0);
ocount4 : out std_logic_vector(13 downto 0);
ocount3 : out std_logic_vector(13 downto 0));
end RAM_Controller;
architecture Behavioral of RAM_Controller is
signal count1 : integer:= -1;
signal count2 : integer:= -1;
signal count3 : integer:= -1;
signal count4 : integer:= -1;
signal count2flag : std_logic;
signal count3flag : std_logic;
signal doneFlag : std_logic:= '0';
signal doneCount : integer :=0;
signal internalCount : std_logic:= '0';
signal Ssel : std_logic_vector(1 downto 0) := "00";
signal selRes : std_logic_vector(1 downto 0) := "00";
--signal sel : std_logic_vector(1 downto 0):= "11";
signal clk_cnt : integer;
signal clk_en : std_logic:= '0';
begin
--Ssel <= sel;
ointernalCount <= internalCount;
process(clk500kHz)
begin
if rising_edge(clk500kHz) then
if clk_cnt >= 2 then
clk_en <= not(clk_en);
else
clk_cnt <= clk_cnt + 1;
end if;
end if;
end process;
process(iadcsel, reset,clk)--idata_valid, iadcsel, reset)
begin
if rising_edge(clk) then
wea <= "1";
if reset = '1' then
count1 <= -1;
elsif reset = '0' then
if iadcsel = '0' then
if count1 < samples then
count1 <= count1 + 1;
--ena1 <= '1';
elsif count1 >= samples - 1 AND ((count2 = samples -1 and sel = "01") or (count2 = samples - 1 and count3 = samples - 1 and internalCount = '0' and doneFlag = '1' and sel = "11")) then
count1 <= -1;
--ena1 <= '0';
end if;
end if;
end if;
end if;
end process;
process(iadcsel)
begin
if iadcsel = '0' then
ena1 <= '1';
ena2 <= '0';
elsif iadcsel = '1' then
ena1 <= '0';
ena2 <= '1';
end if;
end process;
process(iadcsel, reset,clk)--idata_valid, iadcsel, reset)
begin
if rising_edge(clk) then
wea <= "1";
if reset = '1' then
count4 <= -1;
elsif reset = '0' then
if iadcsel = '1' then
if count4 < samples then
count4 <= count4 + 1;
--ena1 <= '1';
elsif count4 >= samples - 1 AND ((count3 = samples -1 and sel = "01") or (count2 = samples - 1 and count3 = samples - 1 and internalCount = '0' and doneFlag = '1' and sel = "11")) then
count4 <= -1;
--ena1 <= '0';
end if;
end if;
end if;
end if;
end process;
-- if count1 < samples and iadcsel = '0' and idata_valid = '1' and Ssel = "00" then
-- count1 <= count1 + 1;
-- ena1 <= '1';
-- ena2 <= '0';
-- elsif count1 >= samples-1 AND ((count2 = samples - 1 and sel = "01") or (count2 = samples -1 and count3 = samples -1 and internalCount = '1' and doneFlag = '1' and sel = "11")) then
-- count1 <= -1;
-- end if;
-- if count4 < samples and iadcsel = '1' and idata_valid = '1' and Ssel = "00" then
-- count4 <= count4 + 1;
-- ena1 <= '0';
-- ena2 <= '1';
-- elsif count4 >= samples-1 AND ((count3 = samples - 1 and sel = "10") or (count2 = samples -1 and count3 = samples -1 and internalCount = '1' and doneFlag = '1' and sel = "11")) then
-- count4 <= -1;
-- end if;
--end if;
-- if rising_edge(clk500kHz) and iadcsel = '1' then
-- if count4 < samples then
-- count4 <= count1 + 1;
-- elsif count4 >= samples-1 AND (internalCount = '0' and doneFlag = '0') then --((count2 = samples-1 and sel = "01") or (count3 = samples-1 and sel = "10") or (count2 = samples - 1 and count3 = samples - 1 and sel = "11") or sel = "00") then
-- count4 <= 0;
-- end if;
-- end if;
--end process;
process(clk11kHz,sel)
begin
if rising_edge(clk11kHz) then
if reset = '1' then
count2 <= -1;
count3 <= -1;
enb1 <= '0';
enb2 <= '0';
--selRes <= "00";
elsif sel = "00" then--selRes = "00" then
elsif sel = "01" then
--selRes <= "01";
if count2 = samples - 1 then
count2 <= -1;
internalCount <= '0';
UARTen <= '0';
enb1 <= '0';
--doneFlag <= '1';
else
count2 <= count2 + 1;
UARTen <= '1';
enb1 <= '1';
internalCount <= '1';
end if;
elsif sel = "10" then
--selRes <= "01";
if count3 = samples - 1 then
count3 <= -1;
internalCount <= '0';
UARTen <= '0';
enb2 <= '0';
else
count3 <= count3 + 1;
internalCount <= '1';
UARTen <= '1';
enb2 <= '1';
end if;
elsif sel = "11" then
--selRes <= "01";
UARTen <= '1';
if count2 = samples - 1 then
if count3 = samples - 1 then
enb1 <= '0';
enb2 <= '0';
doneFlag <= '1';
internalCount <= '0';
--UARTen <= '0';
else
enb1 <= '0';
enb2 <= '1';
count3 <= count3 + 1;
--UARTen <= '1';
internalCount <= '1';
end if;
else
enb1 <= '1';
enb2 <= '0';
count2 <= count2 + 1;
--UARTen <= '1';
internalCount <= '1';
end if;
if doneFlag = '1' then
enb1 <= '0';
enb2 <= '0';
doneCount <= doneCount + 1;
internalCount <= '0';
if doneCount = samples then
count2 <= -1;
count3 <= -1;
doneFlag <= '0';
doneCount <= 0;
end if;
end if;
end if;
end if;
end process;
ocount1 <= std_logic_vector(to_signed(count1, ocount1'length));
ocount2 <= std_logic_vector(to_signed(count2, ocount2'length));
ocount3 <= std_logic_vector(to_signed(count3, ocount3'length));
ocount4 <= std_logic_vector(to_signed(count4, ocount4'length));
end Behavioral;
| gpl-3.0 | 95ca60fdc8c6354233ead8dc2e2d5ff5 | 0.469595 | 3.786654 | false | false | false | false |
TanND/Electronic | VHDL/D5_C1.vhd | 1 | 683 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D5_C1 is
generic (n:integer:=8);
port(
clk : in STD_LOGIC;
sel : in STD_LOGIC;
SI : in bit;
Q : out bit_VECTOR(n-1 downto 0)
);
end D5_C1;
--}} End of automatically maintained section
architecture D5_C1 of D5_C1 is
signal temp:bit_vector(n-1 downto 0);
begin
process (clk,SI)
begin
if (clk'event and clk='1') then
temp <= temp(n-2 downto 0)& SI;
end if;
end process;
process(sel,clk)
begin
if (rising_edge(clk))then
if (sel='1') then Q(0)<=temp(n-1);
else
if (sel='0') then Q<=temp;
end if;
end if;
end if;
end process;
end D5_C1;
| apache-2.0 | 283744ea3b3cfcf80977c73e1fa4d514 | 0.581259 | 2.699605 | false | false | false | false |
JarrettR/FPGA-Cryptoparty | FPGA/hdl/ipcore_dir/fx2_fifo/simulation/fx2_fifo_dverif.vhd | 1 | 5,818 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fx2_fifo_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fx2_fifo_pkg.ALL;
ENTITY fx2_fifo_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF fx2_fifo_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
PROCESS (RD_CLK,RESET)
BEGIN
IF (RESET = '1') THEN
rd_en_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0' AND rd_en_i='1' AND rd_en_d1 = '0') THEN
rd_en_d1 <= '1';
END IF;
END IF;
END PROCESS;
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:fx2_fifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '0') AND (rd_en_i = '1' AND rd_en_d1 = '1')) THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
| gpl-3.0 | 6455050fe7fa3d0a5d93e6480cf26cac | 0.567377 | 3.995879 | false | false | false | false |
TUM-LIS/faultify | hardware/testcases/IIR/fpga_sim/xpsLibraryPath/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/vhdl/faultify_top.vhd | 1 | 20,024 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_top is
generic (
numInj : integer := 56;
numIn : integer := 10;
numOut : integer := 10);
port (
aclk : in std_logic; -- interface clock
arst_n : in std_logic; -- interface reset
clk : in std_logic; -- simulation clock (slow)
clk_x32 : in std_logic; -- prng clock (fast)
-- Write channel
awvalid : in std_logic;
awaddr : in std_logic_vector(31 downto 0);
wvalid : in std_logic;
wdata : in std_logic_vector(31 downto 0);
-- Read channel
arvalid : in std_logic;
araddr : in std_logic_vector(31 downto 0);
rvalid : out std_logic;
rdata : out std_logic_vector(31 downto 0)
);
attribute syn_hier : string;
attribute syn_hier of faultify_top : entity is "hard";
end faultify_top;
architecture behav of faultify_top is
component flag_cdc
port (
clkA : in std_logic;
clkB : in std_logic;
FlagIn_clkA : in std_logic;
FlagOut_clkB : out std_logic;
rst_n : in std_logic);
end component;
component faultify_simulator
generic (
numInj : integer;
numIn : integer;
numOut : integer);
port (
clk : in std_logic;
clk_m : in std_logic;
circ_ce : in std_logic;
circ_rst : in std_logic;
test : out std_logic_vector(31 downto 0);
testvector : in std_logic_vector(numIn-1 downto 0);
resultvector_o : out std_logic_vector(numOut-1 downto 0);
resultvector_f : out std_logic_vector(numOut-1 downto 0);
seed_in_en : in std_logic;
seed_in : in std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
shift_en : in std_logic;
rst_n : in std_logic);
end component;
component lfsr
generic (
width : integer;
seed : integer);
port (
clk : in std_logic;
rand_out : out std_logic_vector(width-1 downto 0));
end component;
type vector is array (0 to numOut-1) of std_logic_vector(31 downto 0);
signal errorSum : vector;
signal errorSumReg : vector;
signal errorSumReg_cdc_0 : vector;
signal errorSumReg_cdc_1 : vector;
signal errorVec : std_logic_vector(numOut-1 downto 0);
signal cnt : integer;
signal cnt_cdc_0 : integer;
signal cnt_cdc_1 : integer;
-- Asymmetric ram larger than 36 bit not supported in synplify I-2013
--type seed_ram_matr is array (0 to numInj-1) of std_logic_vector(63 downto 0);
--signal seed_ram : seed_ram_matr;
-- workaround 2 32-bit rams
type seed_ram_matr is array (0 to numInj-1) of std_logic_vector(31 downto 0);
signal seed_ram_low : seed_ram_matr;
signal seed_ram_high : seed_ram_matr;
--subtype seed_ram_matr_word_t is std_logic_vector(63 downto 0);
--type seed_ram_matr_memory_t is array (0 to numInj-1) of seed_ram_matr_word_t;
--signal seed_ram : seed_ram_matr_memory_t;
type prob_ram_matr is array (0 to numInj-1) of std_logic_vector(31 downto 0);
signal prob_ram : prob_ram_matr;
type reg_type is record
control : std_logic_vector(31 downto 0);
status : std_logic_vector(31 downto 0);
pe_location : std_logic_vector(31 downto 0);
pe_seed_low : std_logic_vector(31 downto 0);
pe_seed_high : std_logic_vector(31 downto 0);
pe_probability : std_logic_vector(31 downto 0);
output : std_logic_vector(31 downto 0);
ovalid : std_logic;
simtime : std_logic_vector(31 downto 0);
sel_soe : std_logic_vector(31 downto 0);
adr_soe : std_logic_vector(31 downto 0);
awaddr : std_logic_vector(31 downto 0);
test : std_logic_vector(31 downto 0);
circreset : std_logic_vector(31 downto 0);
cnt_tmp : std_logic_vector(31 downto 0);
sumoferrors : vector;
end record;
signal busy_loading : std_logic;
signal busy_simulating : std_logic;
signal busy_loading_reg : std_logic_vector(1 downto 0);
signal busy_simulating_reg : std_logic_vector(1 downto 0);
signal sim_done : std_logic;
signal r : reg_type;
type load_fsm_states is (IDLE, LOADSEED, LOADPROB);
signal l_state : load_fsm_states;
type sim_states is (IDLE, DELAY_Z, DELAY, SIMULATION, DELAY2, DELAY3, DELAY4, FREE_SIMULATION);
signal s_state : sim_states;
signal testvector : std_logic_vector(numIn-1 downto 0);
signal resultvector_o : std_logic_vector(numOut-1 downto 0);
signal resultvector_f : std_logic_vector(numOut-1 downto 0);
signal seed_in_en : std_logic;
signal seed_in : std_logic;
signal prob_in_en : std_logic;
signal prob_in : std_logic;
signal shift_en : std_logic;
signal shift_en_l : std_logic;
signal shift_en_s : std_logic;
signal load_seed_prob : std_logic;
signal start_simulation : std_logic;
signal start_free_simulation : std_logic;
signal stop_simulation : std_logic;
signal circ_ce, circ_rst, circ_rst_sim : std_logic;
signal tvec : std_logic_vector(127 downto 0);
signal test : std_logic_vector(31 downto 0);
signal rst_cdc, rst_cdc_n : std_logic;
begin -- behav
-----------------------------------------------------------------------------
-- PRNG shifting
-----------------------------------------------------------------------------
shift_en <= shift_en_l or shift_en_s;
-----------------------------------------------------------------------------
-- Testvector
-----------------------------------------------------------------------------
--testvector <= (others => '0');
lfsr_1 : lfsr
generic map (
width => 128,
seed => 3498327)
port map (
clk => clk,
rand_out => tvec);
testvector <= tvec(numIn-1 downto 0);
-----------------------------------------------------------------------------
-- Simulator
-----------------------------------------------------------------------------
circ_rst <= circ_rst_sim when r.circreset(0) = '1' else '0';
faultify_simulator_1 : faultify_simulator
generic map (
numInj => numInj,
numIn => numIn,
numOut => numOut)
port map (
clk => clk_x32,
clk_m => clk,
circ_ce => circ_ce,
circ_rst => circ_rst,
test => test,
testvector => testvector,
resultvector_o => resultvector_o,
resultvector_f => resultvector_f,
seed_in_en => seed_in_en,
seed_in => seed_in,
prob_in_en => prob_in_en,
prob_in => prob_in,
shift_en => shift_en,
rst_n => arst_n);
-------------------------------------------------------------------------------
-- One Process Flow
-------------------------------------------------------------------------------
register_process : process (aclk, arst_n)
variable write_addr : std_logic_vector(31 downto 0);
begin -- process register_process
if arst_n = '0' then -- asynchronous reset (active low)
r.control <= (others => '0');
r.status <= (others => '0');
r.pe_probability <= (others => '0');
r.pe_seed_high <= (others => '0');
r.pe_seed_low <= (others => '0');
r.pe_location <= (others => '0');
r.ovalid <= '0';
r.simtime <= (others => '0');
r.sel_soe <= (others => '0');
r.adr_soe <= (others => '0');
r.sumoferrors <= (others => (others => '0'));
r.output <= (others => '0');
elsif aclk'event and aclk = '1' then -- rising clock edge
r.control <= (others => '0');
if awvalid = '1' then
r.awaddr <= awaddr;
write_addr := awaddr;
end if;
if wvalid = '1' then
if write_addr = x"00000000" then
r.control <= wdata;
elsif write_addr = x"00000001" then
r.pe_location <= wdata;
elsif write_addr = x"00000002" then
r.pe_seed_low <= wdata;
elsif write_addr = x"00000003" then
r.pe_seed_high <= wdata;
elsif write_addr = x"00000004" then
r.pe_probability <= wdata;
elsif write_addr = x"00000005" then
r.cnt_tmp <= std_logic_vector(to_unsigned(cnt_cdc_1, 32));
r.adr_soe <= wdata;
elsif write_addr = x"00000007" then
r.simtime <= wdata;
elsif write_addr = x"00000009" then
r.circreset <= wdata;
end if;
end if;
if arvalid = '1' then
if araddr = x"0000000F" then
r.output <= r.status;
elsif araddr = x"00000001" then
r.output <= r.pe_location;
elsif araddr = x"00000002" then
r.output <= r.pe_seed_low;
elsif araddr = x"00000003" then
r.output <= r.pe_seed_high;
elsif araddr = x"00000004" then
r.output <= r.pe_probability;
elsif araddr = x"00000006" then
r.output <= r.sel_soe;
elsif araddr = x"00000008" then
r.output <= r.test;
elsif araddr = x"0000000A" then
r.output <= r.cnt_tmp;
end if;
r.ovalid <= '1';
else
r.ovalid <= '0';
end if;
if busy_loading_reg(1) = '1' then
r.status(0) <= '1';
else
r.status(0) <= '0';
end if;
if busy_simulating_reg(1) = '1' then
r.status(1) <= '1';
else
r.status(1) <= '0';
end if;
r.sel_soe <= r.sumoferrors(to_integer(unsigned(r.adr_soe)));
rdata <= r.output;
rvalid <= r.ovalid;
r.sumoferrors <= errorSumReg_cdc_1;
r.test <= errorSum(0);
end if;
end process register_process;
-----------------------------------------------------------------------------
-- simple clock domain crossing
-----------------------------------------------------------------------------
process (aclk, arst_n)
begin -- process
if arst_n = '0' then -- asynchronous reset (active low)
busy_simulating_reg <= (others => '0');
busy_loading_reg <= (others => '0');
elsif aclk'event and aclk = '1' then -- rising clock edge
busy_simulating_reg(0) <= busy_simulating;
busy_loading_reg(0) <= busy_loading;
busy_simulating_reg(1) <= busy_simulating_reg(0);
busy_loading_reg(1) <= busy_loading_reg(0);
cnt_cdc_0 <= cnt;
cnt_cdc_1 <= cnt_cdc_0;
errorSumReg_cdc_0 <= errorSumReg;
errorSumReg_cdc_1 <= errorSumReg_cdc_0;
end if;
end process;
-------------------------------------------------------------------------------
-- Store seeed/prob
-------------------------------------------------------------------------------
store_seed : process (aclk, arst_n)
begin -- process store_seed
if arst_n = '0' then -- asynchronous reset (active low)
elsif aclk'event and aclk = '1' then -- rising clock edge
if r.control(0) = '1' then
-- Synplify bug workaround
--seed_ram(to_integer(unsigned(r.pe_location))) <= r.pe_seed_high & r.pe_seed_low;
seed_ram_low(to_integer(unsigned(r.pe_location))) <= r.pe_seed_low;
seed_ram_high(to_integer(unsigned(r.pe_location))) <= r.pe_seed_high;
prob_ram(to_integer(unsigned(r.pe_location))) <= r.pe_probability;
end if;
end if;
end process store_seed;
-----------------------------------------------------------------------------
-- Seed/prob loading FSM
-----------------------------------------------------------------------------
--flag_cdc_1 : flag_cdc
-- port map (
-- clkA => aclk,
-- clkB => clk_x32,
-- FlagIn_clkA => r.control(1),
-- FlagOut_clkB => load_seed_prob,
-- rst_n => arst_n);
load_seed_prob <= r.control(1);
seed_prob_loading : process (clk_x32, arst_n)
variable cnt_seed : integer range 0 to 64;
variable cnt_inj : integer range 0 to numInj;
variable cnt_prob : integer range 0 to 32;
begin -- process seed_prob_loading
if arst_n = '0' then -- asynchronous reset (active low)
l_state <= IDLE;
seed_in <= '0';
seed_in_en <= '0';
prob_in <= '0';
prob_in_en <= '0';
shift_en_l <= '0';
busy_loading <= '0';
elsif clk_x32'event and clk_x32 = '1' then -- rising clock edge
case l_state is
when IDLE =>
cnt_seed := 0;
cnt_inj := 0;
cnt_prob := 0;
busy_loading <= '0';
seed_in_en <= '0';
prob_in_en <= '0';
shift_en_l <= '0';
if load_seed_prob = '1' then
busy_loading <= '1';
l_state <= LOADSEED;
end if;
when LOADSEED =>
if cnt_seed < 64 then
shift_en_l <= '1';
seed_in_en <= '1';
-- not working in synplify I-2013
--seed_in <= seed_ram(cnt_inj)(cnt_seed);
--
if cnt_seed < 32 then
seed_in <= seed_ram_low(cnt_inj)(cnt_seed);
else
seed_in <= seed_ram_high(cnt_inj)(cnt_seed-32);
end if;
cnt_seed := cnt_seed + 1;
end if;
if cnt_seed = 64 then
cnt_seed := 0;
cnt_inj := cnt_inj + 1;
end if;
if cnt_inj = numInj then
l_state <= LOADPROB;
--seed_in_en <= '0';
cnt_inj := 0;
end if;
when LOADPROB =>
seed_in_en <= '0';
if cnt_prob < 32 then
prob_in_en <= '1';
prob_in <= prob_ram(cnt_inj)(cnt_prob);
cnt_prob := cnt_prob + 1;
end if;
if cnt_prob = 32 then
cnt_prob := 0;
cnt_inj := cnt_inj + 1;
end if;
if cnt_inj = numInj then
l_state <= IDLE;
cnt_inj := 0;
--prob_in_en <= '0';
end if;
end case;
end if;
end process seed_prob_loading;
-----------------------------------------------------------------------------
-- Simulation FSM
-----------------------------------------------------------------------------
flag_cdc_2 : flag_cdc
port map (
clkA => aclk,
clkB => clk,
FlagIn_clkA => r.control(2),
FlagOut_clkB => start_simulation,
rst_n => arst_n);
flag_cdc_3 : flag_cdc
port map (
clkA => aclk,
clkB => clk,
FlagIn_clkA => r.control(3),
FlagOut_clkB => start_free_simulation,
rst_n => arst_n);
flag_cdc_4 : flag_cdc
port map (
clkA => aclk,
clkB => clk,
FlagIn_clkA => r.control(4),
FlagOut_clkB => stop_simulation,
rst_n => arst_n);
rst_cdc_5 : flag_cdc
port map (
clkA => aclk,
clkB => clk,
FlagIn_clkA => not arst_n,
FlagOut_clkB => rst_cdc,
rst_n => '1');
rst_cdc_n <= not rst_cdc;
process (clk, rst_cdc_n)
variable simtime : integer;
variable cnt_delay : integer range 0 to 9;
begin -- process
if clk'event and clk = '1' then -- rising clock edge
if rst_cdc_n = '0' then -- asynchronous reset (active low)
s_state <= IDLE;
errorVec <= (others => '0');
errorSum <= (others => (others => '0'));
circ_ce <= '0';
circ_rst_sim <= '1';
shift_en_s <= '0';
busy_simulating <= '0';
sim_done <= '0';
errorSumReg <= (others => (others => '0'));
else
case s_state is
when IDLE =>
sim_done <= '0';
circ_ce <= '0';
circ_rst_sim <= '1';
shift_en_s <= '0';
errorVec <= (others => '0');
--errorSum <= errorSum;
errorSum <= (others => (others => '0'));
--cnt <= 0;
busy_simulating <= '0';
cnt_delay := 0;
if start_simulation = '1' then
cnt <= 0;
busy_simulating <= '1';
errorSum <= (others => (others => '0'));
errorSumReg <= (others => (others => '0'));
simtime := to_integer(unsigned(r.simtime));
s_state <= DELAY_Z;
circ_ce <= '1';
circ_rst_sim <= '0';
shift_en_s <= '1';
end if;
if start_free_simulation = '1' then
cnt <= 0;
busy_simulating <= '1';
errorSum <= (others => (others => '0'));
errorSumReg <= (others => (others => '0'));
s_state <= FREE_SIMULATION;
circ_ce <= '1';
circ_rst_sim <= '0';
shift_en_s <= '1';
end if;
when DELAY_z =>
cnt_delay := cnt_delay + 1;
if cnt_delay = 9 then
s_state <= DELAY;
end if;
when DELAY =>
s_state <= SIMULATION;
errorVec <= (others => '0');
errorSum <= (others => (others => '0'));
when SIMULATION =>
circ_rst_sim <= '0';
shift_en_s <= '1';
-- collect errors
if (resultvector_o(0) = '1') then
errorVec <= resultvector_o xor resultvector_f;
else
errorVec <= (others => '0');
end if;
for i in 0 to (numOut-1) loop
if (errorVec(i) = '1') then
errorSum(i) <= std_logic_vector(unsigned(errorSum(i)) + 1);
end if;
end loop;
--
errorSumReg <= errorSum;
if cnt = simtime-1 then
s_state <= DELAY2;
circ_ce <= '0';
circ_rst_sim <= '1';
shift_en_s <= '0';
end if;
cnt <= cnt +1;
when DELAY2 =>
errorVec <= resultvector_o xor resultvector_f;
for i in 0 to (numOut-1) loop
if (errorVec(i) = '1') then
errorSum(i) <= std_logic_vector(unsigned(errorSum(i)) + 1);
end if;
end loop;
s_state <= DELAY3;
when DELAY3 =>
s_state <= DELAY4;
errorSumReg <= errorSum;
errorSum <= (others => (others => '0'));
when DELAY4 =>
s_state <= IDLE;
sim_done <= '1';
when FREE_SIMULATION =>
circ_rst_sim <= '0';
shift_en_s <= '1';
-- collect error
if (resultvector_o(0) = '1') then
errorVec <= resultvector_o xor resultvector_f;
else
errorVec <= (others => '0');
end if;
for i in 0 to (numOut-1) loop
if (errorVec(i) = '1') then
errorSum(i) <= std_logic_vector(unsigned(errorSum(i)) + 1);
end if;
end loop;
--
errorSumReg <= errorSum;
if stop_simulation = '1' then
s_state <= IDLE;
sim_done <= '1';
circ_ce <= '0';
circ_rst_sim <= '1';
shift_en_s <= '0';
end if;
cnt <= cnt +1;
when others =>
s_state <= IDLE;
end case;
end if;
end if;
end process;
end behav;
| gpl-2.0 | 16295200d7be0bb5f501ce38c4732cc7 | 0.461396 | 3.838221 | false | false | false | false |
SoCdesign/EHA | RTL/Credit_Based/Checkers/Control_Part_Checkers/LBDR_credit_based_checkers/RTL_and_Synthesis/LBDR_credit_based_pseudo.vhd | 1 | 3,148 | --Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_credit_based_pseudo is
generic (
cur_addr_rst: integer := 5;
Rxy_rst: integer := 60;
Cx_rst: integer := 15;
NoC_size: integer := 4
);
port ( empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
N1_out, E1_out, W1_out, S1_out: out std_logic;
grants_out: out std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: out std_logic
);
end LBDR_credit_based_pseudo;
architecture behavior of LBDR_credit_based_pseudo is
signal Cx: std_logic_vector(3 downto 0);
signal Rxy: std_logic_vector(7 downto 0);
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal N1, E1, W1, S1 :std_logic :='0';
signal grants: std_logic;
begin
grants <= grant_N or grant_E or grant_W or grant_S or grant_L;
grants_out <= grants;
Cx <= std_logic_vector(to_unsigned(Cx_rst, Cx'length));
Rxy <= std_logic_vector(to_unsigned(Rxy_rst, Rxy'length));
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
N1 <= '1' when dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) else '0';
E1 <= '1' when cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) else '0';
W1 <= '1' when dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) else '0';
S1 <= '1' when cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) else '0';
-- Taking X1 signals to the output interface for checking with checkers
N1_out <= N1;
E1_out <= E1;
W1_out <= W1;
S1_out <= S1;
-- The combionational part
process(N1, E1, W1, S1, Rxy, Cx, flit_type, empty, grants, Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF) begin
if flit_type = "001" and empty = '0' then
Req_N_in <= ((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0);
Req_E_in <= ((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1);
Req_W_in <= ((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2);
Req_S_in <= ((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3);
Req_L_in <= not N1 and not E1 and not W1 and not S1;
elsif flit_type = "100" and empty = '0' and grants = '1' then
Req_N_in <= '0';
Req_E_in <= '0';
Req_W_in <= '0';
Req_S_in <= '0';
Req_L_in <= '0';
else -- Body flit
Req_N_in <= Req_N_FF;
Req_E_in <= Req_E_FF;
Req_W_in <= Req_W_FF;
Req_S_in <= Req_S_FF;
Req_L_in <= Req_L_FF;
end if;
end process;
end; | gpl-3.0 | fe7cb3a01096f3ab224412b32c4d7bad | 0.587992 | 2.64094 | false | false | false | false |
TanND/Electronic | VHDL/D4_C1.vhd | 1 | 1,192 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D4_C1 is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR(7 downto 0)
);
end D4_C1;
architecture D4_C1 of D4_C1 is
type state is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9);
signal s:state;
begin
next_state:process(rst,clk)
begin
if (rst='1') then s<=s0;
else
if (rising_edge(clk)) then
case s is
when s0 => s <=s1;
when s1 => s <=s2;
when s2 => s <=s3;
when s3 => s <=s4;
when s4 => s <=s5;
when s5 => s <=s6;
when s6 => s <=s7;
when s7 => s <=s8;
when s8 => s <=s9;
when s9 => s <=s0;
end case;
end if;
end if;
end process;
output_state:process(s)
begin
case s is
when s0 => seg<= x"C0";
when s1 => seg<= x"F9";
when s2 => seg<= x"A4";
when s3 => seg<= x"B0";
when s4 => seg<= x"99";
when s5 => seg<= x"92";
when s6 => seg<= x"82";
when s7 => seg<= x"F8";
when s8 => seg<= x"80";
when s9 => seg<= x"90";
end case;
end process;
end D4_C1;
-- rst=0.5Mhz; clk=20Mhz; | apache-2.0 | 4d8601fae8396eb44bb90ed4f14468eb | 0.469799 | 2.547009 | false | false | false | false |
JarrettR/FPGA-Cryptoparty | FPGA/hdl/ipcore_dir/fx2_fifo/simulation/fx2_fifo_dgen.vhd | 1 | 4,526 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
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-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
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-- applications related to the deployment of airbags, or any
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-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
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-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fx2_fifo_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fx2_fifo_pkg.ALL;
ENTITY fx2_fifo_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fx2_fifo_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 100 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fx2_fifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
| gpl-3.0 | 01697d4adfade1293e36e3dec7090881 | 0.599646 | 4.20632 | false | false | false | false |
TanND/Electronic | VHDL/nt_nt.vhd | 1 | 421 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity nt_nt is
port(
clk : in std_logic;
SI : in BIT;
SO : out BIT
);
end nt_nt;
architecture nt_nt of nt_nt is
signal tmp: bit_vector(7 downto 0);
begin
process (clk)
begin
if (clk'event and clk='1') then
tmp <= tmp(6 downto 0)& SI;
end if;
end process;
SO <= tmp(7);
end nt_nt;
--clk=20Mhz; SI= random 10ns; | apache-2.0 | 64801b87a16577c1f8e3227ff58b45e7 | 0.567696 | 2.903448 | false | false | false | false |
SoCdesign/EHA | RTL/Hand_Shaking/Checkers/Control_part_checkers/Handshaking_FC/Arbiter_checkers/RTL_and_Synthesis/Arbiter_checkers.vhd | 1 | 20,732 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Arbiter_checkers is
port (
Req_N, Req_E, Req_W, Req_S, Req_L :in std_logic;
DCTS: in std_logic;
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L: in std_logic;
Xbar_sel : in std_logic_vector(4 downto 0);
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
next_state_out: in std_logic_vector (5 downto 0);
RTS_FF: in std_logic;
RTS_FF_in: in std_logic;
-- Checker outputs
err_state_IDLE_xbar,
err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE,
err_IDLE_Req_L,
err_Local_Req_L,
err_North_Req_N,
err_East_Req_E,
err_West_Req_W,
err_South_Req_S,
err_IDLE_Req_N,
err_Local_Req_N,
err_North_Req_E,
err_East_Req_W,
err_West_Req_S,
err_South_Req_L,
err_IDLE_Req_E,
err_Local_Req_E,
err_North_Req_W,
err_East_Req_S,
err_West_Req_L,
err_South_Req_N,
err_IDLE_Req_W,
err_Local_Req_W,
err_North_Req_S,
err_East_Req_L,
err_West_Req_N,
err_South_Req_E,
err_IDLE_Req_S,
err_Local_Req_S,
err_North_Req_L,
err_East_Req_N,
err_West_Req_E,
err_South_Req_W,
err_next_state_onehot,
err_state_in_onehot,
err_DCTS_RTS_FF_state_Grant_L,
err_DCTS_RTS_FF_state_Grant_N,
err_DCTS_RTS_FF_state_Grant_E,
err_DCTS_RTS_FF_state_Grant_W,
err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel,
err_state_east_xbar_sel,
err_state_west_xbar_sel,
err_state_south_xbar_sel,
err_state_local_xbar_sel : out std_logic
);
end Arbiter_checkers;
architecture behavior of Arbiter_checkers is
CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001";
CONSTANT Local: std_logic_vector (5 downto 0) := "000010";
CONSTANT North: std_logic_vector (5 downto 0) := "000100";
CONSTANT East: std_logic_vector (5 downto 0) := "001000";
CONSTANT West: std_logic_vector (5 downto 0) := "010000";
CONSTANT South: std_logic_vector (5 downto 0) := "100000";
SIGNAL Requests: std_logic_vector (4 downto 0);
SIGNAL Grants: std_logic_vector (4 downto 0);
begin
Requests <= Req_N & Req_E & Req_W & Req_S & Req_L;
Grants <= Grant_N & Grant_E & Grant_W & Grant_S & Grant_L;
-- Checkers
--checked
process (Xbar_sel, state)
begin
if (state = IDLE and Xbar_sel /= "00000") then
err_state_IDLE_xbar <= '1';
else
err_state_IDLE_xbar <= '0';
end if;
end process;
--checked
process (state, Xbar_sel)
begin
if ( state /= IDLE and
Xbar_sel /= "00001" and Xbar_sel /= "00010" and Xbar_sel /= "00100" and Xbar_sel /= "01000" and Xbar_sel /= "10000") then
err_state_not_IDLE_xbar <= '1';
else
err_state_not_IDLE_xbar <= '0';
end if;
end process;
--checked
process (state, RTS_FF_in)
begin
if (state = IDLE and RTS_FF_in = '1') then
err_state_IDLE_RTS_FF_in <= '1';
else
err_state_IDLE_RTS_FF_in <= '0';
end if;
end process;
--checked
process (state, RTS_FF, RTS_FF_in)
begin
if ( (state = North or state = East or state = West or state = South or state = Local) and RTS_FF = '0' and RTS_FF = '0' and RTS_FF_in = '0') then
err_state_not_IDLE_RTS_FF_RTS_FF_in <= '1';
else
err_state_not_IDLE_RTS_FF_RTS_FF_in <= '0';
end if;
end process;
--checked
process (state, DCTS, RTS_FF, RTS_FF_in)
begin
if ( (state = North or state = East or state = West or state = South or state = Local) and RTS_FF = '1' and DCTS = '1' and RTS_FF_in = '1') then
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in <= '1';
else
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in <= '0';
end if;
end process;
--checked
process (state, DCTS, RTS_FF, RTS_FF_in)
begin
if ( (state = North or state = East or state = West or state = South or state = Local) and RTS_FF = '1' and DCTS = '0' and RTS_FF_in = '0') then
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in <= '1';
else
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in <= '0';
end if;
end process;
--checked
process (RTS_FF, DCTS, state, state_in)
begin
if (RTS_FF = '1' and DCTS = '0' and state /= state_in) then
err_RTS_FF_not_DCTS_state_state_in <= '1';
else
err_RTS_FF_not_DCTS_state_state_in <= '0';
end if;
end process;
--checked
process (RTS_FF, state_in, next_state_out)
begin
if (RTS_FF = '0' and state_in /= next_state_out) then
err_not_RTS_FF_state_in_next_state <= '1';
else
err_not_RTS_FF_state_in_next_state <= '0';
end if;
end process;
--checked
process (RTS_FF, DCTS, state_in, next_state_out)
begin
if (RTS_FF = '1' and DCTS = '1' and state_in /= next_state_out) then
err_RTS_FF_DCTS_state_in_next_state <= '1';
else
err_RTS_FF_DCTS_state_in_next_state <= '0';
end if;
end process;
--checked
process (RTS_FF, Grants)
begin
if (RTS_FF = '0' and Grants /= "00000") then
err_not_DCTS_Grants <= '1';
else
err_not_DCTS_Grants <= '0';
end if;
end process;
--checked
process (DCTS, RTS_FF, Grants)
begin
if (RTS_FF = '1' and DCTS = '0' and Grants /= "00000") then
err_DCTS_not_RTS_FF_Grants <= '1';
else
err_DCTS_not_RTS_FF_Grants <= '0';
end if;
end process;
--checked
process (DCTS, RTS_FF, state, Grants)
begin
if (DCTS = '1' and RTS_FF = '1' and state = IDLE and Grants /= "00000") then
err_DCTS_RTS_FF_IDLE_Grants <= '1';
else
err_DCTS_RTS_FF_IDLE_Grants <= '0';
end if;
end process;
--checked
process (DCTS, RTS_FF, state, Grants)
begin
if (DCTS = '1' and RTS_FF = '1' and state /= IDLE and
Grants /= "00001" and Grants /= "00010" and Grants /= "00100" and Grants /= "01000" and Grants /= "10000") then
err_DCTS_RTS_FF_not_IDLE_Grants_onehot <= '1';
else
err_DCTS_RTS_FF_not_IDLE_Grants_onehot <= '0';
end if;
end process;
--checked
process (state, Requests, next_state_out)
begin
if ( (state = North or state = East or state = West or state = South or state = Local or state = IDLE) and Requests = "00000" and next_state_out /= IDLE ) then
err_Requests_next_state_IDLE <= '1';
else
err_Requests_next_state_IDLE <= '0';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 1
--checked
process (state, Req_L, next_state_out)
begin
if ( state = IDLE and Req_L = '1' and next_state_out /= Local) then
err_IDLE_Req_L <= '1';
else
err_IDLE_Req_L <= '0';
end if;
end process;
process (state, Req_L, next_state_out)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and Req_L = '1' and next_state_out /= Local) then
err_Local_Req_L <= '1';
else
err_Local_Req_L <= '0';
end if;
end process;
--checked
process (state, Req_N, next_state_out)
begin
if (state = North and Req_N = '1' and next_state_out /= North) then
err_North_Req_N <= '1';
else
err_North_Req_N <= '0';
end if;
end process;
--checked
process (state, Req_E, next_state_out)
begin
if (state = East and Req_E = '1' and next_state_out /= East) then
err_East_Req_E <= '1';
else
err_East_Req_E <= '0';
end if;
end process;
--checked
process (state, Req_W, next_state_out)
begin
if (state = West and Req_W = '1' and next_state_out /= West) then
err_West_Req_W <= '1';
else
err_West_Req_W <= '0';
end if;
end process;
--checked
process (state, Req_S, next_state_out)
begin
if (state = South and Req_S = '1' and next_state_out /= South) then
err_South_Req_S <= '1';
else
err_South_Req_S <= '0';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 2
--checked
process (state, Req_L, Req_N, next_state_out)
begin
if ( state = IDLE and Req_L = '0' and Req_N = '1' and next_state_out /= North) then
err_IDLE_Req_N <= '1';
else
err_IDLE_Req_N <= '0';
end if;
end process;
process (state, Req_L, Req_N, next_state_out)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and Req_L = '0' and Req_N = '1' and next_state_out /= North) then
err_Local_Req_N <= '1';
else
err_Local_Req_N <= '0';
end if;
end process;
--checked
process (state, Req_N, Req_E, next_state_out)
begin
if (state = North and Req_N = '0' and Req_E = '1' and next_state_out /= East) then
err_North_Req_E <= '1';
else
err_North_Req_E <= '0';
end if;
end process;
process (state, Req_E, Req_W, next_state_out)
begin
if (state = East and Req_E = '0' and Req_W = '1' and next_state_out /= West) then
err_East_Req_W <= '1';
else
err_East_Req_W <= '0';
end if;
end process;
process (state, Req_W, Req_S, next_state_out)
begin
if (state = West and Req_W = '0' and Req_S = '1' and next_state_out /= South) then
err_West_Req_S <= '1';
else
err_West_Req_S <= '0';
end if;
end process;
process (state, Req_S, Req_L, next_state_out)
begin
if (state = South and Req_S = '0' and Req_L = '1' and next_state_out /= Local) then
err_South_Req_L <= '1';
else
err_South_Req_L <= '0';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 3
process (state, Req_L, Req_N, Req_E, next_state_out)
begin
if ( state = IDLE and Req_L = '0' and Req_N = '0' and Req_E = '1' and next_state_out /= East) then
err_IDLE_Req_E <= '1';
else
err_IDLE_Req_E <= '0';
end if;
end process;
process (state, Req_L, Req_N, Req_E, next_state_out)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
Req_L = '0' and Req_N = '0' and Req_E = '1' and next_state_out /= East) then
err_Local_Req_E <= '1';
else
err_Local_Req_E <= '0';
end if;
end process;
process (state, Req_N, Req_E, Req_W, next_state_out)
begin
if (state = North and Req_N = '0' and Req_E = '0' and Req_W = '1' and next_state_out /= West) then
err_North_Req_W <= '1';
else
err_North_Req_W <= '0';
end if;
end process;
process (state, Req_E, Req_W, Req_S, next_state_out)
begin
if (state = East and Req_E = '0' and Req_W = '0' and Req_S = '1' and next_state_out /= South) then
err_East_Req_S <= '1';
else
err_East_Req_S <= '0';
end if;
end process;
process (state, Req_W, Req_S, Req_L, next_state_out)
begin
if (state = West and Req_W = '0' and Req_S = '0' and Req_L = '1' and next_state_out /= Local) then
err_West_Req_L <= '1';
else
err_West_Req_L <= '0';
end if;
end process;
process (state, Req_S, Req_L, Req_N, next_state_out)
begin
if (state = South and Req_S = '0' and Req_L = '0' and Req_N = '1' and next_state_out /= North) then
err_South_Req_N <= '1';
else
err_South_Req_N <= '0';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 4
process (state, Req_L, Req_N, Req_E, Req_W, next_state_out)
begin
if ( state = IDLE and Req_L = '0' and Req_N = '0' and Req_E = '0' and Req_W = '1' and next_state_out /= West) then
err_IDLE_Req_W <= '1';
else
err_IDLE_Req_W <= '0';
end if;
end process;
process (state, Req_L, Req_N, Req_E, Req_W, next_state_out)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
Req_L = '0' and Req_N = '0' and Req_E = '0' and Req_W = '1' and next_state_out /= West) then
err_Local_Req_W <= '1';
else
err_Local_Req_W <= '0';
end if;
end process;
process (state, Req_N, Req_E, Req_W, Req_S, next_state_out)
begin
if (state = North and Req_N = '0' and Req_E = '0' and Req_W = '0' and Req_S = '1' and next_state_out /= South) then
err_North_Req_S <= '1';
else
err_North_Req_S <= '0';
end if;
end process;
process (state, Req_E, Req_W, Req_S, Req_L, next_state_out)
begin
if (state = East and Req_E = '0' and Req_W = '0' and Req_S = '0' and Req_L = '1' and next_state_out /= Local) then
err_East_Req_L <= '1';
else
err_East_Req_L <= '0';
end if;
end process;
process (state, Req_W, Req_S, Req_L, Req_N, next_state_out)
begin
if (state = West and Req_W = '0' and Req_S = '0' and Req_L = '0' and Req_N = '1' and next_state_out /= North) then
err_West_Req_N <= '1';
else
err_West_Req_N <= '0';
end if;
end process;
process (state, Req_S, Req_L, Req_N, Req_E, next_state_out)
begin
if (state = South and Req_S = '0' and Req_L = '0' and Req_N = '0' and Req_E = '1' and next_state_out /= East) then
err_South_Req_E <= '1';
else
err_South_Req_E <= '0';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 5
process (state, Req_L, Req_N, Req_E, Req_W, Req_S, next_state_out)
begin
if ( state = IDLE and Req_L = '0' and Req_N = '0' and Req_E = '0' and Req_W = '0' and Req_S = '1'
and next_state_out /= South) then
err_IDLE_Req_S <= '1';
else
err_IDLE_Req_S <= '0';
end if;
end process;
process (state, Req_L, Req_N, Req_E, Req_W, Req_S, next_state_out)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
Req_L = '0' and Req_N = '0' and Req_E = '0' and Req_W = '0' and Req_S = '1'
and next_state_out /= South) then
err_Local_Req_S <= '1';
else
err_Local_Req_S <= '0';
end if;
end process;
process (state, Req_N, Req_E, Req_W, Req_S, Req_L, next_state_out)
begin
if (state = North and Req_N = '0' and Req_E = '0' and Req_W = '0' and Req_S = '0' and Req_L = '1'
and next_state_out /= Local) then
err_North_Req_L <= '1';
else
err_North_Req_L <= '0';
end if;
end process;
process (state, Req_E, Req_W, Req_S, Req_L, Req_N, next_state_out)
begin
if (state = East and Req_E = '0' and Req_W = '0' and Req_S = '0' and Req_L = '0' and Req_N = '1'
and next_state_out /= North) then
err_East_Req_N <= '1';
else
err_East_Req_N <= '0';
end if;
end process;
process (state, Req_W, Req_S, Req_L, Req_N, Req_E, next_state_out)
begin
if (state = West and Req_W = '0' and Req_S = '0' and Req_L = '0' and Req_N = '0' and Req_E = '1'
and next_state_out /= East) then
err_West_Req_E <= '1';
else
err_West_Req_E <= '0';
end if;
end process;
process (state, Req_S, Req_L, Req_N, Req_E, Req_W, next_state_out)
begin
if (state = South and Req_S = '0' and Req_L = '0' and Req_N = '0' and Req_E = '0' and Req_W = '1'
and next_state_out /= West) then
err_South_Req_W <= '1';
else
err_South_Req_W <= '0';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
process (next_state_out)
begin
if (next_state_out /= IDLE and next_state_out /= North and next_state_out /= East and next_state_out /= West and
next_state_out /= South and next_state_out /= Local) then
err_next_state_onehot <= '1';
else
err_next_state_onehot <= '0';
end if;
end process;
process (state_in)
begin
if (state_in /= IDLE and state_in /= North and state_in /= East and state_in /= West and
state_in /= South and state_in /= Local) then
err_state_in_onehot <= '1';
else
err_state_in_onehot <= '0';
end if;
end process;
process (DCTS, RTS_FF, state, Grant_L)
begin
if (DCTS = '1' and RTS_FF = '1' and state /= IDLE and state /= North and state /=East and state /=West and
state /= South and Grant_L = '0' ) then
err_DCTS_RTS_FF_state_Grant_L <= '1';
else
err_DCTS_RTS_FF_state_Grant_L <= '0';
end if;
end process;
process (DCTS, RTS_FF, state, Grant_N)
begin
if (DCTS = '1' and RTS_FF = '1' and state = North and Grant_N = '0' ) then
err_DCTS_RTS_FF_state_Grant_N <= '1';
else
err_DCTS_RTS_FF_state_Grant_N <= '0';
end if;
end process;
process (DCTS, RTS_FF, state, Grant_E)
begin
if (DCTS = '1' and RTS_FF = '1' and state = East and Grant_E = '0' ) then
err_DCTS_RTS_FF_state_Grant_E <= '1';
else
err_DCTS_RTS_FF_state_Grant_E <= '0';
end if;
end process;
process (DCTS, RTS_FF, state, Grant_W)
begin
if (DCTS = '1' and RTS_FF = '1' and state = West and Grant_W = '0' ) then
err_DCTS_RTS_FF_state_Grant_W <= '1';
else
err_DCTS_RTS_FF_state_Grant_W <= '0';
end if;
end process;
process (DCTS, RTS_FF, state, Grant_S)
begin
if (DCTS = '1' and RTS_FF = '1' and state = South and Grant_S = '0' ) then
err_DCTS_RTS_FF_state_Grant_S <= '1';
else
err_DCTS_RTS_FF_state_Grant_S <= '0';
end if;
end process;
process (state, Xbar_sel)
begin
if (state = North and Xbar_sel /= "00001" ) then
err_state_north_xbar_sel <= '1';
else
err_state_north_xbar_sel <= '0';
end if;
end process;
process (state, Xbar_sel)
begin
if (state = East and Xbar_sel /= "00010" ) then
err_state_east_xbar_sel <= '1';
else
err_state_east_xbar_sel <= '0';
end if;
end process;
process (state, Xbar_sel)
begin
if (state = West and Xbar_sel /= "00100" ) then
err_state_west_xbar_sel <= '1';
else
err_state_west_xbar_sel <= '0';
end if;
end process;
process (state, Xbar_sel)
begin
if (state = South and Xbar_sel /= "01000" ) then
err_state_south_xbar_sel <= '1';
else
err_state_south_xbar_sel <= '0';
end if;
end process;
process (state, Xbar_sel)
begin
if (state /= IDLE and state /= North and state /= East and state /= West and state /= South and Xbar_sel /= "10000" ) then
err_state_local_xbar_sel <= '1';
else
err_state_local_xbar_sel <= '0';
end if;
end process;
end behavior; | gpl-3.0 | 280840f4d732f22b60a6d844e9b608cf | 0.508586 | 2.958756 | false | false | false | false |
lnls-dig/dsp-cores | hdl/modules/rp_math_pack/rp_math_pack.vhd | 1 | 16,580 | -------------------------------------------------------------------------------
-- Title : Real precision trigonometric function math package
-- Project : (some of the functions are taylored for CORDIC implementations
-- and testbenches)
-------------------------------------------------------------------------------
-- File : rp_math_pack.vhd
-- Author : Matthias Werner <[email protected]>
-- Company :
-- Created : 2015-01-24
-- Last update: 2015-01-24
-- Platform :
-- Standard : VHDL-93
-------------------------------------------------------------------------------
-- Description: This package contains the basic trigonometric functions similar
-- to the functions in IEEE.MATH_REAL, but with a higher precision.
-- Additionally, conversion function between real and (un)signed are included.
-- The functions can be helpful for CORDIC designs and testbenches.
-------------------------------------------------------------------------------
-- C O P Y R I G H T N O T E :
-------------------------------------------------------------------------------
-- This file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This package is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License.
-- If not, see <http://www.gnu.org/licenses/>.
-- Copyright (c) 2015 Matthias Werner
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-01-24 1.0 Matthias Werner Created
-------------------------------------------------------------------------------
-- Detailed description:
-- Package with
-- selfmade trigonometric functions with full precision of real data type
-- selfmade conversion functions for arguments > 32 bit
-- Simulation for trigonometric functions:
-- verified for selected values with external high precision calculator program
-- Simulation for conversion functions done 2014-08-29:
-- For width = 6: all conversion functions tested for all possible numbers, correct rounding verified
-- For numbers around 9.0e15: verified that full precision of real data type is exploited
-- For numbers above 1.0e18: verified that conversion still works with real data type precision
-- Attention:
-- The built-in trigonometric functions and the built-in functions ROUND, FLOOR, CEIL, MOD offer
-- only a limited precision in the order of 32 bits - this has to be considered for the design of
-- the selfmade functions!
--------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.MATH_REAL.all;
use IEEE.NUMERIC_STD.ALL;
package rp_math_pack is
-- Function declarations
function rp_sin (constant f_arg : in real) return real;
function rp_cos (constant f_arg : in real) return real;
function rp_tan (constant f_arg : in real) return real;
function rp_arctan(constant f_arg : in real) return real;
function rp_arctan_nosqrt(constant f_arg : in real) return real; -- Limited arg range, no sqrt() used
function rp_arcsin(constant f_arg : in real) return real;
function rp_arccos(constant f_arg : in real) return real;
function unsigned_to_real(constant u_arg : in unsigned) return real;
function signed_to_real(constant s_arg : in signed) return real;
function mod2(constant f_arg : in real) return real; -- Modulo 2.0
function real_to_unsigned(constant f_arg : in real; constant i_wid : in positive) return unsigned;
function real_to_signed(constant f_arg : in real; constant i_wid : in positive) return signed;
function real_to_signed_old(constant f_arg : in real; constant WID : in positive) return signed;
end rp_math_pack;
---------------
-- Package body
---------------
package body rp_math_pack is
-----------------------------------------------------------
-- Selfmade sine function for argument range -PI/2 to +PI/2
-----------------------------------------------------------
function rp_sin_lowrange (constant f_arg_lorange : in real) return real is
variable f_xpow : real;
variable f_xpow2 : real;
variable f_facul : real;
variable f_sum : real;
variable f_2i : real;
begin
-- Init variables
f_xpow := f_arg_lorange;
f_xpow2 := f_arg_lorange * f_arg_lorange;
f_facul := 1.0;
f_sum := f_arg_lorange;
-- Iteration loop
for i in 1 to 13 loop
f_2i := real(2*i);
f_facul := f_facul * f_2i * (f_2i + 1.0);
f_xpow := -f_xpow * f_xpow2;
f_sum := f_sum + f_xpow / f_facul;
end loop;
-- Return result
return f_sum;
end rp_sin_lowrange;
-------------------------------------------------
-- Selfmade sine function for full argument range
-------------------------------------------------
function rp_sin (constant f_arg : in real) return real is
variable y_flag_neg_result : boolean;
variable f_arg1 : real;
variable f_result : real;
begin
-- Init variable
y_flag_neg_result := False;
-- Reduce range to 0 .. 2*PI
f_arg1 := f_arg MOD (2.0 * MATH_PI);
-- Reduce range to 0 .. PI
if f_arg1 > MATH_PI then
f_arg1 := f_arg1 - MATH_PI;
y_flag_neg_result := True;
end if;
-- Reduce range to 0 .. PI/2
if f_arg1 > MATH_PI/2.0 then
f_arg1 := MATH_PI - f_arg1;
end if;
-- Call function for reduced range, negate if necessary and return the result
f_result := rp_sin_lowrange(f_arg1);
if y_flag_neg_result then
f_result := -f_result;
end if;
return f_result;
end rp_sin;
---------------------------------------------------
-- Selfmade cosine function for full argument range
---------------------------------------------------
function rp_cos (constant f_arg : in real) return real is
begin
return rp_sin(f_arg + MATH_PI / 2.0);
end rp_cos;
------------------------------------------------
-- Selfmade tan function for full argument range
------------------------------------------------
function rp_tan (constant f_arg : in real) return real is
begin
return rp_sin(f_arg) / rp_cos(f_arg);
end rp_tan;
---------------------------------
-- Selfmade arctan for arg <= 0.5
---------------------------------
function rp_arctan_lorange(f_arg_lorange : real) return real is
variable f_arg_v : real := f_arg_lorange;
variable f_result : real := 0.0;
begin
for i in 0 to 25 loop
f_result := f_result + real((-1)**i) * f_arg_v**(2*i+1) / real(2*i+1);
end loop;
return f_result;
end function rp_arctan_lorange;
------------------------------------------
-- Selfmade arctan for full argument range
------------------------------------------
function rp_arctan (constant f_arg : in real) return real is
variable f_abs_arg : real;
variable y_flag_neg_result : boolean;
variable f_abs_result : real;
begin
-- Reduce range to positive values
f_abs_arg := abs(f_arg);
-- Range 0.0 to 1.0
if (f_abs_arg <= 1.0) then
f_abs_result := 2.0 * rp_arctan_lorange(f_abs_arg / (1.0 + sqrt(1.0 + f_abs_arg * f_abs_arg)));
-- Range 1.0 to infinite
else
f_abs_result := MATH_PI / 2.0 - 2.0 * rp_arctan_lorange(1.0 / (f_abs_arg + sqrt(1.0 + f_abs_arg * f_abs_arg)));
end if;
-- Return result regarding argument sign
if f_arg < 0.0 then
return -f_abs_result;
else
return f_abs_result;
end if;
end function rp_arctan;
-------------------------------------------------------------------------------------------
-- Selfmade arctan without use of sqrt() for arg = 1.0 or arg <= 0.5 (as needed for CORDIC)
--
-- Although this algorithm works only for the limited argument range used in CORDIC, its
-- advantage is that the sqrt() function is not used. This can be good if the precision of
-- the sqrt() is not known or not high enough. In ISE, however, the sqrt() is precise enough.
-------------------------------------------------------------------------------------------
function rp_arctan_nosqrt(constant f_arg : in real) return real is
variable f_arg_v : real := f_arg;
variable f_result : real := 0.0;
begin
if f_arg > 0.99 AND f_arg < 1.01 then -- For f_arg = 1.0 (error tolerant)
return MATH_PI / 4.0;
else
return rp_arctan_lorange(f_arg);
end if;
end function rp_arctan_nosqrt;
------------------------------------------
-- Selfmade arcsin for full argument range
------------------------------------------
function rp_arcsin (constant f_arg : in real) return real is
begin
return 2.0 * rp_arctan(f_arg / (1.0 + sqrt(1.0 - f_arg * f_arg)));
end rp_arcsin;
------------------------------------------
-- Selfmade arccos for full argument range
------------------------------------------
function rp_arccos (constant f_arg : in real) return real is
begin
return MATH_PI/2.0 - rp_arcsin(f_arg);
end rp_arccos;
------------------------------------------------------------------------
-- Selfmade unsigned to real conversion for numbers up to 2**53 = 9.0e15
------------------------------------------------------------------------
function unsigned_to_real(constant u_arg : in unsigned) return real is
variable f_result : real := 0.0;
begin
-- For all bits, starting with MSB
for i in u_arg'range loop
-- Loop: multiply by 2, add 1 if bit is '1'
f_result := f_result * 2.0;
if u_arg(i) = '1' then
f_result := f_result + 1.0;
end if;
end loop;
return f_result;
end unsigned_to_real;
----------------------------------------------------------------------
-- Selfmade signed to real conversion for numbers up to 2**53 = 9.0e15
----------------------------------------------------------------------
function signed_to_real(constant s_arg : in signed) return real is
variable s_arg_abs : signed(s_arg'high+1 downto 0); -- arg extended by 1 bit
variable u_arg_abs : unsigned(s_arg'high+1 downto 0); -- s_arg_abs converted to unsigned
variable f_result : real;
begin
-- Absolute value of arg (extended by 1 bit to cover special case 10000....)
s_arg_abs := abs(resize(s_arg, s_arg'length+1));
u_arg_abs := unsigned(s_arg_abs);
-- Convert unsigned to real
f_result := unsigned_to_real(u_arg_abs);
-- Include sign and return
if s_arg < 0 then
f_result := -f_result;
end if;
return f_result;
end signed_to_real;
----------------------------------------
-- Modulo 2 for numbers < 2**53 = 9.0e15
----------------------------------------
-- Called by function real_to_unsigned().
-- This function was designed because the built-in MOD function works only
-- correctly for arguments < 2**32.
-- As also the FLOOR function works only correctly for arguments up to 2**32,
-- a two-step-trick is applied:
-- 1)The argument is reduced maintaining the MOD 2 properties. In this step a division
-- by 2.0**31, followed by a subtraction and subsequent multiplication by 2**31 is used
-- to keep the argument for the FLOOR function below 2**32.
-- 2)The built-in MOD 2 function is applied on the reduced argument.
----------------------------------------
function mod2(constant f_arg : in real) return real is
variable f_quot : real;
begin
-- The MOD function does only work correctly for arguments < 2**32, therefore a trick is applied
f_quot := f_arg / 2.0**31;
return (2.0**31 * (f_quot - floor(f_quot))) MOD 2.0;
end mod2;
------------------------------------------------------------------------
-- Selfmade real to unsigned conversion for numbers up to 2**53 = 9.0e15
------------------------------------------------------------------------
-- This function was designed to convert numbers > 2**31 to unsigned.
-- As the built-in ROUND function works correctly only for arguments < 2**31, a trick was
-- applied to emulate (ROUND and CONVERT): first 0.49 is added, then the MOD - sub - divide loop
-- is applied. This results in (almost) correct rounding also for large numbers - this
-- was verified by simulation for small numbers and for large numbers around 9.0e15.
------------------------------------------------------------------------
function real_to_unsigned(constant f_arg : in real; constant i_wid : in positive) return unsigned is
variable f_arg_04 : real; -- Argument rounded and increased by 0.4
variable f_next : real;
variable u_result : unsigned(i_wid-1 downto 0) := (others => '0');
begin
-- Add 0.49 to achieve correct rounding in combination with the algorithm used.
f_arg_04 := f_arg + 0.49;
-- Error if negative argument
-- !!! The assert "fails" for Virtex-5 (not for Artix-7) in Implementation (not in Simulation) if
-- !!! "f_arg_04 > 0.0" is used instead of "f_arg_04 >= 0.0" even if f_arg_04 is 5.0 (ISE bug ?)
assert f_arg_04 >= 0.0 report "neg. arg at func. real_to_unsigned" severity failure; -- see comment above
-- For all bits, starting at LSB
f_next := f_arg_04;
for i in 0 to i_wid-1 loop
-- Loop: check if value MOD 2 is 1; then divide by 2
if mod2(f_next) >= 0.99 then -- Selfmade modulo 2 function which works also for arguments > 2**32
u_result(i) := '1';
f_next := f_next - 1.0;
end if;
f_next := f_next / 2.0;
end loop;
-- Detect if result was truncated due to small width parameter
assert f_next < 0.5 report "i_wid too small in function real_to_unsigned -> truncated" severity warning;
-- Return result
return u_result;
end real_to_unsigned;
----------------------------------------------------------------------
-- Selfmade real to signed conversion for numbers up to 2**53 = 9.0e15
----------------------------------------------------------------------
function real_to_signed(constant f_arg : in real; constant i_wid : in positive) return signed is
variable f_arg_abs : real;
variable b_sign : std_logic;
variable u_result_long : unsigned(i_wid downto 0); -- Result 1 bit extended, unsigned
variable s_result_long : signed(i_wid downto 0); -- Result 1 bit extended, signed
variable s_result : signed(i_wid-1 downto 0); -- Result
begin
-- Absolute value, tolerant to rounding errors; remember sign
if f_arg < -0.25 then
f_arg_abs := -f_arg;
b_sign := '1';
else
f_arg_abs := f_arg;
b_sign := '0';
end if;
-- Convert to unsigned, result 1 bit longer to cover special case of most negative number 10000...
u_result_long := real_to_unsigned(f_arg_abs, i_wid+1);
-- Include sign
s_result_long := signed(u_result_long);
if b_sign = '1' then
s_result_long := -s_result_long;
end if;
-- Taylor to desired bit width (1 bit less) and check if truncated
s_result := resize(s_result_long, i_wid);
assert s_result_long = s_result
report "i_wid too small in function real_to_signed -> truncated" severity warning;
-- Return result
return s_result;
end real_to_signed;
--------------------------------------------------------------------------------------------
-- Obsolete real to signed conversion, works correctly up to output width of approx. 50 bits
--
-- This algorithm was initially used to compute the arctan table; now replaced by real_to_signed()
-- Works only for positive numbers - just the return value is of signed data type
--------------------------------------------------------------------------------------------
function real_to_signed_old(constant f_arg : in real; constant WID : in positive) return signed is
variable f_arg_v : real := f_arg;
variable s_result_v : signed(WID downto 0) := (others => '0');
begin
-- Scale argument
f_arg_v := f_arg_v / 2.0**(WID-1);
-- Extract (WID + 1) bits, use LSB for rounding after loop
for i in WID downto 0 loop
if f_arg_v >= 1.0 then
s_result_v(i) := '1';
f_arg_v := f_arg_v - 1.0;
else
s_result_v(i) := '0';
end if;
f_arg_v := f_arg_v * 2.0;
end loop;
-- Round
s_result_v(WID downto 1) := s_result_v(WID downto 1) + ('0' & s_result_v(0));
return s_result_v(WID downto 1);
end function real_to_signed_old;
end rp_math_pack;
| lgpl-3.0 | c86c325f440c7635ae184a061a2fc71d | 0.560615 | 3.641555 | false | false | false | false |
SoCdesign/EHA | RTL/Fault_Management/SHMU_prototype/version_2/Arbiter_one_hot.vhd | 2 | 7,577 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Arbiter is
port ( reset: in std_logic;
clk: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules
DCTS: in std_logic; -- Getting the CTS signal from the input FIFO of the next router/NI (for hand-shaking)
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
Xbar_sel : out std_logic_vector(4 downto 0); -- select lines for XBAR
RTS: out std_logic -- Valid output which is sent to the next router/NI to specify that the data on the output port is valid
);
end;
architecture behavior of Arbiter is
-- next
-- Arbiter router or NI
-- --- ---------------------------- ---- ----
-- from LBDR ---> |Req(s) RTS | -----> |DRTS
-- To FIFO <--- |Grant(s) DCTS| <----- |CTS
-- to XBAR <--- |Xbar_sel | |
-- --- ---------------------------- ---- ----
--------------------------------------------------------------------------------------------
-- an example of a request/grant + handshake process with next router or NI
--CLK _|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|__
-- Req _____|'''''''''''''''''''''''''''''''''''''''''''|________
-- _________ ___________________ _______ _______ _______ ____
-- TX _________X_______HEADER______X_Body__X_Body__X__Tail_X____
-- Grant _________________________|'''|___|'''|___|'''|____________
-- RTS _________|'''''''''''''''''''|___|'''''''|___|'''''''|____
-- DCTS _________________________|'''|_______|'''|_______|'''|____
-- |<---------clear----------->|
-- | to send |
--------------------------------------------------------------------------------------------
--TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SUBTYPE STATE_TYPE IS STD_LOGIC_VECTOR (5 downto 0);
CONSTANT IDLE: STATE_TYPE := "000001";
CONSTANT Local: STATE_TYPE := "000010";
CONSTANT North: STATE_TYPE := "000100";
CONSTANT East: STATE_TYPE := "001000";
CONSTANT West: STATE_TYPE := "010000";
CONSTANT South: STATE_TYPE := "100000";
SIGNAL state, state_in, next_state : STATE_TYPE := IDLE;
SIGNAL RTS_FF, RTS_FF_in: std_logic;
begin
-- process for updating the state of arbiter's FSM, also setting RTS based on the state (if Grant is given or not)
process(clk, reset)begin
if reset = '0' then
state<=IDLE;
RTS_FF <= '0';
elsif clk'event and clk = '1' then
-- no grant given yet, it might be that there is no request to
-- arbiter or request is there, but the next router's/NI's FIFO is full
state <= state_in;
RTS_FF <= RTS_FF_in;
end if;
end process;
-- anything below here is pure combinational
RTS <= RTS_FF;
process(RTS_FF, DCTS, state, next_state)begin
if RTS_FF = '1' and DCTS = '0' then
state_in <= state;
else
state_in <= next_state;
end if;
end process;
process(state, RTS_FF, DCTS)begin
if state = IDLE then
RTS_FF_in <= '0';
-- if there was a grant given to one of the inputs,
-- tell the next router/NI that the output data is valid
else
if RTS_FF = '1' and DCTS = '1' then
RTS_FF_in <= '0';
else
RTS_FF_in <= '1';
end if;
end if ;
end process;
-- sets the grants using round robin
-- the order is L --> N --> E --> W --> S and then back to L
process(state, Req_N, Req_E, Req_W, Req_S, Req_L, DCTS, RTS_FF)begin
Grant_N <= '0';
Grant_E <= '0';
Grant_W <= '0';
Grant_S <= '0';
Grant_L <= '0';
Xbar_sel<= "00000";
case(state) is
when IDLE =>
Xbar_sel<= "00000";
If Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
else
next_state <= IDLE;
end if;
when North =>
Grant_N <= DCTS and RTS_FF ;
Xbar_sel<= "00001";
If Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
else
next_state <= IDLE;
end if;
when East =>
Grant_E <= DCTS and RTS_FF;
Xbar_sel<= "00010";
If Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
else
next_state <= IDLE;
end if;
when West =>
Grant_W <= DCTS and RTS_FF;
Xbar_sel<= "00100";
If Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
else
next_state <= IDLE;
end if;
when South =>
Grant_S <= DCTS and RTS_FF;
Xbar_sel<= "01000";
If Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
else
next_state <= IDLE;
end if;
when others => -- Local
Grant_L <= DCTS and RTS_FF;
Xbar_sel<= "10000";
If Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
else
next_state <= IDLE;
end if;
end case ;
end process;
end;
| gpl-3.0 | c8e5268f87c98ef7d7ddb45c0afc9201 | 0.399498 | 4.322305 | false | false | false | false |
Ana06/function-graphing-FPGA | KbdRxData.vhd | 2 | 2,839 | ----------------------------------------------------------------------------------
-- Company:
-- EngINeer: Ali Diouri
--
-- Create Date: 20:59:21 05/03/2012
-- Design Name:
-- Module Name: KbdCore - Behavioral
-- Project Name: KbdRxData
-- Target Devices:
-- TOol versions: XilINx ISE 14.4
-- Description:
--
-- DepENDencies:
--
-- RevISion:
-- RevISion 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
entity KbdRxData IS
Port (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
kbd_Data : IN STD_LOGIC;
kbd_clk : IN STD_LOGIC;
Rx_en : IN STD_LOGIC;
dataValid : OUT STD_LOGIC;
busy : OUT STD_LOGIC;
Data : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END KbdRxData;
ARCHITECTURE Behavioral OF KbdRxData IS
SIGNAL tmpData11 : std_logic_vecTOr(0 TO 10);
SIGNAL count : std_logic_vecTOr(3 DOWNTO 0);
SIGNAL dataSTOred : std_logic;
SIGNAL startGet : std_logic;
BEGIN
PROCESS (clk,rst)
BEGIN
IF (rst ='1') THEN
dataSTOred <= '0';
startGet <= '0';
count <= (OTHERS=>'0');
tmpData11 <= (OTHERS=>'0');
ELSIF (clk='1' and clk'Event) THEN
IF (Rx_en = '1') THEN
IF (startGet = '0') THEN
IF (kbd_data = '0') THEN
startGet <= '1';
ELSE
startGet <= '0';
END IF;
ELSIF(kbd_clk = '0') THEN
IF (dataSTOred = '0') THEN
count <= count + conv_std_logic_vecTOr(1,count'LENGTH);
tmpData11 <= kbd_Data & tmpData11(0 TO 9);
dataSTOred <= '1';
END IF;
ELSIF(kbd_clk = '1') THEN
dataSTOred <= '0';
IF(count = conv_std_logic_vecTOr(11,count'LENGTH)) THEN
startGet <= '0';
count <= (OTHERS=>'0');
END IF;
END IF;
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(rst, clk)
BEGIN
IF(rst = '1') THEN
busy <= '0';
dataValid <= '0';
Data <= (OTHERS=>'0');
ELSIF (clk = '1' and clk'Event) THEN
busy <= startGet;
Data <= (OTHERS=>'0');
dataValid <= '0';
IF (count = conv_std_logic_vecTOr(11,count'LENGTH)) and (kbd_clk = '1') THEN
data <= tmpData11(2 TO 9);
dataValid <= '1';
END IF;
END IF;
END PROCESS;
END Behavioral;
| gpl-3.0 | b4c413b44579c3b4739841c6420aaffa | 0.440296 | 3.800535 | false | false | false | false |
JarrettR/FPGA-Cryptoparty | FPGA/hdl/sha1_pad.vhd | 1 | 2,469 | --------------------------------------------------------------------------------
-- sha1_pad.vhd
-- Pads SHA1 input to nearest 16 word msg and appends length nibble
-- Copyright (C) 2016 Jarrett Rainier
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.sha1_pkg.all;
entity sha1_pad is
port(
clk_i : in std_ulogic;
rst_i : in std_ulogic;
dat_i : in std_ulogic_vector(0 to 31);
valid_i : in std_ulogic;
dat_w_o : out w_input
);
end sha1_pad;
architecture RTL of sha1_pad is
signal w: w_input;
signal w_temp: w_input;
-- Max length of WPA2 will never go over two frames
signal i : integer range 0 to 127;
begin
process(clk_i)
begin
if (clk_i'event and clk_i = '1') then
if rst_i = '1' then
for i in 0 to 15 loop
w(i) <= "00000000000000000000000000000000";
end loop;
else
for i in 1 to 15 loop
w(i) <= w_temp(i - 1);
end loop;
end if;
end if;
end process;
dat_w_o <= w_temp;
--Alt: Use a generate statement
w_temp(0) <= dat_i;
w_temp(1) <= w(1);
w_temp(2) <= w(2);
w_temp(3) <= w(3);
w_temp(4) <= w(4);
w_temp(5) <= w(5);
w_temp(6) <= w(6);
w_temp(7) <= w(7);
w_temp(8) <= w(8);
w_temp(9) <= w(9);
w_temp(10) <= w(10);
w_temp(11) <= w(11);
w_temp(12) <= w(12);
w_temp(13) <= w(13);
w_temp(14) <= w(14);
w_temp(15) <= w(15);
end RTL; | gpl-3.0 | 4a25108417d0efa66a41c9519c4f274c | 0.490482 | 3.497167 | false | false | false | false |
Ana06/function-graphing-FPGA | numero.vhd | 2 | 18,968 | ----------------------------------------------------------------------------------
-- Company: Nameless2
-- Engineer: Ana María Martínez Gómez, Aitor Alonso Lorenzo, Víctor Adolfo Gallego Alcalá
--
-- Create Date: 13:10:11 02/26/2014
-- Design Name:
-- Module Name: expresion - Behavioral
-- Project Name: Representación gráfica de funciones
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use std.textio.all;
--use work.tipos.all
entity numero is
port(
clk: in std_logic;
s: in std_logic_vector(20 downto 0);
addr : in std_logic_vector(5 downto 0);
do : out std_logic_vector(0 to 9)
);
end numero;
architecture Behavioral of numero is
constant anchoExp: integer:=216;
type matriz is array(0 to 63) of std_logic_vector(9 downto 0);
signal num: matriz;
signal miInt, miInt1, miInt2, miInt3, tuInt, tuInt1, tuInt2: std_logic_vector(9 downto 0);
signal ultraAux: std_logic_vector(20 downto 0);
type coeficiente is array (0 to 5) of std_logic_vector(9 downto 0);
constant nada: coeficiente:= ((others=>'0'), (others=>'0'), (others=>'0'), (others=>'0'), (others=>'0'), (others=>'0'));
constant cero: coeficiente:= ("1111111111", "1111111111", "1100000011", "1100000011", "1111111111", "1111111111");
constant uno: coeficiente:= ((others=>'0'), (others=>'0'), "1111111111", "1111111111", (others=>'0'), (others=>'0'));
constant dos: coeficiente:= ("1100111111", "1100111111", "1100110011", "1100110011", "1111110011", "1111110011");
constant tres: coeficiente:= ("1100000011", "1100110011", "1100110011", "1100110011", "1111111111", "1111111111");
constant cuatro: coeficiente:= ("1111110000", "1111110000", "0000110000", "0000110000", "1111111111", "1111111111");
constant cinco: coeficiente:= ("1111110011", "1111110011", "1100110011", "1100110011", "1100111111", "1100111111");
constant seis: coeficiente:= ("1111111111", "1111111111", "1100110011", "1100110011", "1100111111", "1100111111");
constant siete: coeficiente:= ("1100000000", "1100000000", "1100110000", "1111111111", "1111111111", "0000110000");
constant ocho: coeficiente:= ("1111111111", "1111111111", "1100110011", "1100110011", "1111111111", "1111111111");
constant nueve: coeficiente:= ("1111110000", "1111110000", "1100110000", "1100110000", "1111111111", "1111111111");
constant medioInf: coeficiente:= ("0000100000", "0011011000", "0100000100", "0100000100", "0010001000", "0001010000");
begin
--OBTENER TROZO DE LA EXPRESIÓN PEDIDO
expPedida: process (clk)
begin
if rising_edge(clk) then
do <= num(conv_integer(addr));
end if;
end process expPedida;
--EXPRESIÓN
--ESPACIOS (1 columna de ceros)
num(3)<=(others=>'0');
num(17)<=(others=>'0');
num(24)<=(others=>'0');
num(31)<=(others=>'0');
num(34)<=(others=>'0');
num(41)<=(others=>'0');
num(48)<=(others=>'0');
ultraAux <= 0-s;
calculo: process(s, ultraAux)
begin
--SIGNO
if s(20) = '0' then -- si es + no se muestra nada pues es el primer sumando
num(0)<=(others=>'0');
num(1)<=(others=>'0');
num(2)<=(others=>'0');
miInt <= s(19 downto 10);
tuInt <= s(9 downto 0);
else -- signo -
num(0)<="0000110000";
num(1)<="0000110000";
num(2)<="0000110000";
miInt <= ultraAux(19 downto 10);
tuInt <= ultraAux(9 downto 0);
end if;
end process calculo;
calcula: process(miInt, s)
begin
if s = "100000000000000000000" or s = "011111111111111111111" then
num(4)<= medioInf(0);
num(5)<= medioInf(1);
num(6)<= medioInf(2);
num(7)<= medioInf(3);
num(8)<= medioInf(4);
num(9)<= medioInf(5);
miInt1 <= miInt;
--El mayor numero que pueden dar en valor absoluto es 1024
elsif miInt >= 1000 then --primer numero un 1
num(4)<= uno(0);
num(5)<= uno(1);
num(6)<= uno(2);
num(7)<= uno(3);
num(8)<= uno(4);
num(9)<= uno(5);
miInt1 <= miInt -1000;
else --primer numero es un cero asi que no lo pintamos
num(4)<= nada(0);
num(5)<= nada(1);
num(6)<= nada(2);
num(7)<= nada(3);
num(8)<= nada(4);
num(9)<= nada(5);
miInt1 <= miInt;
end if;
if s = "100000000000000000000" or s = "011111111111111111111" then
num(10)<="0000100000";
-- NO PUNTO
num(32)<=(others=>'0');
num(33)<=(others=>'0');
else
num(10)<=(others=>'0');
--PUNTO
num(32)<="0000001111";
num(33)<="0000001111";
end if;
end process calcula;
calcula1: process(miInt1, s, miInt)
begin
--El mayor numero que puede llegar es 900
if s = "100000000000000000000" or s = "011111111111111111111" then
num(11)<= medioInf(5);
num(12)<= medioInf(4);
num(13)<= medioInf(3);
num(14)<= medioInf(2);
num(15)<= medioInf(1);
num(16)<= medioInf(0);
miInt2 <= miInt1;
elsif miInt1 >= 900 then --segundo numero un 9
num(11)<= nueve(0);
num(12)<= nueve(1);
num(13)<= nueve(2);
num(14)<= nueve(3);
num(15)<= nueve(4);
num(16)<= nueve(5);
miInt2 <= miInt1 - 900;
elsif miInt1 >= 800 then --segundo numero un 8
num(11)<= ocho(0);
num(12)<= ocho(1);
num(13)<= ocho(2);
num(14)<= ocho(3);
num(15)<= ocho(4);
num(16)<= ocho(5);
miInt2 <= miInt1 - 800;
elsif miInt1 >= 700 then --segundo numero un 7
num(11)<= siete(0);
num(12)<= siete(1);
num(13)<= siete(2);
num(14)<= siete(3);
num(15)<= siete(4);
num(16)<= siete(5);
miInt2 <= miInt1 - 700;
elsif miInt1 >= 600 then --segundo numero un 6
num(11)<= seis(0);
num(12)<= seis(1);
num(13)<= seis(2);
num(14)<= seis(3);
num(15)<= seis(4);
num(16)<= seis(5);
miInt2 <= miInt1 - 600;
elsif miInt1 >= 500 then --segundo numero un 5
num(11)<= cinco(0);
num(12)<= cinco(1);
num(13)<= cinco(2);
num(14)<= cinco(3);
num(15)<= cinco(4);
num(16)<= cinco(5);
miInt2 <= miInt1 - 500;
elsif miInt1 >= 400 then --segundo numero un 4
num(11)<= cuatro(0);
num(12)<= cuatro(1);
num(13)<= cuatro(2);
num(14)<= cuatro(3);
num(15)<= cuatro(4);
num(16)<= cuatro(5);
miInt2 <= miInt1 - 400;
elsif miInt1 >= 300 then --segundo numero un 3
num(11)<= tres(0);
num(12)<= tres(1);
num(13)<= tres(2);
num(14)<= tres(3);
num(15)<= tres(4);
num(16)<= tres(5);
miInt2 <= miInt1 - 300;
elsif miInt1 >= 200 then --segundo numero un 2
num(11)<= dos(0);
num(12)<= dos(1);
num(13)<= dos(2);
num(14)<= dos(3);
num(15)<= dos(4);
num(16)<= dos(5);
miInt2 <= miInt1 - 200;
elsif miInt1 >= 100 then --segundo numero un 1
num(11)<= uno(0);
num(12)<= uno(1);
num(13)<= uno(2);
num(14)<= uno(3);
num(15)<= uno(4);
num(16)<= uno(5);
miInt2 <= miInt1 - 100;
elsif miInt >= 1000 then -- segundo numero es 0 pero el primero no
num(11)<= cero(0);
num(12)<= cero(1);
num(13)<= cero(2);
num(14)<= cero(3);
num(15)<= cero(4);
num(16)<= cero(5);
miInt2 <= miInt1;
else -- primer y segundo numero son 0 asi que no lo pintamos
num(11)<= nada(0);
num(12)<= nada(1);
num(13)<= nada(2);
num(14)<= nada(3);
num(15)<= nada(4);
num(16)<= nada(5);
miInt2 <= miInt1;
end if;
end process calcula1;
calcula2: process(miInt2, s,miInt, miInt1)
begin
if s = "100000000000000000000" or s = "011111111111111111111" then
num(18)<= (others=>'0');
num(19)<= (others=>'0');
num(20)<= (others=>'0');
num(21)<= (others=>'0');
num(22)<= (others=>'0');
num(23)<= (others=>'0');
miInt3 <= miInt2;
--El mayor numero que puede llegar es 90
elsif miInt2 >= 90 then --tercer numero un 9
num(18)<= nueve(0);
num(19)<= nueve(1);
num(20)<= nueve(2);
num(21)<= nueve(3);
num(22)<= nueve(4);
num(23)<= nueve(5);
miInt3 <= miInt2 - 90;
elsif miInt2 >= 80 then --tercer numero un 8
num(18)<= ocho(0);
num(19)<= ocho(1);
num(20)<= ocho(2);
num(21)<= ocho(3);
num(22)<= ocho(4);
num(23)<= ocho(5);
miInt3 <= miInt2 - 80;
elsif miInt2 >= 70 then --tercer numero un 7
num(18)<= siete(0);
num(19)<= siete(1);
num(20)<= siete(2);
num(21)<= siete(3);
num(22)<= siete(4);
num(23)<= siete(5);
miInt3 <= miInt2 - 70;
elsif miInt2 >= 60 then --tercer numero un 6
num(18)<= seis(0);
num(19)<= seis(1);
num(20)<= seis(2);
num(21)<= seis(3);
num(22)<= seis(4);
num(23)<= seis(5);
miInt3 <= miInt2 - 60;
elsif miInt2 >= 50 then --tercer numero un 5
num(18)<= cinco(0);
num(19)<= cinco(1);
num(20)<= cinco(2);
num(21)<= cinco(3);
num(22)<= cinco(4);
num(23)<= cinco(5);
miInt3 <= miInt2 - 50;
elsif miInt2 >= 40 then --tercer numero un 4
num(18)<= cuatro(0);
num(19)<= cuatro(1);
num(20)<= cuatro(2);
num(21)<= cuatro(3);
num(22)<= cuatro(4);
num(23)<= cuatro(5);
miInt3 <= miInt2 - 40;
elsif miInt2 >= 30 then --tercer numero un 3
num(18)<= tres(0);
num(19)<= tres(1);
num(20)<= tres(2);
num(21)<= tres(3);
num(22)<= tres(4);
num(23)<= tres(5);
miInt3 <= miInt2 - 30;
elsif miInt2 >= 20 then --tercer numero un 2
num(18)<= dos(0);
num(19)<= dos(1);
num(20)<= dos(2);
num(21)<= dos(3);
num(22)<= dos(4);
num(23)<= dos(5);
miInt3 <= miInt2 - 20;
elsif miInt2 >= 10 then --tercer numero un 1
num(18)<= uno(0);
num(19)<= uno(1);
num(20)<= uno(2);
num(21)<= uno(3);
num(22)<= uno(4);
num(23)<= uno(5);
miInt3 <= miInt2 - 10;
elsif miInt >= 1000 or miInt1 >=100 then -- tercero numero es 0 pero el primero o el segundo no
num(18)<= cero(0);
num(19)<= cero(1);
num(20)<= cero(2);
num(21)<= cero(3);
num(22)<= cero(4);
num(23)<= cero(5);
miInt3 <= miInt2;
else -- primer y tercer numero son 0 asi que no lo pintamos
num(18)<= nada(0);
num(19)<= nada(1);
num(20)<= nada(2);
num(21)<= nada(3);
num(22)<= nada(4);
num(23)<= nada(5);
miInt3 <= miInt2;
end if;
end process calcula2;
calcula3: process(miInt3,s)
begin
if s = "100000000000000000000" or s = "011111111111111111111" then
num(25)<= (others=>'0');
num(26)<= (others=>'0');
num(27)<= (others=>'0');
num(28)<= (others=>'0');
num(29)<= (others=>'0');
num(30)<= (others=>'0');
--Quedan los numeros del 0 al 9
elsif miInt3 =9 then --cuarto numero un 9
num(25)<= nueve(0);
num(26)<= nueve(1);
num(27)<= nueve(2);
num(28)<= nueve(3);
num(29)<= nueve(4);
num(30)<= nueve(5);
elsif miInt3 =8 then --cuarto numero un 8
num(25)<= ocho(0);
num(26)<= ocho(1);
num(27)<= ocho(2);
num(28)<= ocho(3);
num(29)<= ocho(4);
num(30)<= ocho(5);
elsif miInt3 =7 then --cuarto numero un 7
num(25)<= siete(0);
num(26)<= siete(1);
num(27)<= siete(2);
num(28)<= siete(3);
num(29)<= siete(4);
num(30)<= siete(5);
elsif miInt3 =6 then --cuarto numero un 6
num(25)<= seis(0);
num(26)<= seis(1);
num(27)<= seis(2);
num(28)<= seis(3);
num(29)<= seis(4);
num(30)<= seis(5);
elsif miInt3 =5 then --cuarto numero un 5
num(25)<= cinco(0);
num(26)<= cinco(1);
num(27)<= cinco(2);
num(28)<= cinco(3);
num(29)<= cinco(4);
num(30)<= cinco(5);
elsif miInt3 =4 then --cuarto numero un 4
num(25)<= cuatro(0);
num(26)<= cuatro(1);
num(27)<= cuatro(2);
num(28)<= cuatro(3);
num(29)<= cuatro(4);
num(30)<= cuatro(5);
elsif miInt3 =3 then --cuarto numero un 3
num(25)<= tres(0);
num(26)<= tres(1);
num(27)<= tres(2);
num(28)<= tres(3);
num(29)<= tres(4);
num(30)<= tres(5);
elsif miInt3 =2 then --cuarto numero un 2
num(25)<= dos(0);
num(26)<= dos(1);
num(27)<= dos(2);
num(28)<= dos(3);
num(29)<= dos(4);
num(30)<= dos(5);
elsif miInt3 =1 then --cuarto numero un 1
num(25)<= uno(0);
num(26)<= uno(1);
num(27)<= uno(2);
num(28)<= uno(3);
num(29)<= uno(4);
num(30)<= uno(5);
else -- cuarto numero un 0
num(25)<= cero(0);
num(26)<= cero(1);
num(27)<= cero(2);
num(28)<= cero(3);
num(29)<= cero(4);
num(30)<= cero(5);
end if;
end process calcula3;
calcula4: process(tuInt, s)
begin
if s = "100000000000000000000" or s = "011111111111111111111" then
num(35)<= (others=>'0');
num(36)<= (others=>'0');
num(37)<= (others=>'0');
num(38)<= (others=>'0');
num(39)<= (others=>'0');
num(40)<= (others=>'0');
tuInt1 <= tuInt;
elsif tuInt >= "1110011001" then
num(35)<= nueve(0);
num(36)<= nueve(1);
num(37)<= nueve(2);
num(38)<= nueve(3);
num(39)<= nueve(4);
num(40)<= nueve(5);
tuInt1 <= tuInt - "1110011001";
elsif tuInt >= "1100110011" then
num(35)<= ocho(0);
num(36)<= ocho(1);
num(37)<= ocho(2);
num(38)<= ocho(3);
num(39)<= ocho(4);
num(40)<= ocho(5);
tuInt1 <= tuInt - "1100110011";
elsif tuInt >= "1011001100" then
num(35)<= siete(0);
num(36)<= siete(1);
num(37)<= siete(2);
num(38)<= siete(3);
num(39)<= siete(4);
num(40)<= siete(5);
tuInt1 <= tuInt - "1011001100";
elsif tuInt >= "1001100110" then
num(35)<= seis(0);
num(36)<= seis(1);
num(37)<= seis(2);
num(38)<= seis(3);
num(39)<= seis(4);
num(40)<= seis(5);
tuInt1 <= tuInt - "1001100110";
elsif tuInt >= "1000000000" then
num(35)<= cinco(0);
num(36)<= cinco(1);
num(37)<= cinco(2);
num(38)<= cinco(3);
num(39)<= cinco(4);
num(40)<= cinco(5);
tuInt1 <= tuInt - "1000000000";
elsif tuInt >= "0110011001" then
num(35)<= cuatro(0);
num(36)<= cuatro(1);
num(37)<= cuatro(2);
num(38)<= cuatro(3);
num(39)<= cuatro(4);
num(40)<= cuatro(5);
tuInt1 <= tuInt - "0110011001";
elsif tuInt >= "0100110011" then
num(35)<= tres(0);
num(36)<= tres(1);
num(37)<= tres(2);
num(38)<= tres(3);
num(39)<= tres(4);
num(40)<= tres(5);
tuInt1 <= tuInt - "0100110011";
elsif tuInt >= "0011001100" then
num(35)<= dos(0);
num(36)<= dos(1);
num(37)<= dos(2);
num(38)<= dos(3);
num(39)<= dos(4);
num(40)<= dos(5);
tuInt1 <= tuInt - "0011001100";
elsif tuInt >= "0001100110" then
num(35)<= uno(0);
num(36)<= uno(1);
num(37)<= uno(2);
num(38)<= uno(3);
num(39)<= uno(4);
num(40)<= uno(5);
tuInt1 <= tuInt - "0001100110";
else
num(35)<= cero(0);
num(36)<= cero(1);
num(37)<= cero(2);
num(38)<= cero(3);
num(39)<= cero(4);
num(40)<= cero(5);
tuInt1 <= tuInt;
end if;
end process calcula4;
calcula5: process(tuInt, tuInt1, s)
begin
if s = "100000000000000000000" or s = "011111111111111111111" then
num(42)<= (others=>'0');
num(43)<= (others=>'0');
num(44)<= (others=>'0');
num(45)<= (others=>'0');
num(46)<= (others=>'0');
num(47)<= (others=>'0');
tuInt2 <= tuInt1;
elsif tuInt1 >= "0001011100" then
num(42)<= nueve(0);
num(43)<= nueve(1);
num(44)<= nueve(2);
num(45)<= nueve(3);
num(46)<= nueve(4);
num(47)<= nueve(5);
tuInt2 <= tuInt1 - "0001011100";
elsif tuInt1 >= "0001010001" then
num(42)<= ocho(0);
num(43)<= ocho(1);
num(44)<= ocho(2);
num(45)<= ocho(3);
num(46)<= ocho(4);
num(47)<= ocho(5);
tuInt2 <= tuInt1 - "0001010001";
elsif tuInt1 >= "0001000111" then
num(42)<= siete(0);
num(43)<= siete(1);
num(44)<= siete(2);
num(45)<= siete(3);
num(46)<= siete(4);
num(47)<= siete(5);
tuInt2 <= tuInt1 - "0001000111";
elsif tuInt1 >= "0000111101" then
num(42)<= seis(0);
num(43)<= seis(1);
num(44)<= seis(2);
num(45)<= seis(3);
num(46)<= seis(4);
num(47)<= seis(5);
tuInt2 <= tuInt1 - "0000111101";
elsif tuInt1 >= "0000110011" then
num(42)<= cinco(0);
num(43)<= cinco(1);
num(44)<= cinco(2);
num(45)<= cinco(3);
num(46)<= cinco(4);
num(47)<= cinco(5);
tuInt2 <= tuInt1 - "0000110011";
elsif tuInt1 >= "0000101000" then
num(42)<= cuatro(0);
num(43)<= cuatro(1);
num(44)<= cuatro(2);
num(45)<= cuatro(3);
num(46)<= cuatro(4);
num(47)<= cuatro(5);
tuInt2 <= tuInt1 - "0000101000";
elsif tuInt1 >= "0000011110" then
num(42)<= tres(0);
num(43)<= tres(1);
num(44)<= tres(2);
num(45)<= tres(3);
num(46)<= tres(4);
num(47)<= tres(5);
tuInt2 <= tuInt1 - "0000011110";
elsif tuInt1 >= "0000010100" then
num(42)<= dos(0);
num(43)<= dos(1);
num(44)<= dos(2);
num(45)<= dos(3);
num(46)<= dos(4);
num(47)<= dos(5);
tuInt2 <= tuInt1 - "0000010100";
elsif tuInt1 >= "0000001010" then
num(42)<= uno(0);
num(43)<= uno(1);
num(44)<= uno(2);
num(45)<= uno(3);
num(46)<= uno(4);
num(47)<= uno(5);
tuInt2 <= tuInt1 - "0000001010";
else
num(42)<= cero(0);
num(43)<= cero(1);
num(44)<= cero(2);
num(45)<= cero(3);
num(46)<= cero(4);
num(47)<= cero(5);
tuInt2 <= tuInt;
end if;
end process calcula5;
calcula6: process(tuInt2, s)
begin
if s = "100000000000000000000" or s = "011111111111111111111" then
num(49)<= (others=>'0');
num(50)<= (others=>'0');
num(51)<= (others=>'0');
num(52)<= (others=>'0');
num(53)<= (others=>'0');
num(54)<= (others=>'0');
elsif tuInt2 >= "0000001001" then
num(49)<= nueve(0);
num(50)<= nueve(1);
num(51)<= nueve(2);
num(52)<= nueve(3);
num(53)<= nueve(4);
num(54)<= nueve(5);
elsif tuInt2 >= "0000001000" then
num(49)<= ocho(0);
num(50)<= ocho(1);
num(51)<= ocho(2);
num(52)<= ocho(3);
num(53)<= ocho(4);
num(54)<= ocho(5);
elsif tuInt2 >= "0000000111" then
num(49)<= siete(0);
num(50)<= siete(1);
num(51)<= siete(2);
num(52)<= siete(3);
num(53)<= siete(4);
num(54)<= siete(5);
elsif tuInt2 >= "0000000110" then
num(49)<= seis(0);
num(50)<= seis(1);
num(51)<= seis(2);
num(52)<= seis(3);
num(53)<= seis(4);
num(54)<= seis(5);
elsif tuInt2 >= "0000000101" then
num(49)<= cinco(0);
num(50)<= cinco(1);
num(51)<= cinco(2);
num(52)<= cinco(3);
num(53)<= cinco(4);
num(54)<= cinco(5);
elsif tuInt2 >= "0000000100" then
num(49)<= cuatro(0);
num(50)<= cuatro(1);
num(51)<= cuatro(2);
num(52)<= cuatro(3);
num(53)<= cuatro(4);
num(54)<= cuatro(5);
elsif tuInt2 >= "0000000011" then
num(49)<= tres(0);
num(50)<= tres(1);
num(51)<= tres(2);
num(52)<= tres(3);
num(53)<= tres(4);
num(54)<= tres(5);
elsif tuInt2 >= "0000000010" then
num(49)<= dos(0);
num(50)<= dos(1);
num(51)<= dos(2);
num(52)<= dos(3);
num(53)<= dos(4);
num(54)<= dos(5);
elsif tuInt2 >= "0000000001" then
num(49)<= uno(0);
num(50)<= uno(1);
num(51)<= uno(2);
num(52)<= uno(3);
num(53)<= uno(4);
num(54)<= uno(5);
else
num(49)<= cero(0);
num(50)<= cero(1);
num(51)<= cero(2);
num(52)<= cero(3);
num(53)<= cero(4);
num(54)<= cero(5);
end if;
end process calcula6;
-- Las posiciones mayores o iguales que 55 las asignamos a 0
num(55 to 63)<=(others=>"0000000000");
end Behavioral; | gpl-3.0 | aa39ea3c68f3164cccd56b900ac0120d | 0.552931 | 2.704306 | false | false | false | false |
bruskajp/EE-316 | Project2/Quartus_DE2Board/TTL_Serial_Display.vhd | 1 | 3,196 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity TTL_Serial_Display is
Port (
Hex_IN : in STD_LOGIC_VECTOR (15 downto 0);
iCLK : in STD_LOGIC;
Tx : out STD_LOGIC);
end TTL_Serial_Display;
architecture Behavioral of TTL_Serial_Display is
signal DIV : unsigned(15 DOWNTO 0) := X"0000";
--Signals for StateMachine:
type stateType is range 0 to 10;
Signal Sel : integer range 0 to 11;
Signal Q : std_logic ;
signal CS : stateType;
--Signals for Splitter:
signal X1,X2,X3,X4 : std_logic_vector (3 downto 0);
signal extend : std_logic_vector (3 downto 0);
signal baud_en : std_logic;
signal HEX2_Data1 : std_logic_vector (7 downto 0);
signal HEX2_Data2 : std_logic_vector (7 downto 0);
signal HEX2_Data3 : std_logic_vector (7 downto 0);
signal HEX2_Data4 : std_logic_vector (7 downto 0);
signal LUT_Data : std_logic_vector (7 downto 0);
BEGIN
LUTConversion:
Process(Hex_IN)
begin
X1 <= Hex_IN(15 downto 12);
X2 <= Hex_IN(11 downto 8);
X3 <= Hex_IN(7 downto 4);
X4 <= Hex_IN(3 downto 0);
extend <= "0000";
end process;
Process(X1, X2, X3, X4)
begin
HEX2_Data1 <= extend & X1;
HEX2_Data2 <= extend & X2;
HEX2_Data3 <= extend & X3;
HEX2_Data4 <= extend & X4;
end process;
LUTMux:
process (Sel)
begin
if (Sel = 0) then
LUT_Data <= X"76";
elsif (Sel = 1) then
LUT_Data <= X"76";
elsif (Sel = 2) then
LUT_Data <= X"76";
elsif (Sel = 3) then
LUT_Data <= X"76";
elsif (Sel = 4) then
LUT_Data <= X"79";
elsif (Sel = 5) then
LUT_Data <= X"00";
elsif (Sel = 6) then
LUT_Data <= X"7A";
elsif (Sel = 7) then
LUT_Data <= X"FF";
elsif (Sel = 8) then
LUT_Data <= HEX2_Data1;
elsif (Sel = 9) then
LUT_Data <= HEX2_Data2;
elsif (Sel = 10) then
LUT_Data <= HEX2_Data3;
elsif (Sel = 11) then
LUT_Data <= HEX2_Data4;
end if;
end process;
StateMachine:
--code pulled from Ring_Counter.vhd
process(iCLK)
begin
if rising_edge(iCLK) then
if DIV >= X"28B1" then
DIV <= X"0000";
baud_en <= '1';
else
DIV <= DIV +1;
baud_en <= '0';
end if;
end if;
end process;
process (CS, iCLK, baud_en)
begin
if rising_edge(iCLK) and baud_en = '1' then
case CS is
when 0 =>
Q <= '0';
CS <= 1;
when 1 =>
Q <= LUT_Data(0);
CS <= 2;
when 2 =>
Q <= LUT_Data(1);
CS <= 3;
when 3 =>
Q <= LUT_Data(2);
CS <= 4;
when 4 =>
Q <= LUT_Data(3);
CS <= 5;
when 5 =>
Q <= LUT_Data(4);
CS <= 6;
when 6 =>
Q <= LUT_Data(5);
CS <= 7;
when 7 =>
Q <= LUT_Data(6);
CS <= 8;
when 8 =>
Q <= LUT_Data(7);
CS <= 9;
when 9 =>
Q <= '1';
CS <= 10;
if (Sel < 11) then
Sel <= Sel+1;
else
Sel <= 8;
end if;
when 10 =>
Q <= '0';
CS <= 1;
end case;
end if;
end process;
Tx <= Q;
end Behavioral;
| gpl-3.0 | 3cca28e579c24bd35b11077aa21ec66d | 0.506571 | 2.781549 | false | false | false | false |
bruskajp/EE-316 | Project1/sram_controller.vhd | 1 | 2,345 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sram_controller is
port
(
r_w : in std_logic;
clk : in std_logic;
addr : in std_logic_vector (17 downto 0);
r_w_en : in std_logic;
data_in : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0);
r_w_status : out std_logic;
sram_addr : out std_logic_vector (17 downto 0);
sram_i_o : inout std_logic_vector (15 downto 0);
sram_n_we : out std_logic;
sram_n_oe : out std_logic;
sram_n_ce : out std_logic;
sram_n_ub : out std_logic;
sram_n_lb : out std_logic
);
end sram_controller;
architecture behavior of sram_controller is
signal buf_data_in : std_logic_vector (15 downto 0);
signal buf_r_w : std_logic := '0';
signal buf_r_w_en : std_logic := '0';
signal flag_r_w_en : std_logic := '0';
type state_type is (s0, s1, s2);
signal state : state_type := s0;
begin
sram_n_ce <= '0';
sram_n_ub <= '0';
sram_n_lb <= '0';
process (clk)
begin
if rising_edge(clk) then
if buf_r_w = '1' then
sram_i_o <= buf_data_in;
else
sram_i_o <= "ZZZZZZZZZZZZZZZZ";
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
sram_addr <= addr;
buf_data_in <= data_in;
if (buf_r_w = '0') then
data_out <= sram_i_o;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
buf_r_w_en <= r_w_en;
if buf_r_w_en = '0' and r_w_en = '1' then
flag_r_w_en <= '1';
else
flag_r_w_en <= '0';
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
case state is
when s0 =>
r_w_status <= '0';
buf_r_w <= r_w;
sram_n_oe <= '1';
sram_n_we <= '1';
if flag_r_w_en = '1' then
state <= s1;
else
state <= s0;
end if;
when s1 =>
r_w_status <= '1';
if (buf_r_w = '0') then
sram_n_oe <= '0';
else
sram_n_we <= '0';
end if;
state <= s2;
when s2 =>
r_w_status <= '1';
if (buf_r_w = '0') then
sram_n_oe <= '0';
else
sram_n_we <= '0';
end if;
state <= s0;
end case;
end if;
end process;
end behavior; | gpl-3.0 | 390dedcf6eb15eae7430b6b8cd5f14f3 | 0.516844 | 2.460651 | false | false | false | false |
SoCdesign/EHA | Simulation/Hand_Shaking/NI_AXI_handshake_wrapper_tb.vhd | 1 | 5,050 | -- Tesbench for testing the AXI handshaking wrapper for NI
-- Copyright (C) 2016 Karl Janson
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity NI_AXI_handshake_wrapper_tb is
generic (
DATA_WIDTH : integer := 32;
NI_DEPTH : integer := 4
);
end NI_AXI_handshake_wrapper_tb;
architecture Behavioral of NI_AXI_handshake_wrapper_tb is
component AXI_handshake_wrapper is
generic (
DATA_WIDTH : integer := DATA_WIDTH;
NI_DEPTH : integer := NI_DEPTH
);
port (
reset : in std_logic;
clk : in std_logic;
--Router connection
R_RX : in std_logic_vector(DATA_WIDTH-1 downto 0);
R_TX : out std_logic_vector(DATA_WIDTH-1 downto 0);
R_DRTS : in std_logic;
R_DCTS : in std_logic;
R_RTS : out std_logic;
R_CTS : out std_logic;
-- Abstraction signals for AXI
AXI_RX_out : out std_logic_vector(DATA_WIDTH-1 downto 0);
AXI_RX_IRQ_out : out std_logic;
AXI_data_read_in : in std_logic;
AXI_TX_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
AXI_send_en : in std_logic
);
end component;
signal reset : std_logic := '0';
signal clk : std_logic := '0';
--Router connection
signal R_RX : std_logic_vector(DATA_WIDTH-1 downto 0);
signal R_TX : std_logic_vector(DATA_WIDTH-1 downto 0);
signal R_DRTS : std_logic;
signal R_DCTS : std_logic;
signal R_RTS : std_logic;
signal R_CTS : std_logic;
-- Abstraction signals for AXI
signal AXI_RX_out : std_logic_vector(DATA_WIDTH-1 downto 0);
signal AXI_RX_IRQ_out : std_logic;
signal AXI_data_read_in : std_logic;
signal AXI_TX : std_logic_vector(DATA_WIDTH-1 downto 0);
signal AXI_send_en : std_logic;
signal counter: integer := 0;
signal counter_data_read: integer := 0;
begin
AXI_Network_interface: AXI_handshake_wrapper
port map (
reset => reset,
clk => clk,
--Router connection
R_RX => R_RX,
R_TX => R_TX,
R_DRTS => R_DRTS,
R_DCTS => R_DCTS,
R_RTS => R_RTS,
R_CTS => R_CTS,
-- Abstraction signals for AXI
AXI_RX_out => AXI_RX_out,
AXI_RX_IRQ_out => AXI_RX_IRQ_out,
AXI_data_read_in => AXI_data_read_in,
AXI_TX_in => AXI_TX,
AXI_send_en => AXI_send_en
);
clk <= not clk after 10 ns;
process (clk)
begin
if clk'event and clk = '1' then
if counter = 1 then
reset <= '1';
elsif counter = 3 then
AXI_TX <= x"11111111";
elsif counter = 8 then
AXI_send_en <= '1';
elsif counter = 9 then
AXI_send_en <= '0';
elsif counter = 13 then
AXI_TX <= x"22222222";
elsif counter = 14 then
AXI_send_en <= '1';
elsif counter = 15 then
AXI_send_en <= '0';
elsif counter = 19 then
AXI_TX <= x"33333333";
elsif counter = 20 then
AXI_send_en <= '1';
elsif counter = 21 then
AXI_send_en <= '0';
elsif counter = 25 then
AXI_TX <= x"44444444";
elsif counter = 26 then
AXI_send_en <= '1';
elsif counter = 27 then
AXI_send_en <= '0';
elsif counter = 33 then
AXI_TX <= x"55555555";
elsif counter = 34 then
AXI_send_en <= '1';
elsif counter = 35 then
AXI_send_en <= '0';
-- elsif counter = 40 then
-- AXI_data_read <= '1';
-- elsif counter = 41 then
-- AXI_data_read <= '0';
-- elsif counter = 44 then
-- AXI_data_read <= '1';
-- elsif counter = 45 then
-- AXI_data_read <= '0';
-- elsif counter = 50 then
-- AXI_data_read <= '1';
-- elsif counter = 51 then
-- AXI_data_read <= '0';
-- elsif counter = 55 then
-- AXI_data_read <= '1';
-- elsif counter = 56 then
-- AXI_data_read <= '0';
-- elsif counter = 60 then
-- AXI_data_read <= '1';
-- elsif counter = 61 then
-- AXI_data_read <= '0';
end if;
counter <= counter + 1;
end if;
end process;
AXI_read_data:process(clk)
begin
if clk'event and clk = '1' then
if (AXI_data_read_in = '1') then
AXI_data_read_in <= '0';
elsif (AXI_RX_IRQ_out = '1') then
counter_data_read <= counter_data_read + 1;
if (counter_data_read = 20) then
AXI_data_read_in <= '1';
counter_data_read <= 0;
end if;
end if;
end if;
end process;
R_RX <= R_TX;
R_DRTS <= R_RTS;
R_DCTS <= R_CTS;
end Behavioral;
| gpl-3.0 | ca31ee87805e1088f951ac1ca34aaff2 | 0.491485 | 3.430707 | false | false | false | false |
TUM-LIS/faultify | hardware/testcases/viterbi/fpga_sim/xpsLibraryPath_viterbi_400_578/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/vhdl/lfsr_pkg.vhd | 17 | 18,262 | ----------------------------------------------------------------------------
---- Create Date: 14:30:08 07/28/2010 ----
---- Design Name: lfsr_pkg ----
---- Project Name: lfsr_randgen ----
---- Description: ----
---- This is the package file used in the lfsr_randgen project.The ----
---- package contain the function for XORing bits from various tap ----
---- locations depending on the generic parameter(width of lfsr ) ----
---- ----
----------------------------------------------------------------------------
---- ----
---- This file is a part of the lfsr_randgen project at ----
---- http://www.opencores.org/ ----
---- ----
---- Author(s): ----
---- Vipin Lal, [email protected] ----
---- ----
----------------------------------------------------------------------------
---- ----
---- Copyright (C) 2010 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package lfsr_pkg is
function xor_gates( random : std_logic_vector) return std_logic;
end lfsr_pkg;
--Package body starts from here.
package body lfsr_pkg is
--function for XORing from tap values.
function xor_gates( random : std_logic_vector ) return std_logic is
variable xor_out : std_logic:='0';
variable rand : std_logic_vector(random'length-1 downto 0):=random;
begin
if(rand'length = 3) then --3
xor_out := rand(2) xor rand(1);
elsif(rand'length = 2) then --2
xor_out := rand(1) xor rand(0);
elsif(rand'length = 4) then --4
xor_out := rand(3) xor rand(2);
elsif(rand'length = 5) then --5
xor_out := rand(4) xor rand(2);
elsif(rand'length = 6) then --6
xor_out := rand(5) xor rand(4);
elsif(rand'length = 7) then --7
xor_out := rand(6) xor rand(5);
elsif(rand'length = 8) then --8
xor_out := rand(7) xor rand(5) xor rand(4) xor rand(3);
elsif(rand'length = 9) then --9
xor_out := rand(8) xor rand(4);
elsif(rand'length = 10)then --10
xor_out := rand(9) xor rand(6);
elsif(rand'length =11) then --11
xor_out := rand(10) xor rand(8);
elsif(rand'length = 12) then --12
xor_out := rand(11) xor rand(5) xor rand(3) xor rand(0);
elsif(rand'length = 13) then --13
xor_out := rand(12) xor rand(3) xor rand(2) xor rand(0);
elsif(rand'length = 14) then --14
xor_out := rand(13) xor rand(4) xor rand(2) xor rand(0);
elsif(rand'length = 15) then --15
xor_out := rand(14) xor rand(13);
elsif(rand'length = 16) then --16
xor_out := rand(15) xor rand(14) xor rand(12) xor rand(3);
elsif(rand'length = 17) then --17
xor_out := rand(16) xor rand(13);
elsif(rand'length = 18) then --18
xor_out := rand(17) xor rand(10);
elsif(rand'length = 19) then --19
xor_out := rand(18) xor rand(5) xor rand(1) xor rand(0);
elsif(rand'length = 20) then --20
xor_out := rand(19) xor rand(16);
elsif(rand'length = 21) then --21
xor_out := rand(20) xor rand(18);
elsif(rand'length = 22) then --22
xor_out := rand(21) xor rand(20);
elsif(rand'length = 23) then --23
xor_out := rand(22) xor rand(17);
elsif(rand'length = 24) then --24
xor_out := rand(23) xor rand(22) xor rand(21) xor rand(16);
elsif(rand'length = 25) then --25
xor_out := rand(24) xor rand(21);
elsif(rand'length = 26) then --26
xor_out := rand(25) xor rand(5) xor rand(1) xor rand(0);
elsif(rand'length = 27) then --27
xor_out := rand(26) xor rand(4) xor rand(1) xor rand(0);
elsif(rand'length = 28) then --28
xor_out := rand(27) xor rand(24);
elsif(rand'length = 29) then --29
xor_out := rand(28) xor rand(26);
elsif(rand'length = 30) then --30
xor_out := rand(29) xor rand(5) xor rand(3) xor rand(0);
elsif(rand'length = 31) then --31
xor_out := rand(30) xor rand(27);
elsif(rand'length = 32) then --32
xor_out := rand(31) xor rand(21) xor rand(1) xor rand(0);
elsif(rand'length = 33) then --33
xor_out := rand(32) xor rand(19);
elsif(rand'length = 34) then --34
xor_out := rand(33) xor rand(26) xor rand(1) xor rand(0);
elsif(rand'length = 35) then --35
xor_out := rand(34) xor rand(32);
elsif(rand'length = 36) then --36
xor_out := rand(35) xor rand(24);
elsif(rand'length = 37) then --37
xor_out := rand(36) xor rand(4) xor rand(3) xor rand(2) xor rand(1) xor rand(0);
elsif(rand'length = 38) then --38
xor_out := rand(37) xor rand(5) xor rand(4) xor rand(0);
elsif(rand'length = 39) then --39
xor_out := rand(38) xor rand(34);
elsif(rand'length = 40) then --40
xor_out := rand(39) xor rand(37) xor rand(20) xor rand(18);
elsif(rand'length = 41) then --41
xor_out := rand(40) xor rand(37);
elsif(rand'length = 42) then --42
xor_out := rand(41) xor rand(40) xor rand(19) xor rand(18);
elsif(rand'length = 43) then --43
xor_out := rand(42) xor rand(41) xor rand(37) xor rand(36);
elsif(rand'length = 44) then --44
xor_out := rand(43) xor rand(42) xor rand(17) xor rand(16);
elsif(rand'length = 45) then --45
xor_out := rand(44) xor rand(43) xor rand(41) xor rand(40);
elsif(rand'length = 46) then --46
xor_out := rand(45) xor rand(44) xor rand(25) xor rand(24);
elsif(rand'length = 47) then --47
xor_out := rand(46) xor rand(41);
elsif(rand'length = 48) then --48
xor_out := rand(47) xor rand(46) xor rand(20) xor rand(19);
elsif(rand'length = 49) then --49
xor_out := rand(48) xor rand(39);
elsif(rand'length = 50) then --50
xor_out := rand(49) xor rand(48) xor rand(23) xor rand(22);
elsif(rand'length = 51) then --51
xor_out := rand(50) xor rand(49) xor rand(35) xor rand(34);
elsif(rand'length = 52) then --52
xor_out := rand(51) xor rand(48);
elsif(rand'length = 53) then --53
xor_out := rand(52) xor rand(51) xor rand(37) xor rand(36);
elsif(rand'length = 54) then --54
xor_out := rand(53) xor rand(52) xor rand(17) xor rand(16);
elsif(rand'length = 55) then --55
xor_out := rand(54) xor rand(30);
elsif(rand'length = 56) then --56
xor_out := rand(55) xor rand(54) xor rand(34) xor rand(33);
elsif(rand'length = 57) then --57
xor_out := rand(56) xor rand(49);
elsif(rand'length = 58) then --58
xor_out := rand(57) xor rand(38);
elsif(rand'length = 59) then --59
xor_out := rand(58) xor rand(57) xor rand(37) xor rand(36);
elsif(rand'length = 60) then --60
xor_out := rand(59) xor rand(58);
elsif(rand'length = 61) then --61
xor_out := rand(60) xor rand(59) xor rand(45) xor rand(44);
elsif(rand'length = 62) then --62
xor_out := rand(61) xor rand(60) xor rand(5) xor rand(4);
elsif(rand'length = 63) then --63
xor_out := rand(62) xor rand(61);
elsif(rand'length = 64) then --64
xor_out := rand(63) xor rand(62) xor rand(60) xor rand(59);
elsif(rand'length = 65) then --65
xor_out := rand(64) xor rand(46);
elsif(rand'length = 66) then --66
xor_out := rand(65) xor rand(64) xor rand(56) xor rand(55);
elsif(rand'length = 67) then --67
xor_out := rand(66) xor rand(65) xor rand(57) xor rand(56);
elsif(rand'length = 68) then --68
xor_out := rand(67) xor rand(58);
elsif(rand'length = 69) then --69
xor_out := rand(68) xor rand(66) xor rand(41) xor rand(39);
elsif(rand'length = 70) then --70
xor_out := rand(69) xor rand(68) xor rand(54) xor rand(53);
elsif(rand'length = 71) then --71
xor_out := rand(70) xor rand(64);
elsif(rand'length = 72) then --72
xor_out := rand(71) xor rand(65) xor rand(24) xor rand(18);
elsif(rand'length = 73) then --73
xor_out := rand(72) xor rand(47);
elsif(rand'length = 74) then --74
xor_out := rand(73) xor rand(72) xor rand(58) xor rand(57);
elsif(rand'length = 75) then --75
xor_out := rand(74) xor rand(73) xor rand(64) xor rand(63);
elsif(rand'length = 76) then --76
xor_out := rand(75) xor rand(74) xor rand(40) xor rand(39);
elsif(rand'length = 77) then --77
xor_out := rand(76) xor rand(75) xor rand(46) xor rand(45);
elsif(rand'length = 78) then --78
xor_out := rand(77) xor rand(76) xor rand(58) xor rand(57);
elsif(rand'length = 79) then --79
xor_out := rand(78) xor rand(69);
elsif(rand'length = 80) then --80
xor_out := rand(79) xor rand(78) xor rand(42) xor rand(41);
elsif(rand'length = 81) then --81
xor_out := rand(80) xor rand(76);
elsif(rand'length = 82) then --82
xor_out := rand(81) xor rand(78) xor rand(46) xor rand(43);
elsif(rand'length = 83) then --83
xor_out := rand(82) xor rand(81) xor rand(37) xor rand(36);
elsif(rand'length = 84) then --84
xor_out := rand(83) xor rand(70);
elsif(rand'length = 85) then --85
xor_out := rand(84) xor rand(83) xor rand(57) xor rand(56);
elsif(rand'length = 86) then --86
xor_out := rand(85) xor rand(84) xor rand(73) xor rand(72);
elsif(rand'length = 87) then --87
xor_out := rand(86) xor rand(73);
elsif(rand'length = 88) then --88
xor_out := rand(87) xor rand(86) xor rand(16) xor rand(15);
elsif(rand'length = 89) then --89
xor_out := rand(88) xor rand(50);
elsif(rand'length = 90) then --90
xor_out := rand(89) xor rand(88) xor rand(71) xor rand(70);
elsif(rand'length = 91) then --91
xor_out := rand(90) xor rand(89) xor rand(7) xor rand(6);
elsif(rand'length = 92) then --92
xor_out := rand(91) xor rand(90) xor rand(79) xor rand(78);
elsif(rand'length = 93) then --93
xor_out := rand(92) xor rand(90);
elsif(rand'length = 94) then --94
xor_out := rand(93) xor rand(72);
elsif(rand'length = 95) then --95
xor_out := rand(94) xor rand(83);
elsif(rand'length = 96) then --96
xor_out := rand(95) xor rand(93) xor rand(48) xor rand(46);
elsif(rand'length = 97) then --97
xor_out := rand(96) xor rand(90);
elsif(rand'length = 98) then --98
xor_out := rand(97) xor rand(86);
elsif(rand'length = 99) then --99
xor_out := rand(98) xor rand(96) xor rand(53) xor rand(51);
elsif(rand'length = 100) then --100
xor_out := rand(99) xor rand(62);
elsif(rand'length = 101) then --101
xor_out := rand(100) xor rand(99) xor rand(94) xor rand(93);
elsif(rand'length = 102) then --102
xor_out := rand(101) xor rand(100) xor rand(35) xor rand(34);
elsif(rand'length = 103) then --103
xor_out := rand(102) xor rand(93);
elsif(rand'length = 104) then --104
xor_out := rand(103) xor rand(102) xor rand(93) xor rand(92);
elsif(rand'length = 105) then --105
xor_out := rand(104) xor rand(88);
elsif(rand'length = 106) then --106
xor_out := rand(105) xor rand(90);
elsif(rand'length = 107) then --107
xor_out := rand(106) xor rand(104) xor rand(43) xor rand(41);
elsif(rand'length = 108) then --108
xor_out := rand(107) xor rand(76);
elsif(rand'length = 109) then --109
xor_out := rand(108) xor rand(107) xor rand(102) xor rand(101);
elsif(rand'length = 110)then --110
xor_out := rand(109) xor rand(108) xor rand(97) xor rand(96);
elsif(rand'length = 111) then --111
xor_out := rand(110) xor rand(100);
elsif(rand'length = 112) then --112
xor_out := rand(111) xor rand(109) xor rand(68) xor rand(66);
elsif(rand'length = 113) then --113
xor_out := rand(112) xor rand(103);
elsif(rand'length = 114) then --114
xor_out := rand(113) xor rand(112) xor rand(32) xor rand(31);
elsif(rand'length = 115) then --115
xor_out := rand(114) xor rand(113) xor rand(100) xor rand(99);
elsif(rand'length = 116) then --116
xor_out := rand(115) xor rand(114) xor rand(45) xor rand(44);
elsif(rand'length = 117) then --117
xor_out := rand(116) xor rand(114) xor rand(98) xor rand(96);
elsif(rand'length = 118) then --118
xor_out := rand(117) xor rand(84);
elsif(rand'length = 119) then --119
xor_out := rand(118) xor rand(110);
elsif(rand'length = 120) then --120
xor_out := rand(119) xor rand(112) xor rand(8) xor rand(1);
elsif(rand'length = 121) then --121
xor_out := rand(120) xor rand(102);
elsif(rand'length = 122) then --122
xor_out := rand(121) xor rand(120) xor rand(62) xor rand(61);
elsif(rand'length = 123) then --123
xor_out := rand(122) xor rand(120);
elsif(rand'length = 124) then --124
xor_out := rand(123) xor rand(86);
elsif(rand'length = 125) then --125
xor_out := rand(124) xor rand(123) xor rand(17) xor rand(16);
elsif(rand'length = 126) then --126
xor_out := rand(125) xor rand(124) xor rand(89) xor rand(88);
elsif(rand'length = 127) then --127
xor_out := rand(126) xor rand(125);
elsif(rand'length = 128) then --128
xor_out := rand(127) xor rand(125) xor rand(100) xor rand(98);
elsif(rand'length = 129) then --129
xor_out := rand(128) xor rand(123);
elsif(rand'length = 130) then --130
xor_out := rand(129) xor rand(126);
elsif(rand'length = 131) then --131
xor_out := rand(130) xor rand(129) xor rand(83) xor rand(82);
elsif(rand'length = 132) then --132
xor_out := rand(131) xor rand(102);
elsif(rand'length = 133) then --133
xor_out := rand(132) xor rand(131) xor rand(81) xor rand(80);
elsif(rand'length = 134) then --134
xor_out := rand(133) xor rand(76);
elsif(rand'length = 135) then --135
xor_out := rand(134) xor rand(123);
elsif(rand'length = 136) then --136
xor_out := rand(135) xor rand(134) xor rand(10) xor rand(9);
elsif(rand'length = 137) then --137
xor_out := rand(136) xor rand(115);
elsif(rand'length = 138) then --138
xor_out := rand(137) xor rand(136) xor rand(130) xor rand(129);
elsif(rand'length = 139) then --139
xor_out := rand(138) xor rand(135) xor rand(133) xor rand(130);
elsif(rand'length = 140) then --140
xor_out := rand(139) xor rand(110);
elsif(rand'length = 141) then --141
xor_out := rand(140) xor rand(139) xor rand(109) xor rand(108);
elsif(rand'length = 142) then --142
xor_out := rand(141) xor rand(120);
elsif(rand'length = 143) then --143
xor_out := rand(142) xor rand(141) xor rand(122) xor rand(121);
elsif(rand'length = 144) then --144
xor_out := rand(143) xor rand(142) xor rand(74) xor rand(73);
elsif(rand'length = 145) then --145
xor_out := rand(144) xor rand(92);
elsif(rand'length = 146) then --146
xor_out := rand(145) xor rand(144) xor rand(86) xor rand(85);
elsif(rand'length = 147) then --147
xor_out := rand(146) xor rand(145) xor rand(109) xor rand(108);
elsif(rand'length = 148) then --148
xor_out := rand(147) xor rand(120);
elsif(rand'length = 149) then --149
xor_out := rand(148) xor rand(147) xor rand(39) xor rand(38);
elsif(rand'length = 150) then --150
xor_out := rand(149) xor rand(96);
elsif(rand'length = 151) then --151
xor_out := rand(150) xor rand(147);
elsif(rand'length = 152) then --152
xor_out := rand(151) xor rand(150) xor rand(86) xor rand(85);
elsif(rand'length = 153) then --153
xor_out := rand(152) xor rand(151);
elsif(rand'length = 154) then --154
xor_out := rand(153) xor rand(151) xor rand(26) xor rand(24);
elsif(rand'length = 155) then --155
xor_out := rand(154) xor rand(153) xor rand(123) xor rand(122);
elsif(rand'length = 156) then --156
xor_out := rand(155) xor rand(154) xor rand(40) xor rand(39);
elsif(rand'length = 157) then --157
xor_out := rand(156) xor rand(155) xor rand(130) xor rand(129);
elsif(rand'length = 158) then --158
xor_out := rand(157) xor rand(156) xor rand(131) xor rand(130);
elsif(rand'length = 159) then --159
xor_out := rand(158) xor rand(127);
elsif(rand'length = 160) then --160
xor_out := rand(159) xor rand(158) xor rand(141) xor rand(140);
elsif(rand'length = 161) then --161
xor_out := rand(160) xor rand(142);
elsif(rand'length = 162) then --162
xor_out := rand(161) xor rand(160) xor rand(74) xor rand(73);
elsif(rand'length = 163) then --163
xor_out := rand(162) xor rand(161) xor rand(103) xor rand(102);
elsif(rand'length = 164) then --164
xor_out := rand(163) xor rand(162) xor rand(150) xor rand(149);
elsif(rand'length = 165) then --165
xor_out := rand(164) xor rand(163) xor rand(134) xor rand(133);
elsif(rand'length = 166) then --166
xor_out := rand(165) xor rand(164) xor rand(127) xor rand(126);
elsif(rand'length = 167) then --167
xor_out := rand(166) xor rand(160);
elsif(rand'length = 168) then --168
xor_out := rand(167) xor rand(165) xor rand(152) xor rand(150);
end if;
return xor_out;
end xor_gates;
--END function for XORing using tap values.
end lfsr_pkg;
--End of the package.
| gpl-2.0 | 2cbd20683823e45ea582f54386eee788 | 0.588216 | 2.992299 | false | false | false | false |
lnls-dig/dsp-cores | hdl/testbench/cic/wb_bpm_swap/bpm_swap/bpm_swap.vhd | 2 | 5,761 | ------------------------------------------------------------------------------
-- Title : BPM RF channels swapping controller
------------------------------------------------------------------------------
-- Author : Jose Alvim Berkenbrock
-- Company : CNPEM LNLS-DIG
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Top level module for BPM RF channels swapping control. User
-- can dynamically set swapping/de-swapping mode, frequency and
-- de-swapping delay.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bpm_swap is
generic(
g_delay_vec_width : natural := 8;
g_swap_div_freq_vec_width : natural := 16;
g_ch_width : natural := 16
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Input data from ADCs
cha_i : in std_logic_vector(g_ch_width-1 downto 0);
chb_i : in std_logic_vector(g_ch_width-1 downto 0);
chc_i : in std_logic_vector(g_ch_width-1 downto 0);
chd_i : in std_logic_vector(g_ch_width-1 downto 0);
ch_valid_i : in std_logic;
-- Output data to BPM DSP chain
cha_o : out std_logic_vector(g_ch_width-1 downto 0);
chb_o : out std_logic_vector(g_ch_width-1 downto 0);
chc_o : out std_logic_vector(g_ch_width-1 downto 0);
chd_o : out std_logic_vector(g_ch_width-1 downto 0);
ch_tag_o : out std_logic_vector(0 downto 0);
ch_valid_o : out std_logic;
-- RFFE swap clock (or switchwing clock)
rffe_swclk_o : out std_logic;
-- Synchronization trigger for swap clock generation
sync_trig_i : in std_logic;
-- Swap mode setting
swap_mode_i : in std_logic_vector(1 downto 0);
-- Swap frequency settings
swap_div_f_i : in std_logic_vector(g_swap_div_freq_vec_width-1 downto 0);
-- De-swap delay setting
deswap_delay_i : in std_logic_vector(g_delay_vec_width-1 downto 0)
);
end bpm_swap;
architecture rtl of bpm_swap is
signal swap : std_logic;
signal deswap : std_logic;
signal deswap_ac : std_logic;
signal deswap_bd : std_logic;
-------------------------------------------------------
-- components declaration
-------------------------------------------------------
component swap_freqgen
generic(
g_delay_vec_width : natural := 8;
g_swap_div_freq_vec_width : natural := 16
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
en_i : in std_logic := '1';
sync_trig_i : in std_logic;
swap_mode_i : in std_logic_vector(1 downto 0);
swap_div_f_i : in std_logic_vector(g_swap_div_freq_vec_width-1 downto 0);
swap_div_f_cnt_en_i : in std_logic := '1';
deswap_delay_i : in std_logic_vector(g_delay_vec_width-1 downto 0);
swap_o : out std_logic;
deswap_o : out std_logic
);
end component;
component deswap_channels
generic(
g_ch_width : natural := 16
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
deswap_i : in std_logic;
ch1_i : in std_logic_vector(g_ch_width-1 downto 0);
ch2_i : in std_logic_vector(g_ch_width-1 downto 0);
ch_valid_i : in std_logic;
ch1_o : out std_logic_vector(g_ch_width-1 downto 0);
ch2_o : out std_logic_vector(g_ch_width-1 downto 0);
deswap_o : out std_logic;
ch_valid_o : out std_logic
);
end component;
begin
-------------------------------------------------------
-- components instantiation
-------------------------------------------------------
cmp_swap_freqgen : swap_freqgen
generic map (
g_delay_vec_width => g_delay_vec_width,
g_swap_div_freq_vec_width => g_swap_div_freq_vec_width
)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
sync_trig_i => sync_trig_i,
swap_mode_i => swap_mode_i,
swap_div_f_i => swap_div_f_i,
deswap_delay_i => deswap_delay_i,
swap_o => swap,
deswap_o => deswap
);
cmp_deswap_ac_channels : deswap_channels
generic map (
g_ch_width => g_ch_width
)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
deswap_i => deswap,
ch1_i => cha_i,
ch2_i => chb_i,
ch_valid_i => ch_valid_i,
ch1_o => cha_o,
ch2_o => chb_o,
deswap_o => deswap_ac,
ch_valid_o => ch_valid_o
);
ch_tag_o(0) <= deswap_ac;
cmp_deswap_bd_channels : deswap_channels
generic map (
g_ch_width => g_ch_width
)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
deswap_i => deswap,
ch1_i => chc_i,
ch2_i => chd_i,
ch_valid_i => ch_valid_i,
ch1_o => chc_o,
ch2_o => chd_o,
-- Only one deswap is necessary
deswap_o => open,
-- Only one ch_valid is necessary
ch_valid_o => open
);
-------------------------------------------------------
-- RTL logic
-------------------------------------------------------
-- RFFE v2 expects switching clock signal to be
-- 'high' when in 'direct path' and 'low' when in 'inverted path'
rffe_swclk_o <= not swap;
end;
| lgpl-3.0 | 21b93ffb882f83664ad911c084bc84f1 | 0.476827 | 3.429167 | false | false | false | false |
TUM-LIS/faultify | hardware/testcases/viterbi/fpga_sim/xpsLibraryPath_viterbi_400_578/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/vhdl/faultify_top.vhd | 3 | 20,597 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_top is
generic (
numInj : integer := 56;
numIn : integer := 10;
numOut : integer := 10);
port (
aclk : in std_logic; -- interface clock
arst_n : in std_logic; -- interface reset
clk : in std_logic; -- simulation clock (slow)
clk_x32 : in std_logic; -- prng clock (fast)
-- Write channel
awvalid : in std_logic;
awaddr : in std_logic_vector(31 downto 0);
wvalid : in std_logic;
wdata : in std_logic_vector(31 downto 0);
-- Read channel
arvalid : in std_logic;
araddr : in std_logic_vector(31 downto 0);
rvalid : out std_logic;
rdata : out std_logic_vector(31 downto 0);
-- AXI IFACE
resultvector_o_p : out std_logic_vector(numOut-1 downto 0);
resultvector_f_p : out std_logic_vector(numOut-1 downto 0);
testvector : in std_logic_vector(numIn-1 downto 0);
s_axis_aresetn : in std_logic
);
attribute syn_hier : string;
attribute syn_hier of faultify_top : entity is "hard";
end faultify_top;
architecture behav of faultify_top is
component flag_cdc
port (
clkA : in std_logic;
clkB : in std_logic;
FlagIn_clkA : in std_logic;
FlagOut_clkB : out std_logic;
rst_n : in std_logic);
end component;
component faultify_simulator
generic (
numInj : integer;
numIn : integer;
numOut : integer);
port (
clk : in std_logic;
clk_m : in std_logic;
circ_ce : in std_logic;
circ_rst : in std_logic;
test : out std_logic_vector(31 downto 0);
testvector : in std_logic_vector(numIn-1 downto 0);
resultvector_o : out std_logic_vector(numOut-1 downto 0);
resultvector_f : out std_logic_vector(numOut-1 downto 0);
seed_in_en : in std_logic;
seed_in : in std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
shift_en : in std_logic;
rst_n : in std_logic);
end component;
component lfsr
generic (
width : integer;
seed : integer);
port (
clk : in std_logic;
rand_out : out std_logic_vector(width-1 downto 0));
end component;
type vector is array (0 to numOut-1) of std_logic_vector(31 downto 0);
signal errorSum : vector;
signal errorSumReg : vector;
signal errorSumReg_cdc_0 : vector;
signal errorSumReg_cdc_1 : vector;
signal errorVec : std_logic_vector(numOut-1 downto 0);
signal cnt : integer;
signal cnt_cdc_0 : integer;
signal cnt_cdc_1 : integer;
-- Asymmetric ram larger than 36 bit not supported in synplify I-2013
--type seed_ram_matr is array (0 to numInj-1) of std_logic_vector(63 downto 0);
--signal seed_ram : seed_ram_matr;
-- workaround 2 32-bit rams
type seed_ram_matr is array (0 to numInj-1) of std_logic_vector(31 downto 0);
signal seed_ram_low : seed_ram_matr;
signal seed_ram_high : seed_ram_matr;
--subtype seed_ram_matr_word_t is std_logic_vector(63 downto 0);
--type seed_ram_matr_memory_t is array (0 to numInj-1) of seed_ram_matr_word_t;
--signal seed_ram : seed_ram_matr_memory_t;
type prob_ram_matr is array (0 to numInj-1) of std_logic_vector(31 downto 0);
signal prob_ram : prob_ram_matr;
type reg_type is record
control : std_logic_vector(31 downto 0);
status : std_logic_vector(31 downto 0);
pe_location : std_logic_vector(31 downto 0);
pe_seed_low : std_logic_vector(31 downto 0);
pe_seed_high : std_logic_vector(31 downto 0);
pe_probability : std_logic_vector(31 downto 0);
output : std_logic_vector(31 downto 0);
ovalid : std_logic;
simtime : std_logic_vector(31 downto 0);
sel_soe : std_logic_vector(31 downto 0);
adr_soe : std_logic_vector(31 downto 0);
awaddr : std_logic_vector(31 downto 0);
test : std_logic_vector(31 downto 0);
circreset : std_logic_vector(31 downto 0);
cnt_tmp : std_logic_vector(31 downto 0);
sumoferrors : vector;
end record;
signal busy_loading : std_logic;
signal busy_simulating : std_logic;
signal busy_loading_reg : std_logic_vector(1 downto 0);
signal busy_simulating_reg : std_logic_vector(1 downto 0);
signal sim_done : std_logic;
signal r : reg_type;
type load_fsm_states is (IDLE, LOADSEED, LOADPROB);
signal l_state : load_fsm_states;
type sim_states is (IDLE, DELAY_Z, DELAY, SIMULATION, DELAY2, DELAY3, DELAY4, FREE_SIMULATION);
signal s_state : sim_states;
--signal testvector : std_logic_vector(numIn-1 downto 0);
signal resultvector_o : std_logic_vector(numOut-1 downto 0);
signal resultvector_f : std_logic_vector(numOut-1 downto 0);
signal seed_in_en : std_logic;
signal seed_in : std_logic;
signal prob_in_en : std_logic;
signal prob_in : std_logic;
signal shift_en : std_logic;
signal shift_en_l : std_logic;
signal shift_en_s : std_logic;
signal load_seed_prob : std_logic;
signal start_simulation : std_logic;
signal start_free_simulation : std_logic;
signal stop_simulation : std_logic;
signal circ_ce, circ_rst, circ_rst_sim : std_logic;
signal tvec : std_logic_vector(127 downto 0);
signal test : std_logic_vector(31 downto 0);
signal rst_cdc, rst_cdc_n : std_logic;
begin -- behav
resultvector_f_p <= resultvector_f;
resultvector_o_p <= resultvector_o;
-----------------------------------------------------------------------------
-- PRNG shifting
-----------------------------------------------------------------------------
shift_en <= shift_en_l or shift_en_s;
-----------------------------------------------------------------------------
-- Testvector
-----------------------------------------------------------------------------
--testvector <= (others => '0');
--lfsr_1 : lfsr
-- generic map (
-- width => 128,
-- seed => 3498327)
-- port map (
-- clk => clk,
-- rand_out => tvec);
--testvector <= tvec(numIn-1 downto 0);
-----------------------------------------------------------------------------
-- Simulator
-----------------------------------------------------------------------------
--active low
circ_rst <= not(not(s_axis_aresetn) or circ_rst_sim);
faultify_simulator_1 : faultify_simulator
generic map (
numInj => numInj,
numIn => numIn,
numOut => numOut)
port map (
clk => clk_x32,
clk_m => clk,
circ_ce => circ_ce,
circ_rst => circ_rst,
test => test,
testvector => testvector,
resultvector_o => resultvector_o,
resultvector_f => resultvector_f,
seed_in_en => seed_in_en,
seed_in => seed_in,
prob_in_en => prob_in_en,
prob_in => prob_in,
shift_en => shift_en,
rst_n => arst_n);
-------------------------------------------------------------------------------
-- One Process Flow
-------------------------------------------------------------------------------
register_process : process (aclk, arst_n)
variable write_addr : std_logic_vector(31 downto 0);
begin -- process register_process
if arst_n = '0' then -- asynchronous reset (active low)
r.control <= (others => '0');
r.status <= (others => '0');
r.pe_probability <= (others => '0');
r.pe_seed_high <= (others => '0');
r.pe_seed_low <= (others => '0');
r.pe_location <= (others => '0');
r.ovalid <= '0';
r.simtime <= (others => '0');
r.sel_soe <= (others => '0');
r.adr_soe <= (others => '0');
r.sumoferrors <= (others => (others => '0'));
r.output <= (others => '0');
elsif aclk'event and aclk = '1' then -- rising clock edge
r.control <= (others => '0');
if awvalid = '1' then
r.awaddr <= awaddr;
write_addr := awaddr;
end if;
if wvalid = '1' then
if write_addr = x"00000000" then
r.control <= wdata;
elsif write_addr = x"00000001" then
r.pe_location <= wdata;
elsif write_addr = x"00000002" then
r.pe_seed_low <= wdata;
elsif write_addr = x"00000003" then
r.pe_seed_high <= wdata;
elsif write_addr = x"00000004" then
r.pe_probability <= wdata;
elsif write_addr = x"00000005" then
r.cnt_tmp <= std_logic_vector(to_unsigned(cnt_cdc_1, 32));
r.adr_soe <= wdata;
elsif write_addr = x"00000007" then
r.simtime <= wdata;
elsif write_addr = x"00000009" then
r.circreset <= wdata;
end if;
end if;
if arvalid = '1' then
if araddr = x"0000000F" then
r.output <= r.status;
elsif araddr = x"00000001" then
r.output <= r.pe_location;
elsif araddr = x"00000002" then
r.output <= r.pe_seed_low;
elsif araddr = x"00000003" then
r.output <= r.pe_seed_high;
elsif araddr = x"00000004" then
r.output <= r.pe_probability;
elsif araddr = x"00000006" then
r.output <= r.sel_soe;
elsif araddr = x"00000008" then
r.output <= r.test;
elsif araddr = x"0000000A" then
r.output <= r.cnt_tmp;
end if;
r.ovalid <= '1';
else
r.ovalid <= '0';
end if;
if busy_loading_reg(1) = '1' then
r.status(0) <= '1';
else
r.status(0) <= '0';
end if;
if busy_simulating_reg(1) = '1' then
r.status(1) <= '1';
else
r.status(1) <= '0';
end if;
r.sel_soe <= r.sumoferrors(to_integer(unsigned(r.adr_soe)));
rdata <= r.output;
rvalid <= r.ovalid;
r.sumoferrors <= errorSumReg_cdc_1;
r.test <= errorSum(0);
end if;
end process register_process;
-----------------------------------------------------------------------------
-- simple clock domain crossing
-----------------------------------------------------------------------------
process (aclk, arst_n)
begin -- process
if arst_n = '0' then -- asynchronous reset (active low)
busy_simulating_reg <= (others => '0');
busy_loading_reg <= (others => '0');
elsif aclk'event and aclk = '1' then -- rising clock edge
busy_simulating_reg(0) <= busy_simulating;
busy_loading_reg(0) <= busy_loading;
busy_simulating_reg(1) <= busy_simulating_reg(0);
busy_loading_reg(1) <= busy_loading_reg(0);
cnt_cdc_0 <= cnt;
cnt_cdc_1 <= cnt_cdc_0;
errorSumReg_cdc_0 <= errorSumReg;
errorSumReg_cdc_1 <= errorSumReg_cdc_0;
end if;
end process;
-------------------------------------------------------------------------------
-- Store seeed/prob
-------------------------------------------------------------------------------
store_seed : process (aclk, arst_n)
begin -- process store_seed
if arst_n = '0' then -- asynchronous reset (active low)
elsif aclk'event and aclk = '1' then -- rising clock edge
if r.control(0) = '1' then
-- Synplify bug workaround
--seed_ram(to_integer(unsigned(r.pe_location))) <= r.pe_seed_high & r.pe_seed_low;
seed_ram_low(to_integer(unsigned(r.pe_location))) <= r.pe_seed_low;
seed_ram_high(to_integer(unsigned(r.pe_location))) <= r.pe_seed_high;
prob_ram(to_integer(unsigned(r.pe_location))) <= r.pe_probability;
end if;
end if;
end process store_seed;
-----------------------------------------------------------------------------
-- Seed/prob loading FSM
-----------------------------------------------------------------------------
--flag_cdc_1 : flag_cdc
-- port map (
-- clkA => aclk,
-- clkB => clk_x32,
-- FlagIn_clkA => r.control(1),
-- FlagOut_clkB => load_seed_prob,
-- rst_n => arst_n);
load_seed_prob <= r.control(1);
seed_prob_loading : process (clk_x32, arst_n)
variable cnt_seed : integer range 0 to 64;
variable cnt_inj : integer range 0 to numInj;
variable cnt_prob : integer range 0 to 32;
begin -- process seed_prob_loading
if arst_n = '0' then -- asynchronous reset (active low)
l_state <= IDLE;
seed_in <= '0';
seed_in_en <= '0';
prob_in <= '0';
prob_in_en <= '0';
shift_en_l <= '0';
busy_loading <= '0';
elsif clk_x32'event and clk_x32 = '1' then -- rising clock edge
case l_state is
when IDLE =>
cnt_seed := 0;
cnt_inj := 0;
cnt_prob := 0;
busy_loading <= '0';
seed_in_en <= '0';
prob_in_en <= '0';
shift_en_l <= '0';
if load_seed_prob = '1' then
busy_loading <= '1';
l_state <= LOADSEED;
end if;
when LOADSEED =>
if cnt_seed < 64 then
shift_en_l <= '1';
seed_in_en <= '1';
-- not working in synplify I-2013
--seed_in <= seed_ram(cnt_inj)(cnt_seed);
--
if cnt_seed < 32 then
seed_in <= seed_ram_low(cnt_inj)(cnt_seed);
else
seed_in <= seed_ram_high(cnt_inj)(cnt_seed-32);
end if;
cnt_seed := cnt_seed + 1;
end if;
if cnt_seed = 64 then
cnt_seed := 0;
cnt_inj := cnt_inj + 1;
end if;
if cnt_inj = numInj then
l_state <= LOADPROB;
--seed_in_en <= '0';
cnt_inj := 0;
end if;
when LOADPROB =>
seed_in_en <= '0';
if cnt_prob < 32 then
prob_in_en <= '1';
prob_in <= prob_ram(cnt_inj)(cnt_prob);
cnt_prob := cnt_prob + 1;
end if;
if cnt_prob = 32 then
cnt_prob := 0;
cnt_inj := cnt_inj + 1;
end if;
if cnt_inj = numInj then
l_state <= IDLE;
cnt_inj := 0;
--prob_in_en <= '0';
end if;
end case;
end if;
end process seed_prob_loading;
-----------------------------------------------------------------------------
-- Simulation FSM
-----------------------------------------------------------------------------
flag_cdc_2 : flag_cdc
port map (
clkA => aclk,
clkB => clk,
FlagIn_clkA => r.control(2),
FlagOut_clkB => start_simulation,
rst_n => arst_n);
flag_cdc_3 : flag_cdc
port map (
clkA => aclk,
clkB => clk,
FlagIn_clkA => r.control(3),
FlagOut_clkB => start_free_simulation,
rst_n => arst_n);
flag_cdc_4 : flag_cdc
port map (
clkA => aclk,
clkB => clk,
FlagIn_clkA => r.control(4),
FlagOut_clkB => stop_simulation,
rst_n => arst_n);
rst_cdc_5 : flag_cdc
port map (
clkA => aclk,
clkB => clk,
FlagIn_clkA => not arst_n,
FlagOut_clkB => rst_cdc,
rst_n => '1');
rst_cdc_n <= not rst_cdc;
process (clk, rst_cdc_n)
variable simtime : integer;
variable cnt_delay : integer range 0 to 9;
begin -- process
if clk'event and clk = '1' then -- rising clock edge
if rst_cdc_n = '0' then -- asynchronous reset (active low)
s_state <= IDLE;
errorVec <= (others => '0');
errorSum <= (others => (others => '0'));
circ_ce <= '0';
circ_rst_sim <= '1';
shift_en_s <= '0';
busy_simulating <= '0';
sim_done <= '0';
errorSumReg <= (others => (others => '0'));
else
case s_state is
when IDLE =>
sim_done <= '0';
circ_ce <= '0';
circ_rst_sim <= '1';
shift_en_s <= '0';
errorVec <= (others => '0');
--errorSum <= errorSum;
errorSum <= (others => (others => '0'));
--cnt <= 0;
busy_simulating <= '0';
cnt_delay := 0;
if start_simulation = '1' then
cnt <= 0;
busy_simulating <= '1';
errorSum <= (others => (others => '0'));
errorSumReg <= (others => (others => '0'));
simtime := to_integer(unsigned(r.simtime));
s_state <= DELAY_Z;
circ_ce <= '1';
circ_rst_sim <= '0';
shift_en_s <= '1';
end if;
if start_free_simulation = '1' then
cnt <= 0;
busy_simulating <= '1';
errorSum <= (others => (others => '0'));
errorSumReg <= (others => (others => '0'));
s_state <= FREE_SIMULATION;
circ_ce <= '1';
circ_rst_sim <= '0';
shift_en_s <= '1';
end if;
when DELAY_z =>
cnt_delay := cnt_delay + 1;
if cnt_delay = 9 then
s_state <= DELAY;
end if;
when DELAY =>
s_state <= SIMULATION;
errorVec <= (others => '0');
errorSum <= (others => (others => '0'));
when SIMULATION =>
circ_rst_sim <= '0';
shift_en_s <= '1';
-- collect errors
if (resultVector_o(1) = '1') then
errorVec <= resultvector_o xor resultvector_f;
else
errorVec <= (others => '0');
end if;
for i in 0 to (numOut-1) loop
if (errorVec(i) = '1') then
errorSum(i) <= std_logic_vector(unsigned(errorSum(i)) + 1);
end if;
end loop;
--
errorSumReg <= errorSum;
if cnt = simtime-1 then
s_state <= DELAY2;
circ_ce <= '0';
circ_rst_sim <= '1';
shift_en_s <= '0';
end if;
cnt <= cnt +1;
when DELAY2 =>
if (resultVector_o(1) = '1') then
errorVec <= resultvector_o xor resultvector_f;
else
errorVec <= (others => '0');
end if;
for i in 0 to (numOut-1) loop
if (errorVec(i) = '1') then
errorSum(i) <= std_logic_vector(unsigned(errorSum(i)) + 1);
end if;
end loop;
s_state <= DELAY3;
when DELAY3 =>
s_state <= DELAY4;
errorSumReg <= errorSum;
errorSum <= (others => (others => '0'));
when DELAY4 =>
s_state <= IDLE;
sim_done <= '1';
when FREE_SIMULATION =>
circ_rst_sim <= '0';
shift_en_s <= '1';
-- collect errors
if (resultVector_o(1) = '1') then
errorVec <= resultvector_o xor resultvector_f;
else
errorVec <= (others => '0');
end if;
for i in 0 to (numOut-1) loop
if (errorVec(i) = '1') then
errorSum(i) <= std_logic_vector(unsigned(errorSum(i)) + 1);
end if;
end loop;
--
errorSumReg <= errorSum;
if stop_simulation = '1' then
s_state <= IDLE;
sim_done <= '1';
circ_ce <= '0';
circ_rst_sim <= '1';
shift_en_s <= '0';
end if;
cnt <= cnt +1;
when others =>
s_state <= IDLE;
end case;
end if;
end if;
end process;
end behav;
| gpl-2.0 | 504218c75d9791f399dd3c8a868aac8e | 0.461524 | 3.843441 | false | false | false | false |
TanND/Electronic | VHDL/D11_C2.vhd | 1 | 311 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D11_C2 is
port(
clk:in std_logic;
s0,s1 : out STD_LOGIC
);
end D11_C2;
architecture D11_C2 of D11_C2 is
begin
process(clk)
begin
if(clk='1') then s0<='1';s1<='1';
else s0<='0';s1<='0';
end if;
end process;
end D11_C2;
-- clk=0.5hz | apache-2.0 | 4d1ff8b931633f1e2999c6cb9ce6e4c4 | 0.604502 | 2.221429 | false | false | false | false |
lnls-dig/dsp-cores | hdl/testbench/cic/wb_bpm_swap/bpm_swap/swap_freqgen.vhd | 1 | 5,416 | ------------------------------------------------------------------------------
-- Title : BPM RF channels swapping and de-swapping frequency generator
------------------------------------------------------------------------------
-- Author : Jose Alvim Berkenbrock
-- Company : CNPEM LNLS-DIG
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Generate swap and de-swap signals for given swapping frequency
-- and de-swapping delay settings.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.swap_pkg.all;
entity swap_freqgen is
generic(
g_delay_vec_width : natural := 8;
g_swap_div_freq_vec_width : natural := 16
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
en_i : in std_logic := '1';
sync_trig_i : in std_logic;
-- Swap and de-swap signals
swap_o : out std_logic;
deswap_o : out std_logic;
-- Swap mode setting
swap_mode_i : in t_swap_mode;
-- Swap frequency settings
swap_div_f_i : in std_logic_vector(g_swap_div_freq_vec_width-1 downto 0);
swap_div_f_cnt_en_i : in std_logic := '1';
-- De-swap delay setting
deswap_delay_i : in std_logic_vector(g_delay_vec_width-1 downto 0)
);
end swap_freqgen;
architecture rtl of swap_freqgen is
component swmode_sel
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
en_i : in std_logic := '1';
clk_swap_i : in std_logic;
swap_mode_i : in t_swap_mode;
swap_o : out std_logic;
deswap_o : out std_logic
);
end component;
component gc_shiftreg
generic (
g_size : integer
);
port (
clk_i : in std_logic;
en_i : in std_logic;
d_i : in std_logic;
q_o : out std_logic;
a_i : in std_logic_vector
);
end component;
signal count : natural range 0 to 2**g_swap_div_freq_vec_width-1;
signal cnst_swap_div_f_old : natural range 0 to 2**g_swap_div_freq_vec_width-1;
signal cnst_swap_div_f : natural range 0 to 2**g_swap_div_freq_vec_width-1;
signal clk_swap : std_logic;
signal deswap : std_logic;
signal synch_pending : std_logic;
begin
----------------------------------------------------------------
-- components instantiation
----------------------------------------------------------------
cmp_swmode_sel: swmode_sel
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
en_i => '1',
clk_swap_i => clk_swap,
swap_mode_i => swap_mode_i,
swap_o => swap_o,
deswap_o => deswap
);
cmp_gc_shiftreg: gc_shiftreg
generic map (
g_size => 2**g_delay_vec_width
)
port map (
clk_i => clk_i,
en_i => '1',
d_i => deswap,
q_o => deswap_o,
a_i => deswap_delay_i
);
----------------------------------------------------------------
-- RTL logic
----------------------------------------------------------------
p_reg_swap_div : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
cnst_swap_div_f_old <= 0;
cnst_swap_div_f <= 0;
else
if en_i = '1' then
cnst_swap_div_f_old <= (to_integer(unsigned(swap_div_f_i))-1);
cnst_swap_div_f <= cnst_swap_div_f_old;
end if;
end if;
end if;
end process p_reg_swap_div;
p_freq_swap : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
count <= 0;
clk_swap <= '1';
synch_pending <= '0';
else
if en_i = '1' then
-- Clear SW counter if we received a new SW divider period
-- This is important to ensure that we don't swap signals
-- between crossed antennas
if cnst_swap_div_f /= cnst_swap_div_f_old then
count <= 0;
clk_swap <= '1';
elsif swap_div_f_cnt_en_i = '1' then
if synch_pending = '1' then
count <= 0;
clk_swap <= '1';
synch_pending <= '0';
elsif count = cnst_swap_div_f then
count <= 0;
clk_swap <= not clk_swap;
else
count <= count + 1;
end if;
end if;
end if;
-- Clear SW counter on sync_trig regardless of en_i
if(sync_trig_i = '1' and -- sync trig arrived,
(count /= cnst_swap_div_f -- but no sync necessary
or clk_swap = '0')) then -- unless it's synchronized with a different phase, then reset it
synch_pending <= '1';
end if;
end if;
end if;
end process p_freq_swap;
end;
| lgpl-3.0 | 83b26a7bd70abd667108bdf1212864f1 | 0.439439 | 3.824859 | false | false | false | false |
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