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lnls-dig/dsp-cores | hdl/modules/pipeline/pipeline.vhd | 1 | 2,079 | -------------------------------------------------------------------------------
-- Title : Pipeline
-- Project :
-------------------------------------------------------------------------------
-- File : pipeline.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-06-10
-- Last update: 2015-10-15
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Pipeline with configurable width and depth
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-06-10 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity pipeline is
generic (
g_width : natural := 32;
g_depth : natural := 2
);
port (
data_i : in std_logic_vector(g_width-1 downto 0);
clk_i : in std_logic;
ce_i : in std_logic;
data_o : out std_logic_vector(g_width-1 downto 0)
);
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of pipeline : entity is "no";
end entity pipeline;
-------------------------------------------------------------------------------
architecture str of pipeline is
type slv_array is array(g_depth-1 downto 0) of std_logic_vector(g_width-1 downto 0);
signal pipe : slv_array;
begin -- architecture str
process(clk_i)
begin
if rising_edge(clk_i) then
if ce_i = '1' then
pipe(0) <= data_i;
for n in 1 to g_depth-1 loop
pipe(n) <= pipe(n-1);
end loop;
end if; --ce_i
end if; --clk_i
end process;
data_o <= pipe(g_depth-1);
end architecture str;
-------------------------------------------------------------------------------
| lgpl-3.0 | 1bb7d7c255685c3a196de247a51c264a | 0.397787 | 4.661435 | false | false | false | false |
TanND/Electronic | VHDL/D2_C1.vhd | 1 | 1,071 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D2_C1 is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(7 downto 0)
);
end D2_C1;
architecture D2_C1 of D2_C1 is
type state is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9);
signal s:state;
begin
next_state:process(rst,clk)
begin
if (rst='1') then s<=s0;
else
if (rising_edge(clk)) then
case s is
when s0 => s <=s1;
when s1 => s <=s2;
when s2 => s <=s3;
when s3 => s <=s4;
when s4 => s <=s5;
when s5 => s <=s6;
when s6 => s <=s7;
when s7 => s <=s8;
when s8 => s <=s9;
when s9 => s <=s0;
end case;
end if;
end if;
end process;
output_state:process(s)
begin
case s is
when s0=> Q<="00000000";
when s1=> Q<="00000001";
when s2=> Q<="00000010";
when s3=> Q<="00000011";
when s4=> Q<="00000100";
when s5=> Q<="00000101";
when s6=> Q<="00000110";
when s7=> Q<="00000111";
when s8=> Q<="00001001";
when s9=> Q<="00001010";
end case;
end process;
end D2_C1;
-- rst = 0.5Mhz, clk=10Mhz
| apache-2.0 | 25ef0817bd000b331bec2b2e0e2345be | 0.54902 | 2.353846 | false | false | false | false |
bruskajp/EE-316 | Project1/lcd_driver.vhd | 1 | 8,828 | ----------------------------------------------------------------------------------
-- Institution: Clarkson Univeristy
-- Engineers: Zander Blasingame and Brandon Norris
--
-- Create Date: 11/11/2016 21:06:23
-- Design Name:
-- Module Name: lcd_driver - Behavioral
-- Project Name:
-- Target Devices: Altera DE2
-- Tool Versions:
-- Description: Created for the final of EE 365, repurposed for EE 316.
-- Display Model:
--
-- | Mode Op/Prog State Reset/Fwd/Bckwd |
-- | Enable/Disable addr data |
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity lcd_driver is
Generic (
-- Input clk frequency is given as 50MHz
-- Internal clk frequency is 200Hz
-- Number picked such that T = 5 ms
constant cnt_max : integer := 83333--333
);
Port (
clk : in std_logic;
reset : in std_logic;
sys_fb : in std_logic;
sys_en : in std_logic;
sys_prog : in std_logic;
is_addr : in std_logic;
address : in std_logic_vector(7 downto 0);
data : in std_logic_vector(15 downto 0);
data_out : out std_logic_vector(7 downto 0);
enable_out : out std_logic;
mode_select_out : out std_logic
);
end lcd_driver;
architecture Behavioral of lcd_driver is
type word_mode is array (0 to 7) of std_logic_vector(7 downto 0);
-- Define signals here
signal lut_sel : integer range 0 to 47;
signal enable_sel : integer range 0 to 3;
signal clk_enable : std_logic := '1';
signal clk_cnt : integer range 0 to cnt_max;
signal sys_state_ascii : word_mode;
signal sys_mode_ascii : word_mode;
signal sys_en_ascii : word_mode;
-- Function to convert hex into ascii
function hex_to_ascii(hex_code : std_logic_vector(3 downto 0))
return std_logic_vector is
variable output : std_logic_vector(7 downto 0) := x"30";
begin
case hex_code is
when x"0" => output := x"30";
when x"1" => output := x"31";
when x"2" => output := x"32";
when x"3" => output := x"33";
when x"4" => output := x"34";
when x"5" => output := x"35";
when x"6" => output := x"36";
when x"7" => output := x"37";
when x"8" => output := x"38";
when x"9" => output := x"39";
when x"A" => output := x"41";
when x"B" => output := x"42";
when x"C" => output := x"43";
when x"D" => output := x"44";
when x"E" => output := x"45";
when x"F" => output := x"46";
when others => output := x"30";
end case;
return output;
end hex_to_ascii;
begin
-- Clock enabler
process(clk)
begin
if rising_edge(clk) then
if clk_cnt = cnt_max then
clk_cnt <= 0;
clk_enable <= '1';
else
clk_cnt <= clk_cnt + 1;
clk_enable <= '0';
end if;
end if;
end process;
-- enable_out selection clock
process(clk)
begin
if rising_edge(clk) and clk_enable = '1' then
if enable_sel = 3 then
enable_sel <= 1;
else
enable_sel <= enable_sel + 1;
end if;
end if;
end process;
-- data_out selection clock
process(clk)
begin
if rising_edge(clk) and clk_enable = '1' and enable_sel = 3 then
if lut_sel = 43 then
lut_sel <= 10;
else
lut_sel <= lut_sel + 1;
end if;
end if;
end process;
-- Mux for mode
process(sys_prog)
begin
if sys_prog = '0' then
sys_mode_ascii <= (x"4F", x"70", x"65", x"72", x"61", x"74", x"65", x"20"); -- Operate
else
sys_mode_ascii <= (x"50", x"72", x"6F", x"67", x"72", x"61", x"6D", x"20"); -- Program
end if;
end process;
-- Mux for state
process(reset, sys_fb)
begin
if reset = '1' then
sys_state_ascii <= (x"52", x"65", x"73", x"65", x"74", x"20", x"20", x"20"); -- Reset
else
if sys_fb = '1' then
sys_state_ascii <= (x"46", x"6F", x"72", x"77", x"61", x"72", x"64", x"20"); -- Forward
else
sys_state_ascii <= (x"42", x"61", x"63", x"6B", x"77", x"61", x"72", x"64"); -- Backward
end if;
end if;
end process;
-- Mux for sys enable ascii
process(sys_en, sys_prog, is_addr)
begin
if sys_prog = '0' then
if sys_en = '1' then
sys_en_ascii <= (x"45", x"6E", x"61", x"62", x"6C", x"65", x"20", x"20"); -- Enable
else
sys_en_ascii <= (x"44", x"69", x"73", x"61", x"62", x"6C", x"65", x"20"); -- Disable
end if;
else
if is_addr = '1' then
sys_en_ascii <= (x"41", x"64", x"64", x"72", x"65", x"73", x"73", x"20"); -- Address
else
sys_en_ascii <= (x"44", x"61", x"74", x"61", x"20", x"20", x"20", x"20"); -- Data
end if;
end if;
end process;
-- LUT for enable_out default 0
with enable_sel select enable_out <=
'1' when 0,
'0' when 1,
'1' when 2,
'0' when 3,
'0' when others;
-- LUT for data_out and mode_select_out default is #ff and 1 respectively
process(lut_sel)
begin
case lut_sel is
-- Initialize
when 0 => data_out <= x"38"; mode_select_out <= '0';
when 1 => data_out <= x"38"; mode_select_out <= '0';
when 2 => data_out <= x"38"; mode_select_out <= '0';
when 3 => data_out <= x"38"; mode_select_out <= '0';
when 4 => data_out <= x"38"; mode_select_out <= '0';
when 5 => data_out <= x"38"; mode_select_out <= '0';
when 6 => data_out <= x"01"; mode_select_out <= '0';
when 7 => data_out <= x"0C"; mode_select_out <= '0';
when 8 => data_out <= x"06"; mode_select_out <= '0';
when 9 => data_out <= x"80"; mode_select_out <= '0';
-- Op/Prog
when 10 => data_out <= sys_mode_ascii(0); mode_select_out <= '1';
when 11 => data_out <= sys_mode_ascii(1); mode_select_out <= '1';
when 12 => data_out <= sys_mode_ascii(2); mode_select_out <= '1';
when 13 => data_out <= sys_mode_ascii(3); mode_select_out <= '1';
when 14 => data_out <= sys_mode_ascii(4); mode_select_out <= '1';
when 15 => data_out <= sys_mode_ascii(5); mode_select_out <= '1';
when 16 => data_out <= sys_mode_ascii(6); mode_select_out <= '1';
when 17 => data_out <= sys_mode_ascii(7); mode_select_out <= '1';
-- System State
when 18 => data_out <= sys_state_ascii(0); mode_select_out <= '1';
when 19 => data_out <= sys_state_ascii(1); mode_select_out <= '1';
when 20 => data_out <= sys_state_ascii(2); mode_select_out <= '1';
when 21 => data_out <= sys_state_ascii(3); mode_select_out <= '1';
when 22 => data_out <= sys_state_ascii(4); mode_select_out <= '1';
when 23 => data_out <= sys_state_ascii(5); mode_select_out <= '1';
when 24 => data_out <= sys_state_ascii(6); mode_select_out <= '1';
when 25 => data_out <= sys_state_ascii(7); mode_select_out <= '1';
-- Newline
when 26 => data_out <= x"C0"; mode_select_out <= '0';
-- Enable / Disable
when 27 => data_out <= sys_en_ascii(0); mode_select_out <= '1';
when 28 => data_out <= sys_en_ascii(1); mode_select_out <= '1';
when 29 => data_out <= sys_en_ascii(2); mode_select_out <= '1';
when 30 => data_out <= sys_en_ascii(3); mode_select_out <= '1';
when 31 => data_out <= sys_en_ascii(4); mode_select_out <= '1';
when 32 => data_out <= sys_en_ascii(5); mode_select_out <= '1';
when 33 => data_out <= sys_en_ascii(6); mode_select_out <= '1';
when 34 => data_out <= sys_en_ascii(7); mode_select_out <= '1';
-- Address ex. x00
when 35 => data_out <= x"78"; mode_select_out <= '1';
when 36 => data_out <= hex_to_ascii(address(7 downto 4)); mode_select_out <= '1';
when 37 => data_out <= hex_to_ascii(address(3 downto 0)); mode_select_out <= '1';
-- Data ex. xA0A0
when 38 => data_out <= x"78"; mode_select_out <= '1';
when 39 => data_out <= hex_to_ascii(data(15 downto 12)); mode_select_out <= '1';
when 40 => data_out <= hex_to_ascii(data(11 downto 8)); mode_select_out <= '1';
when 41 => data_out <= hex_to_ascii(data(7 downto 4)); mode_select_out <= '1';
when 42 => data_out <= hex_to_ascii(data(3 downto 0)); mode_select_out <= '1';
-- Jump to first line
when 43 => data_out <= x"80"; mode_select_out <= '0';
-- Catch errors
when others => data_out <= x"FF"; mode_select_out <= '1';
end case;
end process;
end Behavioral; | gpl-3.0 | f05267138f82d5f9ad2b0e3d12b33b9b | 0.512234 | 3.045188 | false | false | false | false |
lnls-dig/dsp-cores | hdl/modules/cordic_iter/cordic_iter_slv.vhd | 1 | 7,062 | -------------------------------------------------------------------------------
-- Title : Iterative cordic SLV wrapper
-- Project :
-------------------------------------------------------------------------------
-- File : cordic_iter_slv.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2015-06-03
-- Last update: 2015-10-15
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: This wrapper allows for the iterative cordic to run at a rate
-- higher than the input's clock enable rate, while avoiding duplicate signal
-- inputs or losing inputs. It also converts the signed cordic core signals to
-- the std_logic_vector type.
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public License
-- as published by the Free Software Foundation, either version 3 of
-- the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-06-03 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
use work.dsp_cores_pkg.all;
entity cordic_input is
generic (
g_input_width : positive := 16); -- input size for x and y
port (
clk_i : in std_logic; -- clock input
ce_data_i : in std_logic; -- clock enable for data input
valid_i : in std_logic; -- valid data input
x_i : in std_logic_vector(g_input_width-1 downto 0); -- input for x (or I)
y_i : in std_logic_vector(g_input_width-1 downto 0); -- input for y (or Q)
ce_cordic_i : in std_logic; -- clock enable for cordic core
stall_cordic_i : in std_logic; -- signals the cordic core is busy
valid_o : out std_logic; -- indicates valid signal is stored
x_o : out std_logic_vector(g_input_width-1 downto 0); -- data output for x
y_o : out std_logic_vector(g_input_width-1 downto 0) -- data output for y
);
end entity cordic_input;
architecture behavioural of cordic_input is
signal x, y : std_logic_vector(g_input_width-1 downto 0);
signal valid : std_logic := '0';
signal stall : std_logic;
begin -- architecture behavioural
process(clk_i)
begin
if rising_edge(clk_i) then
--Cordic side: it cordic is not stalled, it will consume the data available
if ce_cordic_i = '1' and stall_cordic_i = '0' then
valid <= '0';
end if;
if ce_data_i = '1' and valid_i = '1' then
x <= x_i;
y <= y_i;
valid <= '1';
end if;
end if;
end process;
valid_o <= valid;
x_o <= x;
y_o <= y;
end architecture behavioural;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
use work.dsp_cores_pkg.all;
entity cordic_iter_slv is
generic (
g_input_width : positive := 16; -- input for x and y
g_xy_calc_width : positive := 22; -- xy internal calc width for x,y, including left padding (always 2 bits)
g_x_output_width : positive := 16; -- output for magnitude
g_phase_calc_width : positive := 22; -- internal width for phase, only right padding
g_phase_output_width : positive := 16; -- output width for phase signal (2's complement, -pi to pi
g_stages : positive := 16; -- total cordic stages
g_iter_per_clk : positive := 2; -- number of stages per clock cycle. g_stages must be a multiple of g_iter_per_clk
g_rounding : boolean := true -- Enables unregistered output rouding.
);
port (
clk_i : in std_logic; -- clock input
ce_data_i : in std_logic; -- clock enable for data input (same ce as valid signal)
valid_i : in std_logic; -- new valid data in input signals
ce_i : in std_logic; -- clock enable for internal cordic
x_i : in std_logic_vector(g_input_width-1 downto 0); -- input for x (or I)
y_i : in std_logic_vector(g_input_width-1 downto 0); -- input for y (or Q)
mag_o : out std_logic_vector(g_x_output_width-1 downto 0); -- magnitude output
phase_o : out std_logic_vector(g_phase_output_width-1 downto 0); -- phase output
valid_o : out std_logic); -- valid data on the output signals
end entity cordic_iter_slv;
architecture structural of cordic_iter_slv is
signal x_to_cordic : std_logic_vector(g_input_width-1 downto 0) := (others => '0');
signal y_to_cordic : std_logic_vector(g_input_width-1 downto 0) := (others => '0');
signal valid : std_logic := '0';
signal stall : std_logic := '0';
signal mag_signed : signed(g_x_output_width-1 downto 0) := (others => '0');
signal phase_signed : signed(g_phase_output_width-1 downto 0) := (others => '0');
begin -- architecture structural
cmp_input : cordic_input
generic map (
g_input_width => g_input_width)
port map (
clk_i => clk_i,
ce_data_i => ce_data_i,
valid_i => valid_i,
x_i => x_i,
y_i => y_i,
ce_cordic_i => ce_i,
stall_cordic_i => stall,
valid_o => valid,
x_o => x_to_cordic,
y_o => y_to_cordic);
cmp_cordic_core : cordic
generic map (
XY_CALC_WID => g_xy_calc_width,
XY_IN_WID => g_input_width,
X_OUT_WID => g_x_output_width,
PH_CALC_WID => g_phase_calc_width,
PH_OUT_WID => g_phase_output_width,
NUM_ITER => g_stages,
ITER_PER_CLK => g_iter_per_clk,
USE_INREG => false,
USE_CE => true,
ROUNDING => true)
port map (
clk => clk_i,
ce => ce_i,
b_start_in => valid,
s_x_in => signed(x_to_cordic),
s_y_in => signed(y_to_cordic),
s_x_o => mag_signed,
s_ph_o => phase_signed,
b_rdy_o => valid_o,
b_busy_o => stall);
mag_o <= std_logic_vector(mag_signed);
phase_o <= std_logic_vector(phase_signed);
end architecture structural;
| lgpl-3.0 | 876f9fb9c8e04c2a94bf1cc098ee92d3 | 0.551543 | 3.577508 | false | false | false | false |
TanND/Electronic | VHDL/D13_C1.vhd | 1 | 1,225 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY D13_C1 IS
PORT (
rst:in std_logic;
clk:IN STD_logic;
seg:out STD_Logic_vector(7 downto 0));
END D13_C1;
ARCHITECTURE D13_C1 of D13_C1 IS
signal temp: std_logic_vector(3 downto 0);
signal gray: std_logic_vector(3 downto 0);
begin
process (clk,rst)
begin
if(rst='1') then
temp<="0000";
gray<="0000";
elsif (rising_edge(clk)) then
if(temp="1001") then temp<="0000";
else temp <= temp+1;
end if;
gray(3)<=temp(3);
for i in 2 downto 0 loop
gray(i)<= temp(i+1) xor temp(i);
end loop;
end if;
end process;
process(gray)
begin
case gray is
when "0000" => seg<= x"C0";
when "0001" => seg<= x"F9";
when "0011" => seg<= x"A4";
when "0010" => seg<= x"B0";
when "0110" => seg<= x"99";
when "0111" => seg<= x"92";
when "0101" => seg<= x"82";
when "0100" => seg<= x"F8";
when "1100" => seg<= x"80";
when "1101" => seg<= x"90";
when others =>NULL;
end case;
end process;
end D13_C1;
--d= counter 100 ns; | apache-2.0 | 5355808fb08fd124cb16ccdf1c4f92a6 | 0.529796 | 2.875587 | false | false | false | false |
lnls-dig/dsp-cores | hdl/modules/clock_driver/conv_pkg.vhd | 1 | 54,712 | -------------------------------------------------------------------
-- System Generator version 13.4 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package conv_pkg is
constant simulating : boolean := false
-- synopsys translate_off
or true
-- synopsys translate_on
;
constant xlUnsigned : integer := 1;
constant xlSigned : integer := 2;
constant xlFloat : integer := 3;
constant xlWrap : integer := 1;
constant xlSaturate : integer := 2;
constant xlTruncate : integer := 1;
constant xlRound : integer := 2;
constant xlRoundBanker : integer := 3;
constant xlAddMode : integer := 1;
constant xlSubMode : integer := 2;
attribute black_box : boolean;
attribute syn_black_box : boolean;
attribute fpga_dont_touch: string;
attribute box_type : string;
attribute keep : string;
attribute syn_keep : boolean;
function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned;
function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector;
function std_logic_vector_to_signed(inp : std_logic_vector) return signed;
function signed_to_std_logic_vector(inp : signed) return std_logic_vector;
function unsigned_to_signed(inp : unsigned) return signed;
function signed_to_unsigned(inp : signed) return unsigned;
function pos(inp : std_logic_vector; arith : INTEGER) return boolean;
function all_same(inp: std_logic_vector) return boolean;
function all_zeros(inp: std_logic_vector) return boolean;
function is_point_five(inp: std_logic_vector) return boolean;
function all_ones(inp: std_logic_vector) return boolean;
function convert_type (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith,
quantization, overflow : INTEGER)
return std_logic_vector;
function cast (inp : std_logic_vector; old_bin_pt,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function shift_division_result(quotient, fraction: std_logic_vector;
fraction_width, shift_value, shift_dir: INTEGER)
return std_logic_vector;
function shift_op (inp: std_logic_vector;
result_width, shift_value, shift_dir: INTEGER)
return std_logic_vector;
function vec_slice (inp : std_logic_vector; upper, lower : INTEGER)
return std_logic_vector;
function s2u_slice (inp : signed; upper, lower : INTEGER)
return unsigned;
function u2u_slice (inp : unsigned; upper, lower : INTEGER)
return unsigned;
function s2s_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return signed;
function u2s_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return signed;
function s2u_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return unsigned;
function u2u_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return unsigned;
function u2v_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return std_logic_vector;
function s2v_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return std_logic_vector;
function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt,
new_arith : INTEGER) return std_logic_vector;
function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt,
new_arith : INTEGER) return std_logic_vector;
function max_signed(width : INTEGER) return std_logic_vector;
function min_signed(width : INTEGER) return std_logic_vector;
function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER) return std_logic_vector;
function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER;
function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER)
return INTEGER;
function sign_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector;
function zero_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector;
function zero_ext(inp : std_logic; new_width : INTEGER)
return std_logic_vector;
function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER)
return std_logic_vector;
function align_input(inp : std_logic_vector; old_width, delta, new_arith,
new_width: INTEGER)
return std_logic_vector;
function pad_LSB(inp : std_logic_vector; new_width: integer)
return std_logic_vector;
function pad_LSB(inp : std_logic_vector; new_width, arith : integer)
return std_logic_vector;
function max(L, R: INTEGER) return INTEGER;
function min(L, R: INTEGER) return INTEGER;
function "="(left,right: STRING) return boolean;
function boolean_to_signed (inp : boolean; width: integer)
return signed;
function boolean_to_unsigned (inp : boolean; width: integer)
return unsigned;
function boolean_to_vector (inp : boolean)
return std_logic_vector;
function std_logic_to_vector (inp : std_logic)
return std_logic_vector;
function integer_to_std_logic_vector (inp : integer; width, arith : integer)
return std_logic_vector;
function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer)
return integer;
function std_logic_to_integer(constant inp : std_logic := '0')
return integer;
function bin_string_element_to_std_logic_vector (inp : string; width, index : integer)
return std_logic_vector;
function bin_string_to_std_logic_vector (inp : string)
return std_logic_vector;
function hex_string_to_std_logic_vector (inp : string; width : integer)
return std_logic_vector;
function makeZeroBinStr (width : integer) return STRING;
function and_reduce(inp: std_logic_vector) return std_logic;
-- synopsys translate_off
function is_binary_string_invalid (inp : string)
return boolean;
function is_binary_string_undefined (inp : string)
return boolean;
function is_XorU(inp : std_logic_vector)
return boolean;
function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer)
return real;
function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer)
return real;
function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer)
return std_logic_vector;
function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer)
return std_logic_vector;
constant display_precision : integer := 20;
function real_to_string (inp : real) return string;
function valid_bin_string(inp : string) return boolean;
function std_logic_vector_to_bin_string(inp : std_logic_vector) return string;
function std_logic_to_bin_string(inp : std_logic) return string;
function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer)
return string;
function real_to_bin_string(inp : real; width, bin_pt, arith : integer)
return string;
type stdlogic_to_char_t is array(std_logic) of character;
constant to_char : stdlogic_to_char_t := (
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-');
-- synopsys translate_on
end conv_pkg;
package body conv_pkg is
function std_logic_vector_to_unsigned(inp : std_logic_vector)
return unsigned
is
begin
return unsigned (inp);
end;
function unsigned_to_std_logic_vector(inp : unsigned)
return std_logic_vector
is
begin
return std_logic_vector(inp);
end;
function std_logic_vector_to_signed(inp : std_logic_vector)
return signed
is
begin
return signed (inp);
end;
function signed_to_std_logic_vector(inp : signed)
return std_logic_vector
is
begin
return std_logic_vector(inp);
end;
function unsigned_to_signed (inp : unsigned)
return signed
is
begin
return signed(std_logic_vector(inp));
end;
function signed_to_unsigned (inp : signed)
return unsigned
is
begin
return unsigned(std_logic_vector(inp));
end;
function pos(inp : std_logic_vector; arith : INTEGER)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
if arith = xlUnsigned then
return true;
else
if vec(width-1) = '0' then
return true;
else
return false;
end if;
end if;
return true;
end;
function max_signed(width : INTEGER)
return std_logic_vector
is
variable ones : std_logic_vector(width-2 downto 0);
variable result : std_logic_vector(width-1 downto 0);
begin
ones := (others => '1');
result(width-1) := '0';
result(width-2 downto 0) := ones;
return result;
end;
function min_signed(width : INTEGER)
return std_logic_vector
is
variable zeros : std_logic_vector(width-2 downto 0);
variable result : std_logic_vector(width-1 downto 0);
begin
zeros := (others => '0');
result(width-1) := '1';
result(width-2 downto 0) := zeros;
return result;
end;
function and_reduce(inp: std_logic_vector) return std_logic
is
variable result: std_logic;
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := vec(0);
if width > 1 then
for i in 1 to width-1 loop
result := result and vec(i);
end loop;
end if;
return result;
end;
function all_same(inp: std_logic_vector) return boolean
is
variable result: boolean;
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := true;
if width > 0 then
for i in 1 to width-1 loop
if vec(i) /= vec(0) then
result := false;
end if;
end loop;
end if;
return result;
end;
function all_zeros(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable zero : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
zero := (others => '0');
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then
result := true;
else
result := false;
end if;
return result;
end;
function is_point_five(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (width > 1) then
if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then
result := true;
else
result := false;
end if;
else
if (vec(width-1) = '1') then
result := true;
else
result := false;
end if;
end if;
return result;
end;
function all_ones(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable one : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
one := (others => '1');
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then
result := true;
else
result := false;
end if;
return result;
end;
function full_precision_num_width(quantization, overflow, old_width,
old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return integer
is
variable result : integer;
begin
result := old_width + 2;
return result;
end;
function quantized_num_width(quantization, overflow, old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return integer
is
variable right_of_dp, left_of_dp, result : integer;
begin
right_of_dp := max(new_bin_pt, old_bin_pt);
left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt));
result := (old_width + 2) + (new_bin_pt - old_bin_pt);
return result;
end;
function convert_type (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith,
quantization, overflow : INTEGER)
return std_logic_vector
is
constant fp_width : integer :=
full_precision_num_width(quantization, overflow, old_width,
old_bin_pt, old_arith, new_width,
new_bin_pt, new_arith);
constant fp_bin_pt : integer := old_bin_pt;
constant fp_arith : integer := old_arith;
variable full_precision_result : std_logic_vector(fp_width-1 downto 0);
constant q_width : integer :=
quantized_num_width(quantization, overflow, old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith);
constant q_bin_pt : integer := new_bin_pt;
constant q_arith : integer := old_arith;
variable quantized_result : std_logic_vector(q_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
result := (others => '0');
full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt,
fp_arith);
if (quantization = xlRound) then
quantized_result := round_towards_inf(full_precision_result,
fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt,
q_arith);
elsif (quantization = xlRoundBanker) then
quantized_result := round_towards_even(full_precision_result,
fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt,
q_arith);
else
quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt, q_arith);
end if;
if (overflow = xlSaturate) then
result := saturation_arith(quantized_result, q_width, q_bin_pt,
q_arith, new_width, new_bin_pt, new_arith);
else
result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith,
new_width, new_bin_pt, new_arith);
end if;
return result;
end;
function cast (inp : std_logic_vector; old_bin_pt, new_width,
new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
constant left_of_dp : integer := (new_width - new_bin_pt)
- (old_width - old_bin_pt);
constant right_of_dp : integer := (new_bin_pt - old_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable j : integer;
begin
vec := inp;
for i in new_width-1 downto 0 loop
j := i - right_of_dp;
if ( j > old_width-1) then
if (new_arith = xlUnsigned) then
result(i) := '0';
else
result(i) := vec(old_width-1);
end if;
elsif ( j >= 0) then
result(i) := vec(j);
else
result(i) := '0';
end if;
end loop;
return result;
end;
function shift_division_result(quotient, fraction: std_logic_vector;
fraction_width, shift_value, shift_dir: INTEGER)
return std_logic_vector
is
constant q_width : integer := quotient'length;
constant f_width : integer := fraction'length;
constant vec_MSB : integer := q_width+f_width-1;
constant result_MSB : integer := q_width+fraction_width-1;
constant result_LSB : integer := vec_MSB-result_MSB;
variable vec : std_logic_vector(vec_MSB downto 0);
variable result : std_logic_vector(result_MSB downto 0);
begin
vec := ( quotient & fraction );
if shift_dir = 1 then
for i in vec_MSB downto 0 loop
if (i < shift_value) then
vec(i) := '0';
else
vec(i) := vec(i-shift_value);
end if;
end loop;
else
for i in 0 to vec_MSB loop
if (i > vec_MSB-shift_value) then
vec(i) := vec(vec_MSB);
else
vec(i) := vec(i+shift_value);
end if;
end loop;
end if;
result := vec(vec_MSB downto result_LSB);
return result;
end;
function shift_op (inp: std_logic_vector;
result_width, shift_value, shift_dir: INTEGER)
return std_logic_vector
is
constant inp_width : integer := inp'length;
constant vec_MSB : integer := inp_width-1;
constant result_MSB : integer := result_width-1;
constant result_LSB : integer := vec_MSB-result_MSB;
variable vec : std_logic_vector(vec_MSB downto 0);
variable result : std_logic_vector(result_MSB downto 0);
begin
vec := inp;
if shift_dir = 1 then
for i in vec_MSB downto 0 loop
if (i < shift_value) then
vec(i) := '0';
else
vec(i) := vec(i-shift_value);
end if;
end loop;
else
for i in 0 to vec_MSB loop
if (i > vec_MSB-shift_value) then
vec(i) := vec(vec_MSB);
else
vec(i) := vec(i+shift_value);
end if;
end loop;
end if;
result := vec(vec_MSB downto result_LSB);
return result;
end;
function vec_slice (inp : std_logic_vector; upper, lower : INTEGER)
return std_logic_vector
is
begin
return inp(upper downto lower);
end;
function s2u_slice (inp : signed; upper, lower : INTEGER)
return unsigned
is
begin
return unsigned(vec_slice(std_logic_vector(inp), upper, lower));
end;
function u2u_slice (inp : unsigned; upper, lower : INTEGER)
return unsigned
is
begin
return unsigned(vec_slice(std_logic_vector(inp), upper, lower));
end;
function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER)
return signed
is
begin
return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned));
end;
function s2u_cast (inp : signed; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return unsigned
is
begin
return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned));
end;
function u2s_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return signed
is
begin
return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned));
end;
function u2u_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return unsigned
is
begin
return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned));
end;
function u2v_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return std_logic_vector
is
begin
return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned);
end;
function s2v_cast (inp : signed; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return std_logic_vector
is
begin
return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned);
end;
function boolean_to_signed (inp : boolean; width : integer)
return signed
is
variable result : signed(width - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function boolean_to_unsigned (inp : boolean; width : integer)
return unsigned
is
variable result : unsigned(width - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function boolean_to_vector (inp : boolean)
return std_logic_vector
is
variable result : std_logic_vector(1 - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function std_logic_to_vector (inp : std_logic)
return std_logic_vector
is
variable result : std_logic_vector(1 - 1 downto 0);
begin
result(0) := inp;
return result;
end;
function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
result := zero_ext(vec(old_width-1 downto right_of_dp), new_width);
else
result := sign_ext(vec(old_width-1 downto right_of_dp), new_width);
end if;
else
if new_arith = xlUnsigned then
result := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
result := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
return result;
end;
function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
constant expected_new_width : integer := old_width - right_of_dp + 1;
variable vec : std_logic_vector(old_width-1 downto 0);
variable one_or_zero : std_logic_vector(new_width-1 downto 0);
variable truncated_val : std_logic_vector(new_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
truncated_val := zero_ext(vec(old_width-1 downto right_of_dp),
new_width);
else
truncated_val := sign_ext(vec(old_width-1 downto right_of_dp),
new_width);
end if;
else
if new_arith = xlUnsigned then
truncated_val := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
truncated_val := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
one_or_zero := (others => '0');
if (new_arith = xlSigned) then
if (vec(old_width-1) = '0') then
one_or_zero(0) := '1';
end if;
if (right_of_dp >= 2) and (right_of_dp <= old_width) then
if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then
one_or_zero(0) := '1';
end if;
end if;
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
if vec(right_of_dp-1) = '0' then
one_or_zero(0) := '0';
end if;
else
one_or_zero(0) := '0';
end if;
else
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
one_or_zero(0) := vec(right_of_dp-1);
end if;
end if;
if new_arith = xlSigned then
result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) +
std_logic_vector_to_signed(one_or_zero));
else
result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) +
std_logic_vector_to_unsigned(one_or_zero));
end if;
return result;
end;
function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
constant expected_new_width : integer := old_width - right_of_dp + 1;
variable vec : std_logic_vector(old_width-1 downto 0);
variable one_or_zero : std_logic_vector(new_width-1 downto 0);
variable truncated_val : std_logic_vector(new_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
truncated_val := zero_ext(vec(old_width-1 downto right_of_dp),
new_width);
else
truncated_val := sign_ext(vec(old_width-1 downto right_of_dp),
new_width);
end if;
else
if new_arith = xlUnsigned then
truncated_val := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
truncated_val := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
one_or_zero := (others => '0');
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then
one_or_zero(0) := vec(right_of_dp-1);
else
one_or_zero(0) := vec(right_of_dp);
end if;
end if;
if new_arith = xlSigned then
result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) +
std_logic_vector_to_signed(one_or_zero));
else
result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) +
std_logic_vector_to_unsigned(one_or_zero));
end if;
return result;
end;
function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant left_of_dp : integer := (old_width - old_bin_pt) -
(new_width - new_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable overflow : boolean;
begin
vec := inp;
overflow := true;
result := (others => '0');
if (new_width >= old_width) then
overflow := false;
end if;
if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then
if all_same(vec(old_width-1 downto new_width-1)) then
overflow := false;
end if;
end if;
if (old_arith = xlSigned and new_arith = xlUnsigned) then
if (old_width > new_width) then
if all_zeros(vec(old_width-1 downto new_width)) then
overflow := false;
end if;
else
if (old_width = new_width) then
if (vec(new_width-1) = '0') then
overflow := false;
end if;
end if;
end if;
end if;
if (old_arith = xlUnsigned and new_arith = xlUnsigned) then
if (old_width > new_width) then
if all_zeros(vec(old_width-1 downto new_width)) then
overflow := false;
end if;
else
if (old_width = new_width) then
overflow := false;
end if;
end if;
end if;
if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then
if all_same(vec(old_width-1 downto new_width-1)) then
overflow := false;
end if;
end if;
if overflow then
if new_arith = xlSigned then
if vec(old_width-1) = '0' then
result := max_signed(new_width);
else
result := min_signed(new_width);
end if;
else
if ((old_arith = xlSigned) and vec(old_width-1) = '1') then
result := (others => '0');
else
result := (others => '1');
end if;
end if;
else
if (old_arith = xlSigned) and (new_arith = xlUnsigned) then
if (vec(old_width-1) = '1') then
vec := (others => '0');
end if;
end if;
if new_width <= old_width then
result := vec(new_width-1 downto 0);
else
if new_arith = xlUnsigned then
result := zero_ext(vec, new_width);
else
result := sign_ext(vec, new_width);
end if;
end if;
end if;
return result;
end;
function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
variable result : std_logic_vector(new_width-1 downto 0);
variable result_arith : integer;
begin
if (old_arith = xlSigned) and (new_arith = xlUnsigned) then
result_arith := xlSigned;
end if;
result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith);
return result;
end;
function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is
begin
return max(a_bin_pt, b_bin_pt);
end;
function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER)
return INTEGER is
begin
return max(a_width - a_bin_pt, b_width - b_bin_pt);
end;
function pad_LSB(inp : std_logic_vector; new_width: integer)
return STD_LOGIC_VECTOR
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable pos : integer;
constant pad_pos : integer := new_width - orig_width - 1;
begin
vec := inp;
pos := new_width-1;
if (new_width >= orig_width) then
for i in orig_width-1 downto 0 loop
result(pos) := vec(i);
pos := pos - 1;
end loop;
if pad_pos >= 0 then
for i in pad_pos downto 0 loop
result(i) := '0';
end loop;
end if;
end if;
return result;
end;
function sign_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if new_width >= old_width then
result(old_width-1 downto 0) := vec;
if new_width-1 >= old_width then
for i in new_width-1 downto old_width loop
result(i) := vec(old_width-1);
end loop;
end if;
else
result(new_width-1 downto 0) := vec(new_width-1 downto 0);
end if;
return result;
end;
function zero_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if new_width >= old_width then
result(old_width-1 downto 0) := vec;
if new_width-1 >= old_width then
for i in new_width-1 downto old_width loop
result(i) := '0';
end loop;
end if;
else
result(new_width-1 downto 0) := vec(new_width-1 downto 0);
end if;
return result;
end;
function zero_ext(inp : std_logic; new_width : INTEGER)
return std_logic_vector
is
variable result : std_logic_vector(new_width-1 downto 0);
begin
result(0) := inp;
for i in new_width-1 downto 1 loop
result(i) := '0';
end loop;
return result;
end;
function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER)
return std_logic_vector
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if arith = xlUnsigned then
result := zero_ext(vec, new_width);
else
result := sign_ext(vec, new_width);
end if;
return result;
end;
function pad_LSB(inp : std_logic_vector; new_width, arith: integer)
return STD_LOGIC_VECTOR
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable pos : integer;
begin
vec := inp;
pos := new_width-1;
if (arith = xlUnsigned) then
result(pos) := '0';
pos := pos - 1;
else
result(pos) := vec(orig_width-1);
pos := pos - 1;
end if;
if (new_width >= orig_width) then
for i in orig_width-1 downto 0 loop
result(pos) := vec(i);
pos := pos - 1;
end loop;
if pos >= 0 then
for i in pos downto 0 loop
result(i) := '0';
end loop;
end if;
end if;
return result;
end;
function align_input(inp : std_logic_vector; old_width, delta, new_arith,
new_width: INTEGER)
return std_logic_vector
is
variable vec : std_logic_vector(old_width-1 downto 0);
variable padded_inp : std_logic_vector((old_width + delta)-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if delta > 0 then
padded_inp := pad_LSB(vec, old_width+delta);
result := extend_MSB(padded_inp, new_width, new_arith);
else
result := extend_MSB(vec, new_width, new_arith);
end if;
return result;
end;
function max(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
function "="(left,right: STRING) return boolean is
begin
if (left'length /= right'length) then
return false;
else
test : for i in 1 to left'length loop
if left(i) /= right(i) then
return false;
end if;
end loop test;
return true;
end if;
end;
-- synopsys translate_off
function is_binary_string_invalid (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 1 to vec'length loop
if ( vec(i) = 'X' ) then
result := true;
end if;
end loop;
return result;
end;
function is_binary_string_undefined (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 1 to vec'length loop
if ( vec(i) = 'U' ) then
result := true;
end if;
end loop;
return result;
end;
function is_XorU(inp : std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 0 to width-1 loop
if (vec(i) = 'U') or (vec(i) = 'X') then
result := true;
end if;
end loop;
return result;
end;
function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer)
return real
is
variable vec : std_logic_vector(inp'length-1 downto 0);
variable result, shift_val, undefined_real : real;
variable neg_num : boolean;
begin
vec := inp;
result := 0.0;
neg_num := false;
if vec(inp'length-1) = '1' then
neg_num := true;
end if;
for i in 0 to inp'length-1 loop
if vec(i) = 'U' or vec(i) = 'X' then
return undefined_real;
end if;
if arith = xlSigned then
if neg_num then
if vec(i) = '0' then
result := result + 2.0**i;
end if;
else
if vec(i) = '1' then
result := result + 2.0**i;
end if;
end if;
else
if vec(i) = '1' then
result := result + 2.0**i;
end if;
end if;
end loop;
if arith = xlSigned then
if neg_num then
result := result + 1.0;
result := result * (-1.0);
end if;
end if;
shift_val := 2.0**(-1*bin_pt);
result := result * shift_val;
return result;
end;
function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer)
return real
is
variable result : real := 0.0;
begin
if inp = '1' then
result := 1.0;
end if;
if arith = xlSigned then
assert false
report "It doesn't make sense to convert a 1 bit number to a signed real.";
end if;
return result;
end;
-- synopsys translate_on
function integer_to_std_logic_vector (inp : integer; width, arith : integer)
return std_logic_vector
is
variable result : std_logic_vector(width-1 downto 0);
variable unsigned_val : unsigned(width-1 downto 0);
variable signed_val : signed(width-1 downto 0);
begin
if (arith = xlSigned) then
signed_val := to_signed(inp, width);
result := signed_to_std_logic_vector(signed_val);
else
unsigned_val := to_unsigned(inp, width);
result := unsigned_to_std_logic_vector(unsigned_val);
end if;
return result;
end;
function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer)
return integer
is
constant width : integer := inp'length;
variable unsigned_val : unsigned(width-1 downto 0);
variable signed_val : signed(width-1 downto 0);
variable result : integer;
begin
if (arith = xlSigned) then
signed_val := std_logic_vector_to_signed(inp);
result := to_integer(signed_val);
else
unsigned_val := std_logic_vector_to_unsigned(inp);
result := to_integer(unsigned_val);
end if;
return result;
end;
function std_logic_to_integer(constant inp : std_logic := '0')
return integer
is
begin
if inp = '1' then
return 1;
else
return 0;
end if;
end;
function makeZeroBinStr (width : integer) return STRING is
variable result : string(1 to width+3);
begin
result(1) := '0';
result(2) := 'b';
for i in 3 to width+2 loop
result(i) := '0';
end loop;
result(width+3) := '.';
return result;
end;
-- synopsys translate_off
function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer)
return std_logic_vector
is
variable result : std_logic_vector(width-1 downto 0);
begin
result := (others => '0');
return result;
end;
function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer)
return std_logic_vector
is
variable real_val : real;
variable int_val : integer;
variable result : std_logic_vector(width-1 downto 0) := (others => '0');
variable unsigned_val : unsigned(width-1 downto 0) := (others => '0');
variable signed_val : signed(width-1 downto 0) := (others => '0');
begin
real_val := inp;
int_val := integer(real_val * 2.0**(bin_pt));
if (arith = xlSigned) then
signed_val := to_signed(int_val, width);
result := signed_to_std_logic_vector(signed_val);
else
unsigned_val := to_unsigned(int_val, width);
result := unsigned_to_std_logic_vector(unsigned_val);
end if;
return result;
end;
-- synopsys translate_on
function valid_bin_string (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
begin
vec := inp;
if (vec(1) = '0' and vec(2) = 'b') then
return true;
else
return false;
end if;
end;
function hex_string_to_std_logic_vector(inp: string; width : integer)
return std_logic_vector is
constant strlen : integer := inp'LENGTH;
variable result : std_logic_vector(width-1 downto 0);
variable bitval : std_logic_vector((strlen*4)-1 downto 0);
variable posn : integer;
variable ch : character;
variable vec : string(1 to strlen);
begin
vec := inp;
result := (others => '0');
posn := (strlen*4)-1;
for i in 1 to strlen loop
ch := vec(i);
case ch is
when '0' => bitval(posn downto posn-3) := "0000";
when '1' => bitval(posn downto posn-3) := "0001";
when '2' => bitval(posn downto posn-3) := "0010";
when '3' => bitval(posn downto posn-3) := "0011";
when '4' => bitval(posn downto posn-3) := "0100";
when '5' => bitval(posn downto posn-3) := "0101";
when '6' => bitval(posn downto posn-3) := "0110";
when '7' => bitval(posn downto posn-3) := "0111";
when '8' => bitval(posn downto posn-3) := "1000";
when '9' => bitval(posn downto posn-3) := "1001";
when 'A' | 'a' => bitval(posn downto posn-3) := "1010";
when 'B' | 'b' => bitval(posn downto posn-3) := "1011";
when 'C' | 'c' => bitval(posn downto posn-3) := "1100";
when 'D' | 'd' => bitval(posn downto posn-3) := "1101";
when 'E' | 'e' => bitval(posn downto posn-3) := "1110";
when 'F' | 'f' => bitval(posn downto posn-3) := "1111";
when others => bitval(posn downto posn-3) := "XXXX";
-- synopsys translate_off
ASSERT false
REPORT "Invalid hex value" SEVERITY ERROR;
-- synopsys translate_on
end case;
posn := posn - 4;
end loop;
if (width <= strlen*4) then
result := bitval(width-1 downto 0);
else
result((strlen*4)-1 downto 0) := bitval;
end if;
return result;
end;
function bin_string_to_std_logic_vector (inp : string)
return std_logic_vector
is
variable pos : integer;
variable vec : string(1 to inp'length);
variable result : std_logic_vector(inp'length-1 downto 0);
begin
vec := inp;
pos := inp'length-1;
result := (others => '0');
for i in 1 to vec'length loop
-- synopsys translate_off
if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U') then
assert false
report "Input string is larger than output std_logic_vector. Truncating output.";
return result;
end if;
-- synopsys translate_on
if vec(i) = '0' then
result(pos) := '0';
pos := pos - 1;
end if;
if vec(i) = '1' then
result(pos) := '1';
pos := pos - 1;
end if;
-- synopsys translate_off
if (vec(i) = 'X' or vec(i) = 'U') then
result(pos) := 'U';
pos := pos - 1;
end if;
-- synopsys translate_on
end loop;
return result;
end;
function bin_string_element_to_std_logic_vector (inp : string; width, index : integer)
return std_logic_vector
is
constant str_width : integer := width + 4;
constant inp_len : integer := inp'length;
constant num_elements : integer := (inp_len + 1)/str_width;
constant reverse_index : integer := (num_elements-1) - index;
variable left_pos : integer;
variable right_pos : integer;
variable vec : string(1 to inp'length);
variable result : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := (others => '0');
if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then
left_pos := 1;
right_pos := width + 3;
result := bin_string_to_std_logic_vector(vec(left_pos to right_pos));
end if;
if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then
left_pos := (reverse_index * str_width) + 1;
right_pos := left_pos + width + 2;
result := bin_string_to_std_logic_vector(vec(left_pos to right_pos));
end if;
return result;
end;
-- synopsys translate_off
function std_logic_vector_to_bin_string(inp : std_logic_vector)
return string
is
variable vec : std_logic_vector(1 to inp'length);
variable result : string(vec'range);
begin
vec := inp;
for i in vec'range loop
result(i) := to_char(vec(i));
end loop;
return result;
end;
function std_logic_to_bin_string(inp : std_logic)
return string
is
variable result : string(1 to 3);
begin
result(1) := '0';
result(2) := 'b';
result(3) := to_char(inp);
return result;
end;
function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer)
return string
is
variable width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable str_pos : integer;
variable result : string(1 to width+3);
begin
vec := inp;
str_pos := 1;
result(str_pos) := '0';
str_pos := 2;
result(str_pos) := 'b';
str_pos := 3;
for i in width-1 downto 0 loop
if (((width+3) - bin_pt) = str_pos) then
result(str_pos) := '.';
str_pos := str_pos + 1;
end if;
result(str_pos) := to_char(vec(i));
str_pos := str_pos + 1;
end loop;
if (bin_pt = 0) then
result(str_pos) := '.';
end if;
return result;
end;
function real_to_bin_string(inp : real; width, bin_pt, arith : integer)
return string
is
variable result : string(1 to width);
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := real_to_std_logic_vector(inp, width, bin_pt, arith);
result := std_logic_vector_to_bin_string(vec);
return result;
end;
function real_to_string (inp : real) return string
is
variable result : string(1 to display_precision) := (others => ' ');
begin
result(real'image(inp)'range) := real'image(inp);
return result;
end;
-- synopsys translate_on
end conv_pkg;
| lgpl-3.0 | 53e2c458ca0f3145afcdff60547dc237 | 0.530341 | 3.971545 | false | false | false | false |
SoCdesign/EHA | RTL/Hand_Shaking/Checkers/Control_part_checkers/Handshaking_FC/Arbiter_checkers/RTL_and_Synthesis/Arbiter_pseudo.vhd | 1 | 7,348 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Arbiter_pseudo is
port (
Req_N, Req_E, Req_W,Req_S, Req_L:in std_logic; -- From LBDR modules
DCTS: in std_logic; -- Getting the CTS signal from the input FIFO of the next router/NI (for hand-shaking)
RTS_FF: in std_logic;
state: in std_logic_vector (5 downto 0); -- 6 states for Arbiter's FSM
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
Xbar_sel : out std_logic_vector (4 downto 0); -- select lines for XBAR
RTS_FF_in: out std_logic; -- Valid output which is sent to the next router/NI to specify that the data on the output port is valid
state_in: out std_logic_vector (5 downto 0); -- 6 states for Arbiter's FSM
next_state_out: out std_logic_vector (5 downto 0) -- 6 states for Arbiter's FSM
);
end;
architecture behavior of Arbiter_pseudo is
-- next
-- Arbiter router or NI
-- ------------------------------------- ----
-- from LBDR ---> |Req(s) RTS | -----> |DRTS
-- To FIFO <--- |Grant(s) DCTS| <----- |CTS
-- to XBAR <--- |Xbar_sel | |
-- ------------------------------------- ----
--------------------------------------------------------------------------------------------
-- an example of a request/grant + handshake process with next router or NI
-- CLK _|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|__
-- Req _____|'''''''''''''''''''''''''''''''''''''''''''|________
-- _________ ___________________ _______ _______ _______ ____
-- TX _________X_______HEADER______X_Body__X_Body__X__Tail_X____
-- Grant _________________________|'''|___|'''|___|'''|____________
-- RTs _________|'''''''''''''''''''|___|'''''''|___|'''''''|____
-- DCTS _________________________|'''|_______|'''|_______|'''|____
-- |<---------clear----------->|
-- | to send |
--------------------------------------------------------------------------------------------
SIGNAL next_state: std_logic_vector (5 downto 0); -- : STATE_TYPE := IDLE;
CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001";
CONSTANT Local: std_logic_vector (5 downto 0) := "000010";
CONSTANT North: std_logic_vector (5 downto 0) := "000100";
CONSTANT East: std_logic_vector (5 downto 0) := "001000";
CONSTANT West: std_logic_vector (5 downto 0) := "010000";
CONSTANT South: std_logic_vector (5 downto 0) := "100000";
begin
next_state_out <= next_state;
-- anything below here is pure combinational
process(RTS_FF, DCTS, state, next_state)begin
if RTS_FF = '1' and DCTS = '0' then
state_in <= state;
else
state_in <= next_state;
end if;
end process;
process(state, RTS_FF, DCTS)begin
if state = IDLE then
RTS_FF_in <= '0';
-- if there was a grant given to one of the inputs,
-- tell the next router/NI that the output data is valid
else
if RTS_FF = '1' and DCTS = '1' then
RTS_FF_in <= '0';
else
RTS_FF_in <= '1';
end if;
end if ;
end process;
-- sets the grants using round robin
-- the order is L --> N --> E --> W --> S and then back to L
process(state, Req_N, Req_E, Req_W, Req_S, Req_L, DCTS, RTS_FF) begin
Grant_N <= '0';
Grant_E <= '0';
Grant_W <= '0';
Grant_S <= '0';
Grant_L <= '0';
Xbar_sel<= "00000";
case(state) is
when IDLE =>
Xbar_sel<= "00000";
If Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
else
next_state <= IDLE;
end if;
when North =>
Grant_N <= DCTS and RTS_FF ;
Xbar_sel<= "00001";
If Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
else
next_state <= IDLE;
end if;
when East =>
Grant_E <= DCTS and RTS_FF;
Xbar_sel<= "00010";
If Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
else
next_state <= IDLE;
end if;
when West =>
Grant_W <= DCTS and RTS_FF;
Xbar_sel<= "00100";
If Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
else
next_state <= IDLE;
end if;
when South =>
Grant_S <= DCTS and RTS_FF;
Xbar_sel<= "01000";
If Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
else
next_state <= IDLE;
end if;
when others => -- Local
Grant_L <= DCTS and RTS_FF;
Xbar_sel<= "10000";
If Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
else
next_state <= IDLE;
end if;
end case ;
end process;
end;
| gpl-3.0 | 49861cd1e4f918b7b7101aad1beab431 | 0.393032 | 4.355661 | false | false | false | false |
SoCdesign/EHA | RTL/Immortal_Chip/modules_with_fault_injectors/to_be_tested/FIFO_one_hot_with_checkers_with_FI.vhd | 1 | 10,899 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
DRTS: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
CTS: out std_logic;
empty_out: out std_logic;
read_pointer_out, write_pointer_out: out std_logic_vector(3 downto 0);
write_en_out :out std_logic;
-- fault injector signals
shift: in std_logic;
fault_clk: in std_logic;
data_in_serial: in std_logic;
data_out_serial: out std_logic;
-- Checker outputs
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
--err_CTS_in,
err_write_en,
err_not_CTS_in,
--err_not_write_en,
err_read_en_mismatch : out std_logic
);
end FIFO;
architecture behavior of FIFO is
signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(3 downto 0);
signal full, empty: std_logic;
signal read_en, write_en: std_logic;
signal CTS_in, CTS_out: std_logic;
signal DRTS_faulty, read_en_N_faulty, read_en_E_faulty, read_en_W_faulty, read_en_S_faulty, read_en_L_faulty: std_logic;
signal CTS_out_faulty, CTS_in_faulty: std_logic;
signal read_pointer_faulty, read_pointer_in_faulty, write_pointer_faulty, write_pointer_in_faulty: std_logic_vector (3 downto 0);
signal empty_faulty, full_faulty, read_en_faulty, write_en_faulty: std_logic;
component FIFO_control_part_checkers is
port ( DRTS: in std_logic;
CTS_out: in std_logic;
CTS_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
read_pointer_in: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
write_pointer_in: in std_logic_vector(3 downto 0);
empty_out: in std_logic;
full_out: in std_logic;
read_en_out: in std_logic;
write_en_out: in std_logic;
-- Checker outputs
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
--err_CTS_in,
err_write_en,
err_not_CTS_in,
--err_not_write_en,
err_read_en_mismatch : out std_logic
);
end component;
component fault_injector is
generic(DATA_WIDTH : integer := 32;
ADDRESS_WIDTH : integer := 5);
port(
data_in: in std_logic_vector (DATA_WIDTH-1 downto 0);
address: in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
sta_0: in std_logic;
sta_1: in std_logic;
data_out: out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end component;
component shift_register_serial_in is
generic (
REG_WIDTH: integer := 35
);
port (
clk, reset : in std_logic;
shift: in std_logic;
data_in_serial: in std_logic;
data_out_parallel: out std_logic_vector(REG_WIDTH-1 downto 0);
data_out_serial: out std_logic
);
end component;
signal FI_add_sta: std_logic_vector(34 downto 0); -- 28 bits for inputs and internal signals
-- 5 bits for fault injection location address (ceil of log2(36) = 6)
-- 2 bits for type of fault (SA0 or SA1)
signal non_faulty_signals: std_logic_vector (27 downto 0);
signal faulty_signals: std_logic_vector(27 downto 0); -- 28 bits for inputs and internal signals (with one fault injected in one of them)
begin
non_faulty_signals <= DRTS & read_en_N & read_en_E & read_en_W & read_en_S & read_en_L &
CTS_out & CTS_in & read_pointer & read_pointer_in & write_pointer & write_pointer_in &
empty & full & read_en & write_en;
FI: fault_injector generic map(DATA_WIDTH => 28, ADDRESS_WIDTH => 5)
port map (data_in=> non_faulty_signals , address=> FI_add_sta(6 downto 2), sta_0=> FI_add_sta(1), sta_1=> FI_add_sta(0), data_out=> faulty_signals
);
-- Extracting faulty values for input, internal and output signals
DRTS_faulty <= faulty_signals(27);
read_en_N_faulty <= faulty_signals(26);
read_en_E_faulty <= faulty_signals(25);
read_en_W_faulty <= faulty_signals(24);
read_en_S_faulty <= faulty_signals(23);
read_en_L_faulty <= faulty_signals(22);
CTS_out_faulty <= faulty_signals(21);
CTS_in_faulty <= faulty_signals(20);
read_pointer_faulty <= faulty_signals(19 downto 16);
read_pointer_in_faulty <= faulty_signals(15 downto 12);
write_pointer_faulty <= faulty_signals(11 downto 8);
write_pointer_in_faulty <= faulty_signals(7 downto 4);
empty_faulty <= faulty_signals(3);
full_faulty <= faulty_signals(2);
read_en_faulty <= faulty_signals(1);
write_en_faulty <= faulty_signals(0);
SR: shift_register_serial_in generic map(REG_WIDTH => 35)
port map( clk=> fault_clk, reset=>reset, shift=> shift,data_in_serial=> data_in_serial,
data_out_parallel=> FI_add_sta, data_out_serial=> data_out_serial
);
-- FIFO Control Part checkers instantiation
FIFOCONTROLPARTCHECKERS: FIFO_control_part_checkers port map (
DRTS => DRTS,
CTS_out => CTS_out, CTS_in => CTS_in,
read_en_N => read_en_N, read_en_E => read_en_E, read_en_W => read_en_W, read_en_S => read_en_S, read_en_L => read_en_L,
read_pointer => read_pointer, read_pointer_in => read_pointer_in,
write_pointer => write_pointer, write_pointer_in => write_pointer_in,
empty_out => empty, full_out => full,
read_en_out => read_en, write_en_out => write_en,
err_write_en_write_pointer => err_write_en_write_pointer,
err_not_write_en_write_pointer => err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => err_read_pointer_write_pointer_full,
err_read_pointer_increment => err_read_pointer_increment,
err_read_pointer_not_increment => err_read_pointer_not_increment,
err_write_en => err_write_en,
err_not_CTS_in => err_not_CTS_in,
err_read_en_mismatch => err_read_en_mismatch
);
process (clk, reset)begin
if reset = '0' then
read_pointer <= "0001";
write_pointer <= "0001";
CTS_out<='0';
elsif clk'event and clk = '1' then
write_pointer <= write_pointer_in_faulty;
read_pointer <= read_pointer_in_faulty;
CTS_out<=CTS_in_faulty;
end if;
end process;
-- anything below here is pure combinational
-- combinatorial part
write_pointer_out <= write_pointer;
read_pointer_out <= read_pointer;
write_en_out <= write_en;
read_en <= (read_en_N_faulty or read_en_E_faulty or read_en_W_faulty or read_en_S_faulty or read_en_L_faulty) and not empty_faulty;
empty_out <= empty;
CTS <= CTS_out;
process(write_en_faulty, write_pointer_faulty)begin
if write_en_faulty = '1'then
write_pointer_in <= write_pointer_faulty(2 downto 0)&write_pointer_faulty(3);
else
write_pointer_in <= write_pointer_faulty;
end if;
end process;
process(read_en_faulty, empty_faulty, read_pointer_faulty) begin
if (read_en_faulty = '1' and empty_faulty = '0') then
read_pointer_in <= read_pointer_faulty(2 downto 0)&read_pointer_faulty(3);
else
read_pointer_in <= read_pointer_faulty;
end if;
end process;
process(full_faulty, DRTS_faulty, CTS_out_faulty) begin
if CTS_out_faulty = '0' and DRTS_faulty = '1' and full_faulty ='0' then
CTS_in <= '1';
write_en <= '1';
else
CTS_in <= '0';
write_en <= '0';
end if;
end process;
process(write_pointer_faulty, read_pointer_faulty) begin
if read_pointer_faulty = write_pointer_faulty then
empty <= '1';
else
empty <= '0';
end if;
-- if write_pointer = read_pointer>>1 then
if write_pointer_faulty = read_pointer_faulty(0)&read_pointer_faulty(3 downto 1) then
full <= '1';
else
full <= '0';
end if;
end process;
end;
| gpl-3.0 | bc63804d321968a5f7be44f806e4cdd3 | 0.526103 | 3.864894 | false | false | false | false |
bruskajp/EE-316 | Project2/Vivado_NexysBoard/project_2b/project_2b.srcs/sources_1/imports/Downloads/univ_bin_counter.vhd | 1 | 1,772 | -- Source: http://academic.csuohio.edu/chu_p/rtl/fpga_vhdl.html
-- Listing 4.10
-- modified: added port "clk_en", Sept 5, 2013
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity univ_bin_counter is
generic(N: integer := 8);
port(
clk, reset : in std_logic;
syn_clr, load, en, up : in std_logic;
clk_en : in std_logic ;
d : in std_logic_vector(N-1 downto 0);
max : in unsigned(N-1 downto 0);
min : in unsigned(N-1 downto 0);
q : out std_logic_vector(N-1 downto 0)
);
end univ_bin_counter;
architecture arch of univ_bin_counter is
signal r_reg : unsigned(N-1 downto 0) := min;
signal r_next : unsigned(N-1 downto 0);
signal max_tick : std_logic;
signal min_tick : std_logic;
begin
-- register
process(clk,reset,clk_en,syn_clr,min,r_next)
begin
if (reset='1' or syn_clr = '1') then
r_reg <= min;
elsif rising_edge(clk) and clk_en = '1' then
r_reg <= r_next;
end if;
end process;
process (en,up,r_reg,min,max)
begin
if (en = '1') then
if (up = '1') then
if (r_reg = max) then
r_next <= min;
elsif (r_reg /= max) then
r_next <= r_reg +1;
end if;
elsif (up = '0') then
if (r_reg = min) then
r_next <= max;
elsif (r_reg /= min) then
r_next <= r_reg -1;
end if;
end if;
elsif (en = '0') then
r_next <= r_reg;
end if;
end process;
q <= std_logic_vector(r_reg);
end arch;
| gpl-3.0 | b4b2a56217583e15f05a07768adf4479 | 0.479684 | 3.233577 | false | false | false | false |
TanND/Electronic | VHDL/D15_C1.vhd | 1 | 1,197 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D15_C1 is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR(7 downto 0)
);
end D15_C1;
architecture D15_C1 of D15_C1 is
type state is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9);
signal s:state;
begin
next_state:process(rst,clk)
begin
if (rst='1') then s<=s0;
else
if (rising_edge(clk)) then
case s is
when s0 => s <=s1;
when s1 => s <=s2;
when s2 => s <=s3;
when s3 => s <=s4;
when s4 => s <=s5;
when s5 => s <=s6;
when s6 => s <=s7;
when s7 => s <=s8;
when s8 => s <=s9;
when s9 => s <=s0;
end case;
end if;
end if;
end process;
output_state:process(s)
begin
case s is
when s0 => seg<= x"C0";
when s1 => seg<= x"F9";
when s2 => seg<= x"A4";
when s3 => seg<= x"B0";
when s4 => seg<= x"99";
when s5 => seg<= x"92";
when s6 => seg<= x"82";
when s7 => seg<= x"F8";
when s8 => seg<= x"80";
when s9 => seg<= x"90";
end case;
end process;
end D15_C1;
-- rst=0.5Mhz; clk=20Mhz; | apache-2.0 | 9c973467c4493a3e93f67ae88be5628b | 0.472013 | 2.557692 | false | false | false | false |
SoCdesign/EHA | RTL/Immortal_Chip/modules_with_fault_injectors/Arbiter_one_hot_with_checkers.vhd | 1 | 16,697 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.math_real."ceil";
use IEEE.math_real."log2";
entity Arbiter is
port ( reset: in std_logic;
clk: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules
DCTS: in std_logic; -- Getting the CTS signal from the input FIFO of the next router/NI (for hand-shaking)
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
Xbar_sel : out std_logic_vector(4 downto 0); -- select lines for XBAR
RTS: out std_logic; -- Valid output which is sent to the next router/NI to specify that the data on the output port is valid
-- fault injector signals
shift: in std_logic;
fault_clk: in std_logic;
data_in_serial: in std_logic;
data_out_serial: out std_logic;
-- Checker outputs
err_state_IDLE_xbar,
err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE,
err_IDLE_Req_L,
err_Local_Req_L,
err_North_Req_N,
--err_East_Req_E,
--err_West_Req_W,
--err_South_Req_S,
err_IDLE_Req_N,
err_Local_Req_N,
--err_North_Req_E,
--err_East_Req_W,
--err_West_Req_S,
err_South_Req_L,
--err_IDLE_Req_E,
--err_Local_Req_E,
--err_North_Req_W,
--err_East_Req_S,
err_West_Req_L,
err_South_Req_N,
--err_IDLE_Req_W,
--err_Local_Req_W,
--err_North_Req_S,
err_East_Req_L,
err_West_Req_N,
--err_South_Req_E,
--err_IDLE_Req_S,
--err_Local_Req_S,
--err_North_Req_L,
err_East_Req_N,
--err_West_Req_E,
--err_South_Req_W,
err_next_state_onehot,
err_state_in_onehot,
--err_DCTS_RTS_FF_state_Grant_L,
--err_DCTS_RTS_FF_state_Grant_N,
--err_DCTS_RTS_FF_state_Grant_E,
--err_DCTS_RTS_FF_state_Grant_W,
--err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel,
err_state_east_xbar_sel,
err_state_west_xbar_sel,
err_state_south_xbar_sel : out std_logic
--err_state_local_xbar_sel : out std_logic
);
end;
architecture behavior of Arbiter is
-- TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SUBTYPE STATE_TYPE IS STD_LOGIC_VECTOR (5 downto 0);
CONSTANT IDLE: STATE_TYPE := "000001";
CONSTANT Local: STATE_TYPE := "000010";
CONSTANT North: STATE_TYPE := "000100";
CONSTANT East: STATE_TYPE := "001000";
CONSTANT West: STATE_TYPE := "010000";
CONSTANT South: STATE_TYPE := "100000";
SIGNAL state, state_in, next_state : STATE_TYPE := IDLE;
SIGNAL RTS_FF, RTS_FF_in: std_logic;
signal Grant_N_sig, Grant_E_sig, Grant_W_sig, Grant_S_sig, Grant_L_sig: std_logic;
signal Xbar_sel_sig: std_logic_vector(4 downto 0);
component Arbiter_checkers is
port (
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic;
DCTS: in std_logic;
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L: in std_logic;
Xbar_sel : in std_logic_vector(4 downto 0);
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
next_state_out: in std_logic_vector (5 downto 0);
RTS_FF: in std_logic;
RTS_FF_in: in std_logic;
-- Checker outputs
err_state_IDLE_xbar,
err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE,
err_IDLE_Req_L,
err_Local_Req_L,
err_North_Req_N,
--err_East_Req_E,
--err_West_Req_W,
--err_South_Req_S,
err_IDLE_Req_N,
err_Local_Req_N,
--err_North_Req_E,
--err_East_Req_W,
--err_West_Req_S,
err_South_Req_L,
--err_IDLE_Req_E,
--err_Local_Req_E,
--err_North_Req_W,
--err_East_Req_S,
err_West_Req_L,
err_South_Req_N,
--err_IDLE_Req_W,
--err_Local_Req_W,
--err_North_Req_S,
err_East_Req_L,
err_West_Req_N,
--err_South_Req_E,
--err_IDLE_Req_S,
--err_Local_Req_S,
--err_North_Req_L,
err_East_Req_N,
--err_West_Req_E,
--err_South_Req_W,
err_next_state_onehot,
err_state_in_onehot,
--err_DCTS_RTS_FF_state_Grant_L,
--err_DCTS_RTS_FF_state_Grant_N,
--err_DCTS_RTS_FF_state_Grant_E,
--err_DCTS_RTS_FF_state_Grant_W,
--err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel,
err_state_east_xbar_sel,
err_state_west_xbar_sel,
err_state_south_xbar_sel : out std_logic
--err_state_local_xbar_sel : out std_logic
);
end component;
component fault_injector is
generic(DATA_WIDTH : integer := 32);
port(
data_in: in std_logic_vector (DATA_WIDTH-1 downto 0);
address: in std_logic_vector(integer(ceil(log2(real(DATA_WIDTH))))-1 downto 0);
sta_0: in std_logic;
sta_1: in std_logic;
data_out: out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end component;
component shift_register_serial_in is
generic (
REG_WIDTH: integer := 8
);
port (
clk, reset : in std_logic;
shift: in std_logic;
data_in_serial: in std_logic;
data_out_parallel: out std_logic_vector(REG_WIDTH-1 downto 0);
data_out_serial: out std_logic
);
end component;
signal FI_add_sta: std_logic_vector(?? downto 0);
begin
FI: fault_injector generic map(DATA_WIDTH => ??)
port map (data_in=> ?? , address=> FI_add_sta(?? downto 2), sta_0=> FI_add_sta(1), sta_1=> FI_add_sta(0), data_out=>??
);
SR: shift_register_serial_in generic map(REG_WIDTH => )
port map( clk=> fault_clk, reset=>reset, shift=> shift,data_in_serial=> data_in_serial,
data_out_parallel=> FI_add_sta, data_out_serial=> data_out_serial
);
-- Arbiter checkers instantiation
ARBITERCHECKERS: Arbiter_checkers port map (
Req_N => Req_N,
Req_E => Req_E,
Req_W => Req_W,
Req_S => Req_S,
Req_L => Req_L,
DCTS => DCTS,
Grant_N => Grant_N_sig,
Grant_E => Grant_E_sig,
Grant_W => Grant_W_sig,
Grant_S => Grant_S_sig,
Grant_L => Grant_L_sig,
Xbar_sel=>Xbar_sel_sig,
state => state,
state_in => state_in,
next_state_out => next_state,
RTS_FF => RTS_FF,
RTS_FF_in => RTS_FF_in,
err_state_IDLE_xbar => err_state_IDLE_xbar,
err_state_not_IDLE_xbar => err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in => err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in => err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in => err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state => err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state => err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants => err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants => err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants => err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE => err_Requests_next_state_IDLE,
err_IDLE_Req_L => err_IDLE_Req_L,
err_Local_Req_L => err_Local_Req_L,
err_North_Req_N => err_North_Req_N,
err_IDLE_Req_N => err_IDLE_Req_N,
err_Local_Req_N => err_Local_Req_N,
err_South_Req_L => err_South_Req_L,
err_West_Req_L => err_West_Req_L,
err_South_Req_N => err_South_Req_N,
err_East_Req_L => err_East_Req_L,
err_West_Req_N => err_West_Req_N,
err_East_Req_N => err_East_Req_N,
err_next_state_onehot => err_next_state_onehot,
err_state_in_onehot => err_state_in_onehot,
err_state_north_xbar_sel => err_state_north_xbar_sel,
err_state_east_xbar_sel => err_state_east_xbar_sel,
err_state_west_xbar_sel => err_state_west_xbar_sel,
err_state_south_xbar_sel => err_state_south_xbar_sel
);
-- process for updating the state of arbiter's FSM, also setting RTS based on the state (if Grant is given or not)
process(clk, reset)begin
if reset = '0' then
state<=IDLE;
RTS_FF <= '0';
elsif clk'event and clk = '1' then
-- no grant given yet, it might be that there is no request to
-- arbiter or request is there, but the next router's/NI's FIFO is full
state <= state_in;
RTS_FF <= RTS_FF_in;
end if;
end process;
-- anything below here is pure combinational
RTS <= RTS_FF;
-- Becuase of checkers we did this!
Grant_N <= Grant_N_sig;
Grant_E <= Grant_E_sig;
Grant_W <= Grant_W_sig;
Grant_S <= Grant_S_sig;
Grant_L <= Grant_L_sig;
Xbar_sel <= Xbar_sel_sig;
process(RTS_FF, DCTS, state, next_state)begin
if RTS_FF = '1' and DCTS = '0' then
state_in <= state;
else
state_in <= next_state;
end if;
end process;
process(state, RTS_FF, DCTS)begin
if state = IDLE then
RTS_FF_in <= '0';
-- if there was a grant given to one of the inputs,
-- tell the next router/NI that the output data is valid
else
if RTS_FF = '1' and DCTS = '1' then
RTS_FF_in <= '0';
else
RTS_FF_in <= '1';
end if;
end if ;
end process;
-- sets the grants using round robin
-- the order is L --> N --> E --> W --> S and then back to L
process(state, Req_N, Req_E, Req_W, Req_S, Req_L, DCTS, RTS_FF)begin
Grant_N_sig <= '0';
Grant_E_sig <= '0';
Grant_W_sig <= '0';
Grant_S_sig <= '0';
Grant_L_sig <= '0';
Xbar_sel_sig <= "00000";
case(state) is
when IDLE =>
Xbar_sel_sig <= "00000";
If Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
else
next_state <= IDLE;
end if;
when North =>
Grant_N_sig <= DCTS and RTS_FF ;
Xbar_sel_sig <= "00001";
If Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
else
next_state <= IDLE;
end if;
when East =>
Grant_E_sig <= DCTS and RTS_FF;
Xbar_sel_sig <= "00010";
If Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
else
next_state <= IDLE;
end if;
when West =>
Grant_W_sig <= DCTS and RTS_FF;
Xbar_sel_sig <= "00100";
If Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
else
next_state <= IDLE;
end if;
when South =>
Grant_S_sig <= DCTS and RTS_FF;
Xbar_sel_sig <= "01000";
If Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
else
next_state <= IDLE;
end if;
when others => -- Local
Grant_L_sig <= DCTS and RTS_FF;
Xbar_sel_sig <= "10000";
If Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
else
next_state <= IDLE;
end if;
end case ;
end process;
end;
| gpl-3.0 | 0f3969c8fea8146a0169286e1c50016c | 0.456609 | 3.678564 | false | false | false | false |
SoCdesign/EHA | RTL/Hand_Shaking/Hand_Shaking_FC/Router_32_bit_with_full_set_of_checkers_with_fault_localization.vhd | 1 | 82,867 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 5;
Rxy_rst : integer := 60;
Cx_rst : integer := 15;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
DCTS_N, DCTS_E, DCTS_w, DCTS_S, DCTS_L: in std_logic;
DRTS_N, DRTS_E, DRTS_W, DRTS_S, DRTS_L: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
RTS_N, RTS_E, RTS_W, RTS_S, RTS_L: out std_logic;
CTS_N, CTS_E, CTS_w, CTS_S, CTS_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
fault_out_N, fault_out_E, fault_out_W, fault_out_S, fault_out_L:out std_logic
);
end router;
architecture behavior of router is
COMPONENT FIFO
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
DRTS: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
CTS: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
-- Checker outputs
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_CTS_in,
err_write_en,
err_not_CTS_in,
err_not_write_en,
err_read_en_mismatch : out std_logic
);
end COMPONENT;
COMPONENT Arbiter
port ( reset: in std_logic;
clk: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules
DCTS: in std_logic; -- Getting the CTS signal from the input FIFO of the next router/NI (for hand-shaking)
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
Xbar_sel : out std_logic_vector(4 downto 0); -- select lines for XBAR
RTS: out std_logic; -- Valid output which is sent to the next router/NI to specify that the data on the output port is valid
-- Checker outputs
err_state_IDLE_xbar,
err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE,
err_IDLE_Req_L,
err_Local_Req_L,
err_North_Req_N,
err_East_Req_E,
err_West_Req_W,
err_South_Req_S,
err_IDLE_Req_N,
err_Local_Req_N,
err_North_Req_E,
err_East_Req_W,
err_West_Req_S,
err_South_Req_L,
err_IDLE_Req_E,
err_Local_Req_E,
err_North_Req_W,
err_East_Req_S,
err_West_Req_L,
err_South_Req_N,
err_IDLE_Req_W,
err_Local_Req_W,
err_North_Req_S,
err_East_Req_L,
err_West_Req_N,
err_South_Req_E,
err_IDLE_Req_S,
err_Local_Req_S,
err_North_Req_L,
err_East_Req_N,
err_West_Req_E,
err_South_Req_W,
err_next_state_onehot,
err_state_in_onehot,
err_DCTS_RTS_FF_state_Grant_L,
err_DCTS_RTS_FF_state_Grant_N,
err_DCTS_RTS_FF_state_Grant_E,
err_DCTS_RTS_FF_state_Grant_W,
err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel,
err_state_east_xbar_sel,
err_state_west_xbar_sel,
err_state_south_xbar_sel,
err_state_local_xbar_sel : out std_logic
);
end COMPONENT;
COMPONENT LBDR is
generic (
cur_addr_rst: integer := 5;
Rxy_rst: integer := 60;
Cx_rst: integer := 15;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic;
-- Checker outputs
err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in : out std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
-- Signals related to Checkers
-- LBDR Checkers signals
-- North
signal N_err_header_not_empty_Requests_in_onehot,
N_err_header_empty_Requests_FF_Requests_in,
N_err_tail_Requests_in_all_zero,
N_err_header_tail_Requests_FF_Requests_in,
N_err_dst_addr_cur_addr_N1,
N_err_dst_addr_cur_addr_not_N1,
N_err_dst_addr_cur_addr_E1,
N_err_dst_addr_cur_addr_not_E1,
N_err_dst_addr_cur_addr_W1,
N_err_dst_addr_cur_addr_not_W1,
N_err_dst_addr_cur_addr_S1,
N_err_dst_addr_cur_addr_not_S1,
N_err_dst_addr_cur_addr_not_Req_L_in,
N_err_dst_addr_cur_addr_Req_L_in,
N_err_header_not_empty_Req_N_in,
N_err_header_not_empty_Req_E_in,
N_err_header_not_empty_Req_W_in,
N_err_header_not_empty_Req_S_in : std_logic;
-- East
signal E_err_header_not_empty_Requests_in_onehot,
E_err_header_empty_Requests_FF_Requests_in,
E_err_tail_Requests_in_all_zero,
E_err_header_tail_Requests_FF_Requests_in,
E_err_dst_addr_cur_addr_N1,
E_err_dst_addr_cur_addr_not_N1,
E_err_dst_addr_cur_addr_E1,
E_err_dst_addr_cur_addr_not_E1,
E_err_dst_addr_cur_addr_W1,
E_err_dst_addr_cur_addr_not_W1,
E_err_dst_addr_cur_addr_S1,
E_err_dst_addr_cur_addr_not_S1,
E_err_dst_addr_cur_addr_not_Req_L_in,
E_err_dst_addr_cur_addr_Req_L_in,
E_err_header_not_empty_Req_N_in,
E_err_header_not_empty_Req_E_in,
E_err_header_not_empty_Req_W_in,
E_err_header_not_empty_Req_S_in : std_logic;
-- West
signal W_err_header_not_empty_Requests_in_onehot,
W_err_header_empty_Requests_FF_Requests_in,
W_err_tail_Requests_in_all_zero,
W_err_header_tail_Requests_FF_Requests_in,
W_err_dst_addr_cur_addr_N1,
W_err_dst_addr_cur_addr_not_N1,
W_err_dst_addr_cur_addr_E1,
W_err_dst_addr_cur_addr_not_E1,
W_err_dst_addr_cur_addr_W1,
W_err_dst_addr_cur_addr_not_W1,
W_err_dst_addr_cur_addr_S1,
W_err_dst_addr_cur_addr_not_S1,
W_err_dst_addr_cur_addr_not_Req_L_in,
W_err_dst_addr_cur_addr_Req_L_in,
W_err_header_not_empty_Req_N_in,
W_err_header_not_empty_Req_E_in,
W_err_header_not_empty_Req_W_in,
W_err_header_not_empty_Req_S_in : std_logic;
-- South
signal S_err_header_not_empty_Requests_in_onehot,
S_err_header_empty_Requests_FF_Requests_in,
S_err_tail_Requests_in_all_zero,
S_err_header_tail_Requests_FF_Requests_in,
S_err_dst_addr_cur_addr_N1,
S_err_dst_addr_cur_addr_not_N1,
S_err_dst_addr_cur_addr_E1,
S_err_dst_addr_cur_addr_not_E1,
S_err_dst_addr_cur_addr_W1,
S_err_dst_addr_cur_addr_not_W1,
S_err_dst_addr_cur_addr_S1,
S_err_dst_addr_cur_addr_not_S1,
S_err_dst_addr_cur_addr_not_Req_L_in,
S_err_dst_addr_cur_addr_Req_L_in,
S_err_header_not_empty_Req_N_in,
S_err_header_not_empty_Req_E_in,
S_err_header_not_empty_Req_W_in,
S_err_header_not_empty_Req_S_in : std_logic;
-- Local
signal L_err_header_not_empty_Requests_in_onehot,
L_err_header_empty_Requests_FF_Requests_in,
L_err_tail_Requests_in_all_zero,
L_err_header_tail_Requests_FF_Requests_in,
L_err_dst_addr_cur_addr_N1,
L_err_dst_addr_cur_addr_not_N1,
L_err_dst_addr_cur_addr_E1,
L_err_dst_addr_cur_addr_not_E1,
L_err_dst_addr_cur_addr_W1,
L_err_dst_addr_cur_addr_not_W1,
L_err_dst_addr_cur_addr_S1,
L_err_dst_addr_cur_addr_not_S1,
L_err_dst_addr_cur_addr_not_Req_L_in,
L_err_dst_addr_cur_addr_Req_L_in,
L_err_header_not_empty_Req_N_in,
L_err_header_not_empty_Req_E_in,
L_err_header_not_empty_Req_W_in,
L_err_header_not_empty_Req_S_in : std_logic;
-- Arbiter Checkers signals
-- North
signal N_err_state_IDLE_xbar,
N_err_state_not_IDLE_xbar,
N_err_state_IDLE_RTS_FF_in,
N_err_state_not_IDLE_RTS_FF_RTS_FF_in,
N_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
N_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
N_err_RTS_FF_not_DCTS_state_state_in,
N_err_not_RTS_FF_state_in_next_state,
N_err_RTS_FF_DCTS_state_in_next_state,
N_err_not_DCTS_Grants,
N_err_DCTS_not_RTS_FF_Grants,
N_err_DCTS_RTS_FF_IDLE_Grants,
N_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
N_err_Requests_next_state_IDLE,
N_err_IDLE_Req_L,
N_err_Local_Req_L,
N_err_North_Req_N,
N_err_East_Req_E,
N_err_West_Req_W,
N_err_South_Req_S,
N_err_IDLE_Req_N,
N_err_Local_Req_N,
N_err_North_Req_E,
N_err_East_Req_W,
N_err_West_Req_S,
N_err_South_Req_L,
N_err_IDLE_Req_E,
N_err_Local_Req_E,
N_err_North_Req_W,
N_err_East_Req_S,
N_err_West_Req_L,
N_err_South_Req_N,
N_err_IDLE_Req_W,
N_err_Local_Req_W,
N_err_North_Req_S,
N_err_East_Req_L,
N_err_West_Req_N,
N_err_South_Req_E,
N_err_IDLE_Req_S,
N_err_Local_Req_S,
N_err_North_Req_L,
N_err_East_Req_N,
N_err_West_Req_E,
N_err_South_Req_W,
N_err_next_state_onehot,
N_err_state_in_onehot,
N_err_DCTS_RTS_FF_state_Grant_L,
N_err_DCTS_RTS_FF_state_Grant_N,
N_err_DCTS_RTS_FF_state_Grant_E,
N_err_DCTS_RTS_FF_state_Grant_W,
N_err_DCTS_RTS_FF_state_Grant_S,
N_err_state_north_xbar_sel,
N_err_state_east_xbar_sel,
N_err_state_west_xbar_sel,
N_err_state_south_xbar_sel,
N_err_state_local_xbar_sel: std_logic;
-- East
signal E_err_state_IDLE_xbar,
E_err_state_not_IDLE_xbar,
E_err_state_IDLE_RTS_FF_in,
E_err_state_not_IDLE_RTS_FF_RTS_FF_in,
E_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
E_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
E_err_RTS_FF_not_DCTS_state_state_in,
E_err_not_RTS_FF_state_in_next_state,
E_err_RTS_FF_DCTS_state_in_next_state,
E_err_not_DCTS_Grants,
E_err_DCTS_not_RTS_FF_Grants,
E_err_DCTS_RTS_FF_IDLE_Grants,
E_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
E_err_Requests_next_state_IDLE,
E_err_IDLE_Req_L,
E_err_Local_Req_L,
E_err_North_Req_N,
E_err_East_Req_E,
E_err_West_Req_W,
E_err_South_Req_S,
E_err_IDLE_Req_N,
E_err_Local_Req_N,
E_err_North_Req_E,
E_err_East_Req_W,
E_err_West_Req_S,
E_err_South_Req_L,
E_err_IDLE_Req_E,
E_err_Local_Req_E,
E_err_North_Req_W,
E_err_East_Req_S,
E_err_West_Req_L,
E_err_South_Req_N,
E_err_IDLE_Req_W,
E_err_Local_Req_W,
E_err_North_Req_S,
E_err_East_Req_L,
E_err_West_Req_N,
E_err_South_Req_E,
E_err_IDLE_Req_S,
E_err_Local_Req_S,
E_err_North_Req_L,
E_err_East_Req_N,
E_err_West_Req_E,
E_err_South_Req_W,
E_err_next_state_onehot,
E_err_state_in_onehot,
E_err_DCTS_RTS_FF_state_Grant_L,
E_err_DCTS_RTS_FF_state_Grant_N,
E_err_DCTS_RTS_FF_state_Grant_E,
E_err_DCTS_RTS_FF_state_Grant_W,
E_err_DCTS_RTS_FF_state_Grant_S,
E_err_state_north_xbar_sel,
E_err_state_east_xbar_sel,
E_err_state_west_xbar_sel,
E_err_state_south_xbar_sel,
E_err_state_local_xbar_sel: std_logic;
-- West
signal W_err_state_IDLE_xbar,
W_err_state_not_IDLE_xbar,
W_err_state_IDLE_RTS_FF_in,
W_err_state_not_IDLE_RTS_FF_RTS_FF_in,
W_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
W_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
W_err_RTS_FF_not_DCTS_state_state_in,
W_err_not_RTS_FF_state_in_next_state,
W_err_RTS_FF_DCTS_state_in_next_state,
W_err_not_DCTS_Grants,
W_err_DCTS_not_RTS_FF_Grants,
W_err_DCTS_RTS_FF_IDLE_Grants,
W_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
W_err_Requests_next_state_IDLE,
W_err_IDLE_Req_L,
W_err_Local_Req_L,
W_err_North_Req_N,
W_err_East_Req_E,
W_err_West_Req_W,
W_err_South_Req_S,
W_err_IDLE_Req_N,
W_err_Local_Req_N,
W_err_North_Req_E,
W_err_East_Req_W,
W_err_West_Req_S,
W_err_South_Req_L,
W_err_IDLE_Req_E,
W_err_Local_Req_E,
W_err_North_Req_W,
W_err_East_Req_S,
W_err_West_Req_L,
W_err_South_Req_N,
W_err_IDLE_Req_W,
W_err_Local_Req_W,
W_err_North_Req_S,
W_err_East_Req_L,
W_err_West_Req_N,
W_err_South_Req_E,
W_err_IDLE_Req_S,
W_err_Local_Req_S,
W_err_North_Req_L,
W_err_East_Req_N,
W_err_West_Req_E,
W_err_South_Req_W,
W_err_next_state_onehot,
W_err_state_in_onehot,
W_err_DCTS_RTS_FF_state_Grant_L,
W_err_DCTS_RTS_FF_state_Grant_N,
W_err_DCTS_RTS_FF_state_Grant_E,
W_err_DCTS_RTS_FF_state_Grant_W,
W_err_DCTS_RTS_FF_state_Grant_S,
W_err_state_north_xbar_sel,
W_err_state_east_xbar_sel,
W_err_state_west_xbar_sel,
W_err_state_south_xbar_sel,
W_err_state_local_xbar_sel: std_logic;
-- South
signal S_err_state_IDLE_xbar,
S_err_state_not_IDLE_xbar,
S_err_state_IDLE_RTS_FF_in,
S_err_state_not_IDLE_RTS_FF_RTS_FF_in,
S_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
S_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
S_err_RTS_FF_not_DCTS_state_state_in,
S_err_not_RTS_FF_state_in_next_state,
S_err_RTS_FF_DCTS_state_in_next_state,
S_err_not_DCTS_Grants,
S_err_DCTS_not_RTS_FF_Grants,
S_err_DCTS_RTS_FF_IDLE_Grants,
S_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
S_err_Requests_next_state_IDLE,
S_err_IDLE_Req_L,
S_err_Local_Req_L,
S_err_North_Req_N,
S_err_East_Req_E,
S_err_West_Req_W,
S_err_South_Req_S,
S_err_IDLE_Req_N,
S_err_Local_Req_N,
S_err_North_Req_E,
S_err_East_Req_W,
S_err_West_Req_S,
S_err_South_Req_L,
S_err_IDLE_Req_E,
S_err_Local_Req_E,
S_err_North_Req_W,
S_err_East_Req_S,
S_err_West_Req_L,
S_err_South_Req_N,
S_err_IDLE_Req_W,
S_err_Local_Req_W,
S_err_North_Req_S,
S_err_East_Req_L,
S_err_West_Req_N,
S_err_South_Req_E,
S_err_IDLE_Req_S,
S_err_Local_Req_S,
S_err_North_Req_L,
S_err_East_Req_N,
S_err_West_Req_E,
S_err_South_Req_W,
S_err_next_state_onehot,
S_err_state_in_onehot,
S_err_DCTS_RTS_FF_state_Grant_L,
S_err_DCTS_RTS_FF_state_Grant_N,
S_err_DCTS_RTS_FF_state_Grant_E,
S_err_DCTS_RTS_FF_state_Grant_W,
S_err_DCTS_RTS_FF_state_Grant_S,
S_err_state_north_xbar_sel,
S_err_state_east_xbar_sel,
S_err_state_west_xbar_sel,
S_err_state_south_xbar_sel,
S_err_state_local_xbar_sel: std_logic;
-- Local
signal L_err_state_IDLE_xbar,
L_err_state_not_IDLE_xbar,
L_err_state_IDLE_RTS_FF_in,
L_err_state_not_IDLE_RTS_FF_RTS_FF_in,
L_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
L_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
L_err_RTS_FF_not_DCTS_state_state_in,
L_err_not_RTS_FF_state_in_next_state,
L_err_RTS_FF_DCTS_state_in_next_state,
L_err_not_DCTS_Grants,
L_err_DCTS_not_RTS_FF_Grants,
L_err_DCTS_RTS_FF_IDLE_Grants,
L_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
L_err_Requests_next_state_IDLE,
L_err_IDLE_Req_L,
L_err_Local_Req_L,
L_err_North_Req_N,
L_err_East_Req_E,
L_err_West_Req_W,
L_err_South_Req_S,
L_err_IDLE_Req_N,
L_err_Local_Req_N,
L_err_North_Req_E,
L_err_East_Req_W,
L_err_West_Req_S,
L_err_South_Req_L,
L_err_IDLE_Req_E,
L_err_Local_Req_E,
L_err_North_Req_W,
L_err_East_Req_S,
L_err_West_Req_L,
L_err_South_Req_N,
L_err_IDLE_Req_W,
L_err_Local_Req_W,
L_err_North_Req_S,
L_err_East_Req_L,
L_err_West_Req_N,
L_err_South_Req_E,
L_err_IDLE_Req_S,
L_err_Local_Req_S,
L_err_North_Req_L,
L_err_East_Req_N,
L_err_West_Req_E,
L_err_South_Req_W,
L_err_next_state_onehot,
L_err_state_in_onehot,
L_err_DCTS_RTS_FF_state_Grant_L,
L_err_DCTS_RTS_FF_state_Grant_N,
L_err_DCTS_RTS_FF_state_Grant_E,
L_err_DCTS_RTS_FF_state_Grant_W,
L_err_DCTS_RTS_FF_state_Grant_S,
L_err_state_north_xbar_sel,
L_err_state_east_xbar_sel,
L_err_state_west_xbar_sel,
L_err_state_south_xbar_sel,
L_err_state_local_xbar_sel: std_logic;
-- FIFO Control Part Checkers signals
-- North
signal N_err_write_en_write_pointer,
N_err_not_write_en_write_pointer,
N_err_read_pointer_write_pointer_not_empty,
N_err_read_pointer_write_pointer_empty,
N_err_read_pointer_write_pointer_not_full,
N_err_read_pointer_write_pointer_full,
N_err_read_pointer_increment,
N_err_read_pointer_not_increment,
N_err_CTS_in,
N_err_write_en,
N_err_not_CTS_in,
N_err_not_write_en,
N_err_read_en_mismatch : std_logic;
-- East
signal E_err_write_en_write_pointer,
E_err_not_write_en_write_pointer,
E_err_read_pointer_write_pointer_not_empty,
E_err_read_pointer_write_pointer_empty,
E_err_read_pointer_write_pointer_not_full,
E_err_read_pointer_write_pointer_full,
E_err_read_pointer_increment,
E_err_read_pointer_not_increment,
E_err_CTS_in,
E_err_write_en,
E_err_not_CTS_in,
E_err_not_write_en,
E_err_read_en_mismatch : std_logic;
-- West
signal W_err_write_en_write_pointer,
W_err_not_write_en_write_pointer,
W_err_read_pointer_write_pointer_not_empty,
W_err_read_pointer_write_pointer_empty,
W_err_read_pointer_write_pointer_not_full,
W_err_read_pointer_write_pointer_full,
W_err_read_pointer_increment,
W_err_read_pointer_not_increment,
W_err_CTS_in,
W_err_write_en,
W_err_not_CTS_in,
W_err_not_write_en,
W_err_read_en_mismatch : std_logic;
-- South
signal S_err_write_en_write_pointer,
S_err_not_write_en_write_pointer,
S_err_read_pointer_write_pointer_not_empty,
S_err_read_pointer_write_pointer_empty,
S_err_read_pointer_write_pointer_not_full,
S_err_read_pointer_write_pointer_full,
S_err_read_pointer_increment,
S_err_read_pointer_not_increment,
S_err_CTS_in,
S_err_write_en,
S_err_not_CTS_in,
S_err_not_write_en,
S_err_read_en_mismatch : std_logic;
-- Local
signal L_err_write_en_write_pointer,
L_err_not_write_en_write_pointer,
L_err_read_pointer_write_pointer_not_empty,
L_err_read_pointer_write_pointer_empty,
L_err_read_pointer_write_pointer_not_full,
L_err_read_pointer_write_pointer_full,
L_err_read_pointer_increment,
L_err_read_pointer_not_increment,
L_err_CTS_in,
L_err_write_en,
L_err_not_CTS_in,
L_err_not_write_en,
L_err_read_en_mismatch : std_logic;
-- Fault localization related signals
signal N_E_turn, N_W_turn, S_E_turn, S_W_turn, E_N_turn, E_S_turn, W_N_turn, W_S_turn : std_logic;
signal N_S_path, S_N_path, E_W_path, W_E_path : std_logic;
signal N_FIFO_handshaking_error, E_FIFO_handshaking_error, W_FIFO_handshaking_error, S_FIFO_handshaking_error, L_FIFO_handshaking_error : std_logic;
signal N_Arbiter_handshaking_error, E_Arbiter_handshaking_error, W_Arbiter_handshaking_error, S_Arbiter_handshaking_error, L_Arbiter_handshaking_error : std_logic;
begin
--
------------------------------------------------------------------------------------------------------------------------------
-- block diagram of one channel
--
-- .____________grant_________
-- | ▲
-- | _______ __|_______
-- | | | | |
-- | | LBDR |---req--->| Arbiter | <--handshake-->
-- | |_______| |__________| signals
-- | ▲ |
-- __▼___ | flit ___▼__
-- RX ----->| | | type | |
-- <-handshake->| FIFO |---o------------->| |-----> TX
-- signals |______| ------>| |
-- ------>| XBAR |
-- ------>| |
-- ------>| |
-- |______|
--
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the FIFOs
FIFO_N: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_N, DRTS => DRTS_N,
read_en_N => '0', read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
CTS => CTS_N, empty_out => empty_N, Data_out => FIFO_D_out_N,
err_write_en_write_pointer => N_err_write_en_write_pointer,
err_not_write_en_write_pointer => N_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => N_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => N_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => N_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => N_err_read_pointer_write_pointer_full,
err_read_pointer_increment => N_err_read_pointer_increment,
err_read_pointer_not_increment => N_err_read_pointer_not_increment,
err_CTS_in => N_err_CTS_in,
err_write_en => N_err_write_en,
err_not_CTS_in => N_err_not_CTS_in,
err_not_write_en => N_err_not_write_en,
err_read_en_mismatch => N_err_read_en_mismatch
);
FIFO_E: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_E, DRTS => DRTS_E,
read_en_N => Grant_NE, read_en_E =>'0', read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
CTS => CTS_E, empty_out => empty_E, Data_out => FIFO_D_out_E,
err_write_en_write_pointer => E_err_write_en_write_pointer,
err_not_write_en_write_pointer => E_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => E_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => E_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => E_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => E_err_read_pointer_write_pointer_full,
err_read_pointer_increment => E_err_read_pointer_increment,
err_read_pointer_not_increment => E_err_read_pointer_not_increment,
err_CTS_in => E_err_CTS_in,
err_write_en => E_err_write_en,
err_not_CTS_in => E_err_not_CTS_in,
err_not_write_en => E_err_not_write_en,
err_read_en_mismatch => E_err_read_en_mismatch
);
FIFO_W: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_W, DRTS => DRTS_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>'0', read_en_S =>Grant_SW, read_en_L =>Grant_LW,
CTS => CTS_W, empty_out => empty_W, Data_out => FIFO_D_out_W,
err_write_en_write_pointer => W_err_write_en_write_pointer,
err_not_write_en_write_pointer => W_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => W_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => W_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => W_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => W_err_read_pointer_write_pointer_full,
err_read_pointer_increment => W_err_read_pointer_increment,
err_read_pointer_not_increment => W_err_read_pointer_not_increment,
err_CTS_in => W_err_CTS_in,
err_write_en => W_err_write_en,
err_not_CTS_in => W_err_not_CTS_in,
err_not_write_en => W_err_not_write_en,
err_read_en_mismatch => W_err_read_en_mismatch
);
FIFO_S: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_S, DRTS => DRTS_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>'0', read_en_L =>Grant_LS,
CTS => CTS_S, empty_out => empty_S, Data_out => FIFO_D_out_S,
err_write_en_write_pointer => S_err_write_en_write_pointer,
err_not_write_en_write_pointer => S_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => S_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => S_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => S_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => S_err_read_pointer_write_pointer_full,
err_read_pointer_increment => S_err_read_pointer_increment,
err_read_pointer_not_increment => S_err_read_pointer_not_increment,
err_CTS_in => S_err_CTS_in,
err_write_en => S_err_write_en,
err_not_CTS_in => S_err_not_CTS_in,
err_not_write_en => S_err_not_write_en,
err_read_en_mismatch => S_err_read_en_mismatch
);
FIFO_L: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_L, DRTS => DRTS_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>'0',
CTS => CTS_L, empty_out => empty_L, Data_out => FIFO_D_out_L,
err_write_en_write_pointer => L_err_write_en_write_pointer,
err_not_write_en_write_pointer => L_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => L_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => L_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => L_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => L_err_read_pointer_write_pointer_full,
err_read_pointer_increment => L_err_read_pointer_increment,
err_read_pointer_not_increment => L_err_read_pointer_not_increment,
err_CTS_in => L_err_CTS_in,
err_write_en => L_err_write_en,
err_not_CTS_in => L_err_not_CTS_in,
err_not_write_en => L_err_not_write_en,
err_read_en_mismatch => L_err_read_en_mismatch
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the LBDRs
LBDR_N: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N, flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL,
err_header_not_empty_Requests_in_onehot => N_err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in => N_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => N_err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in => N_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => N_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => N_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => N_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => N_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => N_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => N_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => N_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => N_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => N_err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => N_err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => N_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => N_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => N_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => N_err_header_not_empty_Req_S_in
);
LBDR_E: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E, flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL,
err_header_not_empty_Requests_in_onehot => E_err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in => E_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => E_err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in => E_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => E_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => E_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => E_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => E_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => E_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => E_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => E_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => E_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => E_err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => E_err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => E_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => E_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => E_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => E_err_header_not_empty_Req_S_in
);
LBDR_W: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W, flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL,
err_header_not_empty_Requests_in_onehot => W_err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in => W_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => W_err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in => W_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => W_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => W_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => W_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => W_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => W_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => W_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => W_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => W_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => W_err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => W_err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => W_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => W_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => W_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => W_err_header_not_empty_Req_S_in
);
LBDR_S: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S, flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL,
err_header_not_empty_Requests_in_onehot => S_err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in => S_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => S_err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in => S_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => S_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => S_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => S_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => S_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => S_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => S_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => S_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => S_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => S_err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => S_err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => S_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => S_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => S_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => S_err_header_not_empty_Req_S_in
);
LBDR_L: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L, flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL,
err_header_not_empty_Requests_in_onehot => L_err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in => L_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => L_err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in => L_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => L_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => L_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => L_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => L_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => L_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => L_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => L_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => L_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => L_err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => L_err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => L_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => L_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => L_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => L_err_header_not_empty_Req_S_in
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Arbiters
Arbiter_N: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => '0' , Req_E => Req_EN, Req_W => Req_WN, Req_S => Req_SN, Req_L => Req_LN,
DCTS => DCTS_N, Grant_N => Grant_NN, Grant_E => Grant_NE, Grant_W => Grant_NW, Grant_S => Grant_NS, Grant_L => Grant_NL,
Xbar_sel => Xbar_sel_N,
RTS => RTS_N,
err_state_IDLE_xbar => N_err_state_IDLE_xbar,
err_state_not_IDLE_xbar => N_err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in => N_err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in => N_err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => N_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => N_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in => N_err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state => N_err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state => N_err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants => N_err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants => N_err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants => N_err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => N_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE => N_err_Requests_next_state_IDLE,
err_IDLE_Req_L => N_err_IDLE_Req_L,
err_Local_Req_L => N_err_Local_Req_L,
err_North_Req_N => N_err_North_Req_N,
err_East_Req_E => N_err_East_Req_E,
err_West_Req_W => N_err_West_Req_W,
err_South_Req_S => N_err_South_Req_S,
err_IDLE_Req_N => N_err_IDLE_Req_N,
err_Local_Req_N => N_err_Local_Req_N,
err_North_Req_E => N_err_North_Req_E,
err_East_Req_W => N_err_East_Req_W,
err_West_Req_S => N_err_West_Req_S,
err_South_Req_L => N_err_South_Req_L,
err_IDLE_Req_E => N_err_IDLE_Req_E,
err_Local_Req_E => N_err_Local_Req_E,
err_North_Req_W => N_err_North_Req_W,
err_East_Req_S => N_err_East_Req_S,
err_West_Req_L => N_err_West_Req_L,
err_South_Req_N => N_err_South_Req_N,
err_IDLE_Req_W => N_err_IDLE_Req_W,
err_Local_Req_W => N_err_Local_Req_W,
err_North_Req_S => N_err_North_Req_S,
err_East_Req_L => N_err_East_Req_L,
err_West_Req_N => N_err_West_Req_N,
err_South_Req_E => N_err_South_Req_E,
err_IDLE_Req_S => N_err_IDLE_Req_S,
err_Local_Req_S => N_err_Local_Req_S,
err_North_Req_L => N_err_North_Req_L,
err_East_Req_N => N_err_East_Req_N,
err_West_Req_E => N_err_West_Req_E,
err_South_Req_W => N_err_South_Req_W,
err_next_state_onehot => N_err_next_state_onehot,
err_state_in_onehot => N_err_state_in_onehot,
err_DCTS_RTS_FF_state_Grant_L => N_err_DCTS_RTS_FF_state_Grant_L,
err_DCTS_RTS_FF_state_Grant_N => N_err_DCTS_RTS_FF_state_Grant_N,
err_DCTS_RTS_FF_state_Grant_E => N_err_DCTS_RTS_FF_state_Grant_E,
err_DCTS_RTS_FF_state_Grant_W => N_err_DCTS_RTS_FF_state_Grant_W,
err_DCTS_RTS_FF_state_Grant_S => N_err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel => N_err_state_north_xbar_sel,
err_state_east_xbar_sel => N_err_state_east_xbar_sel,
err_state_west_xbar_sel => N_err_state_west_xbar_sel,
err_state_south_xbar_sel => N_err_state_south_xbar_sel,
err_state_local_xbar_sel => N_err_state_local_xbar_sel
);
Arbiter_E: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NE , Req_E => '0', Req_W => Req_WE, Req_S => Req_SE, Req_L => Req_LE,
DCTS => DCTS_E, Grant_N => Grant_EN, Grant_E => Grant_EE, Grant_W => Grant_EW, Grant_S => Grant_ES, Grant_L => Grant_EL,
Xbar_sel => Xbar_sel_E,
RTS => RTS_E,
err_state_IDLE_xbar => E_err_state_IDLE_xbar,
err_state_not_IDLE_xbar => E_err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in => E_err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in => E_err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => E_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => E_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in => E_err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state => E_err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state => E_err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants => E_err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants => E_err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants => E_err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => E_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE => E_err_Requests_next_state_IDLE,
err_IDLE_Req_L => E_err_IDLE_Req_L,
err_Local_Req_L => E_err_Local_Req_L,
err_North_Req_N => E_err_North_Req_N,
err_East_Req_E => E_err_East_Req_E,
err_West_Req_W => E_err_West_Req_W,
err_South_Req_S => E_err_South_Req_S,
err_IDLE_Req_N => E_err_IDLE_Req_N,
err_Local_Req_N => E_err_Local_Req_N,
err_North_Req_E => E_err_North_Req_E,
err_East_Req_W => E_err_East_Req_W,
err_West_Req_S => E_err_West_Req_S,
err_South_Req_L => E_err_South_Req_L,
err_IDLE_Req_E => E_err_IDLE_Req_E,
err_Local_Req_E => E_err_Local_Req_E,
err_North_Req_W => E_err_North_Req_W,
err_East_Req_S => E_err_East_Req_S,
err_West_Req_L => E_err_West_Req_L,
err_South_Req_N => E_err_South_Req_N,
err_IDLE_Req_W => E_err_IDLE_Req_W,
err_Local_Req_W => E_err_Local_Req_W,
err_North_Req_S => E_err_North_Req_S,
err_East_Req_L => E_err_East_Req_L,
err_West_Req_N => E_err_West_Req_N,
err_South_Req_E => E_err_South_Req_E,
err_IDLE_Req_S => E_err_IDLE_Req_S,
err_Local_Req_S => E_err_Local_Req_S,
err_North_Req_L => E_err_North_Req_L,
err_East_Req_N => E_err_East_Req_N,
err_West_Req_E => E_err_West_Req_E,
err_South_Req_W => E_err_South_Req_W,
err_next_state_onehot => E_err_next_state_onehot,
err_state_in_onehot => E_err_state_in_onehot,
err_DCTS_RTS_FF_state_Grant_L => E_err_DCTS_RTS_FF_state_Grant_L,
err_DCTS_RTS_FF_state_Grant_N => E_err_DCTS_RTS_FF_state_Grant_N,
err_DCTS_RTS_FF_state_Grant_E => E_err_DCTS_RTS_FF_state_Grant_E,
err_DCTS_RTS_FF_state_Grant_W => E_err_DCTS_RTS_FF_state_Grant_W,
err_DCTS_RTS_FF_state_Grant_S => E_err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel => E_err_state_north_xbar_sel,
err_state_east_xbar_sel => E_err_state_east_xbar_sel,
err_state_west_xbar_sel => E_err_state_west_xbar_sel,
err_state_south_xbar_sel => E_err_state_south_xbar_sel,
err_state_local_xbar_sel => E_err_state_local_xbar_sel
);
Arbiter_W: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NW , Req_E => Req_EW, Req_W => '0', Req_S => Req_SW, Req_L => Req_LW,
DCTS => DCTS_W, Grant_N => Grant_WN, Grant_E => Grant_WE, Grant_W => Grant_WW, Grant_S => Grant_WS, Grant_L => Grant_WL,
Xbar_sel => Xbar_sel_W,
RTS => RTS_W,
err_state_IDLE_xbar => W_err_state_IDLE_xbar,
err_state_not_IDLE_xbar => W_err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in => W_err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in => W_err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => W_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => W_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in => W_err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state => W_err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state => W_err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants => W_err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants => W_err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants => W_err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => W_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE => W_err_Requests_next_state_IDLE,
err_IDLE_Req_L => W_err_IDLE_Req_L,
err_Local_Req_L => W_err_Local_Req_L,
err_North_Req_N => W_err_North_Req_N,
err_East_Req_E => W_err_East_Req_E,
err_West_Req_W => W_err_West_Req_W,
err_South_Req_S => W_err_South_Req_S,
err_IDLE_Req_N => W_err_IDLE_Req_N,
err_Local_Req_N => W_err_Local_Req_N,
err_North_Req_E => W_err_North_Req_E,
err_East_Req_W => W_err_East_Req_W,
err_West_Req_S => W_err_West_Req_S,
err_South_Req_L => W_err_South_Req_L,
err_IDLE_Req_E => W_err_IDLE_Req_E,
err_Local_Req_E => W_err_Local_Req_E,
err_North_Req_W => W_err_North_Req_W,
err_East_Req_S => W_err_East_Req_S,
err_West_Req_L => W_err_West_Req_L,
err_South_Req_N => W_err_South_Req_N,
err_IDLE_Req_W => W_err_IDLE_Req_W,
err_Local_Req_W => W_err_Local_Req_W,
err_North_Req_S => W_err_North_Req_S,
err_East_Req_L => W_err_East_Req_L,
err_West_Req_N => W_err_West_Req_N,
err_South_Req_E => W_err_South_Req_E,
err_IDLE_Req_S => W_err_IDLE_Req_S,
err_Local_Req_S => W_err_Local_Req_S,
err_North_Req_L => W_err_North_Req_L,
err_East_Req_N => W_err_East_Req_N,
err_West_Req_E => W_err_West_Req_E,
err_South_Req_W => W_err_South_Req_W,
err_next_state_onehot => W_err_next_state_onehot,
err_state_in_onehot => W_err_state_in_onehot,
err_DCTS_RTS_FF_state_Grant_L => W_err_DCTS_RTS_FF_state_Grant_L,
err_DCTS_RTS_FF_state_Grant_N => W_err_DCTS_RTS_FF_state_Grant_N,
err_DCTS_RTS_FF_state_Grant_E => W_err_DCTS_RTS_FF_state_Grant_E,
err_DCTS_RTS_FF_state_Grant_W => W_err_DCTS_RTS_FF_state_Grant_W,
err_DCTS_RTS_FF_state_Grant_S => W_err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel => W_err_state_north_xbar_sel,
err_state_east_xbar_sel => W_err_state_east_xbar_sel,
err_state_west_xbar_sel => W_err_state_west_xbar_sel,
err_state_south_xbar_sel => W_err_state_south_xbar_sel,
err_state_local_xbar_sel => W_err_state_local_xbar_sel
);
Arbiter_S: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NS , Req_E => Req_ES, Req_W => Req_WS, Req_S => '0', Req_L => Req_LS,
DCTS => DCTS_S, Grant_N => Grant_SN, Grant_E => Grant_SE, Grant_W => Grant_SW, Grant_S => Grant_SS, Grant_L => Grant_SL,
Xbar_sel => Xbar_sel_S,
RTS => RTS_S,
err_state_IDLE_xbar => S_err_state_IDLE_xbar,
err_state_not_IDLE_xbar => S_err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in => S_err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in => S_err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => S_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => S_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in => S_err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state => S_err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state => S_err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants => S_err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants => S_err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants => S_err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => S_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE => S_err_Requests_next_state_IDLE,
err_IDLE_Req_L => S_err_IDLE_Req_L,
err_Local_Req_L => S_err_Local_Req_L,
err_North_Req_N => S_err_North_Req_N,
err_East_Req_E => S_err_East_Req_E,
err_West_Req_W => S_err_West_Req_W,
err_South_Req_S => S_err_South_Req_S,
err_IDLE_Req_N => S_err_IDLE_Req_N,
err_Local_Req_N => S_err_Local_Req_N,
err_North_Req_E => S_err_North_Req_E,
err_East_Req_W => S_err_East_Req_W,
err_West_Req_S => S_err_West_Req_S,
err_South_Req_L => S_err_South_Req_L,
err_IDLE_Req_E => S_err_IDLE_Req_E,
err_Local_Req_E => S_err_Local_Req_E,
err_North_Req_W => S_err_North_Req_W,
err_East_Req_S => S_err_East_Req_S,
err_West_Req_L => S_err_West_Req_L,
err_South_Req_N => S_err_South_Req_N,
err_IDLE_Req_W => S_err_IDLE_Req_W,
err_Local_Req_W => S_err_Local_Req_W,
err_North_Req_S => S_err_North_Req_S,
err_East_Req_L => S_err_East_Req_L,
err_West_Req_N => S_err_West_Req_N,
err_South_Req_E => S_err_South_Req_E,
err_IDLE_Req_S => S_err_IDLE_Req_S,
err_Local_Req_S => S_err_Local_Req_S,
err_North_Req_L => S_err_North_Req_L,
err_East_Req_N => S_err_East_Req_N,
err_West_Req_E => S_err_West_Req_E,
err_South_Req_W => S_err_South_Req_W,
err_next_state_onehot => S_err_next_state_onehot,
err_state_in_onehot => S_err_state_in_onehot,
err_DCTS_RTS_FF_state_Grant_L => S_err_DCTS_RTS_FF_state_Grant_L,
err_DCTS_RTS_FF_state_Grant_N => S_err_DCTS_RTS_FF_state_Grant_N,
err_DCTS_RTS_FF_state_Grant_E => S_err_DCTS_RTS_FF_state_Grant_E,
err_DCTS_RTS_FF_state_Grant_W => S_err_DCTS_RTS_FF_state_Grant_W,
err_DCTS_RTS_FF_state_Grant_S => S_err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel => S_err_state_north_xbar_sel,
err_state_east_xbar_sel => S_err_state_east_xbar_sel,
err_state_west_xbar_sel => S_err_state_west_xbar_sel,
err_state_south_xbar_sel => S_err_state_south_xbar_sel,
err_state_local_xbar_sel => S_err_state_local_xbar_sel
);
Arbiter_L: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NL , Req_E => Req_EL, Req_W => Req_WL, Req_S => Req_SL, Req_L => '0',
DCTS => DCTS_L, Grant_N => Grant_LN, Grant_E => Grant_LE, Grant_W => Grant_LW, Grant_S => Grant_LS, Grant_L => Grant_LL,
Xbar_sel => Xbar_sel_L,
RTS => RTS_L,
err_state_IDLE_xbar => L_err_state_IDLE_xbar,
err_state_not_IDLE_xbar => L_err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in => L_err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in => L_err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => L_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => L_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in => L_err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state => L_err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state => L_err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants => L_err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants => L_err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants => L_err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => L_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE => L_err_Requests_next_state_IDLE,
err_IDLE_Req_L => L_err_IDLE_Req_L,
err_Local_Req_L => L_err_Local_Req_L,
err_North_Req_N => L_err_North_Req_N,
err_East_Req_E => L_err_East_Req_E,
err_West_Req_W => L_err_West_Req_W,
err_South_Req_S => L_err_South_Req_S,
err_IDLE_Req_N => L_err_IDLE_Req_N,
err_Local_Req_N => L_err_Local_Req_N,
err_North_Req_E => L_err_North_Req_E,
err_East_Req_W => L_err_East_Req_W,
err_West_Req_S => L_err_West_Req_S,
err_South_Req_L => L_err_South_Req_L,
err_IDLE_Req_E => L_err_IDLE_Req_E,
err_Local_Req_E => L_err_Local_Req_E,
err_North_Req_W => L_err_North_Req_W,
err_East_Req_S => L_err_East_Req_S,
err_West_Req_L => L_err_West_Req_L,
err_South_Req_N => L_err_South_Req_N,
err_IDLE_Req_W => L_err_IDLE_Req_W,
err_Local_Req_W => L_err_Local_Req_W,
err_North_Req_S => L_err_North_Req_S,
err_East_Req_L => L_err_East_Req_L,
err_West_Req_N => L_err_West_Req_N,
err_South_Req_E => L_err_South_Req_E,
err_IDLE_Req_S => L_err_IDLE_Req_S,
err_Local_Req_S => L_err_Local_Req_S,
err_North_Req_L => L_err_North_Req_L,
err_East_Req_N => L_err_East_Req_N,
err_West_Req_E => L_err_West_Req_E,
err_South_Req_W => L_err_South_Req_W,
err_next_state_onehot => L_err_next_state_onehot,
err_state_in_onehot => L_err_state_in_onehot,
err_DCTS_RTS_FF_state_Grant_L => L_err_DCTS_RTS_FF_state_Grant_L,
err_DCTS_RTS_FF_state_Grant_N => L_err_DCTS_RTS_FF_state_Grant_N,
err_DCTS_RTS_FF_state_Grant_E => L_err_DCTS_RTS_FF_state_Grant_E,
err_DCTS_RTS_FF_state_Grant_W => L_err_DCTS_RTS_FF_state_Grant_W,
err_DCTS_RTS_FF_state_Grant_S => L_err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel => L_err_state_north_xbar_sel,
err_state_east_xbar_sel => L_err_state_east_xbar_sel,
err_state_west_xbar_sel => L_err_state_west_xbar_sel,
err_state_south_xbar_sel => L_err_state_south_xbar_sel,
err_state_local_xbar_sel => L_err_state_local_xbar_sel
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
-- Fault localization logic construction
-- Turns
N_E_turn <= ( N_err_write_en_write_pointer or
N_err_not_write_en_write_pointer or
N_err_read_pointer_write_pointer_not_empty or
N_err_read_pointer_write_pointer_empty or
N_err_read_pointer_write_pointer_not_full or
N_err_read_pointer_write_pointer_full or
N_err_read_pointer_increment or
N_err_read_pointer_not_increment or
N_err_read_en_mismatch ) or
( N_err_header_not_empty_Req_E_in ) or
( E_err_North_Req_N or
E_err_East_Req_N or
E_err_West_Req_N or
E_err_South_Req_N or
E_err_Local_Req_N or
E_err_IDLE_Req_N or
E_err_state_north_xbar_sel or
E_err_DCTS_RTS_FF_state_Grant_N );
N_W_turn <= ( N_err_write_en_write_pointer or
N_err_not_write_en_write_pointer or
N_err_read_pointer_write_pointer_not_empty or
N_err_read_pointer_write_pointer_empty or
N_err_read_pointer_write_pointer_not_full or
N_err_read_pointer_write_pointer_full or
N_err_read_pointer_increment or
N_err_read_pointer_not_increment or
N_err_read_en_mismatch ) or
( N_err_header_not_empty_Req_W_in ) or
( W_err_North_Req_N or
W_err_East_Req_N or
W_err_West_Req_N or
W_err_South_Req_N or
W_err_Local_Req_N or
W_err_IDLE_Req_N or
W_err_state_north_xbar_sel or
W_err_DCTS_RTS_FF_state_Grant_N);
S_W_turn <= ( S_err_write_en_write_pointer or
S_err_not_write_en_write_pointer or
S_err_read_pointer_write_pointer_not_empty or
S_err_read_pointer_write_pointer_empty or
S_err_read_pointer_write_pointer_not_full or
S_err_read_pointer_write_pointer_full or
S_err_read_pointer_increment or
S_err_read_pointer_not_increment or
S_err_read_en_mismatch ) or
( S_err_header_not_empty_Req_W_in ) or
( W_err_North_Req_S or
W_err_East_Req_S or
W_err_West_Req_S or
W_err_South_Req_S or
W_err_Local_Req_S or
W_err_IDLE_Req_S or
W_err_state_South_xbar_sel or
W_err_DCTS_RTS_FF_state_Grant_S);
S_E_turn <= ( S_err_write_en_write_pointer or
S_err_not_write_en_write_pointer or
S_err_read_pointer_write_pointer_not_empty or
S_err_read_pointer_write_pointer_empty or
S_err_read_pointer_write_pointer_not_full or
S_err_read_pointer_write_pointer_full or
S_err_read_pointer_increment or
S_err_read_pointer_not_increment or
S_err_read_en_mismatch ) or
( S_err_header_not_empty_Req_E_in ) or
( E_err_North_Req_S or
E_err_East_Req_S or
E_err_West_Req_S or
E_err_South_Req_S or
E_err_Local_Req_S or
E_err_IDLE_Req_S or
E_err_state_South_xbar_sel or
E_err_DCTS_RTS_FF_state_Grant_S);
W_N_turn <= ( W_err_write_en_write_pointer or
W_err_not_write_en_write_pointer or
W_err_read_pointer_write_pointer_not_empty or
W_err_read_pointer_write_pointer_empty or
W_err_read_pointer_write_pointer_not_full or
W_err_read_pointer_write_pointer_full or
W_err_read_pointer_increment or
W_err_read_pointer_not_increment or
W_err_read_en_mismatch ) or
( W_err_header_not_empty_Req_N_in ) or
( N_err_North_Req_W or
N_err_East_Req_W or
N_err_West_Req_W or
N_err_South_Req_W or
N_err_Local_Req_W or
N_err_IDLE_Req_W or
N_err_state_west_xbar_sel or
N_err_DCTS_RTS_FF_state_Grant_W);
W_S_turn <= ( W_err_write_en_write_pointer or
W_err_not_write_en_write_pointer or
W_err_read_pointer_write_pointer_not_empty or
W_err_read_pointer_write_pointer_empty or
W_err_read_pointer_write_pointer_not_full or
W_err_read_pointer_write_pointer_full or
W_err_read_pointer_increment or
W_err_read_pointer_not_increment or
W_err_read_en_mismatch ) or
( W_err_header_not_empty_Req_S_in ) or
( S_err_North_Req_W or
S_err_East_Req_W or
S_err_West_Req_W or
S_err_South_Req_W or
S_err_Local_Req_W or
S_err_IDLE_Req_W or
S_err_state_west_xbar_sel or
S_err_DCTS_RTS_FF_state_Grant_W);
E_N_turn <= ( E_err_write_en_write_pointer or
E_err_not_write_en_write_pointer or
E_err_read_pointer_write_pointer_not_empty or
E_err_read_pointer_write_pointer_empty or
E_err_read_pointer_write_pointer_not_full or
E_err_read_pointer_write_pointer_full or
E_err_read_pointer_increment or
E_err_read_pointer_not_increment or
E_err_read_en_mismatch ) or
( E_err_header_not_empty_Req_N_in ) or
( N_err_North_Req_E or
N_err_East_Req_E or
N_err_West_Req_E or
N_err_South_Req_E or
N_err_Local_Req_E or
N_err_IDLE_Req_E or
N_err_state_east_xbar_sel or
N_err_DCTS_RTS_FF_state_Grant_E);
E_S_turn <= ( E_err_write_en_write_pointer or
E_err_not_write_en_write_pointer or
E_err_read_pointer_write_pointer_not_empty or
E_err_read_pointer_write_pointer_empty or
E_err_read_pointer_write_pointer_not_full or
E_err_read_pointer_write_pointer_full or
E_err_read_pointer_increment or
E_err_read_pointer_not_increment or
E_err_read_en_mismatch ) or
( E_err_header_not_empty_Req_S_in ) or
( S_err_North_Req_E or
S_err_East_Req_E or
S_err_West_Req_E or
S_err_South_Req_E or
S_err_Local_Req_E or
S_err_IDLE_Req_E or
S_err_state_east_xbar_sel or
S_err_DCTS_RTS_FF_state_Grant_E);
-- Paths
N_S_path <= ( N_err_write_en_write_pointer or
N_err_not_write_en_write_pointer or
N_err_read_pointer_write_pointer_not_empty or
N_err_read_pointer_write_pointer_empty or
N_err_read_pointer_write_pointer_not_full or
N_err_read_pointer_write_pointer_full or
N_err_read_pointer_increment or
N_err_read_pointer_not_increment or
N_err_read_en_mismatch ) or
( N_err_header_not_empty_Req_S_in ) or
( S_err_North_Req_N or
S_err_East_Req_N or
S_err_West_Req_N or
S_err_South_Req_N or
S_err_Local_Req_N or
S_err_IDLE_Req_N or
S_err_state_north_xbar_sel or
S_err_DCTS_RTS_FF_state_Grant_N );
S_N_path <= ( S_err_write_en_write_pointer or
S_err_not_write_en_write_pointer or
S_err_read_pointer_write_pointer_not_empty or
S_err_read_pointer_write_pointer_empty or
S_err_read_pointer_write_pointer_not_full or
S_err_read_pointer_write_pointer_full or
S_err_read_pointer_increment or
S_err_read_pointer_not_increment or
S_err_read_en_mismatch ) or
( S_err_header_not_empty_Req_N_in ) or
( N_err_North_Req_S or
N_err_East_Req_S or
N_err_West_Req_S or
N_err_South_Req_S or
N_err_Local_Req_S or
N_err_IDLE_Req_S or
N_err_state_South_xbar_sel or
N_err_DCTS_RTS_FF_state_Grant_S);
E_W_path <= ( E_err_write_en_write_pointer or
E_err_not_write_en_write_pointer or
E_err_read_pointer_write_pointer_not_empty or
E_err_read_pointer_write_pointer_empty or
E_err_read_pointer_write_pointer_not_full or
E_err_read_pointer_write_pointer_full or
E_err_read_pointer_increment or
E_err_read_pointer_not_increment or
E_err_read_en_mismatch ) or
( E_err_header_not_empty_Req_W_in ) or
( W_err_North_Req_E or
W_err_East_Req_E or
W_err_West_Req_E or
W_err_South_Req_E or
W_err_Local_Req_E or
W_err_IDLE_Req_E or
W_err_state_east_xbar_sel or
W_err_DCTS_RTS_FF_state_Grant_E);
W_E_path <= ( W_err_write_en_write_pointer or
W_err_not_write_en_write_pointer or
W_err_read_pointer_write_pointer_not_empty or
W_err_read_pointer_write_pointer_empty or
W_err_read_pointer_write_pointer_not_full or
W_err_read_pointer_write_pointer_full or
W_err_read_pointer_increment or
W_err_read_pointer_not_increment or
W_err_read_en_mismatch ) or
( W_err_header_not_empty_Req_E_in ) or
( E_err_North_Req_W or
E_err_East_Req_W or
E_err_West_Req_W or
E_err_South_Req_W or
E_err_Local_Req_W or
E_err_IDLE_Req_W or
E_err_state_west_xbar_sel or
E_err_DCTS_RTS_FF_state_Grant_W);
-- FIFO Handshaking error signals
N_FIFO_handshaking_error <= N_err_CTS_in or
N_err_write_en or
N_err_not_CTS_in or
N_err_not_write_en;
E_FIFO_handshaking_error <= E_err_CTS_in or
E_err_write_en or
E_err_not_CTS_in or
E_err_not_write_en;
W_FIFO_handshaking_error <= W_err_CTS_in or
W_err_write_en or
W_err_not_CTS_in or
W_err_not_write_en;
S_FIFO_handshaking_error <= S_err_CTS_in or
S_err_write_en or
S_err_not_CTS_in or
S_err_not_write_en;
L_FIFO_handshaking_error <= L_err_CTS_in or
L_err_write_en or
L_err_not_CTS_in or
L_err_not_write_en;
end;
| gpl-3.0 | f6cdadbbf85539fc54dc5187c6138fb7 | 0.483918 | 3.163523 | false | false | false | false |
TUM-LIS/faultify | software/host/davester_combinational_extractor/voltage_scaling_fpu_mul/txt_util.vhd | 4 | 16,132 | library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package txt_util is
-- prints a message to the screen
procedure print(text: string);
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
-- converts std_logic into a character
function chr(sl: std_logic) return character;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string;
-- converts std_logic_vector into a string (binary base)
function str(slv: std_logic_vector) return string;
-- converts boolean into a string
function str(b: boolean) return string;
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int: integer) return character;
-- converts integer into string using specified base
function str(int: integer; base: integer) return string;
-- converts integer to string, using base 10
function str(int: integer) return string;
-- convert std_logic_vector into a string in hex format
function hstr(slv: std_logic_vector) return string;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character;
-- convert a character to lower case
function to_lower(c: character) return character;
-- convert a string to upper case
function to_upper(s: string) return string;
-- convert a string to lower case
function to_lower(s: string) return string;
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c: character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector;
-- convert Hex string to 32-bit into std_logic_vector
function strhex_to_slv(s : string) return std_logic_vector;
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string);
-- print string to a file and start new line
procedure print(file out_file: TEXT;
new_string: in string);
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character);
end txt_util;
package body txt_util is
-- prints text to the screen
procedure print(text: string) is
variable msg_line: line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
-- prints text to the screen when active
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end print;
-- converts std_logic into a character
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
function str(b: boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end str;
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int: integer) return character is
variable c: character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int: integer; base: integer) return string is
variable temp: string(1 to 10);
variable num: integer;
variable abs_int: integer;
variable len: integer := 1;
variable power: integer := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop ; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop ; -- side.
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end str;
-- convert integer to string, using base 10
function str(int: integer) return string is
begin
return str(int, 10) ;
end str;
-- converts a std_logic_vector into a hex string.
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character is
variable u: character;
begin
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
return u;
end to_upper;
-- convert a character to lower case
function to_lower(c: character) return character is
variable l: character;
begin
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
return l;
end to_lower;
-- convert a string to upper case
function to_upper(s: string) return string is
variable uppercase: string (s'range);
begin
for i in s'range loop
uppercase(i):= to_upper(s(i));
end loop;
return uppercase;
end to_upper;
-- convert a string to lower case
function to_lower(s: string) return string is
variable lowercase: string (s'range);
begin
for i in s'range loop
lowercase(i):= to_lower(s(i));
end loop;
return lowercase;
end to_lower;
-- functions to convert strings into other types
-- converts a character into a std_logic
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
begin
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
end case;
return sl;
end to_std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
-- convert Hex string to 32-bit SLV
function strhex_to_slv(s : string) return std_logic_vector is
variable int : string(1 to s'length) := s;
variable ptr : integer range 0 to 32 := 0;
variable slv: std_logic_vector(31 downto 0) := (others=>'0');
begin
for i in int'reverse_range loop
case int(i) is
when '0' => slv(ptr+3 downto ptr) := "0000"; ptr := ptr+4;
when '1' => slv(ptr+3 downto ptr) := "0001"; ptr := ptr+4;
when '2' => slv(ptr+3 downto ptr) := "0010"; ptr := ptr+4;
when '3' => slv(ptr+3 downto ptr) := "0011"; ptr := ptr+4;
when '4' => slv(ptr+3 downto ptr) := "0100"; ptr := ptr+4;
when '5' => slv(ptr+3 downto ptr) := "0101"; ptr := ptr+4;
when '6' => slv(ptr+3 downto ptr) := "0110"; ptr := ptr+4;
when '7' => slv(ptr+3 downto ptr) := "0111"; ptr := ptr+4;
when '8' => slv(ptr+3 downto ptr) := "1000"; ptr := ptr+4;
when '9' => slv(ptr+3 downto ptr) := "1001"; ptr := ptr+4;
when 'a'|'A' => slv(ptr+3 downto ptr) := "1010"; ptr := ptr+4;
when 'b'|'B' => slv(ptr+3 downto ptr) := "1011"; ptr := ptr+4;
when 'c'|'C' => slv(ptr+3 downto ptr) := "1100"; ptr := ptr+4;
when 'd'|'D' => slv(ptr+3 downto ptr) := "1101"; ptr := ptr+4;
when 'e'|'E' => slv(ptr+3 downto ptr) := "1110"; ptr := ptr+4;
when 'f'|'F' => slv(ptr+3 downto ptr) := "1111"; ptr := ptr+4;
when others => null;
end case;
end loop;
return slv;
end strhex_to_slv;
----------------
-- file I/O --
----------------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string) is
variable l: line;
variable c: character;
variable is_string: boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
-- print string to a file
procedure print(file out_file: TEXT;
new_string: in string) is
variable l: line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character) is
variable l: line;
begin
write(l, char);
writeline(out_file, l);
end print;
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
procedure str_write(file out_file: TEXT;
new_string: in string) is
begin
for i in new_string'range loop
print(out_file, new_string(i));
if new_string(i) = LF then -- end of string
exit;
end if;
end loop;
end str_write;
end txt_util;
| gpl-2.0 | 28b04dc94252bd979949b5817849cee7 | 0.479296 | 3.689001 | false | false | false | false |
TanND/Electronic | VHDL/D11_C1.vhd | 1 | 908 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D11_C1 is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
y : out STD_LOGIC;
d : in BIT
);
end D11_C1;
architecture D11_C1 of D11_C1 is
type state is (s0,s1,s2,s3);
signal s:state;
begin
next_state:process(rst,clk)
begin
if (rst='1') then s<=s0;
else
if (rising_edge(clk)) then
case s is
when s0 =>
if d='0' then s <=s1; else s<=s0;
end if;
when s1 =>
if d='0' then s <=s3; else s<=s2;
end if;
when s2 =>
if d='0' then s <=s1; else s<=s0;
end if;
when s3 =>
if d='0' then s <=s3; else s<=s2;
end if;
end case;
end if;
end if;
end process;
output:process(s,clk)
begin
if (rising_edge(clk)) then
if ((s=s3) and (d='0')) then
y<='1';
else y<='0';
end if;
end if;
end process;
end D11_C1;
--rst=100khz; d= random 100ns; clk=5Mhz; | apache-2.0 | 6fc622fcf25049520c39c4df5dc2ee84 | 0.546256 | 2.328205 | false | false | false | false |
JarrettR/FPGA-Cryptoparty | FPGA/hdl/pbkdf2_main.vhd | 1 | 6,885 | --------------------------------------------------------------------------------
-- pbkdf2_input.vhd
-- Input stage of PBKDF2 algorithm
-- Copyright (C) 2016 Jarrett Rainier
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.sha1_pkg.all;
entity pbkdf2_main is
port(
clk_i : in std_ulogic;
rst_i : in std_ulogic;
load_i : in std_ulogic;
mk_i : in mk_data;
ssid_i : in ssid_data;
dat_o : out w_pmk;
valid_o : out std_ulogic
);
end pbkdf2_main;
architecture RTL of pbkdf2_main is
component hmac_main
port(
clk_i : in std_ulogic;
rst_i : in std_ulogic;
secret_i : in w_input;
value_i : in w_input;
value_len_i : in std_ulogic_vector(0 to 63);
load_i : in std_ulogic;
dat_o : out w_output;
valid_o : out std_ulogic
);
end component;
type state_type is (STATE_IDLE,
STATE_X_START, STATE_X_PROCESS,
STATE_CLEANUP, STATE_FINISHED);
signal state : state_type := STATE_IDLE;
signal mk : mk_data;
signal ssid : ssid_data;
signal ssid_length : std_ulogic_vector(0 to 63);
signal mk_in : w_input;
signal out_x1 : w_output;
signal out_x2 : w_output;
signal f1 : w_output;
signal f2 : w_output;
signal f1_con : w_output;
signal f2_con : w_output;
signal x1 : w_input;
signal x2 : w_input;
signal x1_in : w_input;
signal x2_in : w_input;
--signal mk : w_input;
signal valid : std_ulogic;
signal valid_x1 : std_ulogic;
signal valid_x2 : std_ulogic;
signal load_x1 : std_ulogic;
signal load_x2 : std_ulogic;
signal i: integer range 0 to 4096;
--type w_input is array(0 to 15) of std_ulogic_vector(0 to 31); linksys
begin
HMAC1: hmac_main port map (clk_i,rst_i,mk_in,x1_in,ssid_length,load_x1,out_x1,valid_x1);
HMAC2: hmac_main port map (clk_i,rst_i,mk_in,x2_in,ssid_length,load_x2,out_x2,valid_x2);
process(clk_i)
begin
if (clk_i'event and clk_i = '1') then
if rst_i = '1' then
state <= STATE_IDLE;
i <= 0;
valid_o <= '0';
elsif load_i = '1' and state = STATE_IDLE then
i <= 0;
valid_o <= '0';
mk <= mk_i;
for x in 0 to 1 loop
mk_in(x) <= std_ulogic_vector(mk_i(x*4)) & std_ulogic_vector(mk_i(x * 4 + 1)) & std_ulogic_vector(mk_i(x * 4 + 2)) & std_ulogic_vector(mk_i(x * 4 + 3));
end loop;
--Todo: Fix this, it is dumb
mk_in(2) <= std_ulogic_vector(mk_i(8)) & std_ulogic_vector(mk_i(9)) & X"0000";
for x in 3 to 15 loop
mk_in(x) <= X"00000000";
end loop;
for x in 0 to 4 loop
f1(x) <= X"00000000";
f2(x) <= X"00000000";
end loop;
ssid <= ssid_i;
--Todo: Fix this, it is dumb too
x1_in(0) <= std_ulogic_vector(ssid_i(0)) & std_ulogic_vector(ssid_i(1)) & std_ulogic_vector(ssid_i(2)) & std_ulogic_vector(ssid_i(3));
x1_in(1) <= std_ulogic_vector(ssid_i(4)) & std_ulogic_vector(ssid_i(5)) & std_ulogic_vector(ssid_i(6)) & X"00";
x1_in(2) <= X"00000180";
x2_in(0) <= std_ulogic_vector(ssid_i(0)) & std_ulogic_vector(ssid_i(1)) & std_ulogic_vector(ssid_i(2)) & std_ulogic_vector(ssid_i(3));
x2_in(1) <= std_ulogic_vector(ssid_i(4)) & std_ulogic_vector(ssid_i(5)) & std_ulogic_vector(ssid_i(6)) & X"00";
x2_in(2) <= X"00000280";
for x in 3 to 15 loop
x1_in(x) <= X"00000000";
x2_in(x) <= X"00000000";
end loop;
ssid_length <= X"0000000000000258";
state <= STATE_X_START;
elsif state = STATE_X_START then
load_x1 <= '1';
load_x2 <= '1';
state <= STATE_X_PROCESS;
elsif state = STATE_X_PROCESS then
load_x1 <= '0';
load_x2 <= '0';
if valid_x1 = '1' and valid_x2 = '1' then
if i = 4095 then
state <= STATE_CLEANUP;
else
i <= i + 1;
for x in 0 to 4 loop
x1_in(x) <= out_x1(x);
x2_in(x) <= out_x2(x);
f1(x) <= f1_con(x) xor out_x1(x);
f2(x) <= f2_con(x) xor out_x2(x);
end loop;
x1_in(5) <= X"80000000";
x2_in(5) <= X"80000000";
for x in 6 to 15 loop
x1_in(x) <= X"00000000";
x2_in(x) <= X"00000000";
end loop;
ssid_length <= X"00000000000002A0";
state <= STATE_X_START;
end if;
end if;
elsif state = STATE_CLEANUP then
for x in 0 to 4 loop
f1(x) <= f1_con(x) xor out_x1(x);
f2(x) <= f2_con(x) xor out_x2(x);
end loop;
state <= STATE_FINISHED;
elsif state = STATE_FINISHED then
valid_o <= '1';
state <= STATE_IDLE;
end if;
end if;
end process;
f1_con <= f1;
f2_con <= f2;
dat_o <= w_pmk(f1(0 to 4) & f2(0 to 2));
end RTL;
| gpl-3.0 | 1927c72ec6a4dcc0b184d9f62afb4ce1 | 0.442121 | 3.5953 | false | false | false | false |
SoCdesign/EHA | RTL/Fault_Management/Error_Detection_Correction/hamming_encoder.vhd | 1 | 1,739 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use ieee.std_logic_misc.all;
entity hamming_encoder is
--generic(n: integer := 27);
port(datain : in Std_logic_vector(31 downto 0); -- d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27
dataout : out std_logic_vector(38 downto 0));
end hamming_encoder;
architecture combinational of hamming_encoder is
signal p0, p1, p2, p3, p4, p5, p6 : std_logic; --check bits
--signal dataout_sig:std_logic_vector(34 downto 0);
BEGIN
--dataout<=dataout_sig;
--generate check bits
p0 <= datain(0) xor datain(1) xor datain(3) xor datain(4) xor datain(6) xor datain(8) xor datain(10) xor datain(11) xor datain(13) xor datain(15)
xor datain(17) xor datain(19) xor datain(21) xor datain(23) xor datain(25) xor datain(26) xor datain(28) xor datain(30);
p1 <= datain(0) xor datain(2) xor datain(3) xor datain(5) xor datain(6) xor datain(9) xor datain(10) xor datain(12) xor datain(13) xor datain(16)
xor datain(17) xor datain(20) xor datain(21) xor datain(24) xor datain(25) xor datain(27) xor datain(28) xor datain(31);
p2 <= XOR_REDUCE(datain(3 downto 1)) xor XOR_REDUCE(datain(10 downto 7)) xor XOR_REDUCE(datain(17 downto 14)) xor XOR_REDUCE(datain(25 downto 22)) xor XOR_REDUCE(datain(31 downto 29));
p3 <= XOR_REDUCE(datain(10 downto 4)) xor XOR_REDUCE(datain(25 downto 18));
p4 <= XOR_REDUCE(datain(25 downto 11));
p5 <= XOR_REDUCE(datain(31 downto 26));
P6 <= XOR_REDUCE(datain(31 downto 0)) xor p0 xor p1 xor p2 xor p3 xor p4 xor p5;
dataout <= p6 & p5 & p4 & p3 & p2 & p1 & p0 & datain;
END combinational; | gpl-3.0 | ae1489e1c912e1a801e172a604056324 | 0.66475 | 2.962521 | false | false | false | false |
lnls-dig/dsp-cores | hdl/testbench/cic/wb_bpm_swap/xwb_bpm_swap.vhd | 1 | 4,833 | ------------------------------------------------------------------------------
-- Title : Wishbone BPM SWAP interface
------------------------------------------------------------------------------
-- Author : Jose Alvim Berkenbrock
-- Company : CNPEM LNLS-DIG
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Wishbone interface with BPM Swap core.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-04-11 1.0 jose.berkenbrock Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- DSP Cores
use work.dsp_cores_pkg.all;
-- BPM Cores
use work.swap_pkg.all;
-- Register Bank
use work.bpm_swap_wbgen2_pkg.all;
entity xwb_bpm_swap is
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_delay_vec_width : natural := 8;
g_swap_div_freq_vec_width : natural := 16;
g_ch_width : natural := 16
);
port
(
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
fs_rst_n_i : in std_logic;
fs_clk_i : in std_logic;
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_i : in t_wishbone_slave_in;
wb_slv_o : out t_wishbone_slave_out;
-----------------------------
-- External ports
-----------------------------
-- Input data from ADCs
cha_i : in std_logic_vector(g_ch_width-1 downto 0);
chb_i : in std_logic_vector(g_ch_width-1 downto 0);
chc_i : in std_logic_vector(g_ch_width-1 downto 0);
chd_i : in std_logic_vector(g_ch_width-1 downto 0);
ch_valid_i : in std_logic;
-- Output data to BPM DSP chain
cha_o : out std_logic_vector(g_ch_width-1 downto 0);
chb_o : out std_logic_vector(g_ch_width-1 downto 0);
chc_o : out std_logic_vector(g_ch_width-1 downto 0);
chd_o : out std_logic_vector(g_ch_width-1 downto 0);
ch_tag_o : out std_logic_vector(0 downto 0);
ch_valid_o : out std_logic;
-- RFFE swap clock (or switchwing clock)
rffe_swclk_o : out std_logic;
sync_trig_i : in std_logic
);
end xwb_bpm_swap;
architecture rtl of xwb_bpm_swap is
begin
cmp_wb_bpm_swap : wb_bpm_swap
generic map
(
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
g_delay_vec_width => g_delay_vec_width,
g_swap_div_freq_vec_width => g_swap_div_freq_vec_width,
g_ch_width => g_ch_width
)
port map
(
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
fs_rst_n_i => fs_rst_n_i,
fs_clk_i => fs_clk_i,
wb_adr_i => wb_slv_i.adr,
wb_dat_i => wb_slv_i.dat,
wb_dat_o => wb_slv_o.dat,
wb_sel_i => wb_slv_i.sel,
wb_we_i => wb_slv_i.we,
wb_cyc_i => wb_slv_i.cyc,
wb_stb_i => wb_slv_i.stb,
wb_ack_o => wb_slv_o.ack,
wb_stall_o => wb_slv_o.stall,
cha_i => cha_i,
chb_i => chb_i,
chc_i => chc_i,
chd_i => chd_i,
ch_valid_i => ch_valid_i,
cha_o => cha_o,
chb_o => chb_o,
chc_o => chc_o,
chd_o => chd_o,
ch_tag_o => ch_tag_o,
ch_valid_o => ch_valid_o,
rffe_swclk_o => rffe_swclk_o,
sync_trig_i => sync_trig_i
);
end rtl;
| lgpl-3.0 | f855030d2e1bfcc7f04b9e4925bb6510 | 0.382785 | 4.068182 | false | false | false | false |
carlosrd/DAS | P4/Parte C (Opcional 2)/cronometro.vhd | 1 | 7,283 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
entity cronometro is
port (
-- Entradas
startStop: in std_logic;
puestaCero: in std_logic;
clk: in std_logic;
rst: in std_logic;
shift: in std_logic;
-- Salidas
rightSegs: out std_logic_vector(7 downto 0);
leftSegs: out std_logic_vector(7 downto 0);
decimasSegs: out std_logic_vector(7 downto 0);
puntoDec: out std_logic
);
end cronometro;
architecture Behavioral of cronometro is
signal ssDebounced,ssDebFallEdge,ssDebRiseEdge: std_logic;
signal pODebounced,pODebFallEdge,pODebRiseEdge: std_logic;
signal t: std_logic;
signal salidaCont5kk: std_logic_vector(22 downto 0);
signal salidaContDecimas, salidaContUnidades,salidaContDecenas: std_logic_vector(3 downto 0);
signal cuentaDecimas, cuentaUnidades, cuentaDecenas: std_logic;
signal cs1 : std_logic_vector( 22 downto 0 );
signal cs2,cs3,cs4,cs5,cs6 : std_logic_vector( 3 downto 0 );
-- Señales adicionales para los contadores y visores de Minutos
signal salidaContMinUnidades,salidaContMinDecenas: std_logic_vector(3 downto 0);
signal muxRight, muxLeft: std_logic_vector(3 downto 0);
signal cuentaUnidadesMinutos, cuentaDecenasMinutos: std_logic;
signal lit1,lit2,lit3: std_logic;
component debouncer
port(rst: in std_logic;
clk: in std_logic;
x: in std_logic;
xDeb: out std_logic;
xDebFallingEdge: out std_logic;
xDebRisingEdge: out std_logic);
end component;
component binToSeg is
port (
bin: in std_logic_vector(3 downto 0);
displaySeg: out std_logic_vector(7 downto 0) -- 7 = A / 6 = B / ... / 0 = H
);
end component;
begin
-- ELIMINACION DE REBOTES EN LOS PUSHBUTTONS
debouncerStartStop: debouncer port map (rst,clk,startStop,ssDebounced,ssDebFallEdge,ssDebRiseEdge);
debouncerPuestaCero: debouncer port map (rst,clk,puestaCero,pODebounced,pODebFallEdge,pODebRiseEdge);
-- CONTADORES
contMod5kk:
process( clk, cs1, rst, pODebFallEdge, ssDebFallEdge )
begin
salidaCont5kk <= cs1;
if rst = '0' then
cs1 <= conv_std_logic_vector( 0 , 23 );
elsif clk'event and clk = '1' then
if pODebFallEdge = '1' then
cs1 <= conv_std_logic_vector( 0 , 23 );
elsif t = '1' then
if cs1 = conv_std_logic_vector( 4999999 , 23 ) then
cs1 <= conv_std_logic_vector( 0 , 23 );
else
cs1 <= cs1 + 1;
end if;
end if;
end if;
end process;
-- contDecimas cuenta cuando se tenga 4.999.999 = 10011000100101100111111 en cont5Millones
cuentaDecimas <= salidaCont5kk(22) and salidaCont5kk(19) and salidaCont5kk(18) and salidaCont5kk(14) and salidaCont5kk(11) and
salidaCont5kk(9) and salidaCont5kk(8) and salidaCont5kk(5) and salidaCont5kk(4) and salidaCont5kk(3) and
salidaCont5kk(2) and salidaCont5kk(1) and salidaCont5kk(0);
contDecimas:
process( clk, cs2, rst, pODebFallEdge, cuentaDecimas )
begin
salidaContDecimas <= cs2;
if rst = '0' then
cs2 <= conv_std_logic_vector( 0 , 4 );
elsif clk'event and clk = '1' then
if pODebFallEdge = '1' then
cs2 <= conv_std_logic_vector( 0 , 4 );
elsif cuentaDecimas = '1' then
if cs2 = conv_std_logic_vector( 9 , 4 ) then
cs2 <= conv_std_logic_vector( 0 , 4 );
else
cs2 <= cs2 + 1;
end if;
end if;
end if;
end process;
-- contUnidades cuenta cuando se tenga 9 = 1001 en contDecimas
cuentaUnidades <= (salidaContDecimas(3) and salidaContDecimas(0)) and cuentaDecimas;
contUnidades:
process( clk, cs3, rst, pODebFallEdge, cuentaUnidades )
begin
salidaContUnidades <= cs3;
if rst = '0' then
cs3 <= conv_std_logic_vector( 0 , 4 );
elsif clk'event and clk = '1' then
if pODebFallEdge = '1' then
cs3 <= conv_std_logic_vector( 0 , 4 );
elsif cuentaUnidades = '1' then
if cs3 = conv_std_logic_vector( 9 , 4 ) then
cs3 <= conv_std_logic_vector( 0 , 4 );
else
cs3 <= cs3 + 1;
end if;
end if;
end if;
end process;
cuentaDecenas <= (salidaContUnidades(3) and salidaContUnidades(0)) and (cuentaDecimas and cuentaUnidades);
contDecenas:
process( clk, cs4, rst, pODebFallEdge, cuentaDecenas )
begin
salidaContDecenas <= cs4;
if rst = '0' then
cs4 <= conv_std_logic_vector( 0 , 4 );
elsif clk'event and clk = '1' then
if pODebFallEdge = '1' then
cs4 <= conv_std_logic_vector( 0 , 4 );
elsif cuentaDecenas = '1' then
if cs4 = conv_std_logic_vector( 5 , 4 ) then
cs4 <= conv_std_logic_vector( 0 , 4 );
else
cs4 <= cs4 + 1;
end if;
end if;
end if;
end process;
-- Cuenta minutos cuando Unidades = 9 y Decenas = 5
cuentaUnidadesMinutos <= ((salidaContUnidades(3) and salidaContUnidades(0) and
salidaContDecenas(2) and salidaContDecenas(0)) and (cuentaDecimas and cuentaUnidades and cuentaDecenas));
contMinutosUnidades:
process( clk, cs5, rst, pODebFallEdge, cuentaUnidadesMinutos )
begin
salidaContMinUnidades <= cs5;
if rst = '0' then
cs5 <= conv_std_logic_vector( 0 , 4 );
elsif clk'event and clk = '1' then
if pODebFallEdge = '1' then
cs5 <= conv_std_logic_vector( 0 , 4 );
elsif cuentaUnidadesMinutos = '1' then
if cs5 = conv_std_logic_vector( 9 , 4 ) then
cs5 <= conv_std_logic_vector( 0 , 4 );
else
cs5 <= cs5 + 1;
end if;
end if;
end if;
end process;
cuentaDecenasMinutos <= salidaContMinUnidades(3) and salidaContMinUnidades(0) and cuentaUnidadesMinutos;
contMinutosDecenas:
process( clk, cs5, rst, pODebFallEdge, cuentaDecenasMinutos )
begin
salidaContMinDecenas <= cs6;
if rst = '0' then
cs6 <= conv_std_logic_vector( 0 , 4 );
elsif clk'event and clk = '1' then
if pODebFallEdge = '1' then
cs6 <= conv_std_logic_vector( 0 , 4 );
elsif cuentaDecenasMinutos = '1' then
if cs6 = conv_std_logic_vector( 5 , 4 ) then
cs6 <= conv_std_logic_vector( 0 , 4 );
else
cs6 <= cs6 + 1;
end if;
end if;
end if;
end process;
-- BIESTABLE T
-- Usamos el flanco de bajada (fall) porque la placa tiene logica negativa
biestableT:
process(clk)
begin
if (rst = '0') then
t <= '0';
elsif (clk'event and clk='1') then
if (ssDebFallEdge = '1') then
t <= not (t);
end if;
end if;
end process;
parpadeoPuntoDecimal:
process(salidaContDecimas)
begin
lit1 <= not salidaContDecimas(3) and not salidaContDecimas(2);
lit2 <= not salidaContDecimas(3) and not salidaContDecimas(1) and not salidaContDecimas(0);
lit3 <= lit1 or lit2;
if (lit3 = '1') then
puntoDec <= '1';
else
puntoDec <= '0';
end if;
end process;
muxLeft <= salidaContDecenas when shift = '1' else salidaContMinDecenas;
muxRight <= salidaContUnidades when shift = '1' else salidaContMinUnidades;
-- DISPLAYS 8 SEGMENTOS
deciSeg: binToSeg port map (salidaContDecimas,decimasSegs);
decenasSegm: binToSeg port map (muxLeft,leftSegs);
unidadesSegm: binToSeg port map (muxRight,rightSegs);
end Behavioral;
-- x3 x2 x1 x0 z
--------------------
--0 0 0 0 0 1
--1 0 0 0 1 1
--2 0 0 1 0 1
--3 0 0 1 1 1
--4 0 1 0 0 1
--5 0 1 0 1 0
--6 0 1 1 0 0
--7 0 1 1 1 0
--8 1 0 0 0 0
--9 1 0 0 1 0
-- Mapa de Karnaugh ==> FLASH = (¬ x3)(¬ x2) + (¬ x3)(¬ x1)(¬ x0)
| mit | 0c5506b07462df84c43daf6e34a55aef | 0.665248 | 3.01324 | false | false | false | false |
lnls-dig/dsp-cores | hdl/modules/counters_gen/counters_gen_pkg.vhd | 1 | 3,323 | ------------------------------------------------------------------------------
-- Title : Simple Position Counters package for debugging
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2017-01-20
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Core for generating coutners sync'ed with each incoming data rate.
-- Used for debugging.
-------------------------------------------------------------------------------
-- Copyright (c) 2017 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2017-01-20 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbone_pkg.all;
package counters_gen_pkg is
-------------------------------------------------------------------------------
-- Constants declaration
-------------------------------------------------------------------------------
constant c_max_cnt_width : natural := 32;
-------------------------------------------------------------------------------
-- Types declaration
-------------------------------------------------------------------------------
type t_cnt_width_array is array (natural range <>) of natural;
type t_cnt_array is array (natural range <>) of unsigned(c_max_cnt_width-1 downto 0);
-------------------------------------------------------------------------------
-- Defaults
-------------------------------------------------------------------------------
constant c_default_num_counters : natural := 2;
constant c_default_cnt_width : natural := 32;
constant c_default_cnt_width_array : t_cnt_width_array(c_default_num_counters-1 downto 0) := (
c_default_cnt_width, c_default_cnt_width);
-----------------------------
-- Functions declaration
----------------------------
function f_dup_counter_array(cnt : unsigned; num_dups : natural)
return std_logic_vector;
end counters_gen_pkg;
package body counters_gen_pkg is
function f_dup_counter_array(cnt : unsigned; num_dups : natural)
return std_logic_vector
is
constant c_cnt_size : natural := cnt'length;
variable cnt_out : std_logic_vector(c_cnt_size*num_dups-1 downto 0) :=
(others => '0');
variable cnt_slice : std_logic_vector(c_cnt_size-1 downto 0) :=
(others => '0');
begin
assert (num_dups >= 1)
report "[f_dup_counter_array] num_dups must be greater or equal than 1"
severity Failure;
-- Get only the interesting part of input
cnt_slice := std_logic_vector(cnt(c_cnt_size-1 downto 0));
-- Duplicate "num_dups" times the input array
loop_dup : for i in 0 to num_dups-1 loop
cnt_out(c_cnt_size*(i+1)-1 downto c_cnt_size*i) :=
cnt_slice;
end loop;
return cnt_out;
end;
end counters_gen_pkg;
| lgpl-3.0 | 0256cf78bcbdc7cad61697330bab6e2a | 0.434547 | 4.788184 | false | false | false | false |
bruskajp/EE-316 | Project4/Vivado_NexysBoard/craddockEE316/craddockEE316.srcs/sources_1/imports/testFolder/multiplex_UART.vhd | 1 | 799 | -- file: multiplex.vhd
-------------------------------------
-- n bit multiplexer
-- Shauna Rae
-- October 18, 1999
library ieee;
use ieee.std_logic_1164.all;
--define the entity of multiplex
entity multiplex_UART is
generic (data_width : positive := 8);
port(select_line: in std_logic;
in_a, in_b, in_c: in std_logic_vector(data_width-1 downto 0);
output : out std_logic_vector(data_width-1 downto 0));
end multiplex_UART;
architecture basic of multiplex_UART is
begin
-- define a process which is dependent on select_line
multiplex_behaviour: process --(select_line)
begin
if select_line = '0' then
output <= in_a;
elsif select_line = '1' then
output <= in_b;
end if;
end process;
end basic; | gpl-3.0 | 6465cee6d949799e44a93430b12f0eef | 0.599499 | 3.458874 | false | false | false | false |
TanND/Electronic | VHDL/D3_C1.vhd | 1 | 1,027 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D3_C1 is
port(
rst : in STD_LOGIC;
sel : in STD_LOGIC;
clk : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR(7 downto 0)
);
end D3_C1;
architecture D3_C1 of D3_C1 is
begin
process(rst,clk,sel)
variable dem:integer range 0 to 9;
begin
if (rst='1') then dem:=0;
elsif (rising_edge(clk)) then
if (sel='1') then
if (dem=9) then dem:=0;
else dem:=dem+1;
end if;
elsif (sel='0') then
if(dem=0) then dem:=9;
else dem:=dem-1;
end if;
end if;
end if;
case dem is
when 0 => seg<= x"C0";
when 1 => seg<= x"F9";
when 2 => seg<= x"A4";
when 3 => seg<= x"B0";
when 4 => seg<= x"99";
when 5 => seg<= x"92";
when 6 => seg<= x"82";
when 7 => seg<= x"F8";
when 8 => seg<= x"80";
when others => seg<= x"90";
end case;
end process;
end D3_C1;
-- rst=500Khz; sel=1Mhz; clk=20Mhz; | apache-2.0 | 205c2ac5ac585d7cc147eadd996a7781 | 0.487829 | 2.798365 | false | false | false | false |
SoCdesign/EHA | RTL/Fault_Management/Error_Detection_Correction/crc.vhd | 1 | 1,038 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity crc is
port(rst, clk: in std_logic;
data_in: in std_logic;
ready : out std_logic;
crc_out: out std_logic_vector (7 downto 0)
);
end crc;
architecture beh of crc is
signal crc_in, crc: std_logic_vector (7 downto 0);
signal counter, counter_in : std_logic_vector (5 downto 0);
begin
process(clk, rst) begin
if rst = '0' then
crc <= (others => '0');
counter <= (others => '0');
elsif clk'event and clk = '1' then
crc <= crc_in;
counter <= counter_in;
end if;
end process;
crc_in(0) <= crc(7) xor data_in;
crc_in(1) <= crc(0) xor crc(7);
crc_in(2) <= crc(1) xor crc(7);
crc_in(3) <= crc(2);
crc_in(4) <= crc(3);
crc_in(5) <= crc(4);
crc_in(6) <= crc(5);
crc_in(7) <= crc(6);
crc_out <= crc;
process(counter)begin
if counter = "101001" then
counter_in <= (others => '0');
ready <= '1';
else
counter_in <= counter + 1;
ready <= '0';
end if;
end process;
end architecture;
| gpl-3.0 | 1ccc07090b1da288a3ad8e5a30ce7c93 | 0.609827 | 2.537897 | false | false | false | false |
TUM-LIS/faultify | hardware/testcases/QR/fpga_sim/xpsLibraryPath_asic_400_599/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/vhdl/qr_wrapper_wrapper_stimuli.vhd | 4 | 2,829 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.qr_pack.all;
entity qr_wrapper_wrapper_stimuli is
port (
clk : in std_logic;
rst_n : in std_logic;
reduced_matrix : out std_logic; --! Divides by two the order of matrices involved
start : out std_logic; --! Starts algorithm, beginning with reading of input ports
request_out : out std_logic; --! Requests output vectors
valid_out : in std_logic; --! '1' if there is an available valid output
ready : in std_logic; --! '1' if the hardware is IDLE (waiting for start or request_out)
in_A_r : out std_logic_vector(N_G*WORD_WIDTH_G - 1 downto 0);
in_A_i : out std_logic_vector(N_G*WORD_WIDTH_G - 1 downto 0)
);
end qr_wrapper_wrapper_stimuli;
architecture behav of qr_wrapper_wrapper_stimuli is
type fsm_type is (IDLE, START_STATE, D0, D1, D2, D3, WAIT_FOR_VALID, REQUEST_OUTPUT, WAIT_FOR_READY);
signal state : fsm_type := IDLE;
signal rand_out_1, rand_out_2 : std_logic_vector(N_G*WORD_WIDTH_G - 1 downto 0);
component lfsr
generic (
width : integer;
seed : integer);
port (
clk : in std_logic;
rand_out : out std_logic_vector(width-1 downto 0));
end component;
begin -- behav
lfsr_1 : lfsr
generic map (
width => N_G*WORD_WIDTH_G,
seed => 24242309)
port map (
clk => clk,
rand_out => rand_out_1);
lfsr_2 : lfsr
generic map (
width => N_G*WORD_WIDTH_G,
seed => 3246236)
port map (
clk => clk,
rand_out => rand_out_2);
reduced_matrix <= '0';
in_A_r <= rand_out_1;
in_A_i <= rand_out_2;
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
state <= IDLE;
start <= '0';
request_out <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
case state is
when IDLE =>
if ready = '1' then
state <= START_STATE;
end if;
when START_STATE =>
start <= '1';
state <= D0;
when D0 =>
start <= '0';
state <= D1;
when D1 =>
state <= D2;
when D2 =>
state <= D3;
when D3 =>
state <= WAIT_FOR_VALID;
when WAIT_FOR_VALID =>
if ready = '1' then
state <= REQUEST_OUTPUT;
end if;
when REQUEST_OUTPUT =>
request_out <= '1';
state <= WAIT_FOR_READY;
when WAIT_FOR_READY =>
request_out <= '0';
if ready = '1' then
state <= START_STATE;
end if;
end case;
end if;
end process;
end behav;
| gpl-2.0 | a349507d8d84eaf9f0569af478b9f389 | 0.526688 | 3.441606 | false | false | false | false |
SoCdesign/EHA | RTL/Hand_Shaking/Hand_Shaking_FC/FIFO_one_hot.vhd | 1 | 6,389 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
DRTS: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
CTS: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end;
architecture behavior of FIFO is
signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(3 downto 0);
signal full, empty: std_logic;
signal read_en, write_en: std_logic;
signal CTS_in, CTS_out: std_logic;
signal FIFO_MEM_1, FIFO_MEM_1_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_2, FIFO_MEM_2_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_3, FIFO_MEM_3_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_4, FIFO_MEM_4_in : std_logic_vector(DATA_WIDTH-1 downto 0);
begin
--------------------------------------------------------------------------------------------
-- block diagram of the FIFO!
-- previous
-- router
-- -- ------------------------------------------
-- | | |
-- TX|--------->| RX Data_out|----> goes to Xbar and LBDR
-- | | |
-- RTS|--------->| DRTS FIFO read_en|<---- Comes from Arbiters (N,E,W,S,L)
-- | | (N,E,W,S,L)|
-- DCTS|<---------| CTS |
-- -- ------------------------------------------
--------------------------------------------------------------------------------------------
-- Hand shake protocol!
--
-- |<-Valid->|
-- | Data |
-- _____ _________ ______
-- RX _____X_________X______
-- DRTS _____|'''''''''|_____
-- CTS __________|''''|_______
--
--------------------------------------------------------------------------------------------
-- circular buffer structure
-- <--- WriteP
-- ---------------------------------
-- | 3 | 2 | 1 | 0 |
-- ---------------------------------
-- <--- readP
--------------------------------------------------------------------------------------------
process (clk, reset)begin
if reset = '0' then
read_pointer <= "0001";
write_pointer <= "0001";
CTS_out<='0';
FIFO_MEM_1 <= (others=>'0');
FIFO_MEM_2 <= (others=>'0');
FIFO_MEM_3 <= (others=>'0');
FIFO_MEM_4 <= (others=>'0');
elsif clk'event and clk = '1' then
write_pointer <= write_pointer_in;
read_pointer <= read_pointer_in;
if write_en = '1' then
--write into the memory
FIFO_MEM_1 <= FIFO_MEM_1_in;
FIFO_MEM_2 <= FIFO_MEM_2_in;
FIFO_MEM_3 <= FIFO_MEM_3_in;
FIFO_MEM_4 <= FIFO_MEM_4_in;
end if;
CTS_out<=CTS_in;
end if;
end process;
-- anything below here is pure combinational
-- combinatorial part
process(RX, write_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
end process;
process(read_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( read_pointer ) is
when "0001" => Data_out <= FIFO_MEM_1;
when "0010" => Data_out <= FIFO_MEM_2;
when "0100" => Data_out <= FIFO_MEM_3;
when "1000" => Data_out <= FIFO_MEM_4;
when others => Data_out <= FIFO_MEM_1;
end case ;
end process;
read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty;
empty_out <= empty;
CTS <= CTS_out;
process(write_en, write_pointer)begin
if write_en = '1' then
write_pointer_in <= write_pointer(2 downto 0)&write_pointer(3);
else
write_pointer_in <= write_pointer;
end if;
end process;
process(read_en, empty, read_pointer)begin
if (read_en = '1' and empty = '0') then
read_pointer_in <= read_pointer(2 downto 0)&read_pointer(3);
else
read_pointer_in <= read_pointer;
end if;
end process;
process(full, DRTS, CTS_out) begin
if CTS_out = '0' and DRTS = '1' and full ='0' then
CTS_in <= '1';
write_en <= '1';
else
CTS_in <= '0';
write_en <= '0';
end if;
end process;
process(write_pointer, read_pointer) begin
if read_pointer = write_pointer then
empty <= '1';
else
empty <= '0';
end if;
-- if write_pointer = read_pointer>>1 then
if write_pointer = read_pointer(0)&read_pointer(3 downto 1) then
full <= '1';
else
full <= '0';
end if;
end process;
end;
| gpl-3.0 | ea5c2c97300dc26f82420b07614827e8 | 0.425732 | 3.699479 | false | false | false | false |
mgiacomini/mips-pipeline | MEM_WB.vhd | 1 | 2,021 | -- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- Engineer: Darci Luiz Tomasi Junior
-- E-mail: [email protected]
-- Date : 29/06/2015 - 20:31
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY MEM_WB IS
PORT (clk : in std_logic;
RegWrite : in std_logic;
MemtoReg : in std_logic;
ReadDataW : in std_logic_vector(31 downto 0);
AluOutW : in std_logic_vector(31 downto 0);
WriteRegW : in std_logic_vector(4 downto 0);
outRegWrite : out std_logic;
outMemtoReg : out std_logic;
outReadDataW : out std_logic_vector(31 downto 0);
outAluOutW : out std_logic_vector(31 downto 0);
outWriteRegW : out std_logic_vector(4 downto 0));
END;
Architecture ARC_MEM_WB of MEM_WB is
BEGIN
PROCESS(clk)
BEGIN
IF( clk'event and clk = '1') THEN
outRegWrite <= RegWrite;
outMemtoReg <= MemtoReg;
outAluOutW <= AluOutW;
outReadDataW <= ReadDataW;
outWriteRegW <= WriteRegW;
END IF;
END PROCESS;
END;
| gpl-3.0 | a3d3cc21fb75ef06f4052af1c9cc5f9b | 0.577932 | 4.210417 | false | false | false | false |
JarrettR/FPGA-Cryptoparty | FPGA/hdl/sim_ztex.vhd | 1 | 5,800 | --------------------------------------------------------------------------------
-- sim_ztex.vhd
-- Simulation testbench for ztex_wrapper
-- Copyright (C) 2016 Jarrett Rainier
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sha1_pkg.all;
library std;
use std.textio.all;
entity sim_ztex is
end sim_ztex;
architecture SIM of sim_ztex is
component ztex_wrapper
port(
rst_i : in std_logic; --RESET
cs_i : in std_logic; --CS
cont_i : in std_logic; --CONT
clk_i : in std_logic; --IFCLK
dat_i : in unsigned(0 to 7); --FD
dat_o : out unsigned(0 to 7); --pc
SLOE : out std_logic; --SLOE
SLRD : out std_logic; --SLRD
SLWR : out std_logic; --SLWR
FIFOADR0 : out std_logic; --FIFOADR0
FIFOADR1 : out std_logic; --FIFOADR1
PKTEND : out std_logic; --PKTEND
FLAGA : in std_logic; --FLAGA EP2 FIFO Empty flag (FLAGA)
FLAGB : in std_logic --FLAGB
);
end component;
signal i: integer range 0 to 65535;
signal rst_i: std_logic := '0';
signal cs_i: std_logic := '0';
signal cont_i: std_logic := '0';
signal clk_i: std_logic := '0';
signal dat_i: unsigned(0 to 7);
signal dat_o: unsigned(0 to 7);
signal SLOE: std_logic;
signal SLRD: std_logic;
signal SLWR: std_logic;
signal FIFOADR0: std_logic;
signal FIFOADR1: std_logic;
signal PKTEND: std_logic;
signal FLAGA: std_logic;
signal FLAGB: std_logic;
type t_char_file is file of character;
--type t_byte_arr is unsigned(0 to 7);
signal read_arr_byte : handshake_data;
signal start_mk: mk_data;
signal end_mk: mk_data;
constant clock_period : time := 1 ns;
begin
ZTEX1: ztex_wrapper port map (rst_i, cs_i, cont_i, clk_i,
dat_i, dat_o,
SLOE, SLRD, SLWR, FIFOADR0, FIFOADR1, PKTEND, FLAGA, FLAGB);
stim_proc: process
file file_handshake : t_char_file open read_mode is "wpa2-psk-linksys.hccap";
file file_handshake2 : t_char_file open read_mode is "wpa2-psk-linksys.hccap";
variable char_buffer : character;
begin
rst_i <= '0';
cs_i <= '1';
i <= 0;
start_mk(0) <= "00110001"; --0x31, char 1
start_mk(1) <= "00110000";
start_mk(2) <= "00110000";
start_mk(3) <= "00110000";
start_mk(4) <= "00110000";
start_mk(5) <= "00110000";
start_mk(6) <= "00110000";
start_mk(7) <= "00110000";
start_mk(8) <= "00110000";
start_mk(9) <= "00110001";
end_mk(0) <= "00110001"; --0x31, char 1
end_mk(1) <= "00110000";
end_mk(2) <= "00110000";
end_mk(3) <= "00110000";
end_mk(4) <= "00110000";
end_mk(5) <= "00110000";
end_mk(6) <= "00110000";
end_mk(7) <= "00110011";
end_mk(8) <= "00110000";
end_mk(9) <= "00110000";
wait until rising_edge(clk_i);
rst_i <= '1';
wait until rising_edge(clk_i);
rst_i <= '0';
wait until rising_edge(clk_i);
while not endfile(file_handshake) loop
read(file_handshake, char_buffer);
dat_i <= to_unsigned(character'pos(char_buffer), 8);
i <= i + 1;
wait until rising_edge(clk_i);
end loop;
file_close(file_handshake);
for x in 0 to 9 loop
dat_i <= start_mk(x);
i <= i + 1;
wait until rising_edge(clk_i);
end loop;
for x in 0 to 9 loop
dat_i <= end_mk(x);
i <= i + 1;
wait until rising_edge(clk_i);
end loop;
--Do it all again
while SLOE = '0' loop
wait until rising_edge(clk_i);
end loop;
rst_i <= '1';
wait until rising_edge(clk_i);
rst_i <= '0';
wait until rising_edge(clk_i);
while not endfile(file_handshake2) loop
read(file_handshake2, char_buffer);
dat_i <= to_unsigned(character'pos(char_buffer), 8);
i <= i + 1;
wait until rising_edge(clk_i);
end loop;
file_close(file_handshake2);
for x in 0 to 9 loop
dat_i <= start_mk(x);
i <= i + 1;
wait until rising_edge(clk_i);
end loop;
for x in 0 to 9 loop
dat_i <= end_mk(x);
i <= i + 1;
wait until rising_edge(clk_i);
end loop;
wait;
end process;
--ssid_dat <= ssid_data(handshake_dat(0 to 35)); --36
clock_process: process
begin
clk_i <= '0';
wait for clock_period/2;
clk_i <= '1';
wait for clock_period/2;
end process;
end SIM; | gpl-3.0 | 372076e016afdd878e7ae138c99183b4 | 0.509138 | 3.629537 | false | false | false | false |
TUM-LIS/faultify | hardware/testcases/fpu100_mul/fpga_sim/xpsLibraryPath/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/vhdl/faultify_top.vhd | 1 | 20,999 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_top is
generic (
numInj : integer := 56;
numIn : integer := 10;
numOut : integer := 10);
port (
aclk : in std_logic; -- interface clock
arst_n : in std_logic; -- interface reset
clk : in std_logic; -- simulation clock (slow)
clk_x32 : in std_logic; -- prng clock (fast)
-- Write channel
awvalid : in std_logic;
awaddr : in std_logic_vector(31 downto 0);
wvalid : in std_logic;
wdata : in std_logic_vector(31 downto 0);
-- Read channel
arvalid : in std_logic;
araddr : in std_logic_vector(31 downto 0);
rvalid : out std_logic;
rdata : out std_logic_vector(31 downto 0)
);
attribute syn_hier : string;
attribute syn_hier of faultify_top : entity is "hard";
end faultify_top;
architecture behav of faultify_top is
component flag_cdc
port (
clkA : in std_logic;
clkB : in std_logic;
FlagIn_clkA : in std_logic;
FlagOut_clkB : out std_logic;
rst_n : in std_logic);
end component;
component faultify_simulator
generic (
numInj : integer;
numIn : integer;
numOut : integer);
port (
clk : in std_logic;
clk_m : in std_logic;
circ_ce : in std_logic;
circ_rst : in std_logic;
test : out std_logic_vector(31 downto 0);
testvector : in std_logic_vector(numIn-1 downto 0);
resultvector_o : out std_logic_vector(numOut-1 downto 0);
resultvector_f : out std_logic_vector(numOut-1 downto 0);
seed_in_en : in std_logic;
seed_in : in std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
shift_en : in std_logic;
rst_n : in std_logic);
end component;
component lfsr
generic (
width : integer;
seed : integer);
port (
clk : in std_logic;
rand_out : out std_logic_vector(width-1 downto 0));
end component;
type vector is array (0 to numOut-1) of std_logic_vector(31 downto 0);
signal errorSum : vector;
signal errorSumReg : vector;
signal errorSumReg_cdc_0 : vector;
signal errorSumReg_cdc_1 : vector;
signal errorVec : std_logic_vector(numOut-1 downto 0);
signal cnt : integer;
signal cnt_cdc_0 : integer;
signal cnt_cdc_1 : integer;
-- Asymmetric ram larger than 36 bit not supported in synplify I-2013
--type seed_ram_matr is array (0 to numInj-1) of std_logic_vector(63 downto 0);
--signal seed_ram : seed_ram_matr;
-- workaround 2 32-bit rams
type seed_ram_matr is array (0 to numInj-1) of std_logic_vector(31 downto 0);
signal seed_ram_low : seed_ram_matr;
signal seed_ram_high : seed_ram_matr;
--subtype seed_ram_matr_word_t is std_logic_vector(63 downto 0);
--type seed_ram_matr_memory_t is array (0 to numInj-1) of seed_ram_matr_word_t;
--signal seed_ram : seed_ram_matr_memory_t;
type prob_ram_matr is array (0 to numInj-1) of std_logic_vector(31 downto 0);
signal prob_ram : prob_ram_matr;
type reg_type is record
control : std_logic_vector(31 downto 0);
status : std_logic_vector(31 downto 0);
pe_location : std_logic_vector(31 downto 0);
pe_seed_low : std_logic_vector(31 downto 0);
pe_seed_high : std_logic_vector(31 downto 0);
pe_probability : std_logic_vector(31 downto 0);
output : std_logic_vector(31 downto 0);
ovalid : std_logic;
simtime : std_logic_vector(31 downto 0);
sel_soe : std_logic_vector(31 downto 0);
adr_soe : std_logic_vector(31 downto 0);
awaddr : std_logic_vector(31 downto 0);
test : std_logic_vector(31 downto 0);
circreset : std_logic_vector(31 downto 0);
cnt_tmp : std_logic_vector(31 downto 0);
sumoferrors : vector;
end record;
signal busy_loading : std_logic;
signal busy_simulating : std_logic;
signal busy_loading_reg : std_logic_vector(1 downto 0);
signal busy_simulating_reg : std_logic_vector(1 downto 0);
signal sim_done : std_logic;
signal r : reg_type;
type load_fsm_states is (IDLE, LOADSEED, LOADPROB);
signal l_state : load_fsm_states;
type sim_states is (IDLE, DELAY_Z, DELAY, SIMULATION, DELAY2, DELAY3, DELAY4, FREE_SIMULATION);
signal s_state : sim_states;
signal testvector : std_logic_vector(numIn-1 downto 0);
signal resultvector_o : std_logic_vector(numOut-1 downto 0);
signal resultvector_f : std_logic_vector(numOut-1 downto 0);
signal seed_in_en : std_logic;
signal seed_in : std_logic;
signal prob_in_en : std_logic;
signal prob_in : std_logic;
signal shift_en : std_logic;
signal shift_en_l : std_logic;
signal shift_en_s : std_logic;
signal load_seed_prob : std_logic;
signal start_simulation : std_logic;
signal start_free_simulation : std_logic;
signal stop_simulation : std_logic;
signal circ_ce, circ_rst, circ_rst_sim : std_logic;
signal tvec : std_logic_vector(127 downto 0);
signal test : std_logic_vector(31 downto 0);
signal rst_cdc, rst_cdc_n : std_logic;
type tb_state_defs is (IDLE, DATA, WAITING);
signal tb_state : tb_state_defs;
begin -- behav
-----------------------------------------------------------------------------
-- PRNG shifting
-----------------------------------------------------------------------------
shift_en <= shift_en_l or shift_en_s;
-----------------------------------------------------------------------------
-- Testvector
-----------------------------------------------------------------------------
--testvector <= (others => '0');
lfsr_1 : lfsr
generic map (
width => 128,
seed => 3498327)
port map (
clk => clk,
rand_out => tvec);
testvector(63 downto 0) <= tvec(63 downto 0);
testvector(66 downto 64) <= "010";
testvector(68 downto 67) <= "00";
--testvector(69) <= tvec(64);
process (clk, circ_rst_sim) is
begin -- process
if circ_rst_sim = '1' then -- asynchronous reset (active low)
testvector(69) <= '0';
tb_state <= IDLE;
elsif clk'event and clk = '1' then -- rising clock edge
case tb_state is
when IDLE =>
tb_state <= DATA;
testvector(69) <= '1';
when DATA =>
tb_state <= WAITING;
testvector(69) <= '0';
when WAITING =>
if resultvector_o(32) = '1' then
tb_state <= DATA;
testvector(69) <= '1';
end if;
end case;
end if;
end process;
-----------------------------------------------------------------------------
-- Simulator
-----------------------------------------------------------------------------
circ_rst <= circ_rst_sim when r.circreset(0) = '1' else '0';
faultify_simulator_1 : faultify_simulator
generic map (
numInj => numInj,
numIn => numIn,
numOut => numOut)
port map (
clk => clk_x32,
clk_m => clk,
circ_ce => circ_ce,
circ_rst => circ_rst,
test => test,
testvector => testvector,
resultvector_o => resultvector_o,
resultvector_f => resultvector_f,
seed_in_en => seed_in_en,
seed_in => seed_in,
prob_in_en => prob_in_en,
prob_in => prob_in,
shift_en => shift_en,
rst_n => arst_n);
-------------------------------------------------------------------------------
-- One Process Flow
-------------------------------------------------------------------------------
register_process : process (aclk, arst_n)
variable write_addr : std_logic_vector(31 downto 0);
begin -- process register_process
if arst_n = '0' then -- asynchronous reset (active low)
r.control <= (others => '0');
r.status <= (others => '0');
r.pe_probability <= (others => '0');
r.pe_seed_high <= (others => '0');
r.pe_seed_low <= (others => '0');
r.pe_location <= (others => '0');
r.ovalid <= '0';
r.simtime <= (others => '0');
r.sel_soe <= (others => '0');
r.adr_soe <= (others => '0');
r.sumoferrors <= (others => (others => '0'));
r.output <= (others => '0');
elsif aclk'event and aclk = '1' then -- rising clock edge
r.control <= (others => '0');
if awvalid = '1' then
r.awaddr <= awaddr;
write_addr := awaddr;
end if;
if wvalid = '1' then
if write_addr = x"00000000" then
r.control <= wdata;
elsif write_addr = x"00000001" then
r.pe_location <= wdata;
elsif write_addr = x"00000002" then
r.pe_seed_low <= wdata;
elsif write_addr = x"00000003" then
r.pe_seed_high <= wdata;
elsif write_addr = x"00000004" then
r.pe_probability <= wdata;
elsif write_addr = x"00000005" then
r.cnt_tmp <= std_logic_vector(to_unsigned(cnt_cdc_1, 32));
r.adr_soe <= wdata;
elsif write_addr = x"00000007" then
r.simtime <= wdata;
elsif write_addr = x"00000009" then
r.circreset <= wdata;
end if;
end if;
if arvalid = '1' then
if araddr = x"0000000F" then
r.output <= r.status;
elsif araddr = x"00000001" then
r.output <= r.pe_location;
elsif araddr = x"00000002" then
r.output <= r.pe_seed_low;
elsif araddr = x"00000003" then
r.output <= r.pe_seed_high;
elsif araddr = x"00000004" then
r.output <= r.pe_probability;
elsif araddr = x"00000006" then
r.output <= r.sel_soe;
elsif araddr = x"00000008" then
r.output <= r.test;
elsif araddr = x"0000000A" then
r.output <= r.cnt_tmp;
end if;
r.ovalid <= '1';
else
r.ovalid <= '0';
end if;
if busy_loading_reg(1) = '1' then
r.status(0) <= '1';
else
r.status(0) <= '0';
end if;
if busy_simulating_reg(1) = '1' then
r.status(1) <= '1';
else
r.status(1) <= '0';
end if;
r.sel_soe <= r.sumoferrors(to_integer(unsigned(r.adr_soe)));
rdata <= r.output;
rvalid <= r.ovalid;
r.sumoferrors <= errorSumReg_cdc_1;
r.test <= errorSum(0);
end if;
end process register_process;
-----------------------------------------------------------------------------
-- simple clock domain crossing
-----------------------------------------------------------------------------
process (aclk, arst_n)
begin -- process
if arst_n = '0' then -- asynchronous reset (active low)
busy_simulating_reg <= (others => '0');
busy_loading_reg <= (others => '0');
elsif aclk'event and aclk = '1' then -- rising clock edge
busy_simulating_reg(0) <= busy_simulating;
busy_loading_reg(0) <= busy_loading;
busy_simulating_reg(1) <= busy_simulating_reg(0);
busy_loading_reg(1) <= busy_loading_reg(0);
cnt_cdc_0 <= cnt;
cnt_cdc_1 <= cnt_cdc_0;
errorSumReg_cdc_0 <= errorSumReg;
errorSumReg_cdc_1 <= errorSumReg_cdc_0;
end if;
end process;
-------------------------------------------------------------------------------
-- Store seeed/prob
-------------------------------------------------------------------------------
store_seed : process (aclk, arst_n)
begin -- process store_seed
if arst_n = '0' then -- asynchronous reset (active low)
elsif aclk'event and aclk = '1' then -- rising clock edge
if r.control(0) = '1' then
-- Synplify bug workaround
--seed_ram(to_integer(unsigned(r.pe_location))) <= r.pe_seed_high & r.pe_seed_low;
seed_ram_low(to_integer(unsigned(r.pe_location))) <= r.pe_seed_low;
seed_ram_high(to_integer(unsigned(r.pe_location))) <= r.pe_seed_high;
prob_ram(to_integer(unsigned(r.pe_location))) <= r.pe_probability;
end if;
end if;
end process store_seed;
-----------------------------------------------------------------------------
-- Seed/prob loading FSM
-----------------------------------------------------------------------------
--flag_cdc_1 : flag_cdc
-- port map (
-- clkA => aclk,
-- clkB => clk_x32,
-- FlagIn_clkA => r.control(1),
-- FlagOut_clkB => load_seed_prob,
-- rst_n => arst_n);
load_seed_prob <= r.control(1);
seed_prob_loading : process (clk_x32, arst_n)
variable cnt_seed : integer range 0 to 64;
variable cnt_inj : integer range 0 to numInj;
variable cnt_prob : integer range 0 to 32;
begin -- process seed_prob_loading
if arst_n = '0' then -- asynchronous reset (active low)
l_state <= IDLE;
seed_in <= '0';
seed_in_en <= '0';
prob_in <= '0';
prob_in_en <= '0';
shift_en_l <= '0';
busy_loading <= '0';
elsif clk_x32'event and clk_x32 = '1' then -- rising clock edge
case l_state is
when IDLE =>
cnt_seed := 0;
cnt_inj := 0;
cnt_prob := 0;
busy_loading <= '0';
seed_in_en <= '0';
prob_in_en <= '0';
shift_en_l <= '0';
if load_seed_prob = '1' then
busy_loading <= '1';
l_state <= LOADSEED;
end if;
when LOADSEED =>
if cnt_seed < 64 then
shift_en_l <= '1';
seed_in_en <= '1';
-- not working in synplify I-2013
--seed_in <= seed_ram(cnt_inj)(cnt_seed);
--
if cnt_seed < 32 then
seed_in <= seed_ram_low(cnt_inj)(cnt_seed);
else
seed_in <= seed_ram_high(cnt_inj)(cnt_seed-32);
end if;
cnt_seed := cnt_seed + 1;
end if;
if cnt_seed = 64 then
cnt_seed := 0;
cnt_inj := cnt_inj + 1;
end if;
if cnt_inj = numInj then
l_state <= LOADPROB;
--seed_in_en <= '0';
cnt_inj := 0;
end if;
when LOADPROB =>
seed_in_en <= '0';
if cnt_prob < 32 then
prob_in_en <= '1';
prob_in <= prob_ram(cnt_inj)(cnt_prob);
cnt_prob := cnt_prob + 1;
end if;
if cnt_prob = 32 then
cnt_prob := 0;
cnt_inj := cnt_inj + 1;
end if;
if cnt_inj = numInj then
l_state <= IDLE;
cnt_inj := 0;
--prob_in_en <= '0';
end if;
end case;
end if;
end process seed_prob_loading;
-----------------------------------------------------------------------------
-- Simulation FSM
-----------------------------------------------------------------------------
flag_cdc_2 : flag_cdc
port map (
clkA => aclk,
clkB => clk,
FlagIn_clkA => r.control(2),
FlagOut_clkB => start_simulation,
rst_n => arst_n);
flag_cdc_3 : flag_cdc
port map (
clkA => aclk,
clkB => clk,
FlagIn_clkA => r.control(3),
FlagOut_clkB => start_free_simulation,
rst_n => arst_n);
flag_cdc_4 : flag_cdc
port map (
clkA => aclk,
clkB => clk,
FlagIn_clkA => r.control(4),
FlagOut_clkB => stop_simulation,
rst_n => arst_n);
rst_cdc_5 : flag_cdc
port map (
clkA => aclk,
clkB => clk,
FlagIn_clkA => not arst_n,
FlagOut_clkB => rst_cdc,
rst_n => '1');
rst_cdc_n <= not rst_cdc;
process (clk, rst_cdc_n)
variable simtime : integer;
variable cnt_delay : integer range 0 to 9;
begin -- process
if clk'event and clk = '1' then -- rising clock edge
if rst_cdc_n = '0' then -- asynchronous reset (active low)
s_state <= IDLE;
errorVec <= (others => '0');
errorSum <= (others => (others => '0'));
circ_ce <= '0';
circ_rst_sim <= '1';
shift_en_s <= '0';
busy_simulating <= '0';
sim_done <= '0';
errorSumReg <= (others => (others => '0'));
else
case s_state is
when IDLE =>
sim_done <= '0';
circ_ce <= '0';
circ_rst_sim <= '1';
shift_en_s <= '0';
errorVec <= (others => '0');
--errorSum <= errorSum;
errorSum <= (others => (others => '0'));
--cnt <= 0;
busy_simulating <= '0';
cnt_delay := 0;
if start_simulation = '1' then
cnt <= 0;
busy_simulating <= '1';
errorSum <= (others => (others => '0'));
errorSumReg <= (others => (others => '0'));
simtime := to_integer(unsigned(r.simtime));
s_state <= DELAY_Z;
circ_ce <= '1';
circ_rst_sim <= '0';
shift_en_s <= '1';
end if;
if start_free_simulation = '1' then
cnt <= 0;
busy_simulating <= '1';
errorSum <= (others => (others => '0'));
errorSumReg <= (others => (others => '0'));
s_state <= FREE_SIMULATION;
circ_ce <= '1';
circ_rst_sim <= '0';
shift_en_s <= '1';
end if;
when DELAY_z =>
cnt_delay := cnt_delay + 1;
if cnt_delay = 9 then
s_state <= DELAY;
end if;
when DELAY =>
s_state <= SIMULATION;
errorVec <= (others => '0');
errorSum <= (others => (others => '0'));
when SIMULATION =>
circ_rst_sim <= '0';
shift_en_s <= '1';
-- collect errors
if (resultVector_o(32) = '1') then
errorVec <= resultvector_o xor resultvector_f;
else
errorVec <= (others => '0');
end if;
for i in 0 to (numOut-1) loop
if (errorVec(i) = '1') then
errorSum(i) <= std_logic_vector(unsigned(errorSum(i)) + 1);
end if;
end loop;
--
errorSumReg <= errorSum;
if cnt = simtime-1 then
s_state <= DELAY2;
circ_ce <= '0';
circ_rst_sim <= '1';
shift_en_s <= '0';
end if;
cnt <= cnt +1;
when DELAY2 =>
if (resultVector_o(32) = '1') then
errorVec <= resultvector_o xor resultvector_f;
else
errorVec <= (others => '0');
end if;
for i in 0 to (numOut-1) loop
if (errorVec(i) = '1') then
errorSum(i) <= std_logic_vector(unsigned(errorSum(i)) + 1);
end if;
end loop;
s_state <= DELAY3;
when DELAY3 =>
s_state <= DELAY4;
errorSumReg <= errorSum;
errorSum <= (others => (others => '0'));
when DELAY4 =>
s_state <= IDLE;
sim_done <= '1';
when FREE_SIMULATION =>
circ_rst_sim <= '0';
shift_en_s <= '1';
-- collect errors
if (resultVector_o(32) = '1') then
errorVec <= resultvector_o xor resultvector_f;
else
errorVec <= (others => '0');
end if;
for i in 0 to (numOut-1) loop
if (errorVec(i) = '1') then
errorSum(i) <= std_logic_vector(unsigned(errorSum(i)) + 1);
end if;
end loop;
--
errorSumReg <= errorSum;
if stop_simulation = '1' then
s_state <= IDLE;
sim_done <= '1';
circ_ce <= '0';
circ_rst_sim <= '1';
shift_en_s <= '0';
end if;
cnt <= cnt +1;
when others =>
s_state <= IDLE;
end case;
end if;
end if;
end process;
end behav;
| gpl-2.0 | 499dc0d38edf650b7d9201c464a3b997 | 0.462689 | 3.836134 | false | false | false | false |
bruskajp/EE-316 | Project1/top_level.vhd | 1 | 2,277 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity top_level is
port(
CLOCK_50 : in std_logic;
KEY : in std_logic_vector (3 downto 0);
LEDG : out std_logic_vector(7 downto 0) := X"00";
SRAM_ADDR : out std_logic_vector(17 downto 0);
SRAM_DQ : inout std_logic_vector(15 downto 0);
SRAM_WE_N : out std_logic;
SRAM_OE_N : out std_logic;
SRAM_UB_N : out std_logic;
SRAM_LB_N : out std_logic;
SRAM_CE_N : out std_logic;
ROW_SEL : in std_logic_vector(4 downto 0);
COL_SEL : out std_logic_vector(3 downto 0);
LCD_DATA : out std_logic_vector(7 downto 0);
LCD_EN : out std_logic;
LCD_RS : out std_logic;
LCD_ON : out std_logic;
HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7 : out std_logic_vector(7 downto 0)
);
end top_level;
architecture Behavioral of top_level is
component system_controller is
port (
clk_50 : in std_logic;
reset_key : in std_logic;
op_prog_mode : out std_logic;
sram_addr : out std_logic_vector (17 downto 0);
sram_dq : inout std_logic_vector (15 downto 0);
sram_we_n : out std_logic;
sram_oe_n : out std_logic;
sram_ub_n : out std_logic;
sram_lb_n : out std_logic;
sram_ce_n : out std_logic;
row_sel : in std_logic_vector (4 downto 0);
col_sel : out std_logic_vector(3 downto 0);
lcd_data_out : out std_logic_vector(7 downto 0);
lcd_enable_out : out std_logic;
lcd_select_out : out std_logic;
hex0, hex1, hex2, hex3, hex4, hex5 : out std_logic_vector (7 downto 0)
);
end component;
begin
LCD_ON <= '1';
HEX6 <= X"FF";
HEX7 <= X"FF";
Inst_system_controller: system_controller
port map (
clk_50 => CLOCK_50,
reset_key => KEY(0),
op_prog_mode => LEDG(0),
sram_addr => SRAM_ADDR,
sram_dq => SRAM_DQ,
sram_we_n => SRAM_WE_N,
sram_oe_n => SRAM_OE_N,
sram_ub_n => SRAM_UB_N,
sram_lb_n => SRAM_LB_N,
sram_ce_n => SRAM_CE_N,
row_sel => ROW_SEL,
col_sel => COL_SEL,
lcd_data_out => LCD_DATA,
lcd_enable_out => LCD_EN,
lcd_select_out => LCD_RS,
hex0 => HEX0,
hex1 => HEX1,
hex2 => HEX2,
hex3 => HEX3,
hex4 => HEX4,
hex5 => HEX5
);
end Behavioral; | gpl-3.0 | 1cff85e56164933713f4017befdd4b0d | 0.587176 | 2.440514 | false | false | false | false |
lnls-dig/dsp-cores | hdl/modules/divider/utilities_package.vhd | 1 | 3,420 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package utilities is
function find_msb (signal arg: in std_logic_vector; signal sign: in std_logic) return std_logic_vector;
function log2(arg : natural) return natural;
component data_generator is
generic
(
G_DATA_WIDTH : natural range 2 to 48 := 25
);
port
(
i_clk : in std_logic;
i_rst : in std_logic;
i_data_init : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
i_data_step : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
i_niterations : in std_logic_vector(9 downto 0);
o_data : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
o_trg : out std_logic
);
end component;
end utilities;
package body utilities is
function find_msb (signal arg: in std_logic_vector; signal sign: in std_logic) return std_logic_vector is
variable index: natural := arg'left;
begin
while true loop
if arg(index) = not(sign) then
exit;
elsif index = 0 then
exit;
end if;
index := index - 1;
end loop;
return std_logic_vector(to_unsigned(index,log2(arg'length)+1));
end find_msb;
function log2(arg : natural) return natural is
variable result : natural ;
variable index : natural := 0;
begin
while true loop
if 2**index >= arg then
result := index;
exit ;
end if ;
index := index + 1;
end loop ;
return index;
end function;
end utilities;
----------------------------------------------------------------------------------------------
-- data_generator
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity data_generator is
generic
(
G_DATA_WIDTH : natural range 2 to 48
);
port
(
i_clk : in std_logic;
i_rst : in std_logic;
i_data_init : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
i_data_step : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
i_niterations : in std_logic_vector(9 downto 0);
o_data : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
o_trg : out std_logic
);
end data_generator;
architecture rtl of data_generator is
signal uv_iterations_count : unsigned(9 downto 0);
signal uv_data_count : signed(G_DATA_WIDTH-1 downto 0);
begin
prc_counter: process(i_rst, i_clk)
begin
if i_rst = '1' then
uv_iterations_count <= unsigned(i_niterations);
uv_data_count <= signed(i_data_init);
elsif rising_edge(i_clk) then
if uv_iterations_count = 0 then
o_trg <= '1';
uv_data_count <= uv_data_count + signed(i_data_step);
uv_iterations_count <= unsigned(i_niterations);
else
o_trg <= '0';
uv_iterations_count <= uv_iterations_count - 1;
end if;
end if;
end process;
o_data <= std_logic_vector(uv_data_count);
end rtl; | lgpl-3.0 | 9633edca8d7b5d295894bf2371c10323 | 0.50614 | 3.935558 | false | false | false | false |
JarrettR/FPGA-Cryptoparty | FPGA/hdl/prf_main.vhd | 1 | 6,803 | --------------------------------------------------------------------------------
-- prf_main.vhd
-- Pseudorandom function. PMK, MACs, and Nonces in, PTK out
-- Copyright (C) 2016 Jarrett Rainier
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sha1_pkg.all;
entity prf_main is
port(
clk_i : in std_ulogic;
rst_i : in std_ulogic;
load_i : in std_ulogic;
pmk_i : in w_input;
anonce_dat : in nonce_data;
cnonce_dat : in nonce_data;
amac_dat : in mac_data;
cmac_dat : in mac_data;
ptk_dat_o : out ptk_data;
ptk_valid_o : out std_ulogic
);
end prf_main;
architecture RTL of prf_main is
component hmac_main
port(
clk_i : in std_ulogic;
rst_i : in std_ulogic;
secret_i : in w_input;
value_i : in w_input;
value_len_i : in std_ulogic_vector(0 to 63);
load_i : in std_ulogic;
dat_o : out w_output;
valid_o : out std_ulogic
);
end component;
type state_type is (STATE_IDLE,
STATE_START, STATE_PROCESS,
STATE_CLEANUP, STATE_FINISHED);
signal state : state_type := STATE_IDLE;
--signal pmk : w_input;
signal ssid_length : std_ulogic_vector(0 to 63);
signal mk_in : w_input;
signal out_x1 : w_output;
signal out_x2 : w_output;
signal f1 : w_output;
signal f2 : w_output;
signal f1_con : w_output;
signal f2_con : w_output;
signal x1 : w_input;
signal x2 : w_input;
signal x1_in : w_input;
signal x2_in : w_input;
signal r : w_input;
constant a : w_input := (X"50616972", X"77697365", X"206b6579",
X"20657870", X"616e7369", X"6f6e0000",
others=>(X"00000000"));--Pairwise key expansion
--pmk: 5df920b5481ed70538dd5fd02423d7e2522205feeebb974cad08a52b5613ede2
--a: Pairwise key expansion
--b: 000b86c2a4850013ce5598efae12a150652e9bc22063720c5081e9eb74077fb19fffe871dc4ca1e6f448af85e8dfa16b8769957d8249a4ec68d2b7641d3782162ef0dc37b014cc48343e8dd2
--r: 5e9805e89cb0e84b45e5f9e4a1a80d9d9958c24e
--r: 5e9805e89cb0e84b45e5f9e4a1a80d9d9958c24e2b5ca71661334a890814f53e1d035e8beb4f8361
--r: 5e9805e89cb0e84b45e5f9e4a1a80d9d9958c24e2b5ca71661334a890814f53e1d035e8beb4f83611dc93e2657cecf69a3651bc4fca5880ce9081345
--r: 5e9805e89cb0e84b45e5f9e4a1a80d9d9958c24e2b5ca71661334a890814f53e1d035e8beb4f83611dc93e2657cecf69a3651bc4fca5880ce9081345c5411d489313b29e4aaf287d5231a342b777a67a
signal valid : std_ulogic;
signal valid_x1 : std_ulogic;
signal load : std_ulogic;
signal i: integer range 0 to 4096;
begin
HMAC: hmac_main port map (clk_i,rst_i,pmk_i,a,ssid_length,load,out_x1,valid_x1);
process(clk_i)
begin
if (clk_i'event and clk_i = '1') then
if rst_i = '1' then
state <= STATE_IDLE;
i <= 0;
ptk_valid_o <= '0';
elsif load_i = '1' and state = STATE_IDLE then
i <= 0;
ptk_valid_o <= '0';
--a + X"00" + b + X"00"
for x in 0 to 4 loop
r(x) <= a(x);
end loop;
--Todo figure out a more elegant way to do this awkward bitshift
--b = min(apMac, cMac) + max(apMac, cMac) + min(apNonce, cNonce) + max(apNonce, cNonce)
r(5) <= a(5)(0 to 23) & std_ulogic_vector(amac_dat(0));
r(6) <= std_ulogic_vector(amac_dat(1)) &
std_ulogic_vector(amac_dat(2)) &
std_ulogic_vector(amac_dat(3)) &
std_ulogic_vector(amac_dat(4));
r(7) <= std_ulogic_vector(amac_dat(5)) &
std_ulogic_vector(cmac_dat(1)) &
std_ulogic_vector(cmac_dat(2)) &
std_ulogic_vector(cmac_dat(3));
r(8) <= std_ulogic_vector(cmac_dat(4)) &
std_ulogic_vector(cmac_dat(5)) &
std_ulogic_vector(anonce_dat(0)) &
std_ulogic_vector(anonce_dat(1));
for x in 0 to 6 loop
r(x + 8) <= std_ulogic_vector(anonce_dat((x * 4) + 2)) &
std_ulogic_vector(anonce_dat((x * 4) + 3)) &
std_ulogic_vector(anonce_dat((x * 4) + 4)) &
std_ulogic_vector(anonce_dat((x * 4) + 5));
end loop;
-- r(5) <= std_ulogic_vector(anonce_dat((x * 4) + 2)) &
-- std_ulogic_vector(anonce_dat((x * 4) + 3)) &
-- std_ulogic_vector(anonce_dat((x * 4) + 4)) &
-- std_ulogic_vector(anonce_dat((x * 4) + 5)); --31
--r(x + 1)(0 to 23) <= X"00000000";
state <= STATE_START;
elsif state = STATE_START then
state <= STATE_PROCESS;
elsif state = STATE_PROCESS then
state <= STATE_FINISHED;
elsif state = STATE_FINISHED then
ptk_valid_o <= '1';
state <= STATE_IDLE;
end if;
end if;
end process;
f1_con <= f1;
f2_con <= f2;
end RTL; | gpl-3.0 | c51d8c2c9c4b3f846c01a188d970a00d | 0.485668 | 3.512132 | false | false | false | false |
SoCdesign/EHA | RTL/Credit_Based/Credit_Based_FC/Router_32_bit_credit_based_parity.vhd | 1 | 16,138 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_credit_based_parity is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 60;
Cx_rst : integer := 10;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L:out std_logic;
healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L:out std_logic
);
end router_credit_based_parity;
architecture behavior of router_credit_based_parity is
COMPONENT parity_checker_packet_detector is
generic(DATA_WIDTH : integer := 32
);
port(
reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
faulty_packet, healthy_packet: out std_logic
);
end COMPONENT;
COMPONENT FIFO_credit_based
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
COMPONENT allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic
);
end COMPONENT;
COMPONENT LBDR is
generic (
cur_addr_rst: integer := 0;
Rxy_rst: integer := 60;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
begin
-- all the parity_checkers
PC_N: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_N, valid_in =>valid_in_N, faulty_packet => faulty_packet_N , healthy_packet => healthy_packet_N);
PC_E: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_E, valid_in =>valid_in_E, faulty_packet => faulty_packet_E , healthy_packet => healthy_packet_E);
PC_W: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_W, valid_in =>valid_in_W, faulty_packet => faulty_packet_W , healthy_packet => healthy_packet_W);
PC_S: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_S, valid_in =>valid_in_S, faulty_packet => faulty_packet_S , healthy_packet => healthy_packet_S);
PC_L: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_L, valid_in =>valid_in_L, faulty_packet => faulty_packet_L , healthy_packet => healthy_packet_L);
-- all the FIFOs
FIFO_N: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_N, valid_in => valid_in_N,
read_en_N => '0', read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
credit_out => credit_out_N, empty_out => empty_N, Data_out => FIFO_D_out_N);
FIFO_E: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_E, valid_in => valid_in_E,
read_en_N => Grant_NE, read_en_E =>'0', read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
credit_out => credit_out_E, empty_out => empty_E, Data_out => FIFO_D_out_E);
FIFO_W: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_W, valid_in => valid_in_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>'0', read_en_S =>Grant_SW, read_en_L =>Grant_LW,
credit_out => credit_out_W, empty_out => empty_W, Data_out => FIFO_D_out_W);
FIFO_S: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_S, valid_in => valid_in_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>'0', read_en_L =>Grant_LS,
credit_out => credit_out_S, empty_out => empty_S, Data_out => FIFO_D_out_S);
FIFO_L: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_L, valid_in => valid_in_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>'0',
credit_out => credit_out_L, empty_out => empty_L, Data_out => FIFO_D_out_L);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the LBDRs
LBDR_N: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N, flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
grant_N => '0', grant_E =>Grant_EN, grant_W => Grant_WN, grant_S=>Grant_SN, grant_L =>Grant_LN,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL);
LBDR_E: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E, flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
grant_N => Grant_NE, grant_E =>'0', grant_W => Grant_WE, grant_S=>Grant_SE, grant_L =>Grant_LE,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL);
LBDR_W: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W, flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
grant_N => Grant_NW, grant_E =>Grant_EW, grant_W =>'0' ,grant_S=>Grant_SW, grant_L =>Grant_LW,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL);
LBDR_S: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S, flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
grant_N => Grant_NS, grant_E =>Grant_ES, grant_W =>Grant_WS ,grant_S=>'0', grant_L =>Grant_LS,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL);
LBDR_L: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L, flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
grant_N => Grant_NL, grant_E =>Grant_EL, grant_W => Grant_WL,grant_S=>Grant_SL, grant_L =>'0',
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- switch allocator
allocator_unit: allocator port map ( reset => reset, clk => clk,
-- flow control
credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L,
-- requests from the LBDRS
req_N_N => '0', req_N_E => Req_NE, req_N_W => Req_NW, req_N_S => Req_NS, req_N_L => Req_NL,
req_E_N => Req_EN, req_E_E => '0', req_E_W => Req_EW, req_E_S => Req_ES, req_E_L => Req_EL,
req_W_N => Req_WN, req_W_E => Req_WE, req_W_W => '0', req_W_S => Req_WS, req_W_L => Req_WL,
req_S_N => Req_SN, req_S_E => Req_SE, req_S_W => Req_SW, req_S_S => '0', req_S_L => Req_SL,
req_L_N => Req_LN, req_L_E => Req_LE, req_L_W => Req_LW, req_L_S => Req_LS, req_L_L => '0',
empty_N => empty_N, empty_E => empty_E, empty_w => empty_W, empty_S => empty_S, empty_L => empty_L,
valid_N => valid_out_N, valid_E => valid_out_E, valid_W => valid_out_W, valid_S => valid_out_S, valid_L => valid_out_L,
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
grant_N_N => Grant_NN, grant_N_E => Grant_NE, grant_N_W => Grant_NW, grant_N_S => Grant_NS, grant_N_L => Grant_NL,
grant_E_N => Grant_EN, grant_E_E => Grant_EE, grant_E_W => Grant_EW, grant_E_S => Grant_ES, grant_E_L => Grant_EL,
grant_W_N => Grant_WN, grant_W_E => Grant_WE, grant_W_W => Grant_WW, grant_W_S => Grant_WS, grant_W_L => Grant_WL,
grant_S_N => Grant_SN, grant_S_E => Grant_SE, grant_S_W => Grant_SW, grant_S_S => Grant_SS, grant_S_L => Grant_SL,
grant_L_N => Grant_LN, grant_L_E => Grant_LE, grant_L_W => Grant_LW, grant_L_S => Grant_LS, grant_L_L => Grant_LL
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbar select_signals
Xbar_sel_N <= '0' & Grant_NE & Grant_NW & Grant_NS & Grant_NL;
Xbar_sel_E <= Grant_EN & '0' & Grant_EW & Grant_ES & Grant_EL;
Xbar_sel_W <= Grant_WN & Grant_WE & '0' & Grant_WS & Grant_WL;
Xbar_sel_S <= Grant_SN & Grant_SE & Grant_SW & '0' & Grant_SL;
Xbar_sel_L <= Grant_LN & Grant_LE & Grant_LW & Grant_LS & '0';
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
end;
| gpl-3.0 | 0f68b19010b0d5b943ecbbe7c2f101b4 | 0.536436 | 2.965454 | false | false | false | false |
SoCdesign/EHA | RTL/Immortal_Chip/modules_with_fault_injectors/Channel_32_bit_with_dominant_checkers_shift_register.vhd | 1 | 19,325 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_misc.all;
entity router_channel is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 5;
Rxy_rst : integer := 60;
Cx_rst : integer := 15;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
DCTS : in std_logic;
DRTS : in std_logic;
RTS : out std_logic;
CTS : out std_logic;
flit_type : in std_logic_vector(2 downto 0);
destination_address : in std_logic_vector(NoC_size-1 downto 0);
Grant_N_in , Grant_E_in , Grant_W_in , Grant_S_in , Grant_L_in : in std_logic;
Req_N_in , Req_E_in , Req_W_in , Req_S_in , Req_L_in :in std_logic;
-- fault injector signals
fault_shift: in std_logic;
fault_clk: in std_logic;
fault_data_in_serial: in std_logic;
fault_data_out_serial: out std_logic;
Grant_N_out, Grant_E_out, Grant_W_out, Grant_S_out, Grant_L_out: out std_logic;
Req_N_out , Req_E_out, Req_W_out, Req_S_out, Req_L_out:out std_logic;
read_pointer_out, write_pointer_out: out std_logic_vector(3 downto 0);
write_en_out :out std_logic;
Xbar_sel: out std_logic_vector(4 downto 0);
-- the checker output shift register
shift : in std_logic;
checker_clk: in std_logic;
error_signal_sync: out std_logic; -- this is the or of all outputs of the shift register
error_signal_async: out std_logic; -- this is the or of all outputs of the checkers
shift_serial_data: out std_logic
);
end router_channel;
architecture behavior of router_channel is
COMPONENT FIFO is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
DRTS: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
CTS: out std_logic;
empty_out: out std_logic;
read_pointer_out, write_pointer_out: out std_logic_vector(3 downto 0);
write_en_out :out std_logic;
-- fault injector signals
shift: in std_logic;
fault_clk: in std_logic;
data_in_serial: in std_logic;
data_out_serial: out std_logic;
-- Checker outputs
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
--err_CTS_in,
err_write_en,
err_not_CTS_in,
--err_not_write_en,
err_read_en_mismatch : out std_logic
);
end COMPONENT;
COMPONENT Arbiter
port (reset: in std_logic;
clk: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules
DCTS: in std_logic; -- Getting the CTS signal from the input FIFO of the next router/NI (for hand-shaking)
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
Xbar_sel : out std_logic_vector(4 downto 0); -- select lines for XBAR
RTS: out std_logic; -- Valid output which is sent to the next router/NI to specify that the data on the output port is valid
-- fault injector signals
shift: in std_logic;
fault_clk: in std_logic;
data_in_serial: in std_logic;
data_out_serial: out std_logic;
-- Checker outputs
err_state_IDLE_xbar,
err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE,
err_IDLE_Req_L,
err_Local_Req_L,
err_North_Req_N,
err_IDLE_Req_N,
err_Local_Req_N,
err_South_Req_L,
err_West_Req_L,
err_South_Req_N,
err_East_Req_L,
err_West_Req_N,
err_East_Req_N,
err_next_state_onehot,
err_state_in_onehot,
err_state_north_xbar_sel,
err_state_east_xbar_sel,
err_state_west_xbar_sel,
err_state_south_xbar_sel : out std_logic
);
end COMPONENT;
COMPONENT LBDR is
generic (
cur_addr_rst: integer := 5;
Rxy_rst: integer := 60;
Cx_rst: integer := 15;
NoC_size: integer := 4
);
port (reset: in std_logic;
clk: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic;
-- fault injector signals
shift: in std_logic;
fault_clk: in std_logic;
data_in_serial: in std_logic;
data_out_serial: out std_logic;
-- Checker outputs
--err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in : out std_logic
);
end COMPONENT;
COMPONENT shift_register is
generic (
REG_WIDTH: integer := 8
);
port (
clk, reset : in std_logic;
shift: in std_logic;
data_in: in std_logic_vector(REG_WIDTH-1 downto 0);
data_out_parallel: in std_logic_vector(REG_WIDTH-1 downto 0);
data_out_serial: out std_logic
);
end COMPONENT;
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal empty: std_logic;
signal combined_error_signals: std_logic_vector(58 downto 0);
signal shift_parallel_data: std_logic_vector(58 downto 0);
-- Signals related to Checkers
-- LBDR Checkers signals
signal err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in, err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in : std_logic;
-- Arbiter Checkers signals
signal err_state_IDLE_xbar, err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in, err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in, err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in, err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state, err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants, err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot, err_Requests_next_state_IDLE,
err_IDLE_Req_L, err_Local_Req_L, err_North_Req_N, err_IDLE_Req_N, err_Local_Req_N,
err_South_Req_L, err_West_Req_L, err_South_Req_N, err_East_Req_L,
err_West_Req_N, err_East_Req_N, err_next_state_onehot, err_state_in_onehot,
err_state_north_xbar_sel, err_state_east_xbar_sel,
err_state_west_xbar_sel, err_state_south_xbar_sel : std_logic;
-- FIFO Control Part Checkers signals
signal err_write_en_write_pointer, err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full,
err_read_pointer_increment, err_read_pointer_not_increment,
err_write_en, err_not_CTS_in, err_read_en_mismatch : std_logic;
signal fault_DO_serial_FIFO_2_LBDR, fault_DO_serial_LBDR_2_Arbiter: std_logic;
begin
-- OR of checker outputs
error_signal_sync <= OR_REDUCE(shift_parallel_data);
error_signal_async <= OR_REDUCE(combined_error_signals);
-- making the shift register input signal
-- please keep this like this, i use this for counting the number of the signals.
combined_error_signals <= err_header_empty_Requests_FF_Requests_in &
err_tail_Requests_in_all_zero &
err_header_tail_Requests_FF_Requests_in &
err_dst_addr_cur_addr_N1 &
err_dst_addr_cur_addr_not_N1 &
err_dst_addr_cur_addr_E1 &
err_dst_addr_cur_addr_not_E1 &
err_dst_addr_cur_addr_W1 &
err_dst_addr_cur_addr_not_W1 &
err_dst_addr_cur_addr_S1 &
err_dst_addr_cur_addr_not_S1 &
err_dst_addr_cur_addr_not_Req_L_in &
err_dst_addr_cur_addr_Req_L_in &
err_header_not_empty_Req_N_in &
err_header_not_empty_Req_E_in &
err_header_not_empty_Req_W_in &
err_header_not_empty_Req_S_in &
err_state_IDLE_xbar &
err_state_not_IDLE_xbar &
err_state_IDLE_RTS_FF_in &
err_state_not_IDLE_RTS_FF_RTS_FF_in &
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in &
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in &
err_RTS_FF_not_DCTS_state_state_in &
err_not_RTS_FF_state_in_next_state &
err_RTS_FF_DCTS_state_in_next_state &
err_not_DCTS_Grants &
err_DCTS_not_RTS_FF_Grants &
err_DCTS_RTS_FF_IDLE_Grants &
err_DCTS_RTS_FF_not_IDLE_Grants_onehot &
err_Requests_next_state_IDLE &
err_IDLE_Req_L &
err_Local_Req_L &
err_North_Req_N &
err_IDLE_Req_N &
err_Local_Req_N &
err_South_Req_L &
err_West_Req_L &
err_South_Req_N &
err_East_Req_L &
err_West_Req_N &
err_East_Req_N &
err_next_state_onehot &
err_state_in_onehot &
err_state_north_xbar_sel &
err_state_east_xbar_sel &
err_state_west_xbar_sel &
err_state_south_xbar_sel &
err_write_en_write_pointer &
err_not_write_en_write_pointer &
err_read_pointer_write_pointer_not_empty &
err_read_pointer_write_pointer_empty &
err_read_pointer_write_pointer_not_full &
err_read_pointer_write_pointer_full &
err_read_pointer_increment &
err_read_pointer_not_increment &
err_write_en &
err_not_CTS_in &
err_read_en_mismatch;
---------------------------------------------------------------------------------------------------------------------------
FIFO_unit: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, DRTS => DRTS,
read_en_N => Grant_N_in, read_en_E =>Grant_E_in, read_en_W =>Grant_W_in, read_en_S =>Grant_S_in, read_en_L =>Grant_L_in,
CTS => CTS, empty_out => empty,
read_pointer_out => read_pointer_out, write_pointer_out => write_pointer_out,
write_en_out => write_en_out,
shift=>fault_shift, fault_clk=>fault_clk, data_in_serial=> fault_data_in_serial, data_out_serial=>fault_DO_serial_FIFO_2_LBDR,
err_write_en_write_pointer => err_write_en_write_pointer,
err_not_write_en_write_pointer => err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => err_read_pointer_write_pointer_full,
err_read_pointer_increment => err_read_pointer_increment,
err_read_pointer_not_increment => err_read_pointer_not_increment,
err_write_en => err_write_en,
err_not_CTS_in => err_not_CTS_in,
err_read_en_mismatch => err_read_en_mismatch
);
------------------------------------------------------------------------------------------------------------------------------
LBDR_unit: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty, flit_type => flit_type, dst_addr=> destination_address,
Req_N=> Req_N_out, Req_E=>Req_E_out, Req_W=>Req_W_out, Req_S=>Req_S_out, Req_L=>Req_L_out,
shift=>shift, fault_clk=>fault_clk, data_in_serial=> fault_DO_serial_FIFO_2_LBDR, data_out_serial=>fault_DO_serial_LBDR_2_Arbiter,
err_header_empty_Requests_FF_Requests_in => err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in => err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => err_header_not_empty_Req_S_in
);
------------------------------------------------------------------------------------------------------------------------------
Arbiter_unit: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_N_in , Req_E => Req_E_in, Req_W => Req_W_in, Req_S => Req_S_in, Req_L => Req_L_in,
DCTS => DCTS, Grant_N => Grant_N_out, Grant_E => Grant_E_out, Grant_W => Grant_W_out, Grant_S => Grant_S_out, Grant_L => Grant_L_out,
Xbar_sel => Xbar_sel,
RTS => RTS,
shift=>shift, fault_clk=>fault_clk, data_in_serial=> fault_DO_serial_LBDR_2_Arbiter, data_out_serial=> fault_data_out_serial,
err_state_IDLE_xbar => err_state_IDLE_xbar ,
err_state_not_IDLE_xbar => err_state_not_IDLE_xbar ,
err_state_IDLE_RTS_FF_in => err_state_IDLE_RTS_FF_in ,
err_state_not_IDLE_RTS_FF_RTS_FF_in => err_state_not_IDLE_RTS_FF_RTS_FF_in ,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in ,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in ,
err_RTS_FF_not_DCTS_state_state_in => err_RTS_FF_not_DCTS_state_state_in ,
err_not_RTS_FF_state_in_next_state => err_not_RTS_FF_state_in_next_state ,
err_RTS_FF_DCTS_state_in_next_state => err_RTS_FF_DCTS_state_in_next_state ,
err_not_DCTS_Grants => err_not_DCTS_Grants ,
err_DCTS_not_RTS_FF_Grants => err_DCTS_not_RTS_FF_Grants ,
err_DCTS_RTS_FF_IDLE_Grants => err_DCTS_RTS_FF_IDLE_Grants ,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => err_DCTS_RTS_FF_not_IDLE_Grants_onehot ,
err_Requests_next_state_IDLE => err_Requests_next_state_IDLE ,
err_IDLE_Req_L => err_IDLE_Req_L ,
err_Local_Req_L => err_Local_Req_L ,
err_North_Req_N => err_North_Req_N ,
err_IDLE_Req_N => err_IDLE_Req_N ,
err_Local_Req_N => err_Local_Req_N ,
err_South_Req_L => err_South_Req_L ,
err_West_Req_L => err_West_Req_L ,
err_South_Req_N => err_South_Req_N ,
err_East_Req_L => err_East_Req_L ,
err_West_Req_N => err_West_Req_N ,
err_East_Req_N => err_East_Req_N ,
err_next_state_onehot => err_next_state_onehot ,
err_state_in_onehot => err_state_in_onehot ,
err_state_north_xbar_sel => err_state_north_xbar_sel ,
err_state_east_xbar_sel => err_state_east_xbar_sel ,
err_state_west_xbar_sel => err_state_west_xbar_sel ,
err_state_south_xbar_sel => err_state_south_xbar_sel
);
checker_shifter: shift_register generic map (REG_WIDTH => 59)
port map (
clk => checker_clk, reset => reset,
shift => shift,
data_in => combined_error_signals,
data_out_parallel => shift_parallel_data,
data_out_serial => shift_serial_data
);
end;
| gpl-3.0 | 1a5dd8307fa9f8acf65272a1001315ef | 0.547374 | 3.283772 | false | false | false | false |
SoCdesign/EHA | RTL/Immortal_Chip/modules_with_fault_injectors/to_be_tested/LBDR_with_checkers_with_FI.vhd | 1 | 12,279 | --Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR is
generic (
cur_addr_rst: integer := 5;
Rxy_rst: integer := 60;
Cx_rst: integer := 15;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic;
-- fault injector signals
shift: in std_logic;
fault_clk: in std_logic;
data_in_serial: in std_logic;
data_out_serial: out std_logic;
-- Checker outputs
--err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in : out std_logic
);
end LBDR;
architecture behavior of LBDR is
signal Cx: std_logic_vector(3 downto 0);
signal Rxy: std_logic_vector(7 downto 0);
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal N1, E1, W1, S1 :std_logic := '0';
signal Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: std_logic;
signal Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: std_logic;
-- New signals used for integration of FI(s) in LBDR module
signal empty_faulty: std_logic;
signal flit_type_faulty: std_logic_vector (2 downto 0);
signal dst_addr_faulty: std_logic_vector (NoC_size-1 downto 0);
signal N1_faulty, E1_faulty, W1_faulty, S1_faulty :std_logic;
signal Req_N_in_faulty, Req_E_in_faulty, Req_W_in_faulty, Req_S_in_faulty, Req_L_in_faulty: std_logic;
signal Req_N_FF_faulty, Req_E_FF_faulty, Req_W_FF_faulty, Req_S_FF_faulty, Req_L_FF_faulty: std_logic;
component LBDR_checkers is
generic (
cur_addr_rst: integer := 5;
NoC_size: integer := 4
);
port ( empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic;
N1_out, E1_out, W1_out, S1_out: in std_logic;
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
-- Checker outputs
--err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in : out std_logic
);
end component;
component fault_injector is
generic(DATA_WIDTH : integer := 32;
ADDRESS_WIDTH : integer := 5);
port(
data_in: in std_logic_vector (DATA_WIDTH-1 downto 0);
address: in std_logic_vector (ADDRESS_WIDTH-1 downto 0);
sta_0: in std_logic;
sta_1: in std_logic;
data_out: out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end component;
component shift_register_serial_in is
generic (
REG_WIDTH: integer := 29
);
port (
clk, reset : in std_logic;
shift: in std_logic;
data_in_serial: in std_logic;
data_out_parallel: out std_logic_vector(REG_WIDTH-1 downto 0);
data_out_serial: out std_logic
);
end component;
signal FI_add_sta: std_logic_vector(28 downto 0); -- 22 bits for inputs and internal signals
-- 5 bits for fault injection location address (ceil of log2(22) = 5)
-- 2 bits for type of fault (SA0 or SA1)
signal non_faulty_signals: std_logic_vector (21 downto 0);
signal faulty_signals: std_logic_vector(21 downto 0); -- 22 bits for inputs and internal signals (with one fault injected in one of them)
begin
non_faulty_signals <= empty & flit_type & dst_addr &
Req_N_FF & Req_E_FF & Req_W_FF & Req_S_FF & Req_L_FF &
Req_N_in & Req_E_in & Req_W_in & Req_S_in & Req_L_in &
N1 & E1 & W1 & S1;
FI: fault_injector generic map(DATA_WIDTH => 22, ADDRESS_WIDTH => 5)
port map (data_in=> non_faulty_signals , address=> FI_add_sta(6 downto 2), sta_0=> FI_add_sta(1), sta_1=> FI_add_sta(0), data_out => faulty_signals
);
-- Extracting faulty values for input and internal signals
empty_faulty <= faulty_signals(21);
flit_type_faulty <= faulty_signals (20 downto 18);
dst_addr_faulty <= faulty_signals (17 downto 14);
Req_N_FF_faulty <= faulty_signals(13);
Req_E_FF_faulty <= faulty_signals(12);
Req_W_FF_faulty <= faulty_signals(11);
Req_S_FF_faulty <= faulty_signals(10);
Req_L_FF_faulty <= faulty_signals(9);
Req_N_in_faulty <= faulty_signals(8);
Req_E_in_faulty <= faulty_signals(7);
Req_W_in_faulty <= faulty_signals(6);
Req_S_in_faulty <= faulty_signals(5);
Req_L_in_faulty <= faulty_signals(4);
N1_faulty <= faulty_signals(3);
E1_faulty <= faulty_signals(2);
W1_faulty <= faulty_signals(1);
S1_faulty <= faulty_signals(0);
SR: shift_register_serial_in generic map(REG_WIDTH => 29)
port map( clk=> fault_clk, reset=>reset, shift=> shift,data_in_serial=> data_in_serial,
data_out_parallel=> FI_add_sta, data_out_serial=> data_out_serial
);
Cx <= std_logic_vector(to_unsigned(Cx_rst, Cx'length));
Rxy <= std_logic_vector(to_unsigned(Rxy_rst, Rxy'length));
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
N1 <= '1' when dst_addr_faulty(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) else '0';
E1 <= '1' when cur_addr((NoC_size/2)-1 downto 0) < dst_addr_faulty((NoC_size/2)-1 downto 0) else '0';
W1 <= '1' when dst_addr_faulty((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) else '0';
S1 <= '1' when cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr_faulty(NoC_size-1 downto NoC_size/2) else '0';
LBDRCHECKERS: LBDR_checkers generic map (cur_addr_rst => cur_addr_rst, NoC_size => NoC_size)
port map (
-- the non-faulty values of inputs go to checkers (according to the ReCoSoC, Euromicro DSD and NOCS papers ??)
empty => empty,
flit_type => flit_type,
Req_N_FF => Req_N_FF,
Req_E_FF => Req_E_FF,
Req_W_FF => Req_W_FF,
Req_S_FF => Req_S_FF,
Req_L_FF => Req_L_FF,
Req_N_in => Req_N_in,
Req_E_in => Req_E_in,
Req_W_in => Req_W_in,
Req_S_in => Req_S_in,
Req_L_in => Req_L_in,
N1_out => N1,
E1_out => E1,
W1_out => W1,
S1_out => S1,
dst_addr => dst_addr,
err_header_empty_Requests_FF_Requests_in => err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in => err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => err_header_not_empty_Req_S_in
);
process(clk, reset)
begin
if reset = '0' then
Req_N_FF <= '0';
Req_E_FF <= '0';
Req_W_FF <= '0';
Req_S_FF <= '0';
Req_L_FF <= '0';
elsif clk'event and clk = '1' then
Req_N_FF <= Req_N_in_faulty;
Req_E_FF <= Req_E_in_faulty;
Req_W_FF <= Req_W_in_faulty;
Req_S_FF <= Req_S_in_faulty;
Req_L_FF <= Req_L_in_faulty;
end if;
end process;
-- The combionational part
Req_N <= Req_N_FF;
Req_E <= Req_E_FF;
Req_W <= Req_W_FF;
Req_S <= Req_S_FF;
Req_L <= Req_L_FF;
process(N1_faulty, E1_faulty, W1_faulty, S1_faulty, Rxy, Cx, flit_type_faulty, empty_faulty, Req_N_FF_faulty, Req_E_FF_faulty, Req_W_FF_faulty, Req_S_FF_faulty, Req_L_FF_faulty) begin
if flit_type_faulty = "001" and empty_faulty = '0' then
Req_N_in <= ((N1_faulty and not E1_faulty and not W1_faulty) or (N1_faulty and E1_faulty and Rxy(0)) or (N1_faulty and W1_faulty and Rxy(1))) and Cx(0);
Req_E_in <= ((E1_faulty and not N1_faulty and not S1_faulty) or (E1_faulty and N1_faulty and Rxy(2)) or (E1_faulty and S1_faulty and Rxy(3))) and Cx(1);
Req_W_in <= ((W1_faulty and not N1_faulty and not S1_faulty) or (W1_faulty and N1_faulty and Rxy(4)) or (W1_faulty and S1_faulty and Rxy(5))) and Cx(2);
Req_S_in <= ((S1_faulty and not E1_faulty and not W1_faulty) or (S1_faulty and E1_faulty and Rxy(6)) or (S1_faulty and W1_faulty and Rxy(7))) and Cx(3);
Req_L_in <= not N1_faulty and not E1_faulty and not W1_faulty and not S1_faulty;
elsif flit_type_faulty = "100" then
Req_N_in <= '0';
Req_E_in <= '0';
Req_W_in <= '0';
Req_S_in <= '0';
Req_L_in <= '0';
else
Req_N_in <= Req_N_FF_faulty;
Req_E_in <= Req_E_FF_faulty;
Req_W_in <= Req_W_FF_faulty;
Req_S_in <= Req_S_FF_faulty;
Req_L_in <= Req_L_FF_faulty;
end if;
end process;
END; | gpl-3.0 | b13cf8b7e23e2ea6d961ebaee63d8aed | 0.534571 | 3.086727 | false | false | false | false |
hanyazou/vivado-ws | playpen/dvi2vga_nofilter/dvi2vga_nofilter.srcs/sources_1/bd/design_1/ip/design_1_rgb2vga_0_0/synth/design_1_rgb2vga_0_0.vhd | 1 | 4,991 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
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-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: digilentinc.com:ip:rgb2vga:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_rgb2vga_0_0 IS
PORT (
rgb_pData : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_pVDE : IN STD_LOGIC;
rgb_pHSync : IN STD_LOGIC;
rgb_pVSync : IN STD_LOGIC;
PixelClk : IN STD_LOGIC;
vga_pRed : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
vga_pGreen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
vga_pBlue : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
vga_pHSync : OUT STD_LOGIC;
vga_pVSync : OUT STD_LOGIC
);
END design_1_rgb2vga_0_0;
ARCHITECTURE design_1_rgb2vga_0_0_arch OF design_1_rgb2vga_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_rgb2vga_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT rgb2vga IS
GENERIC (
VID_IN_DATA_WIDTH : INTEGER;
kRedDepth : INTEGER;
kGreenDepth : INTEGER;
kBlueDepth : INTEGER
);
PORT (
rgb_pData : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_pVDE : IN STD_LOGIC;
rgb_pHSync : IN STD_LOGIC;
rgb_pVSync : IN STD_LOGIC;
PixelClk : IN STD_LOGIC;
vga_pRed : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
vga_pGreen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
vga_pBlue : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
vga_pHSync : OUT STD_LOGIC;
vga_pVSync : OUT STD_LOGIC
);
END COMPONENT rgb2vga;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_rgb2vga_0_0_arch: ARCHITECTURE IS "rgb2vga,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_rgb2vga_0_0_arch : ARCHITECTURE IS "design_1_rgb2vga_0_0,rgb2vga,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF rgb_pData: SIGNAL IS "xilinx.com:interface:vid_io:1.0 vid_in DATA";
ATTRIBUTE X_INTERFACE_INFO OF rgb_pVDE: SIGNAL IS "xilinx.com:interface:vid_io:1.0 vid_in ACTIVE_VIDEO";
ATTRIBUTE X_INTERFACE_INFO OF rgb_pHSync: SIGNAL IS "xilinx.com:interface:vid_io:1.0 vid_in HSYNC";
ATTRIBUTE X_INTERFACE_INFO OF rgb_pVSync: SIGNAL IS "xilinx.com:interface:vid_io:1.0 vid_in VSYNC";
ATTRIBUTE X_INTERFACE_INFO OF PixelClk: SIGNAL IS "xilinx.com:signal:clock:1.0 signal_clock CLK";
BEGIN
U0 : rgb2vga
GENERIC MAP (
VID_IN_DATA_WIDTH => 24,
kRedDepth => 5,
kGreenDepth => 6,
kBlueDepth => 5
)
PORT MAP (
rgb_pData => rgb_pData,
rgb_pVDE => rgb_pVDE,
rgb_pHSync => rgb_pHSync,
rgb_pVSync => rgb_pVSync,
PixelClk => PixelClk,
vga_pRed => vga_pRed,
vga_pGreen => vga_pGreen,
vga_pBlue => vga_pBlue,
vga_pHSync => vga_pHSync,
vga_pVSync => vga_pVSync
);
END design_1_rgb2vga_0_0_arch;
| mit | 237842f1c8a2e5ce67cf7873e118379c | 0.707674 | 3.713542 | false | false | false | false |
JarrettR/FPGA-Cryptoparty | FPGA/hdl/ipcore_dir/fx2_fifo/simulation/fx2_fifo_synth.vhd | 1 | 10,955 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fx2_fifo_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.fx2_fifo_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fx2_fifo_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fx2_fifo_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_i <= WR_CLK;
rd_clk_i <= RD_CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fx2_fifo_dgen
GENERIC MAP (
C_DIN_WIDTH => 8,
C_DOUT_WIDTH => 8,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fx2_fifo_dverif
GENERIC MAP (
C_DOUT_WIDTH => 8,
C_DIN_WIDTH => 8,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fx2_fifo_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 8,
C_DIN_WIDTH => 8,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fx2_fifo_inst : fx2_fifo_exdes
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| gpl-3.0 | e8de14df59774d07f89c23ed41ec6bf0 | 0.457417 | 3.950595 | false | false | false | false |
TUM-LIS/faultify | hardware/testcases/viterbi/fpga_sim/xpsLibraryPath/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/vhdl/faultify_top.vhd | 4 | 19,797 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_top is
generic (
numInj : integer := 56;
numIn : integer := 10;
numOut : integer := 10);
port (
aclk : in std_logic; -- interface clock
arst_n : in std_logic; -- interface reset
clk : in std_logic; -- simulation clock (slow)
clk_x32 : in std_logic; -- prng clock (fast)
-- Write channel
awvalid : in std_logic;
awaddr : in std_logic_vector(31 downto 0);
wvalid : in std_logic;
wdata : in std_logic_vector(31 downto 0);
-- Read channel
arvalid : in std_logic;
araddr : in std_logic_vector(31 downto 0);
rvalid : out std_logic;
rdata : out std_logic_vector(31 downto 0)
);
attribute syn_hier : string;
attribute syn_hier of faultify_top : entity is "hard";
end faultify_top;
architecture behav of faultify_top is
component flag_cdc
port (
clkA : in std_logic;
clkB : in std_logic;
FlagIn_clkA : in std_logic;
FlagOut_clkB : out std_logic;
rst_n : in std_logic);
end component;
component faultify_simulator
generic (
numInj : integer;
numIn : integer;
numOut : integer);
port (
clk : in std_logic;
clk_m : in std_logic;
circ_ce : in std_logic;
circ_rst : in std_logic;
test : out std_logic_vector(31 downto 0);
testvector : in std_logic_vector(numIn-1 downto 0);
resultvector_o : out std_logic_vector(numOut-1 downto 0);
resultvector_f : out std_logic_vector(numOut-1 downto 0);
seed_in_en : in std_logic;
seed_in : in std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
shift_en : in std_logic;
rst_n : in std_logic);
end component;
component lfsr
generic (
width : integer;
seed : integer);
port (
clk : in std_logic;
rand_out : out std_logic_vector(width-1 downto 0));
end component;
type vector is array (0 to numOut-1) of std_logic_vector(31 downto 0);
signal errorSum : vector;
signal errorSumReg : vector;
signal errorSumReg_cdc_0 : vector;
signal errorSumReg_cdc_1 : vector;
signal errorVec : std_logic_vector(numOut-1 downto 0);
signal cnt : integer;
signal cnt_cdc_0 : integer;
signal cnt_cdc_1 : integer;
-- Asymmetric ram larger than 36 bit not supported in synplify I-2013
--type seed_ram_matr is array (0 to numInj-1) of std_logic_vector(63 downto 0);
--signal seed_ram : seed_ram_matr;
-- workaround 2 32-bit rams
type seed_ram_matr is array (0 to numInj-1) of std_logic_vector(31 downto 0);
signal seed_ram_low : seed_ram_matr;
signal seed_ram_high : seed_ram_matr;
--subtype seed_ram_matr_word_t is std_logic_vector(63 downto 0);
--type seed_ram_matr_memory_t is array (0 to numInj-1) of seed_ram_matr_word_t;
--signal seed_ram : seed_ram_matr_memory_t;
type prob_ram_matr is array (0 to numInj-1) of std_logic_vector(31 downto 0);
signal prob_ram : prob_ram_matr;
type reg_type is record
control : std_logic_vector(31 downto 0);
status : std_logic_vector(31 downto 0);
pe_location : std_logic_vector(31 downto 0);
pe_seed_low : std_logic_vector(31 downto 0);
pe_seed_high : std_logic_vector(31 downto 0);
pe_probability : std_logic_vector(31 downto 0);
output : std_logic_vector(31 downto 0);
ovalid : std_logic;
simtime : std_logic_vector(31 downto 0);
sel_soe : std_logic_vector(31 downto 0);
adr_soe : std_logic_vector(31 downto 0);
awaddr : std_logic_vector(31 downto 0);
test : std_logic_vector(31 downto 0);
circreset : std_logic_vector(31 downto 0);
cnt_tmp : std_logic_vector(31 downto 0);
sumoferrors : vector;
end record;
signal busy_loading : std_logic;
signal busy_simulating : std_logic;
signal busy_loading_reg : std_logic_vector(1 downto 0);
signal busy_simulating_reg : std_logic_vector(1 downto 0);
signal sim_done : std_logic;
signal r : reg_type;
type load_fsm_states is (IDLE, LOADSEED, LOADPROB);
signal l_state : load_fsm_states;
type sim_states is (IDLE, DELAY_Z, DELAY, SIMULATION, DELAY2, DELAY3, DELAY4, FREE_SIMULATION);
signal s_state : sim_states;
signal testvector : std_logic_vector(numIn-1 downto 0);
signal resultvector_o : std_logic_vector(numOut-1 downto 0);
signal resultvector_f : std_logic_vector(numOut-1 downto 0);
signal seed_in_en : std_logic;
signal seed_in : std_logic;
signal prob_in_en : std_logic;
signal prob_in : std_logic;
signal shift_en : std_logic;
signal shift_en_l : std_logic;
signal shift_en_s : std_logic;
signal load_seed_prob : std_logic;
signal start_simulation : std_logic;
signal start_free_simulation : std_logic;
signal stop_simulation : std_logic;
signal circ_ce, circ_rst, circ_rst_sim : std_logic;
signal tvec : std_logic_vector(127 downto 0);
signal test : std_logic_vector(31 downto 0);
signal rst_cdc, rst_cdc_n : std_logic;
begin -- behav
-----------------------------------------------------------------------------
-- PRNG shifting
-----------------------------------------------------------------------------
shift_en <= shift_en_l or shift_en_s;
-----------------------------------------------------------------------------
-- Testvector
-----------------------------------------------------------------------------
--testvector <= (others => '0');
lfsr_1 : lfsr
generic map (
width => 128,
seed => 3498327)
port map (
clk => clk,
rand_out => tvec);
testvector <= tvec(numIn-1 downto 0);
-----------------------------------------------------------------------------
-- Simulator
-----------------------------------------------------------------------------
circ_rst <= circ_rst_sim when r.circreset(0) = '1' else '0';
faultify_simulator_1 : faultify_simulator
generic map (
numInj => numInj,
numIn => numIn,
numOut => numOut)
port map (
clk => clk_x32,
clk_m => clk,
circ_ce => circ_ce,
circ_rst => circ_rst,
test => test,
testvector => testvector,
resultvector_o => resultvector_o,
resultvector_f => resultvector_f,
seed_in_en => seed_in_en,
seed_in => seed_in,
prob_in_en => prob_in_en,
prob_in => prob_in,
shift_en => shift_en,
rst_n => arst_n);
-------------------------------------------------------------------------------
-- One Process Flow
-------------------------------------------------------------------------------
register_process : process (aclk, arst_n)
variable write_addr : std_logic_vector(31 downto 0);
begin -- process register_process
if arst_n = '0' then -- asynchronous reset (active low)
r.control <= (others => '0');
r.status <= (others => '0');
r.pe_probability <= (others => '0');
r.pe_seed_high <= (others => '0');
r.pe_seed_low <= (others => '0');
r.pe_location <= (others => '0');
r.ovalid <= '0';
r.simtime <= (others => '0');
r.sel_soe <= (others => '0');
r.adr_soe <= (others => '0');
r.sumoferrors <= (others => (others => '0'));
r.output <= (others => '0');
elsif aclk'event and aclk = '1' then -- rising clock edge
r.control <= (others => '0');
if awvalid = '1' then
r.awaddr <= awaddr;
write_addr := awaddr;
end if;
if wvalid = '1' then
if write_addr = x"00000000" then
r.control <= wdata;
elsif write_addr = x"00000001" then
r.pe_location <= wdata;
elsif write_addr = x"00000002" then
r.pe_seed_low <= wdata;
elsif write_addr = x"00000003" then
r.pe_seed_high <= wdata;
elsif write_addr = x"00000004" then
r.pe_probability <= wdata;
elsif write_addr = x"00000005" then
r.cnt_tmp <= std_logic_vector(to_unsigned(cnt_cdc_1, 32));
r.adr_soe <= wdata;
elsif write_addr = x"00000007" then
r.simtime <= wdata;
elsif write_addr = x"00000009" then
r.circreset <= wdata;
end if;
end if;
if arvalid = '1' then
if araddr = x"0000000F" then
r.output <= r.status;
elsif araddr = x"00000001" then
r.output <= r.pe_location;
elsif araddr = x"00000002" then
r.output <= r.pe_seed_low;
elsif araddr = x"00000003" then
r.output <= r.pe_seed_high;
elsif araddr = x"00000004" then
r.output <= r.pe_probability;
elsif araddr = x"00000006" then
r.output <= r.sel_soe;
elsif araddr = x"00000008" then
r.output <= r.test;
elsif araddr = x"0000000A" then
r.output <= r.cnt_tmp;
end if;
r.ovalid <= '1';
else
r.ovalid <= '0';
end if;
if busy_loading_reg(1) = '1' then
r.status(0) <= '1';
else
r.status(0) <= '0';
end if;
if busy_simulating_reg(1) = '1' then
r.status(1) <= '1';
else
r.status(1) <= '0';
end if;
r.sel_soe <= r.sumoferrors(to_integer(unsigned(r.adr_soe)));
rdata <= r.output;
rvalid <= r.ovalid;
r.sumoferrors <= errorSumReg_cdc_1;
r.test <= errorSum(0);
end if;
end process register_process;
-----------------------------------------------------------------------------
-- simple clock domain crossing
-----------------------------------------------------------------------------
process (aclk, arst_n)
begin -- process
if arst_n = '0' then -- asynchronous reset (active low)
busy_simulating_reg <= (others => '0');
busy_loading_reg <= (others => '0');
elsif aclk'event and aclk = '1' then -- rising clock edge
busy_simulating_reg(0) <= busy_simulating;
busy_loading_reg(0) <= busy_loading;
busy_simulating_reg(1) <= busy_simulating_reg(0);
busy_loading_reg(1) <= busy_loading_reg(0);
cnt_cdc_0 <= cnt;
cnt_cdc_1 <= cnt_cdc_0;
errorSumReg_cdc_0 <= errorSumReg;
errorSumReg_cdc_1 <= errorSumReg_cdc_0;
end if;
end process;
-------------------------------------------------------------------------------
-- Store seeed/prob
-------------------------------------------------------------------------------
store_seed : process (aclk, arst_n)
begin -- process store_seed
if arst_n = '0' then -- asynchronous reset (active low)
elsif aclk'event and aclk = '1' then -- rising clock edge
if r.control(0) = '1' then
-- Synplify bug workaround
--seed_ram(to_integer(unsigned(r.pe_location))) <= r.pe_seed_high & r.pe_seed_low;
seed_ram_low(to_integer(unsigned(r.pe_location))) <= r.pe_seed_low;
seed_ram_high(to_integer(unsigned(r.pe_location))) <= r.pe_seed_high;
prob_ram(to_integer(unsigned(r.pe_location))) <= r.pe_probability;
end if;
end if;
end process store_seed;
-----------------------------------------------------------------------------
-- Seed/prob loading FSM
-----------------------------------------------------------------------------
--flag_cdc_1 : flag_cdc
-- port map (
-- clkA => aclk,
-- clkB => clk_x32,
-- FlagIn_clkA => r.control(1),
-- FlagOut_clkB => load_seed_prob,
-- rst_n => arst_n);
load_seed_prob <= r.control(1);
seed_prob_loading : process (clk_x32, arst_n)
variable cnt_seed : integer range 0 to 64;
variable cnt_inj : integer range 0 to numInj;
variable cnt_prob : integer range 0 to 32;
begin -- process seed_prob_loading
if arst_n = '0' then -- asynchronous reset (active low)
l_state <= IDLE;
seed_in <= '0';
seed_in_en <= '0';
prob_in <= '0';
prob_in_en <= '0';
shift_en_l <= '0';
busy_loading <= '0';
elsif clk_x32'event and clk_x32 = '1' then -- rising clock edge
case l_state is
when IDLE =>
cnt_seed := 0;
cnt_inj := 0;
cnt_prob := 0;
busy_loading <= '0';
seed_in_en <= '0';
prob_in_en <= '0';
shift_en_l <= '0';
if load_seed_prob = '1' then
busy_loading <= '1';
l_state <= LOADSEED;
end if;
when LOADSEED =>
if cnt_seed < 64 then
shift_en_l <= '1';
seed_in_en <= '1';
-- not working in synplify I-2013
--seed_in <= seed_ram(cnt_inj)(cnt_seed);
--
if cnt_seed < 32 then
seed_in <= seed_ram_low(cnt_inj)(cnt_seed);
else
seed_in <= seed_ram_high(cnt_inj)(cnt_seed-32);
end if;
cnt_seed := cnt_seed + 1;
end if;
if cnt_seed = 64 then
cnt_seed := 0;
cnt_inj := cnt_inj + 1;
end if;
if cnt_inj = numInj then
l_state <= LOADPROB;
--seed_in_en <= '0';
cnt_inj := 0;
end if;
when LOADPROB =>
seed_in_en <= '0';
if cnt_prob < 32 then
prob_in_en <= '1';
prob_in <= prob_ram(cnt_inj)(cnt_prob);
cnt_prob := cnt_prob + 1;
end if;
if cnt_prob = 32 then
cnt_prob := 0;
cnt_inj := cnt_inj + 1;
end if;
if cnt_inj = numInj then
l_state <= IDLE;
cnt_inj := 0;
--prob_in_en <= '0';
end if;
end case;
end if;
end process seed_prob_loading;
-----------------------------------------------------------------------------
-- Simulation FSM
-----------------------------------------------------------------------------
flag_cdc_2 : flag_cdc
port map (
clkA => aclk,
clkB => clk,
FlagIn_clkA => r.control(2),
FlagOut_clkB => start_simulation,
rst_n => arst_n);
flag_cdc_3 : flag_cdc
port map (
clkA => aclk,
clkB => clk,
FlagIn_clkA => r.control(3),
FlagOut_clkB => start_free_simulation,
rst_n => arst_n);
flag_cdc_4 : flag_cdc
port map (
clkA => aclk,
clkB => clk,
FlagIn_clkA => r.control(4),
FlagOut_clkB => stop_simulation,
rst_n => arst_n);
rst_cdc_5 : flag_cdc
port map (
clkA => aclk,
clkB => clk,
FlagIn_clkA => not arst_n,
FlagOut_clkB => rst_cdc,
rst_n => '1');
rst_cdc_n <= not rst_cdc;
process (clk, rst_cdc_n)
variable simtime : integer;
variable cnt_delay : integer range 0 to 9;
begin -- process
if clk'event and clk = '1' then -- rising clock edge
if rst_cdc_n = '0' then -- asynchronous reset (active low)
s_state <= IDLE;
errorVec <= (others => '0');
errorSum <= (others => (others => '0'));
circ_ce <= '0';
circ_rst_sim <= '1';
shift_en_s <= '0';
busy_simulating <= '0';
sim_done <= '0';
errorSumReg <= (others => (others => '0'));
else
case s_state is
when IDLE =>
sim_done <= '0';
circ_ce <= '0';
circ_rst_sim <= '1';
shift_en_s <= '0';
errorVec <= (others => '0');
--errorSum <= errorSum;
errorSum <= (others => (others => '0'));
--cnt <= 0;
busy_simulating <= '0';
cnt_delay := 0;
if start_simulation = '1' then
cnt <= 0;
busy_simulating <= '1';
errorSum <= (others => (others => '0'));
errorSumReg <= (others => (others => '0'));
simtime := to_integer(unsigned(r.simtime));
s_state <= DELAY_Z;
circ_ce <= '1';
circ_rst_sim <= '0';
shift_en_s <= '1';
end if;
if start_free_simulation = '1' then
cnt <= 0;
busy_simulating <= '1';
errorSum <= (others => (others => '0'));
errorSumReg <= (others => (others => '0'));
s_state <= FREE_SIMULATION;
circ_ce <= '1';
circ_rst_sim <= '0';
shift_en_s <= '1';
end if;
when DELAY_z =>
cnt_delay := cnt_delay + 1;
if cnt_delay = 9 then
s_state <= DELAY;
end if;
when DELAY =>
s_state <= SIMULATION;
errorVec <= (others => '0');
errorSum <= (others => (others => '0'));
when SIMULATION =>
circ_rst_sim <= '0';
shift_en_s <= '1';
-- collect errors
errorVec <= resultvector_o xor resultvector_f;
for i in 0 to (numOut-1) loop
if (errorVec(i) = '1') then
errorSum(i) <= std_logic_vector(unsigned(errorSum(i)) + 1);
end if;
end loop;
--
errorSumReg <= errorSum;
if cnt = simtime-1 then
s_state <= DELAY2;
circ_ce <= '0';
circ_rst_sim <= '1';
shift_en_s <= '0';
end if;
cnt <= cnt +1;
when DELAY2 =>
errorVec <= resultvector_o xor resultvector_f;
for i in 0 to (numOut-1) loop
if (errorVec(i) = '1') then
errorSum(i) <= std_logic_vector(unsigned(errorSum(i)) + 1);
end if;
end loop;
s_state <= DELAY3;
when DELAY3 =>
s_state <= DELAY4;
errorSumReg <= errorSum;
errorSum <= (others => (others => '0'));
when DELAY4 =>
s_state <= IDLE;
sim_done <= '1';
when FREE_SIMULATION =>
circ_rst_sim <= '0';
shift_en_s <= '1';
-- collect errors
errorVec <= resultvector_o xor resultvector_f;
for i in 0 to (numOut-1) loop
if (errorVec(i) = '1') then
errorSum(i) <= std_logic_vector(unsigned(errorSum(i)) + 1);
end if;
end loop;
--
errorSumReg <= errorSum;
if stop_simulation = '1' then
s_state <= IDLE;
sim_done <= '1';
circ_ce <= '0';
circ_rst_sim <= '1';
shift_en_s <= '0';
end if;
cnt <= cnt +1;
when others =>
s_state <= IDLE;
end case;
end if;
end if;
end process;
end behav;
| gpl-2.0 | dd4ef4eea196776ead90feef61c382aa | 0.462191 | 3.837372 | false | false | false | false |
bruskajp/EE-316 | Project4/Vivado_NexysBoard/craddockEE316/craddockEE316.srcs/sources_1/ip/sig1dualRAM/synth/sig1dualRAM.vhd | 1 | 14,814 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_3;
USE blk_mem_gen_v8_3_3.blk_mem_gen_v8_3_3;
ENTITY sig1dualRAM IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END sig1dualRAM;
ARCHITECTURE sig1dualRAM_arch OF sig1dualRAM IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sig1dualRAM_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_3 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_3;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF sig1dualRAM_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_3,Vivado 2016.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF sig1dualRAM_arch : ARCHITECTURE IS "sig1dualRAM,blk_mem_gen_v8_3_3,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF sig1dualRAM_arch: ARCHITECTURE IS "sig1dualRAM,blk_mem_gen_v8_3_3,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file" &
"_loaded,C_INIT_FILE=sig1dualRAM.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=11520,C_READ_DEPTH_A=11520,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_" &
"DEPTH_B=11520,C_READ_DEPTH_B=11520,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DIS" &
"ABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=3,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 4.53475 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_3
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "sig1dualRAM.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 11520,
C_READ_DEPTH_A => 11520,
C_ADDRA_WIDTH => 14,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 11520,
C_READ_DEPTH_B => 11520,
C_ADDRB_WIDTH => 14,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 1,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "3",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 4.53475 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END sig1dualRAM_arch;
| gpl-3.0 | 040d596bf18a78a61fee6fabaae4afd5 | 0.62981 | 3.028209 | false | false | false | false |
TUM-LIS/faultify | hardware/testcases/IIR/fpga_sim/xpsLibraryPath/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/vhdl/faultify_simulator.vhd | 1 | 5,432 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity faultify_simulator is
generic (
numInj : integer := 56;
numIn : integer := 10;
numOut : integer := 10);
port (
clk : in std_logic;
clk_m : in std_logic;
circ_ce : in std_logic;
circ_rst : in std_logic;
test : out std_logic_vector(31 downto 0);
testvector : in std_logic_vector(numIn-1 downto 0);
resultvector_o : out std_logic_vector(numOut-1 downto 0);
resultvector_f : out std_logic_vector(numOut-1 downto 0);
seed_in_en : in std_logic;
seed_in : in std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
shift_en : in std_logic;
rst_n : in std_logic);
end faultify_simulator;
-- 866:0
architecture behav of faultify_simulator is
component faultify_binomial_gen
generic (
width : integer);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : out std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
prob_out_c : out std_logic;
shift_en : in std_logic;
data_out : out std_logic;
data_out_valid : out std_logic);
end component;
component circuit_under_test
port (
clk : in std_logic;
rst : in std_logic;
testvector : in std_logic_vector(numIn-1 downto 0);
resultvector : out std_logic_vector(numOut-1 downto 0);
injectionvector : in std_logic_vector(numInj-1 downto 0));
end component;
component golden_circuit
port (
clk : in std_logic;
rst : in std_logic;
testvector : in std_logic_vector(numIn-1 downto 0);
resultvector : out std_logic_vector(numOut-1 downto 0));
end component;
signal injectionvector : std_logic_vector(numInj-1 downto 0);
signal injectionvector_reg : std_logic_vector(numInj-1 downto 0);
signal injectionvector_reg_o : std_logic_vector(numInj-1 downto 0);
signal seed_chain : std_logic_vector(numInj downto 0);
signal prob_chain : std_logic_vector(numInj downto 0);
signal rst : std_logic;
signal clk_ce_m : std_logic;
signal testvector_reg : std_logic_vector(numIn-1 downto 0);
attribute syn_noprune : boolean;
attribute syn_noprune of circuit_under_test_inst : label is true;
attribute syn_noprune of golden_circuit_inst : label is true;
attribute xc_props : string;
attribute xc_props of circuit_under_test_inst : label is "KEEP_HIERARCHY=TRUE";
attribute xc_props of golden_circuit_inst : label is "KEEP_HIERARCHY=TRUE";
begin -- behav
rst <= not rst_n;
-----------------------------------------------------------------------------
-- debug...
-----------------------------------------------------------------------------
-- resultvector_f <= (others => '1');
-- resultvector_o <= (others => '1');
cgate : bufgce
port map (
I => clk_m,
O => clk_ce_m,
CE => circ_ce);
process (clk_ce_m, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
testvector_reg <= (others => '0');
elsif clk_ce_m'event and clk_ce_m = '1' then -- rising clock edge
testvector_reg <= testvector;
end if;
end process;
circuit_under_test_inst : circuit_under_test
port map (
clk => clk_ce_m,
rst => not circ_rst,
testvector => testvector_reg,
resultvector => resultvector_f,
injectionvector => injectionvector_reg);
golden_circuit_inst : golden_circuit
port map (
clk => clk_ce_m,
rst => not circ_rst,
testvector => testvector_reg,
resultvector => resultvector_o
);
seed_chain(0) <= seed_in;
prob_chain(0) <= prob_in;
prsn_loop : for i in 0 to numInj-1 generate
prsn_top_1 : faultify_binomial_gen
generic map (
width => 32)
port map (
clk => clk,
rst_n => rst_n,
seed_in_en => seed_in_en,
seed_in => seed_chain(i),
seed_out_c => seed_chain(i+1),
prob_in_en => prob_in_en,
prob_in => prob_chain(i),
prob_out_c => prob_chain(i+1),
shift_en => shift_en,
data_out => injectionvector(i),
data_out_valid => open);
end generate prsn_loop;
reg : process (clk_ce_m, rst_n)
begin -- process reg
if rst_n = '0' then -- asynchronous reset (active low)
injectionvector_reg <= (others => '0');
--injectionvector_reg_o <= (others => '0');
--test <= (others => '0');
elsif clk_ce_m'event and clk_ce_m = '1' then -- rising clock edge
injectionvector_reg <= injectionvector;
--injectionvector_reg <= (others => '0');
--test <= injectionvector_reg_o(31 downto 0);
--injectionvector_reg_o(31 downto 0) <= injectionvector_reg_o(31 downto 0) or (resultvector_f(31 downto 0) xor resultvector_o(31 downto 0));
end if;
end process reg;
end behav;
| gpl-2.0 | d34ccd00151e03c052e534d54c7a5eb0 | 0.544919 | 3.650538 | false | true | false | false |
TanND/Electronic | VHDL/D4_C2.vhd | 1 | 745 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D4_C2 is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR(7 downto 0)
);
end D4_C2;
architecture D4_C2 of D4_C2 is
begin
process(rst,clk)
variable dem:integer range 0 to 8;
begin
if (rst='1') then dem:=0;
elsif (rising_edge(clk)) then
if (dem=8) then dem:=0;
else dem:=dem+1;
end if;
end if;
case dem is
when 0=> seg <="00000000";
when 1=> seg <="00000001";
when 2=> seg <="00000011";
when 3=> seg <="00000111";
when 4=> seg <="00001111";
when 5=> seg <="00011111";
when 6=> seg <="00111111";
when 7=> seg <="01111111";
when others=> seg <="11111111";
end case;
end process;
end D4_C2;
--rst=0.5Mhz; clk=20Mhz; | apache-2.0 | 1a5511e53b1abafadc6785c32aa2bfd0 | 0.608054 | 2.651246 | false | false | false | false |
bruskajp/EE-316 | Project2/Vivado_NexysBoard/project_2b/project_2b.srcs/sources_1/ip/blk_mem_LUT/synth/blk_mem_LUT.vhd | 1 | 14,228 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_3;
USE blk_mem_gen_v8_3_3.blk_mem_gen_v8_3_3;
ENTITY blk_mem_LUT IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END blk_mem_LUT;
ARCHITECTURE blk_mem_LUT_arch OF blk_mem_LUT IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF blk_mem_LUT_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_3 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_3;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF blk_mem_LUT_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_3,Vivado 2016.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF blk_mem_LUT_arch : ARCHITECTURE IS "blk_mem_LUT,blk_mem_gen_v8_3_3,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF blk_mem_LUT_arch: ARCHITECTURE IS "blk_mem_LUT,blk_mem_gen_v8_3_3,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=blk_mem_LU" &
"T.mif,C_INIT_FILE=blk_mem_LUT.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=16,C_READ_DEPTH_A=16,C_ADDRA_WIDTH=4,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=16,C_READ_WIDTH_B=16,C_WRITE_DEP" &
"TH_B=16,C_READ_DEPTH_B=16,C_ADDRB_WIDTH=4,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_" &
"BHV_RANGE=0,C_COUNT_36K_BRAM=0,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.7096 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_3
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 3,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "blk_mem_LUT.mif",
C_INIT_FILE => "blk_mem_LUT.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 16,
C_READ_WIDTH_A => 16,
C_WRITE_DEPTH_A => 16,
C_READ_DEPTH_A => 16,
C_ADDRA_WIDTH => 4,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 16,
C_READ_WIDTH_B => 16,
C_WRITE_DEPTH_B => 16,
C_READ_DEPTH_B => 16,
C_ADDRB_WIDTH => 4,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "0",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.7096 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addra => addra,
dina => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END blk_mem_LUT_arch;
| gpl-3.0 | eafd892489016709bc578a0d6c53969d | 0.623559 | 2.992219 | false | false | false | false |
lnls-dig/dsp-cores | hdl/testbench/cordic_iter_slv/cordic_slv_tb.vhd | 1 | 7,349 | -------------------------------------------------------------------------------
-- Title : Cordic SLV testbench
-- Project :
-------------------------------------------------------------------------------
-- File : cordic_slv_tb.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2015-06-11
-- Last update: 2015-06-12
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: SLV version of cordic_tb.
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public License
-- as published by the Free Software Foundation, either version 3 of
-- the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-06-11 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
use std.textio.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
use work.test_pkg.all;
entity cordic_slv_tb is
end entity cordic_slv_tb;
architecture test of cordic_slv_tb is
constant c_CLK_FREQ : real := 100.0e6; -- input clock frequency
constant c_CYCLES_TO_RESET : natural := 4; -- number of clock cycles before reset
constant c_CYCLES_TO_CE_INPUT : natural := 100; -- number of clock cycles for
-- input ce
constant c_CYCLES_TO_CE_CORDIC : natural := 4; -- number of clock cycles for
-- cordic ce
constant c_INPUT_FILE : string := "input.samples";
constant c_OUTPUT_FILE : string := "output.samples";
constant c_INPUT_WIDTH : positive := 32;
constant c_OUTPUT_WIDTH : positive := 32;
constant c_INTERNAL_WIDTH : positive := 38; -- output_width + log2(c_ITER) +
-- 2
constant c_PHASE_OUTPUT_WIDTH : positive := 32; -- width of phase output
constant c_PHASE_INTERNAL_WIDTH : positive := 34; -- width of cordic phase
constant c_ITER : positive := 16; -- number of cordic steps
constant c_ITER_PER_CLK : positive := 2; -- number of iterations per clock cycle
constant c_USE_CE : boolean := true; -- clock enable in cordic
constant c_ROUNDING : boolean := true; -- enable rounding in cordic
constant c_USE_INREG : boolean := true; -- use input register
signal clk : std_ulogic := '0'; -- clock signal
signal rst : std_ulogic := '1'; -- reset signal
signal ce_input : std_ulogic := '0'; -- clock enable
signal ce_cordic : std_ulogic := '0'; -- clock enable
signal valid_in : std_ulogic; -- signals valid input data
signal valid_out : std_ulogic; -- signals new valid output
signal cordic_busy : std_ulogic; -- signals cordic not ready for new inputs
signal cordic_ready : std_ulogic; -- negated cordic_busy
signal end_of_file : std_ulogic;
signal x : signed(c_INPUT_WIDTH-1 downto 0); -- x from the input
signal y : signed(c_INPUT_WIDTH-1 downto 0); -- y from the input
signal x_slv : std_logic_vector(c_INPUT_WIDTH-1 downto 0); -- x from the input
signal y_slv : std_logic_vector(c_INPUT_WIDTH-1 downto 0); -- y from the input
signal mag : signed(c_OUTPUT_WIDTH-1 downto 0); -- magnitude from X output in
-- cordic
signal phase : signed(c_PHASE_OUTPUT_WIDTH-1 downto 0); -- phase from PH output of cordic
signal mag_slv : std_logic_vector(c_OUTPUT_WIDTH-1 downto 0); -- magnitude from X output in
-- cordic
signal phase_slv : std_logic_vector(c_PHASE_OUTPUT_WIDTH-1 downto 0); -- phase from PH output of cordic
component cordic_iter_slv is
generic (
g_input_width : positive;
g_xy_calc_width : positive;
g_x_output_width : positive;
g_phase_calc_width : positive;
g_phase_output_width : positive;
g_stages : positive;
g_iter_per_clk : positive;
g_rounding : boolean);
port (
clk_i : in std_logic;
ce_data_i : in std_logic;
valid_i : in std_logic;
ce_i : in std_logic;
x_i : in std_logic_vector;
y_i : in std_logic_vector;
mag_o : out std_logic_vector;
phase_o : out std_logic_vector;
valid_o : out std_logic);
end component cordic_iter_slv;
begin -- architecture test
p_clk_gen (
clk => clk,
c_FREQ => c_CLK_FREQ);
p_rst_gen (
clk => clk,
rst => rst,
c_CYCLES => 2);
p_ce_gen (
clk => clk,
ce => ce_input,
rst => rst,
c_CYCLES => c_CYCLES_TO_CE_INPUT);
p_ce_gen (
clk => clk,
ce => ce_cordic,
rst => rst,
c_CYCLES => c_CYCLES_TO_CE_CORDIC);
p_read_tsv_file_signed (
c_INPUT_FILE_NAME => c_INPUT_FILE,
c_SAMPLES_PER_LINE => 2,
c_OUTPUT_WIDTH => c_INPUT_WIDTH, --input for the testbench, not the procedure
clk => clk,
rst => rst,
ce => ce_input,
req => ce_input,
sample(0) => x,
sample(1) => y,
valid => valid_in,
end_of_file => end_of_file);
x_slv <= std_logic_vector(x);
y_slv <= std_logic_vector(y);
uut : cordic_iter_slv
generic map (
g_input_width => c_INPUT_WIDTH,
g_xy_calc_width => c_INTERNAL_WIDTH,
g_x_output_width => c_OUTPUT_WIDTH,
g_phase_calc_width => c_PHASE_INTERNAL_WIDTH,
g_phase_output_width => c_PHASE_OUTPUT_WIDTH,
g_stages => c_ITER,
g_iter_per_clk => c_ITER_PER_CLK,
g_rounding => c_ROUNDING)
port map (
clk_i => clk,
ce_data_i => ce_input,
valid_i => valid_in,
ce_i => ce_cordic,
x_i => x_slv,
y_i => y_slv,
mag_o => mag_slv,
phase_o => phase_slv,
valid_o => valid_out);
mag <= signed(mag_slv);
phase <= signed(phase_slv);
p_write_tsv_file_signed (
c_OUTPUT_FILE_NAME => c_OUTPUT_FILE,
c_SAMPLES_PER_LINE => 2,
c_OUTPUT_WIDTH => c_OUTPUT_WIDTH,
clk => clk,
rst => rst,
ce => ce_cordic,
sample(0) => mag,
sample(1) => phase,
valid => valid_out,
end_of_file => end_of_file);
end architecture test;
| lgpl-3.0 | ffabf3988a038e635411513e4e90588b | 0.528099 | 3.732351 | false | false | false | false |
bruskajp/EE-316 | Project1/counter.vhd | 1 | 2,363 | ----------------------------------------------------------------------------------
-- Institution: Clarkson Univeristy
-- Engineer: Zander Blasingame and Brandon Norris
--
-- Create Date: 11/11/2016 21:06:23
-- Design Name:
-- Module Name: counter - Behavioral
-- Project Name: Final Exam
-- Target Devices: Nexys4 DDR
-- Tool Versions:
-- Description: Final Exam for Dr. Abul Khondker's EE 365 class
-- of Fall 2016. counter has two inputs and three outputs
-- as described in the project description.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
entity counter is
Generic (
-- Input clk frequency is given as 50MHz
-- Number picked such that T = 1s
constant cnt_max : integer := 50000000
);
Port (
iClk : in STD_LOGIC;
iReset : in STD_LOGIC;
is_forward : in STD_LOGIC;
is_enabled : in STD_LOGIC;
output_data : out STD_LOGIC_VECTOR(7 downto 0)
);
end counter;
architecture Behavioral of counter is
-- Define signals here
signal clk_enable : std_logic := '1';
signal clk_cnt : integer range 0 to cnt_max;
signal output_cnt : integer range 0 to 255 := 0;
begin
-- Clock enabler
process(iClk)
begin
if rising_edge(iClk) then
if clk_cnt = cnt_max then
clk_cnt <= 0;
clk_enable <= '1';
else
clk_cnt <= clk_cnt + 1;
clk_enable <= '0';
end if;
end if;
end process;
-- oEnable selection clock
process(iClk, iReset, clk_enable, is_enabled)
begin
if iReset = '1' then
output_cnt <= 0;
elsif rising_edge(iClk) and clk_enable = '1' and is_enabled = '1' then
if is_forward = '1' then
if output_cnt = 255 then
output_cnt <= 0;
else
output_cnt <= output_cnt + 1;
end if;
else
if output_cnt = 0 then
output_cnt <= 255;
else
output_cnt <= output_cnt - 1;
end if;
end if;
end if;
end process;
output_data <= std_logic_vector(to_unsigned(output_cnt, 8));
end Behavioral; | gpl-3.0 | baedf0992f463fee599c8b5c2bfaf9f8 | 0.547609 | 3.861111 | false | false | false | false |
SoCdesign/EHA | RTL/Hand_Shaking/Hand_Shaking_FC/Router_32_bit_with_full_set_of_checkers.vhd | 1 | 71,441 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 5;
Rxy_rst : integer := 60;
Cx_rst : integer := 15;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
DCTS_N, DCTS_E, DCTS_w, DCTS_S, DCTS_L: in std_logic;
DRTS_N, DRTS_E, DRTS_W, DRTS_S, DRTS_L: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
RTS_N, RTS_E, RTS_W, RTS_S, RTS_L: out std_logic;
CTS_N, CTS_E, CTS_w, CTS_S, CTS_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
fault_out_N, fault_out_E, fault_out_W, fault_out_S, fault_out_L:out std_logic
);
end router;
architecture behavior of router is
COMPONENT FIFO
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
DRTS: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
CTS: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
-- Checker outputs
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_CTS_in,
err_write_en,
err_not_CTS_in,
err_not_write_en,
err_read_en_mismatch : out std_logic
);
end COMPONENT;
COMPONENT Arbiter
port ( reset: in std_logic;
clk: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules
DCTS: in std_logic; -- Getting the CTS signal from the input FIFO of the next router/NI (for hand-shaking)
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
Xbar_sel : out std_logic_vector(4 downto 0); -- select lines for XBAR
RTS: out std_logic; -- Valid output which is sent to the next router/NI to specify that the data on the output port is valid
-- Checker outputs
err_state_IDLE_xbar,
err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE,
err_IDLE_Req_L,
err_Local_Req_L,
err_North_Req_N,
err_East_Req_E,
err_West_Req_W,
err_South_Req_S,
err_IDLE_Req_N,
err_Local_Req_N,
err_North_Req_E,
err_East_Req_W,
err_West_Req_S,
err_South_Req_L,
err_IDLE_Req_E,
err_Local_Req_E,
err_North_Req_W,
err_East_Req_S,
err_West_Req_L,
err_South_Req_N,
err_IDLE_Req_W,
err_Local_Req_W,
err_North_Req_S,
err_East_Req_L,
err_West_Req_N,
err_South_Req_E,
err_IDLE_Req_S,
err_Local_Req_S,
err_North_Req_L,
err_East_Req_N,
err_West_Req_E,
err_South_Req_W,
err_next_state_onehot,
err_state_in_onehot,
err_DCTS_RTS_FF_state_Grant_L,
err_DCTS_RTS_FF_state_Grant_N,
err_DCTS_RTS_FF_state_Grant_E,
err_DCTS_RTS_FF_state_Grant_W,
err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel,
err_state_east_xbar_sel,
err_state_west_xbar_sel,
err_state_south_xbar_sel,
err_state_local_xbar_sel : out std_logic
);
end COMPONENT;
COMPONENT LBDR is
generic (
cur_addr_rst: integer := 5;
Rxy_rst: integer := 60;
Cx_rst: integer := 15;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic;
-- Checker outputs
err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in : out std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
-- Signals related to Checkers
-- LBDR Checkers signals
-- North
signal N_err_header_not_empty_Requests_in_onehot,
N_err_header_empty_Requests_FF_Requests_in,
N_err_tail_Requests_in_all_zero,
N_err_header_tail_Requests_FF_Requests_in,
N_err_dst_addr_cur_addr_N1,
N_err_dst_addr_cur_addr_not_N1,
N_err_dst_addr_cur_addr_E1,
N_err_dst_addr_cur_addr_not_E1,
N_err_dst_addr_cur_addr_W1,
N_err_dst_addr_cur_addr_not_W1,
N_err_dst_addr_cur_addr_S1,
N_err_dst_addr_cur_addr_not_S1,
N_err_dst_addr_cur_addr_not_Req_L_in,
N_err_dst_addr_cur_addr_Req_L_in,
N_err_header_not_empty_Req_N_in,
N_err_header_not_empty_Req_E_in,
N_err_header_not_empty_Req_W_in,
N_err_header_not_empty_Req_S_in : std_logic;
-- East
signal E_err_header_not_empty_Requests_in_onehot,
E_err_header_empty_Requests_FF_Requests_in,
E_err_tail_Requests_in_all_zero,
E_err_header_tail_Requests_FF_Requests_in,
E_err_dst_addr_cur_addr_N1,
E_err_dst_addr_cur_addr_not_N1,
E_err_dst_addr_cur_addr_E1,
E_err_dst_addr_cur_addr_not_E1,
E_err_dst_addr_cur_addr_W1,
E_err_dst_addr_cur_addr_not_W1,
E_err_dst_addr_cur_addr_S1,
E_err_dst_addr_cur_addr_not_S1,
E_err_dst_addr_cur_addr_not_Req_L_in,
E_err_dst_addr_cur_addr_Req_L_in,
E_err_header_not_empty_Req_N_in,
E_err_header_not_empty_Req_E_in,
E_err_header_not_empty_Req_W_in,
E_err_header_not_empty_Req_S_in : std_logic;
-- West
signal W_err_header_not_empty_Requests_in_onehot,
W_err_header_empty_Requests_FF_Requests_in,
W_err_tail_Requests_in_all_zero,
W_err_header_tail_Requests_FF_Requests_in,
W_err_dst_addr_cur_addr_N1,
W_err_dst_addr_cur_addr_not_N1,
W_err_dst_addr_cur_addr_E1,
W_err_dst_addr_cur_addr_not_E1,
W_err_dst_addr_cur_addr_W1,
W_err_dst_addr_cur_addr_not_W1,
W_err_dst_addr_cur_addr_S1,
W_err_dst_addr_cur_addr_not_S1,
W_err_dst_addr_cur_addr_not_Req_L_in,
W_err_dst_addr_cur_addr_Req_L_in,
W_err_header_not_empty_Req_N_in,
W_err_header_not_empty_Req_E_in,
W_err_header_not_empty_Req_W_in,
W_err_header_not_empty_Req_S_in : std_logic;
-- South
signal S_err_header_not_empty_Requests_in_onehot,
S_err_header_empty_Requests_FF_Requests_in,
S_err_tail_Requests_in_all_zero,
S_err_header_tail_Requests_FF_Requests_in,
S_err_dst_addr_cur_addr_N1,
S_err_dst_addr_cur_addr_not_N1,
S_err_dst_addr_cur_addr_E1,
S_err_dst_addr_cur_addr_not_E1,
S_err_dst_addr_cur_addr_W1,
S_err_dst_addr_cur_addr_not_W1,
S_err_dst_addr_cur_addr_S1,
S_err_dst_addr_cur_addr_not_S1,
S_err_dst_addr_cur_addr_not_Req_L_in,
S_err_dst_addr_cur_addr_Req_L_in,
S_err_header_not_empty_Req_N_in,
S_err_header_not_empty_Req_E_in,
S_err_header_not_empty_Req_W_in,
S_err_header_not_empty_Req_S_in : std_logic;
-- Local
signal L_err_header_not_empty_Requests_in_onehot,
L_err_header_empty_Requests_FF_Requests_in,
L_err_tail_Requests_in_all_zero,
L_err_header_tail_Requests_FF_Requests_in,
L_err_dst_addr_cur_addr_N1,
L_err_dst_addr_cur_addr_not_N1,
L_err_dst_addr_cur_addr_E1,
L_err_dst_addr_cur_addr_not_E1,
L_err_dst_addr_cur_addr_W1,
L_err_dst_addr_cur_addr_not_W1,
L_err_dst_addr_cur_addr_S1,
L_err_dst_addr_cur_addr_not_S1,
L_err_dst_addr_cur_addr_not_Req_L_in,
L_err_dst_addr_cur_addr_Req_L_in,
L_err_header_not_empty_Req_N_in,
L_err_header_not_empty_Req_E_in,
L_err_header_not_empty_Req_W_in,
L_err_header_not_empty_Req_S_in : std_logic;
-- Arbiter Checkers signals
-- North
signal N_err_state_IDLE_xbar,
N_err_state_not_IDLE_xbar,
N_err_state_IDLE_RTS_FF_in,
N_err_state_not_IDLE_RTS_FF_RTS_FF_in,
N_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
N_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
N_err_RTS_FF_not_DCTS_state_state_in,
N_err_not_RTS_FF_state_in_next_state,
N_err_RTS_FF_DCTS_state_in_next_state,
N_err_not_DCTS_Grants,
N_err_DCTS_not_RTS_FF_Grants,
N_err_DCTS_RTS_FF_IDLE_Grants,
N_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
N_err_Requests_next_state_IDLE,
N_err_IDLE_Req_L,
N_err_Local_Req_L,
N_err_North_Req_N,
N_err_East_Req_E,
N_err_West_Req_W,
N_err_South_Req_S,
N_err_IDLE_Req_N,
N_err_Local_Req_N,
N_err_North_Req_E,
N_err_East_Req_W,
N_err_West_Req_S,
N_err_South_Req_L,
N_err_IDLE_Req_E,
N_err_Local_Req_E,
N_err_North_Req_W,
N_err_East_Req_S,
N_err_West_Req_L,
N_err_South_Req_N,
N_err_IDLE_Req_W,
N_err_Local_Req_W,
N_err_North_Req_S,
N_err_East_Req_L,
N_err_West_Req_N,
N_err_South_Req_E,
N_err_IDLE_Req_S,
N_err_Local_Req_S,
N_err_North_Req_L,
N_err_East_Req_N,
N_err_West_Req_E,
N_err_South_Req_W,
N_err_next_state_onehot,
N_err_state_in_onehot,
N_err_DCTS_RTS_FF_state_Grant_L,
N_err_DCTS_RTS_FF_state_Grant_N,
N_err_DCTS_RTS_FF_state_Grant_E,
N_err_DCTS_RTS_FF_state_Grant_W,
N_err_DCTS_RTS_FF_state_Grant_S,
N_err_state_north_xbar_sel,
N_err_state_east_xbar_sel,
N_err_state_west_xbar_sel,
N_err_state_south_xbar_sel,
N_err_state_local_xbar_sel: std_logic;
-- East
signal E_err_state_IDLE_xbar,
E_err_state_not_IDLE_xbar,
E_err_state_IDLE_RTS_FF_in,
E_err_state_not_IDLE_RTS_FF_RTS_FF_in,
E_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
E_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
E_err_RTS_FF_not_DCTS_state_state_in,
E_err_not_RTS_FF_state_in_next_state,
E_err_RTS_FF_DCTS_state_in_next_state,
E_err_not_DCTS_Grants,
E_err_DCTS_not_RTS_FF_Grants,
E_err_DCTS_RTS_FF_IDLE_Grants,
E_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
E_err_Requests_next_state_IDLE,
E_err_IDLE_Req_L,
E_err_Local_Req_L,
E_err_North_Req_N,
E_err_East_Req_E,
E_err_West_Req_W,
E_err_South_Req_S,
E_err_IDLE_Req_N,
E_err_Local_Req_N,
E_err_North_Req_E,
E_err_East_Req_W,
E_err_West_Req_S,
E_err_South_Req_L,
E_err_IDLE_Req_E,
E_err_Local_Req_E,
E_err_North_Req_W,
E_err_East_Req_S,
E_err_West_Req_L,
E_err_South_Req_N,
E_err_IDLE_Req_W,
E_err_Local_Req_W,
E_err_North_Req_S,
E_err_East_Req_L,
E_err_West_Req_N,
E_err_South_Req_E,
E_err_IDLE_Req_S,
E_err_Local_Req_S,
E_err_North_Req_L,
E_err_East_Req_N,
E_err_West_Req_E,
E_err_South_Req_W,
E_err_next_state_onehot,
E_err_state_in_onehot,
E_err_DCTS_RTS_FF_state_Grant_L,
E_err_DCTS_RTS_FF_state_Grant_N,
E_err_DCTS_RTS_FF_state_Grant_E,
E_err_DCTS_RTS_FF_state_Grant_W,
E_err_DCTS_RTS_FF_state_Grant_S,
E_err_state_north_xbar_sel,
E_err_state_east_xbar_sel,
E_err_state_west_xbar_sel,
E_err_state_south_xbar_sel,
E_err_state_local_xbar_sel: std_logic;
-- West
signal W_err_state_IDLE_xbar,
W_err_state_not_IDLE_xbar,
W_err_state_IDLE_RTS_FF_in,
W_err_state_not_IDLE_RTS_FF_RTS_FF_in,
W_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
W_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
W_err_RTS_FF_not_DCTS_state_state_in,
W_err_not_RTS_FF_state_in_next_state,
W_err_RTS_FF_DCTS_state_in_next_state,
W_err_not_DCTS_Grants,
W_err_DCTS_not_RTS_FF_Grants,
W_err_DCTS_RTS_FF_IDLE_Grants,
W_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
W_err_Requests_next_state_IDLE,
W_err_IDLE_Req_L,
W_err_Local_Req_L,
W_err_North_Req_N,
W_err_East_Req_E,
W_err_West_Req_W,
W_err_South_Req_S,
W_err_IDLE_Req_N,
W_err_Local_Req_N,
W_err_North_Req_E,
W_err_East_Req_W,
W_err_West_Req_S,
W_err_South_Req_L,
W_err_IDLE_Req_E,
W_err_Local_Req_E,
W_err_North_Req_W,
W_err_East_Req_S,
W_err_West_Req_L,
W_err_South_Req_N,
W_err_IDLE_Req_W,
W_err_Local_Req_W,
W_err_North_Req_S,
W_err_East_Req_L,
W_err_West_Req_N,
W_err_South_Req_E,
W_err_IDLE_Req_S,
W_err_Local_Req_S,
W_err_North_Req_L,
W_err_East_Req_N,
W_err_West_Req_E,
W_err_South_Req_W,
W_err_next_state_onehot,
W_err_state_in_onehot,
W_err_DCTS_RTS_FF_state_Grant_L,
W_err_DCTS_RTS_FF_state_Grant_N,
W_err_DCTS_RTS_FF_state_Grant_E,
W_err_DCTS_RTS_FF_state_Grant_W,
W_err_DCTS_RTS_FF_state_Grant_S,
W_err_state_north_xbar_sel,
W_err_state_east_xbar_sel,
W_err_state_west_xbar_sel,
W_err_state_south_xbar_sel,
W_err_state_local_xbar_sel: std_logic;
-- South
signal S_err_state_IDLE_xbar,
S_err_state_not_IDLE_xbar,
S_err_state_IDLE_RTS_FF_in,
S_err_state_not_IDLE_RTS_FF_RTS_FF_in,
S_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
S_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
S_err_RTS_FF_not_DCTS_state_state_in,
S_err_not_RTS_FF_state_in_next_state,
S_err_RTS_FF_DCTS_state_in_next_state,
S_err_not_DCTS_Grants,
S_err_DCTS_not_RTS_FF_Grants,
S_err_DCTS_RTS_FF_IDLE_Grants,
S_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
S_err_Requests_next_state_IDLE,
S_err_IDLE_Req_L,
S_err_Local_Req_L,
S_err_North_Req_N,
S_err_East_Req_E,
S_err_West_Req_W,
S_err_South_Req_S,
S_err_IDLE_Req_N,
S_err_Local_Req_N,
S_err_North_Req_E,
S_err_East_Req_W,
S_err_West_Req_S,
S_err_South_Req_L,
S_err_IDLE_Req_E,
S_err_Local_Req_E,
S_err_North_Req_W,
S_err_East_Req_S,
S_err_West_Req_L,
S_err_South_Req_N,
S_err_IDLE_Req_W,
S_err_Local_Req_W,
S_err_North_Req_S,
S_err_East_Req_L,
S_err_West_Req_N,
S_err_South_Req_E,
S_err_IDLE_Req_S,
S_err_Local_Req_S,
S_err_North_Req_L,
S_err_East_Req_N,
S_err_West_Req_E,
S_err_South_Req_W,
S_err_next_state_onehot,
S_err_state_in_onehot,
S_err_DCTS_RTS_FF_state_Grant_L,
S_err_DCTS_RTS_FF_state_Grant_N,
S_err_DCTS_RTS_FF_state_Grant_E,
S_err_DCTS_RTS_FF_state_Grant_W,
S_err_DCTS_RTS_FF_state_Grant_S,
S_err_state_north_xbar_sel,
S_err_state_east_xbar_sel,
S_err_state_west_xbar_sel,
S_err_state_south_xbar_sel,
S_err_state_local_xbar_sel: std_logic;
-- Local
signal L_err_state_IDLE_xbar,
L_err_state_not_IDLE_xbar,
L_err_state_IDLE_RTS_FF_in,
L_err_state_not_IDLE_RTS_FF_RTS_FF_in,
L_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
L_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
L_err_RTS_FF_not_DCTS_state_state_in,
L_err_not_RTS_FF_state_in_next_state,
L_err_RTS_FF_DCTS_state_in_next_state,
L_err_not_DCTS_Grants,
L_err_DCTS_not_RTS_FF_Grants,
L_err_DCTS_RTS_FF_IDLE_Grants,
L_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
L_err_Requests_next_state_IDLE,
L_err_IDLE_Req_L,
L_err_Local_Req_L,
L_err_North_Req_N,
L_err_East_Req_E,
L_err_West_Req_W,
L_err_South_Req_S,
L_err_IDLE_Req_N,
L_err_Local_Req_N,
L_err_North_Req_E,
L_err_East_Req_W,
L_err_West_Req_S,
L_err_South_Req_L,
L_err_IDLE_Req_E,
L_err_Local_Req_E,
L_err_North_Req_W,
L_err_East_Req_S,
L_err_West_Req_L,
L_err_South_Req_N,
L_err_IDLE_Req_W,
L_err_Local_Req_W,
L_err_North_Req_S,
L_err_East_Req_L,
L_err_West_Req_N,
L_err_South_Req_E,
L_err_IDLE_Req_S,
L_err_Local_Req_S,
L_err_North_Req_L,
L_err_East_Req_N,
L_err_West_Req_E,
L_err_South_Req_W,
L_err_next_state_onehot,
L_err_state_in_onehot,
L_err_DCTS_RTS_FF_state_Grant_L,
L_err_DCTS_RTS_FF_state_Grant_N,
L_err_DCTS_RTS_FF_state_Grant_E,
L_err_DCTS_RTS_FF_state_Grant_W,
L_err_DCTS_RTS_FF_state_Grant_S,
L_err_state_north_xbar_sel,
L_err_state_east_xbar_sel,
L_err_state_west_xbar_sel,
L_err_state_south_xbar_sel,
L_err_state_local_xbar_sel: std_logic;
-- FIFO Control Part Checkers signals
-- North
signal N_err_write_en_write_pointer,
N_err_not_write_en_write_pointer,
N_err_read_pointer_write_pointer_not_empty,
N_err_read_pointer_write_pointer_empty,
N_err_read_pointer_write_pointer_not_full,
N_err_read_pointer_write_pointer_full,
N_err_read_pointer_increment,
N_err_read_pointer_not_increment,
N_err_CTS_in,
N_err_write_en,
N_err_not_CTS_in,
N_err_not_write_en,
N_err_read_en_mismatch : std_logic;
-- East
signal E_err_write_en_write_pointer,
E_err_not_write_en_write_pointer,
E_err_read_pointer_write_pointer_not_empty,
E_err_read_pointer_write_pointer_empty,
E_err_read_pointer_write_pointer_not_full,
E_err_read_pointer_write_pointer_full,
E_err_read_pointer_increment,
E_err_read_pointer_not_increment,
E_err_CTS_in,
E_err_write_en,
E_err_not_CTS_in,
E_err_not_write_en,
E_err_read_en_mismatch : std_logic;
-- West
signal W_err_write_en_write_pointer,
W_err_not_write_en_write_pointer,
W_err_read_pointer_write_pointer_not_empty,
W_err_read_pointer_write_pointer_empty,
W_err_read_pointer_write_pointer_not_full,
W_err_read_pointer_write_pointer_full,
W_err_read_pointer_increment,
W_err_read_pointer_not_increment,
W_err_CTS_in,
W_err_write_en,
W_err_not_CTS_in,
W_err_not_write_en,
W_err_read_en_mismatch : std_logic;
-- South
signal S_err_write_en_write_pointer,
S_err_not_write_en_write_pointer,
S_err_read_pointer_write_pointer_not_empty,
S_err_read_pointer_write_pointer_empty,
S_err_read_pointer_write_pointer_not_full,
S_err_read_pointer_write_pointer_full,
S_err_read_pointer_increment,
S_err_read_pointer_not_increment,
S_err_CTS_in,
S_err_write_en,
S_err_not_CTS_in,
S_err_not_write_en,
S_err_read_en_mismatch : std_logic;
-- Local
signal L_err_write_en_write_pointer,
L_err_not_write_en_write_pointer,
L_err_read_pointer_write_pointer_not_empty,
L_err_read_pointer_write_pointer_empty,
L_err_read_pointer_write_pointer_not_full,
L_err_read_pointer_write_pointer_full,
L_err_read_pointer_increment,
L_err_read_pointer_not_increment,
L_err_CTS_in,
L_err_write_en,
L_err_not_CTS_in,
L_err_not_write_en,
L_err_read_en_mismatch : std_logic;
begin
--
------------------------------------------------------------------------------------------------------------------------------
-- block diagram of one channel
--
-- .____________grant_________
-- | ▲
-- | _______ __|_______
-- | | | | |
-- | | LBDR |---req--->| Arbiter | <--handshake-->
-- | |_______| |__________| signals
-- | ▲ |
-- __▼___ | flit ___▼__
-- RX ----->| | | type | |
-- <-handshake->| FIFO |---o------------->| |-----> TX
-- signals |______| ------>| |
-- ------>| XBAR |
-- ------>| |
-- ------>| |
-- |______|
--
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the FIFOs
FIFO_N: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_N, DRTS => DRTS_N,
read_en_N => '0', read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
CTS => CTS_N, empty_out => empty_N, Data_out => FIFO_D_out_N,
err_write_en_write_pointer => N_err_write_en_write_pointer,
err_not_write_en_write_pointer => N_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => N_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => N_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => N_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => N_err_read_pointer_write_pointer_full,
err_read_pointer_increment => N_err_read_pointer_increment,
err_read_pointer_not_increment => N_err_read_pointer_not_increment,
err_CTS_in => N_err_CTS_in,
err_write_en => N_err_write_en,
err_not_CTS_in => N_err_not_CTS_in,
err_not_write_en => N_err_not_write_en,
err_read_en_mismatch => N_err_read_en_mismatch
);
FIFO_E: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_E, DRTS => DRTS_E,
read_en_N => Grant_NE, read_en_E =>'0', read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
CTS => CTS_E, empty_out => empty_E, Data_out => FIFO_D_out_E,
err_write_en_write_pointer => E_err_write_en_write_pointer,
err_not_write_en_write_pointer => E_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => E_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => E_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => E_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => E_err_read_pointer_write_pointer_full,
err_read_pointer_increment => E_err_read_pointer_increment,
err_read_pointer_not_increment => E_err_read_pointer_not_increment,
err_CTS_in => E_err_CTS_in,
err_write_en => E_err_write_en,
err_not_CTS_in => E_err_not_CTS_in,
err_not_write_en => E_err_not_write_en,
err_read_en_mismatch => E_err_read_en_mismatch
);
FIFO_W: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_W, DRTS => DRTS_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>'0', read_en_S =>Grant_SW, read_en_L =>Grant_LW,
CTS => CTS_W, empty_out => empty_W, Data_out => FIFO_D_out_W,
err_write_en_write_pointer => W_err_write_en_write_pointer,
err_not_write_en_write_pointer => W_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => W_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => W_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => W_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => W_err_read_pointer_write_pointer_full,
err_read_pointer_increment => W_err_read_pointer_increment,
err_read_pointer_not_increment => W_err_read_pointer_not_increment,
err_CTS_in => W_err_CTS_in,
err_write_en => W_err_write_en,
err_not_CTS_in => W_err_not_CTS_in,
err_not_write_en => W_err_not_write_en,
err_read_en_mismatch => W_err_read_en_mismatch
);
FIFO_S: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_S, DRTS => DRTS_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>'0', read_en_L =>Grant_LS,
CTS => CTS_S, empty_out => empty_S, Data_out => FIFO_D_out_S,
err_write_en_write_pointer => S_err_write_en_write_pointer,
err_not_write_en_write_pointer => S_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => S_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => S_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => S_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => S_err_read_pointer_write_pointer_full,
err_read_pointer_increment => S_err_read_pointer_increment,
err_read_pointer_not_increment => S_err_read_pointer_not_increment,
err_CTS_in => S_err_CTS_in,
err_write_en => S_err_write_en,
err_not_CTS_in => S_err_not_CTS_in,
err_not_write_en => S_err_not_write_en,
err_read_en_mismatch => S_err_read_en_mismatch
);
FIFO_L: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_L, DRTS => DRTS_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>'0',
CTS => CTS_L, empty_out => empty_L, Data_out => FIFO_D_out_L,
err_write_en_write_pointer => L_err_write_en_write_pointer,
err_not_write_en_write_pointer => L_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => L_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => L_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => L_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => L_err_read_pointer_write_pointer_full,
err_read_pointer_increment => L_err_read_pointer_increment,
err_read_pointer_not_increment => L_err_read_pointer_not_increment,
err_CTS_in => L_err_CTS_in,
err_write_en => L_err_write_en,
err_not_CTS_in => L_err_not_CTS_in,
err_not_write_en => L_err_not_write_en,
err_read_en_mismatch => L_err_read_en_mismatch
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the LBDRs
LBDR_N: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N, flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL,
err_header_not_empty_Requests_in_onehot => N_err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in => N_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => N_err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in => N_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => N_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => N_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => N_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => N_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => N_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => N_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => N_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => N_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => N_err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => N_err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => N_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => N_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => N_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => N_err_header_not_empty_Req_S_in
);
LBDR_E: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E, flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL,
err_header_not_empty_Requests_in_onehot => E_err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in => E_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => E_err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in => E_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => E_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => E_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => E_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => E_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => E_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => E_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => E_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => E_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => E_err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => E_err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => E_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => E_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => E_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => E_err_header_not_empty_Req_S_in
);
LBDR_W: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W, flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL,
err_header_not_empty_Requests_in_onehot => W_err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in => W_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => W_err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in => W_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => W_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => W_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => W_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => W_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => W_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => W_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => W_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => W_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => W_err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => W_err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => W_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => W_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => W_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => W_err_header_not_empty_Req_S_in
);
LBDR_S: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S, flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL,
err_header_not_empty_Requests_in_onehot => S_err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in => S_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => S_err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in => S_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => S_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => S_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => S_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => S_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => S_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => S_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => S_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => S_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => S_err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => S_err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => S_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => S_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => S_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => S_err_header_not_empty_Req_S_in
);
LBDR_L: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L, flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL,
err_header_not_empty_Requests_in_onehot => L_err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in => L_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => L_err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in => L_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => L_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => L_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => L_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => L_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => L_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => L_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => L_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => L_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => L_err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => L_err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => L_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => L_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => L_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => L_err_header_not_empty_Req_S_in
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Arbiters
Arbiter_N: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => '0' , Req_E => Req_EN, Req_W => Req_WN, Req_S => Req_SN, Req_L => Req_LN,
DCTS => DCTS_N, Grant_N => Grant_NN, Grant_E => Grant_NE, Grant_W => Grant_NW, Grant_S => Grant_NS, Grant_L => Grant_NL,
Xbar_sel => Xbar_sel_N,
RTS => RTS_N,
err_state_IDLE_xbar => N_err_state_IDLE_xbar,
err_state_not_IDLE_xbar => N_err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in => N_err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in => N_err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => N_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => N_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in => N_err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state => N_err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state => N_err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants => N_err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants => N_err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants => N_err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => N_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE => N_err_Requests_next_state_IDLE,
err_IDLE_Req_L => N_err_IDLE_Req_L,
err_Local_Req_L => N_err_Local_Req_L,
err_North_Req_N => N_err_North_Req_N,
err_East_Req_E => N_err_East_Req_E,
err_West_Req_W => N_err_West_Req_W,
err_South_Req_S => N_err_South_Req_S,
err_IDLE_Req_N => N_err_IDLE_Req_N,
err_Local_Req_N => N_err_Local_Req_N,
err_North_Req_E => N_err_North_Req_E,
err_East_Req_W => N_err_East_Req_W,
err_West_Req_S => N_err_West_Req_S,
err_South_Req_L => N_err_South_Req_L,
err_IDLE_Req_E => N_err_IDLE_Req_E,
err_Local_Req_E => N_err_Local_Req_E,
err_North_Req_W => N_err_North_Req_W,
err_East_Req_S => N_err_East_Req_S,
err_West_Req_L => N_err_West_Req_L,
err_South_Req_N => N_err_South_Req_N,
err_IDLE_Req_W => N_err_IDLE_Req_W,
err_Local_Req_W => N_err_Local_Req_W,
err_North_Req_S => N_err_North_Req_S,
err_East_Req_L => N_err_East_Req_L,
err_West_Req_N => N_err_West_Req_N,
err_South_Req_E => N_err_South_Req_E,
err_IDLE_Req_S => N_err_IDLE_Req_S,
err_Local_Req_S => N_err_Local_Req_S,
err_North_Req_L => N_err_North_Req_L,
err_East_Req_N => N_err_East_Req_N,
err_West_Req_E => N_err_West_Req_E,
err_South_Req_W => N_err_South_Req_W,
err_next_state_onehot => N_err_next_state_onehot,
err_state_in_onehot => N_err_state_in_onehot,
err_DCTS_RTS_FF_state_Grant_L => N_err_DCTS_RTS_FF_state_Grant_L,
err_DCTS_RTS_FF_state_Grant_N => N_err_DCTS_RTS_FF_state_Grant_N,
err_DCTS_RTS_FF_state_Grant_E => N_err_DCTS_RTS_FF_state_Grant_E,
err_DCTS_RTS_FF_state_Grant_W => N_err_DCTS_RTS_FF_state_Grant_W,
err_DCTS_RTS_FF_state_Grant_S => N_err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel => N_err_state_north_xbar_sel,
err_state_east_xbar_sel => N_err_state_east_xbar_sel,
err_state_west_xbar_sel => N_err_state_west_xbar_sel,
err_state_south_xbar_sel => N_err_state_south_xbar_sel,
err_state_local_xbar_sel => N_err_state_local_xbar_sel
);
Arbiter_E: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NE , Req_E => '0', Req_W => Req_WE, Req_S => Req_SE, Req_L => Req_LE,
DCTS => DCTS_E, Grant_N => Grant_EN, Grant_E => Grant_EE, Grant_W => Grant_EW, Grant_S => Grant_ES, Grant_L => Grant_EL,
Xbar_sel => Xbar_sel_E,
RTS => RTS_E,
err_state_IDLE_xbar => E_err_state_IDLE_xbar,
err_state_not_IDLE_xbar => E_err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in => E_err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in => E_err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => E_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => E_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in => E_err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state => E_err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state => E_err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants => E_err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants => E_err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants => E_err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => E_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE => E_err_Requests_next_state_IDLE,
err_IDLE_Req_L => E_err_IDLE_Req_L,
err_Local_Req_L => E_err_Local_Req_L,
err_North_Req_N => E_err_North_Req_N,
err_East_Req_E => E_err_East_Req_E,
err_West_Req_W => E_err_West_Req_W,
err_South_Req_S => E_err_South_Req_S,
err_IDLE_Req_N => E_err_IDLE_Req_N,
err_Local_Req_N => E_err_Local_Req_N,
err_North_Req_E => E_err_North_Req_E,
err_East_Req_W => E_err_East_Req_W,
err_West_Req_S => E_err_West_Req_S,
err_South_Req_L => E_err_South_Req_L,
err_IDLE_Req_E => E_err_IDLE_Req_E,
err_Local_Req_E => E_err_Local_Req_E,
err_North_Req_W => E_err_North_Req_W,
err_East_Req_S => E_err_East_Req_S,
err_West_Req_L => E_err_West_Req_L,
err_South_Req_N => E_err_South_Req_N,
err_IDLE_Req_W => E_err_IDLE_Req_W,
err_Local_Req_W => E_err_Local_Req_W,
err_North_Req_S => E_err_North_Req_S,
err_East_Req_L => E_err_East_Req_L,
err_West_Req_N => E_err_West_Req_N,
err_South_Req_E => E_err_South_Req_E,
err_IDLE_Req_S => E_err_IDLE_Req_S,
err_Local_Req_S => E_err_Local_Req_S,
err_North_Req_L => E_err_North_Req_L,
err_East_Req_N => E_err_East_Req_N,
err_West_Req_E => E_err_West_Req_E,
err_South_Req_W => E_err_South_Req_W,
err_next_state_onehot => E_err_next_state_onehot,
err_state_in_onehot => E_err_state_in_onehot,
err_DCTS_RTS_FF_state_Grant_L => E_err_DCTS_RTS_FF_state_Grant_L,
err_DCTS_RTS_FF_state_Grant_N => E_err_DCTS_RTS_FF_state_Grant_N,
err_DCTS_RTS_FF_state_Grant_E => E_err_DCTS_RTS_FF_state_Grant_E,
err_DCTS_RTS_FF_state_Grant_W => E_err_DCTS_RTS_FF_state_Grant_W,
err_DCTS_RTS_FF_state_Grant_S => E_err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel => E_err_state_north_xbar_sel,
err_state_east_xbar_sel => E_err_state_east_xbar_sel,
err_state_west_xbar_sel => E_err_state_west_xbar_sel,
err_state_south_xbar_sel => E_err_state_south_xbar_sel,
err_state_local_xbar_sel => E_err_state_local_xbar_sel
);
Arbiter_W: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NW , Req_E => Req_EW, Req_W => '0', Req_S => Req_SW, Req_L => Req_LW,
DCTS => DCTS_W, Grant_N => Grant_WN, Grant_E => Grant_WE, Grant_W => Grant_WW, Grant_S => Grant_WS, Grant_L => Grant_WL,
Xbar_sel => Xbar_sel_W,
RTS => RTS_W,
err_state_IDLE_xbar => W_err_state_IDLE_xbar,
err_state_not_IDLE_xbar => W_err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in => W_err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in => W_err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => W_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => W_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in => W_err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state => W_err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state => W_err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants => W_err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants => W_err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants => W_err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => W_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE => W_err_Requests_next_state_IDLE,
err_IDLE_Req_L => W_err_IDLE_Req_L,
err_Local_Req_L => W_err_Local_Req_L,
err_North_Req_N => W_err_North_Req_N,
err_East_Req_E => W_err_East_Req_E,
err_West_Req_W => W_err_West_Req_W,
err_South_Req_S => W_err_South_Req_S,
err_IDLE_Req_N => W_err_IDLE_Req_N,
err_Local_Req_N => W_err_Local_Req_N,
err_North_Req_E => W_err_North_Req_E,
err_East_Req_W => W_err_East_Req_W,
err_West_Req_S => W_err_West_Req_S,
err_South_Req_L => W_err_South_Req_L,
err_IDLE_Req_E => W_err_IDLE_Req_E,
err_Local_Req_E => W_err_Local_Req_E,
err_North_Req_W => W_err_North_Req_W,
err_East_Req_S => W_err_East_Req_S,
err_West_Req_L => W_err_West_Req_L,
err_South_Req_N => W_err_South_Req_N,
err_IDLE_Req_W => W_err_IDLE_Req_W,
err_Local_Req_W => W_err_Local_Req_W,
err_North_Req_S => W_err_North_Req_S,
err_East_Req_L => W_err_East_Req_L,
err_West_Req_N => W_err_West_Req_N,
err_South_Req_E => W_err_South_Req_E,
err_IDLE_Req_S => W_err_IDLE_Req_S,
err_Local_Req_S => W_err_Local_Req_S,
err_North_Req_L => W_err_North_Req_L,
err_East_Req_N => W_err_East_Req_N,
err_West_Req_E => W_err_West_Req_E,
err_South_Req_W => W_err_South_Req_W,
err_next_state_onehot => W_err_next_state_onehot,
err_state_in_onehot => W_err_state_in_onehot,
err_DCTS_RTS_FF_state_Grant_L => W_err_DCTS_RTS_FF_state_Grant_L,
err_DCTS_RTS_FF_state_Grant_N => W_err_DCTS_RTS_FF_state_Grant_N,
err_DCTS_RTS_FF_state_Grant_E => W_err_DCTS_RTS_FF_state_Grant_E,
err_DCTS_RTS_FF_state_Grant_W => W_err_DCTS_RTS_FF_state_Grant_W,
err_DCTS_RTS_FF_state_Grant_S => W_err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel => W_err_state_north_xbar_sel,
err_state_east_xbar_sel => W_err_state_east_xbar_sel,
err_state_west_xbar_sel => W_err_state_west_xbar_sel,
err_state_south_xbar_sel => W_err_state_south_xbar_sel,
err_state_local_xbar_sel => W_err_state_local_xbar_sel
);
Arbiter_S: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NS , Req_E => Req_ES, Req_W => Req_WS, Req_S => '0', Req_L => Req_LS,
DCTS => DCTS_S, Grant_N => Grant_SN, Grant_E => Grant_SE, Grant_W => Grant_SW, Grant_S => Grant_SS, Grant_L => Grant_SL,
Xbar_sel => Xbar_sel_S,
RTS => RTS_S,
err_state_IDLE_xbar => S_err_state_IDLE_xbar,
err_state_not_IDLE_xbar => S_err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in => S_err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in => S_err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => S_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => S_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in => S_err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state => S_err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state => S_err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants => S_err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants => S_err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants => S_err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => S_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE => S_err_Requests_next_state_IDLE,
err_IDLE_Req_L => S_err_IDLE_Req_L,
err_Local_Req_L => S_err_Local_Req_L,
err_North_Req_N => S_err_North_Req_N,
err_East_Req_E => S_err_East_Req_E,
err_West_Req_W => S_err_West_Req_W,
err_South_Req_S => S_err_South_Req_S,
err_IDLE_Req_N => S_err_IDLE_Req_N,
err_Local_Req_N => S_err_Local_Req_N,
err_North_Req_E => S_err_North_Req_E,
err_East_Req_W => S_err_East_Req_W,
err_West_Req_S => S_err_West_Req_S,
err_South_Req_L => S_err_South_Req_L,
err_IDLE_Req_E => S_err_IDLE_Req_E,
err_Local_Req_E => S_err_Local_Req_E,
err_North_Req_W => S_err_North_Req_W,
err_East_Req_S => S_err_East_Req_S,
err_West_Req_L => S_err_West_Req_L,
err_South_Req_N => S_err_South_Req_N,
err_IDLE_Req_W => S_err_IDLE_Req_W,
err_Local_Req_W => S_err_Local_Req_W,
err_North_Req_S => S_err_North_Req_S,
err_East_Req_L => S_err_East_Req_L,
err_West_Req_N => S_err_West_Req_N,
err_South_Req_E => S_err_South_Req_E,
err_IDLE_Req_S => S_err_IDLE_Req_S,
err_Local_Req_S => S_err_Local_Req_S,
err_North_Req_L => S_err_North_Req_L,
err_East_Req_N => S_err_East_Req_N,
err_West_Req_E => S_err_West_Req_E,
err_South_Req_W => S_err_South_Req_W,
err_next_state_onehot => S_err_next_state_onehot,
err_state_in_onehot => S_err_state_in_onehot,
err_DCTS_RTS_FF_state_Grant_L => S_err_DCTS_RTS_FF_state_Grant_L,
err_DCTS_RTS_FF_state_Grant_N => S_err_DCTS_RTS_FF_state_Grant_N,
err_DCTS_RTS_FF_state_Grant_E => S_err_DCTS_RTS_FF_state_Grant_E,
err_DCTS_RTS_FF_state_Grant_W => S_err_DCTS_RTS_FF_state_Grant_W,
err_DCTS_RTS_FF_state_Grant_S => S_err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel => S_err_state_north_xbar_sel,
err_state_east_xbar_sel => S_err_state_east_xbar_sel,
err_state_west_xbar_sel => S_err_state_west_xbar_sel,
err_state_south_xbar_sel => S_err_state_south_xbar_sel,
err_state_local_xbar_sel => S_err_state_local_xbar_sel
);
Arbiter_L: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NL , Req_E => Req_EL, Req_W => Req_WL, Req_S => Req_SL, Req_L => '0',
DCTS => DCTS_L, Grant_N => Grant_LN, Grant_E => Grant_LE, Grant_W => Grant_LW, Grant_S => Grant_LS, Grant_L => Grant_LL,
Xbar_sel => Xbar_sel_L,
RTS => RTS_L,
err_state_IDLE_xbar => L_err_state_IDLE_xbar,
err_state_not_IDLE_xbar => L_err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in => L_err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in => L_err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => L_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => L_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in => L_err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state => L_err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state => L_err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants => L_err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants => L_err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants => L_err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => L_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE => L_err_Requests_next_state_IDLE,
err_IDLE_Req_L => L_err_IDLE_Req_L,
err_Local_Req_L => L_err_Local_Req_L,
err_North_Req_N => L_err_North_Req_N,
err_East_Req_E => L_err_East_Req_E,
err_West_Req_W => L_err_West_Req_W,
err_South_Req_S => L_err_South_Req_S,
err_IDLE_Req_N => L_err_IDLE_Req_N,
err_Local_Req_N => L_err_Local_Req_N,
err_North_Req_E => L_err_North_Req_E,
err_East_Req_W => L_err_East_Req_W,
err_West_Req_S => L_err_West_Req_S,
err_South_Req_L => L_err_South_Req_L,
err_IDLE_Req_E => L_err_IDLE_Req_E,
err_Local_Req_E => L_err_Local_Req_E,
err_North_Req_W => L_err_North_Req_W,
err_East_Req_S => L_err_East_Req_S,
err_West_Req_L => L_err_West_Req_L,
err_South_Req_N => L_err_South_Req_N,
err_IDLE_Req_W => L_err_IDLE_Req_W,
err_Local_Req_W => L_err_Local_Req_W,
err_North_Req_S => L_err_North_Req_S,
err_East_Req_L => L_err_East_Req_L,
err_West_Req_N => L_err_West_Req_N,
err_South_Req_E => L_err_South_Req_E,
err_IDLE_Req_S => L_err_IDLE_Req_S,
err_Local_Req_S => L_err_Local_Req_S,
err_North_Req_L => L_err_North_Req_L,
err_East_Req_N => L_err_East_Req_N,
err_West_Req_E => L_err_West_Req_E,
err_South_Req_W => L_err_South_Req_W,
err_next_state_onehot => L_err_next_state_onehot,
err_state_in_onehot => L_err_state_in_onehot,
err_DCTS_RTS_FF_state_Grant_L => L_err_DCTS_RTS_FF_state_Grant_L,
err_DCTS_RTS_FF_state_Grant_N => L_err_DCTS_RTS_FF_state_Grant_N,
err_DCTS_RTS_FF_state_Grant_E => L_err_DCTS_RTS_FF_state_Grant_E,
err_DCTS_RTS_FF_state_Grant_W => L_err_DCTS_RTS_FF_state_Grant_W,
err_DCTS_RTS_FF_state_Grant_S => L_err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel => L_err_state_north_xbar_sel,
err_state_east_xbar_sel => L_err_state_east_xbar_sel,
err_state_west_xbar_sel => L_err_state_west_xbar_sel,
err_state_south_xbar_sel => L_err_state_south_xbar_sel,
err_state_local_xbar_sel => L_err_state_local_xbar_sel
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
end;
| gpl-3.0 | ce2f21d6535c1e8905e5d6848d3cebbc | 0.47702 | 3.14475 | false | false | false | false |
TanND/Electronic | VHDL/D10_C1.vhd | 1 | 907 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D10_C1 is
port(
rst : in STD_LOGIC;
d : in BIT;
clk : in STD_LOGIC;
y : out STD_LOGIC
);
end D10_C1;
architecture D10_C1 of D10_C1 is
type state is (s0,s1,s2,s3);
signal s:state;
begin
next_state:process(rst,clk)
begin
if (rst='1') then s<=s0;
else
if (rising_edge(clk)) then
case s is
when s0 =>
if d='0' then s <=s0; else s<=s1;
end if;
when s1 =>
if d='0' then s <=s2; else s<=s3;
end if;
when s2 =>
if d='0' then s <=s0; else s<=s1;
end if;
when s3 =>
if d='0' then s <=s2; else s<=s3;
end if;
end case;
end if;
end if;
end process;
output:process(s,clk)
begin
if (rising_edge(clk)) then
if ((s=s3) and (d='1')) then
y<='1';
else y<='0';
end if;
end if;
end process;
end D10_C1;
--rst=500khz; d= random 100ns; clk= 5Mhz; | apache-2.0 | 63a2b6c7e702defb56d45367e26c4286 | 0.546858 | 2.313776 | false | false | false | false |
TUM-LIS/faultify | hardware/testcases/QR/fpga_sim/xpsLibraryPath_asic_400_599/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/vhdl/qr_pack.vhd | 4 | 1,995 | ----------------------------------------------------------------------------------
-- TU Kaiserslautern
-- Fachbereich Elektrotechnik und Informationstechnik
-- Package for global definitions of the QR decomposition hardware
-- by Gabriel Luca Nazar
-- July 2009
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package qr_pack is
------Global constants
constant WORD_WIDTH_G : integer := 12;
constant INT_BITS_G : integer := 4;
constant N_G : integer := 4;
constant LOG2_N_G : integer := 2;
constant LOG_WORD_WIDTH_G : integer := 4;
--IMPORTANT: When turning the Newton-Raphson iterations ON/OFF, remember to change the inv_sqrt.ucf file
--The "TS_Inv_Sqrt" constraint should be kept updated, according to the CYCLES_DURATION constant
constant USE_NEWTON_G : integer := 1; -- 1 to use one Newton-Raphson iteration. 0 to use none
constant SMALLER_POW2_WW : integer := 16; --Smaller power of two that is larger than WORD_WIDTH
constant MULT_CYCLES : integer := 3;
------Types
type vector is array (integer range <>) of std_logic_vector(WORD_WIDTH_G-1 downto 0);
type matrix is array (integer range <>) of vector(0 to N_G-1);
type log2_N_vec is array (integer range <>) of std_logic_vector(LOG2_N_G-1 downto 0);
--Selects the source of the vector input of the A and Q matrices register block
type vec_in_AQ_sel_type is (EXTERNAL, MULTIPLIER, SUBTRACTER);
--Selects if the source of a signal is EXTERNAL or comes from the FSM
type ext_or_fsm is (EXTERNAL, FSM);
--Selects the source of the single element input of the R matrix
type single_in_R_sel_type is (MULTIPLIER, INNER_PRODUCT);
--Selects the source of the b input (single element) of the vector multiplier block
type in_b_vec_mult_sel_type is (INNER_PRODUCT, INVERSE_SQRT);
--Used to activate the memory bypass for the inputs of the inner product ports
type bypass_or_mem is (BYPASS, MEM);
end qr_pack;
| gpl-2.0 | c2d0606d9267914062fe121997263be1 | 0.661654 | 3.701299 | false | false | false | false |
TUM-LIS/faultify | hardware/testcases/fpu100_div/fpga_sim/xpsLibraryPath_asic/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/vhdl/user_logic.vhd | 1 | 29,243 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Fri May 16 15:25:24 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
faultify_clk_fast : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
component faultify_top
generic (
numInj : integer;
numIn : integer;
numOut : integer);
port (
aclk : in std_logic;
arst_n : in std_logic;
clk : in std_logic;
clk_x32 : in std_logic;
awvalid : in std_logic;
awaddr : in std_logic_vector(31 downto 0);
wvalid : in std_logic;
wdata : in std_logic_vector(31 downto 0);
arvalid : in std_logic;
araddr : in std_logic_vector(31 downto 0);
rvalid : out std_logic;
rdata : out std_logic_vector(31 downto 0));
end component;
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal register_write_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal register_read_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal register_write_address : std_logic_vector(C_NUM_REG-1 downto 0);
signal register_read_address : std_logic_vector(C_NUM_REG-1 downto 0);
signal slv_reg_write_sel : std_logic_vector(31 downto 0);
signal slv_reg_read_sel : std_logic_vector(31 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal faultify_read_valid : std_logic;
signal faultify_read_address_valid : std_logic;
signal faultify_read_address : std_logic_vector(31 downto 0);
signal faultify_write_valid : std_logic;
signal counter, divide : integer := 0;
signal faultify_clk_slow_i : std_logic;
begin
slv_reg_write_sel <= Bus2IP_WrCE(31 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(31 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12) or Bus2IP_WrCE(13) or Bus2IP_WrCE(14) or Bus2IP_WrCE(15) or Bus2IP_WrCE(16) or Bus2IP_WrCE(17) or Bus2IP_WrCE(18) or Bus2IP_WrCE(19) or Bus2IP_WrCE(20) or Bus2IP_WrCE(21) or Bus2IP_WrCE(22) or Bus2IP_WrCE(23) or Bus2IP_WrCE(24) or Bus2IP_WrCE(25) or Bus2IP_WrCE(26) or Bus2IP_WrCE(27) or Bus2IP_WrCE(28) or Bus2IP_WrCE(29) or Bus2IP_WrCE(30) or Bus2IP_WrCE(31);
slv_read_ack <= faultify_read_valid;
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process(Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
register_write_data <= (others => '0');
register_write_address <= (others => '0');
faultify_write_valid <= '0';
else
faultify_write_valid <= slv_write_ack;
case slv_reg_write_sel is
when "10000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(0, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "01000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(1, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00100000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(2, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00010000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(3, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00001000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(4, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000100000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(5, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000010000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(6, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000001000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(7, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000100000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(8, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000010000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(9, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000001000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(10, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000100000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(11, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000010000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(12, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000001000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(13, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000100000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(14, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000010000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(15, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000001000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(16, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000100000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(17, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000010000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(18, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000001000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(19, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000100000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(20, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000010000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(21, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000001000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(22, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000100000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(23, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000010000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(24, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000001000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(25, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(26, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(27, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(28, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(29, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(30, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(31, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process(slv_reg_read_sel, faultify_read_valid) is
begin
faultify_read_address_valid <= '1';
case slv_reg_read_sel is
when "10000000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(0, 32));
when "01000000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(1, 32));
when "00100000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(2, 32));
when "00010000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(3, 32));
when "00001000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(4, 32));
when "00000100000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(5, 32));
when "00000010000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(6, 32));
when "00000001000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(7, 32));
when "00000000100000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(8, 32));
when "00000000010000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(9, 32));
when "00000000001000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(10, 32));
when "00000000000100000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(11, 32));
when "00000000000010000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(12, 32));
when "00000000000001000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(13, 32));
when "00000000000000100000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(14, 32));
when "00000000000000010000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(15, 32));
when "00000000000000001000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(16, 32));
when "00000000000000000100000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(17, 32));
when "00000000000000000010000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(18, 32));
when "00000000000000000001000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(19, 32));
when "00000000000000000000100000000000" => faultify_read_address <= std_logic_vector(to_unsigned(20, 32));
when "00000000000000000000010000000000" => faultify_read_address <= std_logic_vector(to_unsigned(21, 32));
when "00000000000000000000001000000000" => faultify_read_address <= std_logic_vector(to_unsigned(22, 32));
when "00000000000000000000000100000000" => faultify_read_address <= std_logic_vector(to_unsigned(23, 32));
when "00000000000000000000000010000000" => faultify_read_address <= std_logic_vector(to_unsigned(24, 32));
when "00000000000000000000000001000000" => faultify_read_address <= std_logic_vector(to_unsigned(25, 32));
when "00000000000000000000000000100000" => faultify_read_address <= std_logic_vector(to_unsigned(26, 32));
when "00000000000000000000000000010000" => faultify_read_address <= std_logic_vector(to_unsigned(27, 32));
when "00000000000000000000000000001000" => faultify_read_address <= std_logic_vector(to_unsigned(28, 32));
when "00000000000000000000000000000100" => faultify_read_address <= std_logic_vector(to_unsigned(29, 32));
when "00000000000000000000000000000010" => faultify_read_address <= std_logic_vector(to_unsigned(30, 32));
when "00000000000000000000000000000001" => faultify_read_address <= std_logic_vector(to_unsigned(31, 32));
when others => faultify_read_address <= (others => '0');
faultify_read_address_valid <= '0';
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= register_read_data when faultify_read_valid = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
-----------------------------------------------------------------------------
-- clock divider 32 -> 1
-----------------------------------------------------------------------------
divide <= 32;
process(Bus2IP_Clk, Bus2IP_Resetn)
begin
if Bus2IP_Resetn = '0' then
counter <= 0;
faultify_clk_slow_i <= '0';
elsif(rising_edge(Bus2IP_Clk)) then
if(counter < divide/2-1) then
counter <= counter + 1;
faultify_clk_slow_i <= '0';
elsif(counter < divide-1) then
counter <= counter + 1;
faultify_clk_slow_i <= '1';
else
faultify_clk_slow_i <= '0';
counter <= 0;
end if;
end if;
end process;
faultify_top_1 : faultify_top
generic map (
numInj => 442,
numIn => 70,
numOut => 41)
port map (
aclk => Bus2IP_Clk,
arst_n => Bus2IP_Resetn,
clk => faultify_clk_slow_i,
clk_x32 => Bus2IP_Clk,
awvalid => faultify_write_valid,
awaddr => register_write_address,
wvalid => faultify_write_valid,
wdata => register_write_data,
arvalid => faultify_read_address_valid,
araddr => faultify_read_address,
rvalid => faultify_read_valid,
rdata => register_read_data);
end IMP;
| gpl-2.0 | 9fc33f7466b6ea68c7e6a40db60d83b2 | 0.539309 | 4.022974 | false | false | false | false |
lnls-dig/dsp-cores | hdl/modules/counters_gen/counters_gen.vhd | 1 | 2,778 | ------------------------------------------------------------------------------
-- Title : Simple Position Counters for debugging
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2017-01-20
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Core for generating coutners sync'ed with each incoming data rate.
-- Used for debugging.
-------------------------------------------------------------------------------
-- Copyright (c) 2017 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2017-01-20 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Counter Generator Definitions
use work.counters_gen_pkg.all;
entity counters_gen is
generic
(
g_cnt_width : t_cnt_width_array := c_default_cnt_width_array
);
port
(
rst_n_i : in std_logic;
clk_i : in std_logic;
---------------------------------
-- Counter generation interface
---------------------------------
cnt_ce_array_i : in std_logic_vector(g_cnt_width'length-1 downto 0);
cnt_up_array_i : in std_logic_vector(g_cnt_width'length-1 downto 0);
cnt_array_o : out t_cnt_array (g_cnt_width'length-1 downto 0)
);
end counters_gen;
architecture rtl of counters_gen is
-- Constants
constant c_num_counters : natural := g_cnt_width'length;
-- Signals
signal cnt_array : t_cnt_array (c_num_counters-1 downto 0);
begin
gen_counters : for i in 0 to c_num_counters-1 generate
p_counters : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
cnt_array(i) <= to_unsigned(0, cnt_array(i)'length);
elsif cnt_ce_array_i(i) = '1' then
if cnt_up_array_i(i) = '1' then
if cnt_array(i) = 2**g_cnt_width(i)-1 then
cnt_array(i) <= to_unsigned(0, cnt_array(i)'length);
else
cnt_array(i) <= cnt_array(i) + 1;
end if;
end if;
end if;
end if;
end process;
end generate;
cnt_array_o <= cnt_array;
end rtl;
| lgpl-3.0 | 342666ebf2a9a80a88c78d12bd7549d0 | 0.457163 | 4.254211 | false | false | false | false |
SoCdesign/EHA | RTL/Hand_Shaking/Checkers/Modules_with_checkers_integrated/All_checkers/FIFO_one_hot_with_checkers/FIFO_control_part_checkers.vhd | 2 | 4,873 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity FIFO_control_part_checkers is
port ( DRTS: in std_logic;
CTS_out: in std_logic;
CTS_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
read_pointer_in: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
write_pointer_in: in std_logic_vector(3 downto 0);
empty_out: in std_logic;
full_out: in std_logic;
read_en_out: in std_logic;
write_en_out: in std_logic;
-- Checker outputs
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_CTS_in,
err_write_en,
err_not_CTS_in,
err_not_write_en,
err_read_en_mismatch : out std_logic
);
end FIFO_control_part_checkers;
architecture behavior of FIFO_control_part_checkers is
signal read_en_signal: std_logic;
begin
read_en_signal <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty_out;
-- Checkers
process (write_en_out, write_pointer_in, write_pointer)
begin
if (write_en_out = '1' and write_pointer_in /= (write_pointer(2 downto 0) & write_pointer(3)) ) then
err_write_en_write_pointer <= '1';
else
err_write_en_write_pointer <= '0';
end if;
end process;
process (write_en_out, write_pointer_in, write_pointer)
begin
if (write_en_out = '0' and write_pointer_in /= write_pointer ) then
err_not_write_en_write_pointer <= '1';
else
err_not_write_en_write_pointer <= '0';
end if;
end process;
process (read_pointer, write_pointer, empty_out)
begin
if (read_pointer = write_pointer and empty_out = '0' ) then
err_read_pointer_write_pointer_not_empty <= '1';
else
err_read_pointer_write_pointer_not_empty <= '0';
end if;
end process;
process (read_pointer, write_pointer, empty_out)
begin
if (read_pointer /= write_pointer and empty_out = '1' ) then
err_read_pointer_write_pointer_empty <= '1';
else
err_read_pointer_write_pointer_empty <= '0';
end if;
end process;
process (write_pointer, read_pointer, full_out)
begin
if (write_pointer = (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '0' ) then
err_read_pointer_write_pointer_not_full <= '1';
else
err_read_pointer_write_pointer_not_full <= '0';
end if;
end process;
process (write_pointer, read_pointer, full_out)
begin
if (write_pointer /= (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '1' ) then
err_read_pointer_write_pointer_full <= '1';
else
err_read_pointer_write_pointer_full <= '0';
end if;
end process;
process (read_en_out, empty_out, read_pointer_in, read_pointer)
begin
if (read_en_out = '1' and empty_out = '0' and read_pointer_in /= (read_pointer(2 downto 0)&read_pointer(3)) ) then
err_read_pointer_increment <= '1';
else
err_read_pointer_increment <= '0';
end if;
end process;
process (read_en_out, empty_out, read_pointer_in, read_pointer)
begin
if ( (read_en_out = '0' or (read_en_out = '1' and empty_out = '1') ) and read_pointer_in /= read_pointer ) then
err_read_pointer_not_increment <= '1';
else
err_read_pointer_not_increment <= '0';
end if;
end process;
process (CTS_out, DRTS, full_out, CTS_in)
begin
if (CTS_out = '0' and DRTS = '1' and full_out = '0' and CTS_in = '0') then
err_CTS_in <= '1';
else
err_CTS_in <= '0';
end if;
end process;
process (CTS_out, DRTS, full_out, write_en_out)
begin
if (CTS_out = '0' and DRTS = '1' and full_out = '0' and write_en_out = '0') then
err_write_en <= '1';
else
err_write_en <= '0';
end if;
end process;
process (CTS_out, DRTS, full_out, CTS_in)
begin
if ( (CTS_out = '1' or (CTS_out = '0' and DRTS = '0') or (CTS_out = '0' and DRTS = '1' and full_out = '1')) and CTS_in = '1') then
err_not_CTS_in <= '1';
else
err_not_CTS_in <= '0';
end if;
end process;
process (CTS_out, DRTS, full_out, write_en_out)
begin
if ( (CTS_out = '1' or (CTS_out = '0' and DRTS = '0') or (CTS_out = '0' and DRTS = '1' and full_out = '1')) and write_en_out = '1') then
err_not_write_en <= '1';
else
err_not_write_en <= '0';
end if;
end process;
process (read_en_out, read_en_signal)
begin
if (read_en_out /= read_en_signal) then
err_read_en_mismatch <= '1';
else
err_read_en_mismatch <= '0';
end if;
end process;
end behavior; | gpl-3.0 | 9b67c76e704aa8cafcd8f1580a88149a | 0.637184 | 2.708727 | false | false | false | false |
SoCdesign/EHA | RTL/Hand_Shaking/Checkers/Modules_with_checkers_integrated/All_checkers/Arbiter_one_hot_with_checkers/Arbiter_checkers.vhd | 1 | 21,250 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Arbiter_checkers is
port (
Req_N, Req_E, Req_W, Req_S, Req_L :in std_logic;
DCTS: in std_logic;
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L: in std_logic;
Xbar_sel : in std_logic_vector(4 downto 0);
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
next_state_out: in std_logic_vector (5 downto 0);
RTS_FF: in std_logic;
RTS_FF_in: in std_logic;
-- Checker outputs
err_state_IDLE_xbar,
err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE,
err_IDLE_Req_L,
err_Local_Req_L,
err_North_Req_N,
err_East_Req_E,
err_West_Req_W,
err_South_Req_S,
err_IDLE_Req_N,
err_Local_Req_N,
err_North_Req_E,
err_East_Req_W,
err_West_Req_S,
err_South_Req_L,
err_IDLE_Req_E,
err_Local_Req_E,
err_North_Req_W,
err_East_Req_S,
err_West_Req_L,
err_South_Req_N,
err_IDLE_Req_W,
err_Local_Req_W,
err_North_Req_S,
err_East_Req_L,
err_West_Req_N,
err_South_Req_E,
err_IDLE_Req_S,
err_Local_Req_S,
err_North_Req_L,
err_East_Req_N,
err_West_Req_E,
err_South_Req_W,
err_next_state_onehot,
err_state_in_onehot,
err_DCTS_RTS_FF_state_Grant_L,
err_DCTS_RTS_FF_state_Grant_N,
err_DCTS_RTS_FF_state_Grant_E,
err_DCTS_RTS_FF_state_Grant_W,
err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel,
err_state_east_xbar_sel,
err_state_west_xbar_sel,
err_state_south_xbar_sel,
err_state_local_xbar_sel : out std_logic
);
end Arbiter_checkers;
architecture behavior of Arbiter_checkers is
CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001";
CONSTANT Local: std_logic_vector (5 downto 0) := "000010";
CONSTANT North: std_logic_vector (5 downto 0) := "000100";
CONSTANT East: std_logic_vector (5 downto 0) := "001000";
CONSTANT West: std_logic_vector (5 downto 0) := "010000";
CONSTANT South: std_logic_vector (5 downto 0) := "100000";
SIGNAL Requests: std_logic_vector (4 downto 0);
SIGNAL Grants: std_logic_vector (4 downto 0);
begin
Requests <= Req_N & Req_E & Req_W & Req_S & Req_L;
Grants <= Grant_N & Grant_E & Grant_W & Grant_S & Grant_L;
-- Checkers
--checked
process (Xbar_sel, state)
begin
if (state = IDLE and Xbar_sel /= "00000") then
err_state_IDLE_xbar <= '1';
else
err_state_IDLE_xbar <= '0';
end if;
end process;
--checked
process (state, Xbar_sel)
begin
if ( state /= IDLE and
Xbar_sel /= "00001" and Xbar_sel /= "00010" and Xbar_sel /= "00100" and Xbar_sel /= "01000" and Xbar_sel /= "10000") then
err_state_not_IDLE_xbar <= '1';
else
err_state_not_IDLE_xbar <= '0';
end if;
end process;
--checked
process (state, RTS_FF_in)
begin
if (state = IDLE and RTS_FF_in = '1') then
err_state_IDLE_RTS_FF_in <= '1';
else
err_state_IDLE_RTS_FF_in <= '0';
end if;
end process;
--checked
process (state, RTS_FF, RTS_FF_in)
begin
if ( (state = North or state = East or state = West or state = South or state = Local) and RTS_FF = '0' and RTS_FF = '0' and RTS_FF_in = '0') then
err_state_not_IDLE_RTS_FF_RTS_FF_in <= '1';
else
err_state_not_IDLE_RTS_FF_RTS_FF_in <= '0';
end if;
end process;
--checked
process (state, DCTS, RTS_FF, RTS_FF_in)
begin
if ( (state = North or state = East or state = West or state = South or state = Local) and RTS_FF = '1' and DCTS = '1' and RTS_FF_in = '1') then
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in <= '1';
else
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in <= '0';
end if;
end process;
--checked
process (state, DCTS, RTS_FF, RTS_FF_in)
begin
if ( (state = North or state = East or state = West or state = South or state = Local) and RTS_FF = '1' and DCTS = '0' and RTS_FF_in = '0') then
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in <= '1';
else
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in <= '0';
end if;
end process;
--checked
process (RTS_FF, DCTS, state, state_in)
begin
if (RTS_FF = '1' and DCTS = '0' and state /= state_in) then
err_RTS_FF_not_DCTS_state_state_in <= '1';
else
err_RTS_FF_not_DCTS_state_state_in <= '0';
end if;
end process;
--checked
process (RTS_FF, state_in, next_state_out)
begin
if (RTS_FF = '0' and state_in /= next_state_out) then
err_not_RTS_FF_state_in_next_state <= '1';
else
err_not_RTS_FF_state_in_next_state <= '0';
end if;
end process;
--checked
process (RTS_FF, DCTS, state_in, next_state_out)
begin
if (RTS_FF = '1' and DCTS = '1' and state_in /= next_state_out) then
err_RTS_FF_DCTS_state_in_next_state <= '1';
else
err_RTS_FF_DCTS_state_in_next_state <= '0';
end if;
end process;
--checked
process (RTS_FF, Grants)
begin
if (RTS_FF = '0' and Grants /= "00000") then
err_not_DCTS_Grants <= '1';
else
err_not_DCTS_Grants <= '0';
end if;
end process;
--checked
process (DCTS, RTS_FF, Grants)
begin
if (RTS_FF = '1' and DCTS = '0' and Grants /= "00000") then
err_DCTS_not_RTS_FF_Grants <= '1';
else
err_DCTS_not_RTS_FF_Grants <= '0';
end if;
end process;
--checked
process (DCTS, RTS_FF, state, Grants)
begin
if (DCTS = '1' and RTS_FF = '1' and state = IDLE and Grants /= "00000") then
err_DCTS_RTS_FF_IDLE_Grants <= '1';
else
err_DCTS_RTS_FF_IDLE_Grants <= '0';
end if;
end process;
--checked
process (DCTS, RTS_FF, state, Grants)
begin
if (DCTS = '1' and RTS_FF = '1' and state /= IDLE and
Grants /= "00001" and Grants /= "00010" and Grants /= "00100" and Grants /= "01000" and Grants /= "10000") then
err_DCTS_RTS_FF_not_IDLE_Grants_onehot <= '1';
else
err_DCTS_RTS_FF_not_IDLE_Grants_onehot <= '0';
end if;
end process;
--checked
process (state, Requests, next_state_out)
begin
if ( (state = North or state = East or state = West or state = South or state = Local or state = IDLE) and Requests = "00000" and next_state_out /= IDLE ) then
err_Requests_next_state_IDLE <= '1';
else
err_Requests_next_state_IDLE <= '0';
end if;
end process;
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-- Round 1
--checked
process (state, Req_L, next_state_out)
begin
if ( state = IDLE and Req_L = '1' and next_state_out /= Local) then
err_IDLE_Req_L <= '1';
else
err_IDLE_Req_L <= '0';
end if;
end process;
process (state, Req_L, next_state_out)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and Req_L = '1' and next_state_out /= Local) then
err_Local_Req_L <= '1';
else
err_Local_Req_L <= '0';
end if;
end process;
--checked
process (state, Req_N, next_state_out)
begin
if (state = North and Req_N = '1' and next_state_out /= North) then
err_North_Req_N <= '1';
else
err_North_Req_N <= '0';
end if;
end process;
----checked
process (state, Req_E, next_state_out)
begin
if (state = East and Req_E = '1' and next_state_out /= East) then
err_East_Req_E <= '1';
else
err_East_Req_E <= '0';
end if;
end process;
----checked
process (state, Req_W, next_state_out)
begin
if (state = West and Req_W = '1' and next_state_out /= West) then
err_West_Req_W <= '1';
else
err_West_Req_W <= '0';
end if;
end process;
----checked
process (state, Req_S, next_state_out)
begin
if (state = South and Req_S = '1' and next_state_out /= South) then
err_South_Req_S <= '1';
else
err_South_Req_S <= '0';
end if;
end process;
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-- Round 2
--checked
process (state, Req_L, Req_N, next_state_out)
begin
if ( state = IDLE and Req_L = '0' and Req_N = '1' and next_state_out /= North) then
err_IDLE_Req_N <= '1';
else
err_IDLE_Req_N <= '0';
end if;
end process;
process (state, Req_L, Req_N, next_state_out)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and Req_L = '0' and Req_N = '1' and next_state_out /= North) then
err_Local_Req_N <= '1';
else
err_Local_Req_N <= '0';
end if;
end process;
----checked
process (state, Req_N, Req_E, next_state_out)
begin
if (state = North and Req_N = '0' and Req_E = '1' and next_state_out /= East) then
err_North_Req_E <= '1';
else
err_North_Req_E <= '0';
end if;
end process;
process (state, Req_E, Req_W, next_state_out)
begin
if (state = East and Req_E = '0' and Req_W = '1' and next_state_out /= West) then
err_East_Req_W <= '1';
else
err_East_Req_W <= '0';
end if;
end process;
process (state, Req_W, Req_S, next_state_out)
begin
if (state = West and Req_W = '0' and Req_S = '1' and next_state_out /= South) then
err_West_Req_S <= '1';
else
err_West_Req_S <= '0';
end if;
end process;
process (state, Req_S, Req_L, next_state_out)
begin
if (state = South and Req_S = '0' and Req_L = '1' and next_state_out /= Local) then
err_South_Req_L <= '1';
else
err_South_Req_L <= '0';
end if;
end process;
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-- Round 3
process (state, Req_L, Req_N, Req_E, next_state_out)
begin
if ( state = IDLE and Req_L = '0' and Req_N = '0' and Req_E = '1' and next_state_out /= East) then
err_IDLE_Req_E <= '1';
else
err_IDLE_Req_E <= '0';
end if;
end process;
process (state, Req_L, Req_N, Req_E, next_state_out)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
Req_L = '0' and Req_N = '0' and Req_E = '1' and next_state_out /= East) then
err_Local_Req_E <= '1';
else
err_Local_Req_E <= '0';
end if;
end process;
process (state, Req_N, Req_E, Req_W, next_state_out)
begin
if (state = North and Req_N = '0' and Req_E = '0' and Req_W = '1' and next_state_out /= West) then
err_North_Req_W <= '1';
else
err_North_Req_W <= '0';
end if;
end process;
process (state, Req_E, Req_W, Req_S, next_state_out)
begin
if (state = East and Req_E = '0' and Req_W = '0' and Req_S = '1' and next_state_out /= South) then
err_East_Req_S <= '1';
else
err_East_Req_S <= '0';
end if;
end process;
process (state, Req_W, Req_S, Req_L, next_state_out)
begin
if (state = West and Req_W = '0' and Req_S = '0' and Req_L = '1' and next_state_out /= Local) then
err_West_Req_L <= '1';
else
err_West_Req_L <= '0';
end if;
end process;
process (state, Req_S, Req_L, Req_N, next_state_out)
begin
if (state = South and Req_S = '0' and Req_L = '0' and Req_N = '1' and next_state_out /= North) then
err_South_Req_N <= '1';
else
err_South_Req_N <= '0';
end if;
end process;
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-- Round 4
process (state, Req_L, Req_N, Req_E, Req_W, next_state_out)
begin
if ( state = IDLE and Req_L = '0' and Req_N = '0' and Req_E = '0' and Req_W = '1' and next_state_out /= West) then
err_IDLE_Req_W <= '1';
else
err_IDLE_Req_W <= '0';
end if;
end process;
process (state, Req_L, Req_N, Req_E, Req_W, next_state_out)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
Req_L = '0' and Req_N = '0' and Req_E = '0' and Req_W = '1' and next_state_out /= West) then
err_Local_Req_W <= '1';
else
err_Local_Req_W <= '0';
end if;
end process;
process (state, Req_N, Req_E, Req_W, Req_S, next_state_out)
begin
if (state = North and Req_N = '0' and Req_E = '0' and Req_W = '0' and Req_S = '1' and next_state_out /= South) then
err_North_Req_S <= '1';
else
err_North_Req_S <= '0';
end if;
end process;
process (state, Req_E, Req_W, Req_S, Req_L, next_state_out)
begin
if (state = East and Req_E = '0' and Req_W = '0' and Req_S = '0' and Req_L = '1' and next_state_out /= Local) then
err_East_Req_L <= '1';
else
err_East_Req_L <= '0';
end if;
end process;
process (state, Req_W, Req_S, Req_L, Req_N, next_state_out)
begin
if (state = West and Req_W = '0' and Req_S = '0' and Req_L = '0' and Req_N = '1' and next_state_out /= North) then
err_West_Req_N <= '1';
else
err_West_Req_N <= '0';
end if;
end process;
process (state, Req_S, Req_L, Req_N, Req_E, next_state_out)
begin
if (state = South and Req_S = '0' and Req_L = '0' and Req_N = '0' and Req_E = '1' and next_state_out /= East) then
err_South_Req_E <= '1';
else
err_South_Req_E <= '0';
end if;
end process;
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-- Round 5
process (state, Req_L, Req_N, Req_E, Req_W, Req_S, next_state_out)
begin
if ( state = IDLE and Req_L = '0' and Req_N = '0' and Req_E = '0' and Req_W = '0' and Req_S = '1'
and next_state_out /= South) then
err_IDLE_Req_S <= '1';
else
err_IDLE_Req_S <= '0';
end if;
end process;
process (state, Req_L, Req_N, Req_E, Req_W, Req_S, next_state_out)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
Req_L = '0' and Req_N = '0' and Req_E = '0' and Req_W = '0' and Req_S = '1'
and next_state_out /= South) then
err_Local_Req_S <= '1';
else
err_Local_Req_S <= '0';
end if;
end process;
process (state, Req_N, Req_E, Req_W, Req_S, Req_L, next_state_out)
begin
if (state = North and Req_N = '0' and Req_E = '0' and Req_W = '0' and Req_S = '0' and Req_L = '1'
and next_state_out /= Local) then
err_North_Req_L <= '1';
else
err_North_Req_L <= '0';
end if;
end process;
process (state, Req_E, Req_W, Req_S, Req_L, Req_N, next_state_out)
begin
if (state = East and Req_E = '0' and Req_W = '0' and Req_S = '0' and Req_L = '0' and Req_N = '1'
and next_state_out /= North) then
err_East_Req_N <= '1';
else
err_East_Req_N <= '0';
end if;
end process;
process (state, Req_W, Req_S, Req_L, Req_N, Req_E, next_state_out)
begin
if (state = West and Req_W = '0' and Req_S = '0' and Req_L = '0' and Req_N = '0' and Req_E = '1'
and next_state_out /= East) then
err_West_Req_E <= '1';
else
err_West_Req_E <= '0';
end if;
end process;
process (state, Req_S, Req_L, Req_N, Req_E, Req_W, next_state_out)
begin
if (state = South and Req_S = '0' and Req_L = '0' and Req_N = '0' and Req_E = '0' and Req_W = '1'
and next_state_out /= West) then
err_South_Req_W <= '1';
else
err_South_Req_W <= '0';
end if;
end process;
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process (next_state_out)
begin
if (next_state_out /= IDLE and next_state_out /= North and next_state_out /= East and next_state_out /= West and
next_state_out /= South and next_state_out /= Local) then
err_next_state_onehot <= '1';
else
err_next_state_onehot <= '0';
end if;
end process;
process (state_in)
begin
if (state_in /= IDLE and state_in /= North and state_in /= East and state_in /= West and
state_in /= South and state_in /= Local) then
err_state_in_onehot <= '1';
else
err_state_in_onehot <= '0';
end if;
end process;
process (DCTS, RTS_FF, state, Grant_L)
begin
if (DCTS = '1' and RTS_FF = '1' and state /= IDLE and state /= North and state /=East and state /=West and
state /= South and Grant_L = '0' ) then
err_DCTS_RTS_FF_state_Grant_L <= '1';
else
err_DCTS_RTS_FF_state_Grant_L <= '0';
end if;
end process;
process (DCTS, RTS_FF, state, Grant_N)
begin
if (DCTS = '1' and RTS_FF = '1' and state = North and Grant_N = '0' ) then
err_DCTS_RTS_FF_state_Grant_N <= '1';
else
err_DCTS_RTS_FF_state_Grant_N <= '0';
end if;
end process;
process (DCTS, RTS_FF, state, Grant_E)
begin
if (DCTS = '1' and RTS_FF = '1' and state = East and Grant_E = '0' ) then
err_DCTS_RTS_FF_state_Grant_E <= '1';
else
err_DCTS_RTS_FF_state_Grant_E <= '0';
end if;
end process;
process (DCTS, RTS_FF, state, Grant_W)
begin
if (DCTS = '1' and RTS_FF = '1' and state = West and Grant_W = '0' ) then
err_DCTS_RTS_FF_state_Grant_W <= '1';
else
err_DCTS_RTS_FF_state_Grant_W <= '0';
end if;
end process;
process (DCTS, RTS_FF, state, Grant_S)
begin
if (DCTS = '1' and RTS_FF = '1' and state = South and Grant_S = '0' ) then
err_DCTS_RTS_FF_state_Grant_S <= '1';
else
err_DCTS_RTS_FF_state_Grant_S <= '0';
end if;
end process;
process (state, Xbar_sel)
begin
if (state = North and Xbar_sel /= "00001" ) then
err_state_north_xbar_sel <= '1';
else
err_state_north_xbar_sel <= '0';
end if;
end process;
process (state, Xbar_sel)
begin
if (state = East and Xbar_sel /= "00010" ) then
err_state_east_xbar_sel <= '1';
else
err_state_east_xbar_sel <= '0';
end if;
end process;
process (state, Xbar_sel)
begin
if (state = West and Xbar_sel /= "00100" ) then
err_state_west_xbar_sel <= '1';
else
err_state_west_xbar_sel <= '0';
end if;
end process;
process (state, Xbar_sel)
begin
if (state = South and Xbar_sel /= "01000" ) then
err_state_south_xbar_sel <= '1';
else
err_state_south_xbar_sel <= '0';
end if;
end process;
process (state, Xbar_sel)
begin
if (state /= IDLE and state /= North and state /= East and state /= West and state /= South and Xbar_sel /= "10000" ) then
err_state_local_xbar_sel <= '1';
else
err_state_local_xbar_sel <= '0';
end if;
end process;
end behavior; | gpl-3.0 | 2833492081156b88889b14734bc67515 | 0.496188 | 3.055795 | false | false | false | false |
lnls-dig/dsp-cores | hdl/testbench/divider/div_tb_float.vhd | 1 | 2,478 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
use work.arith_dsp48e.all;
use work.utilities.all;
entity div_tb is
end div_tb;
architecture behavioral of div_tb is
constant C_DATAIN_WIDTH : integer := 27;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal trg : std_logic := '0';
signal n : std_logic_vector(C_DATAIN_WIDTH-1 downto 0) := (others => '0');
signal d : std_logic_vector(C_DATAIN_WIDTH-1 downto 0) := (others => '0');
--Outputs
signal q : std_logic_vector(31 downto 0);
signal rdy : std_logic;
signal err : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
constant TAB : character := ht;
file test_out_data : text open write_mode is "./output.dat";
begin
uut_ieee754_single : div_ieee754_single
generic map
(
G_DATA_WIDTH => C_DATAIN_WIDTH
)
port map
(
clk_i => clk,
rst_i => rst,
n_i => n,
d_i => d,
q_o => q,
trg_i => trg,
rdy_o => rdy,
err_o => err
);
-- Clock process definitions
clk_process : process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc : process
variable outline : line;
variable i : integer;
begin
rst <= '1';
wait for clk_period*10.5;
rst <= '0';
wait for clk_period*10;
for i in 0 to 5740 loop
n <= std_logic_vector(to_signed((i*i)/10, C_DATAIN_WIDTH));
d <= std_logic_vector(to_signed(32947600, C_DATAIN_WIDTH));
wait for clk_period*1;
write(outline, to_integer(signed(n)));
write(outline, TAB);
write(outline, to_integer(signed(d)));
trg <= '1';
wait for clk_period;
trg <= '0';
wait for clk_period*31;
write(outline, TAB);
write(outline, to_integer(unsigned(q(30 downto 23))));
write(outline, TAB);
if q(31) = '1' then
write(outline, string'("-"));
end if;
write(outline, to_integer(unsigned(q(22 downto 0))));
wait for clk_period*1;
writeline(test_out_data, outline); -- write row to output file
end loop;
assert (false) report "Test finished." severity failure;
wait;
end process;
end;
| lgpl-3.0 | d5d1fac5e8d3971e056498d3819f0f99 | 0.559726 | 3.380628 | false | false | false | false |
TUM-LIS/faultify | hardware/testcases/viterbi/fpga_sim/xpsLibraryPath_viterbi_200_399/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/vhdl/faultify_simulator.vhd | 1 | 5,686 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity faultify_simulator is
generic (
numInj : integer := 56;
numIn : integer := 10;
numOut : integer := 10);
port (
clk : in std_logic;
clk_m : in std_logic;
circ_ce : in std_logic;
circ_rst : in std_logic;
test : out std_logic_vector(31 downto 0);
testvector : in std_logic_vector(numIn-1 downto 0);
resultvector_o : out std_logic_vector(numOut-1 downto 0);
resultvector_f : out std_logic_vector(numOut-1 downto 0);
seed_in_en : in std_logic;
seed_in : in std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
shift_en : in std_logic;
rst_n : in std_logic);
end faultify_simulator;
-- 866:0
architecture behav of faultify_simulator is
component faultify_binomial_gen
generic (
width : integer);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : out std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
prob_out_c : out std_logic;
shift_en : in std_logic;
data_out : out std_logic;
data_out_valid : out std_logic);
end component;
component circuit_under_test
port (
clk : in std_logic;
rst : in std_logic;
testvector : in std_logic_vector(numIn-1 downto 0);
resultvector : out std_logic_vector(numOut-1 downto 0);
injectionvector : in std_logic_vector(578-1 downto 0));
end component;
component golden_circuit
port (
clk : in std_logic;
rst : in std_logic;
testvector : in std_logic_vector(numIn-1 downto 0);
resultvector : out std_logic_vector(numOut-1 downto 0));
end component;
signal injectionvector : std_logic_vector(numInj-1 downto 0);
signal injectionvector_reg : std_logic_vector(numInj-1 downto 0);
signal injectionvector_reg_o : std_logic_vector(numInj-1 downto 0);
signal seed_chain : std_logic_vector(numInj downto 0);
signal prob_chain : std_logic_vector(numInj downto 0);
signal rst : std_logic;
signal clk_ce_m : std_logic;
signal testvector_reg : std_logic_vector(numIn-1 downto 0);
attribute syn_noprune : boolean;
attribute syn_noprune of circuit_under_test_inst : label is true;
attribute syn_noprune of golden_circuit_inst : label is true;
attribute xc_props : string;
attribute xc_props of circuit_under_test_inst : label is "KEEP_HIERARCHY=TRUE";
attribute xc_props of golden_circuit_inst : label is "KEEP_HIERARCHY=TRUE";
signal injectionvector_reg_cat : std_logic_vector(578-1 downto 0);
begin -- behav
rst <= not rst_n;
-----------------------------------------------------------------------------
-- debug...
-----------------------------------------------------------------------------
-- resultvector_f <= (others => '1');
-- resultvector_o <= (others => '1');
cgate : bufgce
port map (
I => clk_m,
O => clk_ce_m,
CE => '1');
process (clk_ce_m, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
testvector_reg <= (others => '0');
elsif clk_ce_m'event and clk_ce_m = '1' then -- rising clock edge
testvector_reg <= testvector;
end if;
end process;
circuit_under_test_inst : circuit_under_test
port map (
clk => clk_ce_m,
rst => circ_rst,
testvector => testvector_reg,
resultvector => resultvector_f,
injectionvector => injectionvector_reg_cat);
injectionvector_reg_cat(199 downto 0) <= (others => '0');
injectionvector_reg_cat(399 downto 200) <= injectionvector_reg;
injectionvector_reg_cat(578-1 downto 400) <= (others => '0');
golden_circuit_inst : golden_circuit
port map (
clk => clk_ce_m,
rst => circ_rst,
testvector => testvector_reg,
resultvector => resultvector_o
);
seed_chain(0) <= seed_in;
prob_chain(0) <= prob_in;
prsn_loop : for i in 0 to numInj-1 generate
prsn_top_1 : faultify_binomial_gen
generic map (
width => 32)
port map (
clk => clk,
rst_n => rst_n,
seed_in_en => seed_in_en,
seed_in => seed_chain(i),
seed_out_c => seed_chain(i+1),
prob_in_en => prob_in_en,
prob_in => prob_chain(i),
prob_out_c => prob_chain(i+1),
shift_en => shift_en,
data_out => injectionvector(i),
data_out_valid => open);
end generate prsn_loop;
reg : process (clk_ce_m, rst_n)
begin -- process reg
if rst_n = '0' then -- asynchronous reset (active low)
injectionvector_reg <= (others => '0');
--injectionvector_reg_o <= (others => '0');
--test <= (others => '0');
elsif clk_ce_m'event and clk_ce_m = '1' then -- rising clock edge
injectionvector_reg <= injectionvector;
--injectionvector_reg <= (others => '0');
--test <= injectionvector_reg_o(31 downto 0);
--injectionvector_reg_o(31 downto 0) <= injectionvector_reg_o(31 downto 0) or (resultvector_f(31 downto 0) xor resultvector_o(31 downto 0));
end if;
end process reg;
end behav;
| gpl-2.0 | 1503a0a5f0548367e0297bb870492635 | 0.550651 | 3.642537 | false | true | false | false |
bruskajp/EE-316 | Project5/game_logic_1.vhd | 1 | 21,462 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04/05/2017 02:01:44 PM
-- Design Name:
-- Module Name: game_logic - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity game_logic is
port(
clk : in STD_LOGIC;
usb_bt_clk : in STD_LOGIC;
save_button_input : in STD_LOGIC;
keyboard_input : in STD_LOGIC_VECTOR(7 downto 0);
x_pos_input : in STD_LOGIC_VECTOR(7 downto 0);
y_pos_input : in STD_LOGIC_VECTOR(7 downto 0);
usb_bt_input : in STD_LOGIC_VECTOR(7 downto 0);
reset_output : out STD_LOGIC;
screen_size_output : out STD_LOGIC;
pen_width_output : out STD_LOGIC_VECTOR(2 downto 0);
x_pos_output : out STD_LOGIC_VECTOR(7 downto 0);
y_pos_output : out STD_LOGIC_VECTOR(7 downto 0);
tricolor_led_output : out STD_LOGIC_VECTOR(11 downto 0);
usb_bt_output : out STD_LOGIC_VECTOR(15 downto 0);
color_output : out STD_LOGIC_VECTOR(23 downto 0);
ram_we_output : out STD_LOGIC_VECTOR(0 downto 0);
ram_val_output : out STD_LOGIC_VECTOR(11 downto 0);
ram_addr_output : out STD_LOGIC_VECTOR(16 downto 0)
);
end game_logic;
architecture Behavioral of game_logic is
-- Font ROM component
component font_rom is
port(
clk : in STD_LOGIC;
addr : in STD_LOGIC_VECTOR(10 downto 0);
data : out STD_LOGIC_VECTOR(7 downto 0)
);
end component;
-- RAM clock divider component
component clock_divider is
generic(count_max : INTEGER := 8); -- FIX THIS?
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
clk_output : out STD_LOGIC
);
end component;
-- System properties
signal pc_connected : STD_LOGIC := '0';
signal screen_size : STD_LOGIC := '0';
signal reset : STD_LOGIC := '0';
signal pen_width : STD_LOGIC_VECTOR(2 downto 0) := "000";
signal ascii_char : STD_LOGIC_VECTOR(7 downto 0) := x"00";
signal color : STD_LOGIC_VECTOR(23 downto 0) := x"000000";
--USB/bluetooth control send signals
signal prev_screen_size : STD_LOGIC := '0';
signal prev_save : STD_LOGIC := '0';
signal prev_reset : STD_LOGIC := '0';
signal prev_pen_width : STD_LOGIC_VECTOR(2 downto 0):= "000";
signal prev_ascii_char : STD_LOGIC_VECTOR(7 downto 0):= x"00";
signal prev_x_pos, prev_y_pos : STD_LOGIC_VECTOR(7 downto 0):= x"00";
signal prev_color : STD_LOGIC_VECTOR(23 downto 0):= x"000000";
--USB/Bluetooth control receive signals
signal prev_connections : STD_LOGIC_VECTOR(7 downto 0);
-- Keyboard control signals
signal num_values_input : INTEGER := 0;
signal prev_pc_connected : STD_LOGIC := '0';
signal changing_item : STD_LOGIC_VECTOR(2 downto 0) := "000"; -- [color, pen_width, screen_size]
signal hex_input : STD_LOGIC_VECTOR(3 downto 0) := x"0";
signal temp_hex_input : STD_LOGIC_VECTOR(7 downto 0) := x"00";
signal input_values : STD_LOGIC_VECTOR(23 downto 0) := x"000000";
-- Font Rom signals
signal font_rom_addr : UNSIGNED(10 downto 0) := x"00" & "000";
signal font_rom_data : STD_LOGIC_VECTOR(7 downto 0) := x"00";
-- RAM clock divider signals
signal ram_divider_counter : INTEGER := 0;
signal ram_clk : STD_LOGIC := '0';
-- RAM Signals
signal x_pos_int : INTEGER := 0;
signal y_pos_int : INTEGER := 0;
-- RAM fast update signals
signal ram_update_count : INTEGER := 0;
signal ram_update_x_count : INTEGER := 0;
signal ram_update_y_count : INTEGER := 0;
signal ram_update_slow_int : INTEGER := 0;
signal ram_update : STD_LOGIC_VECTOR(2 downto 0) := "000"; -- [pos, sys_text, user_text]
signal ram_update_slow : STD_LOGIC_VECTOR(2 downto 0) := "000";
signal ram_update_pos_slow : STD_LOGIC_VECTOR(7 downto 0) := x"00";
signal ram_update_sys_text_slow : STD_LOGIC_VECTOR(7 downto 0) := x"00";
signal ram_update_user_text_slow : STD_LOGIC_VECTOR(7 downto 0) := x"00";
-- RAM slow control signals
signal x_addr_count, y_addr_count : INTEGER := 0;
-- RAM reset signals
signal ram_reset : STD_LOGIC := '0';
signal ram_reset_slow : STD_LOGIC := '0';
signal ram_reset_count : UNSIGNED(15 downto 0) := x"0000";
signal prev_ram_resets : STD_LOGIC_VECTOR(7 downto 0) := x"00";
begin
screen_size_output <= screen_size;
pen_width_output <= pen_width;
x_pos_output <= x_pos_input;
y_pos_output <= y_pos_input;
tricolor_led_output <= color(11 downto 0);
color_output <= color;
ram_we_output <= "1";
--ram_we_output <= "0";
reset_output <= reset;
-- Previous signal generation process
process(clk)
begin
prev_pc_connected <= pc_connected;
prev_x_pos <= x_pos_input;
prev_y_pos <= y_pos_input;
prev_color <= color;
prev_ascii_char <= ascii_char;
prev_screen_size <= screen_size;
prev_pen_width <= pen_width;
prev_save <= save_button_input;
prev_reset <= reset;
end process;
-- USB/Bluetooth control process
process(clk, usb_bt_clk, prev_x_pos, prev_y_pos) -- FIX THIS (add update method)
begin
-- Sending Data
if rising_edge(clk) then
if reset /= prev_reset then
usb_bt_output(15 downto 12) <= "1111";
usb_bt_output(1) <= save_button_input;
usb_bt_output(0) <= reset;
elsif prev_x_pos /= x_pos_input then
usb_bt_output(15 downto 14) <= "10";
usb_bt_output(8) <= '0';
usb_bt_output(7 downto 0) <= x_pos_input;
elsif prev_y_pos /= y_pos_input then
usb_bt_output(15 downto 14) <= "10";
usb_bt_output(8) <= '1';
usb_bt_output(7 downto 0) <= y_pos_input;
elsif prev_color /= color then
usb_bt_output(15 downto 12) <= "1100";
usb_bt_output(11 downto 0) <= color(11 downto 0); -- change to 24 bit?
elsif prev_screen_size /= screen_size or prev_pen_width /= pen_width then
usb_bt_output(15 downto 12) <= "1110";
usb_bt_output(3) <= screen_size;
usb_bt_output(2 downto 0) <= pen_width;
elsif prev_ascii_char /= ascii_char then
usb_bt_output(15 downto 12) <= "1101";
usb_bt_output(7 downto 0) <= ascii_char;
elsif prev_save /= save_button_input then
usb_bt_output(15 downto 12) <= "1111";
usb_bt_output(1) <= save_button_input;
usb_bt_output(0) <= reset;
else
usb_bt_output <= x"0000";
end if;
end if;
-- Recieving Data
if rising_edge(usb_bt_clk) then
prev_connections <= prev_connections(6 downto 0) & usb_bt_input(0);
if prev_connections = x"00" then
pc_connected <= '0';
else
pc_connected <= '1';
end if;
end if;
end process;
-- Keyboard control process
hex_input <= temp_hex_input(3 downto 0);
process(clk)
begin
-- Keyboard control
if rising_edge(clk) then
if reset = '0' then
if keyboard_input = x"77" and changing_item = "000" then -- input w and changing color
ascii_char <= x"77";
changing_item <= "100";
num_values_input <= 1;
elsif keyboard_input = x"63" and changing_item = "000" then -- input c and changing pen_width
ascii_char <= x"63";
changing_item <= "010";
num_values_input <= 1;
elsif keyboard_input = x"73" and changing_item = "000" then -- input s and changing screen_size
ascii_char <= x"73";
changing_item <= "001";
num_values_input <= 1;
elsif keyboard_input = x"72" and changing_item = "000" then -- input r
reset <= '1';
color <= x"FFFFFF";
pen_width <= "000";
screen_size <= '0';
elsif keyboard_input = x"71" and changing_item /= "000" then -- input q and exit command
ascii_char <= x"71";
-- FIX THIS
elsif keyboard_input = x"08" and num_values_input = 1 then -- input backspace
ascii_char <= x"08";
num_values_input <= 0;
changing_item <= "000";
elsif changing_item /= "000" then
-- Ascii to hex converter
if (keyboard_input >= x"30" and keyboard_input <= x"39") then
temp_hex_input <= std_logic_vector(unsigned(keyboard_input) - x"30");
elsif (keyboard_input >= x"61" and keyboard_input <= x"66") then
temp_hex_input <= std_logic_vector(unsigned(keyboard_input) - x"57");
else
temp_hex_input <= x"FF";
end if;
-- User keyboard input restrictions
if changing_item = "100" and hex_input <= x"F" then -- Limit color
input_values(((num_values_input * 4)-1) downto ((num_values_input-1) * 4)) <= hex_input;
num_values_input <= num_values_input + 1;
elsif changing_item = "010" and hex_input >= x"1" and hex_input <= x"7" then -- Limit pen_width
input_values(3 downto 0) <= hex_input;
num_values_input <= num_values_input + 1;
elsif changing_item = "001" and hex_input <= x"1" then -- Limit screen_size
input_values(3 downto 0) <= hex_input;
num_values_input <= num_values_input + 1;
end if;
elsif keyboard_input = x"0A" then -- input enter
ascii_char <= x"0A";
if changing_item = "100" and num_values_input = 7 then -- new color
color <= input_values;
changing_item <= "000";
elsif changing_item = "010" and num_values_input = 1 then -- new pen_width
pen_width <= input_values(2 downto 0);
changing_item <= "000";
elsif changing_item = "001" and num_values_input = 1 then -- new screen_size
screen_size <= input_values(0);
changing_item <= "000";
end if;
end if;
end if;
-- Reset handling
if reset = '1' and prev_reset = '1' and ram_reset = '0' then
reset <= '0';
color <= x"000000";
end if;
end if;
end process;
-- Font ROM port map
ram_font_rom : font_rom
port map(
clk => clk,
addr => std_logic_vector(font_rom_addr),
data => font_rom_data
);
-- RAM clock divider port map
ram_clock_divider : clock_divider
generic map(count_max => 2) -- CHANGE VALUE
port map(
clk => clk,
reset => '0',
clk_output => ram_clk
);
x_pos_int <= to_integer(unsigned(x_pos_input));
y_pos_int <= to_integer(unsigned(y_pos_input));
-- RAM control process
process(clk, ram_clk)
begin
-- When to update RAM
if rising_edge(clk) then
-- ram_update_pos_slow <= ram_update_pos_slow(6 downto 0) & ram_update_slow(2);
-- ram_update_pos_slow <= ram_update_pos_slow(6 downto 0) & ram_update_slow(2);
-- ram_update_pos_slow <= ram_update_pos_slow(6 downto 0) & ram_update_slow(2);
if (x_pos_input /= prev_x_pos or y_pos_input /= prev_y_pos) then
ram_update(2) <= '1'; -- pos
ram_update_slow_int <= 1;
elsif ram_update slow = 64
ram_update(2) <= '0';
-- elsif (color /= prev_color or pen_width /= prev_pen_width
-- or pc_connected /= prev_pc_connected) then
-- ram_update(1) <= '1'; -- sys_text
-- elsif (ascii_char /= prev_ascii_char) then
-- ram_update(0) <= '1'; -- user_text
end if;
if ram_update_slow_int = 64 then
ram_update_slow_int <= 0;
elsif ram_update_slow_int > 0 then
ram_update_slow_int <= ram_update_slow_int + 1;
end if;
-- if ram_update_pos_slow = x"00" then
-- ram_update(2) <= '0';
-- end if;
-- if ram_update_sys_text_slow = x"00" then
-- ram_update(1) <= '0';
-- end if;
-- if ram_update_user_text_slow = x"00" then
-- ram_update(0) <= '0';
-- end if;
-- if reset = '1' and ram_reset = '0' then
-- ram_reset <= '1';
-- prev_ram_resets <= prev_ram_resets(6 downto 0) & ram_reset;
-- end if;
--
-- if ram_reset_slow = '0' and prev_ram_resets = x"FF" then
-- ram_reset <= '0';
-- end if;
-- end if;
-- Draw to RAM
--if rising_edge(ram_clk) then
--if rising_edge(clk) then
--if ram_reset = '0' then
if ram_update(2) = '1' then -- pos
--if(true) then
--ram_we_output <= "1";
ram_val_output <= color(23 downto 20) & color(15 downto 12) & color(7 downto 4);
--ram_update_slow(2) <= '1';
--ram_update(2) <= '0';
-- if (y_addr_count < unsigned(pen_width)) and
-- ((y_pos_int + y_addr_count) < 256) and
-- ((y_pos_int + y_addr_count) >= 0) then
-- if (x_addr_count < unsigned(pen_width)) and
-- ((x_pos_int + x_addr_count) < 256) and
-- ((x_pos_int + x_addr_count) >= 0) then
ram_addr_output <= std_logic_vector(to_unsigned( ((x_pos_int+x_addr_count) + ((y_pos_int+y_addr_count) * 256)) , 17));
-- else
-- x_addr_count <= 0;
-- end if;
-- y_addr_count <= y_addr_count + 1;
-- else
-- y_addr_count <= 0;
-- end if;
--elsif prev_x_pos /= x_pos_input and prev_y_pos /= y_pos_input then --Not needed?
--ram_update(1) <= '0';
--ram_we_output <= "0"; --Not needed?
--ram_update(2) <= '0'; --Not needed?
-- elsif ram_update(2 downto 1) = "01" then -- sys_text
-- ram_update_slow(2 downto 1) <= "01";
-- if ram_update_count < 3 then
-- if ram_update_y_count < 16 then
-- if ram_update_x_count < 8 then
-- if ram_update_count = 1 then -- Update color
-- ram_addr_output <= std_logic_vector(to_unsigned(65618 + ram_update_x_count
-- + (ram_update_y_count * 384), 17));
-- ram_val_output <= color(11 downto 0);
-- elsif ram_update_count = 2 then -- Update pen_width
-- ram_addr_output <= std_logic_vector(to_unsigned(65768 + ram_update_x_count
-- + (ram_update_y_count * 384), 17));
-- font_rom_addr <= "000" & (x"30" + unsigned("0000" & pen_width)); -- FIX THIS (concurency)
-- if font_rom_data(ram_update_x_count) = '1' then
-- ram_val_output <= x"000";
-- else
-- ram_val_output <= x"FFF";
-- end if;
-- else -- Update pc_connnection
-- ram_addr_output <= std_logic_vector(to_unsigned(65888 + ram_update_x_count
-- + (ram_update_count * 10)
-- + (ram_update_y_count * 384), 17));
-- font_rom_addr <= "00" & (x"30" + "0000000" & pc_connected); -- FIX THIS (concurency)
-- if font_rom_data(ram_update_x_count) = '1' then
-- ram_val_output <= x"000";
-- else
-- ram_val_output <= x"FFF";
-- end if;
-- end if;
-- ram_update_x_count <= ram_update_x_count + 1;
-- else
-- ram_update_x_count <= 0;
-- end if;
-- ram_update_y_count <= ram_update_x_count + 1;
-- else
-- ram_update_y_count <= 0;
-- end if;
-- ram_update_count <= ram_update_count + 1;
-- else
-- ram_update_slow(1) <= '0';
-- ram_update_count <= 0;
-- end if;
-- elsif ram_update = "001" then -- user_text
-- ram_update_slow <= "001";
-- if ram_update_count < 8 then
-- if ram_update_y_count < 16 then
-- if ram_update_x_count < 8 then
-- ram_addr_output <= std_logic_vector(to_unsigned(66102 + ram_update_x_count
-- + (ram_update_y_count * 384), 17));
-- font_rom_addr <= unsigned("000" & ascii_char); -- FIX THIS (concurency)
-- if font_rom_data(ram_update_x_count) = '1' then
-- ram_val_output <= x"000";
-- else
-- ram_val_output <= x"FFF";
-- end if;
-- ram_update_x_count <= ram_update_x_count + 1;
-- else
-- ram_update_x_count <= 0;
-- end if;
-- ram_update_y_count <= ram_update_x_count + 1;
-- else
-- ram_update_y_count <= 0;
-- end if;
-- ram_update_count <= ram_update_count + 1;
-- else
-- ram_update_slow(0) <= '0';
-- ram_update_count <= 0;
-- end if;
-- else
-- ram_update_slow <= "000";
--end if;
---- else -- ram_reset = 1
---- -- Drawing Screen (sys_text and user_text update automatically)
---- if ram_reset_count < 65536 then
---- ram_reset_slow <= '1';
---- ram_reset_count <= ram_reset_count + 1;
---- ram_addr_output <= "0" & std_logic_vector(ram_reset_count);
---- else
---- ram_reset_slow <= '0';
---- ram_reset_count <= x"0000";
---- end if;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | ac9e84e36ce139bae082d57d8cb2e973 | 0.44679 | 3.984775 | false | false | false | false |
SoCdesign/EHA | RTL/Fault_Management/Error_Detection_Correction/ParityChecker.vhd | 1 | 615 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
entity parity_checker is
generic(DATA_WIDTH : integer := 32);
port(
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
DRTS: in std_logic;
fault_out: out std_logic
);
end parity_checker;
architecture behavior of parity_checker is
signal xor_all: std_logic;
begin
xor_all <= XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
process(DRTS, RX)begin
if DRTS = '1' then
if xor_all = RX(0) then
fault_out <= '0';
else
fault_out <= '1';
end if;
else
fault_out <= '0';
end if;
end process;
end; | gpl-3.0 | 597b3e4c2f1bdb9c2ff7b118e04fbea5 | 0.684553 | 2.721239 | false | false | false | false |
SoCdesign/EHA | RTL/Fault_Management/Error_Detection_Correction/hamming_top32.vhd | 1 | 2,649 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_misc.all;
use IEEE.NUMERIC_STD.all;
-- use work.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity hamtm is
-- generic( n: integer := 34);
port (datain : in std_logic_vector(31 downto 0);
data_out: out std_logic_vector(31 downto 0);
se : out std_logic;
de : out std_logic;
ne : out std_logic
);
end hamtm;
architecture Beh of hamtm is
component hamming_encoder is
--generic(n: integer := 34);
port (datain : in Std_logic_vector(31 downto 0); -- d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27
dataout : out std_logic_vector(38 downto 0)
); -- d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 p0 p1
end component;
component hamming_decoder is
--generic(n: integer := 34);
port
(hamming_in : in std_logic_vector(38 downto 0); --d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 --d26 d27 p0 p1 p2 p3 p4 p5 p6
dataout : out std_logic_vector(31 downto 0); --d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 --d26 d27
s_err_corr : out std_logic; --diagnostic outputs
d_err_det : out std_logic; --diagnostic outputs
no_error : out std_logic); --diagnostic outputs
end component;
signal dataout_sig : std_logic_vector (38 downto 0);
signal datain_sig, data_out_sig : std_logic_vector (31 downto 0);
signal serr_sig, derr_sig, ne_sig : std_logic;
-- FOR Hamenc : hamming_encoder USE ENTITY work.hamming_encoder;
-- FOR Hamdec : hamming_decoder USE ENTITY work.hamming_decoder;
begin
datain_sig <= datain;
data_out <= data_out_sig;
se <= serr_sig;
de <= derr_sig;
ne <= ne_sig;
Hamenc : hamming_encoder
--generic map (n => 34)
port map(datain_sig, dataout_sig);
Hamdec : hamming_decoder
--generic map (n => 34)
port map( dataout_sig, data_out_sig, serr_sig, derr_sig, ne_sig );
end Beh; | gpl-3.0 | b5ad712d8d58040f0d1b232fa2579377 | 0.613817 | 3.10551 | false | false | false | false |
Ana06/function-graphing-FPGA | calculo.vhd | 2 | 8,792 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ana María Martínez Gómez, Aitor Alonso Lorenzo, Víctor Adolfo Gallego Alcalá
--
-- Create Date: 12:22:13 12/18/2013
-- Design Name:
-- Module Name: calculo - Behavioral
-- Project Name: Representación gráfica de funciones
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity calculo is
port(reset, clk, enable, integral: in std_logic;
num: in std_logic_vector(20 downto 0);
c: in std_logic_vector(49 downto 0);
s: out std_logic_vector(20 downto 0);
ready: out std_logic);
end calculo;
architecture Behavioral of calculo is
component inversor is
port( valor: in std_logic_vector(20 downto 0);
inverso: out std_logic_vector(20 downto 0));
end component inversor;
component logaritmo is
Port ( valor : in STD_LOGIC_VECTOR (20 downto 0);
log : out STD_LOGIC_VECTOR (20 downto 0);
xlogmx : out STD_LOGIC_VECTOR (20 downto 0));
end component logaritmo;
component trigo is
Port ( valor : in STD_LOGIC_VECTOR (20 downto 0);
sen : out STD_LOGIC_VECTOR (20 downto 0);
cos : out STD_LOGIC_VECTOR (20 downto 0));
end component trigo;
constant b: integer:=11;
constant d: integer:=10;
constant tres: std_logic_vector(20 downto 0):= "000000000000101010101"; -- Un tercio
constant pi: std_logic_vector(20 downto 0):= "000000000000101000101"; -- Inverso de pi
signal inum, sen, cos, log,xlogmx, acc, acc2, accsig, accsig2, mult1, mult2, cumsum, cumsumsig: std_logic_vector(b+d-1 downto 0);
signal rmultaux: std_logic_vector(2*(b+d)-1 downto 0);
signal rmult: std_logic_vector(b+d-1 downto 0);
signal estado, estadosig: std_logic_vector(4 downto 0);
begin
inversa: inversor port map(num, inum);
trigonometrico: trigo port map(num, sen, cos);
loga: logaritmo port map(num, log, xlogmx);
rmultaux <= mult1*mult2;
rmult <= rmultaux(b+2*d-1 downto d);
s <= cumsum;
pestado: process(estado, enable)
begin
if estado = "11111" then
if enable = '1' then
estadosig <= "00000";
else
estadosig <= "11111";
end if;
elsif estado = "01101" then
if enable = '1' then
estadosig <= "11111";
else
estadosig <= "01101";
end if;
elsif estado < "01101" then
estadosig <= estado+1;
else
estadosig <= "11111";
end if;
end process pestado;
asinc: process(estado, cumsum, rmult, acc, enable, num, c, inum, acc2, integral, sen, cos, log, xlogmx)
begin
ready <= '0';
accsig <= acc;
accsig2 <= acc2;
mult1 <= num; --para quitar latches, cuando se usen, aunque sean los mismos,se pondra de forma explicita
mult2 <= num; --para quitar latches, cuando se usen, aunque sean los mismos,se pondra de forma explicita
if integral = '0' then
if estado = "11111" then
cumsumsig(b+d-1 downto 5+d) <= (others => c(19));
cumsumsig(4+d downto d) <= c(19 downto 15);
cumsumsig(d-1 downto 0) <= (others => '0');
elsif estado = "00000" then
mult1 <= num;
mult2(b+d-1 downto 5+d) <= (others => c(24));
mult2(4+d downto d) <= c(24 downto 20);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
elsif estado = "00001" then
mult1 <= num;
mult2 <= num;
accsig <= rmult;
cumsumsig <= cumsum;
elsif estado = "00010" then
mult1 <= acc;
mult2(b+d-1 downto 5+d) <= (others => c(29));
mult2(4+d downto d) <= c(29 downto 25);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
elsif estado = "00011" then
mult1 <= num;
mult2 <= acc;
accsig <= rmult;
cumsumsig <= cumsum;
elsif estado = "00100" then
mult1 <= acc;
mult2(b+d-1 downto 5+d) <= (others => c(34));
mult2(4+d downto d) <= c(34 downto 30);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
elsif estado = "00101" then
mult1 <= inum;
mult2(b+d-1 downto 5+d) <= (others => c(14));
mult2(4+d downto d) <= c(14 downto 10);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
elsif estado = "00110" then
mult1 <= inum;
mult2 <= inum;
accsig <= rmult;
cumsumsig <= cumsum;
elsif estado = "00111" then
mult1 <= acc;
mult2(b+d-1 downto 5+d) <= (others => c(9));
mult2(4+d downto d) <= c(9 downto 5);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
elsif estado = "01000" then
mult1 <= acc;
mult2 <= inum;
accsig <= rmult;
cumsumsig <= cumsum;
elsif estado = "01001" then
mult1 <= acc;
mult2(b+d-1 downto 5+d) <= (others => c(4));
mult2(4+d downto d) <= c(4 downto 0);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
elsif estado = "01010" then
mult1 <= sen;
mult2(b+d-1 downto 5+d) <= (others => c(44));
mult2(4+d downto d) <= c(44 downto 40);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
elsif estado = "01011" then
mult1 <= cos;
mult2(b+d-1 downto 5+d) <= (others => c(39));
mult2(4+d downto d) <= c(39 downto 35);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
elsif estado = "01100" then
mult1 <= log;
mult2(b+d-1 downto 5+d) <= (others => c(49));
mult2(4+d downto d) <= c(49 downto 45);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
else
ready <= '1';
cumsumsig <= cumsum;
end if;
else
if estado = "11111" then
mult1 <= num;
mult2(b+d-1 downto 5+d) <= (others => c(19));
mult2(4+d downto d) <= c(19 downto 15);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= rmult(20 downto 0);
elsif estado = "00000" then
mult1 <= num;
mult2 <= num;
if rmult(20) = '0' then
accsig <= '0' & rmult(20 downto 1);
else
accsig <= '1' & rmult(20 downto 1);
end if;
accsig2 <= rmult;
cumsumsig <= cumsum;
elsif estado = "00001" then
mult1 <= acc;
mult2(b+d-1 downto 5+d) <= (others => c(24));
mult2(4+d downto d) <= c(24 downto 20);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
accsig2 <= acc2;
elsif estado = "00010" then
mult1 <= num;
mult2 <= acc2;
accsig <= rmult;
accsig2 <= rmult;
cumsumsig <= cumsum;
elsif estado = "00011" then
mult1 <= acc;
mult2 <= tres;
accsig2 <= rmult;
cumsumsig <= cumsum;
elsif estado = "00100" then
mult1 <= acc2;
mult2(b+d-1 downto 5+d) <= (others => c(29));
mult2(4+d downto d) <= c(29 downto 25);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
elsif estado = "00101" then
mult1 <= num;
mult2 <= acc;
accsig <= rmult;
cumsumsig <= cumsum;
elsif estado = "00110" then
mult1 <= acc;
mult2(b+d-1 downto 5+d) <= (others => c(34));
mult2(4+d downto d) <= c(34 downto 30);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult(20 downto 2);
elsif estado = "00111" then
mult1 <= 0-cos;
mult2 <= pi;
accsig2 <= rmult;
cumsumsig <= cumsum;
elsif estado = "01000" then
mult1 <= acc2;
mult2(b+d-1 downto 5+d) <= (others => c(44));
mult2(4+d downto d) <= c(44 downto 40);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
elsif estado = "01001" then
mult1 <= sen;
mult2 <= pi;
accsig2 <= rmult;
cumsumsig <= cumsum;
elsif estado = "01010" then
mult1 <= acc2;
mult2(b+d-1 downto 5+d) <= (others => c(39));
mult2(4+d downto d) <= c(39 downto 35);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
elsif estado = "01011" then
mult1 <= xlogmx;
mult2(b+d-1 downto 5+d) <= (others => c(49));
mult2(4+d downto d) <= c(49 downto 45);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
elsif estado = "01100" then
cumsumsig <= cumsum;
else
ready <= '1';
cumsumsig <= cumsum;
end if;
end if;
end process asinc;
sinc: process(reset, clk)
begin
if reset='1' then
estado <= (others => '1');
cumsum <= (others => '0');
acc <= (others => '0');
acc2 <= (others => '0');
elsif clk'event and clk='1' then
estado <= estadosig;
acc <= accsig;
acc2 <= accsig2;
cumsum <= cumsumsig;
end if;
end process sinc;
end Behavioral;
| gpl-3.0 | 846eca0eebb685acea007b8fc63bf3a4 | 0.595788 | 2.902213 | false | false | false | false |
TanND/Electronic | VHDL/D12_C2.vhd | 1 | 356 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D12_C2 is
port(
clk:in std_logic;
s0,s7 : out STD_LOGIC
);
end D12_C2;
--}} End of automatically maintained section
architecture D12_C2 of D12_C2 is
begin
process(clk)
begin
if(clk='1') then s0<='1';s7<='1';
else s0<='0';s7<='0';
end if;
end process;
end D12_C2;
-- clk=0.5hz | apache-2.0 | 83550b6df9968065df05c88b6d06b374 | 0.626404 | 2.405405 | false | false | false | false |
SoCdesign/EHA | Simulation/Hand_Shaking/TB_Package_32_bit.vhd | 1 | 19,373 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_misc.all;
package TB_Package is
function Header_gen(Packet_length, source, destination, packet_id: integer ) return std_logic_vector ;
function Body_gen(Packet_length, Data: integer ) return std_logic_vector ;
function Tail_gen(Packet_length, Data: integer ) return std_logic_vector ;
procedure gen_packet(Packet_length, source, destination, packet_id, initial_delay: in integer; finish_time: in time; signal clk: in std_logic; signal DCTS: in std_logic; signal RTS: out std_logic; signal port_in: out std_logic_vector);
procedure gen_random_packet(frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer; finish_time: in time; signal clk: in std_logic;
signal DCTS: in std_logic; signal RTS: out std_logic;
signal port_in: out std_logic_vector);
procedure gen_bit_reversed_packet(frame_length, source, initial_delay, network_size, min_packet_size, max_packet_size: in integer; finish_time: in time; signal clk: in std_logic;
signal DCTS: in std_logic; signal RTS: out std_logic;
signal port_in: out std_logic_vector);
procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic; signal CTS: out std_logic; signal DRTS: in std_logic; signal port_in: in std_logic_vector);
procedure gen_fault(signal sta_0, sta_1: out std_logic; signal address: out std_logic_vector; delay, seed_1, seed_2: in integer);
end TB_Package;
package body TB_Package is
constant Header_type : std_logic_vector := "001";
constant Body_type : std_logic_vector := "010";
constant Tail_type : std_logic_vector := "100";
function Header_gen(Packet_length, source, destination, packet_id: integer)
return std_logic_vector is
variable Header_flit: std_logic_vector (31 downto 0);
begin
Header_flit := Header_type & std_logic_vector(to_unsigned(Packet_length, 12)) & std_logic_vector(to_unsigned(destination, 4)) &
std_logic_vector(to_unsigned(source, 4)) & std_logic_vector(to_unsigned(packet_id, 8)) & XOR_REDUCE(Header_type &
std_logic_vector(to_unsigned(Packet_length, 12)) & std_logic_vector(to_unsigned(destination, 4)) &
std_logic_vector(to_unsigned(source, 4)) & std_logic_vector(to_unsigned(packet_id, 8)));
return Header_flit;
end Header_gen;
function Body_gen(Packet_length, Data: integer)
return std_logic_vector is
variable Body_flit: std_logic_vector (31 downto 0);
begin
Body_flit := Body_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Body_type & std_logic_vector(to_unsigned(Data, 28)));
return Body_flit;
end Body_gen;
function Tail_gen(Packet_length, Data: integer)
return std_logic_vector is
variable Tail_flit: std_logic_vector (31 downto 0);
begin
Tail_flit := Tail_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Tail_type & std_logic_vector(to_unsigned(Data, 28)));
return Tail_flit;
end Tail_gen;
procedure gen_packet(Packet_length, source, destination, packet_id, initial_delay: in integer;
finish_time: in time; signal clk: in std_logic;
signal DCTS: in std_logic; signal RTS: out std_logic;
signal port_in: out std_logic_vector) is
-- Packet_length of 3 means it has 1 header, 1 body and 1 tail. the number of body packets are equal to Packet_length-2
-- source: id of the source node
-- destination: id of the destination node
-- packet id: packet identification number! TODO: has to be implemented!
-- initial_delay: waits for this number of clock cycles before sending the packet!
variable seed1 :positive ;
variable seed2 :positive ;
variable rand : real ;
variable first_time :boolean := true;
variable destination_id: integer;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
begin
while true loop
RTS <= '0';
if first_time = true then
for i in 0 to initial_delay loop
wait until clk'event and clk ='0';
end loop;
else
wait until clk'event and clk ='0';
end if;
--wait untill the falling edge of the clock to avoid race!
report "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination);
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination) & " with length: "& integer'image(Packet_length));
writeline(VEC_FILE, LINEVARIABLE);
port_in <= Header_gen(Packet_length, source, destination, packet_id);
wait until clk'event and clk ='1';
RTS <= '1';
wait until DCTS'event and DCTS ='1';
wait until clk'event and clk ='1';
RTS <= '0';
for I in 0 to Packet_length-3 loop
uniform(seed1, seed2, rand);
wait until clk'event and clk ='0';
port_in <= Body_gen(Packet_length, integer(rand*1000.0));
wait until clk'event and clk ='1';
RTS <= '1';
wait until DCTS'event and DCTS ='1';
wait until clk'event and clk ='1';
RTS <= '0';
end loop;
wait until clk'event and clk ='0';
port_in <= Tail_gen(Packet_length, 200);
wait until clk'event and clk ='1';
RTS <= '1';
wait until DCTS'event and DCTS ='1';
wait until clk'event and clk ='1';
RTS <= '0';
if now > finish_time then
wait;
end if;
end loop;
end gen_packet;
procedure gen_random_packet(frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal DCTS: in std_logic; signal RTS: out std_logic;
signal port_in: out std_logic_vector) is
-- frame_length is inverse of PIR. with the unit of clock cycles. which means how many clock cycles per packet to
-- be injected. to build a true random traffic generator, we need to make a series of frames:
--
--
-- <--- Frame length-----> <--- Frame length-----> <--- Frame length----->
--
-- <-----> |<--------|///////|---->|<----|///////////|---->|<-|////|-------------->|
-- initial <-------> <----------> <------------->
-- delay frame Packet_size frame
-- initial end delay
-- delay
--
-- source: id of the source node
-- initial_delay: waits for this number of clock cycles before sending the packet!
variable seed1 :positive ;
variable seed2 :positive ;
variable rand : real ;
variable first_time :boolean := true;
variable id_counter : integer:= 0;
variable frame_starting_delay, Packet_length, frame_ending_delay: integer := 0;
variable destination_id: integer;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
begin
while true loop
-- generating the ID
id_counter := id_counter + 1;
if id_counter = 256 then
id_counter := 0;
end if;
-- generating the packet length
uniform(seed1, seed2, rand);
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
if (Packet_length < min_packet_size) then
Packet_length:=min_packet_size;
end if;
if (Packet_length > max_packet_size) then
Packet_length:=max_packet_size;
end if;
assert (3*Packet_length<=frame_length) report "packet_length "& integer'image(Packet_length)&" exceeds frame size "& integer'image(frame_length) severity failure;
--generating the frame initial delay
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - 3*Packet_length)))/100);
--generating the frame ending delay
frame_ending_delay := frame_length - (3*Packet_length+frame_starting_delay);
RTS <= '0';
if first_time = true then
port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ;
wait until clk'event and clk ='1';
for i in 0 to initial_delay loop
-- wait until clk'event and clk ='0';
wait for 1 ns;
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
wait until clk'event and clk ='1';
for k in 0 to frame_starting_delay-1 loop
--wait until clk'event and clk ='0';
wait for 1 ns;
end loop;
first_time := false;
else
wait until clk'event and clk ='1';
for k in 0 to frame_starting_delay-1 loop
--wait until clk'event and clk ='0';
wait for 1 ns;
end loop;
end if;
uniform(seed1, seed2, rand);
destination_id := integer(rand*3.0);
while (destination_id = source) loop
uniform(seed1, seed2, rand);
destination_id := integer(rand*3.0);
end loop;
--wait untill the falling edge of the clock to avoid race!
report "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id);
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " &
integer'image(destination_id) & " with length: "& integer'image(Packet_length)& " with id: "&integer'image(id_counter));
writeline(VEC_FILE, LINEVARIABLE);
port_in <= Header_gen(Packet_length, source, destination_id, id_counter);
wait until clk'event and clk ='1';
RTS <= '1';
wait until DCTS'event and DCTS ='1';
wait until clk'event and clk ='1';
RTS <= '0';
for I in 0 to Packet_length-3 loop
uniform(seed1, seed2, rand);
wait until clk'event and clk ='0';
port_in <= Body_gen(Packet_length, integer(rand*1000.0));
wait until clk'event and clk ='1';
RTS <= '1';
wait until DCTS'event and DCTS ='1';
wait until clk'event and clk ='1';
RTS <= '0';
end loop;
wait until clk'event and clk ='0';
uniform(seed1, seed2, rand);
port_in <= Tail_gen(Packet_length, integer(rand*1000.0));
wait until clk'event and clk ='1';
RTS <= '1';
wait until DCTS'event and DCTS ='1';
wait until clk'event and clk ='1';
RTS <= '0';
port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ;
for l in 0 to frame_ending_delay-1 loop
wait for 1 ns;
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
if now > finish_time then
wait;
end if;
end loop;
end gen_random_packet;
procedure gen_bit_reversed_packet(frame_length, source, initial_delay, network_size, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal DCTS: in std_logic; signal RTS: out std_logic;
signal port_in: out std_logic_vector) is
-- frame_length is inverse of PIR. with the unit of clock cycles. which means how many clock cycles per packet to
-- be injected. to build a true random traffic generator, we need to make a series of frames:
--
--
-- <--- Frame length-----> <--- Frame length-----> <--- Frame length----->
--
-- <-----> |<--------|///////|---->|<----|///////////|---->|<-|////|-------------->|
-- initial <-------> <----------> <------------->
-- delay frame Packet_size frame
-- initial end delay
-- delay
--
-- source: id of the source node
-- initial_delay: waits for this number of clock cycles before sending the packet!
variable seed1 :positive ;
variable seed2 :positive ;
variable rand : real ;
variable first_time :boolean := true;
variable id_counter : integer:= 0;
variable frame_starting_delay, Packet_length, frame_ending_delay: integer := 0;
variable destination_id: integer;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
begin
while true loop
-- generating the ID
id_counter := id_counter + 1;
if id_counter = 256 then
id_counter := 0;
end if;
-- generating the packet length
uniform(seed1, seed2, rand);
Packet_length := integer((integer(rand*100.0)/300)*frame_length);
if (Packet_length < min_packet_size) then
Packet_length := min_packet_size;
end if;
if (Packet_length > max_packet_size) then
Packet_length := max_packet_size;
end if;
assert (3*Packet_length<=frame_length) report "packet_length "& integer'image(Packet_length)&" exceeds frame size "& integer'image(frame_length) severity failure;
--generating the frame initial delay
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - 3*Packet_length)))/100);
--generating the frame ending delay
frame_ending_delay := frame_length - (3*Packet_length+frame_starting_delay);
RTS <= '0';
if first_time = true then
port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ;
wait until clk'event and clk ='1';
for i in 0 to initial_delay loop
-- wait until clk'event and clk ='0';
wait for 1 ns;
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
wait until clk'event and clk ='1';
for k in 0 to frame_starting_delay-1 loop
--wait until clk'event and clk ='0';
wait for 1 ns;
end loop;
first_time := false;
else
wait until clk'event and clk ='1';
for k in 0 to frame_starting_delay-1 loop
--wait until clk'event and clk ='0';
wait for 1 ns;
end loop;
end if;
destination_id := to_integer(unsigned(not std_logic_vector(to_unsigned(source, network_size))));
if destination_id = source then
wait;
end if;
--wait untill the falling edge of the clock to avoid race!
report "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id);
report " frame_size: " & integer'image(frame_length) & " packet_length: " & integer'image(Packet_length) & "starting_delay: " & integer'image(frame_starting_delay) & " ending_delay: " & integer'image(frame_ending_delay);
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " &
integer'image(destination_id) & " with length: "& integer'image(Packet_length)& " with id: "&integer'image(id_counter));
writeline(VEC_FILE, LINEVARIABLE);
port_in <= Header_gen(Packet_length, source, destination_id, id_counter);
wait until clk'event and clk ='1';
RTS <= '1';
wait until DCTS'event and DCTS ='1';
wait until clk'event and clk ='1';
RTS <= '0';
for I in 0 to Packet_length-3 loop
uniform(seed1, seed2, rand);
wait until clk'event and clk ='0';
port_in <= Body_gen(Packet_length, integer(rand*1000.0));
wait until clk'event and clk ='1';
RTS <= '1';
wait until DCTS'event and DCTS ='1';
wait until clk'event and clk ='1';
RTS <= '0';
end loop;
wait until clk'event and clk ='0';
uniform(seed1, seed2, rand);
port_in <= Tail_gen(Packet_length, integer(rand*1000.0));
wait until clk'event and clk ='1';
RTS <= '1';
wait until DCTS'event and DCTS ='1';
wait until clk'event and clk ='1';
RTS <= '0';
port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ;
for l in 0 to frame_ending_delay-1 loop
wait for 1 ns;
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
if now > finish_time then
wait;
end if;
end loop;
end gen_bit_reversed_packet;
procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal CTS: out std_logic; signal DRTS: in std_logic; signal port_in: in std_logic_vector) is
-- initial_delay: waits for this number of clock cycles before sending the packet!
variable source_node, destination_node, P_length, packet_id, counter: integer;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "received.txt";
begin
while true loop
counter := 0;
CTS <= '0';
wait until DRTS'event and DRTS ='1';
wait until clk'event and clk ='1';
CTS <= '1';
wait until clk'event and clk ='1';
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001") then
counter := 1;
P_length := to_integer(unsigned(port_in(28 downto 17)));
destination_node := to_integer(unsigned(port_in(16 downto 13)));
source_node := to_integer(unsigned(port_in(12 downto 9)));
packet_id := to_integer(unsigned(port_in(8 downto 1)));
end if;
CTS <= '0';
while (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) /= "100") loop
wait until DRTS'event and DRTS ='1';
wait until clk'event and clk ='1';
CTS <= '1';
wait until clk'event and clk ='1';
counter := counter+1;
CTS <= '0';
end loop;
report "Packet received at " & time'image(now) & " From " & integer'image(source_node) & " to " & integer'image(destination_node) & " with length: "& integer'image(P_length) & " counter: "& integer'image(counter);
assert (P_length=counter) report "wrong packet size" severity failure;
assert (Node_ID=destination_node) report "wrong packet destination " severity failure;
write(LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(source_node) & " to: " & integer'image(destination_node) & " length: "& integer'image(P_length)& " id: "& integer'image(packet_id));
writeline(VEC_FILE, LINEVARIABLE);
end loop;
end get_packet;
procedure gen_fault(signal sta_0, sta_1: out std_logic; signal address: out std_logic_vector; delay, seed_1, seed_2: in integer) is
variable seed1 :positive := seed_1;
variable seed2 :positive := seed_2;
variable rand : real;
variable stuck: integer;
begin
sta_0 <= '0';
sta_1 <= '0';
while true loop
sta_0 <= '0';
sta_1 <= '0';
for I in 0 to delay loop
wait for 1 ns;
end loop;
uniform(seed1, seed2, rand);
address <= std_logic_vector(to_unsigned(integer(rand*31.0), 5));
uniform(seed1, seed2, rand);
stuck := integer(rand*11.0);
if stuck > 5 then
sta_0 <= '1';
sta_1 <= '0';
else
sta_0 <= '0';
sta_1 <= '1';
end if;
wait for 1 ns;
end loop;
end gen_fault;
end TB_Package;
| gpl-3.0 | 168c4efb8e747cb1e5319d7ba80ef7a1 | 0.595984 | 3.811332 | false | false | false | false |
TanND/Electronic | VHDL/D9_C1.vhd | 1 | 1,146 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use IEEE.numeric_std.all;
entity D9_C1 is
port(
rst : in STD_LOGIC;
cin : in STD_LOGIC;
a : in STD_LOGIC_VECTOR(7 downto 0);
b : in STD_LOGIC_VECTOR(7 downto 0);
sel : in STD_LOGIC_VECTOR(3 downto 0);
y : out STD_LOGIC_VECTOR(7 downto 0)
);
end D9_C1;
architecture D9_C1 of D9_C1 is
begin
process(sel)
variable temp:std_logic_vector (7 downto 0);
begin
case sel is
when "0000" => temp:=a;
when "0001" => temp:=a+1;
when "0010" => temp:=a-1;
when "0011" => temp:=b;
when "0100" => temp:=b+1;
when "0101" => temp:=b-1;
when "0110" => temp:=a+b;
when "0111" => temp:=a + b + cin;
when "1000" => temp:=NOT a;
when "1001" => temp:=NOT b;
when "1010" => temp:=a AND b;
when "1011" => temp:=a OR b;
when "1100" => temp:=a NAND b;
when "1101" => temp:=a NOR b;
when "1110" => temp:=a XOR b;
when others => temp:=a XNOR b ;
end case;
y <=temp;
end process;
end D9_C1;
-- rst=10khz; cin=5Mhz; a,b= counter 0=>1111111 50ns; sel= random 100ns; | apache-2.0 | d9ee2f44374dde6a826e5cf9b7fb3776 | 0.584642 | 2.496732 | false | false | false | false |
Ana06/function-graphing-FPGA | divisor.vhd | 2 | 1,335 | ----------------------------------------------------------------------------------
-- Company: Universidad Complutense de Madrid
-- Engineer: Hortensia Mecha
--
-- Design Name: divisor
-- Module Name: divisor - divisor_arch
-- Project Name:
-- Target Devices:
-- Description: Creación de un reloj de 1Hz a partir de
-- un clk de 100 MHz
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.ALL;
entity divisor is
port (
reset: in STD_LOGIC;
clk_entrada: in STD_LOGIC; -- reloj de entrada de la entity superior
clk_salida: out STD_LOGIC -- reloj que se utiliza en los process del programa principal
);
end divisor;
architecture divisor_arch of divisor is
SIGNAL cuenta: std_logic_vector(1 downto 0);
SIGNAL clk_aux, clk: std_logic;
begin
clk<=clk_entrada;
clk_salida<=clk_aux;
contador:
PROCESS(reset, clk)
BEGIN
IF (reset='1') THEN
cuenta<= (OTHERS=>'0');
clk_aux <= '0';
ELSIF(clk'EVENT AND clk='1') THEN
IF (cuenta="11") THEN
clk_aux <= not clk_aux;
cuenta<= (OTHERS=>'0');
ELSE
cuenta <= cuenta+'1';
END IF;
END IF;
END PROCESS contador;
end divisor_arch;
| gpl-3.0 | 766fc60d97f3881637a95e35461b23ba | 0.53633 | 3.926471 | false | false | false | false |
SoCdesign/EHA | RTL/Fault_Management/SHMU_prototype/version_2/SHMU.vhd | 1 | 8,238 | --Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity SHMU is
generic (
router_fault_info_width: integer := 5;
network_size: integer := 2
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet_E_0, healthy_packet_E_0, faulty_packet_S_0, healthy_packet_S_0, faulty_packet_L_0, healthy_packet_L_0: in std_logic;
faulty_packet_W_1, healthy_packet_W_1, faulty_packet_S_1, healthy_packet_S_1, faulty_packet_L_1, healthy_packet_L_1: in std_logic;
faulty_packet_E_2, healthy_packet_E_2, faulty_packet_N_2, healthy_packet_N_2, faulty_packet_L_2, healthy_packet_L_2: in std_logic;
faulty_packet_W_3, healthy_packet_W_3, faulty_packet_N_3, healthy_packet_N_3, faulty_packet_L_3, healthy_packet_L_3: in std_logic
);
end SHMU;
architecture behavior of SHMU is
type SHM_type is array (0 to network_size*network_size-1) of std_logic_vector(router_fault_info_width-1 downto 0); --memory
signal SHM : SHM_type ;
signal Healthy_N_0, Healthy_E_0, Healthy_W_0, Healthy_S_0, Healthy_L_0: std_logic;
signal Healthy_N_1, Healthy_E_1, Healthy_W_1, Healthy_S_1, Healthy_L_1: std_logic;
signal Healthy_N_2, Healthy_E_2, Healthy_W_2, Healthy_S_2, Healthy_L_2: std_logic;
signal Healthy_N_3, Healthy_E_3, Healthy_W_3, Healthy_S_3, Healthy_L_3: std_logic;
signal Intermittent_N_0, Intermittent_E_0, Intermittent_W_0, Intermittent_S_0, Intermittent_L_0: std_logic;
signal Intermittent_N_1, Intermittent_E_1, Intermittent_W_1, Intermittent_S_1, Intermittent_L_1: std_logic;
signal Intermittent_N_2, Intermittent_E_2, Intermittent_W_2, Intermittent_S_2, Intermittent_L_2: std_logic;
signal Intermittent_N_3, Intermittent_E_3, Intermittent_W_3, Intermittent_S_3, Intermittent_L_3: std_logic;
signal Faulty_N_0, Faulty_E_0, Faulty_W_0, Faulty_S_0, Faulty_L_0: std_logic;
signal Faulty_N_1, Faulty_E_1, Faulty_W_1, Faulty_S_1, Faulty_L_1: std_logic;
signal Faulty_N_2, Faulty_E_2, Faulty_W_2, Faulty_S_2, Faulty_L_2: std_logic;
signal Faulty_N_3, Faulty_E_3, Faulty_W_3, Faulty_S_3, Faulty_L_3: std_logic;
component counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, Intermittent, Faulty:out std_logic
);
end component;
begin
-- these are the signals that do not actually exist because of the topology
Faulty_N_0 <= '0';
Faulty_W_0 <= '0';
Faulty_N_1 <= '0';
Faulty_E_1 <= '0';
Faulty_S_2 <= '0';
Faulty_W_2 <= '0';
Faulty_S_3 <= '0';
Faulty_E_3 <= '0';
CT_0_E: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map( reset => reset,
clk => clk,
faulty_packet => faulty_packet_E_0, Healthy_packet => healthy_packet_E_0,
Healthy => Healthy_E_0, Intermittent => Intermittent_E_0, Faulty => Faulty_E_0);
CT_0_S: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map( reset => reset,
clk => clk,
faulty_packet => faulty_packet_S_0, Healthy_packet => healthy_packet_S_0,
Healthy => Healthy_S_0, Intermittent => Intermittent_S_0, Faulty => Faulty_S_0);
CT_0_L: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map( reset => reset,
clk => clk,
faulty_packet => faulty_packet_L_0, Healthy_packet => healthy_packet_L_0,
Healthy => Healthy_L_0, Intermittent => Intermittent_L_0, Faulty => Faulty_L_0);
------------------------------------------------------------------------------------------------------------
CT_1_W: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_W_1, Healthy_packet => healthy_packet_W_1,
Healthy => Healthy_W_1, Intermittent => Intermittent_W_1, Faulty => Faulty_W_1);
CT_1_S: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_S_1, Healthy_packet => healthy_packet_S_1,
Healthy => Healthy_S_1, Intermittent => Intermittent_S_1, Faulty => Faulty_S_1);
CT_1_L: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_L_1, Healthy_packet => healthy_packet_L_1,
Healthy => Healthy_L_1, Intermittent => Intermittent_L_1, Faulty => Faulty_L_1);
------------------------------------------------------------------------------------------------------------
CT_2_N: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_N_2, Healthy_packet => healthy_packet_N_2,
Healthy => Healthy_N_2, Intermittent => Intermittent_N_2, Faulty => Faulty_N_2);
CT_2_E: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_E_2, Healthy_packet => healthy_packet_E_2,
Healthy => Healthy_E_2, Intermittent => Intermittent_E_2, Faulty => Faulty_E_2);
CT_2_L: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_L_2, Healthy_packet => healthy_packet_L_2,
Healthy => Healthy_L_2, Intermittent => Intermittent_L_2, Faulty => Faulty_L_2);
------------------------------------------------------------------------------------------------------------
CT_3_N: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_N_3, Healthy_packet => healthy_packet_N_3,
Healthy => Healthy_N_3, Intermittent => Intermittent_N_3, Faulty => Faulty_N_3);
CT_3_W: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_W_3, Healthy_packet => healthy_packet_W_3,
Healthy => Healthy_W_3, Intermittent => Intermittent_W_3, Faulty => Faulty_W_3);
CT_3_L: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_L_3, Healthy_packet => healthy_packet_L_3,
Healthy => Healthy_L_3, Intermittent => Intermittent_L_3, Faulty => Faulty_L_3);
process(clk, reset)begin
if reset = '0' then
SHM <= (others => (others => '0'));
elsif clk'event and clk = '1' then
SHM(0) <= Faulty_N_0 & Faulty_E_0 & Faulty_W_0 & Faulty_S_0 & Faulty_L_0;
SHM(1) <= Faulty_N_1 & Faulty_E_1 & Faulty_W_1 & Faulty_S_1 & Faulty_L_1;
SHM(2) <= Faulty_N_2 & Faulty_E_2 & Faulty_W_2 & Faulty_S_2 & Faulty_L_2;
SHM(3) <= Faulty_N_3 & Faulty_E_3 & Faulty_W_3 & Faulty_S_3 & Faulty_L_3;
end if;
end process;
END; | gpl-3.0 | dfdc917d72d43a1fe5dae013e222edfe | 0.611556 | 3.337925 | false | false | false | false |
SoCdesign/EHA | Simulation/Fault_Management/Error_Detection_Correction/Not_tested/Hamming_TB.vhd | 1 | 943 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY hamcdtb IS
END hamcdtb;
ARCHITECTURE behavior OF hamcdtb IS
COMPONENT hamtm
PORT(
datain : IN std_logic_vector(31 downto 0);
data_out : OUT std_logic_vector(31 downto 0);
se : OUT std_logic;
de : OUT std_logic;
ne : OUT std_logic
);
END COMPONENT;
--Inputs
signal datain : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal data_out : std_logic_vector(31 downto 0);
signal se : std_logic;
signal de : std_logic;
signal ne : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: hamtm PORT MAP (
datain => datain,
data_out => data_out,
se => se,
de => de,
ne => ne
);
stim_proc: process
begin
wait for 100 ns;
datain <="10101100101010111010101001111101";
end process;
END;
| gpl-3.0 | d130fb5d8600a041c72093032ba1c1a0 | 0.564157 | 3.640927 | false | false | false | false |
SoCdesign/EHA | RTL/Hand_Shaking/Hand_Shaking_FC/NI_channel.vhd | 1 | 5,785 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.math_real.all;
entity NI_channel is
generic (
DATA_WIDTH: integer := 32;
NI_DEPTH: integer:=16
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
TX: out std_logic_vector(DATA_WIDTH-1 downto 0);
DRTS, DCTS: in std_logic;
RTS,CTS: out std_logic
);
end NI_channel;
architecture behavior of NI_channel is
signal read_pointer, write_pointer, read_pointer_in: std_logic_vector(integer(ceil(log2(real(NI_DEPTH))))-1 downto 0);
signal full, empty: std_logic;
signal CB_write: std_logic;
signal CTS_in, CTS_out: std_logic;
type FIFO_Mem_type is array (0 to NI_DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_Mem : FIFO_Mem_type ;
TYPE READ_STATE_TYPE IS (IDLE, READ_DATA);
SIGNAL HS_read_state_out, HS_read_state_in : READ_STATE_TYPE;
TYPE WRITE_STATE_TYPE IS (IDLE, WRITE_DATA);
SIGNAL HS_write_state_out,HS_write_state_in, HS_write_state_next : WRITE_STATE_TYPE;
SIGNAL RTS_FF, RTS_FF_in: std_logic;
begin
--
-- PE router
-- -- ---- ---------------------------------- -- --
-- RX |<---------| TX RX |<---- | TX_L_R_?
-- DRTS|<---------| RTS DRTS |<---- | RTS_L_R_?
-- CTS |--------->| DCTS CTS |----> | DCTS_L_R_?
-- -- ---- ---------------------------------- -- --
-- circular buffer structure
-- <--- WriteP
-- ---------------------------------
-- | 3 | 2 | 1 | 0 |
-- ---------------------------------
-- <--- readP
process (clk, reset)begin
if reset = '0' then
HS_read_state_out <= IDLE;
HS_write_state_out <= IDLE;
read_pointer <= (others=>'0');
RTS_FF <= '0';
write_pointer <= (others=>'0');
FIFO_Mem <= (others => (others=>'0'));
CTS_out<= '0';
elsif clk'event and clk = '1' then
RTS_FF <= RTS_FF_in;
HS_read_state_out <= HS_read_state_in;
HS_write_state_out <= HS_write_state_next;
if (CB_write = '1' and full = '0')then
--write into the memory
-- update the write pointer
FIFO_Mem(conv_integer(write_pointer)) <= RX;
write_pointer <= write_pointer+ 1;
end if;
read_pointer <= read_pointer_in;
CTS_out<=CTS_in;
end if;
end process;
-- anything below here is pure combinational
TX <= FIFO_Mem(conv_integer(read_pointer));
RTS <= RTS_FF;
CTS <= CTS_out;
process(RTS_FF, empty, DCTS, read_pointer)begin
if (RTS_FF = '1' and DCTS='1' and empty = '0') then
read_pointer_in <= read_pointer+1;
else
read_pointer_in <= read_pointer;
end if;
end process;
process(RTS_FF, DCTS, HS_write_state_out, HS_write_state_in)begin
if RTS_FF = '1' and DCTS = '0' then
HS_write_state_next <= HS_write_state_out;
else
HS_write_state_next <= HS_write_state_in;
end if;
end process;
process(HS_write_state_out, RTS_FF, DCTS, empty)begin
if HS_write_state_out = IDLE then
RTS_FF_in <= '0';
-- if there was a grant given to one of the inputs,
-- tell the next router/NI that the output data is valid
else
if empty = '0' then
if RTS_FF = '1' and DCTS = '1' then
RTS_FF_in <= '0';
else
RTS_FF_in <= '1';
end if;
else
RTS_FF_in <= '0';
end if;
end if ;
end process;
-- read from outside
process(HS_read_state_out, full, DRTS, CTS_out) begin
case(HS_read_state_out) is
when IDLE =>
if CTS_out = '0' and DRTS = '1' and full ='0' then
HS_read_state_in <= READ_DATA;
CTS_in <= '1';
CB_write <= '1';
else
HS_read_state_in <= IDLE;
CTS_in <= '0';
CB_write <= '0';
end if;
when others => -- READ_DATA
if CTS_out = '0' and DRTS = '1' and full ='0' then
HS_read_state_in <= READ_DATA;
CTS_in <= '1';
CB_write <= '1';
else
HS_read_state_in <= IDLE;
CTS_in <= '0';
CB_write <= '0';
end if;
end case ;
end process;
-- write to outside
process(HS_write_state_out, empty) begin
case(HS_write_state_out) is
when IDLE =>
if empty ='0' then
HS_write_state_in <= WRITE_DATA;
else
HS_write_state_in <= IDLE;
end if;
when others => -- WRITE_DATA
if empty ='0' then
HS_write_state_in <= WRITE_DATA;
else
HS_write_state_in <= IDLE;
end if;
end case ;
end process;
process(write_pointer, read_pointer)begin
if read_pointer = write_pointer then
empty <= '1';
else
empty <= '0';
end if;
if write_pointer = read_pointer - 1 then
full <= '1';
else
full <= '0';
end if;
end process;
end;
| gpl-3.0 | e0fa90fc318498af47e25d982d60f7dc | 0.457563 | 3.722651 | false | false | false | false |
TanND/Electronic | VHDL/D6_C1.vhd | 1 | 1,794 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity D6_C1 is
port(
rst : in STD_LOGIC;
sel : in STD_LOGIC;
clk : in STD_LOGIC;
seg1 : out STD_LOGIC_VECTOR(7 downto 0);--hang don vi
seg2 : out STD_LOGIC_VECTOR(7 downto 0)--hang chuc
);
end D6_C1;
architecture D6_C1 of D6_C1 is
begin
process(rst,clk,sel)
variable temp1:integer range 0 to 10;
variable temp2:integer range 0 to 10;
begin
if (rst='1') then
temp1:=0;
temp2:=0;
elsif (rising_edge(clk)) then
if (sel='1') then
if (temp1=10) then
temp1:=0;
temp2:=temp2+1;
if (temp2=10) then temp2:=0;
end if;
else temp1:=temp1+1;
end if;
elsif (sel='0') then
if(temp1=0) then
temp1:=9;
temp2:=temp2-1;
if (temp2=0) then temp2:=9;
end if;
else temp1:=temp1-1;
end if;
end if;
end if;
case temp1 is
when 0 => seg1<= x"C0";
when 1 => seg1<= x"F9";
when 2 => seg1<= x"A4";
when 3 => seg1<= x"B0";
when 4 => seg1<= x"99";
when 5 => seg1<= x"92";
when 6 => seg1<= x"82";
when 7 => seg1<= x"F8";
when 8 => seg1<= x"80";
when 9 => seg1<= x"90";
when others =>NULL;
end case;
case temp2 is
when 0 => seg2<= x"C0";
when 1 => seg2<= x"F9";
when 2 => seg2<= x"A4";
when 3 => seg2<= x"B0";
when 4 => seg2<= x"99";
when 5 => seg2<= x"92";
when 6 => seg2<= x"82";
when 7 => seg2<= x"F8";
when 8 => seg2<= x"80";
when 9 => seg2<= x"90";
when others =>NULL;
end case;
end process;
end D6_C1;
-- rst= 10kHz; sel=50Khz; clk=20Mhz; | apache-2.0 | 2b7215eac339d51aa37048f017d0bfa0 | 0.483835 | 2.77709 | false | false | false | false |
lnls-dig/dsp-cores | hdl/modules/dsp_cores_pkg.vhd | 1 | 24,339 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
use std.textio.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Counter Generator Definitions
use work.counters_gen_pkg.all;
package dsp_cores_pkg is
--------------------------------------------------------------------
-- Constants
--------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Types
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
--------------------------------------------------------------------
-- Components
--------------------------------------------------------------------
component pipeline is
generic (
g_width : natural := 32;
g_depth : natural := 2);
port (
data_i : in std_logic_vector(g_width-1 downto 0);
clk_i : in std_logic;
ce_i : in std_logic;
data_o : out std_logic_vector(g_width-1 downto 0));
end component pipeline;
component pds_first_stage is
generic (
g_WIDTH : natural := 32
);
port (
clk_i : in std_logic;
a_i : in std_logic_vector(g_WIDTH-1 downto 0);
b_i : in std_logic_vector(g_WIDTH-1 downto 0);
c_i : in std_logic_vector(g_WIDTH-1 downto 0);
d_i : in std_logic_vector(g_WIDTH-1 downto 0);
ce_i : in std_logic;
valid_i : in std_logic;
diff_ac_o : out std_logic_vector(g_WIDTH-1 downto 0);
diff_bd_o : out std_logic_vector(g_WIDTH-1 downto 0);
diff_cd_minus_diff_ba_o : out std_logic_vector(g_WIDTH-1 downto 0);
sum_ac_o : out std_logic_vector(g_WIDTH-1 downto 0);
sum_bd_o : out std_logic_vector(g_WIDTH-1 downto 0);
sum_not_scaled_o : out std_logic_vector(g_WIDTH-1 downto 0);
valid_o : out std_logic
);
end component pds_first_stage;
component pds_scaling_stage is
generic (
g_WIDTH : natural := 32;
g_K_WIDTH : natural := 32
);
port (
clk_i : in std_logic;
diff_ac_over_sum_ac_i : in std_logic_vector(g_WIDTH-1 downto 0);
diff_ac_over_sum_ac_valid_i : in std_logic;
diff_bd_over_sum_bd_i : in std_logic_vector(g_WIDTH-1 downto 0);
diff_bd_over_sum_bd_valid_i : in std_logic;
sum_not_scaled_i : in std_logic_vector(g_WIDTH-1 downto 0);
sum_not_scaled_valid_i : in std_logic;
q_i : in std_logic_vector(g_WIDTH-1 downto 0);
q_valid_i : in std_logic;
kx_i : in std_logic_vector(g_K_WIDTH-1 downto 0);
ky_i : in std_logic_vector(g_K_WIDTH-1 downto 0);
ksum_i : in std_logic_vector(g_K_WIDTH-1 downto 0);
ce_i : in std_logic;
x_scaled_o : out std_logic_vector(g_WIDTH-1 downto 0);
y_scaled_o : out std_logic_vector(g_WIDTH-1 downto 0);
q_o : out std_logic_vector(g_WIDTH-1 downto 0);
sum_scaled_o : out std_logic_vector(g_WIDTH-1 downto 0);
valid_o : out std_logic
);
end component pds_scaling_stage;
component pds_offset_stage is
generic (
g_WIDTH : natural := 32;
g_PRECISION : natural := 8;
g_OFFSET_WIDTH : natural := 32;
g_OFFSET_PRECISION : natural := 0
);
port (
clk_i : in std_logic;
x_scaled_i : in std_logic_vector(g_WIDTH-1 downto 0);
y_scaled_i : in std_logic_vector(g_WIDTH-1 downto 0);
q_i : in std_logic_vector(g_WIDTH-1 downto 0);
sum_scaled_i : in std_logic_vector(g_WIDTH-1 downto 0);
offset_x_i : in std_logic_vector(g_OFFSET_WIDTH-1 downto 0);
offset_y_i : in std_logic_vector(g_OFFSET_WIDTH-1 downto 0);
ce_i : in std_logic;
valid_i : in std_logic;
x_o : out std_logic_vector(g_WIDTH-1 downto 0);
y_o : out std_logic_vector(g_WIDTH-1 downto 0);
q_o : out std_logic_vector(g_WIDTH-1 downto 0);
sum_o : out std_logic_vector(g_WIDTH-1 downto 0);
valid_o : out std_logic
);
end component pds_offset_stage;
component part_delta_sigma is
generic (
g_WIDTH : natural := 32;
g_K_WIDTH : natural := 24;
g_OFFSET_WIDTH : natural := 32
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
a_i : in std_logic_vector(g_WIDTH-1 downto 0);
b_i : in std_logic_vector(g_WIDTH-1 downto 0);
c_i : in std_logic_vector(g_WIDTH-1 downto 0);
d_i : in std_logic_vector(g_WIDTH-1 downto 0);
kx_i : in std_logic_vector(g_K_WIDTH-1 downto 0);
ky_i : in std_logic_vector(g_K_WIDTH-1 downto 0);
ksum_i : in std_logic_vector(g_K_WIDTH-1 downto 0);
offset_x_i : in std_logic_vector(g_OFFSET_WIDTH-1 downto 0) := (others => '0');
offset_y_i : in std_logic_vector(g_OFFSET_WIDTH-1 downto 0) := (others => '0');
ce_i : in std_logic;
valid_i : in std_logic;
x_o : out std_logic_vector(g_WIDTH-1 downto 0);
y_o : out std_logic_vector(g_WIDTH-1 downto 0);
q_o : out std_logic_vector(g_WIDTH-1 downto 0);
sum_o : out std_logic_vector(g_WIDTH-1 downto 0);
valid_o : out std_logic
);
end component part_delta_sigma;
component generic_multiplier is
generic (
g_a_width : natural := 16;
g_b_width : natural := 16;
g_signed : boolean := true;
g_tag_width : natural := 1;
g_p_width : natural := 16;
g_round_convergent : natural := 0;
g_levels : natural := 7);
port (
a_i : in std_logic_vector(g_a_width-1 downto 0);
b_i : in std_logic_vector(g_b_width-1 downto 0);
valid_i : in std_logic;
tag_i : in std_logic_vector(g_tag_width-1 downto 0) := (others => '0');
p_o : out std_logic_vector(g_p_width-1 downto 0);
valid_o : out std_logic;
tag_o : out std_logic_vector(g_tag_width-1 downto 0);
ce_i : in std_logic;
clk_i : in std_logic;
rst_i : in std_logic);
end component generic_multiplier;
component div_fixedpoint is
generic (
G_DATAIN_WIDTH : integer range 2 to 48;
G_PRECISION : integer range 1 to 47);
port (
clk_i : in std_logic;
rst_i : in std_logic;
ce_i : in std_logic;
n_i : in std_logic_vector(G_DATAIN_WIDTH-1 downto 0);
d_i : in std_logic_vector(G_DATAIN_WIDTH-1 downto 0);
q_o : out std_logic_vector(G_PRECISION downto 0);
r_o : out std_logic_vector(G_DATAIN_WIDTH-1 downto 0);
trg_i : in std_logic;
rdy_o : out std_logic;
err_o : out std_logic);
end component div_fixedpoint;
component delta_sigma is
generic (
g_width : natural := 32;
g_k_width : natural := 24;
g_offset_width : natural := 32);
port (
a_i : in std_logic_vector(g_width-1 downto 0);
b_i : in std_logic_vector(g_width-1 downto 0);
c_i : in std_logic_vector(g_width-1 downto 0);
d_i : in std_logic_vector(g_width-1 downto 0);
kx_i : in std_logic_vector(g_k_width-1 downto 0);
ky_i : in std_logic_vector(g_k_width-1 downto 0);
ksum_i : in std_logic_vector(g_k_width-1 downto 0);
offset_x_i : in std_logic_vector(g_offset_width-1 downto 0) := (others => '0');
offset_y_i : in std_logic_vector(g_offset_width-1 downto 0) := (others => '0');
clk_i : in std_logic;
ce_i : in std_logic;
valid_i : in std_logic;
valid_o : out std_logic;
rst_i : in std_logic;
x_o : out std_logic_vector(g_width-1 downto 0);
y_o : out std_logic_vector(g_width-1 downto 0);
q_o : out std_logic_vector(g_width-1 downto 0);
sum_o : out std_logic_vector(g_width-1 downto 0));
end component delta_sigma;
component ds_first_stage is
generic (
g_width : natural := 32);
port (
a_i : in std_logic_vector(g_width-1 downto 0);
b_i : in std_logic_vector(g_width-1 downto 0);
c_i : in std_logic_vector(g_width-1 downto 0);
d_i : in std_logic_vector(g_width-1 downto 0);
clk_i : in std_logic;
valid_i : in std_logic;
valid_o : out std_logic;
ce_i : in std_logic;
x_o : out std_logic_vector(g_width-1 downto 0);
y_o : out std_logic_vector(g_width-1 downto 0);
q_o : out std_logic_vector(g_width-1 downto 0);
sum_o : out std_logic_vector(g_width-1 downto 0));
end component ds_first_stage;
component ds_k_scaling is
generic (
g_width : natural := 32;
g_k_width : natural := 32);
port (
x_i : in std_logic_vector(g_width-1 downto 0);
kx_i : in std_logic_vector(g_k_width-1 downto 0);
x_valid_i : in std_logic;
y_i : in std_logic_vector(g_width-1 downto 0);
ky_i : in std_logic_vector(g_k_width-1 downto 0);
y_valid_i : in std_logic;
q_i : in std_logic_vector(g_width-1 downto 0);
q_valid_i : in std_logic;
sum_i : in std_logic_vector(g_width-1 downto 0);
ksum_i : in std_logic_vector(g_k_width-1 downto 0);
sum_valid_i : in std_logic;
clk_i : in std_logic;
ce_i : in std_logic;
x_o : out std_logic_vector(g_width-1 downto 0);
y_o : out std_logic_vector(g_width-1 downto 0);
q_o : out std_logic_vector(g_width-1 downto 0);
sum_o : out std_logic_vector(g_width-1 downto 0);
valid_o : out std_logic);
end component ds_k_scaling;
component ds_offset_scaling
generic (
g_width : natural := 32;
g_precision : natural := 8;
g_offset_width : natural := 32;
g_offset_precision : natural := 0);
port(
clk_i : in std_logic;
ce_i : in std_logic;
x_i : in std_logic_vector(g_width-1 downto 0);
y_i : in std_logic_vector(g_width-1 downto 0);
q_i : in std_logic_vector(g_width-1 downto 0);
sum_i : in std_logic_vector(g_width-1 downto 0);
valid_i : in std_logic;
offset_x_i : in std_logic_vector(g_offset_width-1 downto 0);
offset_y_i : in std_logic_vector(g_offset_width-1 downto 0);
x_o : out std_logic_vector(g_width-1 downto 0);
y_o : out std_logic_vector(g_width-1 downto 0);
q_o : out std_logic_vector(g_width-1 downto 0);
sum_o : out std_logic_vector(g_width-1 downto 0);
valid_o : out std_logic);
end component ds_offset_scaling;
component cordic_iter_slv is
generic (
g_input_width : positive := 16;
g_xy_calc_width : positive := 22;
g_x_output_width : positive := 16;
g_phase_calc_width : positive := 22;
g_phase_output_width : positive := 16;
g_stages : positive := 16;
g_iter_per_clk : positive := 2;
g_rounding : boolean := true);
port (
clk_i : in std_logic;
ce_data_i : in std_logic;
valid_i : in std_logic;
ce_i : in std_logic;
x_i : in std_logic_vector(g_input_width-1 downto 0);
y_i : in std_logic_vector(g_input_width-1 downto 0);
mag_o : out std_logic_vector(g_x_output_width-1 downto 0);
phase_o : out std_logic_vector(g_phase_output_width-1 downto 0);
valid_o : out std_logic);
end component cordic_iter_slv;
component cordic_iter is
generic (
XY_WID : positive := 16;
PH_WID : positive := 18;
NUM_LOOPS : positive := 18;
TAB_AD_WID : positive := 5;
ITER_PER_CLK : positive := 2;
TAB_OFFS : natural := 0);
port (
s_x_in : in signed (XY_WID-1 downto 0);
s_y_in : in signed (XY_WID-1 downto 0);
u_loop_ix_in : in unsigned (TAB_AD_WID-1 downto 0);
s_ph_in : in signed (PH_WID-1 downto 0);
s_x_o : out signed (XY_WID-1 downto 0);
s_y_o : out signed (XY_WID-1 downto 0);
s_ph_o : out signed (PH_WID-1 downto 0));
end component cordic_iter;
component cordic is
generic (
XY_CALC_WID : positive := 32;
XY_IN_WID : positive := 26;
X_OUT_WID : positive := 26;
PH_CALC_WID : positive := 30;
PH_OUT_WID : positive := 24;
NUM_ITER : positive := 24;
ITER_PER_CLK : positive := 4;
USE_INREG : boolean := true;
USE_CE : boolean := true;
ROUNDING : boolean := true);
port (
clk : in std_logic;
ce : in std_logic;
b_start_in : in std_logic;
s_x_in : in signed (XY_IN_WID-1 downto 0);
s_y_in : in signed (XY_IN_WID-1 downto 0);
s_x_o : out signed (X_OUT_WID-1 downto 0);
s_ph_o : out signed (PH_OUT_WID-1 downto 0);
b_rdy_o : out std_logic;
b_busy_o : out std_logic := '0');
end component cordic;
component cordic_input is
generic (
g_input_width : positive := 16);
port (
clk_i : in std_logic;
ce_data_i : in std_logic;
valid_i : in std_logic;
x_i : in std_logic_vector(g_input_width-1 downto 0);
y_i : in std_logic_vector(g_input_width-1 downto 0);
ce_cordic_i : in std_logic;
stall_cordic_i : in std_logic;
valid_o : out std_logic;
x_o : out std_logic_vector(g_input_width-1 downto 0);
y_o : out std_logic_vector(g_input_width-1 downto 0));
end component cordic_input;
component inversion_stage is
generic (
g_mode : string := "rect_to_polar");
port (
x_i : in signed;
y_i : in signed;
z_i : in signed;
clk_i : in std_logic;
ce_i : in std_logic;
valid_i : in std_logic;
rst_i : in std_logic;
x_o : out signed;
y_o : out signed;
z_o : out signed;
valid_o : out std_logic := '0');
end component inversion_stage;
component cordic_vectoring_slv is
generic (
g_stages : natural := 20;
g_width : natural := 32);
port (
x_i : in std_logic_vector(g_width-1 downto 0) := (others => '0');
y_i : in std_logic_vector(g_width-1 downto 0) := (others => '0');
clk_i : in std_logic;
ce_i : in std_logic;
valid_i : in std_logic;
rst_i : in std_logic;
mag_o : out std_logic_vector(g_width-1 downto 0) := (others => '0');
phase_o : out std_logic_vector(g_width-1 downto 0) := (others => '0');
valid_o : out std_logic);
end component cordic_vectoring_slv;
component cordic_core is
generic (
g_stages : natural := 20;
g_bit_growth : natural := 2;
g_mode : string := "rect_to_polar");
port (
x_i : in signed;
y_i : in signed;
z_i : in signed;
clk_i : in std_logic;
ce_i : in std_logic;
rst_i : in std_logic;
valid_i : in std_logic;
x_o : out signed;
y_o : out signed;
z_o : out signed;
valid_o : out std_logic);
end component cordic_core;
component addsub is
port (
a_i : in signed;
b_i : in signed;
sub_i : in boolean;
clk_i : in std_logic;
ce_i : in std_logic;
rst_i : in std_logic;
result_o : out signed;
positive_o : out boolean;
negative_o : out boolean);
end component addsub;
component xlclockdriver is
generic (
period : integer := 2;
log_2_period : integer := 0;
pipeline_regs : integer := 5;
use_bufg : integer := 0
);
port (
sysclk : in std_logic;
sysclr : in std_logic;
sysce : in std_logic;
clk : out std_logic;
clr : out std_logic;
ce : out std_logic;
ce_logic : out std_logic);
end component xlclockdriver;
component ce_synch
generic (
g_data_width : natural := 16
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
ce_in_i : in std_logic;
valid_i : in std_logic;
data_i : in std_logic_vector(g_data_width-1 downto 0);
ce_out_i : in std_logic;
data_o : out std_logic_vector(g_data_width-1 downto 0);
valid_o : out std_logic
);
end component;
component strobe_gen is
generic (
g_maxrate : natural := 2048;
g_bus_width : natural := 11);
port (
clk_i : in std_logic;
rst_i : in std_logic;
ce_i : in std_logic;
ratio_i : in std_logic_vector(g_bus_width-1 downto 0);
strobe_o : out std_logic);
end component strobe_gen;
component cic_dyn is
generic (
g_input_width : natural := 16;
g_output_width : natural := 16;
g_stages : natural := 1; -- aka "N"
g_delay : natural := 1; -- aka "M"
g_max_rate : natural := 2048; -- Max decimation rate
g_tag_desync_cnt_width : natural := 14;
g_bus_width : natural := 11; -- Decimation ratio bus width.
g_with_ce_synch : boolean := false;
g_tag_width : natural := 1; -- Input data tag width
g_data_mask_width : natural := 16; -- Input data mask width
g_round_convergent : natural := 0
);
port (
clk_i : in std_logic := '0';
rst_i : in std_logic := '0';
ce_i : in std_logic := '0';
ce_out_i : in std_logic := '0';
valid_i : in std_logic := '0';
data_i : in std_logic_vector(g_input_width-1 downto 0) := (others => '0');
data_tag_i : in std_logic_vector(g_tag_width-1 downto 0) := (others => '0');
data_tag_en_i : in std_logic := '0';
data_tag_desync_cnt_rst_i : in std_logic := '0';
data_tag_desync_cnt_o : out std_logic_vector(g_tag_desync_cnt_width-1 downto 0);
data_mask_num_samples_beg_i : in unsigned(g_data_mask_width-1 downto 0) := (others => '0');
data_mask_num_samples_end_i : in unsigned(g_data_mask_width-1 downto 0) := (others => '0');
data_mask_en_i : in std_logic := '0';
ratio_i : in std_logic_vector(g_bus_width-1 downto 0) := (others => '0');
data_o : out std_logic_vector(g_output_width-1 downto 0) := (others => '0');
valid_o : out std_logic := '0'
);
end component cic_dyn;
component cic_dual is
generic (
g_input_width : natural := 16;
g_output_width : natural := 16;
g_stages : natural := 1; -- aka "N"
g_delay : natural := 1; -- aka "M"
g_max_rate : natural := 2048; -- Max decimation rate
g_tag_desync_cnt_width : natural := 14;
g_bus_width : natural := 11; -- Decimation ratio bus width.
g_with_ce_synch : boolean := false;
g_tag_width : natural := 1; -- Input data tag width
g_data_mask_width : natural := 16; -- Input data mask width
g_round_convergent : natural := 0
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
ce_i : in std_logic;
ce_out_i : in std_logic := '0';
valid_i : in std_logic;
I_i : in std_logic_vector(g_input_width-1 downto 0);
I_tag_i : in std_logic_vector(g_tag_width-1 downto 0) := (others => '0');
I_tag_en_i : in std_logic := '0';
I_tag_desync_cnt_rst_i : in std_logic := '0';
I_tag_desync_cnt_o : out std_logic_vector(g_tag_desync_cnt_width-1 downto 0);
I_mask_num_samples_beg_i : in unsigned(g_data_mask_width-1 downto 0) := (others => '0');
I_mask_num_samples_end_i : in unsigned(g_data_mask_width-1 downto 0) := (others => '0');
I_mask_en_i : in std_logic := '0';
Q_i : in std_logic_vector(g_input_width-1 downto 0);
Q_tag_i : in std_logic_vector(g_tag_width-1 downto 0) := (others => '0');
Q_tag_en_i : in std_logic := '0';
Q_tag_desync_cnt_rst_i : in std_logic := '0';
Q_tag_desync_cnt_o : out std_logic_vector(g_tag_desync_cnt_width-1 downto 0);
Q_mask_num_samples_beg_i : in unsigned(g_data_mask_width-1 downto 0) := (others => '0');
Q_mask_num_samples_end_i : in unsigned(g_data_mask_width-1 downto 0) := (others => '0');
Q_mask_en_i : in std_logic := '0';
ratio_i : in std_logic_vector(g_bus_width-1 downto 0);
I_o : out std_logic_vector(g_output_width-1 downto 0);
Q_o : out std_logic_vector(g_output_width-1 downto 0);
valid_o : out std_logic
);
end component cic_dual;
component cic_decim is
generic(
DATAIN_WIDTH : integer := 16;
DATAOUT_WIDTH : integer := 16;
M : integer := 2;
N : integer := 5;
MAXRATE : integer := 64;
BITGROWTH : integer := 35;
ROUND_CONVERGENT : integer := 0
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
en_i : in std_logic;
data_i : in std_logic_vector(DATAIN_WIDTH-1 downto 0);
data_o : out std_logic_vector(DATAOUT_WIDTH-1 downto 0);
act_i : in std_logic;
act_out_i : in std_logic;
val_o : out std_logic);
end component;
component counters_gen
generic
(
g_cnt_width : t_cnt_width_array := c_default_cnt_width_array
);
port
(
rst_n_i : in std_logic;
clk_i : in std_logic;
---------------------------------
-- Counter generation interface
---------------------------------
cnt_ce_array_i : in std_logic_vector(g_cnt_width'length-1 downto 0);
cnt_up_array_i : in std_logic_vector(g_cnt_width'length-1 downto 0);
cnt_array_o : out t_cnt_array (g_cnt_width'length-1 downto 0)
);
end component;
end dsp_cores_pkg;
package body dsp_cores_pkg is
end dsp_cores_pkg;
| lgpl-3.0 | 2a3c4daa9b705bb5c69fdef056519f06 | 0.48223 | 3.331371 | false | false | false | false |
JarrettR/FPGA-Cryptoparty | FPGA/hdl/sim_wpa2.vhd | 1 | 3,041 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12/26/2016 11:44:06 PM
-- Design Name:
-- Module Name: sim_pbkdf2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.sha1_pkg.all;
entity sim_pbkdf2 is
end sim_pbkdf2;
architecture Behavioral of sim_pbkdf2 is
component pbkdf2_main is
port(
clk_i : in std_ulogic;
rst_i : in std_ulogic;
load_i : in std_ulogic;
mk_i : in mk_data;
ssid_i : in ssid_data;
dat_o : out w_output;
valid_o : out std_ulogic
);
end component;
signal valid : std_ulogic;
signal load : std_ulogic := '0';
signal clk_i : std_ulogic := '0';
signal rst_i : std_ulogic := '0';
signal mk : mk_data;
signal ssid : ssid_data;
signal dat : w_output;
signal i: integer range 0 to 65535;
constant clock_period : time := 1 ns;
begin
pbkdf2: pbkdf2_main port map (clk_i,rst_i, load, mk, ssid, dat, valid);
stim_proc: process
begin
rst_i <= '0';
i <= 0;
load <= '0';
for x in 0 to 35 loop
ssid(x) <= X"00";
end loop;
--linksys
--6c 69 6e 6b 73 79 73
ssid(0) <= X"6C";
ssid(1) <= X"69";
ssid(2) <= X"6E";
ssid(3) <= X"6B";
ssid(4) <= X"73";
ssid(5) <= X"79";
ssid(6) <= X"73";
--dictionary
--64 69 63 74 69 6f 6e 61 72 79
for x in 0 to 9 loop
mk(x) <= X"00";
end loop;
mk(0) <= X"64";
mk(1) <= X"69";
mk(2) <= X"63";
mk(3) <= X"74";
mk(4) <= X"69";
mk(5) <= X"6F";
mk(6) <= X"6E";
mk(7) <= X"61";
mk(8) <= X"72";
mk(9) <= X"79";
wait until rising_edge(clk_i);
rst_i <= '1';
wait until rising_edge(clk_i);
rst_i <= '0';
wait until rising_edge(clk_i);
load <= '1';
wait until rising_edge(clk_i);
load <= '0';
wait until rising_edge(clk_i);
while valid = '0' loop
i <= i + 1;
wait until rising_edge(clk_i);
end loop;
wait;
end process;
--ssid_dat <= ssid_data(handshake_dat(0 to 35)); --36
clock_process: process
begin
clk_i <= '0';
wait for clock_period/2;
clk_i <= '1';
wait for clock_period/2;
end process;
end Behavioral;
| gpl-3.0 | 2ec913cfa2f44645d1a608eb87846e6c | 0.414009 | 3.515607 | false | false | false | false |
bruskajp/EE-316 | Project2/Vivado_NexysBoard/project_2b/project_2b.srcs/sources_1/imports/Downloads/SPI_Display.vhd | 1 | 4,140 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity SPI_Display is
Port (
Hex_IN : in STD_LOGIC_VECTOR (15 downto 0);
iCLK : in STD_LOGIC;
MOSI : out STD_LOGIC;
CSN : out STD_LOGIC;
SCK : out STD_LOGIC);
end SPI_Display;
architecture Behavioral of SPI_Display is
signal DIV : unsigned(15 DOWNTO 0) :=X"0000";
--Signals for StateMachine:
type stateType is range 0 to 18;
Signal Sel : integer range 0 to 11;
Signal Q : std_logic;
signal CS : stateType;
signal X1,X2,X3,X4 : std_logic_vector (3 downto 0);
signal extend : std_logic_vector (3 downto 0);
signal clk_en : std_logic;
signal HEX2_Data1 : std_logic_vector (7 downto 0);
signal HEX2_Data2 : std_logic_vector (7 downto 0);
signal HEX2_Data3 : std_logic_vector (7 downto 0);
signal HEX2_Data4 : std_logic_vector (7 downto 0);
signal LUT_Data : std_logic_vector (7 downto 0);
signal sCSN : std_logic := '1';
signal sSCK : std_logic := '0';
BEGIN
LUTConversion:
Process(Hex_IN)
begin
X1 <= Hex_IN(15 downto 12);
X2 <= Hex_IN(11 downto 8);
X3 <= Hex_IN(7 downto 4);
X4 <= Hex_IN(3 downto 0);
extend <= "0000";
end process;
Process(X1, X2, X3, X4)
begin
HEX2_Data1 <= extend & X1;
HEX2_Data2 <= extend & X2;
HEX2_Data3 <= extend & X3;
HEX2_Data4 <= extend & X4;
end process;
LUTMux:
process (Sel)
begin
if (Sel = 0) then
LUT_Data <= X"76";
elsif (Sel = 1) then
LUT_Data <= X"76";
elsif (Sel = 2) then
LUT_Data <= X"76";
elsif (Sel = 3) then
LUT_Data <= X"76";
elsif (Sel = 4) then
LUT_Data <= X"79";
elsif (Sel = 5) then
LUT_Data <= X"00";
elsif (Sel = 6) then
LUT_Data <= X"7A";
elsif (Sel = 7) then
LUT_Data <= X"FF";
elsif (Sel = 8) then
LUT_Data <= HEX2_Data1;
elsif (Sel = 9) then
LUT_Data <= HEX2_Data2;
elsif (Sel = 10) then
LUT_Data <= HEX2_Data3;
elsif (Sel = 11) then
LUT_Data <= HEX2_Data4;
end if;
end process;
StateMachine:
--code pulled from Ring_Counter.vhd
process(iCLK)
begin
if rising_edge(iCLK) then
if DIV >= X"0018" then
DIV <= X"0000";
clk_en <= '1';
else
DIV <= DIV +1;
clk_en <= '0';
end if;
end if;
end process;
process (CS, iCLK, clk_en)
begin
if rising_edge(iCLK) and clk_en = '1' then
case CS is
when 0 =>
CS <= 1;
sSCK <= '0';
sCSN <= '0';
Q <= LUT_Data(7);
when 1 =>
CS <= 2;
sSCK <= '1';
Q <= LUT_Data(7);
when 2 =>
Q <= LUT_Data(6);
CS <= 3;
sSCK <= '0';
when 3 =>
Q <= LUT_Data(6);
CS <= 4;
sSCK <= '1';
when 4 =>
Q <= LUT_Data(5);
CS <= 5;
sSCK <= '0';
when 5 =>
Q <= LUT_Data(5);
CS <= 6;
sSCK <= '1';
when 6 =>
Q <= LUT_Data(4);
CS <= 7;
sSCK <= '0';
when 7 =>
Q <= LUT_Data(4);
CS <= 8;
sSCK <= '1';
when 8 =>
Q <= LUT_Data(3);
CS <= 9;
sSCK <= '0';
when 9 =>
Q <= LUT_Data(3);
CS <= 10;
sSCK <= '1';
when 10 =>
Q <= LUT_Data(2);
CS <= 11;
sSCK <= '0';
when 11 =>
Q <= LUT_Data(2);
CS <= 12;
sSCK <= '1';
when 12 =>
Q <= LUT_Data(1);
CS <= 13;
sSCK <= '0';
when 13 =>
Q <= LUT_Data(1);
CS <= 14;
sSCK <= '1';
when 14 =>
Q <= LUT_Data(0);
CS <= 15;
sSCK <= '0';
when 15 =>
Q <= LUT_Data(0);
CS <= 16;
sSCK <= '1';
when 16 =>
Q <= '0';
CS <= 17;
sSCK <= '0';
when 17 =>
Q <= '0';
CS <= 18;
sSCK <= '0';
sCSN <= '1';
if (Sel < 11) then
Sel <= Sel+1;
else
Sel <= 8;
end if;
when 18 =>
Q <= '0';
CS <= 1;
sSCK <= '0';
sCSN <= '0';
end case;
end if;
end process;
MOSI <= Q;
CSN <= sCSN;
SCK <= sSCK;
end Behavioral;
| gpl-3.0 | c4ab3cbdcd5ab8859c79a75ae742a1f8 | 0.464734 | 2.729071 | false | false | false | false |
bruskajp/EE-316 | Project4/Vivado_NexysBoard/craddockEE316/craddockEE316.srcs/sources_1/ip/sig1dualRAM/sig1dualRAM_sim_netlist.vhdl | 1 | 96,464 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.2 (win64) Build 1577090 Thu Jun 2 16:32:40 MDT 2016
-- Date : Wed Mar 15 19:17:34 2017
-- Host : ul-43 running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/ulab/Desktop/craddockEE316/craddockEE316.srcs/sources_1/ip/sig1dualRAM/sig1dualRAM_sim_netlist.vhdl
-- Design : sig1dualRAM
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity sig1dualRAM_bindec is
port (
ena_array : out STD_LOGIC_VECTOR ( 1 downto 0 );
ram_ena : out STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of sig1dualRAM_bindec : entity is "bindec";
end sig1dualRAM_bindec;
architecture STRUCTURE of sig1dualRAM_bindec is
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => ena,
I1 => addra(0),
I2 => addra(1),
O => ena_array(0)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => addra(1),
I1 => addra(0),
I2 => ena,
O => ena_array(1)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => addra(0),
I1 => ena,
I2 => addra(1),
O => ram_ena
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity sig1dualRAM_bindec_0 is
port (
enb_array : out STD_LOGIC_VECTOR ( 1 downto 0 );
ram_enb : out STD_LOGIC;
enb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of sig1dualRAM_bindec_0 : entity is "bindec";
end sig1dualRAM_bindec_0;
architecture STRUCTURE of sig1dualRAM_bindec_0 is
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => enb,
I1 => addrb(0),
I2 => addrb(1),
O => enb_array(0)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => addrb(1),
I1 => addrb(0),
I2 => enb,
O => enb_array(1)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => addrb(0),
I1 => enb,
I2 => addrb(1),
O => ram_enb
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \sig1dualRAM_blk_mem_gen_mux__parameterized0\ is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
enb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 1 downto 0 );
clkb : in STD_LOGIC;
doutb_array : in STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \sig1dualRAM_blk_mem_gen_mux__parameterized0\ : entity is "blk_mem_gen_mux";
end \sig1dualRAM_blk_mem_gen_mux__parameterized0\;
architecture STRUCTURE of \sig1dualRAM_blk_mem_gen_mux__parameterized0\ is
signal sel_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sel_pipe_d1 : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\doutb[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => doutb_array(8),
I1 => doutb_array(16),
I2 => sel_pipe_d1(1),
I3 => doutb_array(0),
I4 => sel_pipe_d1(0),
O => doutb(0)
);
\doutb[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => doutb_array(9),
I1 => doutb_array(17),
I2 => sel_pipe_d1(1),
I3 => doutb_array(1),
I4 => sel_pipe_d1(0),
O => doutb(1)
);
\doutb[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => doutb_array(10),
I1 => doutb_array(18),
I2 => sel_pipe_d1(1),
I3 => doutb_array(2),
I4 => sel_pipe_d1(0),
O => doutb(2)
);
\doutb[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => doutb_array(11),
I1 => doutb_array(19),
I2 => sel_pipe_d1(1),
I3 => doutb_array(3),
I4 => sel_pipe_d1(0),
O => doutb(3)
);
\doutb[4]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => doutb_array(12),
I1 => doutb_array(20),
I2 => sel_pipe_d1(1),
I3 => doutb_array(4),
I4 => sel_pipe_d1(0),
O => doutb(4)
);
\doutb[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => doutb_array(13),
I1 => doutb_array(21),
I2 => sel_pipe_d1(1),
I3 => doutb_array(5),
I4 => sel_pipe_d1(0),
O => doutb(5)
);
\doutb[6]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => doutb_array(14),
I1 => doutb_array(22),
I2 => sel_pipe_d1(1),
I3 => doutb_array(6),
I4 => sel_pipe_d1(0),
O => doutb(6)
);
\doutb[7]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => doutb_array(15),
I1 => doutb_array(23),
I2 => sel_pipe_d1(1),
I3 => doutb_array(7),
I4 => sel_pipe_d1(0),
O => doutb(7)
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => enb,
D => sel_pipe(0),
Q => sel_pipe_d1(0),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => enb,
D => sel_pipe(1),
Q => sel_pipe_d1(1),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => enb,
D => addrb(0),
Q => sel_pipe(0),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => enb,
D => addrb(1),
Q => sel_pipe(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity sig1dualRAM_blk_mem_gen_prim_wrapper is
port (
doutb_array : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
enb_array : in STD_LOGIC_VECTOR ( 0 to 0 );
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of sig1dualRAM_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end sig1dualRAM_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of sig1dualRAM_blk_mem_gen_prim_wrapper is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => doutb_array(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => enb_array(0),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => enb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \sig1dualRAM_blk_mem_gen_prim_wrapper__parameterized0\ is
port (
doutb_array : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
enb_array : in STD_LOGIC_VECTOR ( 0 to 0 );
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \sig1dualRAM_blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \sig1dualRAM_blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \sig1dualRAM_blk_mem_gen_prim_wrapper__parameterized0\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
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INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => doutb_array(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => enb_array(0),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => enb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \sig1dualRAM_blk_mem_gen_prim_wrapper__parameterized1\ is
port (
doutb_array : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ram_ena : in STD_LOGIC;
ram_enb : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \sig1dualRAM_blk_mem_gen_prim_wrapper__parameterized1\ : entity is "blk_mem_gen_prim_wrapper";
end \sig1dualRAM_blk_mem_gen_prim_wrapper__parameterized1\;
architecture STRUCTURE of \sig1dualRAM_blk_mem_gen_prim_wrapper__parameterized1\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => doutb_array(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_ena,
ENBWREN => ram_enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => enb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity sig1dualRAM_blk_mem_gen_prim_width is
port (
doutb_array : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
enb_array : in STD_LOGIC_VECTOR ( 0 to 0 );
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of sig1dualRAM_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end sig1dualRAM_blk_mem_gen_prim_width;
architecture STRUCTURE of sig1dualRAM_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.sig1dualRAM_blk_mem_gen_prim_wrapper
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11 downto 0) => addrb(11 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb_array(7 downto 0) => doutb_array(7 downto 0),
ena_array(0) => ena_array(0),
enb => enb,
enb_array(0) => enb_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \sig1dualRAM_blk_mem_gen_prim_width__parameterized0\ is
port (
doutb_array : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
enb_array : in STD_LOGIC_VECTOR ( 0 to 0 );
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \sig1dualRAM_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \sig1dualRAM_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \sig1dualRAM_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\sig1dualRAM_blk_mem_gen_prim_wrapper__parameterized0\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11 downto 0) => addrb(11 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb_array(7 downto 0) => doutb_array(7 downto 0),
ena_array(0) => ena_array(0),
enb => enb,
enb_array(0) => enb_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \sig1dualRAM_blk_mem_gen_prim_width__parameterized1\ is
port (
doutb_array : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ram_ena : in STD_LOGIC;
ram_enb : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \sig1dualRAM_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \sig1dualRAM_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \sig1dualRAM_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_noinit.ram\: entity work.\sig1dualRAM_blk_mem_gen_prim_wrapper__parameterized1\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11 downto 0) => addrb(11 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb_array(7 downto 0) => doutb_array(7 downto 0),
enb => enb,
ram_ena => ram_ena,
ram_enb => ram_enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity sig1dualRAM_blk_mem_gen_generic_cstr is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
enb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of sig1dualRAM_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end sig1dualRAM_blk_mem_gen_generic_cstr;
architecture STRUCTURE of sig1dualRAM_blk_mem_gen_generic_cstr is
signal doutb_array : STD_LOGIC_VECTOR ( 23 downto 0 );
signal ena_array : STD_LOGIC_VECTOR ( 1 downto 0 );
signal enb_array : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ram_ena : STD_LOGIC;
signal ram_enb : STD_LOGIC;
begin
\bindec_a.bindec_inst_a\: entity work.sig1dualRAM_bindec
port map (
addra(1 downto 0) => addra(13 downto 12),
ena => ena,
ena_array(1 downto 0) => ena_array(1 downto 0),
ram_ena => ram_ena
);
\bindec_b.bindec_inst_b\: entity work.sig1dualRAM_bindec_0
port map (
addrb(1 downto 0) => addrb(13 downto 12),
enb => enb,
enb_array(1 downto 0) => enb_array(1 downto 0),
ram_enb => ram_enb
);
\has_mux_b.B\: entity work.\sig1dualRAM_blk_mem_gen_mux__parameterized0\
port map (
addrb(1 downto 0) => addrb(13 downto 12),
clkb => clkb,
doutb(7 downto 0) => doutb(7 downto 0),
doutb_array(23 downto 0) => doutb_array(23 downto 0),
enb => enb
);
\ramloop[0].ram.r\: entity work.sig1dualRAM_blk_mem_gen_prim_width
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11 downto 0) => addrb(11 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb_array(7 downto 0) => doutb_array(7 downto 0),
ena_array(0) => ena_array(0),
enb => enb,
enb_array(0) => enb_array(0),
wea(0) => wea(0)
);
\ramloop[1].ram.r\: entity work.\sig1dualRAM_blk_mem_gen_prim_width__parameterized0\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11 downto 0) => addrb(11 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb_array(7 downto 0) => doutb_array(15 downto 8),
ena_array(0) => ena_array(1),
enb => enb,
enb_array(0) => enb_array(1),
wea(0) => wea(0)
);
\ramloop[2].ram.r\: entity work.\sig1dualRAM_blk_mem_gen_prim_width__parameterized1\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11 downto 0) => addrb(11 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb_array(7 downto 0) => doutb_array(23 downto 16),
enb => enb,
ram_ena => ram_ena,
ram_enb => ram_enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity sig1dualRAM_blk_mem_gen_top is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
enb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of sig1dualRAM_blk_mem_gen_top : entity is "blk_mem_gen_top";
end sig1dualRAM_blk_mem_gen_top;
architecture STRUCTURE of sig1dualRAM_blk_mem_gen_top is
begin
\valid.cstr\: entity work.sig1dualRAM_blk_mem_gen_generic_cstr
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
ena => ena,
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity sig1dualRAM_blk_mem_gen_v8_3_3_synth is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
enb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of sig1dualRAM_blk_mem_gen_v8_3_3_synth : entity is "blk_mem_gen_v8_3_3_synth";
end sig1dualRAM_blk_mem_gen_v8_3_3_synth;
architecture STRUCTURE of sig1dualRAM_blk_mem_gen_v8_3_3_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.sig1dualRAM_blk_mem_gen_top
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
ena => ena,
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity sig1dualRAM_blk_mem_gen_v8_3_3 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 14;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is "3";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is "Estimated Power for IP : 4.53475 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 1;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 1;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is "sig1dualRAM.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 1;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 11520;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 11520;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 8;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 8;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 11520;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 11520;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is "NO_CHANGE";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 8;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is 8;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is "blk_mem_gen_v8_3_3";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of sig1dualRAM_blk_mem_gen_v8_3_3 : entity is "yes";
end sig1dualRAM_blk_mem_gen_v8_3_3;
architecture STRUCTURE of sig1dualRAM_blk_mem_gen_v8_3_3 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
douta(7) <= \<const0>\;
douta(6) <= \<const0>\;
douta(5) <= \<const0>\;
douta(4) <= \<const0>\;
douta(3) <= \<const0>\;
douta(2) <= \<const0>\;
douta(1) <= \<const0>\;
douta(0) <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.sig1dualRAM_blk_mem_gen_v8_3_3_synth
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
ena => ena,
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity sig1dualRAM is
port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
clkb : in STD_LOGIC;
enb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of sig1dualRAM : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of sig1dualRAM : entity is "sig1dualRAM,blk_mem_gen_v8_3_3,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of sig1dualRAM : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of sig1dualRAM : entity is "blk_mem_gen_v8_3_3,Vivado 2016.2";
end sig1dualRAM;
architecture STRUCTURE of sig1dualRAM is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 14;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "3";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 4.53475 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 1;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 1;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "sig1dualRAM.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 1;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 11520;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 11520;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 8;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 8;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 11520;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 11520;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "NO_CHANGE";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 8;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 8;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute KEEP_HIERARCHY : string;
attribute KEEP_HIERARCHY of U0 : label is "true";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.sig1dualRAM_blk_mem_gen_v8_3_3
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(7 downto 0) => dina(7 downto 0),
dinb(7 downto 0) => B"00000000",
douta(7 downto 0) => NLW_U0_douta_UNCONNECTED(7 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
eccpipece => '0',
ena => ena,
enb => enb,
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(13 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(13 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(13 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(13 downto 0),
s_axi_rdata(7 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(7 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(7 downto 0) => B"00000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
| gpl-3.0 | c97da3e8ae8f3d0543307dd62157b50e | 0.714712 | 4.107823 | false | false | false | false |
SoCdesign/EHA | RTL/Immortal_Chip/xbar.vhd | 4 | 1,004 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity XBAR is
generic (
DATA_WIDTH: integer := 8
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end;
architecture behavior of XBAR is
begin
process(sel, North_in, East_in, West_in, South_in, Local_in) begin
case(sel) is
when "00001" =>
Data_out <= North_in;
when "00010" =>
Data_out <= East_in;
when "00100" =>
Data_out <= West_in;
when "01000" =>
Data_out <= South_in;
when others =>
Data_out <= Local_in;
end case;
end process;
end; | gpl-3.0 | f8d147dc34561decd5b90aa5eb00a033 | 0.59761 | 3.127726 | false | false | false | false |
SoCdesign/EHA | RTL/Hand_Shaking/Checkers/Control_part_checkers/Handshaking_FC/FIFO_control_part_checkers/RTL_and_Synthesis/FIFO_control_part_pseudo.vhd | 1 | 4,099 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_control_part_pseudo is
port ( DRTS: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
CTS_out: in std_logic;
CTS_in: out std_logic;
empty_out: out std_logic;
full_out: out std_logic;
read_pointer_in: out std_logic_vector(3 downto 0);
write_pointer_in: out std_logic_vector(3 downto 0);
read_en_out: out std_logic;
write_en_out: out std_logic
);
end FIFO_control_part_pseudo;
architecture behavior of FIFO_control_part_pseudo is
signal full, empty: std_logic;
signal read_en, write_en: std_logic;
begin
--------------------------------------------------------------------------------------------
-- block diagram of the FIFO!
-- previous
-- router
-- -- ------------------------------------------
-- | | |
-- TX|--------->| RX Data_out|----> goes to Xbar and LBDR
-- | | |
-- RTS|--------->| DRTS FIFO read_en|<---- Comes from Arbiters (N,E,W,S,L)
-- | | (N,E,W,S,L)|
-- DCTS|<---------| CTS |
-- -- ------------------------------------------
--------------------------------------------------------------------------------------------
-- Hand shake protocol!
--
-- |<-Valid->|
-- | Data |
-- _____ _________ ______
-- RX _____X_________X______
-- DRTS _____|'''''''''|_____
-- CTS __________|''''|_______
--
--------------------------------------------------------------------------------------------
-- circular buffer structure
-- <--- WriteP
-- ---------------------------------
-- | 3 | 2 | 1 | 0 |
-- ---------------------------------
-- <--- readP
--------------------------------------------------------------------------------------------
-- anything below here is pure combinational
-- combinatorial part
read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty;
empty_out <= empty;
read_en_out <= read_en;
write_en_out <= write_en;
full_out <= full;
process(write_en, write_pointer)begin
if write_en = '1'then
write_pointer_in <= write_pointer(2 downto 0)&write_pointer(3);
else
write_pointer_in <= write_pointer;
end if;
end process;
process(read_en, empty, read_pointer)begin
if (read_en = '1' and empty = '0') then
read_pointer_in <= read_pointer(2 downto 0)&read_pointer(3);
else
read_pointer_in <= read_pointer;
end if;
end process;
process(full, DRTS, CTS_out) begin
if CTS_out = '0' and DRTS = '1' and full ='0' then
CTS_in <= '1';
write_en <= '1';
else
CTS_in <= '0';
write_en <= '0';
end if;
end process;
process(write_pointer, read_pointer) begin
if read_pointer = write_pointer then
empty <= '1';
else
empty <= '0';
end if;
if write_pointer = read_pointer(0)&read_pointer(3 downto 1) then
full <= '1';
else
full <= '0';
end if;
end process;
end; | gpl-3.0 | e6dd293db43b6039b96f10baa126e12c | 0.374726 | 4.3746 | false | false | false | false |
JarrettR/FPGA-Cryptoparty | FPGA/hdl/gen_ssid.vhd | 1 | 2,156 | --------------------------------------------------------------------------------
-- gen_ssid.vhd
-- SSID generator for hardcoded benchmarking, because ZTEX interface is slow
-- Copyright (C) 2016 Jarrett Rainier
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sha1_pkg.all;
entity gen_ssid is
port(
clk_i : in std_ulogic;
rst_i : in std_ulogic;
complete_o : out std_ulogic;
dat_mk_o : out mk_data
);
end gen_ssid;
architecture RTL of gen_ssid is
signal w: w_input;
signal w_temp: w_input;
signal carry: std_ulogic;
signal pmk : integer range 0 to 50; --Ten digit, hex (16^10)
begin
process(clk_i)
begin
if (clk_i'event and clk_i = '1') then
if rst_i = '1' then
pmk <= 0;
complete_o <= '0';
else
if pmk = 50 then
pmk <= 0;
complete_o <= '1';
else
pmk <= pmk + 1;
complete_o <= '0';
end if;
end if;
end if;
end process;
-- Alt: generate statement
dat_mk_o(0) <= to_unsigned(pmk,8);
dat_mk_o(1) <= to_unsigned(pmk,16) sll 8;
end RTL; | gpl-3.0 | 294b66ccd890fb4cf64f58370c116167 | 0.503711 | 4.007435 | false | false | false | false |
lnls-dig/dsp-cores | hdl/modules/divider/arith_dsp48e_package.vhd | 1 | 22,928 | library ieee;
use ieee.std_logic_1164.all;
use work.utilities.all;
package arith_dsp48e is
------------------------------------------------------------------------------------------
-- Fixed-point divider using DSP48E slice
------------------------------------------------------------------------------------------
-- Performs the operation "n_i" (numerator) divided by "d_i" (denominator), both
-- containing "G_DATAIN_WIDTH" bits, and presents the result in "q_o" (quotient) and
-- "r_o" (remainder) after "G_PRECISION"+2 clock cycles. "q_o" contains "G_PRECISION"+1
-- bits (msb is the sign bit, 2's complement) and "r_o" contains the same number of bits
-- as "n_i" and "d_i". Both division results (quotient and remainder) has the decimal
-- point shifted "G_PRECISION" bits to the left in relation to the operands' (numerator
-- and denominator) decimal points, which must be in the same position.
--
-- "trg" and "rdy" are one-clock-cycle controls to request new division calculation and
-- indicate its completion, respectively.
--
-- "err_o" is asserted when a trigger comes before a division completion. A new trigger
-- is only allowed after "G_PRECISION"+1 clock cycles after the valid trigger.
--
-- Known limitations:
-- - The denominator must be greater than the numerator.
-- - The denominator must be positive.
------------------------------------------------------------------------------------------
component div_fixedpoint is
generic
(
G_DATAIN_WIDTH : integer range 2 to 48;
G_PRECISION : integer range 1 to 47
);
port
(
clk_i : in std_logic;
rst_i : in std_logic;
ce_i : in std_logic;
n_i : in std_logic_vector(G_DATAIN_WIDTH-1 downto 0);
d_i : in std_logic_vector(G_DATAIN_WIDTH-1 downto 0);
q_o : out std_logic_vector(G_PRECISION downto 0);
r_o : out std_logic_vector(G_DATAIN_WIDTH-1 downto 0);
trg_i : in std_logic;
rdy_o : out std_logic;
err_o : out std_logic
);
end component;
------------------------------------------------------------------------------------------
-- Floating-point divider using DSP48E slice
------------------------------------------------------------------------------------------
-- Performs the operation "n_i" (numerator) divided by "d_i" (denominator), both
-- containing "G_DATA_WIDTH" bits, and presents the result in "q_o" (quotient) and
-- "r_o" (remainder) after "G_DATA_WIDTH"+4 clock cycles. "q_o" and "r_o" contain the
-- same number of bits as "n_i" and "d_i" (msb is the sign bit, 2's complement). The
-- decimal point of "n_i" or the decimal point of "d_i" is shifted to the left before
-- performing a fixed-point division. With the left shift, the "n_i" arithmetic msb is
-- put one position below the "d_i" arithmetic msb. The shift amplitude is presented in
-- the "shift_o" output.
--
-- The final division result (quotient and remainder) has the decimal point shifted by
-- "G_DATA_WIDTH" - 1 + shift_o.
--
-- "trg" and "rdy" are one-clock-cycle flags to request new division calculation and
-- indicate its completion, respectively.
--
-- "err_o" is asserted when a trigger comes before a division completion. A new trigger
-- is only allowed after "G_DATA_WIDTH"+5 clock cycles after the valid trigger.
--
-- Known limitations:
-- - The denominator must be positive.
-- - It is not possible to trigger a new calculation during the clock cycle that data
-- ready is asserted.
-- - The position of the most significant bit of the numerator must not exceed
-- "G_DATA_WIDTH"-3.
------------------------------------------------------------------------------------------
component div_floatingpoint is
generic
(
G_DATA_WIDTH : integer range 2 to 48
);
port
(
clk_i : in std_logic;
rst_i : in std_logic;
ce_i : in std_logic;
n_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
d_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
q_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
r_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
shift_o : out std_logic_vector(log2(G_DATA_WIDTH) downto 0);
trg_i : in std_logic;
rdy_o : out std_logic;
err_o : out std_logic
);
end component;
------------------------------------------------------------------------------------------
--
------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
component div_ieee754_single is
generic
(
G_DATA_WIDTH : integer range 2 to 48
);
port
(
clk_i : in std_logic;
rst_i : in std_logic;
ce_i : in std_logic;
n_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
d_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
q_o : out std_logic_vector(31 downto 0);
trg_i : in std_logic;
rdy_o : out std_logic;
err_o : out std_logic
);
end component;
end arith_dsp48e;
----------------------------------------------------------------------------------------------
-- div_fixedpoint
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity div_fixedpoint is
generic
(
G_DATAIN_WIDTH : integer range 2 to 48 := 48;
G_PRECISION : integer range 1 to 47 := 47
);
port
(
clk_i : in std_logic;
rst_i : in std_logic;
ce_i : in std_logic;
n_i : in std_logic_vector(G_DATAIN_WIDTH-1 downto 0);
d_i : in std_logic_vector(G_DATAIN_WIDTH-1 downto 0);
q_o : out std_logic_vector(G_PRECISION downto 0);
r_o : out std_logic_vector(G_DATAIN_WIDTH-1 downto 0);
trg_i : in std_logic;
rdy_o : out std_logic;
err_o : out std_logic
);
end div_fixedpoint;
architecture rtl of div_fixedpoint is
-- Division initialization and operands hold
signal slv_n_hold : std_logic_vector(G_DATAIN_WIDTH-1 downto 0) := (others => '0');
signal slv_d_hold : std_logic_vector(G_DATAIN_WIDTH-1 downto 0) := (others => '0');
signal slv_alumode_init : std_logic_vector(3 downto 0) := (others => '0');
-- Start/stop divison signals
signal sl_init : std_logic := '1';
signal sl_finished : std_logic;
-- Iteration counter
signal uv_count : unsigned(5 downto 0) :=(others => '0');
constant C_MAX_COUNT : unsigned(5 downto 0) := to_unsigned(G_PRECISION+1, 6);
-- Entity outputs (auxiliary signals)
signal slv_q : std_logic_vector(G_PRECISION downto 0) := (others => '0');
signal slv_r : std_logic_vector(G_DATAIN_WIDTH-1 downto 0) := (others => '0');
signal sl_err : std_logic := '0';
-- DSP48E inputs
signal slv_r_extended : std_logic_vector(47 downto 0);
signal slv_d_hold_extended : std_logic_vector(47 downto 0);
signal slv_alumode : std_logic_vector(3 downto 0);
-- DSP48E outputs
signal slv_r_fb : std_logic_vector(47 downto 0);
signal slv_carryout : std_logic_vector(3 downto 0);
begin
DSP48E_inst : DSP48E
generic map
(
ALUMODEREG => 0,
AREG => 0,
ACASCREG => 0,
A_INPUT => "DIRECT",
BREG => 0,
BCASCREG => 0,
B_INPUT => "DIRECT",
CREG => 0,
MREG => 0,
OPMODEREG => 0,
PREG => 1,
USE_MULT => "NONE"
)
port map
(
CARRYOUT => slv_carryout,
P => slv_r_fb,
A => slv_d_hold_extended(47 downto 18),
ACIN => (others => '0'),
ALUMODE => slv_alumode,
B => slv_d_hold_extended(17 downto 0),
BCIN => (others => '0'),
C => slv_r_extended,
CARRYCASCIN => '0',
CARRYIN => '0',
CARRYINSEL => "000",
CEA1 => '0',
CEA2 => ce_i,
CEALUMODE => ce_i,
CEB1 => '0',
CEB2 => ce_i,
CEC => '0',
CECARRYIN => ce_i,
CECTRL => '0',
CEM => '0',
CEMULTCARRYIN => '0',
CEP => ce_i,
CLK => clk_i,
MULTSIGNIN => '0',
OPMODE => "0110011",
PCIN => (others => '0'),
RSTA => rst_i,
RSTALLCARRYIN => rst_i,
RSTALUMODE => rst_i,
RSTB => rst_i,
RSTC => rst_i,
RSTCTRL => rst_i,
RSTM => rst_i,
RSTP => rst_i
);
-- Holds numerator, denominator and add/subtract operation for division initalization
prc_hold_operands : process(clk_i)
begin
if rising_edge(clk_i) then
if ce_i = '1' then
if trg_i = '1' then
slv_n_hold <= n_i;
slv_d_hold <= d_i;
slv_alumode_init <= "00" & not(n_i(G_DATAIN_WIDTH-1)) & not(n_i(G_DATAIN_WIDTH-1));
end if;
end if;
end if;
end process;
-- Iteration counter and start/stop division control
prc_control : process(rst_i, clk_i)
begin
if rst_i = '1' then
sl_init <= '1';
uv_count <= (others => '0');
rdy_o <= '0';
sl_err <= '0';
elsif rising_edge(clk_i) then
if ce_i = '1' then
if uv_count = 0 then
-- Assert data ready ("rdy_o") for one clock cycle if no error has occured
if sl_err = '0' then
if sl_finished = '0' then
rdy_o <= '1';
else
rdy_o <= '0';
end if;
end if;
if trg_i = '1' then
uv_count <= C_MAX_COUNT;
sl_init <= '1';
sl_finished <= '0';
sl_err <= '0';
else
sl_finished <= '1';
end if;
else
uv_count <= uv_count - 1;
sl_init <= '0';
rdy_o <= '0';
-- If a new trigger comes before completion of current division processing,
-- asserts error output high until a new trigger comes in a legal time instant
if trg_i = '1' then
sl_err <= '1';
end if;
end if;
end if;
end if;
end process;
-- Builds quotient bit vector
prc_quotient : process(clk_i)
begin
if rising_edge(clk_i) then
if ce_i = '1' then
slv_q <= slv_q(G_PRECISION-1 downto 0) & slv_carryout(3);
end if;
end if;
end process;
-- Assigns internal signals to output
q_o <= slv_q;
r_o <= slv_r;
err_o <= sl_err;
-- Sets next remainder (current remainder shifted to the left by 2) (or initialization)
slv_r <= slv_n_hold when sl_init = '1' else
slv_r_fb(G_DATAIN_WIDTH-2 downto 0) & '0';
-- Sets next operation (add or subtract) based on carry bit (or initialization)
slv_alumode <= slv_alumode_init when sl_init = '1' else
"00" & slv_carryout(3) & slv_carryout(3);
-- Sign extension for DSP48E input signals
slv_d_hold_extended(G_DATAIN_WIDTH-1 downto 0) <= slv_d_hold;
slv_d_hold_extended(47 downto G_DATAIN_WIDTH) <= (others => slv_d_hold(G_DATAIN_WIDTH-1));
slv_r_extended(G_DATAIN_WIDTH-1 downto 0) <= slv_r;
slv_r_extended(47 downto G_DATAIN_WIDTH) <= (others => slv_r(G_DATAIN_WIDTH-1));
end rtl;
----------------------------------------------------------------------------------------------
-- div_floatingpoint
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arith_dsp48e.all;
use work.utilities.all;
library unisim;
use unisim.vcomponents.all;
entity div_floatingpoint is
generic
(
G_DATA_WIDTH : integer range 2 to 48 := 48
);
port
(
clk_i : in std_logic;
rst_i : in std_logic;
ce_i : in std_logic;
n_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
d_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
q_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
r_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
shift_o : out std_logic_vector(log2(G_DATA_WIDTH) downto 0);
trg_i : in std_logic;
rdy_o : out std_logic;
err_o : out std_logic
);
end div_floatingpoint;
architecture rtl of div_floatingpoint is
-- FSM states
type state_type is (IDLE, CALCULATE_SHIFT, SHIFT, DIVIDE);
signal state : state_type;
-- Division initialization and operands hold
signal slv_n_hold : std_logic_vector(G_DATA_WIDTH-1 downto 0) := (others => '0');
signal slv_d_hold : std_logic_vector(G_DATA_WIDTH-1 downto 0) := (others => '0');
-- Entity outputs (auxiliary signals)
signal sl_rdy : std_logic;
signal sl_err : std_logic;
-- Start/stop divison signals
signal sl_init : std_logic;
-- Number of bits to shift for increasing division precision
signal sv_shift : signed(log2(G_DATA_WIDTH) downto 0) := (others => '0');
begin
div_fixedpoint_inst : div_fixedpoint
generic map
(
G_DATAIN_WIDTH => G_DATA_WIDTH,
G_PRECISION => G_DATA_WIDTH-1
)
port map
(
clk_i => clk_i,
rst_i => rst_i,
ce_i => ce_i,
n_i => slv_n_hold,
d_i => slv_d_hold,
q_o => q_o,
r_o => r_o,
trg_i => sl_init,
rdy_o => sl_rdy,
err_o => open
);
-- Assigns internal signals to output
shift_o <= std_logic_vector(sv_shift);
err_o <= sl_err;
-- Only asserts ready output if fixed-point division has finished and there was no bad trigger.
rdy_o <= sl_rdy and not(sl_err);
-- Finite state-machine which sequences the operations: wait for trigger (idle), calculate shift, shift and divide.
prc_fsm : process(rst_i, clk_i)
variable v_sv_msb_n, v_sv_msb_d : signed(log2(G_DATA_WIDTH) downto 0);
variable v_sv_n_hold, v_sv_d_hold : signed(G_DATA_WIDTH-1 downto 0);
variable v_i_shift : integer range 0 to G_DATA_WIDTH-1;
begin
if rst_i = '1' then
state <= IDLE;
sl_init <= '0';
elsif rising_edge(clk_i) then
if ce_i = '1' then
case state is
when IDLE =>
if trg_i = '1' then
state <= CALCULATE_SHIFT;
end if;
slv_n_hold <= n_i;
slv_d_hold <= d_i;
when CALCULATE_SHIFT =>
state <= SHIFT;
v_sv_msb_n := signed(find_msb(slv_n_hold, slv_n_hold(slv_n_hold'left)));
v_sv_msb_d := signed(find_msb(slv_d_hold, slv_d_hold(slv_d_hold'left)));
sv_shift <= v_sv_msb_d - v_sv_msb_n - 1;
sl_init <= '0';
when SHIFT =>
state <= DIVIDE;
v_i_shift := to_integer(abs(sv_shift));
if sv_shift > 0 then
v_sv_n_hold := signed(slv_n_hold);
slv_n_hold <= std_logic_vector(v_sv_n_hold sll v_i_shift);
else
v_sv_d_hold := signed(slv_d_hold);
slv_d_hold <= std_logic_vector(v_sv_d_hold sll v_i_shift);
end if;
sl_init <= '1';
when DIVIDE =>
if sl_rdy = '1' and trg_i = '1' then
state <= CALCULATE_SHIFT;
elsif sl_rdy = '1' then
state <= IDLE;
end if;
sl_init <= '0';
when others =>
state <= IDLE;
end case;
end if;
end if;
end process;
-- Asserts error when trigger comes before end of division.
prc_error : process(rst_i, clk_i)
begin
if rst_i = '1' then
sl_err <= '0';
elsif rising_edge(clk_i) then
if ce_i = '1' then
if state = IDLE and trg_i = '1' then
sl_err <= '0';
elsif state = DIVIDE and trg_i = '1' and sl_rdy = '1' then
sl_err <= '0';
elsif trg_i = '1' then
sl_err <= '1';
end if;
end if;
end if;
end process;
end rtl;
----------------------------------------------------------------------------------------------
-- div_ieee754_single
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arith_dsp48e.all;
use work.utilities.all;
library unisim;
use unisim.vcomponents.all;
entity div_ieee754_single is
generic
(
G_DATA_WIDTH : integer range 2 to 48 := 48
);
port
(
clk_i : in std_logic;
rst_i : in std_logic;
ce_i : in std_logic;
n_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
d_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
q_o : out std_logic_vector(31 downto 0);
trg_i : in std_logic;
rdy_o : out std_logic;
err_o : out std_logic
);
end div_ieee754_single;
architecture rtl of div_ieee754_single is
-- FSM states
type state_type is (IDLE, CHECK_SIGNAL, CALCULATE_SHIFT, SHIFT, CHECK_ADDITIONAL_SHIFT, DIVIDE);
signal state : state_type := IDLE;
-- Division initialization and operands hold
signal slv_n_hold : std_logic_vector(G_DATA_WIDTH-1 downto 0) := (others => '0');
signal slv_d_hold : std_logic_vector(G_DATA_WIDTH-1 downto 0) := (others => '0');
-- Entity outputs (auxiliary signals)
signal sl_rdy : std_logic;
signal sl_err : std_logic;
-- Start/stop divison signals
signal sl_init : std_logic := '0';
-- Sections of 32-bit single precision binary
signal slv_signed_mantissa : std_logic_vector(24 downto 0);
signal sv_exponent : signed(7 downto 0);
signal sl_result_signal : std_logic;
-- Number of bits to shift for increasing division precision
signal sv_shift : signed(log2(G_DATA_WIDTH) downto 0) := (others => '0');
begin
div_fixedpoint_inst : div_fixedpoint
generic map
(
G_DATAIN_WIDTH => G_DATA_WIDTH,
G_PRECISION => 24
)
port map
(
clk_i => clk_i,
rst_i => rst_i,
ce_i => ce_i,
n_i => slv_n_hold,
d_i => slv_d_hold,
q_o => slv_signed_mantissa,
r_o => open,
trg_i => sl_init,
rdy_o => sl_rdy,
err_o => open
);
-- Assigns internal signals to output
-- Note: additional shift for making 1 <= mantissa < 2 (instead of .5 <= mantissa < 1 result of integer division)
-- The msb (always equals to 1 (positive number) or 0 (negative number)) is discarded since the IEEE 754 already considers it implicitly)
q_o <= sl_result_signal & std_logic_vector(sv_exponent) & slv_signed_mantissa(22 downto 0);
err_o <= sl_err;
-- Only asserts ready output if fixed-point division has finished and there was no bad trigger.
rdy_o <= sl_rdy and not(sl_err);
-- Finite state-machine which sequences the operations: wait for trigger (idle), calculate shift, shift and divide.
prc_fsm : process(rst_i, clk_i)
variable v_sv_msb_n, v_sv_msb_d : signed(log2(G_DATA_WIDTH) downto 0);
variable v_sv_n_hold, v_sv_d_hold : signed(G_DATA_WIDTH-1 downto 0);
variable v_i_shift : integer range 0 to G_DATA_WIDTH-1;
begin
if rst_i = '1' then
state <= IDLE;
sl_init <= '0';
elsif rising_edge(clk_i) then
if ce_i = '1' then
case state is
when IDLE =>
if trg_i = '1' then
state <= CALCULATE_SHIFT;
sl_result_signal <= n_i(n_i'left);
slv_n_hold <= std_logic_vector(abs(signed(n_i)));
slv_d_hold <= d_i;
end if;
when CALCULATE_SHIFT =>
state <= SHIFT;
v_sv_msb_n := signed(find_msb(slv_n_hold, slv_n_hold(slv_n_hold'left)));
v_sv_msb_d := signed(find_msb(slv_d_hold, slv_d_hold(slv_d_hold'left)));
sv_shift <= v_sv_msb_d - v_sv_msb_n;
sl_init <= '0';
when SHIFT =>
state <= CHECK_ADDITIONAL_SHIFT;
v_i_shift := to_integer(abs(sv_shift));
if sv_shift > 0 then
v_sv_n_hold := signed(slv_n_hold);
slv_n_hold <= std_logic_vector(v_sv_n_hold sll v_i_shift);
else
v_sv_d_hold := signed(slv_d_hold);
slv_d_hold <= std_logic_vector(v_sv_d_hold sll v_i_shift);
end if;
sl_init <= '0';
when CHECK_ADDITIONAL_SHIFT =>
state <= DIVIDE;
v_sv_n_hold := signed(slv_n_hold);
v_sv_d_hold := signed(slv_d_hold);
if (v_sv_n_hold > v_sv_d_hold) then
v_sv_n_hold := signed(slv_n_hold);
slv_n_hold <= std_logic_vector(v_sv_n_hold srl 1);
sv_shift <= sv_shift - 1;
end if;
sl_init <= '1';
when DIVIDE =>
-- Add 127 offset to exponent and subtract 1 due to additional shift for making 1 <= mantissa < 2
sv_exponent <= to_signed(126, 8) - resize(sv_shift, 8);
if sl_rdy = '1' and trg_i = '1' then
state <= CALCULATE_SHIFT;
elsif sl_rdy = '1' then
state <= IDLE;
end if;
sl_init <= '0';
when others =>
state <= IDLE;
end case;
end if;
end if;
end process;
-- Asserts error when trigger comes before end of division.
prc_error : process(rst_i, clk_i)
begin
if rst_i = '1' then
sl_err <= '0';
elsif rising_edge(clk_i) then
if ce_i = '1' then
if state = IDLE and trg_i = '1' then
sl_err <= '0';
elsif state = DIVIDE and trg_i = '1' and sl_rdy = '1' then
sl_err <= '0';
elsif trg_i = '1' then
sl_err <= '1';
end if;
end if;
end if;
end process;
end rtl;
| lgpl-3.0 | 36f0a98fd3586f8438a43cd73780b486 | 0.500349 | 3.599937 | false | false | false | false |
bruskajp/EE-316 | Project2/Quartus_DE2Board/clk_enabler.vhd | 1 | 715 | library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use ieee.std_logic_unsigned.all;
entity clk_enabler is
GENERIC (
CONSTANT cnt_max : integer := 39999999);
--CONSTANT cnt_max : integer := 5); --For testing purposes
port(
clock: in std_logic;
clk_en: out std_logic);
end clk_enabler;
----------------------------------------------------
architecture behv of clk_enabler is
signal clk_cnt: integer range 0 to cnt_max;
begin
process(clock)
begin
if rising_edge(clock) then
if (clk_cnt = cnt_max) then
clk_cnt <= 0;
clk_en <= '1';
else
clk_cnt <= clk_cnt + 1;
clk_en <= '0';
end if;
end if;
end process;
end behv;
| gpl-3.0 | a8fb395d67e97c0354e979ea713683a7 | 0.602797 | 2.883065 | false | false | false | false |
bruskajp/EE-316 | Project1/display_driver.vhd | 1 | 1,819 | -- Author: Zander Blasingame
-- Class: EE 316 Spring 2017
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity display_driver is
port (
keycode : in std_logic_vector(7 downto 0);
sram_address : in std_logic_vector(7 downto 0);
sram_data : in std_logic_vector(15 downto 0);
write_address : in std_logic;
is_programming : in std_logic;
clk : in std_logic;
address : out std_logic_vector(7 downto 0);
data : out std_logic_vector(15 downto 0)
);
end display_driver;
architecture behavior of display_driver is
-- Internal Register Signals
signal data_register : std_logic_vector(15 downto 0) := x"0000";
signal address_register : std_logic_vector(7 downto 0) := x"00";
begin
-- Demux for piping input into correct register
process(write_address, keycode)
begin
if keycode(7 downto 4) /= x"F" and rising_edge(clk) then
if write_address = '1' then
address_register(3 downto 0) <= keycode(3 downto 0);
address_register(7 downto 4) <= address_register(3 downto 0);
else
data_register(3 downto 0) <= keycode(3 downto 0);
data_register(7 downto 4) <= data_register(3 downto 0);
data_register(11 downto 8) <= data_register(7 downto 4);
data_register(15 downto 12) <= data_register(11 downto 8);
end if;
end if;
-- Reset registers in op mode
if is_programming = '0' then
address_register <= x"00";
data_register <= x"0000";
end if;
end process;
-- Mux for piping selecting data output stream
process(is_programming, address_register, data_register)
begin
if is_programming = '1' then
address <= address_register;
data <= data_register;
else
address <= sram_address;
data <= sram_data;
end if;
end process;
end behavior; | gpl-3.0 | 7141f0c86f9a32ed3a73e752e78a85b3 | 0.656954 | 3.141623 | false | false | false | false |
lnls-dig/dsp-cores | hdl/testbench/cic/wb_bpm_swap/bpm_swap/deswap_channels.vhd | 2 | 2,028 | ------------------------------------------------------------------------------
-- Title : BPM RF channels de-swapping
------------------------------------------------------------------------------
-- Author : Jose Alvim Berkenbrock
-- Company : CNPEM LNLS-DIG
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Swap data channels when the deswap input signal is high; keep
-- channels paths unchanged otherwise.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity deswap_channels is
generic(
g_ch_width : natural := 16
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
deswap_i : in std_logic;
ch1_i : in std_logic_vector(g_ch_width-1 downto 0);
ch2_i : in std_logic_vector(g_ch_width-1 downto 0);
ch_valid_i : in std_logic;
ch1_o : out std_logic_vector(g_ch_width-1 downto 0);
ch2_o : out std_logic_vector(g_ch_width-1 downto 0);
deswap_o : out std_logic;
ch_valid_o : out std_logic
);
end deswap_channels;
architecture rtl of deswap_channels is
begin
deswap_proc : process (clk_i)
begin
if (rising_edge(clk_i)) then
if (rst_n_i = '0') then
ch1_o <= (others => '0');
ch2_o <= (others => '0');
ch_valid_o <= '0';
else
ch_valid_o <= ch_valid_i;
if (ch_valid_i = '1') then
deswap_o <= deswap_i;
if (deswap_i = '1') then
ch1_o <= ch2_i;
ch2_o <= ch1_i;
else
ch1_o <= ch1_i;
ch2_o <= ch2_i;
end if;
end if;
end if;
end if;
end process deswap_proc;
end;
| lgpl-3.0 | b81997317af1933d9bc9a2af8c0be1e1 | 0.43787 | 3.769517 | false | false | false | false |
lnls-dig/dsp-cores | hdl/modules/cordic/inversion_stage.vhd | 1 | 3,536 | -------------------------------------------------------------------------------
-- Title : Inversion stage
-- Project :
-------------------------------------------------------------------------------
-- File : inversion_stage.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-05-09
-- Last update: 2015-10-15
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: The CORDIC algorithm only converges to the proper value if the
-- initial point to be converted is in the right half plane. So, if the point is in
-- the left halfplane, rotate it 180o and apply the rotation value .
-------------------------------------------------------------------------------
-- This file is part of Concordic.
--
-- Concordic is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Concordic is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- Copyright (c) 2014 Aylons Hazzud
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-05-09 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
-------------------------------------------------------------------------------
entity inversion_stage is
generic (
g_mode : string := "rect_to_polar"
);
port (
x_i : in signed;
y_i : in signed;
z_i : in signed;
clk_i : in std_logic;
ce_i : in std_logic;
valid_i : in std_logic;
rst_i : in std_logic;
x_o : out signed;
y_o : out signed;
z_o : out signed;
valid_o : out std_logic := '0'
);
end entity inversion_stage;
-------------------------------------------------------------------------------
architecture str of inversion_stage is
constant width : integer := z_i'length;
constant rotation_angle : signed := to_signed(integer(-2**(width-1)), width);
-- rotate 180o
begin -- architecture str
process(clk_i) is
variable left_halfplane : boolean := false;
begin
if rising_edge(clk_i) then
if rst_i = '1' then
x_o <= (x_o'length-1 downto 0 => '0');
y_o <= (y_o'length-1 downto 0 => '0');
z_o <= (z_o'length-1 downto 0 => '0');
valid_o <= '0';
else
if ce_i = '1' then
left_halfplane := (x_i < 0);
if left_halfplane then
x_o <= -x_i;
y_o <= -y_i;
z_o <= rotation_angle;
else
x_o <= x_i;
y_o <= y_i;
z_o <= to_signed(0, width);
end if; -- left_halfplane
valid_o <= valid_i;
end if; --clock enable
end if; --reset
end if; --rising edge
end process;
end architecture str;
-------------------------------------------------------------------------------
| lgpl-3.0 | e0b6c51a685b95f3e1f7fd0061102581 | 0.474548 | 4.174734 | false | false | false | false |
SoCdesign/EHA | RTL/Immortal_Chip/LBDR_with_checkers.vhd | 2 | 8,268 | --Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR is
generic (
cur_addr_rst: integer := 5;
Rxy_rst: integer := 60;
Cx_rst: integer := 15;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic;
-- Checker outputs
--err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in : out std_logic
);
end LBDR;
architecture behavior of LBDR is
signal Cx: std_logic_vector(3 downto 0);
signal Rxy: std_logic_vector(7 downto 0);
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal N1, E1, W1, S1 :std_logic := '0';
signal Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: std_logic;
signal Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: std_logic;
component LBDR_checkers is
generic (
cur_addr_rst: integer := 5;
NoC_size: integer := 4
);
port ( empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic;
N1_out, E1_out, W1_out, S1_out: in std_logic;
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
-- Checker outputs
--err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in : out std_logic
);
end component;
begin
Cx <= std_logic_vector(to_unsigned(Cx_rst, Cx'length));
Rxy <= std_logic_vector(to_unsigned(Rxy_rst, Rxy'length));
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
N1 <= '1' when dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) else '0';
E1 <= '1' when cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) else '0';
W1 <= '1' when dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) else '0';
S1 <= '1' when cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) else '0';
LBDRCHECKERS: LBDR_checkers generic map (cur_addr_rst => cur_addr_rst, NoC_size => NoC_size)
port map (
empty => empty,
flit_type => flit_type,
Req_N_FF => Req_N_FF,
Req_E_FF => Req_E_FF,
Req_W_FF => Req_W_FF,
Req_S_FF => Req_S_FF,
Req_L_FF => Req_L_FF,
Req_N_in => Req_N_in,
Req_E_in => Req_E_in,
Req_W_in => Req_W_in,
Req_S_in => Req_S_in,
Req_L_in => Req_L_in,
N1_out => N1,
E1_out => E1,
W1_out => W1,
S1_out => S1,
dst_addr => dst_addr,
err_header_empty_Requests_FF_Requests_in => err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in => err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => err_header_not_empty_Req_S_in
);
process(clk, reset)
begin
if reset = '0' then
Req_N_FF <= '0';
Req_E_FF <= '0';
Req_W_FF <= '0';
Req_S_FF <= '0';
Req_L_FF <= '0';
elsif clk'event and clk = '1' then
Req_N_FF <= Req_N_in;
Req_E_FF <= Req_E_in;
Req_W_FF <= Req_W_in;
Req_S_FF <= Req_S_in;
Req_L_FF <= Req_L_in;
end if;
end process;
-- The combionational part
Req_N <= Req_N_FF;
Req_E <= Req_E_FF;
Req_W <= Req_W_FF;
Req_S <= Req_S_FF;
Req_L <= Req_L_FF;
process(N1, E1, W1, S1, Rxy, Cx, flit_type, empty, Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF) begin
if flit_type = "001" and empty = '0' then
Req_N_in <= ((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0);
Req_E_in <= ((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1);
Req_W_in <= ((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2);
Req_S_in <= ((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3);
Req_L_in <= not N1 and not E1 and not W1 and not S1;
elsif flit_type = "100" then
Req_N_in <= '0';
Req_E_in <= '0';
Req_W_in <= '0';
Req_S_in <= '0';
Req_L_in <= '0';
else
Req_N_in <= Req_N_FF;
Req_E_in <= Req_E_FF;
Req_W_in <= Req_W_FF;
Req_S_in <= Req_S_FF;
Req_L_in <= Req_L_FF;
end if;
end process;
END; | gpl-3.0 | 7d297a0bd873e73d3fa1031684aef51e | 0.487421 | 3.00436 | false | false | false | false |
SoCdesign/EHA | RTL/Credit_Based/Checkers/Control_Part_Checkers/outdated/FIFO_one_hot_credit_based_control_part_checkers/RTL_and_Synthesis/FIFO_one_hot_credit_based_control_part_checkers.vhd | 1 | 4,911 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity FIFO_credit_based_control_part_checkers is
port ( valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
read_pointer_in: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
write_pointer_in: in std_logic_vector(3 downto 0);
credit_out: in std_logic;
empty_out: in std_logic;
full_out: in std_logic;
read_en_out: in std_logic;
write_en_out: in std_logic;
-- Checker outputs
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_read_en_credit_out,
err_not_read_en_credit_out,
err_write_en,
err_not_write_en,
err_read_en_mismatch : out std_logic
);
end FIFO_credit_based_control_part_checkers;
architecture behavior of FIFO_credit_based_control_part_checkers is
signal read_en_signal: std_logic;
begin
read_en_signal <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty_out;
-- Checkers
process (write_en_out, write_pointer_in, write_pointer)
begin
if (write_en_out = '1' and write_pointer_in /= (write_pointer(2 downto 0) & write_pointer(3)) ) then
err_write_en_write_pointer <= '1';
else
err_write_en_write_pointer <= '0';
end if;
end process;
-- Checked !
process (write_en_out, write_pointer_in, write_pointer)
begin
if (write_en_out = '0' and write_pointer_in /= write_pointer ) then
err_not_write_en_write_pointer <= '1';
else
err_not_write_en_write_pointer <= '0';
end if;
end process;
-- Checked !
process (read_pointer, write_pointer, empty_out)
begin
if (read_pointer = write_pointer and empty_out = '0' ) then
err_read_pointer_write_pointer_not_empty <= '1';
else
err_read_pointer_write_pointer_not_empty <= '0';
end if;
end process;
-- Checked !
process (read_pointer, write_pointer, empty_out)
begin
if (read_pointer /= write_pointer and empty_out = '1' ) then
err_read_pointer_write_pointer_empty <= '1';
else
err_read_pointer_write_pointer_empty <= '0';
end if;
end process;
-- Checked !
process (write_pointer, read_pointer, full_out)
begin
if (write_pointer = (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '0' ) then
err_read_pointer_write_pointer_not_full <= '1';
else
err_read_pointer_write_pointer_not_full <= '0';
end if;
end process;
-- Checked !
process (write_pointer, read_pointer, full_out)
begin
if (write_pointer /= (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '1' ) then
err_read_pointer_write_pointer_full <= '1';
else
err_read_pointer_write_pointer_full <= '0';
end if;
end process;
-- Checked !
process (read_en_out, empty_out, read_pointer_in, read_pointer)
begin
if (read_en_out = '1' and empty_out = '0' and read_pointer_in /= (read_pointer(2 downto 0)&read_pointer(3)) ) then
err_read_pointer_increment <= '1';
else
err_read_pointer_increment <= '0';
end if;
end process;
-- Checked !
process (read_en_out, empty_out, read_pointer_in, read_pointer)
begin
if ( (read_en_out = '0' or (read_en_out = '1' and empty_out = '1') ) and read_pointer_in /= read_pointer ) then
err_read_pointer_not_increment <= '1';
else
err_read_pointer_not_increment <= '0';
end if;
end process;
-- Checked !
process (read_en_out, credit_out)
begin
if (read_en_out = '1' and credit_out = '0') then
err_read_en_credit_out <= '1';
else
err_read_en_credit_out <= '0';
end if;
end process;
-- Added !
process (read_en_out, credit_out)
begin
if (read_en_out = '0' and credit_out = '1') then
err_not_read_en_credit_out <= '1';
else
err_not_read_en_credit_out <= '0';
end if;
end process;
-- Added !
process (valid_in, full_out, write_en_out)
begin
if (valid_in = '1' and full_out = '0' and write_en_out = '0') then
err_write_en <= '1';
else
err_write_en <= '0';
end if;
end process;
-- Updated !
process (valid_in, full_out, write_en_out)
begin
if ( (valid_in = '0' or full_out = '1') and write_en_out = '1') then
err_not_write_en <= '1';
else
err_not_write_en <= '0';
end if;
end process;
-- Updated !
process (read_en_out, read_en_signal)
begin
if (read_en_out /= read_en_signal) then
err_read_en_mismatch <= '1';
else
err_read_en_mismatch <= '0';
end if;
end process;
end behavior; | gpl-3.0 | 6a0d28ad86b679d5147eb22158389f00 | 0.644268 | 2.745109 | false | false | false | false |
SoCdesign/EHA | RTL/Immortal_Chip/Arbiter_checkers.vhd | 2 | 21,217 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Arbiter_checkers is
port (
Req_N, Req_E, Req_W, Req_S, Req_L :in std_logic;
DCTS: in std_logic;
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L: in std_logic;
Xbar_sel : in std_logic_vector(4 downto 0);
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
next_state_out: in std_logic_vector (5 downto 0);
RTS_FF: in std_logic;
RTS_FF_in: in std_logic;
-- Checker outputs
err_state_IDLE_xbar,
err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE,
err_IDLE_Req_L,
err_Local_Req_L,
err_North_Req_N,
--err_East_Req_E,
--err_West_Req_W,
--err_South_Req_S,
err_IDLE_Req_N,
err_Local_Req_N,
--err_North_Req_E,
--err_East_Req_W,
--err_West_Req_S,
err_South_Req_L,
--err_IDLE_Req_E,
--err_Local_Req_E,
--err_North_Req_W,
--err_East_Req_S,
err_West_Req_L,
err_South_Req_N,
--err_IDLE_Req_W,
--err_Local_Req_W,
--err_North_Req_S,
err_East_Req_L,
err_West_Req_N,
--err_South_Req_E,
--err_IDLE_Req_S,
--err_Local_Req_S,
--err_North_Req_L,
err_East_Req_N,
--err_West_Req_E,
--err_South_Req_W,
err_next_state_onehot,
err_state_in_onehot,
--err_DCTS_RTS_FF_state_Grant_L,
--err_DCTS_RTS_FF_state_Grant_N,
--err_DCTS_RTS_FF_state_Grant_E,
--err_DCTS_RTS_FF_state_Grant_W,
--err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel,
err_state_east_xbar_sel,
err_state_west_xbar_sel,
err_state_south_xbar_sel : out std_logic
--err_state_local_xbar_sel : out std_logic
);
end Arbiter_checkers;
architecture behavior of Arbiter_checkers is
CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001";
CONSTANT Local: std_logic_vector (5 downto 0) := "000010";
CONSTANT North: std_logic_vector (5 downto 0) := "000100";
CONSTANT East: std_logic_vector (5 downto 0) := "001000";
CONSTANT West: std_logic_vector (5 downto 0) := "010000";
CONSTANT South: std_logic_vector (5 downto 0) := "100000";
SIGNAL Requests: std_logic_vector (4 downto 0);
SIGNAL Grants: std_logic_vector (4 downto 0);
begin
Requests <= Req_N & Req_E & Req_W & Req_S & Req_L;
Grants <= Grant_N & Grant_E & Grant_W & Grant_S & Grant_L;
-- Checkers
--checked
process (Xbar_sel, state)
begin
if (state = IDLE and Xbar_sel /= "00000") then
err_state_IDLE_xbar <= '1';
else
err_state_IDLE_xbar <= '0';
end if;
end process;
--checked
process (state, Xbar_sel)
begin
if ( state /= IDLE and
Xbar_sel /= "00001" and Xbar_sel /= "00010" and Xbar_sel /= "00100" and Xbar_sel /= "01000" and Xbar_sel /= "10000") then
err_state_not_IDLE_xbar <= '1';
else
err_state_not_IDLE_xbar <= '0';
end if;
end process;
--checked
process (state, RTS_FF_in)
begin
if (state = IDLE and RTS_FF_in = '1') then
err_state_IDLE_RTS_FF_in <= '1';
else
err_state_IDLE_RTS_FF_in <= '0';
end if;
end process;
--checked
process (state, RTS_FF, RTS_FF_in)
begin
if ( (state = North or state = East or state = West or state = South or state = Local) and RTS_FF = '0' and RTS_FF = '0' and RTS_FF_in = '0') then
err_state_not_IDLE_RTS_FF_RTS_FF_in <= '1';
else
err_state_not_IDLE_RTS_FF_RTS_FF_in <= '0';
end if;
end process;
--checked
process (state, DCTS, RTS_FF, RTS_FF_in)
begin
if ( (state = North or state = East or state = West or state = South or state = Local) and RTS_FF = '1' and DCTS = '1' and RTS_FF_in = '1') then
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in <= '1';
else
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in <= '0';
end if;
end process;
--checked
process (state, DCTS, RTS_FF, RTS_FF_in)
begin
if ( (state = North or state = East or state = West or state = South or state = Local) and RTS_FF = '1' and DCTS = '0' and RTS_FF_in = '0') then
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in <= '1';
else
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in <= '0';
end if;
end process;
--checked
process (RTS_FF, DCTS, state, state_in)
begin
if (RTS_FF = '1' and DCTS = '0' and state /= state_in) then
err_RTS_FF_not_DCTS_state_state_in <= '1';
else
err_RTS_FF_not_DCTS_state_state_in <= '0';
end if;
end process;
--checked
process (RTS_FF, state_in, next_state_out)
begin
if (RTS_FF = '0' and state_in /= next_state_out) then
err_not_RTS_FF_state_in_next_state <= '1';
else
err_not_RTS_FF_state_in_next_state <= '0';
end if;
end process;
--checked
process (RTS_FF, DCTS, state_in, next_state_out)
begin
if (RTS_FF = '1' and DCTS = '1' and state_in /= next_state_out) then
err_RTS_FF_DCTS_state_in_next_state <= '1';
else
err_RTS_FF_DCTS_state_in_next_state <= '0';
end if;
end process;
--checked
process (RTS_FF, Grants)
begin
if (RTS_FF = '0' and Grants /= "00000") then
err_not_DCTS_Grants <= '1';
else
err_not_DCTS_Grants <= '0';
end if;
end process;
--checked
process (DCTS, RTS_FF, Grants)
begin
if (RTS_FF = '1' and DCTS = '0' and Grants /= "00000") then
err_DCTS_not_RTS_FF_Grants <= '1';
else
err_DCTS_not_RTS_FF_Grants <= '0';
end if;
end process;
--checked
process (DCTS, RTS_FF, state, Grants)
begin
if (DCTS = '1' and RTS_FF = '1' and state = IDLE and Grants /= "00000") then
err_DCTS_RTS_FF_IDLE_Grants <= '1';
else
err_DCTS_RTS_FF_IDLE_Grants <= '0';
end if;
end process;
--checked
process (DCTS, RTS_FF, state, Grants)
begin
if (DCTS = '1' and RTS_FF = '1' and state /= IDLE and
Grants /= "00001" and Grants /= "00010" and Grants /= "00100" and Grants /= "01000" and Grants /= "10000") then
err_DCTS_RTS_FF_not_IDLE_Grants_onehot <= '1';
else
err_DCTS_RTS_FF_not_IDLE_Grants_onehot <= '0';
end if;
end process;
--checked
process (state, Requests, next_state_out)
begin
if ( (state = North or state = East or state = West or state = South or state = Local or state = IDLE) and Requests = "00000" and next_state_out /= IDLE ) then
err_Requests_next_state_IDLE <= '1';
else
err_Requests_next_state_IDLE <= '0';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 1
--checked
process (state, Req_L, next_state_out)
begin
if ( state = IDLE and Req_L = '1' and next_state_out /= Local) then
err_IDLE_Req_L <= '1';
else
err_IDLE_Req_L <= '0';
end if;
end process;
process (state, Req_L, next_state_out)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and Req_L = '1' and next_state_out /= Local) then
err_Local_Req_L <= '1';
else
err_Local_Req_L <= '0';
end if;
end process;
--checked
process (state, Req_N, next_state_out)
begin
if (state = North and Req_N = '1' and next_state_out /= North) then
err_North_Req_N <= '1';
else
err_North_Req_N <= '0';
end if;
end process;
----checked
--process (state, Req_E, next_state_out)
--begin
-- if (state = East and Req_E = '1' and next_state_out /= East) then
-- err_East_Req_E <= '1';
-- else
-- err_East_Req_E <= '0';
-- end if;
--end process;
----checked
--process (state, Req_W, next_state_out)
--begin
-- if (state = West and Req_W = '1' and next_state_out /= West) then
-- err_West_Req_W <= '1';
-- else
-- err_West_Req_W <= '0';
-- end if;
--end process;
----checked
--process (state, Req_S, next_state_out)
--begin
-- if (state = South and Req_S = '1' and next_state_out /= South) then
-- err_South_Req_S <= '1';
-- else
-- err_South_Req_S <= '0';
-- end if;
--end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 2
--checked
process (state, Req_L, Req_N, next_state_out)
begin
if ( state = IDLE and Req_L = '0' and Req_N = '1' and next_state_out /= North) then
err_IDLE_Req_N <= '1';
else
err_IDLE_Req_N <= '0';
end if;
end process;
process (state, Req_L, Req_N, next_state_out)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and Req_L = '0' and Req_N = '1' and next_state_out /= North) then
err_Local_Req_N <= '1';
else
err_Local_Req_N <= '0';
end if;
end process;
----checked
--process (state, Req_N, Req_E, next_state_out)
--begin
-- if (state = North and Req_N = '0' and Req_E = '1' and next_state_out /= East) then
-- err_North_Req_E <= '1';
-- else
-- err_North_Req_E <= '0';
-- end if;
--end process;
--process (state, Req_E, Req_W, next_state_out)
--begin
-- if (state = East and Req_E = '0' and Req_W = '1' and next_state_out /= West) then
-- err_East_Req_W <= '1';
-- else
-- err_East_Req_W <= '0';
-- end if;
--end process;
--process (state, Req_W, Req_S, next_state_out)
--begin
-- if (state = West and Req_W = '0' and Req_S = '1' and next_state_out /= South) then
-- err_West_Req_S <= '1';
-- else
-- err_West_Req_S <= '0';
-- end if;
--end process;
process (state, Req_S, Req_L, next_state_out)
begin
if (state = South and Req_S = '0' and Req_L = '1' and next_state_out /= Local) then
err_South_Req_L <= '1';
else
err_South_Req_L <= '0';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 3
--process (state, Req_L, Req_N, Req_E, next_state_out)
--begin
-- if ( state = IDLE and Req_L = '0' and Req_N = '0' and Req_E = '1' and next_state_out /= East) then
-- err_IDLE_Req_E <= '1';
-- else
-- err_IDLE_Req_E <= '0';
-- end if;
--end process;
--process (state, Req_L, Req_N, Req_E, next_state_out)
--begin
-- if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
-- Req_L = '0' and Req_N = '0' and Req_E = '1' and next_state_out /= East) then
-- err_Local_Req_E <= '1';
-- else
-- err_Local_Req_E <= '0';
-- end if;
--end process;
--process (state, Req_N, Req_E, Req_W, next_state_out)
--begin
-- if (state = North and Req_N = '0' and Req_E = '0' and Req_W = '1' and next_state_out /= West) then
-- err_North_Req_W <= '1';
-- else
-- err_North_Req_W <= '0';
-- end if;
--end process;
--process (state, Req_E, Req_W, Req_S, next_state_out)
--begin
-- if (state = East and Req_E = '0' and Req_W = '0' and Req_S = '1' and next_state_out /= South) then
-- err_East_Req_S <= '1';
-- else
-- err_East_Req_S <= '0';
-- end if;
--end process;
process (state, Req_W, Req_S, Req_L, next_state_out)
begin
if (state = West and Req_W = '0' and Req_S = '0' and Req_L = '1' and next_state_out /= Local) then
err_West_Req_L <= '1';
else
err_West_Req_L <= '0';
end if;
end process;
process (state, Req_S, Req_L, Req_N, next_state_out)
begin
if (state = South and Req_S = '0' and Req_L = '0' and Req_N = '1' and next_state_out /= North) then
err_South_Req_N <= '1';
else
err_South_Req_N <= '0';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 4
--process (state, Req_L, Req_N, Req_E, Req_W, next_state_out)
--begin
-- if ( state = IDLE and Req_L = '0' and Req_N = '0' and Req_E = '0' and Req_W = '1' and next_state_out /= West) then
-- err_IDLE_Req_W <= '1';
-- else
-- err_IDLE_Req_W <= '0';
-- end if;
--end process;
--process (state, Req_L, Req_N, Req_E, Req_W, next_state_out)
--begin
-- if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
-- Req_L = '0' and Req_N = '0' and Req_E = '0' and Req_W = '1' and next_state_out /= West) then
-- err_Local_Req_W <= '1';
-- else
-- err_Local_Req_W <= '0';
-- end if;
--end process;
--process (state, Req_N, Req_E, Req_W, Req_S, next_state_out)
--begin
-- if (state = North and Req_N = '0' and Req_E = '0' and Req_W = '0' and Req_S = '1' and next_state_out /= South) then
-- err_North_Req_S <= '1';
-- else
-- err_North_Req_S <= '0';
-- end if;
--end process;
process (state, Req_E, Req_W, Req_S, Req_L, next_state_out)
begin
if (state = East and Req_E = '0' and Req_W = '0' and Req_S = '0' and Req_L = '1' and next_state_out /= Local) then
err_East_Req_L <= '1';
else
err_East_Req_L <= '0';
end if;
end process;
process (state, Req_W, Req_S, Req_L, Req_N, next_state_out)
begin
if (state = West and Req_W = '0' and Req_S = '0' and Req_L = '0' and Req_N = '1' and next_state_out /= North) then
err_West_Req_N <= '1';
else
err_West_Req_N <= '0';
end if;
end process;
--process (state, Req_S, Req_L, Req_N, Req_E, next_state_out)
--begin
-- if (state = South and Req_S = '0' and Req_L = '0' and Req_N = '0' and Req_E = '1' and next_state_out /= East) then
-- err_South_Req_E <= '1';
-- else
-- err_South_Req_E <= '0';
-- end if;
--end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 5
--process (state, Req_L, Req_N, Req_E, Req_W, Req_S, next_state_out)
--begin
-- if ( state = IDLE and Req_L = '0' and Req_N = '0' and Req_E = '0' and Req_W = '0' and Req_S = '1'
-- and next_state_out /= South) then
-- err_IDLE_Req_S <= '1';
-- else
-- err_IDLE_Req_S <= '0';
-- end if;
--end process;
--process (state, Req_L, Req_N, Req_E, Req_W, Req_S, next_state_out)
--begin
-- if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
-- Req_L = '0' and Req_N = '0' and Req_E = '0' and Req_W = '0' and Req_S = '1'
-- and next_state_out /= South) then
-- err_Local_Req_S <= '1';
-- else
-- err_Local_Req_S <= '0';
-- end if;
--end process;
--process (state, Req_N, Req_E, Req_W, Req_S, Req_L, next_state_out)
--begin
-- if (state = North and Req_N = '0' and Req_E = '0' and Req_W = '0' and Req_S = '0' and Req_L = '1'
-- and next_state_out /= Local) then
-- err_North_Req_L <= '1';
-- else
-- err_North_Req_L <= '0';
-- end if;
--end process;
process (state, Req_E, Req_W, Req_S, Req_L, Req_N, next_state_out)
begin
if (state = East and Req_E = '0' and Req_W = '0' and Req_S = '0' and Req_L = '0' and Req_N = '1'
and next_state_out /= North) then
err_East_Req_N <= '1';
else
err_East_Req_N <= '0';
end if;
end process;
--process (state, Req_W, Req_S, Req_L, Req_N, Req_E, next_state_out)
--begin
-- if (state = West and Req_W = '0' and Req_S = '0' and Req_L = '0' and Req_N = '0' and Req_E = '1'
-- and next_state_out /= East) then
-- err_West_Req_E <= '1';
-- else
-- err_West_Req_E <= '0';
-- end if;
--end process;
--process (state, Req_S, Req_L, Req_N, Req_E, Req_W, next_state_out)
--begin
-- if (state = South and Req_S = '0' and Req_L = '0' and Req_N = '0' and Req_E = '0' and Req_W = '1'
-- and next_state_out /= West) then
-- err_South_Req_W <= '1';
-- else
-- err_South_Req_W <= '0';
-- end if;
--end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
process (next_state_out)
begin
if (next_state_out /= IDLE and next_state_out /= North and next_state_out /= East and next_state_out /= West and
next_state_out /= South and next_state_out /= Local) then
err_next_state_onehot <= '1';
else
err_next_state_onehot <= '0';
end if;
end process;
process (state_in)
begin
if (state_in /= IDLE and state_in /= North and state_in /= East and state_in /= West and
state_in /= South and state_in /= Local) then
err_state_in_onehot <= '1';
else
err_state_in_onehot <= '0';
end if;
end process;
--process (DCTS, RTS_FF, state, Grant_L)
--begin
-- if (DCTS = '1' and RTS_FF = '1' and state /= IDLE and state /= North and state /=East and state /=West and
-- state /= South and Grant_L = '0' ) then
-- err_DCTS_RTS_FF_state_Grant_L <= '1';
-- else
-- err_DCTS_RTS_FF_state_Grant_L <= '0';
-- end if;
--end process;
--process (DCTS, RTS_FF, state, Grant_N)
--begin
-- if (DCTS = '1' and RTS_FF = '1' and state = North and Grant_N = '0' ) then
-- err_DCTS_RTS_FF_state_Grant_N <= '1';
-- else
-- err_DCTS_RTS_FF_state_Grant_N <= '0';
-- end if;
--end process;
--process (DCTS, RTS_FF, state, Grant_E)
--begin
-- if (DCTS = '1' and RTS_FF = '1' and state = East and Grant_E = '0' ) then
-- err_DCTS_RTS_FF_state_Grant_E <= '1';
-- else
-- err_DCTS_RTS_FF_state_Grant_E <= '0';
-- end if;
--end process;
--process (DCTS, RTS_FF, state, Grant_W)
--begin
-- if (DCTS = '1' and RTS_FF = '1' and state = West and Grant_W = '0' ) then
-- err_DCTS_RTS_FF_state_Grant_W <= '1';
-- else
-- err_DCTS_RTS_FF_state_Grant_W <= '0';
-- end if;
--end process;
--process (DCTS, RTS_FF, state, Grant_S)
--begin
-- if (DCTS = '1' and RTS_FF = '1' and state = South and Grant_S = '0' ) then
-- err_DCTS_RTS_FF_state_Grant_S <= '1';
-- else
-- err_DCTS_RTS_FF_state_Grant_S <= '0';
-- end if;
--end process;
process (state, Xbar_sel)
begin
if (state = North and Xbar_sel /= "00001" ) then
err_state_north_xbar_sel <= '1';
else
err_state_north_xbar_sel <= '0';
end if;
end process;
process (state, Xbar_sel)
begin
if (state = East and Xbar_sel /= "00010" ) then
err_state_east_xbar_sel <= '1';
else
err_state_east_xbar_sel <= '0';
end if;
end process;
process (state, Xbar_sel)
begin
if (state = West and Xbar_sel /= "00100" ) then
err_state_west_xbar_sel <= '1';
else
err_state_west_xbar_sel <= '0';
end if;
end process;
process (state, Xbar_sel)
begin
if (state = South and Xbar_sel /= "01000" ) then
err_state_south_xbar_sel <= '1';
else
err_state_south_xbar_sel <= '0';
end if;
end process;
--process (state, Xbar_sel)
--begin
-- if (state /= IDLE and state /= North and state /= East and state /= West and state /= South and Xbar_sel /= "10000" ) then
-- err_state_local_xbar_sel <= '1';
-- else
-- err_state_local_xbar_sel <= '0';
-- end if;
--end process;
end behavior; | gpl-3.0 | f72141878159fa1a25c6d92e88fe605b | 0.497478 | 2.878833 | false | false | false | false |
JarrettR/FPGA-Cryptoparty | FPGA/hdl/sim_hmac.vhd | 1 | 5,269 | --------------------------------------------------------------------------------
-- sim_ztex.vhd
-- Simulation testbench for ztex_wrapper
-- Copyright (C) 2016 Jarrett Rainier
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sha1_pkg.all;
library std;
use std.textio.all;
entity sim_hmac is
end sim_hmac;
architecture SIM of sim_hmac is
component hmac_main is
port(
clk_i : in std_ulogic;
rst_i : in std_ulogic;
secret_i : in w_input;
value_i : in w_input;
value_len_i : in std_ulogic_vector(0 to 63);
load_i : in std_ulogic;
dat_o : out w_output;
valid_o : out std_ulogic
);
end component;
signal i: integer range 0 to 65535;
signal rst_i: std_ulogic := '0';
signal clk_i: std_ulogic := '0';
signal load: std_ulogic := '0';
signal valid: std_ulogic;
signal secret: w_input;
signal value: w_input;
signal value_len: std_ulogic_vector(0 to 63) := X"0000000000000258";
signal dat_o: w_output;
constant clock_period : time := 1 ps;
begin
hmac1: hmac_main port map (clk_i,rst_i, secret, value, value_len, load, dat_o, valid);
stim_proc: process
begin
rst_i <= '0';
i <= 0;
load <= '0';
-- secret(0) <= X"4A656665"; --Jefe
-- secret(1) <= X"00000000";
-- secret(2) <= X"00000000";
-- secret(3) <= X"00000000";
-- secret(4) <= X"00000000";
-- secret(5) <= X"00000000";
-- secret(6) <= X"00000000";
-- secret(7) <= X"00000000";
-- secret(8) <= X"00000000";
-- secret(9) <= X"00000000";
-- secret(10) <= X"00000000";
-- secret(11) <= X"00000000";
-- secret(12) <= X"00000000";
-- secret(13) <= X"00000000";
-- secret(14) <= X"00000000";
-- secret(15) <= X"00000000";
-- --what do ya want for nothing?
-- value(0) <= X"77686174";
-- value(1) <= X"20646F20";
-- value(2) <= X"79612077";
-- value(3) <= X"616E7420";
-- value(4) <= X"666F7220";
-- value(5) <= X"6E6F7468";
-- value(6) <= X"696E673F";
-- value(7) <= X"80000000";
-- value(8) <= X"00000000";
-- value(9) <= X"00000000";
-- value(10) <= X"00000000";
-- value(11) <= X"00000000";
-- value(12) <= X"00000000";
-- value(13) <= X"00000000";
-- value(14) <= X"00000000";
-- value(15) <= X"00000000";
secret(0) <= X"64696374"; --Jefe
secret(1) <= X"696F6E61";
secret(2) <= X"72790000";
secret(3) <= X"00000000";
secret(4) <= X"00000000";
secret(5) <= X"00000000";
secret(6) <= X"00000000";
secret(7) <= X"00000000";
secret(8) <= X"00000000";
secret(9) <= X"00000000";
secret(10) <= X"00000000";
secret(11) <= X"00000000";
secret(12) <= X"00000000";
secret(13) <= X"00000000";
secret(14) <= X"00000000";
secret(15) <= X"00000000";
--what do ya want for nothing?
value(0) <= X"6C696E6B";
value(1) <= X"73797300";
value(2) <= X"00000280";
value(3) <= X"00000000";
value(4) <= X"00000000";
value(5) <= X"00000000";
value(6) <= X"00000000";
value(7) <= X"00000000";
value(8) <= X"00000000";
value(9) <= X"00000000";
value(10) <= X"00000000";
value(11) <= X"00000000";
value(12) <= X"00000000";
value(13) <= X"00000000";
value(14) <= X"00000000";
value(15) <= X"00000000";
wait until rising_edge(clk_i);
rst_i <= '1';
wait until rising_edge(clk_i);
rst_i <= '0';
wait until rising_edge(clk_i);
load <= '1';
wait until rising_edge(clk_i);
load <= '0';
wait until rising_edge(clk_i);
while valid = '0' loop
i <= i + 1;
wait until rising_edge(clk_i);
end loop;
wait;
end process;
--ssid_dat <= ssid_data(handshake_dat(0 to 35)); --36
clock_process: process
begin
clk_i <= '0';
wait for clock_period/2;
clk_i <= '1';
wait for clock_period/2;
end process;
end SIM; | gpl-3.0 | 47f93694096cf9cf653029fbe9271e5e | 0.492693 | 3.448298 | false | false | false | false |
JarrettR/FPGA-Cryptoparty | FPGA/hdl/sha1_scheduler.vhd | 1 | 7,784 | --------------------------------------------------------------------------------
-- Scheduler for running 5 concurrent SHA1 calcs and outputting sequentially
-- Copyright (C) 2016 Jarrett Rainier
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.sha1_pkg.all;
entity sha1_scheduler is
port(
clk_i : in std_ulogic;
load_i : in std_ulogic;
rst_i : in std_ulogic;
dat_i : in std_ulogic_vector(0 to 31);
sot_in : in std_ulogic;
dat_o : out std_ulogic_vector(0 to 31)
);
end sha1_scheduler;
architecture RTL of sha1_scheduler is
component sha1_load
port (
clk_i : in std_ulogic;
rst_i : in std_ulogic;
dat_i : in std_ulogic_vector(0 to 31);
sot_in : in std_ulogic;
dat_w_o : out w_input
);
end component;
component sha1_process_input
port (
clk_i : in std_ulogic;
rst_i : in std_ulogic;
dat_i : in w_input;
load_i : in std_ulogic;
dat_w_o : out w_full;
valid_o : out std_ulogic
);
end component;
component sha1_process_buffer
port (
clk_i : in std_ulogic;
rst_i : in std_ulogic;
dat_i : in w_full;
load_i : in std_ulogic;
new_i : in std_ulogic;
dat_w_i : in w_output;
dat_w_o : out w_output;
valid_o : out std_ulogic
);
end component;
signal w_load: w_input;
signal w_processed_input1: w_full;
signal w_processed_input2: w_full;
signal w_processed_input3: w_full;
signal w_processed_input4: w_full;
signal w_processed_input5: w_full;
signal w_processed_new: std_ulogic;
signal w_processed_buffer: w_output;
signal w_processed_buffer1: w_output;
signal w_processed_buffer2: w_output;
signal w_processed_buffer3: w_output;
signal w_processed_buffer4: w_output;
signal w_processed_buffer5: w_output;
signal w_buffer_valid1: std_ulogic;
signal w_buffer_valid2: std_ulogic;
signal w_buffer_valid3: std_ulogic;
signal w_buffer_valid4: std_ulogic;
signal w_buffer_valid5: std_ulogic;
signal w_pinput: w_input;
signal latch_pinput: std_ulogic_vector(0 to 4);
signal w_processed_valid: std_ulogic_vector(0 to 4);
signal i : integer range 0 to 16;
signal i_mux : integer range 0 to 4;
-- synthesis translate_off
signal test_sha1_process_input_o : std_ulogic_vector(0 to 31);
signal test_sha1_process_buffer0_o : std_ulogic_vector(0 to 31);
signal test_sha1_process_buffer_o : std_ulogic_vector(0 to 31);
signal test_sha1_load_o : std_ulogic_vector(0 to 31);
-- synthesis translate_on
begin
LOAD1: sha1_load port map (clk_i,rst_i,dat_i,sot_in,w_load);
--Alt: Use a generate statement
PINPUT1: sha1_process_input port map (clk_i,rst_i,w_pinput,latch_pinput(0),w_processed_input1,w_processed_valid(0));
PBUFFER1: sha1_process_buffer port map (clk_i,rst_i,w_processed_input1,w_processed_valid(0),w_processed_valid(0),w_processed_buffer1,w_processed_buffer1,w_buffer_valid1);
PINPUT2: sha1_process_input port map (clk_i,rst_i,w_pinput,latch_pinput(1),w_processed_input2,w_processed_valid(1));
PBUFFER2: sha1_process_buffer port map (clk_i,rst_i,w_processed_input2,w_processed_valid(1),w_processed_valid(1),w_processed_buffer2,w_processed_buffer2,w_buffer_valid2);
PINPUT3: sha1_process_input port map (clk_i,rst_i,w_pinput,latch_pinput(2),w_processed_input3,w_processed_valid(2));
PBUFFER3: sha1_process_buffer port map (clk_i,rst_i,w_processed_input3,w_processed_valid(2),w_processed_valid(2),w_processed_buffer3,w_processed_buffer3,w_buffer_valid3);
PINPUT4: sha1_process_input port map (clk_i,rst_i,w_pinput,latch_pinput(3),w_processed_input4,w_processed_valid(3));
PBUFFER4: sha1_process_buffer port map (clk_i,rst_i,w_processed_input4,w_processed_valid(3),w_processed_valid(3),w_processed_buffer4,w_processed_buffer4,w_buffer_valid4);
PINPUT5: sha1_process_input port map (clk_i,rst_i,w_pinput,latch_pinput(4),w_processed_input5,w_processed_valid(4));
PBUFFER5: sha1_process_buffer port map (clk_i,rst_i,w_processed_input5,w_processed_valid(4),w_processed_valid(4),w_processed_buffer5,w_processed_buffer5,w_buffer_valid5);
process(clk_i)
begin
if (clk_i'event and clk_i = '1') then
if rst_i = '1' then
latch_pinput <= "00000";
i <= 0;
--Todo: start from 0 after testing
i_mux <= 0;
for x in 0 to 15 loop
w_pinput(x) <= "00000000000000000000000000000000";
end loop;
else
if i = 15 then
case i_mux is
when 0 => latch_pinput <= "10000";
when 1 => latch_pinput <= "01000";
when 2 => latch_pinput <= "00100";
when 3 => latch_pinput <= "00010";
when 4 => latch_pinput <= "00001";
end case;
w_pinput <= w_load;
i <= 0;
--i <= i + 1;
if i_mux = 4 then
i_mux <= 0;
else
i_mux <= i_mux + 1;
end if;
else
latch_pinput <= "00000";
i <= i + 1;
end if;
end if;
--Alt: Consider other conditionals
if w_processed_valid(0) = '1' then
w_processed_buffer <= w_processed_buffer1;
elsif w_processed_valid(1) = '1' then
w_processed_buffer <= w_processed_buffer2;
elsif w_processed_valid(2) = '1' then
w_processed_buffer <= w_processed_buffer3;
elsif w_processed_valid(3) = '1' then
w_processed_buffer <= w_processed_buffer4;
elsif w_processed_valid(4) = '1' then
w_processed_buffer <= w_processed_buffer5;
end if;
end if;
end process;
dat_1_o <= w_pinput(15);
-- synthesis translate_off
test_sha1_process_input_o <= w_processed_input1(16);
test_sha1_process_buffer0_o <= w_processed_buffer1(0);
test_sha1_process_buffer_o <= w_processed_buffer(0);
test_sha1_load_o <= w_load(15);
-- synthesis translate_on
end RTL; | gpl-3.0 | de2078479e67cfd22c9b84c04c8ed45b | 0.540211 | 3.613742 | false | false | false | false |
carlosrd/DAS | P6/pong.vhd | 1 | 17,339 | -------------------------------------------------------------------
--
-- Fichero:
-- damero.vhd 12/7/2013
--
-- (c) J.M. Mendias
-- Diseño Automático de Sistemas
-- Facultad de Informática. Universidad Complutense de Madrid
--
-- Propósito:
-- Muestra un damero sobre un monitor compatible VGA
--
-- Notas de diseño:
-- La sincronización con la pantalla VGA presupone que la
-- frecuencia de reloj del sistema es de 50 MHz
--
-------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
ENTITY pong IS
PORT (
rst: IN std_logic;
clk: IN std_logic;
ps2Data : IN std_logic;
ps2Clk : IN std_logic;
hSyncQ: OUT std_logic;
vSyncQ: OUT std_logic;
RGBQ: OUT std_logic_vector(8 DOWNTO 0);
altavoz: OUT std_logic
);
END pong;
ARCHITECTURE pongArch OF pong IS
signal pixelCntOut: std_logic_vector(10 downto 0);
signal lineCntOut: std_logic_vector(9 downto 0);
signal blanking, valor: std_logic;
-- SEÑALES PARA PINTAR
signal bordeArriba, bordeAbajo,redCentral: std_logic;
signal raquetaIzq,raquetaDcha, pelota : std_logic;
signal hSync, vSync : std_logic;
signal RGB : std_logic_vector(8 downto 0);
-- CONTADORES: RAQUETAS Y PELOTAS
signal csIzq, raquetaIzqTam: std_logic_vector(6 downto 0);
signal csDcha, raquetaDchaTam: std_logic_vector(6 downto 0);
-- CONTADORES: PELOTA
signal csPelotaY: std_logic_vector(6 downto 0);
signal csPelotaX: std_logic_vector(7 downto 0);
-- RALENTIZADOR
signal csRalentizador : std_logic_vector(22 downto 0);
signal mueve : std_logic;
-- VARIABLES DE JUEGO
signal hayGanador, partidaEnCurso, centrarPelota, centrarPelota_sig, partidaEnCurso_sig: std_logic;
-- VARIABLES SONIDO REBOTAR
signal csOscilador, csCiclosSonido : std_logic_vector(22 downto 0);
signal musica, sonido, sonidoRebotar : std_logic;
-- INTERFAZ TECLADO PS/2
signal data : std_logic_vector (7 DOWNTO 0); -- Salida de datos paralela
signal newData : std_logic; -- Indica la recepción de un nuevo dato por la línea PS2
signal newDataAck : std_logic; -- Reconoce la recepción del nuevo dato
signal ldData, validData, lastBitRcv, ps2ClkSync, ps2ClkFallingEdge: std_logic;
signal ps2DataRegOut: std_logic_vector(10 downto 0);
signal goodParity: std_logic;
-- FLAGS DE TECLAS PULSADAS
signal flagQ,flagA,flagP,flagL,flagSPC : std_logic;
signal flagQnext,flagAnext,flagPnext,flagLnext,flagSPCnext : std_logic;
-- MAQUINA DE ESTADOS PARA EL CONTROL DE TECLAS
type ESTADOS is (WAITING_PRESS, RELEASE_BUTTON);
signal ESTADO, SIG_ESTADO: ESTADOS;
-- MAQUINA DE ESTADOS PARA EL CONTROL DEL JUEGO
type GAME_STATES is (WAITING_SPACE, INITIALIZING_GAME, WAITING_WINNER);
signal GAME, NEXT_GAME: GAME_STATES;
BEGIN
pixelCnt:
PROCESS( rst, clk )
BEGIN
IF (rst='0') THEN
pixelCntOut <= (OTHERS=>'0');
ELSIF(clk'EVENT AND clk='1') THEN
IF (pixelCntOut=1588) THEN
pixelCntOut <= (OTHERS=>'0');
ELSE
pixelCntOut <= pixelCntOut+1;
END IF;
END IF;
END PROCESS pixelCnt;
lineCnt:
PROCESS( rst, clk )
BEGIN
IF (rst='0') THEN
lineCntOut <= (OTHERS=>'0');
ELSIF (clk'EVENT AND clk='1') THEN
IF (pixelCntOut=1588) THEN
IF (lineCntOut=527) THEN
lineCntOut <= (others=>'0');
ELSE
lineCntOut <= lineCntOut+1;
END IF;
END IF;
END IF;
END PROCESS lineCnt;
hSync <= '0' WHEN (pixelCntOut > 1304) AND (pixelCntOut <= 1493) ELSE '1';
vSync <= '0' WHEN (lineCntOut > 493) AND (lineCntOut <= 495) ELSE '1';
blanking <= '1' WHEN (pixelCntOut > 1257) OR (lineCntOut > 479) ELSE '0';
RGB <= valor & valor & valor & valor & valor & valor & valor & valor & valor;
-------------------------------------------------------------------------------------
-- INTRODUCIR CODIGO DESDE AQUI
-- | | | | |
-- v v v v v
-- COMO VA EL LINECOUNT PARA HACER LINEAS MAS GORDAS:
-- 0100
-- 0101
-- 0110
-- 0111
-- 1100 -> Hay que fijarse cuales son los bits comunes para ir
-- 1101 diviendo entre 2. (Con esto, son numeros modulo 2, 4, 8 .. etc)
-- 1110
-- 1111
-- PINTAR EL CAMPO DE JUEGO:
-- *******************************************************************************
-- ! : Si la linea a pintar es la linea 8, pondremos 7 porque empieza a contar desde el 0
-- El borde de arriba es de 3 pix de anchura y en la linea 8
bordeArriba <= '1' WHEN (lineCntOut(9 downto 2) = 7) ELSE '0';
-- El borde de abajo es de 3 px de anchura y esta en la linea 111 = 8 + 1 + 102 + 1
bordeAbajo <= '1' WHEN (lineCntOut(9 downto 2) = 111) ELSE '0';
-- La red central se pinta en la columna 75 = (8 + 1 + 67) y para el tamaño de alternar (es discontinua) usamos el 5 bit del lineCount.
-- Despues aseguramos que se pinta entre los bordes arriba y abajo
redCentral <= '1' WHEN (pixelCntOut(10 downto 3) = 75) AND (lineCntOut(5) = '1') AND (lineCntOut(9 downto 2) > 7) AND (lineCntOut(9 downto 2) < 111) ELSE '0';
-- PINTAR RAQUETAS
-- *******************************************************************************
contRaquetaIzq:
process( clk, rst , flagQ, flagA, csIzq, mueve)
begin
if rst = '0' then
csIzq <= conv_std_logic_vector( 51 , 7 ); -- Situar la raqueta centrada
elsif clk'event and clk = '1' then
if mueve = '1' then
if flagQ = '1' and csIzq > 7 then
csIzq <= csIzq - 1;
elsif flagA = '1' and csIzq < 95 then
csIzq <= csIzq + 1;
end if;
end if;
end if;
end process;
-- La raqueta izquierda tiene un tamaño de 16 px y esta en la columna 9. Las lineas se pintan entre el valor del contador y el del tamaño
raquetaIzqTam <= csIzq + 16;
raquetaIzq <= '1' WHEN (pixelCntOut(10 downto 3) = 8) AND (lineCntOut(9 downto 2) > csIzq) AND (lineCntOut(9 downto 2) < raquetaIzqTam) ELSE '0';
contRaquetaDcha:
process( clk, rst, flagP, flagL, csDcha, mueve)
begin
if rst = '0' then
csDcha <= conv_std_logic_vector( 51 , 7 ); -- Situar la raqueta centrada
elsif clk'event and clk = '1' then
if mueve = '1' then
if flagP = '1' and csDcha > 7 then
csDcha <= csDcha - 1;
elsif flagL = '1' and csDcha < 95 then
csDcha <= csDcha + 1;
end if;
end if;
end if;
end process;
-- La raqueta derecha tiene un tamaño de 16 px y esta en la columna 145. Las lineas se pintan entre el valor del contador y el del tamaño
raquetaDchaTam <= csDcha + 16;
raquetaDcha <= '1' WHEN (pixelCntOut(10 downto 3) = 144) AND (lineCntOut(9 downto 2) > csDcha) AND (lineCntOut(9 downto 2) < raquetaDchaTam) ELSE '0';
-- PINTAR PELOTA
-- *******************************************************************************
pelotaEjeY:
process( clk, rst , csPelotaY, mueve, centrarPelota)
variable arriba : std_logic;
begin
if rst = '0' then
csPelotaY <= conv_std_logic_vector( 59 , 7 ); -- Centro de la pantalla (7 bits)
arriba := '1';
elsif clk'event and clk='1' then
if centrarPelota = '1' then
csPelotaY <= conv_std_logic_vector( 59 , 7 );
elsif mueve = '1' then
-- Rebotar si choca contra los bordes
if csPelotaY = 7 or csPelotaY = 111 then
arriba := not arriba;
end if;
-- Mover la pelota
if arriba = '1' then
csPelotaY <= csPelotaY - 1;
else
csPelotaY <= csPelotaY + 1;
end if;
end if;
end if;
end process;
pelotaEjeX:
process( clk, rst, csPelotaX, mueve, centrarPelota)
variable izquierda : std_logic;
begin
if rst = '0' then
csPelotaX <= conv_std_logic_vector( 76 , 8 ); -- Cento de la pantalla (8 Bits)
izquierda := '1';
hayGanador <= '0';
elsif clk'event and clk='1' then
if centrarPelota = '1' then
csPelotaX <= conv_std_logic_vector( 76 , 8 );
hayGanador <= '0';
elsif mueve = '1' then
-- Rebotar si choca contra la raqueta izquierda o la derecha
if (csPelotaX = 8 and csIzq < csPelotaY and csPelotaY < raquetaIzqTam) or (csPelotaX = 144 and csDcha < csPelotaY and csPelotaY < raquetaDchaTam) then
izquierda := not izquierda;
sonidoRebotar <= '1';
else
sonidoRebotar <= '0';
end if;
-- Si se salio del campo es que marcaron un tanto
if (csPelotaX = 1 or csPelotaX = 152) then
hayGanador <= '1';
end if;
-- Mover la pelota
if izquierda = '1' then
csPelotaX <= csPelotaX - 1;
else
csPelotaX <= csPelotaX + 1;
end if;
end if;
end if;
end process;
-- La pelota se pinta donde marquen los contadores de los ejes X e Y
pelota <= '1' WHEN (pixelCntOut(10 downto 3) = csPelotaX) AND (lineCntOut(9 downto 2) = csPelotaY) ELSE '0';
-- RALENTIZADOR DE MOVIMIENTO: Evita que las raquetas o la pelota se muevan demasiado deprisa por la pantalla
-- *******************************************************************************
ralentizador:
process( clk, rst, csRalentizador, partidaEnCurso)
begin
if rst = '0' then
mueve <= '0';
csRalentizador <= conv_std_logic_vector( 0, 23 );
elsif clk'event and clk = '1' then
if partidaEnCurso = '1' then
if csRalentizador = 1000000 then
mueve <= '1';
csRalentizador <= conv_std_logic_vector( 0, 23 );
else
csRalentizador <= csRalentizador + 1;
mueve <= '0';
end if;
end if;
end if;
end process;
-- SONIDO REBOTAR
-- *******************************************************************************
-- Oscilador que continuamente emite un DO
oscilador:
process( clk, rst )
begin
if rst = '0' then
csOscilador <= conv_std_logic_vector( 0 , 17 );
musica <= '0';
elsif clk'event and clk = '1' then
if csOscilador = "10111010101001110" then
csOscilador <= conv_std_logic_vector( 0 , 17 );
musica <= not (musica);
elsif csOscilador = conv_std_logic_vector( 95566 , 17 ) then
csOscilador <= conv_std_logic_vector( 0 , 17 );
else
csOscilador <= csOscilador + 1;
end if;
end if;
end process;
-- El sonido de rebotar debe sonar durante un breve tiempo
ciclosSonidoReboteCnt:
process( clk, rst, csCiclosSonido, sonidoRebotar)
begin
if rst = '0' then
sonido <= '0';
csCiclosSonido <= conv_std_logic_vector( 0, 23 );
elsif clk'event and clk = '1' then
if sonidoRebotar = '1' then
csCiclosSonido <= conv_std_logic_vector( 0, 23 );
elsif csCiclosSonido = 5000000 then
sonido <= '0';
else
csCiclosSonido <= csCiclosSonido + 1;
sonido <= '1';
end if;
end if;
end process;
altavoz <= musica AND sonido;
-- RESULTADO FINAL EN MONITOR VGA
-- *******************************************************************************
valor <= (bordeArriba OR bordeAbajo OR redCentral OR raquetaIzq OR raquetaDcha OR pelota) AND NOT blanking;
process(clk)
begin
if rst = '0' then
hSyncQ <= '0';
vSyncQ <= '0';
RGBQ <= "000000000";
elsif clk'event and clk = '1' then
hSyncQ <= hSync;
vSyncQ <= vSync;
RGBQ <= RGB;
end if;
end process;
-- INTERFAZ TECLADO PS/2
-- *******************************************************************************************
synchronizer:
PROCESS (rst, clk)
VARIABLE aux1: std_logic;
BEGIN
IF (rst='0') THEN
aux1 := '1';
ps2ClkSync <= '1';
ELSIF (clk'EVENT AND clk='1') THEN
ps2ClkSync <= aux1;
aux1 := ps2Clk;
END IF;
END PROCESS synchronizer;
edgeDetector:
PROCESS (rst, clk)
VARIABLE aux1, aux2: std_logic;
BEGIN
ps2ClkFallingEdge <= (NOT aux1) AND aux2;
IF (rst='0') THEN
aux1 := '1';
aux2 := '1';
ELSIF (clk'EVENT AND clk='1') THEN
aux2 := aux1;
aux1 := ps2ClkSync;
END IF;
END PROCESS edgeDetector;
ps2DataReg:
PROCESS (rst, clk)
BEGIN
IF (rst='0') THEN
ps2DataRegOut <= (OTHERS =>'1');
ELSIF (clk'EVENT AND clk='1') THEN
IF (lastBitRcv='1') THEN
ps2DataRegOut <= (OTHERS=>'1');
ELSIF (ps2ClkFallingEdge='1') THEN
ps2DataRegOut <= ps2Data & ps2DataRegOut(10 downto 1);
END IF;
END IF;
END PROCESS ps2DataReg;
oddParityCheker:
goodParity <=
((ps2DataRegOut(9) XOR ps2DataRegOut(8)) XOR (ps2DataRegOut(7) XOR ps2DataRegOut(6)))
XOR ((ps2DataRegOut(5) XOR ps2DataRegOut(4)) XOR (ps2DataRegOut(3) XOR ps2DataRegOut(2)))
XOR ps2DataRegOut(1);
lastBitRcv <= NOT ps2DataRegOut(0);
validData <= lastBitRcv AND goodParity;
dataReg:
PROCESS (rst, clk)
BEGIN
IF (rst='0') THEN
data <= (OTHERS=>'0');
ELSIF (clk'EVENT AND clk='1') THEN
IF (ldData='1') THEN
data <= ps2DataRegOut(8 downto 1);
END IF;
END IF;
END PROCESS dataReg;
controller:
PROCESS (validData, rst, clk)
TYPE states IS (waitingData, waitingNewDataAck);
VARIABLE state: states;
BEGIN
ldData <= '0';
newData <= '0';
CASE state IS
WHEN waitingData =>
IF (validData='1') THEN
ldData <= '1';
END IF;
WHEN waitingNewDataAck =>
newData <= '1';
WHEN OTHERS => NULL;
END CASE;
IF (rst='0') THEN
state := waitingData;
ELSIF (clk'EVENT AND clk='1') THEN
CASE state IS
WHEN waitingData =>
IF (validData='1') THEN
state := waitingNewDataAck;
END IF;
WHEN waitingNewDataAck =>
IF (newDataAck='1') THEN
state := waitingData;
END IF;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS controller;
-- MAQUINA DE ESTADOS PARA DETECCION DE TECLAS (TECLADO PS/2)
-- *******************************************************************************************
-- MAQUINA ESTADOS: SINCRONO
maqestadosSyn:
process(clk,rst)
begin
if rst ='0' then
flagQ <= '0';
flagA <= '0';
flagP <= '0';
flagL <= '0';
flagSPC <= '0';
ESTADO <= WAITING_PRESS;
elsif clk'event and clk='1' then
flagQ <= flagQnext;
flagA <= flagAnext;
flagP <= flagPnext;
flagL <= flagLnext;
flagSPC <= flagSPCnext;
ESTADO <= SIG_ESTADO;
end if;
end process;
-- MAQUINA ESTADOS: COMBINACIONAL
maqestadosComb:
process(ESTADO,rst,newData,data)
begin
flagQnext <= flagQ;
flagAnext <= flagA;
flagPnext <= flagP;
flagLnext <= flagL;
flagSPCnext <= flagSPC;
SIG_ESTADO <= ESTADO;
case ESTADO is
when WAITING_PRESS =>
newDataAck <= '1';
if newData = '1' then
case data is
when "11110000" => SIG_ESTADO <= RELEASE_BUTTON; -- Si es F0, es una liberacion de tecla
when "00010101" => flagQnext <= '1'; -- Si es Q = 15 (hex), activamos flag de Q
when "00011100" => flagAnext <= '1'; -- Si es A = 1C (hex), activamos flag de A
when "01001101" => flagPnext <= '1'; -- Si es P = 4D (hex), activamos flag de P
when "01001011" => flagLnext <= '1'; -- Si es L = 4B (hex), activamos flag de L
when "00101001" => flagSPCnext <= '1'; -- Si es SPACE = 29 (hex), activamos flag de SPACE
when others => SIG_ESTADO <= WAITING_PRESS;
end case;
end if;
when RELEASE_BUTTON =>
newDataAck <= '1';
if newData = '1' then
case data is
when "00010101" => flagQnext <= '0'; -- Si es Q = 15 (hex), desactivamos flag de Q
when "00011100" => flagAnext <= '0'; -- Si es A = 1C (hex), desactivamos flag de A
when "01001101" => flagPnext <= '0'; -- Si es P = 4D (hex), desactivamos flag de P
when "01001011" => flagLnext <= '0'; -- Si es L = 4B (hex), desactivamos flag de L
when "00101001" => flagSPCnext <= '0'; -- Si es SPACE = 29 (hex), desactivamos flag de SPACE
when others => SIG_ESTADO <= WAITING_PRESS;
end case;
SIG_ESTADO <= WAITING_PRESS;
end if;
end case;
end process;
-- MAQUINA DE ESTADOS PARA EL JUEGO
-- *******************************************************************************************
-- MAQUINA ESTADOS: SINCRONO
maqEstadosJuegoSyn:
process(clk,rst)
begin
if rst ='0' then
--hayGanador <= '0';
GAME <= WAITING_SPACE;
centrarPelota <= '0';
partidaEnCurso <= '0';
elsif clk'event and clk='1' then
GAME <= NEXT_GAME;
partidaEnCurso <= partidaEnCurso_sig;
centrarPelota <= centrarPelota_sig;
end if;
end process;
-- MAQUINA ESTADOS: COMBINACIONAL
maqEstadosJuegoComb:
process(GAME,rst,newData,data,flagSPC,hayGanador)
begin
NEXT_GAME <= GAME;
partidaEnCurso_sig <= partidaEnCurso;
centrarPelota_sig <= centrarPelota;
case GAME is
when WAITING_SPACE =>
partidaEnCurso_sig <= '0';
centrarPelota_sig <= '0';
if flagSPC = '1' then
NEXT_GAME <= INITIALIZING_GAME;
end if;
when INITIALIZING_GAME =>
--partidaEnCurso_sig <= '0';
centrarPelota_sig <= '1';
NEXT_GAME <= WAITING_WINNER;
when WAITING_WINNER =>
partidaEnCurso_sig <= '1';
centrarPelota_sig <= '0';
if hayGanador = '1'then
NEXT_GAME <= WAITING_SPACE;
end if;
end case;
end process;
END pongArch;
| mit | c7e5dc16ee201f827b7ab54fd12b92ec | 0.582733 | 3.390497 | false | false | false | false |
TanND/Electronic | VHDL/nt_ss.vhd | 1 | 486 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity nt_ss is
port(
clk : in STD_LOGIC;
SI : in bit;
PO : out bit_VECTOR(7 downto 0)
);
end nt_ss;
--}} End of automatically maintained section
architecture nt_ss of nt_ss is
signal tmp:bit_vector(7 downto 0);
begin
process (clk)
begin
if (clk'event and clk='1') then
tmp <= tmp(6 downto 0)& SI;
end if;
PO <= tmp;
end process;
end nt_ss;
--clk=20Mhz; SI= random | apache-2.0 | 266d8ee77fd6d8e9d960e802169097e9 | 0.582305 | 3.155844 | false | false | false | false |
lnls-dig/dsp-cores | hdl/testbench/cic/wb_bpm_swap/bpm_swap/swmode_sel.vhd | 1 | 2,660 | ------------------------------------------------------------------------------
-- Title : BPM RF channels swapping and de-swapping mode selector
------------------------------------------------------------------------------
-- Author : Jose Alvim Berkenbrock
-- Company : CNPEM LNLS-DIG
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Select among distinct swapping and de-swapping modes affecting
-- how the swap master clock is propagated to the swap and de-swap
-- output signals.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.swap_pkg.all;
entity swmode_sel is
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
en_i : in std_logic := '1';
-- Swap master clock
clk_swap_i : in std_logic;
-- Swap and de-swap signals
swap_o : out std_logic;
deswap_o : out std_logic;
-- Swap mode setting
swap_mode_i : in t_swap_mode
);
end swmode_sel;
architecture rtl of swmode_sel is
signal swap : std_logic;
signal deswap : std_logic;
begin
p_swap_mode : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
swap <= '0';
deswap <= '0';
else
if en_i = '1' then
case swap_mode_i is
when c_swmode_swap_deswap =>
if clk_swap_i = '1' then
swap <= '1';
deswap <= '1';
else
swap <= '0';
deswap <= '0';
end if;
when c_swmode_static_direct =>
swap <= '0';
deswap <= '0';
when c_swmode_static_inverted =>
swap <= '1';
deswap <= '0';
when c_swmode_rffe_swap =>
if clk_swap_i = '1' then
swap <= '1';
else
swap <= '0';
end if;
deswap <= '0';
when others =>
swap <= '0';
deswap <= '0';
end case;
end if;
end if;
end if;
end process p_swap_mode;
swap_o <= swap;
deswap_o <= deswap;
end rtl;
| lgpl-3.0 | 2ee4e9054787ed69c1681215459d4d99 | 0.395489 | 4.500846 | false | false | false | false |
bruskajp/EE-316 | Project4/Vivado_NexysBoard/craddockEE316/craddockEE316.srcs/sources_1/ip/sig1dualRAM/misc/blk_mem_gen_v8_3.vhd | 4 | 8,325 | library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_3 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_3;
architecture xilinx of blk_mem_gen_v8_3_3 is
begin
end
architecture xilinx;
| gpl-3.0 | 42a2ec400d2ff3468119666413eebdd3 | 0.42967 | 3.611714 | false | false | false | false |
SoCdesign/EHA | RTL/Fault_Management/Fault_management_network/xbar_LV.vhd | 1 | 1,011 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity XBAR_LV is
generic (
DATA_WIDTH: integer := 11
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end;
architecture behavior of XBAR_LV is
begin
process(sel, North_in, East_in, West_in, South_in, Local_in) begin
case(sel) is
when "00001" =>
Data_out <= Local_in;
when "00010" =>
Data_out <= South_in;
when "00100" =>
Data_out <= West_in;
when "01000" =>
Data_out <= East_in;
when others =>
Data_out <= North_in;
end case;
end process;
end; | gpl-3.0 | 072d7f5decd816a6cc35248e2b96240b | 0.598417 | 3.110769 | false | false | false | false |
TanND/Electronic | VHDL/D9_C2.vhd | 1 | 1,293 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D9_C2 is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR(9 downto 0)
);
end D9_C2;
architecture D9_C2 of D9_C2 is
begin
process(rst,clk)
variable dem:integer range 0 to 9;
begin
if (rst='1') then dem:=0;
elsif (rising_edge(clk)) then
if (dem=8) then dem:=0;
else dem:=dem+1;
end if;
end if;
case dem is
when 0 => seg<= "0000000001";
when 1 => seg<= "0000000010";
when 2 => seg<= "0000000100";
when 3 => seg<= "0000001000";
when 4 => seg<= "0000010000";
when 5 => seg<= "0000100000";
when 6 => seg<= "0001000000";
when 7 => seg<= "0010000000";
when 8 => seg<= "0100000000";
when 9 => seg<= "1000000000";
when others =>NULL;
end case;
end process;
end D9_C2;
-- rst= 100Khz; clk=10Mhz; | apache-2.0 | a1b65e47e8de49e434675fb9e5aa446c | 0.385924 | 4.324415 | false | false | false | false |
SoCdesign/EHA | RTL/Fault_Management/Fault_management_network/packetizer_LV.vhd | 1 | 6,295 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
entity PACKETIZER_LV is
generic (
DATA_WIDTH: integer := 11;
current_address : integer := 0;
SHMU_address : integer := 0
);
port (
reset, clk: in std_logic;
faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L: in std_logic;
healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L: in std_logic;
credit_in_LV: in std_logic;
valid_out_LV : out std_logic;
TX_LV: out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end;
architecture behavior of PACKETIZER_LV is
signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(2 downto 0);
signal credit_counter_in, credit_counter_out: std_logic_vector(1 downto 0);
type STATE_TYPE IS (IDLE, HEADER_FLIT, BODY_FLIT, TAIL_FLIT);
signal state, state_in : STATE_TYPE := IDLE;
signal FIFO_MEM_1, FIFO_MEM_1_in : std_logic_vector(9 downto 0);
signal FIFO_MEM_2, FIFO_MEM_2_in : std_logic_vector(9 downto 0);
signal FIFO_MEM_3, FIFO_MEM_3_in : std_logic_vector(9 downto 0);
signal FIFO_Data_out: std_logic_vector(9 downto 0);
signal grant, all_input_signals: std_logic;
begin
process (clk, reset)begin
if reset = '0' then
FIFO_MEM_1 <= (others=>'0');
FIFO_MEM_2 <= (others=>'0');
FIFO_MEM_3 <= (others=>'0');
read_pointer <= "001";
write_pointer <= "001";
credit_counter_out<="01";
state<=IDLE;
elsif clk'event and clk = '1' then
if all_input_signals = '1' then
FIFO_MEM_1 <= FIFO_MEM_1_in;
FIFO_MEM_2 <= FIFO_MEM_2_in;
FIFO_MEM_3 <= FIFO_MEM_3_in;
end if;
read_pointer <= read_pointer_in;
write_pointer <= write_pointer_in;
credit_counter_out <= credit_counter_in;
state <= state_in;
end if;
end process;
all_input_signals <= faulty_packet_N or faulty_packet_E or faulty_packet_W or faulty_packet_S or faulty_packet_L or healthy_packet_N or healthy_packet_E or healthy_packet_W or healthy_packet_S or healthy_packet_L;
--all_input_signals <= faulty_packet_N or faulty_packet_E or faulty_packet_W or faulty_packet_S or faulty_packet_L or healthy_packet_N;
process(all_input_signals)begin
if all_input_signals = '1' then
write_pointer_in <= write_pointer(0) & write_pointer(2 downto 1);
else
write_pointer_in <= write_pointer;
end if;
end process;
process(faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L, healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L, write_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3)begin
case( write_pointer ) is
when "001" => FIFO_MEM_1_in <= faulty_packet_N & faulty_packet_E & faulty_packet_W & faulty_packet_S & faulty_packet_L & healthy_packet_N & healthy_packet_E & healthy_packet_W & healthy_packet_S & healthy_packet_L; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3;
when "010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= faulty_packet_N & faulty_packet_E & faulty_packet_W & faulty_packet_S & faulty_packet_L & healthy_packet_N & healthy_packet_E & healthy_packet_W & healthy_packet_S & healthy_packet_L; FIFO_MEM_3_in <= FIFO_MEM_3;
when "100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= faulty_packet_N & faulty_packet_E & faulty_packet_W & faulty_packet_S & faulty_packet_L & healthy_packet_N & healthy_packet_E & healthy_packet_W & healthy_packet_S & healthy_packet_L;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3;
end case ;
end process;
process(read_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3) begin
case( read_pointer ) is
when "001" => FIFO_Data_out <= FIFO_MEM_1;
when "010" => FIFO_Data_out <= FIFO_MEM_2;
when "100" => FIFO_Data_out <= FIFO_MEM_3;
when others => FIFO_Data_out <= FIFO_MEM_1;
end case ;
end process;
process (credit_in_LV, credit_counter_out, grant)begin
credit_counter_in <= credit_counter_out;
if credit_in_LV = '1' and credit_counter_out < 1 then
credit_counter_in <= credit_counter_out + 1;
elsif grant = '1' then
credit_counter_in <= credit_counter_out - 1;
end if;
end process;
process(all_input_signals, state, read_pointer, credit_counter_out)
begin
TX_LV <= (others => '0');
grant<= '0';
case(state) is
when IDLE =>
if all_input_signals= '1' then
state_in <= HEADER_FLIT;
else
state_in <= IDLE;
end if;
read_pointer_in <= read_pointer;
when HEADER_FLIT =>
if credit_counter_out /= "00" then
grant <= '1';
TX_LV <= std_logic_vector(to_unsigned(current_address, 4)) & std_logic_vector(to_unsigned(SHMU_address, 4)) & "001";
state_in <= BODY_FLIT;
else
state_in <= HEADER_FLIT;
end if;
read_pointer_in <= read_pointer(0) & read_pointer(2 downto 1);
when BODY_FLIT =>
if credit_counter_out /= "00" then
grant <= '1';
TX_LV <= FIFO_Data_out(7 downto 0) & "010";
state_in <= TAIL_FLIT;
else
state_in <= BODY_FLIT;
end if;
when TAIL_FLIT =>
if credit_counter_out /= "00" then
grant <= '1';
TX_LV <= "000000" & FIFO_Data_out(9 downto 8) & "100";
state_in <= IDLE;
else
state_in <= TAIL_FLIT;
end if;
when others =>
state_in <= IDLE;
end case ;
end procesS;
valid_out_LV <= grant;
end; | gpl-3.0 | 4bf6de55116f1bc68be55b2fd615a1e1 | 0.572677 | 3.330688 | false | false | false | false |
SoCdesign/EHA | RTL/Hand_Shaking/Checkers/Modules_with_checkers_integrated/All_checkers/LBDR_with_checkers/LBDR_with_checkers.vhd | 1 | 8,387 | --Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR is
generic (
cur_addr_rst: integer := 5;
Rxy_rst: integer := 60;
Cx_rst: integer := 15;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic;
-- Checker outputs
err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in : out std_logic
);
end LBDR;
architecture behavior of LBDR is
signal Cx: std_logic_vector(3 downto 0);
signal Rxy: std_logic_vector(7 downto 0);
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal N1, E1, W1, S1 :std_logic := '0';
signal Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: std_logic;
signal Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: std_logic;
component LBDR_checkers is
generic (
cur_addr_rst: integer := 5;
NoC_size: integer := 4
);
port ( empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic;
N1_out, E1_out, W1_out, S1_out: in std_logic;
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
-- Checker outputs
err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in : out std_logic
);
end component;
begin
Cx <= std_logic_vector(to_unsigned(Cx_rst, Cx'length));
Rxy <= std_logic_vector(to_unsigned(Rxy_rst, Rxy'length));
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
N1 <= '1' when dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) else '0';
E1 <= '1' when cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) else '0';
W1 <= '1' when dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) else '0';
S1 <= '1' when cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) else '0';
LBDRCHECKERS: LBDR_checkers generic map (cur_addr_rst => cur_addr_rst, NoC_size => NoC_size)
port map (
empty => empty,
flit_type => flit_type,
Req_N_FF => Req_N_FF,
Req_E_FF => Req_E_FF,
Req_W_FF => Req_W_FF,
Req_S_FF => Req_S_FF,
Req_L_FF => Req_L_FF,
Req_N_in => Req_N_in,
Req_E_in => Req_E_in,
Req_W_in => Req_W_in,
Req_S_in => Req_S_in,
Req_L_in => Req_L_in,
N1_out => N1,
E1_out => E1,
W1_out => W1,
S1_out => S1,
dst_addr => dst_addr,
err_header_not_empty_Requests_in_onehot => err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in => err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in => err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => err_header_not_empty_Req_S_in
);
process(clk, reset)
begin
if reset = '0' then
Req_N_FF <= '0';
Req_E_FF <= '0';
Req_W_FF <= '0';
Req_S_FF <= '0';
Req_L_FF <= '0';
elsif clk'event and clk = '1' then
Req_N_FF <= Req_N_in;
Req_E_FF <= Req_E_in;
Req_W_FF <= Req_W_in;
Req_S_FF <= Req_S_in;
Req_L_FF <= Req_L_in;
end if;
end process;
-- The combionational part
Req_N <= Req_N_FF;
Req_E <= Req_E_FF;
Req_W <= Req_W_FF;
Req_S <= Req_S_FF;
Req_L <= Req_L_FF;
process(N1, E1, W1, S1, Rxy, Cx, flit_type, empty, Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF) begin
if flit_type = "001" and empty = '0' then
Req_N_in <= ((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0);
Req_E_in <= ((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1);
Req_W_in <= ((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2);
Req_S_in <= ((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3);
Req_L_in <= not N1 and not E1 and not W1 and not S1;
elsif flit_type = "100" then
Req_N_in <= '0';
Req_E_in <= '0';
Req_W_in <= '0';
Req_S_in <= '0';
Req_L_in <= '0';
else
Req_N_in <= Req_N_FF;
Req_E_in <= Req_E_FF;
Req_W_in <= Req_W_FF;
Req_S_in <= Req_S_FF;
Req_L_in <= Req_L_FF;
end if;
end process;
END; | gpl-3.0 | 6e16dd29e4c2fc9931d946197c93cea0 | 0.488375 | 3.017992 | false | false | false | false |
bruskajp/EE-316 | Project5/game_logic_5.vhd | 1 | 21,740 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04/05/2017 02:01:44 PM
-- Design Name:
-- Module Name: game_logic - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity game_logic is
port(
clk : in STD_LOGIC;
usb_bt_clk : in STD_LOGIC;
save_button_input : in STD_LOGIC;
keyboard_input : in STD_LOGIC_VECTOR(7 downto 0);
x_pos_input : in STD_LOGIC_VECTOR(7 downto 0);
y_pos_input : in STD_LOGIC_VECTOR(7 downto 0);
usb_bt_input : in STD_LOGIC_VECTOR(7 downto 0);
reset_output : out STD_LOGIC;
screen_size_output : out STD_LOGIC;
pen_width_output : out STD_LOGIC_VECTOR(2 downto 0);
x_pos_output : out STD_LOGIC_VECTOR(7 downto 0);
y_pos_output : out STD_LOGIC_VECTOR(7 downto 0);
tricolor_led_output : out STD_LOGIC_VECTOR(11 downto 0);
usb_bt_output : out STD_LOGIC_VECTOR(15 downto 0);
color_output : out STD_LOGIC_VECTOR(23 downto 0);
ram_we_output : out STD_LOGIC_VECTOR(0 downto 0);
ram_val_output : out STD_LOGIC_VECTOR(11 downto 0);
ram_addr_output : out STD_LOGIC_VECTOR(16 downto 0)
);
end game_logic;
architecture Behavioral of game_logic is
-- Font ROM component
component font_rom is
port(
clk : in STD_LOGIC;
addr : in STD_LOGIC_VECTOR(10 downto 0);
data : out STD_LOGIC_VECTOR(7 downto 0)
);
end component;
-- RAM clock divider component
component clock_divider is
generic(count_max : INTEGER := 8); -- FIX THIS?
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
clk_output : out STD_LOGIC
);
end component;
-- System properties
signal pc_connected : STD_LOGIC := '0';
signal screen_size : STD_LOGIC := '0';
signal reset : STD_LOGIC := '0';
signal pen_width : STD_LOGIC_VECTOR(2 downto 0) := "000";
signal ascii_char : STD_LOGIC_VECTOR(7 downto 0) := x"00";
signal color : STD_LOGIC_VECTOR(23 downto 0) := x"000000";
--USB/bluetooth control send signals
signal prev_screen_size : STD_LOGIC := '0';
signal prev_save : STD_LOGIC := '0';
signal prev_reset : STD_LOGIC := '0';
signal prev_pen_width : STD_LOGIC_VECTOR(2 downto 0):= "000";
signal prev_ascii_char : STD_LOGIC_VECTOR(7 downto 0):= x"00";
signal prev_x_pos, prev_y_pos : STD_LOGIC_VECTOR(7 downto 0):= x"00";
signal prev_color : STD_LOGIC_VECTOR(23 downto 0):= x"000000";
--USB/Bluetooth control receive signals
signal prev_connections : STD_LOGIC_VECTOR(7 downto 0);
-- Keyboard control signals
signal num_values_input : INTEGER := 0;
signal prev_pc_connected : STD_LOGIC := '0';
signal changing_item : STD_LOGIC_VECTOR(2 downto 0) := "000"; -- [color, pen_width, screen_size]
signal hex_input : STD_LOGIC_VECTOR(3 downto 0) := x"0";
signal temp_hex_input : STD_LOGIC_VECTOR(7 downto 0) := x"00";
signal input_values : STD_LOGIC_VECTOR(23 downto 0) := x"000000";
-- Font Rom signals
signal font_rom_addr : UNSIGNED(10 downto 0) := x"00" & "000";
signal font_rom_data : STD_LOGIC_VECTOR(7 downto 0) := x"00";
-- RAM clock divider signals
signal ram_divider_counter : INTEGER := 0;
signal ram_clk : STD_LOGIC := '0';
-- RAM Signals
signal x_pos_int : INTEGER := 0;
signal y_pos_int : INTEGER := 0;
-- RAM fast update signals
signal ram_update_count : INTEGER := 0;
signal ram_update_x_count : INTEGER := 0;
signal ram_update_y_count : INTEGER := 0;
signal ram_update_slow_int : INTEGER := 0;
signal ram_update : STD_LOGIC_VECTOR(2 downto 0) := "000"; -- [pos, sys_text, user_text]
signal ram_update_slow : STD_LOGIC_VECTOR(2 downto 0) := "000";
signal ram_update_pos_slow : STD_LOGIC_VECTOR(7 downto 0) := x"00";
signal ram_update_sys_text_slow : STD_LOGIC_VECTOR(7 downto 0) := x"00";
signal ram_update_user_text_slow : STD_LOGIC_VECTOR(7 downto 0) := x"00";
-- RAM slow control signals
signal x_addr_count, y_addr_count : INTEGER := 0;
-- RAM reset signals
signal ram_reset : STD_LOGIC := '0';
signal ram_reset_slow : STD_LOGIC := '0';
signal ram_reset_count : UNSIGNED(15 downto 0) := x"0000";
signal prev_ram_resets : STD_LOGIC_VECTOR(7 downto 0) := x"00";
begin
screen_size_output <= screen_size;
pen_width_output <= pen_width;
x_pos_output <= x_pos_input;
y_pos_output <= y_pos_input;
tricolor_led_output <= color(11 downto 0);
color_output <= color;
ram_we_output <= "1";
--ram_we_output <= "0";
reset_output <= reset;
-- Previous signal generation process
process(clk)
begin
prev_pc_connected <= pc_connected;
prev_x_pos <= x_pos_input;
prev_y_pos <= y_pos_input;
prev_color <= color;
prev_ascii_char <= ascii_char;
prev_screen_size <= screen_size;
prev_pen_width <= pen_width;
prev_save <= save_button_input;
prev_reset <= reset;
end process;
-- USB/Bluetooth control process
process(clk, usb_bt_clk, prev_x_pos, prev_y_pos) -- FIX THIS (add update method)
begin
-- Sending Data
if rising_edge(clk) then
if reset /= prev_reset then
usb_bt_output(15 downto 12) <= "1111";
usb_bt_output(1) <= save_button_input;
usb_bt_output(0) <= reset;
elsif prev_x_pos /= x_pos_input then
usb_bt_output(15 downto 14) <= "10";
usb_bt_output(8) <= '0';
usb_bt_output(7 downto 0) <= x_pos_input;
elsif prev_y_pos /= y_pos_input then
usb_bt_output(15 downto 14) <= "10";
usb_bt_output(8) <= '1';
usb_bt_output(7 downto 0) <= y_pos_input;
elsif prev_color /= color then
usb_bt_output(15 downto 12) <= "1100";
usb_bt_output(11 downto 0) <= color(11 downto 0); -- change to 24 bit?
elsif prev_screen_size /= screen_size or prev_pen_width /= pen_width then
usb_bt_output(15 downto 12) <= "1110";
usb_bt_output(3) <= screen_size;
usb_bt_output(2 downto 0) <= pen_width;
elsif prev_ascii_char /= ascii_char then
usb_bt_output(15 downto 12) <= "1101";
usb_bt_output(7 downto 0) <= ascii_char;
elsif prev_save /= save_button_input then
usb_bt_output(15 downto 12) <= "1111";
usb_bt_output(1) <= save_button_input;
usb_bt_output(0) <= reset;
else
usb_bt_output <= x"0000";
end if;
end if;
-- Recieving Data
if rising_edge(usb_bt_clk) then
prev_connections <= prev_connections(6 downto 0) & usb_bt_input(0);
if prev_connections = x"00" then
pc_connected <= '0';
else
pc_connected <= '1';
end if;
end if;
end process;
-- Keyboard control process
hex_input <= temp_hex_input(3 downto 0);
process(clk)
begin
-- Keyboard control
if rising_edge(clk) then
if reset = '0' then
if keyboard_input = x"77" and changing_item = "000" then -- input w and changing color
ascii_char <= x"77";
changing_item <= "100";
num_values_input <= 1;
elsif keyboard_input = x"63" and changing_item = "000" then -- input c and changing pen_width
ascii_char <= x"63";
changing_item <= "010";
num_values_input <= 1;
elsif keyboard_input = x"73" and changing_item = "000" then -- input s and changing screen_size
ascii_char <= x"73";
changing_item <= "001";
num_values_input <= 1;
elsif keyboard_input = x"72" and changing_item = "000" then -- input r
reset <= '1';
color <= x"FFFFFF";
pen_width <= "000";
screen_size <= '0';
elsif keyboard_input = x"71" and changing_item /= "000" then -- input q and exit command
ascii_char <= x"71";
-- FIX THIS
elsif keyboard_input = x"08" and num_values_input = 1 then -- input backspace
ascii_char <= x"08";
num_values_input <= 0;
changing_item <= "000";
elsif changing_item /= "000" then
-- Ascii to hex converter
if (keyboard_input >= x"30" and keyboard_input <= x"39") then
temp_hex_input <= std_logic_vector(unsigned(keyboard_input) - x"30");
elsif (keyboard_input >= x"61" and keyboard_input <= x"66") then
temp_hex_input <= std_logic_vector(unsigned(keyboard_input) - x"57");
else
temp_hex_input <= x"FF";
end if;
-- User keyboard input restrictions
if changing_item = "100" and hex_input <= x"F" then -- Limit color
input_values(((num_values_input * 4)-1) downto ((num_values_input-1) * 4)) <= hex_input;
num_values_input <= num_values_input + 1;
elsif changing_item = "010" and hex_input >= x"1" and hex_input <= x"7" then -- Limit pen_width
input_values(3 downto 0) <= hex_input;
num_values_input <= num_values_input + 1;
elsif changing_item = "001" and hex_input <= x"1" then -- Limit screen_size
input_values(3 downto 0) <= hex_input;
num_values_input <= num_values_input + 1;
end if;
elsif keyboard_input = x"0A" then -- input enter
ascii_char <= x"0A";
if changing_item = "100" and num_values_input = 7 then -- new color
color <= input_values;
changing_item <= "000";
elsif changing_item = "010" and num_values_input = 1 then -- new pen_width
pen_width <= input_values(2 downto 0);
changing_item <= "000";
elsif changing_item = "001" and num_values_input = 1 then -- new screen_size
screen_size <= input_values(0);
changing_item <= "000";
end if;
end if;
end if;
-- Reset handling
if reset = '1' and prev_reset = '1' and ram_reset = '0' then
reset <= '0';
color <= x"000000";
end if;
end if;
end process;
-- Font ROM port map
ram_font_rom : font_rom
port map(
clk => clk,
addr => std_logic_vector(font_rom_addr),
data => font_rom_data
);
-- RAM clock divider port map
ram_clock_divider : clock_divider
generic map(count_max => 2) -- CHANGE VALUE
port map(
clk => clk,
reset => '0',
clk_output => ram_clk
);
x_pos_int <= to_integer(unsigned(x_pos_input));
y_pos_int <= to_integer(unsigned(y_pos_input));
-- RAM control process
process(clk, ram_clk)
begin
-- When to update RAM
if rising_edge(clk) then
-- ram_update_pos_slow <= ram_update_pos_slow(6 downto 0) & ram_update_slow(2);
-- ram_update_pos_slow <= ram_update_pos_slow(6 downto 0) & ram_update_slow(2);
-- ram_update_pos_slow <= ram_update_pos_slow(6 downto 0) & ram_update_slow(2);
if (x_pos_input = "00000000" or y_pos_input = "000000000") then
ram_update(2) <= '1'; -- pos
ram_update_slow_int <= 1;
-- elsif (color /= prev_color or pen_width /= prev_pen_width
-- or pc_connected /= prev_pc_connected) then
-- ram_update(1) <= '1'; -- sys_text
-- elsif (ascii_char /= prev_ascii_char) then
-- ram_update(0) <= '1'; -- user_text
end if;
if ram_update_slow_int = std_logic_vector(to_unsigned(2048, 17)) then
ram_update_slow_int <= 0;
elsif ram_update_slow_int > 0 then
ram_update_slow_int <= ram_update_slow_int + 1;
ram_update(2) <= '1';
else
ram_update(2) <= '0';
end if;
-- if ram_update_pos_slow = x"00" then
-- ram_update(2) <= '0';
-- end if;
-- if ram_update_sys_text_slow = x"00" then
-- ram_update(1) <= '0';
-- end if;
-- if ram_update_user_text_slow = x"00" then
-- ram_update(0) <= '0';
-- end if;
-- if reset = '1' and ram_reset = '0' then
-- ram_reset <= '1';
-- prev_ram_resets <= prev_ram_resets(6 downto 0) & ram_reset;
-- end if;
--
-- if ram_reset_slow = '0' and prev_ram_resets = x"FF" then
-- ram_reset <= '0';
-- end if;
-- end if;
-- Draw to RAM
--if rising_edge(ram_clk) then
--if rising_edge(clk) then
--if ram_reset = '0' then
if ram_update(2) = '1' then -- pos
--if(true) then
--ram_we_output <= "1";
ram_val_output <= color(23 downto 20) & color(15 downto 12) & color(7 downto 4);
--ram_update_slow(2) <= '1';
--ram_update(2) <= '0';
-- if (y_addr_count < unsigned(pen_width)) and
-- ((y_pos_int + y_addr_count) < 256) and
-- ((y_pos_int + y_addr_count) >= 0) then
-- if (x_addr_count < unsigned(pen_width)) and
-- ((x_pos_int + x_addr_count) < 256) and
-- ((x_pos_int + x_addr_count) >= 0) then
ram_addr_output <= std_logic_vector(to_unsigned( ((x_pos_int+x_addr_count) + ((y_pos_int+y_addr_count) * 256)) , 17));
else
ram_val_output <= x"F00";
ram_addr_output <= std_logic_vector(to_unsigned(66666, 17));
--ram_update(2) <= '1';
-- else
-- x_addr_count <= 0;
-- end if;
-- y_addr_count <= y_addr_count + 1;
-- else
-- y_addr_count <= 0;
-- end if;
--elsif prev_x_pos /= x_pos_input and prev_y_pos /= y_pos_input then --Not needed?
--ram_update(1) <= '0';
--ram_we_output <= "0"; --Not needed?
--ram_update(2) <= '0'; --Not needed?
-- elsif ram_update(2 downto 1) = "01" then -- sys_text
-- ram_update_slow(2 downto 1) <= "01";
-- if ram_update_count < 3 then
-- if ram_update_y_count < 16 then
-- if ram_update_x_count < 8 then
-- if ram_update_count = 1 then -- Update color
-- ram_addr_output <= std_logic_vector(to_unsigned(65618 + ram_update_x_count
-- + (ram_update_y_count * 384), 17));
-- ram_val_output <= color(11 downto 0);
-- elsif ram_update_count = 2 then -- Update pen_width
-- ram_addr_output <= std_logic_vector(to_unsigned(65768 + ram_update_x_count
-- + (ram_update_y_count * 384), 17));
-- font_rom_addr <= "000" & (x"30" + unsigned("0000" & pen_width)); -- FIX THIS (concurency)
-- if font_rom_data(ram_update_x_count) = '1' then
-- ram_val_output <= x"000";
-- else
-- ram_val_output <= x"FFF";
-- end if;
-- else -- Update pc_connnection
-- ram_addr_output <= std_logic_vector(to_unsigned(65888 + ram_update_x_count
-- + (ram_update_count * 10)
-- + (ram_update_y_count * 384), 17));
-- font_rom_addr <= "00" & (x"30" + "0000000" & pc_connected); -- FIX THIS (concurency)
-- if font_rom_data(ram_update_x_count) = '1' then
-- ram_val_output <= x"000";
-- else
-- ram_val_output <= x"FFF";
-- end if;
-- end if;
-- ram_update_x_count <= ram_update_x_count + 1;
-- else
-- ram_update_x_count <= 0;
-- end if;
-- ram_update_y_count <= ram_update_x_count + 1;
-- else
-- ram_update_y_count <= 0;
-- end if;
-- ram_update_count <= ram_update_count + 1;
-- else
-- ram_update_slow(1) <= '0';
-- ram_update_count <= 0;
-- end if;
-- elsif ram_update = "001" then -- user_text
-- ram_update_slow <= "001";
-- if ram_update_count < 8 then
-- if ram_update_y_count < 16 then
-- if ram_update_x_count < 8 then
-- ram_addr_output <= std_logic_vector(to_unsigned(66102 + ram_update_x_count
-- + (ram_update_y_count * 384), 17));
-- font_rom_addr <= unsigned("000" & ascii_char); -- FIX THIS (concurency)
-- if font_rom_data(ram_update_x_count) = '1' then
-- ram_val_output <= x"000";
-- else
-- ram_val_output <= x"FFF";
-- end if;
-- ram_update_x_count <= ram_update_x_count + 1;
-- else
-- ram_update_x_count <= 0;
-- end if;
-- ram_update_y_count <= ram_update_x_count + 1;
-- else
-- ram_update_y_count <= 0;
-- end if;
-- ram_update_count <= ram_update_count + 1;
-- else
-- ram_update_slow(0) <= '0';
-- ram_update_count <= 0;
-- end if;
-- else
-- ram_update_slow <= "000";
--end if;
---- else -- ram_reset = 1
---- -- Drawing Screen (sys_text and user_text update automatically)
---- if ram_reset_count < 65536 then
---- ram_reset_slow <= '1';
---- ram_reset_count <= ram_reset_count + 1;
---- ram_addr_output <= "0" & std_logic_vector(ram_reset_count);
---- else
---- ram_reset_slow <= '0';
---- ram_reset_count <= x"0000";
---- end if;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 7e9d2984b15b479df88054e70f9a476e | 0.446826 | 3.983144 | false | false | false | false |
SoCdesign/EHA | RTL/Fault_Management/SHMU_prototype/version_1/SHMU.vhd | 1 | 1,458 | --Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity SHMU is
generic (
router_fault_info_width: integer := 5;
network_size: integer := 2
);
port ( reset: in std_logic;
clk: in std_logic;
Faulty_N_0, Faulty_E_0, Faulty_W_0, Faulty_S_0, Faulty_L_0: in std_logic;
Faulty_N_1, Faulty_E_1, Faulty_W_1, Faulty_S_1, Faulty_L_1: in std_logic;
Faulty_N_2, Faulty_E_2, Faulty_W_2, Faulty_S_2, Faulty_L_2: in std_logic;
Faulty_N_3, Faulty_E_3, Faulty_W_3, Faulty_S_3, Faulty_L_3: in std_logic
);
end SHMU;
architecture behavior of SHMU is
type SHM_type is array (0 to network_size*network_size-1) of std_logic_vector(router_fault_info_width-1 downto 0); --memory
signal SHM : SHM_type ;
begin
process(clk, reset)begin
if reset = '0' then
SHM <= (others => (others => '0'));
elsif clk'event and clk = '1' then
SHM(0) <= Faulty_N_0 & Faulty_E_0 & Faulty_W_0 & Faulty_S_0 & Faulty_L_0;
SHM(1) <= Faulty_N_1 & Faulty_E_1 & Faulty_W_1 & Faulty_S_1 & Faulty_L_1;
SHM(2) <= Faulty_N_2 & Faulty_E_2 & Faulty_W_2 & Faulty_S_2 & Faulty_L_2;
SHM(3) <= Faulty_N_3 & Faulty_E_3 & Faulty_W_3 & Faulty_S_3 & Faulty_L_3;
end if;
end process;
END; | gpl-3.0 | 4b7816d51e2e341e0c8ec399c7fd632b | 0.604938 | 2.756144 | false | false | false | false |
bruskajp/EE-316 | Project2/Vivado_NexysBoard/project_2b/project_2b.srcs/sources_1/imports/Downloads/TTL_Serial_Display.vhd | 1 | 3,183 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity TTL_Serial_Display is
Port (
Hex_IN : in STD_LOGIC_VECTOR (15 downto 0);
iCLK : in STD_LOGIC;
Tx : out STD_LOGIC);
end TTL_Serial_Display;
architecture Behavioral of TTL_Serial_Display is
signal DIV : unsigned(15 DOWNTO 0) := X"0000";
--Signals for StateMachine:
type stateType is range 0 to 10;
Signal Sel : integer range 0 to 11;
Signal Q : std_logic ;
signal CS : stateType;
--Signals for Splitter:
signal X1,X2,X3,X4 : std_logic_vector (3 downto 0);
signal extend : std_logic_vector (3 downto 0);
signal baud_en : std_logic;
signal HEX2_Data1 : std_logic_vector (7 downto 0);
signal HEX2_Data2 : std_logic_vector (7 downto 0);
signal HEX2_Data3 : std_logic_vector (7 downto 0);
signal HEX2_Data4 : std_logic_vector (7 downto 0);
signal LUT_Data : std_logic_vector (7 downto 0);
BEGIN
LUTConversion:
Process(Hex_IN)
begin
X1 <= Hex_IN(15 downto 12);
X2 <= Hex_IN(11 downto 8);
X3 <= Hex_IN(7 downto 4);
X4 <= Hex_IN(3 downto 0);
extend <= "0000";
end process;
Process(X1, X2, X3, X4)
begin
HEX2_Data1 <= extend & X1;
HEX2_Data2 <= extend & X2;
HEX2_Data3 <= extend & X3;
HEX2_Data4 <= extend & X4;
end process;
LUTMux:
process (Sel)
begin
if (Sel = 0) then
LUT_Data <= X"76";
elsif (Sel = 1) then
LUT_Data <= X"76";
elsif (Sel = 2) then
LUT_Data <= X"76";
elsif (Sel = 3) then
LUT_Data <= X"76";
elsif (Sel = 4) then
LUT_Data <= X"79";
elsif (Sel = 5) then
LUT_Data <= X"00";
elsif (Sel = 6) then
LUT_Data <= X"7A";
elsif (Sel = 7) then
LUT_Data <= X"FF";
elsif (Sel = 8) then
LUT_Data <= HEX2_Data1;
elsif (Sel = 9) then
LUT_Data <= HEX2_Data2;
elsif (Sel = 10) then
LUT_Data <= HEX2_Data3;
elsif (Sel = 11) then
LUT_Data <= HEX2_Data4;
end if;
end process;
StateMachine:
--code pulled from Ring_Counter.vhd
process(iCLK)
begin
if rising_edge(iCLK) then
if DIV >= X"28B1" then
DIV <= X"0000";
baud_en <= '1';
else
DIV <= DIV +1;
baud_en <= '0';
end if;
end if;
end process;
process (CS, iCLK, baud_en)
begin
if rising_edge(iCLK) and baud_en = '1' then
case CS is
when 0 =>
Q <= '0';
CS <= 1;
when 1 =>
Q <= LUT_Data(0);
CS <= 2;
when 2 =>
Q <= LUT_Data(1);
CS <= 3;
when 3 =>
Q <= LUT_Data(2);
CS <= 4;
when 4 =>
Q <= LUT_Data(3);
CS <= 5;
when 5 =>
Q <= LUT_Data(4);
CS <= 6;
when 6 =>
Q <= LUT_Data(5);
CS <= 7;
when 7 =>
Q <= LUT_Data(6);
CS <= 8;
when 8 =>
Q <= LUT_Data(7);
CS <= 9;
when 9 =>
Q <= '1';
CS <= 10;
if (Sel < 11) then
Sel <= Sel+1;
else
Sel <= 8;
end if;
when 10 =>
Q <= '0';
CS <= 1;
end case;
end if;
end process;
Tx <= Q;
end Behavioral;
| gpl-3.0 | f626f77418316367e2dbe5866deb2547 | 0.50864 | 2.775065 | false | false | false | false |
bruskajp/EE-316 | Project4/Vivado_NexysBoard/craddockEE316/craddockEE316.srcs/sources_1/imports/testFolder/en_register.vhd | 1 | 3,043 | -- file: en_register.vhd
-------------------------------------
-- n bit register with enable
-- Shauna Rae
-- October 18, 1999
library ieee;
use ieee.std_logic_1164.all;
--create a package so that the register can be used again and the width
--can be set
package en_register_pkg is
-- set a constant so that it is easy to change the width of the nregister
--creat the enabled register component
component en_register is
generic (data_width : positive := 20);
port(clock, reset, enable_in : in std_logic;
enable_out: out std_logic;
register_in: in std_logic_vector(data_width-1 downto 0);
register_out : out std_logic_vector(data_width-1 downto 0));
end component en_register;
component multiplex is
generic (data_width : positive := 16);
port(select_line : in std_logic;
in_a, in_b: in std_logic_vector(data_width-1 downto 0);
output : out std_logic_vector(data_width-1 downto 0));
end component multiplex;
component nregister is
generic (data_width : positive := 16);
port(clock, reset : in std_logic;
register_in: in std_logic_vector(data_width-1 downto 0);
register_out : out std_logic_vector(data_width-1 downto 0));
end component nregister;
end en_register_pkg;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.en_register_pkg.all;
--define the entity of the enabled register
entity en_register is
generic (data_width : positive := 8);
port(clock, reset, enable_in: in std_logic;
enable_out: out std_logic;
register_in: in std_logic_vector(data_width-1 downto 0);
register_out : out std_logic_vector(data_width-1 downto 0));
end en_register;
-- use structural VHDL to define the enabled register
-- use the packages of the multiplexer and the n-bit register
architecture mixed of en_register is
-- assign internal signals
signal loop_back, throughput: std_logic_vector(data_width-1 downto 0);
begin
-- latch the enable signal so that it can propagate
register_behaviour: process(clock) is
begin
if reset = '0' then -- on reset zero the output
enable_out <= '0';
--on rising edge of clock set output to input
elsif rising_edge(clock) then
enable_out <= enable_in;
end if;
end process register_behaviour;
-- map the multiplexer inside the enabled register
selection : multiplex
generic map (data_width => data_width)
port map(
-- inputs
select_line => enable_in,
in_a => loop_back,
in_b => register_in,
-- outputs
output => throughput);
-- map the register inside the enabled register
register1 : nregister
generic map (data_width => data_width)
port map(
-- inputs
clock => clock,
reset => reset,
register_in => throughput,
-- outputs
register_out => loop_back);
-- assign the values of the output of the register
-- to the output of the enabled register
register_out <= loop_back;
end mixed;
| gpl-3.0 | 5b0b36241e6ad78c193d8835f0990b85 | 0.655274 | 3.626937 | false | false | false | false |
bruskajp/EE-316 | Project5/vga_out.vhd | 1 | 2,220 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vga_out is
PORT ( iCLK : in STD_LOGIC;
px : in STD_LOGIC_VECTOR(9 DOWNTO 0);
py : in STD_LOGIC_VECTOR(9 DOWNTO 0);
potX : in STD_LOGIC_VECTOR(7 DOWNTO 0);
potY : in STD_LOGIC_VECTOR(7 DOWNTO 0);
color : in STD_LOGIC_VECTOR(11 downto 0);
red : out STD_LOGIC_VECTOR(3 DOWNTO 0);
green : out STD_LOGIC_VECTOR(3 DOWNTO 0);
blue : out STD_LOGIC_VECTOR(3 DOWNTO 0);
ram_addr_output : out STD_LOGIC_VECTOR(16 downto 0)
);
end vga_out;
architecture Behavioral of vga_out is
signal px_int: INTEGER := 0;
signal py_int: INTEGER := 0;
begin
px_int <= to_integer(unsigned(px));
py_int <= to_integer(unsigned(py));
process(iCLK)
begin
if (rising_edge(iCLK)) then
if ((py >= 107) and (py <= 363)) then
if ((px >= 192) and (px <= 448)) then
ram_addr_output <= std_logic_vector(to_unsigned( ((px_int-192) + ((py_int-107) * 256)) , 17)); -- FIX THIS
red <= color(11 downto 8);
green <= color(7 downto 4);
blue <= color(3 downto 0);
-- if (((py - 107) = potY) and ((px - 192) = potX)) then
-- red <= "0000";
-- blue <= "0000";
-- green <= "0000";
-- else
-- red <= "1111";
-- blue <= "1111";
-- green <= "1111";
-- end if;
else
red <= "0000";
blue <= "0000";
green <= "0000";
end if;
elsif ((py >= 447) and (py <= 479)) then
if ((px >= 128) and (px <= 512)) then
ram_addr_output <= std_logic_vector(to_unsigned( (65536 + (px_int-128) + ((py_int-447) * 384)) , 17));
red <= color(11 downto 8);
green <= color(7 downto 4);
blue <= color(3 downto 0);
-- red <= "0000";
-- blue <= "0000";
-- green <= "0000";
else
red <= "0000";
blue <= "0000";
green <= "0000";
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | e577bca272ea2d558bce5ba3e779e273 | 0.477928 | 3.44186 | false | false | false | false |
lnls-dig/dsp-cores | hdl/testbench/divider/div_tb.vhd | 1 | 3,065 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
use work.arith_dsp48e.all;
use work.utilities.all;
entity div_tb is
end div_tb;
architecture behavioral of div_tb is
constant C_DATAIN_WIDTH : integer := 32;
constant C_PRECISION : natural := 29; -- Quotient width = 32
constant c_ce_period : natural := 2;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal ce : std_logic := '0';
signal trg : std_logic := '0';
signal n : std_logic_vector(C_DATAIN_WIDTH-1 downto 0) := (others => '0');
signal d : std_logic_vector(C_DATAIN_WIDTH-1 downto 0) := (others => '0');
--Outputs
signal q : std_logic_vector(C_PRECISION downto 0);
signal r : std_logic_vector(C_DATAIN_WIDTH-1 downto 0) := (others => '0');
signal rdy : std_logic;
signal err : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
constant TAB : character := ht;
file test_out_data : text open write_mode is "output.dat";
begin
uut_div_fixedpoint : div_fixedpoint
generic map
(
G_DATAIN_WIDTH => C_DATAIN_WIDTH,
G_PRECISION => C_PRECISION
)
port map
(
clk_i => clk,
rst_i => rst,
ce_i => ce,
n_i => n,
d_i => d,
q_o => q,
r_o => r,
trg_i => trg,
rdy_o => rdy,
err_o => err
);
-- Clock process definitions
clk_process : process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
ce_gen : process(clk)
variable ce_count : natural := 0;
begin
if rising_edge(clk) then
ce_count := ce_count + 1;
if ce_count = c_ce_period then
ce <= '1';
ce_count := 0;
else
ce <= '0';
end if;
end if;
end process;
-- Stimulus process
stim_proc : process
variable outline : line;
variable i : integer;
begin
--rst <= '1';
--wait for clk_period*10.5*c_ce_period;
--rst <= '0';
--wait for clk_period*10*c_ce_period;
for i in 0 to 5740 loop
n <= std_logic_vector(to_signed((i*i)/2, C_DATAIN_WIDTH));
d <= std_logic_vector(to_signed(32947600, C_DATAIN_WIDTH));
wait for clk_period*1;
write(outline, to_integer(signed(n)));
write(outline, TAB);
write(outline, to_integer(signed(d)));
trg <= '1';
wait for clk_period*c_ce_period;
trg <= '0';
wait for clk_period*31*c_ce_period;
write(outline, TAB);
write(outline, to_integer(signed(q)));
write(outline, TAB);
write(outline, to_integer(signed(r)));
wait for clk_period*1*c_ce_period;
writeline(test_out_data, outline); -- write row to output file
end loop;
assert (false) report "Test finished." severity failure;
wait;
end process;
end;
| lgpl-3.0 | 040f5fd86f180e8fc5ad34286a7319bb | 0.547798 | 3.34607 | false | false | false | false |
bruskajp/EE-316 | Project4/Vivado_NexysBoard/craddockEE316/craddockEE316.srcs/sources_1/imports/testFolder/ad_converter.vhd | 1 | 5,780 | -- file: ad_converter.vhd
-------------------------------------
-- control module for the analog to digital converter
-- Shauna Rae
-- October 29, 1999
library ieee;
use ieee.std_logic_1164.all;
package ad_converter_pkg is
component ad_converter
port (from_adc : in std_logic_vector(7 downto 0);
adc_dataReady, slow_clk, reset, enable : in std_logic;
adc_select : out std_logic_vector(1 downto 0);
adc_output00FL, adc_output01FR, adc_output10BL,
adc_output11BR : out std_logic_vector(7 downto 0);
adc_clock, adc_loadAddressStart, adc_outputEnable,
data_valid: out std_logic);
end component;
end ad_converter_pkg;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.ad_converter_pkg.all;
use work.en_register_pkg.all;
entity ad_converter is
port (from_adc : in std_logic_vector(7 downto 0);
adc_dataReady, slow_clk, reset, enable : in std_logic;
adc_select : out std_logic_vector(1 downto 0);
adc_output00FL, adc_output01FR, adc_output10BL, adc_output11BR
: out std_logic_vector(7 downto 0);
adc_clock, adc_loadAddressStart, adc_outputEnable, data_valid
: out std_logic);
end ad_converter;
architecture mixed of ad_converter is
signal selection: std_logic_vector(1 downto 0);
signal count: std_logic_vector(2 downto 0);
signal outputEnable, flag_start, flag_wait, loadAddressStart,
enable00FL, enable01FR, enable10BL, enable11BR,
data_valid00FL, data_valid01FR, data_valid10BL, data_valid11BR
: std_logic;
signal dataReady_curr : std_logic;
signal dataReady_meta : std_logic;
signal dataReady_last : std_logic;
begin
adc_clock <= slow_clk;
adc_loadAddressStart <= loadAddressStart;
adc_select <= selection;
adc_outputEnable <= outputEnable;
process(adc_dataReady, slow_clk)
begin
if rising_edge(slow_clk) then
dataReady_meta <= adc_dataReady;
dataReady_curr <= dataReady_meta;
end if;
end process;
dataReady_last <= dataReady_curr when rising_edge(slow_clk);
test :process(slow_clk, reset)
begin
-- reset state
if reset = '0' then
selection <= "00";
flag_start <= '0';
loadAddressStart <= '0';
data_valid <= '0';
-- on rising edge of slow_clk
elsif slow_clk'event and slow_clk = '1' then
-- data_valid should go high when data from
-- all registers is valid, once all four
data_valid <= data_valid11BR;
-- alternate between starting conversion
-- and reading output from ADC
if flag_start = '0' and enable = '1' then
-- load address and start conversion
-- requires a pulse
if loadAddressStart = '0' then
outputEnable <= '0';
loadAddressStart <= '1';
elsif loadAddressStart = '1' then
loadAddressStart <= '0';
flag_start <= '1';
end if;
-- now read output
elsif flag_start = '1' then
-- check if conversion complete
-- for even addresses flag_wait should
-- be one for odd 0
if flag_wait = '1' and (selection = "00" or
selection = "10") then
-- change address
if selection = "00" then
selection <= "01";
elsif selection = "10" then
selection <= "11";
end if;
-- set outputEnable high
outputEnable <= '1';
-- clear flag to begin next conversion
flag_start <= '0';
-- case for odd addresses
elsif flag_wait = '0' and (selection = "01" or
selection = "11") then
if selection = "11" then
selection <= "00";
elsif selection = "01" then
selection <= "10";
end if;
outputEnable <= '1';
flag_start <= '0';
end if;
end if;
end if;
end process;
-- This process is used to check that the a conversion
-- is complete on the ADC. This is indicated by a
-- rising edge of the adc_dataReady line.
check_dataReady : process(adc_dataReady)
begin
if (dataReady_curr XOR dataReady_last) = '1' then
if flag_wait = '0' then
flag_wait <= '1';
elsif flag_wait = '1' then
flag_wait <= '0';
end if;
end if;
end process check_dataReady;
-- store data in appropriate registers by enabling
with selection select
enable00FL <= outputEnable when "01",
'0' when others;
with selection select
enable01FR <= outputEnable when "10",
'0' when others;
with selection select
enable10BL <= outputEnable when "11",
'0' when others;
with selection select
enable11BR <= outputEnable when "00",
'0' when others;
-- assign the outputs of the converter to an enabled register
inregister00FL : en_register
generic map ( data_width => 8)
port map(
-- inputs
clock => slow_clk,
reset => reset,
enable_in => enable00FL,
register_in => from_adc,
-- outputs
register_out => adc_output00FL,
enable_out => data_valid00FL);
inregister01FR : en_register
generic map ( data_width => 8)
port map(
-- inputs
clock => slow_clk,
reset => reset,
enable_in => enable01FR,
register_in => from_adc,
-- outputs
register_out => adc_output01FR,
enable_out => data_valid01FR);
inregister10BL : en_register
generic map ( data_width => 8)
port map(
-- inputs
clock => slow_clk,
reset => reset,
enable_in => enable10BL,
register_in => from_adc,
-- outputs
register_out => adc_output10BL,
enable_out => data_valid10BL);
inregister11BR : en_register
generic map ( data_width => 8)
port map(
-- inputs
clock => slow_clk,
reset => reset,
enable_in => enable11BR,
register_in => from_adc,
-- outputs
register_out => adc_output11BR,
enable_out => data_valid11BR);
end mixed; | gpl-3.0 | 1be0b83cc286f4a98943a3e21dc209fa | 0.633737 | 3.278503 | false | false | false | false |
Ana06/function-graphing-FPGA | puntos_muestra.vhd | 2 | 8,881 | ----------------------------------------------------------------------------------
-- Company: Nameless2
-- Engineer: Ana María Martínez Gómez, Aitor Alonso Lorenzo, Víctor Adolfo Gallego Alcalá
--
-- Create Date: 13:01:33 11/18/2013
-- Design Name:
-- Module Name: puntos_muestra - Behavioral
-- Project Name: Representación gráfica de funciones
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity puntos_muestra is
Port ( caso : in std_logic_vector(1 downto 0);
numPuntos : in std_logic_vector( 6 downto 0);
enable, retro_muestra : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
fin : out STD_LOGIC;
entradaTeclado: in std_logic_vector(49 downto 0);
punto_o : out STD_LOGIC_VECTOR(20 downto 0);
count_o: out std_logic_vector(3 downto 0));-- Para mostrar en el display de 7 segmentos
end puntos_muestra;
architecture Behavioral of puntos_muestra is
-- En la representación en coma fija
-- DEC es el número de bits reservados a la parte decimal
-- ENT es el número de bits reservados a la parte entera
constant ENT : integer := 11;
constant DEC : integer := 10;
--Tamaño de los coeficientes en la señal de salida del teclado
constant COEF : integer := 5;
constant NUM_COUNT : integer:= 4;
type matriz1 is array(0 to 32) of std_logic_vector(DEC+ENT+NUM_COUNT-1 downto 0);
type matriz2 is array(0 to 31) of std_logic_vector(DEC+ENT+NUM_COUNT-1 downto 0);
-- En función del caso utilizaremos uno de los siguientes muestreos de puntos (para más información consultar genera2.m)
constant puntos1 : matriz1 := (
"0000000000000000000000000",
"0000000000000001000000000",
"0000000000000010000000000",
"0000000000000011000000000",
"0000000000000100000000000",
"0000000000000101000000000",
"0000000000000110000000000",
"0000000000000111000000000",
"0000000000001000000000000",
"0000000000001001000000000",
"0000000000001010000000000",
"0000000000001011000000000",
"0000000000001100000000000",
"0000000000001101000000000",
"0000000000001110000000000",
"0000000000001111000000000",
"0000000000010000000000000",
"0000000000010001000000000",
"0000000000010010000000000",
"0000000000010011000000000",
"0000000000010100000000000",
"0000000000010101000000000",
"0000000000010110000000000",
"0000000000010111000000000",
"0000000000011000000000000",
"0000000000011001000000000",
"0000000000011010000000000",
"0000000000011011000000000",
"0000000000011100000000000",
"0000000000011101000000000",
"0000000000011110000000000",
"0000000000011111000000000",
"0000000000100000000000000");
constant puntos2 : matriz2 := (
"0000000000000000000000000",
"0000000000000010000000000",
"0000000000000011000000000",
"0000000000000100000000000",
"0000000000000101000000000",
"0000000000000110000000000",
"0000000000000111000000000",
"0000000000001000000000000",
"0000000000001001000000000",
"0000000000001010000000000",
"0000000000001011000000000",
"0000000000001100000000000",
"0000000000001101000000000",
"0000000000001110000000000",
"0000000000001111000000000",
"0000000000010000000000000",
"0000000000010001000000000",
"0000000000010010000000000",
"0000000000010011000000000",
"0000000000010100000000000",
"0000000000010101000000000",
"0000000000010110000000000",
"0000000000010111000000000",
"0000000000011000000000000",
"0000000000011001000000000",
"0000000000011010000000000",
"0000000000011011000000000",
"0000000000011100000000000",
"0000000000011101000000000",
"0000000000011110000000000",
"0000000000011111000000000",
"0000000000100000000000000");
constant puntos3 : matriz2 := (
"1111111111100000000000000",
"1111111111100010000000000",
"1111111111100100000000000",
"1111111111100110000000000",
"1111111111101000000000000",
"1111111111101010000000000",
"1111111111101100000000000",
"1111111111101110000000000",
"1111111111110000000000000",
"1111111111110010000000000",
"1111111111110100000000000",
"1111111111110110000000000",
"1111111111111000000000000",
"1111111111111010000000000",
"1111111111111100000000000",
"1111111111111110000000000",
"0000000000000010000000000",
"0000000000000100000000000",
"0000000000000110000000000",
"0000000000001000000000000",
"0000000000001010000000000",
"0000000000001100000000000",
"0000000000001110000000000",
"0000000000010000000000000",
"0000000000010010000000000",
"0000000000010100000000000",
"0000000000010110000000000",
"0000000000011000000000000",
"0000000000011010000000000",
"0000000000011100000000000",
"0000000000011110000000000",
"0000000000100000000000000");
signal punto: STD_LOGIC_VECTOR(DEC+ENT+NUM_COUNT-1 downto 0);
signal count: std_logic_vector(3 downto 0);
signal c3, c2,c1, cn1, cn2, cn3: std_logic_vector(COEF-1 downto 0);
signal puntoAux: std_logic_vector(20 downto 0);
signal estado, estado_sig: std_logic_vector(6 downto 0);
begin
-- Obtenemos los coeficientes introducidos por el teclado, en valor absoluto
process(entradaTeclado)
begin
if entradaTeclado(34)='1' then c3 <= "00000" - entradaTeclado(34 downto 30);
else c3 <= entradaTeclado(34 downto 30);
end if;
if entradaTeclado(29)='1' then c2 <= "00000" - entradaTeclado(29 downto 25);
else c2 <= entradaTeclado(29 downto 25);
end if;
if entradaTeclado(24)='1' then c1 <= "00000" - entradaTeclado(24 downto 20);
else c1 <= entradaTeclado(24 downto 20);
end if;
if entradaTeclado(14)='1' then cn1<= "00000" - entradaTeclado(14 downto 10);
else cn1 <= entradaTeclado(14 downto 10);
end if;
if entradaTeclado(9)='1' then cn2 <= "00000" - entradaTeclado(9 downto 5);
else cn2 <= entradaTeclado(9 downto 5);
end if;
if entradaTeclado(4)='1' then cn3 <= "00000" - entradaTeclado(4 downto 0);
else cn3 <= entradaTeclado(4 downto 0);
end if;
end process;
-- En función de los coeficientes de la función, escogemos el count adecuado (reescalado del eje X)
-- (para más información consultar genera2.m)
pcount: process(c3, c2, c1, cn1, cn2, cn3, caso)
begin
if caso = "00" then
count <= "0000";
else
if c3>0 then
if cn3>0 then
count<="0010";
elsif cn2>0 then
if c3 > cn2(4 downto 1) then
count<="0001";
else
count<="0010";
end if;
elsif cn1>0 then
count<="0001";
else
count<="0001";
end if;
elsif c2>0 then
if cn3>0 then
if cn3 > c2(4 downto 1) then
count<="0011";
else
count<="0010";
end if;
elsif cn2>0 then
count<="0010";
elsif cn1>0 then
if c2 > cn1(4 downto 1) then
count<="0001";
else
count<="0010";
end if;
else
count<="0010";
end if;
elsif c1>0 then
if cn3>0 then
count<="0011";
elsif cn2>0 then
if cn2 > c1(4 downto 1) then
count<="0011";
else
count<="0010";
end if;
else
count<="0010";
end if;
else
if cn3>0 then
count<="0100";
elsif cn2>0 then
count<="0011";
elsif cn1>0 then
count<="0010";
else
count<="0000";
end if;
end if;
end if;
end process pcount;
sincrono: process (clk, reset, enable)
begin
if reset = '1' then
estado <= (others => '0');
elsif clk'event and clk = '1' then
if enable = '1' then
estado <= estado_sig;
elsif retro_muestra = '1'
then estado <= numPuntos-1;
end if;
end if;
end process sincrono;
maquina_estados: process(estado, caso, numPuntos)
begin
if estado = "0000000" then
fin <= '1';
else
fin <= '0';
end if;
if caso = "00" then
punto <= puntos1(conv_integer(unsigned(estado)));
elsif caso = "01" then
punto <= puntos2(conv_integer(unsigned(estado)));
else
punto <= puntos3(conv_integer(unsigned(estado)));
end if;
if estado = numPuntos-1 then
estado_sig <= (others => '0');
fin <= '1';
else
estado_sig <= estado + 1;
fin <= '0';
end if;
end process maquina_estados;
-- En función del count (nos indica la potencia de 2 por la cual tenemos que multiplicar los puntos de muestra),
--elegimos el subvector que nos interesa
puntoAux <= punto(DEC+ENT+NUM_COUNT-1-conv_integer(count) downto NUM_COUNT-conv_integer(count));
punto_o <= puntoAux;
-- Escala x: en el caso normal, 1 unidad equivale a 2^(count-3), por lo que count_o representará este exponente
-- En el caso de solo tomar números positivos (logaritmo), debido al reescalado de los puntos, ahora 1 unidad
-- representará la mitad que en el caso anterior
with caso select
count_o <= count-3 when "10", --eje central
count-4 when others;--eje en la izquierda (log)
end Behavioral;
| gpl-3.0 | 58c620d68abd88ce8600aa4069613746 | 0.699696 | 3.832974 | false | false | false | false |
lnls-dig/dsp-cores | hdl/modules/divider/divider_impl_test_top.vhd | 1 | 5,298 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
use work.arith_dsp48e.all;
use work.utilities.all;
entity divider_impl_test_top is
port
(
CLK_SYS_125_INT_P : in std_logic;
CLK_SYS_125_INT_N : in std_logic;
SYS_FP_LED : out std_logic_vector(7 downto 0)
);
end divider_impl_test_top;
architecture structural of divider_impl_test_top is
---------------------------------------------------------------------------
-- ICON/VIO/ILA components
---------------------------------------------------------------------------
component icon
port
(
CONTROL0 : inout std_logic_vector(35 downto 0);
CONTROL1 : inout std_logic_vector(35 downto 0)
);
end component;
component vio
port
(
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
SYNC_IN : in std_logic_vector(255 downto 0);
SYNC_OUT : out std_logic_vector(255 downto 0)
);
end component;
component ila
port
(
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
DATA : in std_logic_vector(80 downto 0);
TRIG0 : in std_logic_vector(1 downto 0)
);
end component;
---------------------------------------------------------------------------
-- VIO interface
---------------------------------------------------------------------------
signal slv_icon_control0 : std_logic_vector(35 downto 0);
signal slv_icon_control1 : std_logic_vector(35 downto 0);
signal slv_vio_out : std_logic_vector(255 downto 0);
-----------------------------------------------------------------------
-- VIO OUTPUT RANGE
-----------------------------------------------------------------------
-- Reset 0
-- Numerator 25 downto 1
-- Denominator 50 downto 26
-- Trigger 51
-- Select numerator from VIO 52
-- Numerator initialization 77 downto 53
-- Numerator step 102 downto 78
-- Number of iterations 112 downto 103
signal slv_vio_in : std_logic_vector(255 downto 0);
-----------------------------------------------------------------------
-- VIO INPUT RANGE
-----------------------------------------------------------------------
signal sl_clk : std_logic;
signal sl_rdy : std_logic;
signal sl_trg_divider : std_logic;
signal sl_select_n_vio : std_logic;
signal slv_q : std_logic_vector(24 downto 0);
signal slv_r : std_logic_vector(24 downto 0);
signal slv_shift : std_logic_vector(5 downto 0);
signal slv_n : std_logic_vector(24 downto 0);
signal slv_n_generated : std_logic_vector(24 downto 0);
signal slv_ila_trg : std_logic_vector(1 downto 0);
signal slv_data_ila : std_logic_vector(80 downto 0);
signal led: std_logic;
begin
ibufgds_inst: ibufgds
port map
(
I => CLK_SYS_125_INT_P,
IB => CLK_SYS_125_INT_N,
O => sl_clk
);
div_inst: div_floatingpoint
generic map
(
G_DATA_WIDTH => 25
)
port map
(
i_clk => sl_clk,
i_rst => slv_vio_out(0),
i_n => slv_n,
i_d => slv_vio_out(50 downto 26),
o_q => slv_q,
o_r => slv_r,
o_shift => slv_shift,
i_trg => sl_trg_divider,
o_rdy => sl_rdy,
o_err => open
);
icon_inst: icon
port map
(
CONTROL0 => slv_icon_control0,
CONTROL1 => slv_icon_control1
);
vio_inst: vio
port map
(
CONTROL => slv_icon_control0,
CLK => sl_clk,
SYNC_IN => slv_vio_in,
SYNC_OUT => slv_vio_out
);
ila_inst: ila
port map
(
CONTROL => slv_icon_control1,
CLK => sl_clk,
DATA => slv_data_ila,
TRIG0 => slv_ila_trg
);
data_generator_inst: data_generator
generic map
(
G_DATA_WIDTH => 25
)
port map
(
i_clk => sl_clk,
i_rst => slv_vio_out(51),
i_data_init => slv_vio_out(77 downto 53),
i_data_step => slv_vio_out(102 downto 78),
i_niterations => slv_vio_out(112 downto 103),
o_data => slv_n_generated,
o_trg => sl_trg_divider
);
slv_ila_trg <= sl_rdy & slv_vio_out(51);
slv_data_ila <= slv_q & slv_r & slv_shift & slv_n;
sl_select_n_vio <= slv_vio_out(52);
slv_n <= slv_vio_out(25 downto 1) when sl_select_n_vio = '1' else
slv_n_generated;
SYS_FP_LED(7 downto 0) <= (others=>'0');
end structural; | lgpl-3.0 | 2d54d600f4c82d3e33f62d31dea12ddc | 0.4245 | 4.119751 | false | false | false | false |
lnls-dig/dsp-cores | hdl/modules/delta_sigma/delta_sigma.vhd | 1 | 19,200 | -------------------------------------------------------------------------------
-- Title : Delta_sigma calculator
-- Project :
-------------------------------------------------------------------------------
-- File : delta_sigma.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-05-16
-- Last update: 2016-05-09
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: This module gets a,b,c and d values and calculates X, Y, Q and
-- SUM.
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-05-16 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dsp_cores_pkg.all;
-------------------------------------------------------------------------------
entity ds_first_stage is
generic (
g_width : natural := 32
);
port(
a_i : in std_logic_vector(g_width-1 downto 0);
b_i : in std_logic_vector(g_width-1 downto 0);
c_i : in std_logic_vector(g_width-1 downto 0);
d_i : in std_logic_vector(g_width-1 downto 0);
clk_i : in std_logic;
valid_i : in std_logic;
valid_o : out std_logic;
ce_i : in std_logic;
x_o : out std_logic_vector(g_width-1 downto 0);
y_o : out std_logic_vector(g_width-1 downto 0);
q_o : out std_logic_vector(g_width-1 downto 0);
sum_o : out std_logic_vector(g_width-1 downto 0)
);
end entity ds_first_stage;
architecture behavioral of ds_first_stage is
signal diff_ab, diff_cd : signed(g_width-1 downto 0);
signal sum_ab, sum_cd : signed(g_width-1 downto 0);
signal valid_d0 : std_logic := '0';
begin
-- Using these formulas to calculate delta:
-- x = (a-b) - (c-d)
-- y = (a+b) - (c+d)
-- q = (a-b) + (c-d)
-- sum = a+b+c+d
stage1 : process(clk_i)
variable a, b, c, d : signed(g_width-1 downto 0);
begin
-- to avoid multiple stages of combinatorial logic, divide it between difference and sum.
-- Remeber signals are only updated at the end of process
if rising_edge(clk_i) then
if ce_i = '1' then
a := signed(a_i); b := signed(b_i); c := signed(c_i); d := signed(d_i);
-- First cycle
diff_ab <= a - b;
diff_cd <= c - d;
sum_ab <= a + b;
sum_cd <= c + d;
valid_d0 <= valid_i;
-- Second cycle
x_o <= std_logic_vector(diff_ab - diff_cd);
y_o <= std_logic_vector(sum_ab - sum_cd);
q_o <= std_logic_vector(diff_ab + diff_cd);
sum_o <= std_logic_vector(sum_ab + sum_cd);
valid_o <= valid_d0;
end if;
end if;
end process;
end architecture behavioral; --ds_first_stage
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dsp_cores_pkg.all;
entity ds_k_scaling is
generic (
g_width : natural := 32;
g_k_width : natural := 32
);
port(
x_i : in std_logic_vector(g_width-1 downto 0);
kx_i : in std_logic_vector(g_k_width-1 downto 0);
x_valid_i : in std_logic;
y_i : in std_logic_vector(g_width-1 downto 0);
ky_i : in std_logic_vector(g_k_width-1 downto 0);
y_valid_i : in std_logic;
q_i : in std_logic_vector(g_width-1 downto 0);
q_valid_i : in std_logic;
sum_i : in std_logic_vector(g_width-1 downto 0);
ksum_i : in std_logic_vector(g_k_width-1 downto 0);
sum_valid_i : in std_logic;
clk_i : in std_logic;
ce_i : in std_logic;
x_o : out std_logic_vector(g_width-1 downto 0);
y_o : out std_logic_vector(g_width-1 downto 0);
q_o : out std_logic_vector(g_width-1 downto 0);
sum_o : out std_logic_vector(g_width-1 downto 0);
valid_o : out std_logic
);
end entity ds_k_scaling;
architecture structural of ds_k_scaling is
signal x_pre, y_pre, q_pre, sum_pre : std_logic_vector(g_width-1 downto 0);
signal x_valid_int, y_valid_int, q_valid_int, sum_valid_int : std_logic_vector(0 downto 0);
signal x_valid_pre_int, y_valid_pre_int, q_valid_pre_int, sum_valid_pre_int : std_logic_vector(0 downto 0);
signal x_valid_pre, y_valid_pre, q_valid_pre, sum_valid_pre : std_logic;
signal x_valid : std_logic;
signal y_valid : std_logic;
signal q_valid : std_logic;
signal sum_valid : std_logic;
attribute keep : string;
attribute keep of x_pre, y_pre, sum_pre : signal is "true";
constant c_levels : natural := 7;
begin
-- Input registers from division
-- X pipeline
cmp_x_input : pipeline
generic map (
g_width => g_width,
g_depth => 1)
port map (
data_i => x_i,
clk_i => clk_i,
ce_i => ce_i,
data_o => x_pre);
x_valid_int(0) <= x_valid_i;
cmp_x_valid_input : pipeline
generic map (
g_width => 1,
g_depth => 1)
port map (
data_i => x_valid_int,
clk_i => clk_i,
ce_i => ce_i,
data_o => x_valid_pre_int);
x_valid_pre <= x_valid_pre_int(0);
-- Y pipeline
cmp_y_input : pipeline
generic map (
g_width => g_width,
g_depth => 1)
port map (
data_i => y_i,
clk_i => clk_i,
ce_i => ce_i,
data_o => y_pre);
y_valid_int(0) <= y_valid_i;
cmp_y_valid_input : pipeline
generic map (
g_width => 1,
g_depth => 1)
port map (
data_i => y_valid_int,
clk_i => clk_i,
ce_i => ce_i,
data_o => y_valid_pre_int);
y_valid_pre <= y_valid_pre_int(0);
-- Sum pipeline
cmp_sum_input : pipeline
generic map (
g_width => g_width,
g_depth => 1)
port map (
data_i => sum_i,
clk_i => clk_i,
ce_i => ce_i,
data_o => sum_pre);
sum_valid_int(0) <= sum_valid_i;
cmp_sum_valid_input : pipeline
generic map (
g_width => 1,
g_depth => 1)
port map (
data_i => sum_valid_int,
clk_i => clk_i,
ce_i => ce_i,
data_o => sum_valid_pre_int);
sum_valid_pre <= sum_valid_pre_int(0);
-- Q pipeline
cmp_q_input : pipeline
generic map (
g_width => g_width,
g_depth => 1)
port map (
data_i => q_i,
clk_i => clk_i,
ce_i => ce_i,
data_o => q_pre);
q_valid_int(0) <= q_valid_i;
cmp_q_valid_input : pipeline
generic map (
g_width => 1,
g_depth => 1)
port map (
data_i => q_valid_int,
clk_i => clk_i,
ce_i => ce_i,
data_o => q_valid_pre_int);
q_valid_pre <= q_valid_pre_int(0);
-- q is special: it won't be multiplied. So, it must be pipelined to level
-- the delay of the other signals
cmp_q_pipe : pipeline
generic map (
g_width => g_width,
g_depth => c_levels+2)
port map (
data_i => q_pre,
clk_i => clk_i,
ce_i => ce_i,
data_o => q_o);
cmp_mult_x : generic_multiplier
generic map (
g_a_width => g_width,
g_b_width => g_k_width,
g_signed => true,
g_p_width => g_width,
g_levels => c_levels)
port map (
a_i => x_pre,
b_i => kx_i,
valid_i => x_valid_pre,
p_o => x_o,
valid_o => x_valid,
ce_i => ce_i,
clk_i => clk_i,
rst_i => '0');
cmp_mult_y : generic_multiplier
generic map (
g_a_width => g_width,
g_b_width => g_k_width,
g_signed => true,
g_p_width => g_width,
g_levels => c_levels)
port map (
a_i => y_pre,
b_i => ky_i,
valid_i => y_valid_pre,
p_o => y_o,
valid_o => y_valid,
ce_i => ce_i,
clk_i => clk_i,
rst_i => '0');
cmp_mult_sum : generic_multiplier
generic map (
g_a_width => g_width,
g_b_width => g_k_width,
g_signed => true,
g_p_width => g_width,
g_levels => c_levels)
port map (
a_i => sum_pre,
b_i => ksum_i,
valid_i => sum_valid_pre,
p_o => sum_o,
valid_o => sum_valid,
ce_i => ce_i,
clk_i => clk_i,
rst_i => '0');
-- Output X, Y or Sum valid signal as the "valid_o"
valid_o <= x_valid;
end architecture structural; --ds_k_scaling
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dsp_cores_pkg.all;
use work.gencores_pkg.all;
entity ds_offset_scaling is
generic (
g_width : natural := 32;
g_precision : natural := 8;
g_offset_width : natural := 32;
g_offset_precision : natural := 0);
port(
clk_i : in std_logic;
ce_i : in std_logic;
x_i : in std_logic_vector(g_width-1 downto 0);
y_i : in std_logic_vector(g_width-1 downto 0);
q_i : in std_logic_vector(g_width-1 downto 0);
sum_i : in std_logic_vector(g_width-1 downto 0);
valid_i : in std_logic;
offset_x_i : in std_logic_vector(g_offset_width-1 downto 0);
offset_y_i : in std_logic_vector(g_offset_width-1 downto 0);
x_o : out std_logic_vector(g_width-1 downto 0);
y_o : out std_logic_vector(g_width-1 downto 0);
q_o : out std_logic_vector(g_width-1 downto 0);
sum_o : out std_logic_vector(g_width-1 downto 0);
valid_o : out std_logic);
end entity ds_offset_scaling;
architecture structural of ds_offset_scaling is
constant c_levels : natural := 2+1; -- 2 clock cycles for gc_big_adder2 + 1 for registering
signal offset_x_n : std_logic_vector(g_width-1 downto 0);
signal offset_x_shift : std_logic_vector(g_width-1 downto 0);
signal x_offset : std_logic_vector(g_width-1 downto 0);
signal x_offset_valid : std_logic;
signal x_offset_reg : std_logic_vector(g_width-1 downto 0);
signal x_offset_valid_reg : std_logic;
signal offset_y_n : std_logic_vector(g_width-1 downto 0);
signal offset_y_shift : std_logic_vector(g_width-1 downto 0);
signal y_offset : std_logic_vector(g_width-1 downto 0);
signal y_offset_valid : std_logic;
signal y_offset_reg : std_logic_vector(g_width-1 downto 0);
function f_shift_left_gen (arg : signed; count : integer) return signed is
variable v_count : natural := 0;
variable v_ret : signed(arg'range);
begin
if count >= 0 then
v_count := count;
v_ret := shift_left(arg, v_count);
else
v_count := -count;
v_ret := shift_right(arg, v_count);
end if;
return v_ret;
end f_shift_left_gen;
begin
-- q and sum won't be subtracted. So, it must be pipelined to level
-- the delay of the other signals
cmp_q_pipe : pipeline
generic map (
g_width => g_width,
g_depth => c_levels)
port map (
clk_i => clk_i,
ce_i => ce_i,
data_i => q_i,
data_o => q_o);
cmp_sum_pipe : pipeline
generic map (
g_width => g_width,
g_depth => c_levels)
port map (
clk_i => clk_i,
ce_i => ce_i,
data_i => sum_i,
data_o => sum_o);
----------------------------------
-- X Offset
----------------------------------
cmp_x_offset_adder : gc_big_adder2
generic map (
g_data_bits => g_width
)
port map (
clk_i => clk_i,
ce_i => ce_i,
stall_i => '0',
valid_i => valid_i,
a_i => x_i,
b_i => offset_x_n,
c_i => '1',
x2_o => x_offset,
c2x2_valid_o => x_offset_valid);
-- align decimal points
offset_x_shift <= std_logic_vector(f_shift_left_gen(signed(offset_x_i),
g_precision - g_offset_precision));
offset_x_n <= not offset_x_shift;
-- gc_big_adder2 outputs are unregistered. So register them.
p_x_offset_reg : process(clk_i)
begin
if rising_edge(clk_i) then
if ce_i = '1' then
x_offset_reg <= x_offset;
x_offset_valid_reg <= x_offset_valid;
end if;
end if;
end process;
x_o <= x_offset_reg;
valid_o <= x_offset_valid_reg;
----------------------------------
-- Y Offset
----------------------------------
cmp_y_offset_adder : gc_big_adder2
generic map (
g_data_bits => g_width
)
port map (
clk_i => clk_i,
ce_i => ce_i,
stall_i => '0',
valid_i => valid_i,
a_i => y_i,
b_i => offset_y_n,
c_i => '1',
x2_o => y_offset);
-- align decimal points
offset_y_shift <= std_logic_vector(f_shift_left_gen(signed(offset_y_i),
g_precision - g_offset_precision));
offset_y_n <= not offset_y_shift;
-- gc_big_adder2 outputs are unregistered. So register them.
p_y_offset_reg : process(clk_i)
begin
if rising_edge(clk_i) then
if ce_i = '1' then
y_offset_reg <= y_offset;
end if;
end if;
end process;
y_o <= y_offset_reg;
end architecture structural; --ds_offset_scaling
-------------------------------------------------------------------------------
-- Top level
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dsp_cores_pkg.all;
entity delta_sigma is
generic (
g_width : natural := 32;
g_k_width : natural := 24;
g_offset_width : natural := 32
);
port (
a_i : in std_logic_vector(g_width-1 downto 0);
b_i : in std_logic_vector(g_width-1 downto 0);
c_i : in std_logic_vector(g_width-1 downto 0);
d_i : in std_logic_vector(g_width-1 downto 0);
kx_i : in std_logic_vector(g_k_width-1 downto 0);
ky_i : in std_logic_vector(g_k_width-1 downto 0);
ksum_i : in std_logic_vector(g_k_width-1 downto 0);
offset_x_i : in std_logic_vector(g_offset_width-1 downto 0) := (others => '0');
offset_y_i : in std_logic_vector(g_offset_width-1 downto 0) := (others => '0');
clk_i : in std_logic;
ce_i : in std_logic;
valid_i : in std_logic;
valid_o : out std_logic;
rst_i : in std_logic;
x_o : out std_logic_vector(g_width-1 downto 0);
y_o : out std_logic_vector(g_width-1 downto 0);
q_o : out std_logic_vector(g_width-1 downto 0);
sum_o : out std_logic_vector(g_width-1 downto 0)
);
end entity delta_sigma;
-------------------------------------------------------------------------------
architecture str of delta_sigma is
signal x_pre : std_logic_vector(g_width-1 downto 0);
signal y_pre : std_logic_vector(g_width-1 downto 0);
signal q_pre : std_logic_vector(g_width-1 downto 0);
signal sigma : std_logic_vector(g_width-1 downto 0);
signal valid_pre : std_logic;
signal x_pos : std_logic_vector(g_width-1 downto 0);
signal x_rdo : std_logic;
signal y_pos : std_logic_vector(g_width-1 downto 0);
signal y_rdo : std_logic;
signal q_pos : std_logic_vector(g_width-1 downto 0);
signal q_rdo : std_logic;
signal x_scaled : std_logic_vector(g_width-1 downto 0);
signal y_scaled : std_logic_vector(g_width-1 downto 0);
signal q_scaled : std_logic_vector(g_width-1 downto 0);
signal sigma_scaled : std_logic_vector(g_width-1 downto 0);
signal valid_scaled : std_logic;
begin -- architecture str
cmp_first_stage : ds_first_stage
generic map (
g_width => g_width)
port map (
a_i => a_i,
b_i => b_i,
c_i => c_i,
d_i => d_i,
clk_i => clk_i,
valid_i => valid_i,
valid_o => valid_pre,
ce_i => ce_i,
x_o => x_pre,
y_o => y_pre,
q_o => q_pre,
sum_o => sigma);
-- x_pos, y_pos and q_pos are all G_PRECISION+1 bits width the
-- MSB being the sign bit and the decimal point right next to it.
--
-- Example: x31 . x30 x29 ... x0
--
-- sign bit = x31
-- decimal point = between x31 and x30
cmp_divider_x : div_fixedpoint
generic map (
G_DATAIN_WIDTH => g_width,
G_PRECISION => g_width-1)
port map (
clk_i => clk_i,
rst_i => rst_i,
ce_i => ce_i,
n_i => x_pre,
d_i => sigma,
q_o => x_pos,
r_o => open,
trg_i => valid_pre,
rdy_o => x_rdo,
err_o => open);
cmp_divider_y : div_fixedpoint
generic map (
G_DATAIN_WIDTH => g_width,
G_PRECISION => g_width-1)
port map (
clk_i => clk_i,
rst_i => rst_i,
ce_i => ce_i,
n_i => y_pre,
d_i => sigma,
q_o => y_pos,
r_o => open,
trg_i => valid_pre,
rdy_o => y_rdo,
err_o => open);
cmp_divider_q : div_fixedpoint
generic map (
G_DATAIN_WIDTH => g_width,
G_PRECISION => g_width-1)
port map (
clk_i => clk_i,
rst_i => rst_i,
ce_i => ce_i,
n_i => q_pre,
d_i => sigma,
q_o => q_pos,
r_o => open,
trg_i => valid_pre,
rdy_o => q_rdo,
err_o => open);
-- x, y and q are multipled by K factors which are
-- g_k_width bits (integer), so the decimal point
-- is shifted to the right by that same amount.
cmp_k_scaling : ds_k_scaling
generic map (
g_width => g_width,
g_k_width => g_k_width)
port map (
x_i => x_pos,
kx_i => kx_i,
x_valid_i => x_rdo,
y_i => y_pos,
ky_i => ky_i,
y_valid_i => y_rdo,
q_i => q_pos,
q_valid_i => q_rdo,
sum_i => sigma,
ksum_i => ksum_i,
sum_valid_i => valid_pre,
clk_i => clk_i,
ce_i => ce_i,
x_o => x_scaled,
y_o => y_scaled,
q_o => q_scaled,
sum_o => sigma_scaled,
valid_o => valid_scaled);
cmp_offset : ds_offset_scaling
generic map (
g_width => g_width,
g_precision => g_width-g_k_width,
g_offset_width => g_offset_width,
g_offset_precision => 0)
port map (
clk_i => clk_i,
ce_i => ce_i,
x_i => x_scaled,
y_i => y_scaled,
q_i => q_scaled,
sum_i => sigma_scaled,
valid_i => valid_scaled,
offset_x_i => offset_x_i,
offset_y_i => offset_y_i,
x_o => x_o,
y_o => y_o,
q_o => q_o,
sum_o => sum_o,
valid_o => valid_o);
end architecture str;
-------------------------------------------------------------------------------
| lgpl-3.0 | dc03da5ce71ce90dfe1bb77f6decfe25 | 0.494688 | 3.069054 | false | false | false | false |
JarrettR/FPGA-Cryptoparty | FPGA/hdl/ipcore_dir/fx2_fifo/simulation/fx2_fifo_pkg.vhd | 1 | 11,350 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fx2_fifo_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fx2_fifo_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fx2_fifo_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fx2_fifo_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fx2_fifo_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fx2_fifo_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fx2_fifo_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fx2_fifo_exdes IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(8-1 DOWNTO 0);
DOUT : OUT std_logic_vector(8-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fx2_fifo_pkg;
PACKAGE BODY fx2_fifo_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fx2_fifo_pkg;
| gpl-3.0 | 69848551a3b26bea4d7a880666dc47f7 | 0.504934 | 3.920553 | false | false | false | false |
TUM-LIS/faultify | hardware/testcases/QR/fpga_sim/xpsLibraryPath_asic_400_599/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/vhdl/faultify_top.vhd | 4 | 20,823 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.qr_pack.all;
entity faultify_top is
generic (
numInj : integer := 56;
numIn : integer := 10;
numOut : integer := 10);
port (
aclk : in std_logic; -- interface clock
arst_n : in std_logic; -- interface reset
clk : in std_logic; -- simulation clock (slow)
clk_x32 : in std_logic; -- prng clock (fast)
-- Write channel
awvalid : in std_logic;
awaddr : in std_logic_vector(31 downto 0);
wvalid : in std_logic;
wdata : in std_logic_vector(31 downto 0);
-- Read channel
arvalid : in std_logic;
araddr : in std_logic_vector(31 downto 0);
rvalid : out std_logic;
rdata : out std_logic_vector(31 downto 0)
);
attribute syn_hier : string;
attribute syn_hier of faultify_top : entity is "hard";
end faultify_top;
architecture behav of faultify_top is
component qr_wrapper_wrapper_stimuli is
port (
clk : in std_logic;
rst_n : in std_logic;
reduced_matrix : out std_logic;
start : out std_logic;
request_out : out std_logic;
valid_out : in std_logic;
ready : in std_logic;
in_A_r : out std_logic_vector(N_G*WORD_WIDTH_G - 1 downto 0);
in_A_i : out std_logic_vector(N_G*WORD_WIDTH_G - 1 downto 0));
end component qr_wrapper_wrapper_stimuli;
component flag_cdc
port (
clkA : in std_logic;
clkB : in std_logic;
FlagIn_clkA : in std_logic;
FlagOut_clkB : out std_logic;
rst_n : in std_logic);
end component;
component faultify_simulator
generic (
numInj : integer;
numIn : integer;
numOut : integer);
port (
clk : in std_logic;
clk_m : in std_logic;
circ_ce : in std_logic;
circ_rst : in std_logic;
test : out std_logic_vector(31 downto 0);
testvector : in std_logic_vector(numIn-1 downto 0);
resultvector_o : out std_logic_vector(numOut-1 downto 0);
resultvector_f : out std_logic_vector(numOut-1 downto 0);
seed_in_en : in std_logic;
seed_in : in std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
shift_en : in std_logic;
rst_n : in std_logic);
end component;
component lfsr
generic (
width : integer;
seed : integer);
port (
clk : in std_logic;
rand_out : out std_logic_vector(width-1 downto 0));
end component;
type vector is array (0 to numOut-1) of std_logic_vector(31 downto 0);
signal errorSum : vector;
signal errorSumReg : vector;
signal errorSumReg_cdc_0 : vector;
signal errorSumReg_cdc_1 : vector;
signal errorVec : std_logic_vector(numOut-1 downto 0);
signal cnt : integer;
signal cnt_cdc_0 : integer;
signal cnt_cdc_1 : integer;
-- Asymmetric ram larger than 36 bit not supported in synplify I-2013
--type seed_ram_matr is array (0 to numInj-1) of std_logic_vector(63 downto 0);
--signal seed_ram : seed_ram_matr;
-- workaround 2 32-bit rams
type seed_ram_matr is array (0 to numInj-1) of std_logic_vector(31 downto 0);
signal seed_ram_low : seed_ram_matr;
signal seed_ram_high : seed_ram_matr;
--subtype seed_ram_matr_word_t is std_logic_vector(63 downto 0);
--type seed_ram_matr_memory_t is array (0 to numInj-1) of seed_ram_matr_word_t;
--signal seed_ram : seed_ram_matr_memory_t;
type prob_ram_matr is array (0 to numInj-1) of std_logic_vector(31 downto 0);
signal prob_ram : prob_ram_matr;
type reg_type is record
control : std_logic_vector(31 downto 0);
status : std_logic_vector(31 downto 0);
pe_location : std_logic_vector(31 downto 0);
pe_seed_low : std_logic_vector(31 downto 0);
pe_seed_high : std_logic_vector(31 downto 0);
pe_probability : std_logic_vector(31 downto 0);
output : std_logic_vector(31 downto 0);
ovalid : std_logic;
simtime : std_logic_vector(31 downto 0);
sel_soe : std_logic_vector(31 downto 0);
adr_soe : std_logic_vector(31 downto 0);
awaddr : std_logic_vector(31 downto 0);
test : std_logic_vector(31 downto 0);
circreset : std_logic_vector(31 downto 0);
cnt_tmp : std_logic_vector(31 downto 0);
sumoferrors : vector;
end record;
signal busy_loading : std_logic;
signal busy_simulating : std_logic;
signal busy_loading_reg : std_logic_vector(1 downto 0);
signal busy_simulating_reg : std_logic_vector(1 downto 0);
signal sim_done : std_logic;
signal r : reg_type;
type load_fsm_states is (IDLE, LOADSEED, LOADPROB);
signal l_state : load_fsm_states;
type sim_states is (IDLE, DELAY_Z, DELAY, SIMULATION, DELAY2, DELAY3, DELAY4, FREE_SIMULATION);
signal s_state : sim_states;
signal testvector : std_logic_vector(numIn-1 downto 0);
signal resultvector_o : std_logic_vector(numOut-1 downto 0);
signal resultvector_f : std_logic_vector(numOut-1 downto 0);
signal seed_in_en : std_logic;
signal seed_in : std_logic;
signal prob_in_en : std_logic;
signal prob_in : std_logic;
signal shift_en : std_logic;
signal shift_en_l : std_logic;
signal shift_en_s : std_logic;
signal load_seed_prob : std_logic;
signal start_simulation : std_logic;
signal start_free_simulation : std_logic;
signal stop_simulation : std_logic;
signal circ_ce, circ_rst, circ_rst_sim : std_logic;
signal tvec : std_logic_vector(127 downto 0);
signal test : std_logic_vector(31 downto 0);
signal rst_cdc, rst_cdc_n : std_logic;
begin -- behav
-----------------------------------------------------------------------------
-- PRNG shifting
-----------------------------------------------------------------------------
shift_en <= shift_en_l or shift_en_s;
-----------------------------------------------------------------------------
-- Testvector
-----------------------------------------------------------------------------
qr_wrapper_wrapper_stimuli_1 : qr_wrapper_wrapper_stimuli
port map (
clk => clk,
rst_n => not circ_rst,
reduced_matrix => testvector(0),
start => testvector(1),
request_out => testvector(2),
valid_out => resultvector_o(0),
ready => resultvector_o(1),
in_A_r => testvector(50 downto 3),
in_A_i => testvector(98 downto 51));
testvector(110 downto 99) <= (others => '0');
-----------------------------------------------------------------------------
-- Simulator
-----------------------------------------------------------------------------
circ_rst <= circ_rst_sim when r.circreset(0) = '1' else '0';
faultify_simulator_1 : faultify_simulator
generic map (
numInj => numInj,
numIn => numIn,
numOut => numOut)
port map (
clk => clk_x32,
clk_m => clk,
circ_ce => circ_ce,
circ_rst => circ_rst,
test => test,
testvector => testvector,
resultvector_o => resultvector_o,
resultvector_f => resultvector_f,
seed_in_en => seed_in_en,
seed_in => seed_in,
prob_in_en => prob_in_en,
prob_in => prob_in,
shift_en => shift_en,
rst_n => arst_n);
-------------------------------------------------------------------------------
-- One Process Flow
-------------------------------------------------------------------------------
register_process : process (aclk, arst_n)
variable write_addr : std_logic_vector(31 downto 0);
begin -- process register_process
if arst_n = '0' then -- asynchronous reset (active low)
r.control <= (others => '0');
r.status <= (others => '0');
r.pe_probability <= (others => '0');
r.pe_seed_high <= (others => '0');
r.pe_seed_low <= (others => '0');
r.pe_location <= (others => '0');
r.ovalid <= '0';
r.simtime <= (others => '0');
r.sel_soe <= (others => '0');
r.adr_soe <= (others => '0');
r.sumoferrors <= (others => (others => '0'));
r.output <= (others => '0');
elsif aclk'event and aclk = '1' then -- rising clock edge
r.control <= (others => '0');
if awvalid = '1' then
r.awaddr <= awaddr;
write_addr := awaddr;
end if;
if wvalid = '1' then
if write_addr = x"00000000" then
r.control <= wdata;
elsif write_addr = x"00000001" then
r.pe_location <= wdata;
elsif write_addr = x"00000002" then
r.pe_seed_low <= wdata;
elsif write_addr = x"00000003" then
r.pe_seed_high <= wdata;
elsif write_addr = x"00000004" then
r.pe_probability <= wdata;
elsif write_addr = x"00000005" then
r.cnt_tmp <= std_logic_vector(to_unsigned(cnt_cdc_1, 32));
r.adr_soe <= wdata;
elsif write_addr = x"00000007" then
r.simtime <= wdata;
elsif write_addr = x"00000009" then
r.circreset <= wdata;
end if;
end if;
if arvalid = '1' then
if araddr = x"0000000F" then
r.output <= r.status;
elsif araddr = x"00000001" then
r.output <= r.pe_location;
elsif araddr = x"00000002" then
r.output <= r.pe_seed_low;
elsif araddr = x"00000003" then
r.output <= r.pe_seed_high;
elsif araddr = x"00000004" then
r.output <= r.pe_probability;
elsif araddr = x"00000006" then
r.output <= r.sel_soe;
elsif araddr = x"00000008" then
r.output <= r.test;
elsif araddr = x"0000000A" then
r.output <= r.cnt_tmp;
end if;
r.ovalid <= '1';
else
r.ovalid <= '0';
end if;
if busy_loading_reg(1) = '1' then
r.status(0) <= '1';
else
r.status(0) <= '0';
end if;
if busy_simulating_reg(1) = '1' then
r.status(1) <= '1';
else
r.status(1) <= '0';
end if;
r.sel_soe <= r.sumoferrors(to_integer(unsigned(r.adr_soe)));
rdata <= r.output;
rvalid <= r.ovalid;
r.sumoferrors <= errorSumReg_cdc_1;
r.test <= errorSum(0);
end if;
end process register_process;
-----------------------------------------------------------------------------
-- simple clock domain crossing
-----------------------------------------------------------------------------
process (aclk, arst_n)
begin -- process
if arst_n = '0' then -- asynchronous reset (active low)
busy_simulating_reg <= (others => '0');
busy_loading_reg <= (others => '0');
elsif aclk'event and aclk = '1' then -- rising clock edge
busy_simulating_reg(0) <= busy_simulating;
busy_loading_reg(0) <= busy_loading;
busy_simulating_reg(1) <= busy_simulating_reg(0);
busy_loading_reg(1) <= busy_loading_reg(0);
cnt_cdc_0 <= cnt;
cnt_cdc_1 <= cnt_cdc_0;
errorSumReg_cdc_0 <= errorSumReg;
errorSumReg_cdc_1 <= errorSumReg_cdc_0;
end if;
end process;
-------------------------------------------------------------------------------
-- Store seeed/prob
-------------------------------------------------------------------------------
store_seed : process (aclk, arst_n)
begin -- process store_seed
if arst_n = '0' then -- asynchronous reset (active low)
elsif aclk'event and aclk = '1' then -- rising clock edge
if r.control(0) = '1' then
-- Synplify bug workaround
--seed_ram(to_integer(unsigned(r.pe_location))) <= r.pe_seed_high & r.pe_seed_low;
seed_ram_low(to_integer(unsigned(r.pe_location))) <= r.pe_seed_low;
seed_ram_high(to_integer(unsigned(r.pe_location))) <= r.pe_seed_high;
prob_ram(to_integer(unsigned(r.pe_location))) <= r.pe_probability;
end if;
end if;
end process store_seed;
-----------------------------------------------------------------------------
-- Seed/prob loading FSM
-----------------------------------------------------------------------------
--flag_cdc_1 : flag_cdc
-- port map (
-- clkA => aclk,
-- clkB => clk_x32,
-- FlagIn_clkA => r.control(1),
-- FlagOut_clkB => load_seed_prob,
-- rst_n => arst_n);
load_seed_prob <= r.control(1);
seed_prob_loading : process (clk_x32, arst_n)
variable cnt_seed : integer range 0 to 64;
variable cnt_inj : integer range 0 to numInj;
variable cnt_prob : integer range 0 to 32;
begin -- process seed_prob_loading
if arst_n = '0' then -- asynchronous reset (active low)
l_state <= IDLE;
seed_in <= '0';
seed_in_en <= '0';
prob_in <= '0';
prob_in_en <= '0';
shift_en_l <= '0';
busy_loading <= '0';
elsif clk_x32'event and clk_x32 = '1' then -- rising clock edge
case l_state is
when IDLE =>
cnt_seed := 0;
cnt_inj := 0;
cnt_prob := 0;
busy_loading <= '0';
seed_in_en <= '0';
prob_in_en <= '0';
shift_en_l <= '0';
if load_seed_prob = '1' then
busy_loading <= '1';
l_state <= LOADSEED;
end if;
when LOADSEED =>
if cnt_seed < 64 then
shift_en_l <= '1';
seed_in_en <= '1';
-- not working in synplify I-2013
--seed_in <= seed_ram(cnt_inj)(cnt_seed);
--
if cnt_seed < 32 then
seed_in <= seed_ram_low(cnt_inj)(cnt_seed);
else
seed_in <= seed_ram_high(cnt_inj)(cnt_seed-32);
end if;
cnt_seed := cnt_seed + 1;
end if;
if cnt_seed = 64 then
cnt_seed := 0;
cnt_inj := cnt_inj + 1;
end if;
if cnt_inj = numInj then
l_state <= LOADPROB;
--seed_in_en <= '0';
cnt_inj := 0;
end if;
when LOADPROB =>
seed_in_en <= '0';
if cnt_prob < 32 then
prob_in_en <= '1';
prob_in <= prob_ram(cnt_inj)(cnt_prob);
cnt_prob := cnt_prob + 1;
end if;
if cnt_prob = 32 then
cnt_prob := 0;
cnt_inj := cnt_inj + 1;
end if;
if cnt_inj = numInj then
l_state <= IDLE;
cnt_inj := 0;
--prob_in_en <= '0';
end if;
end case;
end if;
end process seed_prob_loading;
-----------------------------------------------------------------------------
-- Simulation FSM
-----------------------------------------------------------------------------
flag_cdc_2 : flag_cdc
port map (
clkA => aclk,
clkB => clk,
FlagIn_clkA => r.control(2),
FlagOut_clkB => start_simulation,
rst_n => arst_n);
flag_cdc_3 : flag_cdc
port map (
clkA => aclk,
clkB => clk,
FlagIn_clkA => r.control(3),
FlagOut_clkB => start_free_simulation,
rst_n => arst_n);
flag_cdc_4 : flag_cdc
port map (
clkA => aclk,
clkB => clk,
FlagIn_clkA => r.control(4),
FlagOut_clkB => stop_simulation,
rst_n => arst_n);
rst_cdc_5 : flag_cdc
port map (
clkA => aclk,
clkB => clk,
FlagIn_clkA => not arst_n,
FlagOut_clkB => rst_cdc,
rst_n => '1');
rst_cdc_n <= not rst_cdc;
process (clk, rst_cdc_n)
variable simtime : integer;
variable cnt_delay : integer range 0 to 9;
begin -- process
if clk'event and clk = '1' then -- rising clock edge
if rst_cdc_n = '0' then -- asynchronous reset (active low)
s_state <= IDLE;
errorVec <= (others => '0');
errorSum <= (others => (others => '0'));
circ_ce <= '0';
circ_rst_sim <= '1';
shift_en_s <= '0';
busy_simulating <= '0';
sim_done <= '0';
errorSumReg <= (others => (others => '0'));
else
case s_state is
when IDLE =>
sim_done <= '0';
circ_ce <= '0';
circ_rst_sim <= '1';
shift_en_s <= '0';
errorVec <= (others => '0');
--errorSum <= errorSum;
errorSum <= (others => (others => '0'));
--cnt <= 0;
busy_simulating <= '0';
cnt_delay := 0;
if start_simulation = '1' then
cnt <= 0;
busy_simulating <= '1';
errorSum <= (others => (others => '0'));
errorSumReg <= (others => (others => '0'));
simtime := to_integer(unsigned(r.simtime));
s_state <= DELAY_Z;
circ_ce <= '1';
circ_rst_sim <= '0';
shift_en_s <= '1';
end if;
if start_free_simulation = '1' then
cnt <= 0;
busy_simulating <= '1';
errorSum <= (others => (others => '0'));
errorSumReg <= (others => (others => '0'));
s_state <= FREE_SIMULATION;
circ_ce <= '1';
circ_rst_sim <= '0';
shift_en_s <= '1';
end if;
when DELAY_z =>
cnt_delay := cnt_delay + 1;
if cnt_delay = 9 then
s_state <= DELAY;
end if;
when DELAY =>
s_state <= SIMULATION;
errorVec <= (others => '0');
errorSum <= (others => (others => '0'));
when SIMULATION =>
circ_rst_sim <= '0';
shift_en_s <= '1';
-- collect errors
if (resultvector_o(0) = '1') then
errorVec <= resultvector_o xor resultvector_f;
else
errorVec <= (others => '0');
end if;
for i in 0 to (numOut-1) loop
if (errorVec(i) = '1') then
errorSum(i) <= std_logic_vector(unsigned(errorSum(i)) + 1);
end if;
end loop;
--
errorSumReg <= errorSum;
if cnt = simtime-1 then
s_state <= DELAY2;
circ_ce <= '0';
circ_rst_sim <= '1';
shift_en_s <= '0';
end if;
cnt <= cnt +1;
when DELAY2 =>
--errorVec <= resultvector_o xor resultvector_f;
--for i in 0 to (numOut-1) loop
-- if (errorVec(i) = '1') then
-- if (resultvector_o(0) = '1') then
-- errorSum(i) <= std_logic_vector(unsigned(errorSum(i)) + 1);
-- end if;
-- end if;
--end loop;
s_state <= DELAY3;
when DELAY3 =>
s_state <= DELAY4;
errorSumReg <= errorSum;
errorSum <= (others => (others => '0'));
when DELAY4 =>
s_state <= IDLE;
sim_done <= '1';
when FREE_SIMULATION =>
circ_rst_sim <= '0';
shift_en_s <= '1';
-- collect errors
errorVec <= resultvector_o xor resultvector_f;
for i in 0 to (numOut-1) loop
if (errorVec(i) = '1') then
errorSum(i) <= std_logic_vector(unsigned(errorSum(i)) + 1);
end if;
end loop;
--
errorSumReg <= errorSum;
if stop_simulation = '1' then
s_state <= IDLE;
sim_done <= '1';
circ_ce <= '0';
circ_rst_sim <= '1';
shift_en_s <= '0';
end if;
cnt <= cnt +1;
when others =>
s_state <= IDLE;
end case;
end if;
end if;
end process;
end behav;
| gpl-2.0 | 858b1e09e186038e5bacc9d7c8b525b1 | 0.464342 | 3.817932 | false | false | false | false |
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