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scottlbaker/PDP11-SOC
src/cmpr.vhd
1
1,149
--======================================================================== -- cmpr.vhd :: 4-bit comparator -- -- (c) Scott L. Baker, Sierra Circuit Design --======================================================================== library IEEE; use IEEE.std_logic_1164.all; entity CMPR is port ( A_LE_B : out std_logic; -- A <= B A : in std_logic_vector(3 downto 0); -- operand A B : in std_logic_vector(3 downto 0) -- operand B ); end CMPR; architecture BEHAVIORAL of CMPR is signal P : std_logic_vector(3 downto 0); signal G : std_logic_vector(3 downto 0); signal CX : std_logic_vector(3 downto 1); begin --===================================== -- Propagate and Generate --===================================== G <= (not A(3 downto 0)) and B(3 downto 0); P <= (not A(3 downto 0)) or B(3 downto 0); A_LE_B <= G(3) or (P(3) and CX(3)); CX(3) <= G(2) or (P(2) and CX(2)); CX(2) <= G(1) or (P(1) and CX(1)); CX(1) <= G(0) or P(0); end BEHAVIORAL;
gpl-3.0
772ec4a5a867dd763ff66a9c5dffa5ea
0.392515
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OrganicMonkeyMotion/fpga_experiments
small_board/LABS/digital_logic/vhdl/lab2/part5/lpm_constant3.vhd
1
3,509
-- megafunction wizard: %LPM_CONSTANT% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: LPM_CONSTANT -- ============================================================ -- File Name: lpm_constant3.vhd -- Megafunction Name(s): -- LPM_CONSTANT -- -- Simulation Library Files(s): -- lpm -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition -- ************************************************************ --Copyright (C) 1991-2011 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.all; ENTITY lpm_constant3 IS PORT ( result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) ); END lpm_constant3; ARCHITECTURE SYN OF lpm_constant3 IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0); COMPONENT lpm_constant GENERIC ( lpm_cvalue : NATURAL; lpm_hint : STRING; lpm_type : STRING; lpm_width : NATURAL ); PORT ( result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) ); END COMPONENT; BEGIN result <= sub_wire0(0 DOWNTO 0); LPM_CONSTANT_component : LPM_CONSTANT GENERIC MAP ( lpm_cvalue => 0, lpm_hint => "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=I0", lpm_type => "LPM_CONSTANT", lpm_width => 1 ) PORT MAP ( result => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1" -- Retrieval info: PRIVATE: JTAG_ID STRING "I0" -- Retrieval info: PRIVATE: Radix NUMERIC "2" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: Value NUMERIC "0" -- Retrieval info: PRIVATE: nBit NUMERIC "1" -- Retrieval info: PRIVATE: new_diagram STRING "1" -- Retrieval info: LIBRARY: lpm lpm.lpm_components.all -- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0" -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=I0" -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1" -- Retrieval info: USED_PORT: result 0 0 1 0 OUTPUT NODEFVAL "result[0..0]" -- Retrieval info: CONNECT: result 0 0 1 0 @result 0 0 1 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.bsf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3_inst.vhd FALSE -- Retrieval info: LIB_FILE: lpm
unlicense
d7315d65ec70f688c5f78d333918ce4e
0.646338
3.801733
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OrganicMonkeyMotion/fpga_experiments
small_board/LABS/digital_logic/vhdl/lab2/part6/sweep.vhd
4
562
LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.numeric_std.all; entity sweep is Port ( mclk : in STD_LOGIC; sweep_out : out std_logic_vector(2 downto 0)); end sweep; architecture arch of sweep is signal q: std_logic_vector(11 downto 0); begin --clock divider process(mclk) begin if q = "111111111111" then q <= "000000000000"; elsif mclk'event and mclk = '1' then q <= std_logic_vector(unsigned(q)+1); end if; end process; sweep_out <= q(11)&q(10)&q(9); end arch;
unlicense
48a11f7b3cde5e9696a9423d4dfbdce5
0.594306
3.365269
false
false
false
false
OrganicMonkeyMotion/fpga_experiments
small_board/LABS/digital_logic/vhdl/lab1/part5/M21EDAversion/clkdiv.vhd
1
547
LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.numeric_std.all; entity clkdiv is Port ( mclk : in STD_LOGIC; selout : out std_logic_vector(1 downto 0)); end clkdiv; architecture arch of clkdiv is signal q: std_logic_vector(9 downto 0); begin --clock divider process(mclk) begin if q = "1111111111" then q <= "0000000000"; elsif mclk'event and mclk = '1' then q <= std_logic_vector(unsigned(q)+1); end if; end process; selout <= q(9)&q(8); end arch;
unlicense
7871ca02e6fce6f517c7fd1a4b2019c5
0.592322
3.440252
false
false
false
false
systec-dk/openPOWERLINK_systec
Examples/altera_nios2/SYSTEC_ECUcore-EP3C/design_nios2_directIO/niosII_openMac_burst_0.vhd
3
41,369
--Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your --use of Altera Corporation's design tools, logic functions and other --software and tools, and its AMPP partner logic functions, and any --output files any of the foregoing (including device programming or --simulation files), and any associated documentation or information are --expressly subject to the terms and conditions of the Altera Program --License Subscription Agreement or other applicable license agreement, --including, without limitation, that your use is for the sole purpose --of programming logic devices manufactured by Altera and sold by Altera --or its authorized distributors. Please refer to the applicable --agreement for further details. --synthesis translate_off library altera; use altera.altera_europa_support_lib.all; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity niosII_openMac_burst_0_fifo_module_fifo_ram_module is port ( -- inputs: signal clk : IN STD_LOGIC; signal data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); signal rdaddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0); signal rdclken : IN STD_LOGIC; signal reset_n : IN STD_LOGIC; signal wraddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0); signal wrclock : IN STD_LOGIC; signal wren : IN STD_LOGIC; -- outputs: signal q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ); end entity niosII_openMac_burst_0_fifo_module_fifo_ram_module; architecture europa of niosII_openMac_burst_0_fifo_module_fifo_ram_module is signal internal_q : STD_LOGIC_VECTOR (31 DOWNTO 0); TYPE mem_array is ARRAY( 3 DOWNTO 0) of STD_LOGIC_VECTOR(31 DOWNTO 0); signal read_address : STD_LOGIC_VECTOR (1 DOWNTO 0); begin process (wrclock, clk) -- MG VARIABLE rd_address_internal : STD_LOGIC_VECTOR (1 DOWNTO 0) := (others => '0'); VARIABLE wr_address_internal : STD_LOGIC_VECTOR (1 DOWNTO 0) := (others => '0'); variable Marc_Gaucherons_Memory_Variable : mem_array; -- MG begin -- Write data if wrclock'event and wrclock = '1' then wr_address_internal := wraddress; if wren = '1' then Marc_Gaucherons_Memory_Variable(CONV_INTEGER(UNSIGNED(wr_address_internal))) := data; end if; end if; -- read data q <= Marc_Gaucherons_Memory_Variable(CONV_INTEGER(UNSIGNED(rd_address_internal))); IF clk'event AND clk = '1' AND rdclken = '1' THEN rd_address_internal := rdaddress; END IF; end process; end europa; --synthesis translate_on --synthesis read_comments_as_HDL on --library altera; --use altera.altera_europa_support_lib.all; -- --library ieee; --use ieee.std_logic_1164.all; --use ieee.std_logic_arith.all; --use ieee.std_logic_unsigned.all; -- --entity niosII_openMac_burst_0_fifo_module_fifo_ram_module is -- port ( -- -- signal clk : IN STD_LOGIC; -- signal data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); -- signal rdaddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0); -- signal rdclken : IN STD_LOGIC; -- signal reset_n : IN STD_LOGIC; -- signal wraddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0); -- signal wrclock : IN STD_LOGIC; -- signal wren : IN STD_LOGIC; -- -- -- signal q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) -- ); --end entity niosII_openMac_burst_0_fifo_module_fifo_ram_module; -- -- --architecture europa of niosII_openMac_burst_0_fifo_module_fifo_ram_module is -- component lpm_ram_dp is --GENERIC ( -- lpm_file : STRING; -- lpm_hint : STRING; -- lpm_indata : STRING; -- lpm_outdata : STRING; -- lpm_rdaddress_control : STRING; -- lpm_width : NATURAL; -- lpm_widthad : NATURAL; -- lpm_wraddress_control : STRING; -- suppress_memory_conversion_warnings : STRING -- ); -- PORT ( -- signal q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); -- signal rdaddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0); -- signal wren : IN STD_LOGIC; -- signal rdclock : IN STD_LOGIC; -- signal wrclock : IN STD_LOGIC; -- signal wraddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0); -- signal data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); -- signal rdclken : IN STD_LOGIC -- ); -- end component lpm_ram_dp; -- signal internal_q : STD_LOGIC_VECTOR (31 DOWNTO 0); -- TYPE mem_array is ARRAY( 3 DOWNTO 0) of STD_LOGIC_VECTOR(31 DOWNTO 0); -- signal read_address : STD_LOGIC_VECTOR (1 DOWNTO 0); -- --begin -- -- process (rdaddress) -- begin -- read_address <= rdaddress; -- -- end process; -- -- lpm_ram_dp_component : lpm_ram_dp -- generic map( -- lpm_file => "UNUSED", -- lpm_hint => "USE_EAB=OFF", -- lpm_indata => "REGISTERED", -- lpm_outdata => "UNREGISTERED", -- lpm_rdaddress_control => "REGISTERED", -- lpm_width => 32, -- lpm_widthad => 2, -- lpm_wraddress_control => "REGISTERED", -- suppress_memory_conversion_warnings => "ON" -- ) -- port map( -- data => data, -- q => internal_q, -- rdaddress => read_address, -- rdclken => rdclken, -- rdclock => clk, -- wraddress => wraddress, -- wrclock => wrclock, -- wren => wren -- ); -- -- -- q <= internal_q; --end europa; -- --synthesis read_comments_as_HDL off -- turn off superfluous VHDL processor warnings -- altera message_level Level1 -- altera message_off 10034 10035 10036 10037 10230 10240 10030 -- turn off superfluous VHDL processor warnings -- altera message_level Level1 -- altera message_off 10034 10035 10036 10037 10230 10240 10030 library altera; use altera.altera_europa_support_lib.all; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity niosII_openMac_burst_0_fifo_module is port ( -- inputs: signal clk : IN STD_LOGIC; signal clk_en : IN STD_LOGIC; signal fifo_read : IN STD_LOGIC; signal fifo_wr_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); signal fifo_write : IN STD_LOGIC; signal flush_fifo : IN STD_LOGIC; signal inc_pending_data : IN STD_LOGIC; signal reset_n : IN STD_LOGIC; -- outputs: signal fifo_datavalid : OUT STD_LOGIC; signal fifo_empty : OUT STD_LOGIC; signal fifo_full : OUT STD_LOGIC; signal fifo_rd_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); signal p1_fifo_empty : OUT STD_LOGIC ); end entity niosII_openMac_burst_0_fifo_module; architecture europa of niosII_openMac_burst_0_fifo_module is component niosII_openMac_burst_0_fifo_module_fifo_ram_module is port ( -- inputs: signal clk : IN STD_LOGIC; signal data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); signal rdaddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0); signal rdclken : IN STD_LOGIC; signal reset_n : IN STD_LOGIC; signal wraddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0); signal wrclock : IN STD_LOGIC; signal wren : IN STD_LOGIC; -- outputs: signal q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ); end component niosII_openMac_burst_0_fifo_module_fifo_ram_module; signal estimated_rdaddress : STD_LOGIC_VECTOR (1 DOWNTO 0); signal estimated_wraddress : STD_LOGIC_VECTOR (1 DOWNTO 0); signal fifo_dec : STD_LOGIC; signal fifo_inc : STD_LOGIC; signal fifo_ram_q : STD_LOGIC_VECTOR (31 DOWNTO 0); signal internal_fifo_empty : STD_LOGIC; signal internal_fifo_full : STD_LOGIC; signal internal_p1_fifo_empty : STD_LOGIC; signal last_write_collision : STD_LOGIC; signal last_write_data : STD_LOGIC_VECTOR (31 DOWNTO 0); signal module_input : STD_LOGIC; signal p1_estimated_wraddress : STD_LOGIC_VECTOR (1 DOWNTO 0); signal p1_fifo_full : STD_LOGIC; signal p1_wraddress : STD_LOGIC_VECTOR (1 DOWNTO 0); signal rdaddress : STD_LOGIC_VECTOR (1 DOWNTO 0); signal rdaddress_reg : STD_LOGIC_VECTOR (1 DOWNTO 0); signal wraddress : STD_LOGIC_VECTOR (1 DOWNTO 0); signal write_collision : STD_LOGIC; begin p1_wraddress <= A_EXT (A_WE_StdLogicVector((std_logic'((fifo_write)) = '1'), ((std_logic_vector'("0000000000000000000000000000000") & (wraddress)) - std_logic_vector'("000000000000000000000000000000001")), (std_logic_vector'("0000000000000000000000000000000") & (wraddress))), 2); process (clk, reset_n) begin if reset_n = '0' then wraddress <= std_logic_vector'("00"); elsif clk'event and clk = '1' then if std_logic'(clk_en) = '1' then if std_logic'(flush_fifo) = '1' then wraddress <= std_logic_vector'("00"); else wraddress <= p1_wraddress; end if; end if; end if; end process; rdaddress <= A_EXT (A_WE_StdLogicVector((std_logic'(flush_fifo) = '1'), std_logic_vector'("000000000000000000000000000000000"), A_WE_StdLogicVector((std_logic'(fifo_read) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (rdaddress_reg)) - std_logic_vector'("000000000000000000000000000000001"))), (std_logic_vector'("0000000000000000000000000000000") & (rdaddress_reg)))), 2); process (clk, reset_n) begin if reset_n = '0' then rdaddress_reg <= std_logic_vector'("00"); elsif clk'event and clk = '1' then rdaddress_reg <= rdaddress; end if; end process; fifo_datavalid <= NOT internal_fifo_empty; fifo_inc <= fifo_write AND NOT fifo_read; fifo_dec <= fifo_read AND NOT fifo_write; estimated_rdaddress <= A_EXT (((std_logic_vector'("0000000000000000000000000000000") & (rdaddress_reg)) - std_logic_vector'("000000000000000000000000000000001")), 2); p1_estimated_wraddress <= A_EXT (A_WE_StdLogicVector((std_logic'((inc_pending_data)) = '1'), ((std_logic_vector'("0000000000000000000000000000000") & (estimated_wraddress)) - std_logic_vector'("000000000000000000000000000000001")), (std_logic_vector'("0000000000000000000000000000000") & (estimated_wraddress))), 2); process (clk, reset_n) begin if reset_n = '0' then estimated_wraddress <= A_REP(std_logic'('1'), 2); elsif clk'event and clk = '1' then if std_logic'(clk_en) = '1' then if std_logic'(flush_fifo) = '1' then estimated_wraddress <= A_REP(std_logic'('1'), 2); else estimated_wraddress <= p1_estimated_wraddress; end if; end if; end if; end process; internal_p1_fifo_empty <= flush_fifo OR ((((NOT fifo_inc AND internal_fifo_empty)) OR ((fifo_dec AND to_std_logic(((wraddress = estimated_rdaddress))))))); process (clk, reset_n) begin if reset_n = '0' then internal_fifo_empty <= std_logic'('1'); elsif clk'event and clk = '1' then if std_logic'(clk_en) = '1' then internal_fifo_empty <= internal_p1_fifo_empty; end if; end if; end process; p1_fifo_full <= NOT flush_fifo AND ((((NOT fifo_dec AND internal_fifo_full)) OR ((inc_pending_data AND to_std_logic(((estimated_wraddress = rdaddress))))))); process (clk, reset_n) begin if reset_n = '0' then internal_fifo_full <= std_logic'('0'); elsif clk'event and clk = '1' then if std_logic'(clk_en) = '1' then internal_fifo_full <= p1_fifo_full; end if; end if; end process; write_collision <= fifo_write AND to_std_logic(((wraddress = rdaddress))); process (clk, reset_n) begin if reset_n = '0' then last_write_data <= std_logic_vector'("00000000000000000000000000000000"); elsif clk'event and clk = '1' then if std_logic'(write_collision) = '1' then last_write_data <= fifo_wr_data; end if; end if; end process; process (clk, reset_n) begin if reset_n = '0' then last_write_collision <= std_logic'('0'); elsif clk'event and clk = '1' then if std_logic'(write_collision) = '1' then last_write_collision <= Vector_To_Std_Logic(-SIGNED(std_logic_vector'("00000000000000000000000000000001"))); elsif std_logic'(fifo_read) = '1' then last_write_collision <= std_logic'('0'); end if; end if; end process; fifo_rd_data <= A_WE_StdLogicVector((std_logic'(last_write_collision) = '1'), last_write_data, fifo_ram_q); --niosII_openMac_burst_0_fifo_module_fifo_ram, which is an e_ram niosII_openMac_burst_0_fifo_module_fifo_ram : niosII_openMac_burst_0_fifo_module_fifo_ram_module port map( q => fifo_ram_q, clk => clk, data => fifo_wr_data, rdaddress => rdaddress, rdclken => module_input, reset_n => reset_n, wraddress => wraddress, wrclock => clk, wren => fifo_write ); module_input <= std_logic'('1'); --vhdl renameroo for output signals fifo_empty <= internal_fifo_empty; --vhdl renameroo for output signals fifo_full <= internal_fifo_full; --vhdl renameroo for output signals p1_fifo_empty <= internal_p1_fifo_empty; end europa; -- turn off superfluous VHDL processor warnings -- altera message_level Level1 -- altera message_off 10034 10035 10036 10037 10230 10240 10030 library altera; use altera.altera_europa_support_lib.all; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library std; use std.textio.all; -- --Burst adapter parameters: --adapter is mastered by: powerlink_0/MAC_DMA --adapter masters: SRAM_0/avalon_tristate_slave --asp_debug: 0 --byteaddr_width: 23 --ceil_data_width: 32 --data_width: 32 --dbs_shift: -1 --dbs_upstream_burstcount_width: 3 --downstream_addr_shift: 2 --downstream_burstcount_width: 1 --downstream_max_burstcount: 1 --downstream_pipeline: 0 --dynamic_slave: 1 --master_always_burst_max_burst: 0 --master_burst_on_burst_boundaries_only: 0 --master_data_width: 16 --master_interleave: 0 --master_linewrap_bursts: 0 --nativeaddr_width: 21 --slave_always_burst_max_burst: 0 --slave_burst_on_burst_boundaries_only: 0 --slave_interleave: 0 --slave_linewrap_bursts: 0 --upstream_burstcount: upstream_burstcount --upstream_burstcount_width: 3 --upstream_max_burstcount: 4 --zero_address_width: 0 entity niosII_openMac_burst_0 is port ( -- inputs: signal clk : IN STD_LOGIC; signal downstream_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0); signal downstream_readdatavalid : IN STD_LOGIC; signal downstream_waitrequest : IN STD_LOGIC; signal reset_n : IN STD_LOGIC; signal upstream_address : IN STD_LOGIC_VECTOR (22 DOWNTO 0); signal upstream_burstcount : IN STD_LOGIC_VECTOR (2 DOWNTO 0); signal upstream_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0); signal upstream_debugaccess : IN STD_LOGIC; signal upstream_nativeaddress : IN STD_LOGIC_VECTOR (20 DOWNTO 0); signal upstream_read : IN STD_LOGIC; signal upstream_write : IN STD_LOGIC; signal upstream_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0); -- outputs: signal downstream_address : OUT STD_LOGIC_VECTOR (20 DOWNTO 0); signal downstream_arbitrationshare : OUT STD_LOGIC_VECTOR (2 DOWNTO 0); signal downstream_burstcount : OUT STD_LOGIC; signal downstream_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); signal downstream_debugaccess : OUT STD_LOGIC; signal downstream_nativeaddress : OUT STD_LOGIC_VECTOR (20 DOWNTO 0); signal downstream_read : OUT STD_LOGIC; signal downstream_write : OUT STD_LOGIC; signal downstream_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); signal upstream_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); signal upstream_readdatavalid : OUT STD_LOGIC; signal upstream_waitrequest : OUT STD_LOGIC ); end entity niosII_openMac_burst_0; architecture europa of niosII_openMac_burst_0 is component niosII_openMac_burst_0_fifo_module is port ( -- inputs: signal clk : IN STD_LOGIC; signal clk_en : IN STD_LOGIC; signal fifo_read : IN STD_LOGIC; signal fifo_wr_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); signal fifo_write : IN STD_LOGIC; signal flush_fifo : IN STD_LOGIC; signal inc_pending_data : IN STD_LOGIC; signal reset_n : IN STD_LOGIC; -- outputs: signal fifo_datavalid : OUT STD_LOGIC; signal fifo_empty : OUT STD_LOGIC; signal fifo_full : OUT STD_LOGIC; signal fifo_rd_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); signal p1_fifo_empty : OUT STD_LOGIC ); end component niosII_openMac_burst_0_fifo_module; signal address_offset : STD_LOGIC_VECTOR (1 DOWNTO 0); signal atomic_counter : STD_LOGIC; signal current_upstream_address : STD_LOGIC_VECTOR (22 DOWNTO 0); signal current_upstream_burstcount : STD_LOGIC_VECTOR (2 DOWNTO 0); signal current_upstream_read : STD_LOGIC; signal current_upstream_write : STD_LOGIC; signal data_counter : STD_LOGIC_VECTOR (2 DOWNTO 0); signal dbs_adjusted_upstream_burstcount : STD_LOGIC_VECTOR (2 DOWNTO 0); signal downstream_address_base : STD_LOGIC_VECTOR (22 DOWNTO 0); signal downstream_burstdone : STD_LOGIC; signal enable_state_change : STD_LOGIC; signal fifo_datavalid : STD_LOGIC; signal fifo_empty : STD_LOGIC; signal fifo_full : STD_LOGIC; signal fifo_rd_data : STD_LOGIC_VECTOR (31 DOWNTO 0); signal fifo_read : STD_LOGIC; signal fifo_wr_data : STD_LOGIC_VECTOR (31 DOWNTO 0); signal fifo_write : STD_LOGIC; signal flush_fifo : STD_LOGIC; signal full_width_rdv_counter : STD_LOGIC_VECTOR (2 DOWNTO 0); signal internal_downstream_burstcount : STD_LOGIC; signal internal_downstream_byteenable : STD_LOGIC_VECTOR (3 DOWNTO 0); signal internal_downstream_read : STD_LOGIC; signal internal_downstream_write : STD_LOGIC; signal internal_upstream_readdatavalid : STD_LOGIC; signal internal_upstream_waitrequest : STD_LOGIC; signal max_burst_size : STD_LOGIC; signal module_input1 : STD_LOGIC; signal negative_dbs_rdv_counter : STD_LOGIC; signal negative_dbs_read_expression : STD_LOGIC_VECTOR (2 DOWNTO 0); signal p1_atomic_counter : STD_LOGIC; signal p1_fifo_empty : STD_LOGIC; signal p1_state_busy : STD_LOGIC; signal p1_state_idle : STD_LOGIC; signal pending_register_enable : STD_LOGIC; signal pending_upstream_read : STD_LOGIC; signal pending_upstream_read_reg : STD_LOGIC; signal pending_upstream_write : STD_LOGIC; signal pending_upstream_write_reg : STD_LOGIC; signal quantized_burst_base : STD_LOGIC_VECTOR (22 DOWNTO 0); signal quantized_burst_limit : STD_LOGIC_VECTOR (22 DOWNTO 0); signal read_address_offset : STD_LOGIC_VECTOR (1 DOWNTO 0); signal read_update_count : STD_LOGIC; signal read_write_dbs_adjusted_upstream_burstcount : STD_LOGIC_VECTOR (2 DOWNTO 0); signal registered_read_write_dbs_adjusted_upstream_burstcount : STD_LOGIC_VECTOR (2 DOWNTO 0); signal registered_upstream_address : STD_LOGIC_VECTOR (22 DOWNTO 0); signal registered_upstream_burstcount : STD_LOGIC_VECTOR (2 DOWNTO 0); signal registered_upstream_nativeaddress : STD_LOGIC_VECTOR (20 DOWNTO 0); signal registered_upstream_read : STD_LOGIC; signal registered_upstream_write : STD_LOGIC; signal state_busy : STD_LOGIC; signal state_idle : STD_LOGIC; signal sync_nativeaddress : STD_LOGIC; signal transactions_remaining : STD_LOGIC_VECTOR (2 DOWNTO 0); signal transactions_remaining_reg : STD_LOGIC_VECTOR (2 DOWNTO 0); signal update_count : STD_LOGIC; signal upstream_burstdone : STD_LOGIC; signal upstream_read_run : STD_LOGIC; signal upstream_write_run : STD_LOGIC; signal write_address_offset : STD_LOGIC_VECTOR (1 DOWNTO 0); signal write_update_count : STD_LOGIC; begin sync_nativeaddress <= or_reduce(upstream_nativeaddress); --downstream, which is an e_avalon_master --upstream, which is an e_avalon_slave upstream_burstdone <= A_WE_StdLogic((std_logic'(current_upstream_read) = '1'), ((to_std_logic(((transactions_remaining = (std_logic_vector'("00") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount)))))) AND internal_downstream_read) AND NOT downstream_waitrequest), ((to_std_logic((((std_logic_vector'("000000000000000000000000000000") & (transactions_remaining)) = (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(atomic_counter))) + std_logic_vector'("000000000000000000000000000000001")))))) AND internal_downstream_write) AND NOT downstream_waitrequest)); p1_atomic_counter <= Vector_To_Std_Logic(((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(atomic_counter))) + (std_logic_vector'("0") & ((A_WE_StdLogicVector((std_logic'(internal_downstream_read) = '1'), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount))), std_logic_vector'("00000000000000000000000000000001"))))))); downstream_burstdone <= (((internal_downstream_read OR internal_downstream_write)) AND NOT downstream_waitrequest) AND to_std_logic(((std_logic'(p1_atomic_counter) = std_logic'(internal_downstream_burstcount)))); quantized_burst_base <= A_EXT (((std_logic_vector'("000000000") & (upstream_address)) AND NOT std_logic_vector'("00000000000000000000000000000011")), 23); quantized_burst_limit <= A_EXT (((std_logic_vector'("0") & ((((((std_logic_vector'("0") & (((std_logic_vector'("0") & ((((std_logic_vector'("000000000") & (upstream_address)) AND NOT std_logic_vector'("00000000000000000000000000000001"))))) + (std_logic_vector'("00000000000000000000000000000") & ((upstream_burstcount & A_ToStdLogicVector(std_logic'('0')))))))) - std_logic_vector'("0000000000000000000000000000000001"))) OR std_logic_vector'("0000000000000000000000000000000011"))))) + std_logic_vector'("00000000000000000000000000000000001")), 23); negative_dbs_read_expression <= A_EXT (A_SRL((((std_logic_vector'("0") & (quantized_burst_limit)) - (std_logic_vector'("0") & (quantized_burst_base)))),std_logic_vector'("00000000000000000000000000000010")), 3); dbs_adjusted_upstream_burstcount <= A_WE_StdLogicVector((std_logic'(pending_register_enable) = '1'), read_write_dbs_adjusted_upstream_burstcount, registered_read_write_dbs_adjusted_upstream_burstcount); read_write_dbs_adjusted_upstream_burstcount <= A_WE_StdLogicVector((std_logic'(upstream_read) = '1'), negative_dbs_read_expression, upstream_burstcount); process (clk, reset_n) begin if reset_n = '0' then registered_read_write_dbs_adjusted_upstream_burstcount <= std_logic_vector'("000"); elsif clk'event and clk = '1' then if std_logic'(pending_register_enable) = '1' then registered_read_write_dbs_adjusted_upstream_burstcount <= read_write_dbs_adjusted_upstream_burstcount; end if; end if; end process; p1_state_idle <= ((state_idle AND NOT upstream_read) AND NOT upstream_write) OR ((((state_busy AND to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (data_counter)) = std_logic_vector'("00000000000000000000000000000000"))))) AND p1_fifo_empty) AND NOT pending_upstream_read) AND NOT pending_upstream_write); p1_state_busy <= (state_idle AND ((upstream_read OR upstream_write))) OR (state_busy AND ((((to_std_logic(NOT (((std_logic_vector'("00000000000000000000000000000") & (data_counter)) = std_logic_vector'("00000000000000000000000000000000")))) OR NOT p1_fifo_empty) OR pending_upstream_read) OR pending_upstream_write))); enable_state_change <= NOT ((internal_downstream_read OR internal_downstream_write)) OR NOT downstream_waitrequest; process (clk, reset_n) begin if reset_n = '0' then pending_upstream_read_reg <= std_logic'('0'); elsif clk'event and clk = '1' then if std_logic'((upstream_read AND state_idle)) = '1' then pending_upstream_read_reg <= Vector_To_Std_Logic(-SIGNED(std_logic_vector'("00000000000000000000000000000001"))); elsif std_logic'(downstream_readdatavalid) = '1' then pending_upstream_read_reg <= std_logic'('0'); end if; end if; end process; process (clk, reset_n) begin if reset_n = '0' then pending_upstream_write_reg <= std_logic'('0'); elsif clk'event and clk = '1' then if std_logic'(upstream_burstdone) = '1' then pending_upstream_write_reg <= std_logic'('0'); elsif std_logic'((upstream_write AND ((state_idle OR NOT internal_upstream_waitrequest)))) = '1' then pending_upstream_write_reg <= Vector_To_Std_Logic(-SIGNED(std_logic_vector'("00000000000000000000000000000001"))); end if; end if; end process; process (clk, reset_n) begin if reset_n = '0' then state_idle <= std_logic'('1'); elsif clk'event and clk = '1' then if std_logic'(enable_state_change) = '1' then state_idle <= p1_state_idle; end if; end if; end process; process (clk, reset_n) begin if reset_n = '0' then state_busy <= std_logic'('0'); elsif clk'event and clk = '1' then if std_logic'(enable_state_change) = '1' then state_busy <= p1_state_busy; end if; end if; end process; pending_upstream_read <= pending_upstream_read_reg; pending_upstream_write <= pending_upstream_write_reg AND NOT upstream_burstdone; pending_register_enable <= state_idle OR ((((upstream_read OR upstream_write)) AND NOT internal_upstream_waitrequest)); process (clk, reset_n) begin if reset_n = '0' then registered_upstream_read <= std_logic'('0'); elsif clk'event and clk = '1' then if std_logic'(pending_register_enable) = '1' then registered_upstream_read <= upstream_read; end if; end if; end process; process (clk, reset_n) begin if reset_n = '0' then registered_upstream_write <= std_logic'('0'); elsif clk'event and clk = '1' then if std_logic'(pending_register_enable) = '1' then registered_upstream_write <= upstream_write; end if; end if; end process; process (clk, reset_n) begin if reset_n = '0' then registered_upstream_burstcount <= std_logic_vector'("000"); elsif clk'event and clk = '1' then if std_logic'(pending_register_enable) = '1' then registered_upstream_burstcount <= upstream_burstcount; end if; end if; end process; process (clk, reset_n) begin if reset_n = '0' then registered_upstream_address <= std_logic_vector'("00000000000000000000000"); elsif clk'event and clk = '1' then if std_logic'(pending_register_enable) = '1' then registered_upstream_address <= upstream_address; end if; end if; end process; process (clk, reset_n) begin if reset_n = '0' then registered_upstream_nativeaddress <= std_logic_vector'("000000000000000000000"); elsif clk'event and clk = '1' then if std_logic'(pending_register_enable) = '1' then registered_upstream_nativeaddress <= upstream_nativeaddress; end if; end if; end process; current_upstream_read <= registered_upstream_read AND NOT(internal_downstream_write); current_upstream_write <= registered_upstream_write; current_upstream_address <= registered_upstream_address; current_upstream_burstcount <= A_WE_StdLogicVector((std_logic'(pending_register_enable) = '1'), upstream_burstcount, registered_upstream_burstcount); process (clk, reset_n) begin if reset_n = '0' then atomic_counter <= std_logic'('0'); elsif clk'event and clk = '1' then if std_logic'((((internal_downstream_read OR internal_downstream_write)) AND NOT downstream_waitrequest)) = '1' then atomic_counter <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(downstream_burstdone) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(p1_atomic_counter))))); end if; end if; end process; read_update_count <= current_upstream_read AND NOT downstream_waitrequest; write_update_count <= (current_upstream_write AND internal_downstream_write) AND downstream_burstdone; update_count <= read_update_count OR write_update_count; transactions_remaining <= A_WE_StdLogicVector((std_logic'(((state_idle AND ((upstream_read OR upstream_write))))) = '1'), dbs_adjusted_upstream_burstcount, transactions_remaining_reg); process (clk, reset_n) begin if reset_n = '0' then transactions_remaining_reg <= std_logic_vector'("000"); elsif clk'event and clk = '1' then transactions_remaining_reg <= A_EXT (A_WE_StdLogicVector((std_logic'(((state_idle AND ((upstream_read OR upstream_write))))) = '1'), (std_logic_vector'("0") & (dbs_adjusted_upstream_burstcount)), A_WE_StdLogicVector((std_logic'(update_count) = '1'), ((std_logic_vector'("0") & (transactions_remaining_reg)) - (std_logic_vector'("000") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount)))), (std_logic_vector'("0") & (transactions_remaining_reg)))), 3); end if; end process; process (clk, reset_n) begin if reset_n = '0' then data_counter <= std_logic_vector'("000"); elsif clk'event and clk = '1' then data_counter <= A_EXT (A_WE_StdLogicVector((std_logic'(((state_idle AND upstream_read) AND NOT internal_upstream_waitrequest)) = '1'), (std_logic_vector'("000000000000000000000000000000") & (dbs_adjusted_upstream_burstcount)), A_WE_StdLogicVector((std_logic'(downstream_readdatavalid) = '1'), ((std_logic_vector'("000000000000000000000000000000") & (data_counter)) - std_logic_vector'("000000000000000000000000000000001")), (std_logic_vector'("000000000000000000000000000000") & (data_counter)))), 3); end if; end process; max_burst_size <= std_logic'('1'); internal_downstream_burstcount <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(current_upstream_read) = '1'), (std_logic_vector'("00000000000000000000000000000") & ((A_WE_StdLogicVector(((transactions_remaining>(std_logic_vector'("00") & (A_TOSTDLOGICVECTOR(max_burst_size))))), (std_logic_vector'("00") & (A_TOSTDLOGICVECTOR(max_burst_size))), transactions_remaining)))), std_logic_vector'("00000000000000000000000000000001"))); downstream_arbitrationshare <= A_WE_StdLogicVector((std_logic'(current_upstream_read) = '1'), (dbs_adjusted_upstream_burstcount), dbs_adjusted_upstream_burstcount); process (clk, reset_n) begin if reset_n = '0' then write_address_offset <= std_logic_vector'("00"); elsif clk'event and clk = '1' then write_address_offset <= A_EXT (A_WE_StdLogicVector((std_logic'((state_idle AND upstream_write)) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("00000000000000000000000000000") & (A_WE_StdLogicVector((std_logic'(((((internal_downstream_write AND NOT downstream_waitrequest) AND downstream_burstdone) AND or_reduce(internal_downstream_byteenable(3 DOWNTO 2))))) = '1'), ((std_logic_vector'("0") & (write_address_offset)) + (std_logic_vector'("00") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount)))), (std_logic_vector'("0") & (write_address_offset)))))), 2); end if; end process; process (clk, reset_n) begin if reset_n = '0' then read_address_offset <= std_logic_vector'("00"); elsif clk'event and clk = '1' then read_address_offset <= A_EXT (A_WE_StdLogicVector((std_logic'((state_idle AND upstream_read)) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("00000000000000000000000000000") & (A_WE_StdLogicVector((std_logic'(((internal_downstream_read AND NOT downstream_waitrequest))) = '1'), ((std_logic_vector'("0") & (read_address_offset)) + (std_logic_vector'("00") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount)))), (std_logic_vector'("0") & (read_address_offset)))))), 2); end if; end process; downstream_nativeaddress <= A_SRL(registered_upstream_nativeaddress,std_logic_vector'("00000000000000000000000000000001")); address_offset <= A_WE_StdLogicVector((std_logic'(current_upstream_read) = '1'), read_address_offset, write_address_offset); downstream_address_base <= current_upstream_address; downstream_address <= A_EXT (((std_logic_vector'("0") & (downstream_address_base)) + (std_logic_vector'("00000000000000000000") & ((address_offset & std_logic_vector'("00"))))), 21); process (clk, reset_n) begin if reset_n = '0' then internal_downstream_read <= std_logic'('0'); elsif clk'event and clk = '1' then if std_logic'((NOT internal_downstream_read OR NOT downstream_waitrequest)) = '1' then internal_downstream_read <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'((state_idle AND upstream_read)) = '1'), std_logic_vector'("00000000000000000000000000000001"), A_WE_StdLogicVector(((transactions_remaining = (std_logic_vector'("00") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount))))), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(internal_downstream_read)))))); end if; end if; end process; process (clk, reset_n) begin if reset_n = '0' then negative_dbs_rdv_counter <= std_logic'('0'); elsif clk'event and clk = '1' then negative_dbs_rdv_counter <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'((((state_idle AND upstream_read) AND NOT internal_upstream_waitrequest))) = '1'), (std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(upstream_address(1)))), A_WE_StdLogicVector((std_logic'(fifo_datavalid) = '1'), ((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(negative_dbs_rdv_counter))) + std_logic_vector'("000000000000000000000000000000001")), (std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(negative_dbs_rdv_counter)))))); end if; end process; fifo_read <= NOT fifo_empty AND to_std_logic((((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(negative_dbs_rdv_counter))) = std_logic_vector'("00000000000000000000000000000001"))) OR (((((std_logic_vector'("000000000000000000000000000000") & (full_width_rdv_counter)) + std_logic_vector'("000000000000000000000000000000001"))) = (std_logic_vector'("000000000000000000000000000000") & (current_upstream_burstcount))))))); fifo_write <= downstream_readdatavalid; fifo_wr_data <= downstream_readdata; flush_fifo <= std_logic'('0'); --the_niosII_openMac_burst_0_fifo_module, which is an e_instance the_niosII_openMac_burst_0_fifo_module : niosII_openMac_burst_0_fifo_module port map( fifo_datavalid => fifo_datavalid, fifo_empty => fifo_empty, fifo_full => fifo_full, fifo_rd_data => fifo_rd_data, p1_fifo_empty => p1_fifo_empty, clk => clk, clk_en => module_input1, fifo_read => fifo_read, fifo_wr_data => fifo_wr_data, fifo_write => fifo_write, flush_fifo => flush_fifo, inc_pending_data => fifo_write, reset_n => reset_n ); module_input1 <= std_logic'('1'); process (clk, reset_n) begin if reset_n = '0' then full_width_rdv_counter <= std_logic_vector'("000"); elsif clk'event and clk = '1' then full_width_rdv_counter <= A_EXT (A_WE_StdLogicVector((std_logic'((((state_idle AND upstream_read) AND NOT internal_upstream_waitrequest))) = '1'), std_logic_vector'("000000000000000000000000000000000"), A_WE_StdLogicVector((std_logic'(internal_upstream_readdatavalid) = '1'), ((std_logic_vector'("000000000000000000000000000000") & (full_width_rdv_counter)) + std_logic_vector'("000000000000000000000000000000001")), (std_logic_vector'("000000000000000000000000000000") & (full_width_rdv_counter)))), 3); end if; end process; internal_upstream_readdatavalid <= fifo_datavalid; upstream_readdata <= A_WE_StdLogicVector(((std_logic_vector'("00000000000000000000000000000000") = (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(negative_dbs_rdv_counter))))), Std_Logic_Vector'(fifo_rd_data(15 DOWNTO 0) & fifo_rd_data(15 DOWNTO 0)), Std_Logic_Vector'(fifo_rd_data(31 DOWNTO 16) & fifo_rd_data(31 DOWNTO 16))); internal_downstream_byteenable <= upstream_byteenable; internal_downstream_write <= ((upstream_write AND state_busy) AND NOT(pending_upstream_read)) AND fifo_empty; downstream_writedata <= upstream_writedata; upstream_read_run <= state_idle AND upstream_read; upstream_write_run <= ((state_busy AND upstream_write) AND NOT downstream_waitrequest) AND NOT(internal_downstream_read); internal_upstream_waitrequest <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(((upstream_read OR current_upstream_read))) = '1'), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT upstream_read_run))), A_WE_StdLogicVector((std_logic'(current_upstream_write) = '1'), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT upstream_write_run))), std_logic_vector'("00000000000000000000000000000001")))); downstream_debugaccess <= upstream_debugaccess; --vhdl renameroo for output signals downstream_burstcount <= internal_downstream_burstcount; --vhdl renameroo for output signals downstream_byteenable <= internal_downstream_byteenable; --vhdl renameroo for output signals downstream_read <= internal_downstream_read; --vhdl renameroo for output signals downstream_write <= internal_downstream_write; --vhdl renameroo for output signals upstream_readdatavalid <= internal_upstream_readdatavalid; --vhdl renameroo for output signals upstream_waitrequest <= internal_upstream_waitrequest; --synthesis translate_off process (clk) VARIABLE write_line : line; begin if clk'event and clk = '1' then if std_logic'((fifo_full AND fifo_write)) = '1' then write(write_line, now); write(write_line, string'(": ")); write(write_line, string'("simulation assertion failed: niosII_openMac_burst_0: illegal write into full fifo.")); write(output, write_line.all); deallocate (write_line); assert false report "VHDL STOP" severity failure; end if; end if; end process; --synthesis translate_on end europa;
gpl-2.0
a3078b6af71df13c5e5eb4ad173a3ba6
0.629457
3.964067
false
false
false
false
simonspa/pixel-dtb-firmware
dtb/ram_dq_PHASE_l.vhd
2
7,072
-- megafunction wizard: %RAM: 1-PORT% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altsyncram -- ============================================================ -- File Name: ram_dq_PHASE_l.vhd -- Megafunction Name(s): -- altsyncram -- -- Simulation Library Files(s): -- altera_mf -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version -- ************************************************************ --Copyright (C) 1991-2012 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY ram_dq_PHASE_l IS PORT ( address : IN STD_LOGIC_VECTOR (4 DOWNTO 0); clock : IN STD_LOGIC := '1'; data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); wren : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END ram_dq_PHASE_l; ARCHITECTURE SYN OF ram_dq_phase_l IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); COMPONENT altsyncram GENERIC ( clock_enable_input_a : STRING; clock_enable_output_a : STRING; intended_device_family : STRING; lpm_hint : STRING; lpm_type : STRING; numwords_a : NATURAL; operation_mode : STRING; outdata_aclr_a : STRING; outdata_reg_a : STRING; power_up_uninitialized : STRING; read_during_write_mode_port_a : STRING; widthad_a : NATURAL; width_a : NATURAL; width_byteena_a : NATURAL ); PORT ( address_a : IN STD_LOGIC_VECTOR (4 DOWNTO 0); clock0 : IN STD_LOGIC ; data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); wren_a : IN STD_LOGIC ; q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT; BEGIN q <= sub_wire0(7 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( clock_enable_input_a => "BYPASS", clock_enable_output_a => "BYPASS", intended_device_family => "Cyclone III", lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=PH_l", lpm_type => "altsyncram", numwords_a => 32, operation_mode => "SINGLE_PORT", outdata_aclr_a => "NONE", outdata_reg_a => "CLOCK0", power_up_uninitialized => "FALSE", read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", widthad_a => 5, width_a => 8, width_byteena_a => 1 ) PORT MAP ( address_a => address, clock0 => clock, data_a => data, wren_a => wren, q_a => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" -- Retrieval info: PRIVATE: AclrByte NUMERIC "0" -- Retrieval info: PRIVATE: AclrData NUMERIC "0" -- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: Clken NUMERIC "0" -- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1" -- Retrieval info: PRIVATE: JTAG_ID STRING "PH_l" -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -- Retrieval info: PRIVATE: MIFfilename STRING "" -- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32" -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" -- Retrieval info: PRIVATE: RegData NUMERIC "1" -- Retrieval info: PRIVATE: RegOutput NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" -- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" -- Retrieval info: PRIVATE: WidthAddr NUMERIC "5" -- Retrieval info: PRIVATE: WidthData NUMERIC "8" -- Retrieval info: PRIVATE: rden NUMERIC "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=PH_l" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" -- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5" -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -- Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL "address[4..0]" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" -- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" -- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" -- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" -- Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 -- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_l.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_l.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_l.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_l.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_l_inst.vhd FALSE -- Retrieval info: LIB_FILE: altera_mf
unlicense
3711fadf78632d32b46111d9fdfeabe9
0.671946
3.438017
false
false
false
false
OrganicMonkeyMotion/fpga_experiments
small_board/LABS/digital_logic/vhdl/lab2/part3/lpm_constant1.vhd
1
3,513
-- megafunction wizard: %LPM_CONSTANT% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: LPM_CONSTANT -- ============================================================ -- File Name: lpm_constant1.vhd -- Megafunction Name(s): -- LPM_CONSTANT -- -- Simulation Library Files(s): -- lpm -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition -- ************************************************************ --Copyright (C) 1991-2011 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.all; ENTITY lpm_constant1 IS PORT ( result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) ); END lpm_constant1; ARCHITECTURE SYN OF lpm_constant1 IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0); COMPONENT lpm_constant GENERIC ( lpm_cvalue : NATURAL; lpm_hint : STRING; lpm_type : STRING; lpm_width : NATURAL ); PORT ( result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) ); END COMPONENT; BEGIN result <= sub_wire0(0 DOWNTO 0); LPM_CONSTANT_component : LPM_CONSTANT GENERIC MAP ( lpm_cvalue => 0, lpm_hint => "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=aas", lpm_type => "LPM_CONSTANT", lpm_width => 1 ) PORT MAP ( result => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1" -- Retrieval info: PRIVATE: JTAG_ID STRING "aas" -- Retrieval info: PRIVATE: Radix NUMERIC "10" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: Value NUMERIC "0" -- Retrieval info: PRIVATE: nBit NUMERIC "1" -- Retrieval info: PRIVATE: new_diagram STRING "1" -- Retrieval info: LIBRARY: lpm lpm.lpm_components.all -- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0" -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=aas" -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1" -- Retrieval info: USED_PORT: result 0 0 1 0 OUTPUT NODEFVAL "result[0..0]" -- Retrieval info: CONNECT: result 0 0 1 0 @result 0 0 1 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.bsf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1_inst.vhd FALSE -- Retrieval info: LIB_FILE: lpm
unlicense
4b7a9a267755ffc8b93c7030a88577f9
0.646741
3.818478
false
false
false
false
scottlbaker/PDP11-SOC
src/decode.vhd
1
28,854
--======================================================================== -- decode.vhd :: PDP-11 Instruction Decoder -- -- (c) Scott L. Baker, Sierra Circuit Design --======================================================================== library IEEE; use IEEE.std_logic_1164.all; use work.my_types.all; entity DECODE is port ( MACRO_OP : out MACRO_OP_TYPE; -- opcode BYTE_OP : out std_logic; -- byte/word FORMAT : out std_logic_vector( 2 downto 0); -- format IR : in std_logic_vector(15 downto 0) -- inst reg ); end DECODE; architecture BEHAVIORAL of DECODE is begin --========================================================= -- Decode the opcode and addressing mode --========================================================= DECODE_OPCODE_AND_ADDRESS_MODE: process(IR) begin -- Set the default states for the addressing modes MACRO_OP <= MOP_NOP; FORMAT <= IMPLIED; BYTE_OP <= '0'; case IR(15 downto 12) is -- Group 0: branches, jumps and Implied operand instructions when "0000" => case IR(11 downto 6) is when "000000" => case IR(2 downto 0) is when "000" => -- HALT :: halt MACRO_OP <= MOP_HALT; FORMAT <= IMPLIED; when "001" => -- WAIT :: wait MACRO_OP <= MOP_WAIT; FORMAT <= IMPLIED; when "010" => -- RTI :: return from interrupt MACRO_OP <= MOP_RTI; FORMAT <= IMPLIED; when "011" => -- BPT :: breakpoint trap MACRO_OP <= MOP_BPT; FORMAT <= IMPLIED; when "100" => -- IOT :: I/O trap MACRO_OP <= MOP_IOT; FORMAT <= IMPLIED; when "101" => -- RESET :: reset bus MACRO_OP <= MOP_RESET; FORMAT <= IMPLIED; when "110" => -- RTT :: return from interrupt MACRO_OP <= MOP_RTT; FORMAT <= IMPLIED; when others => -- MFPT :: move from P-type MACRO_OP <= MOP_MFPT; FORMAT <= IMPLIED; end case; if (IR(5 downto 3) /= "000") then -- UII :: unimplemented MACRO_OP <= MOP_UII; FORMAT <= IMPLIED; end if; when "000001" => -- JMP :: jump MACRO_OP <= MOP_JMP; FORMAT <= ONE_OPERAND; when "000010" => case IR(5 downto 3) is when "000" => -- RTS return from subroutine MACRO_OP <= MOP_RTS; FORMAT <= IMPLIED; when "011" => -- SPL :: set priority level MACRO_OP <= MOP_SPL; FORMAT <= IMPLIED; when "100" => case IR(2 downto 0) is when "000" => -- NOP :: no operation MACRO_OP <= MOP_NOP; FORMAT <= IMPLIED; when "001" => -- CLC :: clear C bit MACRO_OP <= MOP_CLC; FORMAT <= IMPLIED; when "010" => -- CLV :: clear V bit MACRO_OP <= MOP_CLV; FORMAT <= IMPLIED; when "100" => -- CLZ :: clear Z bit MACRO_OP <= MOP_CLZ; FORMAT <= IMPLIED; when others => end case; when "101" => case IR(2 downto 0) is when "000" => -- CLN :: clear N bit MACRO_OP <= MOP_CLN; FORMAT <= IMPLIED; when "111" => -- CCC :: set cond codes MACRO_OP <= MOP_CCC; FORMAT <= IMPLIED; when others => end case; when "110" => case IR(2 downto 0) is when "001" => -- SEC :: set C bit MACRO_OP <= MOP_SEC; FORMAT <= IMPLIED; when "010" => -- SEV :: set V bit MACRO_OP <= MOP_SEV; FORMAT <= IMPLIED; when "100" => -- SEZ :: set Z bit MACRO_OP <= MOP_SEZ; FORMAT <= IMPLIED; when others => end case; when "111" => case IR(2 downto 0) is when "000" => -- SEN :: set N bit MACRO_OP <= MOP_SEN; FORMAT <= IMPLIED; when "111" => -- SCC :: set cond codes MACRO_OP <= MOP_SCC; FORMAT <= IMPLIED; when others => end case; when others => -- UII :: unimplemented MACRO_OP <= MOP_UII; FORMAT <= IMPLIED; end case; when "000011" => -- SWAB :: swap bytes MACRO_OP <= MOP_SWAB; FORMAT <= ONE_OPERAND; when "000100" => -- BR :: branch always MACRO_OP <= MOP_BR; FORMAT <= BRA_FORMAT; when "000101" => -- BR :: branch always MACRO_OP <= MOP_BR; FORMAT <= BRA_FORMAT; when "000110" => -- BR :: branch always MACRO_OP <= MOP_BR; FORMAT <= BRA_FORMAT; when "000111" => -- BR :: branch always MACRO_OP <= MOP_BR; FORMAT <= BRA_FORMAT; when "001000" => -- BNE :: branch if negative MACRO_OP <= MOP_BNE; FORMAT <= BRA_FORMAT; when "001001" => -- BNE :: branch if negative MACRO_OP <= MOP_BNE; FORMAT <= BRA_FORMAT; when "001010" => -- BNE :: branch if negative MACRO_OP <= MOP_BNE; FORMAT <= BRA_FORMAT; when "001011" => -- BNE :: branch if negative MACRO_OP <= MOP_BNE; FORMAT <= BRA_FORMAT; when "001100" => -- BEQ :: branch if equal MACRO_OP <= MOP_BEQ; FORMAT <= BRA_FORMAT; when "001101" => -- BEQ :: branch if equal MACRO_OP <= MOP_BEQ; FORMAT <= BRA_FORMAT; when "001110" => -- BEQ :: branch if equal MACRO_OP <= MOP_BEQ; FORMAT <= BRA_FORMAT; when "001111" => -- BEQ :: branch if equal MACRO_OP <= MOP_BEQ; FORMAT <= BRA_FORMAT; when "010000" => -- BGE :: branch if greater or equal MACRO_OP <= MOP_BGE; FORMAT <= BRA_FORMAT; when "010001" => -- BGE :: branch if greater or equal MACRO_OP <= MOP_BGE; FORMAT <= BRA_FORMAT; when "010010" => -- BGE :: branch if greater or equal MACRO_OP <= MOP_BGE; FORMAT <= BRA_FORMAT; when "010011" => -- BGE :: branch if greater or equal MACRO_OP <= MOP_BGE; FORMAT <= BRA_FORMAT; when "010100" => -- BLT :: branch if less than MACRO_OP <= MOP_BLT; FORMAT <= BRA_FORMAT; when "010101" => -- BLT :: branch if less than MACRO_OP <= MOP_BLT; FORMAT <= BRA_FORMAT; when "010110" => -- BLT :: branch if less than MACRO_OP <= MOP_BLT; FORMAT <= BRA_FORMAT; when "010111" => -- BLT :: branch if less than MACRO_OP <= MOP_BLT; FORMAT <= BRA_FORMAT; when "011000" => -- BGT :: branch if greater than MACRO_OP <= MOP_BGT; FORMAT <= BRA_FORMAT; when "011001" => -- BGT :: branch if greater than MACRO_OP <= MOP_BGT; FORMAT <= BRA_FORMAT; when "011010" => -- BGT :: branch if greater than MACRO_OP <= MOP_BGT; FORMAT <= BRA_FORMAT; when "011011" => -- BGT :: branch if greater than MACRO_OP <= MOP_BGT; FORMAT <= BRA_FORMAT; when "011100" => -- BLE :: branch if less or equal MACRO_OP <= MOP_BLE; FORMAT <= BRA_FORMAT; when "011101" => -- BLE :: branch if less or equal MACRO_OP <= MOP_BLE; FORMAT <= BRA_FORMAT; when "011110" => -- BLE :: branch if less or equal MACRO_OP <= MOP_BLE; FORMAT <= BRA_FORMAT; when "011111" => -- BLE :: branch if less or equal MACRO_OP <= MOP_BLE; FORMAT <= BRA_FORMAT; when "100000" => -- JSR :: jump to subroutine MACRO_OP <= MOP_JSR; FORMAT <= ONE_OPERAND; when "100001" => -- JSR :: jump to subroutine MACRO_OP <= MOP_JSR; FORMAT <= ONE_OPERAND; when "100010" => -- JSR :: jump to subroutine MACRO_OP <= MOP_JSR; FORMAT <= ONE_OPERAND; when "100011" => -- JSR :: jump to subroutine MACRO_OP <= MOP_JSR; FORMAT <= ONE_OPERAND; when "100100" => -- JSR :: jump to subroutine MACRO_OP <= MOP_JSR; FORMAT <= ONE_OPERAND; when "100101" => -- JSR :: jump to subroutine MACRO_OP <= MOP_JSR; FORMAT <= ONE_OPERAND; when "100110" => -- JSR :: jump to subroutine MACRO_OP <= MOP_JSR; FORMAT <= ONE_OPERAND; when "100111" => -- JSR :: jump to subroutine MACRO_OP <= MOP_JSR; FORMAT <= ONE_OPERAND; when "101000" => -- CLR :: clear MACRO_OP <= MOP_CLR; FORMAT <= ONE_OPERAND; when "101001" => -- COM :: ones complement MACRO_OP <= MOP_COM; FORMAT <= ONE_OPERAND; when "101010" => -- INC :: increment MACRO_OP <= MOP_INC; FORMAT <= ONE_OPERAND; when "101011" => -- DEC :: decrement MACRO_OP <= MOP_DEC; FORMAT <= ONE_OPERAND; when "101100" => -- NEG :: twos complement MACRO_OP <= MOP_NEG; FORMAT <= ONE_OPERAND; when "101101" => -- ADC :: add carry MACRO_OP <= MOP_ADC; FORMAT <= ONE_OPERAND; when "101110" => -- SBC :: subtract carry MACRO_OP <= MOP_SBC; FORMAT <= ONE_OPERAND; when "101111" => -- TST :: test MACRO_OP <= MOP_TST; FORMAT <= ONE_OPERAND; when "110000" => -- ROR :: rotate right MACRO_OP <= MOP_ROR; FORMAT <= ONE_OPERAND; when "110001" => -- ROL :: rotate left MACRO_OP <= MOP_ROL; FORMAT <= ONE_OPERAND; when "110010" => -- ASR :: shift right MACRO_OP <= MOP_ASR; FORMAT <= ONE_OPERAND; when "110011" => -- ASL :: shift left MACRO_OP <= MOP_ASL; FORMAT <= ONE_OPERAND; when "110100" => -- MARK :: mark stack MACRO_OP <= MOP_MARK; FORMAT <= IMPLIED; when "110101" => -- MFPI :: move from prev I-space MACRO_OP <= MOP_MFPI; FORMAT <= IMPLIED; when "110110" => -- MTPI :: move to prev I-space MACRO_OP <= MOP_MTPI; FORMAT <= IMPLIED; when "110111" => -- SXT :: sign extend MACRO_OP <= MOP_SXT; FORMAT <= ONE_OPERAND; when "111000" => -- CSM :: call supervisor mode MACRO_OP <= MOP_CSM; FORMAT <= IMPLIED; when "111010" => -- TSTSET :: test and set MACRO_OP <= MOP_TSTSET; FORMAT <= ONE_OPERAND; when "111011" => -- WRTLCK :: write lock MACRO_OP <= MOP_WRTLCK; FORMAT <= ONE_OPERAND; when others => MACRO_OP <= MOP_UII; FORMAT <= IMPLIED; end case; -- Groups 1 through 6: Double operand word instructions when "0001" => -- MOV :: move MACRO_OP <= MOP_MOV; FORMAT <= TWO_OPERAND; when "0010" => -- CMP :: compare MACRO_OP <= MOP_CMP; FORMAT <= TWO_OPERAND; when "0011" => -- BIT :: bit test MACRO_OP <= MOP_BIT; FORMAT <= TWO_OPERAND; when "0100" => -- BCI :: bit clear MACRO_OP <= MOP_BIC; FORMAT <= TWO_OPERAND; when "0101" => -- BIS :: bit set MACRO_OP <= MOP_BIS; FORMAT <= TWO_OPERAND; when "0110" => -- ADD :: add MACRO_OP <= MOP_ADD; FORMAT <= TWO_OPERAND; -- Group 7: Double operand word instructions when "0111" => case IR(11 downto 9) is when "000" => -- MUL :: multiply MACRO_OP <= MOP_MUL; FORMAT <= TWO_OPERAND; when "001" => -- DIV :: divide MACRO_OP <= MOP_DIV; FORMAT <= TWO_OPERAND; when "010" => -- ASH :: shift MACRO_OP <= MOP_ASH; FORMAT <= TWO_OPERAND; when "011" => -- ASHC :: shift with carry MACRO_OP <= MOP_ASHC; FORMAT <= TWO_OPERAND; when "100" => -- XOR :: exclusive OR MACRO_OP <= MOP_XOR; FORMAT <= TWO_OPERAND; when "101" => if (IR(8 downto 6) = "000") then case IR(5 downto 3) is when "000" => -- FADD :: floating add MACRO_OP <= MOP_FADD; FORMAT <= FLOAT; when "001" => -- FSUB :: floating subtract MACRO_OP <= MOP_FSUB; FORMAT <= FLOAT; when "010" => -- FMUL :: floating multiply MACRO_OP <= MOP_FMUL; FORMAT <= FLOAT; when "011" => -- FDIV :: floating divide MACRO_OP <= MOP_FDIV; FORMAT <= FLOAT; when others => -- UII :: unimplemented MACRO_OP <= MOP_UII; FORMAT <= IMPLIED; end case; else -- UII :: unimplemented MACRO_OP <= MOP_UII; FORMAT <= IMPLIED; end if; when "110" => -- UII :: unimplemented MACRO_OP <= MOP_UII; FORMAT <= IMPLIED; when others => -- SOB :: decrement and branch MACRO_OP <= MOP_SOB; FORMAT <= BRA_FORMAT; end case; -- Group 8: branches, traps and Single operand instructions when "1000" => case IR(11 downto 6) is when "000000" => -- BPL :: branch if plus MACRO_OP <= MOP_BPL; FORMAT <= BRA_FORMAT; when "000001" => -- BPL :: branch if plus MACRO_OP <= MOP_BPL; FORMAT <= BRA_FORMAT; when "000010" => -- BPL :: branch if plus MACRO_OP <= MOP_BPL; FORMAT <= BRA_FORMAT; when "000011" => -- BPL :: branch if plus MACRO_OP <= MOP_BPL; FORMAT <= BRA_FORMAT; when "000100" => -- BMI :: branch if minus MACRO_OP <= MOP_BMI; FORMAT <= BRA_FORMAT; when "000101" => -- BMI :: branch if minus MACRO_OP <= MOP_BMI; FORMAT <= BRA_FORMAT; when "000110" => -- BMI :: branch if minus MACRO_OP <= MOP_BMI; FORMAT <= BRA_FORMAT; when "000111" => -- BMI :: branch if minus MACRO_OP <= MOP_BMI; FORMAT <= BRA_FORMAT; when "001000" => -- BHI :: branch if higher MACRO_OP <= MOP_BHI; FORMAT <= BRA_FORMAT; when "001001" => -- BHI :: branch if higher MACRO_OP <= MOP_BHI; FORMAT <= BRA_FORMAT; when "001010" => -- BHI :: branch if higher MACRO_OP <= MOP_BHI; FORMAT <= BRA_FORMAT; when "001011" => -- BHI :: branch if higher MACRO_OP <= MOP_BHI; FORMAT <= BRA_FORMAT; when "001100" => -- BLOS :: branch if lower or same MACRO_OP <= MOP_BLOS; FORMAT <= BRA_FORMAT; when "001101" => -- BLOS :: branch if lower or same MACRO_OP <= MOP_BLOS; FORMAT <= BRA_FORMAT; when "001110" => -- BLOS :: branch if lower or same MACRO_OP <= MOP_BLOS; FORMAT <= BRA_FORMAT; when "001111" => -- BLOS :: branch if lower or same MACRO_OP <= MOP_BLOS; FORMAT <= BRA_FORMAT; when "010000" => -- BVC :: branch if overflow clear MACRO_OP <= MOP_BVC; FORMAT <= BRA_FORMAT; when "010001" => -- BVC :: branch if overflow clear MACRO_OP <= MOP_BVC; FORMAT <= BRA_FORMAT; when "010010" => -- BVC :: branch if overflow clear MACRO_OP <= MOP_BVC; FORMAT <= BRA_FORMAT; when "010011" => -- BVC :: branch if overflow clear MACRO_OP <= MOP_BVC; FORMAT <= BRA_FORMAT; when "010100" => -- BVS :: branch if overflow set MACRO_OP <= MOP_BVS; FORMAT <= BRA_FORMAT; when "010101" => -- BVS :: branch if overflow set MACRO_OP <= MOP_BVS; FORMAT <= BRA_FORMAT; when "010110" => -- BVS :: branch if overflow set MACRO_OP <= MOP_BVS; FORMAT <= BRA_FORMAT; when "010111" => -- BVS :: branch if overflow set MACRO_OP <= MOP_BVS; FORMAT <= BRA_FORMAT; when "011000" => -- BCC :: branch if carry clear MACRO_OP <= MOP_BCC; FORMAT <= BRA_FORMAT; when "011001" => -- BCC :: branch if carry clear MACRO_OP <= MOP_BCC; FORMAT <= BRA_FORMAT; when "011010" => -- BCC :: branch if carry clear MACRO_OP <= MOP_BCC; FORMAT <= BRA_FORMAT; when "011011" => -- BCC :: branch if carry clear MACRO_OP <= MOP_BCC; FORMAT <= BRA_FORMAT; when "011100" => -- BCS :: branch if carry set MACRO_OP <= MOP_BCS; FORMAT <= BRA_FORMAT; when "011101" => -- BCS :: branch if carry set MACRO_OP <= MOP_BCS; FORMAT <= BRA_FORMAT; when "011110" => -- BCS :: branch if carry set MACRO_OP <= MOP_BCS; FORMAT <= BRA_FORMAT; when "011111" => -- BCS :: branch if carry set MACRO_OP <= MOP_BCS; FORMAT <= BRA_FORMAT; when "100000" => -- EMT :: emulator trap MACRO_OP <= MOP_EMT; FORMAT <= IMPLIED; when "100001" => -- EMT :: emulator trap MACRO_OP <= MOP_EMT; FORMAT <= IMPLIED; when "100010" => -- EMT :: emulator trap MACRO_OP <= MOP_EMT; FORMAT <= IMPLIED; when "100011" => -- EMT :: emulator trap MACRO_OP <= MOP_EMT; FORMAT <= IMPLIED; when "100100" => -- TRAP :: SW trap MACRO_OP <= MOP_TRAP; FORMAT <= IMPLIED; when "100101" => -- TRAP :: SW trap MACRO_OP <= MOP_TRAP; FORMAT <= IMPLIED; when "100110" => -- TRAP :: SW trap MACRO_OP <= MOP_TRAP; FORMAT <= IMPLIED; when "100111" => -- TRAP :: SW trap MACRO_OP <= MOP_TRAP; FORMAT <= IMPLIED; when "101000" => -- CLRB :: clear MACRO_OP <= MOP_CLR; FORMAT <= ONE_OPERAND; BYTE_OP <= '1'; when "101001" => -- COMB :: ones complement MACRO_OP <= MOP_COM; FORMAT <= ONE_OPERAND; BYTE_OP <= '1'; when "101010" => -- INCB :: increment MACRO_OP <= MOP_INC; FORMAT <= ONE_OPERAND; BYTE_OP <= '1'; when "101011" => -- DECB :: decrement MACRO_OP <= MOP_DEC; FORMAT <= ONE_OPERAND; BYTE_OP <= '1'; when "101100" => -- NEGB :: twos complement MACRO_OP <= MOP_NEG; FORMAT <= ONE_OPERAND; BYTE_OP <= '1'; when "101101" => -- ADCB :: add carry MACRO_OP <= MOP_ADC; FORMAT <= ONE_OPERAND; BYTE_OP <= '1'; when "101110" => -- SBCB :: subtract carry MACRO_OP <= MOP_SBC; FORMAT <= ONE_OPERAND; BYTE_OP <= '1'; when "101111" => -- TSTB :: test MACRO_OP <= MOP_TST; FORMAT <= ONE_OPERAND; BYTE_OP <= '1'; when "110000" => -- RORB :: rotate right MACRO_OP <= MOP_ROR; FORMAT <= ONE_OPERAND; BYTE_OP <= '1'; when "110001" => -- ROLB :: rotate left MACRO_OP <= MOP_ROL; BYTE_OP <= '1'; when "110010" => -- ASRB :: shift right MACRO_OP <= MOP_ASR; FORMAT <= ONE_OPERAND; BYTE_OP <= '1'; when "110011" => -- ASLB :: shift left MACRO_OP <= MOP_ASL; FORMAT <= ONE_OPERAND; BYTE_OP <= '1'; when "110100" => -- MTPS :: move to status MACRO_OP <= MOP_MTPS; FORMAT <= IMPLIED; when "110101" => -- MFPD :: move from prev D-space MACRO_OP <= MOP_MFPD; FORMAT <= IMPLIED; when "110110" => -- MTPD :: move to prev D-space MACRO_OP <= MOP_MTPD; FORMAT <= IMPLIED; when "110111" => -- MFPS :: move from status MACRO_OP <= MOP_MFPS; FORMAT <= IMPLIED; when others => MACRO_OP <= MOP_UII; FORMAT <= IMPLIED; end case; -- Groups 9 through 14: Double operand byte instructions when "1001" => -- MOVB :: move MACRO_OP <= MOP_MOV; FORMAT <= TWO_OPERAND; BYTE_OP <= '1'; when "1010" => -- CMPB :: compare MACRO_OP <= MOP_CMP; FORMAT <= TWO_OPERAND; BYTE_OP <= '1'; when "1011" => -- BITB :: bit test MACRO_OP <= MOP_BIT; FORMAT <= TWO_OPERAND; BYTE_OP <= '1'; when "1100" => -- BICB :: bit clear MACRO_OP <= MOP_BIC; FORMAT <= TWO_OPERAND; BYTE_OP <= '1'; when "1101" => -- BISB :: bit set MACRO_OP <= MOP_BIS; FORMAT <= TWO_OPERAND; BYTE_OP <= '1'; when "1110" => -- SUB :: subtract MACRO_OP <= MOP_SUB; FORMAT <= TWO_OPERAND; -- Group 15: floating point (currently not implemented) when others => -- call fpp MACRO_OP <= MOP_UII; FORMAT <= FLOAT; end case; end process; end BEHAVIORAL;
gpl-3.0
7d62fafd53140c3162a749afec5fac0d
0.344528
5.237611
false
false
false
false
simonspa/pixel-dtb-firmware
dtb/TBM_H_FSM.vhd
2
4,425
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity TBM_H_FSM is port (clk_i : in std_logic; reset_i : in std_logic; TBM_H_start_i : in std_logic; serdat_i: in std_logic; payload_o : out std_logic_vector(3 downto 0); type_o : out std_logic_vector(3 downto 0); wen_o : out std_logic); end TBM_H_FSM; architecture rtl of TBM_H_FSM is type t_state is (waiting, tick_EN7, tick_EN6, tick_EN5, tick_EN4, tick_EN3, tick_EN2, tick_EN1, tick_EN0, tick_STF, tick_PKR, tick_SC5, tick_SC4, tick_SC3, tick_SC2, tick_SC1, tick_SC0); signal s_state : t_state; begin p_format: process (clk_i, reset_i) begin -- process p_serin if (reset_i = '1') then -- asynchronous reset wen_o <= '0'; payload_o <= "0000"; type_o <= "0000"; s_state <= waiting; elsif rising_edge(clk_i) then -- rising clock edge case s_state is ------------------------------------------------------------------------- when tick_EN7 => wen_o <= '0'; payload_o(3)<=serdat_i; s_state <= tick_EN6 ; ------------------------------------------------------------------------- when tick_EN6 => payload_o(2)<=serdat_i; s_state <= tick_EN5 ; ------------------------------------------------------------------------- when tick_EN5 => payload_o(1)<=serdat_i; s_state <= tick_EN4 ; ------------------------------------------------------------------------- when tick_EN4 => payload_o(0)<=serdat_i; type_o <= "1000"; wen_o <= '1'; s_state <= tick_EN3 ; ------------------------------------------------------------------------- when tick_EN3 => payload_o(3)<=serdat_i; wen_o <= '0'; s_state <= tick_EN2 ; ------------------------------------------------------------------------- when tick_EN2 => payload_o(2)<=serdat_i; s_state <= tick_EN1 ; ------------------------------------------------------------------------- when tick_EN1 => payload_o(1)<=serdat_i; s_state <= tick_EN0 ; ------------------------------------------------------------------------- when tick_EN0 => payload_o(0)<=serdat_i; type_o <= "1001"; wen_o <= '1'; s_state <= tick_STF ; ------------------------------------------------------------------------- when tick_STF => payload_o(3)<=serdat_i; wen_o <= '0'; s_state <= tick_PKR ; ------------------------------------------------------------------------- when tick_PKR => payload_o(2)<=serdat_i; s_state <= tick_SC5 ; ------------------------------------------------------------------------- when tick_SC5 => payload_o(1)<=serdat_i; s_state <= tick_SC4 ; ------------------------------------------------------------------------- when tick_SC4 => payload_o(0)<=serdat_i; type_o <= "1010"; wen_o <= '1'; s_state <= tick_SC3 ; ------------------------------------------------------------------------- when tick_SC3 => payload_o(3)<=serdat_i; wen_o <= '0'; s_state <= tick_SC2 ; ------------------------------------------------------------------------- when tick_SC2 => payload_o(2)<=serdat_i; s_state <= tick_SC1 ; ------------------------------------------------------------------------- when tick_SC1 => payload_o(1)<=serdat_i; s_state <= tick_SC0 ; ------------------------------------------------------------------------- when tick_SC0 => payload_o(0)<=serdat_i; wen_o <= '1'; type_o <= "1011"; s_state <= waiting ; ------------------------------------------------------------------------- when others => if TBM_H_start_i = '1' then wen_o <= '0'; s_state <= tick_EN7; else wen_o <= '0'; s_state <= waiting; end if; end case; end if; end process p_format; end rtl;
unlicense
21e71c8ccfd20e2ba5853b82fca537e2
0.315028
4.333986
false
false
false
false
OrganicMonkeyMotion/fpga_experiments
small_board/LABS/digital_logic/vhdl/lab1/part5/M21EDAversion/lpm_constant0.vhd
1
3,515
-- megafunction wizard: %LPM_CONSTANT% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: LPM_CONSTANT -- ============================================================ -- File Name: lpm_constant0.vhd -- Megafunction Name(s): -- LPM_CONSTANT -- -- Simulation Library Files(s): -- lpm -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition -- ************************************************************ --Copyright (C) 1991-2011 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.all; ENTITY lpm_constant0 IS PORT ( result : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) ); END lpm_constant0; ARCHITECTURE SYN OF lpm_constant0 IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0); COMPONENT lpm_constant GENERIC ( lpm_cvalue : NATURAL; lpm_hint : STRING; lpm_type : STRING; lpm_width : NATURAL ); PORT ( result : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) ); END COMPONENT; BEGIN result <= sub_wire0(5 DOWNTO 0); LPM_CONSTANT_component : LPM_CONSTANT GENERIC MAP ( lpm_cvalue => 6, lpm_hint => "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=MYVA", lpm_type => "LPM_CONSTANT", lpm_width => 6 ) PORT MAP ( result => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1" -- Retrieval info: PRIVATE: JTAG_ID STRING "MYVA" -- Retrieval info: PRIVATE: Radix NUMERIC "2" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: Value NUMERIC "6" -- Retrieval info: PRIVATE: nBit NUMERIC "6" -- Retrieval info: PRIVATE: new_diagram STRING "1" -- Retrieval info: LIBRARY: lpm lpm.lpm_components.all -- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "6" -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=MYVA" -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "6" -- Retrieval info: USED_PORT: result 0 0 6 0 OUTPUT NODEFVAL "result[5..0]" -- Retrieval info: CONNECT: result 0 0 6 0 @result 0 0 6 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.bsf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0_inst.vhd FALSE -- Retrieval info: LIB_FILE: lpm
unlicense
606c3929daf5095fa5adb6a905f61dad
0.646942
3.808234
false
false
false
false
simonspa/pixel-dtb-firmware
dtb/ram_dq_INST_na.vhd
2
7,075
-- megafunction wizard: %RAM: 1-PORT% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altsyncram -- ============================================================ -- File Name: ram_dq_INST_na.vhd -- Megafunction Name(s): -- altsyncram -- -- Simulation Library Files(s): -- altera_mf -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version -- ************************************************************ --Copyright (C) 1991-2012 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY ram_dq_INST_na IS PORT ( address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); clock : IN STD_LOGIC := '1'; data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); wren : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END ram_dq_INST_na; ARCHITECTURE SYN OF ram_dq_inst_na IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); COMPONENT altsyncram GENERIC ( clock_enable_input_a : STRING; clock_enable_output_a : STRING; intended_device_family : STRING; lpm_hint : STRING; lpm_type : STRING; numwords_a : NATURAL; operation_mode : STRING; outdata_aclr_a : STRING; outdata_reg_a : STRING; power_up_uninitialized : STRING; read_during_write_mode_port_a : STRING; widthad_a : NATURAL; width_a : NATURAL; width_byteena_a : NATURAL ); PORT ( address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); clock0 : IN STD_LOGIC ; data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); wren_a : IN STD_LOGIC ; q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT; BEGIN q <= sub_wire0(7 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( clock_enable_input_a => "BYPASS", clock_enable_output_a => "BYPASS", intended_device_family => "Cyclone III", lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=N_na", lpm_type => "altsyncram", numwords_a => 256, operation_mode => "SINGLE_PORT", outdata_aclr_a => "NONE", outdata_reg_a => "CLOCK0", power_up_uninitialized => "FALSE", read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", widthad_a => 8, width_a => 8, width_byteena_a => 1 ) PORT MAP ( address_a => address, clock0 => clock, data_a => data, wren_a => wren, q_a => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" -- Retrieval info: PRIVATE: AclrByte NUMERIC "0" -- Retrieval info: PRIVATE: AclrData NUMERIC "0" -- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: Clken NUMERIC "0" -- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1" -- Retrieval info: PRIVATE: JTAG_ID STRING "N_na" -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -- Retrieval info: PRIVATE: MIFfilename STRING "" -- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256" -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" -- Retrieval info: PRIVATE: RegData NUMERIC "1" -- Retrieval info: PRIVATE: RegOutput NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" -- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" -- Retrieval info: PRIVATE: WidthAddr NUMERIC "8" -- Retrieval info: PRIVATE: WidthData NUMERIC "8" -- Retrieval info: PRIVATE: rden NUMERIC "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=N_na" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" -- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" -- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" -- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" -- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" -- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 -- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_na.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_na.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_na.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_na.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_na_inst.vhd FALSE -- Retrieval info: LIB_FILE: altera_mf
unlicense
fbb956fe2d39127dc55b402895995b6e
0.672085
3.439475
false
false
false
false
systec-dk/openPOWERLINK_systec
Examples/ipcore/xilinx/openmac/src/fifo_write.vhd
3
4,764
------------------------------------------------------------------------------- -- write controller of the fifo -- -- Copyright (C) 2009 B&R -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- -- Note: A general implementation of a asynchronous fifo which is -- using a dual port ram. This file is the write controler. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity fifo_write_ctrl is generic(N: natural:=4); port( clkw, resetw: in std_logic; wr: in std_logic; r_ptr_in: in std_logic_vector(N downto 0); w_full: out std_logic; w_empty: out std_logic; w_ptr_out: out std_logic_vector(N downto 0); w_addr: out std_logic_vector(N-1 downto 0); w_elements: out std_logic_vector(N-1 downto 0) ); end fifo_write_ctrl; architecture gray_arch of fifo_write_ctrl is signal w_ptr_reg, w_ptr_next: std_logic_vector(N downto 0); signal r_ptr_reg, r_ptr_next : std_logic_vector(N downto 0) := (others => '0'); signal gray1, bin, bin1: std_logic_vector(N downto 0); signal waddr_all: std_logic_vector(N-1 downto 0); signal waddr_msb, raddr_msb: std_logic; signal full_flag, empty_flag: std_logic; signal w_elements_wr, w_elements_rd, w_elements_diff : std_logic_vector(N downto 0); signal w_elements_reg, w_elements_next : std_logic_vector(N-1 downto 0); begin -- register process(clkw,resetw) begin if (resetw='1') then w_ptr_reg <= (others=>'0'); --r_ptr_reg <= (others => '0'); w_elements_reg <= (others => '0'); elsif (clkw'event and clkw='1') then w_ptr_reg <= w_ptr_next; --r_ptr_reg <= r_ptr_next; w_elements_reg <= w_elements_next; end if; end process; -- (N+1)-bit Gray counter bin <= w_ptr_reg xor ('0' & bin(N downto 1)); bin1 <= std_logic_vector(unsigned(bin) + 1); gray1 <= bin1 xor ('0' & bin1(N downto 1)); -- update write pointer w_ptr_next <= gray1 when wr='1' and full_flag='0' else w_ptr_reg; -- save read pointer r_ptr_next <= r_ptr_in; -- N-bit Gray counter waddr_msb <= w_ptr_reg(N) xor w_ptr_reg(N-1); waddr_all <= waddr_msb & w_ptr_reg(N-2 downto 0); -- check for FIFO full and empty raddr_msb <= r_ptr_in(N) xor r_ptr_in(N-1); full_flag <= '1' when r_ptr_in(N) /=w_ptr_reg(N) and r_ptr_in(N-2 downto 0)=w_ptr_reg(N-2 downto 0) and raddr_msb = waddr_msb else '0'; empty_flag <= '1' when r_ptr_in(N) =w_ptr_reg(N) and r_ptr_in(N-2 downto 0)=w_ptr_reg(N-2 downto 0) and raddr_msb = waddr_msb else '0'; -- convert gray value to bin and obtain difference w_elements_wr <= bin; w_elements_rd <= r_ptr_in xor ('0' & w_elements_rd(N downto 1)); w_elements_diff <= std_logic_vector(unsigned(w_elements_wr) - unsigned(w_elements_rd)); w_elements_next <= w_elements_diff(w_elements_next'range); -- output w_addr <= waddr_all; w_ptr_out <= w_ptr_reg; w_elements <= w_elements_reg; w_full <= full_flag; w_empty <= empty_flag; end gray_arch;
gpl-2.0
b52cca03d4505667aaa6cc83bb8b4315
0.628883
3.452174
false
false
false
false
simonspa/pixel-dtb-firmware
dtb/ram_dq_PHASE_n.vhd
2
7,072
-- megafunction wizard: %RAM: 1-PORT% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altsyncram -- ============================================================ -- File Name: ram_dq_PHASE_n.vhd -- Megafunction Name(s): -- altsyncram -- -- Simulation Library Files(s): -- altera_mf -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version -- ************************************************************ --Copyright (C) 1991-2012 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY ram_dq_PHASE_n IS PORT ( address : IN STD_LOGIC_VECTOR (4 DOWNTO 0); clock : IN STD_LOGIC := '1'; data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); wren : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END ram_dq_PHASE_n; ARCHITECTURE SYN OF ram_dq_phase_n IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); COMPONENT altsyncram GENERIC ( clock_enable_input_a : STRING; clock_enable_output_a : STRING; intended_device_family : STRING; lpm_hint : STRING; lpm_type : STRING; numwords_a : NATURAL; operation_mode : STRING; outdata_aclr_a : STRING; outdata_reg_a : STRING; power_up_uninitialized : STRING; read_during_write_mode_port_a : STRING; widthad_a : NATURAL; width_a : NATURAL; width_byteena_a : NATURAL ); PORT ( address_a : IN STD_LOGIC_VECTOR (4 DOWNTO 0); clock0 : IN STD_LOGIC ; data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); wren_a : IN STD_LOGIC ; q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT; BEGIN q <= sub_wire0(7 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( clock_enable_input_a => "BYPASS", clock_enable_output_a => "BYPASS", intended_device_family => "Cyclone III", lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=PH_n", lpm_type => "altsyncram", numwords_a => 32, operation_mode => "SINGLE_PORT", outdata_aclr_a => "NONE", outdata_reg_a => "CLOCK0", power_up_uninitialized => "FALSE", read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", widthad_a => 5, width_a => 8, width_byteena_a => 1 ) PORT MAP ( address_a => address, clock0 => clock, data_a => data, wren_a => wren, q_a => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" -- Retrieval info: PRIVATE: AclrByte NUMERIC "0" -- Retrieval info: PRIVATE: AclrData NUMERIC "0" -- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: Clken NUMERIC "0" -- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1" -- Retrieval info: PRIVATE: JTAG_ID STRING "PH_n" -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -- Retrieval info: PRIVATE: MIFfilename STRING "" -- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32" -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" -- Retrieval info: PRIVATE: RegData NUMERIC "1" -- Retrieval info: PRIVATE: RegOutput NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" -- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" -- Retrieval info: PRIVATE: WidthAddr NUMERIC "5" -- Retrieval info: PRIVATE: WidthData NUMERIC "8" -- Retrieval info: PRIVATE: rden NUMERIC "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=PH_n" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" -- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5" -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -- Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL "address[4..0]" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" -- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" -- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" -- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" -- Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 -- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_n.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_n.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_n.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_n.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_n_inst.vhd FALSE -- Retrieval info: LIB_FILE: altera_mf
unlicense
014d0613221ebf2092c75b046af95e13
0.671946
3.438017
false
false
false
false
SoCdesign/EHA
RTL/Hand_Shaking/Hand_Shaking_FC/Arbiter.vhd
1
7,280
--Copyright (C) 2016 Siavoosh Payandeh Azad library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Arbiter is port ( reset: in std_logic; clk: in std_logic; Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules DCTS: in std_logic; -- Getting the CTS signal from the input FIFO of the next router/NI (for hand-shaking) Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot) Xbar_sel : out std_logic_vector(4 downto 0); -- select lines for XBAR RTS: out std_logic -- Valid output which is sent to the next router/NI to specify that the data on the output port is valid ); end; architecture behavior of Arbiter is -- next -- Arbiter router or NI -- --- ---------------------------- ---- ---- -- from LBDR ---> |Req(s) RTS | -----> |DRTS -- To FIFO <--- |Grant(s) DCTS| <----- |CTS -- to XBAR <--- |Xbar_sel | | -- --- ---------------------------- ---- ---- -------------------------------------------------------------------------------------------- -- an example of a request/grant + handshake process with next router or NI --CLK _|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|__ -- Req _____|'''''''''''''''''''''''''''''''''''''''''''|________ -- _________ ___________________ _______ _______ _______ ____ -- TX _________X_______HEADER______X_Body__X_Body__X__Tail_X____ -- Grant _________________________|'''|___|'''|___|'''|____________ -- RTs _________|'''''''''''''''''''|___|'''''''|___|'''''''|____ -- DCTS _________________________|'''|_______|'''|_______|'''|____ -- |<---------clear----------->| -- | to send | -------------------------------------------------------------------------------------------- TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local); SIGNAL state, state_in, next_state : STATE_TYPE := IDLE; SIGNAL RTS_FF, RTS_FF_in: std_logic; begin -- process for updating the state of arbiter's FSM, also setting RTS based on the state (if Grant is given or not) process(clk, reset)begin if reset = '0' then state<=IDLE; RTS_FF <= '0'; elsif clk'event and clk = '1' then -- no grant given yet, it might be that there is no request to -- arbiter or request is there, but the next router's/NI's FIFO is full state <= state_in; RTS_FF <= RTS_FF_in; end if; end process; -- anything below here is pure combinational RTS <= RTS_FF; process(RTS_FF, DCTS, state, next_state)begin if RTS_FF = '1' and DCTS = '0' then state_in <= state; else state_in <= next_state; end if; end process; process(state, RTS_FF, DCTS)begin if state = IDLE then RTS_FF_in <= '0'; -- if there was a grant given to one of the inputs, -- tell the next router/NI that the output data is valid else if RTS_FF = '1' and DCTS = '1' then RTS_FF_in <= '0'; else RTS_FF_in <= '1'; end if; end if ; end process; -- sets the grants using round robin -- the order is L --> N --> E --> W --> S and then back to L process(state, Req_N, Req_E, Req_W, Req_S, Req_L, DCTS, RTS_FF)begin Grant_N <= '0'; Grant_E <= '0'; Grant_W <= '0'; Grant_S <= '0'; Grant_L <= '0'; Xbar_sel<= "00000"; case(state) is when IDLE => Xbar_sel<= "00000"; If Req_L = '1' then next_state <= Local; elsif Req_N = '1' then next_state <= North; elsif Req_E = '1' then next_state <= East; elsif Req_W = '1' then next_state <= West; elsif Req_S = '1' then next_state <= South; else next_state <= IDLE; end if; when North => Grant_N <= DCTS and RTS_FF ; Xbar_sel<= "00001"; If Req_N = '1' then next_state <= North; elsif Req_E = '1' then next_state <= East; elsif Req_W = '1' then next_state <= West; elsif Req_S = '1' then next_state <= South; elsif Req_L = '1' then next_state <= Local; else next_state <= IDLE; end if; when East => Grant_E <= DCTS and RTS_FF; Xbar_sel<= "00010"; If Req_E = '1' then next_state <= East; elsif Req_W = '1' then next_state <= West; elsif Req_S = '1' then next_state <= South; elsif Req_L = '1' then next_state <= Local; elsif Req_N = '1' then next_state <= North; else next_state <= IDLE; end if; when West => Grant_W <= DCTS and RTS_FF; Xbar_sel<= "00100"; If Req_W = '1' then next_state <= West; elsif Req_S = '1' then next_state <= South; elsif Req_L = '1' then next_state <= Local; elsif Req_N = '1' then next_state <= North; elsif Req_E = '1' then next_state <= East; else next_state <= IDLE; end if; when South => Grant_S <= DCTS and RTS_FF; Xbar_sel<= "01000"; If Req_S = '1' then next_state <= South; elsif Req_L = '1' then next_state <= Local; elsif Req_N = '1' then next_state <= North; elsif Req_E = '1' then next_state <= East; elsif Req_W = '1' then next_state <= West; else next_state <= IDLE; end if; when others => -- Local Grant_L <= DCTS and RTS_FF; Xbar_sel<= "10000"; If Req_L = '1' then next_state <= Local; elsif Req_N = '1' then next_state <= North; elsif Req_E = '1' then next_state <= East; elsif Req_W = '1' then next_state <= West; elsif Req_S = '1' then next_state <= South; else next_state <= IDLE; end if; end case ; end process; end;
gpl-3.0
4a24755c11ba94846548a812d4097ed6
0.387637
4.369748
false
false
false
false
mgiacomini/mips-pipeline
ID_EX.vhd
1
3,441
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- Complete implementation of Patterson and Hennessy single cycle MIPS processor -- Copyright (C) 2015 Darci Luiz Tomasi Junior -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, version 3. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. -- -- Engineer: Darci Luiz Tomasi Junior -- E-mail: [email protected] -- Date : 29/06/2015 - 20:31 -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; ENTITY ID_EX IS PORT (clk : IN STD_LOGIC; RegDst : IN STD_LOGIC; Jump : IN STD_LOGIC; Branch : IN STD_LOGIC; MemRead : IN STD_LOGIC; MemtoReg : IN STD_LOGIC; ALUOp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); MemWrite : IN STD_LOGIC; ALUSrc : IN STD_LOGIC; RegWrite : IN STD_LOGIC; JumpAddr : in std_logic_vector(31 downto 0); RD1 : in std_logic_vector(31 downto 0); RD2 : in std_logic_vector(31 downto 0); RtE : in std_logic_vector(4 downto 0); RdE : in std_logic_vector(4 downto 0); SignExt : in std_logic_vector(31 downto 0); PCPlus4 : in std_logic_vector(31 downto 0); outRegDst : out std_logic; outJump : out std_logic; outBranch : out std_logic; outMemRead : out std_logic; outMemtoReg : out std_logic; outALUOp : out STD_LOGIC_VECTOR(1 DOWNTO 0); outMemWrite : out std_logic; outALUSrc : out std_logic; outRegWrite : out std_logic; outRD1 : out std_logic_vector(31 downto 0); outRD2 : out std_logic_vector(31 downto 0); outRtE : out std_logic_vector(4 downto 0); outRdE : out std_logic_vector(4 downto 0); outSignExt : out std_logic_vector(31 downto 0); outPCPlus4 : out std_logic_vector(31 downto 0); JumpAddrOut : out std_logic_vector(31 downto 0)); END; Architecture ARC_ID_EX of ID_EX is BEGIN PROCESS(clk) BEGIN IF( clk'event and clk = '1') THEN outRegWrite <= RegWrite; outMemtoReg <= MemtoReg; outMemWrite <= MemWrite; outBranch <= Branch; outALUOp <= ALUOp; outALUSrc <= ALUSrc; outRegDst <= RegDst; JumpAddrOut <= JumpAddr; outRD1 <= RD1; outRD2 <= RD2; outRtE <= RtE; outRdE <= RdE; outSignExt <= SignExt; outPCPlus4 <= PCPlus4; END IF; END PROCESS; END;
gpl-3.0
e62f8d1a044f9aed05d03ed18782a855
0.518454
4.16586
false
false
false
false
mgiacomini/mips-pipeline
EX_MEM.vhd
1
2,819
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- Complete implementation of Patterson and Hennessy single cycle MIPS processor -- Copyright (C) 2015 Darci Luiz Tomasi Junior -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, version 3. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. -- -- Engineer: Darci Luiz Tomasi Junior -- E-mail: [email protected] -- Date : 29/06/2015 - 20:31 -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; ENTITY EX_MEM IS PORT (clk : in std_logic; RegWrite : in std_logic; MemtoReg : in std_logic; MemWrite : in std_logic; MemRead : in std_logic; Branch : in std_logic; Jump : IN STD_LOGIC; ZeroM : in std_logic; AluOutM : in std_logic_vector(31 downto 0); --SAIDA DA ULA WriteDataM : in std_logic_vector(31 downto 0); -- VEM DA SAIDA 2 DE REG WriteRegM : in std_logic_vector(4 downto 0); -- REG DESTINO VEM DO MX_1 PcBranchM : in std_logic_vector(31 downto 0); --ENDERECO DE DESVIO CONDICIONAL outRegWrite : out std_logic; outMemtoReg : out std_logic; outMemWrite : out std_logic; outMemRead : out std_logic; outBranch : out std_logic; outZeroM : out std_logic; outAluOutM : out std_logic_vector(31 downto 0); outWriteDataM : out std_logic_vector(31 downto 0); outWriteRegM : out std_logic_vector(4 downto 0); outPcBranchM : out std_logic_vector(31 downto 0)); END; Architecture ARC_EX_MEM of EX_MEM is BEGIN PROCESS(clk) BEGIN IF( clk'event and clk = '1') THEN outRegWrite <= RegWrite; outMemtoReg <= MemtoReg; outMemWrite <=MemWrite; outMemRead <=MemRead; outBranch <= Branch; outZeroM <= ZeroM; outAluOutM <= AluOutM; outWriteDataM <= WriteDataM; outWriteRegM <= WriteRegM; outPcBranchM <= PcBranchM; END IF; END PROCESS; END;
gpl-3.0
d0f1d12597557d0bfb26367bb0afdf1b
0.554097
4.26475
false
false
false
false
TanND/Electronic
VHDL/D7_C2.vhd
1
680
library IEEE; use IEEE.STD_LOGIC_1164.all; entity D7_C2 is port( SI : in bit; sel : in bit_VECTOR(2 downto 0); SO : out bit_vector (7 downto 0) ); end D7_C2; architecture D7_C2 of D7_C2 is begin SO <= (SI & "0000000") when (sel="000") else ('0' & SI & "000000") when (sel="001") else ("00" & SI & "00000") when (sel="010") else ("000" & SI & "0000") when (sel="011") else ("0000" & SI & "000") when (sel="100") else ("00000" & SI & "00") when (sel="101") else ("000000" & SI & '0') when (sel="110") else ("0000000" & SI) ; end D7_C2; -- SI=random 1 ns; sel=random 3 ns;
apache-2.0
3bdefc5733728e2f005838bc6bea2b89
0.497059
2.893617
false
false
false
false
TanND/Electronic
VHDL/D2_C2.vhd
1
592
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; entity D2_C2 is port( rst : in STD_LOGIC; clk : in STD_LOGIC; seg : out STD_LOGIC_VECTOR(7 downto 0) ); end D2_C2; --}} End of automatically maintained section architecture D2_C2 of D2_C2 is begin process(rst,clk) variable dem:integer range 0 to 127; begin if (rst='1') then dem:=0; else if (rising_edge(clk)) then if(dem=127) then dem:=0; else dem:=dem+1; end if; end if; end if; seg<=conv_std_logic_vector(dem,8); end process; end D2_C2; -- rst=0 or 78Khz; clk=25Mhz;
apache-2.0
84935dc22150e4eb496d3df39954f10c
0.648649
2.529915
false
false
false
false
JarrettR/FPGA-Cryptoparty
FPGA/hdl/gen_tenhex.vhd
1
3,953
-------------------------------------------------------------------------------- -- gen_tenhex.vhd -- Test 10-digit hex sample PMK generator, because the ZTEX comm bus is slow -- Copyright (C) 2016 Jarrett Rainier -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.sha1_pkg.all; entity gen_tenhex is port( clk_i : in std_ulogic; rst_i : in std_ulogic; load_i : in std_ulogic; start_i : in std_ulogic; start_val_i : in mk_data; end_val_i : in mk_data; complete_o : out std_ulogic := '0'; dat_mk_o : out mk_data ); end gen_tenhex; architecture RTL of gen_tenhex is signal w: w_input; signal w_temp: w_input; signal complete: std_ulogic := '0'; signal running: std_ulogic := '0'; signal carry: unsigned(0 to MK_SIZE + 1) := "00000000001"; --Ten digit, hex (16^10) signal mk : mk_data := (others => "00000000"); signal mk_end : mk_data := (others => "00000000"); signal mk_next : mk_data := (others => "00000000"); begin process(clk_i) variable continue_carry: std_ulogic; variable complete_v: std_ulogic; begin if (clk_i'event and clk_i = '1') then if rst_i = '1' then complete <= '0'; running <= '0'; elsif load_i = '1' then for i in 0 to MK_SIZE loop --Todo: fix to start_val_i and end_val_i mk(i) <= start_val_i(i); mk_end(i) <= end_val_i(i); --mk(i) <= start_val(i); --mk_end(i) <= end_val(i); end loop; elsif start_i = '1' then running <= '1'; elsif running = '1' then complete_v := '1'; for i in MK_SIZE downto 0 loop if mk(i) /= mk_end(i) then complete_v := '0'; end if; end loop; if complete_v = '0' then for i in MK_SIZE downto 0 loop if carry(i + 1) = '1' and continue_carry = '1' then mk(i) <= mk_next(i); else continue_carry := '0'; end if; end loop; continue_carry := '1'; end if; complete <= complete_v; running <= not complete_v; end if; end if; end process; dat_mk_o <= mk; complete_o <= complete; mk_inc: for i in MK_SIZE downto 0 generate begin with mk(i) select mk_next(i) <= X"61" when X"39", X"30" when X"66", mk(i) + 1 when others; with mk(i) select carry(i) <= '1' when X"66", '0' when others; end generate mk_inc; end RTL;
gpl-3.0
0b09b2961788798fe22f9146f381a799
0.453327
4.013198
false
false
false
false
lnls-dig/dsp-cores
hdl/testbench/cordic_iter/cordic_tb.vhd
1
6,678
------------------------------------------------------------------------------- -- Title : Testbench for CORDIC -- Project : ------------------------------------------------------------------------------- -- File : cordic_tb.vhd -- Author : aylons <aylons@LNLS190> -- Company : -- Created : 2015-05-06 -- Last update: 2015-05-28 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: This testbench depends on GNU Octave .m files to generate -- signals and to check them in the output. A Modelsim-compatible TCL run.do -- file invokes GNU Octave to both generate the input data and to check outputs. ------------------------------------------------------------------------------- -- Copyright (c) 2015 Aylons -- This program is free software: you can redistribute it and/or -- modify it under the terms of the GNU Lesser General Public License -- as published by the Free Software Foundation, either version 3 of -- the License, or (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- Lesser General Public License for more details. -- -- You should have received a copy of the GNU Lesser General Public -- License along with this program. If not, see -- <http://www.gnu.org/licenses/>. ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2015-05-06 1.0 aylons Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; library std; use std.textio.all; library UNISIM; use UNISIM.vcomponents.all; library work; use work.test_pkg.all; entity cordic_tb is end entity cordic_tb; architecture test of cordic_tb is constant c_CLK_FREQ : real := 100.0e6; -- input clock frequency constant c_CYCLES_TO_RESET : natural := 4; -- number of clock cycles before reset constant c_CYCLES_TO_CE : natural := 10; -- number of clock cycles before reset constant c_INPUT_FILE : string := "input.samples"; constant c_OUTPUT_FILE : string := "output.samples"; constant c_INPUT_WIDTH : positive := 32; constant c_OUTPUT_WIDTH : positive := 32; constant c_INTERNAL_WIDTH : positive := 38; -- output_width + log2(c_ITER) + -- 2 constant c_PHASE_OUTPUT_WIDTH : positive := 32; -- width of phase output constant c_PHASE_INTERNAL_WIDTH : positive := 34; -- width of cordic phase constant c_ITER : positive := 16; -- number of cordic steps constant c_ITER_PER_CLK : positive := 2; -- number of iterations per clock cycle constant c_USE_CE : boolean := true; -- clock enable in cordic constant c_ROUNDING : boolean := true; -- enable rounding in cordic constant c_USE_INREG : boolean := true; -- use input register signal clk : std_ulogic := '0'; -- clock signal signal rst : std_ulogic := '1'; -- reset signal signal ce : std_ulogic := '0'; -- clock enable signal valid_in : std_ulogic; -- signals valid input data signal valid_out : std_ulogic; -- signals new valid output signal cordic_busy : std_ulogic; -- signals cordic not ready for new inputs signal cordic_ready : std_ulogic; -- negated cordic_busy signal end_of_file : std_ulogic; signal x : signed(c_INPUT_WIDTH-1 downto 0); -- x from the input signal y : signed(c_INPUT_WIDTH-1 downto 0); -- y from the input signal mag : signed(c_OUTPUT_WIDTH-1 downto 0); -- magnitude from X output in -- cordic signal phase : signed(c_PHASE_OUTPUT_WIDTH-1 downto 0); -- phase from PH output of cordic component cordic is generic ( XY_CALC_WID : positive; XY_IN_WID : positive; X_OUT_WID : positive; PH_CALC_WID : positive; PH_OUT_WID : positive; NUM_ITER : positive; ITER_PER_CLK : positive; USE_INREG : boolean; USE_CE : boolean; ROUNDING : boolean); port ( clk : in std_logic; ce : in std_logic; b_start_in : in std_logic; s_x_in : in signed (XY_IN_WID-1 downto 0); s_y_in : in signed (XY_IN_WID-1 downto 0); s_x_o : out signed (X_OUT_WID-1 downto 0); s_ph_o : out signed (PH_OUT_WID-1 downto 0); b_rdy_o : out std_logic; b_busy_o : out std_logic); end component cordic; begin -- architecture test p_clk_gen ( clk => clk, c_FREQ => c_CLK_FREQ); p_rst_gen ( clk => clk, rst => rst, c_CYCLES => 2); p_ce_gen ( clk => clk, ce => ce, rst => rst, c_CYCLES => c_CYCLES_TO_CE); p_read_tsv_file_signed ( c_INPUT_FILE_NAME => c_INPUT_FILE, c_SAMPLES_PER_LINE => 2, c_OUTPUT_WIDTH => c_INPUT_WIDTH, --input for the testbench, output for --the procedure clk => clk, rst => rst, ce => ce, req => cordic_ready, sample(0) => x, sample(1) => y, valid => valid_in, end_of_file => end_of_file); cordic_ready <= not cordic_busy; uut : cordic generic map ( XY_CALC_WID => c_INTERNAL_WIDTH, XY_IN_WID => c_INPUT_WIDTH, X_OUT_WID => c_OUTPUT_WIDTH, PH_CALC_WID => c_PHASE_INTERNAL_WIDTH, PH_OUT_WID => c_PHASE_OUTPUT_WIDTH, NUM_ITER => c_ITER, ITER_PER_CLK => c_ITER_PER_CLK, USE_INREG => c_USE_INREG, USE_CE => c_USE_CE, ROUNDING => c_ROUNDING) port map ( clk => clk, ce => ce, b_start_in => valid_in, b_busy_o => cordic_busy, s_x_in => x, s_y_in => y, s_x_o => mag, s_ph_o => phase, b_rdy_o => valid_out); p_write_tsv_file_signed ( c_OUTPUT_FILE_NAME => c_OUTPUT_FILE, c_SAMPLES_PER_LINE => 2, c_OUTPUT_WIDTH => c_OUTPUT_WIDTH, clk => clk, rst => rst, ce => ce, sample(0) => mag, sample(1) => phase, valid => valid_out, end_of_file => end_of_file); end architecture test;
lgpl-3.0
89012270573d43f3b85a1395d64aa548
0.528302
3.743274
false
false
false
false
SoCdesign/EHA
RTL/Credit_Based/Credit_Based_FC/FIFO_one_hot_credit_based_packet_drop.vhd
1
16,433
--Copyright (C) 2016 Siavoosh Payandeh Azad library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_misc.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity FIFO_credit_based is generic ( DATA_WIDTH: integer := 32 ); port ( reset: in std_logic; clk: in std_logic; RX: in std_logic_vector(DATA_WIDTH-1 downto 0); valid_in: in std_logic; read_en_N : in std_logic; read_en_E : in std_logic; read_en_W : in std_logic; read_en_S : in std_logic; read_en_L : in std_logic; credit_out: out std_logic; empty_out: out std_logic; Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0) ); end FIFO_credit_based; architecture behavior of FIFO_credit_based is signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(3 downto 0); signal full, empty: std_logic; signal read_en, write_en: std_logic; signal FIFO_MEM_1, FIFO_MEM_1_in : std_logic_vector(DATA_WIDTH-1 downto 0); signal FIFO_MEM_2, FIFO_MEM_2_in : std_logic_vector(DATA_WIDTH-1 downto 0); signal FIFO_MEM_3, FIFO_MEM_3_in : std_logic_vector(DATA_WIDTH-1 downto 0); signal FIFO_MEM_4, FIFO_MEM_4_in : std_logic_vector(DATA_WIDTH-1 downto 0); constant fake_tail : std_logic_vector := "10000000000000000000000000000001"; alias flit_type : std_logic_vector(2 downto 0) is RX(DATA_WIDTH-1 downto DATA_WIDTH-3); signal faulty_packet_in, faulty_packet_out: std_logic; signal xor_all, fault_out: std_logic; type state_type is (Idle, Header_flit, Body_flit, Tail_flit, Packet_drop); signal state_out, state_in : state_type; signal fake_credit, credit_in, write_fake_flit: std_logic; signal fake_credit_counter, fake_credit_counter_in: std_logic_vector(1 downto 0); begin -------------------------------------------------------------------------------------------- -- block diagram of the FIFO! -------------------------------------------------------------------------------------------- -- circular buffer structure -- <--- WriteP -- --------------------------------- -- | 3 | 2 | 1 | 0 | -- --------------------------------- -- <--- readP -------------------------------------------------------------------------------------------- -- Packet drop state machine -- +---+ No +---+ No -- | | Flit | | Flit -- | v | v -- +--------+ +--------+ -- healthy | | | |-------------------+ -- +---header-->| Header |---Healthy body-->| Body |------------+ | -- | +--------+ +--------+ | | -- | | ^ | Healthy | ^ Healthy | -- | | | | body | | Tail | -- | | | | +---+ | | -- | | | | v | -- +--------+ | | | +--------+ | -- No +-->| | | | +-----------------Healthy Tail------>| | | -- Flit| | IDLE | | | | Tail |--)--+ -- +---| | | +-----------Healthy Header--------------| | | | -- +--------+ | +--------+ | | -- ^ | ^ | No Faulty | | -- | | | | Flit Flit | | -- | | | +-Faulty Flit+ +---+ +---+ | | -- | | | | | | | | | | -- | | | v | v | v | | -- | | | +------------------+ | | -- | | +----Healthy Tail-----| Packet | | | -- | +-------Faulty Flit----->| Drop |<-----------------------+ | -- | +------------------+ | -- +-------------------------------------------------No Flit------------------+ -- ------------------------------------------------------------------------------------------------ process (clk, reset)begin if reset = '0' then read_pointer <= "0001"; write_pointer <= "0001"; FIFO_MEM_1 <= (others=>'0'); FIFO_MEM_2 <= (others=>'0'); FIFO_MEM_3 <= (others=>'0'); FIFO_MEM_4 <= (others=>'0'); fake_credit_counter <= (others=>'0'); faulty_packet_out <= '0'; credit_out <= '0'; state_out <= Idle; elsif clk'event and clk = '1' then write_pointer <= write_pointer_in; read_pointer <= read_pointer_in; state_out <= state_in; faulty_packet_out <= faulty_packet_in; credit_out <= credit_in; fake_credit_counter <= fake_credit_counter_in; if write_en = '1' then --write into the memory FIFO_MEM_1 <= FIFO_MEM_1_in; FIFO_MEM_2 <= FIFO_MEM_2_in; FIFO_MEM_3 <= FIFO_MEM_3_in; FIFO_MEM_4 <= FIFO_MEM_4_in; end if; end if; end process; -- anything below here is pure combinational -- combinatorial part process(fake_credit, read_en, fake_credit_counter) begin fake_credit_counter_in <= fake_credit_counter; credit_in <= '0'; if fake_credit = '1' and read_en = '1' then fake_credit_counter_in <= fake_credit_counter + 1 ; end if; if (read_en ='1' or fake_credit = '1') then credit_in <= '1'; end if; if read_en = '0' and fake_credit = '0' and fake_credit_counter > 0 then fake_credit_counter_in <= fake_credit_counter - 1 ; credit_in <= '1'; end if; end process; process(valid_in, RX) begin if valid_in = '1' then xor_all <= XOR_REDUCE(RX(DATA_WIDTH-1 downto 1)); else xor_all <= '0'; end if; end process; process(valid_in, RX, xor_all)begin fault_out <= '0'; if valid_in = '1' and xor_all /= RX(0) then fault_out <= '1'; end if; end process; process(RX, faulty_packet_out, fault_out, write_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4, state_out, flit_type, valid_in)begin -- this is the default value of the memory! case( write_pointer ) is when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4; when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX; when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; end case ; --some defaults fake_credit <= '0'; state_in <= state_out; faulty_packet_in <= faulty_packet_out; write_fake_flit <= '0'; case(state_out) is when Idle => if fault_out = '0' then if valid_in = '1' then state_in <= Header_flit; else state_in <= state_out; end if; else fake_credit <= '1'; FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; state_in <= Packet_drop; faulty_packet_in <= '1'; end if; when Header_flit => if valid_in = '1' then if fault_out = '0' then if flit_type = "010" then state_in <= Body_flit; elsif flit_type ="100" then state_in <= Tail_flit; else -- we should not be here! state_in <= state_out; end if; else write_fake_flit <= '1'; case( write_pointer ) is when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4; when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail; when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; end case ; state_in <= Packet_drop; faulty_packet_in <= '1'; end if; else state_in <= state_out; end if; when Body_flit => if valid_in = '1' then if fault_out = '0' then if flit_type = "010" then state_in <= state_out; elsif flit_type = "100" then state_in <= Tail_flit; else -- we should not be here! state_in <= state_out; end if; else write_fake_flit <= '1'; case( write_pointer ) is when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4; when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail; when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; end case ; state_in <= Packet_drop; faulty_packet_in <= '1'; end if; else state_in <= state_out; end if; when Tail_flit => if valid_in = '1' then if fault_out = '0' then if flit_type = "001" then state_in <= Header_flit; else state_in <= state_out; end if; else fake_credit <= '1'; FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; state_in <= Packet_drop; faulty_packet_in <= '1'; end if; else state_in <= state_out; end if; when Packet_drop => if faulty_packet_out = '1' then if valid_in = '1' and flit_type = "001" and fault_out = '0' then faulty_packet_in <= '0'; state_in <= Header_flit; write_fake_flit <= '1'; case( write_pointer ) is when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4; when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX; when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; end case ; elsif valid_in = '1' and flit_type ="100" and fault_out = '0' then FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; faulty_packet_in <= '0'; state_in <= Idle; fake_credit <= '1'; else if valid_in = '1' then fake_credit <= '1'; end if; FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; state_in <= state_out; end if; else -- we should not be here! state_in <= state_out; end if; when others => state_in <= state_out; end case; end process; process(read_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin case( read_pointer ) is when "0001" => Data_out <= FIFO_MEM_1; when "0010" => Data_out <= FIFO_MEM_2; when "0100" => Data_out <= FIFO_MEM_3; when "1000" => Data_out <= FIFO_MEM_4; when others => Data_out <= FIFO_MEM_1; end case ; end process; read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty; empty_out <= empty; process(write_en, write_pointer)begin if write_en = '1' then write_pointer_in <= write_pointer(2 downto 0)&write_pointer(3); else write_pointer_in <= write_pointer; end if; end process; process(read_en, empty, read_pointer)begin if (read_en = '1' and empty = '0') then read_pointer_in <= read_pointer(2 downto 0)&read_pointer(3); else read_pointer_in <= read_pointer; end if; end process; process(full, valid_in, write_fake_flit, faulty_packet_out, fault_out) begin if valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full ='0' then write_en <= '1'; else write_en <= '0'; end if; end process; process(write_pointer, read_pointer) begin if read_pointer = write_pointer then empty <= '1'; else empty <= '0'; end if; -- if write_pointer = read_pointer>>1 then if write_pointer = read_pointer(0)&read_pointer(3 downto 1) then full <= '1'; else full <= '0'; end if; end process; end;
gpl-3.0
766cf67fde121d083718fc600afc5faf
0.408568
3.680403
false
false
false
false
JarrettR/FPGA-Cryptoparty
FPGA/hdl/ztex_wrapper.vhd
1
6,632
library ieee; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use IEEE.std_logic_unsigned.all; use work.sha1_pkg.all; entity ztex_wrapper is port( fd : inout std_logic_vector(15 downto 0); CS : in std_logic; IFCLK : in std_logic; --FXCLK : in std_logic; --sck_i : in std_logic; SLOE : out std_logic; SLRD : out std_logic; SLWR : out std_logic; FIFOADR : out std_logic_vector(1 downto 0); FLAGA : in std_logic; --PF FLAGB : in std_logic; --Full FLAGC : in std_logic; --Empty PKTEND : out std_logic; RESET : in std_logic; RUN : in std_logic -- SCL : in std_logic; -- SDA : in std_logic ); end ztex_wrapper; architecture RTL of ztex_wrapper is COMPONENT fx2_fifo PORT ( rst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; rd_clk : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(15 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC; almost_empty : OUT STD_LOGIC ); END COMPONENT; signal fd_buf : std_logic_vector(15 downto 0); signal fd_in : std_logic_vector(15 downto 0); signal fd_out : std_logic_vector(15 downto 0); signal sloe_buf: std_ulogic; signal slrd_buf: std_ulogic; signal slwr_buf: std_ulogic; signal pktend_buf: std_ulogic; signal fifoadr_buf: std_logic_vector(1 downto 0); --FIFOS signal in_fifo_wr_en: std_ulogic; signal in_fifo_rd_en: std_ulogic; signal in_fifo_full: std_ulogic; signal in_fifo_empty: std_ulogic; signal in_fifo_almost_empty: std_ulogic; signal out_fifo_wr_en: std_ulogic; signal out_fifo_rd_en: std_ulogic; signal out_fifo_full: std_ulogic; signal out_fifo_empty: std_ulogic; signal out_fifo_almost_empty: std_ulogic; signal direction: std_ulogic; --Data signal datablock: ssid_data; type state_type is (STATE_ERROR, STATE_READY, STATE_INPUT, STATE_READ_INPUT, STATE_READ_PROGRESS, STATE_WORKING, STATE_FINISH_FAIL, STATE_FINISH_SUCCEED ); type cmd_type is (CMD_WAIT, --00 CMD_WRITE, --01 CMD_READ, --10 CMD_ERROR --11 ); type data_type is (DATA_NULL, --00 DATA_SSID, --01 DATA_MK, --10 DATA_ERROR --11 ); signal state : state_type := STATE_ERROR; signal command : cmd_type; signal datatype : data_type; signal dataaddr : integer range 0 to 35; signal data : std_logic_vector(7 downto 0); begin SLOE <= sloe_buf when CS = '1' else 'Z'; SLRD <= slrd_buf when CS = '1' else 'Z'; SLWR <= slwr_buf when CS = '1' else 'Z'; FIFOADR <= fifoadr_buf when CS = '1' else "ZZ"; PKTEND <= pktend_buf when CS = '1' else 'Z'; --Unused fd <= fd_out when CS = '1' and direction = '0' else (others => 'Z'); fifoadr_buf <= "10" when direction = '1' else "00"; sloe_buf <= '0' when direction = '1' else '1'; slrd_buf <= '0' when direction = '1' and FLAGC = '1' else '1'; --Input and FX2 not empty --slwr_buf <= '0' when direction = '0' else '1'; --FX2 Flow control direction <= '0' when out_fifo_empty = '0' and FLAGB = '1' else '1'; pktend_buf <= '0' when out_fifo_almost_empty = '1' and out_fifo_rd_en = '1' else '1'; in_fifo_wr_en <= '1' when direction = '1' and CS = '1' and flagc = '1' else '0'; slwr_buf <= '0' when out_fifo_rd_en = '1' and flagb = '1' else '1'; in_fifo : fx2_fifo port map ( rst => RESET, wr_clk => IFCLK, rd_clk => IFCLK, din => fd, wr_en => in_fifo_wr_en, rd_en => in_fifo_rd_en, dout => fd_in, full => in_fifo_full, empty => in_fifo_empty, almost_empty => in_fifo_almost_empty ); out_fifo : fx2_fifo port map ( rst => RESET, wr_clk => IFCLK, rd_clk => IFCLK, din => fd_buf, wr_en => out_fifo_wr_en, rd_en => out_fifo_rd_en, dout => fd_out, full => out_fifo_full, empty => out_fifo_empty, almost_empty => out_fifo_almost_empty ); ztex_comm: process(IFCLK, RESET) begin if RESET = '1' then fd_buf <= X"ce5d"; in_fifo_rd_en <= '1'; out_fifo_rd_en <= '0'; state <= STATE_READY; elsif IFCLK'event and IFCLK = '1' then if in_fifo_empty = '0' then if fd_in(15 downto 14) = "00" then command <= CMD_WAIT; elsif fd_in(15 downto 14) = "01" then command <= CMD_WRITE; elsif fd_in(15 downto 14) = "10" then command <= CMD_READ; else command <= CMD_ERROR; end if; if fd_in(13 downto 12) = "00" then datatype <= DATA_NULL; elsif fd_in(13 downto 12) = "01" then datatype <= DATA_SSID; elsif fd_in(13 downto 12) = "10" then datatype <= DATA_MK; else datatype <= DATA_ERROR; end if; dataaddr <= to_integer(unsigned(fd_in(11 downto 8))); data <= fd_in(7 downto 0); else command <= CMD_WAIT; end if; if state = STATE_READY then out_fifo_wr_en <= '0'; if command = CMD_WRITE then datablock(dataaddr) <= unsigned(data); elsif command = CMD_READ then out_fifo_wr_en <= '1'; fd_buf <= fd_in(15 downto 8) & std_logic_vector(datablock(dataaddr)); end if; elsif state = STATE_READ_INPUT then state <= STATE_READY; end if; --Todo fix for multiple clock domains if direction = '0' then out_fifo_rd_en <= not out_fifo_rd_en; end if; end if; end process ztex_comm; end RTL;
gpl-3.0
f53bd9e5f52770a852320f2cbe248b65
0.484771
3.588745
false
false
false
false
JarrettR/FPGA-Cryptoparty
FPGA/hdl/state_machine.vhd
1
4,375
library ieee; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use IEEE.std_logic_unsigned.all; use work.sha1_pkg.all; entity state_machine is port( IFCLK : in std_logic; rst_i : in std_logic; enable_i : in std_logic; dat_i : in std_logic_vector(7 downto 0); state_o : out integer range 0 to 5; ssid_o : out std_logic_vector(7 downto 0); dat_mk_o : out mk_data; dat_o : out std_logic_vector(7 downto 0); valid_o : out std_ulogic ); end state_machine; architecture RTL of state_machine is component gen_tenhex port( clk_i : in std_ulogic; rst_i : in std_ulogic; load_i : in std_ulogic; start_i : in std_ulogic; start_val_i : in mk_data; end_val_i : in mk_data; complete_o : out std_ulogic; dat_mk_o : out mk_data ); end component; --signal declaration signal state_buff : integer range 0 to 5; signal cmd_buff : std_logic_vector(7 downto 0); signal count : integer range 0 to 9; constant count_max : integer := 9; --gen_tenhex helpers signal load_gen: std_ulogic; signal start_gen: std_ulogic; signal gen_complete: std_ulogic; signal mk_initial: mk_data; signal mk_end: mk_data; signal mk: mk_data; signal mk_read: mk_data; type state_type is (STATE_ERROR, STATE_READY, STATE_INPUT, STATE_READ_INPUT, STATE_READ_PROGRESS, STATE_WORKING, STATE_FINISH_FAIL, STATE_FINISH_SUCCEED ); signal state : state_type := STATE_ERROR; type command_type is (CMD_ERROR, CMD_NULL, CMD_INPUT, CMD_READ_INPUT, CMD_STATUS, CMD_ABORT, CMD_OUTPUT ); signal command : command_type := CMD_ERROR; begin command <= CMD_INPUT when dat_i = X"01" and state = STATE_READY else CMD_READ_INPUT when dat_i = X"02" and state = STATE_READY else CMD_NULL when not (state = STATE_READY) else CMD_ERROR; ztex_state_machine: process(IFCLK) begin if IFCLK'event and IFCLK = '1' then if rst_i = '1' then state <= STATE_READY; dat_o <= X"00"; valid_o <= '0'; for i in 0 to count_max loop mk_initial(i) <= X"00"; end loop; elsif ( enable_i = '1' ) then if ( state = STATE_READY ) then --STATE_READY valid_o <= '0'; if ( command = CMD_INPUT ) then state <= STATE_INPUT; count <= 0; elsif ( command = CMD_READ_INPUT ) then state <= STATE_READ_INPUT; end if; elsif ( state = STATE_INPUT ) then --STATE_INPUT if ( count < count_max ) then mk_initial(count) <= unsigned(dat_i); count <= count + 1; else mk_initial(count) <= unsigned(dat_i); count <= 0; state <= STATE_READY; end if; elsif ( state = STATE_READ_INPUT ) then --STATE_READ_INPUT valid_o <= '1'; if ( count < count_max ) then dat_o <= std_logic_vector(mk_initial(count)); count <= count + 1; else dat_o <= std_logic_vector(mk_initial(count)); count <= 0; state <= STATE_READY; end if; --else end if; else valid_o <= '0'; end if; --count <= count + '1'; end if; end process ztex_state_machine; end RTL;
gpl-3.0
bcfbc02000c4deb35c58afe98816e1db
0.432686
4.268293
false
false
false
false
SoCdesign/EHA
RTL/Immortal_Chip/LBDR_checkers.vhd
2
7,361
library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.ALL; entity LBDR_checkers is generic ( cur_addr_rst: integer := 5; NoC_size: integer := 4 ); port ( empty: in std_logic; flit_type: in std_logic_vector(2 downto 0); Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic; Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic; N1_out, E1_out, W1_out, S1_out: in std_logic; dst_addr: in std_logic_vector(NoC_size-1 downto 0); -- Checker outputs --err_header_not_empty_Requests_in_onehot, err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero, err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_not_Req_L_in, err_dst_addr_cur_addr_Req_L_in, err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in : out std_logic ); end LBDR_checkers; architecture behavior of LBDR_checkers is signal cur_addr: std_logic_vector(NoC_size-1 downto 0); signal Requests_FF: std_logic_vector(4 downto 0); signal Requests_in: std_logic_vector(4 downto 0); begin cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length)); Requests_FF <= Req_N_FF & Req_E_FF & Req_W_FF & Req_S_FF & Req_L_FF; Requests_in <= Req_N_in & Req_E_in & Req_W_in & Req_S_in & Req_L_in; -- Implementing checkers in form of concurrent assignments (combinational assertions) --process (flit_type, empty, Requests_in) --begin -- if (flit_type = "001" and empty = '0' and Requests_in /= "00001" and Requests_in /= "00010" and Requests_in /= "00100" and -- Requests_in /= "01000" and Requests_in /= "10000") then -- err_header_not_empty_Requests_in_onehot <= '1'; -- else -- err_header_not_empty_Requests_in_onehot <= '0'; -- end if; --end process; process (flit_type, empty, Requests_FF, Requests_in) begin if (flit_type = "001" and empty = '1' and Requests_FF /= Requests_in) then err_header_empty_Requests_FF_Requests_in <= '1'; else err_header_empty_Requests_FF_Requests_in <= '0'; end if; end process; process (flit_type, Requests_in) begin if (flit_type = "100" and Requests_in /= "00000") then err_tail_Requests_in_all_zero <= '1'; else err_tail_Requests_in_all_zero <= '0'; end if; end process; process (flit_type, Requests_FF, Requests_in) begin if (flit_type /= "001" and flit_type /= "100" and Requests_FF /= Requests_in) then err_header_tail_Requests_FF_Requests_in <= '1'; else err_header_tail_Requests_FF_Requests_in <= '0'; end if; end process; process (cur_addr, dst_addr, N1_out) begin if ( dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) and N1_out = '0') then err_dst_addr_cur_addr_N1 <= '1'; else err_dst_addr_cur_addr_N1 <= '0'; end if; end process; process (cur_addr, dst_addr, N1_out) begin if ( dst_addr(NoC_size-1 downto NoC_size/2) >= cur_addr(NoC_size-1 downto NoC_size/2) and N1_out = '1') then err_dst_addr_cur_addr_not_N1 <= '1'; else err_dst_addr_cur_addr_not_N1 <= '0'; end if; end process; process (cur_addr, dst_addr, E1_out) begin if ( cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) and E1_out = '0') then err_dst_addr_cur_addr_E1 <= '1'; else err_dst_addr_cur_addr_E1 <= '0'; end if; end process; process (cur_addr, dst_addr, E1_out) begin if ( cur_addr((NoC_size/2)-1 downto 0) >= dst_addr((NoC_size/2)-1 downto 0) and E1_out = '1') then err_dst_addr_cur_addr_not_E1 <= '1'; else err_dst_addr_cur_addr_not_E1 <= '0'; end if; end process; process (cur_addr, dst_addr, W1_out) begin if ( dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) and W1_out = '0') then err_dst_addr_cur_addr_W1 <= '1'; else err_dst_addr_cur_addr_W1 <= '0'; end if; end process; process (cur_addr, dst_addr, W1_out) begin if ( dst_addr((NoC_size/2)-1 downto 0) >= cur_addr((NoC_size/2)-1 downto 0) and W1_out = '1') then err_dst_addr_cur_addr_not_W1 <= '1'; else err_dst_addr_cur_addr_not_W1 <= '0'; end if; end process; process (cur_addr, dst_addr, S1_out) begin if ( cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) and S1_out = '0') then err_dst_addr_cur_addr_S1 <= '1'; else err_dst_addr_cur_addr_S1 <= '0'; end if; end process; process (cur_addr, dst_addr, S1_out) begin if ( cur_addr(NoC_size-1 downto NoC_size/2) >= dst_addr(NoC_size-1 downto NoC_size/2) and S1_out = '1') then err_dst_addr_cur_addr_not_S1 <= '1'; else err_dst_addr_cur_addr_not_S1 <= '0'; end if; end process; process (flit_type, empty, N1_out, E1_out, W1_out, S1_out, Req_L_in) begin if ( flit_type = "001" and empty = '0' and Req_L_in /= (not N1_out and not E1_out and not W1_out and not S1_out) ) then err_dst_addr_cur_addr_not_Req_L_in <= '1'; else err_dst_addr_cur_addr_not_Req_L_in <= '0'; end if; end process; process (flit_type, empty, cur_addr, dst_addr, Req_L_in) begin if ( flit_type = "001" and empty = '0' and cur_addr /= dst_addr and Req_L_in = '1') then err_dst_addr_cur_addr_Req_L_in <= '1'; else err_dst_addr_cur_addr_Req_L_in <= '0'; end if; end process; process (flit_type, empty, Req_N_in, N1_out, E1_out, W1_out) begin if ( flit_type = "001" and empty = '0' and Req_N_in /= (N1_out and not E1_out and not W1_out) ) then err_header_not_empty_Req_N_in <= '1'; else err_header_not_empty_Req_N_in <= '0'; end if; end process; process (flit_type, empty, Req_E_in, N1_out, E1_out, S1_out) begin if ( flit_type = "001" and empty = '0' and Req_E_in /= ((E1_out and not N1_out and not S1_out) or (E1_out and N1_out) or (E1_out and S1_out)) ) then err_header_not_empty_Req_E_in <= '1'; else err_header_not_empty_Req_E_in <= '0'; end if; end process; process (flit_type, empty, Req_W_in, N1_out, W1_out, S1_out) begin if ( flit_type = "001" and empty = '0' and Req_W_in /= ((W1_out and not N1_out and not S1_out) or (W1_out and N1_out) or (W1_out and S1_out)) ) then err_header_not_empty_Req_W_in <= '1'; else err_header_not_empty_Req_W_in <= '0'; end if; end process; process (flit_type, empty, Req_S_in, E1_out, W1_out, S1_out) begin if ( flit_type = "001" and empty = '0' and Req_S_in /= (S1_out and not E1_out and not W1_out) ) then err_header_not_empty_Req_S_in <= '1'; else err_header_not_empty_Req_S_in <= '0'; end if; end process; end behavior;
gpl-3.0
d3b5ad6b2a9e79afdfbe62cab6e788ab
0.59299
2.659321
false
false
false
false
SoCdesign/EHA
RTL/Credit_Based/Checkers/Control_Part_Checkers/Arbiter_in_credit_based_checkers/RTL_and_Synthesis/arbiter_in_one_hot_pseudo.vhd
1
4,152
--Copyright (C) 2016 Siavoosh Payandeh Azad library ieee; use ieee.std_logic_1164.all; -- Is this like the old arbiter in the router with handshaking FC ?? entity arbiter_in_one_hot_pseudo is port ( req_X_N, req_X_E, req_X_W, req_X_S, req_X_L:in std_logic; -- From LBDR modules state: in std_logic_vector (5 downto 0); -- 6 states for Arbiter_in's FSM X_N, X_E, X_W, X_S, X_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot) state_in: out std_logic_vector (5 downto 0) -- 6 states for Arbiter's FSM ); end; architecture behavior of arbiter_in_one_hot_pseudo is CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001"; CONSTANT Local: std_logic_vector (5 downto 0) := "000010"; CONSTANT North: std_logic_vector (5 downto 0) := "000100"; CONSTANT East: std_logic_vector (5 downto 0) := "001000"; CONSTANT West: std_logic_vector (5 downto 0) := "010000"; CONSTANT South: std_logic_vector (5 downto 0) := "100000"; -- anything below here is pure combinational begin process(state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L) begin X_N <= '0'; X_E <= '0'; X_W <= '0'; X_S <= '0'; X_L <= '0'; case state is when IDLE => -- In the arbiter for hand-shaking FC router, L had the highest priority (L, N, E, W, S) -- Here it seems N has the higest priority, am I correct ? if req_X_N ='1' then state_in <= North; X_N <= '1'; elsif req_X_E = '1' then state_in <= East; X_E <= '1'; elsif req_X_W = '1' then state_in <= West; X_W <= '1'; elsif req_X_S = '1' then state_in <= South; X_S <= '1'; elsif req_X_L = '1' then state_in <= Local; X_L <= '1'; else state_in <= state; end if; when North => if req_X_N ='1' then state_in <= North; X_N <= '1'; elsif req_X_E = '1' then state_in <= East; X_E <= '1'; elsif req_X_W = '1' then state_in <= West; X_W <= '1'; elsif req_X_S = '1' then state_in <= South; X_S <= '1'; elsif req_X_L = '1' then state_in <= Local; X_L <= '1'; else state_in <= state; end if; when East => if req_X_E = '1' then state_in <= East; X_E <= '1'; elsif req_X_W = '1' then state_in <= West; X_W <= '1'; elsif req_X_S = '1' then state_in <= South; X_S <= '1'; elsif req_X_L = '1' then state_in <= Local; X_L <= '1'; elsif req_X_N ='1' then state_in <= North; X_N <= '1'; else state_in <= state; end if; when West => if req_X_W = '1' then state_in <= West; X_W <= '1'; elsif req_X_S = '1' then state_in <= South; X_S <= '1'; elsif req_X_L = '1' then state_in <= Local; X_L <= '1'; elsif req_X_N ='1' then state_in <= North; X_N <= '1'; elsif req_X_E = '1' then state_in <= East; X_E <= '1'; else state_in <= state; end if; when South => if req_X_S = '1' then state_in <= South; X_S <= '1'; elsif req_X_L = '1' then state_in <= Local; X_L <= '1'; elsif req_X_N ='1' then state_in <= North; X_N <= '1'; elsif req_X_E = '1' then state_in <= East; X_E <= '1'; elsif req_X_W = '1' then state_in <= West; X_W <= '1'; else state_in <= state; end if; when others => -- Local state and invalid states if req_X_L = '1' then state_in <= Local; X_L <= '1'; elsif req_X_N ='1' then state_in <= North; X_N <= '1'; elsif req_X_E = '1' then state_in <= East; X_E <= '1'; elsif req_X_W = '1' then state_in <= West; X_W <= '1'; elsif req_X_S = '1' then state_in <= South; X_S <= '1'; else state_in <= state; end if; end case; end process; end;
gpl-3.0
74b8983ccfd4ac0e58f588d97644b490
0.473025
2.917779
false
false
false
false
bruskajp/EE-316
Project2/Quartus_DE2Board/btn_debounce_toggle.vhd
1
2,957
---------------------------------------------------------------------------- -- btn_debounce.vhd -- Button Debouncer ---------------------------------------------------------------------------- -- Author: Sam Bobrowicz -- Copyright 2011 Digilent, Inc. -- Modified: Added toggle output ---------------------------------------------------------------------------- -- ---------------------------------------------------------------------------- -- This component is used to debounce signals generated by external push -- buttons. It is designed to independently debounce a Push button signal. -- Debouncing is done by only registering a change in a button state if -- it remains constant for 2^16 clock cycles. -- -- Port Descriptions: -- -- BTN_I - The input button signals -- CLK - Behavior is optimized for a 100 MHz clock -- BTN_O - The debounced button signals -- TOGGLE_O - Debounced toggle output ---------------------------------------------------------------------------- -- ---------------------------------------------------------------------------- -- Revision History: -- 08/08/2011(SamB): Created using Xilinx Tools 13.2 -- 10/06/2013 (CU): Converted to one button and added toggle output ---------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.std_logic_unsigned.all; entity btn_debounce_toggle is GENERIC ( CONSTANT CNTR_MAX : std_logic_vector(15 downto 0) := X"000F"); Port ( BTN_I : in STD_LOGIC; CLK : in STD_LOGIC; BTN_O : out STD_LOGIC; TOGGLE_O : out STD_LOGIC); end btn_debounce_toggle; architecture Behavioral of btn_debounce_toggle is --constant CNTR_MAX : std_logic_vector(15 downto 0) := X"FFFF"; signal btn_cntr : std_logic_vector(15 downto 0) := (others => '0'); signal btn_reg : std_logic := '0'; signal btn_toggle : std_logic := '1'; signal btn_sync : std_logic_vector(1 downto 0) := (others => '0'); signal btn_pulse : std_logic := '0'; begin btn_debounce_process : process (CLK) begin if (rising_edge(CLK)) then if (btn_cntr = CNTR_MAX) then btn_reg <= not(btn_reg); end if; end if; end process; btn_counter_process : process (CLK) begin if (rising_edge(CLK)) then if ((btn_reg = '1') xor (BTN_I = '1')) then if (btn_cntr = CNTR_MAX) then btn_cntr <= (others => '0'); else btn_cntr <= btn_cntr + 1; end if; else btn_cntr <= (others => '0'); end if; end if; end process; btn_toggle_process : process(CLK) begin if (rising_edge(CLK)) then btn_sync(0) <= btn_reg; btn_sync(1) <= btn_sync(0); btn_pulse <= not btn_sync(1) and btn_sync(0); if btn_pulse = '1' then btn_toggle <= not btn_toggle; end if; end if; end process; BTN_O <= btn_reg; TOGGLE_O <= btn_toggle; end Behavioral;
gpl-3.0
2e65b2d1c71484af9ae9cd0199e6cc40
0.50186
3.705514
false
false
false
false
lnls-dig/dsp-cores
hdl/modules/cic/decimation_strober.vhd
1
2,693
------------------------------------------------------------------------------- -- Title : Strobe generator -- Project : ------------------------------------------------------------------------------- -- File : decimation_strober.vhd -- Author : aylons <aylons@LNLS190> -- Company : -- Created : 2016-05-05 -- Last update: -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: Generates one strobe every ratio_i times valid_i is asserted ------------------------------------------------------------------------------- -- Copyright (c) 2016 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2016-05-05 1.0 aylons Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.math_real.all; use ieee.numeric_std.all; library UNISIM; use UNISIM.vcomponents.all; library work; use work.dsp_cores_pkg.all; ------------------------------------------------------------------------------- entity decimation_strober is generic ( g_maxrate : natural := 2048; g_bus_width : natural := 11 ); port ( clk_i : in std_logic; rst_i : in std_logic; ce_i : in std_logic; valid_i : in std_logic; ratio_i : in std_logic_vector(g_bus_width-1 downto 0); strobe_o : out std_logic ); end entity decimation_strober; ------------------------------------------------------------------------------- architecture str of decimation_strober is signal count : unsigned(g_bus_width-1 downto 0) := to_unsigned(0, g_bus_width); signal strobe : std_logic := '0'; signal count_all : std_logic := '0'; begin -- architecture str p_counting : process(clk_i) begin if rising_edge(clk_i) then if rst_i = '1' then count <= to_unsigned(0, count'length); count_all <= '0'; else if ce_i = '1' then if valid_i = '1' then count <= count + 1; count_all <= '0'; if count = to_integer(unsigned(ratio_i))-1 then count <= to_unsigned(0, count'length); count_all <= '1'; end if; -- count_all must be asserted for 1 CE cycle only else count_all <= '0'; end if; -- valid_i end if; -- ce end if; -- reset end if; -- rising_edge end process; strobe_o <= count_all; end architecture str; -------------------------------------------------------------------------------
lgpl-3.0
529dfa03aabe49b469cfc68b646c255c
0.418121
4.350565
false
false
false
false
lnls-dig/dsp-cores
hdl/testbench/cordic/cordic_core_tb.vhd
1
6,070
------------------------------------------------------------------------------- -- Title : Testbench for design "cordic_core" -- Project : ------------------------------------------------------------------------------- -- File : cordic_core_tb.vhd -- Author : Vitor Finotti Ferreira <vfinotti@finotti-Inspiron-7520> -- Company : Brazilian Synchrotron Light Laboratory, LNLS/CNPEM -- Created : 2015-11-19 -- Last update: 2015-11-24 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Copyright (c) 2015 Brazilian Synchrotron Light Laboratory, LNLS/CNPEM -- This program is free software: you can redistribute it and/or -- modify it under the terms of the GNU Lesser General Public License -- as published by the Free Software Foundation, either version 3 of -- the License, or (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- Lesser General Public License for more details. -- -- You should have received a copy of the GNU Lesser General Public -- License along with this program. If not, see -- <http://www.gnu.org/licenses/>. ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2015-11-19 1.0 vfinotti Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; library std; use std.textio.all; library UNISIM; use UNISIM.vcomponents.all; library work; use work.test_pkg.all; ------------------------------------------------------------------------------- entity cordic_core_tb is end entity cordic_core_tb; ------------------------------------------------------------------------------- architecture test of cordic_core_tb is ----------------------------------------------------------------------------- -- Internal signal declarations ----------------------------------------------------------------------------- constant c_CLK_FREQ : real := 100.0e6; constant c_CYCLES_TO_CE : natural := 4; constant c_INPUT_FILE : string := "vectoring_in.samples"; constant c_INPUT_WIDTH : natural := 32; constant c_OUTPUT_FILE : string := "vectoring_out.samples"; constant c_OUTPUT_WIDTH : natural := 32; signal end_of_file : std_logic := '0'; constant cordic_delay : natural := 27; -- component generics constant g_stages : natural := 15; constant g_bit_growth : natural := natural(ceil(log2(real(g_stages)))); constant g_mode : string := "rect_to_polar"; -- component ports signal s_x_i : signed(c_INPUT_WIDTH-1 downto 0); signal s_y_i : signed(c_INPUT_WIDTH-1 downto 0); signal s_z_i : signed(c_INPUT_WIDTH-1 downto 0) := (c_INPUT_WIDTH-1 downto 0 => '0'); signal s_clk : std_logic; signal s_ce : std_logic; signal s_rst : std_logic; signal s_valid_i : std_logic; signal s_x_o : signed(c_INPUT_WIDTH-1 downto 0); signal s_y_o : signed(c_INPUT_WIDTH-1 downto 0); signal s_z_o : signed(c_INPUT_WIDTH-1 downto 0); signal s_valid_o : std_logic; signal s_req_data :std_logic := '1'; signal s_x_i_real :real; signal s_y_i_real :real; signal s_x_o_real :real; signal s_y_o_real :real; component cordic_core is generic ( g_stages : natural; g_bit_growth : natural; g_mode : string); port ( x_i : in signed; y_i : in signed; z_i : in signed; clk_i : in std_logic; ce_i : in std_logic; rst_i : in std_logic; valid_i : in std_logic; x_o : out signed; y_o : out signed; z_o : out signed; valid_o : out std_logic); end component cordic_core; begin -- architecture test p_clk_gen ( clk => s_clk, c_FREQ => c_CLK_FREQ); p_rst_gen ( clk => s_clk, rst => s_rst, c_CYCLES => 2); p_ce_gen ( clk => s_clk, ce => s_ce, rst => s_rst, c_CYCLES => c_CYCLES_TO_CE); p_read_tsv_file_signed ( c_INPUT_FILE_NAME => c_INPUT_FILE, c_SAMPLES_PER_LINE => 2, c_OUTPUT_WIDTH => c_INPUT_WIDTH, --input for the testbench, output for --the procedure clk => s_clk, rst => s_rst, ce => s_ce, req => s_req_data, sample(0) => s_x_i, sample(1) => s_y_i, valid => s_valid_i, end_of_file => end_of_file); -- component instantiation DUT : cordic_core generic map ( g_stages => g_stages, g_bit_growth => g_bit_growth, g_mode => g_mode) port map ( x_i => s_x_i, y_i => s_y_i, z_i => s_z_i, clk_i => s_clk, ce_i => s_ce, rst_i => s_rst, valid_i => s_valid_i, x_o => s_x_o, y_o => s_y_o, z_o => s_z_o, valid_o => s_valid_o); p_write_tsv_file_signed ( c_OUTPUT_FILE_NAME => c_OUTPUT_FILE, c_SAMPLES_PER_LINE => 2, c_OUTPUT_WIDTH => c_OUTPUT_WIDTH, clk => s_clk, rst => s_rst, ce => s_ce, sample(0) => s_x_o, sample(1) => s_z_o, valid => s_valid_o, end_of_file => end_of_file); end architecture test; ------------------------------------------------------------------------------- configuration cordic_core_tb_test_cfg of cordic_core_tb is for test end for; end cordic_core_tb_test_cfg; -------------------------------------------------------------------------------
lgpl-3.0
53688a4bb6459b69c396b3aa489e475f
0.476606
3.685489
false
false
false
false
SoCdesign/EHA
Simulation/Fault_Management/Error_Detection_Correction/crc_encoder_tb.vhd
1
2,128
library ieee; use ieee.std_logic_1164.all; use std.textio.all; use ieee.std_logic_textio.all; use IEEE.NUMERIC_STD.all; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity encoder_tb is end encoder_tb; architecture arch of encoder_tb is component crc is port(rst, clk: in std_logic; data_in: in std_logic; ready : out std_logic; crc_out: out std_logic_vector (7 downto 0) ); end component; file outfile : text; -- declare the file to be a text file signal crc_out : std_logic_vector (7 downto 0); signal data: std_logic_vector (31 downto 0) := (others => '0'); signal clk, reset, data_in, ready: std_logic := '0'; constant clk_period : time := 1 ns; begin encoder: crc port map(rst=>reset, clk =>clk, data_in => data_in, ready => ready, crc_out=>crc_out); process(ready) variable LINEVARIABLE : line; variable fstatus : File_open_status; begin file_open(fstatus,outfile,"encoded.txt",write_mode); if ready'event and ready = '1' then write(LINEVARIABLE, data&crc_out); writeline(outfile, LINEVARIABLE); end if; end process; clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; process variable coutner_i : integer:=0; begin wait until clk'event and clk ='1'; data_in <= data(31); reset <= '0'; wait for 1 ns; reset <= '1'; -- send in the data while coutner_i <32 loop report "coutner_i: " & integer'image(coutner_i) & " "& std_logic'image(data(31-coutner_i)); wait until clk'event and clk ='1'; data_in <= data(31-coutner_i); coutner_i := coutner_i+1; end loop; coutner_i := 0; -- send in 8 zeros while coutner_i < 8 loop report "coutner_i: " & integer'image(coutner_i) & " "& std_logic'image(data(31-coutner_i)); wait until clk'event and clk ='1'; data_in <= '0'; coutner_i := coutner_i+1; end loop; wait until ready <= '1'; coutner_i := 0; data <= data + 1; end process; end architecture ; -- arch
gpl-3.0
ab306c182e5c7cbd2a4531b44a60d617
0.601974
3.180867
false
false
false
false
TanND/Electronic
VHDL/D15_C2.vhd
1
592
library IEEE; use IEEE.STD_LOGIC_1164.all; entity D15_C2 is port( clk : in STD_LOGIC; seg : out STD_LOGIC_VECTOR(7 downto 0) ); end D15_C2; architecture D15_C2 of D15_C2 is begin process(clk) variable dem:integer range 0 to 4; begin if (rising_edge(clk)) then if (dem=4) then dem:=0; else dem:=dem+1; end if; end if; case dem is when 0=> seg <="00000000"; when 1=> seg <="00011000"; when 2=> seg <="00111100"; when 3=> seg <="01111110"; when 4=> seg <="11111111"; when others=> seg <="XXXXXXXX"; end case; end process; end D15_C2; -- clk=5Mhz;
apache-2.0
f922ec20f6bb2d45bec8af4d9d69236a
0.621622
2.654709
false
false
false
false
SoCdesign/EHA
RTL/Hand_Shaking/Hand_Shaking_FC/Router_32_bit_parity_with_dominant_checkers.vhd
1
70,643
--Copyright (C) 2016 Siavoosh Payandeh Azad library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity router_parity is generic ( DATA_WIDTH: integer := 32; current_address : integer := 5; Rxy_rst : integer := 60; Cx_rst : integer := 15; NoC_size: integer := 4 ); port ( reset, clk: in std_logic; DCTS_N, DCTS_E, DCTS_w, DCTS_S, DCTS_L: in std_logic; DRTS_N, DRTS_E, DRTS_W, DRTS_S, DRTS_L: in std_logic; RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0); RTS_N, RTS_E, RTS_W, RTS_S, RTS_L: out std_logic; CTS_N, CTS_E, CTS_w, CTS_S, CTS_L: out std_logic; TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0); fault_out_N, fault_out_E, fault_out_W, fault_out_S, fault_out_L:out std_logic ); end router_parity; architecture behavior of router_parity is COMPONENT parity_checker is generic(DATA_WIDTH : integer := 32); port( RX: in std_logic_vector(DATA_WIDTH-1 downto 0); DRTS: in std_logic; fault_out: out std_logic ); end COMPONENT; COMPONENT FIFO generic ( DATA_WIDTH: integer := 32 ); port ( reset: in std_logic; clk: in std_logic; RX: in std_logic_vector(DATA_WIDTH-1 downto 0); DRTS: in std_logic; read_en_N : in std_logic; read_en_E : in std_logic; read_en_W : in std_logic; read_en_S : in std_logic; read_en_L : in std_logic; CTS: out std_logic; empty_out: out std_logic; Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0); -- Checker outputs err_write_en_write_pointer, err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full, err_read_pointer_increment, err_read_pointer_not_increment, --err_CTS_in, err_write_en, err_not_CTS_in, --err_not_write_en, err_read_en_mismatch : out std_logic ); end COMPONENT; COMPONENT Arbiter port ( reset: in std_logic; clk: in std_logic; Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules DCTS: in std_logic; -- Getting the CTS signal from the input FIFO of the next router/NI (for hand-shaking) Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot) Xbar_sel : out std_logic_vector(4 downto 0); -- select lines for XBAR RTS: out std_logic; -- Valid output which is sent to the next router/NI to specify that the data on the output port is valid -- Checker outputs err_state_IDLE_xbar, err_state_not_IDLE_xbar, err_state_IDLE_RTS_FF_in, err_state_not_IDLE_RTS_FF_RTS_FF_in, err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in, err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in, err_RTS_FF_not_DCTS_state_state_in, err_not_RTS_FF_state_in_next_state, err_RTS_FF_DCTS_state_in_next_state, err_not_DCTS_Grants, err_DCTS_not_RTS_FF_Grants, err_DCTS_RTS_FF_IDLE_Grants, err_DCTS_RTS_FF_not_IDLE_Grants_onehot, err_Requests_next_state_IDLE, err_IDLE_Req_L, err_Local_Req_L, err_North_Req_N, --err_East_Req_E, --err_West_Req_W, --err_South_Req_S, err_IDLE_Req_N, err_Local_Req_N, --err_North_Req_E, --err_East_Req_W, --err_West_Req_S, err_South_Req_L, --err_IDLE_Req_E, --err_Local_Req_E, --err_North_Req_W, --err_East_Req_S, err_West_Req_L, err_South_Req_N, --err_IDLE_Req_W, --err_Local_Req_W, --err_North_Req_S, err_East_Req_L, err_West_Req_N, --err_South_Req_E, --err_IDLE_Req_S, --err_Local_Req_S, --err_North_Req_L, err_East_Req_N, --err_West_Req_E, --err_South_Req_W, err_next_state_onehot, err_state_in_onehot, --err_DCTS_RTS_FF_state_Grant_L, --err_DCTS_RTS_FF_state_Grant_N, --err_DCTS_RTS_FF_state_Grant_E, --err_DCTS_RTS_FF_state_Grant_W, --err_DCTS_RTS_FF_state_Grant_S, err_state_north_xbar_sel, err_state_east_xbar_sel, err_state_west_xbar_sel, err_state_south_xbar_sel : out std_logic --err_state_local_xbar_sel : out std_logic ); end COMPONENT; COMPONENT LBDR is generic ( cur_addr_rst: integer := 5; Rxy_rst: integer := 60; Cx_rst: integer := 15; NoC_size: integer := 4 ); port ( reset: in std_logic; clk: in std_logic; empty: in std_logic; flit_type: in std_logic_vector(2 downto 0); dst_addr: in std_logic_vector(NoC_size-1 downto 0); Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic; -- Checker outputs --err_header_not_empty_Requests_in_onehot, err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero, err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_not_Req_L_in, err_dst_addr_cur_addr_Req_L_in, err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in : out std_logic ); end COMPONENT; COMPONENT XBAR is generic ( DATA_WIDTH: integer := 32 ); port ( North_in: in std_logic_vector(DATA_WIDTH-1 downto 0); East_in: in std_logic_vector(DATA_WIDTH-1 downto 0); West_in: in std_logic_vector(DATA_WIDTH-1 downto 0); South_in: in std_logic_vector(DATA_WIDTH-1 downto 0); Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0); sel: in std_logic_vector (4 downto 0); Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0) ); end COMPONENT; signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0); -- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic; signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic; signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic; signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic; signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic; signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic; signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic; signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic; signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic; signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic; signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic; signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0); -- Signals related to Checkers -- LBDR Checkers signals -- North signal N_err_header_empty_Requests_FF_Requests_in, N_err_tail_Requests_in_all_zero, N_err_header_tail_Requests_FF_Requests_in, N_err_dst_addr_cur_addr_N1, N_err_dst_addr_cur_addr_not_N1, N_err_dst_addr_cur_addr_E1, N_err_dst_addr_cur_addr_not_E1, N_err_dst_addr_cur_addr_W1, N_err_dst_addr_cur_addr_not_W1, N_err_dst_addr_cur_addr_S1, N_err_dst_addr_cur_addr_not_S1, N_err_dst_addr_cur_addr_not_Req_L_in, N_err_dst_addr_cur_addr_Req_L_in, N_err_header_not_empty_Req_N_in, N_err_header_not_empty_Req_E_in, N_err_header_not_empty_Req_W_in, N_err_header_not_empty_Req_S_in : std_logic; -- East signal E_err_header_empty_Requests_FF_Requests_in, E_err_tail_Requests_in_all_zero, E_err_header_tail_Requests_FF_Requests_in, E_err_dst_addr_cur_addr_N1, E_err_dst_addr_cur_addr_not_N1, E_err_dst_addr_cur_addr_E1, E_err_dst_addr_cur_addr_not_E1, E_err_dst_addr_cur_addr_W1, E_err_dst_addr_cur_addr_not_W1, E_err_dst_addr_cur_addr_S1, E_err_dst_addr_cur_addr_not_S1, E_err_dst_addr_cur_addr_not_Req_L_in, E_err_dst_addr_cur_addr_Req_L_in, E_err_header_not_empty_Req_N_in, E_err_header_not_empty_Req_E_in, E_err_header_not_empty_Req_W_in, E_err_header_not_empty_Req_S_in : std_logic; -- West signal W_err_header_empty_Requests_FF_Requests_in, W_err_tail_Requests_in_all_zero, W_err_header_tail_Requests_FF_Requests_in, W_err_dst_addr_cur_addr_N1, W_err_dst_addr_cur_addr_not_N1, W_err_dst_addr_cur_addr_E1, W_err_dst_addr_cur_addr_not_E1, W_err_dst_addr_cur_addr_W1, W_err_dst_addr_cur_addr_not_W1, W_err_dst_addr_cur_addr_S1, W_err_dst_addr_cur_addr_not_S1, W_err_dst_addr_cur_addr_not_Req_L_in, W_err_dst_addr_cur_addr_Req_L_in, W_err_header_not_empty_Req_N_in, W_err_header_not_empty_Req_E_in, W_err_header_not_empty_Req_W_in, W_err_header_not_empty_Req_S_in : std_logic; -- South signal S_err_header_empty_Requests_FF_Requests_in, S_err_tail_Requests_in_all_zero, S_err_header_tail_Requests_FF_Requests_in, S_err_dst_addr_cur_addr_N1, S_err_dst_addr_cur_addr_not_N1, S_err_dst_addr_cur_addr_E1, S_err_dst_addr_cur_addr_not_E1, S_err_dst_addr_cur_addr_W1, S_err_dst_addr_cur_addr_not_W1, S_err_dst_addr_cur_addr_S1, S_err_dst_addr_cur_addr_not_S1, S_err_dst_addr_cur_addr_not_Req_L_in, S_err_dst_addr_cur_addr_Req_L_in, S_err_header_not_empty_Req_N_in, S_err_header_not_empty_Req_E_in, S_err_header_not_empty_Req_W_in, S_err_header_not_empty_Req_S_in : std_logic; -- Local signal L_err_header_empty_Requests_FF_Requests_in, L_err_tail_Requests_in_all_zero, L_err_header_tail_Requests_FF_Requests_in, L_err_dst_addr_cur_addr_N1, L_err_dst_addr_cur_addr_not_N1, L_err_dst_addr_cur_addr_E1, L_err_dst_addr_cur_addr_not_E1, L_err_dst_addr_cur_addr_W1, L_err_dst_addr_cur_addr_not_W1, L_err_dst_addr_cur_addr_S1, L_err_dst_addr_cur_addr_not_S1, L_err_dst_addr_cur_addr_not_Req_L_in, L_err_dst_addr_cur_addr_Req_L_in, L_err_header_not_empty_Req_N_in, L_err_header_not_empty_Req_E_in, L_err_header_not_empty_Req_W_in, L_err_header_not_empty_Req_S_in : std_logic; -- Arbiter Checkers signals -- North signal N_err_state_IDLE_xbar, N_err_state_not_IDLE_xbar, N_err_state_IDLE_RTS_FF_in, N_err_state_not_IDLE_RTS_FF_RTS_FF_in, N_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in, N_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in, N_err_RTS_FF_not_DCTS_state_state_in, N_err_not_RTS_FF_state_in_next_state, N_err_RTS_FF_DCTS_state_in_next_state, N_err_not_DCTS_Grants, N_err_DCTS_not_RTS_FF_Grants, N_err_DCTS_RTS_FF_IDLE_Grants, N_err_DCTS_RTS_FF_not_IDLE_Grants_onehot, N_err_Requests_next_state_IDLE, N_err_IDLE_Req_L, N_err_Local_Req_L, N_err_North_Req_N, N_err_IDLE_Req_N, N_err_Local_Req_N, N_err_South_Req_L, N_err_West_Req_L, N_err_South_Req_N, N_err_East_Req_L, N_err_West_Req_N, N_err_East_Req_N, N_err_next_state_onehot, N_err_state_in_onehot, N_err_state_north_xbar_sel, N_err_state_east_xbar_sel, N_err_state_west_xbar_sel, N_err_state_south_xbar_sel : std_logic; -- East signal E_err_state_IDLE_xbar, E_err_state_not_IDLE_xbar, E_err_state_IDLE_RTS_FF_in, E_err_state_not_IDLE_RTS_FF_RTS_FF_in, E_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in, E_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in, E_err_RTS_FF_not_DCTS_state_state_in, E_err_not_RTS_FF_state_in_next_state, E_err_RTS_FF_DCTS_state_in_next_state, E_err_not_DCTS_Grants, E_err_DCTS_not_RTS_FF_Grants, E_err_DCTS_RTS_FF_IDLE_Grants, E_err_DCTS_RTS_FF_not_IDLE_Grants_onehot, E_err_Requests_next_state_IDLE, E_err_IDLE_Req_L, E_err_Local_Req_L, E_err_North_Req_N, E_err_IDLE_Req_N, E_err_Local_Req_N, E_err_South_Req_L, E_err_West_Req_L, E_err_South_Req_N, E_err_East_Req_L, E_err_West_Req_N, E_err_East_Req_N, E_err_next_state_onehot, E_err_state_in_onehot, E_err_state_north_xbar_sel, E_err_state_east_xbar_sel, E_err_state_west_xbar_sel, E_err_state_south_xbar_sel : std_logic; -- West signal W_err_state_IDLE_xbar, W_err_state_not_IDLE_xbar, W_err_state_IDLE_RTS_FF_in, W_err_state_not_IDLE_RTS_FF_RTS_FF_in, W_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in, W_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in, W_err_RTS_FF_not_DCTS_state_state_in, W_err_not_RTS_FF_state_in_next_state, W_err_RTS_FF_DCTS_state_in_next_state, W_err_not_DCTS_Grants, W_err_DCTS_not_RTS_FF_Grants, W_err_DCTS_RTS_FF_IDLE_Grants, W_err_DCTS_RTS_FF_not_IDLE_Grants_onehot, W_err_Requests_next_state_IDLE, W_err_IDLE_Req_L, W_err_Local_Req_L, W_err_North_Req_N, W_err_IDLE_Req_N, W_err_Local_Req_N, W_err_South_Req_L, W_err_West_Req_L, W_err_South_Req_N, W_err_East_Req_L, W_err_West_Req_N, W_err_East_Req_N, W_err_next_state_onehot, W_err_state_in_onehot, W_err_state_north_xbar_sel, W_err_state_east_xbar_sel, W_err_state_west_xbar_sel, W_err_state_south_xbar_sel : std_logic; -- South signal S_err_state_IDLE_xbar, S_err_state_not_IDLE_xbar, S_err_state_IDLE_RTS_FF_in, S_err_state_not_IDLE_RTS_FF_RTS_FF_in, S_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in, S_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in, S_err_RTS_FF_not_DCTS_state_state_in, S_err_not_RTS_FF_state_in_next_state, S_err_RTS_FF_DCTS_state_in_next_state, S_err_not_DCTS_Grants, S_err_DCTS_not_RTS_FF_Grants, S_err_DCTS_RTS_FF_IDLE_Grants, S_err_DCTS_RTS_FF_not_IDLE_Grants_onehot, S_err_Requests_next_state_IDLE, S_err_IDLE_Req_L, S_err_Local_Req_L, S_err_North_Req_N, S_err_IDLE_Req_N, S_err_Local_Req_N, S_err_South_Req_L, S_err_West_Req_L, S_err_South_Req_N, S_err_East_Req_L, S_err_West_Req_N, S_err_East_Req_N, S_err_next_state_onehot, S_err_state_in_onehot, S_err_state_north_xbar_sel, S_err_state_east_xbar_sel, S_err_state_west_xbar_sel, S_err_state_south_xbar_sel : std_logic; -- Local signal L_err_state_IDLE_xbar, L_err_state_not_IDLE_xbar, L_err_state_IDLE_RTS_FF_in, L_err_state_not_IDLE_RTS_FF_RTS_FF_in, L_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in, L_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in, L_err_RTS_FF_not_DCTS_state_state_in, L_err_not_RTS_FF_state_in_next_state, L_err_RTS_FF_DCTS_state_in_next_state, L_err_not_DCTS_Grants, L_err_DCTS_not_RTS_FF_Grants, L_err_DCTS_RTS_FF_IDLE_Grants, L_err_DCTS_RTS_FF_not_IDLE_Grants_onehot, L_err_Requests_next_state_IDLE, L_err_IDLE_Req_L, L_err_Local_Req_L, L_err_North_Req_N, L_err_IDLE_Req_N, L_err_Local_Req_N, L_err_South_Req_L, L_err_West_Req_L, L_err_South_Req_N, L_err_East_Req_L, L_err_West_Req_N, L_err_East_Req_N, L_err_next_state_onehot, L_err_state_in_onehot, L_err_state_north_xbar_sel, L_err_state_east_xbar_sel, L_err_state_west_xbar_sel, L_err_state_south_xbar_sel : std_logic; -- FIFO Control Part Checkers signals -- North signal N_err_write_en_write_pointer, N_err_not_write_en_write_pointer, N_err_read_pointer_write_pointer_not_empty, N_err_read_pointer_write_pointer_empty, N_err_read_pointer_write_pointer_not_full, N_err_read_pointer_write_pointer_full, N_err_read_pointer_increment, N_err_read_pointer_not_increment, N_err_write_en, N_err_not_CTS_in, N_err_read_en_mismatch : std_logic; -- East signal E_err_write_en_write_pointer, E_err_not_write_en_write_pointer, E_err_read_pointer_write_pointer_not_empty, E_err_read_pointer_write_pointer_empty, E_err_read_pointer_write_pointer_not_full, E_err_read_pointer_write_pointer_full, E_err_read_pointer_increment, E_err_read_pointer_not_increment, E_err_write_en, E_err_not_CTS_in, E_err_read_en_mismatch : std_logic; -- West signal W_err_write_en_write_pointer, W_err_not_write_en_write_pointer, W_err_read_pointer_write_pointer_not_empty, W_err_read_pointer_write_pointer_empty, W_err_read_pointer_write_pointer_not_full, W_err_read_pointer_write_pointer_full, W_err_read_pointer_increment, W_err_read_pointer_not_increment, W_err_write_en, W_err_not_CTS_in, W_err_read_en_mismatch : std_logic; -- South signal S_err_write_en_write_pointer, S_err_not_write_en_write_pointer, S_err_read_pointer_write_pointer_not_empty, S_err_read_pointer_write_pointer_empty, S_err_read_pointer_write_pointer_not_full, S_err_read_pointer_write_pointer_full, S_err_read_pointer_increment, S_err_read_pointer_not_increment, S_err_write_en, S_err_not_CTS_in, S_err_read_en_mismatch : std_logic; -- Local signal L_err_write_en_write_pointer, L_err_not_write_en_write_pointer, L_err_read_pointer_write_pointer_not_empty, L_err_read_pointer_write_pointer_empty, L_err_read_pointer_write_pointer_not_full, L_err_read_pointer_write_pointer_full, L_err_read_pointer_increment, L_err_read_pointer_not_increment, L_err_write_en, L_err_not_CTS_in, L_err_read_en_mismatch : std_logic; -- Error Signals for each module (ORed combination of checker outputs) signal N_LBDR_checkers_output, E_LBDR_checkers_output, W_LBDR_checkers_output, S_LBDR_checkers_output, L_LBDR_checkers_output: std_logic; signal N_Arbiter_checkers_output, E_Arbiter_checkers_output, W_Arbiter_checkers_output, S_Arbiter_checkers_output, L_Arbiter_checkers_output: std_logic; signal N_FIFO_control_part_checkers_output, E_FIFO_control_part_checkers_output, W_FIFO_control_part_checkers_output, S_FIFO_control_part_checkers_output, L_FIFO_control_part_checkers_output: std_logic; begin -- OR of checker outputs for each module (corresponding to each direction) -- This is used for feeding the checker outputs to shift registers (later) -- LBDR N_LBDR_checkers_output <= N_err_header_empty_Requests_FF_Requests_in or N_err_tail_Requests_in_all_zero or N_err_header_tail_Requests_FF_Requests_in or N_err_dst_addr_cur_addr_N1 or N_err_dst_addr_cur_addr_not_N1 or N_err_dst_addr_cur_addr_E1 or N_err_dst_addr_cur_addr_not_E1 or N_err_dst_addr_cur_addr_W1 or N_err_dst_addr_cur_addr_not_W1 or N_err_dst_addr_cur_addr_S1 or N_err_dst_addr_cur_addr_not_S1 or N_err_dst_addr_cur_addr_not_Req_L_in or N_err_dst_addr_cur_addr_Req_L_in or N_err_header_not_empty_Req_N_in or N_err_header_not_empty_Req_E_in or N_err_header_not_empty_Req_W_in or N_err_header_not_empty_Req_S_in; E_LBDR_checkers_output <= E_err_header_empty_Requests_FF_Requests_in or E_err_tail_Requests_in_all_zero or E_err_header_tail_Requests_FF_Requests_in or E_err_dst_addr_cur_addr_N1 or E_err_dst_addr_cur_addr_not_N1 or E_err_dst_addr_cur_addr_E1 or E_err_dst_addr_cur_addr_not_E1 or E_err_dst_addr_cur_addr_W1 or E_err_dst_addr_cur_addr_not_W1 or E_err_dst_addr_cur_addr_S1 or E_err_dst_addr_cur_addr_not_S1 or E_err_dst_addr_cur_addr_not_Req_L_in or E_err_dst_addr_cur_addr_Req_L_in or E_err_header_not_empty_Req_N_in or E_err_header_not_empty_Req_E_in or E_err_header_not_empty_Req_W_in or E_err_header_not_empty_Req_S_in; W_LBDR_checkers_output <= W_err_header_empty_Requests_FF_Requests_in or W_err_tail_Requests_in_all_zero or W_err_header_tail_Requests_FF_Requests_in or W_err_dst_addr_cur_addr_N1 or W_err_dst_addr_cur_addr_not_N1 or W_err_dst_addr_cur_addr_E1 or W_err_dst_addr_cur_addr_not_E1 or W_err_dst_addr_cur_addr_W1 or W_err_dst_addr_cur_addr_not_W1 or W_err_dst_addr_cur_addr_S1 or W_err_dst_addr_cur_addr_not_S1 or W_err_dst_addr_cur_addr_not_Req_L_in or W_err_dst_addr_cur_addr_Req_L_in or W_err_header_not_empty_Req_N_in or W_err_header_not_empty_Req_E_in or W_err_header_not_empty_Req_W_in or W_err_header_not_empty_Req_S_in; S_LBDR_checkers_output <= S_err_header_empty_Requests_FF_Requests_in or S_err_tail_Requests_in_all_zero or S_err_header_tail_Requests_FF_Requests_in or S_err_dst_addr_cur_addr_N1 or S_err_dst_addr_cur_addr_not_N1 or S_err_dst_addr_cur_addr_E1 or S_err_dst_addr_cur_addr_not_E1 or S_err_dst_addr_cur_addr_W1 or S_err_dst_addr_cur_addr_not_W1 or S_err_dst_addr_cur_addr_S1 or S_err_dst_addr_cur_addr_not_S1 or S_err_dst_addr_cur_addr_not_Req_L_in or S_err_dst_addr_cur_addr_Req_L_in or S_err_header_not_empty_Req_N_in or S_err_header_not_empty_Req_E_in or S_err_header_not_empty_Req_W_in or S_err_header_not_empty_Req_S_in; L_LBDR_checkers_output <= L_err_header_empty_Requests_FF_Requests_in or L_err_tail_Requests_in_all_zero or L_err_header_tail_Requests_FF_Requests_in or L_err_dst_addr_cur_addr_N1 or L_err_dst_addr_cur_addr_not_N1 or L_err_dst_addr_cur_addr_E1 or L_err_dst_addr_cur_addr_not_E1 or L_err_dst_addr_cur_addr_W1 or L_err_dst_addr_cur_addr_not_W1 or L_err_dst_addr_cur_addr_S1 or L_err_dst_addr_cur_addr_not_S1 or L_err_dst_addr_cur_addr_not_Req_L_in or L_err_dst_addr_cur_addr_Req_L_in or L_err_header_not_empty_Req_N_in or L_err_header_not_empty_Req_E_in or L_err_header_not_empty_Req_W_in or L_err_header_not_empty_Req_S_in; -- Arbiter N_Arbiter_checkers_output <= N_err_state_IDLE_xbar or N_err_state_not_IDLE_xbar or N_err_state_IDLE_RTS_FF_in or N_err_state_not_IDLE_RTS_FF_RTS_FF_in or N_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in or N_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in or N_err_RTS_FF_not_DCTS_state_state_in or N_err_not_RTS_FF_state_in_next_state or N_err_RTS_FF_DCTS_state_in_next_state or N_err_not_DCTS_Grants or N_err_DCTS_not_RTS_FF_Grants or N_err_DCTS_RTS_FF_IDLE_Grants or N_err_DCTS_RTS_FF_not_IDLE_Grants_onehot or N_err_Requests_next_state_IDLE or N_err_IDLE_Req_L or N_err_Local_Req_L or N_err_North_Req_N or N_err_IDLE_Req_N or N_err_Local_Req_N or N_err_South_Req_L or N_err_West_Req_L or N_err_South_Req_N or N_err_East_Req_L or N_err_West_Req_N or N_err_East_Req_N or N_err_next_state_onehot or N_err_state_in_onehot or N_err_state_north_xbar_sel or N_err_state_east_xbar_sel or N_err_state_west_xbar_sel or N_err_state_south_xbar_sel; E_Arbiter_checkers_output <= E_err_state_IDLE_xbar or E_err_state_not_IDLE_xbar or E_err_state_IDLE_RTS_FF_in or E_err_state_not_IDLE_RTS_FF_RTS_FF_in or E_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in or E_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in or E_err_RTS_FF_not_DCTS_state_state_in or E_err_not_RTS_FF_state_in_next_state or E_err_RTS_FF_DCTS_state_in_next_state or E_err_not_DCTS_Grants or E_err_DCTS_not_RTS_FF_Grants or E_err_DCTS_RTS_FF_IDLE_Grants or E_err_DCTS_RTS_FF_not_IDLE_Grants_onehot or E_err_Requests_next_state_IDLE or E_err_IDLE_Req_L or E_err_Local_Req_L or E_err_North_Req_N or E_err_IDLE_Req_N or E_err_Local_Req_N or E_err_South_Req_L or E_err_West_Req_L or E_err_South_Req_N or E_err_East_Req_L or E_err_West_Req_N or E_err_East_Req_N or E_err_next_state_onehot or E_err_state_in_onehot or E_err_state_north_xbar_sel or E_err_state_east_xbar_sel or E_err_state_west_xbar_sel or E_err_state_south_xbar_sel; W_Arbiter_checkers_output <= W_err_state_IDLE_xbar or W_err_state_not_IDLE_xbar or W_err_state_IDLE_RTS_FF_in or W_err_state_not_IDLE_RTS_FF_RTS_FF_in or W_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in or W_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in or W_err_RTS_FF_not_DCTS_state_state_in or W_err_not_RTS_FF_state_in_next_state or W_err_RTS_FF_DCTS_state_in_next_state or W_err_not_DCTS_Grants or W_err_DCTS_not_RTS_FF_Grants or W_err_DCTS_RTS_FF_IDLE_Grants or W_err_DCTS_RTS_FF_not_IDLE_Grants_onehot or W_err_Requests_next_state_IDLE or W_err_IDLE_Req_L or W_err_Local_Req_L or W_err_North_Req_N or W_err_IDLE_Req_N or W_err_Local_Req_N or W_err_South_Req_L or W_err_West_Req_L or W_err_South_Req_N or W_err_East_Req_L or W_err_West_Req_N or W_err_East_Req_N or W_err_next_state_onehot or W_err_state_in_onehot or W_err_state_north_xbar_sel or W_err_state_east_xbar_sel or W_err_state_west_xbar_sel or W_err_state_south_xbar_sel; S_Arbiter_checkers_output <= S_err_state_IDLE_xbar or S_err_state_not_IDLE_xbar or S_err_state_IDLE_RTS_FF_in or S_err_state_not_IDLE_RTS_FF_RTS_FF_in or S_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in or S_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in or S_err_RTS_FF_not_DCTS_state_state_in or S_err_not_RTS_FF_state_in_next_state or S_err_RTS_FF_DCTS_state_in_next_state or S_err_not_DCTS_Grants or S_err_DCTS_not_RTS_FF_Grants or S_err_DCTS_RTS_FF_IDLE_Grants or S_err_DCTS_RTS_FF_not_IDLE_Grants_onehot or S_err_Requests_next_state_IDLE or S_err_IDLE_Req_L or S_err_Local_Req_L or S_err_North_Req_N or S_err_IDLE_Req_N or S_err_Local_Req_N or S_err_South_Req_L or S_err_West_Req_L or S_err_South_Req_N or S_err_East_Req_L or S_err_West_Req_N or S_err_East_Req_N or S_err_next_state_onehot or S_err_state_in_onehot or S_err_state_north_xbar_sel or S_err_state_east_xbar_sel or S_err_state_west_xbar_sel or S_err_state_south_xbar_sel; L_Arbiter_checkers_output <= L_err_state_IDLE_xbar or L_err_state_not_IDLE_xbar or L_err_state_IDLE_RTS_FF_in or L_err_state_not_IDLE_RTS_FF_RTS_FF_in or L_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in or L_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in or L_err_RTS_FF_not_DCTS_state_state_in or L_err_not_RTS_FF_state_in_next_state or L_err_RTS_FF_DCTS_state_in_next_state or L_err_not_DCTS_Grants or L_err_DCTS_not_RTS_FF_Grants or L_err_DCTS_RTS_FF_IDLE_Grants or L_err_DCTS_RTS_FF_not_IDLE_Grants_onehot or L_err_Requests_next_state_IDLE or L_err_IDLE_Req_L or L_err_Local_Req_L or L_err_North_Req_N or L_err_IDLE_Req_N or L_err_Local_Req_N or L_err_South_Req_L or L_err_West_Req_L or L_err_South_Req_N or L_err_East_Req_L or L_err_West_Req_N or L_err_East_Req_N or L_err_next_state_onehot or L_err_state_in_onehot or L_err_state_north_xbar_sel or L_err_state_east_xbar_sel or L_err_state_west_xbar_sel or L_err_state_south_xbar_sel; -- FIFO Control Part N_FIFO_control_part_checkers_output <= N_err_write_en_write_pointer or N_err_not_write_en_write_pointer or N_err_read_pointer_write_pointer_not_empty or N_err_read_pointer_write_pointer_empty or N_err_read_pointer_write_pointer_not_full or N_err_read_pointer_write_pointer_full or N_err_read_pointer_increment or N_err_read_pointer_not_increment or N_err_write_en or N_err_not_CTS_in or N_err_read_en_mismatch; E_FIFO_control_part_checkers_output <= E_err_write_en_write_pointer or E_err_not_write_en_write_pointer or E_err_read_pointer_write_pointer_not_empty or E_err_read_pointer_write_pointer_empty or E_err_read_pointer_write_pointer_not_full or E_err_read_pointer_write_pointer_full or E_err_read_pointer_increment or E_err_read_pointer_not_increment or E_err_write_en or E_err_not_CTS_in or E_err_read_en_mismatch; W_FIFO_control_part_checkers_output <= W_err_write_en_write_pointer or W_err_not_write_en_write_pointer or W_err_read_pointer_write_pointer_not_empty or W_err_read_pointer_write_pointer_empty or W_err_read_pointer_write_pointer_not_full or W_err_read_pointer_write_pointer_full or W_err_read_pointer_increment or W_err_read_pointer_not_increment or W_err_write_en or W_err_not_CTS_in or W_err_read_en_mismatch; S_FIFO_control_part_checkers_output <= S_err_write_en_write_pointer or S_err_not_write_en_write_pointer or S_err_read_pointer_write_pointer_not_empty or S_err_read_pointer_write_pointer_empty or S_err_read_pointer_write_pointer_not_full or S_err_read_pointer_write_pointer_full or S_err_read_pointer_increment or S_err_read_pointer_not_increment or S_err_write_en or S_err_not_CTS_in or S_err_read_en_mismatch; L_FIFO_control_part_checkers_output <= L_err_write_en_write_pointer or L_err_not_write_en_write_pointer or L_err_read_pointer_write_pointer_not_empty or L_err_read_pointer_write_pointer_empty or L_err_read_pointer_write_pointer_not_full or L_err_read_pointer_write_pointer_full or L_err_read_pointer_increment or L_err_read_pointer_not_increment or L_err_write_en or L_err_not_CTS_in or L_err_read_en_mismatch; ------------------------------------------------------------------------------------------------------------------------------ -- block diagram of one channel -- -- .____________grant_________ -- | ▲ -- | _______ __|_______ -- | | | | | -- | | LBDR |---req--->| Arbiter | <--handshake--> -- | |_______| |__________| signals -- | ▲ | -- __▼___ | flit ___▼__ -- RX ----->| | | type | | -- <-handshake->| FIFO |---o------------->| |-----> TX -- signals |______| ------>| | -- ------>| XBAR | -- ------>| | -- ------>| | -- |______| -- ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- all the parity_checkers PC_N: parity_checker generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP(RX => RX_N, DRTS =>DRTS_N, fault_out => fault_out_N); PC_E: parity_checker generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP(RX => RX_E, DRTS =>DRTS_E, fault_out => fault_out_E); PC_W: parity_checker generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP(RX => RX_W, DRTS =>DRTS_W, fault_out => fault_out_W); PC_S: parity_checker generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP(RX => RX_S, DRTS =>DRTS_S, fault_out => fault_out_S); PC_L: parity_checker generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP(RX => RX_L, DRTS =>DRTS_L, fault_out => fault_out_L); -- all the FIFOs FIFO_N: FIFO generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (reset => reset, clk => clk, RX => RX_N, DRTS => DRTS_N, read_en_N => '0', read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN, CTS => CTS_N, empty_out => empty_N, Data_out => FIFO_D_out_N, err_write_en_write_pointer => N_err_write_en_write_pointer, err_not_write_en_write_pointer => N_err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty => N_err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty => N_err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full => N_err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full => N_err_read_pointer_write_pointer_full, err_read_pointer_increment => N_err_read_pointer_increment, err_read_pointer_not_increment => N_err_read_pointer_not_increment, err_write_en => N_err_write_en, err_not_CTS_in => N_err_not_CTS_in, err_read_en_mismatch => N_err_read_en_mismatch ); FIFO_E: FIFO generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (reset => reset, clk => clk, RX => RX_E, DRTS => DRTS_E, read_en_N => Grant_NE, read_en_E =>'0', read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE, CTS => CTS_E, empty_out => empty_E, Data_out => FIFO_D_out_E, err_write_en_write_pointer => E_err_write_en_write_pointer, err_not_write_en_write_pointer => E_err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty => E_err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty => E_err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full => E_err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full => E_err_read_pointer_write_pointer_full, err_read_pointer_increment => E_err_read_pointer_increment, err_read_pointer_not_increment => E_err_read_pointer_not_increment, err_write_en => E_err_write_en, err_not_CTS_in => E_err_not_CTS_in, err_read_en_mismatch => E_err_read_en_mismatch ); FIFO_W: FIFO generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (reset => reset, clk => clk, RX => RX_W, DRTS => DRTS_W, read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>'0', read_en_S =>Grant_SW, read_en_L =>Grant_LW, CTS => CTS_W, empty_out => empty_W, Data_out => FIFO_D_out_W, err_write_en_write_pointer => W_err_write_en_write_pointer, err_not_write_en_write_pointer => W_err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty => W_err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty => W_err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full => W_err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full => W_err_read_pointer_write_pointer_full, err_read_pointer_increment => W_err_read_pointer_increment, err_read_pointer_not_increment => W_err_read_pointer_not_increment, err_write_en => W_err_write_en, err_not_CTS_in => W_err_not_CTS_in, err_read_en_mismatch => W_err_read_en_mismatch ); FIFO_S: FIFO generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (reset => reset, clk => clk, RX => RX_S, DRTS => DRTS_S, read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>'0', read_en_L =>Grant_LS, CTS => CTS_S, empty_out => empty_S, Data_out => FIFO_D_out_S, err_write_en_write_pointer => S_err_write_en_write_pointer, err_not_write_en_write_pointer => S_err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty => S_err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty => S_err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full => S_err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full => S_err_read_pointer_write_pointer_full, err_read_pointer_increment => S_err_read_pointer_increment, err_read_pointer_not_increment => S_err_read_pointer_not_increment, err_write_en => S_err_write_en, err_not_CTS_in => S_err_not_CTS_in, err_read_en_mismatch => S_err_read_en_mismatch ); FIFO_L: FIFO generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (reset => reset, clk => clk, RX => RX_L, DRTS => DRTS_L, read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>'0', CTS => CTS_L, empty_out => empty_L, Data_out => FIFO_D_out_L, err_write_en_write_pointer => L_err_write_en_write_pointer, err_not_write_en_write_pointer => L_err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty => L_err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty => L_err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full => L_err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full => L_err_read_pointer_write_pointer_full, err_read_pointer_increment => L_err_read_pointer_increment, err_read_pointer_not_increment => L_err_read_pointer_not_increment, err_write_en => L_err_write_en, err_not_CTS_in => L_err_not_CTS_in, err_read_en_mismatch => L_err_read_en_mismatch ); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- all the LBDRs LBDR_N: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty_N, flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) , Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL, err_header_empty_Requests_FF_Requests_in => N_err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero => N_err_tail_Requests_in_all_zero, err_header_tail_Requests_FF_Requests_in => N_err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1 => N_err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1 => N_err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1 => N_err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1 => N_err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1 => N_err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1 => N_err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1 => N_err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1 => N_err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_not_Req_L_in => N_err_dst_addr_cur_addr_not_Req_L_in, err_dst_addr_cur_addr_Req_L_in => N_err_dst_addr_cur_addr_Req_L_in, err_header_not_empty_Req_N_in => N_err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in => N_err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in => N_err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in => N_err_header_not_empty_Req_S_in ); LBDR_E: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty_E, flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) , Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL, err_header_empty_Requests_FF_Requests_in => E_err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero => E_err_tail_Requests_in_all_zero, err_header_tail_Requests_FF_Requests_in => E_err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1 => E_err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1 => E_err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1 => E_err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1 => E_err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1 => E_err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1 => E_err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1 => E_err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1 => E_err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_not_Req_L_in => E_err_dst_addr_cur_addr_not_Req_L_in, err_dst_addr_cur_addr_Req_L_in => E_err_dst_addr_cur_addr_Req_L_in, err_header_not_empty_Req_N_in => E_err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in => E_err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in => E_err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in => E_err_header_not_empty_Req_S_in ); LBDR_W: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty_W, flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) , Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL, err_header_empty_Requests_FF_Requests_in => W_err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero => W_err_tail_Requests_in_all_zero, err_header_tail_Requests_FF_Requests_in => W_err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1 => W_err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1 => W_err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1 => W_err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1 => W_err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1 => W_err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1 => W_err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1 => W_err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1 => W_err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_not_Req_L_in => W_err_dst_addr_cur_addr_not_Req_L_in, err_dst_addr_cur_addr_Req_L_in => W_err_dst_addr_cur_addr_Req_L_in, err_header_not_empty_Req_N_in => W_err_header_not_empty_Req_n_in, err_header_not_empty_Req_E_in => W_err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in => W_err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in => W_err_header_not_empty_Req_S_in ); LBDR_S: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty_S, flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) , Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL, err_header_empty_Requests_FF_Requests_in => S_err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero => S_err_tail_Requests_in_all_zero, err_header_tail_Requests_FF_Requests_in => S_err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1 => S_err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1 => S_err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1 => S_err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1 => S_err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1 => S_err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1 => S_err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1 => S_err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1 => S_err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_not_Req_L_in => S_err_dst_addr_cur_addr_not_Req_L_in, err_dst_addr_cur_addr_Req_L_in => S_err_dst_addr_cur_addr_Req_L_in, err_header_not_empty_Req_N_in => S_err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in => S_err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in => S_err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in => S_err_header_not_empty_Req_S_in ); LBDR_L: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty_L, flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) , Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL, err_header_empty_Requests_FF_Requests_in => L_err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero => L_err_tail_Requests_in_all_zero, err_header_tail_Requests_FF_Requests_in => L_err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1 => L_err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1 => L_err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1 => L_err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1 => L_err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1 => L_err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1 => L_err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1 => L_err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1 => L_err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_not_Req_L_in => L_err_dst_addr_cur_addr_not_Req_L_in, err_dst_addr_cur_addr_Req_L_in => L_err_dst_addr_cur_addr_Req_L_in, err_header_not_empty_Req_N_in => L_err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in => L_err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in => L_err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in => L_err_header_not_empty_Req_S_in ); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- all the Arbiters Arbiter_N: Arbiter PORT MAP (reset => reset, clk => clk, Req_N => '0' , Req_E => Req_EN, Req_W => Req_WN, Req_S => Req_SN, Req_L => Req_LN, DCTS => DCTS_N, Grant_N => Grant_NN, Grant_E => Grant_NE, Grant_W => Grant_NW, Grant_S => Grant_NS, Grant_L => Grant_NL, Xbar_sel => Xbar_sel_N, RTS => RTS_N, err_state_IDLE_xbar => N_err_state_IDLE_xbar , err_state_not_IDLE_xbar => N_err_state_not_IDLE_xbar , err_state_IDLE_RTS_FF_in => N_err_state_IDLE_RTS_FF_in , err_state_not_IDLE_RTS_FF_RTS_FF_in => N_err_state_not_IDLE_RTS_FF_RTS_FF_in , err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => N_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in , err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => N_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in , err_RTS_FF_not_DCTS_state_state_in => N_err_RTS_FF_not_DCTS_state_state_in , err_not_RTS_FF_state_in_next_state => N_err_not_RTS_FF_state_in_next_state , err_RTS_FF_DCTS_state_in_next_state => N_err_RTS_FF_DCTS_state_in_next_state , err_not_DCTS_Grants => N_err_not_DCTS_Grants , err_DCTS_not_RTS_FF_Grants => N_err_DCTS_not_RTS_FF_Grants , err_DCTS_RTS_FF_IDLE_Grants => N_err_DCTS_RTS_FF_IDLE_Grants , err_DCTS_RTS_FF_not_IDLE_Grants_onehot => N_err_DCTS_RTS_FF_not_IDLE_Grants_onehot , err_Requests_next_state_IDLE => N_err_Requests_next_state_IDLE , err_IDLE_Req_L => N_err_IDLE_Req_L , err_Local_Req_L => N_err_Local_Req_L , err_North_Req_N => N_err_North_Req_N , err_IDLE_Req_N => N_err_IDLE_Req_N , err_Local_Req_N => N_err_Local_Req_N , err_South_Req_L => N_err_South_Req_L , err_West_Req_L => N_err_West_Req_L , err_South_Req_N => N_err_South_Req_N , err_East_Req_L => N_err_East_Req_L , err_West_Req_N => N_err_West_Req_N , err_East_Req_N => N_err_East_Req_N , err_next_state_onehot => N_err_next_state_onehot , err_state_in_onehot => N_err_state_in_onehot , err_state_north_xbar_sel => N_err_state_north_xbar_sel , err_state_east_xbar_sel => N_err_state_east_xbar_sel , err_state_west_xbar_sel => N_err_state_west_xbar_sel , err_state_south_xbar_sel => N_err_state_south_xbar_sel ); Arbiter_E: Arbiter PORT MAP (reset => reset, clk => clk, Req_N => Req_NE , Req_E => '0', Req_W => Req_WE, Req_S => Req_SE, Req_L => Req_LE, DCTS => DCTS_E, Grant_N => Grant_EN, Grant_E => Grant_EE, Grant_W => Grant_EW, Grant_S => Grant_ES, Grant_L => Grant_EL, Xbar_sel => Xbar_sel_E, RTS => RTS_E, err_state_IDLE_xbar => E_err_state_IDLE_xbar , err_state_not_IDLE_xbar => E_err_state_not_IDLE_xbar , err_state_IDLE_RTS_FF_in => E_err_state_IDLE_RTS_FF_in , err_state_not_IDLE_RTS_FF_RTS_FF_in => E_err_state_not_IDLE_RTS_FF_RTS_FF_in , err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => E_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in , err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => E_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in , err_RTS_FF_not_DCTS_state_state_in => E_err_RTS_FF_not_DCTS_state_state_in , err_not_RTS_FF_state_in_next_state => E_err_not_RTS_FF_state_in_next_state , err_RTS_FF_DCTS_state_in_next_state => E_err_RTS_FF_DCTS_state_in_next_state , err_not_DCTS_Grants => E_err_not_DCTS_Grants , err_DCTS_not_RTS_FF_Grants => E_err_DCTS_not_RTS_FF_Grants , err_DCTS_RTS_FF_IDLE_Grants => E_err_DCTS_RTS_FF_IDLE_Grants , err_DCTS_RTS_FF_not_IDLE_Grants_onehot => E_err_DCTS_RTS_FF_not_IDLE_Grants_onehot , err_Requests_next_state_IDLE => E_err_Requests_next_state_IDLE , err_IDLE_Req_L => E_err_IDLE_Req_L , err_Local_Req_L => E_err_Local_Req_L , err_North_Req_N => E_err_North_Req_N , err_IDLE_Req_N => E_err_IDLE_Req_N , err_Local_Req_N => E_err_Local_Req_N , err_South_Req_L => E_err_South_Req_L , err_West_Req_L => E_err_West_Req_L , err_South_Req_N => E_err_South_Req_N , err_East_Req_L => E_err_East_Req_L , err_West_Req_N => E_err_West_Req_N , err_East_Req_N => E_err_East_Req_N , err_next_state_onehot => E_err_next_state_onehot , err_state_in_onehot => E_err_state_in_onehot , err_state_north_xbar_sel => E_err_state_north_xbar_sel , err_state_east_xbar_sel => E_err_state_east_xbar_sel , err_state_west_xbar_sel => E_err_state_west_xbar_sel , err_state_south_xbar_sel => E_err_state_south_xbar_sel ); Arbiter_W: Arbiter PORT MAP (reset => reset, clk => clk, Req_N => Req_NW , Req_E => Req_EW, Req_W => '0', Req_S => Req_SW, Req_L => Req_LW, DCTS => DCTS_W, Grant_N => Grant_WN, Grant_E => Grant_WE, Grant_W => Grant_WW, Grant_S => Grant_WS, Grant_L => Grant_WL, Xbar_sel => Xbar_sel_W, RTS => RTS_W, err_state_IDLE_xbar => W_err_state_IDLE_xbar , err_state_not_IDLE_xbar => W_err_state_not_IDLE_xbar , err_state_IDLE_RTS_FF_in => W_err_state_IDLE_RTS_FF_in , err_state_not_IDLE_RTS_FF_RTS_FF_in => W_err_state_not_IDLE_RTS_FF_RTS_FF_in , err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => W_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in , err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => W_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in , err_RTS_FF_not_DCTS_state_state_in => W_err_RTS_FF_not_DCTS_state_state_in , err_not_RTS_FF_state_in_next_state => W_err_not_RTS_FF_state_in_next_state , err_RTS_FF_DCTS_state_in_next_state => W_err_RTS_FF_DCTS_state_in_next_state , err_not_DCTS_Grants => W_err_not_DCTS_Grants , err_DCTS_not_RTS_FF_Grants => W_err_DCTS_not_RTS_FF_Grants , err_DCTS_RTS_FF_IDLE_Grants => W_err_DCTS_RTS_FF_IDLE_Grants , err_DCTS_RTS_FF_not_IDLE_Grants_onehot => W_err_DCTS_RTS_FF_not_IDLE_Grants_onehot , err_Requests_next_state_IDLE => W_err_Requests_next_state_IDLE , err_IDLE_Req_L => W_err_IDLE_Req_L , err_Local_Req_L => W_err_Local_Req_L , err_North_Req_N => W_err_North_Req_N , err_IDLE_Req_N => W_err_IDLE_Req_N , err_Local_Req_N => W_err_Local_Req_N , err_South_Req_L => W_err_South_Req_L , err_West_Req_L => W_err_West_Req_L , err_South_Req_N => W_err_South_Req_N , err_East_Req_L => W_err_East_Req_L , err_West_Req_N => W_err_West_Req_N , err_East_Req_N => W_err_East_Req_N , err_next_state_onehot => W_err_next_state_onehot , err_state_in_onehot => W_err_state_in_onehot , err_state_north_xbar_sel => W_err_state_north_xbar_sel , err_state_east_xbar_sel => W_err_state_east_xbar_sel , err_state_west_xbar_sel => W_err_state_west_xbar_sel , err_state_south_xbar_sel => W_err_state_south_xbar_sel ); Arbiter_S: Arbiter PORT MAP (reset => reset, clk => clk, Req_N => Req_NS , Req_E => Req_ES, Req_W => Req_WS, Req_S => '0', Req_L => Req_LS, DCTS => DCTS_S, Grant_N => Grant_SN, Grant_E => Grant_SE, Grant_W => Grant_SW, Grant_S => Grant_SS, Grant_L => Grant_SL, Xbar_sel => Xbar_sel_S, RTS => RTS_S, err_state_IDLE_xbar => S_err_state_IDLE_xbar , err_state_not_IDLE_xbar => S_err_state_not_IDLE_xbar , err_state_IDLE_RTS_FF_in => S_err_state_IDLE_RTS_FF_in , err_state_not_IDLE_RTS_FF_RTS_FF_in => S_err_state_not_IDLE_RTS_FF_RTS_FF_in , err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => S_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in , err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => S_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in , err_RTS_FF_not_DCTS_state_state_in => S_err_RTS_FF_not_DCTS_state_state_in , err_not_RTS_FF_state_in_next_state => S_err_not_RTS_FF_state_in_next_state , err_RTS_FF_DCTS_state_in_next_state => S_err_RTS_FF_DCTS_state_in_next_state , err_not_DCTS_Grants => S_err_not_DCTS_Grants , err_DCTS_not_RTS_FF_Grants => S_err_DCTS_not_RTS_FF_Grants , err_DCTS_RTS_FF_IDLE_Grants => S_err_DCTS_RTS_FF_IDLE_Grants , err_DCTS_RTS_FF_not_IDLE_Grants_onehot => S_err_DCTS_RTS_FF_not_IDLE_Grants_onehot , err_Requests_next_state_IDLE => S_err_Requests_next_state_IDLE , err_IDLE_Req_L => S_err_IDLE_Req_L , err_Local_Req_L => S_err_Local_Req_L , err_North_Req_N => S_err_North_Req_N , err_IDLE_Req_N => S_err_IDLE_Req_N , err_Local_Req_N => S_err_Local_Req_N , err_South_Req_L => S_err_South_Req_L , err_West_Req_L => S_err_West_Req_L , err_South_Req_N => S_err_South_Req_N , err_East_Req_L => S_err_East_Req_L , err_West_Req_N => S_err_West_Req_N , err_East_Req_N => S_err_East_Req_N , err_next_state_onehot => S_err_next_state_onehot , err_state_in_onehot => S_err_state_in_onehot , err_state_north_xbar_sel => S_err_state_north_xbar_sel , err_state_east_xbar_sel => S_err_state_east_xbar_sel , err_state_west_xbar_sel => S_err_state_west_xbar_sel , err_state_south_xbar_sel => S_err_state_south_xbar_sel ); Arbiter_L: Arbiter PORT MAP (reset => reset, clk => clk, Req_N => Req_NL , Req_E => Req_EL, Req_W => Req_WL, Req_S => Req_SL, Req_L => '0', DCTS => DCTS_L, Grant_N => Grant_LN, Grant_E => Grant_LE, Grant_W => Grant_LW, Grant_S => Grant_LS, Grant_L => Grant_LL, Xbar_sel => Xbar_sel_L, RTS => RTS_L, err_state_IDLE_xbar => L_err_state_IDLE_xbar , err_state_not_IDLE_xbar => L_err_state_not_IDLE_xbar , err_state_IDLE_RTS_FF_in => L_err_state_IDLE_RTS_FF_in , err_state_not_IDLE_RTS_FF_RTS_FF_in => L_err_state_not_IDLE_RTS_FF_RTS_FF_in , err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => L_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in , err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => L_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in , err_RTS_FF_not_DCTS_state_state_in => L_err_RTS_FF_not_DCTS_state_state_in , err_not_RTS_FF_state_in_next_state => L_err_not_RTS_FF_state_in_next_state , err_RTS_FF_DCTS_state_in_next_state => L_err_RTS_FF_DCTS_state_in_next_state , err_not_DCTS_Grants => L_err_not_DCTS_Grants , err_DCTS_not_RTS_FF_Grants => L_err_DCTS_not_RTS_FF_Grants , err_DCTS_RTS_FF_IDLE_Grants => L_err_DCTS_RTS_FF_IDLE_Grants , err_DCTS_RTS_FF_not_IDLE_Grants_onehot => L_err_DCTS_RTS_FF_not_IDLE_Grants_onehot , err_Requests_next_state_IDLE => L_err_Requests_next_state_IDLE , err_IDLE_Req_L => L_err_IDLE_Req_L , err_Local_Req_L => L_err_Local_Req_L , err_North_Req_N => L_err_North_Req_N , err_IDLE_Req_N => L_err_IDLE_Req_N , err_Local_Req_N => L_err_Local_Req_N , err_South_Req_L => L_err_South_Req_L , err_West_Req_L => L_err_West_Req_L , err_South_Req_N => L_err_South_Req_N , err_East_Req_L => L_err_East_Req_L , err_West_Req_N => L_err_West_Req_N , err_East_Req_N => L_err_East_Req_N , err_next_state_onehot => L_err_next_state_onehot , err_state_in_onehot => L_err_state_in_onehot , err_state_north_xbar_sel => L_err_state_north_xbar_sel , err_state_east_xbar_sel => L_err_state_east_xbar_sel , err_state_west_xbar_sel => L_err_state_west_xbar_sel , err_state_south_xbar_sel => L_err_state_south_xbar_sel ); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- all the Xbars XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L, sel => Xbar_sel_N, Data_out=> TX_N); XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L, sel => Xbar_sel_E, Data_out=> TX_E); XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L, sel => Xbar_sel_W, Data_out=> TX_W); XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L, sel => Xbar_sel_S, Data_out=> TX_S); XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L, sel => Xbar_sel_L, Data_out=> TX_L); end;
gpl-3.0
757bcf4ea2a45e921fea7666cebc07f3
0.513386
3.115792
false
false
false
false
SoCdesign/EHA
Simulation/Fault_Management/Error_Detection_Correction/crc_decoder_tb.vhd
1
1,954
library ieee; use ieee.std_logic_1164.all; use std.textio.all; use ieee.std_logic_textio.all; use IEEE.NUMERIC_STD.all; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity decoder_tb is end decoder_tb; architecture arch of decoder_tb is component crc is port(rst, clk: in std_logic; data_in: in std_logic; ready : out std_logic; crc_out: out std_logic_vector (7 downto 0) ); end component; file outfile : text; -- declare the file to be a text file signal crc_out : std_logic_vector (7 downto 0); signal data: std_logic_vector (39 downto 0) := (others => '0'); signal clk, reset, data_in, ready: std_logic := '0'; constant clk_period : time := 1 ns; begin crc_module: crc port map(rst=>reset, clk =>clk, data_in => data_in, ready => ready, crc_out=>crc_out); clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; process variable LINEVARIABLE : line; variable fstatus : File_open_status; variable coutner_i : integer:=0; variable s: std_logic_vector (39 downto 0); file infile : text is in "encoded.txt"; --declare input file begin wait until clk'event and clk ='1'; if (not endfile(infile)) then readline(infile, LINEVARIABLE); read(LINEVARIABLE, s); else wait; end if; -- report integer'image(to_integer(unsigned(s))); data <= s; --data <= "0000000000000000000000000000000100000111"; data_in <= data(39); reset <= '0'; wait for 1 ns; reset <= '1'; while coutner_i < 40 loop wait until clk'event and clk ='1'; data_in <= data(39-coutner_i); coutner_i := coutner_i+1; end loop; wait until clk'event and clk ='1'; data_in<= '0'; wait until ready <= '1'; coutner_i := 0; end process; end architecture ; -- arch
gpl-3.0
a4e3d086e1cf9eac15ffc0475a0d16a4
0.594678
3.422067
false
false
false
false
TanND/Electronic
VHDL/D3_C2.vhd
1
745
library IEEE; use IEEE.STD_LOGIC_1164.all; entity D3_C2 is port( rst : in STD_LOGIC; clk : in STD_LOGIC; seg : out STD_LOGIC_VECTOR(7 downto 0) ); end D3_C2; architecture D3_C2 of D3_C2 is begin process(rst,clk) variable dem:integer range 0 to 9; begin if (rst='1') then dem:=0; elsif (rising_edge(clk)) then if (dem=8) then dem:=0; else dem:=dem+1; end if; end if; case dem is when 0=> seg <="00000000"; when 1=> seg <="00000001"; when 2=> seg <="00000010"; when 3=> seg <="00000100"; when 4=> seg <="00001000"; when 5=> seg <="00010000"; when 6=> seg <="00100000"; when 7=> seg <="01000000"; when others=> seg <="10000000"; end case; end process; end D3_C2; -- rst=500Khz; clk=10Mhz;
apache-2.0
4f9aae230b2bd995d0fcc239898262d7
0.609396
2.679856
false
false
false
false
mgiacomini/mips-pipeline
CTRL.vhd
1
3,055
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- Complete implementation of Patterson and Hennessy single cycle MIPS processor -- Copyright (C) 2015 Darci Luiz Tomasi Junior -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, version 3. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. -- -- Engineer: Darci Luiz Tomasi Junior -- E-mail: [email protected] -- Date : 25/06/2015 - 19:35 -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; ENTITY CTRL IS PORT( OPCode : IN STD_LOGIC_VECTOR(5 DOWNTO 0); RegDst : OUT STD_LOGIC; Jump : OUT STD_LOGIC; Branch : OUT STD_LOGIC; MemRead : OUT STD_LOGIC; MemtoReg : OUT STD_LOGIC; ALUOp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); MemWrite : OUT STD_LOGIC; ALUSrc : OUT STD_LOGIC; RegWrite : OUT STD_LOGIC ); END CTRL; ARCHITECTURE ARC_CTRL OF CTRL IS BEGIN PROCESS(OPCode) BEGIN CASE OPCode IS --TYPE R WHEN "000000" => RegDst <= '1'; Jump <= '0'; ALUSrc <= '0'; MemtoReg <= '0'; RegWrite <= '1'; MemRead <= '0'; MemWrite <= '0'; Branch <= '0'; ALUOp(1) <= '1'; ALUOp(0) <= '0'; --TYPE LW WHEN "100011" => RegDst <= '0'; Jump <= '0'; ALUSrc <= '1'; MemtoReg <= '1'; RegWrite <= '1'; MemRead <= '1'; MemWrite <= '0'; Branch <= '0'; ALUOp(1) <= '0'; ALUOp(0) <= '0'; --TYPE SW WHEN "101011" => RegDst <= '0'; --X Jump <= '0'; ALUSrc <= '1'; MemtoReg <= '0'; --X RegWrite <= '0'; MemRead <= '0'; MemWrite <= '1'; Branch <= '0'; ALUOp(1) <= '0'; ALUOp(0) <= '0'; --TYPE JUMP WHEN "000010" => RegDst <= '0'; --X Jump <= '1'; ALUSrc <= '0'; MemtoReg <= '0'; --X RegWrite <= '0'; MemRead <= '0'; MemWrite <= '0'; Branch <= '0'; ALUOp(1) <= '1'; ALUOp(0) <= '0'; --TYPE BEQ --TYPE BEQ WHEN OTHERS => RegDst <= '0'; --X Jump <= '0'; ALUSrc <= '0'; MemtoReg <= '0'; --X RegWrite <= '0'; MemRead <= '0'; MemWrite <= '0'; Branch <= '1'; ALUOp(1) <= '0'; ALUOp(0) <= '1'; END CASE; END PROCESS; END ARC_CTRL;
gpl-3.0
b3ea7ad68b9230583a7f042fd427c90d
0.47234
3.024752
false
false
false
false
SoCdesign/EHA
RTL/Immortal_Chip/FIFO_control_part_checkers.vhd
2
4,909
library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.ALL; entity FIFO_control_part_checkers is port ( DRTS: in std_logic; CTS_out: in std_logic; CTS_in: in std_logic; read_en_N : in std_logic; read_en_E : in std_logic; read_en_W : in std_logic; read_en_S : in std_logic; read_en_L : in std_logic; read_pointer: in std_logic_vector(3 downto 0); read_pointer_in: in std_logic_vector(3 downto 0); write_pointer: in std_logic_vector(3 downto 0); write_pointer_in: in std_logic_vector(3 downto 0); empty_out: in std_logic; full_out: in std_logic; read_en_out: in std_logic; write_en_out: in std_logic; -- Checker outputs err_write_en_write_pointer, err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full, err_read_pointer_increment, err_read_pointer_not_increment, --err_CTS_in, err_write_en, err_not_CTS_in, --err_not_write_en, err_read_en_mismatch : out std_logic ); end FIFO_control_part_checkers; architecture behavior of FIFO_control_part_checkers is signal read_en_signal: std_logic; begin read_en_signal <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty_out; -- Checkers process (write_en_out, write_pointer_in, write_pointer) begin if (write_en_out = '1' and write_pointer_in /= (write_pointer(2 downto 0) & write_pointer(3)) ) then err_write_en_write_pointer <= '1'; else err_write_en_write_pointer <= '0'; end if; end process; process (write_en_out, write_pointer_in, write_pointer) begin if (write_en_out = '0' and write_pointer_in /= write_pointer ) then err_not_write_en_write_pointer <= '1'; else err_not_write_en_write_pointer <= '0'; end if; end process; process (read_pointer, write_pointer, empty_out) begin if (read_pointer = write_pointer and empty_out = '0' ) then err_read_pointer_write_pointer_not_empty <= '1'; else err_read_pointer_write_pointer_not_empty <= '0'; end if; end process; process (read_pointer, write_pointer, empty_out) begin if (read_pointer /= write_pointer and empty_out = '1' ) then err_read_pointer_write_pointer_empty <= '1'; else err_read_pointer_write_pointer_empty <= '0'; end if; end process; process (write_pointer, read_pointer, full_out) begin if (write_pointer = (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '0' ) then err_read_pointer_write_pointer_not_full <= '1'; else err_read_pointer_write_pointer_not_full <= '0'; end if; end process; process (write_pointer, read_pointer, full_out) begin if (write_pointer /= (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '1' ) then err_read_pointer_write_pointer_full <= '1'; else err_read_pointer_write_pointer_full <= '0'; end if; end process; process (read_en_out, empty_out, read_pointer_in, read_pointer) begin if (read_en_out = '1' and empty_out = '0' and read_pointer_in /= (read_pointer(2 downto 0)&read_pointer(3)) ) then err_read_pointer_increment <= '1'; else err_read_pointer_increment <= '0'; end if; end process; process (read_en_out, empty_out, read_pointer_in, read_pointer) begin if ( (read_en_out = '0' or (read_en_out = '1' and empty_out = '1') ) and read_pointer_in /= read_pointer ) then err_read_pointer_not_increment <= '1'; else err_read_pointer_not_increment <= '0'; end if; end process; --process (CTS_out, DRTS, full_out, CTS_in) --begin -- if (CTS_out = '0' and DRTS = '1' and full_out = '0' and CTS_in = '0') then -- err_CTS_in <= '1'; -- else -- err_CTS_in <= '0'; -- end if; --end process; process (CTS_out, DRTS, full_out, write_en_out) begin if (CTS_out = '0' and DRTS = '1' and full_out = '0' and write_en_out = '0') then err_write_en <= '1'; else err_write_en <= '0'; end if; end process; process (CTS_out, DRTS, full_out, CTS_in) begin if ( (CTS_out = '1' or (CTS_out = '0' and DRTS = '0') or (CTS_out = '0' and DRTS = '1' and full_out = '1')) and CTS_in = '1') then err_not_CTS_in <= '1'; else err_not_CTS_in <= '0'; end if; end process; --process (CTS_out, DRTS, full_out, write_en_out) --begin -- if ( (CTS_out = '1' or (CTS_out = '0' and DRTS = '0') or (CTS_out = '0' and DRTS = '1' and full_out = '1')) and write_en_out = '1') then -- err_not_write_en <= '1'; -- else -- err_not_write_en <= '0'; -- end if; --end process; process (read_en_out, read_en_signal) begin if (read_en_out /= read_en_signal) then err_read_en_mismatch <= '1'; else err_read_en_mismatch <= '0'; end if; end process; end behavior;
gpl-3.0
3572302e4f94d3fe362a3b9496a76fcd
0.632512
2.695772
false
false
false
false
bruskajp/EE-316
Project2/Quartus_DE2Board/i2c_master_2.1.vhd
1
15,693
-------------------------------------------------------------------------------- -- -- FileName: i2c_master.vhd -- Dependencies: none -- Design Software: Quartus II 64-bit Version 13.1 Build 162 SJ Full Version -- -- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY -- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A -- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY -- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL -- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF -- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS -- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), -- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS. -- -- Version History -- Version 1.0 11/1/2012 Scott Larson -- Initial Public Release -- Version 2.0 06/20/2014 Scott Larson -- Added ability to interface with different slaves in the same transaction -- Corrected ack_error bug where ack_error went 'Z' instead of '1' on error -- Corrected timing of when ack_error signal clears -- Version 2.1 10/21/2014 Scott Larson -- Replaced gated clock with clock enable -- Adjusted timing of SCL during start and stop conditions -- -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY i2c_master IS GENERIC( input_clk : INTEGER := 50_000_000; --input clock speed from user logic in Hz bus_clk : INTEGER := 100_000); --speed the i2c bus (scl) will run at in Hz PORT( clk : IN STD_LOGIC; --system clock reset_n : IN STD_LOGIC; --active low reset ena : IN STD_LOGIC; --latch in command addr : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave rw : IN STD_LOGIC; --'0' is write, '1' is read data_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --data to write to slave busy : OUT STD_LOGIC; --indicates transaction in progress data_rd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave ack_error : BUFFER STD_LOGIC; --flag if improper acknowledge from slave sda : INOUT STD_LOGIC; --serial data output of i2c bus scl : INOUT STD_LOGIC); END i2c_master; ARCHITECTURE logic OF i2c_master IS CONSTANT divider : INTEGER := (input_clk/bus_clk)/4; --number of clocks in 1/4 cycle of scl TYPE machine IS(ready, start, command, slv_ack1, wr, rd, slv_ack2, mstr_ack, stop); --needed states SIGNAL state : machine; --state machine SIGNAL data_clk : STD_LOGIC; --data clock for sda SIGNAL data_clk_prev : STD_LOGIC; --data clock during previous system clock SIGNAL data_clk_m : STD_LOGIC; --data clock during previous system clock SIGNAL scl_clk : STD_LOGIC; --constantly running internal scl SIGNAL scl_ena : STD_LOGIC := '0'; --enables internal scl to output SIGNAL sda_int : STD_LOGIC := '1'; --internal sda SIGNAL sda_ena_n : STD_LOGIC; --enables internal sda to output SIGNAL addr_rw : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in address and read/write SIGNAL data_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in data to write to slave SIGNAL data_rx : STD_LOGIC_VECTOR(7 DOWNTO 0); --data received from slave SIGNAL bit_cnt : INTEGER RANGE 0 TO 7 := 7; --tracks bit number in transaction SIGNAL stretch : STD_LOGIC := '0'; --identifies if slave is stretching scl BEGIN --generate the timing for the bus clock (scl_clk) and the data clock (data_clk) PROCESS(clk, reset_n) VARIABLE count : INTEGER RANGE 0 TO divider*4; --timing for clock generation BEGIN IF(reset_n = '0') THEN --reset asserted stretch <= '0'; count := 0; ELSIF(clk'EVENT AND clk = '1') THEN data_clk_prev <= data_clk; --store previous value of data clock IF(count = 499) THEN --end of timing cycle count := 0; --reset timer ELSIF(stretch = '0') THEN --clock stretching from slave not detected count := count + 1; --continue clock generation timing END IF; CASE count IS WHEN 0 TO 124 => --first 1/4 cycle of clocking scl_clk <= '0'; data_clk <= '0'; WHEN 125 TO 249 => --second 1/4 cycle of clocking scl_clk <= '0'; data_clk <= '1'; WHEN 250 TO 324 => --third 1/4 cycle of clocking scl_clk <= '1'; --release scl IF(scl = '0') THEN --detect if slave is stretching clock stretch <= '1'; ELSE stretch <= '0'; END IF; data_clk <= '1'; WHEN OTHERS => --last 1/4 cycle of clocking scl_clk <= '1'; data_clk <= '0'; END CASE; END IF; END PROCESS; --state machine and writing to sda during scl low (data_clk rising edge) PROCESS(clk, reset_n) BEGIN IF(reset_n = '0') THEN --reset asserted state <= ready; --return to initial state busy <= '1'; --indicate not available scl_ena <= '0'; --sets scl high impedance sda_int <= '1'; --sets sda high impedance ack_error <= '0'; --clear acknowledge error flag bit_cnt <= 7; --restarts data bit counter data_rd <= "00000000"; --clear data read port ELSIF(clk'EVENT AND clk = '1') THEN IF(data_clk = '1' AND data_clk_prev = '0') THEN --data clock rising edge CASE state IS WHEN ready => --idle state IF(ena = '1') THEN --transaction requested busy <= '1'; --flag busy addr_rw <= addr & rw; --collect requested slave address and command data_tx <= data_wr; --collect requested data to write state <= start; --go to start bit ELSE --remain idle busy <= '0'; --unflag busy state <= ready; --remain idle END IF; WHEN start => --start bit of transaction busy <= '1'; --resume busy if continuous mode sda_int <= addr_rw(bit_cnt); --set first address bit to bus state <= command; --go to command WHEN command => --address and command byte of transaction IF(bit_cnt = 0) THEN --command transmit finished sda_int <= '1'; --release sda for slave acknowledge bit_cnt <= 7; --reset bit counter for "byte" states state <= slv_ack1; --go to slave acknowledge (command) ELSE --next clock cycle of command state bit_cnt <= bit_cnt - 1; --keep track of transaction bits sda_int <= addr_rw(bit_cnt-1); --write address/command bit to bus state <= command; --continue with command END IF; WHEN slv_ack1 => --slave acknowledge bit (command) IF(addr_rw(0) = '0') THEN --write command sda_int <= data_tx(bit_cnt); --write first bit of data state <= wr; --go to write byte ELSE --read command sda_int <= '1'; --release sda from incoming data state <= rd; --go to read byte END IF; WHEN wr => --write byte of transaction busy <= '1'; --resume busy if continuous mode IF(bit_cnt = 0) THEN --write byte transmit finished sda_int <= '1'; --release sda for slave acknowledge bit_cnt <= 7; --reset bit counter for "byte" states -- added the following line to make sure busy = 0 in the slv_ack2 state busy <= '0'; --continue is accepted (modified by CU) state <= slv_ack2; --go to slave acknowledge (write) ELSE --next clock cycle of write state bit_cnt <= bit_cnt - 1; --keep track of transaction bits sda_int <= data_tx(bit_cnt-1); --write next bit to bus state <= wr; --continue writing END IF; WHEN rd => --read byte of transaction busy <= '1'; --resume busy if continuous mode IF(bit_cnt = 0) THEN --read byte receive finished IF(ena = '1' AND addr_rw = addr & rw) THEN --continuing with another read at same address sda_int <= '0'; --acknowledge the byte has been received ELSE --stopping or continuing with a write sda_int <= '1'; --send a no-acknowledge (before stop or repeated start) END IF; bit_cnt <= 7; --reset bit counter for "byte" states -- added the following line to make sure busy = 0 in the mstr_ack state busy <= '0'; --continue is accepted (modified by CU) data_rd <= data_rx; --output received data state <= mstr_ack; --go to master acknowledge ELSE --next clock cycle of read state bit_cnt <= bit_cnt - 1; --keep track of transaction bits state <= rd; --continue reading END IF; WHEN slv_ack2 => --slave acknowledge bit (write) IF(ena = '1') THEN --continue transaction -- busy <= '0'; --continue is accepted (modified by CU) addr_rw <= addr & rw; --collect requested slave address and command data_tx <= data_wr; --collect requested data to write IF(addr_rw = addr & rw) THEN --continue transaction with another write busy <= '1'; --resume busy in the wr state (modified by CU) sda_int <= data_wr(bit_cnt); --write first bit of data state <= wr; --go to write byte ELSE --continue transaction with a read or new slave state <= start; --go to repeated start END IF; ELSE --complete transaction busy <= '0'; --unflag busy (modified by CU) sda_int <= '1'; --sets sda high impedance (modified by CU) state <= stop; --go to stop bit END IF; WHEN mstr_ack => --master acknowledge bit after a read IF(ena = '1') THEN --continue transaction -- busy <= '0'; --continue is accepted (modified by CU) addr_rw <= addr & rw; --collect requested slave address and command data_tx <= data_wr; --collect requested data to write IF(addr_rw = addr & rw) THEN --continue transaction with another read busy <= '1'; --resume busy in the wr state (modified by CU) sda_int <= '1'; --release sda from incoming data state <= rd; --go to read byte ELSE --continue transaction with a write or new slave state <= start; --repeated start END IF; ELSE --complete transaction busy <= '0'; --unflag busy (modified by CU) sda_int <= '1'; --sets sda high impedance (modified by CU) state <= stop; --go to stop bit END IF; WHEN stop => --stop bit of transaction -- busy <= '0'; --unflag busy (modified by CU) state <= ready; --go to idle state END CASE; ELSIF(data_clk = '0' AND data_clk_prev = '1') THEN --data clock falling edge CASE state IS WHEN start => IF(scl_ena = '0') THEN --starting new transaction scl_ena <= '1'; --enable scl output ack_error <= '0'; --reset acknowledge error output END IF; WHEN slv_ack1 => --receiving slave acknowledge (command) IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge ack_error <= '1'; --set error output if no-acknowledge END IF; WHEN rd => --receiving slave data data_rx(bit_cnt) <= sda; --receive current slave data bit WHEN slv_ack2 => --receiving slave acknowledge (write) IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge ack_error <= '1'; --set error output if no-acknowledge END IF; WHEN stop => scl_ena <= '0'; --disable scl WHEN OTHERS => NULL; END CASE; END IF; END IF; END PROCESS; --set sda output data_clk_m <= data_clk_prev and data_clk; -- Modification added at CU WITH state SELECT sda_ena_n <= data_clk WHEN start, --generate start condition NOT data_clk_m WHEN stop, --generate stop condition (modification added at CU) sda_int WHEN OTHERS; --set to internal sda signal --set scl and sda outputs scl <= '0' WHEN (scl_ena = '1' AND scl_clk = '0') ELSE 'Z'; sda <= '0' WHEN sda_ena_n = '0' ELSE 'Z'; -- Following two signals will be used for tristate obuft (did not work) -- scl <= '1' WHEN (scl_ena = '1' AND scl_clk = '0') ELSE '0'; -- sda <= '1' WHEN sda_ena_n = '0' ELSE '0'; END logic;
gpl-3.0
3c6f8af6efee7f18147f69f345435d18
0.474734
4.685876
false
false
false
false
bruskajp/EE-316
Project5/top_level.vhd
1
20,357
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 04/05/2017 01:36:15 PM -- Design Name: -- Module Name: top_level - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity top_level is port( clk_100mhz : in STD_LOGIC; save_button_input : in STD_LOGIC; ps2_clk : in std_logic; ps2_data : in std_logic; scl : inout std_logic; sda : inout std_logic; tx : inout std_logic; rx : inout std_logic; potX : inout std_logic_vector(7 downto 0); potY : inout std_logic_vector(7 downto 0); VGA_H_SYNC : out std_logic; VGA_V_SYNC : out std_logic; VGA_R : out std_logic_vector(3 downto 0); VGA_G : out std_logic_vector(3 downto 0); VGA_B : out std_logic_vector(3 downto 0) --usb_bt_input : in STD_LOGIC; --keyboard_input : in STD_LOGIC_VECTOR(7 downto 0); --poten_x_pos_input : in STD_LOGIC_VECTOR(7 downto 0); --poten_y_pos_input : in STD_LOGIC_VECTOR(7 downto 0); --usb_bt_output : out STD_LOGIC; --lcd_output : out STD_LOGIC_VECTOR(7 downto 0); -- PUT BACK --vga_output : out STD_LOGIC_VECTOR(11 downto 0); --tricolor_lcd_output : out STD_LOGIC_VECTOR(11 downto 0); -- PUT BACK ); end top_level; architecture Behavioral of top_level is -- RAM component component blk_mem_gen_0 port( clka : in STD_LOGIC; wea : in STD_LOGIC_VECTOR(0 downto 0); addra : in STD_LOGIC_VECTOR(16 downto 0); dina : in STD_LOGIC_VECTOR(11 downto 0); clkb : in STD_LOGIC; addrb : in STD_LOGIC_VECTOR(16 downto 0); doutb : out STD_LOGIC_VECTOR(11 downto 0) ); end component; -- Game logic component component game_logic is port( clk : in STD_LOGIC; usb_bt_clk : in STD_LOGIC; save_button_input : in STD_LOGIC; keyboard_input : in STD_LOGIC_VECTOR(7 downto 0); x_pos_input : in STD_LOGIC_VECTOR(7 downto 0); y_pos_input : in STD_LOGIC_VECTOR(7 downto 0); usb_bt_input : in STD_LOGIC_VECTOR(7 downto 0); reset_output : out STD_LOGIC; screen_size_output : out STD_LOGIC; pen_width_output : out STD_LOGIC_VECTOR(2 downto 0); x_pos_output : out STD_LOGIC_VECTOR(7 downto 0); y_pos_output : out STD_LOGIC_VECTOR(7 downto 0); tricolor_led_output : out STD_LOGIC_VECTOR(11 downto 0); usb_bt_output : out STD_LOGIC_VECTOR(15 downto 0); color_output : out STD_LOGIC_VECTOR(23 downto 0); ram_we_output : out STD_LOGIC_VECTOR(0 downto 0); ram_val_output : out STD_LOGIC_VECTOR(11 downto 0); ram_addr_output : out STD_LOGIC_VECTOR(16 downto 0) ); end component; -- USB/Bluetooth clock divider component component clock_divider is generic(count_max : INTEGER := 2); -- CHANGE VALUE port( clk : in STD_LOGIC; reset : in STD_LOGIC; clk_output : out STD_LOGIC ); end component; component sys_clk IS GENERIC ( CONSTANT REF_CLK : integer := 100000000; -- 100.0 MHz CONSTANT OUT_CLK : integer := 25000000); PORT ( SIGNAL oCLK : INOUT std_logic; SIGNAL iCLK : IN std_logic; SIGNAL iRST : IN std_logic); END component; component vga_sync IS GENERIC ( H_SYNC_TOTAL : INTEGER := 800; H_PIXELS : INTEGER := 640; H_SYNC_START : INTEGER := 659; H_SYNC_WIDTH : INTEGER := 96; V_SYNC_TOTAL : INTEGER := 525; V_PIXELS : INTEGER := 480; V_SYNC_START : INTEGER := 493; V_SYNC_WIDTH : INTEGER := 2; H_START : INTEGER := 699 ); PORT ( iCLK : IN STD_LOGIC; iRST_N : IN STD_LOGIC; iRed : IN STD_LOGIC_VECTOR(3 DOWNTO 0); iGreen : IN STD_LOGIC_VECTOR(3 DOWNTO 0); iBlue : IN STD_LOGIC_VECTOR(3 DOWNTO 0); px : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); py : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); VGA_R : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); VGA_G : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); VGA_B : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); VGA_H_SYNC : OUT STD_LOGIC; VGA_V_SYNC : OUT STD_LOGIC --VGA_BLANK : OUT STD_LOGIC ); END component; component vga_out is PORT ( iCLK : in STD_LOGIC; px : in STD_LOGIC_VECTOR(9 DOWNTO 0); py : in STD_LOGIC_VECTOR(9 DOWNTO 0); potX : in STD_LOGIC_VECTOR(7 DOWNTO 0); potY : in STD_LOGIC_VECTOR(7 DOWNTO 0); color : in STD_LOGIC_VECTOR(11 downto 0); red : out STD_LOGIC_VECTOR(3 DOWNTO 0); green : out STD_LOGIC_VECTOR(3 DOWNTO 0); blue : out STD_LOGIC_VECTOR(3 DOWNTO 0); ram_addr_output : out STD_LOGIC_VECTOR(16 downto 0) ); end component; component i2c_user_logic is Port ( clk : in std_logic; busy : in std_logic; data_rd : in std_logic_vector(7 downto 0); ienable : in std_logic; i2c_ena : out std_logic; i2c_addr : out std_logic_vector(6 downto 0); i2c_rw : out std_logic; reset_n : out std_logic; i2c_data_wr : out std_logic_vector(7 downto 0); valid : out std_logic; data16bit : out std_logic_vector(15 downto 0) ); end component; component i2c_master IS GENERIC( input_clk : INTEGER := 100_000_000; --input clock speed from user logic in Hz bus_clk : INTEGER := 9600); --speed the i2c bus (scl) will run at in Hz PORT( clk : IN STD_LOGIC; --system clock reset_n : IN STD_LOGIC; --active low reset ena : IN STD_LOGIC; --latch in command addr : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave rw : IN STD_LOGIC; --'0' is write, '1' is read data_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --data to write to slave busy : OUT STD_LOGIC; --indicates transaction in progress data_rd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave ack_error : BUFFER STD_LOGIC; --flag if improper acknowledge from slave sda : INOUT STD_LOGIC; --serial data output of i2c bus scl : INOUT STD_LOGIC); --serial clock output of i2c bus end component; component ps2_keyboard_to_ascii IS GENERIC( clk_freq : INTEGER := 100_000_000; --system clock frequency in Hz ps2_debounce_counter_size : INTEGER := 9); --set such that 2^size/clk_freq = 5us (size = 8 for 50MHz) PORT( clk : IN STD_LOGIC; --system clock input ps2_clk : IN STD_LOGIC; --clock signal from PS2 keyboard ps2_data : IN STD_LOGIC; --data signal from PS2 keyboard ascii_new : OUT STD_LOGIC; --output flag indicating new ASCII value ascii_code : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); --ASCII value END component; component uart is port ( reset :in std_logic; txclk :in std_logic; ld_tx_data :in std_logic; tx_data :in std_logic_vector (7 downto 0); tx_enable :in std_logic; tx_out :out std_logic; tx_empty :out std_logic; rxclk :in std_logic; uld_rx_data :in std_logic; rx_data :out std_logic_vector (7 downto 0); rx_enable :in std_logic; rx_in :in std_logic; rx_empty :out std_logic ); end component; -- RAM signals signal ram_addrb : STD_LOGIC_VECTOR(16 downto 0); signal ram_doutb : STD_LOGIC_VECTOR(11 downto 0); -- Game logic signals signal gl_reset : STD_LOGIC; signal gl_screen_size : STD_LOGIC; signal gl_pen_width : STD_LOGIC_VECTOR(2 downto 0); signal gl_x_pos, gl_y_pos : STD_LOGIC_VECTOR(7 downto 0); signal gl_tricolor_led : STD_LOGIC_VECTOR(11 downto 0); signal gl_usb_bt : STD_LOGIC_VECTOR(15 downto 0); signal gl_color : STD_LOGIC_VECTOR(23 downto 0); signal gl_ram_we : STD_LOGIC_VECTOR(0 downto 0); signal gl_ram_val : STD_LOGIC_VECTOR(11 downto 0); signal gl_ram_addr : STD_LOGIC_VECTOR(16 downto 0); -- Potentionmeter interface signals signal poten_x_pos : STD_LOGIC_VECTOR(7 downto 0); signal poten_y_pos : STD_LOGIC_VECTOR(7 downto 0); -- USB/Bluetooth signals signal usb_bt_input_vector : STD_LOGIC_VECTOR(7 downto 0); signal usb_bt_output_vector : STD_LOGIC_VECTOR(7 downto 0); -- USB/Bluetooth clock divider signals signal usb_bt_clk : STD_LOGIC; -- Ryan's shit signal reset_n : std_logic; signal px : std_logic_vector(9 downto 0); signal py : std_logic_vector(9 downto 0); signal red : std_logic_vector(3 downto 0); signal green : std_logic_vector(3 downto 0); signal blue : std_logic_vector(3 downto 0); signal i2cClk : std_logic; signal i2c_ena : std_logic; signal i2c_addr : std_logic_vector(6 downto 0); signal i2c_rw : std_logic; signal i2c_reset : std_logic; signal i2c_data_wr : std_logic_vector(7 downto 0); signal vgaClk : std_logic; signal busy : std_logic; signal ack_error : std_logic; signal ascii_code : std_logic_vector(6 downto 0); signal full_ascii_code : std_logic_vector(7 downto 0); signal ascii_new : std_logic; signal valid : std_logic; signal data_rd : std_logic_vector(7 downto 0); signal data16bit : std_logic_vector(15 downto 0); signal uartClk : std_logic; signal uartClkEna: std_logic; signal rx_data : std_logic_vector(7 downto 0); begin -- RAM port map ram : blk_mem_gen_0 port map ( clka => clk_100mhz, wea => gl_ram_we, addra => gl_ram_addr, dina => gl_ram_val, clkb => clk_100mhz, addrb => ram_addrb, doutb => ram_doutb ); full_ascii_code <= "0" & ascii_code; -- Game logic port map gl : game_logic port map( clk => clk_100mhz, usb_bt_clk => usb_bt_clk, save_button_input => save_button_input, keyboard_input => full_ascii_code, x_pos_input => potX, y_pos_input => potY, usb_bt_input => usb_bt_input_vector, reset_output => gl_reset, screen_size_output => gl_screen_size, pen_width_output => gl_pen_width, x_pos_output => gl_x_pos, y_pos_output => gl_y_pos, color_output => gl_color, tricolor_led_output => gl_tricolor_led, usb_bt_output => gl_usb_bt, ram_we_output => gl_ram_we, ram_val_output => gl_ram_val, ram_addr_output => gl_ram_addr ); -- USB/Bluetooth clock divider port map usb_bt_clock_divider : clock_divider generic map(count_max => 2) -- CHANGE VALUE port map( clk => clk_100mhz, reset => '0', clk_output => usb_bt_clk ); -- Ryan's mess reset_n <= not gl_reset; process(clk_100mhz) begin if(rising_edge(clk_100mhz)) then if(valid = '1') then if(data16bit(12) = '0') then potX <= data16bit(11 downto 4); elsif(data16bit(12) = '1') then potY <= data16bit(11 downto 4); end if; end if; end if; end process; Inst_sys_clk : sys_clk GENERIC map ( REF_CLK => 100000000, -- 100.0 MHz OUT_CLK => 25000000) PORT map ( oCLK => vgaClk, iCLK => clk_100mhz, iRST => gl_reset ); Inst_i2c_clk : sys_clk GENERIC map ( REF_CLK => 100000000, -- 100.0 MHz OUT_CLK => 1000000) PORT map ( oCLK => i2cClk, iCLK => clk_100mhz, iRST => gl_reset ); Inst_uart_clk : sys_clk GENERIC map ( REF_CLK => 100000000, -- 100.0 MHz OUT_CLK => 115200) PORT map ( oCLK => uartClk, iCLK => clk_100mhz, iRST => gl_reset ); Inst_uartEna_clk : sys_clk GENERIC map ( REF_CLK => 100000000, -- 100.0 MHz OUT_CLK => 11520) PORT map ( oCLK => uartClkEna, iCLK => clk_100mhz, iRST => gl_reset ); Inst_vga_sync : vga_sync GENERIC map ( H_SYNC_TOTAL => 800, H_PIXELS => 640, H_SYNC_START => 659, H_SYNC_WIDTH => 96, V_SYNC_TOTAL => 525, V_PIXELS => 480, V_SYNC_START => 493, V_SYNC_WIDTH => 2, H_START => 699) PORT map ( iCLK => vgaClk, iRST_N => reset_n, iRed => red, iGreen => green, iBlue => blue, px => px, py => py, VGA_R => VGA_R, VGA_G => VGA_G, VGA_B => VGA_B, VGA_H_SYNC => VGA_H_SYNC, VGA_V_SYNC => VGA_V_SYNC --VGA_BLANK => ); Inst_vga_out : vga_out PORT map( iCLK => clk_100mhz, px => px, py => py, potX => potX, potY => potY, color => ram_doutb, red => red, green => green, blue => blue, ram_addr_output => ram_addrb ); Inst_i2c_user_logic : i2c_user_logic Port map( clk => clk_100mhz, busy => busy, ienable => '1', data_rd => data_rd, i2c_ena => i2c_ena, i2c_addr => i2c_addr, i2c_rw => i2c_rw, reset_n => i2c_reset, i2c_data_wr => i2c_data_wr, valid => valid, data16bit => data16bit ); Inst_i2c_master : i2c_master GENERIC map( input_clk => 100_000_000, --input clock speed from user logic in Hz bus_clk => 9600) --speed the i2c bus (scl) will run at in Hz PORT map( clk => clk_100mhz, --system clock reset_n => i2c_reset, --active low reset ena => i2c_ena, --latch in command addr => i2c_addr, --address of target slave rw => i2c_rw, --'0' is write, '1' is read data_wr => i2c_data_wr, --data to write to slave busy => busy, --indicates transaction in progress data_rd => data_rd, --data read from slave ack_error => ack_error, --flag if improper acknowledge from slave sda => sda, --serial data output of i2c bus scl => scl --serial clock output of i2c bus ); Inst_ps2_keyboard_to_ascii : ps2_keyboard_to_ascii GENERIC map( clk_freq => 100_000_000, --system clock frequency in Hz ps2_debounce_counter_size => 9) --set such that 2^size/clk_freq = 5us (size = 8 for 50MHz) PORT map( clk => clk_100mhz, --system clock input ps2_clk => ps2_clk, --clock signal from PS2 keyboard ps2_data => ps2_data, --data signal from PS2 keyboard ascii_new => ascii_new, --output flag indicating new ASCII value ascii_code => ascii_code); --ASCII value Inst_uart : uart port map( reset => gl_reset, txclk => uartClk, ld_tx_data => uartClkEna, tx_data => gl_usb_bt(7 downto 0), -- FIX THIS (its actually 2 sets of commands) tx_enable => '1', tx_out => tx, --o tx_empty => open, --o rxclk => uartClk, uld_rx_data => uartClkEna, rx_data => usb_bt_input_vector, --o (7 downto 0) rx_enable => '1', rx_in => rx, rx_empty => open --o ); end Behavioral;
gpl-3.0
0b54bf6558d69aa744227206928e7943
0.437786
4.162986
false
false
false
false
bruskajp/EE-316
Project2/Vivado_NexysBoard/project_2b/project_2b.srcs/sources_1/ip/blk_mem_LUT/blk_mem_LUT_sim_netlist.vhdl
1
41,218
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.2 (win64) Build 1577090 Thu Jun 2 16:32:40 MDT 2016 -- Date : Sun Feb 05 19:48:52 2017 -- Host : ul-13 running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode funcsim {c:/Users/ulab/Documents/James -- Bruska/project_2/project_2.srcs/sources_1/ip/blk_mem_LUT/blk_mem_LUT_sim_netlist.vhdl} -- Design : blk_mem_LUT -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7a100tcsg324-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity blk_mem_LUT_blk_mem_gen_prim_wrapper_init is port ( douta : out STD_LOGIC_VECTOR ( 15 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 3 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of blk_mem_LUT_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init"; end blk_mem_LUT_blk_mem_gen_prim_wrapper_init; architecture STRUCTURE of blk_mem_LUT_blk_mem_gen_prim_wrapper_init is signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_0\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_1\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_10\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_11\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_16\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_17\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_18\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_19\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_2\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_24\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_25\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_26\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_27\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_3\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_8\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_9\ : STD_LOGIC; attribute CLOCK_DOMAINS : string; attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : label is "COMMON"; attribute box_type : string; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : label is "PRIMITIVE"; begin \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\: unisim.vcomponents.RAMB18E1 generic map( DOA_REG => 1, DOB_REG => 1, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"0D0E0A0D0F0E0E0D0C0C0D0D0A0A0B0B0F0E040505000500000A000A00000000", INIT_01 => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0B0E0E0F", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"00000", INIT_B => X"00000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", READ_WIDTH_A => 18, READ_WIDTH_B => 18, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"00000", SRVAL_B => X"00000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 18, WRITE_WIDTH_B => 18 ) port map ( ADDRARDADDR(13 downto 9) => B"00000", ADDRARDADDR(8 downto 5) => addra(3 downto 0), ADDRARDADDR(4 downto 0) => B"00000", ADDRBWRADDR(13 downto 9) => B"00000", ADDRBWRADDR(8 downto 5) => addra(3 downto 0), ADDRBWRADDR(4 downto 0) => B"10000", CLKARDCLK => clka, CLKBWRCLK => clka, DIADI(15 downto 0) => B"0000000000000000", DIBDI(15 downto 0) => B"0000000000000000", DIPADIP(1 downto 0) => B"00", DIPBDIP(1 downto 0) => B"00", DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_0\, DOADO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_1\, DOADO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_2\, DOADO(12) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_3\, DOADO(11 downto 8) => douta(7 downto 4), DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_8\, DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_9\, DOADO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_10\, DOADO(4) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_11\, DOADO(3 downto 0) => douta(3 downto 0), DOBDO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_16\, DOBDO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_17\, DOBDO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_18\, DOBDO(12) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_19\, DOBDO(11 downto 8) => douta(15 downto 12), DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_24\, DOBDO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_25\, DOBDO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_26\, DOBDO(4) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_27\, DOBDO(3 downto 0) => douta(11 downto 8), DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32\, DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33\, DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34\, DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35\, ENARDEN => ena, ENBWREN => ena, REGCEAREGCE => ena, REGCEB => ena, RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', WEA(1 downto 0) => B"00", WEBWE(3 downto 0) => B"0000" ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity blk_mem_LUT_blk_mem_gen_prim_width is port ( douta : out STD_LOGIC_VECTOR ( 15 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 3 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of blk_mem_LUT_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width"; end blk_mem_LUT_blk_mem_gen_prim_width; architecture STRUCTURE of blk_mem_LUT_blk_mem_gen_prim_width is begin \prim_init.ram\: entity work.blk_mem_LUT_blk_mem_gen_prim_wrapper_init port map ( addra(3 downto 0) => addra(3 downto 0), clka => clka, douta(15 downto 0) => douta(15 downto 0), ena => ena ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity blk_mem_LUT_blk_mem_gen_generic_cstr is port ( douta : out STD_LOGIC_VECTOR ( 15 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 3 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of blk_mem_LUT_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr"; end blk_mem_LUT_blk_mem_gen_generic_cstr; architecture STRUCTURE of blk_mem_LUT_blk_mem_gen_generic_cstr is begin \ramloop[0].ram.r\: entity work.blk_mem_LUT_blk_mem_gen_prim_width port map ( addra(3 downto 0) => addra(3 downto 0), clka => clka, douta(15 downto 0) => douta(15 downto 0), ena => ena ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity blk_mem_LUT_blk_mem_gen_top is port ( douta : out STD_LOGIC_VECTOR ( 15 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 3 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of blk_mem_LUT_blk_mem_gen_top : entity is "blk_mem_gen_top"; end blk_mem_LUT_blk_mem_gen_top; architecture STRUCTURE of blk_mem_LUT_blk_mem_gen_top is begin \valid.cstr\: entity work.blk_mem_LUT_blk_mem_gen_generic_cstr port map ( addra(3 downto 0) => addra(3 downto 0), clka => clka, douta(15 downto 0) => douta(15 downto 0), ena => ena ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity blk_mem_LUT_blk_mem_gen_v8_3_3_synth is port ( douta : out STD_LOGIC_VECTOR ( 15 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 3 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of blk_mem_LUT_blk_mem_gen_v8_3_3_synth : entity is "blk_mem_gen_v8_3_3_synth"; end blk_mem_LUT_blk_mem_gen_v8_3_3_synth; architecture STRUCTURE of blk_mem_LUT_blk_mem_gen_v8_3_3_synth is begin \gnbram.gnativebmg.native_blk_mem_gen\: entity work.blk_mem_LUT_blk_mem_gen_top port map ( addra(3 downto 0) => addra(3 downto 0), clka => clka, douta(15 downto 0) => douta(15 downto 0), ena => ena ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity blk_mem_LUT_blk_mem_gen_v8_3_3 is port ( clka : in STD_LOGIC; rsta : in STD_LOGIC; ena : in STD_LOGIC; regcea : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 3 downto 0 ); dina : in STD_LOGIC_VECTOR ( 15 downto 0 ); douta : out STD_LOGIC_VECTOR ( 15 downto 0 ); clkb : in STD_LOGIC; rstb : in STD_LOGIC; enb : in STD_LOGIC; regceb : in STD_LOGIC; web : in STD_LOGIC_VECTOR ( 0 to 0 ); addrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 15 downto 0 ); doutb : out STD_LOGIC_VECTOR ( 15 downto 0 ); injectsbiterr : in STD_LOGIC; injectdbiterr : in STD_LOGIC; eccpipece : in STD_LOGIC; sbiterr : out STD_LOGIC; dbiterr : out STD_LOGIC; rdaddrecc : out STD_LOGIC_VECTOR ( 3 downto 0 ); sleep : in STD_LOGIC; deepsleep : in STD_LOGIC; shutdown : in STD_LOGIC; rsta_busy : out STD_LOGIC; rstb_busy : out STD_LOGIC; s_aclk : in STD_LOGIC; s_aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 15 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 15 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; s_axi_injectsbiterr : in STD_LOGIC; s_axi_injectdbiterr : in STD_LOGIC; s_axi_sbiterr : out STD_LOGIC; s_axi_dbiterr : out STD_LOGIC; s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 3 downto 0 ) ); attribute C_ADDRA_WIDTH : integer; attribute C_ADDRA_WIDTH of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 4; attribute C_ADDRB_WIDTH : integer; attribute C_ADDRB_WIDTH of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 4; attribute C_ALGORITHM : integer; attribute C_ALGORITHM of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 1; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 4; attribute C_AXI_SLAVE_TYPE : integer; attribute C_AXI_SLAVE_TYPE of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 0; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 1; attribute C_BYTE_SIZE : integer; attribute C_BYTE_SIZE of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 9; attribute C_COMMON_CLK : integer; attribute C_COMMON_CLK of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 0; attribute C_COUNT_18K_BRAM : string; attribute C_COUNT_18K_BRAM of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is "1"; attribute C_COUNT_36K_BRAM : string; attribute C_COUNT_36K_BRAM of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is "0"; attribute C_CTRL_ECC_ALGO : string; attribute C_CTRL_ECC_ALGO of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is "NONE"; attribute C_DEFAULT_DATA : string; attribute C_DEFAULT_DATA of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is "0"; attribute C_DISABLE_WARN_BHV_COLL : integer; attribute C_DISABLE_WARN_BHV_COLL of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 0; attribute C_DISABLE_WARN_BHV_RANGE : integer; attribute C_DISABLE_WARN_BHV_RANGE of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 0; attribute C_ELABORATION_DIR : string; attribute C_ELABORATION_DIR of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is "./"; attribute C_ENABLE_32BIT_ADDRESS : integer; attribute C_ENABLE_32BIT_ADDRESS of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 0; attribute C_EN_DEEPSLEEP_PIN : integer; attribute C_EN_DEEPSLEEP_PIN of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 0; attribute C_EN_ECC_PIPE : integer; attribute C_EN_ECC_PIPE of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 0; attribute C_EN_RDADDRA_CHG : integer; attribute C_EN_RDADDRA_CHG of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 0; attribute C_EN_RDADDRB_CHG : integer; attribute C_EN_RDADDRB_CHG of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 0; attribute C_EN_SAFETY_CKT : integer; attribute C_EN_SAFETY_CKT of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 0; attribute C_EN_SHUTDOWN_PIN : integer; attribute C_EN_SHUTDOWN_PIN of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 0; attribute C_EN_SLEEP_PIN : integer; attribute C_EN_SLEEP_PIN of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 0; attribute C_EST_POWER_SUMMARY : string; attribute C_EST_POWER_SUMMARY of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is "Estimated Power for IP : 2.7096 mW"; attribute C_FAMILY : string; attribute C_FAMILY of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is "artix7"; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 0; attribute C_HAS_ENA : integer; attribute C_HAS_ENA of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 1; attribute C_HAS_ENB : integer; attribute C_HAS_ENB of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 0; attribute C_HAS_INJECTERR : integer; attribute C_HAS_INJECTERR of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 0; attribute C_HAS_MEM_OUTPUT_REGS_A : integer; attribute C_HAS_MEM_OUTPUT_REGS_A of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 1; attribute C_HAS_MEM_OUTPUT_REGS_B : integer; attribute C_HAS_MEM_OUTPUT_REGS_B of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 0; attribute C_HAS_MUX_OUTPUT_REGS_A : integer; attribute C_HAS_MUX_OUTPUT_REGS_A of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 0; attribute C_HAS_MUX_OUTPUT_REGS_B : integer; attribute C_HAS_MUX_OUTPUT_REGS_B of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 0; attribute C_HAS_REGCEA : integer; attribute C_HAS_REGCEA of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 0; attribute C_HAS_REGCEB : integer; attribute C_HAS_REGCEB of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 0; attribute C_HAS_RSTA : integer; attribute C_HAS_RSTA of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 0; attribute C_HAS_RSTB : integer; attribute C_HAS_RSTB of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 0; attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; attribute C_HAS_SOFTECC_INPUT_REGS_A of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 0; attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; attribute C_HAS_SOFTECC_OUTPUT_REGS_B of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 0; attribute C_INITA_VAL : string; attribute C_INITA_VAL of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is "0"; attribute C_INITB_VAL : string; attribute C_INITB_VAL of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is "0"; attribute C_INIT_FILE : string; attribute C_INIT_FILE of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is "blk_mem_LUT.mem"; attribute C_INIT_FILE_NAME : string; attribute C_INIT_FILE_NAME of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is "blk_mem_LUT.mif"; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 0; attribute C_LOAD_INIT_FILE : integer; attribute C_LOAD_INIT_FILE of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 1; attribute C_MEM_TYPE : integer; attribute C_MEM_TYPE of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 3; attribute C_MUX_PIPELINE_STAGES : integer; attribute C_MUX_PIPELINE_STAGES of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 0; attribute C_PRIM_TYPE : integer; attribute C_PRIM_TYPE of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 1; attribute C_READ_DEPTH_A : integer; attribute C_READ_DEPTH_A of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 16; attribute C_READ_DEPTH_B : integer; attribute C_READ_DEPTH_B of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 16; attribute C_READ_WIDTH_A : integer; attribute C_READ_WIDTH_A of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 16; attribute C_READ_WIDTH_B : integer; attribute C_READ_WIDTH_B of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 16; attribute C_RSTRAM_A : integer; attribute C_RSTRAM_A of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 0; attribute C_RSTRAM_B : integer; attribute C_RSTRAM_B of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 0; attribute C_RST_PRIORITY_A : string; attribute C_RST_PRIORITY_A of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is "CE"; attribute C_RST_PRIORITY_B : string; attribute C_RST_PRIORITY_B of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is "CE"; attribute C_SIM_COLLISION_CHECK : string; attribute C_SIM_COLLISION_CHECK of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is "ALL"; attribute C_USE_BRAM_BLOCK : integer; attribute C_USE_BRAM_BLOCK of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 0; attribute C_USE_BYTE_WEA : integer; attribute C_USE_BYTE_WEA of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 0; attribute C_USE_BYTE_WEB : integer; attribute C_USE_BYTE_WEB of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 0; attribute C_USE_DEFAULT_DATA : integer; attribute C_USE_DEFAULT_DATA of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 0; attribute C_USE_ECC : integer; attribute C_USE_ECC of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 0; attribute C_USE_SOFTECC : integer; attribute C_USE_SOFTECC of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 0; attribute C_USE_URAM : integer; attribute C_USE_URAM of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 0; attribute C_WEA_WIDTH : integer; attribute C_WEA_WIDTH of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 1; attribute C_WEB_WIDTH : integer; attribute C_WEB_WIDTH of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 1; attribute C_WRITE_DEPTH_A : integer; attribute C_WRITE_DEPTH_A of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 16; attribute C_WRITE_DEPTH_B : integer; attribute C_WRITE_DEPTH_B of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 16; attribute C_WRITE_MODE_A : string; attribute C_WRITE_MODE_A of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is "WRITE_FIRST"; attribute C_WRITE_MODE_B : string; attribute C_WRITE_MODE_B of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is "WRITE_FIRST"; attribute C_WRITE_WIDTH_A : integer; attribute C_WRITE_WIDTH_A of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 16; attribute C_WRITE_WIDTH_B : integer; attribute C_WRITE_WIDTH_B of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is 16; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is "artix7"; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is "blk_mem_gen_v8_3_3"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of blk_mem_LUT_blk_mem_gen_v8_3_3 : entity is "yes"; end blk_mem_LUT_blk_mem_gen_v8_3_3; architecture STRUCTURE of blk_mem_LUT_blk_mem_gen_v8_3_3 is signal \<const0>\ : STD_LOGIC; begin dbiterr <= \<const0>\; doutb(15) <= \<const0>\; doutb(14) <= \<const0>\; doutb(13) <= \<const0>\; doutb(12) <= \<const0>\; doutb(11) <= \<const0>\; doutb(10) <= \<const0>\; doutb(9) <= \<const0>\; doutb(8) <= \<const0>\; doutb(7) <= \<const0>\; doutb(6) <= \<const0>\; doutb(5) <= \<const0>\; doutb(4) <= \<const0>\; doutb(3) <= \<const0>\; doutb(2) <= \<const0>\; doutb(1) <= \<const0>\; doutb(0) <= \<const0>\; rdaddrecc(3) <= \<const0>\; rdaddrecc(2) <= \<const0>\; rdaddrecc(1) <= \<const0>\; rdaddrecc(0) <= \<const0>\; rsta_busy <= \<const0>\; rstb_busy <= \<const0>\; s_axi_arready <= \<const0>\; s_axi_awready <= \<const0>\; s_axi_bid(3) <= \<const0>\; s_axi_bid(2) <= \<const0>\; s_axi_bid(1) <= \<const0>\; s_axi_bid(0) <= \<const0>\; s_axi_bresp(1) <= \<const0>\; s_axi_bresp(0) <= \<const0>\; s_axi_bvalid <= \<const0>\; s_axi_dbiterr <= \<const0>\; s_axi_rdaddrecc(3) <= \<const0>\; s_axi_rdaddrecc(2) <= \<const0>\; s_axi_rdaddrecc(1) <= \<const0>\; s_axi_rdaddrecc(0) <= \<const0>\; s_axi_rdata(15) <= \<const0>\; s_axi_rdata(14) <= \<const0>\; s_axi_rdata(13) <= \<const0>\; s_axi_rdata(12) <= \<const0>\; s_axi_rdata(11) <= \<const0>\; s_axi_rdata(10) <= \<const0>\; s_axi_rdata(9) <= \<const0>\; s_axi_rdata(8) <= \<const0>\; s_axi_rdata(7) <= \<const0>\; s_axi_rdata(6) <= \<const0>\; s_axi_rdata(5) <= \<const0>\; s_axi_rdata(4) <= \<const0>\; s_axi_rdata(3) <= \<const0>\; s_axi_rdata(2) <= \<const0>\; s_axi_rdata(1) <= \<const0>\; s_axi_rdata(0) <= \<const0>\; s_axi_rid(3) <= \<const0>\; s_axi_rid(2) <= \<const0>\; s_axi_rid(1) <= \<const0>\; s_axi_rid(0) <= \<const0>\; s_axi_rlast <= \<const0>\; s_axi_rresp(1) <= \<const0>\; s_axi_rresp(0) <= \<const0>\; s_axi_rvalid <= \<const0>\; s_axi_sbiterr <= \<const0>\; s_axi_wready <= \<const0>\; sbiterr <= \<const0>\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); inst_blk_mem_gen: entity work.blk_mem_LUT_blk_mem_gen_v8_3_3_synth port map ( addra(3 downto 0) => addra(3 downto 0), clka => clka, douta(15 downto 0) => douta(15 downto 0), ena => ena ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity blk_mem_LUT is port ( clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 3 downto 0 ); douta : out STD_LOGIC_VECTOR ( 15 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of blk_mem_LUT : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of blk_mem_LUT : entity is "blk_mem_LUT,blk_mem_gen_v8_3_3,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of blk_mem_LUT : entity is "yes"; attribute x_core_info : string; attribute x_core_info of blk_mem_LUT : entity is "blk_mem_gen_v8_3_3,Vivado 2016.2"; end blk_mem_LUT; architecture STRUCTURE of blk_mem_LUT is signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC; signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC; signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute C_ADDRA_WIDTH : integer; attribute C_ADDRA_WIDTH of U0 : label is 4; attribute C_ADDRB_WIDTH : integer; attribute C_ADDRB_WIDTH of U0 : label is 4; attribute C_ALGORITHM : integer; attribute C_ALGORITHM of U0 : label is 1; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of U0 : label is 4; attribute C_AXI_SLAVE_TYPE : integer; attribute C_AXI_SLAVE_TYPE of U0 : label is 0; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of U0 : label is 1; attribute C_BYTE_SIZE : integer; attribute C_BYTE_SIZE of U0 : label is 9; attribute C_COMMON_CLK : integer; attribute C_COMMON_CLK of U0 : label is 0; attribute C_COUNT_18K_BRAM : string; attribute C_COUNT_18K_BRAM of U0 : label is "1"; attribute C_COUNT_36K_BRAM : string; attribute C_COUNT_36K_BRAM of U0 : label is "0"; attribute C_CTRL_ECC_ALGO : string; attribute C_CTRL_ECC_ALGO of U0 : label is "NONE"; attribute C_DEFAULT_DATA : string; attribute C_DEFAULT_DATA of U0 : label is "0"; attribute C_DISABLE_WARN_BHV_COLL : integer; attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0; attribute C_DISABLE_WARN_BHV_RANGE : integer; attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0; attribute C_ELABORATION_DIR : string; attribute C_ELABORATION_DIR of U0 : label is "./"; attribute C_ENABLE_32BIT_ADDRESS : integer; attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0; attribute C_EN_DEEPSLEEP_PIN : integer; attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0; attribute C_EN_ECC_PIPE : integer; attribute C_EN_ECC_PIPE of U0 : label is 0; attribute C_EN_RDADDRA_CHG : integer; attribute C_EN_RDADDRA_CHG of U0 : label is 0; attribute C_EN_RDADDRB_CHG : integer; attribute C_EN_RDADDRB_CHG of U0 : label is 0; attribute C_EN_SAFETY_CKT : integer; attribute C_EN_SAFETY_CKT of U0 : label is 0; attribute C_EN_SHUTDOWN_PIN : integer; attribute C_EN_SHUTDOWN_PIN of U0 : label is 0; attribute C_EN_SLEEP_PIN : integer; attribute C_EN_SLEEP_PIN of U0 : label is 0; attribute C_EST_POWER_SUMMARY : string; attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 2.7096 mW"; attribute C_FAMILY : string; attribute C_FAMILY of U0 : label is "artix7"; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of U0 : label is 0; attribute C_HAS_ENA : integer; attribute C_HAS_ENA of U0 : label is 1; attribute C_HAS_ENB : integer; attribute C_HAS_ENB of U0 : label is 0; attribute C_HAS_INJECTERR : integer; attribute C_HAS_INJECTERR of U0 : label is 0; attribute C_HAS_MEM_OUTPUT_REGS_A : integer; attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1; attribute C_HAS_MEM_OUTPUT_REGS_B : integer; attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0; attribute C_HAS_MUX_OUTPUT_REGS_A : integer; attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0; attribute C_HAS_MUX_OUTPUT_REGS_B : integer; attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0; attribute C_HAS_REGCEA : integer; attribute C_HAS_REGCEA of U0 : label is 0; attribute C_HAS_REGCEB : integer; attribute C_HAS_REGCEB of U0 : label is 0; attribute C_HAS_RSTA : integer; attribute C_HAS_RSTA of U0 : label is 0; attribute C_HAS_RSTB : integer; attribute C_HAS_RSTB of U0 : label is 0; attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0; attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0; attribute C_INITA_VAL : string; attribute C_INITA_VAL of U0 : label is "0"; attribute C_INITB_VAL : string; attribute C_INITB_VAL of U0 : label is "0"; attribute C_INIT_FILE : string; attribute C_INIT_FILE of U0 : label is "blk_mem_LUT.mem"; attribute C_INIT_FILE_NAME : string; attribute C_INIT_FILE_NAME of U0 : label is "blk_mem_LUT.mif"; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of U0 : label is 0; attribute C_LOAD_INIT_FILE : integer; attribute C_LOAD_INIT_FILE of U0 : label is 1; attribute C_MEM_TYPE : integer; attribute C_MEM_TYPE of U0 : label is 3; attribute C_MUX_PIPELINE_STAGES : integer; attribute C_MUX_PIPELINE_STAGES of U0 : label is 0; attribute C_PRIM_TYPE : integer; attribute C_PRIM_TYPE of U0 : label is 1; attribute C_READ_DEPTH_A : integer; attribute C_READ_DEPTH_A of U0 : label is 16; attribute C_READ_DEPTH_B : integer; attribute C_READ_DEPTH_B of U0 : label is 16; attribute C_READ_WIDTH_A : integer; attribute C_READ_WIDTH_A of U0 : label is 16; attribute C_READ_WIDTH_B : integer; attribute C_READ_WIDTH_B of U0 : label is 16; attribute C_RSTRAM_A : integer; attribute C_RSTRAM_A of U0 : label is 0; attribute C_RSTRAM_B : integer; attribute C_RSTRAM_B of U0 : label is 0; attribute C_RST_PRIORITY_A : string; attribute C_RST_PRIORITY_A of U0 : label is "CE"; attribute C_RST_PRIORITY_B : string; attribute C_RST_PRIORITY_B of U0 : label is "CE"; attribute C_SIM_COLLISION_CHECK : string; attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL"; attribute C_USE_BRAM_BLOCK : integer; attribute C_USE_BRAM_BLOCK of U0 : label is 0; attribute C_USE_BYTE_WEA : integer; attribute C_USE_BYTE_WEA of U0 : label is 0; attribute C_USE_BYTE_WEB : integer; attribute C_USE_BYTE_WEB of U0 : label is 0; attribute C_USE_DEFAULT_DATA : integer; attribute C_USE_DEFAULT_DATA of U0 : label is 0; attribute C_USE_ECC : integer; attribute C_USE_ECC of U0 : label is 0; attribute C_USE_SOFTECC : integer; attribute C_USE_SOFTECC of U0 : label is 0; attribute C_USE_URAM : integer; attribute C_USE_URAM of U0 : label is 0; attribute C_WEA_WIDTH : integer; attribute C_WEA_WIDTH of U0 : label is 1; attribute C_WEB_WIDTH : integer; attribute C_WEB_WIDTH of U0 : label is 1; attribute C_WRITE_DEPTH_A : integer; attribute C_WRITE_DEPTH_A of U0 : label is 16; attribute C_WRITE_DEPTH_B : integer; attribute C_WRITE_DEPTH_B of U0 : label is 16; attribute C_WRITE_MODE_A : string; attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST"; attribute C_WRITE_MODE_B : string; attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST"; attribute C_WRITE_WIDTH_A : integer; attribute C_WRITE_WIDTH_A of U0 : label is 16; attribute C_WRITE_WIDTH_B : integer; attribute C_WRITE_WIDTH_B of U0 : label is 16; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of U0 : label is "artix7"; attribute KEEP_HIERARCHY : string; attribute KEEP_HIERARCHY of U0 : label is "true"; attribute downgradeipidentifiedwarnings of U0 : label is "yes"; begin U0: entity work.blk_mem_LUT_blk_mem_gen_v8_3_3 port map ( addra(3 downto 0) => addra(3 downto 0), addrb(3 downto 0) => B"0000", clka => clka, clkb => '0', dbiterr => NLW_U0_dbiterr_UNCONNECTED, deepsleep => '0', dina(15 downto 0) => B"0000000000000000", dinb(15 downto 0) => B"0000000000000000", douta(15 downto 0) => douta(15 downto 0), doutb(15 downto 0) => NLW_U0_doutb_UNCONNECTED(15 downto 0), eccpipece => '0', ena => ena, enb => '0', injectdbiterr => '0', injectsbiterr => '0', rdaddrecc(3 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(3 downto 0), regcea => '0', regceb => '0', rsta => '0', rsta_busy => NLW_U0_rsta_busy_UNCONNECTED, rstb => '0', rstb_busy => NLW_U0_rstb_busy_UNCONNECTED, s_aclk => '0', s_aresetn => '0', s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_arburst(1 downto 0) => B"00", s_axi_arid(3 downto 0) => B"0000", s_axi_arlen(7 downto 0) => B"00000000", s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED, s_axi_arsize(2 downto 0) => B"000", s_axi_arvalid => '0', s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_awburst(1 downto 0) => B"00", s_axi_awid(3 downto 0) => B"0000", s_axi_awlen(7 downto 0) => B"00000000", s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED, s_axi_awsize(2 downto 0) => B"000", s_axi_awvalid => '0', s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0), s_axi_bready => '0', s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0), s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED, s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED, s_axi_injectdbiterr => '0', s_axi_injectsbiterr => '0', s_axi_rdaddrecc(3 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(3 downto 0), s_axi_rdata(15 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(15 downto 0), s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0), s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED, s_axi_rready => '0', s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0), s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED, s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED, s_axi_wdata(15 downto 0) => B"0000000000000000", s_axi_wlast => '0', s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED, s_axi_wstrb(0) => '0', s_axi_wvalid => '0', sbiterr => NLW_U0_sbiterr_UNCONNECTED, shutdown => '0', sleep => '0', wea(0) => '0', web(0) => '0' ); end STRUCTURE;
gpl-3.0
477240f445fcf4f3abfcdb667f90ff31
0.685186
3.184087
false
false
false
false
TUM-LIS/faultify
software/host/davester_combinational_extractor/voltage_scaling_fpu_mul/tb_fpu_syn.vhd
1
12,093
--Package declaration for the above program library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; package test_pkg is function reverse_any_vector (a : in std_logic_vector) return std_logic_vector; end test_pkg; --end of package. package body test_pkg is --start of package body --definition of function function reverse_any_vector (a : in std_logic_vector) return std_logic_vector is variable result : std_logic_vector(a'range); alias aa : std_logic_vector(a'reverse_range) is a; begin for i in aa'range loop result(i) := aa(i); end loop; return result; end; -- function reverse_any_vector --end function end test_pkg; --end of the package body ------------------------------------------------------------------------------- -- -- Project: <Floating Point Unit Core> -- -- Description: test bench for the FPU core ------------------------------------------------------------------------------- -- -- 100101011010011100100 -- 110000111011100100000 -- 100000111011000101101 -- 100010111100101111001 -- 110000111011101101001 -- 010000001011101001010 -- 110100111001001100001 -- 110111010000001100111 -- 110110111110001011101 -- 101110110010111101000 -- 100000010111000000000 -- -- Author: Jidan Al-eryani -- E-mail: [email protected] -- -- Copyright (C) 2006 -- -- This source file may be used and distributed without -- restriction provided that this copyright statement is not -- removed from the file and that any derivative work contains -- the original copyright notice and the associated disclaimer. -- -- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR -- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.math_real.all; use ieee.std_logic_arith.all; use ieee.std_logic_misc.all; use std.textio.all; use work.txt_util.all; use work.test_pkg.all; -- fpu operations (fpu_op_i): -- ======================== -- 000 = add, -- 001 = substract, -- 010 = multiply, -- 011 = divide, -- 100 = square root -- 101 = unused -- 110 = unused -- 111 = unused -- Rounding Mode: -- ============== -- 00 = round to nearest even(default), -- 01 = round to zero, -- 10 = round up, -- 11 = round down entity tb_fpu is end tb_fpu; architecture rtl of tb_fpu is --component fpu -- port ( -- CLK0I : in std_logic; -- opa0i : in std_logic_vector(31 downto 0); -- opb0i : in std_logic_vector(31 downto 0); -- fpu0op0i : in std_logic_vector(2 downto 0); -- rmode0i : in std_logic_vector(1 downto 0); -- output0o : out std_logic_vector(31 downto 0); -- ine0o : out std_logic; -- overflow0o : out std_logic; -- underflow0o : out std_logic; -- div0zero0o : out std_logic; -- inf0o : out std_logic; -- zero0o : out std_logic; -- qnan0o : out std_logic; -- snan0o : out std_logic; -- start0i : in std_logic; -- ready0o : out std_logic -- ); --end component; component cut_wrapper_static_all port( clk : in std_logic; testVector : in std_logic_vector(69 downto 0); resultVector : out std_logic_vector(40 downto 0) ); end component; signal testVector : std_logic_vector(69 downto 0); signal resultVector : std_logic_vector(40 downto 0); signal clk_i : std_logic := '1'; signal opa_i, opb_i : std_logic_vector(31 downto 0); signal fpu_op_i : std_logic_vector(2 downto 0); signal rmode_i : std_logic_vector(1 downto 0); signal output_o : std_logic_vector(31 downto 0); signal start_i, ready_o : std_logic; signal ine_o, overflow_o, underflow_o, div_zero_o, inf_o, zero_o, qnan_o, snan_o : std_logic; signal slv_out : std_logic_vector(31 downto 0); constant CLK_PERIOD : time := 10 ns; -- period of clk period begin circuit_under_test_1 : cut_wrapper_static_all port map ( clk => clk_i, testVector => testVector, resultVector => resultVector ); testVector(31 downto 0) <= opa_i; testVector(63 downto 32) <= opb_i; testVector(66 downto 64) <= fpu_op_i; testVector(68 downto 67) <= rmode_i; output_o <= resultVector(31 downto 0); testVector(69) <= start_i; ready_o <= resultVector(32); ine_o <= resultVector(33); overflow_o <= resultVector(34); underflow_o <= resultVector(35); div_zero_o <= resultVector(36); inf_o <= resultVector(37); zero_o <= resultVector(38); qnan_o <= resultVector(39); snan_o <= resultVector(40); -- instantiate fpu --i_fpu: fpu port map ( -- CLK0I => clk_i, -- opa0i => opa_i, -- opb0i => opb_i, -- fpu0op0i => fpu_op_i, -- rmode0i => rmode_i, -- output0o => output_o, -- ine0o => ine_o, -- overflow0o => overflow_o, -- underflow0o => underflow_o, -- div0zero0o => div_zero_o, -- inf0o => inf_o, -- zero0o => zero_o, -- qnan0o => qnan_o, -- snan0o => snan_o, -- start0i => start_i, -- ready0o => ready_o); --------------------------------------------------------------------------- -- toggle clock --------------------------------------------------------------------------- clk_i <= not(clk_i) after 10 ns; verify : process --The operands and results are in Hex format. The test vectors must be placed in a strict order for the verfication to work. file testcases_file : text open read_mode is "testcases_mul.txt"; --Name of the file containing the test cases. variable file_line : line; variable str_in : string(8 downto 1); variable str_fpu_op : string(3 downto 1); variable str_rmode : string(2 downto 1); begin --------------------------------------------------------------------------------------------------------------------------------------------------- ---------------------------------------------------SoftFloat test vectors (10000 test cases for each operation) -------------------------------------------------------------------- start_i <= '0'; wait for 20*CLK_PERIOD; while not endfile(testcases_file) loop wait for CLK_PERIOD; start_i <= '1'; str_read(testcases_file, str_in); opa_i <= strhex_to_slv(str_in); str_read(testcases_file, str_in); opb_i <= strhex_to_slv(str_in); str_read(testcases_file, str_fpu_op); fpu_op_i <= to_std_logic_vector(str_fpu_op); str_read(testcases_file, str_rmode); rmode_i <= to_std_logic_vector(str_rmode); str_read(testcases_file, str_in); slv_out <= strhex_to_slv(str_in); wait for CLK_PERIOD; start_i <= '0'; wait until ready_o = '1'; --assert output_o = slv_out -- report "Error!!!" -- severity failure; str_read(testcases_file, str_in); end loop; -------- Boundary values----- start_i <= '0'; -- seeeeeeeefffffffffffffffffffffff --infinity wait for CLK_PERIOD; start_i <= '1'; opa_i <= "01111111011111111111111111111111"; opb_i <= "01111111011111111111111111111111"; fpu_op_i <= "000"; rmode_i <= "00"; wait for CLK_PERIOD; start_i <= '0'; wait until ready_o = '1'; assert output_o = "01111111100000000000000000000000" report "Error!!!" severity warning; -- seeeeeeeefffffffffffffffffffffff -- 1 x1.001 - 1x1.000 = 0x0.001 wait for CLK_PERIOD; start_i <= '1'; opa_i <= "00000000100100000000000000000000"; opb_i <= "10000000100000000000000000000000"; fpu_op_i <= "000"; rmode_i <= "00"; wait for CLK_PERIOD; start_i <= '0'; wait until ready_o = '1'; --assert output_o = "00000000000100000000000000000000" -- report "Error!!!" -- severity failure; -- seeeeeeeefffffffffffffffffffffff -- 10 x 1.0001 - 10 x 1.0000 = wait for CLK_PERIOD; start_i <= '1'; opa_i <= "00000001000010000000000000000000"; opb_i <= "10000001000000000000000000000000"; fpu_op_i <= "000"; rmode_i <= "00"; wait for CLK_PERIOD; start_i <= '0'; wait until ready_o = '1'; --assert output_o = "00000000000100000000000000000000" -- report "Error!!!" -- severity failure; -- seeeeeeeefffffffffffffffffffffff -- -0 -0 = -0 wait for CLK_PERIOD; start_i <= '1'; opa_i <= "10000000000000000000000000000000"; opb_i <= "10000000000000000000000000000000"; fpu_op_i <= "000"; rmode_i <= "00"; wait for CLK_PERIOD; start_i <= '0'; wait until ready_o = '1'; --assert output_o = "10000000000000000000000000000000" -- report "Error!!!" -- severity failure; -- seeeeeeeefffffffffffffffffffffff -- 0 + x = x wait for CLK_PERIOD; start_i <= '1'; opa_i <= "00000000000000000000000000000000"; opb_i <= "01000010001000001000000000100000"; fpu_op_i <= "000"; rmode_i <= "00"; wait for CLK_PERIOD; start_i <= '0'; wait until ready_o = '1'; --assert output_o = "01000010001000001000000000100000" -- report "Error!!!" -- severity failure; ---------------------------------------------------------------------------------------------------------------------------------------------------- assert false report "Success!!!.......Yahoooooooooooooo" severity failure; wait; end process verify; end rtl;
gpl-2.0
192016dca48011e0ffdb7039d4d2a5c5
0.481436
4.360981
false
true
false
false
SoCdesign/EHA
RTL/Fault_Management/Fault_management_network/LBDR_LV.vhd
1
3,383
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.ALL; entity LBDR_LV is generic ( cur_addr_rst: integer := 8; Rxy_rst: integer := 8; Cx_rst: integer := 8; NoC_size: integer := 4 ); port ( reset: in std_logic; clk: in std_logic; empty: in std_logic; dst_addr: in std_logic_vector(NoC_size-1 downto 0); packet_info: in std_logic; flit_type: in std_logic_vector(2 downto 0); grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic; Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic ); end LBDR_LV; architecture behavior of LBDR_LV is signal Cx: std_logic_vector(3 downto 0); signal Rxy: std_logic_vector(7 downto 0); signal cur_addr: std_logic_vector(NoC_size-1 downto 0); signal N1, E1, W1, S1 :std_logic :='0'; signal Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: std_logic; signal Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: std_logic; signal grants: std_logic; begin grants <= grant_N or grant_E or grant_W or grant_S or grant_L; Cx <= std_logic_vector(to_unsigned(Cx_rst, Cx'length)); Rxy <= std_logic_vector(to_unsigned(Rxy_rst, Rxy'length)); cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length)); N1 <= '1' when dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) else '0'; E1 <= '1' when cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) else '0'; W1 <= '1' when dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) else '0'; S1 <= '1' when cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) else '0'; process(clk, reset) begin if reset = '0' then Req_N_FF <= '0'; Req_E_FF <= '0'; Req_W_FF <= '0'; Req_S_FF <= '0'; Req_L_FF <= '0'; elsif clk'event and clk = '1' then Req_N_FF <= Req_N_in; Req_E_FF <= Req_E_in; Req_W_FF <= Req_W_in; Req_S_FF <= Req_S_in; Req_L_FF <= Req_L_in; end if; end process; -- The combionational part Req_N <= Req_N_FF; Req_E <= Req_E_FF; Req_W <= Req_W_FF; Req_S <= Req_S_FF; Req_L <= Req_L_FF; process(N1, E1, W1, S1, Rxy, Cx, empty, Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF, grants) begin if flit_type = "001" and empty = '0' then Req_N_in <= ((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0); Req_E_in <= ((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1); Req_W_in <= ((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2); Req_S_in <= ((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3); Req_L_in <= not N1 and not E1 and not W1 and not S1; elsif ( flit_type = "100" and empty = '0' and grants = '1') then Req_N_in <= '0'; Req_E_in <= '0'; Req_W_in <= '0'; Req_S_in <= '0'; Req_L_in <= '0'; else Req_N_in <= Req_N_FF; Req_E_in <= Req_E_FF; Req_W_in <= Req_W_FF; Req_S_in <= Req_S_FF; Req_L_in <= Req_L_FF; end if; end process; END;
gpl-3.0
2bde79a80edc037995aaf529a8583da9
0.572864
2.513373
false
false
false
false
TonyBrewer/OpenHT
tests/userio_vadd_prbs_test/scripts/aurora_64b66b_25p4G/ip_1/synth/aurora_64b66b_25p4G_fifo_gen_master.vhd
1
39,836
-- (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:fifo_generator:13.2 -- IP Revision: 0 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY fifo_generator_v13_2_0; USE fifo_generator_v13_2_0.fifo_generator_v13_2_0; ENTITY aurora_64b66b_25p4G_fifo_gen_master IS PORT ( srst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; rd_clk : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(71 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(71 DOWNTO 0); full : OUT STD_LOGIC; overflow : OUT STD_LOGIC; empty : OUT STD_LOGIC; underflow : OUT STD_LOGIC; prog_full : OUT STD_LOGIC; prog_empty : OUT STD_LOGIC; wr_rst_busy : OUT STD_LOGIC; rd_rst_busy : OUT STD_LOGIC ); END aurora_64b66b_25p4G_fifo_gen_master; ARCHITECTURE aurora_64b66b_25p4G_fifo_gen_master_arch OF aurora_64b66b_25p4G_fifo_gen_master IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF aurora_64b66b_25p4G_fifo_gen_master_arch: ARCHITECTURE IS "yes"; COMPONENT fifo_generator_v13_2_0 IS GENERIC ( C_COMMON_CLOCK : INTEGER; C_SELECT_XPM : INTEGER; C_COUNT_TYPE : INTEGER; C_DATA_COUNT_WIDTH : INTEGER; C_DEFAULT_VALUE : STRING; C_DIN_WIDTH : INTEGER; C_DOUT_RST_VAL : STRING; C_DOUT_WIDTH : INTEGER; C_ENABLE_RLOCS : INTEGER; C_FAMILY : STRING; C_FULL_FLAGS_RST_VAL : INTEGER; C_HAS_ALMOST_EMPTY : INTEGER; C_HAS_ALMOST_FULL : INTEGER; C_HAS_BACKUP : INTEGER; C_HAS_DATA_COUNT : INTEGER; C_HAS_INT_CLK : INTEGER; C_HAS_MEMINIT_FILE : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_RD_DATA_COUNT : INTEGER; C_HAS_RD_RST : INTEGER; C_HAS_RST : INTEGER; C_HAS_SRST : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_VALID : INTEGER; C_HAS_WR_ACK : INTEGER; C_HAS_WR_DATA_COUNT : INTEGER; C_HAS_WR_RST : INTEGER; C_IMPLEMENTATION_TYPE : INTEGER; C_INIT_WR_PNTR_VAL : INTEGER; C_MEMORY_TYPE : INTEGER; C_MIF_FILE_NAME : STRING; C_OPTIMIZATION_MODE : INTEGER; C_OVERFLOW_LOW : INTEGER; C_PRELOAD_LATENCY : INTEGER; C_PRELOAD_REGS : INTEGER; C_PRIM_FIFO_TYPE : STRING; C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER; C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER; C_PROG_EMPTY_TYPE : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER; C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER; C_PROG_FULL_TYPE : INTEGER; C_RD_DATA_COUNT_WIDTH : INTEGER; C_RD_DEPTH : INTEGER; C_RD_FREQ : INTEGER; C_RD_PNTR_WIDTH : INTEGER; C_UNDERFLOW_LOW : INTEGER; C_USE_DOUT_RST : INTEGER; C_USE_ECC : INTEGER; C_USE_EMBEDDED_REG : INTEGER; C_USE_PIPELINE_REG : INTEGER; C_POWER_SAVING_MODE : INTEGER; C_USE_FIFO16_FLAGS : INTEGER; C_USE_FWFT_DATA_COUNT : INTEGER; C_VALID_LOW : INTEGER; C_WR_ACK_LOW : INTEGER; C_WR_DATA_COUNT_WIDTH : INTEGER; C_WR_DEPTH : INTEGER; C_WR_FREQ : INTEGER; C_WR_PNTR_WIDTH : INTEGER; C_WR_RESPONSE_LATENCY : INTEGER; C_MSGON_VAL : INTEGER; C_ENABLE_RST_SYNC : INTEGER; C_EN_SAFETY_CKT : INTEGER; C_ERROR_INJECTION_TYPE : INTEGER; C_SYNCHRONIZER_STAGE : INTEGER; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_HAS_AXI_WR_CHANNEL : INTEGER; C_HAS_AXI_RD_CHANNEL : INTEGER; C_HAS_SLAVE_CE : INTEGER; C_HAS_MASTER_CE : INTEGER; C_ADD_NGC_CONSTRAINT : INTEGER; C_USE_COMMON_OVERFLOW : INTEGER; C_USE_COMMON_UNDERFLOW : INTEGER; C_USE_DEFAULT_SETTINGS : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_AXI_ADDR_WIDTH : INTEGER; C_AXI_DATA_WIDTH : INTEGER; C_AXI_LEN_WIDTH : INTEGER; C_AXI_LOCK_WIDTH : INTEGER; C_HAS_AXI_ID : INTEGER; C_HAS_AXI_AWUSER : INTEGER; C_HAS_AXI_WUSER : INTEGER; C_HAS_AXI_BUSER : INTEGER; C_HAS_AXI_ARUSER : INTEGER; C_HAS_AXI_RUSER : INTEGER; C_AXI_ARUSER_WIDTH : INTEGER; C_AXI_AWUSER_WIDTH : INTEGER; C_AXI_WUSER_WIDTH : INTEGER; C_AXI_BUSER_WIDTH : INTEGER; C_AXI_RUSER_WIDTH : INTEGER; C_HAS_AXIS_TDATA : INTEGER; C_HAS_AXIS_TID : INTEGER; C_HAS_AXIS_TDEST : INTEGER; C_HAS_AXIS_TUSER : INTEGER; C_HAS_AXIS_TREADY : INTEGER; C_HAS_AXIS_TLAST : INTEGER; C_HAS_AXIS_TSTRB : INTEGER; C_HAS_AXIS_TKEEP : INTEGER; C_AXIS_TDATA_WIDTH : INTEGER; C_AXIS_TID_WIDTH : INTEGER; C_AXIS_TDEST_WIDTH : INTEGER; C_AXIS_TUSER_WIDTH : INTEGER; C_AXIS_TSTRB_WIDTH : INTEGER; C_AXIS_TKEEP_WIDTH : INTEGER; C_WACH_TYPE : INTEGER; C_WDCH_TYPE : INTEGER; C_WRCH_TYPE : INTEGER; C_RACH_TYPE : INTEGER; C_RDCH_TYPE : INTEGER; C_AXIS_TYPE : INTEGER; C_IMPLEMENTATION_TYPE_WACH : INTEGER; C_IMPLEMENTATION_TYPE_WDCH : INTEGER; C_IMPLEMENTATION_TYPE_WRCH : INTEGER; C_IMPLEMENTATION_TYPE_RACH : INTEGER; C_IMPLEMENTATION_TYPE_RDCH : INTEGER; C_IMPLEMENTATION_TYPE_AXIS : INTEGER; C_APPLICATION_TYPE_WACH : INTEGER; C_APPLICATION_TYPE_WDCH : INTEGER; C_APPLICATION_TYPE_WRCH : INTEGER; C_APPLICATION_TYPE_RACH : INTEGER; C_APPLICATION_TYPE_RDCH : INTEGER; C_APPLICATION_TYPE_AXIS : INTEGER; C_PRIM_FIFO_TYPE_WACH : STRING; C_PRIM_FIFO_TYPE_WDCH : STRING; C_PRIM_FIFO_TYPE_WRCH : STRING; C_PRIM_FIFO_TYPE_RACH : STRING; C_PRIM_FIFO_TYPE_RDCH : STRING; C_PRIM_FIFO_TYPE_AXIS : STRING; C_USE_ECC_WACH : INTEGER; C_USE_ECC_WDCH : INTEGER; C_USE_ECC_WRCH : INTEGER; C_USE_ECC_RACH : INTEGER; C_USE_ECC_RDCH : INTEGER; C_USE_ECC_AXIS : INTEGER; C_ERROR_INJECTION_TYPE_WACH : INTEGER; C_ERROR_INJECTION_TYPE_WDCH : INTEGER; C_ERROR_INJECTION_TYPE_WRCH : INTEGER; C_ERROR_INJECTION_TYPE_RACH : INTEGER; C_ERROR_INJECTION_TYPE_RDCH : INTEGER; C_ERROR_INJECTION_TYPE_AXIS : INTEGER; C_DIN_WIDTH_WACH : INTEGER; C_DIN_WIDTH_WDCH : INTEGER; C_DIN_WIDTH_WRCH : INTEGER; C_DIN_WIDTH_RACH : INTEGER; C_DIN_WIDTH_RDCH : INTEGER; C_DIN_WIDTH_AXIS : INTEGER; C_WR_DEPTH_WACH : INTEGER; C_WR_DEPTH_WDCH : INTEGER; C_WR_DEPTH_WRCH : INTEGER; C_WR_DEPTH_RACH : INTEGER; C_WR_DEPTH_RDCH : INTEGER; C_WR_DEPTH_AXIS : INTEGER; C_WR_PNTR_WIDTH_WACH : INTEGER; C_WR_PNTR_WIDTH_WDCH : INTEGER; C_WR_PNTR_WIDTH_WRCH : INTEGER; C_WR_PNTR_WIDTH_RACH : INTEGER; C_WR_PNTR_WIDTH_RDCH : INTEGER; C_WR_PNTR_WIDTH_AXIS : INTEGER; C_HAS_DATA_COUNTS_WACH : INTEGER; C_HAS_DATA_COUNTS_WDCH : INTEGER; C_HAS_DATA_COUNTS_WRCH : INTEGER; C_HAS_DATA_COUNTS_RACH : INTEGER; C_HAS_DATA_COUNTS_RDCH : INTEGER; C_HAS_DATA_COUNTS_AXIS : INTEGER; C_HAS_PROG_FLAGS_WACH : INTEGER; C_HAS_PROG_FLAGS_WDCH : INTEGER; C_HAS_PROG_FLAGS_WRCH : INTEGER; C_HAS_PROG_FLAGS_RACH : INTEGER; C_HAS_PROG_FLAGS_RDCH : INTEGER; C_HAS_PROG_FLAGS_AXIS : INTEGER; C_PROG_FULL_TYPE_WACH : INTEGER; C_PROG_FULL_TYPE_WDCH : INTEGER; C_PROG_FULL_TYPE_WRCH : INTEGER; C_PROG_FULL_TYPE_RACH : INTEGER; C_PROG_FULL_TYPE_RDCH : INTEGER; C_PROG_FULL_TYPE_AXIS : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER; C_PROG_EMPTY_TYPE_WACH : INTEGER; C_PROG_EMPTY_TYPE_WDCH : INTEGER; C_PROG_EMPTY_TYPE_WRCH : INTEGER; C_PROG_EMPTY_TYPE_RACH : INTEGER; C_PROG_EMPTY_TYPE_RDCH : INTEGER; C_PROG_EMPTY_TYPE_AXIS : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER; C_REG_SLICE_MODE_WACH : INTEGER; C_REG_SLICE_MODE_WDCH : INTEGER; C_REG_SLICE_MODE_WRCH : INTEGER; C_REG_SLICE_MODE_RACH : INTEGER; C_REG_SLICE_MODE_RDCH : INTEGER; C_REG_SLICE_MODE_AXIS : INTEGER ); PORT ( backup : IN STD_LOGIC; backup_marker : IN STD_LOGIC; clk : IN STD_LOGIC; rst : IN STD_LOGIC; srst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; wr_rst : IN STD_LOGIC; rd_clk : IN STD_LOGIC; rd_rst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(71 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; prog_empty_thresh : IN STD_LOGIC_VECTOR(8 DOWNTO 0); prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(8 DOWNTO 0); prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(8 DOWNTO 0); prog_full_thresh : IN STD_LOGIC_VECTOR(8 DOWNTO 0); prog_full_thresh_assert : IN STD_LOGIC_VECTOR(8 DOWNTO 0); prog_full_thresh_negate : IN STD_LOGIC_VECTOR(8 DOWNTO 0); int_clk : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; injectsbiterr : IN STD_LOGIC; sleep : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(71 DOWNTO 0); full : OUT STD_LOGIC; almost_full : OUT STD_LOGIC; wr_ack : OUT STD_LOGIC; overflow : OUT STD_LOGIC; empty : OUT STD_LOGIC; almost_empty : OUT STD_LOGIC; valid : OUT STD_LOGIC; underflow : OUT STD_LOGIC; data_count : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); rd_data_count : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); wr_data_count : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); prog_full : OUT STD_LOGIC; prog_empty : OUT STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; wr_rst_busy : OUT STD_LOGIC; rd_rst_busy : OUT STD_LOGIC; m_aclk : IN STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; m_aclk_en : IN STD_LOGIC; s_aclk_en : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awvalid : OUT STD_LOGIC; m_axi_awready : IN STD_LOGIC; m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_wlast : OUT STD_LOGIC; m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wvalid : OUT STD_LOGIC; m_axi_wready : IN STD_LOGIC; m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bvalid : IN STD_LOGIC; m_axi_bready : OUT STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arvalid : OUT STD_LOGIC; m_axi_arready : IN STD_LOGIC; m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_rlast : IN STD_LOGIC; m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rvalid : IN STD_LOGIC; m_axi_rready : OUT STD_LOGIC; s_axis_tvalid : IN STD_LOGIC; s_axis_tready : OUT STD_LOGIC; s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tlast : IN STD_LOGIC; s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0); m_axis_tvalid : OUT STD_LOGIC; m_axis_tready : IN STD_LOGIC; m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tlast : OUT STD_LOGIC; m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_injectsbiterr : IN STD_LOGIC; axi_aw_injectdbiterr : IN STD_LOGIC; axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_sbiterr : OUT STD_LOGIC; axi_aw_dbiterr : OUT STD_LOGIC; axi_aw_overflow : OUT STD_LOGIC; axi_aw_underflow : OUT STD_LOGIC; axi_aw_prog_full : OUT STD_LOGIC; axi_aw_prog_empty : OUT STD_LOGIC; axi_w_injectsbiterr : IN STD_LOGIC; axi_w_injectdbiterr : IN STD_LOGIC; axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_sbiterr : OUT STD_LOGIC; axi_w_dbiterr : OUT STD_LOGIC; axi_w_overflow : OUT STD_LOGIC; axi_w_underflow : OUT STD_LOGIC; axi_w_prog_full : OUT STD_LOGIC; axi_w_prog_empty : OUT STD_LOGIC; axi_b_injectsbiterr : IN STD_LOGIC; axi_b_injectdbiterr : IN STD_LOGIC; axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_sbiterr : OUT STD_LOGIC; axi_b_dbiterr : OUT STD_LOGIC; axi_b_overflow : OUT STD_LOGIC; axi_b_underflow : OUT STD_LOGIC; axi_b_prog_full : OUT STD_LOGIC; axi_b_prog_empty : OUT STD_LOGIC; axi_ar_injectsbiterr : IN STD_LOGIC; axi_ar_injectdbiterr : IN STD_LOGIC; axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_sbiterr : OUT STD_LOGIC; axi_ar_dbiterr : OUT STD_LOGIC; axi_ar_overflow : OUT STD_LOGIC; axi_ar_underflow : OUT STD_LOGIC; axi_ar_prog_full : OUT STD_LOGIC; axi_ar_prog_empty : OUT STD_LOGIC; axi_r_injectsbiterr : IN STD_LOGIC; axi_r_injectdbiterr : IN STD_LOGIC; axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_sbiterr : OUT STD_LOGIC; axi_r_dbiterr : OUT STD_LOGIC; axi_r_overflow : OUT STD_LOGIC; axi_r_underflow : OUT STD_LOGIC; axi_r_prog_full : OUT STD_LOGIC; axi_r_prog_empty : OUT STD_LOGIC; axis_injectsbiterr : IN STD_LOGIC; axis_injectdbiterr : IN STD_LOGIC; axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_sbiterr : OUT STD_LOGIC; axis_dbiterr : OUT STD_LOGIC; axis_overflow : OUT STD_LOGIC; axis_underflow : OUT STD_LOGIC; axis_prog_full : OUT STD_LOGIC; axis_prog_empty : OUT STD_LOGIC ); END COMPONENT fifo_generator_v13_2_0; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF aurora_64b66b_25p4G_fifo_gen_master_arch: ARCHITECTURE IS "fifo_generator_v13_2_0,Vivado 2017.3.1"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF aurora_64b66b_25p4G_fifo_gen_master_arch : ARCHITECTURE IS "aurora_64b66b_25p4G_fifo_gen_master,fifo_generator_v13_2_0,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF aurora_64b66b_25p4G_fifo_gen_master_arch: ARCHITECTURE IS "aurora_64b66b_25p4G_fifo_gen_master,fifo_generator_v13_2_0,{x_ipProduct=Vivado 2017.3.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.2,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=VERILOG,C_COMMON_CLOCK=0,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=9,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=72,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=72,C_ENABLE_RLOCS=0,C_FAMILY=virtexuplus,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DAT" & "A_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=1,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=1,C_HAS_UNDERFLOW=1,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=6,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=4,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=2,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=8,C_PROG_EMPTY_THRESH_NEGATE_VAL=9,C_PROG_EMPTY_TYPE=1,C_PROG_FULL_THR" & "ESH_ASSERT_VAL=450,C_PROG_FULL_THRESH_NEGATE_VAL=449,C_PROG_FULL_TYPE=1,C_RD_DATA_COUNT_WIDTH=9,C_RD_DEPTH=512,C_RD_FREQ=1,C_RD_PNTR_WIDTH=9,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=1,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=9,C_WR_DEPTH=512,C_WR_FREQ=1,C_WR_PNTR_WIDTH=9,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SY" & "NCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BU" & "SER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_" & "RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=512x72,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=512x72,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ER" & "ROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=1,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_R" & "ACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_F" & "ULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=" & "1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_PARAMETER : STRING; ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY"; ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL"; ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA"; ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN"; ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN"; ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA"; ATTRIBUTE X_INTERFACE_PARAMETER OF rd_clk: SIGNAL IS "XIL_INTERFACENAME read_clk, FREQ_HZ 1000000, PHASE 0.000"; ATTRIBUTE X_INTERFACE_INFO OF rd_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 read_clk CLK"; ATTRIBUTE X_INTERFACE_PARAMETER OF wr_clk: SIGNAL IS "XIL_INTERFACENAME write_clk, FREQ_HZ 1000000, PHASE 0.000"; ATTRIBUTE X_INTERFACE_INFO OF wr_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 write_clk CLK"; BEGIN U0 : fifo_generator_v13_2_0 GENERIC MAP ( C_COMMON_CLOCK => 0, C_SELECT_XPM => 0, C_COUNT_TYPE => 0, C_DATA_COUNT_WIDTH => 9, C_DEFAULT_VALUE => "BlankString", C_DIN_WIDTH => 72, C_DOUT_RST_VAL => "0", C_DOUT_WIDTH => 72, C_ENABLE_RLOCS => 0, C_FAMILY => "virtexuplus", C_FULL_FLAGS_RST_VAL => 0, C_HAS_ALMOST_EMPTY => 0, C_HAS_ALMOST_FULL => 0, C_HAS_BACKUP => 0, C_HAS_DATA_COUNT => 0, C_HAS_INT_CLK => 0, C_HAS_MEMINIT_FILE => 0, C_HAS_OVERFLOW => 1, C_HAS_RD_DATA_COUNT => 0, C_HAS_RD_RST => 0, C_HAS_RST => 0, C_HAS_SRST => 1, C_HAS_UNDERFLOW => 1, C_HAS_VALID => 0, C_HAS_WR_ACK => 0, C_HAS_WR_DATA_COUNT => 0, C_HAS_WR_RST => 0, C_IMPLEMENTATION_TYPE => 6, C_INIT_WR_PNTR_VAL => 0, C_MEMORY_TYPE => 4, C_MIF_FILE_NAME => "BlankString", C_OPTIMIZATION_MODE => 0, C_OVERFLOW_LOW => 0, C_PRELOAD_LATENCY => 2, C_PRELOAD_REGS => 1, C_PRIM_FIFO_TYPE => "512x72", C_PROG_EMPTY_THRESH_ASSERT_VAL => 8, C_PROG_EMPTY_THRESH_NEGATE_VAL => 9, C_PROG_EMPTY_TYPE => 1, C_PROG_FULL_THRESH_ASSERT_VAL => 450, C_PROG_FULL_THRESH_NEGATE_VAL => 449, C_PROG_FULL_TYPE => 1, C_RD_DATA_COUNT_WIDTH => 9, C_RD_DEPTH => 512, C_RD_FREQ => 1, C_RD_PNTR_WIDTH => 9, C_UNDERFLOW_LOW => 0, C_USE_DOUT_RST => 1, C_USE_ECC => 0, C_USE_EMBEDDED_REG => 1, C_USE_PIPELINE_REG => 0, C_POWER_SAVING_MODE => 0, C_USE_FIFO16_FLAGS => 0, C_USE_FWFT_DATA_COUNT => 0, C_VALID_LOW => 0, C_WR_ACK_LOW => 0, C_WR_DATA_COUNT_WIDTH => 9, C_WR_DEPTH => 512, C_WR_FREQ => 1, C_WR_PNTR_WIDTH => 9, C_WR_RESPONSE_LATENCY => 1, C_MSGON_VAL => 1, C_ENABLE_RST_SYNC => 1, C_EN_SAFETY_CKT => 0, C_ERROR_INJECTION_TYPE => 0, C_SYNCHRONIZER_STAGE => 2, C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_HAS_AXI_WR_CHANNEL => 1, C_HAS_AXI_RD_CHANNEL => 1, C_HAS_SLAVE_CE => 0, C_HAS_MASTER_CE => 0, C_ADD_NGC_CONSTRAINT => 0, C_USE_COMMON_OVERFLOW => 0, C_USE_COMMON_UNDERFLOW => 0, C_USE_DEFAULT_SETTINGS => 0, C_AXI_ID_WIDTH => 1, C_AXI_ADDR_WIDTH => 32, C_AXI_DATA_WIDTH => 64, C_AXI_LEN_WIDTH => 8, C_AXI_LOCK_WIDTH => 1, C_HAS_AXI_ID => 0, C_HAS_AXI_AWUSER => 0, C_HAS_AXI_WUSER => 0, C_HAS_AXI_BUSER => 0, C_HAS_AXI_ARUSER => 0, C_HAS_AXI_RUSER => 0, C_AXI_ARUSER_WIDTH => 1, C_AXI_AWUSER_WIDTH => 1, C_AXI_WUSER_WIDTH => 1, C_AXI_BUSER_WIDTH => 1, C_AXI_RUSER_WIDTH => 1, C_HAS_AXIS_TDATA => 1, C_HAS_AXIS_TID => 0, C_HAS_AXIS_TDEST => 0, C_HAS_AXIS_TUSER => 1, C_HAS_AXIS_TREADY => 1, C_HAS_AXIS_TLAST => 0, C_HAS_AXIS_TSTRB => 0, C_HAS_AXIS_TKEEP => 0, C_AXIS_TDATA_WIDTH => 8, C_AXIS_TID_WIDTH => 1, C_AXIS_TDEST_WIDTH => 1, C_AXIS_TUSER_WIDTH => 4, C_AXIS_TSTRB_WIDTH => 1, C_AXIS_TKEEP_WIDTH => 1, C_WACH_TYPE => 0, C_WDCH_TYPE => 0, C_WRCH_TYPE => 0, C_RACH_TYPE => 0, C_RDCH_TYPE => 0, C_AXIS_TYPE => 0, C_IMPLEMENTATION_TYPE_WACH => 1, C_IMPLEMENTATION_TYPE_WDCH => 1, C_IMPLEMENTATION_TYPE_WRCH => 1, C_IMPLEMENTATION_TYPE_RACH => 1, C_IMPLEMENTATION_TYPE_RDCH => 1, C_IMPLEMENTATION_TYPE_AXIS => 1, C_APPLICATION_TYPE_WACH => 0, C_APPLICATION_TYPE_WDCH => 0, C_APPLICATION_TYPE_WRCH => 0, C_APPLICATION_TYPE_RACH => 0, C_APPLICATION_TYPE_RDCH => 0, C_APPLICATION_TYPE_AXIS => 0, C_PRIM_FIFO_TYPE_WACH => "512x36", C_PRIM_FIFO_TYPE_WDCH => "512x72", C_PRIM_FIFO_TYPE_WRCH => "512x36", C_PRIM_FIFO_TYPE_RACH => "512x36", C_PRIM_FIFO_TYPE_RDCH => "512x72", C_PRIM_FIFO_TYPE_AXIS => "1kx18", C_USE_ECC_WACH => 0, C_USE_ECC_WDCH => 0, C_USE_ECC_WRCH => 0, C_USE_ECC_RACH => 0, C_USE_ECC_RDCH => 0, C_USE_ECC_AXIS => 0, C_ERROR_INJECTION_TYPE_WACH => 0, C_ERROR_INJECTION_TYPE_WDCH => 0, C_ERROR_INJECTION_TYPE_WRCH => 0, C_ERROR_INJECTION_TYPE_RACH => 0, C_ERROR_INJECTION_TYPE_RDCH => 0, C_ERROR_INJECTION_TYPE_AXIS => 0, C_DIN_WIDTH_WACH => 1, C_DIN_WIDTH_WDCH => 64, C_DIN_WIDTH_WRCH => 2, C_DIN_WIDTH_RACH => 32, C_DIN_WIDTH_RDCH => 64, C_DIN_WIDTH_AXIS => 1, C_WR_DEPTH_WACH => 16, C_WR_DEPTH_WDCH => 1024, C_WR_DEPTH_WRCH => 16, C_WR_DEPTH_RACH => 16, C_WR_DEPTH_RDCH => 1024, C_WR_DEPTH_AXIS => 1024, C_WR_PNTR_WIDTH_WACH => 4, C_WR_PNTR_WIDTH_WDCH => 10, C_WR_PNTR_WIDTH_WRCH => 4, C_WR_PNTR_WIDTH_RACH => 4, C_WR_PNTR_WIDTH_RDCH => 10, C_WR_PNTR_WIDTH_AXIS => 10, C_HAS_DATA_COUNTS_WACH => 0, C_HAS_DATA_COUNTS_WDCH => 0, C_HAS_DATA_COUNTS_WRCH => 0, C_HAS_DATA_COUNTS_RACH => 0, C_HAS_DATA_COUNTS_RDCH => 0, C_HAS_DATA_COUNTS_AXIS => 0, C_HAS_PROG_FLAGS_WACH => 0, C_HAS_PROG_FLAGS_WDCH => 0, C_HAS_PROG_FLAGS_WRCH => 0, C_HAS_PROG_FLAGS_RACH => 0, C_HAS_PROG_FLAGS_RDCH => 0, C_HAS_PROG_FLAGS_AXIS => 0, C_PROG_FULL_TYPE_WACH => 0, C_PROG_FULL_TYPE_WDCH => 0, C_PROG_FULL_TYPE_WRCH => 0, C_PROG_FULL_TYPE_RACH => 0, C_PROG_FULL_TYPE_RDCH => 0, C_PROG_FULL_TYPE_AXIS => 0, C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, C_PROG_EMPTY_TYPE_WACH => 0, C_PROG_EMPTY_TYPE_WDCH => 0, C_PROG_EMPTY_TYPE_WRCH => 0, C_PROG_EMPTY_TYPE_RACH => 0, C_PROG_EMPTY_TYPE_RDCH => 0, C_PROG_EMPTY_TYPE_AXIS => 0, C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, C_REG_SLICE_MODE_WACH => 0, C_REG_SLICE_MODE_WDCH => 0, C_REG_SLICE_MODE_WRCH => 0, C_REG_SLICE_MODE_RACH => 0, C_REG_SLICE_MODE_RDCH => 0, C_REG_SLICE_MODE_AXIS => 0 ) PORT MAP ( backup => '0', backup_marker => '0', clk => '0', rst => '0', srst => srst, wr_clk => wr_clk, wr_rst => '0', rd_clk => rd_clk, rd_rst => '0', din => din, wr_en => wr_en, rd_en => rd_en, prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)), prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)), prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)), prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)), prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)), prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)), int_clk => '0', injectdbiterr => '0', injectsbiterr => '0', sleep => '0', dout => dout, full => full, overflow => overflow, empty => empty, underflow => underflow, prog_full => prog_full, prog_empty => prog_empty, wr_rst_busy => wr_rst_busy, rd_rst_busy => rd_rst_busy, m_aclk => '0', s_aclk => '0', s_aresetn => '0', m_aclk_en => '0', s_aclk_en => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awvalid => '0', s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_wlast => '0', s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wvalid => '0', s_axi_bready => '0', m_axi_awready => '0', m_axi_wready => '0', m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bvalid => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arvalid => '0', s_axi_rready => '0', m_axi_arready => '0', m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_rlast => '0', m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rvalid => '0', s_axis_tvalid => '0', s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tlast => '0', s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), m_axis_tready => '0', axi_aw_injectsbiterr => '0', axi_aw_injectdbiterr => '0', axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_w_injectsbiterr => '0', axi_w_injectdbiterr => '0', axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_b_injectsbiterr => '0', axi_b_injectdbiterr => '0', axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_injectsbiterr => '0', axi_ar_injectdbiterr => '0', axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_r_injectsbiterr => '0', axi_r_injectdbiterr => '0', axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_injectsbiterr => '0', axis_injectdbiterr => '0', axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)) ); END aurora_64b66b_25p4G_fifo_gen_master_arch;
bsd-3-clause
f920d57e220fe7e850885e48cb6f74e1
0.629481
2.902864
false
false
false
false
TanND/Electronic
VHDL/alu8bit_fu.vhd
1
2,280
------------------------------------------------------------------------------- -- -- Title : ALU_function -- Design : de1 -- Author : [email protected] -- Company : homes -- ------------------------------------------------------------------------------- -- -- File : ALU_function.vhd library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ALU_function is port( cin : in STD_LOGIC; a : in STD_LOGIC_VECTOR(7 downto 0); b : in STD_LOGIC_VECTOR(7 downto 0); sel : in STD_LOGIC_VECTOR(3 downto 0); y : out STD_LOGIC_VECTOR(7 downto 0) ); end ALU_function; --}} End of automatically maintained section architecture ALU_function of ALU_function is function hamlogic ( x1,x2: in std_logic_vector(7 downto 0); sel: in std_logic_vector(2 downto 0) ) return std_logic_vector is variable y1: std_logic_vector(7 downto 0); begin if sel = "000" then y1:= not x1; elsif sel ="001" then y1:= not x2; elsif sel ="010" then y1:= x1 and x2; elsif sel ="011" then y1:= x1 or x2; elsif sel ="100" then y1:= x1 nand x2; elsif sel ="101" then y1:= x1 nor x2; elsif sel ="110" then y1:= x1 xor x2; elsif sel ="111" then y1:= x1 xnor x2; end if ; return y1; end hamlogic; function hamsohoc ( a,b: in std_logic_vector(7 downto 0); sel: in std_logic_vector(2 downto 0); cin: in std_logic ) return std_logic_vector is variable y2: std_logic_vector(7 downto 0); begin if sel ="000" then y2:= a; elsif sel ="001" then y2:=a+1; elsif sel ="010" then y2:=a-1; elsif sel ="011" then y2:=b; elsif sel ="100" then y2:=b+1; elsif sel ="101" then y2:=b-1; elsif sel ="110" then y2:=a+b; elsif sel ="111" then y2:=a+b+cin; end if; return y2; end hamsohoc; function hammux ( y1,y2: in std_logic_vector(7 downto 0) ; sel : in STD_LOGIC ) return std_logic_vector is variable z: std_logic_vector(7 downto 0); begin if sel='0'then z:=y1; else z:=y2; end if; return z; end hammux; signal w1,w2: std_logic_vector (7 downto 0); begin process(sel,a,b,cin) begin w1<=hamlogic(a,b,sel(2 downto 0)); w2<=hamsohoc(a,b,sel(2 downto 0),cin); y<=hammux(w1,w2,sel(3)); end process; end ALU_function;
apache-2.0
e7c83cc42c4586e2742fc8915e1f74c3
0.590351
2.746988
false
false
false
false
SoCdesign/EHA
RTL/Immortal_Chip/TB_Package_32_bit.vhd
3
19,373
--Copyright (C) 2016 Siavoosh Payandeh Azad library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use IEEE.NUMERIC_STD.all; use ieee.math_real.all; use std.textio.all; use ieee.std_logic_misc.all; package TB_Package is function Header_gen(Packet_length, source, destination, packet_id: integer ) return std_logic_vector ; function Body_gen(Packet_length, Data: integer ) return std_logic_vector ; function Tail_gen(Packet_length, Data: integer ) return std_logic_vector ; procedure gen_packet(Packet_length, source, destination, packet_id, initial_delay: in integer; finish_time: in time; signal clk: in std_logic; signal DCTS: in std_logic; signal RTS: out std_logic; signal port_in: out std_logic_vector); procedure gen_random_packet(frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer; finish_time: in time; signal clk: in std_logic; signal DCTS: in std_logic; signal RTS: out std_logic; signal port_in: out std_logic_vector); procedure gen_bit_reversed_packet(frame_length, source, initial_delay, network_size, min_packet_size, max_packet_size: in integer; finish_time: in time; signal clk: in std_logic; signal DCTS: in std_logic; signal RTS: out std_logic; signal port_in: out std_logic_vector); procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic; signal CTS: out std_logic; signal DRTS: in std_logic; signal port_in: in std_logic_vector); procedure gen_fault(signal sta_0, sta_1: out std_logic; signal address: out std_logic_vector; delay, seed_1, seed_2: in integer); end TB_Package; package body TB_Package is constant Header_type : std_logic_vector := "001"; constant Body_type : std_logic_vector := "010"; constant Tail_type : std_logic_vector := "100"; function Header_gen(Packet_length, source, destination, packet_id: integer) return std_logic_vector is variable Header_flit: std_logic_vector (31 downto 0); begin Header_flit := Header_type & std_logic_vector(to_unsigned(Packet_length, 12)) & std_logic_vector(to_unsigned(destination, 4)) & std_logic_vector(to_unsigned(source, 4)) & std_logic_vector(to_unsigned(packet_id, 8)) & XOR_REDUCE(Header_type & std_logic_vector(to_unsigned(Packet_length, 12)) & std_logic_vector(to_unsigned(destination, 4)) & std_logic_vector(to_unsigned(source, 4)) & std_logic_vector(to_unsigned(packet_id, 8))); return Header_flit; end Header_gen; function Body_gen(Packet_length, Data: integer) return std_logic_vector is variable Body_flit: std_logic_vector (31 downto 0); begin Body_flit := Body_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Body_type & std_logic_vector(to_unsigned(Data, 28))); return Body_flit; end Body_gen; function Tail_gen(Packet_length, Data: integer) return std_logic_vector is variable Tail_flit: std_logic_vector (31 downto 0); begin Tail_flit := Tail_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Tail_type & std_logic_vector(to_unsigned(Data, 28))); return Tail_flit; end Tail_gen; procedure gen_packet(Packet_length, source, destination, packet_id, initial_delay: in integer; finish_time: in time; signal clk: in std_logic; signal DCTS: in std_logic; signal RTS: out std_logic; signal port_in: out std_logic_vector) is -- Packet_length of 3 means it has 1 header, 1 body and 1 tail. the number of body packets are equal to Packet_length-2 -- source: id of the source node -- destination: id of the destination node -- packet id: packet identification number! TODO: has to be implemented! -- initial_delay: waits for this number of clock cycles before sending the packet! variable seed1 :positive ; variable seed2 :positive ; variable rand : real ; variable first_time :boolean := true; variable destination_id: integer; variable LINEVARIABLE : line; file VEC_FILE : text is out "sent.txt"; begin while true loop RTS <= '0'; if first_time = true then for i in 0 to initial_delay loop wait until clk'event and clk ='0'; end loop; else wait until clk'event and clk ='0'; end if; --wait untill the falling edge of the clock to avoid race! report "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination); write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination) & " with length: "& integer'image(Packet_length)); writeline(VEC_FILE, LINEVARIABLE); port_in <= Header_gen(Packet_length, source, destination, packet_id); wait until clk'event and clk ='1'; RTS <= '1'; wait until DCTS'event and DCTS ='1'; wait until clk'event and clk ='1'; RTS <= '0'; for I in 0 to Packet_length-3 loop uniform(seed1, seed2, rand); wait until clk'event and clk ='0'; port_in <= Body_gen(Packet_length, integer(rand*1000.0)); wait until clk'event and clk ='1'; RTS <= '1'; wait until DCTS'event and DCTS ='1'; wait until clk'event and clk ='1'; RTS <= '0'; end loop; wait until clk'event and clk ='0'; port_in <= Tail_gen(Packet_length, 200); wait until clk'event and clk ='1'; RTS <= '1'; wait until DCTS'event and DCTS ='1'; wait until clk'event and clk ='1'; RTS <= '0'; if now > finish_time then wait; end if; end loop; end gen_packet; procedure gen_random_packet(frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer; finish_time: in time; signal clk: in std_logic; signal DCTS: in std_logic; signal RTS: out std_logic; signal port_in: out std_logic_vector) is -- frame_length is inverse of PIR. with the unit of clock cycles. which means how many clock cycles per packet to -- be injected. to build a true random traffic generator, we need to make a series of frames: -- -- -- <--- Frame length-----> <--- Frame length-----> <--- Frame length-----> -- -- <-----> |<--------|///////|---->|<----|///////////|---->|<-|////|-------------->| -- initial <-------> <----------> <-------------> -- delay frame Packet_size frame -- initial end delay -- delay -- -- source: id of the source node -- initial_delay: waits for this number of clock cycles before sending the packet! variable seed1 :positive ; variable seed2 :positive ; variable rand : real ; variable first_time :boolean := true; variable id_counter : integer:= 0; variable frame_starting_delay, Packet_length, frame_ending_delay: integer := 0; variable destination_id: integer; variable LINEVARIABLE : line; file VEC_FILE : text is out "sent.txt"; begin while true loop -- generating the ID id_counter := id_counter + 1; if id_counter = 256 then id_counter := 0; end if; -- generating the packet length uniform(seed1, seed2, rand); Packet_length := integer((integer(rand*100.0)*frame_length)/300); if (Packet_length < min_packet_size) then Packet_length:=min_packet_size; end if; if (Packet_length > max_packet_size) then Packet_length:=max_packet_size; end if; assert (3*Packet_length<=frame_length) report "packet_length "& integer'image(Packet_length)&" exceeds frame size "& integer'image(frame_length) severity failure; --generating the frame initial delay uniform(seed1, seed2, rand); frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - 3*Packet_length)))/100); --generating the frame ending delay frame_ending_delay := frame_length - (3*Packet_length+frame_starting_delay); RTS <= '0'; if first_time = true then port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ; wait until clk'event and clk ='1'; for i in 0 to initial_delay loop -- wait until clk'event and clk ='0'; wait for 1 ns; end loop; port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ; wait until clk'event and clk ='1'; for k in 0 to frame_starting_delay-1 loop --wait until clk'event and clk ='0'; wait for 1 ns; end loop; first_time := false; else wait until clk'event and clk ='1'; for k in 0 to frame_starting_delay-1 loop --wait until clk'event and clk ='0'; wait for 1 ns; end loop; end if; uniform(seed1, seed2, rand); destination_id := integer(rand*3.0); while (destination_id = source) loop uniform(seed1, seed2, rand); destination_id := integer(rand*3.0); end loop; --wait untill the falling edge of the clock to avoid race! report "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id); write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id) & " with length: "& integer'image(Packet_length)& " with id: "&integer'image(id_counter)); writeline(VEC_FILE, LINEVARIABLE); port_in <= Header_gen(Packet_length, source, destination_id, id_counter); wait until clk'event and clk ='1'; RTS <= '1'; wait until DCTS'event and DCTS ='1'; wait until clk'event and clk ='1'; RTS <= '0'; for I in 0 to Packet_length-3 loop uniform(seed1, seed2, rand); wait until clk'event and clk ='0'; port_in <= Body_gen(Packet_length, integer(rand*1000.0)); wait until clk'event and clk ='1'; RTS <= '1'; wait until DCTS'event and DCTS ='1'; wait until clk'event and clk ='1'; RTS <= '0'; end loop; wait until clk'event and clk ='0'; uniform(seed1, seed2, rand); port_in <= Tail_gen(Packet_length, integer(rand*1000.0)); wait until clk'event and clk ='1'; RTS <= '1'; wait until DCTS'event and DCTS ='1'; wait until clk'event and clk ='1'; RTS <= '0'; port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ; for l in 0 to frame_ending_delay-1 loop wait for 1 ns; end loop; port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ; if now > finish_time then wait; end if; end loop; end gen_random_packet; procedure gen_bit_reversed_packet(frame_length, source, initial_delay, network_size, min_packet_size, max_packet_size: in integer; finish_time: in time; signal clk: in std_logic; signal DCTS: in std_logic; signal RTS: out std_logic; signal port_in: out std_logic_vector) is -- frame_length is inverse of PIR. with the unit of clock cycles. which means how many clock cycles per packet to -- be injected. to build a true random traffic generator, we need to make a series of frames: -- -- -- <--- Frame length-----> <--- Frame length-----> <--- Frame length-----> -- -- <-----> |<--------|///////|---->|<----|///////////|---->|<-|////|-------------->| -- initial <-------> <----------> <-------------> -- delay frame Packet_size frame -- initial end delay -- delay -- -- source: id of the source node -- initial_delay: waits for this number of clock cycles before sending the packet! variable seed1 :positive ; variable seed2 :positive ; variable rand : real ; variable first_time :boolean := true; variable id_counter : integer:= 0; variable frame_starting_delay, Packet_length, frame_ending_delay: integer := 0; variable destination_id: integer; variable LINEVARIABLE : line; file VEC_FILE : text is out "sent.txt"; begin while true loop -- generating the ID id_counter := id_counter + 1; if id_counter = 256 then id_counter := 0; end if; -- generating the packet length uniform(seed1, seed2, rand); Packet_length := integer((integer(rand*100.0)/300)*frame_length); if (Packet_length < min_packet_size) then Packet_length := min_packet_size; end if; if (Packet_length > max_packet_size) then Packet_length := max_packet_size; end if; assert (3*Packet_length<=frame_length) report "packet_length "& integer'image(Packet_length)&" exceeds frame size "& integer'image(frame_length) severity failure; --generating the frame initial delay uniform(seed1, seed2, rand); frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - 3*Packet_length)))/100); --generating the frame ending delay frame_ending_delay := frame_length - (3*Packet_length+frame_starting_delay); RTS <= '0'; if first_time = true then port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ; wait until clk'event and clk ='1'; for i in 0 to initial_delay loop -- wait until clk'event and clk ='0'; wait for 1 ns; end loop; port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ; wait until clk'event and clk ='1'; for k in 0 to frame_starting_delay-1 loop --wait until clk'event and clk ='0'; wait for 1 ns; end loop; first_time := false; else wait until clk'event and clk ='1'; for k in 0 to frame_starting_delay-1 loop --wait until clk'event and clk ='0'; wait for 1 ns; end loop; end if; destination_id := to_integer(unsigned(not std_logic_vector(to_unsigned(source, network_size)))); if destination_id = source then wait; end if; --wait untill the falling edge of the clock to avoid race! report "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id); report " frame_size: " & integer'image(frame_length) & " packet_length: " & integer'image(Packet_length) & "starting_delay: " & integer'image(frame_starting_delay) & " ending_delay: " & integer'image(frame_ending_delay); write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id) & " with length: "& integer'image(Packet_length)& " with id: "&integer'image(id_counter)); writeline(VEC_FILE, LINEVARIABLE); port_in <= Header_gen(Packet_length, source, destination_id, id_counter); wait until clk'event and clk ='1'; RTS <= '1'; wait until DCTS'event and DCTS ='1'; wait until clk'event and clk ='1'; RTS <= '0'; for I in 0 to Packet_length-3 loop uniform(seed1, seed2, rand); wait until clk'event and clk ='0'; port_in <= Body_gen(Packet_length, integer(rand*1000.0)); wait until clk'event and clk ='1'; RTS <= '1'; wait until DCTS'event and DCTS ='1'; wait until clk'event and clk ='1'; RTS <= '0'; end loop; wait until clk'event and clk ='0'; uniform(seed1, seed2, rand); port_in <= Tail_gen(Packet_length, integer(rand*1000.0)); wait until clk'event and clk ='1'; RTS <= '1'; wait until DCTS'event and DCTS ='1'; wait until clk'event and clk ='1'; RTS <= '0'; port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ; for l in 0 to frame_ending_delay-1 loop wait for 1 ns; end loop; port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ; if now > finish_time then wait; end if; end loop; end gen_bit_reversed_packet; procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic; signal CTS: out std_logic; signal DRTS: in std_logic; signal port_in: in std_logic_vector) is -- initial_delay: waits for this number of clock cycles before sending the packet! variable source_node, destination_node, P_length, packet_id, counter: integer; variable LINEVARIABLE : line; file VEC_FILE : text is out "received.txt"; begin while true loop counter := 0; CTS <= '0'; wait until DRTS'event and DRTS ='1'; wait until clk'event and clk ='1'; CTS <= '1'; wait until clk'event and clk ='1'; if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001") then counter := 1; P_length := to_integer(unsigned(port_in(28 downto 17))); destination_node := to_integer(unsigned(port_in(16 downto 13))); source_node := to_integer(unsigned(port_in(12 downto 9))); packet_id := to_integer(unsigned(port_in(8 downto 1))); end if; CTS <= '0'; while (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) /= "100") loop wait until DRTS'event and DRTS ='1'; wait until clk'event and clk ='1'; CTS <= '1'; wait until clk'event and clk ='1'; counter := counter+1; CTS <= '0'; end loop; report "Packet received at " & time'image(now) & " From " & integer'image(source_node) & " to " & integer'image(destination_node) & " with length: "& integer'image(P_length) & " counter: "& integer'image(counter); assert (P_length=counter) report "wrong packet size" severity failure; assert (Node_ID=destination_node) report "wrong packet destination " severity failure; write(LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(source_node) & " to: " & integer'image(destination_node) & " length: "& integer'image(P_length)& " id: "& integer'image(packet_id)); writeline(VEC_FILE, LINEVARIABLE); end loop; end get_packet; procedure gen_fault(signal sta_0, sta_1: out std_logic; signal address: out std_logic_vector; delay, seed_1, seed_2: in integer) is variable seed1 :positive := seed_1; variable seed2 :positive := seed_2; variable rand : real; variable stuck: integer; begin sta_0 <= '0'; sta_1 <= '0'; while true loop sta_0 <= '0'; sta_1 <= '0'; for I in 0 to delay loop wait for 1 ns; end loop; uniform(seed1, seed2, rand); address <= std_logic_vector(to_unsigned(integer(rand*31.0), 5)); uniform(seed1, seed2, rand); stuck := integer(rand*11.0); if stuck > 5 then sta_0 <= '1'; sta_1 <= '0'; else sta_0 <= '0'; sta_1 <= '1'; end if; wait for 2 ns; end loop; end gen_fault; end TB_Package;
gpl-3.0
102a86a81726cfc801b2e22a10c828aa
0.595984
3.811332
false
false
false
false
TUM-LIS/faultify
hardware/testcases/fpu100_div/fpga_sim/xpsLibraryPath_asic/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/vhdl/faultify_top.vhd
2
21,012
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity faultify_top is generic ( numInj : integer := 56; numIn : integer := 10; numOut : integer := 10); port ( aclk : in std_logic; -- interface clock arst_n : in std_logic; -- interface reset clk : in std_logic; -- simulation clock (slow) clk_x32 : in std_logic; -- prng clock (fast) -- Write channel awvalid : in std_logic; awaddr : in std_logic_vector(31 downto 0); wvalid : in std_logic; wdata : in std_logic_vector(31 downto 0); -- Read channel arvalid : in std_logic; araddr : in std_logic_vector(31 downto 0); rvalid : out std_logic; rdata : out std_logic_vector(31 downto 0) ); attribute syn_hier : string; attribute syn_hier of faultify_top : entity is "hard"; end faultify_top; architecture behav of faultify_top is component flag_cdc port ( clkA : in std_logic; clkB : in std_logic; FlagIn_clkA : in std_logic; FlagOut_clkB : out std_logic; rst_n : in std_logic); end component; component faultify_simulator generic ( numInj : integer; numIn : integer; numOut : integer); port ( clk : in std_logic; clk_m : in std_logic; circ_ce : in std_logic; circ_rst : in std_logic; test : out std_logic_vector(31 downto 0); testvector : in std_logic_vector(numIn-1 downto 0); resultvector_o : out std_logic_vector(numOut-1 downto 0); resultvector_f : out std_logic_vector(numOut-1 downto 0); seed_in_en : in std_logic; seed_in : in std_logic; prob_in_en : in std_logic; prob_in : in std_logic; shift_en : in std_logic; rst_n : in std_logic); end component; component lfsr generic ( width : integer; seed : integer); port ( clk : in std_logic; rand_out : out std_logic_vector(width-1 downto 0)); end component; type vector is array (0 to numOut-1) of std_logic_vector(31 downto 0); signal errorSum : vector; signal errorSumReg : vector; signal errorSumReg_cdc_0 : vector; signal errorSumReg_cdc_1 : vector; signal errorVec : std_logic_vector(numOut-1 downto 0); signal cnt : integer; signal cnt_cdc_0 : integer; signal cnt_cdc_1 : integer; -- Asymmetric ram larger than 36 bit not supported in synplify I-2013 --type seed_ram_matr is array (0 to numInj-1) of std_logic_vector(63 downto 0); --signal seed_ram : seed_ram_matr; -- workaround 2 32-bit rams type seed_ram_matr is array (0 to numInj-1) of std_logic_vector(31 downto 0); signal seed_ram_low : seed_ram_matr; signal seed_ram_high : seed_ram_matr; --subtype seed_ram_matr_word_t is std_logic_vector(63 downto 0); --type seed_ram_matr_memory_t is array (0 to numInj-1) of seed_ram_matr_word_t; --signal seed_ram : seed_ram_matr_memory_t; type prob_ram_matr is array (0 to numInj-1) of std_logic_vector(31 downto 0); signal prob_ram : prob_ram_matr; type reg_type is record control : std_logic_vector(31 downto 0); status : std_logic_vector(31 downto 0); pe_location : std_logic_vector(31 downto 0); pe_seed_low : std_logic_vector(31 downto 0); pe_seed_high : std_logic_vector(31 downto 0); pe_probability : std_logic_vector(31 downto 0); output : std_logic_vector(31 downto 0); ovalid : std_logic; simtime : std_logic_vector(31 downto 0); sel_soe : std_logic_vector(31 downto 0); adr_soe : std_logic_vector(31 downto 0); awaddr : std_logic_vector(31 downto 0); test : std_logic_vector(31 downto 0); circreset : std_logic_vector(31 downto 0); cnt_tmp : std_logic_vector(31 downto 0); sumoferrors : vector; end record; signal busy_loading : std_logic; signal busy_simulating : std_logic; signal busy_loading_reg : std_logic_vector(1 downto 0); signal busy_simulating_reg : std_logic_vector(1 downto 0); signal sim_done : std_logic; signal r : reg_type; type load_fsm_states is (IDLE, LOADSEED, LOADPROB); signal l_state : load_fsm_states; type sim_states is (IDLE, DELAY_Z, DELAY, SIMULATION, DELAY2, DELAY3, DELAY4, FREE_SIMULATION); signal s_state : sim_states; signal testvector : std_logic_vector(numIn-1 downto 0); signal resultvector_o : std_logic_vector(numOut-1 downto 0); signal resultvector_f : std_logic_vector(numOut-1 downto 0); signal seed_in_en : std_logic; signal seed_in : std_logic; signal prob_in_en : std_logic; signal prob_in : std_logic; signal shift_en : std_logic; signal shift_en_l : std_logic; signal shift_en_s : std_logic; signal load_seed_prob : std_logic; signal start_simulation : std_logic; signal start_free_simulation : std_logic; signal stop_simulation : std_logic; signal circ_ce, circ_rst, circ_rst_sim : std_logic; signal tvec : std_logic_vector(127 downto 0); signal test : std_logic_vector(31 downto 0); signal rst_cdc, rst_cdc_n : std_logic; type tb_state_defs is (IDLE, DATA, WAITING); signal tb_state : tb_state_defs; begin -- behav ----------------------------------------------------------------------------- -- PRNG shifting ----------------------------------------------------------------------------- shift_en <= shift_en_l or shift_en_s; ----------------------------------------------------------------------------- -- Testvector ----------------------------------------------------------------------------- --testvector <= (others => '0'); lfsr_1 : lfsr generic map ( width => 128, seed => 3498327) port map ( clk => clk, rand_out => tvec); testvector(63 downto 0) <= tvec(63 downto 0); testvector(66 downto 64) <= "011"; testvector(68 downto 67) <= "00"; --testvector(69) <= tvec(64); process (clk, circ_rst_sim) is begin -- process if circ_rst_sim = '1' then -- asynchronous reset (active low) testvector(69) <= '0'; tb_state <= IDLE; elsif clk'event and clk = '1' then -- rising clock edge case tb_state is when IDLE => tb_state <= DATA; testvector(69) <= '1'; when DATA => tb_state <= WAITING; testvector(69) <= '0'; when WAITING => if resultvector_o(32) = '1' then tb_state <= DATA; testvector(69) <= '1'; end if; end case; end if; end process; ----------------------------------------------------------------------------- -- Simulator ----------------------------------------------------------------------------- circ_rst <= circ_rst_sim when r.circreset(0) = '1' else '0'; faultify_simulator_1 : faultify_simulator generic map ( numInj => numInj, numIn => numIn, numOut => numOut) port map ( clk => clk_x32, clk_m => clk, circ_ce => circ_ce, circ_rst => circ_rst, test => test, testvector => testvector, resultvector_o => resultvector_o, resultvector_f => resultvector_f, seed_in_en => seed_in_en, seed_in => seed_in, prob_in_en => prob_in_en, prob_in => prob_in, shift_en => shift_en, rst_n => arst_n); ------------------------------------------------------------------------------- -- One Process Flow ------------------------------------------------------------------------------- register_process : process (aclk, arst_n) variable write_addr : std_logic_vector(31 downto 0); begin -- process register_process if arst_n = '0' then -- asynchronous reset (active low) r.control <= (others => '0'); r.status <= (others => '0'); r.pe_probability <= (others => '0'); r.pe_seed_high <= (others => '0'); r.pe_seed_low <= (others => '0'); r.pe_location <= (others => '0'); r.ovalid <= '0'; r.simtime <= (others => '0'); r.sel_soe <= (others => '0'); r.adr_soe <= (others => '0'); r.sumoferrors <= (others => (others => '0')); r.output <= (others => '0'); elsif aclk'event and aclk = '1' then -- rising clock edge r.control <= (others => '0'); if awvalid = '1' then r.awaddr <= awaddr; write_addr := awaddr; end if; if wvalid = '1' then if write_addr = x"00000000" then r.control <= wdata; elsif write_addr = x"00000001" then r.pe_location <= wdata; elsif write_addr = x"00000002" then r.pe_seed_low <= wdata; elsif write_addr = x"00000003" then r.pe_seed_high <= wdata; elsif write_addr = x"00000004" then r.pe_probability <= wdata; elsif write_addr = x"00000005" then r.cnt_tmp <= std_logic_vector(to_unsigned(cnt_cdc_1, 32)); r.adr_soe <= wdata; elsif write_addr = x"00000007" then r.simtime <= wdata; elsif write_addr = x"00000009" then r.circreset <= wdata; end if; end if; if arvalid = '1' then if araddr = x"0000000F" then r.output <= r.status; elsif araddr = x"00000001" then r.output <= r.pe_location; elsif araddr = x"00000002" then r.output <= r.pe_seed_low; elsif araddr = x"00000003" then r.output <= r.pe_seed_high; elsif araddr = x"00000004" then r.output <= r.pe_probability; elsif araddr = x"00000006" then r.output <= r.sel_soe; elsif araddr = x"00000008" then r.output <= r.test; elsif araddr = x"0000000A" then r.output <= r.cnt_tmp; end if; r.ovalid <= '1'; else r.ovalid <= '0'; end if; if busy_loading_reg(1) = '1' then r.status(0) <= '1'; else r.status(0) <= '0'; end if; if busy_simulating_reg(1) = '1' then r.status(1) <= '1'; else r.status(1) <= '0'; end if; r.sel_soe <= r.sumoferrors(to_integer(unsigned(r.adr_soe))); rdata <= r.output; rvalid <= r.ovalid; r.sumoferrors <= errorSumReg_cdc_1; r.test <= errorSum(0); end if; end process register_process; ----------------------------------------------------------------------------- -- simple clock domain crossing ----------------------------------------------------------------------------- process (aclk, arst_n) begin -- process if arst_n = '0' then -- asynchronous reset (active low) busy_simulating_reg <= (others => '0'); busy_loading_reg <= (others => '0'); elsif aclk'event and aclk = '1' then -- rising clock edge busy_simulating_reg(0) <= busy_simulating; busy_loading_reg(0) <= busy_loading; busy_simulating_reg(1) <= busy_simulating_reg(0); busy_loading_reg(1) <= busy_loading_reg(0); cnt_cdc_0 <= cnt; cnt_cdc_1 <= cnt_cdc_0; errorSumReg_cdc_0 <= errorSumReg; errorSumReg_cdc_1 <= errorSumReg_cdc_0; end if; end process; ------------------------------------------------------------------------------- -- Store seeed/prob ------------------------------------------------------------------------------- store_seed : process (aclk, arst_n) begin -- process store_seed if arst_n = '0' then -- asynchronous reset (active low) elsif aclk'event and aclk = '1' then -- rising clock edge if r.control(0) = '1' then -- Synplify bug workaround --seed_ram(to_integer(unsigned(r.pe_location))) <= r.pe_seed_high & r.pe_seed_low; seed_ram_low(to_integer(unsigned(r.pe_location))) <= r.pe_seed_low; seed_ram_high(to_integer(unsigned(r.pe_location))) <= r.pe_seed_high; prob_ram(to_integer(unsigned(r.pe_location))) <= r.pe_probability; end if; end if; end process store_seed; ----------------------------------------------------------------------------- -- Seed/prob loading FSM ----------------------------------------------------------------------------- --flag_cdc_1 : flag_cdc -- port map ( -- clkA => aclk, -- clkB => clk_x32, -- FlagIn_clkA => r.control(1), -- FlagOut_clkB => load_seed_prob, -- rst_n => arst_n); load_seed_prob <= r.control(1); seed_prob_loading : process (clk_x32, arst_n) variable cnt_seed : integer range 0 to 64; variable cnt_inj : integer range 0 to numInj; variable cnt_prob : integer range 0 to 32; begin -- process seed_prob_loading if arst_n = '0' then -- asynchronous reset (active low) l_state <= IDLE; seed_in <= '0'; seed_in_en <= '0'; prob_in <= '0'; prob_in_en <= '0'; shift_en_l <= '0'; busy_loading <= '0'; elsif clk_x32'event and clk_x32 = '1' then -- rising clock edge case l_state is when IDLE => cnt_seed := 0; cnt_inj := 0; cnt_prob := 0; busy_loading <= '0'; seed_in_en <= '0'; prob_in_en <= '0'; shift_en_l <= '0'; if load_seed_prob = '1' then busy_loading <= '1'; l_state <= LOADSEED; end if; when LOADSEED => if cnt_seed < 64 then shift_en_l <= '1'; seed_in_en <= '1'; -- not working in synplify I-2013 --seed_in <= seed_ram(cnt_inj)(cnt_seed); -- if cnt_seed < 32 then seed_in <= seed_ram_low(cnt_inj)(cnt_seed); else seed_in <= seed_ram_high(cnt_inj)(cnt_seed-32); end if; cnt_seed := cnt_seed + 1; end if; if cnt_seed = 64 then cnt_seed := 0; cnt_inj := cnt_inj + 1; end if; if cnt_inj = numInj then l_state <= LOADPROB; --seed_in_en <= '0'; cnt_inj := 0; end if; when LOADPROB => seed_in_en <= '0'; if cnt_prob < 32 then prob_in_en <= '1'; prob_in <= prob_ram(cnt_inj)(cnt_prob); cnt_prob := cnt_prob + 1; end if; if cnt_prob = 32 then cnt_prob := 0; cnt_inj := cnt_inj + 1; end if; if cnt_inj = numInj then l_state <= IDLE; cnt_inj := 0; --prob_in_en <= '0'; end if; end case; end if; end process seed_prob_loading; ----------------------------------------------------------------------------- -- Simulation FSM ----------------------------------------------------------------------------- flag_cdc_2 : flag_cdc port map ( clkA => aclk, clkB => clk, FlagIn_clkA => r.control(2), FlagOut_clkB => start_simulation, rst_n => arst_n); flag_cdc_3 : flag_cdc port map ( clkA => aclk, clkB => clk, FlagIn_clkA => r.control(3), FlagOut_clkB => start_free_simulation, rst_n => arst_n); flag_cdc_4 : flag_cdc port map ( clkA => aclk, clkB => clk, FlagIn_clkA => r.control(4), FlagOut_clkB => stop_simulation, rst_n => arst_n); rst_cdc_5 : flag_cdc port map ( clkA => aclk, clkB => clk, FlagIn_clkA => not arst_n, FlagOut_clkB => rst_cdc, rst_n => '1'); rst_cdc_n <= not rst_cdc; process (clk, rst_cdc_n) variable simtime : integer; variable cnt_delay : integer range 0 to 9; begin -- process if clk'event and clk = '1' then -- rising clock edge if rst_cdc_n = '0' then -- asynchronous reset (active low) s_state <= IDLE; errorVec <= (others => '0'); errorSum <= (others => (others => '0')); circ_ce <= '0'; circ_rst_sim <= '1'; shift_en_s <= '0'; busy_simulating <= '0'; sim_done <= '0'; errorSumReg <= (others => (others => '0')); else case s_state is when IDLE => sim_done <= '0'; circ_ce <= '0'; circ_rst_sim <= '1'; shift_en_s <= '0'; errorVec <= (others => '0'); --errorSum <= errorSum; errorSum <= (others => (others => '0')); --cnt <= 0; busy_simulating <= '0'; cnt_delay := 0; if start_simulation = '1' then cnt <= 0; busy_simulating <= '1'; errorSum <= (others => (others => '0')); errorSumReg <= (others => (others => '0')); simtime := to_integer(unsigned(r.simtime)); s_state <= DELAY_Z; circ_ce <= '1'; circ_rst_sim <= '0'; shift_en_s <= '1'; end if; if start_free_simulation = '1' then cnt <= 0; busy_simulating <= '1'; errorSum <= (others => (others => '0')); errorSumReg <= (others => (others => '0')); s_state <= FREE_SIMULATION; circ_ce <= '1'; circ_rst_sim <= '0'; shift_en_s <= '1'; end if; when DELAY_z => cnt_delay := cnt_delay + 1; if cnt_delay = 9 then s_state <= DELAY; end if; when DELAY => s_state <= SIMULATION; errorVec <= (others => '0'); errorSum <= (others => (others => '0')); when SIMULATION => circ_rst_sim <= '0'; shift_en_s <= '1'; -- collect errors if (resultVector_o(32) = '1') then errorVec <= resultvector_o xor resultvector_f; else errorVec <= (others => '0'); end if; for i in 0 to (numOut-1) loop if (errorVec(i) = '1') then errorSum(i) <= std_logic_vector(unsigned(errorSum(i)) + 1); end if; end loop; -- errorSumReg <= errorSum; if cnt = simtime-1 then s_state <= DELAY2; circ_ce <= '0'; circ_rst_sim <= '1'; shift_en_s <= '0'; end if; cnt <= cnt +1; when DELAY2 => if (resultVector_o(32) = '1') then errorVec <= resultvector_o xor resultvector_f; else errorVec <= (others => '0'); end if; for i in 0 to (numOut-1) loop if (errorVec(i) = '1') then errorSum(i) <= std_logic_vector(unsigned(errorSum(i)) + 1); end if; end loop; s_state <= DELAY3; when DELAY3 => s_state <= DELAY4; errorSumReg <= errorSum; errorSum <= (others => (others => '0')); when DELAY4 => s_state <= IDLE; sim_done <= '1'; when FREE_SIMULATION => circ_rst_sim <= '0'; shift_en_s <= '1'; -- collect errors if (resultVector_o(32) = '1') then errorVec <= resultvector_o xor resultvector_f; else errorVec <= (others => '0'); end if; for i in 0 to (numOut-1) loop if (errorVec(i) = '1') then errorSum(i) <= std_logic_vector(unsigned(errorSum(i)) + 1); end if; end loop; -- errorSumReg <= errorSum; if stop_simulation = '1' then s_state <= IDLE; sim_done <= '1'; circ_ce <= '0'; circ_rst_sim <= '1'; shift_en_s <= '0'; end if; cnt <= cnt +1; when others => s_state <= IDLE; end case; end if; end if; end process; end behav;
gpl-2.0
536c6a78c7ba439ed4ba526e4bf1179a
0.462402
3.842019
false
false
false
false
bruskajp/EE-316
Project1/rom.vhd
1
6,173
-- megafunction wizard: %ROM: 1-PORT% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altsyncram -- ============================================================ -- File Name: rom.vhd -- Megafunction Name(s): -- altsyncram -- -- Simulation Library Files(s): -- altera_mf -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 13.0.0 Build 156 04/24/2013 SJ Full Version -- ************************************************************ --Copyright (C) 1991-2013 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY rom IS PORT ( address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); clock : IN STD_LOGIC := '1'; q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) ); END rom; ARCHITECTURE SYN OF rom IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0); COMPONENT altsyncram GENERIC ( clock_enable_input_a : STRING; clock_enable_output_a : STRING; init_file : STRING; intended_device_family : STRING; lpm_hint : STRING; lpm_type : STRING; numwords_a : NATURAL; operation_mode : STRING; outdata_aclr_a : STRING; outdata_reg_a : STRING; widthad_a : NATURAL; width_a : NATURAL; width_byteena_a : NATURAL ); PORT ( address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); clock0 : IN STD_LOGIC ; q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) ); END COMPONENT; BEGIN q <= sub_wire0(15 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( clock_enable_input_a => "BYPASS", clock_enable_output_a => "BYPASS", init_file => "sine.mif", intended_device_family => "Cyclone II", lpm_hint => "ENABLE_RUNTIME_MOD=NO", lpm_type => "altsyncram", numwords_a => 256, operation_mode => "ROM", outdata_aclr_a => "NONE", outdata_reg_a => "UNREGISTERED", widthad_a => 8, width_a => 16, width_byteena_a => 1 ) PORT MAP ( address_a => address, clock0 => clock, q_a => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" -- Retrieval info: PRIVATE: AclrByte NUMERIC "0" -- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: Clken NUMERIC "0" -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -- Retrieval info: PRIVATE: MIFfilename STRING "sine.mif" -- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256" -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" -- Retrieval info: PRIVATE: RegOutput NUMERIC "0" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" -- Retrieval info: PRIVATE: WidthAddr NUMERIC "8" -- Retrieval info: PRIVATE: WidthData NUMERIC "16" -- Retrieval info: PRIVATE: rden NUMERIC "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: INIT_FILE STRING "sine.mif" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" -- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" -- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL rom.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL rom.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL rom.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL rom.bsf FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL rom_inst.vhd FALSE -- Retrieval info: LIB_FILE: altera_mf
gpl-3.0
bc598d4df4c730c730e5c6ebf5b4c2d2
0.649441
3.523402
false
false
false
false
TanND/Electronic
VHDL/D14_C2.vhd
1
592
library IEEE; use IEEE.STD_LOGIC_1164.all; entity D14_C2 is port( clk : in STD_LOGIC; seg : out STD_LOGIC_VECTOR(7 downto 0) ); end D14_C2; architecture D14_C2 of D14_C2 is begin process(clk) variable dem:integer range 0 to 4; begin if (rising_edge(clk)) then if (dem=4) then dem:=0; else dem:=dem+1; end if; end if; case dem is when 0=> seg <="00000000"; when 1=> seg <="10000001"; when 2=> seg <="11000011"; when 3=> seg <="11100111"; when 4=> seg <="11111111"; when others=> seg <="XXXXXXXX"; end case; end process; end D14_C2; -- clk=5Mhz;
apache-2.0
6a96471f769e09af1b419ecb04e36ec2
0.621622
2.654709
false
false
false
false
TUM-LIS/faultify
software/host/davester_combinational_extractor/b14.vhd
1
20,464
-- -- ITC99 Benchmark -- Downloaded from http://www.cad.polito.it/tools/itc99.html -- -- Copyright (C) 1999 -- Fulvio Corno, Matteo Sonze Reorda, Giovanni Squillero -- Politecnico di Torino -- -- This source file may be used and distributed without restriction -- provided that this copyright statement is not removed from the -- file and that any derivative work contains the original copyright -- notice and the associated disclaimer. -- -- This source file is free software; you can redistribute it and/or -- modify it under the terms of the GNU General Public License as -- published by the Free Software Foundation. -- -- This source is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this source; if not, download it from -- http://www.gnu.org/copyleft/gpl.html -- -- entity b14 is port ( clock, reset : in bit; addr : out integer range 2**20 - 1 downto 0; datai : in integer; datao : out integer; rd, wr : out bit ); end b14; architecture BEHAV of b14 is begin process(clock, reset) variable reg0 : integer; variable reg1 : integer; variable reg2 : integer; variable reg3 : integer; variable B : bit; variable MAR : integer range 2**20 - 1 downto 0; variable MBR : integer; variable mf : integer range 2**2 - 1 downto 0; variable df : integer range 2**3 - 1 downto 0; variable cf : integer range 1 downto 0; variable ff : integer range 2**4 - 1 downto 0; variable tail : integer range 2**20 - 1 downto 0; variable IR : integer; variable state : integer range 1 downto 0; variable r, m, t : integer; variable d : integer; variable temp : integer; variable s : integer range 3 downto 0; constant FETCH : integer := 0; constant EXEC : integer := 1; begin if reset = '1' then MAR := 0; MBR := 0; IR := 0; d := 0; r := 0; m := 0; s := 0; temp := 0; mf := 0; df := 0; ff := 0; cf := 0; tail := 0; b := '0'; reg0 := 0; reg1 := 0; reg2 := 0; reg3 := 0; addr <= 0; rd <= '0'; wr <= '0'; datao <= 0; state := FETCH; elsif clock'event and clock = '1' then rd <= '0'; wr <= '0'; case state is when FETCH => MAR := reg3 mod 2**20; addr <= MAR; rd <= '1'; MBR := datai; IR := MBR; state := EXEC; when EXEC => if IR < 0 then IR := -IR; end if; mf := (IR / 2**27) mod 4; df := (IR / 2**24) mod 2**3; ff := (IR / 2**19) mod 2**4; cf := (IR / 2**23) mod 2; tail := IR mod 2**20; reg3 := ((reg3 mod 2**29)+ 8); s := (IR/2**29) mod 4; case s is when 0 => r := reg0; when 1 => r := reg1; when 2 => r := reg2; when 3 => r := reg3; end case; case cf is when 1 => case mf is when 0 => m := tail; when 1 => m := datai; addr <= tail; rd <= '1'; when 2 => addr <= (tail + reg1) mod 2**20; rd <= '1'; m := datai; when 3 => addr <= (tail + reg2) mod 2**20; rd <= '1'; m := datai; end case; case ff is when 0 => if r < m then B := '1'; else B := '0'; end if; when 1 => if not(r < m) then B := '1'; else B := '0'; end if; when 2 => if r = m then B := '1'; else B := '0'; end if; when 3 => if not(r = m) then B := '1'; else B := '0'; end if; when 4 => if not(r > m) then B := '1'; else B := '0'; end if; when 5 => if r > m then B := '1'; else B := '0'; end if; when 6 => if r > 2**30 - 1 then r := r - 2**30; end if; if r < m then B := '1'; else B := '0'; end if; when 7 => if r > 2**30 - 1 then r := r - 2**30; end if; if not(r < m) then B := '1'; else B := '0'; end if; when 8 => if (r < m) or (B = '1') then B := '1'; else B := '0'; end if; when 9 => if not(r < m) or (B = '1') then B := '1'; else B := '0'; end if; when 10 => if (r = m) or (B = '1') then B := '1'; else B := '0'; end if; when 11 => if not(r = m) or (B = '1') then B := '1'; else B := '0'; end if; when 12 => if not(r > m) or (B = '1') then B := '1'; else B := '0'; end if; when 13 => if (r > m) or (B = '1') then B := '1'; else B := '0'; end if; when 14 => if r > 2**30 - 1 then r := r - 2**30; end if; if (r < m) or (B = '1') then B := '1'; else B := '0'; end if; when 15 => if r > 2**30 - 1 then r := r - 2**30; end if; if not(r < m) or (B = '1') then B := '1'; else B := '0'; end if; end case; when 0 => if not(df = 7) then if df = 5 then if not(B) = '1' then d := 3; end if; elsif df = 4 then if B = '1' then d := 3; end if; elsif df = 3 then d := 3; elsif df = 2 then d := 2; elsif df = 1 then d := 1; elsif df = 0 then d := 0; end if; case ff is when 0 => case mf is when 0 => m := tail; when 1 => m := datai; addr <= tail; rd <= '1'; when 2 => addr <= (tail + reg1) mod 2**20; rd <= '1'; m := datai; when 3 => addr <= (tail + reg2) mod 2**20; rd <= '1'; m := datai; end case; t := 0; case d is when 0 => reg0 := t - m; when 1 => reg1 := t - m; when 2 => reg2 := t - m; when 3 => reg3 := t - m; when others => null; end case; when 1 => case mf is when 0 => m := tail; when 1 => m := datai; addr <= tail; rd <= '1'; when 2 => addr <= (tail + reg1) mod 2**20; rd <= '1'; m := datai; when 3 => addr <= (tail + reg2) mod 2**20; rd <= '1'; m := datai; end case; reg2 := reg3; reg3 := m; when 2 => case mf is when 0 => m := tail; when 1 => m := datai; addr <= tail; rd <= '1'; when 2 => addr <= (tail + reg1) mod 2**20; rd <= '1'; m := datai; when 3 => addr <= (tail + reg2) mod 2**20; rd <= '1'; m := datai; end case; case d is when 0 => reg0 := m; when 1 => reg1 := m; when 2 => reg2 := m; when 3 => reg3 := m; when others => null; end case; when 3 => case mf is when 0 => m := tail; when 1 => m := datai; addr <= tail; rd <= '1'; when 2 => addr <= (tail + reg1) mod 2**20; rd <= '1'; m := datai; when 3 => addr <= (tail + reg2) mod 2**20; rd <= '1'; m := datai; end case; case d is when 0 => reg0 := m; when 1 => reg1 := m; when 2 => reg2 := m; when 3 => reg3 := m; when others => null; end case; when 4 => case mf is when 0 => m := tail; when 1 => m := datai; addr <= tail; rd <= '1'; when 2 => addr <= (tail + reg1) mod 2**20; rd <= '1'; m := datai; when 3 => addr <= (tail + reg2) mod 2**20; rd <= '1'; m := datai; end case; case d is when 0 => reg0 := (r + m) mod 2**30; when 1 => reg1 := (r + m) mod 2**30; when 2 => reg2 := (r + m) mod 2**30; when 3 => reg3 := (r + m) mod 2**30; when others => null; end case; when 5 => case mf is when 0 => m := tail; when 1 => m := datai; addr <= tail; rd <= '1'; when 2 => addr <= (tail + reg1) mod 2**20; rd <= '1'; m := datai; when 3 => addr <= (tail + reg2) mod 2**20; rd <= '1'; m := datai; end case; case d is when 0 => reg0 := (r + m) mod 2**30; when 1 => reg1 := (r + m) mod 2**30; when 2 => reg2 := (r + m) mod 2**30; when 3 => reg3 := (r + m) mod 2**30; when others => null; end case; when 6 => case mf is when 0 => m := tail; when 1 => m := datai; addr <= tail; rd <= '1'; when 2 => addr <= (tail + reg1) mod 2**20; rd <= '1'; m := datai; when 3 => addr <= (tail + reg2) mod 2**20; rd <= '1'; m := datai; end case; case d is when 0 => reg0 := (r - m) mod 2**30; when 1 => reg1 := (r - m) mod 2**30; when 2 => reg2 := (r - m) mod 2**30; when 3 => reg3 := (r - m) mod 2**30; when others => null; end case; when 7 => case mf is when 0 => m := tail; when 1 => m := datai; addr <= tail; rd <= '1'; when 2 => addr <= (tail + reg1) mod 2**20; rd <= '1'; m := datai; when 3 => addr <= (tail + reg2) mod 2**20; rd <= '1'; m := datai; end case; case d is when 0 => reg0 := (r - m) mod 2**30; when 1 => reg1 := (r - m) mod 2**30; when 2 => reg2 := (r - m) mod 2**30; when 3 => reg3 := (r - m) mod 2**30; when others => null; end case; when 8 => case mf is when 0 => m := tail; when 1 => m := datai; addr <= tail; rd <= '1'; when 2 => addr <= (tail + reg1) mod 2**20; rd <= '1'; m := datai; when 3 => addr <= (tail + reg2) mod 2**20; rd <= '1'; m := datai; end case; case d is when 0 => reg0 := (r + m) mod 2**30; when 1 => reg1 := (r + m) mod 2**30; when 2 => reg2 := (r + m) mod 2**30; when 3 => reg3 := (r + m) mod 2**30; when others => null; end case; when 9 => case mf is when 0 => m := tail; when 1 => m := datai; addr <= tail; rd <= '1'; when 2 => addr <= (tail + reg1) mod 2**20; rd <= '1'; m := datai; when 3 => addr <= (tail + reg2) mod 2**20; rd <= '1'; m := datai; end case; case d is when 0 => reg0 := (r - m) mod 2**30; when 1 => reg1 := (r - m) mod 2**30; when 2 => reg2 := (r - m) mod 2**30; when 3 => reg3 := (r - m) mod 2**30; when others => null; end case; when 10 => case mf is when 0 => m := tail; when 1 => m := datai; addr <= tail; rd <= '1'; when 2 => addr <= (tail + reg1) mod 2**20; rd <= '1'; m := datai; when 3 => addr <= (tail + reg2) mod 2**20; rd <= '1'; m := datai; end case; case d is when 0 => reg0 := (r + m) mod 2**30; when 1 => reg1 := (r + m) mod 2**30; when 2 => reg2 := (r + m) mod 2**30; when 3 => reg3 := (r + m) mod 2**30; when others => null; end case; when 11 => case mf is when 0 => m := tail; when 1 => m := datai; addr <= tail; rd <= '1'; when 2 => addr <= (tail + reg1) mod 2**20; rd <= '1'; m := datai; when 3 => addr <= (tail + reg2) mod 2**20; rd <= '1'; m := datai; end case; case d is when 0 => reg0 := (r - m) mod 2**30; when 1 => reg1 := (r - m) mod 2**30; when 2 => reg2 := (r - m) mod 2**30; when 3 => reg3 := (r - m) mod 2**30; when others => null; end case; when 12 => case mf is when 0 => t := r / 2; when 1 => t := r / 2; if B = '1' then t := t mod 2**29; end if; when 2 => t := (r mod 2**29) * 2; when 3 => t := (r mod 2**29) * 2; if t > 2**30 - 1 then B := '1'; else B := '0'; end if; when others => null; end case; case d is when 0 => reg0 := t; when 1 => reg1 := t; when 2 => reg2 := t; when 3 => reg3 := t; when others => null; end case; when 13 | 14 | 15 => null; end case; elsif df = 7 then case mf is when 0 => m := tail; when 1 => m := tail; when 2 => m := (reg1 mod 2**20) + (tail mod 2**20); when 3 => m := (reg2 mod 2**20) + (tail mod 2**20); end case; -- addr <= m; addr <= m mod 2*20; -- removed (!)fs020699 wr <= '1'; datao <= r; end if; end case; state := FETCH; end case; end if; end process; end BEHAV;
gpl-2.0
5b9eab48c86ce2a58b5ac48ee33cadf6
0.264269
4.938224
false
false
false
false
SoCdesign/EHA
RTL/Immortal_Chip/Channel_32_bit_with_dominant_checkers.vhd
1
19,619
--Copyright (C) 2016 Siavoosh Payandeh Azad library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity router_channel is generic ( DATA_WIDTH: integer := 32; current_address : integer := 5; Rxy_rst : integer := 60; Cx_rst : integer := 15; NoC_size: integer := 4 ); port ( reset, clk: in std_logic; DCTS : in std_logic; DRTS : in std_logic; RTS : out std_logic; CTS : out std_logic; flit_type : in std_logic_vector(2 downto 0); destination_address : in std_logic_vector(NoC_size-1 downto 0); Grant_N_in , Grant_E_in , Grant_W_in , Grant_S_in , Grant_L_in : in std_logic; Grant_N_out, Grant_E_out, Grant_W_out, Grant_S_out, Grant_L_out: out std_logic; Req_N_in , Req_E_in , Req_W_in , Req_S_in , Req_L_in :in std_logic; Req_N_out , Req_E_out, Req_W_out, Req_S_out, Req_L_out:out std_logic; read_pointer_out, write_pointer_out: out std_logic_vector(3 downto 0); write_en_out :out std_logic; Xbar_sel: out std_logic_vector(4 downto 0) ); end router_channel; architecture behavior of router_channel is COMPONENT FIFO is generic ( DATA_WIDTH: integer := 32 ); port ( reset: in std_logic; clk: in std_logic; DRTS: in std_logic; read_en_N : in std_logic; read_en_E : in std_logic; read_en_W : in std_logic; read_en_S : in std_logic; read_en_L : in std_logic; CTS: out std_logic; empty_out: out std_logic; read_pointer_out, write_pointer_out: out std_logic_vector(3 downto 0); write_en_out :out std_logic; -- Checker outputs err_write_en_write_pointer, err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full, err_read_pointer_increment, err_read_pointer_not_increment, --err_CTS_in, err_write_en, err_not_CTS_in, --err_not_write_en, err_read_en_mismatch : out std_logic ); end COMPONENT; COMPONENT Arbiter port ( reset: in std_logic; clk: in std_logic; Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules DCTS: in std_logic; -- Getting the CTS signal from the input FIFO of the next router/NI (for hand-shaking) Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot) Xbar_sel : out std_logic_vector(4 downto 0); -- select lines for XBAR RTS: out std_logic; -- Valid output which is sent to the next router/NI to specify that the data on the output port is valid -- Checker outputs err_state_IDLE_xbar, err_state_not_IDLE_xbar, err_state_IDLE_RTS_FF_in, err_state_not_IDLE_RTS_FF_RTS_FF_in, err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in, err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in, err_RTS_FF_not_DCTS_state_state_in, err_not_RTS_FF_state_in_next_state, err_RTS_FF_DCTS_state_in_next_state, err_not_DCTS_Grants, err_DCTS_not_RTS_FF_Grants, err_DCTS_RTS_FF_IDLE_Grants, err_DCTS_RTS_FF_not_IDLE_Grants_onehot, err_Requests_next_state_IDLE, err_IDLE_Req_L, err_Local_Req_L, err_North_Req_N, --err_East_Req_E, --err_West_Req_W, --err_South_Req_S, err_IDLE_Req_N, err_Local_Req_N, --err_North_Req_E, --err_East_Req_W, --err_West_Req_S, err_South_Req_L, --err_IDLE_Req_E, --err_Local_Req_E, --err_North_Req_W, --err_East_Req_S, err_West_Req_L, err_South_Req_N, --err_IDLE_Req_W, --err_Local_Req_W, --err_North_Req_S, err_East_Req_L, err_West_Req_N, --err_South_Req_E, --err_IDLE_Req_S, --err_Local_Req_S, --err_North_Req_L, err_East_Req_N, --err_West_Req_E, --err_South_Req_W, err_next_state_onehot, err_state_in_onehot, --err_DCTS_RTS_FF_state_Grant_L, --err_DCTS_RTS_FF_state_Grant_N, --err_DCTS_RTS_FF_state_Grant_E, --err_DCTS_RTS_FF_state_Grant_W, --err_DCTS_RTS_FF_state_Grant_S, err_state_north_xbar_sel, err_state_east_xbar_sel, err_state_west_xbar_sel, err_state_south_xbar_sel : out std_logic --err_state_local_xbar_sel : out std_logic ); end COMPONENT; COMPONENT LBDR is generic ( cur_addr_rst: integer := 5; Rxy_rst: integer := 60; Cx_rst: integer := 15; NoC_size: integer := 4 ); port ( reset: in std_logic; clk: in std_logic; empty: in std_logic; flit_type: in std_logic_vector(2 downto 0); dst_addr: in std_logic_vector(NoC_size-1 downto 0); Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic; -- Checker outputs --err_header_not_empty_Requests_in_onehot, err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero, err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_not_Req_L_in, err_dst_addr_cur_addr_Req_L_in, err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in : out std_logic ); end COMPONENT; -- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y signal empty: std_logic; -- Signals related to Checkers -- LBDR Checkers signals -- North signal N_err_header_empty_Requests_FF_Requests_in, N_err_tail_Requests_in_all_zero, N_err_header_tail_Requests_FF_Requests_in, N_err_dst_addr_cur_addr_N1, N_err_dst_addr_cur_addr_not_N1, N_err_dst_addr_cur_addr_E1, N_err_dst_addr_cur_addr_not_E1, N_err_dst_addr_cur_addr_W1, N_err_dst_addr_cur_addr_not_W1, N_err_dst_addr_cur_addr_S1, N_err_dst_addr_cur_addr_not_S1, N_err_dst_addr_cur_addr_not_Req_L_in, N_err_dst_addr_cur_addr_Req_L_in, N_err_header_not_empty_Req_N_in, N_err_header_not_empty_Req_E_in, N_err_header_not_empty_Req_W_in, N_err_header_not_empty_Req_S_in : std_logic; -- Arbiter Checkers signals -- North signal N_err_state_IDLE_xbar, N_err_state_not_IDLE_xbar, N_err_state_IDLE_RTS_FF_in, N_err_state_not_IDLE_RTS_FF_RTS_FF_in, N_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in, N_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in, N_err_RTS_FF_not_DCTS_state_state_in, N_err_not_RTS_FF_state_in_next_state, N_err_RTS_FF_DCTS_state_in_next_state, N_err_not_DCTS_Grants, N_err_DCTS_not_RTS_FF_Grants, N_err_DCTS_RTS_FF_IDLE_Grants, N_err_DCTS_RTS_FF_not_IDLE_Grants_onehot, N_err_Requests_next_state_IDLE, N_err_IDLE_Req_L, N_err_Local_Req_L, N_err_North_Req_N, N_err_IDLE_Req_N, N_err_Local_Req_N, N_err_South_Req_L, N_err_West_Req_L, N_err_South_Req_N, N_err_East_Req_L, N_err_West_Req_N, N_err_East_Req_N, N_err_next_state_onehot, N_err_state_in_onehot, N_err_state_north_xbar_sel, N_err_state_east_xbar_sel, N_err_state_west_xbar_sel, N_err_state_south_xbar_sel : std_logic; -- FIFO Control Part Checkers signals -- North signal N_err_write_en_write_pointer, N_err_not_write_en_write_pointer, N_err_read_pointer_write_pointer_not_empty, N_err_read_pointer_write_pointer_empty, N_err_read_pointer_write_pointer_not_full, N_err_read_pointer_write_pointer_full, N_err_read_pointer_increment, N_err_read_pointer_not_increment, N_err_write_en, N_err_not_CTS_in, N_err_read_en_mismatch : std_logic; -- Error Signals for each module (ORed combination of checker outputs) signal N_LBDR_checkers_output: std_logic; signal N_Arbiter_checkers_output: std_logic; signal N_FIFO_control_part_checkers_output: std_logic; begin -- OR of checker outputs for each module (corresponding to each direction) -- This is used for feeding the checker outputs to shift registers (later) -- LBDR N_LBDR_checkers_output <= N_err_header_empty_Requests_FF_Requests_in or N_err_tail_Requests_in_all_zero or N_err_header_tail_Requests_FF_Requests_in or N_err_dst_addr_cur_addr_N1 or N_err_dst_addr_cur_addr_not_N1 or N_err_dst_addr_cur_addr_E1 or N_err_dst_addr_cur_addr_not_E1 or N_err_dst_addr_cur_addr_W1 or N_err_dst_addr_cur_addr_not_W1 or N_err_dst_addr_cur_addr_S1 or N_err_dst_addr_cur_addr_not_S1 or N_err_dst_addr_cur_addr_not_Req_L_in or N_err_dst_addr_cur_addr_Req_L_in or N_err_header_not_empty_Req_N_in or N_err_header_not_empty_Req_E_in or N_err_header_not_empty_Req_W_in or N_err_header_not_empty_Req_S_in; -- Arbiter N_Arbiter_checkers_output <= N_err_state_IDLE_xbar or N_err_state_not_IDLE_xbar or N_err_state_IDLE_RTS_FF_in or N_err_state_not_IDLE_RTS_FF_RTS_FF_in or N_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in or N_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in or N_err_RTS_FF_not_DCTS_state_state_in or N_err_not_RTS_FF_state_in_next_state or N_err_RTS_FF_DCTS_state_in_next_state or N_err_not_DCTS_Grants or N_err_DCTS_not_RTS_FF_Grants or N_err_DCTS_RTS_FF_IDLE_Grants or N_err_DCTS_RTS_FF_not_IDLE_Grants_onehot or N_err_Requests_next_state_IDLE or N_err_IDLE_Req_L or N_err_Local_Req_L or N_err_North_Req_N or N_err_IDLE_Req_N or N_err_Local_Req_N or N_err_South_Req_L or N_err_West_Req_L or N_err_South_Req_N or N_err_East_Req_L or N_err_West_Req_N or N_err_East_Req_N or N_err_next_state_onehot or N_err_state_in_onehot or N_err_state_north_xbar_sel or N_err_state_east_xbar_sel or N_err_state_west_xbar_sel or N_err_state_south_xbar_sel; -- FIFO Control Part N_FIFO_control_part_checkers_output <= N_err_write_en_write_pointer or N_err_not_write_en_write_pointer or N_err_read_pointer_write_pointer_not_empty or N_err_read_pointer_write_pointer_empty or N_err_read_pointer_write_pointer_not_full or N_err_read_pointer_write_pointer_full or N_err_read_pointer_increment or N_err_read_pointer_not_increment or N_err_write_en or N_err_not_CTS_in or N_err_read_en_mismatch; ------------------------------------------------------------------------------------------------------------------------------ -- all the FIFOs FIFO_unit: FIFO generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (reset => reset, clk => clk, DRTS => DRTS, read_en_N => Grant_N_in, read_en_E =>Grant_E_in, read_en_W =>Grant_W_in, read_en_S =>Grant_S_in, read_en_L =>Grant_L_in, CTS => CTS, empty_out => empty, read_pointer_out => read_pointer_out, write_pointer_out => write_pointer_out, write_en_out => write_en_out, err_write_en_write_pointer => N_err_write_en_write_pointer, err_not_write_en_write_pointer => N_err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty => N_err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty => N_err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full => N_err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full => N_err_read_pointer_write_pointer_full, err_read_pointer_increment => N_err_read_pointer_increment, err_read_pointer_not_increment => N_err_read_pointer_not_increment, err_write_en => N_err_write_en, err_not_CTS_in => N_err_not_CTS_in, err_read_en_mismatch => N_err_read_en_mismatch ); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- all the LBDRs LBDR_unit: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty, flit_type => flit_type, dst_addr=> destination_address, Req_N=> Req_N_out, Req_E=>Req_E_out, Req_W=>Req_W_out, Req_S=>Req_S_out, Req_L=>Req_L_out, err_header_empty_Requests_FF_Requests_in => N_err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero => N_err_tail_Requests_in_all_zero, err_header_tail_Requests_FF_Requests_in => N_err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1 => N_err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1 => N_err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1 => N_err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1 => N_err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1 => N_err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1 => N_err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1 => N_err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1 => N_err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_not_Req_L_in => N_err_dst_addr_cur_addr_not_Req_L_in, err_dst_addr_cur_addr_Req_L_in => N_err_dst_addr_cur_addr_Req_L_in, err_header_not_empty_Req_N_in => N_err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in => N_err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in => N_err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in => N_err_header_not_empty_Req_S_in ); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- all the Arbiters Arbiter_unit: Arbiter PORT MAP (reset => reset, clk => clk, Req_N => Req_N_in , Req_E => Req_E_in, Req_W => Req_W_in, Req_S => Req_S_in, Req_L => Req_L_in, DCTS => DCTS, Grant_N => Grant_N_out, Grant_E => Grant_E_out, Grant_W => Grant_W_out, Grant_S => Grant_S_out, Grant_L => Grant_L_out, Xbar_sel => Xbar_sel, RTS => RTS, err_state_IDLE_xbar => N_err_state_IDLE_xbar , err_state_not_IDLE_xbar => N_err_state_not_IDLE_xbar , err_state_IDLE_RTS_FF_in => N_err_state_IDLE_RTS_FF_in , err_state_not_IDLE_RTS_FF_RTS_FF_in => N_err_state_not_IDLE_RTS_FF_RTS_FF_in , err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => N_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in , err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => N_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in , err_RTS_FF_not_DCTS_state_state_in => N_err_RTS_FF_not_DCTS_state_state_in , err_not_RTS_FF_state_in_next_state => N_err_not_RTS_FF_state_in_next_state , err_RTS_FF_DCTS_state_in_next_state => N_err_RTS_FF_DCTS_state_in_next_state , err_not_DCTS_Grants => N_err_not_DCTS_Grants , err_DCTS_not_RTS_FF_Grants => N_err_DCTS_not_RTS_FF_Grants , err_DCTS_RTS_FF_IDLE_Grants => N_err_DCTS_RTS_FF_IDLE_Grants , err_DCTS_RTS_FF_not_IDLE_Grants_onehot => N_err_DCTS_RTS_FF_not_IDLE_Grants_onehot , err_Requests_next_state_IDLE => N_err_Requests_next_state_IDLE , err_IDLE_Req_L => N_err_IDLE_Req_L , err_Local_Req_L => N_err_Local_Req_L , err_North_Req_N => N_err_North_Req_N , err_IDLE_Req_N => N_err_IDLE_Req_N , err_Local_Req_N => N_err_Local_Req_N , err_South_Req_L => N_err_South_Req_L , err_West_Req_L => N_err_West_Req_L , err_South_Req_N => N_err_South_Req_N , err_East_Req_L => N_err_East_Req_L , err_West_Req_N => N_err_West_Req_N , err_East_Req_N => N_err_East_Req_N , err_next_state_onehot => N_err_next_state_onehot , err_state_in_onehot => N_err_state_in_onehot , err_state_north_xbar_sel => N_err_state_north_xbar_sel , err_state_east_xbar_sel => N_err_state_east_xbar_sel , err_state_west_xbar_sel => N_err_state_west_xbar_sel , err_state_south_xbar_sel => N_err_state_south_xbar_sel ); end;
gpl-3.0
df734ef983dd36cabd483c74817e8dec
0.508436
3.278028
false
false
false
false
SoCdesign/EHA
RTL/Hand_Shaking/Checkers/Modules_with_checkers_integrated/All_checkers/LBDR_with_checkers/LBDR_checkers.vhd
1
7,341
library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.ALL; entity LBDR_checkers is generic ( cur_addr_rst: integer := 5; NoC_size: integer := 4 ); port ( empty: in std_logic; flit_type: in std_logic_vector(2 downto 0); Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic; Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic; N1_out, E1_out, W1_out, S1_out: in std_logic; dst_addr: in std_logic_vector(NoC_size-1 downto 0); -- Checker outputs err_header_not_empty_Requests_in_onehot, err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero, err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_not_Req_L_in, err_dst_addr_cur_addr_Req_L_in, err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in : out std_logic ); end LBDR_checkers; architecture behavior of LBDR_checkers is signal cur_addr: std_logic_vector(NoC_size-1 downto 0); signal Requests_FF: std_logic_vector(4 downto 0); signal Requests_in: std_logic_vector(4 downto 0); begin cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length)); Requests_FF <= Req_N_FF & Req_E_FF & Req_W_FF & Req_S_FF & Req_L_FF; Requests_in <= Req_N_in & Req_E_in & Req_W_in & Req_S_in & Req_L_in; -- Implementing checkers in form of concurrent assignments (combinational assertions) process (flit_type, empty, Requests_in) begin if (flit_type = "001" and empty = '0' and Requests_in /= "00001" and Requests_in /= "00010" and Requests_in /= "00100" and Requests_in /= "01000" and Requests_in /= "10000") then err_header_not_empty_Requests_in_onehot <= '1'; else err_header_not_empty_Requests_in_onehot <= '0'; end if; end process; process (flit_type, empty, Requests_FF, Requests_in) begin if (flit_type = "001" and empty = '1' and Requests_FF /= Requests_in) then err_header_empty_Requests_FF_Requests_in <= '1'; else err_header_empty_Requests_FF_Requests_in <= '0'; end if; end process; process (flit_type, Requests_in) begin if (flit_type = "100" and Requests_in /= "00000") then err_tail_Requests_in_all_zero <= '1'; else err_tail_Requests_in_all_zero <= '0'; end if; end process; process (flit_type, Requests_FF, Requests_in) begin if (flit_type /= "001" and flit_type /= "100" and Requests_FF /= Requests_in) then err_header_tail_Requests_FF_Requests_in <= '1'; else err_header_tail_Requests_FF_Requests_in <= '0'; end if; end process; process (cur_addr, dst_addr, N1_out) begin if ( dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) and N1_out = '0') then err_dst_addr_cur_addr_N1 <= '1'; else err_dst_addr_cur_addr_N1 <= '0'; end if; end process; process (cur_addr, dst_addr, N1_out) begin if ( dst_addr(NoC_size-1 downto NoC_size/2) >= cur_addr(NoC_size-1 downto NoC_size/2) and N1_out = '1') then err_dst_addr_cur_addr_not_N1 <= '1'; else err_dst_addr_cur_addr_not_N1 <= '0'; end if; end process; process (cur_addr, dst_addr, E1_out) begin if ( cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) and E1_out = '0') then err_dst_addr_cur_addr_E1 <= '1'; else err_dst_addr_cur_addr_E1 <= '0'; end if; end process; process (cur_addr, dst_addr, E1_out) begin if ( cur_addr((NoC_size/2)-1 downto 0) >= dst_addr((NoC_size/2)-1 downto 0) and E1_out = '1') then err_dst_addr_cur_addr_not_E1 <= '1'; else err_dst_addr_cur_addr_not_E1 <= '0'; end if; end process; process (cur_addr, dst_addr, W1_out) begin if ( dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) and W1_out = '0') then err_dst_addr_cur_addr_W1 <= '1'; else err_dst_addr_cur_addr_W1 <= '0'; end if; end process; process (cur_addr, dst_addr, W1_out) begin if ( dst_addr((NoC_size/2)-1 downto 0) >= cur_addr((NoC_size/2)-1 downto 0) and W1_out = '1') then err_dst_addr_cur_addr_not_W1 <= '1'; else err_dst_addr_cur_addr_not_W1 <= '0'; end if; end process; process (cur_addr, dst_addr, S1_out) begin if ( cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) and S1_out = '0') then err_dst_addr_cur_addr_S1 <= '1'; else err_dst_addr_cur_addr_S1 <= '0'; end if; end process; process (cur_addr, dst_addr, S1_out) begin if ( cur_addr(NoC_size-1 downto NoC_size/2) >= dst_addr(NoC_size-1 downto NoC_size/2) and S1_out = '1') then err_dst_addr_cur_addr_not_S1 <= '1'; else err_dst_addr_cur_addr_not_S1 <= '0'; end if; end process; process (flit_type, empty, N1_out, E1_out, W1_out, S1_out, Req_L_in) begin if ( flit_type = "001" and empty = '0' and Req_L_in /= (not N1_out and not E1_out and not W1_out and not S1_out) ) then err_dst_addr_cur_addr_not_Req_L_in <= '1'; else err_dst_addr_cur_addr_not_Req_L_in <= '0'; end if; end process; process (flit_type, empty, cur_addr, dst_addr, Req_L_in) begin if ( flit_type = "001" and empty = '0' and cur_addr /= dst_addr and Req_L_in = '1') then err_dst_addr_cur_addr_Req_L_in <= '1'; else err_dst_addr_cur_addr_Req_L_in <= '0'; end if; end process; process (flit_type, empty, Req_N_in, N1_out, E1_out, W1_out) begin if ( flit_type = "001" and empty = '0' and Req_N_in /= (N1_out and not E1_out and not W1_out) ) then err_header_not_empty_Req_N_in <= '1'; else err_header_not_empty_Req_N_in <= '0'; end if; end process; process (flit_type, empty, Req_E_in, N1_out, E1_out, S1_out) begin if ( flit_type = "001" and empty = '0' and Req_E_in /= ((E1_out and not N1_out and not S1_out) or (E1_out and N1_out) or (E1_out and S1_out)) ) then err_header_not_empty_Req_E_in <= '1'; else err_header_not_empty_Req_E_in <= '0'; end if; end process; process (flit_type, empty, Req_W_in, N1_out, W1_out, S1_out) begin if ( flit_type = "001" and empty = '0' and Req_W_in /= ((W1_out and not N1_out and not S1_out) or (W1_out and N1_out) or (W1_out and S1_out)) ) then err_header_not_empty_Req_W_in <= '1'; else err_header_not_empty_Req_W_in <= '0'; end if; end process; process (flit_type, empty, Req_S_in, E1_out, W1_out, S1_out) begin if ( flit_type = "001" and empty = '0' and Req_S_in /= (S1_out and not E1_out and not W1_out) ) then err_header_not_empty_Req_S_in <= '1'; else err_header_not_empty_Req_S_in <= '0'; end if; end process; end behavior;
gpl-3.0
14e07746083081f8da955ed58328471d
0.594606
2.668484
false
false
false
false
JarrettR/FPGA-Cryptoparty
FPGA/hdl/sim_prf.vhd
1
4,587
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 12/26/2016 11:44:06 PM -- Design Name: -- Module Name: sim_prf - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use work.sha1_pkg.all; entity sim_prf is end sim_prf; architecture Behavioral of sim_prf is component prf_main is port( clk_i : in std_ulogic; rst_i : in std_ulogic; load_i : in std_ulogic; pmk_i : in w_input; anonce_dat : in nonce_data; cnonce_dat : in nonce_data; amac_dat : in mac_data; cmac_dat : in mac_data; ptk_dat_o : out ptk_data; ptk_valid_o : out std_ulogic ); end component; signal valid : std_ulogic; signal load : std_ulogic := '0'; signal clk_i : std_ulogic := '0'; signal rst_i : std_ulogic := '0'; signal pmk : w_input; signal anonce : nonce_data; signal cnonce : nonce_data; signal amac_dat : mac_data; signal cmac_dat : mac_data; signal ptk : ptk_data; --pmk: 5df920b5481ed70538dd5fd02423d7e2522205feeebb974cad08a52b5613ede2 --a: 5061697277697365206b657920657870616e73696f6e --b: 000b86c2a4850013ce5598efae12a150652e9bc22063720c5081e9eb74077fb19fffe871dc4ca1e6f448af85e8dfa16b8769957d8249a4ec68d2b7641d3782162ef0dc37b014cc48343e8dd2 --r: 5e9805e89cb0e84b45e5f9e4a1a80d9d9958c24e --r: 5e9805e89cb0e84b45e5f9e4a1a80d9d9958c24e2b5ca71661334a890814f53e1d035e8beb4f8361 --r: 5e9805e89cb0e84b45e5f9e4a1a80d9d9958c24e2b5ca71661334a890814f53e1d035e8beb4f83611dc93e2657cecf69a3651bc4fca5880ce9081345 --r: 5e9805e89cb0e84b45e5f9e4a1a80d9d9958c24e2b5ca71661334a890814f53e1d035e8beb4f83611dc93e2657cecf69a3651bc4fca5880ce9081345c5411d489313b29e4aaf287d5231a342b777a67a --ptk: 5e9805e89cb0e84b45e5f9e4a1a80d9d signal i: integer range 0 to 65535; constant clock_period : time := 1 ns; begin prf: prf_main port map (clk_i,rst_i,load,pmk,anonce,cnonce,amac_dat,cmac_dat,ptk,valid); stim_proc: process begin rst_i <= '0'; i <= 0; load <= '0'; --Ordinally will come from PBKDF2 --5df920b5481ed70538dd5fd02423d7e2 522205feeebb974cad08a52b5613ede2 pmk <= (X"5df920b5",X"481ed705",X"38dd5fd0",X"2423d7e2", X"522205fe",X"eebb974c",X"ad08a52b",X"5613ede2", others=>(X"00000000")); --b = min(apMac, cMac) + max(apMac, cMac) + min(apNonce, cNonce) + max(apNonce, cNonce) --We're assuming that min/max will be calculated host-side --Comes directly from handshake on host --000b86c2a485 amac_dat <= (X"00",X"0b",X"86",X"c2",X"a4",X"85"); --0013ce5598ef cmac_dat <= (X"00",X"13",X"ce",X"55",X"98",X"ef"); --ae12a150652e9bc22063720c5081e9eb 74077fb19fffe871dc4ca1e6f448af85 anonce <= (X"ae",X"12",X"a1",X"50",X"65",X"2e",X"9b",X"c2",X"20",X"63",X"72",X"0c",X"50",X"81",X"e9",X"eb", X"74",X"07",X"7f",X"b1",X"9f",X"ff",X"e8",X"71",X"dc",X"4c",X"a1",X"e6",X"f4",X"48",X"af",X"85"); --e8dfa16b8769957d8249a4ec68d2b764 1d3782162ef0dc37b014cc48343e8dd2 cnonce <= (X"e8",X"df",X"a1",X"6b",X"87",X"69",X"95",X"7d",X"82",X"49",X"a4",X"ec",X"68",X"d2",X"b7",X"64", X"1d",X"37",X"82",X"16",X"2e",X"f0",X"dc",X"37",X"b0",X"14",X"cc",X"48",X"34",X"3e",X"8d",X"d2"); wait until rising_edge(clk_i); rst_i <= '1'; wait until rising_edge(clk_i); rst_i <= '0'; wait until rising_edge(clk_i); load <= '1'; wait until rising_edge(clk_i); load <= '0'; wait until rising_edge(clk_i); while valid = '0' loop i <= i + 1; wait until rising_edge(clk_i); end loop; wait; end process; clock_process: process begin clk_i <= '0'; wait for clock_period/2; clk_i <= '1'; wait for clock_period/2; end process; end Behavioral;
gpl-3.0
385f9efecd53f041536bd415ac32810d
0.557663
2.679322
false
false
false
false
bruskajp/EE-316
Project2/Vivado_NexysBoard/project_2b/project_2b.srcs/sources_1/imports/Downloads/top_level.vhd
1
8,131
library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; entity top_level is port ( iReset : in std_logic; iClk : in std_logic; iCnt_en : in std_logic; iF_B : in std_logic; An_OUT : out std_logic_vector(7 downto 0); SevSeg_OUT : out std_logic_vector(7 downto 0); Tx : out std_logic; SCK : out std_logic; CSN : out std_logic; MOSI : out std_logic; SDA : inout std_logic; SCL : inout std_logic; high : out std_logic ); end top_level; architecture Structural of top_level is component clk_enabler is GENERIC ( CONSTANT cnt_max : integer := 99999999); port( clock : in std_logic; reset : in std_logic; clk_en : out std_logic ); end component; component sys_clk is GENERIC ( CONSTANT REF_CLK : integer := 50000000; -- 50.0 MHz CONSTANT OUT_CLK : integer := 10000000); -- 10.0 MHz PORT ( SIGNAL oCLK : INOUT std_logic; SIGNAL iCLK : IN std_logic; SIGNAL iRST_N : IN std_logic); end component; component Reset_Delay IS PORT ( SIGNAL iCLK : IN std_logic; SIGNAL oRESET : OUT std_logic ); end component; component univ_bin_counter is generic(N: integer := 4); port( clk, reset : in std_logic; syn_clr, en, up : in std_logic; load : in std_logic; clk_en : in std_logic; d : in std_logic_vector(N-1 downto 0); max : in unsigned(N-1 downto 0); min : in unsigned(N-1 downto 0); q : out std_logic_vector(N-1 downto 0) ); end component; component btn_debounce_toggle is GENERIC ( CONSTANT CNTR_MAX : std_logic_vector(15 downto 0)); --:=X"FFFF" Port ( BTN_I : in STD_LOGIC; CLK : in STD_LOGIC; BTN_O : out STD_LOGIC; TOGGLE_O : out STD_LOGIC); end component; component Nexys4_Display is Port ( HEX_IN : in STD_LOGIC_VECTOR (15 downto 0); iCLK : in STD_LOGIC; An_OUT : out STD_LOGIC_VECTOR (7 downto 0); SevSeg_OUT : out STD_LOGIC_VECTOR (7 downto 0)); end component; component TTL_Serial_Display is --generic ( --constant TTL_Driver: unsigned:= X"291E"); port( Hex_IN : in STD_LOGIC_VECTOR (15 downto 0); iCLK : in STD_LOGIC; Tx : out STD_LOGIC); end component; component SPI_Display is Port ( Hex_IN : in STD_LOGIC_VECTOR (15 downto 0); iCLK : in STD_LOGIC; MOSI : out STD_LOGIC; CSN : out STD_LOGIC; SCK : out STD_LOGIC); end component; COMPONENT blk_mem_LUT PORT ( clka : IN STD_LOGIC; ena : IN STD_LOGIC; addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END COMPONENT; COMPONENT interfacer PORT ( CLK : in std_logic; data_in : in std_logic_vector(15 downto 0) := x"0000"; sda : inout std_logic; scl : inout std_logic ); END COMPONENT; signal clk : std_logic; signal clk_enable : std_logic; signal reset, DelayReset : std_logic; signal DelayReset_n : std_logic; signal iReset_deb : std_logic; signal iCnt_en_toggle, iF_B_toggle : std_logic; signal oCOUNT : std_logic_vector(3 downto 0); signal hex : std_logic_vector(15 downto 0); begin high <= '1'; DelayReset <= reset; DelayReset_n <= not DelayReset; Inst_iCnt_en_debounce: btn_debounce_toggle generic map(CNTR_MAX => X"0009") -- For simulation: use CNTR_MAX => X"0009", else use X"FFFF" port map( BTN_I => iCnt_en, CLK => iCLK, BTN_O => open, TOGGLE_O => iCnt_en_toggle); Inst_iReset_debounce: btn_debounce_toggle generic map(CNTR_MAX => X"0009") -- For simulation: use CNTR_MAX => X"0009", else use X"FFFF" port map( BTN_I => iReset, CLK => iCLK, BTN_O => iReset_deb, TOGGLE_O => open); Inst_iF_B_debounce: btn_debounce_toggle generic map(CNTR_MAX => X"0009") -- For simulation: use CNTR_MAX => X"0009", else use X"FFFF"" port map( BTN_I => iF_B, CLK => iCLK, BTN_O => open, TOGGLE_O => iF_B_toggle); Inst_clk_Reset_Delay: Reset_Delay port map( iCLK => iCLK, oRESET => reset ); Inst_clk_enabler: clk_enabler generic map( cnt_max => 9999999 ) --*** -- For simulation: use cnt_max => 99 else use 9999999 (for 1 Hz counters) port map( clock => clk, -- output from sys_clk -- 10 MHz clock reset => iReset_deb, clk_en => clk_enable -- enable every 10,000th sys_clk edge ); Inst_Univ_Counter: univ_bin_counter generic map(N => 4) port map( clk => clk, reset => iReset_deb, syn_clr => DelayReset, en => iCnt_en_toggle, up => iF_B_toggle, load => '0', clk_en => clk_enable, d => (others => '0'), max => "1000", min => "0000", q => oCOUNT ); Inst_sys_clk: sys_clk generic map ( REF_CLK => 100000000, -- 100.0 MHz OUT_CLK => 10000000) -- 10.0 MHz port map ( oCLK => clk, iCLK => iCLK, iRST_N => DelayReset_n ); Inst_Hex_Counter: Nexys4_Display port map ( HEX_IN => hex, iCLK => clk, An_OUT => An_OUT, SevSeg_OUT => SevSeg_OUT ); Inst_TTL_Display: TTL_Serial_Display --generic map( --TTL_Driver => X"291E") Port map( Hex_IN => hex, iCLK => iClk, Tx => Tx); Inst_SPI_Display: SPI_Display Port map( Hex_IN => hex, iCLK => clk, MOSI => MOSI, CSN => CSN, SCK => SCK); your_instance_name : blk_mem_LUT PORT MAP ( clka => iCLK, ena => '1', addra => oCOUNT, douta => hex ); Inst_Interfacer : interfacer PORT MAP ( CLK => iCLK, data_in => hex, sda => SDA, scl => SCL ); end Structural;
gpl-3.0
1f3104ac9bd60358459eadaed7bd4aba
0.41803
4.108641
false
false
false
false
lnls-dig/dsp-cores
hdl/modules/cic/cic_dual.vhd
1
6,508
------------------------------------------------------------------------------- -- Title : Dual cic filters -- Project : ------------------------------------------------------------------------------- -- File : cic_dual.vhd -- Author : aylons <aylons@LNLS190> -- Company : -- Created : 2014-05-26 -- Last update: 2015-10-15 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: Dual cic filters with a commom strobe for I/Q decimation. ------------------------------------------------------------------------------- -- Copyright (c) 2014 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2014-05-26 1.0 aylons Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; library work; use work.dsp_cores_pkg.all; entity cic_dual is generic ( g_input_width : natural := 16; g_output_width : natural := 16; g_stages : natural := 1; -- aka "N" g_delay : natural := 1; -- aka "M" g_max_rate : natural := 2048; -- Max decimation rate g_tag_desync_cnt_width : natural := 14; g_bus_width : natural := 11; -- Decimation ratio bus width. g_with_ce_synch : boolean := false; g_tag_width : natural := 1; -- Input data tag width g_data_mask_width : natural := 16; -- Input data mask width g_round_convergent : natural := 0 ); port ( clk_i : in std_logic; rst_i : in std_logic; ce_i : in std_logic; ce_out_i : in std_logic := '0'; valid_i : in std_logic; I_i : in std_logic_vector(g_input_width-1 downto 0); I_tag_i : in std_logic_vector(g_tag_width-1 downto 0) := (others => '0'); I_tag_en_i : in std_logic := '0'; I_tag_desync_cnt_rst_i : in std_logic := '0'; I_tag_desync_cnt_o : out std_logic_vector(g_tag_desync_cnt_width-1 downto 0); I_mask_num_samples_beg_i : in unsigned(g_data_mask_width-1 downto 0) := (others => '0'); I_mask_num_samples_end_i : in unsigned(g_data_mask_width-1 downto 0) := (others => '0'); I_mask_en_i : in std_logic := '0'; Q_i : in std_logic_vector(g_input_width-1 downto 0); Q_tag_i : in std_logic_vector(g_tag_width-1 downto 0) := (others => '0'); Q_tag_en_i : in std_logic := '0'; Q_tag_desync_cnt_rst_i : in std_logic := '0'; Q_tag_desync_cnt_o : out std_logic_vector(g_tag_desync_cnt_width-1 downto 0); Q_mask_num_samples_beg_i : in unsigned(g_data_mask_width-1 downto 0) := (others => '0'); Q_mask_num_samples_end_i : in unsigned(g_data_mask_width-1 downto 0) := (others => '0'); Q_mask_en_i : in std_logic := '0'; ratio_i : in std_logic_vector(g_bus_width-1 downto 0); I_o : out std_logic_vector(g_output_width-1 downto 0); Q_o : out std_logic_vector(g_output_width-1 downto 0); valid_o : out std_logic ); end entity cic_dual; architecture str of cic_dual is signal decimation_strobe : std_logic; begin -- architecture str cmp_cic_decim_I : cic_dyn generic map ( g_input_width => g_input_width, g_output_width => g_output_width, g_stages => g_stages, g_delay => g_delay, g_max_rate => g_max_rate, g_tag_desync_cnt_width => g_tag_desync_cnt_width, g_bus_width => g_bus_width, g_with_ce_synch => g_with_ce_synch, g_tag_width => g_tag_width, g_data_mask_width => g_data_mask_width, g_round_convergent => g_round_convergent) port map ( clk_i => clk_i, rst_i => rst_i , ce_i => ce_i, ce_out_i => ce_out_i, data_i => I_i, data_tag_i => I_tag_i, data_tag_en_i => I_tag_en_i, data_tag_desync_cnt_rst_i => I_tag_desync_cnt_rst_i, data_tag_desync_cnt_o => I_tag_desync_cnt_o, data_mask_num_samples_beg_i => I_mask_num_samples_beg_i, data_mask_num_samples_end_i => I_mask_num_samples_end_i, data_mask_en_i => I_mask_en_i, data_o => I_o, valid_i => valid_i, ratio_i => ratio_i, valid_o => valid_o); cmp_cic_decim_Q : cic_dyn generic map ( g_input_width => g_input_width, g_output_width => g_output_width, g_stages => g_stages, g_delay => g_delay, g_max_rate => g_max_rate, g_tag_desync_cnt_width => g_tag_desync_cnt_width, g_bus_width => g_bus_width, g_with_ce_synch => g_with_ce_synch, g_tag_width => g_tag_width, g_data_mask_width => g_data_mask_width, g_round_convergent => g_round_convergent) port map ( clk_i => clk_i, rst_i => rst_i , ce_i => ce_i, ce_out_i => ce_out_i, data_i => Q_i, data_tag_i => Q_tag_i, data_tag_en_i => Q_tag_en_i, data_tag_desync_cnt_rst_i => Q_tag_desync_cnt_rst_i, data_tag_desync_cnt_o => Q_tag_desync_cnt_o, data_mask_num_samples_beg_i => Q_mask_num_samples_beg_i, data_mask_num_samples_end_i => Q_mask_num_samples_end_i, data_mask_en_i => Q_mask_en_i, data_o => Q_o, valid_i => valid_i, ratio_i => ratio_i, valid_o => open); end architecture str; -------------------------------------------------------------------------------
lgpl-3.0
b5e5f57f34494f915fd10e8f921a4444
0.426245
3.504577
false
false
false
false
SoCdesign/EHA
RTL/Credit_Based/Credit_Based_FC/LBDR.vhd
1
3,340
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.ALL; entity LBDR is generic ( cur_addr_rst: integer := 8; Rxy_rst: integer := 8; Cx_rst: integer := 8; NoC_size: integer := 4 ); port ( reset: in std_logic; clk: in std_logic; empty: in std_logic; flit_type: in std_logic_vector(2 downto 0); dst_addr: in std_logic_vector(NoC_size-1 downto 0); grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic; Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic ); end LBDR; architecture behavior of LBDR is signal Cx: std_logic_vector(3 downto 0); signal Rxy: std_logic_vector(7 downto 0); signal cur_addr: std_logic_vector(NoC_size-1 downto 0); signal N1, E1, W1, S1 :std_logic :='0'; signal Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: std_logic; signal Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: std_logic; signal grants: std_logic; begin grants <= grant_N or grant_E or grant_W or grant_S or grant_L; Cx <= std_logic_vector(to_unsigned(Cx_rst, Cx'length)); Rxy <= std_logic_vector(to_unsigned(Rxy_rst, Rxy'length)); cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length)); N1 <= '1' when dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) else '0'; E1 <= '1' when cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) else '0'; W1 <= '1' when dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) else '0'; S1 <= '1' when cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) else '0'; process(clk, reset) begin if reset = '0' then Req_N_FF <= '0'; Req_E_FF <= '0'; Req_W_FF <= '0'; Req_S_FF <= '0'; Req_L_FF <= '0'; elsif clk'event and clk = '1' then Req_N_FF <= Req_N_in; Req_E_FF <= Req_E_in; Req_W_FF <= Req_W_in; Req_S_FF <= Req_S_in; Req_L_FF <= Req_L_in; end if; end process; -- The combionational part Req_N <= Req_N_FF; Req_E <= Req_E_FF; Req_W <= Req_W_FF; Req_S <= Req_S_FF; Req_L <= Req_L_FF; process(N1, E1, W1, S1, Rxy, Cx, flit_type, empty, Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF, grants) begin if flit_type = "001" and empty = '0' then Req_N_in <= ((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0); Req_E_in <= ((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1); Req_W_in <= ((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2); Req_S_in <= ((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3); Req_L_in <= not N1 and not E1 and not W1 and not S1; elsif flit_type = "100" and empty = '0' and grants = '1' then Req_N_in <= '0'; Req_E_in <= '0'; Req_W_in <= '0'; Req_S_in <= '0'; Req_L_in <= '0'; else Req_N_in <= Req_N_FF; Req_E_in <= Req_E_FF; Req_W_in <= Req_W_FF; Req_S_in <= Req_S_FF; Req_L_in <= Req_L_FF; end if; end process; END;
gpl-3.0
ba7208709104230a3e30f50c10bf88bd
0.57485
2.511278
false
false
false
false
SoCdesign/EHA
RTL/Hand_Shaking/Hand_Shaking_FC/FIFO.vhd
1
5,396
--Copyright (C) 2016 Siavoosh Payandeh Azad library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity FIFO is generic ( DATA_WIDTH: integer := 32 ); port ( reset: in std_logic; clk: in std_logic; RX: in std_logic_vector(DATA_WIDTH-1 downto 0); DRTS: in std_logic; read_en_N : in std_logic; read_en_E : in std_logic; read_en_W : in std_logic; read_en_S : in std_logic; read_en_L : in std_logic; CTS: out std_logic; empty_out: out std_logic; Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0) ); end; architecture behavior of FIFO is signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(1 downto 0); signal full, empty: std_logic; signal read_en, write_en: std_logic; signal CTS_in, CTS_out: std_logic; type FIFO_Mem_type is array (0 to 3) of std_logic_vector(DATA_WIDTH-1 downto 0); signal FIFO_Mem : FIFO_Mem_type ; TYPE STATE_TYPE IS (IDLE, READ_DATA); SIGNAL HS_state_out,HS_state_in : STATE_TYPE; begin -------------------------------------------------------------------------------------------- -- block diagram of the FIFO! -- previous -- router -- -- ------------------------------------------ -- | | | -- TX|--------->| RX Data_out|----> goes to Xbar and LBDR -- | | | -- RTS|--------->| DRTS FIFO read_en|<---- Comes from Arbiters (N,E,W,S,L) -- | | (N,E,W,S,L)| -- DCTS|<---------| CTS | -- -- ------------------------------------------ -------------------------------------------------------------------------------------------- -- Hand shake protocol! -- -- |<-Valid->| -- | Data | -- _____ _________ ______ -- RX _____X_________X______ -- DRTS _____|'''''''''|_____ -- CTS __________|''''|_______ -- -------------------------------------------------------------------------------------------- -- circular buffer structure -- <--- WriteP -- --------------------------------- -- | 3 | 2 | 1 | 0 | -- --------------------------------- -- <--- readP -------------------------------------------------------------------------------------------- process (clk, reset)begin if reset = '0' then HS_state_out <= IDLE; read_pointer <= "00"; write_pointer <= "00"; CTS_out<='0'; FIFO_Mem<= (others => (others=>'0')); elsif clk'event and clk = '1' then HS_state_out <= HS_state_in; write_pointer <= write_pointer_in; if write_en = '1' then --write into the memory FIFO_Mem(conv_integer(write_pointer)) <= RX; end if; read_pointer <= read_pointer_in; CTS_out<=CTS_in; end if; end process; -- anything below here is pure combinational -- combinatorial part Data_out <= FIFO_Mem(conv_integer(read_pointer)); read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty; empty_out <= empty; CTS <= CTS_out; process(write_en, write_pointer)begin if write_en = '1'then write_pointer_in <= write_pointer+1; else write_pointer_in <= write_pointer; end if; end process; process(read_en, empty, read_pointer)begin if (read_en = '1' and empty = '0') then read_pointer_in <= read_pointer+1; else read_pointer_in <= read_pointer; end if; end process; process(HS_state_out, full, DRTS, CTS_out) begin case(HS_state_out) is when IDLE => if CTS_out = '0' and DRTS = '1' and full ='0' then HS_state_in <= READ_DATA; CTS_in <= '1'; write_en <= '1'; else HS_state_in <= IDLE; CTS_in <= '0'; write_en <= '0'; end if; when others => -- READ_DATA if CTS_out = '0' and DRTS = '1' and full ='0' then HS_state_in <= READ_DATA; CTS_in <= '1'; write_en <= '1'; else HS_state_in <= IDLE; CTS_in <= '0'; write_en <= '0'; end if; end case ; end process; process(write_pointer, read_pointer)begin if read_pointer = write_pointer then empty <= '1'; else empty <= '0'; end if; if write_pointer = read_pointer - 1 then full <= '1'; else full <= '0'; end if; end process; end;
gpl-3.0
e387dac04f9ed46bfe362cb4b73c64d7
0.379726
4.289348
false
false
false
false
SoCdesign/EHA
RTL/Hand_Shaking/Hand_Shaking_FC/Router_32_bit.vhd
1
13,335
--Copyright (C) 2016 Siavoosh Payandeh Azad library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity router is generic ( DATA_WIDTH: integer := 32; current_address : integer := 0; Rxy_rst : integer := 60; Cx_rst : integer := 10; NoC_size: integer := 4 ); port ( reset, clk: in std_logic; DCTS_N, DCTS_E, DCTS_w, DCTS_S, DCTS_L: in std_logic; DRTS_N, DRTS_E, DRTS_W, DRTS_S, DRTS_L: in std_logic; RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0); RTS_N, RTS_E, RTS_W, RTS_S, RTS_L: out std_logic; CTS_N, CTS_E, CTS_w, CTS_S, CTS_L: out std_logic; TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0) ); end router; architecture behavior of router is COMPONENT FIFO generic ( DATA_WIDTH: integer := 32 ); port ( reset: in std_logic; clk: in std_logic; RX: in std_logic_vector (DATA_WIDTH-1 downto 0); DRTS: in std_logic; read_en_N : in std_logic; read_en_E : in std_logic; read_en_W : in std_logic; read_en_S : in std_logic; read_en_L : in std_logic; CTS: out std_logic; empty_out: out std_logic; Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0) ); end COMPONENT; COMPONENT Arbiter port ( reset: in std_logic; clk: in std_logic; Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; DCTS: in std_logic; Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic; Xbar_sel : out std_logic_vector(4 downto 0); RTS: out std_logic ); end COMPONENT; COMPONENT LBDR is generic ( cur_addr_rst: integer := 0; Rxy_rst: integer := 60; Cx_rst: integer := 8; NoC_size: integer := 4 ); port ( reset: in std_logic; clk: in std_logic; empty: in std_logic; flit_type: in std_logic_vector(2 downto 0); dst_addr: in std_logic_vector(NoC_size-1 downto 0); Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic ); end COMPONENT; COMPONENT XBAR is generic ( DATA_WIDTH: integer := 32 ); port ( North_in: in std_logic_vector(DATA_WIDTH-1 downto 0); East_in: in std_logic_vector(DATA_WIDTH-1 downto 0); West_in: in std_logic_vector(DATA_WIDTH-1 downto 0); South_in: in std_logic_vector(DATA_WIDTH-1 downto 0); Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0); sel: in std_logic_vector (4 downto 0); Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0) ); end COMPONENT; signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0); -- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic; signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic; signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic; signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic; signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic; signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic; signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic; signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic; signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic; signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic; signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic; signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0); begin ------------------------------------------------------------------------------------------------------------------------------ -- block diagram of one channel -- -- .____________grant_________ -- | ▲ -- | _______ __|_______ -- | | | | | -- | | LBDR |---req--->| Arbiter | <--handshake--> -- | |_______| |__________| signals -- | ▲ | -- __▼___ | flit ___▼__ -- RX ----->| | | type | | -- <-handshake->| FIFO |---o------------->| |-----> TX -- signals |______| ------>| | -- ------>| XBAR | -- ------>| | -- ------>| | -- |______| -- ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- all the FIFOs FIFO_N: FIFO generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (reset => reset, clk => clk, RX => RX_N, DRTS => DRTS_N, read_en_N => '0', read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN, CTS => CTS_N, empty_out => empty_N, Data_out => FIFO_D_out_N); FIFO_E: FIFO generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (reset => reset, clk => clk, RX => RX_E, DRTS => DRTS_E, read_en_N => Grant_NE, read_en_E =>'0', read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE, CTS => CTS_E, empty_out => empty_E, Data_out => FIFO_D_out_E); FIFO_W: FIFO generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (reset => reset, clk => clk, RX => RX_W, DRTS => DRTS_W, read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>'0', read_en_S =>Grant_SW, read_en_L =>Grant_LW, CTS => CTS_W, empty_out => empty_W, Data_out => FIFO_D_out_W); FIFO_S: FIFO generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (reset => reset, clk => clk, RX => RX_S, DRTS => DRTS_S, read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>'0', read_en_L =>Grant_LS, CTS => CTS_S, empty_out => empty_S, Data_out => FIFO_D_out_S); FIFO_L: FIFO generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (reset => reset, clk => clk, RX => RX_L, DRTS => DRTS_L, read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>'0', CTS => CTS_L, empty_out => empty_L, Data_out => FIFO_D_out_L); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- all the LBDRs LBDR_N: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty_N, flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) , Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL); LBDR_E: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty_E, flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) , Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL); LBDR_W: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty_W, flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) , Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL); LBDR_S: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty_S, flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) , Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL); LBDR_L: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty_L, flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) , Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- all the Arbiters Arbiter_N: Arbiter PORT MAP (reset => reset, clk => clk, Req_N => '0' , Req_E => Req_EN, Req_W => Req_WN, Req_S => Req_SN, Req_L => Req_LN, DCTS => DCTS_N, Grant_N => Grant_NN, Grant_E => Grant_NE, Grant_W => Grant_NW, Grant_S => Grant_NS, Grant_L => Grant_NL, Xbar_sel => Xbar_sel_N, RTS => RTS_N ); Arbiter_E: Arbiter PORT MAP (reset => reset, clk => clk, Req_N => Req_NE , Req_E => '0', Req_W => Req_WE, Req_S => Req_SE, Req_L => Req_LE, DCTS => DCTS_E, Grant_N => Grant_EN, Grant_E => Grant_EE, Grant_W => Grant_EW, Grant_S => Grant_ES, Grant_L => Grant_EL, Xbar_sel => Xbar_sel_E, RTS => RTS_E ); Arbiter_W: Arbiter PORT MAP (reset => reset, clk => clk, Req_N => Req_NW , Req_E => Req_EW, Req_W => '0', Req_S => Req_SW, Req_L => Req_LW, DCTS => DCTS_W, Grant_N => Grant_WN, Grant_E => Grant_WE, Grant_W => Grant_WW, Grant_S => Grant_WS, Grant_L => Grant_WL, Xbar_sel => Xbar_sel_W, RTS => RTS_W ); Arbiter_S: Arbiter PORT MAP (reset => reset, clk => clk, Req_N => Req_NS , Req_E => Req_ES, Req_W => Req_WS, Req_S => '0', Req_L => Req_LS, DCTS => DCTS_S, Grant_N => Grant_SN, Grant_E => Grant_SE, Grant_W => Grant_SW, Grant_S => Grant_SS, Grant_L => Grant_SL, Xbar_sel => Xbar_sel_S, RTS => RTS_S ); Arbiter_L: Arbiter PORT MAP (reset => reset, clk => clk, Req_N => Req_NL , Req_E => Req_EL, Req_W => Req_WL, Req_S => Req_SL, Req_L => '0', DCTS => DCTS_L, Grant_N => Grant_LN, Grant_E => Grant_LE, Grant_W => Grant_LW, Grant_S => Grant_LS, Grant_L => Grant_LL, Xbar_sel => Xbar_sel_L, RTS => RTS_L ); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- all the Xbars XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L, sel => Xbar_sel_N, Data_out=> TX_N); XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L, sel => Xbar_sel_E, Data_out=> TX_E); XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L, sel => Xbar_sel_W, Data_out=> TX_W); XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L, sel => Xbar_sel_S, Data_out=> TX_S); XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L, sel => Xbar_sel_L, Data_out=> TX_L); end;
gpl-3.0
f32dc8397a33e87030d1e9258c4382f2
0.460944
3.283321
false
false
false
false
bruskajp/EE-316
Project5/game_logic.vhd
1
21,030
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 04/05/2017 02:01:44 PM -- Design Name: -- Module Name: game_logic - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity game_logic is port( clk : in STD_LOGIC; usb_bt_clk : in STD_LOGIC; save_button_input : in STD_LOGIC; keyboard_input : in STD_LOGIC_VECTOR(7 downto 0); x_pos_input : in STD_LOGIC_VECTOR(7 downto 0); y_pos_input : in STD_LOGIC_VECTOR(7 downto 0); usb_bt_input : in STD_LOGIC_VECTOR(7 downto 0); reset_output : out STD_LOGIC; screen_size_output : out STD_LOGIC; pen_width_output : out STD_LOGIC_VECTOR(2 downto 0); x_pos_output : out STD_LOGIC_VECTOR(7 downto 0); y_pos_output : out STD_LOGIC_VECTOR(7 downto 0); tricolor_led_output : out STD_LOGIC_VECTOR(11 downto 0); usb_bt_output : out STD_LOGIC_VECTOR(15 downto 0); color_output : out STD_LOGIC_VECTOR(23 downto 0); ram_we_output : out STD_LOGIC_VECTOR(0 downto 0); ram_val_output : out STD_LOGIC_VECTOR(11 downto 0); ram_addr_output : out STD_LOGIC_VECTOR(16 downto 0) ); end game_logic; architecture Behavioral of game_logic is -- Font ROM component component font_rom is port( clk : in STD_LOGIC; addr : in STD_LOGIC_VECTOR(10 downto 0); data : out STD_LOGIC_VECTOR(7 downto 0) ); end component; -- RAM clock divider component component clock_divider is generic(count_max : INTEGER := 8); -- FIX THIS? port( clk : in STD_LOGIC; reset : in STD_LOGIC; clk_output : out STD_LOGIC ); end component; -- System properties signal pc_connected : STD_LOGIC := '0'; signal screen_size : STD_LOGIC := '0'; signal reset : STD_LOGIC := '0'; signal pen_width : STD_LOGIC_VECTOR(2 downto 0) := "000"; signal ascii_char : STD_LOGIC_VECTOR(7 downto 0) := x"00"; signal color : STD_LOGIC_VECTOR(23 downto 0) := x"000000"; --USB/bluetooth control send signals signal prev_screen_size : STD_LOGIC := '0'; signal prev_save : STD_LOGIC := '0'; signal prev_reset : STD_LOGIC := '0'; signal prev_pen_width : STD_LOGIC_VECTOR(2 downto 0):= "000"; signal prev_ascii_char : STD_LOGIC_VECTOR(7 downto 0):= x"00"; signal prev_x_pos, prev_y_pos : STD_LOGIC_VECTOR(7 downto 0):= x"00"; signal prev_color : STD_LOGIC_VECTOR(23 downto 0):= x"000000"; --USB/Bluetooth control receive signals signal prev_connections : STD_LOGIC_VECTOR(7 downto 0); -- Keyboard control signals signal num_values_input : INTEGER := 0; signal prev_pc_connected : STD_LOGIC := '0'; signal changing_item : STD_LOGIC_VECTOR(2 downto 0) := "000"; -- [color, pen_width, screen_size] signal hex_input : STD_LOGIC_VECTOR(3 downto 0) := x"0"; signal temp_hex_input : STD_LOGIC_VECTOR(7 downto 0) := x"00"; signal input_values : STD_LOGIC_VECTOR(23 downto 0) := x"000000"; -- Font Rom signals signal font_rom_addr : UNSIGNED(10 downto 0) := x"00" & "000"; signal font_rom_data : STD_LOGIC_VECTOR(7 downto 0) := x"00"; -- RAM clock divider signals signal ram_divider_counter : INTEGER := 0; signal ram_clk : STD_LOGIC := '0'; -- RAM Signals signal x_pos_int : INTEGER := 0; signal y_pos_int : INTEGER := 0; -- RAM fast update signals signal ram_update_count : INTEGER := 0; signal ram_update_x_count : INTEGER := 0; signal ram_update_y_count : INTEGER := 0; signal ram_update : STD_LOGIC_VECTOR(2 downto 0) := "000"; -- [pos, sys_text, user_text] signal ram_update_slow : STD_LOGIC_VECTOR(2 downto 0) := "000"; signal ram_update_pos_slow : STD_LOGIC_VECTOR(7 downto 0) := x"00"; signal ram_update_sys_text_slow : STD_LOGIC_VECTOR(7 downto 0) := x"00"; signal ram_update_user_text_slow : STD_LOGIC_VECTOR(7 downto 0) := x"00"; -- RAM slow control signals signal x_addr_count, y_addr_count : INTEGER := 0; -- RAM reset signals signal ram_reset : STD_LOGIC := '0'; signal ram_reset_slow : STD_LOGIC := '0'; signal ram_reset_count : UNSIGNED(15 downto 0) := x"0000"; signal prev_ram_resets : STD_LOGIC_VECTOR(7 downto 0) := x"00"; begin screen_size_output <= screen_size; pen_width_output <= pen_width; x_pos_output <= x_pos_input; y_pos_output <= y_pos_input; tricolor_led_output <= color(11 downto 0); color_output <= color; ram_we_output <= "1"; --ram_we_output <= "0"; reset_output <= reset; -- Previous signal generation process process(clk) begin prev_pc_connected <= pc_connected; prev_x_pos <= x_pos_input; prev_y_pos <= y_pos_input; prev_color <= color; prev_ascii_char <= ascii_char; prev_screen_size <= screen_size; prev_pen_width <= pen_width; prev_save <= save_button_input; prev_reset <= reset; end process; -- USB/Bluetooth control process process(clk, usb_bt_clk, prev_x_pos, prev_y_pos) -- FIX THIS (add update method) begin -- Sending Data if rising_edge(clk) then if reset /= prev_reset then usb_bt_output(15 downto 12) <= "1111"; usb_bt_output(1) <= save_button_input; usb_bt_output(0) <= reset; elsif prev_x_pos /= x_pos_input then usb_bt_output(15 downto 14) <= "10"; usb_bt_output(8) <= '0'; usb_bt_output(7 downto 0) <= x_pos_input; elsif prev_y_pos /= y_pos_input then usb_bt_output(15 downto 14) <= "10"; usb_bt_output(8) <= '1'; usb_bt_output(7 downto 0) <= y_pos_input; elsif prev_color /= color then usb_bt_output(15 downto 12) <= "1100"; usb_bt_output(11 downto 0) <= color(11 downto 0); -- change to 24 bit? elsif prev_screen_size /= screen_size or prev_pen_width /= pen_width then usb_bt_output(15 downto 12) <= "1110"; usb_bt_output(3) <= screen_size; usb_bt_output(2 downto 0) <= pen_width; elsif prev_ascii_char /= ascii_char then usb_bt_output(15 downto 12) <= "1101"; usb_bt_output(7 downto 0) <= ascii_char; elsif prev_save /= save_button_input then usb_bt_output(15 downto 12) <= "1111"; usb_bt_output(1) <= save_button_input; usb_bt_output(0) <= reset; else usb_bt_output <= x"0000"; end if; end if; -- Recieving Data if rising_edge(usb_bt_clk) then prev_connections <= prev_connections(6 downto 0) & usb_bt_input(0); if prev_connections = x"00" then pc_connected <= '0'; else pc_connected <= '1'; end if; end if; end process; -- Keyboard control process hex_input <= temp_hex_input(3 downto 0); process(clk) begin -- Keyboard control if rising_edge(clk) then if reset = '0' then if keyboard_input = x"77" and changing_item = "000" then -- input w and changing color ascii_char <= x"77"; changing_item <= "100"; num_values_input <= 1; elsif keyboard_input = x"63" and changing_item = "000" then -- input c and changing pen_width ascii_char <= x"63"; changing_item <= "010"; num_values_input <= 1; elsif keyboard_input = x"73" and changing_item = "000" then -- input s and changing screen_size ascii_char <= x"73"; changing_item <= "001"; num_values_input <= 1; elsif keyboard_input = x"72" and changing_item = "000" then -- input r reset <= '1'; color <= x"FFFFFF"; pen_width <= "000"; screen_size <= '0'; elsif keyboard_input = x"71" and changing_item /= "000" then -- input q and exit command ascii_char <= x"71"; -- FIX THIS elsif keyboard_input = x"08" and num_values_input = 1 then -- input backspace ascii_char <= x"08"; num_values_input <= 0; changing_item <= "000"; elsif changing_item /= "000" then -- Ascii to hex converter if (keyboard_input >= x"30" and keyboard_input <= x"39") then temp_hex_input <= std_logic_vector(unsigned(keyboard_input) - x"30"); elsif (keyboard_input >= x"61" and keyboard_input <= x"66") then temp_hex_input <= std_logic_vector(unsigned(keyboard_input) - x"57"); else temp_hex_input <= x"FF"; end if; -- User keyboard input restrictions if changing_item = "100" and hex_input <= x"F" then -- Limit color input_values(((num_values_input * 4)-1) downto ((num_values_input-1) * 4)) <= hex_input; num_values_input <= num_values_input + 1; elsif changing_item = "010" and hex_input >= x"1" and hex_input <= x"7" then -- Limit pen_width input_values(3 downto 0) <= hex_input; num_values_input <= num_values_input + 1; elsif changing_item = "001" and hex_input <= x"1" then -- Limit screen_size input_values(3 downto 0) <= hex_input; num_values_input <= num_values_input + 1; end if; elsif keyboard_input = x"0A" then -- input enter ascii_char <= x"0A"; if changing_item = "100" and num_values_input = 7 then -- new color color <= input_values; changing_item <= "000"; elsif changing_item = "010" and num_values_input = 1 then -- new pen_width pen_width <= input_values(2 downto 0); changing_item <= "000"; elsif changing_item = "001" and num_values_input = 1 then -- new screen_size screen_size <= input_values(0); changing_item <= "000"; end if; end if; end if; -- Reset handling if reset = '1' and prev_reset = '1' and ram_reset = '0' then reset <= '0'; color <= x"000000"; end if; end if; end process; -- Font ROM port map ram_font_rom : font_rom port map( clk => clk, addr => std_logic_vector(font_rom_addr), data => font_rom_data ); -- RAM clock divider port map ram_clock_divider : clock_divider generic map(count_max => 2) -- CHANGE VALUE port map( clk => clk, reset => '0', clk_output => ram_clk ); x_pos_int <= to_integer(unsigned(x_pos_input)); y_pos_int <= to_integer(unsigned(y_pos_input)); -- RAM control process process(clk, ram_clk) begin -- When to update RAM --if rising_edge(clk) then -- ram_update_pos_slow <= ram_update_pos_slow(6 downto 0) & ram_update_slow(2); -- ram_update_pos_slow <= ram_update_pos_slow(6 downto 0) & ram_update_slow(2); -- ram_update_pos_slow <= ram_update_pos_slow(6 downto 0) & ram_update_slow(2); if (x_pos_input /= prev_x_pos or y_pos_input /= prev_y_pos) then ram_update(2) <= '1'; -- pos elsif (color /= prev_color or pen_width /= prev_pen_width or pc_connected /= prev_pc_connected) then ram_update(1) <= '1'; -- sys_text elsif (ascii_char /= prev_ascii_char) then ram_update(0) <= '1'; -- user_text end if; -- if ram_update_pos_slow = x"00" then -- ram_update(2) <= '0'; -- end if; -- if ram_update_sys_text_slow = x"00" then -- ram_update(1) <= '0'; -- end if; -- if ram_update_user_text_slow = x"00" then -- ram_update(0) <= '0'; -- end if; if reset = '1' and ram_reset = '0' then ram_reset <= '1'; prev_ram_resets <= prev_ram_resets(6 downto 0) & ram_reset; end if; if ram_reset_slow = '0' and prev_ram_resets = x"FF" then ram_reset <= '0'; end if; --end if; -- Draw to RAM --if rising_edge(ram_clk) then if rising_edge(clk) then --if ram_reset = '0' then if ram_update(2) = '1' then -- pos --if(true) then --ram_we_output <= "1"; ram_val_output <= color(23 downto 20) & color(15 downto 12) & color(7 downto 4); --ram_update_slow(2) <= '1'; --ram_update(2) <= '0'; -- if (y_addr_count < unsigned(pen_width)) and -- ((y_pos_int + y_addr_count) < 256) and -- ((y_pos_int + y_addr_count) >= 0) then -- if (x_addr_count < unsigned(pen_width)) and -- ((x_pos_int + x_addr_count) < 256) and -- ((x_pos_int + x_addr_count) >= 0) then ram_addr_output <= std_logic_vector(to_unsigned( ((x_pos_int+x_addr_count) + ((y_pos_int+y_addr_count) * 256)) , 17)); -- else -- x_addr_count <= 0; -- end if; -- y_addr_count <= y_addr_count + 1; -- else -- y_addr_count <= 0; -- end if; --elsif prev_x_pos /= x_pos_input and prev_y_pos /= y_pos_input then --Not needed? --ram_update(1) <= '0'; --ram_we_output <= "0"; --Not needed? --ram_update(2) <= '0'; --Not needed? -- elsif ram_update(2 downto 1) = "01" then -- sys_text -- ram_update_slow(2 downto 1) <= "01"; -- if ram_update_count < 3 then -- if ram_update_y_count < 16 then -- if ram_update_x_count < 8 then -- if ram_update_count = 1 then -- Update color -- ram_addr_output <= std_logic_vector(to_unsigned(65618 + ram_update_x_count -- + (ram_update_y_count * 384), 17)); -- ram_val_output <= color(11 downto 0); -- elsif ram_update_count = 2 then -- Update pen_width -- ram_addr_output <= std_logic_vector(to_unsigned(65768 + ram_update_x_count -- + (ram_update_y_count * 384), 17)); -- font_rom_addr <= "000" & (x"30" + unsigned("0000" & pen_width)); -- FIX THIS (concurency) -- if font_rom_data(ram_update_x_count) = '1' then -- ram_val_output <= x"000"; -- else -- ram_val_output <= x"FFF"; -- end if; -- else -- Update pc_connnection -- ram_addr_output <= std_logic_vector(to_unsigned(65888 + ram_update_x_count -- + (ram_update_count * 10) -- + (ram_update_y_count * 384), 17)); -- font_rom_addr <= "00" & (x"30" + "0000000" & pc_connected); -- FIX THIS (concurency) -- if font_rom_data(ram_update_x_count) = '1' then -- ram_val_output <= x"000"; -- else -- ram_val_output <= x"FFF"; -- end if; -- end if; -- ram_update_x_count <= ram_update_x_count + 1; -- else -- ram_update_x_count <= 0; -- end if; -- ram_update_y_count <= ram_update_x_count + 1; -- else -- ram_update_y_count <= 0; -- end if; -- ram_update_count <= ram_update_count + 1; -- else -- ram_update_slow(1) <= '0'; -- ram_update_count <= 0; -- end if; -- elsif ram_update = "001" then -- user_text -- ram_update_slow <= "001"; -- if ram_update_count < 8 then -- if ram_update_y_count < 16 then -- if ram_update_x_count < 8 then -- ram_addr_output <= std_logic_vector(to_unsigned(66102 + ram_update_x_count -- + (ram_update_y_count * 384), 17)); -- font_rom_addr <= unsigned("000" & ascii_char); -- FIX THIS (concurency) -- if font_rom_data(ram_update_x_count) = '1' then -- ram_val_output <= x"000"; -- else -- ram_val_output <= x"FFF"; -- end if; -- ram_update_x_count <= ram_update_x_count + 1; -- else -- ram_update_x_count <= 0; -- end if; -- ram_update_y_count <= ram_update_x_count + 1; -- else -- ram_update_y_count <= 0; -- end if; -- ram_update_count <= ram_update_count + 1; -- else -- ram_update_slow(0) <= '0'; -- ram_update_count <= 0; -- end if; -- else -- ram_update_slow <= "000"; --end if; ---- else -- ram_reset = 1 ---- -- Drawing Screen (sys_text and user_text update automatically) ---- if ram_reset_count < 65536 then ---- ram_reset_slow <= '1'; ---- ram_reset_count <= ram_reset_count + 1; ---- ram_addr_output <= "0" & std_logic_vector(ram_reset_count); ---- else ---- ram_reset_slow <= '0'; ---- ram_reset_count <= x"0000"; ---- end if; end if; end if; end process; end Behavioral;
gpl-3.0
63ea3a49eafc88966664a2c8bc950e83
0.447266
4.004951
false
false
false
false
TanND/Electronic
VHDL/D13_C2.vhd
1
592
library IEEE; use IEEE.STD_LOGIC_1164.all; entity D13_C2 is port( clk : in STD_LOGIC; seg : out STD_LOGIC_VECTOR(7 downto 0) ); end D13_C2; architecture D13_C2 of D13_C2 is begin process(clk) variable dem:integer range 0 to 4; begin if (rising_edge(clk)) then if (dem=4) then dem:=0; else dem:=dem+1; end if; end if; case dem is when 0=> seg <="00000000"; when 1=> seg <="00011000"; when 2=> seg <="00111100"; when 3=> seg <="01111110"; when 4=> seg <="11111111"; when others=> seg <="XXXXXXXX"; end case; end process; end D13_C2; -- clk=5Mhz;
apache-2.0
c54503059e4babfc3e51b48c53c1b106
0.621622
2.654709
false
false
false
false
bruskajp/EE-316
Project5/game_logic_4.vhd
1
21,708
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 04/05/2017 02:01:44 PM -- Design Name: -- Module Name: game_logic - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity game_logic is port( clk : in STD_LOGIC; usb_bt_clk : in STD_LOGIC; save_button_input : in STD_LOGIC; keyboard_input : in STD_LOGIC_VECTOR(7 downto 0); x_pos_input : in STD_LOGIC_VECTOR(7 downto 0); y_pos_input : in STD_LOGIC_VECTOR(7 downto 0); usb_bt_input : in STD_LOGIC_VECTOR(7 downto 0); reset_output : out STD_LOGIC; screen_size_output : out STD_LOGIC; pen_width_output : out STD_LOGIC_VECTOR(2 downto 0); x_pos_output : out STD_LOGIC_VECTOR(7 downto 0); y_pos_output : out STD_LOGIC_VECTOR(7 downto 0); tricolor_led_output : out STD_LOGIC_VECTOR(11 downto 0); usb_bt_output : out STD_LOGIC_VECTOR(15 downto 0); color_output : out STD_LOGIC_VECTOR(23 downto 0); ram_we_output : out STD_LOGIC_VECTOR(0 downto 0); ram_val_output : out STD_LOGIC_VECTOR(11 downto 0); ram_addr_output : out STD_LOGIC_VECTOR(16 downto 0) ); end game_logic; architecture Behavioral of game_logic is -- Font ROM component component font_rom is port( clk : in STD_LOGIC; addr : in STD_LOGIC_VECTOR(10 downto 0); data : out STD_LOGIC_VECTOR(7 downto 0) ); end component; -- RAM clock divider component component clock_divider is generic(count_max : INTEGER := 8); -- FIX THIS? port( clk : in STD_LOGIC; reset : in STD_LOGIC; clk_output : out STD_LOGIC ); end component; -- System properties signal pc_connected : STD_LOGIC := '0'; signal screen_size : STD_LOGIC := '0'; signal reset : STD_LOGIC := '0'; signal pen_width : STD_LOGIC_VECTOR(2 downto 0) := "000"; signal ascii_char : STD_LOGIC_VECTOR(7 downto 0) := x"00"; signal color : STD_LOGIC_VECTOR(23 downto 0) := x"000000"; --USB/bluetooth control send signals signal prev_screen_size : STD_LOGIC := '0'; signal prev_save : STD_LOGIC := '0'; signal prev_reset : STD_LOGIC := '0'; signal prev_pen_width : STD_LOGIC_VECTOR(2 downto 0):= "000"; signal prev_ascii_char : STD_LOGIC_VECTOR(7 downto 0):= x"00"; signal prev_x_pos, prev_y_pos : STD_LOGIC_VECTOR(7 downto 0):= x"00"; signal prev_color : STD_LOGIC_VECTOR(23 downto 0):= x"000000"; --USB/Bluetooth control receive signals signal prev_connections : STD_LOGIC_VECTOR(7 downto 0); -- Keyboard control signals signal num_values_input : INTEGER := 0; signal prev_pc_connected : STD_LOGIC := '0'; signal changing_item : STD_LOGIC_VECTOR(2 downto 0) := "000"; -- [color, pen_width, screen_size] signal hex_input : STD_LOGIC_VECTOR(3 downto 0) := x"0"; signal temp_hex_input : STD_LOGIC_VECTOR(7 downto 0) := x"00"; signal input_values : STD_LOGIC_VECTOR(23 downto 0) := x"000000"; -- Font Rom signals signal font_rom_addr : UNSIGNED(10 downto 0) := x"00" & "000"; signal font_rom_data : STD_LOGIC_VECTOR(7 downto 0) := x"00"; -- RAM clock divider signals signal ram_divider_counter : INTEGER := 0; signal ram_clk : STD_LOGIC := '0'; -- RAM Signals signal x_pos_int : INTEGER := 0; signal y_pos_int : INTEGER := 0; -- RAM fast update signals signal ram_update_count : INTEGER := 0; signal ram_update_x_count : INTEGER := 0; signal ram_update_y_count : INTEGER := 0; signal ram_update_slow_int : INTEGER := 0; signal ram_update : STD_LOGIC_VECTOR(2 downto 0) := "000"; -- [pos, sys_text, user_text] signal ram_update_slow : STD_LOGIC_VECTOR(2 downto 0) := "000"; signal ram_update_pos_slow : STD_LOGIC_VECTOR(7 downto 0) := x"00"; signal ram_update_sys_text_slow : STD_LOGIC_VECTOR(7 downto 0) := x"00"; signal ram_update_user_text_slow : STD_LOGIC_VECTOR(7 downto 0) := x"00"; -- RAM slow control signals signal x_addr_count, y_addr_count : INTEGER := 0; -- RAM reset signals signal ram_reset : STD_LOGIC := '0'; signal ram_reset_slow : STD_LOGIC := '0'; signal ram_reset_count : UNSIGNED(15 downto 0) := x"0000"; signal prev_ram_resets : STD_LOGIC_VECTOR(7 downto 0) := x"00"; begin screen_size_output <= screen_size; pen_width_output <= pen_width; x_pos_output <= x_pos_input; y_pos_output <= y_pos_input; tricolor_led_output <= color(11 downto 0); color_output <= color; ram_we_output <= "1"; --ram_we_output <= "0"; reset_output <= reset; -- Previous signal generation process process(clk) begin prev_pc_connected <= pc_connected; prev_x_pos <= x_pos_input; prev_y_pos <= y_pos_input; prev_color <= color; prev_ascii_char <= ascii_char; prev_screen_size <= screen_size; prev_pen_width <= pen_width; prev_save <= save_button_input; prev_reset <= reset; end process; -- USB/Bluetooth control process process(clk, usb_bt_clk, prev_x_pos, prev_y_pos) -- FIX THIS (add update method) begin -- Sending Data if rising_edge(clk) then if reset /= prev_reset then usb_bt_output(15 downto 12) <= "1111"; usb_bt_output(1) <= save_button_input; usb_bt_output(0) <= reset; elsif prev_x_pos /= x_pos_input then usb_bt_output(15 downto 14) <= "10"; usb_bt_output(8) <= '0'; usb_bt_output(7 downto 0) <= x_pos_input; elsif prev_y_pos /= y_pos_input then usb_bt_output(15 downto 14) <= "10"; usb_bt_output(8) <= '1'; usb_bt_output(7 downto 0) <= y_pos_input; elsif prev_color /= color then usb_bt_output(15 downto 12) <= "1100"; usb_bt_output(11 downto 0) <= color(11 downto 0); -- change to 24 bit? elsif prev_screen_size /= screen_size or prev_pen_width /= pen_width then usb_bt_output(15 downto 12) <= "1110"; usb_bt_output(3) <= screen_size; usb_bt_output(2 downto 0) <= pen_width; elsif prev_ascii_char /= ascii_char then usb_bt_output(15 downto 12) <= "1101"; usb_bt_output(7 downto 0) <= ascii_char; elsif prev_save /= save_button_input then usb_bt_output(15 downto 12) <= "1111"; usb_bt_output(1) <= save_button_input; usb_bt_output(0) <= reset; else usb_bt_output <= x"0000"; end if; end if; -- Recieving Data if rising_edge(usb_bt_clk) then prev_connections <= prev_connections(6 downto 0) & usb_bt_input(0); if prev_connections = x"00" then pc_connected <= '0'; else pc_connected <= '1'; end if; end if; end process; -- Keyboard control process hex_input <= temp_hex_input(3 downto 0); process(clk) begin -- Keyboard control if rising_edge(clk) then if reset = '0' then if keyboard_input = x"77" and changing_item = "000" then -- input w and changing color ascii_char <= x"77"; changing_item <= "100"; num_values_input <= 1; elsif keyboard_input = x"63" and changing_item = "000" then -- input c and changing pen_width ascii_char <= x"63"; changing_item <= "010"; num_values_input <= 1; elsif keyboard_input = x"73" and changing_item = "000" then -- input s and changing screen_size ascii_char <= x"73"; changing_item <= "001"; num_values_input <= 1; elsif keyboard_input = x"72" and changing_item = "000" then -- input r reset <= '1'; color <= x"FFFFFF"; pen_width <= "000"; screen_size <= '0'; elsif keyboard_input = x"71" and changing_item /= "000" then -- input q and exit command ascii_char <= x"71"; -- FIX THIS elsif keyboard_input = x"08" and num_values_input = 1 then -- input backspace ascii_char <= x"08"; num_values_input <= 0; changing_item <= "000"; elsif changing_item /= "000" then -- Ascii to hex converter if (keyboard_input >= x"30" and keyboard_input <= x"39") then temp_hex_input <= std_logic_vector(unsigned(keyboard_input) - x"30"); elsif (keyboard_input >= x"61" and keyboard_input <= x"66") then temp_hex_input <= std_logic_vector(unsigned(keyboard_input) - x"57"); else temp_hex_input <= x"FF"; end if; -- User keyboard input restrictions if changing_item = "100" and hex_input <= x"F" then -- Limit color input_values(((num_values_input * 4)-1) downto ((num_values_input-1) * 4)) <= hex_input; num_values_input <= num_values_input + 1; elsif changing_item = "010" and hex_input >= x"1" and hex_input <= x"7" then -- Limit pen_width input_values(3 downto 0) <= hex_input; num_values_input <= num_values_input + 1; elsif changing_item = "001" and hex_input <= x"1" then -- Limit screen_size input_values(3 downto 0) <= hex_input; num_values_input <= num_values_input + 1; end if; elsif keyboard_input = x"0A" then -- input enter ascii_char <= x"0A"; if changing_item = "100" and num_values_input = 7 then -- new color color <= input_values; changing_item <= "000"; elsif changing_item = "010" and num_values_input = 1 then -- new pen_width pen_width <= input_values(2 downto 0); changing_item <= "000"; elsif changing_item = "001" and num_values_input = 1 then -- new screen_size screen_size <= input_values(0); changing_item <= "000"; end if; end if; end if; -- Reset handling if reset = '1' and prev_reset = '1' and ram_reset = '0' then reset <= '0'; color <= x"000000"; end if; end if; end process; -- Font ROM port map ram_font_rom : font_rom port map( clk => clk, addr => std_logic_vector(font_rom_addr), data => font_rom_data ); -- RAM clock divider port map ram_clock_divider : clock_divider generic map(count_max => 2) -- CHANGE VALUE port map( clk => clk, reset => '0', clk_output => ram_clk ); x_pos_int <= to_integer(unsigned(x_pos_input)); y_pos_int <= to_integer(unsigned(y_pos_input)); -- RAM control process process(clk, ram_clk) begin -- When to update RAM if rising_edge(clk) then -- ram_update_pos_slow <= ram_update_pos_slow(6 downto 0) & ram_update_slow(2); -- ram_update_pos_slow <= ram_update_pos_slow(6 downto 0) & ram_update_slow(2); -- ram_update_pos_slow <= ram_update_pos_slow(6 downto 0) & ram_update_slow(2); if (x_pos_input /= prev_x_pos or y_pos_input /= prev_y_pos) then ram_update(2) <= '1'; -- pos ram_update_slow_int <= 1; -- elsif (color /= prev_color or pen_width /= prev_pen_width -- or pc_connected /= prev_pc_connected) then -- ram_update(1) <= '1'; -- sys_text -- elsif (ascii_char /= prev_ascii_char) then -- ram_update(0) <= '1'; -- user_text end if; if ram_update_slow_int = std_logic_vector(to_unsigned(2048, 17)) then ram_update_slow_int <= 0; elsif ram_update_slow_int > 0 then ram_update_slow_int <= ram_update_slow_int + 1; ram_update(2) <= '1'; else ram_update(2) <= '0'; end if; -- if ram_update_pos_slow = x"00" then -- ram_update(2) <= '0'; -- end if; -- if ram_update_sys_text_slow = x"00" then -- ram_update(1) <= '0'; -- end if; -- if ram_update_user_text_slow = x"00" then -- ram_update(0) <= '0'; -- end if; -- if reset = '1' and ram_reset = '0' then -- ram_reset <= '1'; -- prev_ram_resets <= prev_ram_resets(6 downto 0) & ram_reset; -- end if; -- -- if ram_reset_slow = '0' and prev_ram_resets = x"FF" then -- ram_reset <= '0'; -- end if; -- end if; -- Draw to RAM --if rising_edge(ram_clk) then --if rising_edge(clk) then --if ram_reset = '0' then if ram_update(2) = '1' then -- pos --if(true) then --ram_we_output <= "1"; ram_val_output <= color(23 downto 20) & color(15 downto 12) & color(7 downto 4); --ram_update_slow(2) <= '1'; --ram_update(2) <= '0'; -- if (y_addr_count < unsigned(pen_width)) and -- ((y_pos_int + y_addr_count) < 256) and -- ((y_pos_int + y_addr_count) >= 0) then -- if (x_addr_count < unsigned(pen_width)) and -- ((x_pos_int + x_addr_count) < 256) and -- ((x_pos_int + x_addr_count) >= 0) then ram_addr_output <= std_logic_vector(to_unsigned( ((x_pos_int+x_addr_count) + ((y_pos_int+y_addr_count) * 256)) , 17)); else ram_val_output <= x"F00"; ram_addr_output <= std_logic_vector(to_unsigned(66666, 17)); --ram_update(2) <= '1'; -- else -- x_addr_count <= 0; -- end if; -- y_addr_count <= y_addr_count + 1; -- else -- y_addr_count <= 0; -- end if; --elsif prev_x_pos /= x_pos_input and prev_y_pos /= y_pos_input then --Not needed? --ram_update(1) <= '0'; --ram_we_output <= "0"; --Not needed? --ram_update(2) <= '0'; --Not needed? -- elsif ram_update(2 downto 1) = "01" then -- sys_text -- ram_update_slow(2 downto 1) <= "01"; -- if ram_update_count < 3 then -- if ram_update_y_count < 16 then -- if ram_update_x_count < 8 then -- if ram_update_count = 1 then -- Update color -- ram_addr_output <= std_logic_vector(to_unsigned(65618 + ram_update_x_count -- + (ram_update_y_count * 384), 17)); -- ram_val_output <= color(11 downto 0); -- elsif ram_update_count = 2 then -- Update pen_width -- ram_addr_output <= std_logic_vector(to_unsigned(65768 + ram_update_x_count -- + (ram_update_y_count * 384), 17)); -- font_rom_addr <= "000" & (x"30" + unsigned("0000" & pen_width)); -- FIX THIS (concurency) -- if font_rom_data(ram_update_x_count) = '1' then -- ram_val_output <= x"000"; -- else -- ram_val_output <= x"FFF"; -- end if; -- else -- Update pc_connnection -- ram_addr_output <= std_logic_vector(to_unsigned(65888 + ram_update_x_count -- + (ram_update_count * 10) -- + (ram_update_y_count * 384), 17)); -- font_rom_addr <= "00" & (x"30" + "0000000" & pc_connected); -- FIX THIS (concurency) -- if font_rom_data(ram_update_x_count) = '1' then -- ram_val_output <= x"000"; -- else -- ram_val_output <= x"FFF"; -- end if; -- end if; -- ram_update_x_count <= ram_update_x_count + 1; -- else -- ram_update_x_count <= 0; -- end if; -- ram_update_y_count <= ram_update_x_count + 1; -- else -- ram_update_y_count <= 0; -- end if; -- ram_update_count <= ram_update_count + 1; -- else -- ram_update_slow(1) <= '0'; -- ram_update_count <= 0; -- end if; -- elsif ram_update = "001" then -- user_text -- ram_update_slow <= "001"; -- if ram_update_count < 8 then -- if ram_update_y_count < 16 then -- if ram_update_x_count < 8 then -- ram_addr_output <= std_logic_vector(to_unsigned(66102 + ram_update_x_count -- + (ram_update_y_count * 384), 17)); -- font_rom_addr <= unsigned("000" & ascii_char); -- FIX THIS (concurency) -- if font_rom_data(ram_update_x_count) = '1' then -- ram_val_output <= x"000"; -- else -- ram_val_output <= x"FFF"; -- end if; -- ram_update_x_count <= ram_update_x_count + 1; -- else -- ram_update_x_count <= 0; -- end if; -- ram_update_y_count <= ram_update_x_count + 1; -- else -- ram_update_y_count <= 0; -- end if; -- ram_update_count <= ram_update_count + 1; -- else -- ram_update_slow(0) <= '0'; -- ram_update_count <= 0; -- end if; -- else -- ram_update_slow <= "000"; --end if; ---- else -- ram_reset = 1 ---- -- Drawing Screen (sys_text and user_text update automatically) ---- if ram_reset_count < 65536 then ---- ram_reset_slow <= '1'; ---- ram_reset_count <= ram_reset_count + 1; ---- ram_addr_output <= "0" & std_logic_vector(ram_reset_count); ---- else ---- ram_reset_slow <= '0'; ---- ram_reset_count <= x"0000"; ---- end if; end if; end if; end process; end Behavioral;
gpl-3.0
7e4f11009e24ffc22e0e2138712ae330
0.446241
3.982389
false
false
false
false
TanND/Electronic
VHDL/D7_C1.vhd
1
1,089
library IEEE; use IEEE.STD_LOGIC_1164.all; entity D7_C1 is generic (n:integer :=9); port( rst : in STD_LOGIC; clk : in STD_LOGIC; seg1 : out STD_LOGIC_VECTOR(7 downto 0) ); end D7_C1; architecture D7_C1 of D7_C1 is begin process(rst,clk) variable temp:integer range 0 to 9; variable num:integer range 0 to 1:=0; begin if (rst='1') then temp:=0; elsif (rising_edge(clk)) then if (num = 0) then if (temp=n) then num:=1; else temp:=temp+1; end if; end if; if (num = 1) then if (temp=0) then num:=0; else temp:=temp-1; end if; end if; end if; case temp is when 0 => seg1<= x"C0"; when 1 => seg1<= x"F9"; when 2 => seg1<= x"A4"; when 3 => seg1<= x"B0"; when 4 => seg1<= x"99"; when 5 => seg1<= x"92"; when 6 => seg1<= x"82"; when 7 => seg1<= x"F8"; when 8 => seg1<= x"80"; when 9 => seg1<= x"90"; when others =>NULL; end case; end process; end D7_C1; --rst=500Khz; clk=20Mhz;
apache-2.0
6a8c09b2f3dbbd2169ca5fdfd8e1a1e0
0.507805
2.688889
false
false
false
false
carlosrd/DAS
P4/Parte A/cronometro.vhd
1
5,334
library IEEE; use IEEE.STD_LOGIC_1164.ALL; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_unsigned.ALL; USE IEEE.std_logic_arith.ALL; entity cronometro is port ( -- Entradas startStop: in std_logic; puestaCero: in std_logic; clk: in std_logic; rst: in std_logic; -- Salidas rightSegs: out std_logic_vector(7 downto 0); leftSegs: out std_logic_vector(7 downto 0); puntoDec: out std_logic ); end cronometro; architecture Behavioral of cronometro is signal ssDebounced,ssDebFallEdge,ssDebRiseEdge: std_logic; signal pODebounced,pODebFallEdge,pODebRiseEdge: std_logic; signal t: std_logic; signal salidaCont5kk: std_logic_vector(22 downto 0); signal salidaContDecimas, salidaContUnidades,salidaContDecenas: std_logic_vector(3 downto 0); signal cuentaDecimas, cuentaUnidades, cuentaDecenas: std_logic; signal cs1 : std_logic_vector( 22 downto 0 ); signal cs2,cs3,cs4 : std_logic_vector( 3 downto 0 ); signal lit1,lit2,lit3: std_logic; component debouncer port(rst: in std_logic; clk: in std_logic; x: in std_logic; xDeb: out std_logic; xDebFallingEdge: out std_logic; xDebRisingEdge: out std_logic); end component; component binToSeg is port ( bin: in std_logic_vector(3 downto 0); displaySeg: out std_logic_vector(7 downto 0) -- 7 = A / 6 = B / ... / 0 = H ); end component; begin -- ELIMINACION DE REBOTES EN LOS PUSHBUTTONS debouncerStartStop: debouncer port map (rst,clk,startStop,ssDebounced,ssDebFallEdge,ssDebRiseEdge); debouncerPuestaCero: debouncer port map (rst,clk,puestaCero,pODebounced,pODebFallEdge,pODebRiseEdge); -- CONTADORES contMod5kk: process( clk, cs1, rst, pODebFallEdge, ssDebFallEdge ) begin salidaCont5kk <= cs1; if rst = '0' then cs1 <= conv_std_logic_vector( 0 , 23 ); elsif clk'event and clk = '1' then if pODebFallEdge = '1' then cs1 <= conv_std_logic_vector( 0 , 23 ); elsif t = '1' then if cs1 = conv_std_logic_vector( 4999999 , 23 ) then cs1 <= conv_std_logic_vector( 0 , 23 ); else cs1 <= cs1 + 1; end if; end if; end if; end process; -- contDecimas cuenta cuando se tenga 4.999.999 = 10011000100101100111111 en cont5Millones cuentaDecimas <= salidaCont5kk(22) and salidaCont5kk(19) and salidaCont5kk(18) and salidaCont5kk(14) and salidaCont5kk(11) and salidaCont5kk(9) and salidaCont5kk(8) and salidaCont5kk(5) and salidaCont5kk(4) and salidaCont5kk(3) and salidaCont5kk(2) and salidaCont5kk(1) and salidaCont5kk(0); contDecimas: process( clk, cs2, rst, pODebFallEdge, cuentaDecimas ) begin salidaContDecimas <= cs2; if rst = '0' then cs2 <= conv_std_logic_vector( 0 , 4 ); elsif clk'event and clk = '1' then if pODebFallEdge = '1' then cs2 <= conv_std_logic_vector( 0 , 4 ); elsif cuentaDecimas = '1' then if cs2 = conv_std_logic_vector( 9 , 4 ) then cs2 <= conv_std_logic_vector( 0 , 4 ); else cs2 <= cs2 + 1; end if; end if; end if; end process; -- contUnidades cuenta cuando se tenga 9 = 1001 en contDecimas cuentaUnidades <= (salidaContDecimas(3) and salidaContDecimas(0)) and cuentaDecimas; contUnidades: process( clk, cs3, rst, pODebFallEdge, cuentaUnidades ) begin salidaContUnidades <= cs3; if rst = '0' then cs3 <= conv_std_logic_vector( 0 , 4 ); elsif clk'event and clk = '1' then if pODebFallEdge = '1' then cs3 <= conv_std_logic_vector( 0 , 4 ); elsif cuentaUnidades = '1' then if cs3 = conv_std_logic_vector( 9 , 4 ) then cs3 <= conv_std_logic_vector( 0 , 4 ); else cs3 <= cs3 + 1; end if; end if; end if; end process; cuentaDecenas <= (salidaContUnidades(3) and salidaContUnidades(0)) and (cuentaDecimas and cuentaUnidades); contDecenas: process( clk, cs4, rst, pODebFallEdge, cuentaDecenas ) begin salidaContDecenas <= cs4; if rst = '0' then cs4 <= conv_std_logic_vector( 0 , 4 ); elsif clk'event and clk = '1' then if pODebFallEdge = '1' then cs4 <= conv_std_logic_vector( 0 , 4 ); elsif cuentaDecenas = '1' then if cs4 = conv_std_logic_vector( 5 , 4 ) then cs4 <= conv_std_logic_vector( 0 , 4 ); else cs4 <= cs4 + 1; end if; end if; end if; end process; -- BIESTABLE T -- Usamos el flanco de bajada (fall) porque la placa tiene logica negativa biestableT: process(clk) begin if (rst = '0') then t <= '0'; elsif (clk'event and clk='1') then if (ssDebFallEdge = '1') then t <= not (t); end if; end if; end process; parpadeoPuntoDecimal: process(salidaContDecimas) begin lit1 <= not salidaContDecimas(3) and not salidaContDecimas(2); lit2 <= not salidaContDecimas(3) and not salidaContDecimas(1) and not salidaContDecimas(0); lit3 <= lit1 or lit2; if (lit3 = '1') then puntoDec <= '1'; else puntoDec <= '0'; end if; end process; -- DISPLAYS 8 SEGMENTOS decenasSeg: binToSeg port map (salidaContDecenas,leftSegs); unidadesSeg: binToSeg port map (salidaContUnidades,rightSegs); end Behavioral; -- x3 x2 x1 x0 z -------------------- --0 0 0 0 0 1 --1 0 0 0 1 1 --2 0 0 1 0 1 --3 0 0 1 1 1 --4 0 1 0 0 1 --5 0 1 0 1 0 --6 0 1 1 0 0 --7 0 1 1 1 0 --8 1 0 0 0 0 --9 1 0 0 1 0 -- Mapa de Karnaugh ==> FLASH = (¬ x3)(¬ x2) + (¬ x3)(¬ x1)(¬ x0)
mit
1941cf95149edbbd8daf5c36e2d2e6b8
0.657159
2.924808
false
false
false
false
bruskajp/EE-316
Project4/Vivado_NexysBoard/craddockEE316/craddockEE316.srcs/sources_1/imports/testFolder/ADC_Controller.vhd
1
2,223
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_arith.all; entity ADC_Controller is generic(samples : integer := 128); Port ( iclk : in STD_LOGIC; reset : in STD_LOGIC; EOC : in STD_LOGIC;--i oStart : out STD_LOGIC;--o ALE : out std_logic;--o oOE : buffer std_logic;--o sel : buffer std_logic;--o oWriteReady : out std_logic;--o oClk_en : out std_logic--o ); end entity ADC_Controller; Architecture Behavioral of ADC_Controller is signal clk_en : std_logic; signal clk_cnt : integer := 0; signal state : integer:=0; signal Write_sig : STD_LOGIC := '0'; signal sadc_dataSelect : std_logic := '0'; signal dataCount : integer:= 0; begin oClk_en <= clk_en; oWriteReady <= Write_sig; process(oOE) begin if(rising_edge(oOE)) then dataCount <= dataCount + 1; if dataCount = samples then sadc_dataSelect <= not(sadc_dataSelect); sel <= sadc_dataSelect; dataCount <= 0; end if; end if; end process; clock_enabler: process(iclk) begin if (rising_edge(iclk)) then if (clk_cnt = 49) then clk_cnt <= 0; clk_en <= not(clk_en); else clk_cnt <= clk_cnt + 1; --clk_en <= '0'; end if; end if; end process; Convert: process (iClk, EOC, reset) begin if reset = '1' then oOE <= '0'; ALE <= '0'; oStart <= '0'; state <= 0; Write_sig <= '0'; elsif rising_edge (iClk) and clk_en = '1' then case state is when 0 => oOE <= '0'; ALE <= '0'; oStart <= '0'; state <= 1; Write_sig <= '0'; when 1 => ALE <= '1'; oStart<='0'; state <= 2; when 2 => ALE <= '1'; oStart <= '1'; state <= 3; when 3 => ALE <= '0'; oStart <= '1'; state <= 4; when 4 => ALE <= '0'; oStart <= '0'; state <= 5; when 5 => if (EOC = '1') then state<=6; else state <= 5; end if; when 6 => oOE <= '1'; state <= 7; when 7 => Write_sig <= '1'; state <= 0; when others => state <= 0; end case; end if; end process; end Behavioral;
gpl-3.0
ef30c8e6cefccd9704ee3ab9007b7517
0.527215
2.948276
false
false
false
false
TanND/Electronic
VHDL/D12_C1.vhd
1
570
library IEEE; use IEEE.STD_LOGIC_1164.all; entity D12_C1 is port( load : in STD_LOGIC; clk : in STD_LOGIC; d : in STD_LOGIC_VECTOR(7 downto 0); dout : out STD_LOGIC ); end D12_C1; architecture D12_C1 of D12_C1 is signal t:std_logic; signal temp:std_logic_vector(7 downto 0); begin process(clk,load,d) begin if (load ='1') then temp<=d; elsif (rising_edge(clk)) then t<=temp(7); temp(7 downto 1)<= temp(6 downto 0); temp(0)<='0'; end if; end process; dout<=t; end D12_C1; --load 500khz;clk=20Mhz; d counter 0-11111111 binary 125 ns;
apache-2.0
28bfe31671a45831e921906860a7a1dc
0.650877
2.522124
false
false
false
false
carlosrd/DAS
P4/Parte C (Opcional 2)/debouncer.vhd
4
3,528
------------------------------------------------------------------- -- -- Fichero: -- debouncer.vhd 12/7/2013 -- -- (c) J.M. Mendias -- Diseño Automático de Sistemas -- Facultad de Informática. Universidad Complutense de Madrid -- -- Propósito: -- Elimina los rebotes de una línea binaria mediante la espera -- de 50 ms tras cada flanco detectado -- -- Notas de diseño: -- El timer usado para medir 50 ms esta dimensionado para -- funcionar con un reloj de 50 MHz -- ------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_unsigned.ALL; ENTITY debouncer IS PORT ( rst: IN std_logic; -- Reset asíncrono del sistema clk: IN std_logic; -- Reloj del sistema x: IN std_logic; -- Entrada binaria a la que deben eliminars los rebotes xDeb: OUT std_logic; -- Salida que sique a la entrada pero sin rebotes xDebFallingEdge: OUT std_logic; -- Se activa durante 1 ciclo cada vez que detecta un flanco de subida en x xDebRisingEdge: OUT std_logic -- Se activa durante 1 ciclo cada vez que detecta un flanco de bajada en x ); END debouncer; ARCHITECTURE debouncerArch of debouncer is SIGNAL xSync: std_logic; SIGNAL startTimer, timerEnd: std_logic; BEGIN synchronizer: PROCESS (rst, clk) VARIABLE aux1: std_logic; BEGIN IF (rst='0') THEN aux1 := '1'; xSync <= '1'; ELSIF (clk'EVENT AND clk='1') THEN xSync <= aux1; aux1 := x; END IF; END PROCESS synchronizer; timer: PROCESS (rst, clk) CONSTANT timeOut: std_logic_vector (21 DOWNTO 0) := "1001100010010110100000"; -- 2500000/(50MHz) = 50 ms VARIABLE count: std_logic_vector (21 DOWNTO 0); BEGIN IF (count=timeOut) THEN timerEnd <= '1'; ELSE timerEnd <= '0'; END IF; IF (rst='0') THEN count := timeOut; ELSIF (clk'EVENT AND clk='1') THEN IF (startTimer='1') THEN count := (OTHERS=>'0'); ELSIF (timerEnd='0') THEN count := count + 1; END IF; END IF; END PROCESS timer; controller: PROCESS (xSync, rst, clk) TYPE states IS (waitingKeyDown, keyDownDebouncing, waitingKeyUp, KeyUpDebouncing); VARIABLE state: states; BEGIN xDeb <= '1'; xDebFallingEdge <= '0'; xDebRisingEdge <= '0'; startTimer <= '0'; CASE state IS WHEN waitingKeyDown => IF (xSync='0') THEN xDebFallingEdge <= '1'; startTimer <= '1'; END IF; WHEN keyDownDebouncing => xDeb <= '0'; WHEN waitingKeyUp => xDeb <= '0'; IF (xSync='1') THEN xDebRisingEdge <= '1'; startTimer <= '1'; END IF; WHEN KeyUpDebouncing => NULL; END CASE; IF (rst='0') THEN state := waitingKeyDown; ELSIF (clk'EVENT AND clk='1') THEN CASE state IS WHEN waitingKeyDown => IF (xSync='0') THEN state := keyDownDebouncing; END IF; WHEN keyDownDebouncing => IF (timerEnd='1') THEN state := waitingKeyUp; END IF; WHEN waitingKeyUp => IF (xSync='1') THEN state := KeyUpDebouncing; END IF; WHEN KeyUpDebouncing => IF (timerEnd='1') THEN state := waitingKeyDown; END IF; END CASE; END IF; END PROCESS controller; END debouncerArch;
mit
90d2932dc36f0c71b553e8fc6ab9ed27
0.553855
4.013652
false
false
false
false
SoCdesign/EHA
RTL/Immortal_Chip/FIFO_Data_path.vhd
1
2,770
library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.ALL; entity FIFO_data_path is generic ( DATA_WIDTH: integer := 32 ); port ( reset: in std_logic; clk: in std_logic; RX: in std_logic_vector(DATA_WIDTH-1 downto 0); read_pointer, write_pointer: in std_logic_vector(3 downto 0); write_en : in std_logic; Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0) ); end FIFO_data_path; architecture behavior of FIFO_data_path is signal FIFO_MEM_1 , FIFO_MEM_1_in : std_logic_vector(DATA_WIDTH-1 downto 0); signal FIFO_MEM_2 , FIFO_MEM_2_in : std_logic_vector(DATA_WIDTH-1 downto 0); signal FIFO_MEM_3 , FIFO_MEM_3_in : std_logic_vector(DATA_WIDTH-1 downto 0); signal FIFO_MEM_4 , FIFO_MEM_4_in : std_logic_vector(DATA_WIDTH-1 downto 0); begin process (clk, reset)begin if reset = '0' then FIFO_MEM_1 <= (others=>'0'); FIFO_MEM_2 <= (others=>'0'); FIFO_MEM_3 <= (others=>'0'); FIFO_MEM_4 <= (others=>'0'); elsif clk'event and clk = '1' then if write_en = '1' then --write into the memory FIFO_MEM_1 <= FIFO_MEM_1_in; FIFO_MEM_2 <= FIFO_MEM_2_in; FIFO_MEM_3 <= FIFO_MEM_3_in; FIFO_MEM_4 <= FIFO_MEM_4_in; end if; end if; end process; process(RX, write_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin case( write_pointer ) is when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4; when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX; when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; end case ; end process; process(read_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin case( read_pointer ) is when "0001" => Data_out <= FIFO_MEM_1; when "0010" => Data_out <= FIFO_MEM_2; when "0100" => Data_out <= FIFO_MEM_3; when "1000" => Data_out <= FIFO_MEM_4; when others => Data_out <= FIFO_MEM_1; end case ; end process; end behavior;
gpl-3.0
e1a95840827b5056ceca6d1580bd0447
0.556318
2.885417
false
false
false
false
bruskajp/EE-316
Project2/Quartus_DE2Board/Hex_ROM.vhd
1
6,206
-- megafunction wizard: %ROM: 1-PORT% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altsyncram -- ============================================================ -- File Name: Hex_ROM.vhd -- Megafunction Name(s): -- altsyncram -- -- Simulation Library Files(s): -- altera_mf -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 13.0.0 Build 156 04/24/2013 SJ Full Version -- ************************************************************ --Copyright (C) 1991-2013 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY Hex_ROM IS PORT ( address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); clock : IN STD_LOGIC := '1'; q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) ); END Hex_ROM; ARCHITECTURE SYN OF hex_rom IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0); COMPONENT altsyncram GENERIC ( clock_enable_input_a : STRING; clock_enable_output_a : STRING; init_file : STRING; intended_device_family : STRING; lpm_hint : STRING; lpm_type : STRING; numwords_a : NATURAL; operation_mode : STRING; outdata_aclr_a : STRING; outdata_reg_a : STRING; widthad_a : NATURAL; width_a : NATURAL; width_byteena_a : NATURAL ); PORT ( address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); clock0 : IN STD_LOGIC ; q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) ); END COMPONENT; BEGIN q <= sub_wire0(15 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( clock_enable_input_a => "BYPASS", clock_enable_output_a => "BYPASS", init_file => "Hex_ROM.mif", intended_device_family => "Cyclone II", lpm_hint => "ENABLE_RUNTIME_MOD=NO", lpm_type => "altsyncram", numwords_a => 256, operation_mode => "ROM", outdata_aclr_a => "NONE", outdata_reg_a => "CLOCK0", widthad_a => 8, width_a => 16, width_byteena_a => 1 ) PORT MAP ( address_a => address, clock0 => clock, q_a => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" -- Retrieval info: PRIVATE: AclrByte NUMERIC "0" -- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: Clken NUMERIC "0" -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -- Retrieval info: PRIVATE: MIFfilename STRING "Hex_ROM.mif" -- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256" -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" -- Retrieval info: PRIVATE: RegOutput NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" -- Retrieval info: PRIVATE: WidthAddr NUMERIC "8" -- Retrieval info: PRIVATE: WidthData NUMERIC "16" -- Retrieval info: PRIVATE: rden NUMERIC "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: INIT_FILE STRING "Hex_ROM.mif" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" -- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" -- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL Hex_ROM.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL Hex_ROM.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL Hex_ROM.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL Hex_ROM.bsf FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL Hex_ROM_inst.vhd FALSE -- Retrieval info: LIB_FILE: altera_mf
gpl-3.0
889842974e4ff7dc81a73da5a960d10e
0.649372
3.490439
false
false
false
false
TUM-LIS/faultify
hardware/testcases/viterbi/fpga_sim/xpsLibraryPath_viterbi_400_578/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/vhdl/lfsr.vhd
17
4,148
---------------------------------------------------------------------------- ---- Create Date: 13:06:08 07/28/2010 ---- ---- Design Name: lfsr ---- ---- Project Name: lfsr_randgen ---- ---- Description: ---- ---- A random number generator based on linear feedback shift ---- ---- register(LFSR).A LFSR is a shift register whose input bit is a ---- ---- linear function of its previous state.The detailed documentation ---- ---- is available in the file named manual.pdf. ---- ---- ---- ---------------------------------------------------------------------------- ---- ---- ---- This file is a part of the lfsr_randgen project at ---- ---- http://www.opencores.org/ ---- ---- ---- ---- Author(s): ---- ---- Vipin Lal, [email protected] ---- ---- ---- ---------------------------------------------------------------------------- ---- ---- ---- Copyright (C) 2010 Authors and OPENCORES.ORG ---- ---- ---- ---- This source file may be used and distributed without ---- ---- restriction provided that this copyright statement is not ---- ---- removed from the file and that any derivative work contains ---- ---- the original copyright notice and the associated disclaimer. ---- ---- ---- ---- This source file is free software; you can redistribute it ---- ---- and/or modify it under the terms of the GNU Lesser General ---- ---- Public License as published by the Free Software Foundation; ---- ---- either version 2.1 of the License, or (at your option) any ---- ---- later version. ---- ---- ---- ---- This source is distributed in the hope that it will be ---- ---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ---- PURPOSE. See the GNU Lesser General Public License for more ---- ---- details. ---- ---- ---- ---- You should have received a copy of the GNU Lesser General ---- ---- Public License along with this source; if not, download it ---- ---- from http://www.opencores.org/lgpl.shtml ---- ---- ---- ---------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use IEEE.NUMERIC_STD.ALL; library work; use work.lfsr_pkg.ALL; entity lfsr is generic (width : integer := 4; seed : integer :=1); port (clk : in std_logic; --set_seed : in std_logic; --seed : in std_logic_vector(width-1 downto 0); rand_out : out std_logic_vector(width-1 downto 0) ); end lfsr; architecture Behavioral of lfsr is begin process(clk) variable rand_temp : std_logic_vector (width-1 downto 0):=std_logic_vector(to_unsigned(seed,width));--(0 => '1',others => '0'); variable temp : std_logic := '0'; begin if(rising_edge(clk)) then --if(set_seed = '1') then --rand_temp := seed; --end if; temp := xor_gates(rand_temp); rand_temp(width-1 downto 1) := rand_temp(width-2 downto 0); rand_temp(0) := temp; end if; rand_out <= rand_temp; end process; end Behavioral;
gpl-2.0
751074debe95b788bc5bcea4e4b97386
0.412729
5.159204
false
false
false
false
bruskajp/EE-316
Project2/Vivado_NexysBoard/project_2b/project_2b.srcs/sources_1/imports/Downloads/Nexys4_Display.vhd
1
3,862
---------------------------------------------------------------------------------- -- Company: -- Engineer: John Dobson -- -- Create Date: 10/08/2013 08:05:27 PM -- Design Name: -- Module Name: Nexys3_Display - Behavioral -- Project Name: -- Target Devices: Nexys3 Spartan-6, Alterra DE0-Nano -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Nexys4_Display is Port ( Hex_IN : in STD_LOGIC_VECTOR (15 downto 0); iCLK : in STD_LOGIC; An_OUT : out STD_LOGIC_VECTOR (7 downto 0); SevSeg_OUT : out STD_LOGIC_VECTOR (7 downto 0)); end Nexys4_Display; architecture Behavioral of Nexys4_Display is signal DIV : unsigned(15 DOWNTO 0) :=X"0000"; --Signals for StateMachine: type stateType is (A, B, C, D); Signal Q : std_logic_vector(3 downto 0); Signal Y : std_logic_vector(1 downto 0); signal CS, NS : stateType; --Signals for Splitter: signal X : std_logic_vector (3 downto 0); signal clk_en: std_logic; signal An_OFF : std_logic_vector(3 downto 0); BEGIN StateMachine: --code pulled from Ring_Counter.vhd process(iCLK) begin if rising_edge(iCLK) then if DIV >= X"31" then DIV <= X"0000"; clk_en <= '1'; else DIV <= DIV +1; clk_en <= '0'; end if; end if; end process; Process(iCLK, clk_en) Begin if rising_edge(iCLK) and clk_en = '1' then CS <= NS; end if; end process; process (CS) begin Y <= "00"; case CS is when A => Y <= "00"; Q <= "1110"; NS <= B; when B => Y <= "01"; Q <= "1101"; NS <= C; when C => Y <= "10"; Q <= "1011"; NS <= D; when D => Y <= "11"; Q <= "0111"; NS <= A; end case; end process; An_OFF <= "1111"; An_OUT <= An_OFF & Q; HexSplitter: Process(Hex_IN, Y) begin case Y is when "00" => X <= Hex_IN(3 downto 0); when "01" => X <= Hex_IN(7 downto 4); when "10" => X <= Hex_IN(11 downto 8); when "11" => X <= Hex_IN(15 downto 12); when others => X <= "1111"; end case; end process; HexToSevenSeg: Process(X) begin case X is when "0000" => SevSeg_OUT <= "11000000"; -- 0 when "0001" => SevSeg_OUT <= "11111001"; -- 1 when "0010" => SevSeg_OUT <= "10100100"; -- 2 when "0011" => SevSeg_OUT <= "10110000"; -- 3 when "0100" => SevSeg_OUT <= "10011001"; -- 4 when "0101" => SevSeg_OUT <= "10010010"; -- 5 when "0110" => SevSeg_OUT <= "10000010"; -- 6 when "0111" => SevSeg_OUT <= "11111000"; -- 7 when "1000" => SevSeg_OUT <= "10000000"; -- 8 when "1001" => SevSeg_OUT <= "10011000"; -- 9 when "1010" => SevSeg_OUT <= "10001000"; -- A when "1011" => SevSeg_OUT <= "10000011"; -- b when "1100" => SevSeg_OUT <= "11000110"; -- C when "1101" => SevSeg_OUT <= "10100001"; -- d when "1110" => SevSeg_OUT <= "10000110"; -- E when "1111" => SevSeg_OUT <= "10001110"; -- F when others => SevSeg_OUT <= "11111111"; end case; end process; end Behavioral;
gpl-3.0
04199cc98ce5da1b6fb2a7324bfcb3cd
0.498187
3.399648
false
false
false
false
JarrettR/FPGA-Cryptoparty
sdk/examples/usb-fpga-1.15y/intraffic/fpga/intraffic.vhd
6
2,355
library ieee; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity intraffic is port( RESET : in std_logic; CS : in std_logic; CONT : in std_logic; IFCLK : in std_logic; FD : out std_logic_vector(15 downto 0); SLOE : out std_logic; SLRD : out std_logic; SLWR : out std_logic; FIFOADR0 : out std_logic; FIFOADR1 : out std_logic; PKTEND : out std_logic; FLAGB : in std_logic -- SCL : in std_logic; -- SDA : in std_logic ); end intraffic; architecture RTL of intraffic is ---------------------------- -- test pattern generator -- ---------------------------- -- 30 bit counter signal GEN_CNT : std_logic_vector(29 downto 0); signal INT_CNT : std_logic_vector(6 downto 0); signal FIFO_WORD : std_logic; signal SLWR_R : std_logic; signal FD_R : std_logic_vector(15 downto 0); begin SLOE <= '1' when CS = '1' else 'Z'; SLRD <= '1' when CS = '1' else 'Z'; SLWR <= SLWR_R when CS = '1' else 'Z'; FIFOADR0 <= '0' when CS = '1' else 'Z'; FIFOADR1 <= '0' when CS = '1' else 'Z'; PKTEND <= '1' when CS = '1' else 'Z'; -- no data alignment FD <= FD_R when CS = '1' else (others => 'Z'); dpIFCLK: process (IFCLK, RESET) begin -- reset if RESET = '1' then GEN_CNT <= ( others => '0' ); INT_CNT <= ( others => '0' ); FIFO_WORD <= '0'; SLWR_R <= '1'; -- IFCLK elsif IFCLK'event and IFCLK = '1' then if CONT = '1' or FLAGB = '1' then if FIFO_WORD = '0' then FD_R(14 downto 0) <= GEN_CNT(14 downto 0); else FD_R(14 downto 0) <= GEN_CNT(29 downto 15); end if; FD_R(15) <= FIFO_WORD; if FIFO_WORD = '1' then GEN_CNT <= GEN_CNT + '1'; if INT_CNT = conv_std_logic_vector(99,7) then INT_CNT <= ( others => '0' ); else INT_CNT <= INT_CNT + '1'; end if; end if; FIFO_WORD <= not FIFO_WORD; end if; if ( INT_CNT >= conv_std_logic_vector(90,7) ) and ( CONT = '0' ) then SLWR_R <= '1'; else SLWR_R <= '0'; end if; end if; end process dpIFCLK; end RTL;
gpl-3.0
346b587fb108e48957476e7b037d7361
0.487049
3.15261
false
false
false
false
lnls-dig/dsp-cores
hdl/modules/strobe_gen/strobe_gen.vhd
1
2,870
------------------------------------------------------------------------------- -- Title : Strobe generator -- Project : ------------------------------------------------------------------------------- -- File : strobe_gen.vhd -- Author : aylons <aylons@LNLS190> -- Company : -- Created : 2014-03-11 -- Last update: 2014-06-20 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: Generates strobes at decimation rate for CIC filter ------------------------------------------------------------------------------- -- Copyright (c) 2014 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2014-03-11 1.0 aylons Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.math_real.all; use ieee.numeric_std.all; library UNISIM; use UNISIM.vcomponents.all; library work; use work.dsp_cores_pkg.all; ------------------------------------------------------------------------------- entity strobe_gen is generic ( g_maxrate : natural := 2048; g_bus_width : natural := 11 ); port ( clk_i : in std_logic; rst_i : in std_logic; ce_i : in std_logic; ratio_i : in std_logic_vector(g_bus_width-1 downto 0); strobe_o : out std_logic ); end entity strobe_gen; ------------------------------------------------------------------------------- architecture str of strobe_gen is --signal zeroed : std_logic := '0'; begin -- architecture str cmp_xlclockdriver : xlclockdriver generic map ( period => g_maxrate, log_2_period => g_bus_width ) port map ( sysclk => clk_i, sysclr => rst_i, sysce => ce_i, clk => open, clr => open, ce => strobe_o, ce_logic => open ); --counting : process(clk_i ) -- variable count : natural := 0; --begin -- if rising_edge(clk_i ) then -- if rst_i = '1' then -- count := to_integer(unsigned(ratio_i))-1; -- else -- if ce_i = '1' then -- if count = 0 then -- count := to_integer(unsigned(ratio_i))-1; -- zeroed <= '1'; -- else -- count := count - 1; -- zeroed <= '0'; -- end if; --count = 0 -- end if; -- ce -- end if; -- reset -- end if; -- rising_edge --end process counting; --strobe_o <= zeroed; end architecture str; -------------------------------------------------------------------------------
lgpl-3.0
321dce2b2b5da5141d07f3d144696a9c
0.373519
4.449612
false
false
false
false
lnls-dig/dsp-cores
hdl/modules/cordic_iter/cordic.vhd
1
16,978
---------------------------------------------------------------------------------- -- Engineer: Matthias Werner -- Create Date: 23:53:29 06/26/2014 -- Module Name: cordic - Behavioral -- Target Devices: tried for Virtex-5 and Virtex-6, other devices should be possible ---------------------------------------------------------------------------------- -- Description: -- Conversion from rectangular to polar coordinates using CORDIC algorithm -- GENERAL: -- This is a serial algorithm designed to achieve low latency even at moderate clk frequencies. -- Depending on the clk frequency, more than one iteration per clk can be executed, -- controlled by the ITER_PER_CLK parameter. As it is a serial algorithm, a new input -- value is allowed only every ..... clk cycles. -- The algorithm will not allow to do all iterations in one clk cycle; even at very low clk -- frequencies at least two clk cycles must be selected: NUM_ITER / ITER_PER_CLK must be > 1. -- The "Cordic Factor" (0.607252935008881...) is not yet applied; this has to be done in an extra -- step for the result "s_x_o" if necessary. -- PRECISION: -- The maximum precision for X, Y and phase is about 48 bits, limited by the precision -- of the arctan tables which are generated using the double precision math library. -- As the built-in arctan function offers only very limited precision, an extra arctan -- function (not generally usable because of the limited argument range) was designed -- using a Taylor series. -- For a result to be precise to the last digit, the internal precision should be higher -- than the output port bit width: for example XY_CALC_WID should be about X_OUT_WID + LOG2(NUM_ITER) + 1, -- and PH_CALC_WID should be about PH_OUT_WID + LOG2(NUM_ITER) + 1. -- Also the number of iterations NUM_ITER must be set appropriately: every iteration -- will increase the precision of the phase output by about 1 bit and the precision of the -- X output by about 2 bits. NUM_ITER can be rounded up to be an integer multiple of -- ITER_PER_CLK. -- Rounding can be selected by the parameter ROUNDING. The rounded value is not registered -- again to save one clock cycle. -- INPUT REGISTER: -- An input register can be selected by USE_INREG = True, this adds an extra clk cycle. -- OUTPUT REGISTER: -- If ROUNDING = False, the result is registered. -- If ROUNDING = True, an additional "add" operation behind the "raw" result register -- executes the rounding, but no additional output register is implemented. -- So the number of clk cycles appears the same with / without rounding. -- CLOCK FREQUENCY: -- This algorithm is not optimized for fastest clock speed with 1 iteration per clk cycle; -- for this case, the Xilinx CORDIC IP-Core is faster. -- For moderate clk frequencies (e.g. 180 MHz at 18 bit I/O width), 2 iterations per clk -- cycle are possible; at 110 MHz even 4 iterations per clk can be achieved. -- RECIPE: -- Select input and output bit width XY_IN_WID, X_OUT_WID and PH_OUT_WID. -- Select USE_INREG and ROUNDING. -- Start with a "reasonable" NUM_ITER, then do the following two steps iteratively: -- Set XY_CALC_WID = X_OUT_WID + LOG2(NUM_ITER) + 1, PH_CALC_WID = PH_OUT_WID + LOG2(NUM_ITER) + 1. -- Set NUM_ITER = maximum (PH_CALC_WID, X_OUT_WID/2 + 3). -- Try which maximum ITER_PER_CLK is possible with the given clk frequency; -- round up NUM_ITER to be an integer multiple of ITER_PER_CLK; -- make sure that NUM_ITER > ITER_PER_CLK. -- If desired, do a fine tuning of XY_CALC_WID, PH_CALC_WID, NUM_ITER to -- achieve the desired precision with the least number of clk cycles and / or -- with the least FPGA resources; use the simulator to check the precision. -- HINT: -- For implementation (also for clock speed check), set parameters in file cordic.vhd; -- for simulation, set parameters in your testbench ------------------------------------------------------------------------------- -- C O P Y R I G H T N O T E : ------------------------------------------------------------------------------- -- This file is free software: you can redistribute it and/or modify -- it under the terms of the GNU Lesser General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This code is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU Lesser General Public License for more details. -- -- You should have received a copy of the GNU Lesser General Public License. -- If not, see <http://www.gnu.org/licenses/>. -- Copyright (c) 2015 Matthias Werner ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.math_real.all; use IEEE.NUMERIC_STD.all; entity cordic is generic (XY_CALC_WID : positive := 32; -- Number of bits for internal X and Y calculation XY_IN_WID : positive := 26; -- Number of bits for X an Y input ports X_OUT_WID : positive := 26; -- Number of bits for X output port PH_CALC_WID : positive := 30; -- Number of bits for internal phase calculation PH_OUT_WID : positive := 24; -- Number of bits for phase output NUM_ITER : positive := 24; -- Must be divisible by ITER_PER_CLK; NUM_ITER/ITER_PER_CLK > 1 ITER_PER_CLK : positive := 4; -- Iterations per clk cycle; NUM_ITER must be an integer multiple of -- ... ITER_PER_CLK USE_INREG : boolean := true; -- Use input register if True USE_CE : boolean := true; -- Use clock enable input port "ce" if True ROUNDING : boolean := true); -- Round results (without extra register) port (clk : in std_logic; -- Clock ce : in std_logic; -- Clock enable b_start_in : in std_logic; -- s_x_in and s_y_in valid - 1 clk long s_x_in : in signed (XY_IN_WID-1 downto 0); -- X input - must be valid when b_start_in = '1' s_y_in : in signed (XY_IN_WID-1 downto 0); -- Y input - must be valid when b_start_in = '1' s_x_o : out signed (X_OUT_WID-1 downto 0); -- X result; registered if ROUNDING = False, ... -- ... Cordic Factor is not yet applied. s_ph_o : out signed (PH_OUT_WID-1 downto 0); -- Phase result; registered if ROUNDING = False b_rdy_o : out std_logic :='0'; -- Result valid b_busy_o : out std_logic := '0'); -- Busy states (does not accept new data) end cordic; architecture Behavioral of cordic is -- Parameters and constants derived from Generics constant NUM_LOOPS : positive := NUM_ITER / ITER_PER_CLK; constant TRAIL_ZEROES_XY : signed(XY_CALC_WID - XY_IN_WID - 3 downto 0) := (others => '0'); constant TRAIL_ZEROES_PH : signed (PH_CALC_WID-2 downto 0) := (others => '0'); -- =================================================================== -- Calculate address width of phase table: CEIL(Log2(NUM_ITER/ITER_PER_CLK) -- =================================================================== function ceil_log2(arg : positive) return natural is variable i_result_v : natural; variable arg_m1_v : natural; -- arg-1 as variable begin i_result_v := 0; arg_m1_v := arg-1; for i in 1 to 31 loop if arg_m1_v /= 0 then i_result_v := i; end if; arg_m1_v := arg_m1_v / 2; end loop; return i_result_v; end function; -- Address width of phase table constant TAB_AD_WID : positive := ceil_log2(NUM_ITER/ITER_PER_CLK); -- =================================================================== -- Signals signal i_ix : integer range -1 to NUM_LOOPS := NUM_LOOPS-1; signal s_x_reg : signed (XY_IN_WID-1 downto 0) := (others => '0'); -- Input register X signal s_y_reg : signed (XY_IN_WID-1 downto 0) := (others => '0'); -- Input register Y signal s_x_toCordic : signed (XY_CALC_WID-1 downto 0) := (others => '0'); signal s_y_toCordic : signed (XY_CALC_WID-1 downto 0) := (others => '0'); signal s_ph_toCordic : signed (PH_CALC_WID-1 downto 0) := (others => '0'); signal s_x_fromCordic : signed (XY_CALC_WID-1 downto 0); signal s_y_fromCordic : signed (XY_CALC_WID-1 downto 0); signal s_ph_fromCordic : signed (PH_CALC_WID-1 downto 0); signal s_x_unrounded : signed (XY_CALC_WID-1 downto 0); -- Result x, not (yet) rounded signal s_ph_unrounded : signed (PH_CALC_WID-1 downto 0); -- Result phase, not (yet) rounded signal b_start_dly : std_logic := '0'; -- b_start_in delayed 1 clk signal y_last_state_dly : boolean := true; -- Used to enable output registers ------------------------------------------------------------- -- Function: Calculate CORDIC factor and assign to a constant ------------------------------------------------------------- function calc_cordic_factor return real is variable f_result : real; begin f_result := 1.0; for i in 0 to NUM_LOOPS*ITER_PER_CLK-1 loop f_result := f_result / sqrt(1.0 + 2.0**(-2*i)); -- 2**(int), not 2**(real) -> more precise! end loop; return f_result; end function calc_cordic_factor; -- CORDIC factor constant f_cordic_factor : real := calc_cordic_factor; --------------------------------------------------- begin ------------------- -- Check parameters ------------------- assert (XY_CALC_WID >= 3) and (XY_CALC_WID <= 56) report "XY_CALC_WID must be within 3 .. 56" severity failure; assert (ROUNDING and (XY_CALC_WID > X_OUT_WID)) or (not ROUNDING and (XY_CALC_WID >= X_OUT_WID)) report "Required: XY_CALC_WID > X_OUT_WID if ROUNDING, XY_CALC_WID >= X_OUT_WID if NOT ROUNDING" severity failure; assert (XY_CALC_WID >= XY_IN_WID + 2) report "Required: XY_CALC_WID >= XY_IN_WID + 2" severity failure; assert (PH_CALC_WID >= 2) and (PH_CALC_WID <= 56) report "PH_CALC_WID must be within 2 .. 56" severity failure; assert (ROUNDING and (PH_CALC_WID > PH_OUT_WID)) or (not ROUNDING and (PH_CALC_WID >= PH_OUT_WID)) report "Required: PH_CALC_WID > PH_OUT_WID if ROUNDING, PH_CALC_WID >= PH_OUT_WID if NOT ROUNDING" severity failure; assert (NUM_ITER mod ITER_PER_CLK = 0) report "NUM_ITER must be an integer multiple of ITER_PER_CLK" severity failure; assert (NUM_ITER / ITER_PER_CLK > 1) report "Required: NUM_ITER / ITER_PER_CLK > 1" severity failure; -------------- -- clk process -------------- proc_clk : process(clk) -- Values directly from input ports or from input registers variable s_x_v : signed (XY_IN_WID-1 downto 0); variable s_y_v : signed (XY_IN_WID-1 downto 0); -- Values with range reduced to quadrant 1 or 4 variable s_x_red_v : signed (XY_IN_WID-1 downto 0); -- @ MSB is always '0' here -> always unsigned variable s_y_red_v : signed (XY_IN_WID-1 downto 0); -- Other variables variable b_ph_msb_v : std_logic; variable b_new_iter_v : std_logic; variable y_last_state_v : boolean := false; variable v_busy : boolean := false; -- marks if core is busy begin if rising_edge(clk) then if ((ce = '1') or not USE_CE) then -- With clock enable if USE_CE is True -- Delayed start signal b_start_dly <= b_start_in; -- Decide if new value for iteration loop from inputs, not from last iteration if USE_INREG then b_new_iter_v := b_start_dly; else b_new_iter_v := b_start_in; end if; -- Index counter if b_new_iter_v = '1' then i_ix <= 0; elsif i_ix < NUM_LOOPS-1 then i_ix <= i_ix + 1; end if; -- Input registers s_x_reg <= s_x_in; s_y_reg <= s_y_in; -- Use input registers or not if USE_INREG then s_x_v := s_x_reg; s_y_v := s_y_reg; else s_x_v := s_x_in; s_y_v := s_y_in; end if; -- Range reduction to right plane (+/- PI/2) if s_x_v(s_x_v'high) = '1' then s_x_red_v := - s_x_v; s_y_red_v := - s_y_v; b_ph_msb_v := '1'; -- MSB of phase else s_x_red_v := s_x_v; s_y_red_v := s_y_v; b_ph_msb_v := '0'; end if; -- Control CORDIC iterations if b_new_iter_v = '1' then -- Input to CORDIC from input port s_x_toCordic <= resize(s_x_red_v, s_x_red_v'length+2) & TRAIL_ZEROES_XY; s_y_toCordic <= resize(s_y_red_v, s_x_red_v'length+2) & TRAIL_ZEROES_XY; s_ph_toCordic <= b_ph_msb_v & TRAIL_ZEROES_PH; else -- Input to CORDIC from last CORDIC output s_x_toCordic <= s_x_fromCordic; s_y_toCordic <= s_y_fromCordic; s_ph_toCordic <= s_ph_fromCordic; end if; -- Prepare enable for output registers y_last_state_v := (i_ix = NUM_LOOPS-1); y_last_state_dly <= y_last_state_v; -- Results to register, ready flag if y_last_state_v and not y_last_state_dly then s_x_unrounded <= s_x_fromCordic; s_ph_unrounded <= s_ph_fromCordic; b_rdy_o <= '1'; else b_rdy_o <= '0'; end if; -- Mark busy between receiving b_start and reaching last state if b_start_in = '1' or b_new_iter_v = '1' then v_busy := true; elsif y_last_state_v and v_busy then v_busy := false; end if; -- cannot directly convert from boolean to std_logic if v_busy = true then b_busy_o <= '1'; else b_busy_o <= '0'; end if; end if; end if; end process; ------------------------------------------------------------------------- -- Cut off protection digits and round if desired (without extra register ------------------------------------------------------------------------- -- ROUNDING = True: Cut off protection digits and round gen_round : if ROUNDING generate begin s_x_o <= s_x_unrounded(XY_CALC_WID-1 downto XY_CALC_WID - X_OUT_WID) -- @ result is unsigned + ('0' & s_x_unrounded(XY_CALC_WID - X_OUT_WID -1)); s_ph_o <= s_ph_unrounded(PH_CALC_WID-1 downto PH_CALC_WID - PH_OUT_WID) + ('0' & s_ph_unrounded(PH_CALC_WID - PH_OUT_WID -1)); end generate; -- ROUNDING = False: Cut off protection digits but no round gen_no_round : if not ROUNDING generate begin s_x_o <= s_x_unrounded(XY_CALC_WID-1 downto XY_CALC_WID - X_OUT_WID); s_ph_o <= s_ph_unrounded(PH_CALC_WID-1 downto PH_CALC_WID - PH_OUT_WID); end generate; --------------------------------- -- Iterations for one clock cycle --------------------------------- BLK_ITER : block -- Signals to connect the iteration stages type t_arr_xy is array(0 to ITER_PER_CLK) of signed(XY_CALC_WID-1 downto 0); type t_arr_ph is array(0 to ITER_PER_CLK) of signed(PH_CALC_WID-1 downto 0); signal s_x_i : t_arr_xy; signal s_y_i : t_arr_xy; signal s_ph_i : t_arr_ph; signal u_loop_ix_raw : unsigned (TAB_AD_WID downto 0); signal u_loop_ix : unsigned (TAB_AD_WID-1 downto 0); begin -- Loop index (convert to unsigned in two steps to avoid truncate warning when ... -- i_ix = 2**TAB_AD_WID after the last iteration) u_loop_ix_raw <= to_unsigned(i_ix, TAB_AD_WID+1); u_loop_ix <= u_loop_ix_raw(TAB_AD_WID-1 downto 0); -- Input to first stage s_x_i(0) <= s_x_toCordic; s_y_i(0) <= s_y_toCordic; s_ph_i(0) <= s_ph_toCordic; -- Sequence of iterations in a single clk cycle gen_iter : for i in 0 to ITER_PER_CLK-1 generate -- CORDIC iteration cordic_iter : entity work.cordic_iter generic map( XY_WID => XY_CALC_WID, PH_WID => PH_CALC_WID, NUM_LOOPS => NUM_LOOPS, TAB_AD_WID => TAB_AD_WID, ITER_PER_CLK => ITER_PER_CLK, TAB_OFFS => i ) port map( s_x_in => s_x_i(i), s_y_in => s_y_i(i), u_loop_ix_in => u_loop_ix, s_ph_in => s_ph_i(i), s_x_o => s_x_i(i+1), s_y_o => s_y_i(i+1), s_ph_o => s_ph_i(i+1) ); end generate; -- Output from last stage s_x_fromCordic <= s_x_i(ITER_PER_CLK); s_y_fromCordic <= s_y_i(ITER_PER_CLK); s_ph_fromCordic <= s_ph_i(ITER_PER_CLK); end block BLK_ITER; end architecture Behavioral;
lgpl-3.0
b753e25122398e6dd8d60ed4e091c7c2
0.567146
3.554858
false
false
false
false
TUM-LIS/faultify
hardware/testcases/viterbi/fpga_sim/xpsLibraryPath_viterbi_400_578/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/vhdl/faultify_binomial_gen.vhd
17
2,919
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity faultify_binomial_gen is generic ( width : integer := 32); port ( clk : in std_logic; rst_n : in std_logic; seed_in_en : in std_logic; seed_in : in std_logic; seed_out_c : out std_logic; prob_in_en : in std_logic; prob_in : in std_logic; prob_out_c : out std_logic; shift_en : in std_logic; data_out : out std_logic; data_out_valid : out std_logic); end faultify_binomial_gen; architecture behav of faultify_binomial_gen is signal prob_srl : std_logic_vector(width-1 downto 0); signal prsn_srl : std_logic_vector(63 downto 0); signal prsn_srl_in : std_logic; signal prob_srl_in : std_logic; type TapPointArray is array (3 downto 0) of integer; constant Tap : TapPointArray := (63, 62, 60, 59); signal par_fdbk : std_logic; signal cnt : integer range 0 to width; signal prsn_out, prob_out, done : std_logic; begin -- behav process (clk, rst_n) begin -- process if rst_n = '0' then -- asynchronous reset (active low) --prob_srl <= (others => '0'); --prsn_srl <= (others => '0'); elsif clk'event and clk = '1' then -- rising clock edge if shift_en = '1' then prob_srl <= prob_srl_in & prob_srl(prob_srl'high downto 1); prsn_srl <= prsn_srl(prsn_srl'high-1 downto 0) & prsn_srl_in; end if; end if; end process; prsn_srl_in <= seed_in when seed_in_en = '1' else par_fdbk; prob_srl_in <= prob_in when prob_in_en = '1' else prob_srl(prob_srl'low); par_fdbk <= prsn_srl(Tap(0)) xor prsn_srl(Tap(1)) xor prsn_srl(Tap(2)) xor prsn_srl(Tap(3)); prob_out <= prob_srl(prob_srl'low); prsn_out <= prsn_srl(prsn_srl'high); prob_out_c <= prob_out; seed_out_c <= prsn_out; process (clk, rst_n) begin -- process if rst_n = '0' then -- asynchronous reset (active low) cnt <= 0; data_out <= '0'; elsif clk'event and clk = '1' then -- rising clock edge if shift_en = '1' then cnt <= cnt + 1; if cnt < width and done = '0' then if (prsn_out = '0') and (prob_out = '1') then data_out <= '1'; done <= '1'; --data_out_valid <= '1'; elsif prsn_out = '1' and prob_out = '0' then data_out <= '0'; done <= '1'; --data_out_valid <= '1'; else done <= '0'; --data_out <= '0'; --data_out_valid <= '0'; end if; end if; if cnt = width -1 then done <= '0'; cnt <= 0; --data_out_valid <= '0'; end if; --if done = '1' then --data_out_valid <= '0'; --end if; end if; end if; end process; end;
gpl-2.0
2c35b74a05a4960ea933c798d5193f35
0.519013
3.125268
false
false
false
false
lnls-dig/dsp-cores
hdl/testbench/cic/wb_bpm_swap/wb_bpm_swap.vhd
1
9,413
------------------------------------------------------------------------------ -- Title : Wishbone BPM SWAP flat interface ------------------------------------------------------------------------------ -- Author : Jose Alvim Berkenbrock -- Company : CNPEM LNLS-DIG -- Platform : FPGA-generic ------------------------------------------------------------------------------- -- Description: Wishbone interface with BPM Swap core. In flat style. ------------------------------------------------------------------------------- -- Copyright (c) 2013 CNPEM -- Licensed under GNU Lesser General Public License (LGPL) v3.0 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2013-04-12 1.0 jose.berkenbrock Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; -- Main Wishbone Definitions use work.wishbone_pkg.all; -- BPM cores use work.swap_pkg.all; -- Register Bank use work.bpm_swap_wbgen2_pkg.all; entity wb_bpm_swap is generic ( g_interface_mode : t_wishbone_interface_mode := CLASSIC; g_address_granularity : t_wishbone_address_granularity := WORD; g_delay_vec_width : natural := 8; g_swap_div_freq_vec_width : natural := 16; g_ch_width : natural := 16 ); port ( rst_n_i : in std_logic; clk_sys_i : in std_logic; fs_rst_n_i : in std_logic; fs_clk_i : in std_logic; ----------------------------- -- Wishbone signals ----------------------------- wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0'); wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0'); wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0); wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0) := (others => '0'); wb_we_i : in std_logic := '0'; wb_cyc_i : in std_logic := '0'; wb_stb_i : in std_logic := '0'; wb_ack_o : out std_logic; wb_stall_o : out std_logic; ----------------------------- -- External ports ----------------------------- -- Input data from ADCs cha_i : in std_logic_vector(g_ch_width-1 downto 0); chb_i : in std_logic_vector(g_ch_width-1 downto 0); chc_i : in std_logic_vector(g_ch_width-1 downto 0); chd_i : in std_logic_vector(g_ch_width-1 downto 0); ch_valid_i : in std_logic; -- Output data to BPM DSP chain cha_o : out std_logic_vector(g_ch_width-1 downto 0); chb_o : out std_logic_vector(g_ch_width-1 downto 0); chc_o : out std_logic_vector(g_ch_width-1 downto 0); chd_o : out std_logic_vector(g_ch_width-1 downto 0); ch_tag_o : out std_logic_vector(0 downto 0); ch_valid_o : out std_logic; -- RFFE swap clock (or switchwing clock) rffe_swclk_o : out std_logic; -- RFFE swap clock synchronization trigger sync_trig_i : in std_logic ); end wb_bpm_swap; architecture rtl of wb_bpm_swap is constant c_periph_addr_size : natural := 1+2; signal fs_rst_n : std_logic; ----------------------------- -- Wishbone Register Interface signals ----------------------------- -- wb_bpm_swap reg structure signal regs_in : t_bpm_swap_in_registers; signal regs_out : t_bpm_swap_out_registers; ----------------------------- -- Wishbone slave adapter signals/structures ----------------------------- signal wb_slv_adp_out : t_wishbone_master_out; signal wb_slv_adp_in : t_wishbone_master_in; signal resized_addr : std_logic_vector(c_wishbone_address_width-1 downto 0); signal deswap_delay : std_logic_vector(g_delay_vec_width-1 downto 0); component wb_bpm_swap_regs port ( rst_n_i : in std_logic; clk_sys_i : in std_logic; wb_adr_i : in std_logic_vector(0 downto 0); wb_dat_i : in std_logic_vector(31 downto 0); wb_dat_o : out std_logic_vector(31 downto 0); wb_cyc_i : in std_logic; wb_sel_i : in std_logic_vector(3 downto 0); wb_stb_i : in std_logic; wb_we_i : in std_logic; wb_ack_o : out std_logic; wb_stall_o : out std_logic; fs_clk_i : in std_logic; regs_i : in t_bpm_swap_in_registers; regs_o : out t_bpm_swap_out_registers ); end component; begin ----------------------------- -- Slave adapter for Wishbone Register Interface ----------------------------- cmp_slave_adapter : wb_slave_adapter generic map ( g_master_use_struct => true, g_master_mode => PIPELINED, g_master_granularity => WORD, g_slave_use_struct => false, g_slave_mode => g_interface_mode, g_slave_granularity => g_address_granularity ) port map ( clk_sys_i => clk_sys_i, rst_n_i => rst_n_i, master_i => wb_slv_adp_in, master_o => wb_slv_adp_out, sl_adr_i => resized_addr, sl_dat_i => wb_dat_i, sl_sel_i => wb_sel_i, sl_cyc_i => wb_cyc_i, sl_stb_i => wb_stb_i, sl_we_i => wb_we_i, sl_dat_o => wb_dat_o, sl_ack_o => wb_ack_o, sl_rty_o => open, sl_err_o => open, sl_stall_o => wb_stall_o ); -- See wb_bpm_swap_port.vhd for register bank addresses. resized_addr(c_periph_addr_size-1 downto 0) <= wb_adr_i(c_periph_addr_size-1 downto 0); --cbar_master_out(0).adr(c_periph_addr_size-1 downto 0); resized_addr(c_wishbone_address_width-1 downto c_periph_addr_size) <= (others => '0'); -- Register Bank / Wishbone Interface cmp_wb_bpm_swap_regs : wb_bpm_swap_regs port map ( rst_n_i => rst_n_i, clk_sys_i => clk_sys_i, wb_adr_i => wb_slv_adp_out.adr(0 downto 0), wb_dat_i => wb_slv_adp_out.dat, wb_dat_o => wb_slv_adp_in.dat, wb_cyc_i => wb_slv_adp_out.cyc, wb_sel_i => wb_slv_adp_out.sel, wb_stb_i => wb_slv_adp_out.stb, wb_we_i => wb_slv_adp_out.we, wb_ack_o => wb_slv_adp_in.ack, wb_stall_o => wb_slv_adp_in.stall, fs_clk_i => fs_clk_i, regs_i => regs_in, regs_o => regs_out ); -- Registers assignment regs_in.ctrl_reserved_i <= (others => '0'); regs_in.dly_reserved_i <= (others => '0'); -- Unused wishbone signals wb_slv_adp_in.err <= '0'; wb_slv_adp_in.rty <= '0'; cmp_bpm_swap : bpm_swap generic map ( g_delay_vec_width => g_delay_vec_width, g_swap_div_freq_vec_width => g_swap_div_freq_vec_width, g_ch_width => g_ch_width ) port map ( clk_i => fs_clk_i, rst_n_i => fs_rst_n_i, cha_i => cha_i, chb_i => chb_i, chc_i => chc_i, chd_i => chd_i, ch_valid_i => ch_valid_i, cha_o => cha_o, chb_o => chb_o, chc_o => chc_o, chd_o => chd_o, ch_tag_o => ch_tag_o, ch_valid_o => ch_valid_o, rffe_swclk_o => rffe_swclk_o, sync_trig_i => sync_trig_i, swap_mode_i => regs_out.ctrl_mode_o, swap_div_f_i => regs_out.ctrl_swap_div_f_o, deswap_delay_i => deswap_delay ); deswap_delay <= regs_out.dly_deswap_o(g_delay_vec_width-1 downto 0); end rtl;
lgpl-3.0
f780e6de3a5c4c43588a4b043a8be0f6
0.404334
3.881649
false
false
false
false
bruskajp/EE-316
Project2/Quartus_DE2Board/univ_bin_counter.vhd
1
1,979
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity univ_bin_counter is generic(N: natural := 8; count_max : INTEGER := 8); port( clk : in std_logic; syn_clr, en, up : in std_logic; clk_en : in std_logic := '1'; qo : out std_logic_vector(N-1 downto 0) ); end univ_bin_counter; architecture arch of univ_bin_counter is signal count : integer := 0; --signal r_reg : unsigned(N-1 downto 0); --signal r_next : unsigned(N-1 downto 0); begin -- register-- -- process(clk, syn_clr) -- begin -- if (syn_clr='1') then -- r_reg <= (others=>'0'); -- elsif rising_edge(clk) and clk_en = '1' then -- r_reg <= r_next; -- end if; -- end process; process(clk, en, syn_clr, up, count) begin if rising_edge(clk) then if syn_clr = '1' then count <= 0; elsif up = '1' and en = '1' then count <= count + 1; elsif up = '0' and en = '1' then count <= count - 1; end if; if up = '1' and count = count_max then count <= 0; elsif up = '0' and count = 0 then count <= count_max; end if; end if; end process; -- next-state logic-- -- r_next <= (others=>'0') when syn_clr='1' else -- "00000000" when r_reg = "00001000" and en='1' and up='1' else -- "00001000" when r_reg = "00000000" and en='1' and up='0' else -- r_reg + 1 when en ='1' and up='1' else -- r_reg - 1 when en ='1' and up='0' else -- r_reg; -- output logic-- process(count) begin case (count) is when 0 => qo <= X"07"; when 1 => qo <= X"0F"; when 2 => qo <= X"17"; when 3 => qo <= X"1F"; when 4 => qo <= X"27"; when 5 => qo <= X"2F"; when 6 => qo <= X"37"; when 7 => qo <= X"3F"; when 8 => qo <= X"47"; when others => qo <= X"3F"; end case; end process; end arch;
gpl-3.0
fe8abfb83e24f46898ba4f628edbabad
0.507832
2.771709
false
false
false
false
lnls-dig/dsp-cores
hdl/testbench/delta_sigma/delta_sigma_tb.vhd
1
7,465
------------------------------------------------------------------------------- -- Title : Delta over sigma testbench -- Project : ------------------------------------------------------------------------------- -- File : delta_sigma_tb.vhd -- Author : aylons <aylons@LNLS190> -- Company : -- Created : 2014-05-19 -- Last update: 2016-05-09 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: Tests delta over sigma calculation ------------------------------------------------------------------------------- -- Copyright (c) 2014 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2014-05-19 1.0 aylons Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; library std; use std.textio.all; --use work.arith_dsp48e.all; --use work.utilities.all; ------------------------------------------------------------------------------- entity delta_sigma_tb is end entity delta_sigma_tb; ------------------------------------------------------------------------------- architecture str of delta_sigma_tb is constant c_input_freq : real := 120.0e6; constant c_half_period : time := 1.0 sec / (2.0 * c_input_freq); constant c_ce_period : natural := 2; -- in number of clock cycles constant c_valid_period : natural := 100; -- in number of ce cycles constant c_output_file : string := "./delta_sigma.samples"; constant c_width : natural := 32; constant c_k : real := 2.0**real(c_width-2); constant c_k_width : natural := 24; -- Signals signal clock : std_logic := '0'; signal endoffile : bit := '0'; signal ce : std_logic := '0'; signal reset : std_logic := '0'; signal valid : std_logic := '0'; signal valid_out : std_logic := '0'; signal a, b, c, d : std_logic_vector(c_width-1 downto 0); signal x_in, y_in, q_in, sum_in : real; signal x_out, y_out, q_out, sum_out : std_logic_vector(c_width-1 downto 0); constant c_kx : std_logic_vector(c_k_width-1 downto 0) := "011111111111111111111111"; constant c_ky : std_logic_vector(c_k_width-1 downto 0) := "011111111111111111111111"; constant c_ksum : std_logic_vector(c_k_width-1 downto 0) := "011111111111111111111111"; component delta_sigma is generic ( g_width : natural; g_k_width : natural); port ( a_i : in std_logic_vector(g_width-1 downto 0); b_i : in std_logic_vector(g_width-1 downto 0); c_i : in std_logic_vector(g_width-1 downto 0); d_i : in std_logic_vector(g_width-1 downto 0); kx_i : in std_logic_vector(g_k_width-1 downto 0); ky_i : in std_logic_vector(g_k_width-1 downto 0); ksum_i : in std_logic_vector(g_k_width-1 downto 0); clk_i : in std_logic; ce_i : in std_logic; valid_i : in std_logic; valid_o : out std_logic; rst_i : in std_logic; x_o : out std_logic_vector(g_width-1 downto 0); y_o : out std_logic_vector(g_width-1 downto 0); q_o : out std_logic_vector(g_width-1 downto 0); sum_o : out std_logic_vector(g_width-1 downto 0)); end component delta_sigma; begin -- architecture str clk_gen : process begin clock <= '0'; wait for c_half_period; clock <= '1'; wait for c_half_period; end process; rst_gen : process(clock) constant clocks_to_reset : natural := 1; variable reset_count : natural := 0; begin if rising_edge(clock) then if reset_count = 0 then reset <= '1'; reset_count := reset_count + 1; elsif reset_count = clocks_to_reset then reset <= '0'; else reset_count := reset_count +1; end if; end if; end process; ce_gen : process(clock) variable ce_count : natural := 0; begin if rising_edge(clock) then ce_count := ce_count + 1; if ce_count = c_ce_period then ce <= '1'; ce_count := 0; else ce <= '0'; end if; end if; end process; valid_gen : process(clock) variable valid_count : natural := 0; begin if rising_edge(clock) and ce = '1' then valid_count := valid_count + 1; if valid_count = c_valid_period then valid <= '1'; valid_count := 0; else valid <= '0'; end if; end if; end process; data_gen : process variable x_temp, y_temp : real; begin wait until valid = '1'; for x_int in -999 to 999 loop --avoid extremes because the math is --not defined for them x_temp := real(x_int)/1000.0; x_in <= x_temp; for y_int in -99 to 99 loop y_temp := real(y_int)/100.0; y_in <= y_temp; a <= std_logic_vector(to_signed(integer( 0.25*c_k*(x_temp + y_temp + 1.0)),c_width)); b <= std_logic_vector(to_signed(integer( 0.25*c_k*(- x_temp + y_temp + 1.0)),c_width)); c <= std_logic_vector(to_signed(integer( 0.25*c_k*(- x_temp - y_temp + 1.0)),c_width)); d <= std_logic_vector(to_signed(integer( 0.25*c_k*(x_temp - y_temp + 1.0)),c_width)); wait until valid = '1'; end loop; end loop; assert(false) report "end of input stream" severity failure; end process; output_check : process(clock) file samples_file : text open write_mode is "delta_sigma.samples"; variable cur_line : line; variable x_diff, y_diff, sum_diff : real; begin if rising_edge(clock) and ce = '1' and valid_out = '1' then write(cur_line, x_in); write(cur_line, ht); write(cur_line, y_in); write(cur_line, ht); write(cur_line, to_integer(signed(x_out))); write(cur_line, ht); write(cur_line, to_integer(signed(y_out))); write(cur_line, ht); write(cur_line, to_integer(signed(q_out))); write(cur_line, ht); write(cur_line, to_integer(signed(sum_out))); write(cur_line, ht); writeline(samples_file, cur_line); -- compare results directly x_diff := real(to_integer(signed(x_out)))/2.0**31.0 - x_in; y_diff := real(to_integer(signed(y_out)))/2.0**31.0 - y_in; sum_diff := real(to_integer(signed(sum_out)))/2.0**31.0 - sum_in; --assert x_diff < x_in/(10.0**5.0) -- report "x difference too big" -- severity failure; end if; end process; uut : delta_sigma generic map ( g_width => c_width, g_k_width => c_k_width) port map ( a_i => a, b_i => b, c_i => c, d_i => d, kx_i => c_kx, ky_i => c_ky, ksum_i => c_ksum, clk_i => clock, rst_i => reset, ce_i => ce, valid_i => valid, valid_o => valid_out, x_o => x_out, y_o => y_out, q_o => q_out, sum_o => sum_out); end architecture str; -------------------------------------------------------------------------------
lgpl-3.0
8f806859e8090616925f5bbd3c415467
0.48935
3.427456
false
false
false
false
lnls-dig/dsp-cores
hdl/testbench/cordic/cordic_bench.vhd
1
6,164
------------------------------------------------------------------------------- -- Title : Testbench for CORDIC module -- Project : ------------------------------------------------------------------------------- -- File : cordic_bench.vhd -- Author : aylons <aylons@LNLS190> -- Company : -- Created : 2014-03-21 -- Last update: 2014-03-31 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Copyright (c) 2014 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2014-03-21 1.0 aylons Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; library std; use std.textio.all; library UNISIM; use UNISIM.vcomponents.all; entity cordic_bench is end entity cordic_bench; architecture test of cordic_bench is ----------------------------------------------------------------------------- -- Internal signal declarations ----------------------------------------------------------------------------- constant c_input_freq : real := 100.0e6; constant c_clock_period : time := 1.0 sec /(2.0*c_input_freq); constant c_cycles_to_reset : natural := 4; signal clock : std_logic := '0'; signal rst_n : std_logic := '0'; constant c_width : natural := 24; signal I_in : std_logic_vector(c_width-1 downto 0) := (others => '0'); signal Q_in : std_logic_vector(c_width-1 downto 0) := (others => '0'); signal mag_in : std_logic_vector(c_width-1 downto 0) := (others => '0'); signal phase_in : std_logic_vector(c_width-1 downto 0) := (others => '0'); signal I_out : std_logic_vector(c_width-1 downto 0); signal Q_out : std_logic_vector(c_width-1 downto 0); signal mag_out : std_logic_vector(c_width-1 downto 0); signal phase_out : std_logic_vector(c_width-1 downto 0); signal endoffile : std_logic := '0'; constant cordic_delay : natural := 27; component cordic is generic ( g_width : natural; g_mode : string); port ( clk_i : in std_logic; rst_n_i : in std_logic; I_i : in std_logic_vector(g_width-1 downto 0) := (others => '0'); Q_i : in std_logic_vector(g_width-1 downto 0) := (others => '0'); mag_i : in std_logic_vector(g_width-1 downto 0) := (others => '0'); phase_i : in std_logic_vector(g_width-1 downto 0) := (others => '0'); I_o : out std_logic_vector(g_width-1 downto 0); Q_o : out std_logic_vector(g_width-1 downto 0); mag_o : out std_logic_vector(g_width-1 downto 0); phase_o : out std_logic_vector(g_width-1 downto 0)); end component cordic; begin clk_gen : process begin clock <= '0'; wait for c_clock_period; clock <= '1'; wait for c_clock_period; end process; rst_gen : process(clock) variable clock_count : natural := c_cycles_to_reset; begin if rising_edge(clock) and clock_count /= 0 then clock_count := clock_count - 1; if clock_count = 0 then rst_n <= '1'; end if; end if; end process; sample_read : process(clock) file vect_file : text open read_mode is "vectoring_in.dat"; file rotate_file : text open read_mode is "rotating_in.dat"; variable cur_line : line; variable datain1, datain2 : real; begin if rising_edge(clock) then --Pick samples for vectoring mode if not endfile(vect_file) then readline(vect_file, cur_line); read(cur_line, datain1); I_in <= std_logic_vector(to_signed(integer(datain1*(2.0**(c_width-1))), c_width)); read(cur_line, datain2); Q_in <= std_logic_vector(to_signed(integer(datain2*(2.0**(c_width-1))), c_width)); else endoffile <= '1'; end if; -- pick samples for rotation mode if not endfile(rotate_file) then readline(rotate_file, cur_line); read(cur_line, datain1); mag_in <= std_logic_vector(to_signed(integer(datain1*(2.0**(c_width-1))), c_width)); read(cur_line, datain2); phase_in <= std_logic_vector(to_signed(integer(datain2*(2.0**(c_width-1))), c_width)); else endoffile <= '1'; end if; end if; end process sample_read; uut1 : cordic generic map ( g_width => c_width, g_mode => "rect_to_polar") port map ( clk_i => clock, rst_n_i => rst_n, I_i => I_in, Q_i => Q_in, mag_o => mag_out, phase_o => phase_out); uut2 : cordic generic map ( g_width => c_width, g_mode => "polar_to_rect") port map ( clk_i => clock, rst_n_i => rst_n, mag_i => mag_in, phase_i => phase_in, I_o => I_out, Q_o => Q_out); signal_write : process(clock) file vect_file : text open write_mode is "vectoring_out.dat"; file rotate_file : text open write_mode is "rotating_out.dat"; variable cur_line : line; variable mag, phase : integer; variable I, Q : integer; -- variable counter : natural = cordic_delay; begin if rising_edge(clock) then if(endoffile = '0') then mag := to_integer(unsigned(mag_out)); write(cur_line, mag); write(cur_line, string'(" ")); phase := to_integer(signed(phase_out)); write(cur_line, phase); writeline(vect_file, cur_line); I := to_integer(signed(I_out)); write(cur_line, I); write(cur_line, string'(" ")); Q := to_integer(signed(Q_out)); write(cur_line, Q); writeline(rotate_file, cur_line); else assert (false) report "Input file finished." severity failure; end if; end if; end process signal_write; end architecture test;
lgpl-3.0
df3b518fe5b65b33a517412fecc57c55
0.510383
3.554787
false
false
false
false
TUM-LIS/faultify
hardware/testcases/IIR/fpga_sim/xpsLibraryPath/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/vhdl/user_logic.vhd
1
29,243
------------------------------------------------------------------------------ -- user_logic.vhd - entity/architecture pair ------------------------------------------------------------------------------ -- -- *************************************************************************** -- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** Xilinx, Inc. ** -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** -- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** -- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** -- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** -- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** -- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** -- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** -- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** -- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** -- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** -- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** -- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** -- ** FOR A PARTICULAR PURPOSE. ** -- ** ** -- *************************************************************************** -- ------------------------------------------------------------------------------ -- Filename: user_logic.vhd -- Version: 1.00.a -- Description: User logic. -- Date: Fri May 16 15:25:24 2014 (by Create and Import Peripheral Wizard) -- VHDL Standard: VHDL'93 ------------------------------------------------------------------------------ -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port: "*_i" -- device pins: "*_pin" -- ports: "- Names begin with Uppercase" -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC>" ------------------------------------------------------------------------------ -- DO NOT EDIT BELOW THIS LINE -------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library proc_common_v3_00_a; use proc_common_v3_00_a.proc_common_pkg.all; -- DO NOT EDIT ABOVE THIS LINE -------------------- --USER libraries added here ------------------------------------------------------------------------------ -- Entity section ------------------------------------------------------------------------------ -- Definition of Generics: -- C_NUM_REG -- Number of software accessible registers -- C_SLV_DWIDTH -- Slave interface data bus width -- -- Definition of Ports: -- Bus2IP_Clk -- Bus to IP clock -- Bus2IP_Resetn -- Bus to IP reset -- Bus2IP_Data -- Bus to IP data bus -- Bus2IP_BE -- Bus to IP byte enables -- Bus2IP_RdCE -- Bus to IP read chip enable -- Bus2IP_WrCE -- Bus to IP write chip enable -- IP2Bus_Data -- IP to Bus data bus -- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement -- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement -- IP2Bus_Error -- IP to Bus error response ------------------------------------------------------------------------------ entity user_logic is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- --USER generics added here -- ADD USER GENERICS ABOVE THIS LINE --------------- -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_NUM_REG : integer := 32; C_SLV_DWIDTH : integer := 32 -- DO NOT EDIT ABOVE THIS LINE --------------------- ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ --USER ports added here faultify_clk_fast : in std_logic; -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete Bus2IP_Clk : in std_logic; Bus2IP_Resetn : in std_logic; Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0); Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0); Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0); Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0); IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0); IP2Bus_RdAck : out std_logic; IP2Bus_WrAck : out std_logic; IP2Bus_Error : out std_logic -- DO NOT EDIT ABOVE THIS LINE --------------------- ); attribute MAX_FANOUT : string; attribute SIGIS : string; attribute SIGIS of Bus2IP_Clk : signal is "CLK"; attribute SIGIS of Bus2IP_Resetn : signal is "RST"; end entity user_logic; ------------------------------------------------------------------------------ -- Architecture section ------------------------------------------------------------------------------ architecture IMP of user_logic is --USER signal declarations added here, as needed for user logic component faultify_top generic ( numInj : integer; numIn : integer; numOut : integer); port ( aclk : in std_logic; arst_n : in std_logic; clk : in std_logic; clk_x32 : in std_logic; awvalid : in std_logic; awaddr : in std_logic_vector(31 downto 0); wvalid : in std_logic; wdata : in std_logic_vector(31 downto 0); arvalid : in std_logic; araddr : in std_logic_vector(31 downto 0); rvalid : out std_logic; rdata : out std_logic_vector(31 downto 0)); end component; ------------------------------------------ -- Signals for user logic slave model s/w accessible register example ------------------------------------------ signal register_write_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal register_read_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal register_write_address : std_logic_vector(C_NUM_REG-1 downto 0); signal register_read_address : std_logic_vector(C_NUM_REG-1 downto 0); signal slv_reg_write_sel : std_logic_vector(31 downto 0); signal slv_reg_read_sel : std_logic_vector(31 downto 0); signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_read_ack : std_logic; signal slv_write_ack : std_logic; signal faultify_read_valid : std_logic; signal faultify_read_address_valid : std_logic; signal faultify_read_address : std_logic_vector(31 downto 0); signal faultify_write_valid : std_logic; signal counter, divide : integer := 0; signal faultify_clk_slow_i : std_logic; begin slv_reg_write_sel <= Bus2IP_WrCE(31 downto 0); slv_reg_read_sel <= Bus2IP_RdCE(31 downto 0); slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12) or Bus2IP_WrCE(13) or Bus2IP_WrCE(14) or Bus2IP_WrCE(15) or Bus2IP_WrCE(16) or Bus2IP_WrCE(17) or Bus2IP_WrCE(18) or Bus2IP_WrCE(19) or Bus2IP_WrCE(20) or Bus2IP_WrCE(21) or Bus2IP_WrCE(22) or Bus2IP_WrCE(23) or Bus2IP_WrCE(24) or Bus2IP_WrCE(25) or Bus2IP_WrCE(26) or Bus2IP_WrCE(27) or Bus2IP_WrCE(28) or Bus2IP_WrCE(29) or Bus2IP_WrCE(30) or Bus2IP_WrCE(31); slv_read_ack <= faultify_read_valid; -- implement slave model software accessible register(s) SLAVE_REG_WRITE_PROC : process(Bus2IP_Clk) is begin if Bus2IP_Clk'event and Bus2IP_Clk = '1' then if Bus2IP_Resetn = '0' then register_write_data <= (others => '0'); register_write_address <= (others => '0'); faultify_write_valid <= '0'; else faultify_write_valid <= slv_write_ack; case slv_reg_write_sel is when "10000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(0, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "01000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(1, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00100000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(2, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00010000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(3, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00001000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(4, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000100000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(5, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000010000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(6, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000001000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(7, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000100000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(8, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000010000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(9, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000001000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(10, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000100000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(11, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000010000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(12, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000001000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(13, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000100000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(14, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000010000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(15, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000001000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(16, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000100000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(17, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000010000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(18, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000001000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(19, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000000100000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(20, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000000010000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(21, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000000001000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(22, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000000000100000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(23, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000000000010000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(24, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000000000001000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(25, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000000000000100000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(26, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000000000000010000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(27, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000000000000001000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(28, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000000000000000100" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(29, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000000000000000010" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(30, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000000000000000001" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(31, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when others => null; end case; end if; end if; end process SLAVE_REG_WRITE_PROC; -- implement slave model software accessible register(s) read mux SLAVE_REG_READ_PROC : process(slv_reg_read_sel, faultify_read_valid) is begin faultify_read_address_valid <= '1'; case slv_reg_read_sel is when "10000000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(0, 32)); when "01000000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(1, 32)); when "00100000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(2, 32)); when "00010000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(3, 32)); when "00001000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(4, 32)); when "00000100000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(5, 32)); when "00000010000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(6, 32)); when "00000001000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(7, 32)); when "00000000100000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(8, 32)); when "00000000010000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(9, 32)); when "00000000001000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(10, 32)); when "00000000000100000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(11, 32)); when "00000000000010000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(12, 32)); when "00000000000001000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(13, 32)); when "00000000000000100000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(14, 32)); when "00000000000000010000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(15, 32)); when "00000000000000001000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(16, 32)); when "00000000000000000100000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(17, 32)); when "00000000000000000010000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(18, 32)); when "00000000000000000001000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(19, 32)); when "00000000000000000000100000000000" => faultify_read_address <= std_logic_vector(to_unsigned(20, 32)); when "00000000000000000000010000000000" => faultify_read_address <= std_logic_vector(to_unsigned(21, 32)); when "00000000000000000000001000000000" => faultify_read_address <= std_logic_vector(to_unsigned(22, 32)); when "00000000000000000000000100000000" => faultify_read_address <= std_logic_vector(to_unsigned(23, 32)); when "00000000000000000000000010000000" => faultify_read_address <= std_logic_vector(to_unsigned(24, 32)); when "00000000000000000000000001000000" => faultify_read_address <= std_logic_vector(to_unsigned(25, 32)); when "00000000000000000000000000100000" => faultify_read_address <= std_logic_vector(to_unsigned(26, 32)); when "00000000000000000000000000010000" => faultify_read_address <= std_logic_vector(to_unsigned(27, 32)); when "00000000000000000000000000001000" => faultify_read_address <= std_logic_vector(to_unsigned(28, 32)); when "00000000000000000000000000000100" => faultify_read_address <= std_logic_vector(to_unsigned(29, 32)); when "00000000000000000000000000000010" => faultify_read_address <= std_logic_vector(to_unsigned(30, 32)); when "00000000000000000000000000000001" => faultify_read_address <= std_logic_vector(to_unsigned(31, 32)); when others => faultify_read_address <= (others => '0'); faultify_read_address_valid <= '0'; end case; end process SLAVE_REG_READ_PROC; ------------------------------------------ -- Example code to drive IP to Bus signals ------------------------------------------ IP2Bus_Data <= register_read_data when faultify_read_valid = '1' else (others => '0'); IP2Bus_WrAck <= slv_write_ack; IP2Bus_RdAck <= slv_read_ack; IP2Bus_Error <= '0'; ----------------------------------------------------------------------------- -- clock divider 32 -> 1 ----------------------------------------------------------------------------- divide <= 32; process(Bus2IP_Clk, Bus2IP_Resetn) begin if Bus2IP_Resetn = '0' then counter <= 0; faultify_clk_slow_i <= '0'; elsif(rising_edge(Bus2IP_Clk)) then if(counter < divide/2-1) then counter <= counter + 1; faultify_clk_slow_i <= '0'; elsif(counter < divide-1) then counter <= counter + 1; faultify_clk_slow_i <= '1'; else faultify_clk_slow_i <= '0'; counter <= 0; end if; end if; end process; faultify_top_1 : faultify_top generic map ( numInj => 346, numIn => 19, numOut => 19) port map ( aclk => Bus2IP_Clk, arst_n => Bus2IP_Resetn, clk => faultify_clk_slow_i, clk_x32 => Bus2IP_Clk, awvalid => faultify_write_valid, awaddr => register_write_address, wvalid => faultify_write_valid, wdata => register_write_data, arvalid => faultify_read_address_valid, araddr => faultify_read_address, rvalid => faultify_read_valid, rdata => register_read_data); end IMP;
gpl-2.0
18b44751eb03d2640aad554cbefc0e76
0.539309
4.022974
false
false
false
false
bruskajp/EE-316
Project4/Vivado_NexysBoard/craddockEE316/craddockEE316.srcs/sources_1/imports/testFolder/clk1Mhz.vhd
1
1,730
LIBRARY ieee; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH; use IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY clk1Mhz IS PORT ( SIGNAL samplingFreq : INOUT std_logic:= '1'; signal baudRate : INOUT std_logic:= '1'; signal rx_clk : inout std_logic:= '1'; signal tx_clk : inout std_logic:= '1'; SIGNAL iCLK : IN std_logic); END clk1Mhz; ARCHITECTURE Arch OF clk1Mhz IS SIGNAL DIV : std_logic_vector (25 DOWNTO 0):="00"&X"000000"; SIGNAL DIV2 : std_logic_vector (25 DOWNTO 0):="00"&X"000000"; SIGNAL DIV3 : std_logic_vector (25 DOWNTO 0):="00"&X"000000"; SIGNAL DIV4 : std_logic_vector (25 DOWNTO 0):="00"&X"000000"; BEGIN PROCESS(iCLK) -- 11.52 kHz clock BEGIN IF rising_edge(iCLK) THEN IF DIV >= 4341 THEN DIV <= "00"&X"000000"; baudRate <= NOT baudRate; ELSE DIV <= DIV + '1'; END IF; END IF; END PROCESS; PROCESS(iCLK) -- 1 MHz clock BEGIN IF rising_edge(iCLK) THEN IF DIV2 >= 49 THEN DIV2 <= "00"&X"000000"; samplingFreq <= NOT samplingFreq; ELSE DIV2 <= DIV2 + '1'; END IF; END IF; END PROCESS; PROCESS(iCLK) -- 1 MHz clock BEGIN IF rising_edge(iCLK) THEN -- 11.52kHz*16 IF DIV3 >= 272 THEN DIV3 <= "00"&X"000000"; rx_clk <= NOT rx_clk; ELSE DIV3 <= DIV3 + '1'; END IF; END IF; END PROCESS; process(iCLK) begin IF rising_edge(iCLK) THEN -- 115.20k*10 IF DIV4 >= 435 THEN DIV4 <= "00"&X"000000"; tx_clk <= NOT tx_clk; ELSE DIV4 <= DIV4 + '1'; END IF; END IF; END PROCESS; END Arch;
gpl-3.0
f19fa0adaf1159d4ae876ace1e95b003
0.542775
3.174312
false
false
false
false
hanyazou/vivado-ws
playpen/dvi2vga_nofilter/dvi2vga_nofilter.srcs/sources_1/bd/design_1/ip/design_1_dvi2rgb_0_1/sim/design_1_dvi2rgb_0_1.vhd
1
7,004
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: digilentinc.com:ip:dvi2rgb:1.5 -- IP Revision: 1 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY design_1_dvi2rgb_0_1 IS PORT ( TMDS_Clk_p : IN STD_LOGIC; TMDS_Clk_n : IN STD_LOGIC; TMDS_Data_p : IN STD_LOGIC_VECTOR(2 DOWNTO 0); TMDS_Data_n : IN STD_LOGIC_VECTOR(2 DOWNTO 0); RefClk : IN STD_LOGIC; aRst_n : IN STD_LOGIC; vid_pData : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); vid_pVDE : OUT STD_LOGIC; vid_pHSync : OUT STD_LOGIC; vid_pVSync : OUT STD_LOGIC; PixelClk : OUT STD_LOGIC; aPixelClkLckd : OUT STD_LOGIC; DDC_SDA_I : IN STD_LOGIC; DDC_SDA_O : OUT STD_LOGIC; DDC_SDA_T : OUT STD_LOGIC; DDC_SCL_I : IN STD_LOGIC; DDC_SCL_O : OUT STD_LOGIC; DDC_SCL_T : OUT STD_LOGIC; pRst_n : IN STD_LOGIC ); END design_1_dvi2rgb_0_1; ARCHITECTURE design_1_dvi2rgb_0_1_arch OF design_1_dvi2rgb_0_1 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_dvi2rgb_0_1_arch: ARCHITECTURE IS "yes"; COMPONENT dvi2rgb IS GENERIC ( kEmulateDDC : BOOLEAN; kRstActiveHigh : BOOLEAN; kClkRange : INTEGER; kIDLY_TapValuePs : INTEGER; kIDLY_TapWidth : INTEGER; kAddBUFG : BOOLEAN ); PORT ( TMDS_Clk_p : IN STD_LOGIC; TMDS_Clk_n : IN STD_LOGIC; TMDS_Data_p : IN STD_LOGIC_VECTOR(2 DOWNTO 0); TMDS_Data_n : IN STD_LOGIC_VECTOR(2 DOWNTO 0); RefClk : IN STD_LOGIC; aRst : IN STD_LOGIC; aRst_n : IN STD_LOGIC; vid_pData : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); vid_pVDE : OUT STD_LOGIC; vid_pHSync : OUT STD_LOGIC; vid_pVSync : OUT STD_LOGIC; PixelClk : OUT STD_LOGIC; SerialClk : OUT STD_LOGIC; aPixelClkLckd : OUT STD_LOGIC; DDC_SDA_I : IN STD_LOGIC; DDC_SDA_O : OUT STD_LOGIC; DDC_SDA_T : OUT STD_LOGIC; DDC_SCL_I : IN STD_LOGIC; DDC_SCL_O : OUT STD_LOGIC; DDC_SCL_T : OUT STD_LOGIC; pRst : IN STD_LOGIC; pRst_n : IN STD_LOGIC ); END COMPONENT dvi2rgb; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF TMDS_Clk_p: SIGNAL IS "digilentinc.com:interface:tmds:1.0 TMDS CLK_P"; ATTRIBUTE X_INTERFACE_INFO OF TMDS_Clk_n: SIGNAL IS "digilentinc.com:interface:tmds:1.0 TMDS CLK_N"; ATTRIBUTE X_INTERFACE_INFO OF TMDS_Data_p: SIGNAL IS "digilentinc.com:interface:tmds:1.0 TMDS DATA_P"; ATTRIBUTE X_INTERFACE_INFO OF TMDS_Data_n: SIGNAL IS "digilentinc.com:interface:tmds:1.0 TMDS DATA_N"; ATTRIBUTE X_INTERFACE_INFO OF RefClk: SIGNAL IS "xilinx.com:signal:clock:1.0 RefClk CLK"; ATTRIBUTE X_INTERFACE_INFO OF aRst_n: SIGNAL IS "xilinx.com:signal:reset:1.0 AsyncRst_n RST"; ATTRIBUTE X_INTERFACE_INFO OF vid_pData: SIGNAL IS "xilinx.com:interface:vid_io:1.0 RGB DATA"; ATTRIBUTE X_INTERFACE_INFO OF vid_pVDE: SIGNAL IS "xilinx.com:interface:vid_io:1.0 RGB ACTIVE_VIDEO"; ATTRIBUTE X_INTERFACE_INFO OF vid_pHSync: SIGNAL IS "xilinx.com:interface:vid_io:1.0 RGB HSYNC"; ATTRIBUTE X_INTERFACE_INFO OF vid_pVSync: SIGNAL IS "xilinx.com:interface:vid_io:1.0 RGB VSYNC"; ATTRIBUTE X_INTERFACE_INFO OF PixelClk: SIGNAL IS "xilinx.com:signal:clock:1.0 PixelClk CLK"; ATTRIBUTE X_INTERFACE_INFO OF DDC_SDA_I: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SDA_I"; ATTRIBUTE X_INTERFACE_INFO OF DDC_SDA_O: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SDA_O"; ATTRIBUTE X_INTERFACE_INFO OF DDC_SDA_T: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SDA_T"; ATTRIBUTE X_INTERFACE_INFO OF DDC_SCL_I: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SCL_I"; ATTRIBUTE X_INTERFACE_INFO OF DDC_SCL_O: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SCL_O"; ATTRIBUTE X_INTERFACE_INFO OF DDC_SCL_T: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SCL_T"; ATTRIBUTE X_INTERFACE_INFO OF pRst_n: SIGNAL IS "xilinx.com:signal:reset:1.0 SyncRst_n RST"; BEGIN U0 : dvi2rgb GENERIC MAP ( kEmulateDDC => true, kRstActiveHigh => false, kClkRange => 2, kIDLY_TapValuePs => 78, kIDLY_TapWidth => 5, kAddBUFG => true ) PORT MAP ( TMDS_Clk_p => TMDS_Clk_p, TMDS_Clk_n => TMDS_Clk_n, TMDS_Data_p => TMDS_Data_p, TMDS_Data_n => TMDS_Data_n, RefClk => RefClk, aRst => '0', aRst_n => aRst_n, vid_pData => vid_pData, vid_pVDE => vid_pVDE, vid_pHSync => vid_pHSync, vid_pVSync => vid_pVSync, PixelClk => PixelClk, aPixelClkLckd => aPixelClkLckd, DDC_SDA_I => DDC_SDA_I, DDC_SDA_O => DDC_SDA_O, DDC_SDA_T => DDC_SDA_T, DDC_SCL_I => DDC_SCL_I, DDC_SCL_O => DDC_SCL_O, DDC_SCL_T => DDC_SCL_T, pRst => '0', pRst_n => pRst_n ); END design_1_dvi2rgb_0_1_arch;
mit
da357e75f620525bd53e1ad1419afb62
0.686608
3.462185
false
false
false
false
SoCdesign/EHA
RTL/Hand_Shaking/Checkers/Modules_with_checkers_integrated/All_checkers/Arbiter_one_hot_with_checkers/Arbiter_one_hot_with_checkers.vhd
1
17,445
--Copyright (C) 2016 Siavoosh Payandeh Azad library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Arbiter is port ( reset: in std_logic; clk: in std_logic; Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules DCTS: in std_logic; -- Getting the CTS signal from the input FIFO of the next router/NI (for hand-shaking) Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot) Xbar_sel : out std_logic_vector(4 downto 0); -- select lines for XBAR RTS: out std_logic; -- Valid output which is sent to the next router/NI to specify that the data on the output port is valid -- Checker outputs err_state_IDLE_xbar, err_state_not_IDLE_xbar, err_state_IDLE_RTS_FF_in, err_state_not_IDLE_RTS_FF_RTS_FF_in, err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in, err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in, err_RTS_FF_not_DCTS_state_state_in, err_not_RTS_FF_state_in_next_state, err_RTS_FF_DCTS_state_in_next_state, err_not_DCTS_Grants, err_DCTS_not_RTS_FF_Grants, err_DCTS_RTS_FF_IDLE_Grants, err_DCTS_RTS_FF_not_IDLE_Grants_onehot, err_Requests_next_state_IDLE, err_IDLE_Req_L, err_Local_Req_L, err_North_Req_N, err_East_Req_E, err_West_Req_W, err_South_Req_S, err_IDLE_Req_N, err_Local_Req_N, err_North_Req_E, err_East_Req_W, err_West_Req_S, err_South_Req_L, err_IDLE_Req_E, err_Local_Req_E, err_North_Req_W, err_East_Req_S, err_West_Req_L, err_South_Req_N, err_IDLE_Req_W, err_Local_Req_W, err_North_Req_S, err_East_Req_L, err_West_Req_N, err_South_Req_E, err_IDLE_Req_S, err_Local_Req_S, err_North_Req_L, err_East_Req_N, err_West_Req_E, err_South_Req_W, err_next_state_onehot, err_state_in_onehot, err_DCTS_RTS_FF_state_Grant_L, err_DCTS_RTS_FF_state_Grant_N, err_DCTS_RTS_FF_state_Grant_E, err_DCTS_RTS_FF_state_Grant_W, err_DCTS_RTS_FF_state_Grant_S, err_state_north_xbar_sel, err_state_east_xbar_sel, err_state_west_xbar_sel, err_state_south_xbar_sel, err_state_local_xbar_sel : out std_logic ); end; architecture behavior of Arbiter is -- next -- Arbiter router or NI -- ------------------------------------- ---- -- from LBDR ---> |Req(s) RTS | -----> |DRTS -- To FIFO <--- |Grant(s) DCTS| <----- |CTS -- to XBAR <--- |Xbar_sel | | -- ------------------------------------- ---- -------------------------------------------------------------------------------------------- -- an example of a request/grant + handshake process with next router or NI --CLK _|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|__ -- Req _____|'''''''''''''''''''''''''''''''''''''''''''|________ -- _________ ___________________ _______ _______ _______ ____ -- TX _________X_______HEADER______X_Body__X_Body__X__Tail_X____ -- Grant _________________________|'''|___|'''|___|'''|____________ -- RTs _________|'''''''''''''''''''|___|'''''''|___|'''''''|____ -- DCTS _________________________|'''|_______|'''|_______|'''|____ -- |<---------clear----------->| -- | to send | -------------------------------------------------------------------------------------------- -- TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local); SUBTYPE STATE_TYPE IS STD_LOGIC_VECTOR (5 downto 0); CONSTANT IDLE: STATE_TYPE := "000001"; CONSTANT Local: STATE_TYPE := "000010"; CONSTANT North: STATE_TYPE := "000100"; CONSTANT East: STATE_TYPE := "001000"; CONSTANT West: STATE_TYPE := "010000"; CONSTANT South: STATE_TYPE := "100000"; SIGNAL state, state_in, next_state : STATE_TYPE := IDLE; SIGNAL RTS_FF, RTS_FF_in: std_logic; signal Grant_N_sig, Grant_E_sig, Grant_W_sig, Grant_S_sig, Grant_L_sig: std_logic; signal Xbar_sel_sig: std_logic_vector(4 downto 0); component Arbiter_checkers is port ( Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; DCTS: in std_logic; Grant_N, Grant_E, Grant_W, Grant_S, Grant_L: in std_logic; Xbar_sel : in std_logic_vector(4 downto 0); state: in std_logic_vector (5 downto 0); state_in: in std_logic_vector (5 downto 0); next_state_out: in std_logic_vector (5 downto 0); RTS_FF: in std_logic; RTS_FF_in: in std_logic; -- Checker outputs err_state_IDLE_xbar, err_state_not_IDLE_xbar, err_state_IDLE_RTS_FF_in, err_state_not_IDLE_RTS_FF_RTS_FF_in, err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in, err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in, err_RTS_FF_not_DCTS_state_state_in, err_not_RTS_FF_state_in_next_state, err_RTS_FF_DCTS_state_in_next_state, err_not_DCTS_Grants, err_DCTS_not_RTS_FF_Grants, err_DCTS_RTS_FF_IDLE_Grants, err_DCTS_RTS_FF_not_IDLE_Grants_onehot, err_Requests_next_state_IDLE, err_IDLE_Req_L, err_Local_Req_L, err_North_Req_N, err_East_Req_E, err_West_Req_W, err_South_Req_S, err_IDLE_Req_N, err_Local_Req_N, err_North_Req_E, err_East_Req_W, err_West_Req_S, err_South_Req_L, err_IDLE_Req_E, err_Local_Req_E, err_North_Req_W, err_East_Req_S, err_West_Req_L, err_South_Req_N, err_IDLE_Req_W, err_Local_Req_W, err_North_Req_S, err_East_Req_L, err_West_Req_N, err_South_Req_E, err_IDLE_Req_S, err_Local_Req_S, err_North_Req_L, err_East_Req_N, err_West_Req_E, err_South_Req_W, err_next_state_onehot, err_state_in_onehot, err_DCTS_RTS_FF_state_Grant_L, err_DCTS_RTS_FF_state_Grant_N, err_DCTS_RTS_FF_state_Grant_E, err_DCTS_RTS_FF_state_Grant_W, err_DCTS_RTS_FF_state_Grant_S, err_state_north_xbar_sel, err_state_east_xbar_sel, err_state_west_xbar_sel, err_state_south_xbar_sel, err_state_local_xbar_sel : out std_logic ); end component; begin -- Arbiter checkers instantiation ARBITERCHECKERS: Arbiter_checkers port map ( Req_N => Req_N, Req_E => Req_E, Req_W => Req_W, Req_S => Req_S, Req_L => Req_L, DCTS => DCTS, Grant_N => Grant_N_sig, Grant_E => Grant_E_sig, Grant_W => Grant_W_sig, Grant_S => Grant_S_sig, Grant_L => Grant_L_sig, Xbar_sel=>Xbar_sel_sig, state => state, state_in => state_in, next_state_out => next_state, RTS_FF => RTS_FF, RTS_FF_in => RTS_FF_in, err_state_IDLE_xbar => err_state_IDLE_xbar, err_state_not_IDLE_xbar => err_state_not_IDLE_xbar, err_state_IDLE_RTS_FF_in => err_state_IDLE_RTS_FF_in, err_state_not_IDLE_RTS_FF_RTS_FF_in => err_state_not_IDLE_RTS_FF_RTS_FF_in, err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in, err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in, err_RTS_FF_not_DCTS_state_state_in => err_RTS_FF_not_DCTS_state_state_in, err_not_RTS_FF_state_in_next_state => err_not_RTS_FF_state_in_next_state, err_RTS_FF_DCTS_state_in_next_state => err_RTS_FF_DCTS_state_in_next_state, err_not_DCTS_Grants => err_not_DCTS_Grants, err_DCTS_not_RTS_FF_Grants => err_DCTS_not_RTS_FF_Grants, err_DCTS_RTS_FF_IDLE_Grants => err_DCTS_RTS_FF_IDLE_Grants, err_DCTS_RTS_FF_not_IDLE_Grants_onehot => err_DCTS_RTS_FF_not_IDLE_Grants_onehot, err_Requests_next_state_IDLE => err_Requests_next_state_IDLE, err_IDLE_Req_L => err_IDLE_Req_L, err_Local_Req_L => err_Local_Req_L, err_North_Req_N => err_North_Req_N, err_East_Req_E => err_East_Req_E, err_West_Req_W => err_West_Req_W, err_South_Req_S => err_South_Req_S, err_IDLE_Req_N => err_IDLE_Req_N, err_Local_Req_N => err_Local_Req_N, err_North_Req_E => err_North_Req_E, err_East_Req_W => err_East_Req_W, err_West_Req_S => err_West_Req_S, err_South_Req_L => err_South_Req_L, err_IDLE_Req_E => err_IDLE_Req_E, err_Local_Req_E => err_Local_Req_E, err_North_Req_W => err_North_Req_W, err_East_Req_S => err_East_Req_S, err_West_Req_L => err_West_Req_L, err_South_Req_N => err_South_Req_N, err_IDLE_Req_W => err_IDLE_Req_W, err_Local_Req_W => err_Local_Req_W, err_North_Req_S => err_North_Req_S, err_East_Req_L => err_East_Req_L, err_West_Req_N => err_West_Req_N, err_South_Req_E => err_South_Req_E, err_IDLE_Req_S => err_IDLE_Req_S, err_Local_Req_S => err_Local_Req_S, err_North_Req_L => err_North_Req_L, err_East_Req_N => err_East_Req_N, err_West_Req_E => err_West_Req_E, err_South_Req_W => err_South_Req_W, err_next_state_onehot => err_next_state_onehot, err_state_in_onehot => err_state_in_onehot, err_DCTS_RTS_FF_state_Grant_L => err_DCTS_RTS_FF_state_Grant_L, err_DCTS_RTS_FF_state_Grant_N => err_DCTS_RTS_FF_state_Grant_N, err_DCTS_RTS_FF_state_Grant_E => err_DCTS_RTS_FF_state_Grant_E, err_DCTS_RTS_FF_state_Grant_W => err_DCTS_RTS_FF_state_Grant_W, err_DCTS_RTS_FF_state_Grant_S => err_DCTS_RTS_FF_state_Grant_S, err_state_north_xbar_sel => err_state_north_xbar_sel, err_state_east_xbar_sel => err_state_east_xbar_sel, err_state_west_xbar_sel => err_state_west_xbar_sel, err_state_south_xbar_sel => err_state_south_xbar_sel, err_state_local_xbar_sel => err_state_local_xbar_sel ); -- process for updating the state of arbiter's FSM, also setting RTS based on the state (if Grant is given or not) process(clk, reset)begin if reset = '0' then state<=IDLE; RTS_FF <= '0'; elsif clk'event and clk = '1' then -- no grant given yet, it might be that there is no request to -- arbiter or request is there, but the next router's/NI's FIFO is full state <= state_in; RTS_FF <= RTS_FF_in; end if; end process; -- anything below here is pure combinational RTS <= RTS_FF; -- Becuase of checkers we did this! Grant_N <= Grant_N_sig; Grant_E <= Grant_E_sig; Grant_W <= Grant_W_sig; Grant_S <= Grant_S_sig; Grant_L <= Grant_L_sig; Xbar_sel <= Xbar_sel_sig; process(RTS_FF, DCTS, state, next_state)begin if RTS_FF = '1' and DCTS = '0' then state_in <= state; else state_in <= next_state; end if; end process; process(state, RTS_FF, DCTS)begin if state = IDLE then RTS_FF_in <= '0'; -- if there was a grant given to one of the inputs, -- tell the next router/NI that the output data is valid else if RTS_FF = '1' and DCTS = '1' then RTS_FF_in <= '0'; else RTS_FF_in <= '1'; end if; end if ; end process; -- sets the grants using round robin -- the order is L --> N --> E --> W --> S and then back to L process(state, Req_N, Req_E, Req_W, Req_S, Req_L, DCTS, RTS_FF)begin Grant_N_sig <= '0'; Grant_E_sig <= '0'; Grant_W_sig <= '0'; Grant_S_sig <= '0'; Grant_L_sig <= '0'; Xbar_sel_sig <= "00000"; case(state) is when IDLE => Xbar_sel_sig <= "00000"; If Req_L = '1' then next_state <= Local; elsif Req_N = '1' then next_state <= North; elsif Req_E = '1' then next_state <= East; elsif Req_W = '1' then next_state <= West; elsif Req_S = '1' then next_state <= South; else next_state <= IDLE; end if; when North => Grant_N_sig <= DCTS and RTS_FF ; Xbar_sel_sig <= "00001"; If Req_N = '1' then next_state <= North; elsif Req_E = '1' then next_state <= East; elsif Req_W = '1' then next_state <= West; elsif Req_S = '1' then next_state <= South; elsif Req_L = '1' then next_state <= Local; else next_state <= IDLE; end if; when East => Grant_E_sig <= DCTS and RTS_FF; Xbar_sel_sig <= "00010"; If Req_E = '1' then next_state <= East; elsif Req_W = '1' then next_state <= West; elsif Req_S = '1' then next_state <= South; elsif Req_L = '1' then next_state <= Local; elsif Req_N = '1' then next_state <= North; else next_state <= IDLE; end if; when West => Grant_W_sig <= DCTS and RTS_FF; Xbar_sel_sig <= "00100"; If Req_W = '1' then next_state <= West; elsif Req_S = '1' then next_state <= South; elsif Req_L = '1' then next_state <= Local; elsif Req_N = '1' then next_state <= North; elsif Req_E = '1' then next_state <= East; else next_state <= IDLE; end if; when South => Grant_S_sig <= DCTS and RTS_FF; Xbar_sel_sig <= "01000"; If Req_S = '1' then next_state <= South; elsif Req_L = '1' then next_state <= Local; elsif Req_N = '1' then next_state <= North; elsif Req_E = '1' then next_state <= East; elsif Req_W = '1' then next_state <= West; else next_state <= IDLE; end if; when others => -- Local Grant_L_sig <= DCTS and RTS_FF; Xbar_sel_sig <= "10000"; If Req_L = '1' then next_state <= Local; elsif Req_N = '1' then next_state <= North; elsif Req_E = '1' then next_state <= East; elsif Req_W = '1' then next_state <= West; elsif Req_S = '1' then next_state <= South; else next_state <= IDLE; end if; end case ; end process; end;
gpl-3.0
f40a64ac76394c200bf39fbc59ec1a48
0.437833
3.642723
false
false
false
false
bruskajp/EE-316
Project2/Vivado_NexysBoard/project_2b/project_2b.srcs/sources_1/imports/Downloads/i2c_master_2.1.vhd
1
15,694
-------------------------------------------------------------------------------- -- -- FileName: i2c_master.vhd -- Dependencies: none -- Design Software: Quartus II 64-bit Version 13.1 Build 162 SJ Full Version -- -- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY -- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A -- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY -- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL -- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF -- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS -- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), -- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS. -- -- Version History -- Version 1.0 11/1/2012 Scott Larson -- Initial Public Release -- Version 2.0 06/20/2014 Scott Larson -- Added ability to interface with different slaves in the same transaction -- Corrected ack_error bug where ack_error went 'Z' instead of '1' on error -- Corrected timing of when ack_error signal clears -- Version 2.1 10/21/2014 Scott Larson -- Replaced gated clock with clock enable -- Adjusted timing of SCL during start and stop conditions -- -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY i2c_master IS GENERIC( input_clk : INTEGER := 100_000_000; --input clock speed from user logic in Hz bus_clk : INTEGER := 100_000); --speed the i2c bus (scl) will run at in Hz PORT( clk : IN STD_LOGIC; --system clock reset_n : IN STD_LOGIC; --active low reset ena : IN STD_LOGIC; --latch in command addr : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave rw : IN STD_LOGIC; --'0' is write, '1' is read data_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --data to write to slave busy : OUT STD_LOGIC; --indicates transaction in progress data_rd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave ack_error : BUFFER STD_LOGIC; --flag if improper acknowledge from slave sda : INOUT STD_LOGIC; --serial data output of i2c bus scl : INOUT STD_LOGIC); END i2c_master; ARCHITECTURE logic OF i2c_master IS CONSTANT divider : INTEGER := (input_clk/bus_clk)/4; --number of clocks in 1/4 cycle of scl TYPE machine IS(ready, start, command, slv_ack1, wr, rd, slv_ack2, mstr_ack, stop); --needed states SIGNAL state : machine; --state machine SIGNAL data_clk : STD_LOGIC; --data clock for sda SIGNAL data_clk_prev : STD_LOGIC; --data clock during previous system clock SIGNAL data_clk_m : STD_LOGIC; --data clock during previous system clock SIGNAL scl_clk : STD_LOGIC; --constantly running internal scl SIGNAL scl_ena : STD_LOGIC := '0'; --enables internal scl to output SIGNAL sda_int : STD_LOGIC := '1'; --internal sda SIGNAL sda_ena_n : STD_LOGIC; --enables internal sda to output SIGNAL addr_rw : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in address and read/write SIGNAL data_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in data to write to slave SIGNAL data_rx : STD_LOGIC_VECTOR(7 DOWNTO 0); --data received from slave SIGNAL bit_cnt : INTEGER RANGE 0 TO 7 := 7; --tracks bit number in transaction SIGNAL stretch : STD_LOGIC := '0'; --identifies if slave is stretching scl BEGIN --generate the timing for the bus clock (scl_clk) and the data clock (data_clk) PROCESS(clk, reset_n) VARIABLE count : INTEGER RANGE 0 TO divider*4; --timing for clock generation BEGIN IF(reset_n = '0') THEN --reset asserted stretch <= '0'; count := 0; ELSIF(clk'EVENT AND clk = '1') THEN data_clk_prev <= data_clk; --store previous value of data clock IF(count = 999) THEN --end of timing cycle count := 0; --reset timer ELSIF(stretch = '0') THEN --clock stretching from slave not detected count := count + 1; --continue clock generation timing END IF; CASE count IS WHEN 0 TO 249 => --first 1/4 cycle of clocking scl_clk <= '0'; data_clk <= '0'; WHEN 250 TO 499 => --second 1/4 cycle of clocking scl_clk <= '0'; data_clk <= '1'; WHEN 500 TO 749 => --third 1/4 cycle of clocking scl_clk <= '1'; --release scl IF(scl = '0') THEN --detect if slave is stretching clock stretch <= '1'; ELSE stretch <= '0'; END IF; data_clk <= '1'; WHEN OTHERS => --last 1/4 cycle of clocking scl_clk <= '1'; data_clk <= '0'; END CASE; END IF; END PROCESS; --state machine and writing to sda during scl low (data_clk rising edge) PROCESS(clk, reset_n) BEGIN IF(reset_n = '0') THEN --reset asserted state <= ready; --return to initial state busy <= '1'; --indicate not available scl_ena <= '0'; --sets scl high impedance sda_int <= '1'; --sets sda high impedance ack_error <= '0'; --clear acknowledge error flag bit_cnt <= 7; --restarts data bit counter data_rd <= "00000000"; --clear data read port ELSIF(clk'EVENT AND clk = '1') THEN IF(data_clk = '1' AND data_clk_prev = '0') THEN --data clock rising edge CASE state IS WHEN ready => --idle state IF(ena = '1') THEN --transaction requested busy <= '1'; --flag busy addr_rw <= addr & rw; --collect requested slave address and command data_tx <= data_wr; --collect requested data to write state <= start; --go to start bit ELSE --remain idle busy <= '0'; --unflag busy state <= ready; --remain idle END IF; WHEN start => --start bit of transaction busy <= '1'; --resume busy if continuous mode sda_int <= addr_rw(bit_cnt); --set first address bit to bus state <= command; --go to command WHEN command => --address and command byte of transaction IF(bit_cnt = 0) THEN --command transmit finished sda_int <= '1'; --release sda for slave acknowledge bit_cnt <= 7; --reset bit counter for "byte" states state <= slv_ack1; --go to slave acknowledge (command) ELSE --next clock cycle of command state bit_cnt <= bit_cnt - 1; --keep track of transaction bits sda_int <= addr_rw(bit_cnt-1); --write address/command bit to bus state <= command; --continue with command END IF; WHEN slv_ack1 => --slave acknowledge bit (command) IF(addr_rw(0) = '0') THEN --write command sda_int <= data_tx(bit_cnt); --write first bit of data state <= wr; --go to write byte ELSE --read command sda_int <= '1'; --release sda from incoming data state <= rd; --go to read byte END IF; WHEN wr => --write byte of transaction busy <= '1'; --resume busy if continuous mode IF(bit_cnt = 0) THEN --write byte transmit finished sda_int <= '1'; --release sda for slave acknowledge bit_cnt <= 7; --reset bit counter for "byte" states -- added the following line to make sure busy = 0 in the slv_ack2 state busy <= '0'; --continue is accepted (modified by CU) state <= slv_ack2; --go to slave acknowledge (write) ELSE --next clock cycle of write state bit_cnt <= bit_cnt - 1; --keep track of transaction bits sda_int <= data_tx(bit_cnt-1); --write next bit to bus state <= wr; --continue writing END IF; WHEN rd => --read byte of transaction busy <= '1'; --resume busy if continuous mode IF(bit_cnt = 0) THEN --read byte receive finished IF(ena = '1' AND addr_rw = addr & rw) THEN --continuing with another read at same address sda_int <= '0'; --acknowledge the byte has been received ELSE --stopping or continuing with a write sda_int <= '1'; --send a no-acknowledge (before stop or repeated start) END IF; bit_cnt <= 7; --reset bit counter for "byte" states -- added the following line to make sure busy = 0 in the mstr_ack state busy <= '0'; --continue is accepted (modified by CU) data_rd <= data_rx; --output received data state <= mstr_ack; --go to master acknowledge ELSE --next clock cycle of read state bit_cnt <= bit_cnt - 1; --keep track of transaction bits state <= rd; --continue reading END IF; WHEN slv_ack2 => --slave acknowledge bit (write) IF(ena = '1') THEN --continue transaction -- busy <= '0'; --continue is accepted (modified by CU) addr_rw <= addr & rw; --collect requested slave address and command data_tx <= data_wr; --collect requested data to write IF(addr_rw = addr & rw) THEN --continue transaction with another write busy <= '1'; --resume busy in the wr state (modified by CU) sda_int <= data_wr(bit_cnt); --write first bit of data state <= wr; --go to write byte ELSE --continue transaction with a read or new slave state <= start; --go to repeated start END IF; ELSE --complete transaction busy <= '0'; --unflag busy (modified by CU) sda_int <= '1'; --sets sda high impedance (modified by CU) state <= stop; --go to stop bit END IF; WHEN mstr_ack => --master acknowledge bit after a read IF(ena = '1') THEN --continue transaction -- busy <= '0'; --continue is accepted (modified by CU) addr_rw <= addr & rw; --collect requested slave address and command data_tx <= data_wr; --collect requested data to write IF(addr_rw = addr & rw) THEN --continue transaction with another read busy <= '1'; --resume busy in the wr state (modified by CU) sda_int <= '1'; --release sda from incoming data state <= rd; --go to read byte ELSE --continue transaction with a write or new slave state <= start; --repeated start END IF; ELSE --complete transaction busy <= '0'; --unflag busy (modified by CU) sda_int <= '1'; --sets sda high impedance (modified by CU) state <= stop; --go to stop bit END IF; WHEN stop => --stop bit of transaction -- busy <= '0'; --unflag busy (modified by CU) state <= ready; --go to idle state END CASE; ELSIF(data_clk = '0' AND data_clk_prev = '1') THEN --data clock falling edge CASE state IS WHEN start => IF(scl_ena = '0') THEN --starting new transaction scl_ena <= '1'; --enable scl output ack_error <= '0'; --reset acknowledge error output END IF; WHEN slv_ack1 => --receiving slave acknowledge (command) IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge ack_error <= '1'; --set error output if no-acknowledge END IF; WHEN rd => --receiving slave data data_rx(bit_cnt) <= sda; --receive current slave data bit WHEN slv_ack2 => --receiving slave acknowledge (write) IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge ack_error <= '1'; --set error output if no-acknowledge END IF; WHEN stop => scl_ena <= '0'; --disable scl WHEN OTHERS => NULL; END CASE; END IF; END IF; END PROCESS; --set sda output data_clk_m <= data_clk_prev and data_clk; -- Modification added at CU WITH state SELECT sda_ena_n <= data_clk WHEN start, --generate start condition NOT data_clk_m WHEN stop, --generate stop condition (modification added at CU) sda_int WHEN OTHERS; --set to internal sda signal --set scl and sda outputs scl <= '0' WHEN (scl_ena = '1' AND scl_clk = '0') ELSE 'Z'; sda <= '0' WHEN sda_ena_n = '0' ELSE 'Z'; -- Following two signals will be used for tristate obuft (did not work) -- scl <= '1' WHEN (scl_ena = '1' AND scl_clk = '0') ELSE '0'; -- sda <= '1' WHEN sda_ena_n = '0' ELSE '0'; END logic;
gpl-3.0
d9c0715b7034f4203ed44e94578916d1
0.474767
4.686175
false
false
false
false
TUM-LIS/faultify
hardware/testcases/viterbi/fpga_sim/xpsLibraryPath/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/vhdl/user_logic.vhd
2
29,243
------------------------------------------------------------------------------ -- user_logic.vhd - entity/architecture pair ------------------------------------------------------------------------------ -- -- *************************************************************************** -- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** Xilinx, Inc. ** -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** -- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** -- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** -- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** -- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** -- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** -- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** -- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** -- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** -- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** -- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** -- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** -- ** FOR A PARTICULAR PURPOSE. ** -- ** ** -- *************************************************************************** -- ------------------------------------------------------------------------------ -- Filename: user_logic.vhd -- Version: 1.00.a -- Description: User logic. -- Date: Fri May 16 15:25:24 2014 (by Create and Import Peripheral Wizard) -- VHDL Standard: VHDL'93 ------------------------------------------------------------------------------ -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port: "*_i" -- device pins: "*_pin" -- ports: "- Names begin with Uppercase" -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC>" ------------------------------------------------------------------------------ -- DO NOT EDIT BELOW THIS LINE -------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library proc_common_v3_00_a; use proc_common_v3_00_a.proc_common_pkg.all; -- DO NOT EDIT ABOVE THIS LINE -------------------- --USER libraries added here ------------------------------------------------------------------------------ -- Entity section ------------------------------------------------------------------------------ -- Definition of Generics: -- C_NUM_REG -- Number of software accessible registers -- C_SLV_DWIDTH -- Slave interface data bus width -- -- Definition of Ports: -- Bus2IP_Clk -- Bus to IP clock -- Bus2IP_Resetn -- Bus to IP reset -- Bus2IP_Data -- Bus to IP data bus -- Bus2IP_BE -- Bus to IP byte enables -- Bus2IP_RdCE -- Bus to IP read chip enable -- Bus2IP_WrCE -- Bus to IP write chip enable -- IP2Bus_Data -- IP to Bus data bus -- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement -- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement -- IP2Bus_Error -- IP to Bus error response ------------------------------------------------------------------------------ entity user_logic is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- --USER generics added here -- ADD USER GENERICS ABOVE THIS LINE --------------- -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_NUM_REG : integer := 32; C_SLV_DWIDTH : integer := 32 -- DO NOT EDIT ABOVE THIS LINE --------------------- ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ --USER ports added here faultify_clk_fast : in std_logic; -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete Bus2IP_Clk : in std_logic; Bus2IP_Resetn : in std_logic; Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0); Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0); Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0); Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0); IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0); IP2Bus_RdAck : out std_logic; IP2Bus_WrAck : out std_logic; IP2Bus_Error : out std_logic -- DO NOT EDIT ABOVE THIS LINE --------------------- ); attribute MAX_FANOUT : string; attribute SIGIS : string; attribute SIGIS of Bus2IP_Clk : signal is "CLK"; attribute SIGIS of Bus2IP_Resetn : signal is "RST"; end entity user_logic; ------------------------------------------------------------------------------ -- Architecture section ------------------------------------------------------------------------------ architecture IMP of user_logic is --USER signal declarations added here, as needed for user logic component faultify_top generic ( numInj : integer; numIn : integer; numOut : integer); port ( aclk : in std_logic; arst_n : in std_logic; clk : in std_logic; clk_x32 : in std_logic; awvalid : in std_logic; awaddr : in std_logic_vector(31 downto 0); wvalid : in std_logic; wdata : in std_logic_vector(31 downto 0); arvalid : in std_logic; araddr : in std_logic_vector(31 downto 0); rvalid : out std_logic; rdata : out std_logic_vector(31 downto 0)); end component; ------------------------------------------ -- Signals for user logic slave model s/w accessible register example ------------------------------------------ signal register_write_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal register_read_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal register_write_address : std_logic_vector(C_NUM_REG-1 downto 0); signal register_read_address : std_logic_vector(C_NUM_REG-1 downto 0); signal slv_reg_write_sel : std_logic_vector(31 downto 0); signal slv_reg_read_sel : std_logic_vector(31 downto 0); signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_read_ack : std_logic; signal slv_write_ack : std_logic; signal faultify_read_valid : std_logic; signal faultify_read_address_valid : std_logic; signal faultify_read_address : std_logic_vector(31 downto 0); signal faultify_write_valid : std_logic; signal counter, divide : integer := 0; signal faultify_clk_slow_i : std_logic; begin slv_reg_write_sel <= Bus2IP_WrCE(31 downto 0); slv_reg_read_sel <= Bus2IP_RdCE(31 downto 0); slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12) or Bus2IP_WrCE(13) or Bus2IP_WrCE(14) or Bus2IP_WrCE(15) or Bus2IP_WrCE(16) or Bus2IP_WrCE(17) or Bus2IP_WrCE(18) or Bus2IP_WrCE(19) or Bus2IP_WrCE(20) or Bus2IP_WrCE(21) or Bus2IP_WrCE(22) or Bus2IP_WrCE(23) or Bus2IP_WrCE(24) or Bus2IP_WrCE(25) or Bus2IP_WrCE(26) or Bus2IP_WrCE(27) or Bus2IP_WrCE(28) or Bus2IP_WrCE(29) or Bus2IP_WrCE(30) or Bus2IP_WrCE(31); slv_read_ack <= faultify_read_valid; -- implement slave model software accessible register(s) SLAVE_REG_WRITE_PROC : process(Bus2IP_Clk) is begin if Bus2IP_Clk'event and Bus2IP_Clk = '1' then if Bus2IP_Resetn = '0' then register_write_data <= (others => '0'); register_write_address <= (others => '0'); faultify_write_valid <= '0'; else faultify_write_valid <= slv_write_ack; case slv_reg_write_sel is when "10000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(0, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "01000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(1, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00100000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(2, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00010000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(3, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00001000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(4, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000100000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(5, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000010000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(6, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000001000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(7, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000100000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(8, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000010000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(9, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000001000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(10, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000100000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(11, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000010000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(12, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000001000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(13, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000100000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(14, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000010000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(15, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000001000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(16, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000100000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(17, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000010000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(18, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000001000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(19, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000000100000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(20, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000000010000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(21, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000000001000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(22, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000000000100000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(23, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000000000010000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(24, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000000000001000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(25, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000000000000100000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(26, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000000000000010000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(27, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000000000000001000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(28, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000000000000000100" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(29, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000000000000000010" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(30, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000000000000000001" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(31, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when others => null; end case; end if; end if; end process SLAVE_REG_WRITE_PROC; -- implement slave model software accessible register(s) read mux SLAVE_REG_READ_PROC : process(slv_reg_read_sel, faultify_read_valid) is begin faultify_read_address_valid <= '1'; case slv_reg_read_sel is when "10000000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(0, 32)); when "01000000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(1, 32)); when "00100000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(2, 32)); when "00010000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(3, 32)); when "00001000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(4, 32)); when "00000100000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(5, 32)); when "00000010000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(6, 32)); when "00000001000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(7, 32)); when "00000000100000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(8, 32)); when "00000000010000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(9, 32)); when "00000000001000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(10, 32)); when "00000000000100000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(11, 32)); when "00000000000010000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(12, 32)); when "00000000000001000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(13, 32)); when "00000000000000100000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(14, 32)); when "00000000000000010000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(15, 32)); when "00000000000000001000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(16, 32)); when "00000000000000000100000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(17, 32)); when "00000000000000000010000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(18, 32)); when "00000000000000000001000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(19, 32)); when "00000000000000000000100000000000" => faultify_read_address <= std_logic_vector(to_unsigned(20, 32)); when "00000000000000000000010000000000" => faultify_read_address <= std_logic_vector(to_unsigned(21, 32)); when "00000000000000000000001000000000" => faultify_read_address <= std_logic_vector(to_unsigned(22, 32)); when "00000000000000000000000100000000" => faultify_read_address <= std_logic_vector(to_unsigned(23, 32)); when "00000000000000000000000010000000" => faultify_read_address <= std_logic_vector(to_unsigned(24, 32)); when "00000000000000000000000001000000" => faultify_read_address <= std_logic_vector(to_unsigned(25, 32)); when "00000000000000000000000000100000" => faultify_read_address <= std_logic_vector(to_unsigned(26, 32)); when "00000000000000000000000000010000" => faultify_read_address <= std_logic_vector(to_unsigned(27, 32)); when "00000000000000000000000000001000" => faultify_read_address <= std_logic_vector(to_unsigned(28, 32)); when "00000000000000000000000000000100" => faultify_read_address <= std_logic_vector(to_unsigned(29, 32)); when "00000000000000000000000000000010" => faultify_read_address <= std_logic_vector(to_unsigned(30, 32)); when "00000000000000000000000000000001" => faultify_read_address <= std_logic_vector(to_unsigned(31, 32)); when others => faultify_read_address <= (others => '0'); faultify_read_address_valid <= '0'; end case; end process SLAVE_REG_READ_PROC; ------------------------------------------ -- Example code to drive IP to Bus signals ------------------------------------------ IP2Bus_Data <= register_read_data when faultify_read_valid = '1' else (others => '0'); IP2Bus_WrAck <= slv_write_ack; IP2Bus_RdAck <= slv_read_ack; IP2Bus_Error <= '0'; ----------------------------------------------------------------------------- -- clock divider 32 -> 1 ----------------------------------------------------------------------------- divide <= 32; process(Bus2IP_Clk, Bus2IP_Resetn) begin if Bus2IP_Resetn = '0' then counter <= 0; faultify_clk_slow_i <= '0'; elsif(rising_edge(Bus2IP_Clk)) then if(counter < divide/2-1) then counter <= counter + 1; faultify_clk_slow_i <= '0'; elsif(counter < divide-1) then counter <= counter + 1; faultify_clk_slow_i <= '1'; else faultify_clk_slow_i <= '0'; counter <= 0; end if; end if; end process; faultify_top_1 : faultify_top generic map ( numInj => 216, numIn => 32, numOut => 54) port map ( aclk => Bus2IP_Clk, arst_n => Bus2IP_Resetn, clk => faultify_clk_slow_i, clk_x32 => Bus2IP_Clk, awvalid => faultify_write_valid, awaddr => register_write_address, wvalid => faultify_write_valid, wdata => register_write_data, arvalid => faultify_read_address_valid, araddr => faultify_read_address, rvalid => faultify_read_valid, rdata => register_read_data); end IMP;
gpl-2.0
f153d38ce5fe4c48f1c5d5243bb3219a
0.539309
4.022974
false
false
false
false
bruskajp/EE-316
Project4/Vivado_NexysBoard/craddockEE316/craddockEE316.srcs/sources_1/new/PWM_Controller.vhd
1
1,394
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 03/16/2017 12:12:06 PM -- Design Name: -- Module Name: PWM_Controller - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity PWM_Controller is port( iadc_sel : in std_logic; iSW : in std_logic; iData : in std_logic_vector(7 downto 0); --iData2 : in std_logic_vector(7 downto 0); oData : out std_logic_vector(7 downto 0) ); end PWM_Controller; architecture Behavioral of PWM_Controller is begin process(iadc_sel,iSW) begin if iadc_sel = '0' and iSW = '0' then oData <= iData; elsif iadc_sel = '1' and iSW = '1' then oData <= iData; else oData <= "00000000"; end if; end process; end Behavioral;
gpl-3.0
44c17cbccf7873ceae8ce4d3716ab2d8
0.565997
3.883008
false
false
false
false
SoCdesign/EHA
RTL/Hand_Shaking/Checkers/Modules_with_checkers_integrated/Dominant_checkers/FIFO_one_hot_with_dominant_checkers/FIFO_one_hot_with_checkers.vhd
1
10,696
--Copyright (C) 2016 Siavoosh Payandeh Azad library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity FIFO is generic ( DATA_WIDTH: integer := 32 ); port ( reset: in std_logic; clk: in std_logic; RX: in std_logic_vector(DATA_WIDTH-1 downto 0); DRTS: in std_logic; read_en_N : in std_logic; read_en_E : in std_logic; read_en_W : in std_logic; read_en_S : in std_logic; read_en_L : in std_logic; CTS: out std_logic; empty_out: out std_logic; Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0); -- Checker outputs err_write_en_write_pointer, err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full, err_read_pointer_increment, err_read_pointer_not_increment, --err_CTS_in, err_write_en, err_not_CTS_in, --err_not_write_en, err_read_en_mismatch : out std_logic ); end FIFO; architecture behavior of FIFO is signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(3 downto 0); signal full, empty: std_logic; signal read_en, write_en: std_logic; signal CTS_in, CTS_out: std_logic; signal FIFO_MEM_1, FIFO_MEM_1_in : std_logic_vector(DATA_WIDTH-1 downto 0); signal FIFO_MEM_2, FIFO_MEM_2_in : std_logic_vector(DATA_WIDTH-1 downto 0); signal FIFO_MEM_3, FIFO_MEM_3_in : std_logic_vector(DATA_WIDTH-1 downto 0); signal FIFO_MEM_4, FIFO_MEM_4_in : std_logic_vector(DATA_WIDTH-1 downto 0); component FIFO_control_part_checkers is port ( DRTS: in std_logic; CTS_out: in std_logic; CTS_in: in std_logic; read_en_N : in std_logic; read_en_E : in std_logic; read_en_W : in std_logic; read_en_S : in std_logic; read_en_L : in std_logic; read_pointer: in std_logic_vector(3 downto 0); read_pointer_in: in std_logic_vector(3 downto 0); write_pointer: in std_logic_vector(3 downto 0); write_pointer_in: in std_logic_vector(3 downto 0); empty_out: in std_logic; full_out: in std_logic; read_en_out: in std_logic; write_en_out: in std_logic; -- Checker outputs err_write_en_write_pointer, err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full, err_read_pointer_increment, err_read_pointer_not_increment, --err_CTS_in, err_write_en, err_not_CTS_in, --err_not_write_en, err_read_en_mismatch : out std_logic ); end component; begin -------------------------------------------------------------------------------------------- -- block diagram of the FIFO! -- previous -- router -- -- ------------------------------------------ -- | | | -- TX|--------->| RX Data_out|----> goes to Xbar and LBDR -- | | | -- RTS|--------->| DRTS FIFO read_en|<---- Comes from Arbiters (N,E,W,S,L) -- | | (N,E,W,S,L)| -- DCTS|<---------| CTS | -- -- ------------------------------------------ -------------------------------------------------------------------------------------------- -- Hand shake protocol! -- -- |<-Valid->| -- | Data | -- _____ _________ ______ -- RX _____X_________X______ -- DRTS _____|'''''''''|_____ -- CTS __________|''''|_______ -- -------------------------------------------------------------------------------------------- -- circular buffer structure -- <--- WriteP -- --------------------------------- -- | 3 | 2 | 1 | 0 | -- --------------------------------- -- <--- readP -------------------------------------------------------------------------------------------- -- FIFO Control Part checkers instantiation FIFOCONTROLPARTCHECKERS: FIFO_control_part_checkers port map ( DRTS => DRTS, CTS_out => CTS_out, CTS_in => CTS_in, read_en_N => read_en_N, read_en_E => read_en_E, read_en_W => read_en_W, read_en_S => read_en_S, read_en_L => read_en_L, read_pointer => read_pointer, read_pointer_in => read_pointer_in, write_pointer => write_pointer, write_pointer_in => write_pointer_in, empty_out => empty, full_out => full, read_en_out => read_en, write_en_out => write_en, err_write_en_write_pointer => err_write_en_write_pointer, err_not_write_en_write_pointer => err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty => err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty => err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full => err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full => err_read_pointer_write_pointer_full, err_read_pointer_increment => err_read_pointer_increment, err_read_pointer_not_increment => err_read_pointer_not_increment, err_write_en => err_write_en, err_not_CTS_in => err_not_CTS_in, err_read_en_mismatch => err_read_en_mismatch ); process (clk, reset)begin if reset = '0' then read_pointer <= "0001"; write_pointer <= "0001"; CTS_out<='0'; FIFO_MEM_1 <= (others=>'0'); FIFO_MEM_2 <= (others=>'0'); FIFO_MEM_3 <= (others=>'0'); FIFO_MEM_4 <= (others=>'0'); elsif clk'event and clk = '1' then write_pointer <= write_pointer_in; if write_en = '1' then --write into the memory FIFO_MEM_1 <= FIFO_MEM_1_in; FIFO_MEM_2 <= FIFO_MEM_2_in; FIFO_MEM_3 <= FIFO_MEM_3_in; FIFO_MEM_4 <= FIFO_MEM_4_in; end if; read_pointer <= read_pointer_in; CTS_out<=CTS_in; end if; end process; -- anything below here is pure combinational -- combinatorial part process(RX, write_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin case( write_pointer ) is when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4; when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX; when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; end case ; end process; process(read_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin case( read_pointer ) is when "0001" => Data_out <= FIFO_MEM_1; when "0010" => Data_out <= FIFO_MEM_2; when "0100" => Data_out <= FIFO_MEM_3; when "1000" => Data_out <= FIFO_MEM_4; when others => Data_out <= FIFO_MEM_1; end case ; end process; read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty; empty_out <= empty; CTS <= CTS_out; process(write_en, write_pointer)begin if write_en = '1'then write_pointer_in <= write_pointer(2 downto 0)&write_pointer(3); else write_pointer_in <= write_pointer; end if; end process; process(read_en, empty, read_pointer)begin if (read_en = '1' and empty = '0') then read_pointer_in <= read_pointer(2 downto 0)&read_pointer(3); else read_pointer_in <= read_pointer; end if; end process; process(full, DRTS, CTS_out) begin if CTS_out = '0' and DRTS = '1' and full ='0' then CTS_in <= '1'; write_en <= '1'; else CTS_in <= '0'; write_en <= '0'; end if; end process; process(write_pointer, read_pointer) begin if read_pointer = write_pointer then empty <= '1'; else empty <= '0'; end if; -- if write_pointer = read_pointer>>1 then if write_pointer = read_pointer(0)&read_pointer(3 downto 1) then full <= '1'; else full <= '0'; end if; end process; end;
gpl-3.0
b1f6ce4812712d288cd0f2b0dc3d2233
0.430909
4.004493
false
false
false
false
SoCdesign/EHA
RTL/Immortal_Chip/Router_32_bit.vhd
1
12,178
--Copyright (C) 2016 Siavoosh Payandeh Azad library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity router is generic ( DATA_WIDTH: integer := 32; current_address : integer := 5; Rxy_rst : integer := 60; Cx_rst : integer := 15; NoC_size: integer := 4 ); port ( reset, clk: in std_logic; DCTS_N, DCTS_E, DCTS_w, DCTS_S, DCTS_L: in std_logic; DRTS_N, DRTS_E, DRTS_W, DRTS_S, DRTS_L: in std_logic; RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0); RTS_N, RTS_E, RTS_W, RTS_S, RTS_L: out std_logic; CTS_N, CTS_E, CTS_w, CTS_S, CTS_L: out std_logic; TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0) ); end router; architecture behavior of router is COMPONENT router_channel is generic ( DATA_WIDTH: integer := 32; current_address : integer := 5; Rxy_rst : integer := 60; Cx_rst : integer := 15; NoC_size: integer := 4 ); port ( reset, clk: in std_logic; DCTS : in std_logic; DRTS : in std_logic; RTS : out std_logic; CTS : out std_logic; flit_type : in std_logic_vector(2 downto 0); destination_address : in std_logic_vector(NoC_size-1 downto 0); Grant_N_in , Grant_E_in , Grant_W_in , Grant_S_in , Grant_L_in : in std_logic; Grant_N_out, Grant_E_out, Grant_W_out, Grant_S_out, Grant_L_out: out std_logic; Req_N_in , Req_E_in , Req_W_in , Req_S_in , Req_L_in :in std_logic; Req_N_out , Req_E_out, Req_W_out, Req_S_out, Req_L_out:out std_logic; read_pointer_out, write_pointer_out: out std_logic_vector(3 downto 0); write_en_out :out std_logic; Xbar_sel: out std_logic_vector(4 downto 0) ); end COMPONENT; COMPONENT XBAR is generic ( DATA_WIDTH: integer := 32 ); port ( North_in: in std_logic_vector(DATA_WIDTH-1 downto 0); East_in: in std_logic_vector(DATA_WIDTH-1 downto 0); West_in: in std_logic_vector(DATA_WIDTH-1 downto 0); South_in: in std_logic_vector(DATA_WIDTH-1 downto 0); Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0); sel: in std_logic_vector (4 downto 0); Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0) ); end COMPONENT; COMPONENT FIFO_data_path is generic ( DATA_WIDTH: integer := 32 ); port ( reset: in std_logic; clk: in std_logic; RX: in std_logic_vector(DATA_WIDTH-1 downto 0); read_pointer, write_pointer: in std_logic_vector(3 downto 0); write_en : in std_logic; Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0) ); end COMPONENT; signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0); signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0); signal write_pointer_out_N, write_pointer_out_E, write_pointer_out_W, write_pointer_out_S, write_pointer_out_L: std_logic_vector(3 downto 0); signal read_pointer_out_N, read_pointer_out_E, read_pointer_out_W, read_pointer_out_S, read_pointer_out_L: std_logic_vector(3 downto 0); signal write_en_out_N, write_en_out_E, write_en_out_W, write_en_out_S, write_en_out_L: std_logic; signal Grant_N_N, Grant_N_E, Grant_N_W, Grant_N_S, Grant_N_L: std_logic; signal Grant_E_N, Grant_E_E, Grant_E_W, Grant_E_S, Grant_E_L: std_logic; signal Grant_W_N, Grant_W_E, Grant_W_W, Grant_W_S, Grant_W_L: std_logic; signal Grant_S_N, Grant_S_E, Grant_S_W, Grant_S_S, Grant_S_L: std_logic; signal Grant_L_N, Grant_L_E, Grant_L_W, Grant_L_S, Grant_L_L: std_logic; signal Req_N_N, Req_E_N, Req_W_N, Req_S_N, Req_L_N: std_logic; signal Req_N_E, Req_E_E, Req_W_E, Req_S_E, Req_L_E: std_logic; signal Req_N_W, Req_E_W, Req_W_W, Req_S_W, Req_L_W: std_logic; signal Req_N_S, Req_E_S, Req_W_S, Req_S_S, Req_L_S: std_logic; signal Req_N_L, Req_E_L, Req_W_L, Req_S_L, Req_L_L: std_logic; begin Channel_N: router_channel generic map (DATA_WIDTH => DATA_WIDTH, current_address =>current_address, Rxy_rst =>Rxy_rst, Cx_rst =>Cx_rst, NoC_size => NoC_size) port map (reset=> reset, clk => clk, DCTS => DCTS_N, DRTS => DRTS_N, RTS=>RTS_N, CTS=>CTS_N, flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), destination_address=> FIFO_D_out_N(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19), Grant_N_in => '0' , Grant_E_in => Grant_E_N , Grant_W_in => Grant_W_N , Grant_S_in => Grant_S_N , Grant_L_in => Grant_L_N , Grant_N_out => Grant_N_N, Grant_E_out => Grant_N_E, Grant_W_out => Grant_N_W, Grant_S_out => Grant_N_S, Grant_L_out => Grant_N_L, Req_N_in => '0' , Req_E_in => Req_E_N , Req_W_in => Req_W_N , Req_S_in => Req_S_N , Req_L_in => Req_L_N , Req_N_out => Req_N_N , Req_E_out => Req_N_E , Req_W_out => Req_N_W , Req_S_out => Req_N_S , Req_L_out => Req_N_L , read_pointer_out => read_pointer_out_N, write_pointer_out => write_pointer_out_N, write_en_out=>write_en_out_N, Xbar_sel=>Xbar_sel_N); Channel_E: router_channel generic map (DATA_WIDTH => DATA_WIDTH, current_address =>current_address, Rxy_rst =>Rxy_rst, Cx_rst =>Cx_rst, NoC_size => NoC_size) port map (reset=> reset, clk => clk, DCTS => DCTS_E, DRTS => DRTS_E, RTS=>RTS_E, CTS=>CTS_E, flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), destination_address=> FIFO_D_out_E(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19), Grant_N_in => Grant_N_E , Grant_E_in => '0' , Grant_W_in => Grant_W_E , Grant_S_in => Grant_S_E , Grant_L_in => Grant_L_E , Grant_N_out => Grant_E_N, Grant_E_out => Grant_E_E, Grant_W_out => Grant_E_W, Grant_S_out => Grant_E_S, Grant_L_out => Grant_E_L, Req_N_in => Req_N_E , Req_E_in => '0' , Req_W_in => Req_W_E , Req_S_in => Req_S_E , Req_L_in => Req_L_E , Req_N_out => Req_E_N , Req_E_out => Req_E_E , Req_W_out => Req_E_W , Req_S_out => Req_E_S , Req_L_out => Req_E_L , read_pointer_out => read_pointer_out_E, write_pointer_out => write_pointer_out_E, write_en_out=>write_en_out_E, Xbar_sel=>Xbar_sel_E); Channel_W: router_channel generic map (DATA_WIDTH => DATA_WIDTH, current_address =>current_address, Rxy_rst =>Rxy_rst, Cx_rst =>Cx_rst, NoC_size => NoC_size) port map (reset=> reset, clk => clk, DCTS => DCTS_W, DRTS => DRTS_W, RTS=>RTS_W, CTS=>CTS_W, flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), destination_address=> FIFO_D_out_W(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19), Grant_N_in => Grant_N_W , Grant_E_in => Grant_E_W , Grant_W_in => '0' , Grant_S_in => Grant_S_W , Grant_L_in => Grant_L_W , Grant_N_out => Grant_W_N, Grant_E_out => Grant_W_E, Grant_W_out => Grant_W_W, Grant_S_out => Grant_W_S, Grant_L_out => Grant_W_L, Req_N_in => Req_N_W , Req_E_in => Req_E_W , Req_W_in => '0' , Req_S_in => Req_S_W , Req_L_in => Req_L_W , Req_N_out => Req_W_N , Req_E_out => Req_W_E , Req_W_out => Req_W_W , Req_S_out => Req_W_S , Req_L_out => Req_W_L , read_pointer_out => read_pointer_out_W, write_pointer_out => write_pointer_out_W, write_en_out=>write_en_out_W, Xbar_sel=>Xbar_sel_W); Channel_S: router_channel generic map (DATA_WIDTH => DATA_WIDTH, current_address =>current_address, Rxy_rst =>Rxy_rst, Cx_rst =>Cx_rst, NoC_size => NoC_size) port map (reset=> reset, clk => clk, DCTS => DCTS_S, DRTS => DRTS_S, RTS=>RTS_S, CTS=>CTS_S, flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), destination_address=> FIFO_D_out_S(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19), Grant_N_in => Grant_N_S , Grant_E_in => Grant_E_S , Grant_W_in => Grant_W_S , Grant_S_in => '0' , Grant_L_in => Grant_L_S , Grant_N_out => Grant_S_N, Grant_E_out => Grant_S_E, Grant_W_out => Grant_S_W, Grant_S_out => Grant_S_S, Grant_L_out => Grant_S_L, Req_N_in => Req_N_S , Req_E_in => Req_E_S , Req_W_in => Req_W_S , Req_S_in => '0' , Req_L_in => Req_L_S , Req_N_out => Req_S_N , Req_E_out => Req_S_E , Req_W_out => Req_S_W , Req_S_out => Req_S_S , Req_L_out => Req_S_L , read_pointer_out => read_pointer_out_S, write_pointer_out => write_pointer_out_S, write_en_out=>write_en_out_S, Xbar_sel=>Xbar_sel_S); Channel_L: router_channel generic map (DATA_WIDTH => DATA_WIDTH, current_address =>current_address, Rxy_rst =>Rxy_rst, Cx_rst =>Cx_rst, NoC_size => NoC_size) port map (reset=> reset, clk => clk, DCTS => DCTS_L, DRTS => DRTS_L, RTS=>RTS_L, CTS=>CTS_L, flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), destination_address=> FIFO_D_out_L(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19), Grant_N_in => Grant_N_L , Grant_E_in => Grant_E_L , Grant_W_in => Grant_W_L , Grant_S_in => Grant_S_L , Grant_L_in => '0' , Grant_N_out => Grant_L_N, Grant_E_out => Grant_L_E, Grant_W_out => Grant_L_W, Grant_S_out => Grant_L_S, Grant_L_out => Grant_L_L, Req_N_in => Req_N_L , Req_E_in => Req_E_L , Req_W_in => Req_W_L , Req_S_in => Req_S_L , Req_L_in => '0' , Req_N_out => Req_L_N , Req_E_out => Req_L_E , Req_W_out => Req_L_W , Req_S_out => Req_L_S , Req_L_out => Req_L_L , read_pointer_out => read_pointer_out_L, write_pointer_out => write_pointer_out_L, write_en_out=>write_en_out_L, Xbar_sel=>Xbar_sel_L); xbar_N: XBAR generic map(DATA_WIDTH => DATA_WIDTH) port map (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in=> FIFO_D_out_W, South_in=> FIFO_D_out_S, Local_in=> FIFO_D_out_L, sel=>Xbar_sel_N, Data_out=> TX_N); xbar_E: XBAR generic map(DATA_WIDTH => DATA_WIDTH) port map (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in=> FIFO_D_out_W, South_in=> FIFO_D_out_S, Local_in=> FIFO_D_out_L, sel=>Xbar_sel_E, Data_out=> TX_E); xbar_W: XBAR generic map(DATA_WIDTH => DATA_WIDTH) port map (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in=> FIFO_D_out_W, South_in=> FIFO_D_out_S, Local_in=> FIFO_D_out_L, sel=>Xbar_sel_W, Data_out=> TX_W); xbar_S: XBAR generic map(DATA_WIDTH => DATA_WIDTH) port map (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in=> FIFO_D_out_W, South_in=> FIFO_D_out_S, Local_in=> FIFO_D_out_L, sel=>Xbar_sel_S, Data_out=> TX_S); xbar_L: XBAR generic map(DATA_WIDTH => DATA_WIDTH) port map (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in=> FIFO_D_out_W, South_in=> FIFO_D_out_S, Local_in=> FIFO_D_out_L, sel=>Xbar_sel_L, Data_out=> TX_L); FIFO_N: FIFO_data_path generic map(DATA_WIDTH => DATA_WIDTH) port map(clk => clk, reset => reset, RX => RX_N, read_pointer => read_pointer_out_N, write_pointer => write_pointer_out_N, write_en => write_en_out_N, Data_out => FIFO_D_out_N); FIFO_E: FIFO_data_path generic map(DATA_WIDTH => DATA_WIDTH) port map(clk => clk, reset => reset, RX => RX_E, read_pointer => read_pointer_out_E, write_pointer => write_pointer_out_E, write_en => write_en_out_E, Data_out => FIFO_D_out_E); FIFO_W: FIFO_data_path generic map(DATA_WIDTH => DATA_WIDTH) port map(clk => clk, reset => reset, RX => RX_W, read_pointer => read_pointer_out_W, write_pointer => write_pointer_out_W, write_en => write_en_out_W, Data_out => FIFO_D_out_W); FIFO_S: FIFO_data_path generic map(DATA_WIDTH => DATA_WIDTH) port map(clk => clk, reset => reset, RX => RX_S, read_pointer => read_pointer_out_S, write_pointer => write_pointer_out_S, write_en => write_en_out_S, Data_out => FIFO_D_out_S); FIFO_L: FIFO_data_path generic map(DATA_WIDTH => DATA_WIDTH) port map(clk => clk, reset => reset, RX => RX_L, read_pointer => read_pointer_out_L, write_pointer => write_pointer_out_L, write_en => write_en_out_L, Data_out => FIFO_D_out_L); end;
gpl-3.0
239566ccb3bd1be8951343c9beadb68c
0.591066
2.628534
false
false
false
false
SoCdesign/EHA
RTL/Credit_Based/Checkers/Control_Part_Checkers/LBDR_credit_based_checkers/RTL_and_Synthesis/LBDR_credit_based_with_checkers_top.vhd
1
10,433
library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.ALL; entity LBDR_credit_based_with_checkers_top is generic ( cur_addr_rst: integer := 5; Rxy_rst: integer := 60; Cx_rst: integer := 15; NoC_size: integer := 4 ); port ( empty: in std_logic; flit_type: in std_logic_vector(2 downto 0); dst_addr: in std_logic_vector(NoC_size-1 downto 0); grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic; Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic; -- LBDR outputs N1_out, E1_out, W1_out, S1_out: out std_logic; grants_out: out std_logic; Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: out std_logic; -- Checker outputs err_header_not_empty_Requests_in_onehot, err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot, err_grants_mismatch, err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_not_Req_L_in, err_dst_addr_cur_addr_Req_L_in, err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in : out std_logic ); end LBDR_credit_based_with_checkers_top; architecture behavior of LBDR_credit_based_with_checkers_top is component LBDR_credit_based_pseudo is generic ( cur_addr_rst: integer := 5; Rxy_rst: integer := 60; Cx_rst: integer := 15; NoC_size: integer := 4 ); port ( empty: in std_logic; flit_type: in std_logic_vector(2 downto 0); dst_addr: in std_logic_vector(NoC_size-1 downto 0); grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic; Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic; N1_out, E1_out, W1_out, S1_out: out std_logic; grants_out: out std_logic; Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: out std_logic ); end component; component LBDR_credit_based_checkers is generic ( cur_addr_rst: integer := 5; NoC_size: integer := 4 ); port ( empty: in std_logic; flit_type: in std_logic_vector(2 downto 0); Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic; Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic; N1_out, E1_out, W1_out, S1_out: in std_logic; grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic; grants: in std_logic; dst_addr: in std_logic_vector(NoC_size-1 downto 0); -- Checker outputs err_header_not_empty_Requests_in_onehot, err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot, err_grants_mismatch, err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_not_Req_L_in, err_dst_addr_cur_addr_Req_L_in, err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in : out std_logic ); end component; signal Req_N_in_sig, Req_E_in_sig, Req_W_in_sig, Req_S_in_sig, Req_L_in_sig: std_logic; signal N1_out_sig, E1_out_sig, W1_out_sig, S1_out_sig: std_logic; signal grants_out_sig: std_logic; begin Req_N_in <= Req_N_in_sig; Req_E_in <= Req_E_in_sig; Req_W_in <= Req_W_in_sig; Req_S_in <= Req_S_in_sig; Req_L_in <= Req_L_in_sig; N1_out <= N1_out_sig; E1_out <= E1_out_sig; W1_out <= W1_out_sig; S1_out <= S1_out_sig; grants_out <= grants_out_sig; -- LBDR instantiation LBDR_credit_based: LBDR_credit_based_pseudo generic map (cur_addr_rst => 5, Rxy_rst => 60, Cx_rst => 15, NoC_size => 4) port map ( empty=>empty, flit_type=>flit_type, dst_addr=>dst_addr, grant_N=>grant_N, grant_E=>grant_E, grant_W=>grant_W, grant_S=>grant_S, grant_L=>grant_L, Req_N_FF=>Req_N_FF, Req_E_FF=>Req_E_FF, Req_W_FF=>Req_W_FF, Req_S_FF=>Req_S_FF, Req_L_FF=>Req_L_FF, N1_out => N1_out_sig, E1_out => E1_out_sig, W1_out => W1_out_sig, S1_out => S1_out_sig, grants_out => grants_out_sig, Req_N_in=>Req_N_in_sig, Req_E_in=>Req_E_in_sig, Req_W_in=>Req_W_in_sig, Req_S_in=>Req_S_in_sig, Req_L_in=>Req_L_in_sig ); -- Checkers instantiation CHECKERS: LBDR_credit_based_checkers generic map (cur_addr_rst => 5, NoC_size => 4) port map (empty=>empty, flit_type=>flit_type, Req_N_FF=>Req_N_FF, Req_E_FF=>Req_E_FF, Req_W_FF=>Req_W_FF, Req_S_FF=>Req_S_FF, Req_L_FF=>Req_L_FF, Req_N_in=>Req_N_in_sig, Req_E_in=>Req_E_in_sig, Req_W_in=>Req_W_in_sig, Req_S_in=>Req_S_in_sig, Req_L_in=>Req_L_in_sig, N1_out => N1_out_sig, E1_out => E1_out_sig, W1_out => W1_out_sig, S1_out => S1_out_sig, grant_N => grant_N, grant_E => grant_E, grant_W => grant_W, grant_S => grant_S, grant_L => grant_L, grants => grants_out_sig, dst_addr => dst_addr, err_header_not_empty_Requests_in_onehot => err_header_not_empty_Requests_in_onehot, err_header_empty_Requests_FF_Requests_in => err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero => err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in => err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in => err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot => err_grants_onehot, err_grants_mismatch => err_grants_mismatch, err_header_tail_Requests_FF_Requests_in => err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1 => err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1 => err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1 => err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1 => err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1 => err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1 => err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1 => err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1 => err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_not_Req_L_in => err_dst_addr_cur_addr_not_Req_L_in, err_dst_addr_cur_addr_Req_L_in => err_dst_addr_cur_addr_Req_L_in, err_header_not_empty_Req_N_in => err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in => err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in => err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in => err_header_not_empty_Req_S_in ); end behavior;
gpl-3.0
ad7009f9272936be68b04c748f837de7
0.440813
3.521093
false
false
false
false
bruskajp/EE-316
Project2/Vivado_NexysBoard/project_2b/project_2b.srcs/sources_1/imports/Downloads/btn_debounce_toggle.vhd
1
2,949
---------------------------------------------------------------------------- -- btn_debounce.vhd -- Button Debouncer ---------------------------------------------------------------------------- -- Author: Sam Bobrowicz -- Copyright 2011 Digilent, Inc. -- Modified: Added toggle output ---------------------------------------------------------------------------- -- ---------------------------------------------------------------------------- -- This component is used to debounce signals generated by external push -- buttons. It is designed to independently debounce a Push button signal. -- Debouncing is done by only registering a change in a button state if -- it remains constant for 2^16 clock cycles. -- -- Port Descriptions: -- -- BTN_I - The input button signals -- CLK - Behavior is optimized for a 100 MHz clock -- BTN_O - The debounced button signals -- TOGGLE_O - Debounced toggle output ---------------------------------------------------------------------------- -- ---------------------------------------------------------------------------- -- Revision History: -- 08/08/2011(SamB): Created using Xilinx Tools 13.2 -- 10/06/2013 (CU): Converted to one button and added toggle output ---------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.std_logic_unsigned.all; entity btn_debounce_toggle is GENERIC ( CONSTANT CNTR_MAX : std_logic_vector(15 downto 0) := X"FFFF"); Port ( BTN_I : in STD_LOGIC; CLK : in STD_LOGIC; BTN_O : out STD_LOGIC; TOGGLE_O : out STD_LOGIC); end btn_debounce_toggle; architecture Behavioral of btn_debounce_toggle is --constant CNTR_MAX : std_logic_vector(15 downto 0) := X"FFFF"; signal btn_cntr : std_logic_vector(15 downto 0) := (others => '0'); signal btn_reg : std_logic := '0'; signal btn_toggle : std_logic := '1'; signal btn_sync : std_logic_vector(1 downto 0) := (others => '0'); signal btn_pulse : std_logic := '0'; begin btn_debounce_process : process (CLK) begin if (rising_edge(CLK)) then if (btn_cntr = CNTR_MAX) then btn_reg <= not(btn_reg); end if; end if; end process; btn_counter_process : process (CLK) begin if (rising_edge(CLK)) then if ((btn_reg = '1') xor (BTN_I = '1')) then if (btn_cntr = CNTR_MAX) then btn_cntr <= (others => '0'); else btn_cntr <= btn_cntr + 1; end if; else btn_cntr <= (others => '0'); end if; end if; end process; btn_toggle_process : process(CLK) begin if (rising_edge(CLK)) then btn_sync(0) <= btn_reg; btn_sync(1) <= btn_sync(0); btn_pulse <= not btn_sync(1) and btn_sync(0); if btn_pulse = '1' then btn_toggle <= not btn_toggle; end if; end if; end process; BTN_O <= btn_reg; TOGGLE_O <= btn_toggle; end Behavioral;
gpl-3.0
5c0b34c0f8f4beb013d37a20cd5b1146
0.503221
3.704774
false
false
false
false
SoCdesign/EHA
RTL/Immortal_Chip/modules_with_fault_injectors/to_be_tested/Channel_32_bit_with_dominant_checkers_shift_register.vhd
1
19,432
--Copyright (C) 2016 Siavoosh Payandeh Azad library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.std_logic_misc.all; entity router_channel is generic ( DATA_WIDTH: integer := 32; current_address : integer := 5; Rxy_rst : integer := 60; Cx_rst : integer := 15; NoC_size: integer := 4 ); port ( reset, clk: in std_logic; DCTS : in std_logic; DRTS : in std_logic; RTS : out std_logic; CTS : out std_logic; flit_type : in std_logic_vector(2 downto 0); destination_address : in std_logic_vector(NoC_size-1 downto 0); Grant_N_in , Grant_E_in , Grant_W_in , Grant_S_in , Grant_L_in : in std_logic; Req_N_in , Req_E_in , Req_W_in , Req_S_in , Req_L_in :in std_logic; -- fault injector signals fault_shift: in std_logic; fault_clk: in std_logic; fault_data_in_serial: in std_logic; fault_data_out_serial: out std_logic; Grant_N_out, Grant_E_out, Grant_W_out, Grant_S_out, Grant_L_out: out std_logic; Req_N_out , Req_E_out, Req_W_out, Req_S_out, Req_L_out:out std_logic; read_pointer_out, write_pointer_out: out std_logic_vector(3 downto 0); write_en_out :out std_logic; Xbar_sel: out std_logic_vector(4 downto 0); -- the checker output shift register shift : in std_logic; checker_clk: in std_logic; error_signal_sync: out std_logic; -- this is the or of all outputs of the shift register error_signal_async: out std_logic; -- this is the or of all outputs of the checkers shift_serial_data: out std_logic ); end router_channel; architecture behavior of router_channel is COMPONENT FIFO is generic ( DATA_WIDTH: integer := 32 ); port ( reset: in std_logic; clk: in std_logic; DRTS: in std_logic; read_en_N : in std_logic; read_en_E : in std_logic; read_en_W : in std_logic; read_en_S : in std_logic; read_en_L : in std_logic; CTS: out std_logic; empty_out: out std_logic; read_pointer_out, write_pointer_out: out std_logic_vector(3 downto 0); write_en_out :out std_logic; -- fault injector signals shift: in std_logic; fault_clk: in std_logic; data_in_serial: in std_logic; data_out_serial: out std_logic; -- Checker outputs err_write_en_write_pointer, err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full, err_read_pointer_increment, err_read_pointer_not_increment, --err_CTS_in, err_write_en, err_not_CTS_in, --err_not_write_en, err_read_en_mismatch : out std_logic ); end COMPONENT; COMPONENT Arbiter port (reset: in std_logic; clk: in std_logic; Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules DCTS: in std_logic; -- Getting the CTS signal from the input FIFO of the next router/NI (for hand-shaking) Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot) Xbar_sel : out std_logic_vector(4 downto 0); -- select lines for XBAR RTS: out std_logic; -- Valid output which is sent to the next router/NI to specify that the data on the output port is valid -- fault injector signals shift: in std_logic; fault_clk: in std_logic; data_in_serial: in std_logic; data_out_serial: out std_logic; -- Checker outputs err_state_IDLE_xbar, err_state_not_IDLE_xbar, err_state_IDLE_RTS_FF_in, err_state_not_IDLE_RTS_FF_RTS_FF_in, err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in, err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in, err_RTS_FF_not_DCTS_state_state_in, err_not_RTS_FF_state_in_next_state, err_RTS_FF_DCTS_state_in_next_state, err_not_DCTS_Grants, err_DCTS_not_RTS_FF_Grants, err_DCTS_RTS_FF_IDLE_Grants, err_DCTS_RTS_FF_not_IDLE_Grants_onehot, err_Requests_next_state_IDLE, err_IDLE_Req_L, err_Local_Req_L, err_North_Req_N, err_IDLE_Req_N, err_Local_Req_N, err_South_Req_L, err_West_Req_L, err_South_Req_N, err_East_Req_L, err_West_Req_N, err_East_Req_N, err_next_state_onehot, err_state_in_onehot, err_state_north_xbar_sel, err_state_east_xbar_sel, err_state_west_xbar_sel, err_state_south_xbar_sel : out std_logic ); end COMPONENT; COMPONENT LBDR is generic ( cur_addr_rst: integer := 5; Rxy_rst: integer := 60; Cx_rst: integer := 15; NoC_size: integer := 4 ); port (reset: in std_logic; clk: in std_logic; empty: in std_logic; flit_type: in std_logic_vector(2 downto 0); dst_addr: in std_logic_vector(NoC_size-1 downto 0); Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic; -- fault injector signals shift: in std_logic; fault_clk: in std_logic; data_in_serial: in std_logic; data_out_serial: out std_logic; -- Checker outputs --err_header_not_empty_Requests_in_onehot, err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero, err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_not_Req_L_in, err_dst_addr_cur_addr_Req_L_in, err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in : out std_logic ); end COMPONENT; COMPONENT shift_register is generic ( REG_WIDTH: integer := 8 ); port ( clk, reset : in std_logic; shift: in std_logic; data_in: in std_logic_vector(REG_WIDTH-1 downto 0); data_out_parallel: in std_logic_vector(REG_WIDTH-1 downto 0); data_out_serial: out std_logic ); end COMPONENT; -- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y signal empty: std_logic; signal combined_error_signals: std_logic_vector(58 downto 0); signal shift_parallel_data: std_logic_vector(58 downto 0); -- Signals related to Checkers -- LBDR Checkers signals signal err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero, err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_not_Req_L_in, err_dst_addr_cur_addr_Req_L_in, err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in : std_logic; -- Arbiter Checkers signals signal err_state_IDLE_xbar, err_state_not_IDLE_xbar, err_state_IDLE_RTS_FF_in, err_state_not_IDLE_RTS_FF_RTS_FF_in, err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in, err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in, err_RTS_FF_not_DCTS_state_state_in, err_not_RTS_FF_state_in_next_state, err_RTS_FF_DCTS_state_in_next_state, err_not_DCTS_Grants, err_DCTS_not_RTS_FF_Grants, err_DCTS_RTS_FF_IDLE_Grants, err_DCTS_RTS_FF_not_IDLE_Grants_onehot, err_Requests_next_state_IDLE, err_IDLE_Req_L, err_Local_Req_L, err_North_Req_N, err_IDLE_Req_N, err_Local_Req_N, err_South_Req_L, err_West_Req_L, err_South_Req_N, err_East_Req_L, err_West_Req_N, err_East_Req_N, err_next_state_onehot, err_state_in_onehot, err_state_north_xbar_sel, err_state_east_xbar_sel, err_state_west_xbar_sel, err_state_south_xbar_sel : std_logic; -- FIFO Control Part Checkers signals signal err_write_en_write_pointer, err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full, err_read_pointer_increment, err_read_pointer_not_increment, err_write_en, err_not_CTS_in, err_read_en_mismatch : std_logic; signal fault_DO_serial_FIFO_2_LBDR, fault_DO_serial_LBDR_2_Arbiter: std_logic; begin -- OR of checker outputs error_signal_sync <= OR_REDUCE(shift_parallel_data); error_signal_async <= OR_REDUCE(combined_error_signals); -- making the shift register input signal -- please keep this like this, i use this for counting the number of the signals. combined_error_signals <= err_header_empty_Requests_FF_Requests_in & err_tail_Requests_in_all_zero & err_header_tail_Requests_FF_Requests_in & err_dst_addr_cur_addr_N1 & err_dst_addr_cur_addr_not_N1 & err_dst_addr_cur_addr_E1 & err_dst_addr_cur_addr_not_E1 & err_dst_addr_cur_addr_W1 & err_dst_addr_cur_addr_not_W1 & err_dst_addr_cur_addr_S1 & err_dst_addr_cur_addr_not_S1 & err_dst_addr_cur_addr_not_Req_L_in & err_dst_addr_cur_addr_Req_L_in & err_header_not_empty_Req_N_in & err_header_not_empty_Req_E_in & err_header_not_empty_Req_W_in & err_header_not_empty_Req_S_in & err_state_IDLE_xbar & err_state_not_IDLE_xbar & err_state_IDLE_RTS_FF_in & err_state_not_IDLE_RTS_FF_RTS_FF_in & err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in & err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in & err_RTS_FF_not_DCTS_state_state_in & err_not_RTS_FF_state_in_next_state & err_RTS_FF_DCTS_state_in_next_state & err_not_DCTS_Grants & err_DCTS_not_RTS_FF_Grants & err_DCTS_RTS_FF_IDLE_Grants & err_DCTS_RTS_FF_not_IDLE_Grants_onehot & err_Requests_next_state_IDLE & err_IDLE_Req_L & err_Local_Req_L & err_North_Req_N & err_IDLE_Req_N & err_Local_Req_N & err_South_Req_L & err_West_Req_L & err_South_Req_N & err_East_Req_L & err_West_Req_N & err_East_Req_N & err_next_state_onehot & err_state_in_onehot & err_state_north_xbar_sel & err_state_east_xbar_sel & err_state_west_xbar_sel & err_state_south_xbar_sel & err_write_en_write_pointer & err_not_write_en_write_pointer & err_read_pointer_write_pointer_not_empty & err_read_pointer_write_pointer_empty & err_read_pointer_write_pointer_not_full & err_read_pointer_write_pointer_full & err_read_pointer_increment & err_read_pointer_not_increment & err_write_en & err_not_CTS_in & err_read_en_mismatch; --------------------------------------------------------------------------------------------------------------------------- FIFO_unit: FIFO generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (reset => reset, clk => clk, DRTS => DRTS, read_en_N => Grant_N_in, read_en_E =>Grant_E_in, read_en_W =>Grant_W_in, read_en_S =>Grant_S_in, read_en_L =>Grant_L_in, CTS => CTS, empty_out => empty, read_pointer_out => read_pointer_out, write_pointer_out => write_pointer_out, write_en_out => write_en_out, shift=>fault_shift, fault_clk=>fault_clk, data_in_serial=> fault_data_in_serial, data_out_serial=>fault_DO_serial_FIFO_2_LBDR, err_write_en_write_pointer => err_write_en_write_pointer, err_not_write_en_write_pointer => err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty => err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty => err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full => err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full => err_read_pointer_write_pointer_full, err_read_pointer_increment => err_read_pointer_increment, err_read_pointer_not_increment => err_read_pointer_not_increment, err_write_en => err_write_en, err_not_CTS_in => err_not_CTS_in, err_read_en_mismatch => err_read_en_mismatch ); ------------------------------------------------------------------------------------------------------------------------------ LBDR_unit: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty, flit_type => flit_type, dst_addr=> destination_address, Req_N=> Req_N_out, Req_E=>Req_E_out, Req_W=>Req_W_out, Req_S=>Req_S_out, Req_L=>Req_L_out, shift=>shift, fault_clk=>fault_clk, data_in_serial=> fault_DO_serial_FIFO_2_LBDR, data_out_serial=>fault_DO_serial_LBDR_2_Arbiter, err_header_empty_Requests_FF_Requests_in => err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero => err_tail_Requests_in_all_zero, err_header_tail_Requests_FF_Requests_in => err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1 => err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1 => err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1 => err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1 => err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1 => err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1 => err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1 => err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1 => err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_not_Req_L_in => err_dst_addr_cur_addr_not_Req_L_in, err_dst_addr_cur_addr_Req_L_in => err_dst_addr_cur_addr_Req_L_in, err_header_not_empty_Req_N_in => err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in => err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in => err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in => err_header_not_empty_Req_S_in ); ------------------------------------------------------------------------------------------------------------------------------ Arbiter_unit: Arbiter PORT MAP (reset => reset, clk => clk, Req_N => Req_N_in , Req_E => Req_E_in, Req_W => Req_W_in, Req_S => Req_S_in, Req_L => Req_L_in, DCTS => DCTS, Grant_N => Grant_N_out, Grant_E => Grant_E_out, Grant_W => Grant_W_out, Grant_S => Grant_S_out, Grant_L => Grant_L_out, Xbar_sel => Xbar_sel, RTS => RTS, shift=>shift, fault_clk=>fault_clk, data_in_serial=> fault_DO_serial_LBDR_2_Arbiter, data_out_serial=> fault_data_out_serial, err_state_IDLE_xbar => err_state_IDLE_xbar , err_state_not_IDLE_xbar => err_state_not_IDLE_xbar , err_state_IDLE_RTS_FF_in => err_state_IDLE_RTS_FF_in , err_state_not_IDLE_RTS_FF_RTS_FF_in => err_state_not_IDLE_RTS_FF_RTS_FF_in , err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in , err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in , err_RTS_FF_not_DCTS_state_state_in => err_RTS_FF_not_DCTS_state_state_in , err_not_RTS_FF_state_in_next_state => err_not_RTS_FF_state_in_next_state , err_RTS_FF_DCTS_state_in_next_state => err_RTS_FF_DCTS_state_in_next_state , err_not_DCTS_Grants => err_not_DCTS_Grants , err_DCTS_not_RTS_FF_Grants => err_DCTS_not_RTS_FF_Grants , err_DCTS_RTS_FF_IDLE_Grants => err_DCTS_RTS_FF_IDLE_Grants , err_DCTS_RTS_FF_not_IDLE_Grants_onehot => err_DCTS_RTS_FF_not_IDLE_Grants_onehot , err_Requests_next_state_IDLE => err_Requests_next_state_IDLE , err_IDLE_Req_L => err_IDLE_Req_L , err_Local_Req_L => err_Local_Req_L , err_North_Req_N => err_North_Req_N , err_IDLE_Req_N => err_IDLE_Req_N , err_Local_Req_N => err_Local_Req_N , err_South_Req_L => err_South_Req_L , err_West_Req_L => err_West_Req_L , err_South_Req_N => err_South_Req_N , err_East_Req_L => err_East_Req_L , err_West_Req_N => err_West_Req_N , err_East_Req_N => err_East_Req_N , err_next_state_onehot => err_next_state_onehot , err_state_in_onehot => err_state_in_onehot , err_state_north_xbar_sel => err_state_north_xbar_sel , err_state_east_xbar_sel => err_state_east_xbar_sel , err_state_west_xbar_sel => err_state_west_xbar_sel , err_state_south_xbar_sel => err_state_south_xbar_sel ); checker_shifter: shift_register generic map (REG_WIDTH => 59) port map ( clk => clk, reset => reset, shift => shift, data_in => combined_error_signals, data_out_parallel => shift_parallel_data, data_out_serial => shift_serial_data ); end;
gpl-3.0
cd574cc68693954279a8b7be1826c1bf
0.544
3.3042
false
false
false
false
TUM-LIS/faultify
hardware/testcases/fpu100_mul/fpga_sim/xpsLibraryPath/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/vhdl/user_logic.vhd
1
29,243
------------------------------------------------------------------------------ -- user_logic.vhd - entity/architecture pair ------------------------------------------------------------------------------ -- -- *************************************************************************** -- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** Xilinx, Inc. ** -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** -- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** -- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** -- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** -- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** -- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** -- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** -- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** -- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** -- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** -- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** -- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** -- ** FOR A PARTICULAR PURPOSE. ** -- ** ** -- *************************************************************************** -- ------------------------------------------------------------------------------ -- Filename: user_logic.vhd -- Version: 1.00.a -- Description: User logic. -- Date: Fri May 16 15:25:24 2014 (by Create and Import Peripheral Wizard) -- VHDL Standard: VHDL'93 ------------------------------------------------------------------------------ -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port: "*_i" -- device pins: "*_pin" -- ports: "- Names begin with Uppercase" -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC>" ------------------------------------------------------------------------------ -- DO NOT EDIT BELOW THIS LINE -------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library proc_common_v3_00_a; use proc_common_v3_00_a.proc_common_pkg.all; -- DO NOT EDIT ABOVE THIS LINE -------------------- --USER libraries added here ------------------------------------------------------------------------------ -- Entity section ------------------------------------------------------------------------------ -- Definition of Generics: -- C_NUM_REG -- Number of software accessible registers -- C_SLV_DWIDTH -- Slave interface data bus width -- -- Definition of Ports: -- Bus2IP_Clk -- Bus to IP clock -- Bus2IP_Resetn -- Bus to IP reset -- Bus2IP_Data -- Bus to IP data bus -- Bus2IP_BE -- Bus to IP byte enables -- Bus2IP_RdCE -- Bus to IP read chip enable -- Bus2IP_WrCE -- Bus to IP write chip enable -- IP2Bus_Data -- IP to Bus data bus -- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement -- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement -- IP2Bus_Error -- IP to Bus error response ------------------------------------------------------------------------------ entity user_logic is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- --USER generics added here -- ADD USER GENERICS ABOVE THIS LINE --------------- -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_NUM_REG : integer := 32; C_SLV_DWIDTH : integer := 32 -- DO NOT EDIT ABOVE THIS LINE --------------------- ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ --USER ports added here faultify_clk_fast : in std_logic; -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete Bus2IP_Clk : in std_logic; Bus2IP_Resetn : in std_logic; Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0); Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0); Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0); Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0); IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0); IP2Bus_RdAck : out std_logic; IP2Bus_WrAck : out std_logic; IP2Bus_Error : out std_logic -- DO NOT EDIT ABOVE THIS LINE --------------------- ); attribute MAX_FANOUT : string; attribute SIGIS : string; attribute SIGIS of Bus2IP_Clk : signal is "CLK"; attribute SIGIS of Bus2IP_Resetn : signal is "RST"; end entity user_logic; ------------------------------------------------------------------------------ -- Architecture section ------------------------------------------------------------------------------ architecture IMP of user_logic is --USER signal declarations added here, as needed for user logic component faultify_top generic ( numInj : integer; numIn : integer; numOut : integer); port ( aclk : in std_logic; arst_n : in std_logic; clk : in std_logic; clk_x32 : in std_logic; awvalid : in std_logic; awaddr : in std_logic_vector(31 downto 0); wvalid : in std_logic; wdata : in std_logic_vector(31 downto 0); arvalid : in std_logic; araddr : in std_logic_vector(31 downto 0); rvalid : out std_logic; rdata : out std_logic_vector(31 downto 0)); end component; ------------------------------------------ -- Signals for user logic slave model s/w accessible register example ------------------------------------------ signal register_write_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal register_read_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal register_write_address : std_logic_vector(C_NUM_REG-1 downto 0); signal register_read_address : std_logic_vector(C_NUM_REG-1 downto 0); signal slv_reg_write_sel : std_logic_vector(31 downto 0); signal slv_reg_read_sel : std_logic_vector(31 downto 0); signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_read_ack : std_logic; signal slv_write_ack : std_logic; signal faultify_read_valid : std_logic; signal faultify_read_address_valid : std_logic; signal faultify_read_address : std_logic_vector(31 downto 0); signal faultify_write_valid : std_logic; signal counter, divide : integer := 0; signal faultify_clk_slow_i : std_logic; begin slv_reg_write_sel <= Bus2IP_WrCE(31 downto 0); slv_reg_read_sel <= Bus2IP_RdCE(31 downto 0); slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12) or Bus2IP_WrCE(13) or Bus2IP_WrCE(14) or Bus2IP_WrCE(15) or Bus2IP_WrCE(16) or Bus2IP_WrCE(17) or Bus2IP_WrCE(18) or Bus2IP_WrCE(19) or Bus2IP_WrCE(20) or Bus2IP_WrCE(21) or Bus2IP_WrCE(22) or Bus2IP_WrCE(23) or Bus2IP_WrCE(24) or Bus2IP_WrCE(25) or Bus2IP_WrCE(26) or Bus2IP_WrCE(27) or Bus2IP_WrCE(28) or Bus2IP_WrCE(29) or Bus2IP_WrCE(30) or Bus2IP_WrCE(31); slv_read_ack <= faultify_read_valid; -- implement slave model software accessible register(s) SLAVE_REG_WRITE_PROC : process(Bus2IP_Clk) is begin if Bus2IP_Clk'event and Bus2IP_Clk = '1' then if Bus2IP_Resetn = '0' then register_write_data <= (others => '0'); register_write_address <= (others => '0'); faultify_write_valid <= '0'; else faultify_write_valid <= slv_write_ack; case slv_reg_write_sel is when "10000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(0, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "01000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(1, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00100000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(2, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00010000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(3, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00001000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(4, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000100000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(5, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000010000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(6, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000001000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(7, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000100000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(8, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000010000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(9, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000001000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(10, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000100000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(11, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000010000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(12, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000001000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(13, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000100000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(14, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000010000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(15, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000001000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(16, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000100000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(17, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000010000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(18, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000001000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(19, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000000100000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(20, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000000010000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(21, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000000001000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(22, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000000000100000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(23, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000000000010000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(24, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000000000001000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(25, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000000000000100000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(26, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000000000000010000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(27, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000000000000001000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(28, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000000000000000100" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(29, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000000000000000010" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(30, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "00000000000000000000000000000001" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if (Bus2IP_BE(byte_index) = '1') then register_write_address <= std_logic_vector(to_unsigned(31, 32)); register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when others => null; end case; end if; end if; end process SLAVE_REG_WRITE_PROC; -- implement slave model software accessible register(s) read mux SLAVE_REG_READ_PROC : process(slv_reg_read_sel, faultify_read_valid) is begin faultify_read_address_valid <= '1'; case slv_reg_read_sel is when "10000000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(0, 32)); when "01000000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(1, 32)); when "00100000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(2, 32)); when "00010000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(3, 32)); when "00001000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(4, 32)); when "00000100000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(5, 32)); when "00000010000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(6, 32)); when "00000001000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(7, 32)); when "00000000100000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(8, 32)); when "00000000010000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(9, 32)); when "00000000001000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(10, 32)); when "00000000000100000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(11, 32)); when "00000000000010000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(12, 32)); when "00000000000001000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(13, 32)); when "00000000000000100000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(14, 32)); when "00000000000000010000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(15, 32)); when "00000000000000001000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(16, 32)); when "00000000000000000100000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(17, 32)); when "00000000000000000010000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(18, 32)); when "00000000000000000001000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(19, 32)); when "00000000000000000000100000000000" => faultify_read_address <= std_logic_vector(to_unsigned(20, 32)); when "00000000000000000000010000000000" => faultify_read_address <= std_logic_vector(to_unsigned(21, 32)); when "00000000000000000000001000000000" => faultify_read_address <= std_logic_vector(to_unsigned(22, 32)); when "00000000000000000000000100000000" => faultify_read_address <= std_logic_vector(to_unsigned(23, 32)); when "00000000000000000000000010000000" => faultify_read_address <= std_logic_vector(to_unsigned(24, 32)); when "00000000000000000000000001000000" => faultify_read_address <= std_logic_vector(to_unsigned(25, 32)); when "00000000000000000000000000100000" => faultify_read_address <= std_logic_vector(to_unsigned(26, 32)); when "00000000000000000000000000010000" => faultify_read_address <= std_logic_vector(to_unsigned(27, 32)); when "00000000000000000000000000001000" => faultify_read_address <= std_logic_vector(to_unsigned(28, 32)); when "00000000000000000000000000000100" => faultify_read_address <= std_logic_vector(to_unsigned(29, 32)); when "00000000000000000000000000000010" => faultify_read_address <= std_logic_vector(to_unsigned(30, 32)); when "00000000000000000000000000000001" => faultify_read_address <= std_logic_vector(to_unsigned(31, 32)); when others => faultify_read_address <= (others => '0'); faultify_read_address_valid <= '0'; end case; end process SLAVE_REG_READ_PROC; ------------------------------------------ -- Example code to drive IP to Bus signals ------------------------------------------ IP2Bus_Data <= register_read_data when faultify_read_valid = '1' else (others => '0'); IP2Bus_WrAck <= slv_write_ack; IP2Bus_RdAck <= slv_read_ack; IP2Bus_Error <= '0'; ----------------------------------------------------------------------------- -- clock divider 32 -> 1 ----------------------------------------------------------------------------- divide <= 32; process(Bus2IP_Clk, Bus2IP_Resetn) begin if Bus2IP_Resetn = '0' then counter <= 0; faultify_clk_slow_i <= '0'; elsif(rising_edge(Bus2IP_Clk)) then if(counter < divide/2-1) then counter <= counter + 1; faultify_clk_slow_i <= '0'; elsif(counter < divide-1) then counter <= counter + 1; faultify_clk_slow_i <= '1'; else faultify_clk_slow_i <= '0'; counter <= 0; end if; end if; end process; faultify_top_1 : faultify_top generic map ( numInj => 142, numIn => 70, numOut => 41) port map ( aclk => Bus2IP_Clk, arst_n => Bus2IP_Resetn, clk => faultify_clk_slow_i, clk_x32 => Bus2IP_Clk, awvalid => faultify_write_valid, awaddr => register_write_address, wvalid => faultify_write_valid, wdata => register_write_data, arvalid => faultify_read_address_valid, araddr => faultify_read_address, rvalid => faultify_read_valid, rdata => register_read_data); end IMP;
gpl-2.0
3f9fda6a61f07fb7b041a7fc09f50b26
0.539309
4.022974
false
false
false
false
JarrettR/FPGA-Cryptoparty
FPGA/hdl/sim_pbkdf2.vhd
1
3,445
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 12/26/2016 11:44:06 PM -- Design Name: -- Module Name: sim_pbkdf2 - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- Takes about 1400us to complete -- signal 'i' will be 0x157002 -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use work.sha1_pkg.all; entity sim_pbkdf2 is end sim_pbkdf2; architecture Behavioral of sim_pbkdf2 is component pbkdf2_main is port( clk_i : in std_ulogic; rst_i : in std_ulogic; load_i : in std_ulogic; mk_i : in mk_data; ssid_i : in ssid_data; dat_o : out w_pmk; valid_o : out std_ulogic ); end component; signal valid : std_ulogic; signal load : std_ulogic := '0'; signal clk_i : std_ulogic := '0'; signal rst_i : std_ulogic := '0'; signal mk : mk_data; signal ssid : ssid_data; signal dat : w_pmk; signal i: integer range 0 to 65535; constant clock_period : time := 1 ns; begin pbkdf2: pbkdf2_main port map (clk_i,rst_i, load, mk, ssid, dat, valid); stim_proc: process begin rst_i <= '0'; i <= 0; load <= '0'; for x in 0 to 35 loop ssid(x) <= X"00"; end loop; --linksys --6c 69 6e 6b 73 79 73 ssid(0) <= X"6C"; ssid(1) <= X"69"; ssid(2) <= X"6E"; ssid(3) <= X"6B"; ssid(4) <= X"73"; ssid(5) <= X"79"; ssid(6) <= X"73"; --dictionary --64 69 63 74 69 6f 6e 61 72 79 for x in 0 to 9 loop mk(x) <= X"00"; end loop; mk(0) <= X"64"; mk(1) <= X"69"; mk(2) <= X"63"; mk(3) <= X"74"; mk(4) <= X"69"; mk(5) <= X"6F"; mk(6) <= X"6E"; mk(7) <= X"61"; mk(8) <= X"72"; mk(9) <= X"79"; wait until rising_edge(clk_i); rst_i <= '1'; wait until rising_edge(clk_i); rst_i <= '0'; wait until rising_edge(clk_i); load <= '1'; wait until rising_edge(clk_i); load <= '0'; wait until rising_edge(clk_i); while valid = '0' loop i <= i + 1; wait until rising_edge(clk_i); end loop; -- 5df920b5481ed70538dd5fd02423d7e2522205feeebb974cad08a52b5613ede2 assert not ( dat(0) = X"5df920b5" and dat(0) = X"481ed705" and dat(0) = X"38dd5fd0" and dat(0) = X"2423d7e2" and dat(0) = X"522205fe" and dat(0) = X"eebb974c" and dat(0) = X"ad08a52b" and dat(0) = X"5613ede2" ) report "Data output is wrong." severity ERROR; wait; end process; --ssid_dat <= ssid_data(handshake_dat(0 to 35)); --36 clock_process: process begin clk_i <= '0'; wait for clock_period/2; clk_i <= '1'; wait for clock_period/2; end process; end Behavioral;
gpl-3.0
2e178908a3e69b81ce7a798a91a86676
0.445283
3.338178
false
false
false
false
SoCdesign/EHA
RTL/Hand_Shaking/Hand_Shaking_FC/NI.vhd
1
2,805
--Copyright (C) 2016 Siavoosh Payandeh Azad library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity NI is generic ( DATA_WIDTH: integer := 32; NI_DEPTH: integer:=16 ); port ( reset: in std_logic; clk: in std_logic; RX1: in std_logic_vector(DATA_WIDTH-1 downto 0); TX1: out std_logic_vector(DATA_WIDTH-1 downto 0); DRTS1, DCTS1: in std_logic; RTS1,CTS1: out std_logic; RX2: in std_logic_vector(DATA_WIDTH-1 downto 0); TX2: out std_logic_vector(DATA_WIDTH-1 downto 0); DRTS2, DCTS2: in std_logic; RTS2,CTS2: out std_logic ); end NI; architecture behavior of NI is component NI_channel is generic ( DATA_WIDTH: integer := 32; NI_DEPTH: integer:=16 ); port ( reset: in std_logic; clk: in std_logic; RX: in std_logic_vector(DATA_WIDTH-1 downto 0); TX: out std_logic_vector(DATA_WIDTH-1 downto 0); DRTS, DCTS: in std_logic; RTS,CTS: out std_logic ); end component; begin -- -- PE router -- -- ---- ---------------------------------- -- -- -- RX |<---------| TX1 RX1|<---- | TX_L_R_? -- DRTS|<---------| RTS1 DRTS1|<---- | RTS_L_R_? -- CTS |--------->| DCTS1 CTS1|----> | DCTS_L_R_? -- | | NI | | -- TX|--------->| RX2 TX2|----> | RX_L_R_? -- RTS|--------->| DRTS2 RTS2|----> | DRTS_L_R_? -- DCTS|<---------| CTS2 DCTS2|<---- | CTS_L_R_? -- -- ---- ---------------------------------- -- -- -- circular buffer structure -- <--- WriteP -- --------------------------------- -- | 3 | 2 | 1 | 0 | -- --------------------------------- -- <--- readP Channel_1: NI_channel generic map(DATA_WIDTH => DATA_WIDTH, NI_DEPTH => NI_DEPTH) port map(reset=>reset, clk =>clk, RX => RX1, TX => TX1, DRTS=>DRTS1, DCTS=>DCTS1, RTS=>RTS1,CTS=>CTS1); Channel_2: NI_channel generic map(DATA_WIDTH => DATA_WIDTH, NI_DEPTH => NI_DEPTH) port map(reset=>reset, clk =>clk, RX => RX2, TX => TX2, DRTS=>DRTS2, DCTS=>DCTS2, RTS=>RTS2,CTS=>CTS2); end;
gpl-3.0
c131be9be04100d143b8108ac02b8398
0.379679
3.950704
false
false
false
false
bruskajp/EE-316
Project1/system_controller.vhd
1
10,462
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity system_controller is port ( clk_50 : in std_logic; reset_key : in std_logic; op_prog_mode : out std_logic; sram_addr : out std_logic_vector (17 downto 0); sram_dq : inout std_logic_vector (15 downto 0); sram_we_n : out std_logic; sram_oe_n : out std_logic; sram_ub_n : out std_logic; sram_lb_n : out std_logic; sram_ce_n : out std_logic; row_sel : in std_logic_vector (4 downto 0); col_sel : out std_logic_vector(3 downto 0); lcd_data_out : out std_logic_vector(7 downto 0); lcd_enable_out : out std_logic; lcd_select_out : out std_logic; hex0, hex1, hex2, hex3, hex4, hex5 : out std_logic_vector (7 downto 0) ); end system_controller; architecture behavior of system_controller is -- keypad input signal keypress : std_logic_vector (7 downto 0); signal keypad_addr : std_logic_vector (7 downto 0); signal keypad_data : std_logic_vector (15 downto 0); signal key_out : std_logic_vector(7 downto 0); signal keypress_out : std_logic; -- unneeded -- keypad debouncer signal clk_cnt : integer range 0 to 500000; signal buf_f_b : std_logic; signal buf_reset_key : std_logic; signal flag_reset : std_logic; signal buf_keypress : std_logic_vector (7 downto 0); signal flag_keypress : std_logic_vector (7 downto 0); -- keypress to single pulse signal deb_keypress :std_logic_vector (7 downto 0); signal buf_deb_keypress : std_logic_vector (7 downto 0); -- state control for initialization, operation, and programming mode type state_type is (init, op_mode, prog_mode); signal state : state_type := init; -- internal state data signal buf_addr_data : std_logic; signal buf_clk_en : std_logic := '0'; signal counter_reset : std_logic; signal counter_out : std_logic_vector (7 downto 0); signal counter2_out : std_logic_vector (7 downto 0); signal buf_op_prog_mode : std_logic; -- rom control signal rom_addr : std_logic_vector (7 downto 0); signal rom_out : std_logic_vector (15 downto 0); -- sram controller signal sram_cntlr_data_in : std_logic_vector (15 downto 0); signal sram_cntlr_addr : std_logic_vector (17 downto 0); signal sram_cntlr_r_w : std_logic; signal sram_cntlr_r_w_en : std_logic := '0'; signal sram_cntlr_r_w_stat : std_logic; signal sram_cntlr_data_out : std_logic_vector (15 downto 0); component input_handler is generic ( COUNT_MAX : integer := 500000 ); port ( row_sel : in std_logic_vector(4 downto 0); clk : in std_logic; reset : in std_logic; key_out : out std_logic_vector(7 downto 0); col_sel : out std_logic_vector(3 downto 0); keypress_out : out std_logic ); end component; component counter is generic ( constant cnt_max : integer := 50000000 -- fix this value ); port ( iClk : in std_logic; iReset : in std_logic; is_forward : in std_logic; is_enabled : in std_logic; output_data : out std_logic_vector(7 downto 0) ); end component; component rom is port ( address : in std_logic_vector (7 DOWNTO 0); clock : in std_logic; q : out std_logic_vector (15 DOWNTO 0) ); end component; component sram_controller is port ( r_w : in std_logic; clk : in std_logic; addr : in std_logic_vector (17 downto 0); r_w_en : in std_logic; data_in : in std_logic_vector (15 downto 0); data_out : out std_logic_vector (15 downto 0); r_w_status : out std_logic; sram_addr : out std_logic_vector (17 downto 0); sram_i_o : inout std_logic_vector (15 downto 0); sram_n_we : out std_logic; sram_n_oe : out std_logic; sram_n_ce : out std_logic; sram_n_ub : out std_logic; sram_n_lb : out std_logic ); end component; component display_driver is port ( keycode : in std_logic_vector(7 downto 0); sram_address : in std_logic_vector(7 downto 0); sram_data : in std_logic_vector(15 downto 0); write_address : in std_logic; is_programming : in std_logic; clk : in std_logic; address : out std_logic_vector(7 downto 0); data : out std_logic_vector(15 downto 0) ); end component; component seven_seg_driver is port( data : in std_logic_vector(15 downto 0); address : in std_logic_vector(7 downto 0); hex0 : out std_logic_vector(7 downto 0); hex1 : out std_logic_vector(7 downto 0); hex2 : out std_logic_vector(7 downto 0); hex3 : out std_logic_vector(7 downto 0); hex4 : out std_logic_vector(7 downto 0); hex5 : out std_logic_vector(7 downto 0) ); end component; component lcd_driver is generic ( constant cnt_max : integer := 83333--333 ); port ( clk : in std_logic; reset : in std_logic; sys_fb : in std_logic; sys_en : in std_logic; sys_prog : in std_logic; is_addr : in std_logic; address : in std_logic_vector(7 downto 0); data : in std_logic_vector(15 downto 0); data_out : out std_logic_vector(7 downto 0); enable_out : out std_logic; mode_select_out : out std_logic ); end component; begin Inst_input_handler: input_handler generic map (COUNT_MAX => 500000) port map ( row_sel => row_sel, clk => clk_50, reset => flag_reset, key_out => keypress, col_sel => col_sel, keypress_out => keypress_out ); Inst_counter: counter generic map (cnt_max => 50000000) port map ( iClk => clk_50, iReset => counter_reset, is_forward => not buf_f_b, is_enabled => buf_clk_en, output_data => counter_out ); Inst_counter2: counter generic map (cnt_max => 5000) port map ( iClk => clk_50, iReset => counter_reset, is_forward => not buf_f_b, is_enabled => buf_clk_en, output_data => counter2_out ); Inst_rom: rom port map ( address => rom_addr, clock => clk_50, q => rom_out ); Inst_sram_controller: sram_controller port map ( r_w => sram_cntlr_r_w, clk => clk_50, addr => sram_cntlr_addr, r_w_en => sram_cntlr_r_w_en, data_in => sram_cntlr_data_in, data_out => sram_cntlr_data_out, r_w_status => sram_cntlr_r_w_stat, sram_addr => sram_addr, sram_i_o => sram_dq, sram_n_we => sram_we_n, sram_n_oe => sram_oe_n, sram_n_ce => sram_ce_n, sram_n_ub => sram_ub_n, sram_n_lb => sram_lb_n ); Inst_display_driver: display_driver port map ( keycode => flag_keypress, sram_address => sram_cntlr_addr(7 downto 0), sram_data => sram_cntlr_data_out, write_address => buf_addr_data, is_programming => buf_op_prog_mode, clk => clk_50, address => keypad_addr, data => keypad_data ); Inst_seven_seg_driver: seven_seg_driver port map( data => keypad_data, address => keypad_addr, hex0 => hex0, hex1 => hex1, hex2 => hex2, hex3 => hex3, hex4 => hex4, hex5 => hex5 ); Inst_lcd_driver: lcd_driver generic map ( cnt_max => 83333) port map( clk => clk_50, reset => not reset_key, sys_fb => not buf_f_b, sys_en => buf_clk_en, sys_prog => buf_op_prog_mode, is_addr => buf_addr_data, address => keypad_addr, data => keypad_data, data_out => lcd_data_out, enable_out => lcd_enable_out, mode_select_out => lcd_select_out ); -- keypad debouncer process(clk_50) begin if rising_edge(clk_50) then if clk_cnt = 100000 then clk_cnt <= 0; buf_keypress <= keypress; if buf_keypress = X"FF" and keypress /= X"FF" then deb_keypress <= keypress; else deb_keypress <= X"FF"; end if; else clk_cnt <= clk_cnt + 1; end if; end if; end process; -- keypress to single pulse process (clk_50) begin if rising_edge(clk_50) then buf_deb_keypress <= deb_keypress; if buf_deb_keypress = X"FF" and deb_keypress /= X"FF" then flag_keypress <= deb_keypress; else flag_keypress <= X"FF"; end if; end if; end process; -- state control for initialization, operation, and programming mode process (clk_50) begin if rising_edge(clk_50) then case state is when init => -- initialization mode counter_reset <= '0'; if counter2_out = X"FF" then state <= op_mode; buf_f_b <= '0'; buf_clk_en <= '0'; buf_addr_data <= '0'; counter_reset <= '1'; else buf_f_b <= '0'; buf_clk_en <= not buf_clk_en; sram_cntlr_r_w <= '1'; sram_cntlr_r_w_en <= not sram_cntlr_r_w_en; sram_cntlr_addr <= "0000000000" & counter2_out; rom_addr <= counter2_out; sram_cntlr_data_in <= rom_out; end if; when op_mode => -- operation mode op_prog_mode <= '0'; buf_op_prog_mode <= '0'; if flag_keypress = X"F2" then -- L buf_f_b <= not buf_f_b; elsif flag_keypress = X"F1" then -- H buf_clk_en <= not buf_clk_en; elsif flag_keypress = X"F0" then -- Shift state <= prog_mode; sram_cntlr_r_w_en <= '0'; elsif reset_key = '0' then state <= init; counter_reset <= '1'; else end if; sram_cntlr_r_w <= '0'; sram_cntlr_r_w_en <= not sram_cntlr_r_w_en; sram_cntlr_addr <= "0000000000" & counter_out; --rom_addr <= counter_out; -- DEBUGGING CODE counter_reset <= '0'; when prog_mode => -- programming mode op_prog_mode <= '1'; buf_op_prog_mode <= '1'; if flag_keypress = X"F2" and sram_cntlr_r_w_stat = '0' then -- L sram_cntlr_r_w_en <= '1'; elsif flag_keypress = X"F1" then -- H buf_addr_data <= not buf_addr_data; elsif flag_keypress = X"F0" then -- Shift state <= op_mode; counter_reset <= '1'; elsif reset_key = '0' then state <= init; counter_reset <= '1'; else sram_cntlr_r_w_en <= '0'; end if; buf_clk_en <= '0'; sram_cntlr_r_w <= '1'; sram_cntlr_addr <= "0000000000" & keypad_addr; sram_cntlr_data_in <= keypad_data; end case; end if; end process; end behavior;
gpl-3.0
229ba517a40badde8d0640cca1e815a7
0.58096
2.753883
false
false
false
false
SoCdesign/EHA
RTL/Credit_Based/Checkers/Control_Part_Checkers/outdated/FIFO_one_hot_credit_based_control_part_checkers/RTL_and_Synthesis/FIFO_one_hot_credit_based_control_part_pseudo.vhd
1
4,502
--Copyright (C) 2016 Siavoosh Payandeh Azad library ieee; use ieee.std_logic_1164.all; --use IEEE.STD_LOGIC_ARITH.ALL; --use IEEE.STD_LOGIC_UNSIGNED.ALL; entity FIFO_credit_based_control_part_pseudo is port ( valid_in: in std_logic; read_en_N : in std_logic; read_en_E : in std_logic; read_en_W : in std_logic; read_en_S : in std_logic; read_en_L : in std_logic; read_pointer: in std_logic_vector(3 downto 0); write_pointer: in std_logic_vector(3 downto 0); credit_out: out std_logic; empty_out: out std_logic; full_out: out std_logic; read_pointer_in: out std_logic_vector(3 downto 0); write_pointer_in: out std_logic_vector(3 downto 0); read_en_out: out std_logic; write_en_out: out std_logic ); end FIFO_credit_based_control_part_pseudo; architecture behavior of FIFO_credit_based_control_part_pseudo is signal full, empty: std_logic; signal read_en, write_en: std_logic; begin -------------------------------------------------------------------------------------------- -- block diagram of the FIFO! -------------------------------------------------------------------------------------------- -- circular buffer structure -- <--- WriteP -- --------------------------------- -- | 3 | 2 | 1 | 0 | -- --------------------------------- -- <--- readP -------------------------------------------------------------------------------------------- --process (clk, reset)begin -- if reset = '0' then -- read_pointer <= "0001"; -- write_pointer <= "0001"; -- FIFO_MEM_1 <= (others=>'0'); -- FIFO_MEM_2 <= (others=>'0'); -- FIFO_MEM_3 <= (others=>'0'); -- FIFO_MEM_4 <= (others=>'0'); -- credit_out <= '0'; -- elsif clk'event and clk = '1' then -- write_pointer <= write_pointer_in; -- read_pointer <= read_pointer_in; -- credit_out <= '0'; -- if write_en = '1' then -- --write into the memory -- FIFO_MEM_1 <= FIFO_MEM_1_in; -- FIFO_MEM_2 <= FIFO_MEM_2_in; -- FIFO_MEM_3 <= FIFO_MEM_3_in; -- FIFO_MEM_4 <= FIFO_MEM_4_in; -- end if; -- if read_en = '1' then -- credit_out <= '1'; -- end if; -- end if; -- end process; -- Since generating credit_out is part of the control part and the process with clk and reset is already -- removed, I am not sure whether it is correct to create another separate process and check read_en in -- it and based on that generate credit_out or not, something like the following: process (read_en) begin credit_out <= '0'; if read_en = '1' then credit_out <= '1'; else credit_out <= '0'; end if; end process; -- anything below here is pure combinational -- combinatorial part read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty; empty_out <= empty; read_en_out <= read_en; write_en_out <= write_en; full_out <= full; process(write_en, write_pointer)begin if write_en = '1'then write_pointer_in <= write_pointer(2 downto 0)&write_pointer(3); else write_pointer_in <= write_pointer; end if; end process; process(read_en, empty, read_pointer)begin if (read_en = '1' and empty = '0') then read_pointer_in <= read_pointer(2 downto 0)&read_pointer(3); else read_pointer_in <= read_pointer; end if; end process; process(full, valid_in) begin if valid_in = '1' and full ='0' then write_en <= '1'; else write_en <= '0'; end if; end process; process(write_pointer, read_pointer) begin if read_pointer = write_pointer then empty <= '1'; else empty <= '0'; end if; -- if write_pointer = read_pointer>>1 then if write_pointer = read_pointer(0)&read_pointer(3 downto 1) then full <= '1'; else full <= '0'; end if; end process; end;
gpl-3.0
7cf80c0e78d8acf3e1db3f146031cabb
0.469569
3.847863
false
false
false
false
bruskajp/EE-316
Project4/Vivado_NexysBoard/craddockEE316/craddockEE316.srcs/sources_1/imports/testFolder/UART.vhd
1
12,579
---- UART code taken from http://www.bealto.com/fpga-uart.html -- -- Eric Bainville -- -- Mar 2013 --library IEEE; --use IEEE.STD_LOGIC_1164.ALL; --use IEEE.STD_LOGIC_UNSIGNED.ALL; --library work; --use work.math_real.all; --entity basic_uart is -- generic ( -- DIVISOR: natural := 54 -- DIVISOR = 100,000,000 / (16 x BAUD_RATE) -- -- 2400 -> 2604 -- -- 9600 -> 651 -- -- 115200 -> 54 -- -- 1562500 -> 4 -- -- 2083333 -> 3 -- ); -- port ( -- clk: in std_logic; -- clock -- reset: in std_logic; -- reset -- -- Client interface -- rx_data: out std_logic_vector(7 downto 0); -- received byte -- rx_enable: out std_logic; -- validates received byte (1 system clock spike) -- tx_data: in std_logic_vector(7 downto 0); -- byte to send -- tx_enable: in std_logic; -- validates byte to send if tx_ready is '1' -- tx_ready: out std_logic; -- if '1', we can send a new byte, otherwise we won't take it -- -- Physical interface -- rx: in std_logic; -- tx: out std_logic -- ); --end basic_uart; --architecture Behavioral of basic_uart is -- constant COUNTER_BITS : natural := integer(ceil(log(2,real(DIVISOR)))); -- type fsm_state_t is (idle, active); -- common to both RX and TX FSM -- type rx_state_t is -- record -- fsm_state: fsm_state_t; -- FSM state -- counter: std_logic_vector(3 downto 0); -- tick count -- bits: std_logic_vector(7 downto 0); -- received bits -- nbits: std_logic_vector(3 downto 0); -- number of received bits (includes start bit) -- enable: std_logic; -- signal we received a new byte -- end record; -- type tx_state_t is -- record -- fsm_state: fsm_state_t; -- FSM state -- counter: std_logic_vector(3 downto 0); -- tick count -- bits: std_logic_vector(8 downto 0); -- bits to emit, includes start bit -- nbits: std_logic_vector(3 downto 0); -- number of bits left to send -- ready: std_logic; -- signal we are accepting a new byte -- end record; -- signal rx_state,rx_state_next: rx_state_t; -- signal tx_state,tx_state_next: tx_state_t; -- signal sample: std_logic; -- 1 clk spike at 16x baud rate -- signal sample_counter: std_logic_vector(COUNTER_BITS-1 downto 0); -- should fit values in 0..DIVISOR-1 --begin -- -- sample signal at 16x baud rate, 1 CLK spikes -- sample_process: process (clk,reset) is -- begin -- if reset = '1' then -- sample_counter <= (others => '0'); -- sample <= '0'; -- elsif rising_edge(clk) then -- if sample_counter = DIVISOR-1 then -- sample <= '1'; -- sample_counter <= (others => '0'); -- else -- sample <= '0'; -- sample_counter <= sample_counter + 1; -- end if; -- end if; -- end process; -- -- RX, TX state registers update at each CLK, and RESET -- reg_process: process (clk,reset) is -- begin -- if reset = '1' then -- rx_state.fsm_state <= idle; -- rx_state.bits <= (others => '0'); -- rx_state.nbits <= (others => '0'); -- rx_state.enable <= '0'; -- tx_state.fsm_state <= idle; -- tx_state.bits <= (others => '1'); -- tx_state.nbits <= (others => '0'); -- tx_state.ready <= '1'; -- elsif rising_edge(clk) then -- rx_state <= rx_state_next; -- tx_state <= tx_state_next; -- end if; -- end process; -- -- RX FSM -- rx_process: process (rx_state,sample,rx) is -- begin -- case rx_state.fsm_state is -- when idle => -- rx_state_next.counter <= (others => '0'); -- rx_state_next.bits <= (others => '0'); -- rx_state_next.nbits <= (others => '0'); -- rx_state_next.enable <= '0'; -- if rx = '0' then -- -- start a new byte -- rx_state_next.fsm_state <= active; -- else -- -- keep idle -- rx_state_next.fsm_state <= idle; -- end if; -- when active => -- rx_state_next <= rx_state; -- if sample = '1' then -- if rx_state.counter = 8 then -- -- sample next RX bit (at the middle of the counter cycle) -- if rx_state.nbits = 9 then -- rx_state_next.fsm_state <= idle; -- back to idle state to wait for next start bit -- rx_state_next.enable <= rx; -- OK if stop bit is '1' -- else -- rx_state_next.bits <= rx & rx_state.bits(7 downto 1); -- rx_state_next.nbits <= rx_state.nbits + 1; -- end if; -- end if; -- rx_state_next.counter <= rx_state.counter + 1; -- end if; -- end case; -- end process; -- -- RX output -- rx_output: process (rx_state) is -- begin -- rx_enable <= rx_state.enable; -- rx_data <= rx_state.bits; -- end process; -- -- TX FSM -- tx_process: process (tx_state,sample,tx_enable,tx_data) is -- begin -- case tx_state.fsm_state is -- when idle => -- if tx_enable = '1' then -- -- start a new bit -- tx_state_next.bits <= tx_data & '0'; -- data & start -- tx_state_next.nbits <= "0000" + 10; -- send 10 bits (includes '1' stop bit) -- tx_state_next.counter <= (others => '0'); -- tx_state_next.fsm_state <= active; -- tx_state_next.ready <= '0'; -- else -- -- keep idle -- tx_state_next.bits <= (others => '1'); -- tx_state_next.nbits <= (others => '0'); -- tx_state_next.counter <= (others => '0'); -- tx_state_next.fsm_state <= idle; -- tx_state_next.ready <= '1'; -- end if; -- when active => -- tx_state_next <= tx_state; -- if sample = '1' then -- if tx_state.counter = 15 then -- -- send next bit -- if tx_state.nbits = 0 then -- -- turn idle -- tx_state_next.bits <= (others => '1'); -- tx_state_next.nbits <= (others => '0'); -- tx_state_next.counter <= (others => '0'); -- tx_state_next.fsm_state <= idle; -- tx_state_next.ready <= '1'; -- else -- tx_state_next.bits <= '1' & tx_state.bits(8 downto 1); -- tx_state_next.nbits <= tx_state.nbits - 1; -- end if; -- end if; -- tx_state_next.counter <= tx_state.counter + 1; -- end if; -- end case; -- end process; -- -- TX output -- tx_output: process (tx_state) is -- begin -- tx_ready <= tx_state.ready; -- tx <= tx_state.bits(0); -- end process; --end Behavioral; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity uart is port ( reset :in std_logic; txclk :in std_logic; ld_tx_data :in std_logic; tx_data :in std_logic_vector (7 downto 0); tx_enable :in std_logic; selCheck :in std_logic_vector(1 downto 0); tx_out :out std_logic; tx_empty :out std_logic; rxclk :in std_logic; uld_rx_data :in std_logic; rx_data :out std_logic_vector (7 downto 0); rx_enable :in std_logic; rx_in :in std_logic; rx_empty :out std_logic ); end entity; architecture rtl of uart is -- Internal Variables signal tx_reg :std_logic_vector (7 downto 0); signal tx_over_run :std_logic; signal tx_cnt :std_logic_vector (3 downto 0); signal rx_reg :std_logic_vector (7 downto 0); signal rx_sample_cnt :std_logic_vector (3 downto 0); signal rx_cnt :std_logic_vector (3 downto 0); signal rx_frame_err :std_logic; signal rx_over_run :std_logic; signal rx_d1 :std_logic; signal rx_d2 :std_logic; signal rx_busy :std_logic; signal rx_is_empty :std_logic; signal tx_is_empty :std_logic; begin -- UART RX Logic process (rxclk, reset,selCheck) begin if (reset = '1') then rx_reg <= (others=>'0'); rx_data <= (others=>'0'); rx_sample_cnt <= (others=>'0'); rx_cnt <= (others=>'0'); rx_frame_err <= '0'; rx_over_run <= '0'; rx_is_empty <= '1'; rx_d1 <= '1'; rx_d2 <= '1'; rx_busy <= '0'; elsif (rising_edge(rxclk)) then -- Synchronize the asynch signal rx_d1 <= rx_in; rx_d2 <= rx_d1; -- Uload the rx data if (uld_rx_data = '1') then rx_data <= rx_reg; rx_is_empty <= '1'; end if; if uld_rx_data = '1' and selCheck /= "00" and rx_is_empty = '1' then rx_data <= "00000000"; end if; -- Receive data only when rx is enabled if (rx_enable = '1') then -- Check if just received start of frame if (rx_busy = '0' and rx_d2 = '0') then rx_busy <= '1'; rx_sample_cnt <= X"1"; rx_cnt <= X"0"; end if; -- Start of frame detected, Proceed with rest of data if (rx_busy = '1') then rx_sample_cnt <= rx_sample_cnt + 1; -- Logic to sample at middle of data if (rx_sample_cnt = 7) then if ((rx_d2 = '1') and (rx_cnt = 0)) then rx_busy <= '0'; else rx_cnt <= rx_cnt + 1; -- Start storing the rx data if (rx_cnt > 0 and rx_cnt < 9) then rx_reg(conv_integer(rx_cnt) - 1) <= rx_d2; end if; if (rx_cnt = 9) then rx_busy <= '0'; -- Check if End of frame received correctly if (rx_d2 = '0') then rx_frame_err <= '1'; else rx_is_empty <= '0'; rx_frame_err <= '0'; -- Check if last rx data was not unloaded, if (rx_is_empty = '1') then rx_over_run <= '0'; else rx_over_run <= '1'; end if; end if; end if; end if; end if; end if; end if; if (rx_enable = '0') then rx_busy <= '0'; end if; end if; end process; rx_empty <= rx_is_empty; -- UART TX Logic process (txclk, reset) begin if (reset = '1') then tx_reg <= (others=>'0'); tx_is_empty <= '1'; tx_over_run <= '0'; tx_out <= '0'; tx_cnt <= (others=>'0'); elsif (rising_edge(txclk)) then if (ld_tx_data = '1') then if (tx_is_empty = '0') then tx_over_run <= '0'; else tx_reg <= tx_data; tx_is_empty <= '0'; end if; end if; if (tx_enable = '1' and tx_is_empty = '0') then tx_cnt <= tx_cnt + 1; if (tx_cnt = 0) then tx_out <= '0'; end if; if (tx_cnt > 0 and tx_cnt < 9) then tx_out <= tx_reg(conv_integer(tx_cnt) -1); end if; if (tx_cnt = 9) then tx_out <= '1'; tx_cnt <= X"0"; tx_is_empty <= '1'; end if; end if; if (tx_enable = '0') then tx_cnt <= X"0"; end if; end if; end process; -- process(uld_rx_data) -- begin -- if uld_rx_data = '1' and selCheck /= "00" and rx_is_empty = '1' then -- rx_data <= "00000000"; -- end if; -- end process; -- tx_empty <= tx_is_empty; end architecture;
gpl-3.0
e7c55def8a97dc1a41a4e2e423c8e1bb
0.452103
3.4672
false
false
false
false
bruskajp/EE-316
Project5/game_logic_2.vhd
1
21,652
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 04/05/2017 02:01:44 PM -- Design Name: -- Module Name: game_logic - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity game_logic is port( clk : in STD_LOGIC; usb_bt_clk : in STD_LOGIC; save_button_input : in STD_LOGIC; keyboard_input : in STD_LOGIC_VECTOR(7 downto 0); x_pos_input : in STD_LOGIC_VECTOR(7 downto 0); y_pos_input : in STD_LOGIC_VECTOR(7 downto 0); usb_bt_input : in STD_LOGIC_VECTOR(7 downto 0); reset_output : out STD_LOGIC; screen_size_output : out STD_LOGIC; pen_width_output : out STD_LOGIC_VECTOR(2 downto 0); x_pos_output : out STD_LOGIC_VECTOR(7 downto 0); y_pos_output : out STD_LOGIC_VECTOR(7 downto 0); tricolor_led_output : out STD_LOGIC_VECTOR(11 downto 0); usb_bt_output : out STD_LOGIC_VECTOR(15 downto 0); color_output : out STD_LOGIC_VECTOR(23 downto 0); ram_we_output : out STD_LOGIC_VECTOR(0 downto 0); ram_val_output : out STD_LOGIC_VECTOR(11 downto 0); ram_addr_output : out STD_LOGIC_VECTOR(16 downto 0) ); end game_logic; architecture Behavioral of game_logic is -- Font ROM component component font_rom is port( clk : in STD_LOGIC; addr : in STD_LOGIC_VECTOR(10 downto 0); data : out STD_LOGIC_VECTOR(7 downto 0) ); end component; -- RAM clock divider component component clock_divider is generic(count_max : INTEGER := 8); -- FIX THIS? port( clk : in STD_LOGIC; reset : in STD_LOGIC; clk_output : out STD_LOGIC ); end component; -- System properties signal pc_connected : STD_LOGIC := '0'; signal screen_size : STD_LOGIC := '0'; signal reset : STD_LOGIC := '0'; signal pen_width : STD_LOGIC_VECTOR(2 downto 0) := "000"; signal ascii_char : STD_LOGIC_VECTOR(7 downto 0) := x"00"; signal color : STD_LOGIC_VECTOR(23 downto 0) := x"000000"; --USB/bluetooth control send signals signal prev_screen_size : STD_LOGIC := '0'; signal prev_save : STD_LOGIC := '0'; signal prev_reset : STD_LOGIC := '0'; signal prev_pen_width : STD_LOGIC_VECTOR(2 downto 0):= "000"; signal prev_ascii_char : STD_LOGIC_VECTOR(7 downto 0):= x"00"; signal prev_x_pos, prev_y_pos : STD_LOGIC_VECTOR(7 downto 0):= x"00"; signal prev_color : STD_LOGIC_VECTOR(23 downto 0):= x"000000"; --USB/Bluetooth control receive signals signal prev_connections : STD_LOGIC_VECTOR(7 downto 0); -- Keyboard control signals signal num_values_input : INTEGER := 0; signal prev_pc_connected : STD_LOGIC := '0'; signal changing_item : STD_LOGIC_VECTOR(2 downto 0) := "000"; -- [color, pen_width, screen_size] signal hex_input : STD_LOGIC_VECTOR(3 downto 0) := x"0"; signal temp_hex_input : STD_LOGIC_VECTOR(7 downto 0) := x"00"; signal input_values : STD_LOGIC_VECTOR(23 downto 0) := x"000000"; -- Font Rom signals signal font_rom_addr : UNSIGNED(10 downto 0) := x"00" & "000"; signal font_rom_data : STD_LOGIC_VECTOR(7 downto 0) := x"00"; -- RAM clock divider signals signal ram_divider_counter : INTEGER := 0; signal ram_clk : STD_LOGIC := '0'; -- RAM Signals signal x_pos_int : INTEGER := 0; signal y_pos_int : INTEGER := 0; -- RAM fast update signals signal ram_update_count : INTEGER := 0; signal ram_update_x_count : INTEGER := 0; signal ram_update_y_count : INTEGER := 0; signal ram_update_slow_int : INTEGER := 0; signal ram_update : STD_LOGIC_VECTOR(2 downto 0) := "000"; -- [pos, sys_text, user_text] signal ram_update_slow : STD_LOGIC_VECTOR(2 downto 0) := "000"; signal ram_update_pos_slow : STD_LOGIC_VECTOR(7 downto 0) := x"00"; signal ram_update_sys_text_slow : STD_LOGIC_VECTOR(7 downto 0) := x"00"; signal ram_update_user_text_slow : STD_LOGIC_VECTOR(7 downto 0) := x"00"; -- RAM slow control signals signal x_addr_count, y_addr_count : INTEGER := 0; -- RAM reset signals signal ram_reset : STD_LOGIC := '0'; signal ram_reset_slow : STD_LOGIC := '0'; signal ram_reset_count : UNSIGNED(15 downto 0) := x"0000"; signal prev_ram_resets : STD_LOGIC_VECTOR(7 downto 0) := x"00"; begin screen_size_output <= screen_size; pen_width_output <= pen_width; x_pos_output <= x_pos_input; y_pos_output <= y_pos_input; tricolor_led_output <= color(11 downto 0); color_output <= color; ram_we_output <= "1"; --ram_we_output <= "0"; reset_output <= reset; -- Previous signal generation process process(clk) begin prev_pc_connected <= pc_connected; prev_x_pos <= x_pos_input; prev_y_pos <= y_pos_input; prev_color <= color; prev_ascii_char <= ascii_char; prev_screen_size <= screen_size; prev_pen_width <= pen_width; prev_save <= save_button_input; prev_reset <= reset; end process; -- USB/Bluetooth control process process(clk, usb_bt_clk, prev_x_pos, prev_y_pos) -- FIX THIS (add update method) begin -- Sending Data if rising_edge(clk) then if reset /= prev_reset then usb_bt_output(15 downto 12) <= "1111"; usb_bt_output(1) <= save_button_input; usb_bt_output(0) <= reset; elsif prev_x_pos /= x_pos_input then usb_bt_output(15 downto 14) <= "10"; usb_bt_output(8) <= '0'; usb_bt_output(7 downto 0) <= x_pos_input; elsif prev_y_pos /= y_pos_input then usb_bt_output(15 downto 14) <= "10"; usb_bt_output(8) <= '1'; usb_bt_output(7 downto 0) <= y_pos_input; elsif prev_color /= color then usb_bt_output(15 downto 12) <= "1100"; usb_bt_output(11 downto 0) <= color(11 downto 0); -- change to 24 bit? elsif prev_screen_size /= screen_size or prev_pen_width /= pen_width then usb_bt_output(15 downto 12) <= "1110"; usb_bt_output(3) <= screen_size; usb_bt_output(2 downto 0) <= pen_width; elsif prev_ascii_char /= ascii_char then usb_bt_output(15 downto 12) <= "1101"; usb_bt_output(7 downto 0) <= ascii_char; elsif prev_save /= save_button_input then usb_bt_output(15 downto 12) <= "1111"; usb_bt_output(1) <= save_button_input; usb_bt_output(0) <= reset; else usb_bt_output <= x"0000"; end if; end if; -- Recieving Data if rising_edge(usb_bt_clk) then prev_connections <= prev_connections(6 downto 0) & usb_bt_input(0); if prev_connections = x"00" then pc_connected <= '0'; else pc_connected <= '1'; end if; end if; end process; -- Keyboard control process hex_input <= temp_hex_input(3 downto 0); process(clk) begin -- Keyboard control if rising_edge(clk) then if reset = '0' then if keyboard_input = x"77" and changing_item = "000" then -- input w and changing color ascii_char <= x"77"; changing_item <= "100"; num_values_input <= 1; elsif keyboard_input = x"63" and changing_item = "000" then -- input c and changing pen_width ascii_char <= x"63"; changing_item <= "010"; num_values_input <= 1; elsif keyboard_input = x"73" and changing_item = "000" then -- input s and changing screen_size ascii_char <= x"73"; changing_item <= "001"; num_values_input <= 1; elsif keyboard_input = x"72" and changing_item = "000" then -- input r reset <= '1'; color <= x"FFFFFF"; pen_width <= "000"; screen_size <= '0'; elsif keyboard_input = x"71" and changing_item /= "000" then -- input q and exit command ascii_char <= x"71"; -- FIX THIS elsif keyboard_input = x"08" and num_values_input = 1 then -- input backspace ascii_char <= x"08"; num_values_input <= 0; changing_item <= "000"; elsif changing_item /= "000" then -- Ascii to hex converter if (keyboard_input >= x"30" and keyboard_input <= x"39") then temp_hex_input <= std_logic_vector(unsigned(keyboard_input) - x"30"); elsif (keyboard_input >= x"61" and keyboard_input <= x"66") then temp_hex_input <= std_logic_vector(unsigned(keyboard_input) - x"57"); else temp_hex_input <= x"FF"; end if; -- User keyboard input restrictions if changing_item = "100" and hex_input <= x"F" then -- Limit color input_values(((num_values_input * 4)-1) downto ((num_values_input-1) * 4)) <= hex_input; num_values_input <= num_values_input + 1; elsif changing_item = "010" and hex_input >= x"1" and hex_input <= x"7" then -- Limit pen_width input_values(3 downto 0) <= hex_input; num_values_input <= num_values_input + 1; elsif changing_item = "001" and hex_input <= x"1" then -- Limit screen_size input_values(3 downto 0) <= hex_input; num_values_input <= num_values_input + 1; end if; elsif keyboard_input = x"0A" then -- input enter ascii_char <= x"0A"; if changing_item = "100" and num_values_input = 7 then -- new color color <= input_values; changing_item <= "000"; elsif changing_item = "010" and num_values_input = 1 then -- new pen_width pen_width <= input_values(2 downto 0); changing_item <= "000"; elsif changing_item = "001" and num_values_input = 1 then -- new screen_size screen_size <= input_values(0); changing_item <= "000"; end if; end if; end if; -- Reset handling if reset = '1' and prev_reset = '1' and ram_reset = '0' then reset <= '0'; color <= x"000000"; end if; end if; end process; -- Font ROM port map ram_font_rom : font_rom port map( clk => clk, addr => std_logic_vector(font_rom_addr), data => font_rom_data ); -- RAM clock divider port map ram_clock_divider : clock_divider generic map(count_max => 2) -- CHANGE VALUE port map( clk => clk, reset => '0', clk_output => ram_clk ); x_pos_int <= to_integer(unsigned(x_pos_input)); y_pos_int <= to_integer(unsigned(y_pos_input)); -- RAM control process process(clk, ram_clk) begin -- When to update RAM if rising_edge(clk) then -- ram_update_pos_slow <= ram_update_pos_slow(6 downto 0) & ram_update_slow(2); -- ram_update_pos_slow <= ram_update_pos_slow(6 downto 0) & ram_update_slow(2); -- ram_update_pos_slow <= ram_update_pos_slow(6 downto 0) & ram_update_slow(2); if (x_pos_input /= prev_x_pos or y_pos_input /= prev_y_pos) then ram_update(2) <= '1'; -- pos ram_update_slow_int <= 1; elsif ram_update slow = 64 ram_update(2) <= '0'; -- elsif (color /= prev_color or pen_width /= prev_pen_width -- or pc_connected /= prev_pc_connected) then -- ram_update(1) <= '1'; -- sys_text -- elsif (ascii_char /= prev_ascii_char) then -- ram_update(0) <= '1'; -- user_text end if; if ram_update_slow_int = 64 then ram_update_slow_int <= 0; elsif ram_update_slow_int > 0 then ram_update_slow_int <= ram_update_slow_int + 1; end if; -- if ram_update_pos_slow = x"00" then -- ram_update(2) <= '0'; -- end if; -- if ram_update_sys_text_slow = x"00" then -- ram_update(1) <= '0'; -- end if; -- if ram_update_user_text_slow = x"00" then -- ram_update(0) <= '0'; -- end if; -- if reset = '1' and ram_reset = '0' then -- ram_reset <= '1'; -- prev_ram_resets <= prev_ram_resets(6 downto 0) & ram_reset; -- end if; -- -- if ram_reset_slow = '0' and prev_ram_resets = x"FF" then -- ram_reset <= '0'; -- end if; -- end if; -- Draw to RAM --if rising_edge(ram_clk) then --if rising_edge(clk) then --if ram_reset = '0' then if ram_update(2) = '1' then -- pos --if(true) then --ram_we_output <= "1"; ram_val_output <= color(23 downto 20) & color(15 downto 12) & color(7 downto 4); --ram_update_slow(2) <= '1'; --ram_update(2) <= '0'; -- if (y_addr_count < unsigned(pen_width)) and -- ((y_pos_int + y_addr_count) < 256) and -- ((y_pos_int + y_addr_count) >= 0) then -- if (x_addr_count < unsigned(pen_width)) and -- ((x_pos_int + x_addr_count) < 256) and -- ((x_pos_int + x_addr_count) >= 0) then ram_addr_output <= std_logic_vector(to_unsigned( ((x_pos_int+x_addr_count) + ((y_pos_int+y_addr_count) * 256)) , 17)); else ram_val_output <= x"F00"; ram_addr_output <= std_logic_vector(to_unsigned(66666, 17)); ram_update(2) <= '1'; -- else -- x_addr_count <= 0; -- end if; -- y_addr_count <= y_addr_count + 1; -- else -- y_addr_count <= 0; -- end if; --elsif prev_x_pos /= x_pos_input and prev_y_pos /= y_pos_input then --Not needed? --ram_update(1) <= '0'; --ram_we_output <= "0"; --Not needed? --ram_update(2) <= '0'; --Not needed? -- elsif ram_update(2 downto 1) = "01" then -- sys_text -- ram_update_slow(2 downto 1) <= "01"; -- if ram_update_count < 3 then -- if ram_update_y_count < 16 then -- if ram_update_x_count < 8 then -- if ram_update_count = 1 then -- Update color -- ram_addr_output <= std_logic_vector(to_unsigned(65618 + ram_update_x_count -- + (ram_update_y_count * 384), 17)); -- ram_val_output <= color(11 downto 0); -- elsif ram_update_count = 2 then -- Update pen_width -- ram_addr_output <= std_logic_vector(to_unsigned(65768 + ram_update_x_count -- + (ram_update_y_count * 384), 17)); -- font_rom_addr <= "000" & (x"30" + unsigned("0000" & pen_width)); -- FIX THIS (concurency) -- if font_rom_data(ram_update_x_count) = '1' then -- ram_val_output <= x"000"; -- else -- ram_val_output <= x"FFF"; -- end if; -- else -- Update pc_connnection -- ram_addr_output <= std_logic_vector(to_unsigned(65888 + ram_update_x_count -- + (ram_update_count * 10) -- + (ram_update_y_count * 384), 17)); -- font_rom_addr <= "00" & (x"30" + "0000000" & pc_connected); -- FIX THIS (concurency) -- if font_rom_data(ram_update_x_count) = '1' then -- ram_val_output <= x"000"; -- else -- ram_val_output <= x"FFF"; -- end if; -- end if; -- ram_update_x_count <= ram_update_x_count + 1; -- else -- ram_update_x_count <= 0; -- end if; -- ram_update_y_count <= ram_update_x_count + 1; -- else -- ram_update_y_count <= 0; -- end if; -- ram_update_count <= ram_update_count + 1; -- else -- ram_update_slow(1) <= '0'; -- ram_update_count <= 0; -- end if; -- elsif ram_update = "001" then -- user_text -- ram_update_slow <= "001"; -- if ram_update_count < 8 then -- if ram_update_y_count < 16 then -- if ram_update_x_count < 8 then -- ram_addr_output <= std_logic_vector(to_unsigned(66102 + ram_update_x_count -- + (ram_update_y_count * 384), 17)); -- font_rom_addr <= unsigned("000" & ascii_char); -- FIX THIS (concurency) -- if font_rom_data(ram_update_x_count) = '1' then -- ram_val_output <= x"000"; -- else -- ram_val_output <= x"FFF"; -- end if; -- ram_update_x_count <= ram_update_x_count + 1; -- else -- ram_update_x_count <= 0; -- end if; -- ram_update_y_count <= ram_update_x_count + 1; -- else -- ram_update_y_count <= 0; -- end if; -- ram_update_count <= ram_update_count + 1; -- else -- ram_update_slow(0) <= '0'; -- ram_update_count <= 0; -- end if; -- else -- ram_update_slow <= "000"; --end if; ---- else -- ram_reset = 1 ---- -- Drawing Screen (sys_text and user_text update automatically) ---- if ram_reset_count < 65536 then ---- ram_reset_slow <= '1'; ---- ram_reset_count <= ram_reset_count + 1; ---- ram_addr_output <= "0" & std_logic_vector(ram_reset_count); ---- else ---- ram_reset_slow <= '0'; ---- ram_reset_count <= x"0000"; ---- end if; end if; end if; end process; end Behavioral;
gpl-3.0
8997007fea5268925088232e1a3d6c54
0.446333
3.986009
false
false
false
false
JarrettR/FPGA-Cryptoparty
FPGA/hdl/hmac_scheduler.vhd
1
7,784
-------------------------------------------------------------------------------- -- Scheduler for running 5 concurrent SHA1 calcs and outputting sequentially -- Copyright (C) 2016 Jarrett Rainier -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.sha1_pkg.all; entity hmac_scheduler is port( clk_i : in std_ulogic; load_i : in std_ulogic; rst_i : in std_ulogic; dat_i : in std_ulogic_vector(0 to 31); sot_in : in std_ulogic; dat_1_o : out std_ulogic_vector(0 to 31); dat_2_o : out std_ulogic_vector(0 to 31); dat_3_o : out std_ulogic_vector(0 to 31) ); end hmac_scheduler; architecture RTL of hmac_scheduler is component sha1_load port ( clk_i : in std_ulogic; rst_i : in std_ulogic; dat_i : in std_ulogic_vector(0 to 31); sot_in : in std_ulogic; dat_w_o : out w_input ); end component; component sha1_process_input port ( clk_i : in std_ulogic; rst_i : in std_ulogic; dat_i : in w_input; load_i : in std_ulogic; dat_w_o : out w_full; valid_o : out std_ulogic ); end component; component sha1_process_buffer port ( clk_i : in std_ulogic; rst_i : in std_ulogic; dat_i : in w_full; load_i : in std_ulogic; new_i : in std_ulogic; dat_w_o : out w_output; valid_o : out std_ulogic ); end component; signal w_load: w_input; signal w_processed_input1: w_full; signal w_processed_input2: w_full; signal w_processed_input3: w_full; signal w_processed_input4: w_full; signal w_processed_input5: w_full; signal w_processed_new: std_ulogic; signal w_processed_buffer: w_output; signal w_processed_buffer1: w_output; signal w_processed_buffer2: w_output; signal w_processed_buffer3: w_output; signal w_processed_buffer4: w_output; signal w_processed_buffer5: w_output; signal w_buffer_valid1: std_ulogic; signal w_buffer_valid2: std_ulogic; signal w_buffer_valid3: std_ulogic; signal w_buffer_valid4: std_ulogic; signal w_buffer_valid5: std_ulogic; signal w_pinput: w_input; signal latch_pinput: std_ulogic_vector(0 to 4); signal w_processed_valid: std_ulogic_vector(0 to 4); signal i : integer range 0 to 16; signal i_mux : integer range 0 to 4; -- synthesis translate_off signal test_sha1_process_input_o : std_ulogic_vector(0 to 31); signal test_sha1_process_buffer0_o : std_ulogic_vector(0 to 31); signal test_sha1_process_buffer_o : std_ulogic_vector(0 to 31); signal test_sha1_load_o : std_ulogic_vector(0 to 31); -- synthesis translate_on begin LOAD1: sha1_load port map (clk_i,rst_i,dat_i,sot_in,w_load); --Alt: Use a generate statement PINPUT1: sha1_process_input port map (clk_i,rst_i,w_pinput,latch_pinput(0),w_processed_input1,w_processed_valid(0)); PBUFFER1: sha1_process_buffer port map (clk_i,rst_i,w_processed_input1,w_processed_valid(0),w_processed_valid(0),w_processed_buffer1,w_buffer_valid1); PINPUT2: sha1_process_input port map (clk_i,rst_i,w_pinput,latch_pinput(1),w_processed_input2,w_processed_valid(1)); PBUFFER2: sha1_process_buffer port map (clk_i,rst_i,w_processed_input2,w_processed_valid(1),w_processed_valid(1),w_processed_buffer2,w_buffer_valid2); PINPUT3: sha1_process_input port map (clk_i,rst_i,w_pinput,latch_pinput(2),w_processed_input3,w_processed_valid(2)); PBUFFER3: sha1_process_buffer port map (clk_i,rst_i,w_processed_input3,w_processed_valid(2),w_processed_valid(2),w_processed_buffer3,w_buffer_valid3); PINPUT4: sha1_process_input port map (clk_i,rst_i,w_pinput,latch_pinput(3),w_processed_input4,w_processed_valid(3)); PBUFFER4: sha1_process_buffer port map (clk_i,rst_i,w_processed_input4,w_processed_valid(3),w_processed_valid(3),w_processed_buffer4,w_buffer_valid4); PINPUT5: sha1_process_input port map (clk_i,rst_i,w_pinput,latch_pinput(4),w_processed_input5,w_processed_valid(4)); PBUFFER5: sha1_process_buffer port map (clk_i,rst_i,w_processed_input5,w_processed_valid(4),w_processed_valid(4),w_processed_buffer5,w_buffer_valid5); process(clk_i) begin if (clk_i'event and clk_i = '1') then if rst_i = '1' then latch_pinput <= "00000"; i <= 0; --Todo: start from 0 after testing i_mux <= 0; for x in 0 to 15 loop w_pinput(x) <= "00000000000000000000000000000000"; end loop; else if i = 15 then case i_mux is when 0 => latch_pinput <= "10000"; when 1 => latch_pinput <= "01000"; when 2 => latch_pinput <= "00100"; when 3 => latch_pinput <= "00010"; when 4 => latch_pinput <= "00001"; end case; w_pinput <= w_load; i <= 0; --i <= i + 1; if i_mux = 4 then i_mux <= 0; else i_mux <= i_mux + 1; end if; else latch_pinput <= "00000"; i <= i + 1; end if; end if; --Alt: Consider other conditionals if w_processed_valid(0) = '1' then w_processed_buffer <= w_processed_buffer1; elsif w_processed_valid(1) = '1' then w_processed_buffer <= w_processed_buffer2; elsif w_processed_valid(2) = '1' then w_processed_buffer <= w_processed_buffer3; elsif w_processed_valid(3) = '1' then w_processed_buffer <= w_processed_buffer4; elsif w_processed_valid(4) = '1' then w_processed_buffer <= w_processed_buffer5; end if; end if; end process; dat_1_o <= w_pinput(15); -- synthesis translate_off test_sha1_process_input_o <= w_processed_input1(16); test_sha1_process_buffer0_o <= w_processed_buffer1(0); test_sha1_process_buffer_o <= w_processed_buffer(0); test_sha1_load_o <= w_load(15); -- synthesis translate_on end RTL;
gpl-3.0
1b739d0d9b89e5e76a6b2c8c02905a21
0.534815
3.630597
false
false
false
false
lnls-dig/dsp-cores
hdl/modules/daphine/daphine.vhd
1
15,883
------------------------------------------------------------------------------- -- Title : Daphine calculator -- Project : ------------------------------------------------------------------------------- -- File : daphine.vhd -- Author : vfinotti -- Company : -- Created : 2015-07-01 -- Last update: 2015-07-01 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: This module gets a,b,c and d values and calculates X and Y. ------------------------------------------------------------------------------- -- Copyright (c) 2015 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2015-07-01 1.0 vfinotti Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ------------------------------------------------------------------------------- entity ds_first_stage is generic ( g_width : natural := 32 ); port( a_i : in std_logic_vector(g_width-1 downto 0); b_i : in std_logic_vector(g_width-1 downto 0); c_i : in std_logic_vector(g_width-1 downto 0); d_i : in std_logic_vector(g_width-1 downto 0); clk_i : in std_logic; valid_i : in std_logic; valid_o : out std_logic; ce_i : in std_logic; x_o : out std_logic_vector(g_width-1 downto 0); y_o : out std_logic_vector(g_width-1 downto 0); -- q_o : out std_logic_vector(g_width-1 downto 0); -- sum_o : out std_logic_vector(g_width-1 downto 0) sum_ac_o : out std_logic_vector(g_width-1 downto 0) sum_db_o : out std_logic_vector(g_width-1 downto 0) ); end entity ds_first_stage; architecture behavioral of ds_first_stage is signal diff_ac, diff_db : signed(g_width-1 downto 0); signal sum_ac, sum_db : signed(g_width-1 downto 0); signal valid_d0 : std_logic := '0'; begin -- Using these formulas to calculate delta: -- x = (a-c) + (d-b) -- y = (a-c) + (d-b) -- sum_ac = a+c -- sum_db = d+b stage1 : process(clk_i) variable a, b, c, d : signed(g_width-1 downto 0); begin -- to avoid multiple stages of combinatorial logic, divide it between difference and sum. -- Remeber signals are only updated at the end of process if rising_edge(clk_i) then if ce_i = '1' then a := signed(a_i); b := signed(b_i); c := signed(c_i); d := signed(d_i); -- First cycle diff_ac <= a - c; diff_db <= d - b; sum_ac <= a + c; sum_db <= d + b; valid_d0 <= valid_i; -- Second cycle x_o <= std_logic_vector(diff_ac + diff_bd); y_o <= std_logic_vector(diff_ac - diff_bd); -- q_o <= std_logic_vector(diff_cd - diff_ba); -- sum_o <= std_logic_vector(sum_ab + sum_cd); sum_ac_o <= std_logic_vector(sum_ac); sum_db_o <= std_logic_vector(sum_db); valid_o <= valid_d0; end if; end if; end process; end architecture behavioral; --ds_first_stage library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity ds_output_stage is generic ( g_width : natural := 32; g_k_width : natural := 32 ); port( x_i : in std_logic_vector(g_width-1 downto 0); kx_i : in std_logic_vector(g_k_width-1 downto 0); x_valid_i : in std_logic; y_i : in std_logic_vector(g_width-1 downto 0); ky_i : in std_logic_vector(g_k_width-1 downto 0); y_valid_i : in std_logic; -- q_i : in std_logic_vector(g_width-1 downto 0); -- q_valid_i : in std_logic; -- sum_i : in std_logic_vector(g_width-1 downto 0); -- ksum_i : in std_logic_vector(g_k_width-1 downto 0); -- sum_valid_i : in std_logic; clk_i : in std_logic; ce_i : in std_logic; x_o : out std_logic_vector(g_width-1 downto 0); y_o : out std_logic_vector(g_width-1 downto 0); -- q_o : out std_logic_vector(g_width-1 downto 0); -- sum_o : out std_logic_vector(g_width-1 downto 0); sum_ac_o : out std_logic_vector(g_width-1 downto 0); sum_db_o : out std_logic_vector(g_width-1 downto 0); valid_o : out std_logic ); end entity ds_output_stage; architecture structural of ds_output_stage is -- signal x_pre, y_pre, q_pre, sum_pre : std_logic_vector(g_width-1 downto 0); signal x_pre, y_pre : std_logic_vector(g_width-1 downto 0); signal valid : std_logic; -- signal x_ce_valid, y_ce_valid, q_ce_valid, sum_ce_valid : std_logic; signal x_ce_valid, y_ce_valid : std_logic; attribute keep : string; -- attribute keep of x_pre, y_pre, sum_pre : signal is "true"; attribute keep of x_pre, y_pre : signal is "true"; constant c_levels : natural := 7; component pipeline is generic ( g_width : natural; g_depth : natural); port ( data_i : in std_logic_vector(g_width-1 downto 0); clk_i : in std_logic; ce_i : in std_logic; data_o : out std_logic_vector(g_width-1 downto 0)); end component pipeline; component generic_multiplier is generic ( g_a_width : natural; g_b_width : natural; g_signed : boolean; g_p_width : natural; g_levels : natural); port ( a_i : in std_logic_vector(g_a_width-1 downto 0); b_i : in std_logic_vector(g_b_width-1 downto 0); p_o : out std_logic_vector(g_p_width-1 downto 0); ce_i : in std_logic; clk_i : in std_logic; rst_i : in std_logic); end component generic_multiplier; begin -- Input registers from division x_ce_valid <= ce_i and x_valid_i; cmp_x_input : pipeline generic map ( g_width => g_width, g_depth => 1) port map ( data_i => x_i, clk_i => clk_i, ce_i => x_ce_valid, data_o => x_pre); y_ce_valid <= ce_i and y_valid_i; cmp_y_input : pipeline generic map ( g_width => g_width, g_depth => 1) port map ( data_i => y_i, clk_i => clk_i, ce_i => y_ce_valid, data_o => y_pre); -- sum_ce_valid <= ce_i and sum_valid_i; -- cmp_sum_input : pipeline -- generic map ( -- g_width => g_width, -- g_depth => 1) -- port map ( -- data_i => sum_i, -- clk_i => clk_i, -- ce_i => sum_ce_valid, -- data_o => sum_pre); -- q_ce_valid <= ce_i and q_valid_i; -- cmp_q_input : pipeline -- generic map ( -- g_width => g_width, -- g_depth => 1) -- port map ( -- data_i => q_i, -- clk_i => clk_i, -- ce_i => q_ce_valid, -- data_o => q_pre); -- q is special: it won't be multiplied. So, it must be pipelined to level -- the delay of the other signals -- cmp_q_pipe : pipeline -- generic map ( -- g_width => g_width, -- g_depth => c_levels+2) -- port map ( -- data_i => q_pre, -- clk_i => clk_i, -- ce_i => ce_i, -- data_o => q_o); cmp_mult_x : generic_multiplier generic map ( g_a_width => g_width, g_b_width => g_k_width, g_signed => true, g_p_width => g_width, g_levels => c_levels) port map ( a_i => x_pre, b_i => kx_i, p_o => x_o, ce_i => ce_i, clk_i => clk_i, rst_i => '0'); cmp_mult_y : generic_multiplier generic map ( g_a_width => g_width, g_b_width => g_k_width, g_signed => true, g_p_width => g_width, g_levels => c_levels) port map ( a_i => y_pre, b_i => ky_i, p_o => y_o, ce_i => ce_i, clk_i => clk_i, rst_i => '0'); -- cmp_mult_sum : generic_multiplier -- generic map ( -- g_a_width => g_width, -- g_b_width => g_k_width, -- g_signed => true, -- g_p_width => g_width, -- g_levels => c_levels) -- port map ( -- a_i => sum_pre, -- b_i => ksum_i, -- p_o => sum_o, -- ce_i => ce_i, -- clk_i => clk_i, -- rst_i => '0'); -- The valid signal must go through the same number of registers as the other -- signals, which have the input register and through the ones inside the pipeline -- cmp_valid_pipe : pipeline -- generic map ( -- g_width => 1, -- g_depth => c_levels+3) -- port map ( -- data_i(0) => q_valid_i, -- clk_i => clk_i, -- ce_i => ce_i, -- data_o(0) => valid_o); end architecture structural; --ds_output_stage ------------------------------------------------------------------------------- -- Top level ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity daphine is generic ( g_width : natural := 32; g_k_width : natural := 24 ); port ( a_i : in std_logic_vector(g_width-1 downto 0); b_i : in std_logic_vector(g_width-1 downto 0); c_i : in std_logic_vector(g_width-1 downto 0); d_i : in std_logic_vector(g_width-1 downto 0); kx_i : in std_logic_vector(g_k_width-1 downto 0); ky_i : in std_logic_vector(g_k_width-1 downto 0); -- ksum_i : in std_logic_vector(g_k_width-1 downto 0); clk_i : in std_logic; ce_i : in std_logic; valid_i : in std_logic; valid_o : out std_logic; rst_i : in std_logic; x_o : out std_logic_vector(g_width-1 downto 0); y_o : out std_logic_vector(g_width-1 downto 0); -- q_o : out std_logic_vector(g_width-1 downto 0); -- sum_o : out std_logic_vector(g_width-1 downto 0); sum_ac_o : out std_logic_vector(g_width-1 downto 0); sum_db_o : out std_logic_vector(g_width-1 downto 0); ); end entity daphine; ------------------------------------------------------------------------------- architecture str of daphine is signal x_pre : std_logic_vector(g_width-1 downto 0); signal y_pre : std_logic_vector(g_width-1 downto 0); -- signal q_pre : std_logic_vector(g_width-1 downto 0); signal sigma_ac : std_logic_vector(g_width-1 downto 0); signal sigma_db : std_logic_vector(g_width-1 downto 0); signal x_pos : std_logic_vector(g_width-1 downto 0); signal x_rdo : std_logic; signal y_pos : std_logic_vector(g_width-1 downto 0); signal y_rdo : std_logic; -- signal q_pos : std_logic_vector(g_width-1 downto 0); -- signal q_rdo : std_logic; signal valid_pre : std_logic; component ds_first_stage is generic ( g_width : natural); port ( a_i : in std_logic_vector(g_width-1 downto 0); b_i : in std_logic_vector(g_width-1 downto 0); c_i : in std_logic_vector(g_width-1 downto 0); d_i : in std_logic_vector(g_width-1 downto 0); clk_i : in std_logic; valid_i : in std_logic; valid_o : out std_logic; ce_i : in std_logic; x_o : out std_logic_vector(g_width-1 downto 0); y_o : out std_logic_vector(g_width-1 downto 0); -- q_o : out std_logic_vector(g_width-1 downto 0); -- sum_o : out std_logic_vector(g_width-1 downto 0)); sum_ac_o : out std_logic_vector(g_width-1 downto 0); sum_db_o : out std_logic_vector(g_width-1 downto 0); end component ds_first_stage; component div_fixedpoint is generic ( G_DATAIN_WIDTH : integer range 2 to 48; G_PRECISION : integer range 1 to 47); port ( clk_i : in std_logic; rst_i : in std_logic; ce_i : in std_logic; n_i : in std_logic_vector(G_DATAIN_WIDTH-1 downto 0); d_i : in std_logic_vector(G_DATAIN_WIDTH-1 downto 0); q_o : out std_logic_vector(G_PRECISION downto 0); r_o : out std_logic_vector(G_DATAIN_WIDTH-1 downto 0); trg_i : in std_logic; rdy_o : out std_logic; err_o : out std_logic); end component div_fixedpoint; component ds_output_stage is generic ( g_width : natural; g_k_width : natural); port ( x_i : in std_logic_vector(g_width-1 downto 0); kx_i : in std_logic_vector(g_k_width-1 downto 0); x_valid_i : in std_logic; y_i : in std_logic_vector(g_width-1 downto 0); ky_i : in std_logic_vector(g_k_width-1 downto 0); y_valid_i : in std_logic; -- q_i : in std_logic_vector(g_width-1 downto 0); -- q_valid_i : in std_logic; -- sum_i : in std_logic_vector(g_width-1 downto 0); -- ksum_i : in std_logic_vector(g_k_width-1 downto 0); -- sum_valid_i : in std_logic; clk_i : in std_logic; ce_i : in std_logic; x_o : out std_logic_vector(g_width-1 downto 0); y_o : out std_logic_vector(g_width-1 downto 0); -- q_o : out std_logic_vector(g_width-1 downto 0); -- sum_o : out std_logic_vector(g_width-1 downto 0); sum_ac_o : out std_logic_vector(g_width-1 downto 0); sum_db_o : out std_logic_vector(g_width-1 downto 0); valid_o : out std_logic); end component ds_output_stage; begin -- architecture str cmp_first_stage : ds_first_stage generic map ( g_width => g_width) port map ( a_i => a_i, b_i => b_i, c_i => c_i, d_i => d_i, clk_i => clk_i, valid_i => valid_i, valid_o => valid_pre, ce_i => ce_i, x_o => x_pre, y_o => y_pre, -- q_o => q_pre, -- sum_o => sigma); sum_ac_o => sigma_ac, sum_bd_o => sigma_bd); cmp_divider_x : div_fixedpoint generic map ( G_DATAIN_WIDTH => g_width, G_PRECISION => g_width-1) port map ( clk_i => clk_i, rst_i => rst_i, ce_i => ce_i, n_i => x_pre, d_i => sigma, q_o => x_pos, r_o => open, trg_i => valid_pre, rdy_o => x_rdo, err_o => open); cmp_divider_y : div_fixedpoint generic map ( G_DATAIN_WIDTH => g_width, G_PRECISION => g_width-1) port map ( clk_i => clk_i, rst_i => rst_i, ce_i => ce_i, n_i => y_pre, d_i => sigma, q_o => y_pos, r_o => open, trg_i => valid_pre, rdy_o => y_rdo, err_o => open); -- --cmp_divider_q : div_fixedpoint -- generic map ( -- G_DATAIN_WIDTH => g_width, -- G_PRECISION => g_width-1) -- port map ( -- clk_i => clk_i, -- rst_i => rst_i, -- ce_i => ce_i, -- n_i => q_pre, -- d_i => sigma, -- q_o => q_pos, -- r_o => open, -- trg_i => valid_pre, -- rdy_o => q_rdo, -- err_o => open); cmp_output_buffer : ds_output_stage generic map ( g_width => g_width, g_k_width => g_k_width) port map ( x_i => x_pos, kx_i => kx_i, x_valid_i => x_rdo, y_i => y_pos, ky_i => ky_i, y_valid_i => y_rdo, -- q_i => q_pos, -- q_valid_i => q_rdo, -- sum_i => sigma, -- ksum_i => ksum_i, -- sum_valid_i => valid_pre, clk_i => clk_i, ce_i => ce_i, x_o => x_o, y_o => y_o, -- q_o => q_o, -- sum_o => sum_o, sum_ac_o => sum_ac_o, sum_db_o => sum_db_o, valid_o => valid_o); end architecture str; -------------------------------------------------------------------------------
lgpl-3.0
2645cd5417929f58df726c88bde47260
0.487943
2.95223
false
false
false
false
Ana06/function-graphing-FPGA
KbdCore.vhd
2
7,770
---------------------------------------------------------------------------------- -- Company: -- Engineer: Ali Diouri -- -- Create Date: 20:59:21 05/03/2012 -- Design Name: -- Module Name: KbdCore - Behavioral -- Project Name: Keyboard IP -- Target Devices: -- Tool versions: Xilinx ISE 14.4 -- Description: -- Keyboard Core Top file -- -- Dependencies: -- KbdRxData.vhd -- KbdTxData.vhd -- KbdDataCtrl.vhd -- KbdFilter.vhd -- IOBuffer.xco -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- statusReg : -- 0 : Full OUTput buffer -- 1 : Full Input buffer -- 2 : -- 3 : -- 4 : -- 5 : -- 6 : Empty Input buffer -- 7 : Empty OUTput buffer -- controlReg : -- 0 : -- 1 : -- 2 : -- 3 : -- 4 : -- 5 : -- 6 : -- 7 : ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_unsigned.all; use IEEE.NUMERIC_STD.ALL; library UNISIM; use UNISIM.Vcomponents.ALL; entity KbdCore is PORT ( clk : IN STD_LOGIC; rst : IN STD_LOGIC; rdOBuff : IN STD_LOGIC; wrIBuffer : IN STD_LOGIC; dataFromHost : IN STD_LOGIC_VECTOR(7 downto 0); KBData : INOUT STD_LOGIC; KBClk : INOUT STD_LOGIC; statusReg : OUT STD_LOGIC_VECTOR(7 downto 0); dataToHost : OUT STD_LOGIC_VECTOR(7 downto 0) ); end KbdCore; architecture Behavioral of KbdCore is Component KbdTxData PORT( clk : IN STD_LOGIC; rst : IN STD_LOGIC; Tx_en : IN STD_LOGIC; kbd_dataf : IN STD_LOGIC; kbd_clkf : IN STD_LOGIC; Data : IN STD_LOGIC_VECTOR(7 downto 0); busy : OUT STD_LOGIC; T_Data : OUT STD_LOGIC; --when T=0, IO = OUT; when T=1, IO = IN; T_Clk : OUT STD_LOGIC; --when T=0, IO = OUT; when T=1, IO = IN; KbdData : OUT STD_LOGIC; KbdClk : OUT STD_LOGIC ); end component; Component KbdRxData PORT( clk : IN STD_LOGIC; rst : IN STD_LOGIC; kbd_Data : IN STD_LOGIC; kbd_clk : IN STD_LOGIC; Rx_en : IN STD_LOGIC; busy : OUT STD_LOGIC; dataValid : OUT STD_LOGIC; Data : OUT STD_LOGIC_VECTOR (7 downto 0) ); end component; Component KbdDataCtrl PORT( clk : IN STD_LOGIC; rst : IN STD_LOGIC; busyRx : IN STD_LOGIC; busyTx : in STD_LOGIC; validDataKb : IN STD_LOGIC; dataInIBuff : IN STD_LOGIC; DataFromKb : IN STD_LOGIC_VECTOR (7 downto 0); DataFromIBuff : IN STD_LOGIC_VECTOR (7 downto 0); Rx_en : OUT STD_LOGIC; Tx_en : OUT STD_LOGIC; rd_en : OUT STD_LOGIC; wr_en : OUT STD_LOGIC; DataTokb : OUT STD_LOGIC_VECTOR (7 downto 0); DataToOBuff : OUT STD_LOGIC_VECTOR (7 downto 0) ); end component; Component KbdFilter PORT( clk : IN STD_LOGIC; rst : IN STD_LOGIC; kbdClk : IN STD_LOGIC; kbdData : IN STD_LOGIC; kbdClkF : OUT STD_LOGIC; kbdDataF : OUT STD_LOGIC ); end component; COMPONENT IOBuffer PORT ( clk : IN STD_LOGIC; rst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(7 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC ); END COMPONENT; COMPONENT IOBUF PORT ( I : IN std_logic; IO : INOUT std_logic; O : OUT std_logic; T : IN std_logic ); END COMPONENT; SIGNAL dataFromKB : STD_LOGIC; SIGNAL dataToKB : STD_LOGIC; SIGNAL ClkToKb : STD_LOGIC; SIGNAL ClkFromKb : STD_LOGIC; SIGNAL TData : STD_LOGIC; --when T=0, IO = OUT; when T=1, IO = IN; SIGNAL TClk : STD_LOGIC; --when T=0, IO = OUT; when T=1, IO = IN; SIGNAL Tx_en : STD_LOGIC; SIGNAL Rx_en : STD_LOGIC; SIGNAL busyRx : STD_LOGIC; SIGNAL busyTx : STD_LOGIC; SIGNAL dataValid : STD_LOGIC; SIGNAL kbdDataF : STD_LOGIC; SIGNAL kbdClkF : STD_LOGIC; SIGNAL emptyIBuff : STD_LOGIC; SIGNAL wrOBuff : STD_LOGIC; SIGNAL rdIBuff : STD_LOGIC; SIGNAL DataFromIBuff : STD_LOGIC_VECTOR(7 downto 0); SIGNAL DataToOBuff : STD_LOGIC_VECTOR(7 downto 0); SIGNAL DataTxKb : STD_LOGIC_VECTOR(7 downto 0); SIGNAL DataRxKb : STD_LOGIC_VECTOR(7 downto 0); BEGIN SendKB: KbdTxData PORT MAP( clk => clk, rst => rst, Tx_en => Tx_en, kbd_dataf => kbdDataF, kbd_clkf => kbdClkF, Data => DataTxKb, busy => busyTx, T_Data => TData, T_Clk => TClk, KbdData => dataToKb, KbdClk => ClkToKb ); RecieveKb: KbdRxData PORT MAP( clk => clk, rst => rst, kbd_Data => kbdDataF, kbd_clk => kbdClkF, Rx_en => Rx_en, busy => BusyRx, dataValid => dataValid, Data => DataRxKb ); ProcData:KbdDataCtrl PORT MAP( clk => clk, rst => rst, busyRx => busyRx, busyTx => busyTx, validDataKb => dataValid, dataInIBuff => emptyIBuff, DataFromKb => DataRxKb, DataFromIBuff => DataFromIBuff, rd_en => rdIBuff, wr_en => wrOBuff, Rx_en => Rx_en, Tx_en => Tx_en, DataTokb => DataTxKb, DataToOBuff => DataToOBuff ); Filter:KbdFilter PORT MAP( clk => clk, rst => rst, kbdClk => clkFromKb, kbdData => dataFromKb, kbdClkF => kbdClkF, kbdDataF => kbdDataF ); OBuffer : IOBuffer PORT MAP ( clk => clk, rst => rst, din => DataToOBuff, wr_en => wrOBuff, rd_en => rdOBuff, dOUT => dataToHost, full => statusReg(0), empty => statusReg(7) ); IBuffer : IOBuffer PORT MAP ( clk => clk, rst => rst, din => dataFromHost, wr_en => wrIBuffer, rd_en => rdIBuff, dOUT => DataFromIBuff, full => statusReg(1), empty => emptyIBuff ); IOData: IOBUF PORT MAP( I => dataToKb, IO => KBData, O => dataFromKB, T => TData ); IOClk: IOBUF PORT MAP( I => ClkToKb, IO => KBClk, O => ClkFromKb, T => TClk ); statusReg(6 DOWNTO 2) <= (OTHERS => '0'); end Behavioral;
gpl-3.0
f8775257dc8e6a2f44f13e3118c5f794
0.437323
3.784705
false
false
false
false
TUM-LIS/faultify
hardware/testcases/QR/fpga_sim/xpsLibraryPath_asic_400_599/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/vhdl/viterbi_stimuli.vhd
3
2,753
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.qr_pack.all; entity viterbi_stimuli is port ( clk : in std_logic; rst_n : in std_logic; s_axis_input_tvalid : out std_logic; s_axis_input_tdata : out std_logic_vector(31 downto 0); s_axis_input_tlast : out std_logic; s_axis_input_tready : in std_logic; m_axis_output_tvalid : in std_logic; m_axis_output_tdata : in std_logic; m_axis_output_tlast : in std_logic; m_axis_output_tready : out std_logic; s_axis_ctrl_tvalid : out std_logic; s_axis_ctrl_tdata : out std_logic_vector(31 downto 0); s_axis_ctrl_tlast : out std_logic; s_axis_ctrl_tready : in std_logic ); end viterbi_stimuli; architecture behav of viterbi_stimuli is type fsm_type is (IDLE, START_STATE, ); signal state : fsm_type := IDLE; signal rand_out_1, rand_out_2 : std_logic_vector(32-1 downto 0); component lfsr generic ( width : integer; seed : integer); port ( clk : in std_logic; rand_out : out std_logic_vector(width-1 downto 0)); end component; begin -- behav lfsr_1 : lfsr generic map ( width => 32, seed => 242) port map ( clk => clk, rand_out => rand_out_1); lfsr_2 : lfsr generic map ( width => 32, seed => 324) port map ( clk => clk, rand_out => rand_out_2); in_A_r <= rand_out_1(3 downto 0); in_A_i <= rand_out_2(3 downto 0); process (clk, rst_n) begin -- process if rst_n = '0' then -- asynchronous reset (active low) state <= IDLE; m_axis_ctrl_tlast <= '0'; m_axis_ctrl_tvalid <= '0'; m_axis_ctrl_tdata <= (others => '0'); m_axis_input_tlast <= '0'; m_axis_input_tvalid <= '0'; m_axis_input_tdata <= (others => '0'); elsif clk'event and clk = '1' then -- rising clock edge case state is when IDLE => if ready = '1' then state <= START_STATE; end if; when START_STATE => start <= '1'; state <= D0; when D0 => start <= '0'; state <= D1; when D1 => state <= D2; when D2 => state <= D3; when D3 => state <= WAIT_FOR_VALID; when WAIT_FOR_VALID => if ready = '1' then state <= REQUEST_OUTPUT; end if; when REQUEST_OUTPUT => request_out <= '1'; state <= WAIT_FOR_READY; when WAIT_FOR_READY => request_out <= '0'; if ready = '1' then state <= START_STATE; end if; end case; end if; end process; end behav;
gpl-2.0
25da6ac6f2c511aca99d123053031c01
0.527788
3.204889
false
false
false
false
carlosrd/DAS
P2/Parte B/switchToSeg.vhd
1
1,697
---------------------------------------------------------------------------------- -- ESQUEMA LEDS 8 SEGMENTOS: -- -- A -- --- -- F | | B -- -G- -- E | | C -- --- . DP -- D ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity switchToSeg is port ( switch: in std_logic_vector(7 downto 0); rightSeg: out std_logic_vector(7 downto 0); leftSeg: out std_logic_vector(7 downto 0) -- 7 = A / 6 = B / ... / 0 = H ); end switchToSeg; architecture Behavioral of switchToSeg is -- Lista de componentes que se van a utilizar dentro de esta arquitectura component binToSeg port( bin: in std_logic_vector(3 downto 0); displaySeg: out std_logic_vector(7 downto 0)); end component; -- Señales (cables) auxiliares signal rightSwitch: std_logic_vector(3 downto 0); signal leftSwitch: std_logic_vector(3 downto 0); begin -- Partimos los 8 switch en 2 bloques de 4. -- Recordamos de la practica anterior que es necesario usar -- un negador con los switch para que funcionen de la manera esperada leftSwitch(3) <= not(switch(0)); leftSwitch(2) <= not(switch(1)); leftSwitch(1) <= not(switch(2)); leftSwitch(0) <= not(switch(3)); rightSwitch(3) <= not(switch(4)); rightSwitch(2) <= not(switch(5)); rightSwitch(1) <= not(switch(6)); rightSwitch(0) <= not(switch(7)); -- Creamos 2 instancias del componente "binToSeg" y como entrada -- uno de los bloques dividido antes y salida una de la arquitectura leftDisplay: binToSeg port map (leftSwitch,leftSeg); rightDisplay: binToSeg port map (rightSwitch,rightSeg); end Behavioral;
mit
315da2d1a99442cd1da114832a8f591c
0.595168
3.506198
false
false
false
false
JarrettR/FPGA-Cryptoparty
FPGA/hdl/wpa2_main.vhd
1
5,074
-------------------------------------------------------------------------------- -- wpa2_main.vhd -- Master file, starting at PBKDF2 and cascading down -- Copyright (C) 2016 Jarrett Rainier -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.sha1_pkg.all; entity wpa2_main is port( clk_i : in std_ulogic; rst_i : in std_ulogic; start_i : in std_ulogic; ssid_dat_i : in ssid_data; data_dat_i : in packet_data; anonce_dat : in nonce_data; cnonce_dat : in nonce_data; amac_dat : in mac_data; cmac_dat : in mac_data; mk_initial : in mk_data; mk_end : in mk_data; mk_dat_o : out mk_data; mk_valid_o : out std_ulogic; wpa2_complete_o : out std_ulogic ); end wpa2_main; architecture RTL of wpa2_main is -- Fixed input format for benchmarking -- Generates sample passwords of ten ascii digits, 0-f component gen_tenhex port( clk_i : in std_ulogic; rst_i : in std_ulogic; load_i : in std_ulogic; start_i : in std_ulogic; start_val_i : in mk_data; end_val_i : in mk_data; complete_o : out std_ulogic; dat_mk_o : out mk_data ); end component; component pbkdf2_main is port( clk_i : in std_ulogic; rst_i : in std_ulogic; load_i : in std_ulogic; mk_i : in mk_data; ssid_i : in ssid_data; dat_o : out w_output; valid_o : out std_ulogic ); end component; component wpa2_compare_test port( clk_i : in std_ulogic; rst_i : in std_ulogic; mk_dat_i : in mk_data; data_dat_i : in w_input; pke_dat_i : in w_input; mic_dat_i : in w_input; pmk_dat_o : out pmk_data; pmk_valid_o : out std_ulogic ); end component; signal w: w_input; signal w_temp: w_input; --signal mk_init_load: std_ulogic; signal mk: mk_data; signal pmk: pmk_data; --signal i : integer range 0 to 4; signal gen_complete: std_ulogic := '0'; signal comp_complete: std_ulogic := '0'; signal running: std_ulogic := '0'; signal load_gen: std_ulogic := '0'; signal start_gen: std_ulogic := '0'; signal pbkdf_valid : std_ulogic; signal pbkdf_load : std_ulogic := '0'; signal pbkdf_mk : mk_data; signal pbkdf_ssid : ssid_data; signal pbkdf_dat : w_output; begin gen1: gen_tenhex port map (clk_i,rst_i,load_gen,start_gen,mk_initial,mk_end,gen_complete,mk); pbkdf2: pbkdf2_main port map (clk_i,rst_i, pbkdf_load, pbkdf_mk, pbkdf_ssid, pbkdf_dat, pbkdf_valid); comp1: wpa2_compare_test port map (clk_i,rst_i,mk,w,w,w,pmk,comp_complete); process(clk_i) begin if (clk_i'event and clk_i = '1') then if rst_i = '1' then wpa2_complete_o <= '0'; running <= '0'; --mk_init_load <= '1'; else if start_i = '1' then running <= '1'; load_gen <= '1'; elsif load_gen = '1' then load_gen <= '0'; start_gen <= '1'; else start_gen <= '0'; end if; --mk_init_load <= '0'; if gen_complete = '1' or comp_complete = '1' then wpa2_complete_o <= '1'; running <= '0'; else wpa2_complete_o <= '0'; end if; end if; end if; end process; mk_valid_o <= comp_complete; end RTL;
gpl-3.0
6391843f0110785382ff3e9a204916ec
0.461569
3.758519
false
false
false
false