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chiggs/oc_mkjpeg
design/bytestuffer/ByteStuffer.vhd
2
7,740
------------------------------------------------------------------------------- -- File Name : ByteStuffer.vhd -- -- Project : JPEG_ENC -- -- Module : ByteStuffer -- -- Content : ByteStuffer -- -- Description : ByteStuffer core -- -- Spec. : -- -- Author : Michal Krepa -- ------------------------------------------------------------------------------- -- History : -- 20090301: (MK): Initial Creation. ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ----------------------------------- LIBRARY/PACKAGE --------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- generic packages/libraries: ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ------------------------------------------------------------------------------- -- user packages/libraries: ------------------------------------------------------------------------------- library work; use work.JPEG_PKG.all; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ----------------------------------- ENTITY ------------------------------------ ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- entity ByteStuffer is port ( CLK : in std_logic; RST : in std_logic; -- CTRL start_pb : in std_logic; ready_pb : out std_logic; -- HOST IF sof : in std_logic; num_enc_bytes : out std_logic_vector(23 downto 0); outram_base_addr : in std_logic_vector(9 downto 0); -- Huffman huf_buf_sel : out std_logic; huf_fifo_empty : in std_logic; huf_rd_req : out std_logic; huf_packed_byte : in std_logic_vector(7 downto 0); -- OUT RAM ram_byte : out std_logic_vector(7 downto 0); ram_wren : out std_logic; ram_wraddr : out std_logic_vector(23 downto 0) ); end entity ByteStuffer; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ----------------------------------- ARCHITECTURE ------------------------------ ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- architecture RTL of ByteStuffer is signal huf_data_val : std_logic_vector(3 downto 0); signal wdata_reg : std_logic_vector(15 downto 0); signal wraddr : unsigned(23 downto 0); signal wr_n_cnt : unsigned(1 downto 0); signal huf_buf_sel_s : std_logic; signal rd_en : std_logic; signal rd_en_d1 : std_logic; signal huf_rd_req_s : std_logic; signal latch_byte : std_logic_vector(7 downto 0); signal data_valid : std_logic; signal wait_for_ndata : std_logic; ------------------------------------------------------------------------------- -- Architecture: begin ------------------------------------------------------------------------------- begin huf_buf_sel <= huf_buf_sel_s; huf_rd_req <= huf_rd_req_s; ------------------------------------------------------------------- -- CTRL_SM ------------------------------------------------------------------- p_ctrl_sm : process(CLK, RST) begin if RST = '1' then wr_n_cnt <= (others => '0'); ready_pb <= '0'; huf_rd_req_s <= '0'; huf_data_val <= (others => '0'); rd_en <= '0'; rd_en_d1 <= '0'; wdata_reg <= (others => '0'); ram_wren <= '0'; wraddr <= (others => '0'); ram_wraddr <= (others => '0'); ram_byte <= (others => '0'); latch_byte <= (others => '0'); wait_for_ndata <= '0'; data_valid <= '0'; elsif CLK'event and CLK = '1' then huf_rd_req_s <= '0'; ready_pb <= '0'; huf_data_val <= huf_data_val(huf_data_val'length-2 downto 0) & huf_rd_req_s; rd_en_d1 <= rd_en; ram_wren <= '0'; data_valid <= '0'; if start_pb = '1' then rd_en <= '1'; end if; -- read FIFO until it becomes empty. wait until last byte read is -- serviced if rd_en_d1 = '1' and wait_for_ndata = '0' then -- FIFO empty if huf_fifo_empty = '1' then rd_en <= '0'; rd_en_d1 <= '0'; ready_pb <= '1'; else huf_rd_req_s <= '1'; wait_for_ndata <= '1'; end if; end if; -- show ahead FIFO, capture data early if huf_rd_req_s = '1' then latch_byte <= huf_packed_byte; data_valid <= '1'; end if; if huf_data_val(1) = '1' then wait_for_ndata <= '0'; end if; -- data from FIFO is valid if data_valid = '1' then -- stuffing necessary if latch_byte = X"FF" then -- two writes are necessary for byte stuffing wr_n_cnt <= "10"; wdata_reg <= X"FF00"; -- no stuffing else wr_n_cnt <= "01"; wdata_reg <= X"00" & latch_byte; end if; end if; if wr_n_cnt > 0 then wr_n_cnt <= wr_n_cnt - 1; ram_wren <= '1'; wraddr <= wraddr + 1; end if; -- delayed to make address post-increment ram_wraddr <= std_logic_vector(wraddr); -- stuffing if wr_n_cnt = 2 then ram_byte <= wdata_reg(15 downto 8); elsif wr_n_cnt = 1 then ram_byte <= wdata_reg(7 downto 0); end if; if sof = '1' then wraddr <= to_unsigned(C_HDR_SIZE,wraddr'length); end if; end if; end process; ------------------------------------------------------------------- -- HUFFMAN buf_sel ------------------------------------------------------------------- p_huf_buf_sel : process(CLK, RST) begin if RST = '1' then huf_buf_sel_s <= '0'; elsif CLK'event and CLK = '1' then if start_pb = '1' then huf_buf_sel_s <= not huf_buf_sel_s; end if; end if; end process; ------------------------------------------------------------------- -- num_enc_bytes ------------------------------------------------------------------- p_num_enc_bytes : process(CLK, RST) begin if RST = '1' then num_enc_bytes <= (others => '0'); elsif CLK'event and CLK = '1' then -- plus 2 for EOI marker last bytes num_enc_bytes <= std_logic_vector(wraddr + 2); end if; end process; end architecture RTL; ------------------------------------------------------------------------------- -- Architecture: end -------------------------------------------------------------------------------
lgpl-3.0
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cnplab/blockmon
fw-combo/src/CBF/application.vhd
1
30,158
-- ---------------------------------------------------------------------------- -- modified by sal -- ---------------------------------------------------------------------------- -- application.vhd : Combov2 NetCOPE application module -- Copyright (C) 2009 CESNET -- Author(s): Jan Stourac <[email protected]> -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in -- the documentation and/or other materials provided with the -- distribution. -- 3. Neither the name of the Company nor the names of its contributors -- may be used to endorse or promote products derived from this -- software without specific prior written permission. -- -- This software is provided ``as is'', and any express or implied -- warranties, including, but not limited to, the implied warranties of -- merchantability and fitness for a particular purpose are disclaimed. -- In no event shall the company or contributors be liable for any -- direct, indirect, incidental, special, exemplary, or consequential -- damages (including, but not limited to, procurement of substitute -- goods or services; loss of use, data, or profits; or business -- interruption) however caused and on any theory of liability, whether -- in contract, strict liability, or tort (including negligence or -- otherwise) arising in any way out of the use of this software, even -- if advised of the possibility of such damage. -- -- $Id$ -- -- ---------------------------------------------------------------------------- -- Entity declaration -- ---------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use work.combov2_core_const.all; use work.combov2_user_const.all; use work.math_pack.all; use work.ibuf_general_pkg.all; use work.addr_space.all; use work.network_mod_10g2_64_const.all; use work.utils.all; Library UNISIM; use UNISIM.vcomponents.all; architecture full of APPLICATION is component tsu_async is -- PORTS port ( RESET : in std_logic; -- Input interface IN_CLK : in std_logic; IN_TS : in std_logic_vector(63 downto 0); IN_TS_DV : in std_logic; -- Output interface OUT_CLK : in std_logic; OUT_TS : out std_logic_vector(63 downto 0); OUT_TS_DV : out std_logic ); end component tsu_async; component GICS_IB_ENDPOINT_SYNTH port( -- Common interface ----------------------------------------------------- CLK : in std_logic; RESET : in std_logic; -- IB Interface --------------------------------------------------------- IB_DOWN_DATA : in std_logic_vector(63 downto 0); IB_DOWN_SOF_N : in std_logic; IB_DOWN_EOF_N : in std_logic; IB_DOWN_SRC_RDY_N : in std_logic; IB_DOWN_DST_RDY_N : out std_logic; IB_UP_DATA : out std_logic_vector(63 downto 0); IB_UP_SOF_N : out std_logic; IB_UP_EOF_N : out std_logic; IB_UP_SRC_RDY_N : out std_logic; IB_UP_DST_RDY_N : in std_logic; -- Write Interface ------------------------------------------------------ WR_REQ : out std_logic; WR_RDY : in std_logic; WR_DATA : out std_logic_vector(63 downto 0); WR_ADDR : out std_logic_vector(31 downto 0); WR_BE : out std_logic_vector(7 downto 0); WR_LENGTH : out std_logic_vector(11 downto 0); WR_SOF : out std_logic; WR_EOF : out std_logic; -- Read Interface ------------------------------------------------------- RD_REQ : out std_logic; RD_ARDY_ACCEPT : in std_logic; RD_ADDR : out std_logic_vector(31 downto 0); RD_BE : out std_logic_vector(7 downto 0); RD_LENGTH : out std_logic_vector(11 downto 0); RD_SOF : out std_logic; RD_EOF : out std_logic; RD_DATA : in std_logic_vector(63 downto 0); RD_SRC_RDY : in std_logic; RD_DST_RDY : out std_logic; -- Bus Master Interface ------------------------------------------------- BM_DATA : in std_logic_vector(63 downto 0); BM_SOF_N : in std_logic; BM_EOF_N : in std_logic; BM_SRC_RDY_N : in std_logic; BM_DST_RDY_N : out std_logic; BM_TAG : out std_logic_vector(7 downto 0); BM_TAG_VLD : out std_logic ); end component; -- ---------------------------------------------------------------------------- -- Signal declaration -- ---------------------------------------------------------------------------- -- Signals Internal Bus Endpoint signals signal ibep_wr_req : std_logic; signal ibep_rd_req : std_logic; signal reg_ibep_rd_req : std_logic; signal ibep_rd_dst_rdy : std_logic; signal ibep_dwr : std_logic_vector(63 downto 0); signal ibep_wr_be : std_logic_vector(7 downto 0); signal ibep_wraddr : std_logic_vector(31 downto 0); signal ibep_rdaddr : std_logic_vector(31 downto 0); signal ibep_wr : std_logic; signal ibep_rd : std_logic; signal ibep_drd : std_logic_vector(63 downto 0); signal ibep_ack : std_logic; signal reg_ibep_drdy : std_logic; -- ------------------------------------------------------------------------- -- Pacodag signals -- ------------------------------------------------------------------------- signal ts0_sync : std_logic_vector(63 downto 0); signal ts0_dv_sync : std_logic; signal ts1_sync : std_logic_vector(63 downto 0); signal ts1_dv_sync : std_logic; -- ------------------------------------------------------------------------- -- ------------------------------------------------------------------------- -- ------------------------------------------------------------------------- -- inizio codice sal -- ------------------------------------------------------------------------- -- ------------------------------------------------------------------------- -- ------------------------------------------------------------------------- -- ---------------------------------------------------------------------------- -- Signal declaration -- ---------------------------------------------------------------------------- -- ---------------------------------------------------------------------------- -- signals for FSM FrameLink decoding -- ---------------------------------------------------------------------------- type fsm_states is (WAIT_FOR_FRAME, FRAME_HEADER, SRC_MAC_ADDRESS, DST_MAC_ADDRESS, IP1, IP2, IP3, DATA); signal curr_state, next_state : fsm_states; signal step: boolean; -- ---------------------------------------------------------------------------- -- signals for packet classification -- ---------------------------------------------------------------------------- signal is_IP,is_UDP,is_TCP: boolean; signal src_mac,dst_mac: std_logic_vector(47 downto 0); signal exchange: std_logic_vector(63 downto 0); signal src_ip,dst_ip: std_logic_vector(31 downto 0); signal src_port,dst_port: std_logic_vector(15 downto 0); -- ---------------------------------------------------------------------------- -- stats -- ---------------------------------------------------------------------------- signal ip_count,tcp_count,udp_count:std_logic_vector(31 downto 0); -- ---------------------------------------------------------------------------- -- signals for CBF -- ---------------------------------------------------------------------------- signal max_sip : STD_LOGIC_VECTOR(31 downto 0); -- SRC IP of the last flow over the threshold signal max_dip : STD_LOGIC_VECTOR(31 downto 0); -- DST IP of the last flow over the threshold signal max_port : STD_LOGIC_VECTOR(31 downto 0); -- SRC & DST PORT of the last flow over the threshold signal max_count : STD_LOGIC_VECTOR(31 downto 0); -- SRC & DST PORT of the last flow over the threshold signal osip : STD_LOGIC_VECTOR(31 downto 0); -- SRC IP of the last flow over the threshold signal odip : STD_LOGIC_VECTOR(31 downto 0); -- DST IP of the last flow over the threshold signal oport : STD_LOGIC_VECTOR(31 downto 0); -- SRC & DST PORT of the last flow over the threshold signal decrement,dump,start_CBF:std_logic; signal TIMEDEC,Threshold: std_logic_vector(31 downto 0); signal Data_CBF_dump: std_logic_vector(31 downto 0); signal counter_item: std_logic_vector(31 downto 0); signal counter_overflow: std_logic_vector(31 downto 0); -- ---------------------------------------------------------------------------- -- signals for MI32 BUS -- ---------------------------------------------------------------------------- signal MI32_RD_d : std_logic; signal int_mi32_addr : std_logic_vector(31 downto 0); -- ---------------------------------------------------------------------------- -- Architecture body -- ---------------------------------------------------------------------------- begin -- ------------------------------------------------------------------------- -- FrameLink -- ------------------------------------------------------------------------- -- DMA -> NET OBUF0_RX_DATA <= RX0_DATA; OBUF0_RX_REM <= RX0_DREM; OBUF0_RX_SOF_N <= RX0_SOF_N; OBUF0_RX_EOF_N <= RX0_EOF_N; OBUF0_RX_SOP_N <= RX0_SOP_N; OBUF0_RX_EOP_N <= RX0_EOP_N; OBUF0_RX_SRC_RDY_N<= RX0_SRC_RDY_N; RX0_DST_RDY_N <= OBUF0_RX_DST_RDY_N; OBUF1_RX_DATA <= RX1_DATA; OBUF1_RX_REM <= RX1_DREM; OBUF1_RX_SOF_N <= RX1_SOF_N; OBUF1_RX_EOF_N <= RX1_EOF_N; OBUF1_RX_SOP_N <= RX1_SOP_N; OBUF1_RX_EOP_N <= RX1_EOP_N; OBUF1_RX_SRC_RDY_N<= RX1_SRC_RDY_N; RX1_DST_RDY_N <= OBUF1_RX_DST_RDY_N; -- NET -> DMA TX0_DATA <= IBUF0_TX_DATA; TX0_DREM <= IBUF0_TX_REM; TX0_SOF_N <= IBUF0_TX_SOF_N; TX0_EOF_N <= IBUF0_TX_EOF_N; TX0_SOP_N <= IBUF0_TX_SOP_N; TX0_EOP_N <= IBUF0_TX_EOP_N; TX0_SRC_RDY_N <= IBUF0_TX_SRC_RDY_N; IBUF0_TX_DST_RDY_N<= TX0_DST_RDY_N; TX1_DATA <= IBUF1_TX_DATA; TX1_DREM <= IBUF1_TX_REM; TX1_SOF_N <= IBUF1_TX_SOF_N; TX1_EOF_N <= IBUF1_TX_EOF_N; TX1_SOP_N <= IBUF1_TX_SOP_N; TX1_EOP_N <= IBUF1_TX_EOP_N; TX1_SRC_RDY_N <= IBUF1_TX_SRC_RDY_N; IBUF1_TX_DST_RDY_N<= TX1_DST_RDY_N; -- ------------------------------------------------------------------------- -- Internal Bus -- ------------------------------------------------------------------------- IB_ENDPOINT_I : GICS_IB_ENDPOINT_SYNTH port map( -- Common Interface CLK => CLK, RESET => RESET, -- Internal Bus Interface IB_DOWN_DATA => IB_DOWN_DATA, IB_DOWN_SOF_N => IB_DOWN_SOF_N, IB_DOWN_EOF_N => IB_DOWN_EOF_N, IB_DOWN_SRC_RDY_N => IB_DOWN_SRC_RDY_N, IB_DOWN_DST_RDY_N => IB_DOWN_DST_RDY_N, IB_UP_DATA => IB_UP_DATA, IB_UP_SOF_N => IB_UP_SOF_N, IB_UP_EOF_N => IB_UP_EOF_N, IB_UP_SRC_RDY_N => IB_UP_SRC_RDY_N, IB_UP_DST_RDY_N => IB_UP_DST_RDY_N, -- Write Interface WR_REQ => ibep_wr_req, WR_RDY => ibep_wr_req, WR_DATA => ibep_dwr, WR_ADDR => ibep_wraddr, WR_BE => ibep_wr_be, WR_LENGTH => open, WR_SOF => open, WR_EOF => open, -- Read Interface RD_REQ => ibep_rd_req, RD_ARDY_ACCEPT => ibep_rd_dst_rdy, RD_ADDR => ibep_rdaddr, RD_BE => open, RD_LENGTH => open, RD_SOF => open, RD_EOF => open, RD_DATA => ibep_drd, RD_SRC_RDY => reg_ibep_rd_req, RD_DST_RDY => ibep_rd_dst_rdy, -- Bus Master Interface BM_DATA => X"0000000000000000", BM_SOF_N => '1', BM_EOF_N => '1', BM_SRC_RDY_N => '1', BM_DST_RDY_N => open, BM_TAG => open, BM_TAG_VLD => open ); RAMB18SDP_inst0 : RAMB18SDP generic map ( DO_REG => 0, -- Optional output register (0 or 1) INIT => X"000000000", -- Initial values on output port SIM_COLLISION_CHECK => "ALL", SIM_MODE => "SAFE", SRVAL => X"000000000" -- Set/Reset value for port output ) port map ( DO => ibep_drd(31 downto 0), -- 32-bit Data Output DOP => open, -- 4-bit Parity Output RDCLK => CLK, -- 1-bit read port clock RDEN => ibep_rd_req, -- 1-bit read port enable REGCE => '1', -- 1-bit register enable input SSR => '0', -- 1-bit synchronous output set/reset input WRCLK => CLK, -- 1-bit write port clock WREN => ibep_wr_req, -- 1-bit write port enable WRADDR => ibep_wraddr(10 downto 2),-- 9-bit write port address input RDADDR => ibep_rdaddr(10 downto 2),-- 9-bit read port address input DI => ibep_dwr(31 downto 0), -- 32-bit data input DIP => "0000", -- 4-bit parity data input WE => ibep_wr_be(3 downto 0) -- 4-bit write enable input ); RAMB18SDP_inst1 : RAMB18SDP generic map ( DO_REG => 0, -- Optional output register (0 or 1) INIT => X"000000000", -- Initial values on output port SIM_COLLISION_CHECK => "ALL", SIM_MODE => "SAFE", SRVAL => X"000000000" -- Set/Reset value for port output ) port map ( DO => ibep_drd(63 downto 32), -- 32-bit Data Output DOP => open, -- 4-bit Parity Output RDCLK => CLK, -- 1-bit read port clock RDEN => ibep_rd_req, -- 1-bit read port enable REGCE => '1', -- 1-bit register enable input SSR => '0', -- 1-bit synchronous output set/reset input WRCLK => CLK, -- 1-bit write port clock WREN => ibep_wr_req, -- 1-bit write port enable WRADDR => ibep_wraddr(10 downto 2),-- 9-bit write port address input RDADDR => ibep_rdaddr(10 downto 2),-- 9-bit read port address input DI => ibep_dwr(63 downto 32), -- 32-bit data input DIP => "0000", -- 4-bit parity data input WE => ibep_wr_be(7 downto 4) -- 4-bit write enable input ); -- Delay read request and use it as acknowledge of read data reg_ibep_rd_req_p : process(CLK) begin if CLK'event and CLK = '1' then reg_ibep_rd_req <= ibep_rd_req; end if; end process; -- ------------------------------------------------------------------------- -- PACODAG -- ------------------------------------------------------------------------- PACODAG_TOP_I: entity work.pacodag_tsu_top2_t64 generic map( HEADER_EN => PACODAG_HEADER_EN, FOOTER_EN => PACODAG_FOOTER_EN ) port map( -- Common interface RESET => RESET, -- IBUF interface PCD0_CTRL_CLK => IBUF0_CTRL_CLK, PCD0_CTRL_DATA => IBUF0_CTRL_DATA, PCD0_CTRL_REM => IBUF0_CTRL_REM, PCD0_CTRL_SRC_RDY_N => IBUF0_CTRL_SRC_RDY_N, PCD0_CTRL_SOP_N => IBUF0_CTRL_SOP_N, PCD0_CTRL_EOP_N => IBUF0_CTRL_EOP_N, PCD0_CTRL_DST_RDY_N => IBUF0_CTRL_DST_RDY_N, PCD0_CTRL_RDY => IBUF0_CTRL_RDY, PCD0_SOP => IBUF0_SOP, PCD0_STAT_PAYLOAD_LEN => IBUF0_PAYLOAD_LEN, PCD0_STAT_FRAME_ERROR => IBUF0_FRAME_ERROR, PCD0_STAT_CRC_CHECK_FAILED => IBUF0_CRC_CHECK_FAILED, PCD0_STAT_MAC_CHECK_FAILED => IBUF0_MAC_CHECK_FAILED, PCD0_STAT_LEN_BELOW_MIN => IBUF0_LEN_BELOW_MIN, PCD0_STAT_LEN_OVER_MTU => IBUF0_LEN_OVER_MTU, PCD0_STAT_DV => IBUF0_STAT_DV, PCD1_CTRL_CLK => IBUF1_CTRL_CLK, PCD1_CTRL_DATA => IBUF1_CTRL_DATA, PCD1_CTRL_REM => IBUF1_CTRL_REM, PCD1_CTRL_SRC_RDY_N => IBUF1_CTRL_SRC_RDY_N, PCD1_CTRL_SOP_N => IBUF1_CTRL_SOP_N, PCD1_CTRL_EOP_N => IBUF1_CTRL_EOP_N, PCD1_CTRL_DST_RDY_N => IBUF1_CTRL_DST_RDY_N, PCD1_CTRL_RDY => IBUF1_CTRL_RDY, PCD1_SOP => IBUF1_SOP, PCD1_STAT_PAYLOAD_LEN => IBUF1_PAYLOAD_LEN, PCD1_STAT_FRAME_ERROR => IBUF1_FRAME_ERROR, PCD1_STAT_CRC_CHECK_FAILED => IBUF1_CRC_CHECK_FAILED, PCD1_STAT_MAC_CHECK_FAILED => IBUF1_MAC_CHECK_FAILED, PCD1_STAT_LEN_BELOW_MIN => IBUF1_LEN_BELOW_MIN, PCD1_STAT_LEN_OVER_MTU => IBUF1_LEN_OVER_MTU, PCD1_STAT_DV => IBUF1_STAT_DV, TS0 => ts0_sync, TS0_DV => ts0_dv_sync, TS1 => ts1_sync, TS1_DV => ts1_dv_sync ); -- --------------------------------------------------------------- -- Generate tsu_async only if timestamp unit is also generated ts_true_async : if TIMESTAMP_UNIT = true generate tsu_async_i0 : tsu_async -- PORTS port map ( RESET => RESET, -- Input interface IN_CLK => TS_CLK, IN_TS => TS, IN_TS_DV => TS_DV, -- Output interface OUT_CLK => IBUF0_CTRL_CLK, OUT_TS => ts0_sync, OUT_TS_DV => ts0_dv_sync ); tsu_async_i1 : tsu_async -- PORTS port map ( RESET => RESET, -- Input interface IN_CLK => TS_CLK, IN_TS => TS, IN_TS_DV => TS_DV, -- Output interface OUT_CLK => IBUF1_CTRL_CLK, OUT_TS => ts1_sync, OUT_TS_DV => ts1_dv_sync ); end generate ts_true_async; -- Else map TS and TS_DV signals directly into pacodag ts_false_async : if TIMESTAMP_UNIT = false generate ts0_sync <= TS; ts0_dv_sync <= TS_DV; ts1_sync <= TS; ts1_dv_sync <= TS_DV; end generate ts_false_async; -- ------------------------------------------------------------------------- -- inizio codice sal -- ------------------------------------------------------------------------- -- ------------------------------------------------------------------------- -- ------------------------------------------------------------------------- -- exchange from network order to little endian -- ------------------------------------------------------------------------- exchange(31 downto 0)<=IBUF0_TX_DATA(39 downto 32) & IBUF0_TX_DATA(47 downto 40) & IBUF0_TX_DATA(55 downto 48) & IBUF0_TX_DATA(63 downto 56); exchange(63 downto 32)<=IBUF0_TX_DATA(7 downto 0) & IBUF0_TX_DATA(15 downto 8) & IBUF0_TX_DATA(23 downto 16) & IBUF0_TX_DATA(31 downto 24); -- ------------------------------------------------------------------------- -- -- process to detect if the next word is available -- -- ------------------------------------------------------------------------- step_assign: step<= true when (IBUF0_TX_SRC_RDY_N = '0') and (TX0_DST_RDY_N = '0') else false; -- ------------------------------------------------------------------------- -- -- process for FrameLink FSM -- extract Header ETH-IP-TCP/UDP -- -- ------------------------------------------------------------------------- process(CLK, RESET) begin if (CLK'event and CLK = '1') then if (RESET = '1') then curr_state <= WAIT_FOR_FRAME; dst_mac <= (others => '0'); src_mac <= (others => '0'); src_ip <= (others => '0'); dst_ip <= (others => '0'); src_port <= (others => '0'); dst_port <= (others => '0'); start_CBF <='0'; ip_count<= (others => '0'); tcp_count<= (others => '0'); udp_count<= (others => '0'); is_ip<=false; is_UDP<=false; is_TCP<=false; else curr_state <= next_state; case curr_state is when WAIT_FOR_FRAME => dst_mac <= (others => '0'); src_mac <= (others => '0'); src_ip <= (others => '0'); dst_ip <= (others => '0'); src_port <= (others => '0'); dst_port <= (others => '0'); start_CBF <='0'; is_ip<=false; is_UDP<=false; is_TCP<=false; when DST_MAC_ADDRESS => if (step) then report "tx_data DST_MAC_ADDRESS STATE: " & hstr(exchange) & LF ; dst_mac <= exchange(47 downto 0); src_mac(47 downto 32) <= exchange(63 downto 48); end if; when SRC_MAC_ADDRESS => if (step) then src_mac(31 downto 0) <= exchange(31 downto 0); report "tx_data SRC_MAC_ADDRESS STATE: " & hstr(exchange) & LF ; --report "tx_data: " & integer'image(conv_integer() & LF ; if (exchange(31 downto 16)=x"0800") then ip_count <= ip_count+1; is_ip<=true; end if; end if; when IP1 => if (step) then report "tx_data IP1 STATE: " & hstr(exchange) & LF ; if exchange(7 downto 0)=x"11" and is_ip then --FIXME does not check eth header lenght report "UDP packet" ; udp_count <= udp_count+1; is_UDP<=true; elsif exchange(7 downto 0)=x"06" then report "TCP packet" ; tcp_count <= tcp_count+1; is_TCP<=true; end if; end if; when IP2 => if (step) then report "tx_data IP2 STATE: " & hstr(exchange) & LF ; src_ip <= exchange(47 downto 16); dst_ip(31 downto 16) <= exchange(15 downto 0); end if; when IP3 => if (step) then report "tx_data IP3 STATE: " & hstr(exchange) & LF ; dst_ip(15 downto 0) <= exchange(63 downto 48); if is_TCP or is_UDP then src_port <= exchange(47 downto 32); dst_port <= exchange(31 downto 16); end if; if is_IP then start_CBF <='1'; end if; end if; when DATA => start_CBF <='0'; when others => null; end case; end if; end if; end process; process(curr_state, step, IBUF0_TX_SOF_N, IBUF0_TX_EOF_N, IBUF0_TX_SOP_N, IBUF0_TX_EOP_N) begin next_state <= curr_state; case curr_state is when WAIT_FOR_FRAME => if (IBUF0_TX_SOF_N = '0' and step ) then next_state <= FRAME_HEADER; end if; when FRAME_HEADER => if (IBUF0_TX_EOP_N = '0' and step ) then next_state <= DST_MAC_ADDRESS; end if; when DST_MAC_ADDRESS => if (step) then next_state <= SRC_MAC_ADDRESS; end if; when SRC_MAC_ADDRESS => if (step) then next_state <= IP1; end if; when IP1 => if (step) then next_state <= IP2; end if; when IP2 => if (step) then next_state <= IP3; end if; when IP3 => if (step) then next_state <= DATA; end if; when DATA => if (IBUF0_TX_EOF_N = '0' and step) then report "src ip: " & integer'image(conv_integer(src_ip(31 downto 24))) & "." & integer'image(conv_integer(src_ip(23 downto 16))) & "." & integer'image(conv_integer(src_ip(15 downto 8))) & "." & integer'image(conv_integer(src_ip(7 downto 0))) & LF ; report "dst ip: " & integer'image(conv_integer(dst_ip(31 downto 24))) & "." & integer'image(conv_integer(dst_ip(23 downto 16))) & "." & integer'image(conv_integer(dst_ip(15 downto 8))) & "." & integer'image(conv_integer(dst_ip(7 downto 0))) & LF ; report "src port " & integer'image(conv_integer(src_port)) & LF ; report "dst port " & integer'image(conv_integer(dst_port)) & LF ; next_state <= WAIT_FOR_FRAME; end if; end case; end process; -- ------------------------------------------------------------------------- -- MI32 interface -- ------------------------------------------------------------------------- MI32_ARDY <= MI32_WR or MI32_RD; -- Store the MI32_ADDR -- can be avoided if read latency =1 process(CLK) begin if (CLK'event and CLK = '1') then if (RESET = '1') then int_mi32_addr <= (others => '0'); elsif MI32_RD='1' then int_mi32_addr <= MI32_ADDR; end if; end if; end process; -- Create two cycle reading latency --can be only one when address \= 0009 are used process(CLK) begin if (CLK'event and CLK = '1') then if (RESET = '1') then MI32_DRDY <= '0'; MI32_RD_d <= '0'; else MI32_RD_d <= MI32_RD; MI32_DRDY <= MI32_RD_d; end if; end if; end process; -- ------------------------------------------------------------------------- -- csbus: 0x00089000 -- MI32 ADDRESS: -- 0x0008 A000 : Threshold -- 0x0008 A004 : TIMEDEC -- 0x0008 A008 : counter_overflow (RD_ONLY) -- 0x0008 A00C : counter_item (RD_ONLY) -- 0x0008 A010 : osip (RD_ONLY) last overthreshold flow -- 0x0008 A014 : odip (RD_ONLY) -- 0x0008 A018 : oport (RD_ONLY) -- 0x0008 A01C : N/A -- 0x0008 A020 : maxsip (RD_ONLY) biggest flow -- 0x0008 A024 : maxdip (RD_ONLY) -- 0x0008 A028 : maxport (RD_ONLY) -- 0x0008 A02C : maxcount value of the biggest flow -- 0x0008 A030 : ip_count (RD_ONLY) -- 0x0008 A034 : udp_count (RD_ONLY) -- 0x0008 A038 : tcp_count (RD_ONLY) -- 0x0008 A03C : N/A -- 0x0009 0000 - 0x0009 1FFF: CBF dump (RD_ONLY) -- ------------------------------------------------------------------------- -- ------------------------------------------------------------------------- -- Threshold/TIMEDEC Registers -- ------------------------------------------------------------------------- process(CLK) begin if (CLK'event and CLK = '1') then if (RESET = '1') then Threshold <= x"0000ffff"; TIMEDEC <= x"00000000"; else if ( MI32_ADDR=x"0008A000" and MI32_WR = '1') then Threshold <= MI32_DWR; end if; if ( MI32_ADDR=x"0008A004" and MI32_WR = '1') then TIMEDEC <= MI32_DWR; end if; end if; end if; end process; process(CLK) begin if (CLK'event and CLK = '1') then if MI32_RD_d='1' then if int_mi32_addr(31 downto 16)= x"0009" then --FIXME addr should be 31 downto 13 MI32_DRD <= Data_CBF_dump; elsif int_mi32_addr = x"0008A000" then MI32_DRD <= Threshold; elsif int_mi32_addr = x"0008A004" then MI32_DRD <= TIMEDEC; elsif int_mi32_addr = x"0008A008" then MI32_DRD <= counter_overflow; elsif int_mi32_addr = x"0008A00C" then MI32_DRD <= counter_item; elsif int_mi32_addr = x"0008A010" then MI32_DRD <= osip; elsif int_mi32_addr = x"0008A014" then MI32_DRD <= odip; elsif int_mi32_addr = x"0008A018" then MI32_DRD <= oport; elsif int_mi32_addr = x"0008A020" then MI32_DRD <= max_sip; elsif int_mi32_addr = x"0008A024" then MI32_DRD <= max_dip; elsif int_mi32_addr = x"0008A028" then MI32_DRD <= max_port; elsif int_mi32_addr = x"0008A02C" then MI32_DRD <= max_count; elsif int_mi32_addr = x"0008A030" then MI32_DRD <= ip_count; elsif int_mi32_addr = x"0008A034" then MI32_DRD <= udp_count; elsif int_mi32_addr = x"0008A038" then MI32_DRD <= tcp_count; else MI32_DRD <= x"beefbeef"; end if; end if; end if; end process; -------------------------------------- -- Timer to activate the CBF decrement -------------------------------------- T: entity work.timer port map( clock => CLK, reset => RESET, TIMEDEC => TIMEDEC, decrement => decrement ); -------------------------------------- -- CBF instanziation -------------------------------------- dump<= MI32_RD when MI32_ADDR(31 downto 12)=x"00090" or MI32_ADDR(31 downto 12)=x"00091" else '0'; CBF: entity work.CBFfilter port map( clock => CLK, reset => RESET, src_ip => src_ip, dst_ip => dst_ip, src_port => src_port, dst_port => dst_port, start => start_CBF, decrement => decrement, -- MI32 interface Address_CBF_dump => MI32_ADDR(12 downto 2), --FIXME should be (12 downto 2) dump => dump, Data_CBF_dump => Data_CBF_dump, osip => osip, odip => odip, oport => oport, max_sip => max_sip, max_dip => max_dip, max_port => max_port, max_count => max_count, Threshold => Threshold, counter_item => counter_item, counter_overflow => counter_overflow ); end architecture full;
bsd-3-clause
0e0e6cd4c858da623bf027853c70da26
0.462929
3.727812
false
false
false
false
SylvainLesne/openPOWERLINK_V2
hardware/ipcore/altera/hostinterface/src/alteraHostInterfaceRtl.vhd
2
9,482
------------------------------------------------------------------------------- --! @file alteraHostInterface.vhd -- --! @brief toplevel of host interface for Altera FPGA -- --! @details This toplevel interfaces to Altera specific implementation. -- ------------------------------------------------------------------------------- -- -- (c) B&R, 2014 -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; --! Common library library libcommon; --! Use common library global package use libcommon.global.all; entity alteraHostInterface is generic ( --! Version major gVersionMajor : natural := 16#FF#; --! Version minor gVersionMinor : natural := 16#FF#; --! Version revision gVersionRevision : natural := 16#FF#; --! Version count gVersionCount : natural := 0; -- Base address mapping --! Base address Dynamic Buffer 0 gBaseDynBuf0 : natural := 16#00800#; --! Base address Dynamic Buffer 1 gBaseDynBuf1 : natural := 16#01000#; --! Base address Error Counter gBaseErrCntr : natural := 16#01800#; --! Base address TX NMT Queue gBaseTxNmtQ : natural := 16#02800#; --! Base address TX Generic Queue gBaseTxGenQ : natural := 16#03800#; --! Base address TX SyncRequest Queue gBaseTxSynQ : natural := 16#04800#; --! Base address TX Virtual Ethernet Queue gBaseTxVetQ : natural := 16#05800#; --! Base address RX Virtual Ethernet Queue gBaseRxVetQ : natural := 16#06800#; --! Base address Kernel-to-User Queue gBaseK2UQ : natural := 16#07000#; --! Base address User-to-Kernel Queue gBaseU2KQ : natural := 16#09000#; --! Base address Tpdo gBasePdo : natural := 16#0B000#; --! Base address Reserved (-1 = high address of Pdo) gBaseRes : natural := 16#0E000#; --! Host address width gHostAddrWidth : natural := 16 ); port ( --! Clock Source input csi_c0_clock : in std_logic; --! Reset Source input rsi_r0_reset : in std_logic; -- Avalon Memory Mapped Slave for Host --! Avalon-MM slave host address avs_host_address : in std_logic_vector(gHostAddrWidth-1 downto 2); --! Avalon-MM slave host byteenable avs_host_byteenable : in std_logic_vector(3 downto 0); --! Avalon-MM slave host read avs_host_read : in std_logic; --! Avalon-MM slave host readdata avs_host_readdata : out std_logic_vector(31 downto 0); --! Avalon-MM slave host write avs_host_write : in std_logic; --! Avalon-MM slave host writedata avs_host_writedata : in std_logic_vector(31 downto 0); --! Avalon-MM slave host waitrequest avs_host_waitrequest : out std_logic; -- Avalon Memory Mapped Slave for PCP --! Avalon-MM slave pcp address avs_pcp_address : in std_logic_vector(10 downto 2); --! Avalon-MM slave pcp byteenable avs_pcp_byteenable : in std_logic_vector(3 downto 0); --! Avalon-MM slave pcp read avs_pcp_read : in std_logic; --! Avalon-MM slave pcp readdata avs_pcp_readdata : out std_logic_vector(31 downto 0); --! Avalon-MM slave pcp write avs_pcp_write : in std_logic; --! Avalon-MM slave pcp writedata avs_pcp_writedata : in std_logic_vector(31 downto 0); --! Avalon-MM slave pcp waitrequest avs_pcp_waitrequest : out std_logic; -- Avalon Memory Mapped Master for Host via Magic Bridge --! Avalon-MM master hostBridge address avm_hostBridge_address : out std_logic_vector(29 downto 0); --! Avalon-MM master hostBridge byteenable avm_hostBridge_byteenable : out std_logic_vector(3 downto 0); --! Avalon-MM master hostBridge read avm_hostBridge_read : out std_logic; --! Avalon-MM master hostBridge readdata avm_hostBridge_readdata : in std_logic_vector(31 downto 0); --! Avalon-MM master hostBridge write avm_hostBridge_write : out std_logic; --! Avalon-MM master hostBridge writedata avm_hostBridge_writedata : out std_logic_vector(31 downto 0); --! Avalon-MM master hostBridge waitrequest avm_hostBridge_waitrequest : in std_logic; --! Interrupt receiver inr_irqSync_irq : in std_logic; --! Interrupt sender ins_irqOut_irq : out std_logic; --! External Sync Source coe_ExtSync_exsync : in std_logic ); end alteraHostInterface; architecture rtl of alteraHostInterface is --! The bridge translation lut is implemented in memory blocks to save logic resources. --! If no M9K shall be used, set this constant to 0. constant cBridgeUseMemBlock : natural := 1; begin --! The host interface theHostInterface: entity work.hostInterface generic map ( gVersionMajor => gVersionMajor, gVersionMinor => gVersionMinor, gVersionRevision => gVersionRevision, gVersionCount => gVersionCount, gBridgeUseMemBlock => cBridgeUseMemBlock, gBaseDynBuf0 => gBaseDynBuf0, gBaseDynBuf1 => gBaseDynBuf1, gBaseErrCntr => gBaseErrCntr, gBaseTxNmtQ => gBaseTxNmtQ, gBaseTxGenQ => gBaseTxGenQ, gBaseTxSynQ => gBaseTxSynQ, gBaseTxVetQ => gBaseTxVetQ, gBaseRxVetQ => gBaseRxVetQ, gBaseK2UQ => gBaseK2UQ, gBaseU2KQ => gBaseU2KQ, gBasePdo => gBasePdo, gBaseRes => gBaseRes, gHostAddrWidth => gHostAddrWidth ) port map ( iClk => csi_c0_clock, iRst => rsi_r0_reset, iHostAddress => avs_host_address, iHostByteenable => avs_host_byteenable, iHostRead => avs_host_read, oHostReaddata => avs_host_readdata, iHostWrite => avs_host_write, iHostWritedata => avs_host_writedata, oHostWaitrequest => avs_host_waitrequest, iPcpAddress => avs_pcp_address, iPcpByteenable => avs_pcp_byteenable, iPcpRead => avs_pcp_read, oPcpReaddata => avs_pcp_readdata, iPcpWrite => avs_pcp_write, iPcpWritedata => avs_pcp_writedata, oPcpWaitrequest => avs_pcp_waitrequest, oHostBridgeAddress => avm_hostBridge_address, oHostBridgeByteenable => avm_hostBridge_byteenable, oHostBridgeRead => avm_hostBridge_read, iHostBridgeReaddata => avm_hostBridge_readdata, oHostBridgeWrite => avm_hostBridge_write, oHostBridgeWritedata => avm_hostBridge_writedata, iHostBridgeWaitrequest => avm_hostBridge_waitrequest, iIrqIntSync => inr_irqSync_irq, iIrqExtSync => coe_ExtSync_exsync, oIrq => ins_irqOut_irq ); end rtl;
gpl-2.0
d2641e1d1d78684cb0c8cfe238e5b3b2
0.567602
4.880082
false
false
false
false
SylvainLesne/openPOWERLINK_V2
hardware/ipcore/xilinx/memory/src/dpRamOpenmac-rtl-a.vhd
1
5,958
--! @file dpRam-bhv-a.vhd -- --! @brief Dual Port Ram Register Transfer Level Architecture -- --! @details This is the DPRAM intended for synthesis on Xilinx Spartan 6 only. --! It is specific for the openMAC descriptor DPRAM which require --! simultaneous write/read from the same address. --! Timing as follows [clk-cycles]: write=0 / read=1 --! @note Note that only port B reads valid data reliably! -- ------------------------------------------------------------------------------- -- Architecture : rtl ------------------------------------------------------------------------------- -- -- (c) B&R, 2015 -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; --! Common library library libcommon; --! Use common library global package use libcommon.global.all; architecture rtl of dpRamOpenmac is --! Width of a byte constant cByte : natural := 8; --! Address width (used to generate size depending on address width) constant cAddrWidth : natural := iAddress_A'length; --! RAM size constant cRamSize : natural := 2**cAddrWidth; --! Type for data port subtype tDataPort is std_logic_vector(gWordWidth-1 downto 0); --! RAM type with given size type tRam is array (cRamSize-1 downto 0) of tDataPort; --! Shared variable to model and synthesize a DPR shared variable vDpram : tRam := (others => (others => cInactivated)); --! Port A readport signal readdataA : tDataPort; --! Port B readport signal readdataB : tDataPort; begin assert (gInitFile = "UNUSED") report "Memory initialization is not supported in this architecture!" severity warning; -- assign readdata to ports oReaddata_A <= readdataA; oReaddata_B <= readdataB; --! This process describes port A of the DPRAM. The write process considers --! iWriteEnable_A and iByteenable_A. The read process is done with every --! rising iClk_A edge. PORTA : process(iClk_A) begin if rising_edge(iClk_A) then if iEnable_A = cActivated then --------------------------------------------------------------- -- Set write port A to READ_FIRST to enable reliable read at -- port B! -- read word from DPRAM readdataA <= vDpram(to_integer(unsigned(iAddress_A))); --------------------------------------------------------------- if iWriteEnable_A = cActivated then for i in iByteenable_A'range loop if iByteenable_A(i) = cActivated then -- write byte to DPRAM vDpram(to_integer(unsigned(iAddress_A)))( (i+1)*cByte-1 downto i*cByte ) := iWritedata_A( (i+1)*cByte-1 downto i*cByte ); end if; --byteenable end loop; end if; --writeenable end if; --enable end if; end process PORTA; --! This process describes port B of the DPRAM. The write process considers --! iWriteEnable_B and iByteenable_B. The read process is done with every --! rising iClk_B edge. PORTB : process(iClk_B) begin if rising_edge(iClk_B) then if iEnable_B = cActivated then if iWriteEnable_B = cActivated then for i in iByteenable_B'range loop if iByteenable_B(i) = cActivated then -- write byte to DPRAM vDpram(to_integer(unsigned(iAddress_B)))( (i+1)*cByte-1 downto i*cByte ) := iWritedata_B( (i+1)*cByte-1 downto i*cByte ); end if; --byteenable end loop; end if; --writeenable -- read word from DPRAM readdataB <= vDpram(to_integer(unsigned(iAddress_B))); end if; --enable end if; end process PORTB; end architecture rtl;
gpl-2.0
675c6865d1de65c28741bb48da06e5e8
0.567304
5.044877
false
false
false
false
SylvainLesne/openPOWERLINK_V2
hardware/ipcore/altera/fifo/src/asyncFifo-syn-a.vhd
3
3,712
------------------------------------------------------------------------------- --! @file asyncFifo-syn-a.vhd -- --! @brief The asynchronous Fifo architecture for Altera -- --! @details This is a dual clock fifo generated in Megawizard! -- ------------------------------------------------------------------------------- -- -- (c) B&R, 2014 -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; --! use altera_mf library library altera_mf; use altera_mf.altera_mf_components.all; architecture syn of asyncFifo is begin theAlteraDcFifo : dcfifo generic map ( intended_device_family => "Cyclone IV E", lpm_width => gDataWidth, lpm_widthu => logDualis(gWordSize), lpm_numwords => gWordSize, lpm_showahead => "OFF", lpm_type => "DCFIFO", overflow_checking => "ON", underflow_checking => "ON", delay_rdusedw => 1, delay_wrusedw => 1, add_usedw_msb_bit => "OFF", rdsync_delaypipe => gSyncStages+2, wrsync_delaypipe => gSyncStages+2, use_eab => gMemRes, write_aclr_synch => "ON", read_aclr_synch => "ON", clocks_are_synchronized => "FALSE", add_ram_output_register => "ON" ) port map ( aclr => iAclr, data => iWrData, q => oRdData, rdclk => iRdClk, rdempty => oRdEmpty, rdfull => oRdFull, rdreq => iRdReq, rdusedw => oRdUsedw, wrclk => iWrClk, wrempty => oWrEmpty, wrfull => oWrFull, wrreq => iWrReq, wrusedw => oWrUsedw ); end architecture syn;
gpl-2.0
d6fadd2f481928a5f02cedaa73db786e
0.548222
4.910053
false
false
false
false
SylvainLesne/openPOWERLINK_V2
hardware/ipcore/altera/memory/src/dpRamSplx-rtl-a.vhd
3
3,526
--! @file dpRamSplx-rtl-a.vhd -- --! @brief Simplex Dual Port Ram Register Transfer Level Architecture -- --! @details This is the Simplex DPRAM intended for synthesis on Altera --! platforms only. --! Timing as follows [clk-cycles]: write=0 / read=1 -- ------------------------------------------------------------------------------- -- Architecture : rtl ------------------------------------------------------------------------------- -- -- (c) B&R, 2014 -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; --! use altera_mf library library altera_mf; use altera_mf.altera_mf_components.all; architecture rtl of dpRamSplx is begin altsyncram_component : altsyncram generic map ( operation_mode => "DUAL_PORT", intended_device_family => "Cyclone IV", init_file => gInitFile, numwords_a => gNumberOfWordsA, numwords_b => gNumberOfWordsB, widthad_a => logDualis(gNumberOfWordsA), widthad_b => logDualis(gNumberOfWordsB), width_a => gWordWidthA, width_b => gWordWidthB, width_byteena_a => gByteenableWidthA, width_byteena_b => gByteenableWidthA ) port map ( clock0 => iClk_A, clocken0 => iEnable_A, wren_a => iWriteEnable_A, address_a => iAddress_A, byteena_a => iByteenable_A, data_a => iWritedata_A, clock1 => iClk_B, clocken1 => iEnable_B, address_b => iAddress_B, q_b => oReaddata_B ); end architecture rtl;
gpl-2.0
c75e6f862b9dc7ace2a3c035d484d11c
0.579977
4.771313
false
false
false
false
cnplab/blockmon
fw-combo/src/IPFIX/comp/fl_multiplexer.vhd
1
8,099
-- ----------------------------------------------------------------------- -- -- Company: INVEA-TECH a.s. -- -- Project: IPFIX design -- -- ----------------------------------------------------------------------- -- -- (c) Copyright 2011 INVEA-TECH a.s. -- All rights reserved. -- -- Please review the terms of the license agreement before using this -- file. If you are not an authorized user, please destroy this -- source code file and notify INVEA-TECH a.s. immediately that you -- inadvertently received an unauthorized copy. -- -- ----------------------------------------------------------------------- -- -- multiplexer.vhd: FrameLink Multiplexer -- Copyright (C) 2010 CESNET -- Author(s): Viktor Puš <[email protected]> -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in -- the documentation and/or other materials provided with the -- distribution. -- 3. Neither the name of the Company nor the names of its contributors -- may be used to endorse or promote products derived from this -- software without specific prior written permission. -- -- This software is provided ``as is'', and any express or implied -- warranties, including, but not limited to, the implied warranties of -- merchantability and fitness for a particular purpose are disclaimed. -- In no event shall the company or contributors be liable for any -- direct, indirect, incidental, special, exemplary, or consequential -- damages (including, but not limited to, procurement of substitute -- goods or services; loss of use, data, or profits; or business -- interruption) however caused and on any theory of liability, whether -- in contract, strict liability, or tort (including negligence or -- otherwise) arising in any way out of the use of this software, even -- if advised of the possibility of such damage. -- -- $Id$ -- -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use work.math_pack.all; -- ---------------------------------------------------------------------------- -- ENTITY DECLARATION -- ---------------------------------------------------------------------------- -- * FrameLink Multiplexer merges more FrameLinks into one Multiplexed FL. entity FL_MULTIPLEXER is generic( --* FrameLink data width DATA_WIDTH : integer := 64; --* Number of FrameLink channels CHANNELS : integer := 4 ); port( --+ Common interface CLK : in std_logic; RESET : in std_logic; --+ Input FrameLink interface RX_SOF_N : in std_logic_vector(CHANNELS-1 downto 0); RX_SOP_N : in std_logic_vector(CHANNELS-1 downto 0); RX_EOP_N : in std_logic_vector(CHANNELS-1 downto 0); RX_EOF_N : in std_logic_vector(CHANNELS-1 downto 0); RX_SRC_RDY_N : in std_logic_vector(CHANNELS-1 downto 0); RX_DST_RDY_N : out std_logic_vector(CHANNELS-1 downto 0); RX_DATA : in std_logic_vector(DATA_WIDTH*CHANNELS-1 downto 0); RX_DREM : in std_logic_vector(CHANNELS*log2(DATA_WIDTH/8)-1 downto 0); --+ Output FrameLink interface TX_SOF_N : out std_logic; TX_EOP_N : out std_logic; TX_SOP_N : out std_logic; TX_EOF_N : out std_logic; TX_SRC_RDY_N : out std_logic; TX_DATA : out std_logic_vector(DATA_WIDTH-1 downto 0); TX_DREM : out std_logic_vector(log2(DATA_WIDTH/8)-1 downto 0); --* Output FrameLink interface: one bit for each channel TX_DST_RDY_N : in std_logic_vector(CHANNELS-1 downto 0); --* Determines the number of active input channel TX_CHANNEL : out std_logic_vector(log2(CHANNELS)-1 downto 0) ); end entity FL_MULTIPLEXER; -- ---------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -- ---------------------------------------------------------------------------- --* FULL arhitecture implementing the module architecture fl_multiplexer_arch of FL_MULTIPLEXER is constant REM_WIDTH : integer := log2(DATA_WIDTH/8); --* data, drem, (s/e)o(p/f) constant MUX_WORD:integer:=DATA_WIDTH+REM_WIDTH+4; -- data, rem, (s/e)o(f/p) signal reg_last_sel : std_logic_vector(log2(CHANNELS)-1 downto 0); signal shift : std_logic_vector(log2(CHANNELS)-1 downto 0); signal firstone : std_logic_vector(log2(CHANNELS)-1 downto 0); signal sel : std_logic_vector(log2(CHANNELS)-1 downto 0); signal channel_rdy : std_logic_vector(CHANNELS-1 downto 0); signal channel_rdy_sh : std_logic_vector(CHANNELS-1 downto 0); signal rx_dst_rdy : std_logic_vector(CHANNELS-1 downto 0); signal output_enable : std_logic; signal mux_din : std_logic_vector(CHANNELS*MUX_WORD-1 downto 0); signal mux_dout : std_logic_vector(MUX_WORD-1 downto 0); begin channel_gen : for i in 0 to CHANNELS-1 generate channel_rdy(i) <= not(RX_SRC_RDY_N(i) or TX_DST_RDY_N(i)); mux_din(i*MUX_WORD) <= RX_SOP_N(i); mux_din(i*MUX_WORD+1) <= RX_EOP_N(i); mux_din(i*MUX_WORD+2) <= RX_SOF_N(i); mux_din(i*MUX_WORD+3) <= RX_EOF_N(i); mux_din((i*MUX_WORD)+4+REM_WIDTH-1 downto (i*MUX_WORD)+4) <= RX_DREM((i+1)*REM_WIDTH-1 downto i*REM_WIDTH); mux_din((i*MUX_WORD)+4+REM_WIDTH+DATA_WIDTH-1 downto (i*MUX_WORD)+4+REM_WIDTH) <= RX_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH); end generate; shift <= reg_last_sel + 1; --* This module mixes channel priorities. shifter_i : entity work.barrel_bit_shifter generic map( DATA_WIDTH => CHANNELS, SHIFT_LEFT => false ) port map( DATA_IN => channel_rdy, DATA_OUT => channel_rdy_sh, SEL => shift ); --* This module selects active input firstone_i : entity work.first_one_detector generic map( DATA_WIDTH => CHANNELS ) port map( MASK => channel_rdy_sh, FIRST_ONE_ONEHOT => open, FIRST_ONE_BINARY => firstone, FIRST_ONE_PRESENT => output_enable ); sel <= firstone + shift; --* Store the last selected channel reg_last_sel_p : process(CLK) begin if CLK'event and CLK = '1' then if RESET = '1' then reg_last_sel <= (others => '0'); else if output_enable = '1' then reg_last_sel <= sel; end if; end if; end if; end process; --* Output multiplexer out_mux_i : entity work.gen_mux generic map( DATA_WIDTH => MUX_WORD, MUX_WIDTH => CHANNELS ) port map( DATA_IN => mux_din, SEL => sel, DATA_OUT => mux_dout ); --* Binary to onehot encoder for RX_DST_RDY_N setting dec1ofn_i : entity work.dec1fn_enable generic map( ITEMS => CHANNELS ) port map( ADDR => sel, ENABLE => output_enable, DO => rx_dst_rdy ); -- Output interface mapping TX_DATA <= mux_dout(4+REM_WIDTH+DATA_WIDTH-1 downto 4+REM_WIDTH); TX_DREM <= mux_dout(4+REM_WIDTH-1 downto 4); TX_EOF_N <= mux_dout(3); TX_SOF_N <= mux_dout(2); TX_EOP_N <= mux_dout(1); TX_SOP_N <= mux_dout(0); TX_SRC_RDY_N<= not output_enable; TX_CHANNEL <= sel; rx_dst_rdy_n_p : process(rx_dst_rdy, output_enable, TX_DST_RDY_N) begin if output_enable = '1' then RX_DST_RDY_N<= not rx_dst_rdy; else RX_DST_RDY_N <= TX_DST_RDY_N; end if; end process; end fl_multiplexer_arch;
bsd-3-clause
b28880364ab845b73b4d8d13c7674a21
0.576068
3.699406
false
false
false
false
augustollenz/pwm-controller
src/pwm.vhd
1
963
library ieee; use ieee.std_logic_1164.all; entity pwm is port ( clk: in std_logic; reset: in std_logic; output: out std_logic ); end pwm; architecture example of pwm is constant frequency: integer := 1000; constant duty_cycle: integer range 0 to 100 := 50; -- signal counter: integer range 0 to 1000 := 0; signal counter: integer := 0; signal out_buffer: std_logic := '0'; begin process (clk, reset) is begin if reset = '0' then output <= '0'; out_buffer <= '0'; counter <= 0; elsif rising_edge(clk) then counter <= counter + 1; if counter = frequency then counter <= 0; out_buffer <= '0'; elsif counter > (100 - duty_cycle) * (frequency / 100) then out_buffer <= '1'; end if; end if; end process; output <= out_buffer; end example;
unlicense
a8dc04cfa56ffc38ae186eec1f5ff8bb
0.523364
4.0125
false
false
false
false
cnplab/blockmon
fw-combo/src/generator/comp/pseudorand_data_gen.vhd
1
128,506
-- ----------------------------------------------------------------------- -- -- Company: INVEA-TECH a.s. -- -- Project: IPFIX design -- -- ----------------------------------------------------------------------- -- -- (c) Copyright 2011 INVEA-TECH a.s. -- All rights reserved. -- -- Please review the terms of the license agreement before using this -- file. If you are not an authorized user, please destroy this -- source code file and notify INVEA-TECH a.s. immediately that you -- inadvertently received an unauthorized copy. -- -- ----------------------------------------------------------------------- -- -- pseudorand_data_gen.vhd : LFSR based pseudorandom generator module -- Copyright (C) 2009 CESNET -- Author(s): Pavol Korcek <[email protected]> -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in -- the documentation and/or other materials provided with the -- distribution. -- 3. Neither the name of the Company nor the names of its contributors -- may be used to endorse or promote products derived from this -- software without specific prior written permission. -- -- This software is provided ``as is'', and any express or implied -- warranties, including, but not limited to, the implied warranties of -- merchantability and fitness for a particular purpose are disclaimed. -- In no event shall the company or contributors be liable for any -- direct, indirect, incidental, special, exemplary, or consequential -- damages (including, but not limited to, procurement of substitute -- goods or services; loss of use, data, or profits; or business -- interruption) however caused and on any theory of liability, whether -- in contract, strict liability, or tort (including negligence or -- otherwise) arising in any way out of the use of this software, even -- if advised of the possibility of such damage. -- -- $Id: pseudorand_data_gen.vhd 11967 2009-11-11 22:34:43Z korcek $ -- library ieee; use ieee.std_logic_1164.all; use work.lfsr_pkg.all; -- ---------------------------------------------------------------------------- -- Entity declaration -- ---------------------------------------------------------------------------- entity pseudorand_data_gen is generic ( LFSR_LENGTH : integer := 64; -- internal LFSR width OUTPUT_WIDTH : integer := 128; -- output data width TAPS : LFSR_TAPS :=(64,63,61,60) -- polynomial ); port ( CLK : in std_logic; -- clock signal S_EN : in std_logic; -- shift enable F_EN : in std_logic; -- fill enable DIN : in std_logic_vector(LFSR_LENGTH-1 downto 0); -- seed DOUT : out std_logic_vector(OUTPUT_WIDTH-1 downto 0) -- data out ); end entity pseudorand_data_gen; -- ---------------------------------------------------------------------------- -- Architecture declaration -- ---------------------------------------------------------------------------- architecture beh of pseudorand_data_gen is signal init0 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init1 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init2 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init3 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init4 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init5 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init6 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init7 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init8 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init9 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init10 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init11 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init12 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init13 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init14 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init15 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init16 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init17 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init18 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init19 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init20 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init21 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init22 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init23 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init24 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init25 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init26 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init27 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init28 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init29 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init30 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init31 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init32 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init33 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init34 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init35 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init36 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init37 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init38 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init39 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init40 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init41 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init42 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init43 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init44 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init45 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init46 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init47 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init48 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init49 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init50 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init51 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init52 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init53 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init54 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init55 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init56 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init57 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init58 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init59 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init60 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init61 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init62 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init63 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init64 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init65 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init66 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init67 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init68 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init69 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init70 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init71 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init72 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init73 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init74 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init75 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init76 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init77 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init78 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init79 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init80 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init81 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init82 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init83 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init84 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init85 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init86 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init87 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init88 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init89 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init90 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init91 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init92 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init93 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init94 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init95 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init96 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init97 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init98 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init99 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init100 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init101 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init102 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init103 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init104 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init105 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init106 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init107 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init108 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init109 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init110 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init111 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init112 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init113 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init114 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init115 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init116 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init117 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init118 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init119 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init120 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init121 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init122 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init123 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init124 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init125 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init126 : std_logic_vector(LFSR_LENGTH-1 downto 0); signal init127 : std_logic_vector(LFSR_LENGTH-1 downto 0); begin inst0_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init0, DOUT => DOUT(0) ); init0 <= DIN(7) & DIN(28) & DIN(61) & DIN(33) & DIN(1) & DIN(52) & DIN(2) & DIN(14) & DIN(17) & DIN(20) & DIN(52) & DIN(27) & DIN(6) & DIN(13) & DIN(50) & DIN(43) & DIN(20) & DIN(30) & DIN(41) & DIN(24) & DIN(23) & DIN(5) & DIN(29) & DIN(37) & DIN(26) & DIN(35) & DIN(24) & DIN(49) & DIN(55) & DIN(13) & DIN(50) & DIN(38) & DIN(26) & DIN(9) & DIN(31) & DIN(51) & DIN(35) & DIN(46) & DIN(26) & DIN(54) & DIN(13) & DIN(39) & DIN(40) & DIN(27) & DIN(56) & DIN(20) & DIN(2) & DIN(60) & DIN(6) & DIN(35) & DIN(59) & DIN(50) & DIN(43) & DIN(58) & DIN(13) & DIN(41) & DIN(44) & DIN(10) & DIN(63) & DIN(17) & DIN(51) & DIN(41) & DIN(6) & DIN(39); inst1_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init1, DOUT => DOUT(1) ); init1 <= DIN(51) & DIN(49) & DIN(43) & DIN(49) & DIN(21) & DIN(15) & DIN(25) & DIN(40) & DIN(59) & DIN(28) & DIN(57) & DIN(9) & DIN(33) & DIN(62) & DIN(24) & DIN(53) & DIN(20) & DIN(60) & DIN(60) & DIN(5) & DIN(38) & DIN(17) & DIN(41) & DIN(59) & DIN(58) & DIN(42) & DIN(58) & DIN(59) & DIN(3) & DIN(62) & DIN(26) & DIN(2) & DIN(28) & DIN(27) & DIN(24) & DIN(44) & DIN(20) & DIN(60) & DIN(47) & DIN(50) & DIN(59) & DIN(59) & DIN(48) & DIN(44) & DIN(42) & DIN(28) & DIN(56) & DIN(15) & DIN(22) & DIN(43) & DIN(28) & DIN(42) & DIN(23) & DIN(62) & DIN(1) & DIN(62) & DIN(39) & DIN(60) & DIN(33) & DIN(1) & DIN(33) & DIN(62) & DIN(41) & DIN(48); inst2_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init2, DOUT => DOUT(2) ); init2 <= DIN(53) & DIN(61) & DIN(27) & DIN(58) & DIN(25) & DIN(34) & DIN(47) & DIN(59) & DIN(28) & DIN(21) & DIN(7) & DIN(8) & DIN(16) & DIN(35) & DIN(13) & DIN(51) & DIN(59) & DIN(47) & DIN(16) & DIN(27) & DIN(50) & DIN(44) & DIN(20) & DIN(42) & DIN(28) & DIN(9) & DIN(30) & DIN(17) & DIN(36) & DIN(36) & DIN(48) & DIN(59) & DIN(35) & DIN(57) & DIN(11) & DIN(30) & DIN(5) & DIN(26) & DIN(51) & DIN(20) & DIN(5) & DIN(36) & DIN(59) & DIN(28) & DIN(40) & DIN(30) & DIN(35) & DIN(31) & DIN(61) & DIN(36) & DIN(7) & DIN(8) & DIN(16) & DIN(11) & DIN(11) & DIN(10) & DIN(37) & DIN(58) & DIN(33) & DIN(41) & DIN(0) & DIN(55) & DIN(47) & DIN(5); inst3_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init3, DOUT => DOUT(3) ); init3 <= DIN(41) & DIN(14) & DIN(2) & DIN(61) & DIN(9) & DIN(21) & DIN(50) & DIN(15) & DIN(30) & DIN(36) & DIN(48) & DIN(34) & DIN(47) & DIN(51) & DIN(20) & DIN(54) & DIN(19) & DIN(28) & DIN(4) & DIN(59) & DIN(51) & DIN(53) & DIN(48) & DIN(62) & DIN(34) & DIN(21) & DIN(26) & DIN(42) & DIN(43) & DIN(33) & DIN(6) & DIN(44) & DIN(5) & DIN(44) & DIN(11) & DIN(58) & DIN(55) & DIN(14) & DIN(31) & DIN(60) & DIN(52) & DIN(61) & DIN(13) & DIN(57) & DIN(32) & DIN(56) & DIN(50) & DIN(24) & DIN(40) & DIN(14) & DIN(10) & DIN(53) & DIN(19) & DIN(27) & DIN(36) & DIN(56) & DIN(41) & DIN(56) & DIN(35) & DIN(63) & DIN(28) & DIN(26) & DIN(33) & DIN(11); inst4_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init4, DOUT => DOUT(4) ); init4 <= DIN(3) & DIN(6) & DIN(58) & DIN(32) & DIN(57) & DIN(11) & DIN(44) & DIN(52) & DIN(4) & DIN(7) & DIN(50) & DIN(59) & DIN(44) & DIN(5) & DIN(35) & DIN(32) & DIN(54) & DIN(48) & DIN(4) & DIN(10) & DIN(44) & DIN(28) & DIN(50) & DIN(30) & DIN(7) & DIN(54) & DIN(20) & DIN(45) & DIN(45) & DIN(63) & DIN(4) & DIN(35) & DIN(13) & DIN(47) & DIN(51) & DIN(4) & DIN(6) & DIN(37) & DIN(2) & DIN(9) & DIN(27) & DIN(45) & DIN(23) & DIN(12) & DIN(14) & DIN(51) & DIN(27) & DIN(44) & DIN(4) & DIN(40) & DIN(24) & DIN(14) & DIN(21) & DIN(60) & DIN(10) & DIN(26) & DIN(8) & DIN(20) & DIN(41) & DIN(10) & DIN(50) & DIN(20) & DIN(48) & DIN(8); inst5_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init5, DOUT => DOUT(5) ); init5 <= DIN(37) & DIN(41) & DIN(60) & DIN(27) & DIN(46) & DIN(4) & DIN(23) & DIN(50) & DIN(16) & DIN(25) & DIN(49) & DIN(59) & DIN(20) & DIN(58) & DIN(19) & DIN(4) & DIN(8) & DIN(51) & DIN(37) & DIN(17) & DIN(62) & DIN(12) & DIN(62) & DIN(42) & DIN(41) & DIN(26) & DIN(26) & DIN(16) & DIN(35) & DIN(38) & DIN(41) & DIN(9) & DIN(58) & DIN(56) & DIN(4) & DIN(60) & DIN(52) & DIN(62) & DIN(1) & DIN(20) & DIN(5) & DIN(54) & DIN(40) & DIN(16) & DIN(50) & DIN(32) & DIN(30) & DIN(55) & DIN(52) & DIN(25) & DIN(19) & DIN(20) & DIN(35) & DIN(35) & DIN(16) & DIN(25) & DIN(55) & DIN(51) & DIN(39) & DIN(25) & DIN(44) & DIN(49) & DIN(5) & DIN(62); inst6_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init6, DOUT => DOUT(6) ); init6 <= DIN(59) & DIN(60) & DIN(0) & DIN(60) & DIN(49) & DIN(38) & DIN(12) & DIN(12) & DIN(49) & DIN(5) & DIN(36) & DIN(23) & DIN(44) & DIN(0) & DIN(21) & DIN(6) & DIN(44) & DIN(45) & DIN(17) & DIN(19) & DIN(25) & DIN(23) & DIN(14) & DIN(9) & DIN(37) & DIN(60) & DIN(30) & DIN(4) & DIN(41) & DIN(0) & DIN(34) & DIN(63) & DIN(10) & DIN(26) & DIN(48) & DIN(37) & DIN(53) & DIN(7) & DIN(40) & DIN(25) & DIN(24) & DIN(36) & DIN(2) & DIN(38) & DIN(20) & DIN(40) & DIN(53) & DIN(24) & DIN(20) & DIN(58) & DIN(5) & DIN(16) & DIN(50) & DIN(18) & DIN(42) & DIN(32) & DIN(19) & DIN(30) & DIN(34) & DIN(41) & DIN(53) & DIN(8) & DIN(15) & DIN(37); inst7_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init7, DOUT => DOUT(7) ); init7 <= DIN(31) & DIN(52) & DIN(1) & DIN(22) & DIN(37) & DIN(17) & DIN(9) & DIN(55) & DIN(29) & DIN(56) & DIN(10) & DIN(37) & DIN(24) & DIN(2) & DIN(57) & DIN(5) & DIN(44) & DIN(18) & DIN(22) & DIN(45) & DIN(24) & DIN(39) & DIN(3) & DIN(36) & DIN(36) & DIN(7) & DIN(1) & DIN(53) & DIN(35) & DIN(54) & DIN(20) & DIN(9) & DIN(15) & DIN(47) & DIN(13) & DIN(45) & DIN(52) & DIN(17) & DIN(45) & DIN(56) & DIN(31) & DIN(7) & DIN(44) & DIN(19) & DIN(22) & DIN(39) & DIN(47) & DIN(63) & DIN(58) & DIN(47) & DIN(41) & DIN(52) & DIN(3) & DIN(60) & DIN(34) & DIN(47) & DIN(35) & DIN(11) & DIN(33) & DIN(26) & DIN(38) & DIN(36) & DIN(60) & DIN(34); inst8_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init8, DOUT => DOUT(8) ); init8 <= DIN(63) & DIN(1) & DIN(6) & DIN(17) & DIN(35) & DIN(5) & DIN(13) & DIN(25) & DIN(36) & DIN(62) & DIN(17) & DIN(24) & DIN(20) & DIN(26) & DIN(22) & DIN(34) & DIN(0) & DIN(11) & DIN(57) & DIN(12) & DIN(25) & DIN(19) & DIN(18) & DIN(45) & DIN(25) & DIN(42) & DIN(23) & DIN(12) & DIN(26) & DIN(40) & DIN(3) & DIN(46) & DIN(30) & DIN(0) & DIN(3) & DIN(9) & DIN(33) & DIN(15) & DIN(8) & DIN(11) & DIN(42) & DIN(55) & DIN(2) & DIN(50) & DIN(25) & DIN(10) & DIN(40) & DIN(52) & DIN(50) & DIN(38) & DIN(58) & DIN(44) & DIN(58) & DIN(40) & DIN(22) & DIN(13) & DIN(16) & DIN(46) & DIN(9) & DIN(44) & DIN(10) & DIN(2) & DIN(42) & DIN(21); inst9_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init9, DOUT => DOUT(9) ); init9 <= DIN(60) & DIN(36) & DIN(27) & DIN(7) & DIN(42) & DIN(12) & DIN(60) & DIN(57) & DIN(61) & DIN(50) & DIN(14) & DIN(62) & DIN(12) & DIN(41) & DIN(13) & DIN(63) & DIN(39) & DIN(27) & DIN(3) & DIN(62) & DIN(61) & DIN(33) & DIN(43) & DIN(1) & DIN(63) & DIN(36) & DIN(62) & DIN(42) & DIN(54) & DIN(15) & DIN(39) & DIN(53) & DIN(58) & DIN(14) & DIN(11) & DIN(49) & DIN(15) & DIN(9) & DIN(43) & DIN(62) & DIN(38) & DIN(37) & DIN(49) & DIN(13) & DIN(1) & DIN(50) & DIN(60) & DIN(41) & DIN(30) & DIN(34) & DIN(19) & DIN(60) & DIN(33) & DIN(7) & DIN(2) & DIN(21) & DIN(46) & DIN(47) & DIN(3) & DIN(1) & DIN(21) & DIN(25) & DIN(42) & DIN(9); inst10_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init10, DOUT => DOUT(10) ); init10 <= DIN(12) & DIN(30) & DIN(23) & DIN(48) & DIN(31) & DIN(10) & DIN(9) & DIN(35) & DIN(57) & DIN(6) & DIN(2) & DIN(47) & DIN(45) & DIN(46) & DIN(33) & DIN(14) & DIN(22) & DIN(5) & DIN(62) & DIN(61) & DIN(54) & DIN(22) & DIN(50) & DIN(37) & DIN(22) & DIN(1) & DIN(24) & DIN(21) & DIN(14) & DIN(43) & DIN(63) & DIN(27) & DIN(62) & DIN(13) & DIN(39) & DIN(60) & DIN(17) & DIN(3) & DIN(33) & DIN(10) & DIN(24) & DIN(20) & DIN(14) & DIN(31) & DIN(23) & DIN(27) & DIN(16) & DIN(25) & DIN(15) & DIN(39) & DIN(11) & DIN(16) & DIN(0) & DIN(48) & DIN(13) & DIN(1) & DIN(51) & DIN(44) & DIN(22) & DIN(50) & DIN(45) & DIN(50) & DIN(52) & DIN(2); inst11_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init11, DOUT => DOUT(11) ); init11 <= DIN(40) & DIN(42) & DIN(59) & DIN(44) & DIN(40) & DIN(30) & DIN(57) & DIN(59) & DIN(12) & DIN(36) & DIN(38) & DIN(43) & DIN(46) & DIN(26) & DIN(19) & DIN(28) & DIN(8) & DIN(1) & DIN(13) & DIN(36) & DIN(29) & DIN(43) & DIN(34) & DIN(7) & DIN(32) & DIN(37) & DIN(47) & DIN(19) & DIN(30) & DIN(45) & DIN(55) & DIN(60) & DIN(2) & DIN(29) & DIN(51) & DIN(44) & DIN(17) & DIN(21) & DIN(21) & DIN(33) & DIN(53) & DIN(11) & DIN(24) & DIN(18) & DIN(18) & DIN(18) & DIN(15) & DIN(35) & DIN(36) & DIN(33) & DIN(2) & DIN(22) & DIN(11) & DIN(61) & DIN(24) & DIN(13) & DIN(7) & DIN(1) & DIN(27) & DIN(33) & DIN(43) & DIN(26) & DIN(9) & DIN(22); inst12_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init12, DOUT => DOUT(12) ); init12 <= DIN(19) & DIN(28) & DIN(43) & DIN(50) & DIN(24) & DIN(15) & DIN(42) & DIN(6) & DIN(28) & DIN(12) & DIN(48) & DIN(21) & DIN(22) & DIN(56) & DIN(7) & DIN(27) & DIN(13) & DIN(29) & DIN(7) & DIN(13) & DIN(34) & DIN(13) & DIN(32) & DIN(3) & DIN(27) & DIN(53) & DIN(49) & DIN(13) & DIN(39) & DIN(10) & DIN(34) & DIN(32) & DIN(4) & DIN(27) & DIN(8) & DIN(17) & DIN(51) & DIN(30) & DIN(22) & DIN(7) & DIN(54) & DIN(56) & DIN(14) & DIN(58) & DIN(43) & DIN(42) & DIN(20) & DIN(0) & DIN(59) & DIN(58) & DIN(44) & DIN(31) & DIN(50) & DIN(43) & DIN(18) & DIN(13) & DIN(14) & DIN(38) & DIN(43) & DIN(7) & DIN(6) & DIN(6) & DIN(24) & DIN(51); inst13_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init13, DOUT => DOUT(13) ); init13 <= DIN(0) & DIN(59) & DIN(41) & DIN(10) & DIN(31) & DIN(51) & DIN(60) & DIN(17) & DIN(15) & DIN(10) & DIN(45) & DIN(30) & DIN(48) & DIN(25) & DIN(23) & DIN(28) & DIN(34) & DIN(28) & DIN(57) & DIN(0) & DIN(55) & DIN(15) & DIN(37) & DIN(46) & DIN(49) & DIN(40) & DIN(43) & DIN(33) & DIN(13) & DIN(54) & DIN(49) & DIN(53) & DIN(27) & DIN(54) & DIN(14) & DIN(14) & DIN(35) & DIN(50) & DIN(35) & DIN(49) & DIN(26) & DIN(20) & DIN(7) & DIN(19) & DIN(55) & DIN(59) & DIN(35) & DIN(34) & DIN(37) & DIN(42) & DIN(26) & DIN(9) & DIN(29) & DIN(61) & DIN(2) & DIN(16) & DIN(27) & DIN(53) & DIN(48) & DIN(24) & DIN(26) & DIN(58) & DIN(39) & DIN(13); inst14_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init14, DOUT => DOUT(14) ); init14 <= DIN(1) & DIN(9) & DIN(2) & DIN(32) & DIN(46) & DIN(47) & DIN(48) & DIN(46) & DIN(29) & DIN(59) & DIN(23) & DIN(21) & DIN(38) & DIN(51) & DIN(9) & DIN(33) & DIN(30) & DIN(7) & DIN(10) & DIN(40) & DIN(53) & DIN(13) & DIN(10) & DIN(63) & DIN(49) & DIN(8) & DIN(3) & DIN(22) & DIN(61) & DIN(22) & DIN(32) & DIN(33) & DIN(27) & DIN(18) & DIN(48) & DIN(0) & DIN(18) & DIN(53) & DIN(23) & DIN(8) & DIN(21) & DIN(36) & DIN(12) & DIN(4) & DIN(20) & DIN(2) & DIN(23) & DIN(54) & DIN(18) & DIN(61) & DIN(30) & DIN(53) & DIN(27) & DIN(2) & DIN(60) & DIN(27) & DIN(10) & DIN(45) & DIN(54) & DIN(28) & DIN(59) & DIN(13) & DIN(49) & DIN(26); inst15_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init15, DOUT => DOUT(15) ); init15 <= DIN(42) & DIN(39) & DIN(21) & DIN(2) & DIN(57) & DIN(63) & DIN(58) & DIN(46) & DIN(42) & DIN(60) & DIN(36) & DIN(53) & DIN(44) & DIN(10) & DIN(49) & DIN(10) & DIN(13) & DIN(41) & DIN(63) & DIN(37) & DIN(6) & DIN(39) & DIN(6) & DIN(5) & DIN(45) & DIN(46) & DIN(15) & DIN(28) & DIN(11) & DIN(37) & DIN(21) & DIN(40) & DIN(45) & DIN(22) & DIN(8) & DIN(11) & DIN(21) & DIN(62) & DIN(9) & DIN(52) & DIN(16) & DIN(26) & DIN(4) & DIN(34) & DIN(61) & DIN(8) & DIN(11) & DIN(40) & DIN(34) & DIN(24) & DIN(31) & DIN(1) & DIN(57) & DIN(24) & DIN(54) & DIN(17) & DIN(35) & DIN(41) & DIN(7) & DIN(35) & DIN(56) & DIN(63) & DIN(32) & DIN(34); inst16_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init16, DOUT => DOUT(16) ); init16 <= DIN(17) & DIN(47) & DIN(29) & DIN(41) & DIN(14) & DIN(41) & DIN(13) & DIN(24) & DIN(31) & DIN(25) & DIN(55) & DIN(23) & DIN(30) & DIN(22) & DIN(10) & DIN(17) & DIN(30) & DIN(57) & DIN(40) & DIN(28) & DIN(20) & DIN(10) & DIN(12) & DIN(57) & DIN(58) & DIN(36) & DIN(29) & DIN(15) & DIN(3) & DIN(40) & DIN(42) & DIN(40) & DIN(33) & DIN(52) & DIN(27) & DIN(54) & DIN(10) & DIN(52) & DIN(32) & DIN(7) & DIN(59) & DIN(33) & DIN(13) & DIN(13) & DIN(55) & DIN(17) & DIN(40) & DIN(2) & DIN(37) & DIN(30) & DIN(16) & DIN(27) & DIN(16) & DIN(39) & DIN(28) & DIN(43) & DIN(33) & DIN(53) & DIN(36) & DIN(27) & DIN(7) & DIN(54) & DIN(12) & DIN(43); inst17_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init17, DOUT => DOUT(17) ); init17 <= DIN(32) & DIN(54) & DIN(23) & DIN(38) & DIN(42) & DIN(3) & DIN(4) & DIN(38) & DIN(1) & DIN(16) & DIN(0) & DIN(39) & DIN(43) & DIN(2) & DIN(27) & DIN(29) & DIN(36) & DIN(40) & DIN(7) & DIN(29) & DIN(19) & DIN(7) & DIN(32) & DIN(15) & DIN(38) & DIN(29) & DIN(52) & DIN(33) & DIN(47) & DIN(35) & DIN(40) & DIN(58) & DIN(12) & DIN(19) & DIN(34) & DIN(4) & DIN(2) & DIN(51) & DIN(38) & DIN(25) & DIN(37) & DIN(61) & DIN(12) & DIN(13) & DIN(30) & DIN(51) & DIN(22) & DIN(7) & DIN(21) & DIN(0) & DIN(60) & DIN(4) & DIN(33) & DIN(3) & DIN(27) & DIN(5) & DIN(46) & DIN(17) & DIN(57) & DIN(53) & DIN(23) & DIN(20) & DIN(23) & DIN(8); inst18_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init18, DOUT => DOUT(18) ); init18 <= DIN(2) & DIN(34) & DIN(0) & DIN(16) & DIN(43) & DIN(7) & DIN(55) & DIN(52) & DIN(47) & DIN(21) & DIN(19) & DIN(61) & DIN(30) & DIN(54) & DIN(15) & DIN(13) & DIN(26) & DIN(49) & DIN(60) & DIN(38) & DIN(63) & DIN(45) & DIN(13) & DIN(42) & DIN(3) & DIN(28) & DIN(28) & DIN(53) & DIN(63) & DIN(22) & DIN(8) & DIN(50) & DIN(54) & DIN(57) & DIN(24) & DIN(55) & DIN(24) & DIN(34) & DIN(32) & DIN(50) & DIN(55) & DIN(29) & DIN(46) & DIN(17) & DIN(28) & DIN(29) & DIN(17) & DIN(52) & DIN(50) & DIN(14) & DIN(25) & DIN(21) & DIN(42) & DIN(48) & DIN(13) & DIN(13) & DIN(29) & DIN(6) & DIN(45) & DIN(13) & DIN(32) & DIN(15) & DIN(25) & DIN(63); inst19_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init19, DOUT => DOUT(19) ); init19 <= DIN(56) & DIN(53) & DIN(26) & DIN(9) & DIN(58) & DIN(37) & DIN(18) & DIN(7) & DIN(50) & DIN(61) & DIN(21) & DIN(15) & DIN(19) & DIN(43) & DIN(35) & DIN(30) & DIN(47) & DIN(13) & DIN(60) & DIN(49) & DIN(21) & DIN(16) & DIN(1) & DIN(42) & DIN(63) & DIN(3) & DIN(59) & DIN(20) & DIN(4) & DIN(58) & DIN(54) & DIN(47) & DIN(59) & DIN(53) & DIN(55) & DIN(50) & DIN(51) & DIN(21) & DIN(50) & DIN(35) & DIN(41) & DIN(42) & DIN(43) & DIN(53) & DIN(59) & DIN(22) & DIN(34) & DIN(62) & DIN(56) & DIN(43) & DIN(47) & DIN(43) & DIN(17) & DIN(62) & DIN(47) & DIN(43) & DIN(63) & DIN(1) & DIN(30) & DIN(21) & DIN(62) & DIN(1) & DIN(56) & DIN(9); inst20_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init20, DOUT => DOUT(20) ); init20 <= DIN(43) & DIN(28) & DIN(12) & DIN(33) & DIN(47) & DIN(25) & DIN(7) & DIN(19) & DIN(30) & DIN(35) & DIN(17) & DIN(45) & DIN(56) & DIN(52) & DIN(13) & DIN(21) & DIN(9) & DIN(43) & DIN(8) & DIN(45) & DIN(28) & DIN(37) & DIN(53) & DIN(43) & DIN(50) & DIN(10) & DIN(54) & DIN(48) & DIN(52) & DIN(17) & DIN(48) & DIN(9) & DIN(44) & DIN(51) & DIN(26) & DIN(28) & DIN(58) & DIN(36) & DIN(2) & DIN(49) & DIN(42) & DIN(29) & DIN(31) & DIN(35) & DIN(43) & DIN(34) & DIN(13) & DIN(28) & DIN(15) & DIN(34) & DIN(56) & DIN(49) & DIN(51) & DIN(43) & DIN(53) & DIN(2) & DIN(21) & DIN(36) & DIN(0) & DIN(43) & DIN(37) & DIN(61) & DIN(47) & DIN(16); inst21_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init21, DOUT => DOUT(21) ); init21 <= DIN(48) & DIN(38) & DIN(35) & DIN(8) & DIN(22) & DIN(17) & DIN(13) & DIN(3) & DIN(43) & DIN(47) & DIN(59) & DIN(38) & DIN(0) & DIN(13) & DIN(40) & DIN(36) & DIN(61) & DIN(14) & DIN(26) & DIN(26) & DIN(44) & DIN(5) & DIN(4) & DIN(31) & DIN(57) & DIN(26) & DIN(27) & DIN(26) & DIN(11) & DIN(60) & DIN(49) & DIN(40) & DIN(15) & DIN(17) & DIN(58) & DIN(19) & DIN(38) & DIN(30) & DIN(7) & DIN(5) & DIN(47) & DIN(46) & DIN(61) & DIN(27) & DIN(16) & DIN(26) & DIN(10) & DIN(35) & DIN(34) & DIN(21) & DIN(21) & DIN(12) & DIN(12) & DIN(42) & DIN(4) & DIN(30) & DIN(14) & DIN(31) & DIN(41) & DIN(35) & DIN(44) & DIN(31) & DIN(45) & DIN(60); inst22_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init22, DOUT => DOUT(22) ); init22 <= DIN(11) & DIN(6) & DIN(11) & DIN(48) & DIN(45) & DIN(43) & DIN(55) & DIN(41) & DIN(59) & DIN(36) & DIN(7) & DIN(19) & DIN(39) & DIN(55) & DIN(57) & DIN(46) & DIN(18) & DIN(13) & DIN(48) & DIN(19) & DIN(34) & DIN(63) & DIN(61) & DIN(27) & DIN(11) & DIN(52) & DIN(46) & DIN(49) & DIN(24) & DIN(7) & DIN(27) & DIN(27) & DIN(24) & DIN(32) & DIN(57) & DIN(4) & DIN(48) & DIN(19) & DIN(33) & DIN(40) & DIN(60) & DIN(16) & DIN(26) & DIN(57) & DIN(37) & DIN(43) & DIN(62) & DIN(63) & DIN(43) & DIN(49) & DIN(22) & DIN(7) & DIN(52) & DIN(8) & DIN(44) & DIN(26) & DIN(28) & DIN(39) & DIN(21) & DIN(61) & DIN(46) & DIN(59) & DIN(34) & DIN(20); inst23_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init23, DOUT => DOUT(23) ); init23 <= DIN(6) & DIN(61) & DIN(0) & DIN(35) & DIN(17) & DIN(3) & DIN(13) & DIN(12) & DIN(16) & DIN(61) & DIN(19) & DIN(14) & DIN(26) & DIN(5) & DIN(2) & DIN(33) & DIN(50) & DIN(27) & DIN(47) & DIN(51) & DIN(27) & DIN(52) & DIN(45) & DIN(9) & DIN(12) & DIN(53) & DIN(39) & DIN(56) & DIN(30) & DIN(4) & DIN(32) & DIN(35) & DIN(44) & DIN(61) & DIN(22) & DIN(5) & DIN(50) & DIN(16) & DIN(57) & DIN(2) & DIN(34) & DIN(14) & DIN(11) & DIN(57) & DIN(18) & DIN(39) & DIN(50) & DIN(63) & DIN(0) & DIN(58) & DIN(6) & DIN(18) & DIN(40) & DIN(56) & DIN(34) & DIN(20) & DIN(22) & DIN(35) & DIN(23) & DIN(59) & DIN(24) & DIN(35) & DIN(13) & DIN(39); inst24_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init24, DOUT => DOUT(24) ); init24 <= DIN(18) & DIN(31) & DIN(54) & DIN(48) & DIN(50) & DIN(62) & DIN(15) & DIN(38) & DIN(13) & DIN(44) & DIN(26) & DIN(62) & DIN(27) & DIN(18) & DIN(61) & DIN(22) & DIN(26) & DIN(56) & DIN(36) & DIN(48) & DIN(14) & DIN(55) & DIN(8) & DIN(5) & DIN(60) & DIN(60) & DIN(43) & DIN(53) & DIN(10) & DIN(6) & DIN(28) & DIN(34) & DIN(45) & DIN(55) & DIN(32) & DIN(12) & DIN(49) & DIN(35) & DIN(11) & DIN(14) & DIN(17) & DIN(8) & DIN(1) & DIN(5) & DIN(56) & DIN(4) & DIN(50) & DIN(42) & DIN(42) & DIN(45) & DIN(39) & DIN(9) & DIN(58) & DIN(12) & DIN(26) & DIN(7) & DIN(49) & DIN(37) & DIN(25) & DIN(40) & DIN(25) & DIN(36) & DIN(1) & DIN(33); inst25_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init25, DOUT => DOUT(25) ); init25 <= DIN(35) & DIN(29) & DIN(41) & DIN(48) & DIN(49) & DIN(27) & DIN(33) & DIN(23) & DIN(31) & DIN(50) & DIN(51) & DIN(19) & DIN(52) & DIN(14) & DIN(22) & DIN(29) & DIN(53) & DIN(6) & DIN(32) & DIN(27) & DIN(17) & DIN(53) & DIN(62) & DIN(50) & DIN(36) & DIN(26) & DIN(55) & DIN(3) & DIN(4) & DIN(51) & DIN(42) & DIN(51) & DIN(44) & DIN(14) & DIN(14) & DIN(26) & DIN(60) & DIN(47) & DIN(36) & DIN(12) & DIN(61) & DIN(37) & DIN(60) & DIN(23) & DIN(24) & DIN(16) & DIN(61) & DIN(26) & DIN(53) & DIN(43) & DIN(29) & DIN(31) & DIN(17) & DIN(36) & DIN(59) & DIN(33) & DIN(22) & DIN(4) & DIN(24) & DIN(16) & DIN(7) & DIN(28) & DIN(37) & DIN(18); inst26_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init26, DOUT => DOUT(26) ); init26 <= DIN(23) & DIN(55) & DIN(4) & DIN(13) & DIN(4) & DIN(60) & DIN(20) & DIN(37) & DIN(24) & DIN(57) & DIN(46) & DIN(35) & DIN(15) & DIN(19) & DIN(16) & DIN(60) & DIN(22) & DIN(47) & DIN(29) & DIN(45) & DIN(3) & DIN(12) & DIN(26) & DIN(51) & DIN(49) & DIN(13) & DIN(4) & DIN(49) & DIN(18) & DIN(9) & DIN(47) & DIN(10) & DIN(51) & DIN(8) & DIN(57) & DIN(31) & DIN(36) & DIN(27) & DIN(54) & DIN(52) & DIN(42) & DIN(27) & DIN(19) & DIN(18) & DIN(60) & DIN(33) & DIN(31) & DIN(41) & DIN(44) & DIN(17) & DIN(19) & DIN(15) & DIN(27) & DIN(12) & DIN(47) & DIN(0) & DIN(59) & DIN(58) & DIN(1) & DIN(8) & DIN(22) & DIN(39) & DIN(17) & DIN(19); inst27_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init27, DOUT => DOUT(27) ); init27 <= DIN(46) & DIN(5) & DIN(19) & DIN(54) & DIN(25) & DIN(21) & DIN(62) & DIN(33) & DIN(47) & DIN(62) & DIN(46) & DIN(22) & DIN(3) & DIN(55) & DIN(17) & DIN(44) & DIN(24) & DIN(6) & DIN(4) & DIN(28) & DIN(9) & DIN(47) & DIN(49) & DIN(9) & DIN(49) & DIN(54) & DIN(39) & DIN(31) & DIN(61) & DIN(17) & DIN(40) & DIN(56) & DIN(44) & DIN(62) & DIN(55) & DIN(56) & DIN(38) & DIN(0) & DIN(51) & DIN(25) & DIN(59) & DIN(55) & DIN(4) & DIN(22) & DIN(31) & DIN(11) & DIN(40) & DIN(59) & DIN(60) & DIN(21) & DIN(43) & DIN(0) & DIN(62) & DIN(59) & DIN(34) & DIN(17) & DIN(56) & DIN(22) & DIN(55) & DIN(5) & DIN(37) & DIN(42) & DIN(1) & DIN(52); inst28_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init28, DOUT => DOUT(28) ); init28 <= DIN(62) & DIN(44) & DIN(30) & DIN(58) & DIN(27) & DIN(13) & DIN(13) & DIN(5) & DIN(42) & DIN(37) & DIN(2) & DIN(62) & DIN(22) & DIN(21) & DIN(16) & DIN(41) & DIN(23) & DIN(32) & DIN(42) & DIN(47) & DIN(52) & DIN(34) & DIN(25) & DIN(52) & DIN(50) & DIN(8) & DIN(56) & DIN(31) & DIN(1) & DIN(44) & DIN(61) & DIN(4) & DIN(17) & DIN(17) & DIN(45) & DIN(22) & DIN(34) & DIN(40) & DIN(2) & DIN(44) & DIN(14) & DIN(45) & DIN(46) & DIN(45) & DIN(62) & DIN(47) & DIN(63) & DIN(40) & DIN(44) & DIN(8) & DIN(22) & DIN(0) & DIN(48) & DIN(16) & DIN(59) & DIN(19) & DIN(7) & DIN(12) & DIN(34) & DIN(61) & DIN(27) & DIN(44) & DIN(22) & DIN(59); inst29_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init29, DOUT => DOUT(29) ); init29 <= DIN(31) & DIN(42) & DIN(56) & DIN(57) & DIN(18) & DIN(20) & DIN(44) & DIN(20) & DIN(46) & DIN(12) & DIN(53) & DIN(2) & DIN(6) & DIN(34) & DIN(36) & DIN(6) & DIN(58) & DIN(42) & DIN(8) & DIN(16) & DIN(7) & DIN(31) & DIN(54) & DIN(14) & DIN(14) & DIN(61) & DIN(63) & DIN(45) & DIN(55) & DIN(18) & DIN(36) & DIN(38) & DIN(24) & DIN(36) & DIN(13) & DIN(61) & DIN(38) & DIN(32) & DIN(31) & DIN(43) & DIN(5) & DIN(18) & DIN(30) & DIN(0) & DIN(40) & DIN(57) & DIN(62) & DIN(42) & DIN(35) & DIN(40) & DIN(26) & DIN(57) & DIN(17) & DIN(57) & DIN(15) & DIN(33) & DIN(5) & DIN(44) & DIN(8) & DIN(17) & DIN(58) & DIN(0) & DIN(25) & DIN(27); inst30_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init30, DOUT => DOUT(30) ); init30 <= DIN(55) & DIN(29) & DIN(33) & DIN(60) & DIN(35) & DIN(3) & DIN(62) & DIN(6) & DIN(4) & DIN(42) & DIN(33) & DIN(63) & DIN(41) & DIN(17) & DIN(39) & DIN(60) & DIN(46) & DIN(26) & DIN(4) & DIN(14) & DIN(20) & DIN(46) & DIN(18) & DIN(20) & DIN(19) & DIN(1) & DIN(28) & DIN(9) & DIN(55) & DIN(4) & DIN(53) & DIN(59) & DIN(58) & DIN(30) & DIN(62) & DIN(29) & DIN(62) & DIN(19) & DIN(36) & DIN(5) & DIN(1) & DIN(16) & DIN(24) & DIN(45) & DIN(34) & DIN(12) & DIN(56) & DIN(32) & DIN(6) & DIN(21) & DIN(60) & DIN(0) & DIN(27) & DIN(17) & DIN(56) & DIN(10) & DIN(10) & DIN(24) & DIN(20) & DIN(60) & DIN(10) & DIN(23) & DIN(61) & DIN(29); inst31_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init31, DOUT => DOUT(31) ); init31 <= DIN(51) & DIN(47) & DIN(35) & DIN(27) & DIN(9) & DIN(62) & DIN(36) & DIN(57) & DIN(15) & DIN(10) & DIN(10) & DIN(29) & DIN(19) & DIN(30) & DIN(40) & DIN(34) & DIN(55) & DIN(30) & DIN(18) & DIN(15) & DIN(61) & DIN(20) & DIN(14) & DIN(24) & DIN(4) & DIN(39) & DIN(55) & DIN(2) & DIN(21) & DIN(5) & DIN(19) & DIN(24) & DIN(38) & DIN(37) & DIN(55) & DIN(16) & DIN(46) & DIN(26) & DIN(47) & DIN(50) & DIN(55) & DIN(44) & DIN(52) & DIN(49) & DIN(39) & DIN(10) & DIN(15) & DIN(40) & DIN(33) & DIN(62) & DIN(1) & DIN(37) & DIN(16) & DIN(38) & DIN(33) & DIN(1) & DIN(18) & DIN(50) & DIN(47) & DIN(61) & DIN(31) & DIN(46) & DIN(33) & DIN(22); inst32_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init32, DOUT => DOUT(32) ); init32 <= DIN(54) & DIN(36) & DIN(58) & DIN(34) & DIN(22) & DIN(37) & DIN(2) & DIN(63) & DIN(3) & DIN(18) & DIN(11) & DIN(60) & DIN(44) & DIN(22) & DIN(25) & DIN(63) & DIN(48) & DIN(0) & DIN(28) & DIN(39) & DIN(58) & DIN(24) & DIN(6) & DIN(22) & DIN(11) & DIN(4) & DIN(5) & DIN(13) & DIN(0) & DIN(7) & DIN(29) & DIN(20) & DIN(14) & DIN(21) & DIN(31) & DIN(23) & DIN(34) & DIN(48) & DIN(51) & DIN(7) & DIN(38) & DIN(53) & DIN(35) & DIN(45) & DIN(38) & DIN(25) & DIN(34) & DIN(9) & DIN(6) & DIN(4) & DIN(32) & DIN(36) & DIN(13) & DIN(2) & DIN(17) & DIN(62) & DIN(4) & DIN(61) & DIN(48) & DIN(44) & DIN(57) & DIN(8) & DIN(52) & DIN(55); inst33_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init33, DOUT => DOUT(33) ); init33 <= DIN(46) & DIN(56) & DIN(31) & DIN(16) & DIN(36) & DIN(33) & DIN(30) & DIN(41) & DIN(25) & DIN(15) & DIN(40) & DIN(51) & DIN(23) & DIN(12) & DIN(15) & DIN(29) & DIN(52) & DIN(62) & DIN(47) & DIN(25) & DIN(25) & DIN(23) & DIN(23) & DIN(51) & DIN(47) & DIN(21) & DIN(42) & DIN(46) & DIN(14) & DIN(57) & DIN(52) & DIN(30) & DIN(19) & DIN(62) & DIN(50) & DIN(59) & DIN(8) & DIN(14) & DIN(1) & DIN(38) & DIN(56) & DIN(27) & DIN(35) & DIN(57) & DIN(24) & DIN(17) & DIN(46) & DIN(27) & DIN(37) & DIN(24) & DIN(2) & DIN(38) & DIN(40) & DIN(1) & DIN(9) & DIN(1) & DIN(7) & DIN(49) & DIN(58) & DIN(48) & DIN(37) & DIN(54) & DIN(43) & DIN(24); inst34_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init34, DOUT => DOUT(34) ); init34 <= DIN(27) & DIN(53) & DIN(35) & DIN(57) & DIN(32) & DIN(10) & DIN(8) & DIN(30) & DIN(32) & DIN(15) & DIN(59) & DIN(6) & DIN(58) & DIN(57) & DIN(10) & DIN(15) & DIN(16) & DIN(29) & DIN(11) & DIN(26) & DIN(8) & DIN(20) & DIN(51) & DIN(16) & DIN(18) & DIN(11) & DIN(7) & DIN(40) & DIN(61) & DIN(22) & DIN(22) & DIN(34) & DIN(21) & DIN(25) & DIN(49) & DIN(2) & DIN(42) & DIN(57) & DIN(35) & DIN(26) & DIN(20) & DIN(2) & DIN(60) & DIN(43) & DIN(41) & DIN(44) & DIN(3) & DIN(54) & DIN(21) & DIN(55) & DIN(38) & DIN(56) & DIN(2) & DIN(40) & DIN(8) & DIN(41) & DIN(14) & DIN(49) & DIN(18) & DIN(27) & DIN(1) & DIN(61) & DIN(49) & DIN(19); inst35_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init35, DOUT => DOUT(35) ); init35 <= DIN(29) & DIN(10) & DIN(42) & DIN(42) & DIN(42) & DIN(33) & DIN(2) & DIN(3) & DIN(52) & DIN(15) & DIN(0) & DIN(63) & DIN(60) & DIN(8) & DIN(19) & DIN(7) & DIN(47) & DIN(53) & DIN(13) & DIN(29) & DIN(18) & DIN(12) & DIN(20) & DIN(62) & DIN(27) & DIN(41) & DIN(54) & DIN(4) & DIN(6) & DIN(2) & DIN(32) & DIN(51) & DIN(32) & DIN(8) & DIN(40) & DIN(38) & DIN(45) & DIN(51) & DIN(3) & DIN(52) & DIN(19) & DIN(56) & DIN(44) & DIN(53) & DIN(24) & DIN(29) & DIN(58) & DIN(18) & DIN(35) & DIN(1) & DIN(8) & DIN(20) & DIN(49) & DIN(43) & DIN(8) & DIN(23) & DIN(35) & DIN(52) & DIN(35) & DIN(19) & DIN(34) & DIN(24) & DIN(11) & DIN(57); inst36_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init36, DOUT => DOUT(36) ); init36 <= DIN(20) & DIN(14) & DIN(45) & DIN(26) & DIN(41) & DIN(15) & DIN(43) & DIN(14) & DIN(15) & DIN(7) & DIN(30) & DIN(56) & DIN(12) & DIN(15) & DIN(36) & DIN(21) & DIN(52) & DIN(30) & DIN(31) & DIN(24) & DIN(21) & DIN(48) & DIN(16) & DIN(18) & DIN(49) & DIN(61) & DIN(29) & DIN(15) & DIN(60) & DIN(51) & DIN(2) & DIN(58) & DIN(37) & DIN(30) & DIN(46) & DIN(26) & DIN(0) & DIN(36) & DIN(48) & DIN(22) & DIN(58) & DIN(15) & DIN(20) & DIN(55) & DIN(27) & DIN(5) & DIN(54) & DIN(27) & DIN(9) & DIN(46) & DIN(8) & DIN(2) & DIN(63) & DIN(19) & DIN(53) & DIN(34) & DIN(0) & DIN(41) & DIN(13) & DIN(2) & DIN(14) & DIN(36) & DIN(12) & DIN(10); inst37_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init37, DOUT => DOUT(37) ); init37 <= DIN(34) & DIN(27) & DIN(51) & DIN(4) & DIN(30) & DIN(48) & DIN(39) & DIN(17) & DIN(2) & DIN(24) & DIN(50) & DIN(45) & DIN(50) & DIN(34) & DIN(4) & DIN(26) & DIN(33) & DIN(34) & DIN(33) & DIN(24) & DIN(13) & DIN(54) & DIN(52) & DIN(13) & DIN(0) & DIN(46) & DIN(44) & DIN(34) & DIN(61) & DIN(59) & DIN(20) & DIN(30) & DIN(60) & DIN(3) & DIN(29) & DIN(13) & DIN(46) & DIN(15) & DIN(31) & DIN(20) & DIN(38) & DIN(16) & DIN(41) & DIN(23) & DIN(1) & DIN(34) & DIN(57) & DIN(8) & DIN(21) & DIN(42) & DIN(36) & DIN(0) & DIN(54) & DIN(6) & DIN(33) & DIN(30) & DIN(49) & DIN(48) & DIN(14) & DIN(30) & DIN(63) & DIN(17) & DIN(1) & DIN(47); inst38_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init38, DOUT => DOUT(38) ); init38 <= DIN(12) & DIN(30) & DIN(49) & DIN(28) & DIN(0) & DIN(62) & DIN(2) & DIN(41) & DIN(45) & DIN(3) & DIN(5) & DIN(33) & DIN(34) & DIN(18) & DIN(59) & DIN(19) & DIN(33) & DIN(46) & DIN(54) & DIN(30) & DIN(18) & DIN(59) & DIN(31) & DIN(17) & DIN(33) & DIN(2) & DIN(49) & DIN(32) & DIN(51) & DIN(8) & DIN(18) & DIN(48) & DIN(30) & DIN(51) & DIN(26) & DIN(23) & DIN(16) & DIN(63) & DIN(35) & DIN(12) & DIN(32) & DIN(51) & DIN(37) & DIN(15) & DIN(49) & DIN(13) & DIN(29) & DIN(3) & DIN(27) & DIN(59) & DIN(63) & DIN(1) & DIN(26) & DIN(28) & DIN(32) & DIN(1) & DIN(15) & DIN(41) & DIN(13) & DIN(2) & DIN(41) & DIN(31) & DIN(22) & DIN(7); inst39_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init39, DOUT => DOUT(39) ); init39 <= DIN(49) & DIN(41) & DIN(8) & DIN(11) & DIN(3) & DIN(46) & DIN(11) & DIN(32) & DIN(32) & DIN(41) & DIN(46) & DIN(46) & DIN(8) & DIN(58) & DIN(62) & DIN(15) & DIN(51) & DIN(17) & DIN(28) & DIN(14) & DIN(6) & DIN(60) & DIN(36) & DIN(15) & DIN(61) & DIN(40) & DIN(15) & DIN(28) & DIN(62) & DIN(10) & DIN(26) & DIN(38) & DIN(38) & DIN(26) & DIN(0) & DIN(35) & DIN(14) & DIN(33) & DIN(50) & DIN(50) & DIN(33) & DIN(52) & DIN(48) & DIN(56) & DIN(6) & DIN(45) & DIN(51) & DIN(37) & DIN(10) & DIN(32) & DIN(42) & DIN(55) & DIN(63) & DIN(60) & DIN(0) & DIN(33) & DIN(41) & DIN(5) & DIN(2) & DIN(24) & DIN(35) & DIN(63) & DIN(38) & DIN(3); inst40_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init40, DOUT => DOUT(40) ); init40 <= DIN(42) & DIN(12) & DIN(31) & DIN(5) & DIN(62) & DIN(3) & DIN(19) & DIN(18) & DIN(24) & DIN(10) & DIN(46) & DIN(56) & DIN(5) & DIN(57) & DIN(35) & DIN(31) & DIN(35) & DIN(55) & DIN(40) & DIN(60) & DIN(20) & DIN(42) & DIN(18) & DIN(0) & DIN(32) & DIN(58) & DIN(8) & DIN(36) & DIN(40) & DIN(13) & DIN(12) & DIN(37) & DIN(14) & DIN(28) & DIN(50) & DIN(44) & DIN(43) & DIN(8) & DIN(35) & DIN(32) & DIN(5) & DIN(53) & DIN(21) & DIN(37) & DIN(21) & DIN(43) & DIN(55) & DIN(39) & DIN(35) & DIN(61) & DIN(41) & DIN(20) & DIN(10) & DIN(24) & DIN(55) & DIN(60) & DIN(18) & DIN(59) & DIN(24) & DIN(2) & DIN(62) & DIN(48) & DIN(51) & DIN(34); inst41_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init41, DOUT => DOUT(41) ); init41 <= DIN(54) & DIN(18) & DIN(18) & DIN(26) & DIN(35) & DIN(29) & DIN(24) & DIN(32) & DIN(18) & DIN(34) & DIN(61) & DIN(13) & DIN(42) & DIN(28) & DIN(26) & DIN(4) & DIN(20) & DIN(50) & DIN(12) & DIN(3) & DIN(15) & DIN(14) & DIN(22) & DIN(12) & DIN(51) & DIN(32) & DIN(48) & DIN(20) & DIN(62) & DIN(63) & DIN(7) & DIN(28) & DIN(47) & DIN(53) & DIN(2) & DIN(3) & DIN(10) & DIN(54) & DIN(35) & DIN(5) & DIN(56) & DIN(32) & DIN(50) & DIN(38) & DIN(8) & DIN(40) & DIN(55) & DIN(16) & DIN(35) & DIN(62) & DIN(45) & DIN(3) & DIN(27) & DIN(54) & DIN(27) & DIN(31) & DIN(34) & DIN(49) & DIN(12) & DIN(34) & DIN(16) & DIN(18) & DIN(25) & DIN(44); inst42_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init42, DOUT => DOUT(42) ); init42 <= DIN(35) & DIN(37) & DIN(18) & DIN(31) & DIN(18) & DIN(30) & DIN(45) & DIN(24) & DIN(32) & DIN(13) & DIN(49) & DIN(61) & DIN(17) & DIN(38) & DIN(50) & DIN(54) & DIN(46) & DIN(9) & DIN(23) & DIN(3) & DIN(10) & DIN(21) & DIN(51) & DIN(15) & DIN(39) & DIN(21) & DIN(33) & DIN(61) & DIN(6) & DIN(0) & DIN(40) & DIN(4) & DIN(19) & DIN(52) & DIN(50) & DIN(57) & DIN(61) & DIN(31) & DIN(39) & DIN(35) & DIN(60) & DIN(10) & DIN(11) & DIN(27) & DIN(56) & DIN(41) & DIN(30) & DIN(43) & DIN(63) & DIN(2) & DIN(16) & DIN(59) & DIN(46) & DIN(30) & DIN(46) & DIN(42) & DIN(14) & DIN(32) & DIN(20) & DIN(2) & DIN(45) & DIN(52) & DIN(18) & DIN(25); inst43_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init43, DOUT => DOUT(43) ); init43 <= DIN(58) & DIN(48) & DIN(61) & DIN(10) & DIN(11) & DIN(45) & DIN(0) & DIN(32) & DIN(0) & DIN(26) & DIN(8) & DIN(50) & DIN(7) & DIN(13) & DIN(17) & DIN(12) & DIN(51) & DIN(62) & DIN(2) & DIN(23) & DIN(60) & DIN(30) & DIN(45) & DIN(48) & DIN(41) & DIN(12) & DIN(59) & DIN(56) & DIN(54) & DIN(28) & DIN(57) & DIN(48) & DIN(37) & DIN(16) & DIN(10) & DIN(42) & DIN(45) & DIN(37) & DIN(24) & DIN(14) & DIN(19) & DIN(58) & DIN(33) & DIN(59) & DIN(26) & DIN(19) & DIN(10) & DIN(28) & DIN(2) & DIN(35) & DIN(42) & DIN(12) & DIN(53) & DIN(32) & DIN(52) & DIN(49) & DIN(22) & DIN(31) & DIN(62) & DIN(6) & DIN(55) & DIN(41) & DIN(37) & DIN(58); inst44_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init44, DOUT => DOUT(44) ); init44 <= DIN(1) & DIN(38) & DIN(10) & DIN(15) & DIN(14) & DIN(31) & DIN(41) & DIN(44) & DIN(46) & DIN(51) & DIN(8) & DIN(7) & DIN(8) & DIN(18) & DIN(33) & DIN(61) & DIN(28) & DIN(21) & DIN(59) & DIN(24) & DIN(16) & DIN(6) & DIN(38) & DIN(23) & DIN(4) & DIN(50) & DIN(32) & DIN(26) & DIN(58) & DIN(7) & DIN(28) & DIN(50) & DIN(24) & DIN(43) & DIN(38) & DIN(33) & DIN(49) & DIN(54) & DIN(36) & DIN(38) & DIN(43) & DIN(54) & DIN(38) & DIN(10) & DIN(54) & DIN(12) & DIN(2) & DIN(3) & DIN(5) & DIN(53) & DIN(50) & DIN(57) & DIN(1) & DIN(52) & DIN(55) & DIN(42) & DIN(56) & DIN(24) & DIN(61) & DIN(8) & DIN(47) & DIN(49) & DIN(12) & DIN(55); inst45_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init45, DOUT => DOUT(45) ); init45 <= DIN(21) & DIN(29) & DIN(48) & DIN(34) & DIN(44) & DIN(55) & DIN(29) & DIN(34) & DIN(0) & DIN(63) & DIN(35) & DIN(24) & DIN(46) & DIN(2) & DIN(25) & DIN(10) & DIN(16) & DIN(13) & DIN(47) & DIN(37) & DIN(9) & DIN(37) & DIN(27) & DIN(3) & DIN(56) & DIN(38) & DIN(55) & DIN(35) & DIN(1) & DIN(50) & DIN(52) & DIN(51) & DIN(49) & DIN(56) & DIN(5) & DIN(10) & DIN(55) & DIN(30) & DIN(63) & DIN(40) & DIN(16) & DIN(32) & DIN(63) & DIN(36) & DIN(50) & DIN(12) & DIN(27) & DIN(43) & DIN(4) & DIN(9) & DIN(10) & DIN(6) & DIN(45) & DIN(53) & DIN(11) & DIN(21) & DIN(37) & DIN(5) & DIN(46) & DIN(14) & DIN(1) & DIN(60) & DIN(46) & DIN(39); inst46_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init46, DOUT => DOUT(46) ); init46 <= DIN(56) & DIN(58) & DIN(46) & DIN(10) & DIN(26) & DIN(12) & DIN(43) & DIN(31) & DIN(0) & DIN(42) & DIN(20) & DIN(23) & DIN(22) & DIN(1) & DIN(11) & DIN(36) & DIN(46) & DIN(62) & DIN(21) & DIN(51) & DIN(31) & DIN(8) & DIN(18) & DIN(11) & DIN(12) & DIN(63) & DIN(38) & DIN(52) & DIN(53) & DIN(39) & DIN(56) & DIN(46) & DIN(31) & DIN(33) & DIN(30) & DIN(59) & DIN(12) & DIN(1) & DIN(11) & DIN(41) & DIN(20) & DIN(19) & DIN(12) & DIN(50) & DIN(19) & DIN(13) & DIN(15) & DIN(58) & DIN(30) & DIN(12) & DIN(33) & DIN(20) & DIN(60) & DIN(19) & DIN(37) & DIN(23) & DIN(10) & DIN(63) & DIN(60) & DIN(7) & DIN(7) & DIN(22) & DIN(15) & DIN(36); inst47_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init47, DOUT => DOUT(47) ); init47 <= DIN(14) & DIN(9) & DIN(62) & DIN(4) & DIN(22) & DIN(40) & DIN(26) & DIN(8) & DIN(10) & DIN(43) & DIN(41) & DIN(54) & DIN(22) & DIN(22) & DIN(13) & DIN(32) & DIN(3) & DIN(15) & DIN(63) & DIN(8) & DIN(39) & DIN(31) & DIN(23) & DIN(35) & DIN(45) & DIN(37) & DIN(52) & DIN(47) & DIN(18) & DIN(14) & DIN(3) & DIN(10) & DIN(51) & DIN(22) & DIN(41) & DIN(13) & DIN(30) & DIN(47) & DIN(31) & DIN(20) & DIN(21) & DIN(19) & DIN(40) & DIN(53) & DIN(18) & DIN(62) & DIN(33) & DIN(59) & DIN(40) & DIN(32) & DIN(48) & DIN(4) & DIN(50) & DIN(50) & DIN(47) & DIN(62) & DIN(19) & DIN(38) & DIN(44) & DIN(7) & DIN(26) & DIN(45) & DIN(33) & DIN(38); inst48_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init48, DOUT => DOUT(48) ); init48 <= DIN(46) & DIN(3) & DIN(16) & DIN(7) & DIN(40) & DIN(5) & DIN(55) & DIN(14) & DIN(8) & DIN(49) & DIN(50) & DIN(16) & DIN(1) & DIN(62) & DIN(50) & DIN(26) & DIN(20) & DIN(63) & DIN(27) & DIN(32) & DIN(34) & DIN(51) & DIN(57) & DIN(37) & DIN(14) & DIN(34) & DIN(40) & DIN(49) & DIN(51) & DIN(11) & DIN(43) & DIN(39) & DIN(27) & DIN(11) & DIN(15) & DIN(26) & DIN(60) & DIN(6) & DIN(28) & DIN(56) & DIN(48) & DIN(52) & DIN(30) & DIN(39) & DIN(42) & DIN(51) & DIN(62) & DIN(52) & DIN(29) & DIN(40) & DIN(38) & DIN(60) & DIN(37) & DIN(23) & DIN(61) & DIN(29) & DIN(47) & DIN(29) & DIN(5) & DIN(12) & DIN(48) & DIN(32) & DIN(23) & DIN(1); inst49_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init49, DOUT => DOUT(49) ); init49 <= DIN(10) & DIN(44) & DIN(55) & DIN(34) & DIN(20) & DIN(53) & DIN(8) & DIN(55) & DIN(32) & DIN(49) & DIN(43) & DIN(19) & DIN(2) & DIN(35) & DIN(61) & DIN(33) & DIN(36) & DIN(24) & DIN(50) & DIN(53) & DIN(53) & DIN(1) & DIN(56) & DIN(44) & DIN(36) & DIN(58) & DIN(63) & DIN(39) & DIN(30) & DIN(4) & DIN(35) & DIN(40) & DIN(24) & DIN(2) & DIN(26) & DIN(28) & DIN(20) & DIN(23) & DIN(12) & DIN(13) & DIN(47) & DIN(7) & DIN(22) & DIN(33) & DIN(63) & DIN(36) & DIN(47) & DIN(47) & DIN(35) & DIN(49) & DIN(61) & DIN(9) & DIN(29) & DIN(62) & DIN(45) & DIN(61) & DIN(28) & DIN(58) & DIN(3) & DIN(54) & DIN(44) & DIN(33) & DIN(14) & DIN(59); inst50_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init50, DOUT => DOUT(50) ); init50 <= DIN(30) & DIN(39) & DIN(26) & DIN(50) & DIN(5) & DIN(57) & DIN(54) & DIN(62) & DIN(34) & DIN(39) & DIN(46) & DIN(45) & DIN(43) & DIN(20) & DIN(0) & DIN(39) & DIN(26) & DIN(4) & DIN(14) & DIN(51) & DIN(10) & DIN(25) & DIN(9) & DIN(49) & DIN(8) & DIN(55) & DIN(10) & DIN(44) & DIN(27) & DIN(36) & DIN(9) & DIN(44) & DIN(34) & DIN(33) & DIN(59) & DIN(7) & DIN(23) & DIN(15) & DIN(15) & DIN(53) & DIN(59) & DIN(26) & DIN(45) & DIN(4) & DIN(58) & DIN(60) & DIN(25) & DIN(39) & DIN(58) & DIN(53) & DIN(42) & DIN(25) & DIN(17) & DIN(17) & DIN(39) & DIN(27) & DIN(28) & DIN(38) & DIN(35) & DIN(47) & DIN(2) & DIN(40) & DIN(48) & DIN(27); inst51_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init51, DOUT => DOUT(51) ); init51 <= DIN(3) & DIN(33) & DIN(55) & DIN(4) & DIN(7) & DIN(55) & DIN(17) & DIN(17) & DIN(21) & DIN(4) & DIN(53) & DIN(37) & DIN(61) & DIN(18) & DIN(43) & DIN(51) & DIN(17) & DIN(25) & DIN(24) & DIN(61) & DIN(50) & DIN(17) & DIN(41) & DIN(50) & DIN(36) & DIN(25) & DIN(1) & DIN(42) & DIN(19) & DIN(41) & DIN(57) & DIN(62) & DIN(25) & DIN(0) & DIN(51) & DIN(54) & DIN(34) & DIN(12) & DIN(28) & DIN(48) & DIN(7) & DIN(35) & DIN(57) & DIN(9) & DIN(1) & DIN(18) & DIN(27) & DIN(20) & DIN(39) & DIN(7) & DIN(20) & DIN(63) & DIN(45) & DIN(16) & DIN(49) & DIN(58) & DIN(6) & DIN(24) & DIN(49) & DIN(21) & DIN(16) & DIN(57) & DIN(11) & DIN(35); inst52_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init52, DOUT => DOUT(52) ); init52 <= DIN(45) & DIN(8) & DIN(18) & DIN(56) & DIN(58) & DIN(27) & DIN(13) & DIN(29) & DIN(39) & DIN(4) & DIN(55) & DIN(56) & DIN(2) & DIN(8) & DIN(25) & DIN(17) & DIN(46) & DIN(63) & DIN(22) & DIN(57) & DIN(34) & DIN(46) & DIN(48) & DIN(57) & DIN(23) & DIN(63) & DIN(40) & DIN(61) & DIN(1) & DIN(40) & DIN(13) & DIN(53) & DIN(13) & DIN(55) & DIN(42) & DIN(29) & DIN(52) & DIN(9) & DIN(38) & DIN(47) & DIN(2) & DIN(47) & DIN(30) & DIN(48) & DIN(26) & DIN(26) & DIN(59) & DIN(53) & DIN(29) & DIN(40) & DIN(9) & DIN(41) & DIN(23) & DIN(48) & DIN(17) & DIN(25) & DIN(62) & DIN(63) & DIN(48) & DIN(12) & DIN(27) & DIN(22) & DIN(10) & DIN(48); inst53_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init53, DOUT => DOUT(53) ); init53 <= DIN(40) & DIN(3) & DIN(6) & DIN(18) & DIN(8) & DIN(3) & DIN(44) & DIN(46) & DIN(45) & DIN(15) & DIN(38) & DIN(15) & DIN(44) & DIN(57) & DIN(63) & DIN(38) & DIN(52) & DIN(50) & DIN(24) & DIN(39) & DIN(40) & DIN(19) & DIN(52) & DIN(47) & DIN(60) & DIN(0) & DIN(12) & DIN(30) & DIN(46) & DIN(24) & DIN(49) & DIN(22) & DIN(58) & DIN(3) & DIN(37) & DIN(26) & DIN(22) & DIN(29) & DIN(8) & DIN(30) & DIN(35) & DIN(44) & DIN(16) & DIN(5) & DIN(5) & DIN(12) & DIN(14) & DIN(13) & DIN(10) & DIN(5) & DIN(51) & DIN(57) & DIN(23) & DIN(52) & DIN(34) & DIN(29) & DIN(17) & DIN(52) & DIN(45) & DIN(24) & DIN(29) & DIN(46) & DIN(48) & DIN(32); inst54_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init54, DOUT => DOUT(54) ); init54 <= DIN(6) & DIN(58) & DIN(58) & DIN(43) & DIN(12) & DIN(53) & DIN(44) & DIN(21) & DIN(23) & DIN(47) & DIN(36) & DIN(12) & DIN(59) & DIN(55) & DIN(45) & DIN(53) & DIN(56) & DIN(29) & DIN(21) & DIN(8) & DIN(57) & DIN(47) & DIN(23) & DIN(59) & DIN(61) & DIN(24) & DIN(22) & DIN(50) & DIN(2) & DIN(4) & DIN(28) & DIN(26) & DIN(46) & DIN(5) & DIN(63) & DIN(55) & DIN(29) & DIN(60) & DIN(48) & DIN(11) & DIN(52) & DIN(45) & DIN(31) & DIN(6) & DIN(63) & DIN(16) & DIN(32) & DIN(48) & DIN(36) & DIN(38) & DIN(49) & DIN(61) & DIN(50) & DIN(62) & DIN(37) & DIN(10) & DIN(22) & DIN(18) & DIN(22) & DIN(39) & DIN(22) & DIN(22) & DIN(27) & DIN(55); inst55_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init55, DOUT => DOUT(55) ); init55 <= DIN(28) & DIN(2) & DIN(20) & DIN(46) & DIN(4) & DIN(12) & DIN(63) & DIN(29) & DIN(9) & DIN(10) & DIN(49) & DIN(50) & DIN(34) & DIN(57) & DIN(7) & DIN(14) & DIN(25) & DIN(12) & DIN(31) & DIN(5) & DIN(12) & DIN(40) & DIN(30) & DIN(1) & DIN(40) & DIN(20) & DIN(12) & DIN(49) & DIN(3) & DIN(6) & DIN(16) & DIN(46) & DIN(61) & DIN(8) & DIN(47) & DIN(39) & DIN(2) & DIN(52) & DIN(44) & DIN(23) & DIN(40) & DIN(55) & DIN(43) & DIN(19) & DIN(32) & DIN(59) & DIN(47) & DIN(20) & DIN(0) & DIN(55) & DIN(39) & DIN(10) & DIN(63) & DIN(10) & DIN(53) & DIN(55) & DIN(17) & DIN(6) & DIN(32) & DIN(21) & DIN(9) & DIN(8) & DIN(63) & DIN(22); inst56_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init56, DOUT => DOUT(56) ); init56 <= DIN(0) & DIN(29) & DIN(60) & DIN(56) & DIN(38) & DIN(50) & DIN(56) & DIN(19) & DIN(4) & DIN(58) & DIN(21) & DIN(4) & DIN(0) & DIN(35) & DIN(3) & DIN(36) & DIN(59) & DIN(13) & DIN(57) & DIN(5) & DIN(56) & DIN(8) & DIN(22) & DIN(50) & DIN(48) & DIN(52) & DIN(12) & DIN(29) & DIN(29) & DIN(13) & DIN(41) & DIN(8) & DIN(55) & DIN(10) & DIN(0) & DIN(18) & DIN(46) & DIN(62) & DIN(62) & DIN(0) & DIN(57) & DIN(50) & DIN(1) & DIN(28) & DIN(40) & DIN(54) & DIN(43) & DIN(54) & DIN(20) & DIN(49) & DIN(46) & DIN(6) & DIN(24) & DIN(34) & DIN(38) & DIN(18) & DIN(22) & DIN(62) & DIN(52) & DIN(21) & DIN(22) & DIN(31) & DIN(8) & DIN(37); inst57_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init57, DOUT => DOUT(57) ); init57 <= DIN(12) & DIN(35) & DIN(20) & DIN(41) & DIN(18) & DIN(15) & DIN(48) & DIN(40) & DIN(11) & DIN(21) & DIN(58) & DIN(63) & DIN(32) & DIN(62) & DIN(43) & DIN(63) & DIN(7) & DIN(17) & DIN(51) & DIN(21) & DIN(56) & DIN(10) & DIN(38) & DIN(3) & DIN(29) & DIN(4) & DIN(7) & DIN(52) & DIN(26) & DIN(20) & DIN(34) & DIN(35) & DIN(16) & DIN(4) & DIN(56) & DIN(42) & DIN(4) & DIN(27) & DIN(46) & DIN(12) & DIN(53) & DIN(59) & DIN(20) & DIN(33) & DIN(55) & DIN(26) & DIN(12) & DIN(50) & DIN(25) & DIN(40) & DIN(47) & DIN(53) & DIN(45) & DIN(34) & DIN(59) & DIN(40) & DIN(41) & DIN(51) & DIN(18) & DIN(55) & DIN(3) & DIN(30) & DIN(43) & DIN(38); inst58_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init58, DOUT => DOUT(58) ); init58 <= DIN(21) & DIN(62) & DIN(42) & DIN(27) & DIN(35) & DIN(9) & DIN(23) & DIN(62) & DIN(53) & DIN(55) & DIN(45) & DIN(10) & DIN(41) & DIN(43) & DIN(16) & DIN(3) & DIN(53) & DIN(43) & DIN(23) & DIN(63) & DIN(38) & DIN(41) & DIN(52) & DIN(33) & DIN(3) & DIN(58) & DIN(14) & DIN(50) & DIN(57) & DIN(6) & DIN(7) & DIN(58) & DIN(27) & DIN(32) & DIN(3) & DIN(37) & DIN(20) & DIN(32) & DIN(17) & DIN(43) & DIN(14) & DIN(1) & DIN(58) & DIN(38) & DIN(54) & DIN(37) & DIN(44) & DIN(54) & DIN(4) & DIN(45) & DIN(11) & DIN(5) & DIN(38) & DIN(57) & DIN(18) & DIN(17) & DIN(1) & DIN(8) & DIN(43) & DIN(62) & DIN(43) & DIN(39) & DIN(55) & DIN(54); inst59_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init59, DOUT => DOUT(59) ); init59 <= DIN(7) & DIN(8) & DIN(60) & DIN(24) & DIN(13) & DIN(41) & DIN(47) & DIN(3) & DIN(44) & DIN(4) & DIN(36) & DIN(9) & DIN(60) & DIN(14) & DIN(62) & DIN(50) & DIN(45) & DIN(42) & DIN(21) & DIN(23) & DIN(63) & DIN(35) & DIN(17) & DIN(23) & DIN(39) & DIN(54) & DIN(6) & DIN(42) & DIN(2) & DIN(31) & DIN(33) & DIN(46) & DIN(59) & DIN(19) & DIN(41) & DIN(9) & DIN(61) & DIN(43) & DIN(31) & DIN(34) & DIN(8) & DIN(22) & DIN(11) & DIN(10) & DIN(32) & DIN(20) & DIN(29) & DIN(22) & DIN(43) & DIN(49) & DIN(6) & DIN(40) & DIN(60) & DIN(27) & DIN(17) & DIN(61) & DIN(52) & DIN(39) & DIN(9) & DIN(19) & DIN(36) & DIN(14) & DIN(5) & DIN(49); inst60_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init60, DOUT => DOUT(60) ); init60 <= DIN(57) & DIN(49) & DIN(59) & DIN(49) & DIN(10) & DIN(18) & DIN(17) & DIN(1) & DIN(48) & DIN(56) & DIN(53) & DIN(39) & DIN(45) & DIN(18) & DIN(12) & DIN(37) & DIN(27) & DIN(54) & DIN(1) & DIN(45) & DIN(27) & DIN(43) & DIN(62) & DIN(51) & DIN(2) & DIN(58) & DIN(31) & DIN(49) & DIN(53) & DIN(47) & DIN(50) & DIN(7) & DIN(39) & DIN(41) & DIN(32) & DIN(9) & DIN(34) & DIN(24) & DIN(12) & DIN(9) & DIN(11) & DIN(35) & DIN(26) & DIN(8) & DIN(55) & DIN(22) & DIN(36) & DIN(45) & DIN(26) & DIN(22) & DIN(47) & DIN(40) & DIN(40) & DIN(4) & DIN(19) & DIN(17) & DIN(5) & DIN(48) & DIN(63) & DIN(45) & DIN(8) & DIN(9) & DIN(39) & DIN(30); inst61_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init61, DOUT => DOUT(61) ); init61 <= DIN(11) & DIN(38) & DIN(0) & DIN(55) & DIN(2) & DIN(44) & DIN(3) & DIN(11) & DIN(18) & DIN(1) & DIN(15) & DIN(41) & DIN(10) & DIN(38) & DIN(17) & DIN(20) & DIN(46) & DIN(49) & DIN(19) & DIN(28) & DIN(63) & DIN(36) & DIN(23) & DIN(49) & DIN(16) & DIN(8) & DIN(37) & DIN(41) & DIN(21) & DIN(3) & DIN(1) & DIN(20) & DIN(36) & DIN(19) & DIN(51) & DIN(55) & DIN(26) & DIN(2) & DIN(59) & DIN(41) & DIN(55) & DIN(41) & DIN(24) & DIN(54) & DIN(56) & DIN(31) & DIN(1) & DIN(17) & DIN(50) & DIN(47) & DIN(5) & DIN(13) & DIN(20) & DIN(15) & DIN(12) & DIN(38) & DIN(51) & DIN(33) & DIN(40) & DIN(0) & DIN(31) & DIN(46) & DIN(33) & DIN(45); inst62_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init62, DOUT => DOUT(62) ); init62 <= DIN(41) & DIN(6) & DIN(2) & DIN(10) & DIN(27) & DIN(42) & DIN(22) & DIN(50) & DIN(30) & DIN(8) & DIN(8) & DIN(9) & DIN(60) & DIN(11) & DIN(56) & DIN(59) & DIN(32) & DIN(40) & DIN(9) & DIN(30) & DIN(34) & DIN(62) & DIN(45) & DIN(48) & DIN(33) & DIN(46) & DIN(17) & DIN(33) & DIN(45) & DIN(22) & DIN(56) & DIN(30) & DIN(43) & DIN(23) & DIN(52) & DIN(41) & DIN(12) & DIN(14) & DIN(41) & DIN(21) & DIN(12) & DIN(61) & DIN(17) & DIN(1) & DIN(43) & DIN(16) & DIN(49) & DIN(2) & DIN(6) & DIN(11) & DIN(49) & DIN(50) & DIN(29) & DIN(63) & DIN(31) & DIN(0) & DIN(0) & DIN(59) & DIN(41) & DIN(15) & DIN(43) & DIN(32) & DIN(42) & DIN(1); inst63_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init63, DOUT => DOUT(63) ); init63 <= DIN(53) & DIN(11) & DIN(14) & DIN(63) & DIN(29) & DIN(1) & DIN(38) & DIN(41) & DIN(29) & DIN(20) & DIN(55) & DIN(3) & DIN(29) & DIN(48) & DIN(0) & DIN(24) & DIN(7) & DIN(4) & DIN(27) & DIN(39) & DIN(5) & DIN(42) & DIN(0) & DIN(0) & DIN(26) & DIN(0) & DIN(5) & DIN(40) & DIN(35) & DIN(9) & DIN(35) & DIN(53) & DIN(46) & DIN(13) & DIN(25) & DIN(52) & DIN(36) & DIN(18) & DIN(50) & DIN(25) & DIN(55) & DIN(7) & DIN(3) & DIN(5) & DIN(41) & DIN(59) & DIN(60) & DIN(31) & DIN(63) & DIN(49) & DIN(39) & DIN(4) & DIN(16) & DIN(63) & DIN(59) & DIN(50) & DIN(29) & DIN(60) & DIN(4) & DIN(45) & DIN(27) & DIN(22) & DIN(28) & DIN(58); inst64_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init64, DOUT => DOUT(64) ); init64 <= DIN(55) & DIN(59) & DIN(27) & DIN(33) & DIN(54) & DIN(61) & DIN(32) & DIN(35) & DIN(21) & DIN(43) & DIN(29) & DIN(44) & DIN(19) & DIN(25) & DIN(41) & DIN(36) & DIN(49) & DIN(59) & DIN(45) & DIN(13) & DIN(41) & DIN(38) & DIN(41) & DIN(48) & DIN(38) & DIN(10) & DIN(18) & DIN(14) & DIN(47) & DIN(30) & DIN(53) & DIN(21) & DIN(5) & DIN(29) & DIN(1) & DIN(19) & DIN(40) & DIN(53) & DIN(5) & DIN(41) & DIN(24) & DIN(4) & DIN(2) & DIN(46) & DIN(39) & DIN(46) & DIN(55) & DIN(36) & DIN(17) & DIN(7) & DIN(36) & DIN(57) & DIN(0) & DIN(31) & DIN(30) & DIN(24) & DIN(26) & DIN(51) & DIN(24) & DIN(26) & DIN(25) & DIN(24) & DIN(20) & DIN(49); inst65_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init65, DOUT => DOUT(65) ); init65 <= DIN(38) & DIN(55) & DIN(19) & DIN(39) & DIN(35) & DIN(31) & DIN(3) & DIN(32) & DIN(33) & DIN(26) & DIN(55) & DIN(5) & DIN(39) & DIN(12) & DIN(10) & DIN(24) & DIN(54) & DIN(57) & DIN(38) & DIN(12) & DIN(60) & DIN(13) & DIN(12) & DIN(35) & DIN(37) & DIN(6) & DIN(55) & DIN(11) & DIN(42) & DIN(50) & DIN(27) & DIN(62) & DIN(20) & DIN(52) & DIN(36) & DIN(3) & DIN(61) & DIN(41) & DIN(40) & DIN(28) & DIN(50) & DIN(43) & DIN(59) & DIN(15) & DIN(22) & DIN(16) & DIN(50) & DIN(42) & DIN(61) & DIN(25) & DIN(0) & DIN(25) & DIN(39) & DIN(5) & DIN(43) & DIN(26) & DIN(28) & DIN(5) & DIN(48) & DIN(44) & DIN(30) & DIN(38) & DIN(26) & DIN(16); inst66_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init66, DOUT => DOUT(66) ); init66 <= DIN(36) & DIN(27) & DIN(15) & DIN(21) & DIN(15) & DIN(18) & DIN(48) & DIN(50) & DIN(60) & DIN(3) & DIN(40) & DIN(13) & DIN(57) & DIN(61) & DIN(33) & DIN(15) & DIN(51) & DIN(15) & DIN(28) & DIN(47) & DIN(36) & DIN(54) & DIN(53) & DIN(18) & DIN(7) & DIN(53) & DIN(37) & DIN(36) & DIN(48) & DIN(6) & DIN(13) & DIN(15) & DIN(12) & DIN(60) & DIN(37) & DIN(29) & DIN(22) & DIN(45) & DIN(10) & DIN(47) & DIN(10) & DIN(43) & DIN(44) & DIN(42) & DIN(9) & DIN(18) & DIN(50) & DIN(4) & DIN(42) & DIN(38) & DIN(58) & DIN(18) & DIN(47) & DIN(0) & DIN(44) & DIN(35) & DIN(4) & DIN(31) & DIN(23) & DIN(33) & DIN(58) & DIN(16) & DIN(42) & DIN(46); inst67_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init67, DOUT => DOUT(67) ); init67 <= DIN(19) & DIN(35) & DIN(18) & DIN(13) & DIN(47) & DIN(3) & DIN(41) & DIN(23) & DIN(24) & DIN(32) & DIN(14) & DIN(2) & DIN(38) & DIN(24) & DIN(29) & DIN(31) & DIN(29) & DIN(59) & DIN(63) & DIN(48) & DIN(18) & DIN(29) & DIN(35) & DIN(56) & DIN(46) & DIN(38) & DIN(59) & DIN(46) & DIN(13) & DIN(52) & DIN(36) & DIN(6) & DIN(52) & DIN(15) & DIN(36) & DIN(24) & DIN(43) & DIN(9) & DIN(9) & DIN(21) & DIN(57) & DIN(54) & DIN(37) & DIN(7) & DIN(58) & DIN(34) & DIN(31) & DIN(45) & DIN(41) & DIN(34) & DIN(12) & DIN(26) & DIN(47) & DIN(61) & DIN(61) & DIN(63) & DIN(25) & DIN(7) & DIN(10) & DIN(7) & DIN(0) & DIN(21) & DIN(33) & DIN(28); inst68_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init68, DOUT => DOUT(68) ); init68 <= DIN(50) & DIN(12) & DIN(59) & DIN(18) & DIN(47) & DIN(27) & DIN(10) & DIN(8) & DIN(15) & DIN(37) & DIN(52) & DIN(17) & DIN(47) & DIN(35) & DIN(59) & DIN(17) & DIN(42) & DIN(6) & DIN(2) & DIN(52) & DIN(55) & DIN(10) & DIN(27) & DIN(7) & DIN(48) & DIN(61) & DIN(22) & DIN(6) & DIN(50) & DIN(3) & DIN(0) & DIN(32) & DIN(29) & DIN(31) & DIN(8) & DIN(38) & DIN(12) & DIN(37) & DIN(20) & DIN(62) & DIN(53) & DIN(17) & DIN(21) & DIN(30) & DIN(57) & DIN(53) & DIN(15) & DIN(54) & DIN(15) & DIN(55) & DIN(25) & DIN(48) & DIN(26) & DIN(29) & DIN(48) & DIN(42) & DIN(11) & DIN(19) & DIN(6) & DIN(18) & DIN(37) & DIN(32) & DIN(23) & DIN(55); inst69_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init69, DOUT => DOUT(69) ); init69 <= DIN(33) & DIN(32) & DIN(29) & DIN(25) & DIN(8) & DIN(41) & DIN(33) & DIN(44) & DIN(40) & DIN(54) & DIN(10) & DIN(58) & DIN(57) & DIN(4) & DIN(21) & DIN(5) & DIN(14) & DIN(22) & DIN(6) & DIN(40) & DIN(6) & DIN(42) & DIN(62) & DIN(7) & DIN(56) & DIN(26) & DIN(11) & DIN(59) & DIN(45) & DIN(25) & DIN(24) & DIN(7) & DIN(23) & DIN(51) & DIN(56) & DIN(28) & DIN(1) & DIN(43) & DIN(33) & DIN(46) & DIN(60) & DIN(6) & DIN(36) & DIN(52) & DIN(54) & DIN(63) & DIN(63) & DIN(37) & DIN(16) & DIN(28) & DIN(42) & DIN(62) & DIN(49) & DIN(36) & DIN(60) & DIN(61) & DIN(45) & DIN(50) & DIN(34) & DIN(38) & DIN(1) & DIN(37) & DIN(15) & DIN(59); inst70_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init70, DOUT => DOUT(70) ); init70 <= DIN(61) & DIN(33) & DIN(8) & DIN(2) & DIN(5) & DIN(30) & DIN(1) & DIN(31) & DIN(21) & DIN(31) & DIN(22) & DIN(37) & DIN(6) & DIN(55) & DIN(23) & DIN(25) & DIN(0) & DIN(63) & DIN(55) & DIN(3) & DIN(33) & DIN(25) & DIN(27) & DIN(8) & DIN(9) & DIN(10) & DIN(53) & DIN(33) & DIN(62) & DIN(12) & DIN(56) & DIN(58) & DIN(27) & DIN(42) & DIN(1) & DIN(38) & DIN(9) & DIN(33) & DIN(9) & DIN(47) & DIN(25) & DIN(31) & DIN(14) & DIN(45) & DIN(55) & DIN(24) & DIN(34) & DIN(61) & DIN(30) & DIN(30) & DIN(39) & DIN(25) & DIN(16) & DIN(17) & DIN(19) & DIN(39) & DIN(11) & DIN(41) & DIN(41) & DIN(4) & DIN(48) & DIN(14) & DIN(57) & DIN(53); inst71_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init71, DOUT => DOUT(71) ); init71 <= DIN(53) & DIN(12) & DIN(45) & DIN(16) & DIN(9) & DIN(50) & DIN(25) & DIN(6) & DIN(52) & DIN(2) & DIN(12) & DIN(57) & DIN(49) & DIN(47) & DIN(62) & DIN(0) & DIN(40) & DIN(35) & DIN(37) & DIN(6) & DIN(15) & DIN(1) & DIN(59) & DIN(20) & DIN(29) & DIN(48) & DIN(16) & DIN(60) & DIN(6) & DIN(37) & DIN(54) & DIN(36) & DIN(3) & DIN(59) & DIN(55) & DIN(2) & DIN(62) & DIN(22) & DIN(58) & DIN(59) & DIN(17) & DIN(28) & DIN(58) & DIN(49) & DIN(7) & DIN(27) & DIN(27) & DIN(34) & DIN(20) & DIN(36) & DIN(10) & DIN(59) & DIN(36) & DIN(11) & DIN(4) & DIN(33) & DIN(42) & DIN(43) & DIN(5) & DIN(34) & DIN(34) & DIN(59) & DIN(45) & DIN(0); inst72_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init72, DOUT => DOUT(72) ); init72 <= DIN(31) & DIN(8) & DIN(42) & DIN(2) & DIN(17) & DIN(52) & DIN(21) & DIN(61) & DIN(52) & DIN(53) & DIN(23) & DIN(4) & DIN(29) & DIN(36) & DIN(45) & DIN(12) & DIN(37) & DIN(24) & DIN(7) & DIN(31) & DIN(53) & DIN(50) & DIN(23) & DIN(18) & DIN(4) & DIN(51) & DIN(20) & DIN(29) & DIN(30) & DIN(23) & DIN(49) & DIN(29) & DIN(55) & DIN(53) & DIN(44) & DIN(19) & DIN(0) & DIN(32) & DIN(38) & DIN(48) & DIN(23) & DIN(51) & DIN(23) & DIN(17) & DIN(63) & DIN(20) & DIN(5) & DIN(6) & DIN(35) & DIN(21) & DIN(7) & DIN(35) & DIN(45) & DIN(36) & DIN(62) & DIN(39) & DIN(21) & DIN(61) & DIN(44) & DIN(1) & DIN(32) & DIN(59) & DIN(49) & DIN(36); inst73_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init73, DOUT => DOUT(73) ); init73 <= DIN(47) & DIN(9) & DIN(39) & DIN(47) & DIN(21) & DIN(27) & DIN(16) & DIN(61) & DIN(46) & DIN(57) & DIN(14) & DIN(4) & DIN(51) & DIN(20) & DIN(47) & DIN(42) & DIN(14) & DIN(15) & DIN(57) & DIN(12) & DIN(12) & DIN(44) & DIN(55) & DIN(22) & DIN(4) & DIN(59) & DIN(40) & DIN(59) & DIN(52) & DIN(43) & DIN(10) & DIN(63) & DIN(51) & DIN(12) & DIN(31) & DIN(24) & DIN(44) & DIN(23) & DIN(46) & DIN(42) & DIN(6) & DIN(58) & DIN(21) & DIN(8) & DIN(6) & DIN(32) & DIN(49) & DIN(2) & DIN(2) & DIN(13) & DIN(21) & DIN(54) & DIN(40) & DIN(60) & DIN(46) & DIN(9) & DIN(7) & DIN(60) & DIN(49) & DIN(52) & DIN(56) & DIN(62) & DIN(32) & DIN(27); inst74_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init74, DOUT => DOUT(74) ); init74 <= DIN(38) & DIN(16) & DIN(31) & DIN(3) & DIN(45) & DIN(3) & DIN(20) & DIN(59) & DIN(22) & DIN(46) & DIN(48) & DIN(24) & DIN(29) & DIN(0) & DIN(43) & DIN(10) & DIN(62) & DIN(54) & DIN(5) & DIN(1) & DIN(53) & DIN(20) & DIN(50) & DIN(30) & DIN(50) & DIN(51) & DIN(0) & DIN(29) & DIN(0) & DIN(15) & DIN(63) & DIN(35) & DIN(35) & DIN(28) & DIN(47) & DIN(50) & DIN(45) & DIN(38) & DIN(11) & DIN(61) & DIN(16) & DIN(48) & DIN(45) & DIN(19) & DIN(1) & DIN(52) & DIN(5) & DIN(61) & DIN(1) & DIN(48) & DIN(14) & DIN(23) & DIN(34) & DIN(63) & DIN(29) & DIN(21) & DIN(51) & DIN(49) & DIN(30) & DIN(28) & DIN(44) & DIN(35) & DIN(52) & DIN(49); inst75_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init75, DOUT => DOUT(75) ); init75 <= DIN(38) & DIN(0) & DIN(14) & DIN(19) & DIN(61) & DIN(52) & DIN(31) & DIN(24) & DIN(1) & DIN(60) & DIN(18) & DIN(16) & DIN(5) & DIN(15) & DIN(52) & DIN(10) & DIN(34) & DIN(5) & DIN(62) & DIN(13) & DIN(52) & DIN(51) & DIN(36) & DIN(45) & DIN(38) & DIN(49) & DIN(43) & DIN(26) & DIN(51) & DIN(62) & DIN(0) & DIN(19) & DIN(3) & DIN(26) & DIN(51) & DIN(37) & DIN(51) & DIN(35) & DIN(6) & DIN(48) & DIN(54) & DIN(3) & DIN(28) & DIN(59) & DIN(45) & DIN(46) & DIN(11) & DIN(20) & DIN(17) & DIN(11) & DIN(41) & DIN(7) & DIN(13) & DIN(51) & DIN(2) & DIN(12) & DIN(62) & DIN(45) & DIN(25) & DIN(32) & DIN(59) & DIN(38) & DIN(31) & DIN(30); inst76_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init76, DOUT => DOUT(76) ); init76 <= DIN(8) & DIN(44) & DIN(24) & DIN(55) & DIN(4) & DIN(51) & DIN(35) & DIN(42) & DIN(53) & DIN(16) & DIN(31) & DIN(9) & DIN(57) & DIN(9) & DIN(61) & DIN(59) & DIN(51) & DIN(45) & DIN(14) & DIN(46) & DIN(35) & DIN(49) & DIN(29) & DIN(34) & DIN(53) & DIN(18) & DIN(32) & DIN(7) & DIN(59) & DIN(17) & DIN(61) & DIN(17) & DIN(40) & DIN(36) & DIN(19) & DIN(25) & DIN(62) & DIN(19) & DIN(11) & DIN(43) & DIN(22) & DIN(22) & DIN(12) & DIN(62) & DIN(21) & DIN(16) & DIN(44) & DIN(5) & DIN(10) & DIN(29) & DIN(17) & DIN(0) & DIN(59) & DIN(11) & DIN(2) & DIN(46) & DIN(23) & DIN(15) & DIN(10) & DIN(41) & DIN(41) & DIN(25) & DIN(62) & DIN(15); inst77_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init77, DOUT => DOUT(77) ); init77 <= DIN(26) & DIN(41) & DIN(2) & DIN(4) & DIN(58) & DIN(8) & DIN(43) & DIN(33) & DIN(23) & DIN(63) & DIN(32) & DIN(29) & DIN(23) & DIN(19) & DIN(7) & DIN(26) & DIN(58) & DIN(0) & DIN(60) & DIN(43) & DIN(51) & DIN(39) & DIN(26) & DIN(33) & DIN(5) & DIN(54) & DIN(30) & DIN(18) & DIN(53) & DIN(11) & DIN(61) & DIN(22) & DIN(46) & DIN(57) & DIN(24) & DIN(25) & DIN(49) & DIN(44) & DIN(1) & DIN(58) & DIN(40) & DIN(13) & DIN(22) & DIN(61) & DIN(24) & DIN(6) & DIN(30) & DIN(15) & DIN(13) & DIN(21) & DIN(17) & DIN(18) & DIN(33) & DIN(36) & DIN(3) & DIN(51) & DIN(1) & DIN(18) & DIN(21) & DIN(30) & DIN(29) & DIN(3) & DIN(62) & DIN(21); inst78_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init78, DOUT => DOUT(78) ); init78 <= DIN(43) & DIN(48) & DIN(30) & DIN(57) & DIN(3) & DIN(41) & DIN(59) & DIN(20) & DIN(15) & DIN(38) & DIN(40) & DIN(56) & DIN(11) & DIN(4) & DIN(13) & DIN(18) & DIN(55) & DIN(34) & DIN(58) & DIN(8) & DIN(14) & DIN(52) & DIN(32) & DIN(20) & DIN(41) & DIN(57) & DIN(22) & DIN(10) & DIN(5) & DIN(63) & DIN(4) & DIN(50) & DIN(45) & DIN(53) & DIN(62) & DIN(46) & DIN(26) & DIN(21) & DIN(44) & DIN(22) & DIN(26) & DIN(36) & DIN(43) & DIN(57) & DIN(12) & DIN(43) & DIN(24) & DIN(47) & DIN(20) & DIN(5) & DIN(40) & DIN(58) & DIN(11) & DIN(39) & DIN(62) & DIN(31) & DIN(52) & DIN(23) & DIN(5) & DIN(18) & DIN(17) & DIN(15) & DIN(52) & DIN(63); inst79_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init79, DOUT => DOUT(79) ); init79 <= DIN(48) & DIN(58) & DIN(10) & DIN(3) & DIN(49) & DIN(33) & DIN(5) & DIN(10) & DIN(36) & DIN(55) & DIN(2) & DIN(32) & DIN(45) & DIN(36) & DIN(23) & DIN(55) & DIN(20) & DIN(52) & DIN(41) & DIN(61) & DIN(29) & DIN(31) & DIN(52) & DIN(24) & DIN(12) & DIN(12) & DIN(13) & DIN(2) & DIN(51) & DIN(54) & DIN(25) & DIN(45) & DIN(9) & DIN(40) & DIN(62) & DIN(38) & DIN(61) & DIN(13) & DIN(8) & DIN(4) & DIN(10) & DIN(30) & DIN(9) & DIN(54) & DIN(15) & DIN(35) & DIN(14) & DIN(23) & DIN(23) & DIN(10) & DIN(9) & DIN(5) & DIN(18) & DIN(39) & DIN(11) & DIN(10) & DIN(25) & DIN(22) & DIN(41) & DIN(5) & DIN(45) & DIN(48) & DIN(47) & DIN(35); inst80_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init80, DOUT => DOUT(80) ); init80 <= DIN(40) & DIN(60) & DIN(31) & DIN(37) & DIN(41) & DIN(17) & DIN(18) & DIN(58) & DIN(52) & DIN(58) & DIN(20) & DIN(25) & DIN(19) & DIN(16) & DIN(4) & DIN(55) & DIN(49) & DIN(38) & DIN(29) & DIN(50) & DIN(53) & DIN(39) & DIN(10) & DIN(59) & DIN(5) & DIN(23) & DIN(42) & DIN(33) & DIN(1) & DIN(56) & DIN(49) & DIN(3) & DIN(18) & DIN(14) & DIN(18) & DIN(47) & DIN(29) & DIN(24) & DIN(37) & DIN(26) & DIN(39) & DIN(4) & DIN(21) & DIN(28) & DIN(31) & DIN(30) & DIN(26) & DIN(63) & DIN(49) & DIN(54) & DIN(39) & DIN(58) & DIN(33) & DIN(51) & DIN(17) & DIN(36) & DIN(22) & DIN(50) & DIN(48) & DIN(62) & DIN(37) & DIN(35) & DIN(49) & DIN(35); inst81_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init81, DOUT => DOUT(81) ); init81 <= DIN(57) & DIN(4) & DIN(52) & DIN(18) & DIN(61) & DIN(19) & DIN(30) & DIN(6) & DIN(27) & DIN(39) & DIN(47) & DIN(7) & DIN(25) & DIN(42) & DIN(6) & DIN(5) & DIN(24) & DIN(0) & DIN(5) & DIN(32) & DIN(13) & DIN(22) & DIN(44) & DIN(17) & DIN(24) & DIN(30) & DIN(50) & DIN(12) & DIN(5) & DIN(58) & DIN(11) & DIN(39) & DIN(7) & DIN(33) & DIN(51) & DIN(54) & DIN(56) & DIN(55) & DIN(23) & DIN(19) & DIN(14) & DIN(5) & DIN(1) & DIN(20) & DIN(17) & DIN(6) & DIN(63) & DIN(56) & DIN(51) & DIN(47) & DIN(52) & DIN(60) & DIN(62) & DIN(14) & DIN(31) & DIN(12) & DIN(25) & DIN(56) & DIN(1) & DIN(30) & DIN(50) & DIN(42) & DIN(52) & DIN(17); inst82_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init82, DOUT => DOUT(82) ); init82 <= DIN(23) & DIN(36) & DIN(30) & DIN(52) & DIN(37) & DIN(46) & DIN(16) & DIN(38) & DIN(56) & DIN(48) & DIN(27) & DIN(20) & DIN(13) & DIN(35) & DIN(15) & DIN(48) & DIN(7) & DIN(48) & DIN(3) & DIN(50) & DIN(43) & DIN(0) & DIN(35) & DIN(42) & DIN(22) & DIN(21) & DIN(47) & DIN(12) & DIN(19) & DIN(11) & DIN(46) & DIN(35) & DIN(63) & DIN(47) & DIN(36) & DIN(63) & DIN(54) & DIN(32) & DIN(11) & DIN(36) & DIN(35) & DIN(55) & DIN(5) & DIN(28) & DIN(28) & DIN(30) & DIN(45) & DIN(21) & DIN(5) & DIN(3) & DIN(14) & DIN(0) & DIN(42) & DIN(14) & DIN(59) & DIN(10) & DIN(1) & DIN(36) & DIN(29) & DIN(48) & DIN(12) & DIN(63) & DIN(62) & DIN(63); inst83_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init83, DOUT => DOUT(83) ); init83 <= DIN(4) & DIN(17) & DIN(6) & DIN(10) & DIN(55) & DIN(10) & DIN(63) & DIN(41) & DIN(37) & DIN(24) & DIN(58) & DIN(53) & DIN(23) & DIN(57) & DIN(21) & DIN(60) & DIN(48) & DIN(37) & DIN(60) & DIN(60) & DIN(2) & DIN(32) & DIN(23) & DIN(16) & DIN(10) & DIN(35) & DIN(33) & DIN(39) & DIN(25) & DIN(50) & DIN(39) & DIN(58) & DIN(26) & DIN(60) & DIN(11) & DIN(13) & DIN(36) & DIN(38) & DIN(47) & DIN(48) & DIN(1) & DIN(1) & DIN(32) & DIN(27) & DIN(8) & DIN(48) & DIN(0) & DIN(52) & DIN(35) & DIN(28) & DIN(37) & DIN(50) & DIN(21) & DIN(52) & DIN(47) & DIN(35) & DIN(9) & DIN(46) & DIN(0) & DIN(31) & DIN(24) & DIN(43) & DIN(47) & DIN(12); inst84_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init84, DOUT => DOUT(84) ); init84 <= DIN(16) & DIN(62) & DIN(48) & DIN(35) & DIN(52) & DIN(59) & DIN(57) & DIN(23) & DIN(10) & DIN(32) & DIN(0) & DIN(36) & DIN(62) & DIN(51) & DIN(60) & DIN(5) & DIN(12) & DIN(45) & DIN(7) & DIN(26) & DIN(54) & DIN(1) & DIN(61) & DIN(59) & DIN(44) & DIN(6) & DIN(60) & DIN(20) & DIN(18) & DIN(30) & DIN(19) & DIN(45) & DIN(10) & DIN(53) & DIN(42) & DIN(29) & DIN(48) & DIN(25) & DIN(23) & DIN(38) & DIN(34) & DIN(13) & DIN(39) & DIN(56) & DIN(39) & DIN(15) & DIN(62) & DIN(50) & DIN(55) & DIN(5) & DIN(28) & DIN(59) & DIN(21) & DIN(55) & DIN(62) & DIN(24) & DIN(52) & DIN(30) & DIN(1) & DIN(36) & DIN(20) & DIN(30) & DIN(3) & DIN(45); inst85_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init85, DOUT => DOUT(85) ); init85 <= DIN(50) & DIN(0) & DIN(28) & DIN(11) & DIN(47) & DIN(0) & DIN(0) & DIN(34) & DIN(53) & DIN(51) & DIN(4) & DIN(12) & DIN(27) & DIN(34) & DIN(29) & DIN(27) & DIN(10) & DIN(13) & DIN(27) & DIN(22) & DIN(60) & DIN(14) & DIN(30) & DIN(48) & DIN(14) & DIN(20) & DIN(43) & DIN(39) & DIN(0) & DIN(39) & DIN(62) & DIN(39) & DIN(16) & DIN(28) & DIN(11) & DIN(13) & DIN(11) & DIN(12) & DIN(29) & DIN(40) & DIN(24) & DIN(34) & DIN(47) & DIN(0) & DIN(24) & DIN(15) & DIN(0) & DIN(52) & DIN(17) & DIN(12) & DIN(55) & DIN(12) & DIN(0) & DIN(10) & DIN(5) & DIN(38) & DIN(20) & DIN(3) & DIN(41) & DIN(25) & DIN(23) & DIN(34) & DIN(28) & DIN(3); inst86_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init86, DOUT => DOUT(86) ); init86 <= DIN(8) & DIN(35) & DIN(44) & DIN(35) & DIN(0) & DIN(11) & DIN(37) & DIN(57) & DIN(28) & DIN(39) & DIN(14) & DIN(56) & DIN(24) & DIN(35) & DIN(20) & DIN(44) & DIN(46) & DIN(35) & DIN(4) & DIN(5) & DIN(14) & DIN(62) & DIN(57) & DIN(20) & DIN(2) & DIN(58) & DIN(53) & DIN(28) & DIN(56) & DIN(37) & DIN(20) & DIN(37) & DIN(34) & DIN(33) & DIN(62) & DIN(7) & DIN(47) & DIN(62) & DIN(43) & DIN(36) & DIN(14) & DIN(42) & DIN(36) & DIN(44) & DIN(53) & DIN(48) & DIN(40) & DIN(41) & DIN(21) & DIN(6) & DIN(12) & DIN(58) & DIN(60) & DIN(62) & DIN(31) & DIN(38) & DIN(2) & DIN(16) & DIN(7) & DIN(18) & DIN(2) & DIN(51) & DIN(39) & DIN(27); inst87_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init87, DOUT => DOUT(87) ); init87 <= DIN(37) & DIN(4) & DIN(0) & DIN(40) & DIN(31) & DIN(35) & DIN(51) & DIN(60) & DIN(15) & DIN(33) & DIN(5) & DIN(29) & DIN(15) & DIN(25) & DIN(17) & DIN(55) & DIN(9) & DIN(43) & DIN(44) & DIN(49) & DIN(30) & DIN(5) & DIN(45) & DIN(61) & DIN(12) & DIN(12) & DIN(32) & DIN(24) & DIN(58) & DIN(1) & DIN(29) & DIN(61) & DIN(36) & DIN(29) & DIN(53) & DIN(35) & DIN(20) & DIN(18) & DIN(55) & DIN(49) & DIN(17) & DIN(44) & DIN(12) & DIN(24) & DIN(16) & DIN(37) & DIN(10) & DIN(24) & DIN(13) & DIN(39) & DIN(4) & DIN(33) & DIN(57) & DIN(32) & DIN(29) & DIN(52) & DIN(18) & DIN(31) & DIN(59) & DIN(61) & DIN(29) & DIN(0) & DIN(8) & DIN(1); inst88_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init88, DOUT => DOUT(88) ); init88 <= DIN(27) & DIN(31) & DIN(11) & DIN(5) & DIN(50) & DIN(47) & DIN(52) & DIN(35) & DIN(55) & DIN(40) & DIN(20) & DIN(40) & DIN(59) & DIN(41) & DIN(11) & DIN(10) & DIN(13) & DIN(16) & DIN(30) & DIN(15) & DIN(36) & DIN(11) & DIN(33) & DIN(47) & DIN(1) & DIN(31) & DIN(38) & DIN(40) & DIN(60) & DIN(35) & DIN(60) & DIN(22) & DIN(45) & DIN(28) & DIN(16) & DIN(15) & DIN(55) & DIN(12) & DIN(14) & DIN(15) & DIN(45) & DIN(43) & DIN(28) & DIN(49) & DIN(28) & DIN(59) & DIN(44) & DIN(62) & DIN(44) & DIN(19) & DIN(45) & DIN(53) & DIN(10) & DIN(2) & DIN(8) & DIN(25) & DIN(35) & DIN(3) & DIN(44) & DIN(38) & DIN(54) & DIN(31) & DIN(5) & DIN(30); inst89_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init89, DOUT => DOUT(89) ); init89 <= DIN(25) & DIN(16) & DIN(12) & DIN(48) & DIN(23) & DIN(49) & DIN(9) & DIN(38) & DIN(49) & DIN(2) & DIN(0) & DIN(54) & DIN(44) & DIN(9) & DIN(48) & DIN(58) & DIN(9) & DIN(17) & DIN(28) & DIN(50) & DIN(46) & DIN(39) & DIN(38) & DIN(20) & DIN(0) & DIN(42) & DIN(25) & DIN(40) & DIN(18) & DIN(40) & DIN(50) & DIN(41) & DIN(57) & DIN(27) & DIN(38) & DIN(49) & DIN(0) & DIN(7) & DIN(38) & DIN(59) & DIN(21) & DIN(55) & DIN(6) & DIN(50) & DIN(63) & DIN(30) & DIN(30) & DIN(23) & DIN(35) & DIN(52) & DIN(12) & DIN(25) & DIN(39) & DIN(60) & DIN(59) & DIN(24) & DIN(24) & DIN(48) & DIN(54) & DIN(41) & DIN(47) & DIN(23) & DIN(2) & DIN(7); inst90_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init90, DOUT => DOUT(90) ); init90 <= DIN(58) & DIN(0) & DIN(29) & DIN(51) & DIN(5) & DIN(55) & DIN(38) & DIN(9) & DIN(42) & DIN(41) & DIN(26) & DIN(13) & DIN(3) & DIN(28) & DIN(57) & DIN(4) & DIN(15) & DIN(40) & DIN(4) & DIN(57) & DIN(3) & DIN(14) & DIN(19) & DIN(24) & DIN(33) & DIN(63) & DIN(9) & DIN(38) & DIN(24) & DIN(33) & DIN(17) & DIN(6) & DIN(58) & DIN(38) & DIN(13) & DIN(60) & DIN(13) & DIN(61) & DIN(47) & DIN(29) & DIN(37) & DIN(62) & DIN(19) & DIN(63) & DIN(12) & DIN(17) & DIN(63) & DIN(22) & DIN(37) & DIN(54) & DIN(38) & DIN(43) & DIN(45) & DIN(20) & DIN(15) & DIN(59) & DIN(38) & DIN(39) & DIN(21) & DIN(18) & DIN(39) & DIN(43) & DIN(57) & DIN(62); inst91_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init91, DOUT => DOUT(91) ); init91 <= DIN(55) & DIN(20) & DIN(1) & DIN(34) & DIN(52) & DIN(53) & DIN(47) & DIN(2) & DIN(36) & DIN(60) & DIN(45) & DIN(6) & DIN(15) & DIN(15) & DIN(14) & DIN(43) & DIN(27) & DIN(63) & DIN(33) & DIN(52) & DIN(51) & DIN(51) & DIN(7) & DIN(44) & DIN(20) & DIN(1) & DIN(41) & DIN(47) & DIN(63) & DIN(52) & DIN(30) & DIN(20) & DIN(32) & DIN(11) & DIN(51) & DIN(50) & DIN(17) & DIN(51) & DIN(21) & DIN(30) & DIN(45) & DIN(30) & DIN(56) & DIN(36) & DIN(52) & DIN(15) & DIN(10) & DIN(39) & DIN(11) & DIN(46) & DIN(45) & DIN(7) & DIN(30) & DIN(5) & DIN(3) & DIN(37) & DIN(2) & DIN(53) & DIN(17) & DIN(42) & DIN(20) & DIN(18) & DIN(33) & DIN(46); inst92_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init92, DOUT => DOUT(92) ); init92 <= DIN(20) & DIN(51) & DIN(47) & DIN(53) & DIN(21) & DIN(57) & DIN(30) & DIN(23) & DIN(57) & DIN(27) & DIN(25) & DIN(28) & DIN(13) & DIN(17) & DIN(47) & DIN(2) & DIN(45) & DIN(62) & DIN(36) & DIN(15) & DIN(28) & DIN(21) & DIN(63) & DIN(37) & DIN(34) & DIN(46) & DIN(15) & DIN(36) & DIN(17) & DIN(44) & DIN(44) & DIN(31) & DIN(29) & DIN(54) & DIN(23) & DIN(62) & DIN(63) & DIN(2) & DIN(61) & DIN(29) & DIN(14) & DIN(8) & DIN(45) & DIN(11) & DIN(36) & DIN(49) & DIN(30) & DIN(30) & DIN(34) & DIN(14) & DIN(16) & DIN(55) & DIN(51) & DIN(17) & DIN(22) & DIN(62) & DIN(29) & DIN(35) & DIN(55) & DIN(49) & DIN(14) & DIN(54) & DIN(8) & DIN(31); inst93_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init93, DOUT => DOUT(93) ); init93 <= DIN(28) & DIN(25) & DIN(43) & DIN(34) & DIN(35) & DIN(60) & DIN(7) & DIN(8) & DIN(34) & DIN(31) & DIN(29) & DIN(61) & DIN(12) & DIN(43) & DIN(54) & DIN(17) & DIN(51) & DIN(11) & DIN(47) & DIN(23) & DIN(45) & DIN(30) & DIN(42) & DIN(17) & DIN(59) & DIN(59) & DIN(25) & DIN(40) & DIN(40) & DIN(54) & DIN(20) & DIN(58) & DIN(54) & DIN(46) & DIN(27) & DIN(26) & DIN(26) & DIN(40) & DIN(43) & DIN(37) & DIN(18) & DIN(50) & DIN(7) & DIN(59) & DIN(56) & DIN(43) & DIN(34) & DIN(28) & DIN(30) & DIN(16) & DIN(45) & DIN(28) & DIN(35) & DIN(47) & DIN(56) & DIN(19) & DIN(19) & DIN(34) & DIN(20) & DIN(46) & DIN(0) & DIN(37) & DIN(31) & DIN(28); inst94_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init94, DOUT => DOUT(94) ); init94 <= DIN(41) & DIN(8) & DIN(31) & DIN(24) & DIN(25) & DIN(45) & DIN(23) & DIN(41) & DIN(24) & DIN(47) & DIN(36) & DIN(36) & DIN(43) & DIN(27) & DIN(56) & DIN(47) & DIN(53) & DIN(42) & DIN(16) & DIN(13) & DIN(41) & DIN(29) & DIN(27) & DIN(57) & DIN(29) & DIN(52) & DIN(56) & DIN(52) & DIN(58) & DIN(22) & DIN(53) & DIN(17) & DIN(47) & DIN(49) & DIN(1) & DIN(48) & DIN(21) & DIN(39) & DIN(5) & DIN(51) & DIN(4) & DIN(8) & DIN(44) & DIN(60) & DIN(38) & DIN(13) & DIN(30) & DIN(40) & DIN(1) & DIN(51) & DIN(50) & DIN(48) & DIN(0) & DIN(39) & DIN(1) & DIN(41) & DIN(58) & DIN(34) & DIN(63) & DIN(41) & DIN(39) & DIN(4) & DIN(16) & DIN(63); inst95_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init95, DOUT => DOUT(95) ); init95 <= DIN(6) & DIN(57) & DIN(9) & DIN(42) & DIN(0) & DIN(19) & DIN(44) & DIN(27) & DIN(6) & DIN(54) & DIN(21) & DIN(17) & DIN(25) & DIN(60) & DIN(51) & DIN(37) & DIN(60) & DIN(5) & DIN(21) & DIN(32) & DIN(1) & DIN(33) & DIN(60) & DIN(45) & DIN(34) & DIN(2) & DIN(41) & DIN(48) & DIN(50) & DIN(2) & DIN(25) & DIN(28) & DIN(57) & DIN(54) & DIN(62) & DIN(37) & DIN(13) & DIN(54) & DIN(6) & DIN(53) & DIN(29) & DIN(24) & DIN(30) & DIN(52) & DIN(0) & DIN(46) & DIN(16) & DIN(28) & DIN(3) & DIN(52) & DIN(36) & DIN(20) & DIN(63) & DIN(57) & DIN(4) & DIN(50) & DIN(16) & DIN(38) & DIN(23) & DIN(22) & DIN(9) & DIN(35) & DIN(30) & DIN(20); inst96_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init96, DOUT => DOUT(96) ); init96 <= DIN(57) & DIN(2) & DIN(8) & DIN(3) & DIN(30) & DIN(10) & DIN(10) & DIN(29) & DIN(19) & DIN(10) & DIN(38) & DIN(6) & DIN(10) & DIN(2) & DIN(37) & DIN(37) & DIN(36) & DIN(59) & DIN(21) & DIN(24) & DIN(43) & DIN(1) & DIN(0) & DIN(0) & DIN(42) & DIN(44) & DIN(42) & DIN(50) & DIN(26) & DIN(54) & DIN(55) & DIN(53) & DIN(35) & DIN(62) & DIN(57) & DIN(1) & DIN(55) & DIN(0) & DIN(55) & DIN(13) & DIN(0) & DIN(36) & DIN(32) & DIN(37) & DIN(29) & DIN(42) & DIN(16) & DIN(12) & DIN(16) & DIN(19) & DIN(24) & DIN(43) & DIN(23) & DIN(19) & DIN(21) & DIN(55) & DIN(18) & DIN(52) & DIN(59) & DIN(37) & DIN(18) & DIN(57) & DIN(60) & DIN(34); inst97_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init97, DOUT => DOUT(97) ); init97 <= DIN(32) & DIN(39) & DIN(61) & DIN(5) & DIN(13) & DIN(11) & DIN(34) & DIN(51) & DIN(18) & DIN(1) & DIN(33) & DIN(28) & DIN(63) & DIN(25) & DIN(49) & DIN(26) & DIN(37) & DIN(15) & DIN(27) & DIN(54) & DIN(56) & DIN(30) & DIN(45) & DIN(5) & DIN(5) & DIN(32) & DIN(40) & DIN(5) & DIN(61) & DIN(12) & DIN(5) & DIN(27) & DIN(26) & DIN(50) & DIN(35) & DIN(26) & DIN(57) & DIN(33) & DIN(18) & DIN(53) & DIN(2) & DIN(7) & DIN(43) & DIN(37) & DIN(52) & DIN(33) & DIN(63) & DIN(46) & DIN(23) & DIN(61) & DIN(9) & DIN(50) & DIN(24) & DIN(13) & DIN(29) & DIN(0) & DIN(34) & DIN(28) & DIN(0) & DIN(34) & DIN(50) & DIN(19) & DIN(56) & DIN(63); inst98_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init98, DOUT => DOUT(98) ); init98 <= DIN(57) & DIN(40) & DIN(49) & DIN(28) & DIN(21) & DIN(7) & DIN(50) & DIN(5) & DIN(62) & DIN(48) & DIN(50) & DIN(59) & DIN(60) & DIN(42) & DIN(26) & DIN(58) & DIN(52) & DIN(58) & DIN(26) & DIN(27) & DIN(26) & DIN(19) & DIN(50) & DIN(19) & DIN(49) & DIN(25) & DIN(40) & DIN(5) & DIN(56) & DIN(26) & DIN(7) & DIN(29) & DIN(18) & DIN(41) & DIN(41) & DIN(16) & DIN(9) & DIN(2) & DIN(19) & DIN(3) & DIN(52) & DIN(8) & DIN(33) & DIN(1) & DIN(54) & DIN(31) & DIN(32) & DIN(25) & DIN(32) & DIN(7) & DIN(40) & DIN(6) & DIN(34) & DIN(25) & DIN(43) & DIN(43) & DIN(33) & DIN(13) & DIN(62) & DIN(27) & DIN(8) & DIN(30) & DIN(51) & DIN(2); inst99_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init99, DOUT => DOUT(99) ); init99 <= DIN(28) & DIN(31) & DIN(31) & DIN(45) & DIN(8) & DIN(21) & DIN(0) & DIN(42) & DIN(3) & DIN(59) & DIN(60) & DIN(14) & DIN(11) & DIN(22) & DIN(11) & DIN(33) & DIN(47) & DIN(56) & DIN(42) & DIN(2) & DIN(34) & DIN(29) & DIN(48) & DIN(6) & DIN(4) & DIN(24) & DIN(4) & DIN(7) & DIN(26) & DIN(21) & DIN(60) & DIN(47) & DIN(23) & DIN(10) & DIN(45) & DIN(30) & DIN(17) & DIN(5) & DIN(45) & DIN(53) & DIN(47) & DIN(38) & DIN(3) & DIN(42) & DIN(39) & DIN(18) & DIN(55) & DIN(44) & DIN(22) & DIN(13) & DIN(18) & DIN(28) & DIN(24) & DIN(24) & DIN(2) & DIN(61) & DIN(62) & DIN(47) & DIN(11) & DIN(42) & DIN(62) & DIN(49) & DIN(2) & DIN(56); inst100_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init100, DOUT => DOUT(100) ); init100 <= DIN(30) & DIN(63) & DIN(58) & DIN(21) & DIN(58) & DIN(26) & DIN(0) & DIN(16) & DIN(23) & DIN(10) & DIN(5) & DIN(1) & DIN(29) & DIN(16) & DIN(43) & DIN(26) & DIN(30) & DIN(16) & DIN(20) & DIN(58) & DIN(1) & DIN(36) & DIN(33) & DIN(19) & DIN(35) & DIN(0) & DIN(15) & DIN(36) & DIN(2) & DIN(40) & DIN(22) & DIN(9) & DIN(5) & DIN(31) & DIN(21) & DIN(42) & DIN(3) & DIN(53) & DIN(10) & DIN(22) & DIN(45) & DIN(53) & DIN(22) & DIN(3) & DIN(50) & DIN(27) & DIN(6) & DIN(36) & DIN(15) & DIN(48) & DIN(25) & DIN(46) & DIN(1) & DIN(32) & DIN(4) & DIN(62) & DIN(62) & DIN(39) & DIN(14) & DIN(56) & DIN(34) & DIN(54) & DIN(52) & DIN(27); inst101_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init101, DOUT => DOUT(101) ); init101 <= DIN(11) & DIN(38) & DIN(29) & DIN(42) & DIN(34) & DIN(23) & DIN(49) & DIN(46) & DIN(48) & DIN(56) & DIN(52) & DIN(30) & DIN(56) & DIN(20) & DIN(12) & DIN(9) & DIN(12) & DIN(5) & DIN(31) & DIN(6) & DIN(27) & DIN(5) & DIN(43) & DIN(11) & DIN(9) & DIN(32) & DIN(16) & DIN(7) & DIN(23) & DIN(56) & DIN(38) & DIN(32) & DIN(4) & DIN(5) & DIN(57) & DIN(52) & DIN(39) & DIN(57) & DIN(58) & DIN(18) & DIN(63) & DIN(31) & DIN(18) & DIN(47) & DIN(8) & DIN(7) & DIN(42) & DIN(6) & DIN(42) & DIN(26) & DIN(27) & DIN(15) & DIN(60) & DIN(10) & DIN(59) & DIN(2) & DIN(9) & DIN(23) & DIN(33) & DIN(54) & DIN(52) & DIN(32) & DIN(39) & DIN(16); inst102_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init102, DOUT => DOUT(102) ); init102 <= DIN(36) & DIN(57) & DIN(8) & DIN(7) & DIN(12) & DIN(48) & DIN(9) & DIN(34) & DIN(36) & DIN(48) & DIN(21) & DIN(2) & DIN(58) & DIN(32) & DIN(17) & DIN(49) & DIN(27) & DIN(25) & DIN(29) & DIN(52) & DIN(25) & DIN(29) & DIN(26) & DIN(34) & DIN(41) & DIN(5) & DIN(10) & DIN(60) & DIN(11) & DIN(55) & DIN(57) & DIN(29) & DIN(45) & DIN(23) & DIN(62) & DIN(42) & DIN(12) & DIN(24) & DIN(13) & DIN(34) & DIN(54) & DIN(53) & DIN(48) & DIN(8) & DIN(5) & DIN(56) & DIN(20) & DIN(38) & DIN(0) & DIN(0) & DIN(26) & DIN(55) & DIN(51) & DIN(21) & DIN(24) & DIN(45) & DIN(58) & DIN(19) & DIN(2) & DIN(46) & DIN(10) & DIN(34) & DIN(30) & DIN(3); inst103_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init103, DOUT => DOUT(103) ); init103 <= DIN(7) & DIN(6) & DIN(43) & DIN(25) & DIN(6) & DIN(57) & DIN(27) & DIN(7) & DIN(43) & DIN(23) & DIN(17) & DIN(37) & DIN(32) & DIN(11) & DIN(40) & DIN(11) & DIN(41) & DIN(28) & DIN(11) & DIN(9) & DIN(9) & DIN(44) & DIN(58) & DIN(40) & DIN(39) & DIN(5) & DIN(36) & DIN(23) & DIN(40) & DIN(61) & DIN(34) & DIN(46) & DIN(0) & DIN(50) & DIN(61) & DIN(62) & DIN(13) & DIN(4) & DIN(54) & DIN(6) & DIN(55) & DIN(6) & DIN(61) & DIN(21) & DIN(34) & DIN(12) & DIN(63) & DIN(32) & DIN(18) & DIN(31) & DIN(14) & DIN(33) & DIN(4) & DIN(53) & DIN(4) & DIN(16) & DIN(28) & DIN(39) & DIN(53) & DIN(58) & DIN(61) & DIN(48) & DIN(48) & DIN(1); inst104_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init104, DOUT => DOUT(104) ); init104 <= DIN(10) & DIN(11) & DIN(45) & DIN(54) & DIN(42) & DIN(43) & DIN(37) & DIN(23) & DIN(49) & DIN(27) & DIN(46) & DIN(15) & DIN(22) & DIN(63) & DIN(9) & DIN(25) & DIN(59) & DIN(27) & DIN(45) & DIN(28) & DIN(12) & DIN(12) & DIN(38) & DIN(9) & DIN(20) & DIN(12) & DIN(17) & DIN(37) & DIN(60) & DIN(5) & DIN(49) & DIN(20) & DIN(32) & DIN(1) & DIN(16) & DIN(19) & DIN(58) & DIN(10) & DIN(40) & DIN(33) & DIN(4) & DIN(47) & DIN(6) & DIN(61) & DIN(4) & DIN(46) & DIN(44) & DIN(30) & DIN(14) & DIN(33) & DIN(54) & DIN(3) & DIN(56) & DIN(26) & DIN(56) & DIN(47) & DIN(16) & DIN(12) & DIN(52) & DIN(40) & DIN(36) & DIN(47) & DIN(3) & DIN(13); inst105_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init105, DOUT => DOUT(105) ); init105 <= DIN(1) & DIN(27) & DIN(44) & DIN(38) & DIN(9) & DIN(41) & DIN(28) & DIN(21) & DIN(49) & DIN(28) & DIN(14) & DIN(46) & DIN(7) & DIN(51) & DIN(17) & DIN(9) & DIN(8) & DIN(15) & DIN(58) & DIN(45) & DIN(36) & DIN(41) & DIN(28) & DIN(18) & DIN(20) & DIN(37) & DIN(45) & DIN(27) & DIN(59) & DIN(21) & DIN(8) & DIN(26) & DIN(18) & DIN(2) & DIN(10) & DIN(52) & DIN(56) & DIN(63) & DIN(7) & DIN(2) & DIN(21) & DIN(27) & DIN(29) & DIN(62) & DIN(42) & DIN(2) & DIN(15) & DIN(27) & DIN(43) & DIN(16) & DIN(17) & DIN(18) & DIN(21) & DIN(54) & DIN(36) & DIN(57) & DIN(42) & DIN(24) & DIN(18) & DIN(33) & DIN(3) & DIN(6) & DIN(16) & DIN(30); inst106_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init106, DOUT => DOUT(106) ); init106 <= DIN(1) & DIN(31) & DIN(2) & DIN(32) & DIN(0) & DIN(10) & DIN(48) & DIN(21) & DIN(19) & DIN(27) & DIN(23) & DIN(3) & DIN(16) & DIN(2) & DIN(14) & DIN(27) & DIN(30) & DIN(54) & DIN(52) & DIN(40) & DIN(38) & DIN(0) & DIN(4) & DIN(31) & DIN(20) & DIN(48) & DIN(18) & DIN(22) & DIN(63) & DIN(46) & DIN(52) & DIN(33) & DIN(31) & DIN(56) & DIN(48) & DIN(42) & DIN(55) & DIN(20) & DIN(62) & DIN(16) & DIN(11) & DIN(21) & DIN(52) & DIN(53) & DIN(36) & DIN(24) & DIN(39) & DIN(53) & DIN(16) & DIN(52) & DIN(36) & DIN(7) & DIN(43) & DIN(20) & DIN(13) & DIN(62) & DIN(48) & DIN(35) & DIN(34) & DIN(30) & DIN(15) & DIN(60) & DIN(49) & DIN(52); inst107_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init107, DOUT => DOUT(107) ); init107 <= DIN(50) & DIN(37) & DIN(35) & DIN(28) & DIN(33) & DIN(53) & DIN(19) & DIN(20) & DIN(8) & DIN(41) & DIN(10) & DIN(59) & DIN(63) & DIN(10) & DIN(30) & DIN(42) & DIN(29) & DIN(28) & DIN(45) & DIN(52) & DIN(43) & DIN(49) & DIN(25) & DIN(21) & DIN(20) & DIN(52) & DIN(51) & DIN(31) & DIN(54) & DIN(17) & DIN(46) & DIN(22) & DIN(4) & DIN(46) & DIN(9) & DIN(13) & DIN(45) & DIN(42) & DIN(10) & DIN(13) & DIN(42) & DIN(0) & DIN(29) & DIN(20) & DIN(44) & DIN(1) & DIN(61) & DIN(41) & DIN(49) & DIN(59) & DIN(27) & DIN(22) & DIN(29) & DIN(36) & DIN(34) & DIN(53) & DIN(62) & DIN(34) & DIN(48) & DIN(31) & DIN(13) & DIN(0) & DIN(13) & DIN(55); inst108_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init108, DOUT => DOUT(108) ); init108 <= DIN(23) & DIN(45) & DIN(52) & DIN(41) & DIN(27) & DIN(29) & DIN(50) & DIN(26) & DIN(56) & DIN(33) & DIN(60) & DIN(48) & DIN(49) & DIN(19) & DIN(58) & DIN(21) & DIN(50) & DIN(46) & DIN(4) & DIN(12) & DIN(32) & DIN(60) & DIN(4) & DIN(61) & DIN(18) & DIN(24) & DIN(7) & DIN(28) & DIN(24) & DIN(3) & DIN(63) & DIN(46) & DIN(18) & DIN(23) & DIN(55) & DIN(1) & DIN(36) & DIN(17) & DIN(30) & DIN(8) & DIN(48) & DIN(41) & DIN(53) & DIN(27) & DIN(33) & DIN(12) & DIN(17) & DIN(38) & DIN(13) & DIN(7) & DIN(8) & DIN(35) & DIN(42) & DIN(43) & DIN(54) & DIN(54) & DIN(0) & DIN(4) & DIN(29) & DIN(42) & DIN(48) & DIN(40) & DIN(55) & DIN(17); inst109_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init109, DOUT => DOUT(109) ); init109 <= DIN(7) & DIN(47) & DIN(46) & DIN(27) & DIN(4) & DIN(48) & DIN(31) & DIN(12) & DIN(9) & DIN(16) & DIN(8) & DIN(12) & DIN(29) & DIN(33) & DIN(2) & DIN(3) & DIN(50) & DIN(24) & DIN(38) & DIN(52) & DIN(32) & DIN(27) & DIN(48) & DIN(61) & DIN(3) & DIN(26) & DIN(30) & DIN(54) & DIN(36) & DIN(59) & DIN(46) & DIN(44) & DIN(43) & DIN(62) & DIN(60) & DIN(56) & DIN(38) & DIN(14) & DIN(4) & DIN(61) & DIN(51) & DIN(39) & DIN(10) & DIN(25) & DIN(46) & DIN(41) & DIN(29) & DIN(62) & DIN(56) & DIN(10) & DIN(4) & DIN(35) & DIN(24) & DIN(22) & DIN(31) & DIN(12) & DIN(53) & DIN(34) & DIN(8) & DIN(56) & DIN(16) & DIN(48) & DIN(48) & DIN(51); inst110_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init110, DOUT => DOUT(110) ); init110 <= DIN(23) & DIN(19) & DIN(13) & DIN(39) & DIN(2) & DIN(3) & DIN(34) & DIN(14) & DIN(1) & DIN(12) & DIN(7) & DIN(26) & DIN(59) & DIN(49) & DIN(18) & DIN(53) & DIN(36) & DIN(27) & DIN(56) & DIN(35) & DIN(0) & DIN(27) & DIN(37) & DIN(41) & DIN(49) & DIN(63) & DIN(56) & DIN(59) & DIN(57) & DIN(35) & DIN(53) & DIN(48) & DIN(16) & DIN(9) & DIN(5) & DIN(52) & DIN(2) & DIN(21) & DIN(6) & DIN(39) & DIN(17) & DIN(22) & DIN(8) & DIN(5) & DIN(13) & DIN(55) & DIN(61) & DIN(0) & DIN(26) & DIN(28) & DIN(62) & DIN(23) & DIN(42) & DIN(38) & DIN(49) & DIN(54) & DIN(6) & DIN(21) & DIN(6) & DIN(9) & DIN(18) & DIN(44) & DIN(43) & DIN(28); inst111_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init111, DOUT => DOUT(111) ); init111 <= DIN(18) & DIN(53) & DIN(39) & DIN(4) & DIN(0) & DIN(7) & DIN(45) & DIN(14) & DIN(62) & DIN(40) & DIN(40) & DIN(28) & DIN(38) & DIN(6) & DIN(28) & DIN(50) & DIN(38) & DIN(41) & DIN(6) & DIN(32) & DIN(48) & DIN(10) & DIN(44) & DIN(45) & DIN(51) & DIN(20) & DIN(34) & DIN(63) & DIN(60) & DIN(51) & DIN(48) & DIN(13) & DIN(53) & DIN(32) & DIN(23) & DIN(50) & DIN(9) & DIN(4) & DIN(37) & DIN(34) & DIN(2) & DIN(34) & DIN(0) & DIN(52) & DIN(32) & DIN(51) & DIN(44) & DIN(6) & DIN(56) & DIN(59) & DIN(51) & DIN(3) & DIN(23) & DIN(24) & DIN(11) & DIN(52) & DIN(24) & DIN(47) & DIN(15) & DIN(46) & DIN(62) & DIN(16) & DIN(54) & DIN(2); inst112_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init112, DOUT => DOUT(112) ); init112 <= DIN(26) & DIN(11) & DIN(45) & DIN(42) & DIN(59) & DIN(14) & DIN(34) & DIN(2) & DIN(1) & DIN(16) & DIN(49) & DIN(57) & DIN(63) & DIN(40) & DIN(29) & DIN(59) & DIN(29) & DIN(42) & DIN(32) & DIN(46) & DIN(30) & DIN(12) & DIN(28) & DIN(4) & DIN(29) & DIN(51) & DIN(48) & DIN(15) & DIN(59) & DIN(38) & DIN(45) & DIN(48) & DIN(16) & DIN(31) & DIN(7) & DIN(56) & DIN(13) & DIN(18) & DIN(17) & DIN(8) & DIN(17) & DIN(9) & DIN(27) & DIN(3) & DIN(11) & DIN(51) & DIN(27) & DIN(46) & DIN(12) & DIN(20) & DIN(18) & DIN(26) & DIN(46) & DIN(41) & DIN(20) & DIN(14) & DIN(56) & DIN(9) & DIN(34) & DIN(11) & DIN(22) & DIN(14) & DIN(40) & DIN(23); inst113_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init113, DOUT => DOUT(113) ); init113 <= DIN(56) & DIN(5) & DIN(0) & DIN(52) & DIN(41) & DIN(27) & DIN(34) & DIN(39) & DIN(16) & DIN(26) & DIN(18) & DIN(47) & DIN(14) & DIN(12) & DIN(48) & DIN(4) & DIN(8) & DIN(2) & DIN(43) & DIN(60) & DIN(19) & DIN(59) & DIN(14) & DIN(32) & DIN(39) & DIN(11) & DIN(13) & DIN(2) & DIN(37) & DIN(6) & DIN(58) & DIN(4) & DIN(28) & DIN(37) & DIN(18) & DIN(2) & DIN(11) & DIN(7) & DIN(20) & DIN(33) & DIN(12) & DIN(6) & DIN(62) & DIN(10) & DIN(4) & DIN(46) & DIN(24) & DIN(11) & DIN(47) & DIN(48) & DIN(46) & DIN(51) & DIN(19) & DIN(3) & DIN(19) & DIN(37) & DIN(37) & DIN(7) & DIN(8) & DIN(33) & DIN(41) & DIN(21) & DIN(49) & DIN(26); inst114_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init114, DOUT => DOUT(114) ); init114 <= DIN(49) & DIN(23) & DIN(43) & DIN(53) & DIN(4) & DIN(37) & DIN(5) & DIN(43) & DIN(24) & DIN(26) & DIN(18) & DIN(63) & DIN(24) & DIN(20) & DIN(8) & DIN(61) & DIN(38) & DIN(43) & DIN(52) & DIN(39) & DIN(29) & DIN(56) & DIN(25) & DIN(18) & DIN(4) & DIN(13) & DIN(51) & DIN(13) & DIN(20) & DIN(15) & DIN(36) & DIN(60) & DIN(19) & DIN(6) & DIN(48) & DIN(25) & DIN(13) & DIN(43) & DIN(25) & DIN(25) & DIN(2) & DIN(62) & DIN(55) & DIN(27) & DIN(46) & DIN(28) & DIN(8) & DIN(63) & DIN(14) & DIN(60) & DIN(14) & DIN(10) & DIN(52) & DIN(12) & DIN(31) & DIN(55) & DIN(56) & DIN(36) & DIN(41) & DIN(24) & DIN(60) & DIN(30) & DIN(11) & DIN(58); inst115_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init115, DOUT => DOUT(115) ); init115 <= DIN(0) & DIN(57) & DIN(39) & DIN(49) & DIN(4) & DIN(62) & DIN(8) & DIN(31) & DIN(7) & DIN(55) & DIN(37) & DIN(5) & DIN(43) & DIN(16) & DIN(8) & DIN(10) & DIN(20) & DIN(37) & DIN(59) & DIN(22) & DIN(26) & DIN(1) & DIN(33) & DIN(12) & DIN(46) & DIN(23) & DIN(50) & DIN(2) & DIN(42) & DIN(17) & DIN(47) & DIN(15) & DIN(53) & DIN(41) & DIN(40) & DIN(37) & DIN(55) & DIN(17) & DIN(58) & DIN(2) & DIN(12) & DIN(20) & DIN(61) & DIN(33) & DIN(60) & DIN(35) & DIN(14) & DIN(61) & DIN(11) & DIN(58) & DIN(53) & DIN(14) & DIN(19) & DIN(10) & DIN(25) & DIN(44) & DIN(45) & DIN(33) & DIN(19) & DIN(26) & DIN(28) & DIN(6) & DIN(39) & DIN(15); inst116_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init116, DOUT => DOUT(116) ); init116 <= DIN(48) & DIN(22) & DIN(5) & DIN(5) & DIN(61) & DIN(27) & DIN(38) & DIN(59) & DIN(50) & DIN(0) & DIN(32) & DIN(57) & DIN(30) & DIN(3) & DIN(9) & DIN(28) & DIN(46) & DIN(17) & DIN(62) & DIN(29) & DIN(3) & DIN(49) & DIN(21) & DIN(0) & DIN(56) & DIN(49) & DIN(56) & DIN(22) & DIN(40) & DIN(49) & DIN(20) & DIN(42) & DIN(25) & DIN(42) & DIN(31) & DIN(2) & DIN(41) & DIN(38) & DIN(27) & DIN(56) & DIN(33) & DIN(28) & DIN(48) & DIN(2) & DIN(21) & DIN(56) & DIN(29) & DIN(16) & DIN(13) & DIN(13) & DIN(8) & DIN(3) & DIN(57) & DIN(35) & DIN(8) & DIN(34) & DIN(9) & DIN(6) & DIN(1) & DIN(61) & DIN(24) & DIN(42) & DIN(11) & DIN(22); inst117_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init117, DOUT => DOUT(117) ); init117 <= DIN(31) & DIN(15) & DIN(16) & DIN(58) & DIN(11) & DIN(33) & DIN(30) & DIN(32) & DIN(35) & DIN(24) & DIN(59) & DIN(42) & DIN(15) & DIN(50) & DIN(23) & DIN(2) & DIN(26) & DIN(4) & DIN(20) & DIN(60) & DIN(15) & DIN(42) & DIN(40) & DIN(55) & DIN(46) & DIN(36) & DIN(29) & DIN(16) & DIN(36) & DIN(52) & DIN(6) & DIN(36) & DIN(4) & DIN(46) & DIN(28) & DIN(42) & DIN(62) & DIN(6) & DIN(37) & DIN(57) & DIN(8) & DIN(9) & DIN(19) & DIN(13) & DIN(23) & DIN(19) & DIN(45) & DIN(30) & DIN(52) & DIN(42) & DIN(20) & DIN(24) & DIN(60) & DIN(3) & DIN(26) & DIN(30) & DIN(0) & DIN(40) & DIN(9) & DIN(0) & DIN(48) & DIN(24) & DIN(8) & DIN(26); inst118_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init118, DOUT => DOUT(118) ); init118 <= DIN(41) & DIN(39) & DIN(6) & DIN(22) & DIN(16) & DIN(17) & DIN(6) & DIN(15) & DIN(59) & DIN(6) & DIN(30) & DIN(31) & DIN(17) & DIN(14) & DIN(34) & DIN(61) & DIN(34) & DIN(60) & DIN(36) & DIN(31) & DIN(38) & DIN(61) & DIN(52) & DIN(18) & DIN(48) & DIN(12) & DIN(19) & DIN(32) & DIN(52) & DIN(62) & DIN(56) & DIN(19) & DIN(23) & DIN(53) & DIN(15) & DIN(1) & DIN(22) & DIN(0) & DIN(49) & DIN(27) & DIN(53) & DIN(15) & DIN(61) & DIN(20) & DIN(44) & DIN(37) & DIN(25) & DIN(2) & DIN(22) & DIN(39) & DIN(43) & DIN(20) & DIN(12) & DIN(39) & DIN(63) & DIN(16) & DIN(24) & DIN(21) & DIN(40) & DIN(33) & DIN(38) & DIN(3) & DIN(4) & DIN(22); inst119_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init119, DOUT => DOUT(119) ); init119 <= DIN(30) & DIN(2) & DIN(23) & DIN(37) & DIN(2) & DIN(11) & DIN(18) & DIN(1) & DIN(41) & DIN(39) & DIN(5) & DIN(29) & DIN(11) & DIN(27) & DIN(24) & DIN(63) & DIN(43) & DIN(25) & DIN(16) & DIN(27) & DIN(43) & DIN(48) & DIN(45) & DIN(59) & DIN(50) & DIN(60) & DIN(46) & DIN(20) & DIN(49) & DIN(31) & DIN(41) & DIN(56) & DIN(0) & DIN(11) & DIN(19) & DIN(1) & DIN(34) & DIN(43) & DIN(59) & DIN(12) & DIN(27) & DIN(42) & DIN(5) & DIN(12) & DIN(47) & DIN(63) & DIN(46) & DIN(16) & DIN(45) & DIN(32) & DIN(46) & DIN(48) & DIN(62) & DIN(49) & DIN(12) & DIN(30) & DIN(11) & DIN(15) & DIN(42) & DIN(56) & DIN(31) & DIN(30) & DIN(37) & DIN(62); inst120_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init120, DOUT => DOUT(120) ); init120 <= DIN(34) & DIN(32) & DIN(12) & DIN(26) & DIN(14) & DIN(61) & DIN(52) & DIN(61) & DIN(11) & DIN(17) & DIN(3) & DIN(63) & DIN(48) & DIN(21) & DIN(6) & DIN(16) & DIN(16) & DIN(51) & DIN(53) & DIN(40) & DIN(44) & DIN(54) & DIN(25) & DIN(36) & DIN(34) & DIN(34) & DIN(45) & DIN(41) & DIN(23) & DIN(38) & DIN(30) & DIN(7) & DIN(17) & DIN(15) & DIN(38) & DIN(17) & DIN(49) & DIN(35) & DIN(58) & DIN(12) & DIN(33) & DIN(46) & DIN(57) & DIN(32) & DIN(5) & DIN(18) & DIN(26) & DIN(39) & DIN(7) & DIN(63) & DIN(15) & DIN(8) & DIN(20) & DIN(54) & DIN(55) & DIN(56) & DIN(11) & DIN(7) & DIN(11) & DIN(16) & DIN(20) & DIN(15) & DIN(33) & DIN(0); inst121_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init121, DOUT => DOUT(121) ); init121 <= DIN(1) & DIN(21) & DIN(43) & DIN(9) & DIN(24) & DIN(7) & DIN(23) & DIN(6) & DIN(5) & DIN(5) & DIN(1) & DIN(29) & DIN(2) & DIN(56) & DIN(42) & DIN(60) & DIN(59) & DIN(8) & DIN(57) & DIN(62) & DIN(22) & DIN(12) & DIN(6) & DIN(52) & DIN(46) & DIN(2) & DIN(8) & DIN(57) & DIN(43) & DIN(17) & DIN(29) & DIN(56) & DIN(61) & DIN(36) & DIN(50) & DIN(18) & DIN(2) & DIN(18) & DIN(5) & DIN(39) & DIN(3) & DIN(8) & DIN(51) & DIN(6) & DIN(61) & DIN(34) & DIN(2) & DIN(61) & DIN(50) & DIN(45) & DIN(55) & DIN(34) & DIN(29) & DIN(4) & DIN(44) & DIN(53) & DIN(23) & DIN(54) & DIN(28) & DIN(51) & DIN(20) & DIN(57) & DIN(6) & DIN(43); inst122_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init122, DOUT => DOUT(122) ); init122 <= DIN(55) & DIN(60) & DIN(22) & DIN(51) & DIN(50) & DIN(58) & DIN(22) & DIN(48) & DIN(31) & DIN(14) & DIN(26) & DIN(14) & DIN(31) & DIN(10) & DIN(21) & DIN(55) & DIN(0) & DIN(33) & DIN(15) & DIN(19) & DIN(47) & DIN(32) & DIN(16) & DIN(57) & DIN(45) & DIN(22) & DIN(60) & DIN(55) & DIN(51) & DIN(12) & DIN(8) & DIN(4) & DIN(10) & DIN(28) & DIN(29) & DIN(1) & DIN(26) & DIN(7) & DIN(22) & DIN(17) & DIN(47) & DIN(15) & DIN(57) & DIN(40) & DIN(10) & DIN(52) & DIN(39) & DIN(45) & DIN(50) & DIN(47) & DIN(2) & DIN(54) & DIN(51) & DIN(58) & DIN(60) & DIN(53) & DIN(35) & DIN(48) & DIN(47) & DIN(47) & DIN(2) & DIN(44) & DIN(39) & DIN(8); inst123_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init123, DOUT => DOUT(123) ); init123 <= DIN(12) & DIN(57) & DIN(33) & DIN(29) & DIN(58) & DIN(9) & DIN(54) & DIN(25) & DIN(40) & DIN(11) & DIN(15) & DIN(58) & DIN(18) & DIN(62) & DIN(34) & DIN(10) & DIN(13) & DIN(24) & DIN(27) & DIN(43) & DIN(46) & DIN(55) & DIN(29) & DIN(59) & DIN(19) & DIN(49) & DIN(24) & DIN(2) & DIN(51) & DIN(21) & DIN(2) & DIN(47) & DIN(63) & DIN(24) & DIN(39) & DIN(32) & DIN(33) & DIN(43) & DIN(10) & DIN(46) & DIN(57) & DIN(16) & DIN(24) & DIN(8) & DIN(49) & DIN(9) & DIN(46) & DIN(34) & DIN(42) & DIN(36) & DIN(13) & DIN(51) & DIN(36) & DIN(44) & DIN(35) & DIN(17) & DIN(61) & DIN(3) & DIN(0) & DIN(4) & DIN(22) & DIN(42) & DIN(8) & DIN(30); inst124_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init124, DOUT => DOUT(124) ); init124 <= DIN(20) & DIN(48) & DIN(14) & DIN(37) & DIN(54) & DIN(57) & DIN(4) & DIN(32) & DIN(49) & DIN(28) & DIN(42) & DIN(7) & DIN(46) & DIN(62) & DIN(19) & DIN(26) & DIN(57) & DIN(42) & DIN(20) & DIN(47) & DIN(20) & DIN(13) & DIN(6) & DIN(8) & DIN(20) & DIN(54) & DIN(24) & DIN(5) & DIN(21) & DIN(31) & DIN(20) & DIN(47) & DIN(57) & DIN(20) & DIN(33) & DIN(22) & DIN(8) & DIN(40) & DIN(53) & DIN(42) & DIN(46) & DIN(44) & DIN(52) & DIN(20) & DIN(4) & DIN(40) & DIN(5) & DIN(10) & DIN(22) & DIN(7) & DIN(40) & DIN(12) & DIN(57) & DIN(16) & DIN(48) & DIN(14) & DIN(33) & DIN(57) & DIN(49) & DIN(38) & DIN(37) & DIN(0) & DIN(14) & DIN(35); inst125_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init125, DOUT => DOUT(125) ); init125 <= DIN(11) & DIN(51) & DIN(7) & DIN(62) & DIN(15) & DIN(5) & DIN(0) & DIN(13) & DIN(24) & DIN(50) & DIN(26) & DIN(17) & DIN(26) & DIN(32) & DIN(14) & DIN(35) & DIN(23) & DIN(39) & DIN(22) & DIN(22) & DIN(47) & DIN(7) & DIN(39) & DIN(17) & DIN(49) & DIN(35) & DIN(8) & DIN(11) & DIN(52) & DIN(12) & DIN(43) & DIN(13) & DIN(36) & DIN(1) & DIN(62) & DIN(1) & DIN(45) & DIN(14) & DIN(51) & DIN(7) & DIN(23) & DIN(58) & DIN(3) & DIN(55) & DIN(8) & DIN(38) & DIN(13) & DIN(1) & DIN(56) & DIN(15) & DIN(46) & DIN(30) & DIN(21) & DIN(4) & DIN(9) & DIN(38) & DIN(47) & DIN(60) & DIN(32) & DIN(39) & DIN(40) & DIN(41) & DIN(15) & DIN(34); inst126_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init126, DOUT => DOUT(126) ); init126 <= DIN(30) & DIN(15) & DIN(60) & DIN(30) & DIN(42) & DIN(56) & DIN(29) & DIN(54) & DIN(63) & DIN(15) & DIN(10) & DIN(4) & DIN(16) & DIN(35) & DIN(9) & DIN(30) & DIN(20) & DIN(0) & DIN(7) & DIN(23) & DIN(18) & DIN(15) & DIN(39) & DIN(6) & DIN(47) & DIN(31) & DIN(17) & DIN(37) & DIN(7) & DIN(34) & DIN(3) & DIN(0) & DIN(37) & DIN(4) & DIN(1) & DIN(51) & DIN(57) & DIN(14) & DIN(44) & DIN(59) & DIN(63) & DIN(39) & DIN(59) & DIN(49) & DIN(14) & DIN(9) & DIN(23) & DIN(61) & DIN(46) & DIN(55) & DIN(47) & DIN(11) & DIN(32) & DIN(8) & DIN(53) & DIN(10) & DIN(24) & DIN(46) & DIN(34) & DIN(7) & DIN(61) & DIN(63) & DIN(63) & DIN(50); inst127_u: entity work.lfsr_serial generic map( LFSR_LENGTH => LFSR_LENGTH, TAPS => TAPS ) port map( CLK => CLK, S_EN => S_EN, F_EN => F_EN, DIN => init127, DOUT => DOUT(127) ); init127 <= DIN(43) & DIN(2) & DIN(28) & DIN(5) & DIN(36) & DIN(27) & DIN(16) & DIN(5) & DIN(55) & DIN(43) & DIN(35) & DIN(50) & DIN(48) & DIN(58) & DIN(9) & DIN(44) & DIN(16) & DIN(48) & DIN(49) & DIN(42) & DIN(38) & DIN(26) & DIN(14) & DIN(59) & DIN(23) & DIN(51) & DIN(23) & DIN(43) & DIN(41) & DIN(3) & DIN(38) & DIN(38) & DIN(30) & DIN(1) & DIN(52) & DIN(30) & DIN(35) & DIN(37) & DIN(34) & DIN(5) & DIN(59) & DIN(41) & DIN(40) & DIN(4) & DIN(42) & DIN(25) & DIN(58) & DIN(37) & DIN(9) & DIN(23) & DIN(28) & DIN(43) & DIN(3) & DIN(27) & DIN(36) & DIN(44) & DIN(9) & DIN(20) & DIN(4) & DIN(3) & DIN(37) & DIN(37) & DIN(50) & DIN(63); end architecture beh;
bsd-3-clause
94740394515312f0fc6bac079a17a314
0.483822
2.208652
false
false
false
false
ARC-Lab-UF/window_gen
template/template.vhd
1
13,598
-- Copyright (c) University of Florida -- -- This file is part of window_gen. -- -- window_gen is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- window_gen is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with window_gen. If not, see <http://www.gnu.org/licenses/>. -- Greg Stitt -- University of Florida -- This file provides a template for integrating the window generator into -- a datapath. Note that this is not a functional example and is instead -- used solely for explaining how to interface an input source with the -- generator, and how to handle outputs from the generator. -- -- The code has various TODO markers that should be updated when using a -- specific application. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.math_custom.all; use work.window_gen_pkg.all; entity template is generic ( IN_RAM_WORDS : positive; OUT_RAM_WORDS : positive; IN_DATA_WIDTH : positive; OUT_DATA_WIDTH : positive; MAX_WINDOW_ROWS : positive; MAX_WINDOW_COLS : positive; MAX_IMAGE_ROWS : positive; MAX_IMAGE_COLS : positive; NUM_PIPELINES : positive); port ( clk : in std_logic; rst : in std_logic; go : in std_logic; window_rows : in std_logic_vector(bitsNeeded(MAX_WINDOW_ROWS)-1 downto 0); window_cols : in std_logic_vector(bitsNeeded(MAX_WINDOW_COLS)-1 downto 0); image_cols : in std_logic_vector(bitsNeeded(MAX_IMAGE_COLS)-1 downto 0); image_rows : in std_logic_vector(bitsNeeded(MAX_IMAGE_ROWS)-1 downto 0) -- TODO: add application specific I/O ); end template; architecture default of template is constant WINDOW_BITS : positive := MAX_WINDOW_ROWS*MAX_WINDOW_COLS*IN_DATA_WIDTH; -- 2D array representing a window type window_t is array(0 to MAX_WINDOW_ROWS-1, 0 to MAX_WINDOW_COLS-1) of std_logic_vector(IN_DATA_WIDTH-1 downto 0); -- 1D array of 2D windows type window_array_t is array (0 to NUM_PIPELINES-1) of window_t; -- a huge vectorized version of all NUM_PIPELINE windows signal wg_out : std_logic_vector(MAX_WINDOW_ROWS*(MAX_WINDOW_COLS+NUM_PIPELINES-1)*IN_DATA_WIDTH-1 downto 0); -- all of the windows in 2D format signal windows : window_array_t; signal window_valid : std_logic_vector(NUM_PIPELINES-1 downto 0); signal wg_done : std_logic; signal wg_empty : std_logic; signal wg_ready : std_logic; signal read_windows : std_logic; signal input_valid : std_logic; signal pipe_valid_in : std_logic_vector(NUM_PIPELINES-1 downto 0); signal in_ram_wen : std_logic; signal in_ram_waddr : std_logic_vector(bitsNeeded(IN_RAM_WORDS)-1 downto 0); signal in_ram_wdata : std_logic_vector(IN_DATA_WIDTH-1 downto 0); signal in_ram_raddr : std_logic_vector(bitsNeeded(IN_RAM_WORDS)-1 downto 0); signal in_ram_rdata : std_logic_vector(IN_DATA_WIDTH-1 downto 0); signal out_ram_wen : std_logic; signal out_ram_waddr : std_logic_vector(bitsNeeded(OUT_RAM_WORDS)-1 downto 0); signal out_ram_wdata : std_logic_vector(OUT_DATA_WIDTH-1 downto 0); signal out_ram_raddr : std_logic_vector(bitsNeeded(OUT_RAM_WORDS)-1 downto 0); signal out_ram_rdata : std_logic_vector(OUT_DATA_WIDTH-1 downto 0); type state_t is (WAIT_FOR_GO, GENERATE_ADDRESS); signal state : state_t; ----------------------------------------------------------------------- -- Procedure devectorizeWindow -- Description: convert a 1D vectorized representation of an output window -- into a corresponding 2D array for easier processing. Note -- that this always determines a window of size -- MAX_WINDOW_ROWS X MAX_WINDOW_COLS. For smaller windows, -- just ignore the extra rows and columns. -- -- Parameters: -- vector : The 1D-vectorized version of the 2D array, stored in row-major -- order. Index (0,0) starts at the MSB in the vector, with the -- LSB storing the end of index (total_rows-1, total_cols-1) -- window : the window as a 2D array (t_window) -- index : In case multiple windows are specified in the output, index -- specifies which one to get -- -- Preconditions: index < PARALLEL_IO, vector must be the -- appropriate size with data stored as described above. ----------------------------------------------------------------------- procedure devectorizeWindow(signal vector : std_logic_vector; window : out window_t; index : natural) is begin for i in 0 to MAX_WINDOW_ROWS-1 loop for j in index to MAX_WINDOW_COLS+index-1 loop window(i, j-index) := getVectorElement(vector, i, j, MAX_WINDOW_ROWS, MAX_WINDOW_COLS+NUM_PIPELINES-1, IN_DATA_WIDTH); end loop; end loop; end devectorizeWindow; begin -- STR ------------------------------------------------------------------------- -- Input Source -- Notes: Inputs can be provided to the sliding-window generator from -- potentially any source. In this example, we instantiate a block RAM with -- a word width equivalent to the number of replicated pipelines we would -- like to use. For example, if NUM_PIPELINES is 4, this RAM can provide 4 -- inputs to the window generator every cycle, which will later output up -- to 4 windows per cycle. -- -- If using an external RAM as the input source, this RAM would likely be -- replaced with a FIFO that has a read port width of the same size as this -- RAM word width. In most cases, that FIFO will have a write port width -- equivalent to the width of the external memory's data bus. For example, -- if reading from a memory with a 128-bit data bus into a window generator -- that reads 64 bits per cycle, you would use a FIFO with a 128-bit write -- port and 64-bit read port. -- -- A third possibility for the input source is to connect the window -- generator directly to the output of another entity. e.g. a chain -- of filters, where each filter uses a sliding-window generator followed -- by a pipeline that provides input to the next window generator. ------------------------------------------------------------------------- U_INPUT_RAM : entity work.RAM(SYNC_READ) generic map( num_words => IN_RAM_WORDS, word_width => IN_DATA_WIDTH*NUM_PIPELINES, addr_width => bitsNeeded(IN_RAM_WORDS)) port map ( clk => clk, wen => in_ram_wen, waddr => in_ram_waddr, wdata => in_ram_wdata, raddr => in_ram_raddr, rdata => in_ram_rdata); -- example addressing logic for the input RAM -- The exact logic depends on the type input source, the timing of the -- input source, etc. This example is simply meant to illustrate the -- basic concept for generating an input stream for the for the window -- generator. process(clk, rst) begin if (rst = '1') then in_ram_raddr <= (others => '0'); input_valid <= '0'; state <= WAIT_FOR_GO; elsif (rising_edge(clk)) then case state is when WAIT_FOR_GO => in_ram_raddr <= (others => '0'); input_valid <= '0'; if (go = '1') then state <= GENERATE_ADDRESS; end if; when GENERATE_ADDRESS => if (wg_ready = '1') then in_ram_raddr <= std_logic_vector(unsigned(in_ram_raddr) + 1); -- TODO: Update timing depending on latency of input source input_valid <= '1'; end if; -- TODO: Add completion logic when others => null; end case; end if; end process; ------------------------------------------------------------------------- -- Sliding-window generator ------------------------------------------------------------------------- U_WINDOW_GEN : entity work.window_gen generic map ( PARALLEL_IO => NUM_PIPELINES, MAX_WINDOW_ROWS => MAX_WINDOW_ROWS, MAX_WINDOW_COLS => MAX_WINDOW_COLS, MAX_IMAGE_ROWS => MAX_IMAGE_ROWS, MAX_IMAGE_COLS => MAX_IMAGE_COLS, INPUT0_AT_MSB => false, -- RAM likely stores first input at LSB DATA_WIDTH => IN_DATA_WIDTH) port map ( clk => clk, rst => rst, go => go, ready => wg_ready, read_enable => read_windows, empty => wg_empty, image_rows => image_rows, image_cols => image_cols, window_rows => window_rows, window_cols => window_cols, input => in_ram_rdata, -- input from RAM input_valid => input_valid, -- TODO: Make sure this logic is timed -- appropriately. output => wg_out, window_valid => window_valid, done => wg_done ); -- The output of the window buffer is a huge std_logic_vector that -- represents all NUM_PIPELINES windows. This code converts the huge vector -- into an 2D array representation that is easier to work with. -- -- This would be made much easier by VHDL 2008, where the generator could -- output this array itself. Once 2008 is more widely supported, we plan to -- add a 2008 wrapper around the window generator to provide a more -- convenient interface. process(wg_out) variable temp_window : window_t; begin for i in 0 to NUM_PIPELINES-1 loop devectorizeWindow(wg_out, temp_window, i); windows(i) <= temp_window; end loop; end process; -- read/remove the current windows when the generator isn't empty -- TODO: add pipeline enable here if necessary (e.g. likely shouldn't read -- if the pipeline is stalled) read_windows <= not wg_empty; ------------------------------------------------------------------------- -- Replicated Pipelines -- TODO: Add sliding-window function here for each window. ------------------------------------------------------------------------- U_PIPELINES : for i in 0 to NUM_PIPELINES-1 generate -- determine the validity of each pipeline input (i.e. window) -- TODO: add pipeline enable here if necessary (e.g., if the window -- wasn't read from the generator, you might not want to tell the -- pipeline the input is valid) pipe_valid_in(i) <= window_valid(i); -- TODO: INSTANTIATE SLIDING-WINDOW FUNCTION PIPELINES -- FOR EACH WIDOW window(i) end generate; ------------------------------------------------------------------------- -- Output -- Notes: Like the input source, the output can potentially be any circuit -- that can accept a stream of pipeline outputs. -- -- One additional challenge for storing outputs is that there are cases -- where the window generator will output less than NUM_PIPELINES windows, -- in which case some of the pipeline outputs will be invalid while others -- are valid. -- -- To deal with this situation, we recommend several possibilities. One -- simple solution if storing to memory is to also store the invalid -- outputs and then use softwareto filter out the invalid outputs. -- A second option is to use a FIFO-like entity that can accept a -- variable number of inputs (i.e. pipeline outputs) every cycle. -- In this case, the FIFO will only store the valid outputs, -- which filters out the invalid outputs. If connecting the pipeline -- outputs to another downstream entity, it may also be convenient to -- filter out the invalid outputs there. ------------------------------------------------------------------------- U_OUTPUT_RAM : entity work.RAM(SYNC_READ) generic map( num_words => OUT_RAM_WORDS, word_width => OUT_DATA_WIDTH, addr_width => bitsNeeded(OUT_RAM_WORDS)) port map ( clk => clk, wen => out_ram_wen, waddr => out_ram_waddr, wdata => out_ram_wdata, raddr => out_ram_raddr, rdata => out_ram_rdata); end default;
gpl-3.0
2a964d315cd1761b6c61489b2efc558d
0.564789
4.396379
false
false
false
false
SylvainLesne/openPOWERLINK_V2
hardware/ipcore/common/lib/src/nShiftRegRtl.vhd
3
5,381
------------------------------------------------------------------------------- --! @file nShiftRegRtl.vhd -- --! @brief Shift register with n-bit-width -- --! @details This shift register implementation provides a configurable width. ------------------------------------------------------------------------------- -- -- (c) B&R, 2014 -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; --! Common library library libcommon; --! Use common library global package use libcommon.global.all; entity nShiftReg is generic ( --! Data width gWidth : natural := 8; --! Number of tabs gTabs : natural := 4; --! Shift direction ("left" or "right") gShiftDir : string := "left" ); port ( --! Asynchronous reset iArst : in std_logic; --! Clock iClk : in std_logic; --! Parallel Load iLoad : in std_logic; --! Shift Enable iShift : in std_logic; --! Load Data (gTabs x gWidth) iLoadData : in std_logic_vector(gWidth*gTabs-1 downto 0); --! Parallel Output Data oParData : out std_logic_vector(gWidth*gTabs-1 downto 0); --! Input Shift Data iData : in std_logic_vector(gWidth-1 downto 0); --! Ouptut Shift Data oData : out std_logic_vector(gWidth-1 downto 0) ); end nShiftReg; architecture rtl of nShiftReg is --! Shift register type type tShiftReg is array (gTabs-1 downto 0) of std_logic_vector(gWidth-1 downto 0); --! Function to convert std_logic_vector into tShiftReg function convStdLogicToShiftReg (din : std_logic_vector) return tShiftReg is variable vTmp : tShiftReg; begin --default vTmp := (others => (others => cInactivated)); --loop tab-wise for i in gTabs-1 downto 0 loop vTmp(i) := din((i+1)*gWidth-1 downto i*gWidth); end loop; return vTmp; end function; --! Function to convert tShiftReg into std_logic_vector function convShiftRegToStdLogic (din : tShiftReg) return std_logic_vector is variable vTmp : std_logic_vector(gWidth*gTabs-1 downto 0); begin --default vTmp := (others => cInactivated); --loop tab-wise for i in gTabs-1 downto 0 loop vTmp((i+1)*gWidth-1 downto i*gWidth) := din(i); end loop; return vTmp; end function; --! Shift register signal reg, reg_next : tShiftReg; begin assert (gShiftDir = "left" or gShiftDir = "right") report "Set either left or right for shift direction!" severity failure; --serial output oData <= reg(reg'right) when gShiftDir = "right" else reg(reg'left); --parallel output oParData <= convShiftRegToStdLogic(reg); --! Process doing loading and shifting comb : process ( reg, iLoad, iShift, iLoadData, iData ) begin --default reg_next <= reg; if iLoad = cActivated then reg_next <= convStdLogicToShiftReg(iLoadData); elsif iShift = cActivated then if gShiftDir = "right" then reg_next <= iData & reg(reg'left downto 1); else reg_next <= reg(reg'left-1 downto 0) & iData; end if; end if; end process; --! Register process regClk : process(iArst, iClk) begin if iArst = cActivated then reg <= (others => (others => cInactivated)); elsif rising_edge(iClk) then reg <= reg_next; end if; end process; end rtl;
gpl-2.0
f3a93d26cc51bbccdbe08503e15ff325
0.60026
4.407043
false
false
false
false
cnplab/blockmon
fw-combo/src/netcope-sim/synth_models/tsu_async.vhd
1
57,200
-------------------------------------------------------------------------------- -- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: O.40d -- \ \ Application: netgen -- / / Filename: tsu_async.vhd -- /___/ /\ Timestamp: Wed Mar 30 10:05:04 2011 -- \ \ / \ -- \___\/\___\ -- -- Command : -ofmt vhdl -w ngc/tsu_async.ngc sim/synth_models/tsu_async.vhd -- Device : xc5vlx155t-2-ff1136 -- Input file : ngc/tsu_async.ngc -- Output file : sim/synth_models/tsu_async.vhd -- # of Entities : 1 -- Design Name : tsu_async -- Xilinx : /usr/local/fpga/xilinx131/ISE_DS/ISE/ -- -- Purpose: -- This VHDL netlist is a verification model and uses simulation -- primitives which may not represent the true implementation of the -- device, however the netlist is functionally correct and should not -- be modified. This file cannot be synthesized and should only be used -- with supported simulation tools. -- -- Reference: -- Command Line Tools User Guide, Chapter 23 -- Synthesis and Simulation Design Guide, Chapter 6 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; use UNISIM.VPKG.ALL; entity tsu_async is port ( IN_TS_DV : in STD_LOGIC := 'X'; IN_CLK : in STD_LOGIC := 'X'; RESET : in STD_LOGIC := 'X'; OUT_TS_DV : out STD_LOGIC; OUT_CLK : in STD_LOGIC := 'X'; OUT_TS : out STD_LOGIC_VECTOR ( 63 downto 0 ); IN_TS : in STD_LOGIC_VECTOR ( 63 downto 0 ) ); end tsu_async; architecture STRUCTURE of tsu_async is signal N0 : STD_LOGIC; signal NlwRenamedSig_OI_OUT_TS_DV : STD_LOGIC; signal ts_data_asfifo_cnt_read_addr_up_reg_cnt_or0000 : STD_LOGIC; signal ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000 : STD_LOGIC; signal ts_data_asfifo_full_allow : STD_LOGIC; signal ts_data_asfifo_read_nextgray_0_xor0000 : STD_LOGIC; signal ts_data_asfifo_regasync_empty_166 : STD_LOGIC; signal ts_data_asfifo_regasync_full_167 : STD_LOGIC; signal ts_data_asfifo_write_nextgray_0_xor0000 : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory64_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory63_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory62_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory61_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory60_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory59_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory58_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory57_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory56_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory55_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory54_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory53_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory52_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory51_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory49_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory48_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory50_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory47_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory46_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory45_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory44_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory43_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory42_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory40_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory39_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory41_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory38_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory37_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory36_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory35_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory34_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory33_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory31_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory30_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory32_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory29_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory28_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory27_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory26_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory25_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory24_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory22_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory21_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory23_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory20_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory19_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory18_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory17_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory16_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory15_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory13_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory12_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory14_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory11_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory10_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory9_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory8_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory7_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory6_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory4_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory3_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory5_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory2_SPO_UNCONNECTED : STD_LOGIC; signal NLW_ts_data_asfifo_MEM_U_Mram_memory1_SPO_UNCONNECTED : STD_LOGIC; signal ts_data_asfifo_cnt_read_addr_up_cin : STD_LOGIC_VECTOR ( 1 downto 1 ); signal ts_data_asfifo_cnt_read_addr_up_reg_cnt : STD_LOGIC_VECTOR ( 1 downto 0 ); signal ts_data_asfifo_cnt_read_addr_up_s : STD_LOGIC_VECTOR ( 1 downto 0 ); signal ts_data_asfifo_cnt_read_addr_up_xo : STD_LOGIC_VECTOR ( 1 downto 0 ); signal ts_data_asfifo_cnt_write_addr_u_cin : STD_LOGIC_VECTOR ( 1 downto 1 ); signal ts_data_asfifo_cnt_write_addr_u_reg_cnt : STD_LOGIC_VECTOR ( 1 downto 0 ); signal ts_data_asfifo_cnt_write_addr_u_s : STD_LOGIC_VECTOR ( 1 downto 0 ); signal ts_data_asfifo_cnt_write_addr_u_xo : STD_LOGIC_VECTOR ( 1 downto 0 ); signal ts_data_asfifo_ecomp : STD_LOGIC_VECTOR ( 1 downto 0 ); signal ts_data_asfifo_emuxcyo : STD_LOGIC_VECTOR ( 2 downto 1 ); signal ts_data_asfifo_fcomp : STD_LOGIC_VECTOR ( 1 downto 0 ); signal ts_data_asfifo_fmuxcyo : STD_LOGIC_VECTOR ( 2 downto 1 ); signal ts_data_asfifo_read_addrgray : STD_LOGIC_VECTOR ( 1 downto 0 ); signal ts_data_asfifo_read_lastgray : STD_LOGIC_VECTOR ( 1 downto 0 ); signal ts_data_asfifo_read_nextgray : STD_LOGIC_VECTOR ( 1 downto 0 ); signal ts_data_asfifo_write_addrgray : STD_LOGIC_VECTOR ( 1 downto 0 ); signal ts_data_asfifo_write_nextgray : STD_LOGIC_VECTOR ( 1 downto 0 ); begin OUT_TS_DV <= NlwRenamedSig_OI_OUT_TS_DV; XST_GND : GND port map ( G => N0 ); XST_VCC : VCC port map ( P => NlwRenamedSig_OI_OUT_TS_DV ); ts_data_asfifo_cnt_read_addr_up_reg_cnt_0 : FDCE port map ( C => OUT_CLK, CE => ts_data_asfifo_cnt_read_addr_up_reg_cnt_or0000, CLR => RESET, D => ts_data_asfifo_cnt_read_addr_up_xo(0), Q => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0) ); ts_data_asfifo_cnt_read_addr_up_reg_cnt_1 : FDCE port map ( C => OUT_CLK, CE => ts_data_asfifo_cnt_read_addr_up_reg_cnt_or0000, CLR => RESET, D => ts_data_asfifo_cnt_read_addr_up_xo(1), Q => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1) ); ts_data_asfifo_cnt_read_addr_up_gen_width_gt1_gen_muxcy_l_0_MUXCY_L_U : MUXCY_L port map ( CI => NlwRenamedSig_OI_OUT_TS_DV, DI => N0, S => ts_data_asfifo_cnt_read_addr_up_s(0), LO => ts_data_asfifo_cnt_read_addr_up_cin(1) ); ts_data_asfifo_cnt_read_addr_up_gen_width_gt1_gen_lut1_l_0_gen_init_const_up_LUT1_L_U : LUT1_L generic map( INIT => X"2" ) port map ( I0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), LO => ts_data_asfifo_cnt_read_addr_up_s(0) ); ts_data_asfifo_cnt_read_addr_up_gen_width_gt1_gen_lut1_l_1_gen_init_const_up_LUT1_L_U : LUT1_L generic map( INIT => X"2" ) port map ( I0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), LO => ts_data_asfifo_cnt_read_addr_up_s(1) ); ts_data_asfifo_cnt_read_addr_up_gen_width_gt1_gen_xorcy_0_XORCY_U : XORCY port map ( CI => NlwRenamedSig_OI_OUT_TS_DV, LI => ts_data_asfifo_cnt_read_addr_up_s(0), O => ts_data_asfifo_cnt_read_addr_up_xo(0) ); ts_data_asfifo_cnt_read_addr_up_gen_width_gt1_gen_xorcy_1_XORCY_U : XORCY port map ( CI => ts_data_asfifo_cnt_read_addr_up_cin(1), LI => ts_data_asfifo_cnt_read_addr_up_s(1), O => ts_data_asfifo_cnt_read_addr_up_xo(1) ); ts_data_asfifo_cnt_write_addr_u_reg_cnt_0 : FDCE port map ( C => IN_CLK, CE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, CLR => RESET, D => ts_data_asfifo_cnt_write_addr_u_xo(0), Q => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0) ); ts_data_asfifo_cnt_write_addr_u_reg_cnt_1 : FDCE port map ( C => IN_CLK, CE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, CLR => RESET, D => ts_data_asfifo_cnt_write_addr_u_xo(1), Q => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1) ); ts_data_asfifo_cnt_write_addr_u_gen_width_gt1_gen_muxcy_l_0_MUXCY_L_U : MUXCY_L port map ( CI => NlwRenamedSig_OI_OUT_TS_DV, DI => N0, S => ts_data_asfifo_cnt_write_addr_u_s(0), LO => ts_data_asfifo_cnt_write_addr_u_cin(1) ); ts_data_asfifo_cnt_write_addr_u_gen_width_gt1_gen_lut1_l_0_gen_init_const_up_LUT1_L_U : LUT1_L generic map( INIT => X"2" ) port map ( I0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), LO => ts_data_asfifo_cnt_write_addr_u_s(0) ); ts_data_asfifo_cnt_write_addr_u_gen_width_gt1_gen_lut1_l_1_gen_init_const_up_LUT1_L_U : LUT1_L generic map( INIT => X"2" ) port map ( I0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), LO => ts_data_asfifo_cnt_write_addr_u_s(1) ); ts_data_asfifo_cnt_write_addr_u_gen_width_gt1_gen_xorcy_0_XORCY_U : XORCY port map ( CI => NlwRenamedSig_OI_OUT_TS_DV, LI => ts_data_asfifo_cnt_write_addr_u_s(0), O => ts_data_asfifo_cnt_write_addr_u_xo(0) ); ts_data_asfifo_cnt_write_addr_u_gen_width_gt1_gen_xorcy_1_XORCY_U : XORCY port map ( CI => ts_data_asfifo_cnt_write_addr_u_cin(1), LI => ts_data_asfifo_cnt_write_addr_u_s(1), O => ts_data_asfifo_cnt_write_addr_u_xo(1) ); ts_data_asfifo_FMUXCY_GEN_1_fmuxcyX : MUXCY_L port map ( CI => ts_data_asfifo_fmuxcyo(1), DI => N0, S => ts_data_asfifo_fcomp(1), LO => ts_data_asfifo_fmuxcyo(2) ); ts_data_asfifo_FMUXCY_GEN_0_fmuxcyX : MUXCY_L port map ( CI => NlwRenamedSig_OI_OUT_TS_DV, DI => N0, S => ts_data_asfifo_fcomp(0), LO => ts_data_asfifo_fmuxcyo(1) ); ts_data_asfifo_EMUXCY_GEN_1_emuxcyX : MUXCY_L port map ( CI => ts_data_asfifo_emuxcyo(1), DI => N0, S => ts_data_asfifo_ecomp(1), LO => ts_data_asfifo_emuxcyo(2) ); ts_data_asfifo_EMUXCY_GEN_0_emuxcyX : MUXCY_L port map ( CI => NlwRenamedSig_OI_OUT_TS_DV, DI => N0, S => ts_data_asfifo_ecomp(0), LO => ts_data_asfifo_emuxcyo(1) ); ts_data_asfifo_MEM_U_Mram_memory64 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(63), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory64_SPO_UNCONNECTED, DPO => OUT_TS(63) ); ts_data_asfifo_MEM_U_Mram_memory63 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(62), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory63_SPO_UNCONNECTED, DPO => OUT_TS(62) ); ts_data_asfifo_MEM_U_Mram_memory62 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(61), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory62_SPO_UNCONNECTED, DPO => OUT_TS(61) ); ts_data_asfifo_MEM_U_Mram_memory61 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(60), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory61_SPO_UNCONNECTED, DPO => OUT_TS(60) ); ts_data_asfifo_MEM_U_Mram_memory60 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(59), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory60_SPO_UNCONNECTED, DPO => OUT_TS(59) ); ts_data_asfifo_MEM_U_Mram_memory59 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(58), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory59_SPO_UNCONNECTED, DPO => OUT_TS(58) ); ts_data_asfifo_MEM_U_Mram_memory58 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(57), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory58_SPO_UNCONNECTED, DPO => OUT_TS(57) ); ts_data_asfifo_MEM_U_Mram_memory57 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(56), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory57_SPO_UNCONNECTED, DPO => OUT_TS(56) ); ts_data_asfifo_MEM_U_Mram_memory56 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(55), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory56_SPO_UNCONNECTED, DPO => OUT_TS(55) ); ts_data_asfifo_MEM_U_Mram_memory55 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(54), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory55_SPO_UNCONNECTED, DPO => OUT_TS(54) ); ts_data_asfifo_MEM_U_Mram_memory54 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(53), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory54_SPO_UNCONNECTED, DPO => OUT_TS(53) ); ts_data_asfifo_MEM_U_Mram_memory53 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(52), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory53_SPO_UNCONNECTED, DPO => OUT_TS(52) ); ts_data_asfifo_MEM_U_Mram_memory52 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(51), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory52_SPO_UNCONNECTED, DPO => OUT_TS(51) ); ts_data_asfifo_MEM_U_Mram_memory51 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(50), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory51_SPO_UNCONNECTED, DPO => OUT_TS(50) ); ts_data_asfifo_MEM_U_Mram_memory49 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(48), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory49_SPO_UNCONNECTED, DPO => OUT_TS(48) ); ts_data_asfifo_MEM_U_Mram_memory48 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(47), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory48_SPO_UNCONNECTED, DPO => OUT_TS(47) ); ts_data_asfifo_MEM_U_Mram_memory50 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(49), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory50_SPO_UNCONNECTED, DPO => OUT_TS(49) ); ts_data_asfifo_MEM_U_Mram_memory47 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(46), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory47_SPO_UNCONNECTED, DPO => OUT_TS(46) ); ts_data_asfifo_MEM_U_Mram_memory46 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(45), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory46_SPO_UNCONNECTED, DPO => OUT_TS(45) ); ts_data_asfifo_MEM_U_Mram_memory45 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(44), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory45_SPO_UNCONNECTED, DPO => OUT_TS(44) ); ts_data_asfifo_MEM_U_Mram_memory44 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(43), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory44_SPO_UNCONNECTED, DPO => OUT_TS(43) ); ts_data_asfifo_MEM_U_Mram_memory43 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(42), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory43_SPO_UNCONNECTED, DPO => OUT_TS(42) ); ts_data_asfifo_MEM_U_Mram_memory42 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(41), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory42_SPO_UNCONNECTED, DPO => OUT_TS(41) ); ts_data_asfifo_MEM_U_Mram_memory40 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(39), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory40_SPO_UNCONNECTED, DPO => OUT_TS(39) ); ts_data_asfifo_MEM_U_Mram_memory39 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(38), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory39_SPO_UNCONNECTED, DPO => OUT_TS(38) ); ts_data_asfifo_MEM_U_Mram_memory41 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(40), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory41_SPO_UNCONNECTED, DPO => OUT_TS(40) ); ts_data_asfifo_MEM_U_Mram_memory38 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(37), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory38_SPO_UNCONNECTED, DPO => OUT_TS(37) ); ts_data_asfifo_MEM_U_Mram_memory37 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(36), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory37_SPO_UNCONNECTED, DPO => OUT_TS(36) ); ts_data_asfifo_MEM_U_Mram_memory36 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(35), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory36_SPO_UNCONNECTED, DPO => OUT_TS(35) ); ts_data_asfifo_MEM_U_Mram_memory35 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(34), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory35_SPO_UNCONNECTED, DPO => OUT_TS(34) ); ts_data_asfifo_MEM_U_Mram_memory34 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(33), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory34_SPO_UNCONNECTED, DPO => OUT_TS(33) ); ts_data_asfifo_MEM_U_Mram_memory33 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(32), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory33_SPO_UNCONNECTED, DPO => OUT_TS(32) ); ts_data_asfifo_MEM_U_Mram_memory31 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(30), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory31_SPO_UNCONNECTED, DPO => OUT_TS(30) ); ts_data_asfifo_MEM_U_Mram_memory30 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(29), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory30_SPO_UNCONNECTED, DPO => OUT_TS(29) ); ts_data_asfifo_MEM_U_Mram_memory32 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(31), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory32_SPO_UNCONNECTED, DPO => OUT_TS(31) ); ts_data_asfifo_MEM_U_Mram_memory29 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(28), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory29_SPO_UNCONNECTED, DPO => OUT_TS(28) ); ts_data_asfifo_MEM_U_Mram_memory28 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(27), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory28_SPO_UNCONNECTED, DPO => OUT_TS(27) ); ts_data_asfifo_MEM_U_Mram_memory27 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(26), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory27_SPO_UNCONNECTED, DPO => OUT_TS(26) ); ts_data_asfifo_MEM_U_Mram_memory26 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(25), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory26_SPO_UNCONNECTED, DPO => OUT_TS(25) ); ts_data_asfifo_MEM_U_Mram_memory25 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(24), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory25_SPO_UNCONNECTED, DPO => OUT_TS(24) ); ts_data_asfifo_MEM_U_Mram_memory24 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(23), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory24_SPO_UNCONNECTED, DPO => OUT_TS(23) ); ts_data_asfifo_MEM_U_Mram_memory22 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(21), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory22_SPO_UNCONNECTED, DPO => OUT_TS(21) ); ts_data_asfifo_MEM_U_Mram_memory21 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(20), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory21_SPO_UNCONNECTED, DPO => OUT_TS(20) ); ts_data_asfifo_MEM_U_Mram_memory23 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(22), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory23_SPO_UNCONNECTED, DPO => OUT_TS(22) ); ts_data_asfifo_MEM_U_Mram_memory20 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(19), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory20_SPO_UNCONNECTED, DPO => OUT_TS(19) ); ts_data_asfifo_MEM_U_Mram_memory19 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(18), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory19_SPO_UNCONNECTED, DPO => OUT_TS(18) ); ts_data_asfifo_MEM_U_Mram_memory18 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(17), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory18_SPO_UNCONNECTED, DPO => OUT_TS(17) ); ts_data_asfifo_MEM_U_Mram_memory17 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(16), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory17_SPO_UNCONNECTED, DPO => OUT_TS(16) ); ts_data_asfifo_MEM_U_Mram_memory16 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(15), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory16_SPO_UNCONNECTED, DPO => OUT_TS(15) ); ts_data_asfifo_MEM_U_Mram_memory15 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(14), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory15_SPO_UNCONNECTED, DPO => OUT_TS(14) ); ts_data_asfifo_MEM_U_Mram_memory13 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(12), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory13_SPO_UNCONNECTED, DPO => OUT_TS(12) ); ts_data_asfifo_MEM_U_Mram_memory12 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(11), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory12_SPO_UNCONNECTED, DPO => OUT_TS(11) ); ts_data_asfifo_MEM_U_Mram_memory14 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(13), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory14_SPO_UNCONNECTED, DPO => OUT_TS(13) ); ts_data_asfifo_MEM_U_Mram_memory11 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(10), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory11_SPO_UNCONNECTED, DPO => OUT_TS(10) ); ts_data_asfifo_MEM_U_Mram_memory10 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(9), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory10_SPO_UNCONNECTED, DPO => OUT_TS(9) ); ts_data_asfifo_MEM_U_Mram_memory9 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(8), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory9_SPO_UNCONNECTED, DPO => OUT_TS(8) ); ts_data_asfifo_MEM_U_Mram_memory8 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(7), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory8_SPO_UNCONNECTED, DPO => OUT_TS(7) ); ts_data_asfifo_MEM_U_Mram_memory7 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(6), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory7_SPO_UNCONNECTED, DPO => OUT_TS(6) ); ts_data_asfifo_MEM_U_Mram_memory6 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(5), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory6_SPO_UNCONNECTED, DPO => OUT_TS(5) ); ts_data_asfifo_MEM_U_Mram_memory4 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(3), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory4_SPO_UNCONNECTED, DPO => OUT_TS(3) ); ts_data_asfifo_MEM_U_Mram_memory3 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(2), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory3_SPO_UNCONNECTED, DPO => OUT_TS(2) ); ts_data_asfifo_MEM_U_Mram_memory5 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(4), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory5_SPO_UNCONNECTED, DPO => OUT_TS(4) ); ts_data_asfifo_MEM_U_Mram_memory2 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(1), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory2_SPO_UNCONNECTED, DPO => OUT_TS(1) ); ts_data_asfifo_MEM_U_Mram_memory1 : RAM32X1D port map ( A0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), A1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), A2 => N0, A3 => N0, A4 => N0, D => IN_TS(0), DPRA0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), DPRA1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), DPRA2 => N0, DPRA3 => N0, DPRA4 => N0, WCLK => IN_CLK, WE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, SPO => NLW_ts_data_asfifo_MEM_U_Mram_memory1_SPO_UNCONNECTED, DPO => OUT_TS(0) ); ts_data_asfifo_read_lastgray_0 : FDPE port map ( C => OUT_CLK, CE => ts_data_asfifo_cnt_read_addr_up_reg_cnt_or0000, D => ts_data_asfifo_read_addrgray(0), PRE => RESET, Q => ts_data_asfifo_read_lastgray(0) ); ts_data_asfifo_read_lastgray_1 : FDCE port map ( C => OUT_CLK, CE => ts_data_asfifo_cnt_read_addr_up_reg_cnt_or0000, CLR => RESET, D => ts_data_asfifo_read_addrgray(1), Q => ts_data_asfifo_read_lastgray(1) ); ts_data_asfifo_write_addrgray_1 : FDPE port map ( C => IN_CLK, CE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, D => ts_data_asfifo_write_nextgray(1), PRE => RESET, Q => ts_data_asfifo_write_addrgray(1) ); ts_data_asfifo_write_addrgray_0 : FDPE port map ( C => IN_CLK, CE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, D => ts_data_asfifo_write_nextgray(0), PRE => RESET, Q => ts_data_asfifo_write_addrgray(0) ); ts_data_asfifo_read_addrgray_1 : FDPE port map ( C => OUT_CLK, CE => ts_data_asfifo_cnt_read_addr_up_reg_cnt_or0000, D => ts_data_asfifo_read_nextgray(1), PRE => RESET, Q => ts_data_asfifo_read_addrgray(1) ); ts_data_asfifo_read_addrgray_0 : FDPE port map ( C => OUT_CLK, CE => ts_data_asfifo_cnt_read_addr_up_reg_cnt_or0000, D => ts_data_asfifo_read_nextgray(0), PRE => RESET, Q => ts_data_asfifo_read_addrgray(0) ); ts_data_asfifo_regasync_empty : FDP port map ( C => OUT_CLK, D => ts_data_asfifo_emuxcyo(2), PRE => RESET, Q => ts_data_asfifo_regasync_empty_166 ); ts_data_asfifo_write_nextgray_0 : FDCE port map ( C => IN_CLK, CE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, CLR => RESET, D => ts_data_asfifo_write_nextgray_0_xor0000, Q => ts_data_asfifo_write_nextgray(0) ); ts_data_asfifo_regasync_full : FDPE port map ( C => IN_CLK, CE => ts_data_asfifo_full_allow, D => ts_data_asfifo_fmuxcyo(2), PRE => RESET, Q => ts_data_asfifo_regasync_full_167 ); ts_data_asfifo_read_nextgray_0 : FDCE port map ( C => OUT_CLK, CE => ts_data_asfifo_cnt_read_addr_up_reg_cnt_or0000, CLR => RESET, D => ts_data_asfifo_read_nextgray_0_xor0000, Q => ts_data_asfifo_read_nextgray(0) ); ts_data_asfifo_write_nextgray_1 : FDPE port map ( C => IN_CLK, CE => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000, D => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), PRE => RESET, Q => ts_data_asfifo_write_nextgray(1) ); ts_data_asfifo_read_nextgray_1 : FDPE port map ( C => OUT_CLK, CE => ts_data_asfifo_cnt_read_addr_up_reg_cnt_or0000, D => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), PRE => RESET, Q => ts_data_asfifo_read_nextgray(1) ); ts_data_asfifo_Mxor_write_nextgray_0_xor0000_Result1 : LUT2 generic map( INIT => X"6" ) port map ( I0 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(0), I1 => ts_data_asfifo_cnt_write_addr_u_reg_cnt(1), O => ts_data_asfifo_write_nextgray_0_xor0000 ); ts_data_asfifo_Mxor_read_nextgray_0_xor0000_Result1 : LUT2 generic map( INIT => X"6" ) port map ( I0 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(0), I1 => ts_data_asfifo_cnt_read_addr_up_reg_cnt(1), O => ts_data_asfifo_read_nextgray_0_xor0000 ); ts_data_asfifo_fcomp_1_or00001 : LUT4 generic map( INIT => X"E14B" ) port map ( I0 => ts_data_asfifo_regasync_full_167, I1 => ts_data_asfifo_write_nextgray(1), I2 => ts_data_asfifo_read_lastgray(1), I3 => ts_data_asfifo_write_addrgray(1), O => ts_data_asfifo_fcomp(1) ); ts_data_asfifo_ecomp_1_or00001 : LUT4 generic map( INIT => X"E14B" ) port map ( I0 => ts_data_asfifo_regasync_empty_166, I1 => ts_data_asfifo_read_nextgray(1), I2 => ts_data_asfifo_write_addrgray(1), I3 => ts_data_asfifo_read_addrgray(1), O => ts_data_asfifo_ecomp(1) ); ts_data_asfifo_fcomp_0_or00001 : LUT4 generic map( INIT => X"E14B" ) port map ( I0 => ts_data_asfifo_regasync_full_167, I1 => ts_data_asfifo_write_nextgray(0), I2 => ts_data_asfifo_read_lastgray(0), I3 => ts_data_asfifo_write_addrgray(0), O => ts_data_asfifo_fcomp(0) ); ts_data_asfifo_ecomp_0_or00001 : LUT4 generic map( INIT => X"E14B" ) port map ( I0 => ts_data_asfifo_regasync_empty_166, I1 => ts_data_asfifo_read_nextgray(0), I2 => ts_data_asfifo_write_addrgray(0), I3 => ts_data_asfifo_read_addrgray(0), O => ts_data_asfifo_ecomp(0) ); ts_data_asfifo_write_allow1 : LUT2 generic map( INIT => X"2" ) port map ( I0 => IN_TS_DV, I1 => ts_data_asfifo_regasync_full_167, O => ts_data_asfifo_cnt_write_addr_u_reg_cnt_or0000 ); ts_data_asfifo_full_allow1 : LUT2 generic map( INIT => X"E" ) port map ( I0 => ts_data_asfifo_regasync_full_167, I1 => IN_TS_DV, O => ts_data_asfifo_full_allow ); ts_data_asfifo_read_allow1_INV_0 : INV port map ( I => ts_data_asfifo_regasync_empty_166, O => ts_data_asfifo_cnt_read_addr_up_reg_cnt_or0000 ); end STRUCTURE;
bsd-3-clause
78df119e4b8b7f52fe0494341298e955
0.575804
2.624576
false
false
false
false
cnplab/blockmon
fw-combo/src/common/frame_fifo.vhd
1
6,462
-- ----------------------------------------------------------------- -- FIFO with a FrameLink interface -- ----------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use work.math_pack.all; entity FRAME_FIFO is generic ( DATA_WIDTH : integer := 64; DEPTH : integer := 512 ); port ( -- global FPGA clock CLK : in std_logic; -- global synchronous reset RESET : in std_logic; -- RX FrameLink interface RX_DATA : in std_logic_vector(DATA_WIDTH-1 downto 0); RX_REM : in std_logic_vector(log2(DATA_WIDTH/8) - 1 downto 0); RX_SOF_N : in std_logic; RX_EOF_N : in std_logic; RX_SOP_N : in std_logic; RX_EOP_N : in std_logic; RX_SRC_RDY_N : in std_logic; RX_DST_RDY_N : out std_logic; -- TX FrameLink interface TX_DATA : out std_logic_vector(DATA_WIDTH-1 downto 0); TX_REM : out std_logic_vector(log2(DATA_WIDTH/8) - 1 downto 0); TX_SOF_N : out std_logic; TX_EOF_N : out std_logic; TX_SOP_N : out std_logic; TX_EOP_N : out std_logic; TX_SRC_RDY_N : out std_logic; TX_DST_RDY_N : in std_logic ); end entity FRAME_FIFO; architecture behavioral of FRAME_FIFO is -- FIFO width: with control signals constant FIFO_DATA_WIDTH : integer := DATA_WIDTH + log2(DATA_WIDTH/8) + 4; -- ----------------------------------------------------------------- -- Signals -- ----------------------------------------------------------------- -- FIFO connection signal fifo_data_in : std_logic_vector(FIFO_DATA_WIDTH-1 downto 0); signal fifo_data_out : std_logic_vector(FIFO_DATA_WIDTH-1 downto 0); signal fifo_full : std_logic; signal fifo_empty : std_logic; signal fifo_write_en : std_logic; signal fifo_read_en : std_logic; -- Keep data control signal data_long_stored : std_logic; signal data_just_stored : std_logic; signal data_just_unstored : std_logic; signal data_stored : std_logic; signal data_from_fifo : std_logic; -- Keep data signal tx_data_read : std_logic_vector(DATA_WIDTH-1 downto 0); signal tx_rem_read : std_logic_vector(log2(DATA_WIDTH/8) - 1 downto 0); signal tx_sof_n_read : std_logic; signal tx_eof_n_read : std_logic; signal tx_sop_n_read : std_logic; signal tx_eop_n_read : std_logic; signal tx_data_keep : std_logic_vector(DATA_WIDTH-1 downto 0); signal tx_rem_keep : std_logic_vector(log2(DATA_WIDTH/8) - 1 downto 0); signal tx_sof_n_keep : std_logic; signal tx_eof_n_keep : std_logic; signal tx_sop_n_keep : std_logic; signal tx_eop_n_keep : std_logic; begin -- ----------------------------------------------------------------- -- Simple FIFO instance -- ----------------------------------------------------------------- SIMPLE_FIFO_inst : entity work.SIMPLE_FIFO generic map ( DATA_WIDTH => FIFO_DATA_WIDTH, DEPTH => DEPTH ) port map ( CLK => CLK, RESET => RESET, DATA_IN => fifo_data_in, WRITE_EN => fifo_write_en, DATA_OUT => fifo_data_out, READ_EN => fifo_read_en, STATE_FULL => fifo_full, STATE_EMPTY => fifo_empty ); -- ----------------------------------------------------------------- -- Logic -- ----------------------------------------------------------------- -- FIFO data connection fifo_data_in <= RX_DATA & RX_REM & RX_SOF_N & RX_EOF_N & RX_SOP_N & RX_EOP_N; tx_data_read <= fifo_data_out(FIFO_DATA_WIDTH-1 downto FIFO_DATA_WIDTH-DATA_WIDTH); tx_rem_read <= fifo_data_out(FIFO_DATA_WIDTH-DATA_WIDTH-1 downto 4); tx_sof_n_read <= fifo_data_out(3); tx_eof_n_read <= fifo_data_out(2); tx_sop_n_read <= fifo_data_out(1); tx_eop_n_read <= fifo_data_out(0); -- FrameLink write connections RX_DST_RDY_N <= fifo_full; fifo_write_en <= (not RX_SRC_RDY_N) and (not fifo_full); -- FrameLink read connections: keep data if dst not ready process(CLK) begin if (CLK'event and CLK = '1') then if (RESET = '1') then data_long_stored <= '0'; else if (TX_DST_RDY_N = '0') then data_long_stored <= '0'; elsif (data_just_stored = '1') then data_long_stored <= '1'; end if; data_from_fifo <= fifo_read_en; end if; end if; end process; data_just_stored <= data_from_fifo and TX_DST_RDY_N; data_just_unstored <= (not data_from_fifo) and (not TX_DST_RDY_N); data_stored <= (data_just_stored or data_long_stored) and not data_just_unstored; fifo_read_en <= (not data_stored) and (not fifo_empty); TX_SRC_RDY_N <= (not data_from_fifo) and (not data_long_stored); -- Keep the read values if destination is not ready TX_DATA <= tx_data_read when (data_from_fifo = '1') else tx_data_keep; TX_REM <= tx_rem_read when (data_from_fifo = '1') else tx_rem_keep; TX_SOF_N <= tx_sof_n_read when (data_from_fifo = '1') else tx_sof_n_keep; TX_EOF_N <= tx_eof_n_read when (data_from_fifo = '1') else tx_eof_n_keep; TX_SOP_N <= tx_sop_n_read when (data_from_fifo = '1') else tx_sop_n_keep; TX_EOP_N <= tx_eop_n_read when (data_from_fifo = '1') else tx_eop_n_keep; process(CLK) begin if (CLK'event and CLK = '1') then if (RESET = '1') then tx_data_keep <= (others => '0'); tx_rem_keep <= (others => '0'); tx_sof_n_keep <= '0'; tx_eof_n_keep <= '0'; tx_sop_n_keep <= '0'; tx_eop_n_keep <= '0'; elsif (data_from_fifo = '1') then tx_data_keep <= tx_data_read; tx_rem_keep <= tx_rem_read; tx_sof_n_keep <= tx_sof_n_read; tx_eof_n_keep <= tx_eof_n_read; tx_sop_n_keep <= tx_sop_n_read; tx_eop_n_keep <= tx_eop_n_read; end if; end if; end process; end;
bsd-3-clause
fd59ca7d9d15d016453bcc1e2fd910f6
0.495822
3.422669
false
false
false
false
SylvainLesne/openPOWERLINK_V2
hardware/ipcore/xilinx/parallelinterface/src/parallelInterface-rtl-ea.vhd
3
18,895
------------------------------------------------------------------------------- --! @file parallelInterfaceRtl.vhd -- --! @brief Parallel Interface for Host Interface -- --! @details This is the parallel interface implementation for --! the host interface suitable for inbuilt Xilinx EPC. -- ------------------------------------------------------------------------------- -- -- Copyright (c) 2014, Bernecker+Rainer Industrie-Elektronik Ges.m.b.H. (B&R) -- Copyright (c) 2014, Kalycito Infotech Private Limited. -- All rights reserved. -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- --! Use standard ieee library library ieee; --! Use logic elements use ieee.std_logic_1164.all; --! Use numerics use ieee.numeric_std.all; --! Common library library libcommon; --! Use common library global package use libcommon.global.all; --! Work library library work; --! use host interface package for specific types use work.hostInterfacePkg.all; entity parallelInterface is generic ( --! Data bus width gDataWidth : natural := 16; --! Address and Data bus are multiplexed (0 = FALSE, otherwise = TRUE) gMultiplex : natural := 0 ); port ( -- Parallel Interface --! Chip select iParHostChipselect : in std_logic := cInactivated; --! Read strobe iParHostRead : in std_logic := cInactivated; --! Write strobe iParHostWrite : in std_logic := cInactivated; --! Address Latch enable (Multiplexed only) iParHostAddressLatchEnable : in std_logic := cInactivated; --! High active Acknowledge oParHostAcknowledge : out std_logic := cInactivated; --! Byte enable iParHostByteenable : in std_logic_vector(gDataWidth/cByte-1 downto 0) := (others => cInactivated); --! Address bus (De-multiplexed, word-address) iParHostAddress : in std_logic_vector(15 downto 0) := (others => cInactivated); --! Data bus out (De-multiplexed) oParHostData : out std_logic_vector(gDataWidth-1 downto 0) := (others => cInactivated); --! Data bus in (De-multiplexed) iParHostData : in std_logic_vector(gDataWidth-1 downto 0) := (others => cInactivated); --! Data bus output enable (De-multiplexed) oParHostDataEnable : out std_logic; --! Address/Data bus out (Multiplexed, word-address)) oParHostAddressData : out std_logic_vector(gDataWidth-1 downto 0) := (others => cInactivated); --! Address/Data bus in (Multiplexed, word-address)) iParHostAddressData : in std_logic_vector(gDataWidth-1 downto 0) := (others => cInactivated); --! Address/Data bus output enable (Multiplexed, word-address)) oParHostAddressDataEnable : out std_logic; -- Clock/Reset sources --! Clock Source input iClk : in std_logic:= cInactivated; --! Reset Source input iRst : in std_logic:= cInactivated; -- Memory Mapped Slave for Host --! MM slave host address oHostAddress : out std_logic_vector(16 downto 2) := (others => cInactivated); --! MM slave host byte enable oHostByteenable : out std_logic_vector(3 downto 0) := (others => cInactivated); --! MM slave host read oHostRead : out std_logic := cInactivated; --! MM slave host read data iHostReaddata : in std_logic_vector(31 downto 0) := (others => cInactivated); --! MM slave host write oHostWrite : out std_logic := cInactivated; --! MM slave host write data oHostWritedata : out std_logic_vector(31 downto 0) := (others => cInactivated); --! MM slave host wait request iHostWaitrequest : in std_logic := cInactivated ); end parallelInterface; architecture rtl of parallelInterface is --! address register to store the address populated to the interface signal addressRegister : std_logic_vector(iParHostAddress'range); --! register clock enable signal addressRegClkEnable : std_logic; --! byte enable register to store byte enable qualifiers signal byteenableRegister : std_logic_vector(gDataWidth/cByte-1 downto 0); --! register clock enable signal byteenableRegClkEnable : std_logic; --! write data register to store the data populated to the interface signal writeDataRegister : std_logic_vector(gDataWidth-1 downto 0); --! register clock enable signal writeDataRegClkEnable : std_logic; --! read data register to store the read data populated to the host signal readDataRegister : std_logic_vector(gDataWidth-1 downto 0); --! temporary readDataRegister signal readDataRegister_next : std_logic_vector(gDataWidth-1 downto 0); -- synchronized signals --! Synchronized chip select signal signal hostChipselect : std_logic; --! Write signal for initialize the transfer signal hostWrite : std_logic; --! Synchronized Write signal signal hostWrite_noCs : std_logic; --! Read signal for initialize transfer signal hostRead : std_logic; --! Synchronized Read signal signal hostRead_noCs : std_logic; --! Address latch Enable signal hostAle : std_logic; --! Synchronized Address Latch Enable signal signal hostAle_noCs : std_logic; --! signal hostAle_noCsEdge : std_logic; --! Data Enable signal hostDataEnable : std_logic; --! Registered data Enable signal hostDataEnable_reg : std_logic; --! Transfer complete Acknowledgement signal signal hostAck : std_logic; --! Transfer complete Acknowledgement signal for registering signal hostAck_reg : std_logic; -- fsm --! FSM state for Parallel Interface type tFsm is (sIdle, sDo, sWait, sDone ); --! state signal signal fsm : tFsm; -- Counter will enable only after the wait request gets activated. --! timeout counter width constant cCountWidth : natural := 4; --! Timeout counter signal count : std_logic_vector(cCountWidth-1 downto 0); --! MSB of timeout counter alias countTc : std_logic is count(cCountWidth-1); --! Enable counter signal countEn : std_logic; --! Reset counter signal countRst : std_logic; --! Enable ACK for Write operations constant cCountWrAckAct : std_logic_vector(count'range) := "0000"; --0 --! Disable ACK for Write operations constant cCountWrAckDea : std_logic_vector(count'range) := "0111";--1 --! Enable ACK for Read operations constant cCountRdAckAct : std_logic_vector(count'range) := "0010";--1 --! Disable ACK for Read operations constant cCountRdAckDea : std_logic_vector(count'range) := "0111";--2 begin --! The processes describe the register, which store the unsynchronized --! inputs! reg : process(iClk) begin if rising_edge(iClk) then if iRst = cActivated then addressRegister <= (others => cInactivated); byteenableRegister <= (others => cInactivated); writeDataRegister <= (others => cInactivated); readDataRegister <= (others => cInactivated); hostDataEnable_reg <= cInactivated; hostAck_reg <= cInactivated; else hostDataEnable_reg <= hostDataEnable; hostAck_reg <= hostAck; if byteenableRegClkEnable = cActivated then byteenableRegister <= iParHostByteenable; end if; if addressRegClkEnable = cActivated then if gMultiplex = 0 then addressRegister <= iParHostAddress; else addressRegister <= iParHostAddressData; end if; end if; if writeDataRegClkEnable = cActivated then if gMultiplex = 0 then writeDataRegister <= iParHostData; else writeDataRegister <= iParHostAddressData; end if; end if; if iHostWaitrequest = cInactivated and hostRead = cActivated then readDataRegister <= readDataRegister_next; end if; end if; end if; end process; oHostAddress <= addressRegister(15 downto 1); oParHostDataEnable <= hostDataEnable_reg; oParHostAddressDataEnable <= hostDataEnable_reg; oParHostAcknowledge <= hostAck_reg; oParHostAddressData <= readDataRegister; oParHostData <= readDataRegister; countRst <= cActivated when fsm = sIdle else cInactivated; countEn <= cActivated when fsm = sWait else cInactivated; --! combinatoric process for ack and output enable generation combProc : process ( count, hostWrite, hostRead, fsm ) begin -- default assignments to avoid unwanted latches hostAck <= cInactivated; hostDataEnable <= cInactivated; if fsm = sWait then if hostRead = cActivated then -- activate ack signal for read if count >= cCountRdAckAct and count <= cCountRdAckDea then hostAck <= cActivated; end if; elsif hostWrite = cActivated then -- activate ack signal for write if count >= cCountWrAckAct and count <= cCountWrAckDea then hostAck <= cActivated; end if; end if; end if; -- Keep Data available at Bus until the read operations ends at Master -- side if fsm = sWait or fsm = sDone then if hostRead = cActivated then hostDataEnable <= cActivated; end if; end if; end process; --! Fsm to control access and timeout counter fsmProc : process(iClk) begin if rising_edge(iClk) then if iRst = cActivated then fsm <= sIdle; addressRegClkEnable <= cInactivated; byteenableRegClkEnable <= cInactivated; writeDataRegClkEnable <= cInactivated; oHostWrite <= cInactivated; oHostRead <= cInactivated; count <= (others => cInactivated); else if countRst = cActivated then count <= (others => cInactivated); elsif countEn = cActivated and countTc /= cActivated then count <= std_logic_vector(unsigned(count) + 1); end if; --defaults addressRegClkEnable <= cInactivated; byteenableRegClkEnable <= cInactivated; writeDataRegClkEnable <= cInactivated; oHostWrite <= cInactivated; oHostRead <= cInactivated; if hostAle = cActivated and gMultiplex /= 0 then addressRegClkEnable <= cActivated; end if; case fsm is --Start the operations if Read/write activated by Master when sIdle => if hostRead = cActivated or hostWrite = cActivated then fsm <= sDo; if gMultiplex = 0 then addressRegClkEnable <= cActivated; end if; byteenableRegClkEnable <= cActivated; writeDataRegClkEnable <= hostWrite; end if; --Wait for the response from Avalon side when sDo => oHostRead <= hostRead; oHostWrite <= hostWrite; if iHostWaitrequest = cInactivated then fsm <= sWait; oHostRead <= cInactivated; oHostWrite <= cInactivated; end if; -- Generate ACK signals when sWait => if countTc = cActivated then fsm <= sDone; end if; --Wait for transfer to end at Parallel Master side when sDone => if (hostRead = cInactivated and hostWrite = cInactivated) then fsm <= sIdle; else fsm <= sDone; end if; end case; end if; end if; end process; -- Generate signals for DWORD data width genHostBusDword : if gDataWidth = cDword generate begin oHostByteenable <= byteenableRegister; oHostWritedata <= writeDataRegister; readDataRegister_next <= iHostReaddata; end generate; -- Generate signals for WORD data width genHostBusWord : if gDataWidth = cWord generate begin oHostWritedata <= writeDataRegister & writeDataRegister; --! Create ByteEnable and Read data from WORD based signals busCombProc : process ( byteenableRegister, addressRegister, iHostReaddata ) begin --default assignments (to avoid evil latches) oHostByteenable <= (others => cInactivated); readDataRegister_next <= (others => cInactivated); -- assign byte enable to lower/upper word for i in gDataWidth/8-1 downto 0 loop if addressRegister(addressRegister'right) = cActivated then -- upper word is selected oHostByteenable(cWord/cByte+i) <= byteenableRegister(i); else -- lower word is selected oHostByteenable(i) <= byteenableRegister(i); end if; end loop; -- assign lower/upper word to output for i in gDataWidth-1 downto 0 loop if addressRegister(addressRegister'right) = cActivated then -- upper word is selected readDataRegister_next(i) <= iHostReaddata(cWord+i); else -- lower word is selected readDataRegister_next(i) <= iHostReaddata(i); end if; end loop; end process; end generate; -- synchronize all available control signals --! Two synchronizer for ChipSelect syncChipselect : entity libcommon.synchronizer generic map ( gStages => 2, gInit => cInactivated ) port map ( iArst => iRst, iClk => iClk, iAsync => iParHostChipselect, oSync => hostChipselect ); --! Two synchronizer for Write syncWrite : entity libcommon.synchronizer generic map ( gStages => 2, gInit => cInactivated ) port map ( iArst => iRst, iClk => iClk, iAsync => iParHostWrite, oSync => hostWrite_noCs ); hostWrite <= hostChipselect and hostWrite_noCs; --! Two synchronizer for Read syncRead : entity libcommon.synchronizer generic map ( gStages => 2, gInit => cInactivated ) port map ( iArst => iRst, iClk => iClk, iAsync => iParHostRead, oSync => hostRead_noCs ); hostRead <= hostChipselect and hostRead_noCs; genSyncAle : if gMultiplex /= 0 generate begin --! Two synchronizer for ALE syncAle : entity libcommon.synchronizer generic map ( gStages => 2, gInit => cInactivated ) port map ( iArst => iRst, iClk => iClk, iAsync => iParHostAddressLatchEnable, oSync => hostAle_noCs ); --! Edge Detector for ALE edgeAle : entity libcommon.edgedetector port map ( iArst => iRst, iClk => iClk, iEnable => cActivated, iData => hostAle_noCs, oRising => hostAle_noCsEdge, oFalling => open, oAny => open ); hostAle <= hostChipselect and hostAle_noCsEdge; end generate; end rtl;
gpl-2.0
3ba3eed7b390ea63ee27432ffb6abc8f
0.556338
5.565538
false
false
false
false
marcelokk/ir_controller
ir_decoder.vhd
1
2,984
libraRY ieee; use ieee.std_LOGIC_1164.all; use ieee.std_LOGIC_ARITH.all; use ieee.std_LOGIC_unsigned.all; use ieee.numeric_std.all; entity ir_decoder is port( clk : in std_logic; reset : in std_logic; ir_signal : in std_logic; led0 : out std_logic; led1 : out std_logic; led2 : out std_logic; led3 : out std_logic; led4 : out std_logic; output : out std_logic_vector(15 downto 0) ); end ir_decoder; ARCHITECTURE main of ir_decoder is type states is (waiting, header, receiving); constant nbits : integer := 3; begin -- Maquina de Controle process(clk, reset) variable contador : integer; variable received_bits : integer; variable output_buffer : std_logic_vector(15 downto 0); variable state : states; variable next_state : states; begin if(reset = '1') then contador := 0; received_bits := 0; output_buffer := x"0000"; state := waiting; next_state := header; led0 <= '0'; led1 <= '0'; led2 <= '0'; led3 <= '0'; led4 <= '0'; elsif(clk'event and clk = '1') then case state is when waiting => led0 <= '1'; led1 <= '0'; led2 <= '0'; contador := 0; -- reseta contador if(ir_signal = '1') then state := next_state; end if; when header => led0 <= '0'; led1 <= '1'; led2 <= '0'; led3 <= '0'; if(ir_signal = '0') then -- parou de receber sinal if(0 <= contador and contador < 2300) then -- nao recebeu o header state := waiting; next_state := header; else -- recebeu o header contador := 0; -- reseta contador state := waiting; next_state := receiving; end if; end if; when receiving => led0 <= '0'; led1 <= '0'; led2 <= '1'; --output <= CONV_STD_LOGIC_VECTOR(CONV_INTEGER(received_bits), 16); if(received_bits = nbits) then state := waiting; next_state := header; received_bits := 0; output <= output_buffer; led4 <= '1'; end if; if(ir_signal = '0') then -- parou de receber sinal if(400 < contador and contador < 800) then -- bit 0 = 600 output_buffer(nbits - received_bits - 1) := '0'; received_bits := received_bits + 1; state := waiting; next_state := receiving; elsif(1000 < contador and contador < 1400) then -- bit 1 = 1200 output_buffer(nbits - received_bits - 1) := '1'; received_bits := received_bits + 1; state := waiting; next_state := receiving; else state := waiting; next_state := header; received_bits := 0; led3 <= '1'; --output <= CONV_STD_LOGIC_VECTOR(CONV_INTEGER(received_bits), 16); end if; end if; end case; -- sempre conta if(ir_signal = '1') then contador := contador + 1; end if; end if; end process; end main;
mit
5926367bab9a9f34e1a5c187282ab755
0.546247
3.101871
false
false
false
false
SylvainLesne/openPOWERLINK_V2
staging/fpga/boards/altera/SYSTEC_ECUcore-EP3C/design_nios2_directIO/altpll0.vhd
8
16,616
-- megafunction wizard: %ALTPLL% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altpll -- ============================================================ -- File Name: altpll0.vhd -- Megafunction Name(s): -- altpll -- -- Simulation Library Files(s): -- altera_mf -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 11.0 Build 208 07/03/2011 SP 1 SJ Web Edition -- ************************************************************ --Copyright (C) 1991-2011 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY altpll0 IS PORT ( inclk0 : IN STD_LOGIC := '0'; c0 : OUT STD_LOGIC ; c1 : OUT STD_LOGIC ; locked : OUT STD_LOGIC ); END altpll0; ARCHITECTURE SYN OF altpll0 IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC ; SIGNAL sub_wire2 : STD_LOGIC ; SIGNAL sub_wire3 : STD_LOGIC ; SIGNAL sub_wire4 : STD_LOGIC ; SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0); SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0); SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0); COMPONENT altpll GENERIC ( bandwidth_type : STRING; clk0_divide_by : NATURAL; clk0_duty_cycle : NATURAL; clk0_multiply_by : NATURAL; clk0_phase_shift : STRING; clk1_divide_by : NATURAL; clk1_duty_cycle : NATURAL; clk1_multiply_by : NATURAL; clk1_phase_shift : STRING; compensate_clock : STRING; inclk0_input_frequency : NATURAL; intended_device_family : STRING; lpm_hint : STRING; lpm_type : STRING; operation_mode : STRING; pll_type : STRING; port_activeclock : STRING; port_areset : STRING; port_clkbad0 : STRING; port_clkbad1 : STRING; port_clkloss : STRING; port_clkswitch : STRING; port_configupdate : STRING; port_fbin : STRING; port_inclk0 : STRING; port_inclk1 : STRING; port_locked : STRING; port_pfdena : STRING; port_phasecounterselect : STRING; port_phasedone : STRING; port_phasestep : STRING; port_phaseupdown : STRING; port_pllena : STRING; port_scanaclr : STRING; port_scanclk : STRING; port_scanclkena : STRING; port_scandata : STRING; port_scandataout : STRING; port_scandone : STRING; port_scanread : STRING; port_scanwrite : STRING; port_clk0 : STRING; port_clk1 : STRING; port_clk2 : STRING; port_clk3 : STRING; port_clk4 : STRING; port_clk5 : STRING; port_clkena0 : STRING; port_clkena1 : STRING; port_clkena2 : STRING; port_clkena3 : STRING; port_clkena4 : STRING; port_clkena5 : STRING; port_extclk0 : STRING; port_extclk1 : STRING; port_extclk2 : STRING; port_extclk3 : STRING; self_reset_on_loss_lock : STRING; width_clock : NATURAL ); PORT ( clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); locked : OUT STD_LOGIC ); END COMPONENT; BEGIN sub_wire6_bv(0 DOWNTO 0) <= "0"; sub_wire6 <= To_stdlogicvector(sub_wire6_bv); sub_wire3 <= sub_wire0(0); sub_wire1 <= sub_wire0(1); c1 <= sub_wire1; locked <= sub_wire2; c0 <= sub_wire3; sub_wire4 <= inclk0; sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4; altpll_component : altpll GENERIC MAP ( bandwidth_type => "AUTO", clk0_divide_by => 1, clk0_duty_cycle => 50, clk0_multiply_by => 1, clk0_phase_shift => "0", clk1_divide_by => 1, clk1_duty_cycle => 50, clk1_multiply_by => 2, clk1_phase_shift => "0", compensate_clock => "CLK0", inclk0_input_frequency => 20000, intended_device_family => "Cyclone III", lpm_hint => "CBX_MODULE_PREFIX=altpll0", lpm_type => "altpll", operation_mode => "NORMAL", pll_type => "AUTO", port_activeclock => "PORT_UNUSED", port_areset => "PORT_UNUSED", port_clkbad0 => "PORT_UNUSED", port_clkbad1 => "PORT_UNUSED", port_clkloss => "PORT_UNUSED", port_clkswitch => "PORT_UNUSED", port_configupdate => "PORT_UNUSED", port_fbin => "PORT_UNUSED", port_inclk0 => "PORT_USED", port_inclk1 => "PORT_UNUSED", port_locked => "PORT_USED", port_pfdena => "PORT_UNUSED", port_phasecounterselect => "PORT_UNUSED", port_phasedone => "PORT_UNUSED", port_phasestep => "PORT_UNUSED", port_phaseupdown => "PORT_UNUSED", port_pllena => "PORT_UNUSED", port_scanaclr => "PORT_UNUSED", port_scanclk => "PORT_UNUSED", port_scanclkena => "PORT_UNUSED", port_scandata => "PORT_UNUSED", port_scandataout => "PORT_UNUSED", port_scandone => "PORT_UNUSED", port_scanread => "PORT_UNUSED", port_scanwrite => "PORT_UNUSED", port_clk0 => "PORT_USED", port_clk1 => "PORT_USED", port_clk2 => "PORT_UNUSED", port_clk3 => "PORT_UNUSED", port_clk4 => "PORT_UNUSED", port_clk5 => "PORT_UNUSED", port_clkena0 => "PORT_UNUSED", port_clkena1 => "PORT_UNUSED", port_clkena2 => "PORT_UNUSED", port_clkena3 => "PORT_UNUSED", port_clkena4 => "PORT_UNUSED", port_clkena5 => "PORT_UNUSED", port_extclk0 => "PORT_UNUSED", port_extclk1 => "PORT_UNUSED", port_extclk2 => "PORT_UNUSED", port_extclk3 => "PORT_UNUSED", self_reset_on_loss_lock => "OFF", width_clock => 5 ) PORT MAP ( inclk => sub_wire5, clk => sub_wire0, locked => sub_wire2 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" -- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" -- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" -- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" -- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" -- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" -- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" -- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" -- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" -- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" -- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" -- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" -- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" -- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000" -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" -- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" -- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" -- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" -- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" -- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" -- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" -- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" -- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" -- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" -- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" -- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" -- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" -- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" -- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" -- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" -- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" -- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" -- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" -- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll0.mif" -- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" -- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" -- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" -- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" -- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" -- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" -- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" -- Retrieval info: PRIVATE: SPREAD_USE STRING "0" -- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" -- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" -- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" -- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" -- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: USE_CLK0 STRING "1" -- Retrieval info: PRIVATE: USE_CLK1 STRING "1" -- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" -- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" -- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" -- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" -- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" -- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" -- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" -- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" -- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" -- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" -- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" -- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" -- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 -- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.ppf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.bsf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_inst.vhd FALSE -- Retrieval info: LIB_FILE: altera_mf -- Retrieval info: CBX_MODULE_PREFIX: ON
gpl-2.0
7ca8a0df15f26cc48e70a0aea186a78d
0.699988
3.322535
false
false
false
false
ARC-Lab-UF/window_gen
src/wg_fifo.vhd
1
7,265
-- Copyright (c) University of Florida -- -- This file is part of window_gen. -- -- window_gen is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- window_gen is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with window_gen. If not, see <http://www.gnu.org/licenses/>. -- Greg Stitt -- University of Florida -- Description: This entity maintains the FIFO used in each row of a -- window buffer. This FIFO differs from others by having a read option and a -- pop option, which are maintained by different pointers. The read option -- simply scans through the FIFO contents without removing any data. -- This functionality is needed because the window buffer will read the same -- FIFO data multiple times before popping data out of the buffer. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.math_custom.all; ------------------------------------------------------------------------------- -- Generics Description -- DATA_WIDTH : The width of each element in the FIFO. -- ADDR_WIDTH : The address width of the FIFO. This defines the number of -- maximum number of words in the FIFO as 2**ADDR_WIDTH. -- SIZE_WIDTH : The width of the size input. ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Port Descriptions (all control signals are active high) -- clk: Clock -- rst: Asynchronous reset -- wen : '1' to write current input into fifo -- wdata : Write data -- ren : '1' to read from the current read pointer without removing data from -- the FIFO. -- pop : '1' to pop data from from fifo (i.e. a traditional FIFO read) -- read_reset : Resets read pointer to back to actual front of FIFO -- read_empty : '1' if nothing to read -- rdata : Data read/output from the fifo -- empty : '1' if empty for popping -- full : '1' if full -- size : The size of the fifo. This can be any value from 1 to 2**ADDR_WIDTH. -- The size is used to determine when full should be asserted. ------------------------------------------------------------------------------- entity wg_fifo is generic ( DATA_WIDTH : positive; ADDR_WIDTH : positive; SIZE_WIDTH : positive); port ( clk : in std_logic; rst : in std_logic; wen : in std_logic; wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); ren : in std_logic; -- doesn't decrement count pop : in std_logic; -- decrements count read_reset : in std_logic; read_empty : out std_logic; -- similar to empty, but for reads rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); empty : out std_logic; full : out std_logic; size : in std_logic_vector(SIZE_WIDTH-1 downto 0) ); end wg_fifo; architecture RTL of wg_fifo is signal front, next_front : unsigned(ADDR_WIDTH-1 downto 0); signal back, next_back : unsigned(ADDR_WIDTH-1 downto 0); signal read_ptr, next_read_ptr : unsigned(ADDR_WIDTH-1 downto 0); signal count, next_count : unsigned(SIZE_WIDTH-1 downto 0); signal read_count, next_read_count : unsigned(SIZE_WIDTH-1 downto 0); signal wen_ram : std_logic; signal full_s : std_logic; signal empty_s : std_logic; signal read_empty_s : std_logic; begin -- instantiate RAM uses for FIFO storage U_RAM : entity work.ram(SYNC_READ_DURING_WRITE) generic map ( NUM_WORDS => 2**ADDR_WIDTH, WORD_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH) port map ( clk => clk, wen => wen_ram, waddr => std_logic_vector(back), wdata => wdata, raddr => std_logic_vector(next_read_ptr), rdata => rdata); -- create necessary registers process(clk, rst) begin if (rst = '1') then front <= (others => '0'); back <= (others => '0'); read_ptr <= (others => '0'); count <= (others => '0'); read_count <= (others => '0'); elsif(clk'event and clk = '1') then count <= next_count; read_count <= next_read_count; back <= next_back; front <= next_front; read_ptr <= next_read_ptr; end if; end process; -- combinational logic for maintaining FIFO process (front, back, read_ptr, count, read_count, wen, ren, pop, read_reset, full_s, read_empty_s, empty_s) variable temp_count : unsigned(SIZE_WIDTH-1 downto 0); variable temp_read_count : unsigned(SIZE_WIDTH-1 downto 0); begin temp_count := count; temp_read_count := read_count; -- if data is pushed in, move back and increment counts if (wen = '1' and full_s = '0') then next_back <= back + 1; temp_count := temp_count + 1; temp_read_count := temp_read_count + 1; else next_back <= back; end if; -- read_reset resets the read_ptr to the front pointer if (read_reset = '1') then next_read_ptr <= front; temp_read_count := temp_count; elsif (ren = '1' and read_empty_s = '0') then -- if a read, advance the read pointer, but do not move front next_read_ptr <= read_ptr + 1; temp_read_count := temp_read_count - 1; else next_read_ptr <= read_ptr; end if; -- a pop moves front and updates the count, and resets the read_ptr if (pop = '1' and empty_s = '0') then next_front <= front + 1; next_read_ptr <= front + 1; temp_count := temp_count - 1; temp_read_count := temp_count; else next_front <= front; end if; next_count <= temp_count; next_read_count <= temp_read_count; end process; full_s <= '1' when count = unsigned(size) else '0'; empty_s <= '1' when count = 0 else '0'; read_empty_s <= '1' when read_count = 0 else '0'; full <= full_s; empty <= empty_s; read_empty <= read_empty_s; -- protect against writes when full wen_ram <= '1' when wen = '1' and full_s = '0' else '0'; end RTL;
gpl-3.0
165203543a2c7a77d593efde2c2a84c8
0.532553
3.980822
false
false
false
false
chiggs/oc_mkjpeg
design/common/JPEG_PKG.vhd
1
2,509
-------------------------------------------------------------------------------- -- -- -- V H D L F I L E -- -- COPYRIGHT (C) 2009 -- -- -- -------------------------------------------------------------------------------- -- -- Title : JPEG_PKG -- Design : JPEG_ENC -- Author : Michal Krepa -- -------------------------------------------------------------------------------- -- -- File : JPEG_PKG.VHD -- Created : Sat Mar 7 2009 -- -------------------------------------------------------------------------------- -- -- Description : Package for JPEG core -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.all; use ieee.numeric_std.all; package JPEG_PKG is -- do not change, constant constant C_HDR_SIZE : integer := 623; -- warning! this parameter heavily affects memory size required -- if expected image width is known change this parameter to match this -- otherwise some onchip RAM will be wasted and never used constant C_MAX_LINE_WIDTH : integer := 640; -- memory/performance tradeoff -- 8 extra lines highest performance -- 0 extra lines lowest area --constant C_EXTRA_LINES : integer := 0; -- from 0 to 8 -- 24 bit format RGB/YCbCr 888 bits -- 16 bit format RGB/YCbCr 565 bits constant C_PIXEL_BITS : integer := 24; -- 0 = RGB -- 1 = YUV/YCbCr constant C_YUV_INPUT : std_logic := '0'; type T_SM_SETTINGS is record x_cnt : unsigned(15 downto 0); y_cnt : unsigned(15 downto 0); cmp_idx : unsigned(2 downto 0); end record; constant C_SM_SETTINGS : T_SM_SETTINGS := ( (others => '0'), (others => '0'), (others => '0') ); function log2(n : natural) return natural; end package JPEG_PKG; package body JPEG_PKG is ----------------------------------------------------------------------------- function log2(n : natural) return natural is begin for i in 0 to 31 loop if (2**i) >= n then return i; end if; end loop; return 32; end log2; ----------------------------------------------------------------------------- end package body JPEG_PKG;
lgpl-3.0
cca32140ab848b8a6b66e07def2aa460
0.394181
5.018
false
false
false
false
SylvainLesne/openPOWERLINK_V2
hardware/ipcore/altera/latch/src/dataLatch-syn-a.vhd
3
3,085
--! @file dataLatch-syn-a.vhd --! @brief Data latch generated architecture ------------------------------------------------------------------------------- -- Architecture : syn ------------------------------------------------------------------------------- -- -- (c) B&R, 2014 -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- --! Use standard ieee library library ieee; --! Use logic elements use ieee.std_logic_1164.all; --! Use libcommon library library libcommon; --! Use global package use libcommon.global.all; --! Use altera library library altera; --! Use primitive components use altera.altera_primitives_components.dlatch; --! @brief Altera data latch architecture --! @details This architecture uses an Altera primitive component for the data --! latch implementation. architecture syn of dataLatch is --! Low active clear signal nClear : std_logic; --! Low active preset signal nPreset : std_logic; begin -- Generate low active signals nClear <= not iClear; nPreset <= cnInactivated; --unused preset GEN_LATCH : for i in gDataWidth-1 downto 0 generate INST_LATCH : dlatch port map ( d => iData(i), ena => iEnable, clrn => nClear, prn => nPreset, q => oData(i) ); end generate GEN_LATCH; end architecture syn;
gpl-2.0
3daacf81e286a5d8991d8d0f76ee98d7
0.630146
4.820313
false
false
false
false
tech4me/NIOS2-DOOM
DE1_SoC_Computer/Computer_System/Computer_System_inst.vhd
1
29,586
component Computer_System is port ( adc_sclk : out std_logic; -- sclk adc_cs_n : out std_logic; -- cs_n adc_dout : in std_logic := 'X'; -- dout adc_din : out std_logic; -- din audio_ADCDAT : in std_logic := 'X'; -- ADCDAT audio_ADCLRCK : in std_logic := 'X'; -- ADCLRCK audio_BCLK : in std_logic := 'X'; -- BCLK audio_DACDAT : out std_logic; -- DACDAT audio_DACLRCK : in std_logic := 'X'; -- DACLRCK audio_clk_clk : out std_logic; -- clk audio_pll_ref_clk_clk : in std_logic := 'X'; -- clk audio_pll_ref_reset_reset : in std_logic := 'X'; -- reset av_config_SDAT : inout std_logic := 'X'; -- SDAT av_config_SCLK : out std_logic; -- SCLK expansion_jp1_export : inout std_logic_vector(31 downto 0) := (others => 'X'); -- export expansion_jp2_export : inout std_logic_vector(31 downto 0) := (others => 'X'); -- export hex3_hex0_export : out std_logic_vector(31 downto 0); -- export hex5_hex4_export : out std_logic_vector(15 downto 0); -- export hps_io_hps_io_emac1_inst_TX_CLK : out std_logic; -- hps_io_emac1_inst_TX_CLK hps_io_hps_io_emac1_inst_TXD0 : out std_logic; -- hps_io_emac1_inst_TXD0 hps_io_hps_io_emac1_inst_TXD1 : out std_logic; -- hps_io_emac1_inst_TXD1 hps_io_hps_io_emac1_inst_TXD2 : out std_logic; -- hps_io_emac1_inst_TXD2 hps_io_hps_io_emac1_inst_TXD3 : out std_logic; -- hps_io_emac1_inst_TXD3 hps_io_hps_io_emac1_inst_RXD0 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD0 hps_io_hps_io_emac1_inst_MDIO : inout std_logic := 'X'; -- hps_io_emac1_inst_MDIO hps_io_hps_io_emac1_inst_MDC : out std_logic; -- hps_io_emac1_inst_MDC hps_io_hps_io_emac1_inst_RX_CTL : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CTL hps_io_hps_io_emac1_inst_TX_CTL : out std_logic; -- hps_io_emac1_inst_TX_CTL hps_io_hps_io_emac1_inst_RX_CLK : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CLK hps_io_hps_io_emac1_inst_RXD1 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD1 hps_io_hps_io_emac1_inst_RXD2 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD2 hps_io_hps_io_emac1_inst_RXD3 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD3 hps_io_hps_io_qspi_inst_IO0 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO0 hps_io_hps_io_qspi_inst_IO1 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO1 hps_io_hps_io_qspi_inst_IO2 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO2 hps_io_hps_io_qspi_inst_IO3 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO3 hps_io_hps_io_qspi_inst_SS0 : out std_logic; -- hps_io_qspi_inst_SS0 hps_io_hps_io_qspi_inst_CLK : out std_logic; -- hps_io_qspi_inst_CLK hps_io_hps_io_sdio_inst_CMD : inout std_logic := 'X'; -- hps_io_sdio_inst_CMD hps_io_hps_io_sdio_inst_D0 : inout std_logic := 'X'; -- hps_io_sdio_inst_D0 hps_io_hps_io_sdio_inst_D1 : inout std_logic := 'X'; -- hps_io_sdio_inst_D1 hps_io_hps_io_sdio_inst_CLK : out std_logic; -- hps_io_sdio_inst_CLK hps_io_hps_io_sdio_inst_D2 : inout std_logic := 'X'; -- hps_io_sdio_inst_D2 hps_io_hps_io_sdio_inst_D3 : inout std_logic := 'X'; -- hps_io_sdio_inst_D3 hps_io_hps_io_usb1_inst_D0 : inout std_logic := 'X'; -- hps_io_usb1_inst_D0 hps_io_hps_io_usb1_inst_D1 : inout std_logic := 'X'; -- hps_io_usb1_inst_D1 hps_io_hps_io_usb1_inst_D2 : inout std_logic := 'X'; -- hps_io_usb1_inst_D2 hps_io_hps_io_usb1_inst_D3 : inout std_logic := 'X'; -- hps_io_usb1_inst_D3 hps_io_hps_io_usb1_inst_D4 : inout std_logic := 'X'; -- hps_io_usb1_inst_D4 hps_io_hps_io_usb1_inst_D5 : inout std_logic := 'X'; -- hps_io_usb1_inst_D5 hps_io_hps_io_usb1_inst_D6 : inout std_logic := 'X'; -- hps_io_usb1_inst_D6 hps_io_hps_io_usb1_inst_D7 : inout std_logic := 'X'; -- hps_io_usb1_inst_D7 hps_io_hps_io_usb1_inst_CLK : in std_logic := 'X'; -- hps_io_usb1_inst_CLK hps_io_hps_io_usb1_inst_STP : out std_logic; -- hps_io_usb1_inst_STP hps_io_hps_io_usb1_inst_DIR : in std_logic := 'X'; -- hps_io_usb1_inst_DIR hps_io_hps_io_usb1_inst_NXT : in std_logic := 'X'; -- hps_io_usb1_inst_NXT hps_io_hps_io_spim1_inst_CLK : out std_logic; -- hps_io_spim1_inst_CLK hps_io_hps_io_spim1_inst_MOSI : out std_logic; -- hps_io_spim1_inst_MOSI hps_io_hps_io_spim1_inst_MISO : in std_logic := 'X'; -- hps_io_spim1_inst_MISO hps_io_hps_io_spim1_inst_SS0 : out std_logic; -- hps_io_spim1_inst_SS0 hps_io_hps_io_uart0_inst_RX : in std_logic := 'X'; -- hps_io_uart0_inst_RX hps_io_hps_io_uart0_inst_TX : out std_logic; -- hps_io_uart0_inst_TX hps_io_hps_io_i2c0_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c0_inst_SDA hps_io_hps_io_i2c0_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c0_inst_SCL hps_io_hps_io_i2c1_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c1_inst_SDA hps_io_hps_io_i2c1_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c1_inst_SCL hps_io_hps_io_gpio_inst_GPIO09 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO09 hps_io_hps_io_gpio_inst_GPIO35 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO35 hps_io_hps_io_gpio_inst_GPIO40 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO40 hps_io_hps_io_gpio_inst_GPIO41 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO41 hps_io_hps_io_gpio_inst_GPIO48 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO48 hps_io_hps_io_gpio_inst_GPIO53 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO53 hps_io_hps_io_gpio_inst_GPIO54 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO54 hps_io_hps_io_gpio_inst_GPIO61 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO61 irda_TXD : out std_logic; -- TXD irda_RXD : in std_logic := 'X'; -- RXD leds_export : out std_logic_vector(9 downto 0); -- export memory_mem_a : out std_logic_vector(14 downto 0); -- mem_a memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba memory_mem_ck : out std_logic; -- mem_ck memory_mem_ck_n : out std_logic; -- mem_ck_n memory_mem_cke : out std_logic; -- mem_cke memory_mem_cs_n : out std_logic; -- mem_cs_n memory_mem_ras_n : out std_logic; -- mem_ras_n memory_mem_cas_n : out std_logic; -- mem_cas_n memory_mem_we_n : out std_logic; -- mem_we_n memory_mem_reset_n : out std_logic; -- mem_reset_n memory_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq memory_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs memory_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n memory_mem_odt : out std_logic; -- mem_odt memory_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin ps2_port_CLK : inout std_logic := 'X'; -- CLK ps2_port_DAT : inout std_logic := 'X'; -- DAT ps2_port_dual_CLK : inout std_logic := 'X'; -- CLK ps2_port_dual_DAT : inout std_logic := 'X'; -- DAT pushbuttons_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export sdram_addr : out std_logic_vector(12 downto 0); -- addr sdram_ba : out std_logic_vector(1 downto 0); -- ba sdram_cas_n : out std_logic; -- cas_n sdram_cke : out std_logic; -- cke sdram_cs_n : out std_logic; -- cs_n sdram_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq sdram_dqm : out std_logic_vector(1 downto 0); -- dqm sdram_ras_n : out std_logic; -- ras_n sdram_we_n : out std_logic; -- we_n sdram_clk_clk : out std_logic; -- clk slider_switches_export : in std_logic_vector(9 downto 0) := (others => 'X'); -- export system_pll_ref_clk_clk : in std_logic := 'X'; -- clk system_pll_ref_reset_reset : in std_logic := 'X'; -- reset vga_CLK : out std_logic; -- CLK vga_HS : out std_logic; -- HS vga_VS : out std_logic; -- VS vga_BLANK : out std_logic; -- BLANK vga_SYNC : out std_logic; -- SYNC vga_R : out std_logic_vector(7 downto 0); -- R vga_G : out std_logic_vector(7 downto 0); -- G vga_B : out std_logic_vector(7 downto 0); -- B vga_pll_ref_clk_clk : in std_logic := 'X'; -- clk vga_pll_ref_reset_reset : in std_logic := 'X'; -- reset video_in_TD_CLK27 : in std_logic := 'X'; -- TD_CLK27 video_in_TD_DATA : in std_logic_vector(7 downto 0) := (others => 'X'); -- TD_DATA video_in_TD_HS : in std_logic := 'X'; -- TD_HS video_in_TD_VS : in std_logic := 'X'; -- TD_VS video_in_clk27_reset : in std_logic := 'X'; -- clk27_reset video_in_TD_RESET : out std_logic; -- TD_RESET video_in_overflow_flag : out std_logic -- overflow_flag ); end component Computer_System; u0 : component Computer_System port map ( adc_sclk => CONNECTED_TO_adc_sclk, -- adc.sclk adc_cs_n => CONNECTED_TO_adc_cs_n, -- .cs_n adc_dout => CONNECTED_TO_adc_dout, -- .dout adc_din => CONNECTED_TO_adc_din, -- .din audio_ADCDAT => CONNECTED_TO_audio_ADCDAT, -- audio.ADCDAT audio_ADCLRCK => CONNECTED_TO_audio_ADCLRCK, -- .ADCLRCK audio_BCLK => CONNECTED_TO_audio_BCLK, -- .BCLK audio_DACDAT => CONNECTED_TO_audio_DACDAT, -- .DACDAT audio_DACLRCK => CONNECTED_TO_audio_DACLRCK, -- .DACLRCK audio_clk_clk => CONNECTED_TO_audio_clk_clk, -- audio_clk.clk audio_pll_ref_clk_clk => CONNECTED_TO_audio_pll_ref_clk_clk, -- audio_pll_ref_clk.clk audio_pll_ref_reset_reset => CONNECTED_TO_audio_pll_ref_reset_reset, -- audio_pll_ref_reset.reset av_config_SDAT => CONNECTED_TO_av_config_SDAT, -- av_config.SDAT av_config_SCLK => CONNECTED_TO_av_config_SCLK, -- .SCLK expansion_jp1_export => CONNECTED_TO_expansion_jp1_export, -- expansion_jp1.export expansion_jp2_export => CONNECTED_TO_expansion_jp2_export, -- expansion_jp2.export hex3_hex0_export => CONNECTED_TO_hex3_hex0_export, -- hex3_hex0.export hex5_hex4_export => CONNECTED_TO_hex5_hex4_export, -- hex5_hex4.export hps_io_hps_io_emac1_inst_TX_CLK => CONNECTED_TO_hps_io_hps_io_emac1_inst_TX_CLK, -- hps_io.hps_io_emac1_inst_TX_CLK hps_io_hps_io_emac1_inst_TXD0 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD0, -- .hps_io_emac1_inst_TXD0 hps_io_hps_io_emac1_inst_TXD1 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD1, -- .hps_io_emac1_inst_TXD1 hps_io_hps_io_emac1_inst_TXD2 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD2, -- .hps_io_emac1_inst_TXD2 hps_io_hps_io_emac1_inst_TXD3 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD3, -- .hps_io_emac1_inst_TXD3 hps_io_hps_io_emac1_inst_RXD0 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD0, -- .hps_io_emac1_inst_RXD0 hps_io_hps_io_emac1_inst_MDIO => CONNECTED_TO_hps_io_hps_io_emac1_inst_MDIO, -- .hps_io_emac1_inst_MDIO hps_io_hps_io_emac1_inst_MDC => CONNECTED_TO_hps_io_hps_io_emac1_inst_MDC, -- .hps_io_emac1_inst_MDC hps_io_hps_io_emac1_inst_RX_CTL => CONNECTED_TO_hps_io_hps_io_emac1_inst_RX_CTL, -- .hps_io_emac1_inst_RX_CTL hps_io_hps_io_emac1_inst_TX_CTL => CONNECTED_TO_hps_io_hps_io_emac1_inst_TX_CTL, -- .hps_io_emac1_inst_TX_CTL hps_io_hps_io_emac1_inst_RX_CLK => CONNECTED_TO_hps_io_hps_io_emac1_inst_RX_CLK, -- .hps_io_emac1_inst_RX_CLK hps_io_hps_io_emac1_inst_RXD1 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD1, -- .hps_io_emac1_inst_RXD1 hps_io_hps_io_emac1_inst_RXD2 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD2, -- .hps_io_emac1_inst_RXD2 hps_io_hps_io_emac1_inst_RXD3 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD3, -- .hps_io_emac1_inst_RXD3 hps_io_hps_io_qspi_inst_IO0 => CONNECTED_TO_hps_io_hps_io_qspi_inst_IO0, -- .hps_io_qspi_inst_IO0 hps_io_hps_io_qspi_inst_IO1 => CONNECTED_TO_hps_io_hps_io_qspi_inst_IO1, -- .hps_io_qspi_inst_IO1 hps_io_hps_io_qspi_inst_IO2 => CONNECTED_TO_hps_io_hps_io_qspi_inst_IO2, -- .hps_io_qspi_inst_IO2 hps_io_hps_io_qspi_inst_IO3 => CONNECTED_TO_hps_io_hps_io_qspi_inst_IO3, -- .hps_io_qspi_inst_IO3 hps_io_hps_io_qspi_inst_SS0 => CONNECTED_TO_hps_io_hps_io_qspi_inst_SS0, -- .hps_io_qspi_inst_SS0 hps_io_hps_io_qspi_inst_CLK => CONNECTED_TO_hps_io_hps_io_qspi_inst_CLK, -- .hps_io_qspi_inst_CLK hps_io_hps_io_sdio_inst_CMD => CONNECTED_TO_hps_io_hps_io_sdio_inst_CMD, -- .hps_io_sdio_inst_CMD hps_io_hps_io_sdio_inst_D0 => CONNECTED_TO_hps_io_hps_io_sdio_inst_D0, -- .hps_io_sdio_inst_D0 hps_io_hps_io_sdio_inst_D1 => CONNECTED_TO_hps_io_hps_io_sdio_inst_D1, -- .hps_io_sdio_inst_D1 hps_io_hps_io_sdio_inst_CLK => CONNECTED_TO_hps_io_hps_io_sdio_inst_CLK, -- .hps_io_sdio_inst_CLK hps_io_hps_io_sdio_inst_D2 => CONNECTED_TO_hps_io_hps_io_sdio_inst_D2, -- .hps_io_sdio_inst_D2 hps_io_hps_io_sdio_inst_D3 => CONNECTED_TO_hps_io_hps_io_sdio_inst_D3, -- .hps_io_sdio_inst_D3 hps_io_hps_io_usb1_inst_D0 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D0, -- .hps_io_usb1_inst_D0 hps_io_hps_io_usb1_inst_D1 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D1, -- .hps_io_usb1_inst_D1 hps_io_hps_io_usb1_inst_D2 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D2, -- .hps_io_usb1_inst_D2 hps_io_hps_io_usb1_inst_D3 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D3, -- .hps_io_usb1_inst_D3 hps_io_hps_io_usb1_inst_D4 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D4, -- .hps_io_usb1_inst_D4 hps_io_hps_io_usb1_inst_D5 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D5, -- .hps_io_usb1_inst_D5 hps_io_hps_io_usb1_inst_D6 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D6, -- .hps_io_usb1_inst_D6 hps_io_hps_io_usb1_inst_D7 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D7, -- .hps_io_usb1_inst_D7 hps_io_hps_io_usb1_inst_CLK => CONNECTED_TO_hps_io_hps_io_usb1_inst_CLK, -- .hps_io_usb1_inst_CLK hps_io_hps_io_usb1_inst_STP => CONNECTED_TO_hps_io_hps_io_usb1_inst_STP, -- .hps_io_usb1_inst_STP hps_io_hps_io_usb1_inst_DIR => CONNECTED_TO_hps_io_hps_io_usb1_inst_DIR, -- .hps_io_usb1_inst_DIR hps_io_hps_io_usb1_inst_NXT => CONNECTED_TO_hps_io_hps_io_usb1_inst_NXT, -- .hps_io_usb1_inst_NXT hps_io_hps_io_spim1_inst_CLK => CONNECTED_TO_hps_io_hps_io_spim1_inst_CLK, -- .hps_io_spim1_inst_CLK hps_io_hps_io_spim1_inst_MOSI => CONNECTED_TO_hps_io_hps_io_spim1_inst_MOSI, -- .hps_io_spim1_inst_MOSI hps_io_hps_io_spim1_inst_MISO => CONNECTED_TO_hps_io_hps_io_spim1_inst_MISO, -- .hps_io_spim1_inst_MISO hps_io_hps_io_spim1_inst_SS0 => CONNECTED_TO_hps_io_hps_io_spim1_inst_SS0, -- .hps_io_spim1_inst_SS0 hps_io_hps_io_uart0_inst_RX => CONNECTED_TO_hps_io_hps_io_uart0_inst_RX, -- .hps_io_uart0_inst_RX hps_io_hps_io_uart0_inst_TX => CONNECTED_TO_hps_io_hps_io_uart0_inst_TX, -- .hps_io_uart0_inst_TX hps_io_hps_io_i2c0_inst_SDA => CONNECTED_TO_hps_io_hps_io_i2c0_inst_SDA, -- .hps_io_i2c0_inst_SDA hps_io_hps_io_i2c0_inst_SCL => CONNECTED_TO_hps_io_hps_io_i2c0_inst_SCL, -- .hps_io_i2c0_inst_SCL hps_io_hps_io_i2c1_inst_SDA => CONNECTED_TO_hps_io_hps_io_i2c1_inst_SDA, -- .hps_io_i2c1_inst_SDA hps_io_hps_io_i2c1_inst_SCL => CONNECTED_TO_hps_io_hps_io_i2c1_inst_SCL, -- .hps_io_i2c1_inst_SCL hps_io_hps_io_gpio_inst_GPIO09 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO09, -- .hps_io_gpio_inst_GPIO09 hps_io_hps_io_gpio_inst_GPIO35 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO35, -- .hps_io_gpio_inst_GPIO35 hps_io_hps_io_gpio_inst_GPIO40 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO40, -- .hps_io_gpio_inst_GPIO40 hps_io_hps_io_gpio_inst_GPIO41 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO41, -- .hps_io_gpio_inst_GPIO41 hps_io_hps_io_gpio_inst_GPIO48 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO48, -- .hps_io_gpio_inst_GPIO48 hps_io_hps_io_gpio_inst_GPIO53 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO53, -- .hps_io_gpio_inst_GPIO53 hps_io_hps_io_gpio_inst_GPIO54 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO54, -- .hps_io_gpio_inst_GPIO54 hps_io_hps_io_gpio_inst_GPIO61 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO61, -- .hps_io_gpio_inst_GPIO61 irda_TXD => CONNECTED_TO_irda_TXD, -- irda.TXD irda_RXD => CONNECTED_TO_irda_RXD, -- .RXD leds_export => CONNECTED_TO_leds_export, -- leds.export memory_mem_a => CONNECTED_TO_memory_mem_a, -- memory.mem_a memory_mem_ba => CONNECTED_TO_memory_mem_ba, -- .mem_ba memory_mem_ck => CONNECTED_TO_memory_mem_ck, -- .mem_ck memory_mem_ck_n => CONNECTED_TO_memory_mem_ck_n, -- .mem_ck_n memory_mem_cke => CONNECTED_TO_memory_mem_cke, -- .mem_cke memory_mem_cs_n => CONNECTED_TO_memory_mem_cs_n, -- .mem_cs_n memory_mem_ras_n => CONNECTED_TO_memory_mem_ras_n, -- .mem_ras_n memory_mem_cas_n => CONNECTED_TO_memory_mem_cas_n, -- .mem_cas_n memory_mem_we_n => CONNECTED_TO_memory_mem_we_n, -- .mem_we_n memory_mem_reset_n => CONNECTED_TO_memory_mem_reset_n, -- .mem_reset_n memory_mem_dq => CONNECTED_TO_memory_mem_dq, -- .mem_dq memory_mem_dqs => CONNECTED_TO_memory_mem_dqs, -- .mem_dqs memory_mem_dqs_n => CONNECTED_TO_memory_mem_dqs_n, -- .mem_dqs_n memory_mem_odt => CONNECTED_TO_memory_mem_odt, -- .mem_odt memory_mem_dm => CONNECTED_TO_memory_mem_dm, -- .mem_dm memory_oct_rzqin => CONNECTED_TO_memory_oct_rzqin, -- .oct_rzqin ps2_port_CLK => CONNECTED_TO_ps2_port_CLK, -- ps2_port.CLK ps2_port_DAT => CONNECTED_TO_ps2_port_DAT, -- .DAT ps2_port_dual_CLK => CONNECTED_TO_ps2_port_dual_CLK, -- ps2_port_dual.CLK ps2_port_dual_DAT => CONNECTED_TO_ps2_port_dual_DAT, -- .DAT pushbuttons_export => CONNECTED_TO_pushbuttons_export, -- pushbuttons.export sdram_addr => CONNECTED_TO_sdram_addr, -- sdram.addr sdram_ba => CONNECTED_TO_sdram_ba, -- .ba sdram_cas_n => CONNECTED_TO_sdram_cas_n, -- .cas_n sdram_cke => CONNECTED_TO_sdram_cke, -- .cke sdram_cs_n => CONNECTED_TO_sdram_cs_n, -- .cs_n sdram_dq => CONNECTED_TO_sdram_dq, -- .dq sdram_dqm => CONNECTED_TO_sdram_dqm, -- .dqm sdram_ras_n => CONNECTED_TO_sdram_ras_n, -- .ras_n sdram_we_n => CONNECTED_TO_sdram_we_n, -- .we_n sdram_clk_clk => CONNECTED_TO_sdram_clk_clk, -- sdram_clk.clk slider_switches_export => CONNECTED_TO_slider_switches_export, -- slider_switches.export system_pll_ref_clk_clk => CONNECTED_TO_system_pll_ref_clk_clk, -- system_pll_ref_clk.clk system_pll_ref_reset_reset => CONNECTED_TO_system_pll_ref_reset_reset, -- system_pll_ref_reset.reset vga_CLK => CONNECTED_TO_vga_CLK, -- vga.CLK vga_HS => CONNECTED_TO_vga_HS, -- .HS vga_VS => CONNECTED_TO_vga_VS, -- .VS vga_BLANK => CONNECTED_TO_vga_BLANK, -- .BLANK vga_SYNC => CONNECTED_TO_vga_SYNC, -- .SYNC vga_R => CONNECTED_TO_vga_R, -- .R vga_G => CONNECTED_TO_vga_G, -- .G vga_B => CONNECTED_TO_vga_B, -- .B vga_pll_ref_clk_clk => CONNECTED_TO_vga_pll_ref_clk_clk, -- vga_pll_ref_clk.clk vga_pll_ref_reset_reset => CONNECTED_TO_vga_pll_ref_reset_reset, -- vga_pll_ref_reset.reset video_in_TD_CLK27 => CONNECTED_TO_video_in_TD_CLK27, -- video_in.TD_CLK27 video_in_TD_DATA => CONNECTED_TO_video_in_TD_DATA, -- .TD_DATA video_in_TD_HS => CONNECTED_TO_video_in_TD_HS, -- .TD_HS video_in_TD_VS => CONNECTED_TO_video_in_TD_VS, -- .TD_VS video_in_clk27_reset => CONNECTED_TO_video_in_clk27_reset, -- .clk27_reset video_in_TD_RESET => CONNECTED_TO_video_in_TD_RESET, -- .TD_RESET video_in_overflow_flag => CONNECTED_TO_video_in_overflow_flag -- .overflow_flag );
mit
7ce7d9d6cd351a8c7c4592af3a46ddf0
0.416447
3.373162
false
false
false
false
cnplab/blockmon
fw-combo/src/IPFIX/comp/mi32_async_arch.vhd
1
4,146
-- ----------------------------------------------------------------------- -- -- Company: INVEA-TECH a.s. -- -- Project: IPFIX design -- -- ----------------------------------------------------------------------- -- -- (c) Copyright 2011 INVEA-TECH a.s. -- All rights reserved. -- -- Please review the terms of the license agreement before using this -- file. If you are not an authorized user, please destroy this -- source code file and notify INVEA-TECH a.s. immediately that you -- inadvertently received an unauthorized copy. -- -- ----------------------------------------------------------------------- -- -- mi32_async_arch.vhd: Envelope for mi_32_async_arch_norec.vhd using t_mi32 -- inout record -- Copyright (C) 2008 CESNET -- Author(s): Jiri Matousek <[email protected]> -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in -- the documentation and/or other materials provided with the -- distribution. -- 3. Neither the name of the Company nor the names of its contributors -- may be used to endorse or promote products derived from this -- software without specific prior written permission. -- -- This software is provided ``as is'', and any express or implied -- warranties, including, but not limited to, the implied warranties of -- merchantability and fitness for a particular purpose are disclaimed. -- In no event shall the company or contributors be liable for any -- direct, indirect, incidental, special, exemplary, or consequential -- damages (including, but not limited to, procurement of substitute -- goods or services; loss of use, data, or profits; or business -- interruption) however caused and on any theory of liability, whether -- in contract, strict liability, or tort (including negligence or -- otherwise) arising in any way out of the use of this software, even -- if advised of the possibility of such damage. -- -- $Id: mi32_async_arch.vhd 6110 2008-10-26 22:48:24Z xmatou06 $ -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; -- library with MI_32 interface definition use work.lb_pkg.all; -- ---------------------------------------------------------------------------- -- Architecture -- ---------------------------------------------------------------------------- architecture full of MI32_ASYNC is begin -- ------------------------------------------------------------------------- -- Instantiation of mi32_async_norec -- ------------------------------------------------------------------------- mi32_async_norec_i: entity work.MI32_ASYNC_NOREC port map( RESET => RESET, -- Master interface CLK_M => CLK_M, MI_M_DWR => MI_M.DWR, -- Input Data MI_M_ADDR => MI_M.ADDR, -- Address MI_M_RD => MI_M.RD, -- Read Request MI_M_WR => MI_M.WR, -- Write Request MI_M_BE => MI_M.BE, -- Byte Enable MI_M_DRD => MI_M.DRD, -- Output Data MI_M_ARDY => MI_M.ARDY, -- Address Ready MI_M_DRDY => MI_M.DRDY, -- Data Ready -- Slave interface CLK_S => CLK_S, MI_S_DWR => MI_S.DWR, -- Input Data MI_S_ADDR => MI_S.ADDR, -- Address MI_S_RD => MI_S.RD, -- Read Request MI_S_WR => MI_S.WR, -- Write Request MI_S_BE => MI_S.BE, -- Byte Enable MI_S_DRD => MI_S.DRD, -- Output Data MI_S_ARDY => MI_S.ARDY, -- Address Ready MI_S_DRDY => MI_S.DRDY -- Data Ready ); end architecture full;
bsd-3-clause
d7de2a75de3ec191c8338d3142b2a5f6
0.541245
4.121272
false
false
false
false
cnplab/blockmon
fw-combo/src/IPFIX/comp/dec1fn_enable.vhd
1
3,404
-- ----------------------------------------------------------------------- -- -- Company: INVEA-TECH a.s. -- -- Project: IPFIX design -- -- ----------------------------------------------------------------------- -- -- (c) Copyright 2011 INVEA-TECH a.s. -- All rights reserved. -- -- Please review the terms of the license agreement before using this -- file. If you are not an authorized user, please destroy this -- source code file and notify INVEA-TECH a.s. immediately that you -- inadvertently received an unauthorized copy. -- -- ----------------------------------------------------------------------- -- -- -- dec1fn_enable.vhd: Decoder 1 from n with ENABLE -- Copyright (C) 2007 CESNET -- Author(s): Martin Kosek <[email protected]> -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in -- the documentation and/or other materials provided with the -- distribution. -- 3. Neither the name of the Company nor the names of its contributors -- may be used to endorse or promote products derived from this -- software without specific prior written permission. -- -- This software is provided ``as is'', and any express or implied -- warranties, including, but not limited to, the implied warranties of -- merchantability and fitness for a particular purpose are disclaimed. -- In no event shall the company or contributors be liable for any -- direct, indirect, incidental, special, exemplary, or consequential -- damages (including, but not limited to, procurement of substitute -- goods or services; loss of use, data, or profits; or business -- interruption) however caused and on any theory of liability, whether -- in contract, strict liability, or tort (including negligence or -- otherwise) arising in any way out of the use of this software, even -- if advised of the possibility of such damage. -- -- -- TODO: -- -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_arith.all; use work.math_pack.all; -- ---------------------------------------------------------------------------- -- Entity declaration -- ---------------------------------------------------------------------------- entity dec1fn_enable is generic( ITEMS : integer ); port( ADDR : in std_logic_vector(log2(ITEMS)-1 downto 0); ENABLE : in std_logic; DO : out std_logic_vector(ITEMS-1 downto 0) ); end entity dec1fn_enable; -- ---------------------------------------------------------------------------- -- Architecture declaration -- ---------------------------------------------------------------------------- architecture behavioral of dec1fn_enable is begin process(ADDR, ENABLE) begin DO <= (others => '0'); if ENABLE = '1' then for i in 0 to (ITEMS-1) loop if (conv_std_logic_vector(i, log2(ITEMS)) = ADDR) then DO(i) <= '1'; end if; end loop; end if; end process; end architecture behavioral;
bsd-3-clause
1791afd9f8384a1b19dd677e828b8c1f
0.581081
4.606225
false
false
false
false
SylvainLesne/openPOWERLINK_V2
hardware/boards/terasic-de2-115/cn-single-gpio/quartus/toplevel.vhd
1
13,407
------------------------------------------------------------------------------- --! @file toplevel.vhd -- --! @brief Toplevel of Nios CN FPGA directIO part -- --! @details This is the toplevel of the Nios CN FPGA directIO design for the --! INK DE2-115 Evaluation Board. -- ------------------------------------------------------------------------------- -- -- (c) B&R, 2013 -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library libcommon; use libcommon.global.all; entity toplevel is port ( -- 50 MHZ CLK IN EXT_CLK : in std_logic; -- PHY Interfaces PHY_GXCLK : out std_logic_vector(1 downto 0); PHY_RXCLK : in std_logic_vector(1 downto 0); PHY_RXER : in std_logic_vector(1 downto 0); PHY_RXDV : in std_logic_vector(1 downto 0); PHY_RXD : in std_logic_vector(7 downto 0); PHY_TXCLK : in std_logic_vector(1 downto 0); PHY_TXER : out std_logic_vector(1 downto 0); PHY_TXEN : out std_logic_vector(1 downto 0); PHY_TXD : out std_logic_vector(7 downto 0); PHY_MDIO : inout std_logic_vector(1 downto 0); PHY_MDC : out std_logic_vector(1 downto 0); PHY_RESET_n : out std_logic_vector(1 downto 0); -- EPCS EPCS_DCLK : out std_logic; EPCS_SCE : out std_logic; EPCS_SDO : out std_logic; EPCS_DATA0 : in std_logic; -- 2 MB SRAM SRAM_CE_n : out std_logic; SRAM_OE_n : out std_logic; SRAM_WE_n : out std_logic; SRAM_ADDR : out std_logic_vector(20 downto 1); SRAM_BE_n : out std_logic_vector(1 downto 0); SRAM_DQ : inout std_logic_vector(15 downto 0); -- NODE_SWITCH NODE_SWITCH : in std_logic_vector(7 downto 0); -- KEY KEY : in std_logic_vector(3 downto 0); -- LED LEDG : out std_logic_vector(7 downto 0); LEDR : out std_logic_vector(15 downto 0); -- HEX LED HEX0 : out std_logic_vector(6 downto 0); HEX1 : out std_logic_vector(6 downto 0); HEX2 : out std_logic_vector(6 downto 0); HEX3 : out std_logic_vector(6 downto 0); HEX4 : out std_logic_vector(6 downto 0); HEX5 : out std_logic_vector(6 downto 0); HEX6 : out std_logic_vector(6 downto 0); HEX7 : out std_logic_vector(6 downto 0); -- BENCHMARK_OUT BENCHMARK : out std_logic_vector(7 downto 0); -- LCD LCD_ON : out std_logic; LCD_BLON : out std_logic; LCD_DQ : inout std_logic_vector(7 downto 0); LCD_E : out std_logic; LCD_RS : out std_logic; LCD_RW : out std_logic ); end toplevel; architecture rtl of toplevel is component cnSingleGpio is port ( clk25_clk : in std_logic := 'X'; clk50_clk : in std_logic := 'X'; reset_reset_n : in std_logic := 'X'; clk100_clk : in std_logic := 'X'; -- SRAM tri_state_0_tcm_address_out : out std_logic_vector(20 downto 0); tri_state_0_tcm_byteenable_n_out : out std_logic_vector(1 downto 0); tri_state_0_tcm_read_n_out : out std_logic; tri_state_0_tcm_write_n_out : out std_logic; tri_state_0_tcm_data_out : inout std_logic_vector(15 downto 0) := (others => 'X'); tri_state_0_tcm_chipselect_n_out : out std_logic; -- OPENMAC openmac_0_mii_txEnable : out std_logic_vector(1 downto 0); openmac_0_mii_txData : out std_logic_vector(7 downto 0); openmac_0_mii_txClk : in std_logic_vector(1 downto 0) := (others => 'X'); openmac_0_mii_rxError : in std_logic_vector(1 downto 0) := (others => 'X'); openmac_0_mii_rxDataValid : in std_logic_vector(1 downto 0) := (others => 'X'); openmac_0_mii_rxData : in std_logic_vector(7 downto 0) := (others => 'X'); openmac_0_mii_rxClk : in std_logic_vector(1 downto 0) := (others => 'X'); openmac_0_smi_nPhyRst : out std_logic_vector(1 downto 0); openmac_0_smi_clk : out std_logic_vector(1 downto 0); openmac_0_smi_dio : inout std_logic_vector(1 downto 0) := (others => 'X'); -- BENCHMARK pcp_0_benchmark_pio_export : out std_logic_vector(7 downto 0); -- EPCS epcs_flash_dclk : out std_logic; epcs_flash_sce : out std_logic; epcs_flash_sdo : out std_logic; epcs_flash_data0 : in std_logic := 'X'; -- LCD lcd_data : inout std_logic_vector(7 downto 0) := (others => 'X'); lcd_E : out std_logic; lcd_RS : out std_logic; lcd_RW : out std_logic; -- NODE SWITCH node_switch_pio_export : in std_logic_vector(7 downto 0) := (others => 'X'); -- STATUS ERROR LED status_led_pio_export : out std_logic_vector(1 downto 0); -- HEX hex_pio_export : out std_logic_vector(31 downto 0); -- LEDR ledr_pio_export : out std_logic_vector(15 downto 0); -- KEY key_pio_export : in std_logic_vector(3 downto 0) := (others => 'X') ); end component cnSingleGpio; -- PLL component component pll port ( inclk0 : in std_logic; c0 : out std_logic; c1 : out std_logic; c2 : out std_logic; c3 : out std_logic; locked : out std_logic ); end component; signal clk25 : std_logic; signal clk50 : std_logic; signal clk100 : std_logic; signal pllLocked : std_logic; signal sramAddr : std_logic_vector(SRAM_ADDR'high downto 0); signal plk_status_error : std_logic_vector(1 downto 0); type tSevenSegArray is array (natural range <>) of std_logic_vector(6 downto 0); constant cNumberOfHex : natural := 8; signal hex : std_logic_vector(cNumberOfHex*4-1 downto 0); signal sevenSegArray : tSevenSegArray(cNumberOfHex-1 downto 0); begin SRAM_ADDR <= sramAddr(SRAM_ADDR'range); PHY_GXCLK <= (others => '0'); PHY_TXER <= (others => '0'); LCD_ON <= '1'; LCD_BLON <= '1'; LEDG <= "000000" & plk_status_error; inst : component cnSingleGpio port map ( clk25_clk => clk25, clk50_clk => clk50, clk100_clk => clk100, reset_reset_n => pllLocked, openmac_0_mii_txEnable => PHY_TXEN, openmac_0_mii_txData => PHY_TXD, openmac_0_mii_txClk => PHY_TXCLK, openmac_0_mii_rxError => PHY_RXER, openmac_0_mii_rxDataValid => PHY_RXDV, openmac_0_mii_rxData => PHY_RXD, openmac_0_mii_rxClk => PHY_RXCLK, openmac_0_smi_nPhyRst => PHY_RESET_n, openmac_0_smi_clk => PHY_MDC, openmac_0_smi_dio => PHY_MDIO, tri_state_0_tcm_address_out => sramAddr, tri_state_0_tcm_read_n_out => SRAM_OE_n, tri_state_0_tcm_byteenable_n_out => SRAM_BE_n, tri_state_0_tcm_write_n_out => SRAM_WE_n, tri_state_0_tcm_data_out => SRAM_DQ, tri_state_0_tcm_chipselect_n_out => SRAM_CE_n, pcp_0_benchmark_pio_export => BENCHMARK, epcs_flash_dclk => EPCS_DCLK, epcs_flash_sce => EPCS_SCE, epcs_flash_sdo => EPCS_SDO, epcs_flash_data0 => EPCS_DATA0, node_switch_pio_export => NODE_SWITCH, status_led_pio_export => plk_status_error, lcd_data => LCD_DQ, lcd_E => LCD_E, lcd_RS => LCD_RS, lcd_RW => LCD_RW, hex_pio_export => hex, ledr_pio_export => LEDR, key_pio_export => KEY ); -- Pll Instance pllInst : pll port map ( inclk0 => EXT_CLK, c0 => clk50, c1 => clk100, c2 => clk25, c3 => open, locked => pllLocked ); -- bcd to 7 segment genBcdTo7Seg : for i in cNumberOfHex-1 downto 0 generate signal tmpHex : std_logic_vector(3 downto 0); signal tmpSev : std_logic_vector(6 downto 0); begin tmpHex <= hex((i+1)*4-1 downto i*4); sevenSegArray(i) <= tmpSev; bcdTo7Seg0 : entity libcommon.bcd2led port map ( iBcdVal => tmpHex, oLed => open, onLed => tmpSev ); end generate genBcdTo7Seg; -- assign outports to array HEX0 <= sevenSegArray(0); HEX1 <= sevenSegArray(1); HEX2 <= sevenSegArray(2); HEX3 <= sevenSegArray(3); HEX4 <= sevenSegArray(4); HEX5 <= sevenSegArray(5); HEX6 <= sevenSegArray(6); HEX7 <= sevenSegArray(7); end rtl;
gpl-2.0
07005be114ffb6ec5044540f4741b279
0.439397
4.408747
false
false
false
false
SylvainLesne/openPOWERLINK_V2
hardware/ipcore/common/hostinterface/src/dynamicBridgeRtl.vhd
3
16,530
------------------------------------------------------------------------------- --! @file dynamicBridgeRtl.vhd -- --! @brief Dynamic Bridge for translating static to dynamic memory spaces -- --! @details The Dynamic Bridge component translates a static memory mapping --! into a dynamic memory map that can be changed during runtime. --! This enhances the functionality of an ordinary memory mapped bridge logic. --! Additionally several memory spaces can be configured (compilation). ------------------------------------------------------------------------------- -- -- (c) B&R, 2014 -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; --! need reduce or operation use ieee.std_logic_misc.OR_REDUCE; --! Common library library libcommon; --! Use common library global package use libcommon.global.all; --! Work library library work; --! use host interface package for specific types use work.hostInterfacePkg.all; ------------------------------------------------------------------------------- --! @brief Dynamic bridge translates a fixed address space into a flexible one. ------------------------------------------------------------------------------- --! @details --! The dynamic bridge has an input port with a fixed (before runtime) memory --! mapping, which is translated to a flexible address space mapping. --! The flexible address space can be changed during runtime in order to --! redirect accesses from the input to other locations. --! The base addresses for the static port are set by generic gBaseAddressArray. --! The base addresses for the dynamic port are set through the BaseSet port ------------------------------------------------------------------------------- entity dynamicBridge is generic ( --! number of static address spaces gAddressSpaceCount : natural := 2; --! select wheather DPRAM or registers will be used as memory (false = 0, true /= 0) gUseMemBlock : integer := 0; --! base addresses in static address space (note: last-1 = high address) gBaseAddressArray : tArrayStd32 := (x"0000_1000" , x"0000_2000" , x"0000_3000") ); port ( -- Global --! component-wide clock signal iClk : in std_logic; --! component-wide reset signal iRst : in std_logic; -- Bridge --! address of static address space iBridgeAddress : in std_logic_vector; --! Request strobe iBridgeRequest : in std_logic; --! address of dynamic address space (translated input) oBridgeAddress : out std_logic_vector; --! Select signal of any address space selected oBridgeSelectAny : out std_logic; --! select signals of all address spaces oBridgeSelect : out std_logic_vector(gAddressSpaceCount-1 downto 0); --! Bridge output valid oBridgeValid : out std_logic; -- BaseSet Memory Mapped Write Bus --! BaseSet write strobe iBaseSetWrite : in std_logic; --! BaseSet read strobe iBaseSetRead : in std_logic; --! BaseSet byteenable iBaseSetByteenable : in std_logic_vector; --! BaseSet address bus iBaseSetAddress : in std_logic_vector(LogDualis(gAddressSpaceCount)-1 downto 0); --! BaseSet write data bus iBaseSetData : in std_logic_vector; --! BaseSet read data bus oBaseSetData : out std_logic_vector; --! BaseSet acknowledge oBaseSetAck : out std_logic ); end dynamicBridge; ------------------------------------------------------------------------------- --! @brief Register Transfer Level of Dynamic Bridge device ------------------------------------------------------------------------------- --! @details --! The dynamic bridge rtl applies generated address decoders --! to generate select signals for the static address spaces. --! The select signals are forwarded register file holding the base address --! offsets in the dynamic memory space. The input address is manipulated with --! arithmetic operators to gain the output address. The lut file holds the --! base addresses in the static memory space. ------------------------------------------------------------------------------- architecture rtl of dynamicBridge is --! Bridge cycle delay constant cBridgeCycleDelay : natural := 3; --! Bridge read path enable all bytes constant cByteenableAllOnes : std_logic_vector(iBaseSetByteenable'range) := (others => cActivated); --! convert address array into stream constant cBaseAddressArrayStd : std_logic_vector ((gAddressSpaceCount+1)*cArrayStd32ElementSize-1 downto 0) := CONV_STDLOGICVECTOR(gBaseAddressArray, gBaseAddressArray'length); --! Input address register signal inAddrReg : std_logic_vector(iBridgeAddress'range); --! Request rising edge signal bridgeRequest_rising : std_logic; --! Input address store strobe signal inAddrStore : std_logic; --! Request acknowledge terminal count strobe signal reqAckTcnt : std_logic; --! address decoder select signals one hot coded signal addrDecSelOneHot : std_logic_vector(gAddressSpaceCount-1 downto 0); --! address decoder select signals binary coded signal addrDecSelBinary : std_logic_vector(LogDualis(gAddressSpaceCount)-1 downto 0); --! selected static lut file base offset signal lutFileBase : std_logic_vector(inAddrReg'range); --! Base address in bridge master environment signal addrSpaceOffset : std_logic_vector(inAddrReg'range); --! Base address in bridge master environment (unregistered) signal addrSpaceOffset_unreg : std_logic_vector(inAddrReg'range); --! Dynamic address offset within selected static space signal dynamicOffset : std_logic_vector(iBaseSetData'range); --! Translated address signal translateAddress : std_logic_vector(maximum(iBaseSetData'high, oBridgeAddress'high) downto inAddrReg'low); begin -- assert assert (cBridgeCycleDelay > 0) report "Set cBridgeCycleDelay > 0" severity failure; -- export oBridgeSelect <= addrDecSelOneHot; oBridgeSelectAny <= OR_REDUCE(addrDecSelOneHot); oBridgeValid <= reqAckTcnt; oBridgeAddress <= translateAddress(oBridgeAddress'range); --! Store the input address with the request strobe storeAddr : process(iRst, iClk) begin if iRst = cActivated then inAddrReg <= (others => cInactivated); elsif rising_edge(iClk) then if inAddrStore = cActivated then inAddrReg <= iBridgeAddress; end if; end if; end process; --! Get rising edge of request signaling reqEdge : entity libcommon.edgedetector port map ( iArst => iRst, iClk => iClk, iEnable => cActivated, iData => iBridgeRequest, oRising => bridgeRequest_rising, oFalling => open, oAny => open ); inAddrStore <= bridgeRequest_rising; --! Generate the request acknowledge signal reqAck : entity libcommon.cnt generic map ( gCntWidth => logDualis(cBridgeCycleDelay+1), gTcntVal => cBridgeCycleDelay ) port map ( iArst => iRst, iClk => iClk, iEnable => iBridgeRequest, iSrst => cInactivated, oCnt => open, oTcnt => reqAckTcnt ); --! Generate Address Decoders genAddressDecoder : for i in 0 to gAddressSpaceCount-1 generate insAddressDecoder : entity libcommon.addrDecode generic map ( gAddrWidth => inAddrReg'length, gBaseAddr => to_integer(unsigned(gBaseAddressArray(i)(inAddrReg'range))), gHighAddr => to_integer(unsigned(gBaseAddressArray(i+1)(inAddrReg'range))-1) ) port map ( iEnable => iBridgeRequest, iAddress => inAddrReg, oSelect => addrDecSelOneHot(i) ); end generate; --! Convert one hot from address decoder to binary insBinaryEncoder : entity libcommon.binaryEncoder generic map ( gDataWidth => gAddressSpaceCount ) port map ( iOneHot => addrDecSelOneHot, oBinary => addrDecSelBinary ); --! select static base address in lut file insLutFile : entity libcommon.lutFile generic map ( gLutCount => gAddressSpaceCount, gLutWidth => cArrayStd32ElementSize, gLutInitValue => cBaseAddressArrayStd(cBaseAddressArrayStd'left downto cArrayStd32ElementSize) -- omit high address of last memory map ) port map ( iAddrRead => addrDecSelBinary, oData => lutFileBase ); -- calculate address offset within static space addrSpaceOffset_unreg <= std_logic_vector( unsigned(inAddrReg) - unsigned(lutFileBase) ); --! Registers to break combinational path of lut file output. regAddrSpace : process(iRst, iClk) begin if iRst = cActivated then addrSpaceOffset <= (others => cInactivated); elsif rising_edge(iClk) then addrSpaceOffset <= addrSpaceOffset_unreg; end if; end process; REGFILE : if gUseMemBlock = 0 generate signal dynamicOffset_unreg : std_logic_vector(dynamicOffset'range); begin --! select dynamic base address in register file insRegFile : entity libcommon.registerFile generic map ( gRegCount => gAddressSpaceCount ) port map ( iClk => iClk, iRst => iRst, iWriteA => iBaseSetWrite, iWriteB => cInactivated, -- write port B unused iByteenableA => iBaseSetByteenable, iByteenableB => cByteenableAllOnes, iAddrA => iBaseSetAddress, iAddrB => addrDecSelBinary, iWritedataA => iBaseSetData, oReaddataA => oBaseSetData, iWritedataB => iBaseSetData, -- write port B unused oReaddataB => dynamicOffset_unreg ); regDynOff : process(iRst, iClk) begin if iRst = cActivated then dynamicOffset <= (others => cInactivated); elsif rising_edge(iClk) then dynamicOffset <= dynamicOffset_unreg; end if; end process; BASESETACK : oBaseSetAck <= iBaseSetWrite or iBaseSetRead; end generate REGFILE; genDPRAM : if gUseMemBlock /= 0 generate -- Clip dpr word width to values of power 2 (e.g. 8, 16, 32) constant cDprWordWidth : natural := 2**logDualis(iBaseSetData'length); constant cDprAddrWidth : natural := logDualis(gAddressSpaceCount); constant cDprReadDel : natural := 1; type tDprPort is record write : std_logic; read : std_logic; address : std_logic_vector(cDprAddrWidth-1 downto 0); byteenable : std_logic_vector(cDprWordWidth/8-1 downto 0); writedata : std_logic_vector(cDprWordWidth-1 downto 0); readdata : std_logic_vector(cDprWordWidth-1 downto 0); end record; signal dprPortA : tDprPort; signal dprPortA_readAck : std_logic; signal dprPortB : tDprPort; begin --! This combinatoric process assigns base sets to the dpr. --! The default assignments avoid warnings in synthesize tools. dprAssign : process ( iBaseSetByteenable, iBaseSetData ) begin --default assignments dprPortA.byteenable <= (others => cInactivated); dprPortA.writedata <= (others => cInactivated); dprPortB.byteenable <= (others => cInactivated); dprPortB.writedata <= (others => cInactivated); dprPortA.byteenable(iBaseSetByteenable'range) <= iBaseSetByteenable; dprPortA.writedata(iBaseSetData'range) <= iBaseSetData; dprPortB.byteenable <= (others => cInactivated); dprPortB.writedata(iBaseSetData'range) <= iBaseSetData; end process; dprPortA.write <= iBaseSetWrite; dprPortA.read <= iBaseSetRead; dprPortA.address <= iBaseSetAddress; oBaseSetData <= dprPortA.readdata(oBaseSetData'range); dprPortB.write <= cInactivated; --unused dprPortB.read <= cActivated; --unused dprPortB.address <= addrDecSelBinary; dynamicOffset <= dprPortB.readdata(dynamicOffset'range); insDPRAM: entity work.dpRam generic map( gWordWidth => cDprWordWidth, gNumberOfWords => gAddressSpaceCount ) port map( iClk_A => iClk, iEnable_A => cActivated, iWriteEnable_A => dprPortA.write, iAddress_A => dprPortA.address, iByteEnable_A => dprPortA.byteenable, iWritedata_A => dprPortA.writedata, oReaddata_A => dprPortA.readdata, iClk_B => iClk, iEnable_B => cActivated, iWriteEnable_B => dprPortB.write, iAddress_B => dprPortB.address, iByteEnable_B => dprPortB.byteenable, iWritedata_B => dprPortB.writedata, oReaddata_B => dprPortB.readdata ); BASESETACK : oBaseSetAck <= dprPortA.write or dprPortA_readAck; --! Generate the read acknowledge signal rdAck : entity libcommon.cnt generic map ( gCntWidth => logDualis(cDprReadDel+1), gTcntVal => cDprReadDel ) port map ( iArst => iRst, iClk => iClk, iEnable => dprPortA.read, iSrst => cInactivated, oCnt => open, oTcnt => dprPortA_readAck ); end generate genDPRAM; -- calculate translated address offset in dynamic space translateAddress <= std_logic_vector( unsigned(dynamicOffset) + unsigned(addrSpaceOffset) ); end rtl;
gpl-2.0
a585e94a2a728f989bbcdc5b88fbf02b
0.589111
5.097132
false
false
false
false
SylvainLesne/openPOWERLINK_V2
hardware/ipcore/common/openmac/src/openMAC_DMAmaster.vhd
3
20,706
------------------------------------------------------------------------------- -- Entity : openMAC_DMAmaster ------------------------------------------------------------------------------- -- -- (c) B&R, 2014 -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.math_real.log2; use ieee.math_real.ceil; --! Common library library libcommon; --! Use common library global package use libcommon.global.all; entity openMAC_DMAmaster is generic( simulate : boolean := false; dma_highadr_g : integer := 31; gen_tx_fifo_g : boolean := true; gen_rx_fifo_g : boolean := true; m_burstcount_width_g : integer := 4; m_burstcount_const_g : boolean := true; m_tx_burst_size_g : integer := 16; m_rx_burst_size_g : integer := 16; tx_fifo_word_size_g : integer := 32; rx_fifo_word_size_g : integer := 32; fifo_data_width_g : integer := 16; gen_dma_observer_g : boolean := true ); port( dma_clk : in std_logic; dma_req_overflow : in std_logic; dma_req_rd : in std_logic; dma_req_wr : in std_logic; m_clk : in std_logic; m_readdatavalid : in std_logic; m_waitrequest : in std_logic; mac_rx_off : in std_logic; mac_tx_off : in std_logic; rst : in std_logic; dma_addr : in std_logic_vector(dma_highadr_g downto 1); dma_dout : in std_logic_vector(15 downto 0); dma_rd_len : in std_logic_vector(11 downto 0); m_readdata : in std_logic_vector(fifo_data_width_g-1 downto 0); dma_ack_rd : out std_logic; dma_ack_wr : out std_logic; dma_rd_err : out std_logic; dma_wr_err : out std_logic; m_read : out std_logic; m_write : out std_logic; dma_din : out std_logic_vector(15 downto 0); m_address : out std_logic_vector(dma_highadr_g downto 0); m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0); m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0); m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0); m_writedata : out std_logic_vector(fifo_data_width_g-1 downto 0) ); end openMAC_DMAmaster; architecture strct of openMAC_DMAmaster is ---- Component declarations ----- component dma_handler generic( dma_highadr_g : integer := 31; gen_dma_observer_g : boolean := true; gen_rx_fifo_g : boolean := true; gen_tx_fifo_g : boolean := true; rx_fifo_word_size_log2_g : natural := 5; tx_fifo_word_size_log2_g : natural := 5 ); port ( dma_addr : in std_logic_vector(dma_highadr_g downto 1); dma_clk : in std_logic; dma_rd_len : in std_logic_vector(11 downto 0); dma_req_overflow : in std_logic; dma_req_rd : in std_logic; dma_req_wr : in std_logic; mac_rx_off : in std_logic; mac_tx_off : in std_logic; rst : in std_logic; rx_wr_clk : in std_logic; rx_wr_empty : in std_logic; rx_wr_full : in std_logic; rx_wr_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0); tx_rd_clk : in std_logic; tx_rd_empty : in std_logic; tx_rd_full : in std_logic; tx_rd_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0); dma_ack_rd : out std_logic; dma_ack_wr : out std_logic; dma_addr_out : out std_logic_vector(dma_highadr_g downto 1); dma_new_addr_rd : out std_logic; dma_new_addr_wr : out std_logic; dma_new_len : out std_logic; dma_rd_err : out std_logic; dma_rd_len_out : out std_logic_vector(11 downto 0); dma_wr_err : out std_logic; rx_aclr : out std_logic; rx_wr_req : out std_logic; tx_rd_req : out std_logic ); end component; component master_handler generic( dma_highadr_g : integer := 31; fifo_data_width_g : integer := 16; gen_rx_fifo_g : boolean := true; gen_tx_fifo_g : boolean := true; m_burst_wr_const_g : boolean := true; m_burstcount_width_g : integer := 4; m_rx_burst_size_g : integer := 16; m_tx_burst_size_g : integer := 16; rx_fifo_word_size_log2_g : natural := 5; tx_fifo_word_size_log2_g : natural := 5 ); port ( dma_addr_in : in std_logic_vector(dma_highadr_g downto 1); dma_len_rd : in std_logic_vector(11 downto 0); dma_new_addr_rd : in std_logic; dma_new_addr_wr : in std_logic; dma_new_len_rd : in std_logic; m_clk : in std_logic; m_readdatavalid : in std_logic; m_waitrequest : in std_logic; mac_rx_off : in std_logic; mac_tx_off : in std_logic; rst : in std_logic; rx_rd_clk : in std_logic; rx_rd_empty : in std_logic; rx_rd_full : in std_logic; rx_rd_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0); tx_wr_clk : in std_logic; tx_wr_empty : in std_logic; tx_wr_full : in std_logic; tx_wr_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0); m_address : out std_logic_vector(dma_highadr_g downto 0); m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0); m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0); m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0); m_read : out std_logic; m_write : out std_logic; rx_rd_req : out std_logic; tx_aclr : out std_logic; tx_wr_req : out std_logic ); end component; ---- Architecture declarations ----- --constants constant tx_fifo_word_size_c : natural := natural(tx_fifo_word_size_g); constant tx_fifo_word_size_log2_c : natural := natural(ceil(log2(real(tx_fifo_word_size_c)))); constant rx_fifo_word_size_c : natural := natural(rx_fifo_word_size_g); constant rx_fifo_word_size_log2_c : natural := natural(ceil(log2(real(rx_fifo_word_size_c)))); ---- Signal declarations used on the diagram ---- signal dma_new_addr_rd : std_logic; signal dma_new_addr_wr : std_logic; signal dma_new_rd_len : std_logic; signal m_dma_new_addr_rd : std_logic; signal m_dma_new_addr_wr : std_logic; signal m_dma_new_rd_len : std_logic; signal m_mac_rx_off : std_logic; signal m_mac_tx_off : std_logic; signal rx_aclr : std_logic; signal rx_rd_clk : std_logic; signal rx_rd_empty : std_logic; signal rx_rd_full : std_logic; signal rx_rd_req : std_logic; signal rx_wr_clk : std_logic; signal rx_wr_empty : std_logic; signal rx_wr_full : std_logic; signal rx_wr_req : std_logic; signal rx_wr_req_s : std_logic; signal tx_aclr : std_logic; signal tx_rd_clk : std_logic; signal tx_rd_empty : std_logic; signal tx_rd_empty_s : std_logic; signal tx_rd_empty_s_l : std_logic; signal tx_rd_full : std_logic; signal tx_rd_req : std_logic; signal tx_rd_req_s : std_logic; signal tx_rd_sel_word : std_logic; signal tx_wr_clk : std_logic; signal tx_wr_empty : std_logic; signal tx_wr_full : std_logic; signal tx_wr_req : std_logic; signal dma_addr_trans : std_logic_vector (dma_highadr_g downto 1); signal dma_rd_len_trans : std_logic_vector (11 downto 0); signal rd_data : std_logic_vector (fifo_data_width_g-1 downto 0); signal rx_rd_usedw : std_logic_vector (rx_fifo_word_size_log2_c-1 downto 0); signal rx_wr_usedw : std_logic_vector (rx_fifo_word_size_log2_c-1 downto 0); signal tx_rd_usedw : std_logic_vector (tx_fifo_word_size_log2_c-1 downto 0); signal tx_wr_usedw : std_logic_vector (tx_fifo_word_size_log2_c-1 downto 0); signal wr_data : std_logic_vector (fifo_data_width_g-1 downto 0); signal wr_data_s : std_logic_vector (fifo_data_width_g/2-1 downto 0); begin ---- Component instantiations ---- THE_DMA_HANDLER : dma_handler generic map ( dma_highadr_g => dma_highadr_g, gen_dma_observer_g => gen_dma_observer_g, gen_rx_fifo_g => gen_rx_fifo_g, gen_tx_fifo_g => gen_tx_fifo_g, rx_fifo_word_size_log2_g => rx_fifo_word_size_log2_c, tx_fifo_word_size_log2_g => tx_fifo_word_size_log2_c ) port map( dma_ack_rd => dma_ack_rd, dma_ack_wr => dma_ack_wr, dma_addr => dma_addr( dma_highadr_g downto 1 ), dma_addr_out => dma_addr_trans( dma_highadr_g downto 1 ), dma_clk => dma_clk, dma_new_addr_rd => dma_new_addr_rd, dma_new_addr_wr => dma_new_addr_wr, dma_new_len => dma_new_rd_len, dma_rd_err => dma_rd_err, dma_rd_len => dma_rd_len, dma_rd_len_out => dma_rd_len_trans, dma_req_overflow => dma_req_overflow, dma_req_rd => dma_req_rd, dma_req_wr => dma_req_wr, dma_wr_err => dma_wr_err, mac_rx_off => mac_rx_off, mac_tx_off => mac_tx_off, rst => rst, rx_aclr => rx_aclr, rx_wr_clk => rx_wr_clk, rx_wr_empty => rx_wr_empty, rx_wr_full => rx_wr_full, rx_wr_req => rx_wr_req, rx_wr_usedw => rx_wr_usedw( rx_fifo_word_size_log2_c-1 downto 0 ), tx_rd_clk => tx_rd_clk, tx_rd_empty => tx_rd_empty, tx_rd_full => tx_rd_full, tx_rd_req => tx_rd_req, tx_rd_usedw => tx_rd_usedw( tx_fifo_word_size_log2_c-1 downto 0 ) ); THE_MASTER_HANDLER : master_handler generic map ( dma_highadr_g => dma_highadr_g, fifo_data_width_g => fifo_data_width_g, gen_rx_fifo_g => gen_rx_fifo_g, gen_tx_fifo_g => gen_tx_fifo_g, m_burst_wr_const_g => m_burstcount_const_g, m_burstcount_width_g => m_burstcount_width_g, m_rx_burst_size_g => m_rx_burst_size_g, m_tx_burst_size_g => m_tx_burst_size_g, rx_fifo_word_size_log2_g => rx_fifo_word_size_log2_c, tx_fifo_word_size_log2_g => tx_fifo_word_size_log2_c ) port map( dma_addr_in => dma_addr_trans( dma_highadr_g downto 1 ), dma_len_rd => dma_rd_len_trans, dma_new_addr_rd => m_dma_new_addr_rd, dma_new_addr_wr => m_dma_new_addr_wr, dma_new_len_rd => m_dma_new_rd_len, m_address => m_address( dma_highadr_g downto 0 ), m_burstcount => m_burstcount( m_burstcount_width_g-1 downto 0 ), m_burstcounter => m_burstcounter( m_burstcount_width_g-1 downto 0 ), m_byteenable => m_byteenable( fifo_data_width_g/8-1 downto 0 ), m_clk => m_clk, m_read => m_read, m_readdatavalid => m_readdatavalid, m_waitrequest => m_waitrequest, m_write => m_write, mac_rx_off => m_mac_rx_off, mac_tx_off => m_mac_tx_off, rst => rst, rx_rd_clk => rx_rd_clk, rx_rd_empty => rx_rd_empty, rx_rd_full => rx_rd_full, rx_rd_req => rx_rd_req, rx_rd_usedw => rx_rd_usedw( rx_fifo_word_size_log2_c-1 downto 0 ), tx_aclr => tx_aclr, tx_wr_clk => tx_wr_clk, tx_wr_empty => tx_wr_empty, tx_wr_full => tx_wr_full, tx_wr_req => tx_wr_req, tx_wr_usedw => tx_wr_usedw( tx_fifo_word_size_log2_c-1 downto 0 ) ); rx_rd_clk <= m_clk; tx_rd_clk <= dma_clk; rx_wr_clk <= dma_clk; tx_wr_clk <= m_clk; sync1 : entity libcommon.syncTog generic map ( gStages => 2, gInit => cInactivated ) port map ( iSrc_rst => rst, iSrc_clk => dma_clk, iSrc_data => mac_tx_off, iDst_rst => rst, iDst_clk => m_clk, oDst_data => m_mac_tx_off ); sync2 : entity libcommon.syncTog generic map ( gStages => 2, gInit => cInactivated ) port map ( iSrc_rst => rst, iSrc_clk => dma_clk, iSrc_data => mac_rx_off, iDst_rst => rst, iDst_clk => m_clk, oDst_data => m_mac_rx_off ); ---- Generate statements ---- gen16bitFifo : if fifo_data_width_g = 16 generate begin txFifoGen : if gen_tx_fifo_g generate begin TX_FIFO_16 : entity work.asyncFifo generic map ( gDataWidth => fifo_data_width_g, gWordSize => tx_fifo_word_size_c, gSyncStages => 2, gMemRes => "ON" ) port map( iAclr => tx_aclr, iWrClk => tx_wr_clk, iWrReq => tx_wr_req, iWrData => m_readdata, oWrEmpty => tx_wr_empty, oWrFull => tx_wr_full, oWrUsedw => tx_wr_usedw, iRdClk => tx_rd_clk, iRdReq => tx_rd_req, oRdData => rd_data, oRdEmpty => tx_rd_empty_s, oRdFull => tx_rd_full, oRdUsedw => tx_rd_usedw ); tx_rd_empty_proc : process(tx_aclr, tx_rd_clk) begin if tx_aclr = '1' then tx_rd_empty_s_l <= '0'; elsif rising_edge(tx_rd_clk) then if mac_tx_off = '1' then tx_rd_empty_s_l <= '0'; elsif tx_rd_req = '1' then if tx_rd_empty_s = '0' then tx_rd_empty_s_l <= '1'; else tx_rd_empty_s_l <= '0'; end if; end if; end if; end process; tx_rd_empty <= tx_rd_empty_s when tx_rd_empty_s_l = '0' else '0'; end generate txFifoGen; rxFifoGen : if gen_rx_fifo_g generate begin RX_FIFO_16 : entity work.asyncFifo generic map ( gDataWidth => fifo_data_width_g, gWordSize => rx_fifo_word_size_c, gSyncStages => 2, gMemRes => "ON" ) port map( iAclr => rx_aclr, iWrClk => rx_wr_clk, iWrReq => rx_wr_req, iWrData => wr_data, oWrEmpty => rx_wr_empty, oWrFull => rx_wr_full, oWrUsedw => rx_wr_usedw, iRdClk => rx_rd_clk, iRdReq => rx_rd_req, oRdData => m_writedata, oRdEmpty => rx_rd_empty, oRdFull => rx_rd_full, oRdUsedw => rx_rd_usedw ); end generate rxFifoGen; wr_data <= dma_dout; dma_din <= rd_data; end generate gen16bitFifo; genRxAddrSync : if gen_rx_fifo_g generate begin sync4 : entity libcommon.syncTog generic map ( gStages => 2, gInit => cInactivated ) port map ( iSrc_rst => rst, iSrc_clk => dma_clk, iSrc_data => dma_new_addr_wr, iDst_rst => rst, iDst_clk => m_clk, oDst_data => m_dma_new_addr_wr ); end generate genRxAddrSync; genTxAddrSync : if gen_tx_fifo_g generate begin sync5 : entity libcommon.syncTog generic map ( gStages => 2, gInit => cInactivated ) port map( iSrc_rst => rst, iSrc_clk => dma_clk, iSrc_data => dma_new_addr_rd, iDst_rst => rst, iDst_clk => m_clk, oDst_data => m_dma_new_addr_rd ); sync6 : entity libcommon.syncTog generic map ( gStages => 2, gInit => cInactivated ) port map( iSrc_rst => rst, iSrc_clk => dma_clk, iSrc_data => dma_new_rd_len, iDst_rst => rst, iDst_clk => m_clk, oDst_data => m_dma_new_rd_len ); end generate genTxAddrSync; gen32bitFifo : if fifo_data_width_g = 32 generate begin txFifoGen32 : if gen_tx_fifo_g generate begin TX_FIFO_32 : entity work.asyncFifo generic map ( gDataWidth => fifo_data_width_g, gWordSize => tx_fifo_word_size_c, gSyncStages => 2, gMemRes => "ON" ) port map( iAclr => tx_aclr, iWrClk => tx_wr_clk, iWrReq => tx_wr_req, iWrData => m_readdata, oWrEmpty => tx_wr_empty, oWrFull => tx_wr_full, oWrUsedw => tx_wr_usedw, iRdClk => tx_rd_clk, iRdReq => tx_rd_req_s, oRdData => rd_data, oRdEmpty => tx_rd_empty_s, oRdFull => tx_rd_full, oRdUsedw => tx_rd_usedw ); tx_rd_proc : process (tx_rd_clk, rst) begin if rst = '1' then tx_rd_sel_word <= '0'; tx_rd_empty_s_l <= '0'; elsif rising_edge(tx_rd_clk) then if mac_tx_off = '1' then tx_rd_sel_word <= '0'; tx_rd_empty_s_l <= '0'; elsif tx_rd_req = '1' then if tx_rd_sel_word = '0' then tx_rd_sel_word <= '1'; else tx_rd_sel_word <= '0'; --workaround... if tx_rd_empty_s = '0' then tx_rd_empty_s_l <= '1'; else tx_rd_empty_s_l <= '0'; end if; end if; end if; end if; end process; tx_rd_req_s <= tx_rd_req when tx_rd_sel_word = '0' else '0'; tx_rd_empty <= tx_rd_empty_s when tx_rd_empty_s_l = '0' else '0'; dma_din <= rd_data(15 downto 0) when tx_rd_sel_word = '1' else rd_data(31 downto 16); end generate txFifoGen32; rxFifoGen32 : if gen_rx_fifo_g generate begin RX_FIFO_32 : entity work.asyncFifo generic map ( gDataWidth => fifo_data_width_g, gWordSize => rx_fifo_word_size_c, gSyncStages => rx_fifo_word_size_log2_c, gMemRes => "ON" ) port map( iAclr => rx_aclr, iWrClk => rx_wr_clk, iWrReq => rx_wr_req_s, iWrData => wr_data, oWrEmpty => rx_wr_empty, oWrFull => rx_wr_full, oWrUsedw => rx_wr_usedw, iRdClk => rx_rd_clk, iRdReq => rx_rd_req, oRdData => m_writedata, oRdEmpty => rx_rd_empty, oRdFull => rx_rd_full, oRdUsedw => rx_rd_usedw ); rx_wr_proc : process (rx_wr_clk, rst) variable toggle : std_logic; begin if rst = '1' then wr_data_s <= (others => '0'); toggle := '0'; rx_wr_req_s <= '0'; elsif rising_edge(rx_wr_clk) then rx_wr_req_s <= '0'; if mac_rx_off = '1' then if toggle = '1' then rx_wr_req_s <= '1'; end if; toggle := '0'; elsif rx_wr_req = '1' then if toggle = '0' then --capture data wr_data_s <= dma_dout; toggle := '1'; else rx_wr_req_s <= '1'; toggle := '0'; end if; end if; end if; end process; wr_data <= dma_dout & wr_data_s; end generate rxFifoGen32; end generate gen32bitFifo; end strct;
gpl-2.0
ab2f335585d5884b434aa47f8d6b52dc
0.543369
3.246472
false
false
false
false
SylvainLesne/openPOWERLINK_V2
hardware/ipcore/common/hostinterface/src/statusControlRegRtl.vhd
3
23,761
------------------------------------------------------------------------------- --! @file statusControlReg.vhd -- --! @brief Host interface Status-/Control Registers -- --! @details The host interface status/control registers provide memory mapped --! control of the interrupt generator (irqGen) and bridge (magicBridge). -- ------------------------------------------------------------------------------- -- -- (c) B&R, 2014 -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; --! Common library library libcommon; --! Use common library global package use libcommon.global.all; --! Work library library work; --! use host interface package for specific types use work.hostInterfacePkg.all; entity statusControlReg is generic ( --! Magic gMagic : natural := 16#504C4B00#; -- Version --! Version major gVersionMajor : natural := 16#FF#; --! Version minor gVersionMinor : natural := 16#FF#; --! Version revision gVersionRevision : natural := 16#FF#; --! Version count pattern gVersionCount : natural := 0; -- BaseSets --! BaseSets by Host gHostBaseSet : natural := 2; --! BaseSets by Pcp gPcpBaseSet : natural := 10; --! Interrupt source number gIrqSourceCount : natural range 1 to 15 := 3 ); port ( -- Global --! component wide clock signal iClk : in std_logic; --! component wide reset signal iRst : in std_logic; -- slave Host interface --! host read iHostRead : in std_logic; --! host write iHostWrite : in std_logic; --! host byteenable iHostByteenable : in std_logic_vector(cDword/8-1 downto 0); --! host address iHostAddress : in std_logic_vector(10 downto 2); --! host readdata oHostReaddata : out std_logic_vector(cDword-1 downto 0); --! host writedata iHostWritedata : in std_logic_vector(cDword-1 downto 0); --! host waitrequest oHostWaitrequest : out std_logic; -- slave PCP interface --! pcp read iPcpRead : in std_logic; --! pcp write iPcpWrite : in std_logic; --! pcp byteenable iPcpByteenable : in std_logic_vector(cDword/8-1 downto 0); --! pcp address iPcpAddress : in std_logic_vector(10 downto 2); --! pcp readdata oPcpReaddata : out std_logic_vector(cDword-1 downto 0); --! pcp writedata iPcpWritedata : in std_logic_vector(cDword-1 downto 0); --! pcp waitrequest oPcpWaitrequest : out std_logic; -- BaseSet link --! BaseSet write strobe oBaseSetWrite : out std_logic; --! BaseSet read strobe oBaseSetRead : out std_logic; --! BaseSet byteenable oBaseSetByteenable : out std_logic_vector; --! BaseSet address bus oBaseSetAddress : out std_logic_vector(LogDualis(gHostBaseSet+gPcpBaseSet)+2-1 downto 2); --! BaseSet read data bus iBaseSetData : in std_logic_vector; --! BaseSet write data bus oBaseSetData : out std_logic_vector; --! BaseSet acknowledge iBaseSetAck : in std_logic; -- Interrupt control --! master enable oIrqMasterEnable : out std_logic; --! interrupt source enable vector ('right is sync) oIrqSourceEnable : out std_logic_vector(gIrqSourceCount downto 0); --! interrupt acknowledge (pulse, 'right is sync) oIrqAcknowledge : out std_logic_vector(gIrqSourceCount downto 0); --! interrup set (pulse, no sync!) oIrqSet : out std_logic_vector(gIrqSourceCount downto 1); --! interrupt source pending iIrqPending : in std_logic_vector(gIrqSourceCount downto 0); --! external sync source enable oExtSyncEnable : out std_logic; --! external sync source config oExtSyncConfig : out std_logic_vector(cExtSyncEdgeConfigWidth-1 downto 0); -- miscellaneous --! bridge activates oBridgeEnable : out std_logic ); end statusControlReg; architecture Rtl of statusControlReg is -- base for register content --! magic base constant cBaseMagic : natural := 16#0000#; --! version base constant cBaseVersion : natural := 16#0004#; --! boot base constant cBaseBootBase : natural := 16#0008#; --! init base constant cBaseInitBase : natural := 16#000C#; --! bridge enable base constant cBaseBridgeEnable : natural := 16#0200#; --! command base constant cBaseCommand : natural := 16#0204#; --! state base constant cBaseState : natural := 16#0206#; --! error base constant cBaseError : natural := 16#0208#; --! heart beat constant cBaseHeartBeat : natural := 16#020A#; --! irq enable base constant cBaseIrqEnable : natural := 16#0300#; --! irq pending base constant cBaseIrqPending : natural := 16#0302#; --! irq master enable base constant cBaseIrqMasterEnable : natural := 16#0304#; --! irq ack base (host only) constant cBaseIrqAck : natural := 16#0306#; --! irq set base (pcp only) constant cBaseIrqSet : natural := 16#0306#; --! sync config base constant cBaseSyncConfig : natural := 16#030C#; --! base for base set constant cBaseBaseSet : natural := 16#0400#; --! base reserved constant cBaseReserved : natural := 16#0500#; --! type base registers (stored content) type tRegisterInfo is record --magic --version bootBase : std_logic_vector(cDword-1 downto 0); initBase : std_logic_vector(cDword-1 downto 0); end record; --! type control register (stored content) type tRegisterControl is record bridgeEnable : std_logic; command : std_logic_vector(cWord-1 downto 0); state : std_logic_vector(cWord-1 downto 0); error : std_logic_vector(cWord-1 downto 0); heartBeat : std_logic_vector(cWord-1 downto 0); end record; --! type synchronization register (stored content) type tRegisterSynchronization is record irqSrcEnableHost : std_logic_vector(gIrqSourceCount downto 0); irqSrcEnablePcp : std_logic_vector(gIrqSourceCount downto 0); irqMasterEnable : std_logic; syncConfig : std_logic_vector(cExtSyncConfigWidth-1 downto 0); end record; --! info register signal regInfo, regInfo_next : tRegisterInfo; --! info register initialisation constant cRegInfoInit : tRegisterInfo := ( bootBase => (others => cInactivated), initBase => (others => cInactivated) ); --! control register signal regControl : tRegisterControl; --! control register next signal regControl_next : tRegisterControl; --! control register initialisation constant cRegControlInit : tRegisterControl := ( bridgeEnable => cInactivated, command => (others => cInactivated), state => (others => cInactivated), error => (others => cInactivated), heartBeat => (others => cInactivated) ); --! synchronization register signal regSynchron : tRegisterSynchronization; --! synchronization register next signal regSynchron_next : tRegisterSynchronization; --! synchronization register initialisation constant cRegSynchronInit : tRegisterSynchronization := ( irqSrcEnableHost => (others => cInactivated), irqSrcEnablePcp => (others => cInactivated), irqMasterEnable => cInactivated, syncConfig => (others => cInactivated) ); --! host base writedata signal hostBaseSetData : std_logic_vector(iBaseSetData'range); --! host base write signal hostBaseSetWrite : std_logic; --! host base read signal hostBaseSetRead : std_logic; --! pcp base writedata signal pcpBaseSetData : std_logic_vector(iBaseSetData'range); --! pcp base write signal pcpBaseSetWrite : std_logic; --! pcp base read signal pcpBaseSetRead : std_logic; begin --! register process creates storage of values regClk : process(iClk) begin if rising_edge(iClk) then if iRst = cActivated then regInfo <= cRegInfoInit; regControl <= cRegControlInit; regSynchron <= cRegSynchronInit; else regInfo <= regInfo_next; regControl <= regControl_next; regSynchron <= regSynchron_next; end if; end if; end process; oHostWaitrequest <= not iBaseSetAck when (hostBaseSetRead = cActivated or hostBaseSetWrite = cActivated) else not(iHostWrite or iHostRead); oPcpWaitrequest <= not iBaseSetAck when (pcpBaseSetRead = cActivated or pcpBaseSetWrite = cActivated) else not(iPcpWrite or iPcpRead); oIrqMasterEnable <= regSynchron.irqMasterEnable; oIrqSourceEnable <= regSynchron.irqSrcEnableHost and regSynchron.irqSrcEnablePcp; oExtSyncEnable <= regSynchron.syncConfig(0); oExtSyncConfig <= regSynchron.syncConfig(2 downto 1); oBridgeEnable <= regControl.bridgeEnable; -- pcp overrules host! oBaseSetData <= pcpBaseSetData when pcpBaseSetWrite = cActivated else pcpBaseSetData when pcpBaseSetRead = cActivated else hostBaseSetData; oBaseSetByteenable <= iPcpByteenable when pcpBaseSetWrite = cActivated else iPcpByteenable when pcpBaseSetRead = cActivated else iHostByteenable; oBaseSetAddress <= std_logic_vector(unsigned(iPcpAddress(oBaseSetAddress'range))+gHostBaseSet) when pcpBaseSetRead = cActivated or pcpBaseSetWrite = cActivated else iHostAddress(oBaseSetAddress'range); oBaseSetWrite <= pcpBaseSetWrite or hostBaseSetWrite; oBaseSetRead <= pcpBaseSetRead or hostBaseSetRead; --! register access regAcc : process ( iHostWrite, iHostRead, iHostByteenable, iHostAddress, iHostWritedata, iPcpWrite, iPcpRead, iPcpByteenable, iPcpAddress, iPcpWritedata, regInfo, regControl, regSynchron, iIrqPending, iBaseSetData ) variable vHostSelAddr : natural; variable vPcpSelAddr : natural; begin -- default -- registers regInfo_next <= regInfo; regControl_next <= regControl; regSynchron_next <= regSynchron; -- outputs oHostReaddata <= (others => cInactivated); oIrqAcknowledge <= (others => cInactivated); hostBaseSetData <= (others => cInactivated); hostBaseSetWrite <= cInactivated; hostBaseSetRead <= cInactivated; oIrqSet <= (others => cInactivated); oPcpReaddata <= (others => cInactivated); pcpBaseSetData <= (others => cInactivated); pcpBaseSetWrite <= cInactivated; pcpBaseSetRead <= cInactivated; -- HOST -- select content -- write to content -- and read from content vHostSelAddr := to_integer(unsigned(iHostAddress))*4; case vHostSelAddr is when cBaseMagic => oHostReaddata <= std_logic_vector(to_unsigned(gMagic, cDword)); --magic is RO when cBaseVersion => oHostReaddata <= std_logic_vector(to_unsigned(gVersionMajor, cByte)) & std_logic_vector(to_unsigned(gVersionMinor, cByte)) & std_logic_vector(to_unsigned(gVersionRevision, cByte)) & std_logic_vector(to_unsigned(gVersionCount, cByte)); --version is RO when cBaseBootBase => oHostReaddata <= regInfo.bootBase; --bootBase is RO when cBaseInitBase => oHostReaddata <= regInfo.initBase; --initBase is RO when cBaseBridgeEnable => oHostReaddata(0) <= regControl.bridgeEnable; --bridge enable is RO when cBaseState | cBaseCommand => oHostReaddata <= regControl.state & regControl.command; if iHostWrite = cActivated then --state is RO if iHostByteenable(1) = cActivated then regControl_next.command(cWord-1 downto cByte) <= iHostWritedata(cWord-1 downto cByte); end if; if iHostByteenable(0) = cActivated then regControl_next.command(cByte-1 downto 0) <= iHostWritedata(cByte-1 downto 0); end if; end if; when cBaseHeartBeat | cBaseError => oHostReaddata <= regControl.heartBeat & regControl.error; --heartbeat and error are RO when cBaseIrqPending | cBaseIrqEnable => oHostReaddata(cWord+gIrqSourceCount downto cWord) <= iIrqPending; oHostReaddata(gIrqSourceCount downto 0) <= regSynchron.irqSrcEnableHost; if iHostWrite = cActivated then for i in cWord-1 downto 0 loop if iHostByteenable(i/cByte) = cActivated and i <= gIrqSourceCount then regSynchron_next.irqSrcEnableHost(i) <= iHostWritedata(i); end if; end loop; end if; when cBaseIrqAck | cBaseIrqMasterEnable => -- irq ack is SC oHostReaddata(0) <= regSynchron.irqMasterEnable; if iHostWrite = cActivated then if iHostByteenable(0) = cActivated then regSynchron_next.irqMasterEnable <= iHostWritedata(0); end if; for i in cDword-1 downto cWord loop if iHostByteenable(i/cByte) = cActivated and (i-cWord) <= gIrqSourceCount then oIrqAcknowledge(i-cWord) <= iHostWritedata(i); end if; end loop; end if; when cBaseSyncConfig => oHostReaddata(cExtSyncConfigWidth-1 downto 0) <= regSynchron.syncConfig; if iHostWrite = cActivated then for i in cWord-1 downto 0 loop if iHostByteenable(i/cByte) = cActivated and i < cExtSyncConfigWidth then regSynchron_next.syncConfig(i) <= iHostWritedata(i); end if; end loop; end if; when cBaseBaseSet to cBaseReserved-1 => if vHostSelAddr < cBaseBaseSet+gHostBaseSet*cDword/cByte then oHostReaddata(iBaseSetData'range) <= iBaseSetData; if iHostWrite = cActivated then hostBaseSetData <= iHostWritedata(hostBaseSetData'range); hostBaseSetWrite <= cActivated; hostBaseSetRead <= cInactivated; elsif iHostRead = cActivated then hostBaseSetRead <= cActivated; hostBaseSetWrite <= cInactivated; else hostBaseSetWrite <= cInactivated; hostBaseSetRead <= cInactivated; end if; end if; when others => null; end case; -- PCP -- select content -- write to content -- and read from content vPcpSelAddr := to_integer(unsigned(iPcpAddress)) * 4; case vPcpSelAddr is when cBaseMagic => oPcpReaddata <= std_logic_vector(to_unsigned(gMagic, cDword)); --magic is RO when cBaseVersion => oPcpReaddata <= std_logic_vector(to_unsigned(gVersionMajor, cByte)) & std_logic_vector(to_unsigned(gVersionMinor, cByte)) & std_logic_vector(to_unsigned(gVersionRevision, cByte)) & std_logic_vector(to_unsigned(gVersionCount, cByte)); --version is RO when cBaseBootBase => oPcpReaddata <= regInfo.bootBase; if iPcpWrite = cActivated then for i in cDword-1 downto 0 loop if iPcpByteenable(i/cByte) = cActivated then regInfo_next.bootBase(i) <= iPcpWritedata(i); end if; end loop; end if; when cBaseInitBase => oPcpReaddata <= regInfo.initBase; if iPcpWrite = cActivated then for i in cDword-1 downto 0 loop if iPcpByteenable(i/cByte) = cActivated then regInfo_next.initBase(i) <= iPcpWritedata(i); end if; end loop; end if; when cBaseBridgeEnable => oPcpReaddata(0) <= regControl.bridgeEnable; if iPcpWrite = cActivated then regControl_next.bridgeEnable <= iPcpWritedata(0); end if; when cBaseState | cBaseCommand => oPcpReaddata <= regControl.state & regControl.command; if iPcpWrite = cActivated then for i in cDword-1 downto cWord loop if iPcpByteenable(i/cByte) = cActivated then regControl_next.state(i-cWord) <= iPcpWritedata(i); end if; end loop; for i in cWord-1 downto 0 loop if iPcpByteenable(i/cByte) = cActivated then regControl_next.command(i) <= iPcpWritedata(i); end if; end loop; end if; when cBaseHeartBeat | cBaseError => oPcpReaddata <= regControl.heartBeat & regControl.error; if iPcpWrite = cActivated then for i in cDword-1 downto cWord loop if iPcpByteenable(i/cByte) = cActivated then regControl_next.heartBeat(i-cWord) <= iPcpWritedata(i); end if; end loop; for i in cWord-1 downto 0 loop if iPcpByteenable(i/cByte) = cActivated then regControl_next.error(i) <= iPcpWritedata(i); end if; end loop; end if; when cBaseIrqPending | cBaseIrqEnable => oPcpReaddata(cWord+gIrqSourceCount downto cWord) <= iIrqPending; oPcpReaddata(gIrqSourceCount downto 0) <= regSynchron.irqSrcEnablePcp; if iPcpWrite = cActivated then for i in cWord-1 downto 0 loop if iPcpByteenable(i/cByte) = cActivated and i <= gIrqSourceCount then regSynchron_next.irqSrcEnablePcp(i) <= iPcpWritedata(i); end if; end loop; end if; when cBaseIrqSet | cBaseIrqMasterEnable => -- irq set is self-clearing oPcpReaddata(0) <= regSynchron.irqMasterEnable; if iPcpWrite = cActivated then for i in cDword-1 downto cWord+1 loop if iPcpByteenable(i/cByte) = cActivated and (i-cWord) <= gIrqSourceCount then oIrqSet(i-cWord) <= iPcpWritedata(i); end if; end loop; end if; when cBaseSyncConfig => oPcpReaddata(cExtSyncConfigWidth-1 downto 0) <= regSynchron.syncConfig; when cBaseBaseSet to cBaseReserved-1 => if vPcpSelAddr < cBaseBaseSet+gPcpBaseSet*cDword/cByte then oPcpReaddata(iBaseSetData'range) <= iBaseSetData; if iPcpWrite = cActivated then pcpBaseSetData <= iPcpWritedata(pcpBaseSetData'range); pcpBaseSetWrite <= cActivated; pcpBaseSetRead <= cInactivated; elsif iPcpRead = cActivated then pcpBaseSetRead <= cActivated; pcpBaseSetWrite <= cInactivated; else pcpBaseSetRead <= cInactivated; pcpBaseSetWrite <= cInactivated; end if; end if; when others => null; end case; end process; end Rtl;
gpl-2.0
7f167ced47f562038772228e7663a850
0.54783
5.478672
false
false
false
false
simonspa/pixel-dtb-firmware
dtb/I2C_ADN2816.vhd
2
7,823
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity I2C_ADN2816 is port (clk_i : in std_logic; sub_i2c_i: in std_logic; reset_n_i : in std_logic; sda_o : out std_logic; sda_dir_o : out std_logic; sclen_o: out std_logic); end I2C_ADN2816; architecture rtl of I2C_ADN2816 is type t_state is (waiting, send_START, send_A7, send_A6, send_A5, send_A4, send_A3, send_A2, send_A1, send_RW, read_A_ACK, send_SA7, send_SA6, send_SA5, send_SA4, send_SA3, send_SA2, send_SA1, send_SA0, read_SA_ACK, send_D7, send_D6, send_D5, send_D4, send_D3, send_D2, send_D1, send_D0, read_D_ACK, send_ACK, send_STOPCLK, send_PAUS1, send_PAUS2, send_PAUS3, send_PAUS4, send_PAUS5, send_PAUS6, send_PAUS7, send_STOP); signal s_state : t_state; signal s_count : std_logic; begin p_i2cmaster: process (clk_i, reset_n_i) begin -- process p_serin if (reset_n_i = '0') then -- asynchronous reset (active low) sda_dir_o <= '1'; sda_o <= '1'; sclen_o <= '0'; s_count <= '0'; s_state <= waiting; elsif rising_edge(clk_i) then -- rising clock edge case s_state is when send_START => sda_dir_o <= '1'; sda_o <= '0'; s_state <= send_A7 ; ------------------------------------------------------------------------- when send_A7 => sclen_o <= '1'; sda_o <= '1'; s_state <= send_A6; ------------------------------------------------------------------------- when send_A6 => sda_o <= s_count; --sda_o <= '1'; old PCB version s_state <= send_A5; ------------------------------------------------------------------------- when send_A5 => sda_o <= '0'; s_state <= send_A4; ------------------------------------------------------------------------- when send_A4 => sda_o <= '0'; s_state <= send_A3; ------------------------------------------------------------------------- when send_A3 => sda_o <= '0'; s_state <= send_A2; ------------------------------------------------------------------------- when send_A2 => sda_o <= '0'; s_state <= send_A1; ------------------------------------------------------------------------- when send_A1 => sda_o <= '0'; s_state <= send_RW; ----------------------------------------------------------------------- when send_RW => sda_o <= '0'; s_state <= read_A_ACK; ------------------------------------------------------------------------- when read_A_ACK => sda_o <= '0'; sda_dir_o <= '0'; s_state <= send_SA7; ------------------------------------------------------------------------- when send_SA7 => sda_dir_o <= '1'; sda_o <= '0'; s_state <= send_SA6; ------------------------------------------------------------------------- when send_SA6 => sda_o <= '0'; s_state <= send_SA5; ------------------------------------------------------------------------- when send_SA5 => sda_o <= '0'; s_state <= send_SA4; ------------------------------------------------------------------------- when send_SA4 => sda_o <= '0'; s_state <= send_SA3; ------------------------------------------------------------------------- when send_SA3 => sda_o <= '1'; s_state <= send_SA2; ------------------------------------------------------------------------- when send_SA2 => sda_o <= '0'; s_state <= send_SA1; ------------------------------------------------------------------------- when send_SA1 => sda_o <= '0'; s_state <= send_SA0; ----------------------------------------------------------------------- when send_SA0 => sda_o <= '0'; s_state <= read_SA_ACK; ------------------------------------------------------------------------- when read_SA_ACK => sda_o <= '0'; sda_dir_o <= '0'; s_state <= send_D7; ------------------------------------------------------------------------- when send_D7 => sda_dir_o <= '1'; sda_o <= '1'; s_state <= send_D6; ------------------------------------------------------------------------- when send_D6 => sda_o <= '1'; s_state <= send_D5; ------------------------------------------------------------------------- when send_D5 => sda_o <= '0'; s_state <= send_D4; ------------------------------------------------------------------------- when send_D4 => sda_o <= '1'; s_state <= send_D3; ------------------------------------------------------------------------- when send_D3 => sda_o <= '0'; s_state <= send_D2; ------------------------------------------------------------------------- when send_D2 => sda_o <= '1'; s_state <= send_D1; ------------------------------------------------------------------------- when send_D1 => sda_o <= '0'; s_state <= send_D0; ------------------------------------------------------------------------- when send_D0 => sda_o <= '1'; s_state <= read_D_ACK; ------------------------------------------------------------------------- when read_D_ACK => sda_o <= '0'; sda_dir_o <= '0'; s_state <= send_STOPCLK; ------------------------------------------------------------------------- when send_STOPCLK => sda_dir_o <= '1'; sda_o <= '0'; --sclen_o <= '0'; s_state <= send_STOP; ------------------------------------------------------------------------- when send_STOP => sda_o <= '1'; sclen_o <= '0'; s_state <= send_PAUS1; ------------------------------------------------------------------------- when send_PAUS1 => if (s_count ='0') then s_state <= send_PAUS2; else s_state <= waiting; end if; ------------------------------------------------------------------------- when send_PAUS2 => s_count <= '1'; s_state <= send_PAUS3; ------------------------------------------------------------------------- when send_PAUS3 => s_state <= send_PAUS4; ------------------------------------------------------------------------- when send_PAUS4 => s_state <= send_PAUS5; ------------------------------------------------------------------------- when send_PAUS5 => s_state <= send_PAUS6; ------------------------------------------------------------------------- when send_PAUS6 => s_state <= send_PAUS7; ------------------------------------------------------------------------- when send_PAUS7 => s_state <= send_START; ------------------------------------------------------ when others => if sub_i2c_i = '1' then -- VME Start I2C Cycle command detected. s_count <= '0'; s_state <= send_START; end if; end case; end if; end process p_i2cmaster; end rtl;
unlicense
41e1bc1d6ea96d1980748dd3dc6da2cf
0.26192
4.662098
false
false
false
false
simonspa/pixel-dtb-firmware
dtb/lpm_mux0.vhd
2
10,531
-- megafunction wizard: %LPM_MUX% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: LPM_MUX -- ============================================================ -- File Name: lpm_mux0.vhd -- Megafunction Name(s): -- LPM_MUX -- -- Simulation Library Files(s): -- lpm -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version -- ************************************************************ --Copyright (C) 1991-2012 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.lpm_components.all; ENTITY lpm_mux0 IS PORT ( clock : IN STD_LOGIC ; data0x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); data1x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); data2x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); data3x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); data4x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); data5x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); data6x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); data7x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0); result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) ); END lpm_mux0; ARCHITECTURE SYN OF lpm_mux0 IS -- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC_VECTOR (15 DOWNTO 0); SIGNAL sub_wire2 : STD_LOGIC_2D (7 DOWNTO 0, 15 DOWNTO 0); SIGNAL sub_wire3 : STD_LOGIC_VECTOR (15 DOWNTO 0); SIGNAL sub_wire4 : STD_LOGIC_VECTOR (15 DOWNTO 0); SIGNAL sub_wire5 : STD_LOGIC_VECTOR (15 DOWNTO 0); SIGNAL sub_wire6 : STD_LOGIC_VECTOR (15 DOWNTO 0); SIGNAL sub_wire7 : STD_LOGIC_VECTOR (15 DOWNTO 0); SIGNAL sub_wire8 : STD_LOGIC_VECTOR (15 DOWNTO 0); SIGNAL sub_wire9 : STD_LOGIC_VECTOR (15 DOWNTO 0); BEGIN sub_wire9 <= data0x(15 DOWNTO 0); sub_wire8 <= data1x(15 DOWNTO 0); sub_wire7 <= data2x(15 DOWNTO 0); sub_wire6 <= data3x(15 DOWNTO 0); sub_wire5 <= data4x(15 DOWNTO 0); sub_wire4 <= data5x(15 DOWNTO 0); sub_wire3 <= data6x(15 DOWNTO 0); result <= sub_wire0(15 DOWNTO 0); sub_wire1 <= data7x(15 DOWNTO 0); sub_wire2(7, 0) <= sub_wire1(0); sub_wire2(7, 1) <= sub_wire1(1); sub_wire2(7, 2) <= sub_wire1(2); sub_wire2(7, 3) <= sub_wire1(3); sub_wire2(7, 4) <= sub_wire1(4); sub_wire2(7, 5) <= sub_wire1(5); sub_wire2(7, 6) <= sub_wire1(6); sub_wire2(7, 7) <= sub_wire1(7); sub_wire2(7, 8) <= sub_wire1(8); sub_wire2(7, 9) <= sub_wire1(9); sub_wire2(7, 10) <= sub_wire1(10); sub_wire2(7, 11) <= sub_wire1(11); sub_wire2(7, 12) <= sub_wire1(12); sub_wire2(7, 13) <= sub_wire1(13); sub_wire2(7, 14) <= sub_wire1(14); sub_wire2(7, 15) <= sub_wire1(15); sub_wire2(6, 0) <= sub_wire3(0); sub_wire2(6, 1) <= sub_wire3(1); sub_wire2(6, 2) <= sub_wire3(2); sub_wire2(6, 3) <= sub_wire3(3); sub_wire2(6, 4) <= sub_wire3(4); sub_wire2(6, 5) <= sub_wire3(5); sub_wire2(6, 6) <= sub_wire3(6); sub_wire2(6, 7) <= sub_wire3(7); sub_wire2(6, 8) <= sub_wire3(8); sub_wire2(6, 9) <= sub_wire3(9); sub_wire2(6, 10) <= sub_wire3(10); sub_wire2(6, 11) <= sub_wire3(11); sub_wire2(6, 12) <= sub_wire3(12); sub_wire2(6, 13) <= sub_wire3(13); sub_wire2(6, 14) <= sub_wire3(14); sub_wire2(6, 15) <= sub_wire3(15); sub_wire2(5, 0) <= sub_wire4(0); sub_wire2(5, 1) <= sub_wire4(1); sub_wire2(5, 2) <= sub_wire4(2); sub_wire2(5, 3) <= sub_wire4(3); sub_wire2(5, 4) <= sub_wire4(4); sub_wire2(5, 5) <= sub_wire4(5); sub_wire2(5, 6) <= sub_wire4(6); sub_wire2(5, 7) <= sub_wire4(7); sub_wire2(5, 8) <= sub_wire4(8); sub_wire2(5, 9) <= sub_wire4(9); sub_wire2(5, 10) <= sub_wire4(10); sub_wire2(5, 11) <= sub_wire4(11); sub_wire2(5, 12) <= sub_wire4(12); sub_wire2(5, 13) <= sub_wire4(13); sub_wire2(5, 14) <= sub_wire4(14); sub_wire2(5, 15) <= sub_wire4(15); sub_wire2(4, 0) <= sub_wire5(0); sub_wire2(4, 1) <= sub_wire5(1); sub_wire2(4, 2) <= sub_wire5(2); sub_wire2(4, 3) <= sub_wire5(3); sub_wire2(4, 4) <= sub_wire5(4); sub_wire2(4, 5) <= sub_wire5(5); sub_wire2(4, 6) <= sub_wire5(6); sub_wire2(4, 7) <= sub_wire5(7); sub_wire2(4, 8) <= sub_wire5(8); sub_wire2(4, 9) <= sub_wire5(9); sub_wire2(4, 10) <= sub_wire5(10); sub_wire2(4, 11) <= sub_wire5(11); sub_wire2(4, 12) <= sub_wire5(12); sub_wire2(4, 13) <= sub_wire5(13); sub_wire2(4, 14) <= sub_wire5(14); sub_wire2(4, 15) <= sub_wire5(15); sub_wire2(3, 0) <= sub_wire6(0); sub_wire2(3, 1) <= sub_wire6(1); sub_wire2(3, 2) <= sub_wire6(2); sub_wire2(3, 3) <= sub_wire6(3); sub_wire2(3, 4) <= sub_wire6(4); sub_wire2(3, 5) <= sub_wire6(5); sub_wire2(3, 6) <= sub_wire6(6); sub_wire2(3, 7) <= sub_wire6(7); sub_wire2(3, 8) <= sub_wire6(8); sub_wire2(3, 9) <= sub_wire6(9); sub_wire2(3, 10) <= sub_wire6(10); sub_wire2(3, 11) <= sub_wire6(11); sub_wire2(3, 12) <= sub_wire6(12); sub_wire2(3, 13) <= sub_wire6(13); sub_wire2(3, 14) <= sub_wire6(14); sub_wire2(3, 15) <= sub_wire6(15); sub_wire2(2, 0) <= sub_wire7(0); sub_wire2(2, 1) <= sub_wire7(1); sub_wire2(2, 2) <= sub_wire7(2); sub_wire2(2, 3) <= sub_wire7(3); sub_wire2(2, 4) <= sub_wire7(4); sub_wire2(2, 5) <= sub_wire7(5); sub_wire2(2, 6) <= sub_wire7(6); sub_wire2(2, 7) <= sub_wire7(7); sub_wire2(2, 8) <= sub_wire7(8); sub_wire2(2, 9) <= sub_wire7(9); sub_wire2(2, 10) <= sub_wire7(10); sub_wire2(2, 11) <= sub_wire7(11); sub_wire2(2, 12) <= sub_wire7(12); sub_wire2(2, 13) <= sub_wire7(13); sub_wire2(2, 14) <= sub_wire7(14); sub_wire2(2, 15) <= sub_wire7(15); sub_wire2(1, 0) <= sub_wire8(0); sub_wire2(1, 1) <= sub_wire8(1); sub_wire2(1, 2) <= sub_wire8(2); sub_wire2(1, 3) <= sub_wire8(3); sub_wire2(1, 4) <= sub_wire8(4); sub_wire2(1, 5) <= sub_wire8(5); sub_wire2(1, 6) <= sub_wire8(6); sub_wire2(1, 7) <= sub_wire8(7); sub_wire2(1, 8) <= sub_wire8(8); sub_wire2(1, 9) <= sub_wire8(9); sub_wire2(1, 10) <= sub_wire8(10); sub_wire2(1, 11) <= sub_wire8(11); sub_wire2(1, 12) <= sub_wire8(12); sub_wire2(1, 13) <= sub_wire8(13); sub_wire2(1, 14) <= sub_wire8(14); sub_wire2(1, 15) <= sub_wire8(15); sub_wire2(0, 0) <= sub_wire9(0); sub_wire2(0, 1) <= sub_wire9(1); sub_wire2(0, 2) <= sub_wire9(2); sub_wire2(0, 3) <= sub_wire9(3); sub_wire2(0, 4) <= sub_wire9(4); sub_wire2(0, 5) <= sub_wire9(5); sub_wire2(0, 6) <= sub_wire9(6); sub_wire2(0, 7) <= sub_wire9(7); sub_wire2(0, 8) <= sub_wire9(8); sub_wire2(0, 9) <= sub_wire9(9); sub_wire2(0, 10) <= sub_wire9(10); sub_wire2(0, 11) <= sub_wire9(11); sub_wire2(0, 12) <= sub_wire9(12); sub_wire2(0, 13) <= sub_wire9(13); sub_wire2(0, 14) <= sub_wire9(14); sub_wire2(0, 15) <= sub_wire9(15); LPM_MUX_component : LPM_MUX GENERIC MAP ( lpm_pipeline => 1, lpm_size => 8, lpm_type => "LPM_MUX", lpm_width => 16, lpm_widths => 3 ) PORT MAP ( clock => clock, data => sub_wire2, sel => sel, result => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: new_diagram STRING "1" -- Retrieval info: LIBRARY: lpm lpm.lpm_components.all -- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1" -- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "8" -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" -- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "3" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" -- Retrieval info: USED_PORT: data0x 0 0 16 0 INPUT NODEFVAL "data0x[15..0]" -- Retrieval info: USED_PORT: data1x 0 0 16 0 INPUT NODEFVAL "data1x[15..0]" -- Retrieval info: USED_PORT: data2x 0 0 16 0 INPUT NODEFVAL "data2x[15..0]" -- Retrieval info: USED_PORT: data3x 0 0 16 0 INPUT NODEFVAL "data3x[15..0]" -- Retrieval info: USED_PORT: data4x 0 0 16 0 INPUT NODEFVAL "data4x[15..0]" -- Retrieval info: USED_PORT: data5x 0 0 16 0 INPUT NODEFVAL "data5x[15..0]" -- Retrieval info: USED_PORT: data6x 0 0 16 0 INPUT NODEFVAL "data6x[15..0]" -- Retrieval info: USED_PORT: data7x 0 0 16 0 INPUT NODEFVAL "data7x[15..0]" -- Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL "result[15..0]" -- Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL "sel[2..0]" -- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: @data 1 0 16 0 data0x 0 0 16 0 -- Retrieval info: CONNECT: @data 1 1 16 0 data1x 0 0 16 0 -- Retrieval info: CONNECT: @data 1 2 16 0 data2x 0 0 16 0 -- Retrieval info: CONNECT: @data 1 3 16 0 data3x 0 0 16 0 -- Retrieval info: CONNECT: @data 1 4 16 0 data4x 0 0 16 0 -- Retrieval info: CONNECT: @data 1 5 16 0 data5x 0 0 16 0 -- Retrieval info: CONNECT: @data 1 6 16 0 data6x 0 0 16 0 -- Retrieval info: CONNECT: @data 1 7 16 0 data7x 0 0 16 0 -- Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0 -- Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.bsf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0_inst.vhd FALSE -- Retrieval info: LIB_FILE: lpm
unlicense
a01cc79e4d9eb98f63e033dc25564198
0.592441
2.437167
false
false
false
false
simonspa/pixel-dtb-firmware
dtb/HeRhTr.vhd
2
4,092
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity HeRhTr is Port ( clk : in STD_LOGIC; reset:in STD_LOGIC; sd_in: in STD_LOGIC; sd_out:out STD_LOGIC; TbmHeader:out STD_LOGIC; RocHeader:out STD_LOGIC; TbmTrailer:out STD_LOGIC; TP:out STD_LOGIC; TPP:out STD_LOGIC; allowRocH:out STD_LOGIC); end HeRhTr; architecture Behaviorial of HeRhTr is --signal signal s_1: STD_LOGIC:='0'; signal s_2: STD_LOGIC:='0'; signal s_3: STD_LOGIC:='0'; signal s_4: STD_LOGIC:='0'; signal s_5: STD_LOGIC:='0'; signal s_6: STD_LOGIC:='0'; signal s_7: STD_LOGIC:='0'; signal s_8: STD_LOGIC:='0'; signal s_9: STD_LOGIC:='0'; signal s_10: STD_LOGIC:='0'; signal s_11: STD_LOGIC:='0'; signal s_12: STD_LOGIC:='0'; signal s_13: STD_LOGIC:='0'; signal s_d1: STD_LOGIC:='0'; signal s_d2: STD_LOGIC:='0'; signal s_d3: STD_LOGIC:='0'; signal s_d4: STD_LOGIC:='0'; signal s_d5: STD_LOGIC:='0'; signal s_d6: STD_LOGIC:='0'; signal s_d7: STD_LOGIC:='0'; signal s_d8: STD_LOGIC:='0'; signal s_d9: STD_LOGIC:='0'; signal s_d10: STD_LOGIC:='0'; signal s_d11: STD_LOGIC:='0'; signal s_d12: STD_LOGIC:='0'; signal s_d13: STD_LOGIC:='0'; signal s_d14: STD_LOGIC:='0'; signal s_d15: STD_LOGIC:='0'; signal s_d16: STD_LOGIC:='0'; signal s_HEADER: STD_LOGIC:='0'; signal s_ROC: STD_LOGIC:='0'; signal s_TRAILER: STD_LOGIC:='0'; signal s_DataWindow: STD_LOGIC:='0'; signal s_count: STD_LOGIC_VECTOR (3 downto 0):="0000"; signal s_TC: STD_LOGIC:='0'; begin ------------------------------------------------------------ p_pipe: process (clk) begin if (rising_edge(clk)) then s_1 <= sd_in; s_2 <= s_1; s_3 <= s_2; s_4 <= s_3; s_5 <= s_4; s_6 <= s_5; s_7 <= s_6; s_8 <= s_7; s_9 <= s_8; s_10 <= s_9; s_11 <= s_10; s_12 <= s_11; s_13 <= s_12; end if; end process p_pipe; sd_out <= s_13; ------------------------------------------------------------ s_HEADER <= ( (not s_11) and s_10 and s_9 and s_8 and s_7 and s_6 and s_5 and s_4 and s_3 and s_2 and (not s_1) and (not sd_in) ); s_ROC <= ( (not s_11) and s_10 and s_9 and s_8 and s_7 and s_6 and s_5 and s_4 and s_3 and (not s_2) and s_d15 and s_DataWindow); s_TRAILER <= ( (not s_11) and s_10 and s_9 and s_8 and s_7 and s_6 and s_5 and s_4 and s_3 and s_2 and s_1 and sd_in ); ------------------------------------------------------------ p_DataWindow: process (clk, reset) begin if (reset = '1') then s_DataWindow <= '0'; elsif (rising_edge(clk)) then if ( s_HEADER = '1') then s_DataWindow <= '1'; elsif ( s_TRAILER = '1') then s_DataWindow <= '0'; end if; end if; end process p_DataWindow; TP <= s_DataWindow; ------------------------------------------------------------ p_Mod12Cnt: process (clk) begin if (rising_edge(clk)) then if (s_DataWindow = '1') then --count if (s_count= "1011") then s_count <= "0000"; s_TC <='1'; else s_count <= s_count +1; s_TC <='0'; end if; else -- do not count s_count <= "0000"; s_TC <='0'; end if; end if; end process p_Mod12Cnt; TPP <= s_TC; ------------------------------------------------------------ p_delay: process (clk) begin if (rising_edge(clk)) then s_d1 <= s_TC; s_d2 <= s_d1; s_d3 <= s_d2; s_d4 <= s_d3; s_d5 <= s_d4; s_d6 <= s_d5; s_d7 <= s_d6; s_d8 <= s_d7; s_d9 <= s_d8; s_d10 <= s_d9; s_d11 <= s_d10; s_d12 <= s_d11; s_d13 <= s_d12; s_d14 <= s_d13; s_d15 <= s_d14; s_d16 <= s_d15; end if; end process p_delay; allowRocH <= s_d16; ------------------------------------------------------------ p_output_registers : process (clk) begin if (rising_edge(clk)) then TbmHeader <= s_HEADER; RocHeader <= s_ROC; TbmTrailer <= s_TRAILER; end if; end process p_output_registers; ------------------------------------------------------------ end;--Behavioral
unlicense
7ef2cbda871689044626eaf18d3d0677
0.495601
2.653696
false
false
false
false
amethystek/VHDL_SPACE_INVADER
alien.vhd
1
4,459
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity alien is port(MOVE_CLK: in std_logic; MISSILE_POS_H:in std_logic_vector(10 downto 0); MISSILE_POS_V:in std_logic_vector(10 downto 0); HCount: in std_logic_vector(10 downto 0); VCount: in std_logic_vector(10 downto 0); INIT_POS_H: in std_logic_vector(10 downto 0);--decide where an alien appear after be resetted ALIEN_HIT: out std_logic;--if alien was hit, send 1 to missile VGA_ALIEN_EN: out std_logic;--whether show on screen ALIEN_WON: out std_logic:='0');--if a alien touch the bottom, game over end alien; architecture behave of alien is signal MOV_DIR :std_logic;--0 to right,1 to left signal POS_H :std_logic_vector(10 downto 0):=INIT_POS_H;--such as "00000001010"; signal POS_V :std_logic_vector(10 downto 0):="00011001000"; signal ALIEN_EN :std_logic; signal ALIEN_CLK_COUNT:std_logic_vector(2 downto 0); constant ALIEN_HEIGHT :integer:= 32; constant ALIEN_WIDTH :integer:= 32; constant MISSILE_HEIGHT:integer:= 16; constant MISSILE_WIDTH :integer:= 4; begin HIT_OR_WIN:process(MOVE_CLK)--check if alien hit by missile begin if rising_edge(MOVE_CLK)then ALIEN_EN<='1'; ALIEN_WON<='0'; ALIEN_HIT<='0'; if((MISSILE_POS_H+MISSILE_WIDTH)>POS_H and MISSILE_POS_H<(POS_H+ALIEN_WIDTH) and (MISSILE_POS_V+MISSILE_HEIGHT)>POS_V and MISSILE_POS_V<(POS_V+ALIEN_HEIGHT))then--if missile hit the alien ALIEN_EN<='0'; ALIEN_HIT<='1'; elsif(POS_V>480)then ALIEN_EN<='0'; ALIEN_WON<='1'; end if; end if; end process HIT_OR_WIN; MOVEMENT_AND_RST:process(MOVE_CLK)--calculate the movement of alien begin if rising_edge(MOVE_CLK)then if(ALIEN_EN='0')then POS_H<=INIT_POS_H;--such as"00000001010";--=10; POS_V<="00011001000";--=200; elsif(ALIEN_EN='1')then if(ALIEN_CLK_COUNT/="111")then ALIEN_CLK_COUNT<=ALIEN_CLK_COUNT+1; else ALIEN_CLK_COUNT<="000"; if(MOV_DIR='0')then--move to right if(POS_H<800-96)then POS_H<=POS_H+16; else MOV_DIR<='1'; end if; else if(POS_H>32)then POS_H<=POS_H-16; else MOV_DIR<='0'; end if; end if; POS_V<=POS_V+1; end if; end if; end if; end process MOVEMENT_AND_RST; ALIEN_SHOW:process(HCount,VCount) begin vga_alien_en<='0'; if(ALIEN_EN='1')then if(VCount>POS_V+3 and VCount<POS_V+6)then if((HCount>POS_H+5 and Hcount<POS_H+8)or(HCount>POS_H+22 and Hcount<POS_H+25))then vga_alien_en<='1'; end if; elsif(VCount>POS_V+6 and VCount<POS_V+10)then if((HCount>POS_H+8 and Hcount<POS_H+11)or(HCount>POS_H+19 and Hcount<POS_H+22))then vga_alien_en<='1'; end if; elsif(VCount>POS_V+9 and VCount<POS_V+12)then if((HCount>POS_H+5 and Hcount<POS_H+25))then vga_alien_en<='1'; end if; elsif(VCount=POS_V+12)then if((HCount>POS_H+5 and Hcount<POS_H+8)or(HCount>POS_H+11 and Hcount<POS_H+19)or (HCount>POS_H+22 and Hcount<POS_H+25))then vga_alien_en<='1'; end if; elsif(VCount=POS_V+13)then if((HCount>POS_H+2 and Hcount<POS_H+8)or(HCount>POS_H+11 and Hcount<POS_H+19)or (HCount>POS_H+22 and Hcount<POS_H+28))then vga_alien_en<='1'; end if; elsif(VCount>POS_V+13 and VCount<POS_V+16)then if((HCount>POS_H+3 and Hcount<POS_H+8)or(HCount>POS_H+11 and Hcount<POS_H+19)or (HCount>POS_H+22 and Hcount<POS_H+28))then vga_alien_en<='1'; end if; elsif(VCount>POS_V+15 and VCount<POS_V+18)then if((HCount>POS_H+0 and Hcount<POS_H+30))then vga_alien_en<='1'; end if; elsif(VCount>POS_V+17 and VCount<POS_V+21)then if((HCount>POS_H+0 and Hcount<POS_H+2)or(HCount>POS_H+5 and Hcount<POS_H+25)or (HCount>POS_H+28 and Hcount<POS_H+30))then vga_alien_en<='1'; end if; elsif(VCount>POS_V+20 and VCount<POS_V+24)then if((HCount>POS_H+0 and Hcount<POS_H+2)or(HCount>POS_H+5 and Hcount<POS_H+8)or (HCount>POS_H+22 and Hcount<POS_H+25)or(HCount>POS_H+28 and Hcount<POS_H+30))then vga_alien_en<='1'; end if; elsif(VCount=POS_V+25)then if((HCount>POS_H+8 and Hcount<POS_H+13)or(HCount>POS_H+17 and Hcount<POS_H+22))then vga_alien_en<='1'; end if; elsif(VCount=POS_V+26)then if((HCount>POS_H+8 and Hcount<POS_H+14)or(HCount>POS_H+17 and Hcount<POS_H+22))then vga_alien_en<='1'; end if; end if; end if; end process ALIEN_SHOW; end behave;
bsd-2-clause
b41225f6d7a5bf2b05e0ca5cab34aaa4
0.65037
2.65733
false
false
false
false
notti/dis_lu
vhdl/top.vhd
1
2,676
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; entity top is port( clk : in std_logic; btn_north_i : in std_logic; -- LCD Interface lcd_db_io : inout std_logic_vector(7 downto 0); lcd_rs_o : out std_logic; lcd_en_o : out std_logic; lcd_rw_o : out std_logic; -- Rotary Knob (ROT) rot_center_i : in std_logic; rot_a_i : in std_logic; rot_b_i : in std_logic; -- Mechanical Switches switch_i : in std_logic_vector(3 downto 0) ); end entity top; architecture beh of top is signal rst : std_logic; signal rst_n_i : std_logic; signal address : std_logic_vector(7 downto 0); signal data : std_logic_vector(7 downto 0); signal lcd_db : std_logic_vector (7 downto 0); signal lcd_rs : std_logic; signal lcd_en : std_logic; signal lcd_rw : std_logic; signal lcd_wr : std_logic; signal lcd_out : std_logic_vector(7 downto 0); signal rightInt : std_logic; signal leftInt : std_logic; signal pushInt : std_logic; begin deb_rst: entity work.debounce port map( clk => clk, input => btn_north_i, output => rst, riseedge => open, falledge => open ); rst_n_i <= not rst; mem_inst: entity work.memory port map( address => address, data => data ); cpu_core: entity work.core port map( clk => clk, rst => rst_n_i, address => address, data => data, lcd_out => lcd_out, lcd_wr => lcd_wr, rightInt => rightInt, leftInt => leftInt, pushInt => pushInt, switch => switch_i ); inst_rotKey : entity work.rotKey port map( clk => clk, rotA => rot_a_i, rotB => rot_b_i, rotPush => rot_center_i, rotRightEvent => rightInt, rotLeftEvent => leftInt, rotPushEvent => pushInt); i_lcd_core : entity work.lcd_core port map ( clk_i => clk, reset_n_i => rst_n_i, lcd_cs_i => lcd_wr, lcd_data_i => lcd_out, lcd_data_o => lcd_db, lcd_rs_o => lcd_rs, lcd_en_o => lcd_en, lcd_rw_o => lcd_rw ); lcd_db_io <= lcd_db when (lcd_rw = '0') else (others => 'Z'); lcd_rs_o <= lcd_rs; lcd_en_o <= lcd_en; lcd_rw_o <= lcd_rw; end architecture beh;
mit
de876ce2a2186beec110770a0e5d98c4
0.485052
3.421995
false
false
false
false
simonspa/pixel-dtb-firmware
dtb/ram_dqINST_la.vhd
2
7,078
-- megafunction wizard: %RAM: 1-PORT% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altsyncram -- ============================================================ -- File Name: ram_dqINST_la.vhd -- Megafunction Name(s): -- altsyncram -- -- Simulation Library Files(s): -- altera_mf -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version -- ************************************************************ --Copyright (C) 1991-2012 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY ram_dqINST_la IS PORT ( address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); clock : IN STD_LOGIC := '1'; data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); wren : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END ram_dqINST_la; ARCHITECTURE SYN OF ram_dqinst_la IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); COMPONENT altsyncram GENERIC ( clock_enable_input_a : STRING; clock_enable_output_a : STRING; intended_device_family : STRING; lpm_hint : STRING; lpm_type : STRING; numwords_a : NATURAL; operation_mode : STRING; outdata_aclr_a : STRING; outdata_reg_a : STRING; power_up_uninitialized : STRING; read_during_write_mode_port_a : STRING; widthad_a : NATURAL; width_a : NATURAL; width_byteena_a : NATURAL ); PORT ( address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); clock0 : IN STD_LOGIC ; data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); wren_a : IN STD_LOGIC ; q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT; BEGIN q <= sub_wire0(7 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( clock_enable_input_a => "BYPASS", clock_enable_output_a => "BYPASS", intended_device_family => "Cyclone III", lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=N_la", lpm_type => "altsyncram", numwords_a => 256, operation_mode => "SINGLE_PORT", outdata_aclr_a => "NONE", outdata_reg_a => "UNREGISTERED", power_up_uninitialized => "FALSE", read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", widthad_a => 8, width_a => 8, width_byteena_a => 1 ) PORT MAP ( address_a => address, clock0 => clock, data_a => data, wren_a => wren, q_a => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" -- Retrieval info: PRIVATE: AclrByte NUMERIC "0" -- Retrieval info: PRIVATE: AclrData NUMERIC "0" -- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: Clken NUMERIC "0" -- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1" -- Retrieval info: PRIVATE: JTAG_ID STRING "N_la" -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -- Retrieval info: PRIVATE: MIFfilename STRING "" -- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256" -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" -- Retrieval info: PRIVATE: RegData NUMERIC "1" -- Retrieval info: PRIVATE: RegOutput NUMERIC "0" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" -- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" -- Retrieval info: PRIVATE: WidthAddr NUMERIC "8" -- Retrieval info: PRIVATE: WidthData NUMERIC "8" -- Retrieval info: PRIVATE: rden NUMERIC "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=N_la" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" -- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" -- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" -- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" -- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" -- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 -- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dqINST_la.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dqINST_la.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dqINST_la.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dqINST_la.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dqINST_la_inst.vhd FALSE -- Retrieval info: LIB_FILE: altera_mf
unlicense
ac0b3fa99e68e48392d2f11d459d2963
0.673495
3.473013
false
false
false
false
OrganicMonkeyMotion/fpga_experiments
small_board/LABS/digital_logic/vhdl/lab2/part3/ripple_adder.vhd
1
837
library ieee; USE ieee.std_logic_1164.all; ENTITY ripple_adder IS PORT (b_in : IN STD_LOGIC_VECTOR (3 DOWNTO 0); a_in : IN STD_LOGIC_VECTOR (3 DOWNTO 0); c_in : IN STD_LOGIC; c_out : OUT STD_LOGIC; s_out : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)) ; END ripple_adder; ARCHITECTURE Behavior OF ripple_adder IS SIGNAL c1, c2, c3: STD_LOGIC; COMPONENT adder PORT (b : IN STD_LOGIC; a : IN STD_LOGIC; ci : IN STD_LOGIC; co : OUT STD_LOGIC; s : OUT STD_LOGIC) ; END COMPONENT; BEGIN FA3: adder PORT MAP (b=> b_in(3), a=> a_in(3), ci=>c3, co=>c_out, s=>s_out(3)); FA2: adder PORT MAP (b=> b_in(2), a=> a_in(2), ci=>c2, co=>c3, s=>s_out(2)); FA1: adder PORT MAP (b=> b_in(1), a=> a_in(1), ci=>c1, co=>c2, s=>s_out(1)); FA0: adder PORT MAP (b=> b_in(0), a=> a_in(0), ci=>c_in, co=>c1, s=>s_out(0)); END Behavior;
unlicense
4d43619bfdb95ba153d082a8fd0c0bc3
0.597372
2.299451
false
false
false
false
OrganicMonkeyMotion/fpga_experiments
small_board/LABS/digital_logic/vhdl/lab2/part6/bin2bcd_6bit.vhd
1
1,739
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.all; entity bin2bcd_6bit is Port ( binIN : in STD_LOGIC_VECTOR (5 downto 0); ones : out STD_LOGIC_VECTOR (3 downto 0); tens : out STD_LOGIC_VECTOR (3 downto 0) ); end bin2bcd_6bit; architecture Behavioral of bin2bcd_6bit is begin bcd1: process(binIN) -- temporary variable variable temp : STD_LOGIC_VECTOR (5 downto 0); -- variable to store the output BCD number -- organized as follows -- tens = bcd(7 downto 4) -- units = bcd(3 downto 0) variable bcd : UNSIGNED (7 downto 0) := (others => '0'); -- by -- https://en.wikipedia.org/wiki/Double_dabble begin -- zero the bcd variable bcd := (others => '0'); -- read input into temp variable temp(5 downto 0) := binIN; -- cycle 12 times as we have 12 input bits -- this could be optimized, we dont need to check and add 3 for the -- first 3 iterations as the number can never be >4 for i in 0 to 5 loop if bcd(3 downto 0) > 4 then bcd(3 downto 0) := bcd(3 downto 0) + 3; end if; if bcd(7 downto 4) > 4 then bcd(7 downto 4) := bcd(7 downto 4) + 3; end if; -- thousands can't be >4 for a 12-bit input number -- so don't need to do anything to upper 4 bits of bcd -- shift bcd left by 1 bit, copy MSB of temp into LSB of bcd bcd := bcd(7 downto 0) & temp(5); -- shift temp left by 1 bit temp := temp(4 downto 0) & '0'; end loop; -- set outputs ones <= STD_LOGIC_VECTOR(bcd(3 downto 0)); tens <= STD_LOGIC_VECTOR(bcd(7 downto 4)); end process bcd1; end Behavioral;
unlicense
953b2e3154ad58f5b882b625635aae7f
0.583094
3.570842
false
false
false
false
systec-dk/openPOWERLINK_systec
Examples/ipcore/xilinx/openmac/src/async_fifo_ctrl.vhd
3
5,435
------------------------------------------------------------------------------- -- controller (top level file) of the async fifo -- -- Copyright (C) 2011 B&R -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- -- Note: A general implementation of a asynchronous fifo which is -- using a dual port ram. This file is the controler top level entity. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity async_fifo_ctrl is generic(ADDR_WIDTH : natural := 5); port( -- write part clkw: in std_logic; resetw: in std_logic; wr: in std_logic; w_empty: out std_logic; w_full: out std_logic; w_addr: out std_logic_vector (ADDR_WIDTH-1 downto 0); rd_used_w: out std_logic_vector(ADDR_WIDTH-1 downto 0); -- read part clkr: in std_logic; resetr: in std_logic; rd: in std_logic; r_empty: out std_logic; r_full: out std_logic; r_addr: out std_logic_vector (ADDR_WIDTH-1 downto 0); wd_used_w: out std_logic_vector(ADDR_WIDTH-1 downto 0) ); end async_fifo_ctrl ; architecture str_arch of async_fifo_ctrl is signal r_ptr_in: std_logic_vector(ADDR_WIDTH downto 0); signal r_ptr_out: std_logic_vector(ADDR_WIDTH downto 0); signal w_ptr_in: std_logic_vector(ADDR_WIDTH downto 0); signal w_ptr_out: std_logic_vector(ADDR_WIDTH downto 0); -- component declarations component fifo_read_ctrl generic(N: natural); port( clkr: in std_logic; rd: in std_logic; resetr: in std_logic; w_ptr_in: in std_logic_vector (N downto 0); r_full: out std_logic; r_empty: out std_logic; r_addr: out std_logic_vector (N-1 downto 0); r_ptr_out: out std_logic_vector (N downto 0); r_elements: out std_logic_vector(N-1 downto 0) ); end component; component fifo_write_ctrl generic(N: natural); port( clkw: in std_logic; r_ptr_in: in std_logic_vector (N downto 0); resetw: in std_logic; wr: in std_logic; w_full: out std_logic; w_empty: out std_logic; w_addr: out std_logic_vector (N-1 downto 0); w_ptr_out: out std_logic_vector (N downto 0); w_elements: out std_logic_vector(N-1 downto 0) ); end component; component synchronizer_g generic(N: natural); port( clk: in std_logic; in_async: in std_logic_vector (N-1 downto 0); reset: in std_logic; out_sync: out std_logic_vector (N-1 downto 0) ); end component; begin read_ctrl: fifo_read_ctrl generic map(N=>ADDR_WIDTH) port map (clkr=>clkr, resetr=>resetr, rd=>rd, w_ptr_in=>w_ptr_in, r_empty=>r_empty, r_full=>r_full, r_ptr_out=>r_ptr_out, r_addr=>r_addr, r_elements=>rd_used_w ); write_ctrl: fifo_write_ctrl generic map(N =>ADDR_WIDTH) port map(clkw=>clkw, resetw=>resetw, wr=>wr, r_ptr_in=>r_ptr_in, w_empty=>w_empty, w_full=>w_full, w_ptr_out=>w_ptr_out, w_addr=>w_addr, w_elements=>wd_used_w ); sync_w_ptr: synchronizer_g generic map(N=>ADDR_WIDTH+1) port map(clk=>clkr, reset=>resetr, in_async=>w_ptr_out, out_sync=>w_ptr_in ); sync_r_ptr: synchronizer_g generic map(N=>ADDR_WIDTH+1) port map(clk=>clkw, reset=>resetw, in_async=>r_ptr_out, out_sync =>r_ptr_in ); end str_arch;
gpl-2.0
395dd0362b7dd24fdd0be0fe5fa87f57
0.585465
3.779555
false
false
false
false
scottlbaker/PDP11-SOC
src/mytypes.vhd
1
10,363
--================================================================ -- mytypes.vhd :: PDP-11 global type definitions -- -- (c) Scott L. Baker, Sierra Circuit Design --================================================================ library IEEE; use IEEE.std_logic_1164.ALL; package MY_TYPES is --======================================= -- ALU operations --======================================= type ALU_OP_TYPE is ( OP_ADD, -- add OP_ADC, -- add carry OP_SBC, -- subtract carry OP_SUBA, -- subtract B-A OP_SUBB, -- subtract A-B OP_INCA1, -- increment A OP_INCA2, -- increment A by 2 OP_DECA1, -- decrement A OP_DECA2, -- decrement A by 2 OP_INV, -- 1's complement A OP_NEG, -- 2's complement A OP_AND, -- A AND B OP_BIC, -- not A AND B OP_CZC, -- A AND not B OP_SZC, -- not A AND B OP_OR, -- A OR B OP_XOR, -- A XOR B OP_ZERO, -- zero OP_ONES, -- all ones OP_TA, -- Transfer A OP_TB, -- Transfer B OP_SWP, -- Swap bytes of A OP_ASL, -- arithmetic shift left A OP_ASR, -- arithmetic shift right A OP_LSR, -- logical shift right A OP_ROL, -- rotate left A OP_ROR -- rotate right A ); --======================================= -- Opcode Formats --======================================= constant ONE_OPERAND : std_logic_vector(2 downto 0) := "000"; constant TWO_OPERAND : std_logic_vector(2 downto 0) := "001"; constant BRA_FORMAT : std_logic_vector(2 downto 0) := "010"; constant IMPLIED : std_logic_vector(2 downto 0) := "011"; constant FLOAT : std_logic_vector(2 downto 0) := "100"; --======================================= -- Macro Operations (Instructions) --======================================= type MACRO_OP_TYPE is ( MOP_ADC, -- add with carry MOP_ADD, -- add source to destination MOP_ASH, -- shift arithmetically MOP_ASHC, -- arithmetic shift combined MOP_ASL, -- arithmetic shift left MOP_ASR, -- arithmetic shift right MOP_BR, -- branch unconditional MOP_BNE, -- branch not equal MOP_BEQ, -- branch equal MOP_BGE, -- branch greater than of equal MOP_BLT, -- branch less than MOP_BGT, -- branch greater than MOP_BLE, -- branch less than or equal MOP_BPL, -- branch plus MOP_BMI, -- branch minus MOP_BHI, -- branch higher MOP_BLOS, -- branch lower or same MOP_BVC, -- branch overflow clear MOP_BVS, -- branch overflow set MOP_BCC, -- branch carry clear MOP_BCS, -- branch carry set MOP_BIC, -- bit clear MOP_BIS, -- bit set MOP_BIT, -- bit test MOP_BPT, -- breakpoint trap MOP_CCC, -- clear condition code MOP_CLN, -- clear N bit MOP_CLC, -- clear C bit MOP_CLV, -- clear V bit MOP_CLZ, -- clear Z bit MOP_CLR, -- clear dst MOP_CMP, -- compare source to destination MOP_COM, -- 1's complement dst MOP_CSM, -- call to supervisor mode MOP_DEC, -- decrement dst MOP_DIV, -- divide MOP_EMT, -- emulator trap MOP_FADD, -- floating-point add MOP_FDIV, -- floating-point divide MOP_FMUL, -- floating-point multiply MOP_FSUB, -- floating-point subtract MOP_HALT, -- halt MOP_INC, -- increment dst MOP_IOT, -- input/output trap MOP_JMP, -- jump MOP_JSR, -- jump to subroutine MOP_MARK, -- facilitates stack clean-up procedures MOP_MFPD, -- move from previous instruction space MOP_MFPI, -- move from previous instruction space MOP_MFPS, -- move byte from processor status word MOP_MFPT, -- move from processor type MOP_MOV, -- move source to destination MOP_MTPD, -- move to previous data space MOP_MTPI, -- move to previous instruction space MOP_MTPS, -- move byte to processor status word MOP_MUL, -- multiply MOP_NEG, -- 2's complement negate dst MOP_NOP, -- no operation MOP_RESET, -- reset UNIBUS MOP_ROL, -- rotate left MOP_ROR, -- rotate right MOP_RTI, -- return from interrupt MOP_RTS, -- return from subroutine MOP_RTT, -- return from interrupt MOP_SBC, -- subtract with carry MOP_SCC, -- set condition code MOP_SEN, -- set N bit MOP_SEC, -- set C bit MOP_SEV, -- set V bit MOP_SEZ, -- set Z bit MOP_SOB, -- subtract one and branch (if not = 0) MOP_SPL, -- set priority level MOP_SUB, -- subtract source from destination MOP_SWAB, -- swap bytes MOP_SXT, -- sign extend MOP_TRAP, -- trap MOP_TST, -- test dst MOP_TSTSET, -- test/set dst (MICRO/J-11 only) MOP_UII, -- unimplemened instruction MOP_WAIT, -- wait for interrupt MOP_WRTLCK, -- read/lock dst (MICRO/J-11 only) MOP_XOR -- exclusive OR ); --================================================================= -- Microcode States --================================================================= type UCODE_STATE_TYPE is ( FETCH_OPCODE, GOT_OPCODE, EXEC_OPCODE, DIV_1, DIV_2, DIV_3, DIV_4, DIV_5, DIV_6, HALT_1, IRQ_1, IRQ_2, JSR_1, JSR_2, JSR_3, MPY_1, MPY_2, MPY_3, DST_RI1, DST_PI1, DST_PI2, DST_PD1, DST_X1, DST_X2, SRC_RI1, SRC_PI1, SRC_PI2, SRC_PD1, SRC_X1, SRC_X2, RST_1, RTS_1, SBO_1, SBZ_1, SHIFT_1, SHIFT_1A, SHIFT_1B, SHIFT_2, SHIFT_3, STORE_D, UII_1 ); --================================================================= -- PC operations --================================================================= type PC_OP_TYPE is ( LOAD_FROM_SX, -- load from address adder LOAD_FROM_ALU, -- load from ALU LOAD_FROM_MEM, -- load from memory LOAD_FROM_DA, -- load from DA register HOLD -- hold ); --================================================================= -- Register operations --================================================================= type REG_OP_TYPE is ( LOAD_FROM_ALU, -- load from ALU LOAD_FROM_REG, -- load from register LOAD_FROM_MEM, -- load from memory HOLD -- hold ); --================================================================= -- Count Register operations --================================================================= type CNT_OP_TYPE is ( LOAD_COUNT, -- load from opcode field DEC, -- decrement HOLD -- hold ); --======================================= -- Address adder operations --======================================= type SX_OP_TYPE is ( OP_REL, -- Relative OP_INC2, -- Increment by 2 OP_DEC2 -- Decrement by 2 ); --================================================================= -- AMUX operand selector --================================================================= type ASEL_TYPE is ( SEL_SA, -- select SA SEL_DA, -- select DA SEL_S, -- select S SEL_D, -- select D SEL_DMUX, -- select DMUX SEL_SMUX, -- select SMUX SEL_PSW, -- select PSW SEL_SP, -- select SP SEL_PC -- select PC ); --================================================================= -- BMUX operand selector --================================================================= type BSEL_TYPE is ( SEL_SA, -- Select SA SEL_DMUX, -- Select DMUX SEL_SMUX, -- Select SMUX SEL_T, -- Select T SEL_D -- Select D ); --======================================= -- Shifter control --======================================= type SHIFT_CTL_TYPE is ( NOP, -- no shift LEFT, -- shift left RIGHT, -- shift right SWAP -- swap hi and lo bytes ); end MY_TYPES;
gpl-3.0
fef397e8f85cb13c86a29459312f8ba9
0.355882
5.015973
false
false
false
false
systec-dk/openPOWERLINK_systec
Examples/ipcore/common/lib/src/req_ack.vhd
3
3,089
------------------------------------------------------------------------------- -- -- (c) B&R, 2011 -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; USE ieee.math_real.log2; USE ieee.math_real.ceil; entity req_ack is generic( ack_delay_g : integer := 1; zero_delay_g : boolean := false ); port( clk : in std_logic; rst : in std_logic; enable : in std_logic; ack : out std_logic ); end req_ack; architecture rtl of req_ack is constant iMaxCnt : integer := ack_delay_g; constant iMaxCntLog2 : integer := integer(ceil(log2(real(iMaxCnt)))); signal cnt, cnt_next : std_logic_vector(iMaxCntLog2 downto 0); signal cnt_tc : std_logic; begin genDelay : if zero_delay_g = false generate theCnter : process(clk, rst) begin if rst = '1' then cnt <= (others => '0'); elsif clk = '1' and clk'event then cnt <= cnt_next; end if; end process; cnt_next <= cnt + 1 when enable = '1' and cnt_tc /= '1' else (others => '0'); cnt_tc <= '1' when cnt = iMaxCnt else '0'; ack <= cnt_tc; end generate; genNoDelay : if zero_delay_g = true generate ack <= enable; end generate; end rtl;
gpl-2.0
d9a4466df30f1b037e2ea9081bb151d8
0.618647
4.197011
false
false
false
false
OrganicMonkeyMotion/fpga_experiments
small_board/LABS/digital_logic/vhdl/lab2/part5/bcd_adder.vhd
1
850
library ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.ALL; ENTITY bcd_adder IS PORT (b_in : IN STD_LOGIC_VECTOR (3 DOWNTO 0); a_in : IN STD_LOGIC_VECTOR (3 DOWNTO 0); c_in : IN STD_LOGIC; c_out : OUT STD_LOGIC; s_out : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)) ; END bcd_adder; ARCHITECTURE Behavior OF bcd_adder IS signal t: STD_LOGIC_VECTOR (3 DOWNTO 0); signal z: STD_LOGIC_VECTOR (3 DOWNTO 0); signal a: STD_LOGIC_VECTOR (3 DOWNTO 0); signal b: STD_LOGIC_VECTOR (3 DOWNTO 0); signal c1: STD_LOGIC; BEGIN process (a_in, b_in) begin t <= STD_LOGIC_VECTOR(unsigned(a_in) + unsigned(b_in) + (c_in & "")); if (t > "1001") then z <= "1010"; c1 <= '1'; else z <= "0000"; c1 <= '0'; end if; s_out <= STD_LOGIC_VECTOR(unsigned(t) - unsigned(z)); c_out <= c1; end process; END Behavior;
unlicense
10c9f63b47b627e4275fe5b7425e7f5e
0.612941
2.607362
false
false
false
false
systec-dk/openPOWERLINK_systec
Examples/ipcore/common/pdi/src/pdi_apIrqGen.vhd
3
5,594
------------------------------------------------------------------------------- -- Process Data Interface (PDI) ap irq generator -- -- Copyright (C) 2011 B&R -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; entity apIrqGen is generic ( genOnePdiClkDomain_g : boolean := false ); port ( --CLOCK DOMAIN PCP clkA : in std_logic; rstA : in std_logic; irqA : in std_logic; --toggle from MAC enableA : in std_logic; --APIRQ_CONTROL / IRQ_En modeA : in std_logic; --APIRQ_CONTROL / IRQ_MODE setA : in std_logic; --APIRQ_CONTROL / IRQ_SET --CLOCK DOMAIN AP clkB : in std_logic; rstB : in std_logic; ackB : in std_logic; --APIRQ_CONTROL / IRQ_ACK irqB : out std_logic ); end entity apIrqGen; architecture rtl of apIrqGen is type fsm_t is (wait4event, setIrq, wait4ack); signal fsm : fsm_t; signal enable, mode, irq, toggle, set : std_logic; begin --everything is done in clkB domain! theFsm : process(clkB, rstB) begin if rstB = '1' then irqB <= '0'; fsm <= wait4event; elsif clkB = '1' and clkB'event then if enable = '1' then case fsm is when wait4event => if mode = '0' and set = '1' then fsm <= setIrq; elsif mode = '1' and irq = '1' then fsm <= setIrq; else fsm <= wait4event; end if; when setIrq => irqB <= '1'; fsm <= wait4ack; when wait4ack => if ackB = '1' then irqB <= '0'; fsm <= wait4event; else fsm <= wait4ack; end if; end case; else irqB <= '0'; fsm <= wait4event; end if; end if; end process; syncEnable : entity work.sync generic map ( doSync_g => not genOnePdiClkDomain_g ) port map ( din => enableA, dout => enable, clk => clkB, rst => rstB ); syncSet : entity work.slow2fastSync generic map ( doSync_g => not genOnePdiClkDomain_g ) port map ( dataSrc => setA, dataDst => set, clkSrc => clkA, rstSrc => rstA, clkDst => clkB, rstDst => rstB ); syncMode : entity work.sync generic map ( doSync_g => not genOnePdiClkDomain_g ) port map ( din => modeA, dout => mode, clk => clkB, rst => rstB ); syncToggle : entity work.sync generic map ( doSync_g => not genOnePdiClkDomain_g ) port map ( din => irqA, dout => toggle, clk => clkB, rst => rstB ); toggleEdgeDet : entity work.edgeDet port map ( din => toggle, rising => open, falling => open, any => irq, clk => clkB, rst => rstB ); end architecture rtl;
gpl-2.0
471ff643487cbaa45122ac65f8f88668
0.480515
4.919965
false
false
false
false
systec-dk/openPOWERLINK_systec
Examples/ipcore/common/pdi/src/pdi.vhd
3
69,180
------------------------------------------------------------------------------- -- Process Data Interface (PDI) for -- POWERLINK Communication Processor (PCP): Avalon -- Application Processor (AP): Avalon -- -- Copyright (C) 2010 B&R -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; USE ieee.math_real.log2; USE ieee.math_real.ceil; USE work.memMap.all; --used for memory mapping (alignment, ...) entity pdi is generic ( genOnePdiClkDomain_g : boolean := false; iPdiRev_g : integer := 0; --for HW/SW match verification (0..65535) pcpSysId : integer := 0; --for HW/SW match verification (0..65535) iRpdos_g : integer := 3; iTpdos_g : integer := 1; genABuf1_g : boolean := true; --if false iABuf1_g must be set to 0! genABuf2_g : boolean := true; --if false iABuf2_g must be set to 0! genLedGadget_g : boolean := false; genTimeSync_g : boolean := false; genEvent_g : boolean := false; --PDO buffer size *3 iTpdoBufSize_g : integer := 100; iRpdo0BufSize_g : integer := 116; --includes header iRpdo1BufSize_g : integer := 116; --includes header iRpdo2BufSize_g : integer := 116; --includes header --asynchronous buffer size iABuf1_g : integer := 512; --includes header iABuf2_g : integer := 512 --includes header ); port ( pcp_reset : in std_logic; pcp_clk : in std_logic; ap_reset : in std_logic; ap_clk : in std_logic; -- Avalon Slave Interface for PCP pcp_chipselect : in std_logic; pcp_read : in std_logic; pcp_write : in std_logic; pcp_byteenable : in std_logic_vector(3 DOWNTO 0); pcp_address : in std_logic_vector(12 DOWNTO 0); pcp_writedata : in std_logic_vector(31 DOWNTO 0); pcp_readdata : out std_logic_vector(31 DOWNTO 0); pcp_waitrequest : out std_logic; pcp_irq : in std_logic; --should be connected to the Time Cmp Toggle of openMAC! -- Avalon Slave Interface for AP ap_chipselect : in std_logic; ap_read : in std_logic; ap_write : in std_logic; ap_byteenable : in std_logic_vector(3 DOWNTO 0); ap_address : in std_logic_vector(12 DOWNTO 0); ap_writedata : in std_logic_vector(31 DOWNTO 0); ap_readdata : out std_logic_vector(31 DOWNTO 0); ap_waitrequest : out std_logic; ap_irq : out std_logic; --Sync Irq to the AP -- async interrupt ap_asyncIrq : out std_logic; --Async Irq to the Ap -- LED ledsOut : out std_logic_vector(15 downto 0) := (others => '0'); --LEDs: GPO7, ..., GPO0, O1, O0, PA1, PL1, PA0, PL0, E, S phyLink : in std_logic_vector(1 downto 0); --link: phy1, phy0 phyAct : in std_logic_vector(1 downto 0); --acti: phy1, phy0 --PDI change buffer triggers rpdo_change_tog : in std_logic_vector(2 downto 0); tpdo_change_tog : in std_logic ); end entity pdi; architecture rtl of pdi is ------------------------------------------------------------------------------------------------------------------------ --types ---for pcp and ap side type pdiSel_t is record pcp : std_logic; ap : std_logic; end record; type pdiTrig_t is record pcp : std_logic_vector(3 downto 0); ap : std_logic_vector(3 downto 0); end record; type pdi32Bit_t is record pcp : std_logic_vector(31 downto 0); ap : std_logic_vector(31 downto 0); end record; ------------------------------------------------------------------------------------------------------------------------ --constants ---memory mapping from outside (e.g. Avalon or SPI) ----max memory span of one space constant extMaxOneSpan : integer := 2 * 1024; --2kB constant extLog2MaxOneSpan : integer := integer(ceil(log2(real(extMaxOneSpan)))); ----control / status register constant extCntStReg_c : memoryMapping_t := (16#0000#, 16#98#); ----asynchronous buffers constant extABuf1Tx_c : memoryMapping_t := (16#0800#, iABuf1_g); --header is included in generic value! constant extABuf1Rx_c : memoryMapping_t := (16#1000#, iABuf1_g); --header is included in generic value! constant extABuf2Tx_c : memoryMapping_t := (16#1800#, iABuf2_g); --header is included in generic value! constant extABuf2Rx_c : memoryMapping_t := (16#2000#, iABuf2_g); --header is included in generic value! ----pdo buffer constant extTpdoBuf_c : memoryMapping_t := (16#2800#, iTpdoBufSize_g); --header is included in generic value! constant extRpdo0Buf_c : memoryMapping_t := (16#3000#, iRpdo0BufSize_g); --header is included in generic value! constant extRpdo1Buf_c : memoryMapping_t := (16#3800#, iRpdo1BufSize_g); --header is included in generic value! constant extRpdo2Buf_c : memoryMapping_t := (16#4000#, iRpdo2BufSize_g); --header is included in generic value! ---memory mapping inside the PDI's DPR ----control / status register constant intCntStReg_c : memoryMapping_t := (16#0000#, 22 * 4); --bytes mapped to dpr (dword alignment!!!), note: 4 times a double buffer! ----asynchronous buffers constant intABuf1Tx_c : memoryMapping_t := (intCntStReg_c.base + intCntStReg_c.span, align32(extABuf1Tx_c.span)); constant intABuf1Rx_c : memoryMapping_t := (intABuf1Tx_c.base + intABuf1Tx_c.span, align32(extABuf1Rx_c.span)); constant intABuf2Tx_c : memoryMapping_t := (intABuf1Rx_c.base + intABuf1Rx_c.span, align32(extABuf2Tx_c.span)); constant intABuf2Rx_c : memoryMapping_t := (intABuf2Tx_c.base + intABuf2Tx_c.span, align32(extABuf2Rx_c.span)); ----pdo buffers (triple buffers considered!) constant intTpdoBuf_c : memoryMapping_t := (intABuf2Rx_c.base + intABuf2Rx_c.span, align32(extTpdoBuf_c.span) *3); constant intRpdo0Buf_c : memoryMapping_t := (intTpdoBuf_c.base + intTpdoBuf_c.span, align32(extRpdo0Buf_c.span)*3); constant intRpdo1Buf_c : memoryMapping_t := (intRpdo0Buf_c.base + intRpdo0Buf_c.span, align32(extRpdo1Buf_c.span)*3); constant intRpdo2Buf_c : memoryMapping_t := (intRpdo1Buf_c.base + intRpdo1Buf_c.span, align32(extRpdo2Buf_c.span)*3); ----obtain dpr size of different configurations constant dprSize_c : integer := ( intCntStReg_c.span + intABuf1Tx_c.span + intABuf1Rx_c.span + intABuf2Tx_c.span + intABuf2Rx_c.span + intTpdoBuf_c.span + intRpdo0Buf_c.span + intRpdo1Buf_c.span + intRpdo2Buf_c.span ); constant dprAddrWidth_c : integer := integer(ceil(log2(real(dprSize_c)))); ---other constants constant magicNumber_c : integer := 16#50435000#; constant pdiRev_c : integer := iPdiRev_g; constant pcpSysId_c : integer := pcpSysId; ------------------------------------------------------------------------------------------------------------------------ --signals ---dpr type dprSig_t is record addr : std_logic_vector(dprAddrWidth_c-2-1 downto 0); --double word address! addrOff : std_logic_vector(dprAddrWidth_c-2 downto 0); --double word address! be : std_logic_vector(3 downto 0); din : std_logic_vector(31 downto 0); wr : std_logic; end record; type dprPdi_t is record pcp : dprSig_t; ap : dprSig_t; end record; ----signals to the DPR signal dpr : dprPdi_t; signal dprOut : pdi32Bit_t; ----control / status register signal dprCntStReg_s : dprPdi_t; ----asynchronous buffers signal dprABuf1Tx_s : dprPdi_t; signal dprABuf1Rx_s : dprPdi_t; signal dprABuf2Tx_s : dprPdi_t; signal dprABuf2Rx_s : dprPdi_t; ----pdo buffers (triple buffers considered!) signal dprTpdoBuf_s : dprPdi_t := (((others => '0'), (others => '0'), (others => '0'), (others => '0'), '0'), ((others => '0'), (others => '0'), (others => '0'), (others => '0'), '0')); signal dprRpdo0Buf_s : dprPdi_t := (((others => '0'), (others => '0'), (others => '0'), (others => '0'), '0'), ((others => '0'), (others => '0'), (others => '0'), (others => '0'), '0')); signal dprRpdo1Buf_s : dprPdi_t := (((others => '0'), (others => '0'), (others => '0'), (others => '0'), '0'), ((others => '0'), (others => '0'), (others => '0'), (others => '0'), '0')); signal dprRpdo2Buf_s : dprPdi_t := (((others => '0'), (others => '0'), (others => '0'), (others => '0'), '0'), ((others => '0'), (others => '0'), (others => '0'), (others => '0'), '0')); ---chip select ----control / status register signal selCntStReg_s : pdiSel_t; ----asynchronous buffers signal selABuf1Tx_s : pdiSel_t; signal selABuf1Rx_s : pdiSel_t; signal selABuf2Tx_s : pdiSel_t; signal selABuf2Rx_s : pdiSel_t; ----pdo buffers (triple buffers considered!) signal selTpdoBuf_s : pdiSel_t; signal selRpdo0Buf_s : pdiSel_t; signal selRpdo1Buf_s : pdiSel_t; signal selRpdo2Buf_s : pdiSel_t; ---data output ----control / status register signal outCntStReg_s : pdi32Bit_t; ----asynchronous buffers signal outABuf1Tx_s : pdi32Bit_t; signal outABuf1Rx_s : pdi32Bit_t; signal outABuf2Tx_s : pdi32Bit_t; signal outABuf2Rx_s : pdi32Bit_t; ----pdo buffers (triple buffers considered!) signal outTpdoBuf_s : pdi32Bit_t := ((others => '0'), (others => '0')); signal outRpdo0Buf_s : pdi32Bit_t := ((others => '0'), (others => '0')); signal outRpdo1Buf_s : pdi32Bit_t := ((others => '0'), (others => '0')); signal outRpdo2Buf_s : pdi32Bit_t := ((others => '0'), (others => '0')); ---virtual buffer control/state signal vBufTriggerPdo_s : pdiTrig_t; --tpdo, rpdo2, rpdo1, rpdo0 signal vBufSel_s : pdi32Bit_t := ((others => '1'), (others => '1')); --TXPDO_ACK | RXPDO2_ACK | RXPDO1_ACK | RXPDO0_ACK ---ap irq generation signal apIrqValue : std_logic_vector(31 downto 0); signal apIrqControlPcp, apIrqControlPcp2, apIrqControlApOut, apIrqControlApIn : std_logic_vector(15 downto 0); signal ap_irq_s : std_logic; ---address calulation result signal pcp_addrRes : std_logic_vector(dprAddrWidth_c-2 downto 0); signal ap_addrRes : std_logic_vector(dprAddrWidth_c-2 downto 0); ---EVENT stuff signal pcp_eventSet_s, --pulse to set event pcp_eventRead : std_logic_vector(15 downto 0); signal ap_eventAck_p, --pulse to ack event ap_eventAck : std_logic_vector(15 downto 0); signal asyncIrqCtrlOut_s, asyncIrqCtrlIn_s : std_logic_vector(15 downto 0); signal ap_asyncIrq_s : std_logic; --Async Irq to the Ap signal phyLink_s, phyLinkEvent : std_logic_vector(phyLink'range); --LED stuff signal pcp_ledForce_s, pcp_ledSet_s : std_logic_vector(15 downto 0) := (others => '0'); signal ap_ledForce_s, ap_ledSet_s : std_logic_vector(15 downto 0) := (others => '0'); signal hw_ledForce_s, hw_ledSet_s : std_logic_vector(15 downto 0) := (others => '0'); --TIME SYNCHRONIZATION signal pcp_timeSyncDBufSel : std_logic; signal ap_timeSyncDBufSel : std_logic; begin ASSERT NOT(iRpdos_g < 1 or iRpdos_g > 3) REPORT "Only 1, 2 or 3 Rpdos are supported!" severity failure; ASSERT NOT(iTpdos_g /= 1) REPORT "Only 1 Tpdo is supported!" severity failure; ------------------------------------------------------------------------------------------------------------------------ -- merge data to pcp/ap theMerger : block begin pcp_readdata <= outCntStReg_s.pcp when selCntStReg_s.pcp = '1' else outABuf1Tx_s.pcp when selABuf1Tx_s.pcp = '1' else outABuf1Rx_s.pcp when selABuf1Rx_s.pcp = '1' else outABuf2Tx_s.pcp when selABuf2Tx_s.pcp = '1' else outABuf2Rx_s.pcp when selABuf2Rx_s.pcp = '1' else outTpdoBuf_s.pcp when selTpdoBuf_s.pcp = '1' else outRpdo0Buf_s.pcp when selRpdo0Buf_s.pcp = '1' else outRpdo1Buf_s.pcp when selRpdo1Buf_s.pcp = '1' else outRpdo2Buf_s.pcp when selRpdo2Buf_s.pcp = '1' else (others => '0'); ap_readdata <= outCntStReg_s.ap when selCntStReg_s.ap = '1' else outABuf1Tx_s.ap when selABuf1Tx_s.ap = '1' else outABuf1Rx_s.ap when selABuf1Rx_s.ap = '1' else outABuf2Tx_s.ap when selABuf2Tx_s.ap = '1' else outABuf2Rx_s.ap when selABuf2Rx_s.ap = '1' else outTpdoBuf_s.ap when selTpdoBuf_s.ap = '1' else outRpdo0Buf_s.ap when selRpdo0Buf_s.ap = '1' else outRpdo1Buf_s.ap when selRpdo1Buf_s.ap = '1' else outRpdo2Buf_s.ap when selRpdo2Buf_s.ap = '1' else (others => '0'); end block; -- ------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------ -- dual ported RAM theDpr : entity work.pdi_dpr generic map ( NUM_WORDS => (dprSize_c/4), LOG2_NUM_WORDS => dprAddrWidth_c-2 ) port map ( address_a => pcp_addrRes(dprAddrWidth_c-2-1 downto 0), address_b => ap_addrRes(dprAddrWidth_c-2-1 downto 0), byteena_a => dpr.pcp.be, byteena_b => dpr.ap.be, clock_a => pcp_clk, clock_b => ap_clk, data_a => dpr.pcp.din, data_b => dpr.ap.din, wren_a => dpr.pcp.wr, wren_b => dpr.ap.wr, q_a => dprOut.pcp, q_b => dprOut.ap ); pcp_addrRes <= EXT('0' & pcp_address(extLog2MaxOneSpan-2-1 downto 0) + dpr.pcp.addrOff, pcp_addrRes'length); dpr.pcp <= dprCntStReg_s.pcp when selCntStReg_s.pcp = '1' else dprABuf1Tx_s.pcp when selABuf1Tx_s.pcp = '1' else dprABuf1Rx_s.pcp when selABuf1Rx_s.pcp = '1' else dprABuf2Tx_s.pcp when selABuf2Tx_s.pcp = '1' else dprABuf2Rx_s.pcp when selABuf2Rx_s.pcp = '1' else dprTpdoBuf_s.pcp when selTpdoBuf_s.pcp = '1' else dprRpdo0Buf_s.pcp when selRpdo0Buf_s.pcp = '1' and iRpdos_g >= 1 else dprRpdo1Buf_s.pcp when selRpdo1Buf_s.pcp = '1' and iRpdos_g >= 2 else dprRpdo2Buf_s.pcp when selRpdo2Buf_s.pcp = '1' and iRpdos_g >= 3 else ((others => '0'), (others => '0'), (others => '0'), (others => '0'), '0'); ap_addrRes <= EXT('0' & ap_address(extLog2MaxOneSpan-2-1 downto 0) + dpr.ap.addrOff, ap_addrRes'length); dpr.ap <= dprCntStReg_s.ap when selCntStReg_s.ap = '1' else dprABuf1Tx_s.ap when selABuf1Tx_s.ap = '1' else dprABuf1Rx_s.ap when selABuf1Rx_s.ap = '1' else dprABuf2Tx_s.ap when selABuf2Tx_s.ap = '1' else dprABuf2Rx_s.ap when selABuf2Rx_s.ap = '1' else dprTpdoBuf_s.ap when selTpdoBuf_s.ap = '1' else dprRpdo0Buf_s.ap when selRpdo0Buf_s.ap = '1' and iRpdos_g >= 1 else dprRpdo1Buf_s.ap when selRpdo1Buf_s.ap = '1' and iRpdos_g >= 2 else dprRpdo2Buf_s.ap when selRpdo2Buf_s.ap = '1' and iRpdos_g >= 3 else ((others => '0'), (others => '0'), (others => '0'), (others => '0'), '0'); ------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------ -- address decoder to generate select signals for different memory ranges theAddressDecoder : block begin --pcp side ---control / status register selCntStReg_s.pcp <= pcp_chipselect when (conv_integer(pcp_address)*4 >= extCntStReg_c.base and (conv_integer(pcp_address)*4 < extCntStReg_c.base + extCntStReg_c.span)) else '0'; ---asynchronous buffers selABuf1Tx_s.pcp <= pcp_chipselect when (conv_integer(pcp_address)*4 >= extABuf1Tx_c.base and (conv_integer(pcp_address)*4 < extABuf1Tx_c.base + extABuf1Tx_c.span)) else '0'; selABuf1Rx_s.pcp <= pcp_chipselect when (conv_integer(pcp_address)*4 >= extABuf1Rx_c.base and (conv_integer(pcp_address)*4 < extABuf1Rx_c.base + extABuf1Rx_c.span)) else '0'; selABuf2Tx_s.pcp <= pcp_chipselect when (conv_integer(pcp_address)*4 >= extABuf2Tx_c.base and (conv_integer(pcp_address)*4 < extABuf2Tx_c.base + extABuf2Tx_c.span)) else '0'; selABuf2Rx_s.pcp <= pcp_chipselect when (conv_integer(pcp_address)*4 >= extABuf2Rx_c.base and (conv_integer(pcp_address)*4 < extABuf2Rx_c.base + extABuf2Rx_c.span)) else '0'; ---pdo buffers (triple buffers considered!) selTpdoBuf_s.pcp <= pcp_chipselect when (conv_integer(pcp_address)*4 >= extTpdoBuf_c.base and (conv_integer(pcp_address)*4 < extTpdoBuf_c.base + extTpdoBuf_c.span)) else '0'; selRpdo0Buf_s.pcp <= pcp_chipselect when (conv_integer(pcp_address)*4 >= extRpdo0Buf_c.base and (conv_integer(pcp_address)*4 < extRpdo0Buf_c.base + extRpdo0Buf_c.span)) else '0'; selRpdo1Buf_s.pcp <= pcp_chipselect when (conv_integer(pcp_address)*4 >= extRpdo1Buf_c.base and (conv_integer(pcp_address)*4 < extRpdo1Buf_c.base + extRpdo1Buf_c.span)) else '0'; selRpdo2Buf_s.pcp <= pcp_chipselect when (conv_integer(pcp_address)*4 >= extRpdo2Buf_c.base and (conv_integer(pcp_address)*4 < extRpdo2Buf_c.base + extRpdo2Buf_c.span)) else '0'; --ap side ---control / status register selCntStReg_s.ap <= ap_chipselect when (conv_integer(ap_address)*4 >= extCntStReg_c.base and (conv_integer(ap_address)*4 < extCntStReg_c.base + extCntStReg_c.span)) else '0'; ---asynchronous buffers selABuf1Tx_s.ap <= ap_chipselect when (conv_integer(ap_address)*4 >= extABuf1Tx_c.base and (conv_integer(ap_address)*4 < extABuf1Tx_c.base + extABuf1Tx_c.span)) else '0'; selABuf1Rx_s.ap <= ap_chipselect when (conv_integer(ap_address)*4 >= extABuf1Rx_c.base and (conv_integer(ap_address)*4 < extABuf1Rx_c.base + extABuf1Rx_c.span)) else '0'; selABuf2Tx_s.ap <= ap_chipselect when (conv_integer(ap_address)*4 >= extABuf2Tx_c.base and (conv_integer(ap_address)*4 < extABuf2Tx_c.base + extABuf2Tx_c.span)) else '0'; selABuf2Rx_s.ap <= ap_chipselect when (conv_integer(ap_address)*4 >= extABuf2Rx_c.base and (conv_integer(ap_address)*4 < extABuf2Rx_c.base + extABuf2Rx_c.span)) else '0'; ---pdo buffers (triple buffers considered!) selTpdoBuf_s.ap <= ap_chipselect when (conv_integer(ap_address)*4 >= extTpdoBuf_c.base and (conv_integer(ap_address)*4 < extTpdoBuf_c.base + extTpdoBuf_c.span)) else '0'; selRpdo0Buf_s.ap <= ap_chipselect when (conv_integer(ap_address)*4 >= extRpdo0Buf_c.base and (conv_integer(ap_address)*4 < extRpdo0Buf_c.base + extRpdo0Buf_c.span)) else '0'; selRpdo1Buf_s.ap <= ap_chipselect when (conv_integer(ap_address)*4 >= extRpdo1Buf_c.base and (conv_integer(ap_address)*4 < extRpdo1Buf_c.base + extRpdo1Buf_c.span)) else '0'; selRpdo2Buf_s.ap <= ap_chipselect when (conv_integer(ap_address)*4 >= extRpdo2Buf_c.base and (conv_integer(ap_address)*4 < extRpdo2Buf_c.base + extRpdo2Buf_c.span)) else '0'; end block theAddressDecoder; ------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------ -- control / status register theCntrlStatReg4Pcp : entity work.pdiControlStatusReg generic map ( bIsPcp => true, iAddrWidth_g => extLog2MaxOneSpan-2, iBaseDpr_g => 16#8#/4, --base address of content to be mapped to dpr iSpanDpr_g => intCntStReg_c.span/4, --size of content to be mapped to dpr iBaseMap2_g => intCntStReg_c.base/4, --base address in dpr iDprAddrWidth_g => dprCntStReg_s.pcp.addr'length, iRpdos_g => iRpdos_g, genLedGadget_g => genLedGadget_g, genTimeSync_g => genTimeSync_g, genEvent_g => genEvent_g, --register content ---constant values magicNumber => conv_std_logic_vector(magicNumber_c, 32), pdiRev => conv_std_logic_vector(pdiRev_c, 16), pcpSysId => conv_std_logic_vector(pcpSysId_c, 16), tPdoBuffer => conv_std_logic_vector(extTpdoBuf_c.base, 16) & conv_std_logic_vector(extTpdoBuf_c.span, 16), rPdo0Buffer => conv_std_logic_vector(extRpdo0Buf_c.base, 16) & conv_std_logic_vector(extRpdo0Buf_c.span, 16), rPdo1Buffer => conv_std_logic_vector(extRpdo1Buf_c.base, 16) & conv_std_logic_vector(extRpdo1Buf_c.span, 16), rPdo2Buffer => conv_std_logic_vector(extRpdo2Buf_c.base, 16) & conv_std_logic_vector(extRpdo2Buf_c.span, 16), asyncBuffer1Tx => conv_std_logic_vector(extABuf1Tx_c.base, 16) & conv_std_logic_vector(extABuf1Tx_c.span, 16), asyncBuffer1Rx => conv_std_logic_vector(extABuf1Rx_c.base, 16) & conv_std_logic_vector(extABuf1Rx_c.span, 16), asyncBuffer2Tx => conv_std_logic_vector(extABuf2Tx_c.base, 16) & conv_std_logic_vector(extABuf2Tx_c.span, 16), asyncBuffer2Rx => conv_std_logic_vector(extABuf2Rx_c.base, 16) & conv_std_logic_vector(extABuf2Rx_c.span, 16) ) port map ( --memory mapped interface clk => pcp_clk, rst => pcp_reset, sel => selCntStReg_s.pcp, wr => pcp_write, rd => pcp_read, addr => pcp_address(extLog2MaxOneSpan-1-2 downto 0), be => pcp_byteenable, din => pcp_writedata, dout => outCntStReg_s.pcp, --register content ---virtual buffer control signals pdoVirtualBufferSel => vBufSel_s.pcp, tPdoTrigger => vBufTriggerPdo_s.pcp(3), rPdoTrigger => vBufTriggerPdo_s.pcp(2 downto 0), ---event registers eventAckIn => pcp_eventRead, eventAckOut => pcp_eventSet_s, ---async irq (by event) asyncIrqCtrlIn => (others => '0'), --not for pcp asyncIrqCtrlOut => open, --not for pcp ---led stuff ledCnfgIn => pcp_ledForce_s, ledCnfgOut => pcp_ledForce_s, ledCtrlIn => pcp_ledSet_s, ledCtrlOut => pcp_ledSet_s, ---time synchronization doubleBufSel_out => open, --PCP is the sink doubleBufSel_in => pcp_timeSyncDBufSel, timeSyncIrq => '0', --pcp is not interested --dpr interface (from PCP/AP to DPR) dprAddrOff => dprCntStReg_s.pcp.addrOff, dprDin => dprCntStReg_s.pcp.din, dprDout => dprOut.pcp, dprBe => dprCntStReg_s.pcp.be, dprWr => dprCntStReg_s.pcp.wr, --ap irq generation apIrqControlOut => apIrqControlPcp, --SW is blind, thus, use the transferred enable signal from AP! apIrqControlIn => apIrqControlPcp2, --hw acc triggering rpdo_change_tog => rpdo_change_tog, tpdo_change_tog => tpdo_change_tog ); --only read 15 bits of the written, the msbit is read from transferred AP bit apIrqControlPcp2(14 downto 0) <= apIrqControlPcp(14 downto 0); --transfer the AP's enable signal to PCP, since SW is blind... :) syncApEnable2Pcp : entity work.sync generic map ( doSync_g => not genOnePdiClkDomain_g ) port map ( din => apIrqControlApOut(15), dout => apIrqControlPcp2(15), clk => pcp_clk, rst => pcp_reset ); --sync double buffer select for time sync to AP if the feature is enabled -- note: signal toggles on PCP side when NETTIME [seconds] is written syncDBuf_TimeSync : entity work.sync generic map ( doSync_g => not genOnePdiClkDomain_g ) port map ( dout => pcp_timeSyncDBufSel, din => ap_timeSyncDBufSel, clk => pcp_clk, rst => pcp_reset ); theCntrlStatReg4Ap : entity work.pdiControlStatusReg generic map ( bIsPcp => false, iAddrWidth_g => extLog2MaxOneSpan-2, iBaseDpr_g => 16#8#/4, --base address of content to be mapped to dpr iSpanDpr_g => intCntStReg_c.span/4, --size of content to be mapped to dpr iBaseMap2_g => intCntStReg_c.base/4, --base address in dpr iDprAddrWidth_g => dprCntStReg_s.ap.addr'length, iRpdos_g => iRpdos_g, genLedGadget_g => genLedGadget_g, genTimeSync_g => genTimeSync_g, genEvent_g => genEvent_g, --register content ---constant values magicNumber => conv_std_logic_vector(magicNumber_c, 32), pdiRev => conv_std_logic_vector(pdiRev_c, 16), pcpSysId => conv_std_logic_vector(pcpSysId_c, 16), tPdoBuffer => conv_std_logic_vector(extTpdoBuf_c.base, 16) & conv_std_logic_vector(extTpdoBuf_c.span, 16), rPdo0Buffer => conv_std_logic_vector(extRpdo0Buf_c.base, 16) & conv_std_logic_vector(extRpdo0Buf_c.span, 16), rPdo1Buffer => conv_std_logic_vector(extRpdo1Buf_c.base, 16) & conv_std_logic_vector(extRpdo1Buf_c.span, 16), rPdo2Buffer => conv_std_logic_vector(extRpdo2Buf_c.base, 16) & conv_std_logic_vector(extRpdo2Buf_c.span, 16), asyncBuffer1Tx => conv_std_logic_vector(extABuf1Tx_c.base, 16) & conv_std_logic_vector(extABuf1Tx_c.span, 16), asyncBuffer1Rx => conv_std_logic_vector(extABuf1Rx_c.base, 16) & conv_std_logic_vector(extABuf1Rx_c.span, 16), asyncBuffer2Tx => conv_std_logic_vector(extABuf2Tx_c.base, 16) & conv_std_logic_vector(extABuf2Tx_c.span, 16), asyncBuffer2Rx => conv_std_logic_vector(extABuf2Rx_c.base, 16) & conv_std_logic_vector(extABuf2Rx_c.span, 16) ) port map ( --memory mapped interface clk => ap_clk, rst => ap_reset, sel => selCntStReg_s.ap, wr => ap_write, rd => ap_read, addr => ap_address(extLog2MaxOneSpan-1-2 downto 0), be => ap_byteenable, din => ap_writedata, dout => outCntStReg_s.ap, --register content ---virtual buffer control signals pdoVirtualBufferSel => vBufSel_s.ap, tPdoTrigger => vBufTriggerPdo_s.ap(3), rPdoTrigger => vBufTriggerPdo_s.ap(2 downto 0), ---event registers eventAckIn => ap_eventAck, eventAckOut => ap_eventAck_p, ---async irq (by event) asyncIrqCtrlIn => asyncIrqCtrlIn_s, asyncIrqCtrlOut => asyncIrqCtrlOut_s, ---led stuff ledCnfgIn => ap_ledForce_s, ledCnfgOut => ap_ledForce_s, ledCtrlIn => ap_ledSet_s, ledCtrlOut => ap_ledSet_s, ---time synchronization doubleBufSel_out => ap_timeSyncDBufSel, doubleBufSel_in => '0', --AP is the source timeSyncIrq => ap_irq_s, --dpr interface (from PCP/AP to DPR) dprAddrOff => dprCntStReg_s.ap.addrOff, dprDin => dprCntStReg_s.ap.din, dprDout => dprOut.ap, dprBe => dprCntStReg_s.ap.be, dprWr => dprCntStReg_s.ap.wr, --ap irq generation --apIrqValue => apIrqControlOut => apIrqControlApOut, apIrqControlIn => apIrqControlApIn, rpdo_change_tog => (others => '0'), tpdo_change_tog => '0' ); theApIrqGenerator : entity work.apIrqGen generic map ( genOnePdiClkDomain_g => genOnePdiClkDomain_g ) port map ( --CLOCK DOMAIN PCP clkA => pcp_clk, rstA => pcp_reset, irqA => pcp_irq, --preValA => apIrqValue, enableA => apIrqControlPcp(7), modeA => apIrqControlPcp(6), setA => apIrqControlPcp(0), --CLOCK DOMAIN AP clkB => ap_clk, rstB => ap_reset, ackB => apIrqControlApOut(0), irqB => ap_irq_s ); --irq enabled by apIrqControlApOut(15) ap_irq <= ap_irq_s and apIrqControlApOut(15); apIrqControlApIn <= apIrqControlApOut(15) & "000" & x"00" & "000" & ap_irq_s; --the LED stuff genLedGadget : if genLedGadget_g generate --first set the hw leds hw_ledForce_s <= x"00" & "00111100"; --phy1 and 0 act and link hw_ledSet_s <= x"00" & "00" & (phyAct(1) and phyLink(1)) & phyLink(1) & (phyAct(0) and phyLink(0)) & phyLink(0) & "00"; theLedGadget : entity work.pdiLed generic map ( iLedWidth_g => ledsOut'length ) port map ( --src A (lowest priority) srcAled => hw_ledSet_s(ledsOut'range), srcAforce => hw_ledForce_s(ledsOut'range), --src B srcBled => pcp_ledSet_s(ledsOut'range), srcBforce => pcp_ledForce_s(ledsOut'range), --src C (highest priority) srcCled => ap_ledSet_s(ledsOut'range), srcCforce => ap_ledForce_s(ledsOut'range), --led output ledOut => ledsOut ); end generate; genEventComp : if genEvent_g generate begin theEventBlock : block --set here the number of events constant iSwEvent_c : integer := 1; constant iHwEvent_c : integer := 2; signal eventSetA : std_logic_vector(iSwEvent_c-1 downto 0); signal eventReadA : std_logic_vector(iSwEvent_c+iHwEvent_c-1 downto 0); signal eventAckB : std_logic_vector(iSwEvent_c+iHwEvent_c-1 downto 0); signal eventReadB : std_logic_vector(iSwEvent_c+iHwEvent_c-1 downto 0); begin --event mapping: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -- in register x x x x x x x x hw hw x x x x x sw -- in pdiEvent hw hw sw eventSetA <= pcp_eventSet_s(0 downto 0); --pcp sets sw event (I know, its called generic event, bla...) pcp_eventRead <= x"00" & eventReadA(iSwEvent_c+iHwEvent_c-1 downto iSwEvent_c) & "00000" & eventReadA(iSwEvent_c-1 downto 0); eventAckB <= ap_eventAck_p(7 downto 6) & ap_eventAck_p(0); --ap acks events ap_eventAck <= x"00" & eventReadB(iSwEvent_c+iHwEvent_c-1 downto iSwEvent_c) & "00000" & eventReadB(iSwEvent_c-1 downto 0); theEventStuff : entity work.pdiEvent --16 bit -- sw is at bit 0 -- hw is at bit 6 and 7 generic map ( genOnePdiClkDomain_g => genOnePdiClkDomain_g, iSwEvent_g => 1, iHwEvent_g => 2 ) port map ( --port A -> PCP clkA => pcp_clk, rstA => pcp_reset, eventSetA => eventSetA, eventReadA => eventReadA, --port B -> AP clkB => ap_clk, rstB => ap_reset, eventAckB => eventAckB, eventReadB => eventReadB, --hw event set pulse (must be synchronous to clkB!) hwEventSetPulseB => phyLinkEvent ); --generate async interrupt asyncIrq : process(ap_eventAck) variable tmp : std_logic; begin tmp := '0'; for i in ap_eventAck'range loop tmp := tmp or ap_eventAck(i); end loop; ap_asyncIrq_s <= tmp; end process; --IRQ is asserted if enabled by AP ap_asyncIrq <= ap_asyncIrq_s and asyncIrqCtrlOut_s(15); asyncIrqCtrlIn_s(15) <= asyncIrqCtrlOut_s(15); asyncIrqCtrlIn_s(14 downto 1) <= (others => '0'); --ignoring the rest asyncIrqCtrlIn_s(0) <= ap_asyncIrq_s; --AP may poll IRQ level syncPhyLinkGen : for i in phyLink'range generate syncPhyLink : entity work.sync generic map ( doSync_g => not genOnePdiClkDomain_g ) port map ( din => phyLink(i), dout => phyLink_s(i), clk => ap_clk, rst => ap_reset ); detPhyLinkEdge : entity work.edgeDet port map ( din => phyLink_s(i), rising => open, falling => phyLinkEvent(i), --if phy link deasserts - EVENT!!! any => open, clk => ap_clk, rst => ap_reset ); end generate; end block; end generate; ------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------ -- asynchronous Buffer 1 Tx genABuf1Tx : if genABuf1_g generate theAsyncBuf1Tx4Pcp : entity work.pdiSimpleReg generic map ( iAddrWidth_g => extLog2MaxOneSpan-2, iBaseMap2_g => intABuf1Tx_c.base/4, iDprAddrWidth_g => dprABuf1Tx_s.pcp.addr'length ) port map ( --memory mapped interface sel => selABuf1Tx_s.pcp, wr => pcp_write, rd => pcp_read, addr => pcp_address(extLog2MaxOneSpan-1-2 downto 0), be => pcp_byteenable, din => pcp_writedata, dout => outABuf1Tx_s.pcp, --dpr interface (from PCP/AP to DPR) dprAddrOff => dprABuf1Tx_s.pcp.addrOff, dprDin => dprABuf1Tx_s.pcp.din, dprDout => dprOut.pcp, dprBe => dprABuf1Tx_s.pcp.be, dprWr => dprABuf1Tx_s.pcp.wr ); theAsyncBuf1Tx4Ap : entity work.pdiSimpleReg generic map ( iAddrWidth_g => extLog2MaxOneSpan-2, iBaseMap2_g => intABuf1Tx_c.base/4, iDprAddrWidth_g => dprABuf1Tx_s.ap.addr'length ) port map ( --memory mapped interface sel => selABuf1Tx_s.ap, wr => ap_write, rd => ap_read, addr => ap_address(extLog2MaxOneSpan-1-2 downto 0), be => ap_byteenable, din => ap_writedata, dout => outABuf1Tx_s.ap, --dpr interface (from PCP/AP to DPR) dprAddrOff => dprABuf1Tx_s.ap.addrOff, dprDin => dprABuf1Tx_s.ap.din, dprDout => dprOut.ap, dprBe => dprABuf1Tx_s.ap.be, dprWr => dprABuf1Tx_s.ap.wr ); end generate; ------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------ -- asynchronous Buffer 1 Rx genABuf1Rx : if genABuf1_g generate theAsyncBuf1Rx4Pcp : entity work.pdiSimpleReg generic map ( iAddrWidth_g => extLog2MaxOneSpan-2, iBaseMap2_g => intABuf1Rx_c.base/4, iDprAddrWidth_g => dprABuf1Rx_s.pcp.addr'length ) port map ( --memory mapped interface sel => selABuf1Rx_s.pcp, wr => pcp_write, rd => pcp_read, addr => pcp_address(extLog2MaxOneSpan-1-2 downto 0), be => pcp_byteenable, din => pcp_writedata, dout => outABuf1Rx_s.pcp, --dpr interface (from PCP/AP to DPR) dprAddrOff => dprABuf1Rx_s.pcp.addrOff, dprDin => dprABuf1Rx_s.pcp.din, dprDout => dprOut.pcp, dprBe => dprABuf1Rx_s.pcp.be, dprWr => dprABuf1Rx_s.pcp.wr ); theAsyncBuf1Rx4Ap : entity work.pdiSimpleReg generic map ( iAddrWidth_g => extLog2MaxOneSpan-2, iBaseMap2_g => intABuf1Rx_c.base/4, iDprAddrWidth_g => dprABuf1Rx_s.ap.addr'length ) port map ( --memory mapped interface sel => selABuf1Rx_s.ap, wr => ap_write, rd => ap_read, addr => ap_address(extLog2MaxOneSpan-1-2 downto 0), be => ap_byteenable, din => ap_writedata, dout => outABuf1Rx_s.ap, --dpr interface (from PCP/AP to DPR) dprAddrOff => dprABuf1Rx_s.ap.addrOff, dprDin => dprABuf1Rx_s.ap.din, dprDout => dprOut.ap, dprBe => dprABuf1Rx_s.ap.be, dprWr => dprABuf1Rx_s.ap.wr ); end generate; ------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------ -- asynchronous Buffer 2 Tx genABuf2Tx : if genABuf2_g generate theAsyncBuf2Tx4Pcp : entity work.pdiSimpleReg generic map ( iAddrWidth_g => extLog2MaxOneSpan-2, iBaseMap2_g => intABuf2Tx_c.base/4, iDprAddrWidth_g => dprABuf2Tx_s.pcp.addr'length ) port map ( --memory mapped interface sel => selABuf2Tx_s.pcp, wr => pcp_write, rd => pcp_read, addr => pcp_address(extLog2MaxOneSpan-1-2 downto 0), be => pcp_byteenable, din => pcp_writedata, dout => outABuf2Tx_s.pcp, --dpr interface (from PCP/AP to DPR) dprAddrOff => dprABuf2Tx_s.pcp.addrOff, dprDin => dprABuf2Tx_s.pcp.din, dprDout => dprOut.pcp, dprBe => dprABuf2Tx_s.pcp.be, dprWr => dprABuf2Tx_s.pcp.wr ); theAsyncBuf2Tx4Ap : entity work.pdiSimpleReg generic map ( iAddrWidth_g => extLog2MaxOneSpan-2, iBaseMap2_g => intABuf2Tx_c.base/4, iDprAddrWidth_g => dprABuf2Tx_s.ap.addr'length ) port map ( --memory mapped interface sel => selABuf2Tx_s.ap, wr => ap_write, rd => ap_read, addr => ap_address(extLog2MaxOneSpan-1-2 downto 0), be => ap_byteenable, din => ap_writedata, dout => outABuf2Tx_s.ap, --dpr interface (from PCP/AP to DPR) dprAddrOff => dprABuf2Tx_s.ap.addrOff, dprDin => dprABuf2Tx_s.ap.din, dprDout => dprOut.ap, dprBe => dprABuf2Tx_s.ap.be, dprWr => dprABuf2Tx_s.ap.wr ); end generate; ------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------ -- asynchronous Buffer 2 Rx genABuf2Rx : if genABuf2_g generate theAsyncBuf2Rx4Pcp : entity work.pdiSimpleReg generic map ( iAddrWidth_g => extLog2MaxOneSpan-2, iBaseMap2_g => intABuf2Rx_c.base/4, iDprAddrWidth_g => dprABuf2Rx_s.pcp.addr'length ) port map ( --memory mapped interface sel => selABuf2Rx_s.pcp, wr => pcp_write, rd => pcp_read, addr => pcp_address(extLog2MaxOneSpan-1-2 downto 0), be => pcp_byteenable, din => pcp_writedata, dout => outABuf2Rx_s.pcp, --dpr interface (from PCP/AP to DPR) dprAddrOff => dprABuf2Rx_s.pcp.addrOff, dprDin => dprABuf2Rx_s.pcp.din, dprDout => dprOut.pcp, dprBe => dprABuf2Rx_s.pcp.be, dprWr => dprABuf2Rx_s.pcp.wr ); theAsyncBuf2Rx4Ap : entity work.pdiSimpleReg generic map ( iAddrWidth_g => extLog2MaxOneSpan-2, iBaseMap2_g => intABuf2Rx_c.base/4, iDprAddrWidth_g => dprABuf2Rx_s.ap.addr'length ) port map ( --memory mapped interface sel => selABuf2Rx_s.ap, wr => ap_write, rd => ap_read, addr => ap_address(extLog2MaxOneSpan-1-2 downto 0), be => ap_byteenable, din => ap_writedata, dout => outABuf2Rx_s.ap, --dpr interface (from PCP/AP to DPR) dprAddrOff => dprABuf2Rx_s.ap.addrOff, dprDin => dprABuf2Rx_s.ap.din, dprDout => dprOut.ap, dprBe => dprABuf2Rx_s.ap.be, dprWr => dprABuf2Rx_s.ap.wr ); end generate; ------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------ --TPDO buffer theTpdoTrippleBuffer : block signal selVBufPcpOneHot : std_logic_vector(2 downto 0); signal selVBufApOneHot : std_logic_vector(2 downto 0); begin vBufSel_s.pcp(31 downto 24) <= x"00" when selVBufPcpOneHot = "001" else x"11" when selVBufPcpOneHot = "010" else x"22" when selVBufPcpOneHot = "100" else x"FF"; vBufSel_s.ap(31 downto 24) <= x"00" when selVBufApOneHot = "001" else x"11" when selVBufApOneHot = "010" else x"22" when selVBufApOneHot = "100" else x"FF"; dprTpdoBuf_s.pcp.din <= pcp_writedata; outTpdoBuf_s.pcp <= dprOut.pcp; dprTpdoBuf_s.pcp.be <= pcp_byteenable; dprTpdoBuf_s.pcp.wr <= pcp_write; dprTpdoBuf_s.ap.din <= ap_writedata; outTpdoBuf_s.ap <= dprOut.ap; dprTpdoBuf_s.ap.be <= ap_byteenable; dprTpdoBuf_s.ap.wr <= ap_write; theTrippleMechanism : entity work.tripleVBufLogic generic map ( genOnePdiClkDomain_g => genOnePdiClkDomain_g, --base address of virtual buffers in DPR iVirtualBufferBase_g => intTpdoBuf_c.base/4, --double word! --size of one virtual buffer in DPR (must be aligned!!!) iVirtualBufferSize_g => intTpdoBuf_c.span/3/4, --double word! --out address width iOutAddrWidth_g => dprTpdoBuf_s.pcp.addr'length, --in address width iInAddrWidth_g => extLog2MaxOneSpan-2, --ap is producer bApIsProducer => true ) port map ( pcpClk => pcp_clk, pcpReset => pcp_reset, pcpTrigger => vBufTriggerPdo_s.pcp(3), pcpOutAddrOff => dprTpdoBuf_s.pcp.addrOff, pcpOutSelVBuf => selVBufPcpOneHot, apClk => ap_clk, apReset => ap_reset, apTrigger => vBufTriggerPdo_s.ap(3), apOutAddrOff => dprTpdoBuf_s.ap.addrOff, apOutSelVBuf => selVBufApOneHot ); end block; -- ------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------ --RPDO0 buffer theRpdo0TrippleBuffer : block signal selVBufPcpOneHot : std_logic_vector(2 downto 0); signal selVBufApOneHot : std_logic_vector(2 downto 0); begin vBufSel_s.pcp(7 downto 0) <= x"00" when selVBufPcpOneHot = "001" else x"11" when selVBufPcpOneHot = "010" else x"22" when selVBufPcpOneHot = "100" else x"FF"; vBufSel_s.ap(7 downto 0) <= x"00" when selVBufApOneHot = "001" else x"11" when selVBufApOneHot = "010" else x"22" when selVBufApOneHot = "100" else x"FF"; dprRpdo0Buf_s.pcp.din <= pcp_writedata; outRpdo0Buf_s.pcp <= dprOut.pcp; dprRpdo0Buf_s.pcp.be <= pcp_byteenable; dprRpdo0Buf_s.pcp.wr <= pcp_write; dprRpdo0Buf_s.ap.din <= ap_writedata; outRpdo0Buf_s.ap <= dprOut.ap; dprRpdo0Buf_s.ap.be <= ap_byteenable; dprRpdo0Buf_s.ap.wr <= ap_write; theTrippleMechanism : entity work.tripleVBufLogic generic map ( genOnePdiClkDomain_g => genOnePdiClkDomain_g, --base address of virtual buffers in DPR iVirtualBufferBase_g => intRpdo0Buf_c.base/4, --double word! --size of one virtual buffer in DPR (must be aligned!!!) iVirtualBufferSize_g => intRpdo0Buf_c.span/3/4, --double word! --out address width iOutAddrWidth_g => dprRpdo0Buf_s.pcp.addr'length, --in address width iInAddrWidth_g => extLog2MaxOneSpan-2, --ap is NOT producer bApIsProducer => false ) port map ( pcpClk => pcp_clk, pcpReset => pcp_reset, pcpTrigger => vBufTriggerPdo_s.pcp(0), pcpOutAddrOff => dprRpdo0Buf_s.pcp.addrOff, pcpOutSelVBuf => selVBufPcpOneHot, apClk => ap_clk, apReset => ap_reset, apTrigger => vBufTriggerPdo_s.ap(0), apOutAddrOff => dprRpdo0Buf_s.ap.addrOff, apOutSelVBuf => selVBufApOneHot ); end block; -- ------------------------------------------------------------------------------------------------------------------------ genRpdo1 : if iRpdos_g >= 2 generate ------------------------------------------------------------------------------------------------------------------------ --RPDO1 buffer theRpdo1TrippleBuffer : block signal selVBufPcpOneHot : std_logic_vector(2 downto 0); signal selVBufApOneHot : std_logic_vector(2 downto 0); begin vBufSel_s.pcp(15 downto 8) <= x"00" when selVBufPcpOneHot = "001" else x"11" when selVBufPcpOneHot = "010" else x"22" when selVBufPcpOneHot = "100" else x"FF"; vBufSel_s.ap(15 downto 8) <= x"00" when selVBufApOneHot = "001" else x"11" when selVBufApOneHot = "010" else x"22" when selVBufApOneHot = "100" else x"FF"; dprRpdo1Buf_s.pcp.din <= pcp_writedata; outRpdo1Buf_s.pcp <= dprOut.pcp; dprRpdo1Buf_s.pcp.be <= pcp_byteenable; dprRpdo1Buf_s.pcp.wr <= pcp_write; dprRpdo1Buf_s.ap.din <= ap_writedata; outRpdo1Buf_s.ap <= dprOut.ap; dprRpdo1Buf_s.ap.be <= ap_byteenable; dprRpdo1Buf_s.ap.wr <= ap_write; theTrippleMechanism : entity work.tripleVBufLogic generic map ( genOnePdiClkDomain_g => genOnePdiClkDomain_g, --base address of virtual buffers in DPR iVirtualBufferBase_g => intRpdo1Buf_c.base/4, --double word! --size of one virtual buffer in DPR (must be aligned!!!) iVirtualBufferSize_g => intRpdo1Buf_c.span/3/4, --double word! --out address width iOutAddrWidth_g => dprRpdo1Buf_s.pcp.addr'length, --in address width iInAddrWidth_g => extLog2MaxOneSpan-2, --ap is NOT producer bApIsProducer => false ) port map ( pcpClk => pcp_clk, pcpReset => pcp_reset, pcpTrigger => vBufTriggerPdo_s.pcp(1), pcpOutAddrOff => dprRpdo1Buf_s.pcp.addrOff, pcpOutSelVBuf => selVBufPcpOneHot, apClk => ap_clk, apReset => ap_reset, apTrigger => vBufTriggerPdo_s.ap(1), apOutAddrOff => dprRpdo1Buf_s.ap.addrOff, apOutSelVBuf => selVBufApOneHot ); end block; -- ------------------------------------------------------------------------------------------------------------------------ end generate; genRpdo2 : if iRpdos_g >= 3 generate ------------------------------------------------------------------------------------------------------------------------ --RPDO2 buffer theRpdo2TrippleBuffer : block signal selVBufPcpOneHot : std_logic_vector(2 downto 0); signal selVBufApOneHot : std_logic_vector(2 downto 0); begin vBufSel_s.pcp(23 downto 16) <= x"00" when selVBufPcpOneHot = "001" else x"11" when selVBufPcpOneHot = "010" else x"22" when selVBufPcpOneHot = "100" else x"FF"; vBufSel_s.ap(23 downto 16) <= x"00" when selVBufApOneHot = "001" else x"11" when selVBufApOneHot = "010" else x"22" when selVBufApOneHot = "100" else x"FF"; dprRpdo2Buf_s.pcp.din <= pcp_writedata; outRpdo2Buf_s.pcp <= dprOut.pcp; dprRpdo2Buf_s.pcp.be <= pcp_byteenable; dprRpdo2Buf_s.pcp.wr <= pcp_write; dprRpdo2Buf_s.ap.din <= ap_writedata; outRpdo2Buf_s.ap <= dprOut.ap; dprRpdo2Buf_s.ap.be <= ap_byteenable; dprRpdo2Buf_s.ap.wr <= ap_write; theTrippleMechanism : entity work.tripleVBufLogic generic map ( genOnePdiClkDomain_g => genOnePdiClkDomain_g, --base address of virtual buffers in DPR iVirtualBufferBase_g => intRpdo2Buf_c.base/4, --double word! --size of one virtual buffer in DPR (must be aligned!!!) iVirtualBufferSize_g => intRpdo2Buf_c.span/3/4, --double word! --out address width iOutAddrWidth_g => dprRpdo2Buf_s.pcp.addr'length, --in address width iInAddrWidth_g => extLog2MaxOneSpan-2, --ap is NOT producer bApIsProducer => false ) port map ( pcpClk => pcp_clk, pcpReset => pcp_reset, pcpTrigger => vBufTriggerPdo_s.pcp(2), pcpOutAddrOff => dprRpdo2Buf_s.pcp.addrOff, pcpOutSelVBuf => selVBufPcpOneHot, apClk => ap_clk, apReset => ap_reset, apTrigger => vBufTriggerPdo_s.ap(2), apOutAddrOff => dprRpdo2Buf_s.ap.addrOff, apOutSelVBuf => selVBufApOneHot ); end block; -- ------------------------------------------------------------------------------------------------------------------------ end generate; ------------------------------------------------------------------------------------------------------------------------ -- waitrequest signals theWaitrequestGenerators : block signal pcp_wr, pcp_rd, pcp_rd_ack, pcp_wr_ack : std_logic; signal ap_wr, ap_rd, ap_rd_ack, ap_wr_ack : std_logic; begin -- PCP thePcpWrWaitReqAckGen : entity work.req_ack generic map ( zero_delay_g => true ) port map ( clk => pcp_clk, rst => pcp_reset, enable => pcp_wr, ack => pcp_wr_ack ); thePcpRdWaitReqAckGen : entity work.req_ack generic map ( ack_delay_g => 2, zero_delay_g => false ) port map ( clk => pcp_clk, rst => pcp_reset, enable => pcp_rd, ack => pcp_rd_ack ); pcp_wr <= pcp_chipselect and pcp_write; pcp_rd <= pcp_chipselect and pcp_read; pcp_waitrequest <= not(pcp_rd_ack or pcp_wr_ack); -- AP theApWrWaitReqAckGen : entity work.req_ack generic map ( zero_delay_g => true ) port map ( clk => ap_clk, rst => ap_reset, enable => ap_wr, ack => ap_wr_ack ); theApRdWaitReqAckGen : entity work.req_ack generic map ( ack_delay_g => 2, zero_delay_g => false ) port map ( clk => ap_clk, rst => ap_reset, enable => ap_rd, ack => ap_rd_ack ); ap_wr <= ap_chipselect and ap_write; ap_rd <= ap_chipselect and ap_read; ap_waitrequest <= not(ap_rd_ack or ap_wr_ack); end block; -- ------------------------------------------------------------------------------------------------------------------------ end architecture rtl;
gpl-2.0
3986983085400204c0cd09bb1a2cff3a
0.423229
4.815872
false
false
false
false
OrganicMonkeyMotion/fpga_experiments
small_board/LABS/digital_logic/vhdl/lab2/part6/lpm_constant2.vhd
1
3,515
-- megafunction wizard: %LPM_CONSTANT% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: LPM_CONSTANT -- ============================================================ -- File Name: lpm_constant2.vhd -- Megafunction Name(s): -- LPM_CONSTANT -- -- Simulation Library Files(s): -- lpm -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition -- ************************************************************ --Copyright (C) 1991-2011 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.all; ENTITY lpm_constant2 IS PORT ( result : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ); END lpm_constant2; ARCHITECTURE SYN OF lpm_constant2 IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0); COMPONENT lpm_constant GENERIC ( lpm_cvalue : NATURAL; lpm_hint : STRING; lpm_type : STRING; lpm_width : NATURAL ); PORT ( result : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ); END COMPONENT; BEGIN result <= sub_wire0(3 DOWNTO 0); LPM_CONSTANT_component : LPM_CONSTANT GENERIC MAP ( lpm_cvalue => 8, lpm_hint => "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=NONE", lpm_type => "LPM_CONSTANT", lpm_width => 4 ) PORT MAP ( result => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1" -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" -- Retrieval info: PRIVATE: Radix NUMERIC "2" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: Value NUMERIC "8" -- Retrieval info: PRIVATE: nBit NUMERIC "4" -- Retrieval info: PRIVATE: new_diagram STRING "1" -- Retrieval info: LIBRARY: lpm lpm.lpm_components.all -- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "8" -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=NONE" -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4" -- Retrieval info: USED_PORT: result 0 0 4 0 OUTPUT NODEFVAL "result[3..0]" -- Retrieval info: CONNECT: result 0 0 4 0 @result 0 0 4 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.bsf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2_inst.vhd FALSE -- Retrieval info: LIB_FILE: lpm
unlicense
ef702251676006e878a94dbe8806f5fd
0.646942
3.820652
false
false
false
false
simonspa/pixel-dtb-firmware
dtb/ram_dqINST_lb.vhd
2
7,061
-- megafunction wizard: %RAM: 1-PORT% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altsyncram -- ============================================================ -- File Name: ram_dqINST_lb.vhd -- Megafunction Name(s): -- altsyncram -- -- Simulation Library Files(s): -- altera_mf -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version -- ************************************************************ --Copyright (C) 1991-2012 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY ram_dqINST_lb IS PORT ( address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); clock : IN STD_LOGIC := '1'; data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); wren : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END ram_dqINST_lb; ARCHITECTURE SYN OF ram_dqinst_lb IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); COMPONENT altsyncram GENERIC ( clock_enable_input_a : STRING; clock_enable_output_a : STRING; intended_device_family : STRING; lpm_hint : STRING; lpm_type : STRING; numwords_a : NATURAL; operation_mode : STRING; outdata_aclr_a : STRING; outdata_reg_a : STRING; power_up_uninitialized : STRING; read_during_write_mode_port_a : STRING; widthad_a : NATURAL; width_a : NATURAL; width_byteena_a : NATURAL ); PORT ( address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); clock0 : IN STD_LOGIC ; data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); wren_a : IN STD_LOGIC ; q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT; BEGIN q <= sub_wire0(7 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( clock_enable_input_a => "BYPASS", clock_enable_output_a => "BYPASS", intended_device_family => "Cyclone III", lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=N_lb", lpm_type => "altsyncram", numwords_a => 256, operation_mode => "SINGLE_PORT", outdata_aclr_a => "NONE", outdata_reg_a => "CLOCK0", power_up_uninitialized => "FALSE", read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", widthad_a => 8, width_a => 8, width_byteena_a => 1 ) PORT MAP ( address_a => address, clock0 => clock, data_a => data, wren_a => wren, q_a => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" -- Retrieval info: PRIVATE: AclrByte NUMERIC "0" -- Retrieval info: PRIVATE: AclrData NUMERIC "0" -- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: Clken NUMERIC "0" -- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1" -- Retrieval info: PRIVATE: JTAG_ID STRING "N_lb" -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -- Retrieval info: PRIVATE: MIFfilename STRING "" -- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256" -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" -- Retrieval info: PRIVATE: RegData NUMERIC "1" -- Retrieval info: PRIVATE: RegOutput NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" -- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" -- Retrieval info: PRIVATE: WidthAddr NUMERIC "8" -- Retrieval info: PRIVATE: WidthData NUMERIC "8" -- Retrieval info: PRIVATE: rden NUMERIC "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=N_lb" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" -- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" -- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" -- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" -- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" -- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 -- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dqINST_lb.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dqINST_lb.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dqINST_lb.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dqINST_lb.bsf FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dqINST_lb_inst.vhd FALSE -- Retrieval info: LIB_FILE: altera_mf
unlicense
02c4e9ef63dbcdc924a32e203450fd04
0.672851
3.462972
false
false
false
false
simonspa/pixel-dtb-firmware
dtb/nedge_s.vhd
2
2,654
-- Copyright (C) 1991-2010 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License -- Subscription Agreement, Altera MegaCore Function License -- Agreement, or other applicable license agreement, including, -- without limitation, that your use is for the sole purpose of -- programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the -- applicable agreement for further details. -- PROGRAM "Quartus II 64-Bit" -- VERSION "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Full Version" -- CREATED "Thu Oct 31 13:57:57 2013" LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY work; ENTITY nedge_s IS PORT ( D : IN STD_LOGIC; CK : IN STD_LOGIC; Q : OUT STD_LOGIC ); END nedge_s; ARCHITECTURE bdf_type OF nedge_s IS SIGNAL SYNTHESIZED_WIRE_0 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_1 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_2 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_8 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_3 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_4 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_5 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_6 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_7 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_9 : STD_LOGIC; BEGIN SYNTHESIZED_WIRE_0 <= '1'; SYNTHESIZED_WIRE_1 <= '1'; SYNTHESIZED_WIRE_2 <= '1'; SYNTHESIZED_WIRE_3 <= '1'; SYNTHESIZED_WIRE_4 <= '1'; SYNTHESIZED_WIRE_6 <= '1'; PROCESS(CK,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_1) BEGIN IF (SYNTHESIZED_WIRE_0 = '0') THEN SYNTHESIZED_WIRE_8 <= '0'; ELSIF (SYNTHESIZED_WIRE_1 = '0') THEN SYNTHESIZED_WIRE_8 <= '1'; ELSIF (RISING_EDGE(CK)) THEN SYNTHESIZED_WIRE_8 <= D; END IF; END PROCESS; PROCESS(CK,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_3) BEGIN IF (SYNTHESIZED_WIRE_2 = '0') THEN SYNTHESIZED_WIRE_9 <= '0'; ELSIF (SYNTHESIZED_WIRE_3 = '0') THEN SYNTHESIZED_WIRE_9 <= '1'; ELSIF (RISING_EDGE(CK)) THEN SYNTHESIZED_WIRE_9 <= SYNTHESIZED_WIRE_8; END IF; END PROCESS; PROCESS(CK,SYNTHESIZED_WIRE_4,SYNTHESIZED_WIRE_6) BEGIN IF (SYNTHESIZED_WIRE_4 = '0') THEN Q <= '0'; ELSIF (SYNTHESIZED_WIRE_6 = '0') THEN Q <= '1'; ELSIF (RISING_EDGE(CK)) THEN Q <= SYNTHESIZED_WIRE_5; END IF; END PROCESS; SYNTHESIZED_WIRE_5 <= SYNTHESIZED_WIRE_7 AND SYNTHESIZED_WIRE_9; SYNTHESIZED_WIRE_7 <= SYNTHESIZED_WIRE_8 XOR SYNTHESIZED_WIRE_9; END bdf_type;
unlicense
ddec95cb093fb5d98c82ba81942f0026
0.718538
3.16329
false
false
false
false
simonspa/pixel-dtb-firmware
dtb/IS_ram.vhd
2
6,910
-- megafunction wizard: %LPM_RAM_DQ% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altsyncram -- ============================================================ -- File Name: IS_ram.vhd -- Megafunction Name(s): -- altsyncram -- -- Simulation Library Files(s): -- altera_mf -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 9.1 Build 222 10/21/2009 SJ Full Version -- ************************************************************ --Copyright (C) 1991-2009 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY IS_ram IS PORT ( address : IN STD_LOGIC_VECTOR (4 DOWNTO 0); clock : IN STD_LOGIC ; data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); wren : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END IS_ram; ARCHITECTURE SYN OF is_ram IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); COMPONENT altsyncram GENERIC ( clock_enable_input_a : STRING; clock_enable_output_a : STRING; intended_device_family : STRING; lpm_hint : STRING; lpm_type : STRING; numwords_a : NATURAL; operation_mode : STRING; outdata_aclr_a : STRING; outdata_reg_a : STRING; power_up_uninitialized : STRING; widthad_a : NATURAL; width_a : NATURAL; width_byteena_a : NATURAL ); PORT ( wren_a : IN STD_LOGIC ; clock0 : IN STD_LOGIC ; address_a : IN STD_LOGIC_VECTOR (4 DOWNTO 0); q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT; BEGIN q <= sub_wire0(7 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( clock_enable_input_a => "BYPASS", clock_enable_output_a => "BYPASS", intended_device_family => "Arria GX", lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=PhK", lpm_type => "altsyncram", numwords_a => 32, operation_mode => "SINGLE_PORT", outdata_aclr_a => "NONE", outdata_reg_a => "CLOCK0", power_up_uninitialized => "FALSE", widthad_a => 5, width_a => 8, width_byteena_a => 1 ) PORT MAP ( wren_a => wren, clock0 => clock, address_a => address, data_a => data, q_a => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" -- Retrieval info: PRIVATE: AclrByte NUMERIC "0" -- Retrieval info: PRIVATE: AclrData NUMERIC "0" -- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: Clken NUMERIC "0" -- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1" -- Retrieval info: PRIVATE: JTAG_ID STRING "PhK" -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -- Retrieval info: PRIVATE: MIFfilename STRING "" -- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32" -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" -- Retrieval info: PRIVATE: RegData NUMERIC "1" -- Retrieval info: PRIVATE: RegOutput NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" -- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" -- Retrieval info: PRIVATE: WidthAddr NUMERIC "5" -- Retrieval info: PRIVATE: WidthData NUMERIC "8" -- Retrieval info: PRIVATE: rden NUMERIC "0" -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria GX" -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=PhK" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5" -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -- Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL address[4..0] -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock -- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0] -- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0] -- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren -- Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0 -- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 -- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: GEN_FILE: TYPE_NORMAL IS_ram.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL IS_ram.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL IS_ram.cmp FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL IS_ram.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL IS_ram_inst.vhd FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL IS_ram_waveforms.html TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL IS_ram_wave*.jpg FALSE -- Retrieval info: LIB_FILE: altera_mf
unlicense
5c2a39fbf6de6da24c79effc5385e89b
0.673082
3.509396
false
false
false
false
simonspa/pixel-dtb-firmware
dtb/lpm_counter0.vhd
2
4,431
-- megafunction wizard: %LPM_COUNTER% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: lpm_counter -- ============================================================ -- File Name: lpm_counter0.vhd -- Megafunction Name(s): -- lpm_counter -- -- Simulation Library Files(s): -- lpm -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 9.1 Build 222 10/21/2009 SJ Full Version -- ************************************************************ --Copyright (C) 1991-2009 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.all; ENTITY lpm_counter0 IS PORT ( aclr : IN STD_LOGIC ; clock : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0) ); END lpm_counter0; ARCHITECTURE SYN OF lpm_counter0 IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (29 DOWNTO 0); COMPONENT lpm_counter GENERIC ( lpm_direction : STRING; lpm_port_updown : STRING; lpm_type : STRING; lpm_width : NATURAL ); PORT ( aclr : IN STD_LOGIC ; clock : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0) ); END COMPONENT; BEGIN q <= sub_wire0(29 DOWNTO 0); lpm_counter_component : lpm_counter GENERIC MAP ( lpm_direction => "UP", lpm_port_updown => "PORT_UNUSED", lpm_type => "LPM_COUNTER", lpm_width => 30 ) PORT MAP ( aclr => aclr, clock => clock, q => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ACLR NUMERIC "1" -- Retrieval info: PRIVATE: ALOAD NUMERIC "0" -- Retrieval info: PRIVATE: ASET NUMERIC "0" -- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" -- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" -- Retrieval info: PRIVATE: CNT_EN NUMERIC "0" -- Retrieval info: PRIVATE: CarryIn NUMERIC "0" -- Retrieval info: PRIVATE: CarryOut NUMERIC "0" -- Retrieval info: PRIVATE: Direction NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX" -- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0" -- Retrieval info: PRIVATE: ModulusValue NUMERIC "0" -- Retrieval info: PRIVATE: SCLR NUMERIC "0" -- Retrieval info: PRIVATE: SLOAD NUMERIC "0" -- Retrieval info: PRIVATE: SSET NUMERIC "0" -- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: nBit NUMERIC "30" -- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP" -- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "30" -- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock -- Retrieval info: USED_PORT: q 0 0 30 0 OUTPUT NODEFVAL q[29..0] -- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 30 0 @q 0 0 30 0 -- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 -- Retrieval info: LIBRARY: lpm lpm.lpm_components.all -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.cmp FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_inst.vhd FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_waveforms.html TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_wave*.jpg FALSE -- Retrieval info: LIB_FILE: lpm
unlicense
3eb3a70c0307954ecf041817e148c992
0.655383
3.70795
false
false
false
false
Alix82/mip32vhdl
testbench.vhd
1
5,453
library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use ieee.std_logic_unsigned.all; -- use IEEE.std_logic_arith.all; use STD.textio.all; ----------------------------------------------------------- -- TB use WORK.mips; entity testbench is end entity testbench; architecture TB of testbench is component mips is port(inInstruction : in std_logic_vector(31 downto 0); clk : in std_logic; reset : in std_logic; O_Fetch : out std_logic; O_PCNext : out std_logic_vector(31 downto 0); outMemAddr : out std_logic_vector(31 downto 0); outMemRead : out std_logic; inMemReadData : in std_logic_vector(31 downto 0); inMemRead : in std_logic; outMemWrite : out std_logic; outMemWriteData : out std_logic_vector(31 downto 0) -- error_control : out std_logic ); end component; -- for mips0: mipspipe use entity work.mipspipe; signal erro : boolean := false; constant clk_period : time := 10 ns; signal instr : std_logic_vector(31 downto 0) := (others => '0'); signal pcfetch : std_logic; signal pcnext : std_logic_vector(31 downto 0) := X"00000000"; signal pc : std_logic_vector(31 downto 0) := X"00000000"; signal clk : std_logic := '0'; signal reset : std_logic := '1'; signal do_reset : std_logic := '0'; signal memaddr : std_logic_vector(31 downto 0) := (others => '0'); signal memreaddata : std_logic_vector(31 downto 0) := (others => '0'); signal memwritedata : std_logic_vector(31 downto 0) := (others => '0'); signal memwrite : std_logic := '0'; signal memread : std_logic := '0'; signal memreadack : std_logic := '0'; -- constant mem_size : Integer := 1024; constant stack_size : Integer := 128; type memory_array is array(0 to mem_size) of std_logic_vector(31 downto 0); type stack_array is array(0 to stack_size) of std_logic_vector(31 downto 0); signal stack_segment : stack_array := ( others => X"00000000" ); signal memory : memory_array := ( -- DATA_SECTION X"00000005", -- 0x5 00000000 -- TEXT_SECTION X"3c080000", -- lui t0,0x0 00000000 X"8d080000", -- lw t0,0(t0) 00000001 X"24090005", -- addiu t1,zero,5 00000002 X"00000000", X"01094820", -- add t1,t0,t1 00000003 X"3c010000", -- lui at,0x0 00000004 X"ac290000", -- sw t1,0(at) 00000005 X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", others=>X"00000000" ); begin mips0: mips port map(instr, clk, reset, pcfetch, pcnext, memaddr, memread, memreaddata, memreadack, memwrite, memwritedata); process begin clk <= not clk; wait for 10 ns; end process; process(clk) file log : text; variable line_num : line; variable line_content : string(1 to 32); variable i : integer := 0; Variable pctmp : std_logic_vector (31 downto 0) := (others => '0'); Variable memaddrlocal : std_logic_vector (31 downto 0) := (others => '0'); begin if(falling_edge(clk)) then if do_reset = '1' then reset <= '1'; do_reset <= '0'; else reset <= '0'; if pcfetch = '1' then pctmp := pcnext; pctmp(29 downto 0) := pctmp(31 downto 2); instr <= memory(to_integer(unsigned(pctmp))); end if; if memread = '1' then if memaddr >= X"10010000" then memaddrlocal := X"7FFFFFFF" - memaddr; memaddrlocal(29 downto 0) := memaddrlocal(31 downto 2); memreaddata <= stack_segment(to_integer(unsigned(memaddrlocal))); else memaddrlocal := memaddr; memaddrlocal(29 downto 0) := memaddrlocal(31 downto 2); memreaddata <= memory(to_integer(unsigned(memaddrlocal))); -- end if; memreadack <= '1'; elsif memwrite = '1' then if memaddr >= X"10010000" then memaddrlocal := X"7FFFFFFF" - memaddr; memaddrlocal(29 downto 0) := memaddrlocal(31 downto 2); stack_segment(to_integer(unsigned(memaddrlocal))) <= memwritedata; else memaddrlocal := memaddr; memaddrlocal(29 downto 0) := memaddrlocal(31 downto 2); memory(to_integer(unsigned(memaddrlocal))) <= memwritedata; end if; memreadack <= '0'; else memreadack <= '0'; end if; end if; end if; end process; stop_simulation :process --file file_pointer : text; begin wait for 300 ns; assert false report "simulation ended" severity failure; end process ; end TB;
bsd-2-clause
1f38a4d2e4390ecf7a8fe90cff7c90ac
0.505593
4.233696
false
false
false
false
simonspa/pixel-dtb-firmware
dtb/USBspy.vhd
2
7,009
-- megafunction wizard: %RAM: 1-PORT% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altsyncram -- ============================================================ -- File Name: USBspy.vhd -- Megafunction Name(s): -- altsyncram -- -- Simulation Library Files(s): -- altera_mf -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version -- ************************************************************ --Copyright (C) 1991-2012 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY USBspy IS PORT ( address : IN STD_LOGIC_VECTOR (4 DOWNTO 0); clock : IN STD_LOGIC := '1'; data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); wren : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END USBspy; ARCHITECTURE SYN OF usbspy IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); COMPONENT altsyncram GENERIC ( clock_enable_input_a : STRING; clock_enable_output_a : STRING; intended_device_family : STRING; lpm_hint : STRING; lpm_type : STRING; numwords_a : NATURAL; operation_mode : STRING; outdata_aclr_a : STRING; outdata_reg_a : STRING; power_up_uninitialized : STRING; read_during_write_mode_port_a : STRING; widthad_a : NATURAL; width_a : NATURAL; width_byteena_a : NATURAL ); PORT ( address_a : IN STD_LOGIC_VECTOR (4 DOWNTO 0); clock0 : IN STD_LOGIC ; data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); wren_a : IN STD_LOGIC ; q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT; BEGIN q <= sub_wire0(7 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( clock_enable_input_a => "BYPASS", clock_enable_output_a => "BYPASS", intended_device_family => "Cyclone III", lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=USB", lpm_type => "altsyncram", numwords_a => 32, operation_mode => "SINGLE_PORT", outdata_aclr_a => "NONE", outdata_reg_a => "UNREGISTERED", power_up_uninitialized => "FALSE", read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", widthad_a => 5, width_a => 8, width_byteena_a => 1 ) PORT MAP ( address_a => address, clock0 => clock, data_a => data, wren_a => wren, q_a => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" -- Retrieval info: PRIVATE: AclrByte NUMERIC "0" -- Retrieval info: PRIVATE: AclrData NUMERIC "0" -- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: Clken NUMERIC "0" -- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1" -- Retrieval info: PRIVATE: JTAG_ID STRING "USB" -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -- Retrieval info: PRIVATE: MIFfilename STRING "" -- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32" -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" -- Retrieval info: PRIVATE: RegData NUMERIC "1" -- Retrieval info: PRIVATE: RegOutput NUMERIC "0" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" -- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" -- Retrieval info: PRIVATE: WidthAddr NUMERIC "5" -- Retrieval info: PRIVATE: WidthData NUMERIC "8" -- Retrieval info: PRIVATE: rden NUMERIC "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=USB" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" -- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5" -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -- Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL "address[4..0]" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" -- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" -- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" -- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" -- Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 -- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL USBspy.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL USBspy.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL USBspy.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL USBspy.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL USBspy_inst.vhd FALSE -- Retrieval info: LIB_FILE: altera_mf
unlicense
88ec5ba419082b8d6b8f9909a3e16497
0.673277
3.497505
false
false
false
false
OrganicMonkeyMotion/fpga_experiments
small_board/LABS/digital_logic/vhdl/lab1/part5/M21EDAversion/lpm_decode0.vhd
1
4,265
-- megafunction wizard: %LPM_DECODE% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: LPM_DECODE -- ============================================================ -- File Name: lpm_decode0.vhd -- Megafunction Name(s): -- LPM_DECODE -- -- Simulation Library Files(s): -- lpm -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition -- ************************************************************ --Copyright (C) 1991-2011 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.all; ENTITY lpm_decode0 IS PORT ( data : IN STD_LOGIC_VECTOR (1 DOWNTO 0); eq0 : OUT STD_LOGIC ; eq1 : OUT STD_LOGIC ; eq2 : OUT STD_LOGIC ); END lpm_decode0; ARCHITECTURE SYN OF lpm_decode0 IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (2 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC ; SIGNAL sub_wire2 : STD_LOGIC ; SIGNAL sub_wire3 : STD_LOGIC ; COMPONENT lpm_decode GENERIC ( lpm_decodes : NATURAL; lpm_type : STRING; lpm_width : NATURAL ); PORT ( data : IN STD_LOGIC_VECTOR (1 DOWNTO 0); eq : OUT STD_LOGIC_VECTOR (2 DOWNTO 0) ); END COMPONENT; BEGIN sub_wire3 <= sub_wire0(2); sub_wire2 <= sub_wire0(1); sub_wire1 <= sub_wire0(0); eq0 <= sub_wire1; eq1 <= sub_wire2; eq2 <= sub_wire3; LPM_DECODE_component : LPM_DECODE GENERIC MAP ( lpm_decodes => 4, lpm_type => "LPM_DECODE", lpm_width => 2 ) PORT MAP ( data => data, eq => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: BaseDec NUMERIC "1" -- Retrieval info: PRIVATE: EnableInput NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" -- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0" -- Retrieval info: PRIVATE: Latency NUMERIC "0" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: aclr NUMERIC "0" -- Retrieval info: PRIVATE: clken NUMERIC "0" -- Retrieval info: PRIVATE: eq0 NUMERIC "1" -- Retrieval info: PRIVATE: eq1 NUMERIC "1" -- Retrieval info: PRIVATE: eq2 NUMERIC "1" -- Retrieval info: PRIVATE: eq3 NUMERIC "0" -- Retrieval info: PRIVATE: nBit NUMERIC "2" -- Retrieval info: PRIVATE: new_diagram STRING "1" -- Retrieval info: LIBRARY: lpm lpm.lpm_components.all -- Retrieval info: CONSTANT: LPM_DECODES NUMERIC "4" -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DECODE" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2" -- Retrieval info: USED_PORT: data 0 0 2 0 INPUT NODEFVAL "data[1..0]" -- Retrieval info: USED_PORT: eq0 0 0 0 0 OUTPUT NODEFVAL "eq0" -- Retrieval info: USED_PORT: eq1 0 0 0 0 OUTPUT NODEFVAL "eq1" -- Retrieval info: USED_PORT: eq2 0 0 0 0 OUTPUT NODEFVAL "eq2" -- Retrieval info: CONNECT: @data 0 0 2 0 data 0 0 2 0 -- Retrieval info: CONNECT: eq0 0 0 0 0 @eq 0 0 1 0 -- Retrieval info: CONNECT: eq1 0 0 0 0 @eq 0 0 1 1 -- Retrieval info: CONNECT: eq2 0 0 0 0 @eq 0 0 1 2 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_decode0.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_decode0.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_decode0.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_decode0.bsf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_decode0_inst.vhd TRUE -- Retrieval info: LIB_FILE: lpm
unlicense
bd125e70463995c26c6958b5fe24e9a8
0.641032
3.498769
false
false
false
false
OrganicMonkeyMotion/fpga_experiments
small_board/LABS/digital_logic/vhdl/lab2/part5/lpm_constant4.vhd
2
3,518
-- megafunction wizard: %LPM_CONSTANT% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: LPM_CONSTANT -- ============================================================ -- File Name: lpm_constant4.vhd -- Megafunction Name(s): -- LPM_CONSTANT -- -- Simulation Library Files(s): -- lpm -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition -- ************************************************************ --Copyright (C) 1991-2011 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.all; ENTITY lpm_constant4 IS PORT ( result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) ); END lpm_constant4; ARCHITECTURE SYN OF lpm_constant4 IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0); COMPONENT lpm_constant GENERIC ( lpm_cvalue : NATURAL; lpm_hint : STRING; lpm_type : STRING; lpm_width : NATURAL ); PORT ( result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) ); END COMPONENT; BEGIN result <= sub_wire0(0 DOWNTO 0); LPM_CONSTANT_component : LPM_CONSTANT GENERIC MAP ( lpm_cvalue => 0, lpm_hint => "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=cin", lpm_type => "LPM_CONSTANT", lpm_width => 1 ) PORT MAP ( result => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1" -- Retrieval info: PRIVATE: JTAG_ID STRING "cin" -- Retrieval info: PRIVATE: Radix NUMERIC "2" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: Value NUMERIC "0" -- Retrieval info: PRIVATE: nBit NUMERIC "1" -- Retrieval info: PRIVATE: new_diagram STRING "1" -- Retrieval info: LIBRARY: lpm lpm.lpm_components.all -- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0" -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=cin" -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1" -- Retrieval info: USED_PORT: result 0 0 1 0 OUTPUT NODEFVAL "result[0..0]" -- Retrieval info: CONNECT: result 0 0 1 0 @result 0 0 1 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4_inst.vhd FALSE -- Retrieval info: LIB_FILE: lpm
unlicense
0e7dc5b0ce97de181f55e4d7d79baca1
0.646958
3.819761
false
false
false
false
simonspa/pixel-dtb-firmware
dtb/ram_dq_INST_ka.vhd
2
7,075
-- megafunction wizard: %RAM: 1-PORT% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altsyncram -- ============================================================ -- File Name: ram_dq_INST_ka.vhd -- Megafunction Name(s): -- altsyncram -- -- Simulation Library Files(s): -- altera_mf -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version -- ************************************************************ --Copyright (C) 1991-2012 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY ram_dq_INST_ka IS PORT ( address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); clock : IN STD_LOGIC := '1'; data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); wren : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END ram_dq_INST_ka; ARCHITECTURE SYN OF ram_dq_inst_ka IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); COMPONENT altsyncram GENERIC ( clock_enable_input_a : STRING; clock_enable_output_a : STRING; intended_device_family : STRING; lpm_hint : STRING; lpm_type : STRING; numwords_a : NATURAL; operation_mode : STRING; outdata_aclr_a : STRING; outdata_reg_a : STRING; power_up_uninitialized : STRING; read_during_write_mode_port_a : STRING; widthad_a : NATURAL; width_a : NATURAL; width_byteena_a : NATURAL ); PORT ( address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); clock0 : IN STD_LOGIC ; data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); wren_a : IN STD_LOGIC ; q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT; BEGIN q <= sub_wire0(7 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( clock_enable_input_a => "BYPASS", clock_enable_output_a => "BYPASS", intended_device_family => "Cyclone III", lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=N_ka", lpm_type => "altsyncram", numwords_a => 256, operation_mode => "SINGLE_PORT", outdata_aclr_a => "NONE", outdata_reg_a => "CLOCK0", power_up_uninitialized => "FALSE", read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", widthad_a => 8, width_a => 8, width_byteena_a => 1 ) PORT MAP ( address_a => address, clock0 => clock, data_a => data, wren_a => wren, q_a => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" -- Retrieval info: PRIVATE: AclrByte NUMERIC "0" -- Retrieval info: PRIVATE: AclrData NUMERIC "0" -- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: Clken NUMERIC "0" -- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1" -- Retrieval info: PRIVATE: JTAG_ID STRING "N_ka" -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -- Retrieval info: PRIVATE: MIFfilename STRING "" -- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256" -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" -- Retrieval info: PRIVATE: RegData NUMERIC "1" -- Retrieval info: PRIVATE: RegOutput NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" -- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" -- Retrieval info: PRIVATE: WidthAddr NUMERIC "8" -- Retrieval info: PRIVATE: WidthData NUMERIC "8" -- Retrieval info: PRIVATE: rden NUMERIC "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=N_ka" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" -- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" -- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" -- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" -- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" -- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 -- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_ka.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_ka.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_ka.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_ka.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_ka_inst.vhd FALSE -- Retrieval info: LIB_FILE: altera_mf
unlicense
36e29e32b198704c4e0bfea5f7ea34d5
0.672085
3.439475
false
false
false
false
simonspa/pixel-dtb-firmware
dtb/I2C_ADN2816a.vhd
2
7,043
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity I2C_ADN2816a is port (clk_i : in std_logic; sub_i2c_i: in std_logic; reset_n_i : in std_logic; sda_o : out std_logic; sda_dir_o : out std_logic; sclen_o: out std_logic); end I2C_ADN2816a; architecture rtl of I2C_ADN2816a is type t_state is (waiting, send_START, send_A7, send_A6, send_A5, send_A4, send_A3, send_A2, send_A1, send_RW, read_A_ACK, send_SA7, send_SA6, send_SA5, send_SA4, send_SA3, send_SA2, send_SA1, send_SA0, read_SA_ACK, send_D7, send_D6, send_D5, send_D4, send_D3, send_D2, send_D1, send_D0, read_D_ACK, send_ACK, send_STOPCLK, send_STOP); signal s_state : t_state; signal s_sdadir : std_logic; -- Signal buffer for sdadir_o !! signal s_sda_response : std_logic; signal s_count : unsigned(3 downto 0); signal s_timeout: unsigned(4 downto 0); signal s_d_serin : std_logic_vector(7 downto 0); signal s_addrw : std_logic_vector(7 downto 0); signal s_nbytes : unsigned(7 downto 0); signal s_bytecount : unsigned(7 downto 0); signal s_rwq : std_logic; begin p_i2cmaster: process (clk_i, reset_n_i) begin -- process p_serin if (reset_n_i = '0') then -- asynchronous reset (active low) sda_dir_o <= '1'; sda_o <= '1'; sclen_o <= '0'; s_state <= waiting; elsif rising_edge(clk_i) then -- rising clock edge case s_state is when send_START => sda_dir_o <= '1'; sda_o <= '0'; s_state <= send_A7 ; ------------------------------------------------------------------------- when send_A7 => sclen_o <= '1'; sda_o <= '1'; s_state <= send_A6; ------------------------------------------------------------------------- when send_A6 => sda_o <= '1'; --sda_o <= '1'; old PCB version s_state <= send_A5; ------------------------------------------------------------------------- when send_A5 => sda_o <= '0'; s_state <= send_A4; ------------------------------------------------------------------------- when send_A4 => sda_o <= '0'; s_state <= send_A3; ------------------------------------------------------------------------- when send_A3 => sda_o <= '0'; s_state <= send_A2; ------------------------------------------------------------------------- when send_A2 => sda_o <= '0'; s_state <= send_A1; ------------------------------------------------------------------------- when send_A1 => sda_o <= '0'; s_state <= send_RW; ----------------------------------------------------------------------- when send_RW => sda_o <= '0'; s_state <= read_A_ACK; ------------------------------------------------------------------------- when read_A_ACK => sda_o <= '0'; sda_dir_o <= '0'; s_state <= send_SA7; ------------------------------------------------------------------------- when send_SA7 => sda_dir_o <= '1'; sda_o <= '0'; s_state <= send_SA6; ------------------------------------------------------------------------- when send_SA6 => sda_o <= '0'; s_state <= send_SA5; ------------------------------------------------------------------------- when send_SA5 => sda_o <= '0'; s_state <= send_SA4; ------------------------------------------------------------------------- when send_SA4 => sda_o <= '0'; s_state <= send_SA3; ------------------------------------------------------------------------- when send_SA3 => sda_o <= '1'; s_state <= send_SA2; ------------------------------------------------------------------------- when send_SA2 => sda_o <= '0'; s_state <= send_SA1; ------------------------------------------------------------------------- when send_SA1 => sda_o <= '0'; s_state <= send_SA0; ----------------------------------------------------------------------- when send_SA0 => sda_o <= '0'; s_state <= read_SA_ACK; ------------------------------------------------------------------------- when read_SA_ACK => sda_o <= '0'; sda_dir_o <= '0'; s_state <= send_D7; ------------------------------------------------------------------------- when send_D7 => sda_dir_o <= '1'; sda_o <= '1'; s_state <= send_D6; ------------------------------------------------------------------------- when send_D6 => sda_o <= '1'; s_state <= send_D5; ------------------------------------------------------------------------- when send_D5 => sda_o <= '0'; s_state <= send_D4; ------------------------------------------------------------------------- when send_D4 => sda_o <= '1'; s_state <= send_D3; ------------------------------------------------------------------------- when send_D3 => sda_o <= '0'; s_state <= send_D2; ------------------------------------------------------------------------- when send_D2 => sda_o <= '1'; s_state <= send_D1; ------------------------------------------------------------------------- when send_D1 => sda_o <= '0'; s_state <= send_D0; ------------------------------------------------------------------------- when send_D0 => sda_o <= '1'; s_state <= read_D_ACK; ------------------------------------------------------------------------- when read_D_ACK => sda_o <= '0'; sda_dir_o <= '0'; s_state <= send_STOPCLK; ------------------------------------------------------------------------- when send_STOPCLK => sda_dir_o <= '1'; sda_o <= '0'; sclen_o <= '0'; s_state <= send_STOP; ------------------------------------------------------------------------- when send_STOP => sda_o <= '1'; sclen_o <= '0'; s_state <= waiting; ------------------------------------------------------------------------- ------------------------------------------------------------------------- when others => if sub_i2c_i = '1' then -- VME Start I2C Cycle command detected. s_state <= send_START; end if; end case; end if; end process p_i2cmaster; end rtl;
unlicense
caacd38522cb732ff863fd3d18256d53
0.28184
4.474587
false
false
false
false
simonspa/pixel-dtb-firmware
dtb/simple_i2c.vhd
3
11,622
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity simple_i2c is port (clk_i : in std_logic; reset_n_i : in std_logic; sub_i2c_i : in std_logic; sda_i : in std_logic; scl_i: in std_logic; sda_o : out std_logic; ack_o : out std_logic; sdadir_o : out std_logic; sclen_o: out std_logic; addrw_i : in std_logic_vector(7 downto 0); data_i : in std_logic_vector(7 downto 0); nbytes_i : in unsigned(7 downto 0); pd_o : out std_logic_vector(7 downto 0); error_o : out std_logic_vector(7 downto 0); readen_o : out std_logic; next_b : out std_logic_vector(1 downto 0)); end simple_i2c; architecture rtl of simple_i2c is type t_state is (waiting, check_bus_busy, send_START, send_A7, send_A6, send_A5, send_A4, send_A3, send_A2, send_A1, send_RW, read_A_ACK, send_D7, send_D6, send_D5, send_D4, send_D3, send_D2, send_D1, send_D0, read_D_ACK, read_D7, read_D6, read_D5, read_D4, read_D3, read_D2, read_D1, read_D0, send_NOACK, send_ACK, restart_READ, restart_DATA, send_STOPCLKRD, send_STOPCLK, send_STOP, write_sda); signal s_state : t_state; signal s_sdadir : std_logic; -- Signal buffer for sdadir_o !! signal s_sda_response : std_logic; signal s_count : unsigned(3 downto 0); signal s_timeout: unsigned(4 downto 0); signal s_d_serin : std_logic_vector(7 downto 0); signal s_addrw : std_logic_vector(7 downto 0); signal s_nbytes : unsigned(7 downto 0); signal s_bytecount : unsigned(7 downto 0); signal s_rwq : std_logic; begin p_get_SDA: process (clk_i, reset_n_i) begin if (reset_n_i = '0') then s_sda_response <= '1'; elsif clk_i'EVENT AND clk_i = '0' then if ( s_sdadir= '0' AND sda_i = '0') then s_sda_response <= '0'; else s_sda_response <= '1'; end if; end if; ack_o <= s_sda_response; end process p_get_SDA; p_i2cmaster: process (clk_i, reset_n_i) begin -- process p_serin if (reset_n_i = '0') then -- asynchronous reset (active low) s_state <= waiting; s_count <= conv_unsigned(0,4); s_d_serin <= "00000000"; pd_o <= "00000000"; error_o <= "00000000"; sclen_o <= '0'; readen_o <= '0'; sda_o <= '1'; sdadir_o <= '0'; s_sdadir <= '0'; elsif rising_edge(clk_i) then -- rising clock edge case s_state is ------------------------------------------------------------------------- when check_bus_busy => if ( sda_i = '1' AND scl_i = '1' ) then -- bus is free s_state <= send_START; else -- bus isn't free s_timeout <= s_timeout - conv_unsigned(1,1); -- decrement s_timeout if (s_timeout = 0) then error_o <= "00000001"; s_state <= waiting; end if; end if; ------------------------------------------------------------------------- when send_START => sdadir_o <= '1'; s_sdadir <= '0'; sclen_o <= '1'; readen_o <= '0'; sda_o <= '0'; s_bytecount <= conv_unsigned(0,8); next_b <= CONV_STD_LOGIC_VECTOR(s_bytecount,2); s_state <= send_A7 ; ------------------------------------------------------------------------- when send_A7 => sda_o <= s_addrw(7); s_state <= send_A6; ------------------------------------------------------------------------- when send_A6 => sda_o <= s_addrw(6); s_state <= send_A5; ------------------------------------------------------------------------- when send_A5 => sda_o <= s_addrw(5); s_state <= send_A4; ------------------------------------------------------------------------- when send_A4 => sda_o <= s_addrw(4); s_state <= send_A3; ------------------------------------------------------------------------- when send_A3 => sda_o <= s_addrw(3); s_state <= send_A2; ------------------------------------------------------------------------- when send_A2 => sda_o <= s_addrw(2); s_state <= send_A1; ------------------------------------------------------------------------- when send_A1 => sda_o <= s_addrw(1); s_state <= send_RW; ----------------------------------------------------------------------- when send_RW => sda_o <= s_addrw(0); s_state <= read_A_ACK; ------------------------------------------------------------------------- when read_A_ACK => sda_o <= '0'; sdadir_o <= '0'; s_sdadir <= '0'; s_state <= send_D7; if ( s_rwq = '1') then -- read s_state <= read_D7; else -- write s_state <= send_D7; end if; ------------------------------------------------------------------------- when send_D7 => sdadir_o <= '1'; s_sdadir <= '0'; if(s_sda_response = '0') then -- ADDRESS acknowledged sda_o <= data_i(7); s_state <= send_D6; else -- A_ACK ERROR error_o <= "00000010"; sda_o <= '1'; sclen_o <= '0'; s_state <= waiting; end if; ------------------------------------------------------------------------- when send_D6 => sda_o <= data_i(6); s_bytecount <= s_bytecount + conv_unsigned(1,8); s_state <= send_D5; ------------------------------------------------------------------------- when send_D5 => sda_o <= data_i(5); s_state <= send_D4; ------------------------------------------------------------------------- when send_D4 => sda_o <= data_i(4); s_state <= send_D3; ------------------------------------------------------------------------- when send_D3 => sda_o <= data_i(3); s_state <= send_D2; ------------------------------------------------------------------------- when send_D2 => sda_o <= data_i(2); s_state <= send_D1; ------------------------------------------------------------------------- when send_D1 => sda_o <= data_i(1); s_state <= send_D0; ----------------------------------------------------------------------- when send_D0 => sda_o <= data_i(0); s_state <= read_D_ACK; ------------------------------------------------------------------------- when read_D_ACK => sda_o <= '0'; sdadir_o <= '0'; s_sdadir <= '0'; if(s_nbytes = s_bytecount) then s_state <= send_STOPCLK; else s_state <= restart_DATA; next_b <= CONV_STD_LOGIC_VECTOR(s_bytecount,2); end if; ------------------------------------------------------------------------- when read_D7 => if(s_sda_response = '0') then -- ADDRESS acknowledged s_state <= read_D6; else -- A_ACK ERROR sdadir_o <= '1'; s_sdadir <= '0'; error_o <= "00000010"; sda_o <= '1'; sclen_o <= '0'; s_state <= waiting; end if; ------------------------------------------------------------------------- when read_D6 => readen_o <= '0'; s_d_serin(7)<= s_sda_response; s_bytecount <= s_bytecount + conv_unsigned(1,8); next_b <= CONV_STD_LOGIC_VECTOR(s_bytecount,2); s_state <= read_D5; ------------------------------------------------------------------------- when read_D5 => s_d_serin(6)<= s_sda_response; s_state <= read_D4; ------------------------------------------------------------------------- when read_D4 => s_d_serin(5)<= s_sda_response; s_state <= read_D3; ------------------------------------------------------------------------- when read_D3 => s_d_serin(4)<=s_sda_response; s_state <= read_D2; ------------------------------------------------------------------------- when read_D2 => s_d_serin(3)<= s_sda_response; s_state <= read_D1; ------------------------------------------------------------------------- when read_D1 => s_d_serin(2)<= s_sda_response; s_state <= read_D0; ------------------------------------------------------------------------- when read_D0 => s_d_serin(1)<= s_sda_response; if(s_nbytes = s_bytecount) then s_state <= send_NOACK; else s_state <= send_ACK; end if; ------------------------------------------------------------------------- when send_NOACK => s_d_serin(0)<= s_sda_response; sdadir_o <= '1'; s_sdadir <= '1'; sda_o <= '1'; -- NOACK BY MASTER s_state <= send_STOPCLKRD; ------------------------------------------------------------------------- when send_ACK => s_d_serin(0)<= s_sda_response; sdadir_o <= '1'; s_sdadir <= '1'; sda_o <= '0'; -- DTACK by Master s_state <= restart_READ; ------------------------------------------------------------------------- when restart_READ => sdadir_o <= '0'; s_sdadir <= '0'; readen_o <= '1'; pd_o <= s_d_serin; s_d_serin(7)<= s_sda_response; s_state <= read_D6; ------------------------------------------------------------------------- when restart_DATA => if(s_sda_response = '0') then -- DATA acknowledged sdadir_o <= '1'; s_sdadir <= '1'; sda_o <= data_i(7); s_state <= send_D6; else -- D_ACK ERROR error_o <= "00000100"; s_state <= send_STOP; end if; ------------------------------------------------------------------------- when send_STOPCLKRD => sda_o <= '0'; sclen_o <= '0'; readen_o <= '1'; pd_o <= s_d_serin; s_state <= send_STOP; ------------------------------------------------------------------------- when send_STOPCLK => sda_o <= '0'; sclen_o <= '0'; if(s_sda_response = '0') then -- DATA acknowledged s_state <= send_STOP; else -- D_ACK ERROR error_o <= "00000100"; s_state <= send_STOP; end if; ------------------------------------------------------------------------- when send_STOP => sda_o <= '1'; sclen_o <= '0'; readen_o <= '0'; s_state <= waiting; ------------------------------------------------------------------------- ------------------------------------------------------------------------- when others => if sub_i2c_i = '1' then -- VME Start I2C Cycle command detected. s_addrw <= addrw_i; s_nbytes <= nbytes_i; s_rwq <= addrw_i(0); s_state <= check_bus_busy; -- Initialize input counter s_timeout <= conv_unsigned(10,5); end if; end case; end if; end process p_i2cmaster; end rtl;
unlicense
03ee1a0f60dd149104c21351862215c3
0.344175
4.043841
false
false
false
false
systec-dk/openPOWERLINK_systec
Examples/ipcore/xilinx/openmac/src/openMAC_DMAFifo.vhd
3
6,044
------------------------------------------------------------------------------- -- Entity : OpenMAC_DMAFifo_Xilinx ------------------------------------------------------------------------------- -- -- (c) B&R, 2012 -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity openMAC_DMAfifo is generic( fifo_data_width_g : NATURAL := 16; fifo_word_size_g : NATURAL := 32; fifo_word_size_log2_g : NATURAL := 5 ); port( aclr : in std_logic; rd_clk : in std_logic; rd_req : in std_logic; wr_clk : in std_logic; wr_req : in std_logic; wr_data : in std_logic_vector(fifo_data_width_g - 1 downto 0); rd_empty : out std_logic; rd_full : out std_logic; wr_empty : out std_logic; wr_full : out std_logic; rd_data : out std_logic_vector(fifo_data_width_g - 1 downto 0); rd_usedw : out std_logic_vector(fifo_word_size_log2_g - 1 downto 0); wr_usedw : out std_logic_vector(fifo_word_size_log2_g - 1 downto 0) ); end openMAC_DMAfifo; architecture struct of openMAC_DMAfifo is ---- Component declarations ----- component async_fifo_ctrl generic( ADDR_WIDTH : natural := 5 ); port ( clkr : in std_logic; clkw : in std_logic; rd : in std_logic; resetr : in std_logic; resetw : in std_logic; wr : in std_logic; r_addr : out std_logic_vector(ADDR_WIDTH-1 downto 0); r_empty : out std_logic; r_full : out std_logic; rd_used_w : out std_logic_vector(ADDR_WIDTH-1 downto 0); w_addr : out std_logic_vector(ADDR_WIDTH-1 downto 0); w_empty : out std_logic; w_full : out std_logic; wd_used_w : out std_logic_vector(ADDR_WIDTH-1 downto 0) ); end component; component dc_dpr generic( ADDRWIDTH : integer := 7; WIDTH : integer := 16 ); port ( addrA : in std_logic_vector(ADDRWIDTH-1 downto 0); addrB : in std_logic_vector(ADDRWIDTH-1 downto 0); clkA : in std_logic; clkB : in std_logic; diA : in std_logic_vector(WIDTH-1 downto 0); diB : in std_logic_vector(WIDTH-1 downto 0); enA : in std_logic; enB : in std_logic; weA : in std_logic; weB : in std_logic; doA : out std_logic_vector(WIDTH-1 downto 0); doB : out std_logic_vector(WIDTH-1 downto 0) ); end component; ---- Signal declarations used on the diagram ---- signal enA : std_logic; signal enB : std_logic; signal wea : std_logic; signal weB : std_logic; signal wr_full_s : std_logic; signal diB : std_logic_vector (fifo_data_width_g-1 downto 0); signal rd_addr : std_logic_vector (fifo_word_size_log2_g-1 downto 0); signal wr_addr : std_logic_vector (fifo_word_size_log2_g-1 downto 0); begin ---- User Signal Assignments ---- --assignments ---port a writes only enA <= wea; ---port b reads only enB <= rd_req; weB <= '0'; diB <= (others => '0'); ---- Component instantiations ---- THE_FIFO_CONTROL : async_fifo_ctrl generic map ( ADDR_WIDTH => fifo_word_size_log2_g ) port map( clkr => rd_clk, clkw => wr_clk, r_addr => rd_addr( fifo_word_size_log2_g-1 downto 0 ), r_empty => rd_empty, r_full => rd_full, rd => rd_req, rd_used_w => rd_usedw( fifo_word_size_log2_g - 1 downto 0 ), resetr => aclr, resetw => aclr, w_addr => wr_addr( fifo_word_size_log2_g-1 downto 0 ), w_empty => wr_empty, w_full => wr_full_s, wd_used_w => wr_usedw( fifo_word_size_log2_g - 1 downto 0 ), wr => wr_req ); THE_FIFO_DPR : dc_dpr generic map ( ADDRWIDTH => fifo_word_size_log2_g, WIDTH => fifo_data_width_g ) port map( addrA => wr_addr( fifo_word_size_log2_g-1 downto 0 ), addrB => rd_addr( fifo_word_size_log2_g-1 downto 0 ), clkA => wr_clk, clkB => rd_clk, diA => wr_data( fifo_data_width_g - 1 downto 0 ), diB => diB( fifo_data_width_g-1 downto 0 ), doB => rd_data( fifo_data_width_g - 1 downto 0 ), enA => enA, enB => enB, weA => wea, weB => weB ); wea <= not(wr_full_s) and wr_req; ---- Terminal assignment ---- -- Output\buffer terminals wr_full <= wr_full_s; end struct;
gpl-2.0
3134985f9718a1096fc8600679cd5989
0.599107
3.555294
false
false
false
false
amethystek/VHDL_SPACE_INVADER
missile.vhd
1
2,436
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity missile is port(MOVE_CLK :in std_logic; HCount :in std_logic_vector(10 downto 0); VCount :in std_logic_vector(10 downto 0); MISSILE_BUTTON:in std_logic; ALIEN_HIT :in std_logic_vector(2 downto 0); PLAYER_POS_H :in std_logic_vector(10 downto 0);--get from player MISSILE_OUT :out std_logic;--send to alien MISSILE_POS_H :out std_logic_vector(10 downto 0);--send to alien MISSILE_POS_V :out std_logic_vector(10 downto 0);--send to alien VGA_MISSILE_EN:out std_logic);--whether show on screen end missile; architecture behave of missile is signal MPOS_H :std_logic_vector(10 downto 0):="00000000000"; signal MPOS_V :std_logic_vector(10 downto 0):="01000100101"; signal missile_en:std_logic:='0'; signal OUT_POS_V :std_logic_vector(10 downto 0); constant MISSILE_HEIGHT:integer:= 16; constant MISSILE_WIDTH :integer:= 4; begin MISSILE_OUT<=missile_en; MISSILE_POS_H<=MPOS_H; MISSILE_POS_V<=MPOS_V; ------------------------------------------------- MOVEMENT:process(MOVE_CLK)--calculate the movement of alien begin if (rising_edge(MOVE_CLK))then--the movement of missile and process of out of range if(missile_en='1')then if(VCount<MPOS_V or VCount>(MPOS_V+MISSILE_HEIGHT))then --make sure the missile will not change it position while scan its area if(MPOS_V>200)then MPOS_V<=MPOS_V-8; MPOS_H<=OUT_POS_V+10; end if; end if; elsif(missile_en='0')then MPOS_V<="01000100101"; end if; end if; end process MOVEMENT; RESET:process(MPOS_V,MISSILE_BUTTON,ALIEN_HIT) begin if(missile_en='1')then if(MPOS_V<200)then missile_en<='0'; elsif(ALIEN_HIT(0)='1' or ALIEN_HIT(1)='1' or ALIEN_HIT(2)='1')then--if any alien has been hit missile_en<='0'; end if; elsif missile_en='0' then if(MISSILE_BUTTON='0')then--if the button of missile be pressed OUT_POS_V<=PLAYER_POS_H; missile_en<='1'; end if; end if; end process RESET; ------------------------------------------------ MISSILE_SHOW:process(HCount,VCount) begin vga_missile_en<='0'; if(MISSILE_EN='1')then if(VCount>(MPOS_V-1) and VCount<(MPOS_V+MISSILE_HEIGHT+1))then if(HCount>(MPOS_H-1) and HCount<(MPOS_H+MISSILE_WIDTH+1))then vga_missile_en<='1'; end if; end if; end if; end process MISSILE_SHOW; end behave;
bsd-2-clause
6150672f554d4a0a19f56443b1d77c87
0.655583
3.131105
false
false
false
false
scottlbaker/PDP11-SOC
src/alu.vhd
1
14,197
--======================================================================== -- alu.vhd :: PDP-11 16-bit ALU -- -- (c) Scott L. Baker, Sierra Circuit Design --======================================================================== library IEEE; use IEEE.std_logic_1164.all; use work.my_types.all; entity ALU is port ( COUT : out std_logic; -- carry out ZERO : out std_logic; -- zero OVFL : out std_logic; -- overflow SIGN : out std_logic; -- sign bit RBUS : out std_logic_vector(15 downto 0); -- result bus A : in std_logic_vector(15 downto 0); -- operand A B : in std_logic_vector(15 downto 0); -- operand B OP : in ALU_OP_TYPE; -- micro op BYTE_OP : in std_logic; -- 1=byte/0=word DIV_OP : in std_logic; -- divide op DIV_SBIT : in std_logic; -- divide sign bit CIN : in std_logic -- carry in ); end ALU; architecture BEHAVIORAL of ALU is --================================================================= -- Types, component, and signal definitions --================================================================= --================================================================= -- A input mux selects (buffer, invert, or supply a constant) --================================================================= type AMUX_SEL_TYPE is ( ALL_ZERO, -- all zeros SWAP, -- swap bytes BUF, -- buffer INV -- invert ); --================================================================= -- B input mux selects (buffer, invert, or supply a constant) --================================================================= type BMUX_SEL_TYPE is ( ALL_ZERO, -- all zeros TWO, -- two MINUS1, -- all ones MINUS2, -- minus two BUF, -- buffer INV -- invert ); --================================================================= -- Ouput mux selects ( xor, or, and, shift, or sum) --================================================================= type OMUX_SEL_TYPE is ( SEL_XOR, -- logical xor SEL_OR, -- logical or SEL_AND, -- logical and SEL_SUM, -- arithmetic sum SEL_ASL, -- arithmetic shift left SEL_ASR, -- arithmetic shift right SEL_LSR, -- logical shift right SEL_ROR -- rotate right ); -- ALU mux selects signal ASEL : AMUX_SEL_TYPE; signal BSEL : BMUX_SEL_TYPE; signal RSEL : OMUX_SEL_TYPE; -- ALU busses signal AX : std_logic_vector(16 downto 0); signal BX : std_logic_vector(16 downto 0); signal AXB : std_logic_vector(16 downto 0); signal SUM : std_logic_vector(16 downto 0); signal RBI : std_logic_vector(15 downto 0); -- propagate and generate signal P : std_logic_vector(15 downto 0); signal G : std_logic_vector(15 downto 0); -- flags signal V : std_logic; -- overflow signal Z : std_logic; -- zero signal N : std_logic; -- sign bit -- internal carries signal CO : std_logic; signal CIN1 : std_logic; signal CX : std_logic_vector(16 downto 0); -- misc signal ASE : std_logic_vector(8 downto 0); signal BSE : std_logic_vector(8 downto 0); begin --================================================================ -- Start of the behavioral description --================================================================ --==================== -- Opcode Decoding --==================== OPCODE_DECODING: process(OP, CIN) begin -- Default values ASEL <= BUF; BSEL <= BUF; RSEL <= SEL_SUM; CIN1 <= '0'; case OP is when OP_ADD => -- A plus B when OP_ADC => -- A plus Cin BSEL <= ALL_ZERO; CIN1 <= CIN; when OP_SUBB => -- A minus B BSEL <= INV; CIN1 <= '1'; when OP_SUBA => -- B minus A ASEL <= INV; CIN1 <= '1'; when OP_SBC => -- A minus CIN BSEL <= MINUS1; CIN1 <= not CIN; when OP_INCA1 => -- increment A BSEL <= ALL_ZERO; CIN1 <= '1'; when OP_INCA2 => -- increment A by 2 BSEL <= TWO; CIN1 <= '0'; when OP_DECA1 => -- decrement A BSEL <= MINUS1; when OP_DECA2 => -- decrement A by 2 BSEL <= MINUS2; when OP_INV => -- 1's complement A ASEL <= INV; BSEL <= ALL_ZERO; RSEL <= SEL_OR; when OP_NEG => -- 2's complement A ASEL <= INV; BSEL <= ALL_ZERO; CIN1 <= '1'; when OP_AND => -- A and B RSEL <= SEL_AND; when OP_BIC => -- not A and B ASEL <= INV; RSEL <= SEL_AND; when OP_CZC => -- A and not B BSEL <= INV; RSEL <= SEL_AND; when OP_SZC => -- not A and B ASEL <= INV; RSEL <= SEL_AND; when OP_OR => -- A or B RSEL <= SEL_OR; when OP_XOR => -- A xor B RSEL <= SEL_XOR; when OP_TA => -- transfer A BSEL <= ALL_ZERO; RSEL <= SEL_OR; when OP_TB => -- transfer B ASEL <= ALL_ZERO; RSEL <= SEL_OR; when OP_SWP => -- swap bytes of A BSEL <= ALL_ZERO; ASEL <= SWAP; RSEL <= SEL_OR; when OP_ASL => -- arithmetic shift left A BSEL <= ALL_ZERO; RSEL <= SEL_ASL; when OP_LSR => -- logical shift right A BSEL <= ALL_ZERO; RSEL <= SEL_LSR; when OP_ASR => -- logical shift right A BSEL <= ALL_ZERO; RSEL <= SEL_ASR; when OP_ROR => -- rotate right A BSEL <= ALL_ZERO; RSEL <= SEL_ROR; when OP_ONES => -- output all ones ASEL <= ALL_ZERO; BSEL <= MINUS1; RSEL <= SEL_OR; when others => -- output all zeros ASEL <= ALL_ZERO; BSEL <= ALL_ZERO; RSEL <= SEL_OR; end case; end process; BSE <= (others => B(7)); ASE <= (others => A(7)); --========================= -- Operand A mux --========================= OPERAND_A_MUX: process(ASEL, A, ASE, BYTE_OP) begin case ASEL is when BUF => -- A AX <= A(15) & A; if (BYTE_OP = '1') then AX <= ASE & A(7 downto 0); end if; when INV => -- not A AX <= not (A(15) & A); if (BYTE_OP = '1') then AX <= not (ASE & A(7 downto 0)); end if; when SWAP => -- swap bytes AX <= '0' & A(7 downto 0) & A(15 downto 8); when others => -- zero AX <= (others => '0'); end case; end process; --========================= -- Operand B mux --========================= OPERAND_B_MUX: process(BSEL, B, BSE, BYTE_OP, DIV_OP, DIV_SBIT) begin case BSEL is when MINUS1 => -- for decrement BX <= (others => '1'); when MINUS2 => -- for decrement by 2 BX <= "11111111111111110"; when TWO => -- for increment by 2 BX <= "00000000000000010"; when BUF => -- B BX <= B(15) & B; if (BYTE_OP = '1') then BX <= BSE & B(7 downto 0); end if; if (DIV_OP = '1') then BX <= (DIV_SBIT or B(15)) & B; end if; when INV => -- not B BX <= not(B(15) & B); if (BYTE_OP = '1') then BX <= not (BSE & B(7 downto 0)); end if; when others => -- zero BX <= (others => '0'); end case; end process; --================================================ -- ALU output mux --================================================ ALU_OUTPUT_MUX: process(RSEL, AXB, SUM, B, P, G, CX, BYTE_OP, DIV_OP, DIV_SBIT) begin case RSEL is when SEL_ASL => -- arithmetic shift left RBI <= P(14 downto 0) & '0'; CO <= P(15); when SEL_LSR => -- logical shift right RBI <= '0' & P(15 downto 1); CO <= P(0); when SEL_ASR => -- arithmetic shift right RBI <= P(15) & P(15 downto 1); CO <= P(0); when SEL_ROR => -- right rotate RBI <= P(0) & P(15 downto 1); CO <= P(0); when SEL_XOR => -- A xor B RBI <= AXB(15 downto 0); CO <= P(15); when SEL_OR => -- A or B RBI <= P(15 downto 0); CO <= P(15); when SEL_AND => -- A and B RBI <= G(15 downto 0); CO <= P(15); when others => -- Arithmetic ops RBI <= SUM(15 downto 0); CO <= CX(16); end case; -- for byte operations if (BYTE_OP = '1') then CO <= CX(8); end if; -- for divide if (DIV_OP = '1') then CO <= CX(16) or DIV_SBIT; end if; end process; RBUS <= RBI; --===================================== -- Propagate and Generate --===================================== G <= AX(15 downto 0) and BX(15 downto 0); P <= AX(15 downto 0) or BX(15 downto 0); --===================================== -- carry look-ahead logic --===================================== CX(16) <= G(15) or (P(15) and CX(15)); CX(15) <= G(14) or (P(14) and CX(14)); CX(14) <= G(13) or (P(13) and CX(13)); CX(13) <= G(12) or (P(12) and CX(12)); CX(12) <= G(11) or (P(11) and CX(11)); CX(11) <= G(10) or (P(10) and CX(10)); CX(10) <= G(9) or (P(9) and CX(9)); CX(9) <= G(8) or (P(8) and CX(8)); CX(8) <= G(7) or (P(7) and CX(7)); CX(7) <= G(6) or (P(6) and CX(6)); CX(6) <= G(5) or (P(5) and CX(5)); CX(5) <= G(4) or (P(4) and CX(4)); CX(4) <= G(3) or (P(3) and CX(3)); CX(3) <= G(2) or (P(2) and CX(2)); CX(2) <= G(1) or (P(1) and CX(1)); CX(1) <= G(0) or (P(0) and CX(0)); CX(0) <= CIN1; --========================= -- ALU SUM --========================= AXB <= AX xor BX; SUM <= CX xor AXB; --========================= -- Overflow flag --========================= OVERFLOW_FLAG: process(BYTE_OP, A, RSEL, SUM) begin V <= '0'; if (RSEL = SEL_SUM) then V <= SUM(16) xor SUM(15); if (BYTE_OP = '1') then V <= SUM(8) xor SUM(7); end if; end if; -- for left shifts set when sign changes if (RSEL = SEL_ASL) then V <= A(15) xor SUM(14); end if; end process; --========================= -- Zero flag --========================= ZERO_FLAG: process(BYTE_OP, RBI) begin Z <= (not(RBI(15) or RBI(14) or RBI(13) or RBI(12) or RBI(11) or RBI(10) or RBI(9) or RBI(8) or RBI(7) or RBI(6) or RBI(5) or RBI(4) or RBI(3) or RBI(2) or RBI(1) or RBI(0))); if (BYTE_OP = '1') then Z <= (not(RBI(7) or RBI(6) or RBI(5) or RBI(4) or RBI(3) or RBI(2) or RBI(1) or RBI(0))); end if; end process; --========================= -- Sign-bit Flag --========================= SIGN_FLAG: process(BYTE_OP, RBI) begin N <= RBI(15); if (BYTE_OP = '1') then N <= RBI(7); end if; end process; --========================= -- Flags --========================= -- zero ZERO <= Z; -- carry out COUT <= CO; -- overflow OVFL <= V; -- sign SIGN <= N; end BEHAVIORAL;
gpl-3.0
f3fcfc6f232cf98a5eca1397347749df
0.32845
4.433791
false
false
false
false
simonspa/pixel-dtb-firmware
dtb/lpm_mux1.vhd
2
5,446
-- megafunction wizard: %LPM_MUX% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: LPM_MUX -- ============================================================ -- File Name: lpm_mux1.vhd -- Megafunction Name(s): -- LPM_MUX -- -- Simulation Library Files(s): -- lpm -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version -- ************************************************************ --Copyright (C) 1991-2012 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.lpm_components.all; ENTITY lpm_mux1 IS PORT ( clock : IN STD_LOGIC ; data0 : IN STD_LOGIC ; data1 : IN STD_LOGIC ; data2 : IN STD_LOGIC ; data3 : IN STD_LOGIC ; data4 : IN STD_LOGIC ; data5 : IN STD_LOGIC ; data6 : IN STD_LOGIC ; data7 : IN STD_LOGIC ; sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0); result : OUT STD_LOGIC ); END lpm_mux1; ARCHITECTURE SYN OF lpm_mux1 IS -- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC ; SIGNAL sub_wire2 : STD_LOGIC ; SIGNAL sub_wire3 : STD_LOGIC_2D (7 DOWNTO 0, 0 DOWNTO 0); SIGNAL sub_wire4 : STD_LOGIC ; SIGNAL sub_wire5 : STD_LOGIC ; SIGNAL sub_wire6 : STD_LOGIC ; SIGNAL sub_wire7 : STD_LOGIC ; SIGNAL sub_wire8 : STD_LOGIC ; SIGNAL sub_wire9 : STD_LOGIC ; SIGNAL sub_wire10 : STD_LOGIC ; BEGIN sub_wire10 <= data0; sub_wire9 <= data1; sub_wire8 <= data2; sub_wire7 <= data3; sub_wire6 <= data4; sub_wire5 <= data5; sub_wire4 <= data6; sub_wire1 <= sub_wire0(0); result <= sub_wire1; sub_wire2 <= data7; sub_wire3(7, 0) <= sub_wire2; sub_wire3(6, 0) <= sub_wire4; sub_wire3(5, 0) <= sub_wire5; sub_wire3(4, 0) <= sub_wire6; sub_wire3(3, 0) <= sub_wire7; sub_wire3(2, 0) <= sub_wire8; sub_wire3(1, 0) <= sub_wire9; sub_wire3(0, 0) <= sub_wire10; LPM_MUX_component : LPM_MUX GENERIC MAP ( lpm_pipeline => 1, lpm_size => 8, lpm_type => "LPM_MUX", lpm_width => 1, lpm_widths => 3 ) PORT MAP ( clock => clock, data => sub_wire3, sel => sel, result => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: new_diagram STRING "1" -- Retrieval info: LIBRARY: lpm lpm.lpm_components.all -- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1" -- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "8" -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1" -- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "3" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" -- Retrieval info: USED_PORT: data0 0 0 0 0 INPUT NODEFVAL "data0" -- Retrieval info: USED_PORT: data1 0 0 0 0 INPUT NODEFVAL "data1" -- Retrieval info: USED_PORT: data2 0 0 0 0 INPUT NODEFVAL "data2" -- Retrieval info: USED_PORT: data3 0 0 0 0 INPUT NODEFVAL "data3" -- Retrieval info: USED_PORT: data4 0 0 0 0 INPUT NODEFVAL "data4" -- Retrieval info: USED_PORT: data5 0 0 0 0 INPUT NODEFVAL "data5" -- Retrieval info: USED_PORT: data6 0 0 0 0 INPUT NODEFVAL "data6" -- Retrieval info: USED_PORT: data7 0 0 0 0 INPUT NODEFVAL "data7" -- Retrieval info: USED_PORT: result 0 0 0 0 OUTPUT NODEFVAL "result" -- Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL "sel[2..0]" -- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: @data 1 0 1 0 data0 0 0 0 0 -- Retrieval info: CONNECT: @data 1 1 1 0 data1 0 0 0 0 -- Retrieval info: CONNECT: @data 1 2 1 0 data2 0 0 0 0 -- Retrieval info: CONNECT: @data 1 3 1 0 data3 0 0 0 0 -- Retrieval info: CONNECT: @data 1 4 1 0 data4 0 0 0 0 -- Retrieval info: CONNECT: @data 1 5 1 0 data5 0 0 0 0 -- Retrieval info: CONNECT: @data 1 6 1 0 data6 0 0 0 0 -- Retrieval info: CONNECT: @data 1 7 1 0 data7 0 0 0 0 -- Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0 -- Retrieval info: CONNECT: result 0 0 0 0 @result 0 0 1 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.bsf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1_inst.vhd FALSE -- Retrieval info: LIB_FILE: lpm
unlicense
3b11aa7961d4a9b3f175f5d9a958c08c
0.63588
3.169965
false
false
false
false
OrganicMonkeyMotion/fpga_experiments
small_board/LABS/digital_logic/vhdl/lab2/part2/circuita.vhd
1
383
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY circuita IS -- PORT ( INPUT : IN STD_LOGIC_VECTOR (2 DOWNTO 0); -- (2)=A, (1)=B, (0)=C OUTPUT : OUT STD_LOGIC_VECTOR (2 DOWNTO 0) -- F0, F1, F2 ); END circuita; ARCHITECTURE Behavior OF circuita IS BEGIN OUTPUT(0) <= INPUT(0); OUTPUT(1) <= NOT INPUT(1); OUTPUT(2) <= INPUT(2) OR INPUT(1); END Behavior;
unlicense
ccf556fba70f40ddf83e711a9566d917
0.610966
2.641379
false
false
false
false
OrganicMonkeyMotion/fpga_experiments
small_board/LABS/digital_logic/vhdl/lab2/part2/comparator.vhd
1
350
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY comparator IS PORT ( INPUT : IN STD_LOGIC_VECTOR (3 DOWNTO 0); -- (3)=A, (2)=B, (1)=C, (0)=D OUTPUT : OUT STD_LOGIC -- F0, F1, F2 ); END comparator; ARCHITECTURE Behaviour OF comparator IS BEGIN OUTPUT <= (NOT INPUT(3) AND NOT INPUT(1)) OR (NOT INPUT(3) AND NOT INPUT(2)); END Behaviour;
unlicense
e0b2a3cf4d7439a6530e048ede4ff4b5
0.657143
2.868852
false
false
false
false
OrganicMonkeyMotion/fpga_experiments
small_board/LABS/digital_logic/vhdl/lab2/part6/segseven.vhd
1
1,724
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY segseven IS PORT (SW : IN STD_LOGIC_VECTOR (3 DOWNTO 0); -- (3)=A, (2)=B, (1)=C, (0)=D LEDSEG : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) ); END segseven; ARCHITECTURE Behavior OF segseven IS BEGIN -- SEG A : In3' In2' In1' In0 + In2 In1' In0' + In3 In1 + In3 In2; LEDSEG(0) <= (NOT SW(3) AND NOT SW(2) AND NOT SW(1) AND SW(0)) OR (SW(2) AND NOT SW(1) AND NOT SW(0)) OR (SW(3) AND SW(1)) OR (SW(3) AND SW(2)); -- SEG B : In2 In1' In0 + In3 In1 + In2 In1 In0' + In3 In2; LEDSEG(1) <= (SW(2) AND NOT SW(1) AND SW(0)) OR (SW(3) AND SW(1)) OR (SW(2) AND SW(1) AND NOT SW(0)) OR (SW(3) AND SW(2)); -- SEG C : In2' In1 In0' + In3 In2 + In3 In1; LEDSEG(2) <= (NOT SW(2) AND SW(1) AND NOT SW(0)) OR (SW(3) AND SW(2)) OR (SW(3) AND SW(1)); -- SEG D : In3 In0 + In2 In1' In0' + In2' In1' In0 + In3 In1 + In2 In1 In0; LEDSEG(3) <= (SW(3) AND SW(0)) OR (SW(2) AND NOT SW(1) AND NOT SW(0)) OR (NOT SW(2) AND NOT SW(1) AND SW(0)) OR (SW(2) AND SW(1) AND SW(0)) OR (SW(3) AND SW(1)); -- SEG E : In2 In1' + In3 In1 + In0; LEDSEG(4) <= (SW(3) AND SW(1)) OR (SW(2) AND NOT SW(1)) OR (SW(0)); -- SEG F : In3 In2 + In3' In2' In0 + In2' In1 + In1 In0; LEDSEG(5) <= (NOT SW(3) AND NOT SW(2) AND SW(0)) OR (SW(3) AND SW(2)) OR (NOT SW(2) AND SW(1)) OR (SW(1) AND SW(0)); -- SED G : In3' In2' In1' + In2 In1 In0 + In3 In2 + In3 In1; LEDSEG(6) <= (NOT SW(3) AND NOT SW(2) AND NOT SW(1)) OR (SW(2) AND SW(1) AND SW(0)) OR (SW(3) AND SW(1)) OR (SW(3) AND SW(2)); END Behavior;
unlicense
c4ae9a2ab013ad6a74011fd3eaca47fb
0.49768
2.301736
false
false
false
false
OrganicMonkeyMotion/fpga_experiments
small_board/LABS/digital_logic/vhdl/lab2/part5/part4_code.vhd
2
1,807
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY part4_code IS PORT( BUTTONS : IN STD_LOGIC_VECTOR (3 DOWNTO 0); CONSTANTS : IN STD_LOGIC_VECTOR (3 DOWNTO 0); LED : OUT STD_LOGIC_VECTOR (6 DOWNTO 0); DISP: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); clk_in : IN STD_LOGIC; carry_in : IN STD_LOGIC; carry_out : OUT STD_LOGIC ); END part4_code; ARCHITECTURE Behaviour of part4_code IS SIGNAL carry : STD_LOGIC; SIGNAL HEX_0, HEX_1, BLANK: STD_LOGIC_VECTOR (6 DOWNTO 0); SIGNAL s_o : STD_LOGIC_VECTOR (3 DOWNTO 0); COMPONENT segseven PORT ( SW : IN STD_LOGIC_VECTOR (3 DOWNTO 0); LEDSEG : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)); END COMPONENT; COMPONENT circuitb PORT ( SW : IN STD_LOGIC; LEDSEG : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)); END COMPONENT; COMPONENT DE1_disp PORT ( HEX0, HEX1, HEX2, HEX3 : IN STD_LOGIC_VECTOR(6 DOWNTO 0); clk : IN STD_LOGIC; HEX : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); DISPn: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END COMPONENT; COMPONENT bcd_adder PORT (b_in : IN STD_LOGIC_VECTOR (3 DOWNTO 0); a_in : IN STD_LOGIC_VECTOR (3 DOWNTO 0); c_in : IN STD_LOGIC; c_out : OUT STD_LOGIC; s_out : OUT STD_LOGIC_VECTOR (3 DOWNTO 0));END COMPONENT; BEGIN BLANK <= "1111111"; S0 : segseven PORT MAP (SW=>s_o, LEDSEG=>HEX_0); S1 : circuitb PORT MAP (SW=>carry, LEDSEG=>HEX_1); DE1: DE1_disp PORT MAP (HEX0=>HEX_0, HEX1=>HEX_1, HEX2=>BLANK, HEX3=>BLANK, clk=>clk_in,HEX=>LED,DISPn=>DISP); badder: bcd_adder PORT MAP (b_in=> NOT BUTTONS, a_in => CONSTANTS, c_in =>carry_in, c_out=> carry, s_out => s_o); carry_out <= carry; END Behaviour;
unlicense
48717743ebfb16ae341db5e0e3cab43d
0.590481
3.164623
false
false
false
false
notti/dis_lu
vhdl/rotkey.vhd
1
1,431
library ieee; use ieee.std_logic_1164.all; entity rotKey is generic( CNT : integer := 5000 -- 30 ms at 50 MHz ); port( clk : in std_logic; rotA : in std_logic; rotB : in std_logic; rotPush : in std_logic; rotRightEvent : out std_logic; rotLeftEvent : out std_logic; rotPushEvent : out std_logic ); end entity rotKey; architecture beh of rotKey is signal rotA_d : std_logic; signal rotB_d : std_logic; signal rotA_rise : std_logic; signal rotB_rise : std_logic; begin deb_rotA: entity work.debounce generic map( CNT => CNT) port map( clk => clk, input => rotA, output => rotA_d, riseedge => rotA_rise, falledge => open ); deb_rotB: entity work.debounce generic map( CNT => CNT) port map( clk => clk, input => rotB, output => rotB_d, riseedge => rotB_rise, falledge => open ); deb_rotPush: entity work.debounce generic map( CNT => CNT) port map( clk => clk, input => rotPush, output => open, riseedge => rotPushEvent, falledge => open ); rotRightEvent <= '1' when rotA_rise = '1' and rotB_d = '0' else '0'; rotLeftEvent <= '1' when rotB_rise = '1' and rotA_d = '0' else '0'; end architecture beh;
mit
750e9649bf7635460f469c0a82344a2d
0.525507
3.659847
false
false
false
false
simonspa/pixel-dtb-firmware
dtb/ram_dq_PHASE_m.vhd
2
7,072
-- megafunction wizard: %RAM: 1-PORT% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altsyncram -- ============================================================ -- File Name: ram_dq_PHASE_m.vhd -- Megafunction Name(s): -- altsyncram -- -- Simulation Library Files(s): -- altera_mf -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version -- ************************************************************ --Copyright (C) 1991-2012 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY ram_dq_PHASE_m IS PORT ( address : IN STD_LOGIC_VECTOR (4 DOWNTO 0); clock : IN STD_LOGIC := '1'; data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); wren : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END ram_dq_PHASE_m; ARCHITECTURE SYN OF ram_dq_phase_m IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); COMPONENT altsyncram GENERIC ( clock_enable_input_a : STRING; clock_enable_output_a : STRING; intended_device_family : STRING; lpm_hint : STRING; lpm_type : STRING; numwords_a : NATURAL; operation_mode : STRING; outdata_aclr_a : STRING; outdata_reg_a : STRING; power_up_uninitialized : STRING; read_during_write_mode_port_a : STRING; widthad_a : NATURAL; width_a : NATURAL; width_byteena_a : NATURAL ); PORT ( address_a : IN STD_LOGIC_VECTOR (4 DOWNTO 0); clock0 : IN STD_LOGIC ; data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); wren_a : IN STD_LOGIC ; q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT; BEGIN q <= sub_wire0(7 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( clock_enable_input_a => "BYPASS", clock_enable_output_a => "BYPASS", intended_device_family => "Cyclone III", lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=PH_m", lpm_type => "altsyncram", numwords_a => 32, operation_mode => "SINGLE_PORT", outdata_aclr_a => "NONE", outdata_reg_a => "CLOCK0", power_up_uninitialized => "FALSE", read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", widthad_a => 5, width_a => 8, width_byteena_a => 1 ) PORT MAP ( address_a => address, clock0 => clock, data_a => data, wren_a => wren, q_a => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" -- Retrieval info: PRIVATE: AclrByte NUMERIC "0" -- Retrieval info: PRIVATE: AclrData NUMERIC "0" -- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: Clken NUMERIC "0" -- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1" -- Retrieval info: PRIVATE: JTAG_ID STRING "PH_m" -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -- Retrieval info: PRIVATE: MIFfilename STRING "" -- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32" -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" -- Retrieval info: PRIVATE: RegData NUMERIC "1" -- Retrieval info: PRIVATE: RegOutput NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" -- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" -- Retrieval info: PRIVATE: WidthAddr NUMERIC "5" -- Retrieval info: PRIVATE: WidthData NUMERIC "8" -- Retrieval info: PRIVATE: rden NUMERIC "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=PH_m" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" -- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5" -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -- Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL "address[4..0]" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" -- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" -- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" -- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" -- Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 -- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_m.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_m.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_m.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_m.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_m_inst.vhd FALSE -- Retrieval info: LIB_FILE: altera_mf
unlicense
5b376ab24751dce4e2dde73debefd9a7
0.671946
3.438017
false
false
false
false
systec-dk/openPOWERLINK_systec
Examples/ipcore/common/openmac/src/openMAC_16to32conv.vhd
3
6,703
------------------------------------------------------------------------------- -- -- (c) B&R, 2011 -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- -- -- This is a 32-to-16 bit converter which is necessary for e.g. Xilinx PLB. -- The component has to be connected to openMAC_Ethernet or powerlink. -- NOT use this directly with openMAC! -- ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_unsigned.ALL; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; entity openMAC_16to32conv is generic( gEndian : string := "little"; bus_address_width : integer := 10 ); port( clk : in std_logic; rst : in std_logic; --port from 32bit bus bus_select : in std_logic; bus_write : in std_logic; bus_read : in std_logic; bus_byteenable : in std_logic_vector(3 downto 0); bus_writedata : in std_logic_vector(31 downto 0); bus_readdata : out std_logic_vector(31 downto 0); bus_address : in std_logic_vector(bus_address_width-1 downto 0); bus_ack_wr : out std_logic; bus_ack_rd : out std_logic; --port to openMAC_Ethernet s_chipselect : out std_logic; s_write : out std_logic; s_read : out std_logic; s_address : out std_logic_vector(bus_address_width-1 downto 0); s_byteenable : out std_logic_vector(1 downto 0); s_waitrequest : in std_logic; s_readdata : in std_logic_vector(15 downto 0); s_writedata : out std_logic_vector(15 downto 0) ); end openMAC_16to32conv; architecture rtl of openMAC_16to32conv is -- types type fsm_t is (idle, doAccess); type bus_access_t is (none, dword, word); -- fsm signal fsm, fsm_next : fsm_t; signal bus_access : bus_access_t; -- cnt signal cnt, cnt_next, cnt_load_val : std_logic_vector(1 downto 0); signal cnt_load, cnt_dec, cnt_zero : std_logic; signal bus_ack : std_logic; -- word register signal word_reg, word_reg_next : std_logic_vector(15 downto 0); begin process(clk, rst) begin if rst = '1' then cnt <= (others => '0'); fsm <= idle; word_reg <= (others => '0'); elsif clk = '1' and clk'event then cnt <= cnt_next; fsm <= fsm_next; word_reg <= word_reg_next; end if; end process; word_reg_next <= s_readdata when bus_access = dword and cnt = 2 and s_waitrequest = '0' else word_reg; s_chipselect <= bus_select; --not cnt_zero; s_write <= bus_write and bus_select; s_read <= bus_read and bus_select; cnt_dec <= (not s_waitrequest) and bus_select; bus_readdata <= s_readdata & word_reg when bus_access = dword else s_readdata & s_readdata; bus_ack <= '1' when cnt = 1 and s_waitrequest = '0' and bus_access = dword else '1' when s_waitrequest = '0' and bus_access = word else '0'; bus_ack_wr <= bus_ack and bus_write; bus_ack_rd <= bus_ack and bus_read; s_address(bus_address_width-1 downto 1) <= '0' & bus_address(bus_address_width-1 downto 2); --word address set to +0 (little) when first dword access or word access with selected word/byte s_address(0) <= '0' when bus_access = dword and (cnt = 2 or cnt = 0) and gEndian = "little" else --first word of dword access '1' when bus_access = dword and cnt = 1 and gEndian = "little" else '1' when bus_access = dword and (cnt = 2 or cnt = 0) and gEndian = "big" else '0' when bus_access = dword and cnt = 1 and gEndian = "big" else --first word of dword access bus_address(1); s_byteenable <= "11" when bus_access = dword else bus_byteenable(3 downto 2) or bus_byteenable(1 downto 0); s_writedata <= bus_writedata(15 downto 0) when bus_access = dword and (cnt = 2 or cnt = 0) else bus_writedata(31 downto 16) when bus_access = dword and cnt = 1 else bus_writedata(15 downto 0) when bus_address(1) = '0' else bus_writedata(31 downto 16); --when bus_address(1) = '1' else --fsm bus_access <= none when bus_select /= '1' else dword when bus_byteenable = "1111" else word; fsm_next <= doAccess when fsm = idle and cnt_zero = '1' and bus_access = dword else idle when fsm = doAccess and cnt_zero = '1' and bus_access = none else fsm; --if dword, access twice, otherwise (byte, word) access once cnt_load_val <= "10" when bus_byteenable = "1111" and bus_read = '1' else "01"; cnt_load <= '1' when fsm_next = doAccess and fsm = idle else '0'; --counter cnt_next <= cnt_load_val when cnt_load = '1' else cnt - 1 when cnt_dec = '1' and bus_access = dword else cnt; cnt_zero <= '1' when cnt = 0 else '0'; end rtl;
gpl-2.0
0a28349af851ce0948d6993ee8a7f7b6
0.597792
3.850086
false
false
false
false
simonspa/pixel-dtb-firmware
dtb/Counter3bMOD5.vhd
2
4,777
-- megafunction wizard: %LPM_COUNTER% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: lpm_counter -- ============================================================ -- File Name: Counter3bMOD5.vhd -- Megafunction Name(s): -- lpm_counter -- -- Simulation Library Files(s): -- lpm -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 9.1 Build 222 10/21/2009 SJ Full Version -- ************************************************************ --Copyright (C) 1991-2009 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.all; ENTITY Counter3bMOD5 IS PORT ( clock : IN STD_LOGIC ; sclr : IN STD_LOGIC ; cout : OUT STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0) ); END Counter3bMOD5; ARCHITECTURE SYN OF counter3bmod5 IS SIGNAL sub_wire0 : STD_LOGIC ; SIGNAL sub_wire1 : STD_LOGIC_VECTOR (2 DOWNTO 0); COMPONENT lpm_counter GENERIC ( lpm_direction : STRING; lpm_modulus : NATURAL; lpm_port_updown : STRING; lpm_type : STRING; lpm_width : NATURAL ); PORT ( sclr : IN STD_LOGIC ; clock : IN STD_LOGIC ; cout : OUT STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0) ); END COMPONENT; BEGIN cout <= sub_wire0; q <= sub_wire1(2 DOWNTO 0); lpm_counter_component : lpm_counter GENERIC MAP ( lpm_direction => "UP", lpm_modulus => 5, lpm_port_updown => "PORT_UNUSED", lpm_type => "LPM_COUNTER", lpm_width => 3 ) PORT MAP ( sclr => sclr, clock => clock, cout => sub_wire0, q => sub_wire1 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ACLR NUMERIC "0" -- Retrieval info: PRIVATE: ALOAD NUMERIC "0" -- Retrieval info: PRIVATE: ASET NUMERIC "0" -- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" -- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" -- Retrieval info: PRIVATE: CNT_EN NUMERIC "0" -- Retrieval info: PRIVATE: CarryIn NUMERIC "0" -- Retrieval info: PRIVATE: CarryOut NUMERIC "1" -- Retrieval info: PRIVATE: Direction NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX" -- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1" -- Retrieval info: PRIVATE: ModulusValue NUMERIC "5" -- Retrieval info: PRIVATE: SCLR NUMERIC "1" -- Retrieval info: PRIVATE: SLOAD NUMERIC "0" -- Retrieval info: PRIVATE: SSET NUMERIC "0" -- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: nBit NUMERIC "3" -- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP" -- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "5" -- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "3" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock -- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout -- Retrieval info: USED_PORT: q 0 0 3 0 OUTPUT NODEFVAL q[2..0] -- Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL sclr -- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 3 0 @q 0 0 3 0 -- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0 -- Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0 -- Retrieval info: LIBRARY: lpm lpm.lpm_components.all -- Retrieval info: GEN_FILE: TYPE_NORMAL Counter3bMOD5.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL Counter3bMOD5.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL Counter3bMOD5.cmp FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL Counter3bMOD5.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL Counter3bMOD5_inst.vhd FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL Counter3bMOD5_waveforms.html TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL Counter3bMOD5_wave*.jpg FALSE -- Retrieval info: LIB_FILE: lpm
unlicense
115ceba95f09bfafcc04a9264c33ce43
0.657526
3.629939
false
false
false
false
systec-dk/openPOWERLINK_systec
Examples/ipcore/common/pdi/src/pdi_controlStatusReg.vhd
3
26,620
------------------------------------------------------------------------------- -- Process Data Interface (PDI) status control register -- -- Copyright (C) 2011 B&R -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; entity pdiControlStatusReg is generic ( bIsPcp : boolean := true; iAddrWidth_g : integer := 8; iBaseDpr_g : integer := 16#4#; --base address (in external mapping) of content in dpr iSpanDpr_g : integer := 12; --span of content in dpr iBaseMap2_g : integer := 0; --base address in dpr iDprAddrWidth_g : integer := 11; iRpdos_g : integer := 3; genLedGadget_g : boolean := false; genTimeSync_g : boolean := false; genEvent_g : boolean := false; --register content ---constant values magicNumber : std_Logic_vector(31 downto 0) := (others => '0'); pdiRev : std_logic_vector(15 downto 0) := (others => '0'); pcpSysId : std_logic_vector(15 downto 0) := (others => '0'); tPdoBuffer : std_logic_vector(31 downto 0) := (others => '0'); rPdo0Buffer : std_logic_vector(31 downto 0) := (others => '0'); rPdo1Buffer : std_logic_vector(31 downto 0) := (others => '0'); rPdo2Buffer : std_logic_vector(31 downto 0) := (others => '0'); asyncBuffer1Tx : std_logic_vector(31 downto 0) := (others => '0'); asyncBuffer1Rx : std_logic_vector(31 downto 0) := (others => '0'); asyncBuffer2Tx : std_logic_vector(31 downto 0) := (others => '0'); asyncBuffer2Rx : std_logic_vector(31 downto 0) := (others => '0') ); port ( --memory mapped interface clk : in std_logic; rst : in std_logic; sel : in std_logic; wr : in std_logic; rd : in std_logic; addr : in std_logic_vector(iAddrWidth_g-1 downto 0); be : in std_logic_vector(3 downto 0); din : in std_logic_vector(31 downto 0); dout : out std_logic_vector(31 downto 0); --register content ---virtual buffer control signals rpdo_change_tog : in std_logic_vector(2 downto 0); --change buffer from hw acc tpdo_change_tog : in std_logic; --change buffer from hw acc pdoVirtualBufferSel : in std_logic_vector(31 downto 0); --for debugging purpose from SW side --TXPDO_ACK | RXPDO2_ACK | RXPDO1_ACK | RXPDO0_ACK tPdoTrigger : out std_logic; --TPDO virtual buffer change trigger rPdoTrigger : out std_logic_vector(2 downto 0); --RPDOs virtual buffer change triggers ---is used for Irq Generation and should be mapped to apIrqGen apIrqControlOut : out std_logic_vector(15 downto 0); apIrqControlIn : in std_logic_vector(15 downto 0); ---event registers eventAckIn : in std_logic_vector(15 downto 0); eventAckOut : out std_logic_vector(15 downto 0); ---async irq (by event) asyncIrqCtrlIn : In std_logic_vector(15 downto 0); --Ap only asyncIrqCtrlOut : out std_logic_vector(15 downto 0); --Ap only ---led stuff ledCnfgIn : in std_logic_vector(15 downto 0); ledCnfgOut : out std_logic_vector(15 downto 0); ledCtrlIn : in std_logic_vector(15 downto 0); ledCtrlOut : out std_logic_vector(15 downto 0); ---time synchronization doubleBufSel_out : out std_logic; --Ap only doubleBufSel_in : in std_logic := '0'; --Pcp only timeSyncIrq : in std_logic; --SYNC IRQ to Ap (Ap only) --dpr interface (from PCP/AP to DPR) dprAddrOff : out std_logic_vector(iDprAddrWidth_g downto 0); dprDin : out std_logic_vector(31 downto 0); dprDout : in std_logic_vector(31 downto 0); dprBe : out std_logic_vector(3 downto 0); dprWr : out std_logic ); end entity pdiControlStatusReg; architecture rtl of pdiControlStatusReg is constant c_num_dbuf_dpr : integer := 4; --number of dbuf in DPR (per buffer 4 byte) signal selDpr : std_logic; --if '1' get/write content from/to dpr signal nonDprDout : std_logic_vector(31 downto 0); signal addrRes : std_logic_vector(dprAddrOff'range); --signal apIrqValue_s : std_logic_vector(31 downto 0); --pcp only signal virtualBufferSelectTpdo : std_logic_vector(15 downto 0); signal virtualBufferSelectRpdo0 : std_logic_vector(15 downto 0); signal virtualBufferSelectRpdo1 : std_logic_vector(15 downto 0); signal virtualBufferSelectRpdo2 : std_logic_vector(15 downto 0); --edge detection signal rpdo_change_tog_l : std_logic_vector(2 downto 0); --change buffer from hw acc signal tpdo_change_tog_l : std_logic; --change buffer from hw acc --time synchronization signal timeSyncIrq_rising : std_logic; ---select signals signal sel_time_after_sync : std_logic; signal sel_double_buffer : std_logic; ----double buffered content signal sel_relative_time_l : std_logic; signal sel_relative_time_h : std_logic; signal sel_nettime_nsec : std_logic; signal sel_nettime_sec : std_logic; signal sel_time_sync_regs : std_logic; ---time after sync counter constant c_time_after_sync_cnt_size : integer := 16; --revise code if changed signal time_after_sync_cnt : std_logic_vector(c_time_after_sync_cnt_size-1 downto 0); signal time_after_sync_cnt_latch : std_logic_vector(c_time_after_sync_cnt_size/2-1 downto 0); signal time_after_sync_cnt_next : std_logic_vector(c_time_after_sync_cnt_size-1 downto 0); signal time_after_sync_cnt_out : std_logic_vector(c_time_after_sync_cnt_size-1 downto 0) := (others => '0'); constant time_after_sync_res : std_logic_vector(32-c_time_after_sync_cnt_size-1 downto 0) := (others => '0'); ---address offsets constant c_addr_time_after_sync : integer := 16#50#; constant c_addr_relative_time_l : integer := 16#40#; constant c_addr_relative_time_h : integer := 16#44#; constant c_addr_nettime_nsec : integer := 16#48#; constant c_addr_nettime_sec : integer := 16#4C#; begin --map to 16bit register --TXPDO_ACK | RXPDO2_ACK | RXPDO1_ACK | RXPDO0_ACK virtualBufferSelectRpdo0 <= pdoVirtualBufferSel( 7 downto 0) & pdoVirtualBufferSel( 7 downto 0); virtualBufferSelectRpdo1 <= pdoVirtualBufferSel(15 downto 8) & pdoVirtualBufferSel(15 downto 8); virtualBufferSelectRpdo2 <= pdoVirtualBufferSel(23 downto 16) & pdoVirtualBufferSel(23 downto 16); virtualBufferSelectTpdo <= pdoVirtualBufferSel(31 downto 24) & pdoVirtualBufferSel(31 downto 24); --generate dpr select signal selDpr <= sel when (conv_integer(addr) >= iBaseDpr_g AND conv_integer(addr) < iBaseDpr_g + iSpanDpr_g - c_num_dbuf_dpr) else '0'; --time sync select content if the double buffer has to be generated (genTimeSync_g) sel_time_after_sync <= '1' when conv_integer(addr)*4 = c_addr_time_after_sync and genTimeSync_g else '0'; sel_relative_time_l <= '1' when conv_integer(addr)*4 = c_addr_relative_time_l and genTimeSync_g else '0'; sel_relative_time_h <= '1' when conv_integer(addr)*4 = c_addr_relative_time_h and genTimeSync_g else '0'; sel_nettime_nsec <= '1' when conv_integer(addr)*4 = c_addr_nettime_nsec and genTimeSync_g else '0'; sel_nettime_sec <= '1' when conv_integer(addr)*4 = c_addr_nettime_sec and genTimeSync_g else '0'; ---or them up... sel_time_sync_regs <= sel_relative_time_l or sel_relative_time_h or sel_nettime_nsec or sel_nettime_sec; genTimeSync : if genTimeSync_g generate begin --we need a rising edge to do magic apSyncIrqEdgeDet : entity work.edgedet port map ( din => timeSyncIrq, rising => timeSyncIrq_rising, falling => open, any => open, clk => clk, rst => rst ); genDoubleBufPcp : if bIsPcp generate begin --take the other buffer (Ap has already inverted, see lines below!) sel_double_buffer <= doubleBufSel_in; --Pcp has no timer time_after_sync_cnt_out <= (others => '0'); end generate; genDoubleBufAp : if not bIsPcp generate begin --output the inverted to the PCP doubleBufSel_out <= not sel_double_buffer; --switch the double buffer with the sync irq, rising edge of course process(clk, rst) begin if rst = '1' then sel_double_buffer <= '0'; elsif rising_edge(clk) then if timeSyncIrq_rising = '1' then --rising edge sel_double_buffer <= not sel_double_buffer; end if; end if; end process; end generate; genTimeAfterSyncCnt : if not bIsPcp generate constant ZEROS : std_logic_vector(time_after_sync_cnt'range) := (others => '0'); constant ONES : std_logic_vector(time_after_sync_cnt'range) := (others => '1'); begin --TIME_AFTER_SYNC counter process(clk, rst) begin if rst = '1' then time_after_sync_cnt <= (others => '0'); elsif clk = '1' and clk'event then time_after_sync_cnt <= time_after_sync_cnt_next; --there are some kind of interfaces that read only the half of a word... -- so store the half that is not read -- and forward it to the Ap at the next read if sel = '1' and sel_time_after_sync = '1' and be = "0001" then time_after_sync_cnt_latch <= time_after_sync_cnt(c_time_after_sync_cnt_size-1 downto c_time_after_sync_cnt_size/2); end if; end if; end process; time_after_sync_cnt_next <= ZEROS when timeSyncIrq_rising = '1' else --rising edge time_after_sync_cnt when time_after_sync_cnt = ONES else --saturate time_after_sync_cnt + 1; --count for your life! time_after_sync_cnt_out <= time_after_sync_cnt when be(3 downto 2) = "11" or be(1 downto 0) = "11" else time_after_sync_cnt_latch & time_after_sync_cnt(time_after_sync_cnt_latch'range); end generate; end generate; --assign content depending on selDpr dprDin <= din; dprBe <= be; dprWr <= wr when selDpr = '1' else '0'; dout <= dprDout when selDpr = '1' else nonDprDout; dprAddrOff <= addrRes + 4 when sel_double_buffer = '1' and sel_time_sync_regs = '1' and genTimeSync_g else --select 2nd double buffer addrRes; --select 1st double buffer or other content --address conversion ---map external address mapping into dpr addrRes <= conv_std_logic_vector(iBaseMap2_g - iBaseDpr_g, addrRes'length); --non dpr read with conv_integer(addr)*4 select nonDprDout <= magicNumber when 16#00#, (pcpSysId & pdiRev) when 16#04#, --STORED IN DPR when 16#08#, --STORED IN DPR when 16#0C#, --STORED IN DPR when 16#10#, --STORED IN DPR when 16#14#, --STORED IN DPR when 16#18#, --STORED IN DPR when 16#1C#, --STORED IN DPR when 16#20#, --STORED IN DPR when 16#24#, --STORED IN DPR when 16#28#, --STORED IN DPR when 16#2C#, --STORED IN DPR when 16#30#, --STORED IN DPR when 16#34#, --RESERVED --STORED IN DPR when 16#38#, --RESERVED --STORED IN DPR when 16#3C#, --RESERVED --STORED IN DPR x2 when c_addr_relative_time_l, --RELATIVE_TIME low --STORED IN DPR x2 when c_addr_relative_time_h, --RELATIVE_TIME high --STORED IN DPR x2 when c_addr_nettime_nsec, --NETTIME nsec --STORED IN DPR x2 when c_addr_nettime_sec, --NETTIME sec (time_after_sync_res & time_after_sync_cnt_out) when c_addr_time_after_sync, --RES / TIME_AFTER_SYNC (eventAckIn & asyncIrqCtrlIn) when 16#54#, tPdoBuffer when 16#58#, rPdo0Buffer when 16#5C#, rPdo1Buffer when 16#60#, rPdo2Buffer when 16#64#, asyncBuffer1Tx when 16#68#, asyncBuffer1Rx when 16#6C#, asyncBuffer2Tx when 16#70#, asyncBuffer2Rx when 16#74#, --RESERVED when 16#78#, --RESERVED when 16#7C#, (virtualBufferSelectRpdo0 & virtualBufferSelectTpdo) when 16#80#, (virtualBufferSelectRpdo2 & virtualBufferSelectRpdo1) when 16#84#, (x"0000" & apIrqControlIn) when 16#88#, --RESERVED when 16#8C#, --RESERVED when 16#90#, (ledCnfgIn & ledCtrlIn) when 16#94#, (others => '0') when others; --ignored values asyncIrqCtrlOut(14 downto 1) <= (others => '0'); eventAckOut(15 downto 8) <= (others => '0'); --non dpr write process(clk, rst) begin if rst = '1' then tPdoTrigger <= '0'; rPdoTrigger <= (others => '0'); --apIrqControlOut <= (others => '0'); if bIsPcp = true then apIrqControlOut(7) <= '0'; apIrqControlOut(6) <= '0'; end if; if bIsPcp = false then apIrqControlOut(15) <= '0'; end if; apIrqControlOut(0) <= '0'; if genEvent_g then if bIsPcp = false then asyncIrqCtrlOut(0) <= '0'; asyncIrqCtrlOut(15) <= '0'; end if; eventAckOut(7 downto 0) <= (others => '0'); end if; if genLedGadget_g then ledCtrlOut(7 downto 0) <= (others => '0'); ledCnfgOut(7 downto 0) <= (others => '0'); end if; if bIsPcp then rpdo_change_tog_l <= (others => '0'); tpdo_change_tog_l <= '0'; end if; elsif clk = '1' and clk'event then --default assignments tPdoTrigger <= '0'; rPdoTrigger <= (others => '0'); apIrqControlOut(0) <= '0'; --PCP: set pulse // AP: ack pulse if genEvent_g then eventAckOut(7 downto 0) <= (others => '0'); --PCP: set pulse // AP: ack pulse end if; if bIsPcp then --shift register for edge det rpdo_change_tog_l <= rpdo_change_tog; tpdo_change_tog_l <= tpdo_change_tog; --edge detection ---tpdo if tpdo_change_tog_l /= tpdo_change_tog then tPdoTrigger <= '1'; end if; ---rpdo for i in rpdo_change_tog'range loop if rpdo_change_tog_l(i) /= rpdo_change_tog(i) then rPdoTrigger(i) <= '1'; end if; end loop; end if; if wr = '1' and sel = '1' and selDpr = '0' then case conv_integer(addr)*4 is when 16#00# => --RO when 16#04# => --RO when 16#08# => --STORED IN DPR when 16#0C# => --STORED IN DPR when 16#10# => --STORED IN DPR when 16#14# => --STORED IN DPR when 16#18# => --STORED IN DPR when 16#1C# => --STORED IN DPR when 16#20# => --STORED IN DPR when 16#24# => --STORED IN DPR when 16#28# => --STORED IN DPR when 16#2C# => --STORED IN DPR when 16#30# => --STORED IN DPR when 16#34# => --STORED IN DPR RESERVED when 16#38# => --STORED IN DPR RESERVED when 16#3C# => --STORED IN DPR RESERVED when 16#40# => --STORED IN DPR x2 when 16#44# => --STORED IN DPR x2 when 16#48# => --STORED IN DPR x2 when 16#4C# => --STORED IN DPR x2 when c_addr_time_after_sync => --RO when 16#54# => --AP ONLY if genEvent_g then if be(0) = '1' and bIsPcp = false then --asyncIrqCtrlOut(7 downto 0) <= din(7 downto 0); asyncIrqCtrlOut(0) <= din(0); --rest is ignored end if; if be(1) = '1' and bIsPcp = false then --asyncIrqCtrlOut(15 downto 8) <= din(15 downto 8); asyncIrqCtrlOut(15) <= din(15); --rest is ignored end if; if be(2) = '1' then eventAckOut(7 downto 0) <= din(23 downto 16); end if; --ignore higher byte of event ack -- if be(3) = '1' then -- eventAckOut(15 downto 8) <= din(31 downto 24); -- end if; end if; when 16#58# => --RO when 16#5C# => --RO when 16#60# => --RO when 16#64# => --RO when 16#68# => --RO when 16#6C# => --RO when 16#70# => --RO when 16#74# => --RO when 16#78# => --RESERVED when 16#7C# => --RESERVED when 16#80# => if be(0) = '1' then tPdoTrigger <= '1'; end if; if be(1) = '1' then tPdoTrigger <= '1'; end if; if be(2) = '1' then rPdoTrigger(0) <= '1'; end if; if be(3) = '1' then rPdoTrigger(0) <= '1'; end if; when 16#84# => if be(0) = '1' then rPdoTrigger(1) <= '1'; end if; if be(1) = '1' then rPdoTrigger(1) <= '1'; end if; if be(2) = '1' then rPdoTrigger(2) <= '1'; end if; if be(3) = '1' then rPdoTrigger(2) <= '1'; end if; when 16#88# => if be(0) = '1' then --apIrqControlOut(7 downto 0) <= din(7 downto 0); if bIsPcp = true then apIrqControlOut(7) <= din(7); apIrqControlOut(6) <= din(6); end if; apIrqControlOut(0) <= din(0); end if; if be(1) = '1' then --apIrqControlOut(15 downto 8) <= din(15 downto 8); if bIsPcp = false then apIrqControlOut(15) <= din(15); end if; end if; when 16#8C# => --RESERVED when 16#90# => --RESERVED when 16#94# => if genLedGadget_g then if be(0) = '1' then ledCtrlOut(7 downto 0) <= din(7 downto 0); end if; if be(1) = '1' then ledCtrlOut(15 downto 8) <= din(15 downto 8); end if; if be(2) = '1' then ledCnfgOut(7 downto 0) <= din(23 downto 16); end if; if be(3) = '1' then ledCnfgOut(15 downto 8) <= din(31 downto 24); end if; end if; when others => end case; end if; end if; end process; end architecture rtl;
gpl-2.0
35766f08713ba410544b7616b5a0c231
0.436026
4.789493
false
false
false
false
systec-dk/openPOWERLINK_systec
Examples/ipcore/xilinx/library/pcores/axi_powerlink_v0_30_a/hdl/vhdl/axi_powerlink.vhd
3
86,416
------------------------------------------------------------------------------- --! @file axi_powerlink.vhd -- --! @brief -- ------------------------------------------------------------------------------- -- -- (c) B&R, 2012 -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- -- -- This is the toplevel file for using the POWERLINK IP-Core -- with Xilinx AXI. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.math_real.log2; use ieee.math_real.ceil; use work.global.all; library proc_common_v3_00_a; use proc_common_v3_00_a.proc_common_pkg.all; use proc_common_v3_00_a.ipif_pkg.all; library axi_lite_ipif_v1_01_a; use axi_lite_ipif_v1_01_a.axi_lite_ipif; library axi_master_burst_v1_00_a; use axi_master_burst_v1_00_a.axi_master_burst; -- standard libraries declarations library UNISIM; use UNISIM.vcomponents.all; -- pragma synthesis_off library IEEE; use IEEE.vital_timing.all; -- pragma synthesis_on -- other libraries declarations library AXI_LITE_IPIF_V1_01_A; library AXI_MASTER_BURST_V1_00_A; entity axi_powerlink is generic( C_FAMILY : string := "spartan6"; -- general C_GEN_PDI : boolean := false; C_GEN_PAR_IF : boolean := false; C_GEN_SPI_IF : boolean := false; C_GEN_AXI_BUS_IF : boolean := false; C_GEN_SIMPLE_IO : boolean := false; -- openMAC C_MAC_PKT_SIZE : integer := 1024; C_MAC_PKT_SIZE_LOG2 : integer := 10; C_MAC_RX_BUFFERS : integer := 16; C_USE_RMII : boolean := false; C_TX_INT_PKT : boolean := false; C_RX_INT_PKT : boolean := false; C_USE_2ND_PHY : boolean := true; C_NUM_SMI : integer range 1 to 2 := 2; C_MAC_GEN_SECOND_TIMER : boolean := false; --pdi C_PDI_REV : integer := 0; C_PCP_SYS_ID : integer := 0; C_PDI_GEN_ASYNC_BUF_0 : boolean := true; C_PDI_ASYNC_BUF_0 : integer := 50; C_PDI_GEN_ASYNC_BUF_1 : boolean := true; C_PDI_ASYNC_BUF_1 : integer := 50; C_PDI_GEN_LED : boolean := false; C_PDI_GEN_TIME_SYNC : boolean := true; C_PDI_GEN_EVENT : boolean := true; --global pdi and mac C_NUM_RPDO : integer := 3; C_RPDO_0_BUF_SIZE : integer := 100; C_RPDO_1_BUF_SIZE : integer := 100; C_RPDO_2_BUF_SIZE : integer := 100; C_NUM_TPDO : integer := 1; C_TPDO_BUF_SIZE : integer := 100; -- pap C_PAP_DATA_WIDTH : integer := 16; --C_PAP_BIG_END : boolean := false; C_PAP_LOW_ACT : boolean := false; -- spi C_SPI_CPOL : boolean := false; C_SPI_CPHA : boolean := false; --C_SPI_BIG_END : boolean := false; -- simpleIO C_PIO_VAL_LENGTH : integer := 50; -- debug C_OBSERVER_ENABLE : boolean := false; -- clock stabiliser C_INSTANCE_ODDR2 : boolean := false; -- sync IRQ pulse width C_USE_PULSE_2nd_CMP_TIMER : boolean := true; C_PULSE_WIDTH_2nd_CMP_TIMER : integer := 9; -- PDI AP AXI Slave C_S_AXI_PDI_AP_BASEADDR : std_logic_vector := X"00000000"; C_S_AXI_PDI_AP_HIGHADDR : std_logic_vector := X"000FFFFF"; C_S_AXI_PDI_AP_DATA_WIDTH : integer := 32; C_S_AXI_PDI_AP_ADDR_WIDTH : integer := 32; C_S_AXI_PDI_AP_USE_WSTRB : integer := 1; C_S_AXI_PDI_AP_DPHASE_TIMEOUT : integer := 8; -- PDI AP AXI Slave C_S_AXI_SMP_PCP_BASEADDR : std_logic_vector := X"00000000"; C_S_AXI_SMP_PCP_HIGHADDR : std_logic_vector := X"000FFFFF"; C_S_AXI_SMP_PCP_DATA_WIDTH : integer := 32; C_S_AXI_SMP_PCP_ADDR_WIDTH : integer := 32; C_S_AXI_SMP_PCP_USE_WSTRB : integer := 1; C_S_AXI_SMP_PCP_DPHASE_TIMEOUT : integer := 8; -- PDI PCP AXI Slave C_S_AXI_PDI_PCP_BASEADDR : std_logic_vector := X"00000000"; C_S_AXI_PDI_PCP_HIGHADDR : std_logic_vector := X"000FFFFF"; C_S_AXI_PDI_PCP_DATA_WIDTH : integer := 32; C_S_AXI_PDI_PCP_ADDR_WIDTH : integer := 32; C_S_AXI_PDI_PCP_USE_WSTRB : integer := 1; C_S_AXI_PDI_PCP_DPHASE_TIMEOUT : integer := 8; -- openMAC DMA AXI Master C_M_AXI_MAC_DMA_ADDR_WIDTH : INTEGER := 32; C_M_AXI_MAC_DMA_DATA_WIDTH : INTEGER := 32; C_M_AXI_MAC_DMA_NATIVE_DWIDTH : INTEGER := 32; C_M_AXI_MAC_DMA_LENGTH_WIDTH : INTEGER := 12; C_M_AXI_MAC_DMA_MAX_BURST_LEN : INTEGER := 16; C_MAC_DMA_BURST_SIZE_RX : INTEGER := 8; --in bytes C_MAC_DMA_BURST_SIZE_TX : INTEGER := 8; --in bytes C_MAC_DMA_FIFO_SIZE_RX : INTEGER := 32; --in bytes C_MAC_DMA_FIFO_SIZE_TX : INTEGER := 32; --in bytes -- openMAC PKT AXI Slave C_S_AXI_MAC_PKT_BASEADDR : std_logic_vector := X"00000000"; C_S_AXI_MAC_PKT_HIGHADDR : std_logic_vector := X"000FFFFF"; C_S_AXI_MAC_PKT_DATA_WIDTH : integer := 32; C_S_AXI_MAC_PKT_ADDR_WIDTH : integer := 32; C_S_AXI_MAC_PKT_USE_WSTRB : integer := 1; C_S_AXI_MAC_PKT_DPHASE_TIMEOUT : integer := 8; -- openMAC REG AXI Slave --- MAC_REG C_S_AXI_MAC_REG_RNG0_BASEADDR : std_logic_vector := X"00000000"; C_S_AXI_MAC_REG_RNG0_HIGHADDR : std_logic_vector := X"0000FFFF"; --- MAC_CMP C_S_AXI_MAC_REG_RNG1_BASEADDR : std_logic_vector := X"00000000"; C_S_AXI_MAC_REG_RNG1_HIGHADDR : std_logic_vector := X"0000FFFF"; C_S_AXI_MAC_REG_DATA_WIDTH : integer := 32; C_S_AXI_MAC_REG_ADDR_WIDTH : integer := 32; C_S_AXI_MAC_REG_USE_WSTRB : integer := 1; C_S_AXI_MAC_REG_DPHASE_TIMEOUT : integer := 8; C_S_AXI_MAC_REG_ACLK_FREQ_HZ : integer := 20 --clock frequency in Hz ); port( M_AXI_MAC_DMA_aclk : in std_logic; M_AXI_MAC_DMA_aresetn : in std_logic; M_AXI_MAC_DMA_arready : in std_logic; M_AXI_MAC_DMA_awready : in std_logic; M_AXI_MAC_DMA_bvalid : in std_logic; M_AXI_MAC_DMA_rlast : in std_logic; M_AXI_MAC_DMA_rvalid : in std_logic; M_AXI_MAC_DMA_wready : in std_logic; S_AXI_MAC_PKT_ACLK : in std_logic; S_AXI_MAC_PKT_ARESETN : in std_logic; S_AXI_MAC_PKT_ARVALID : in std_logic; S_AXI_MAC_PKT_AWVALID : in std_logic; S_AXI_MAC_PKT_BREADY : in std_logic; S_AXI_MAC_PKT_RREADY : in std_logic; S_AXI_MAC_PKT_WVALID : in std_logic; S_AXI_MAC_REG_ACLK : in std_logic; S_AXI_MAC_REG_ARESETN : in std_logic; S_AXI_MAC_REG_ARVALID : in std_logic; S_AXI_MAC_REG_AWVALID : in std_logic; S_AXI_MAC_REG_BREADY : in std_logic; S_AXI_MAC_REG_RREADY : in std_logic; S_AXI_MAC_REG_WVALID : in std_logic; S_AXI_PDI_AP_ACLK : in std_logic; S_AXI_PDI_AP_ARESETN : in std_logic; S_AXI_PDI_AP_ARVALID : in std_logic; S_AXI_PDI_AP_AWVALID : in std_logic; S_AXI_PDI_AP_BREADY : in std_logic; S_AXI_PDI_AP_RREADY : in std_logic; S_AXI_PDI_AP_WVALID : in std_logic; S_AXI_PDI_PCP_ACLK : in std_logic; S_AXI_PDI_PCP_ARESETN : in std_logic; S_AXI_PDI_PCP_ARVALID : in std_logic; S_AXI_PDI_PCP_AWVALID : in std_logic; S_AXI_PDI_PCP_BREADY : in std_logic; S_AXI_PDI_PCP_RREADY : in std_logic; S_AXI_PDI_PCP_WVALID : in std_logic; S_AXI_SMP_PCP_ACLK : in std_logic; S_AXI_SMP_PCP_ARESETN : in std_logic; S_AXI_SMP_PCP_ARVALID : in std_logic; S_AXI_SMP_PCP_AWVALID : in std_logic; S_AXI_SMP_PCP_BREADY : in std_logic; S_AXI_SMP_PCP_RREADY : in std_logic; S_AXI_SMP_PCP_WVALID : in std_logic; clk100 : in std_logic; clk50 : in std_logic; pap_cs : in std_logic; pap_cs_n : in std_logic; pap_rd : in std_logic; pap_rd_n : in std_logic; pap_wr : in std_logic; pap_wr_n : in std_logic; phy0_RxDv : in std_logic; phy0_RxErr : in std_logic; phy0_SMIDat_I : in std_logic; phy0_link : in std_logic; phy1_RxDv : in std_logic; phy1_RxErr : in std_logic; phy1_SMIDat_I : in std_logic; phy1_link : in std_logic; phyMii0_RxClk : in std_logic; phyMii0_RxDv : in std_logic; phyMii0_RxEr : in std_logic; phyMii0_TxClk : in std_logic; phyMii1_RxClk : in std_logic; phyMii1_RxDv : in std_logic; phyMii1_RxEr : in std_logic; phyMii1_TxClk : in std_logic; phy_SMIDat_I : in std_logic; spi_clk : in std_logic; spi_mosi : in std_logic; spi_sel_n : in std_logic; M_AXI_MAC_DMA_bresp : in std_logic_vector(1 downto 0); M_AXI_MAC_DMA_rdata : in std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0); M_AXI_MAC_DMA_rresp : in std_logic_vector(1 downto 0); S_AXI_MAC_PKT_ARADDR : in std_logic_vector(C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0); S_AXI_MAC_PKT_AWADDR : in std_logic_vector(C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0); S_AXI_MAC_PKT_WDATA : in std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0); S_AXI_MAC_PKT_WSTRB : in std_logic_vector((C_S_AXI_MAC_PKT_DATA_WIDTH/8)-1 downto 0); S_AXI_MAC_REG_ARADDR : in std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0); S_AXI_MAC_REG_AWADDR : in std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0); S_AXI_MAC_REG_WDATA : in std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0); S_AXI_MAC_REG_WSTRB : in std_logic_vector((C_S_AXI_MAC_REG_DATA_WIDTH/8)-1 downto 0); S_AXI_PDI_AP_ARADDR : in std_logic_vector(C_S_AXI_PDI_AP_ADDR_WIDTH-1 downto 0); S_AXI_PDI_AP_AWADDR : in std_logic_vector(C_S_AXI_PDI_AP_ADDR_WIDTH-1 downto 0); S_AXI_PDI_AP_WDATA : in std_logic_vector(C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0); S_AXI_PDI_AP_WSTRB : in std_logic_vector((C_S_AXI_PDI_AP_DATA_WIDTH/8)-1 downto 0); S_AXI_PDI_PCP_ARADDR : in std_logic_vector(C_S_AXI_PDI_PCP_ADDR_WIDTH-1 downto 0); S_AXI_PDI_PCP_AWADDR : in std_logic_vector(C_S_AXI_PDI_PCP_ADDR_WIDTH-1 downto 0); S_AXI_PDI_PCP_WDATA : in std_logic_vector(C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0); S_AXI_PDI_PCP_WSTRB : in std_logic_vector((C_S_AXI_PDI_PCP_DATA_WIDTH/8)-1 downto 0); S_AXI_SMP_PCP_ARADDR : in std_logic_vector(C_S_AXI_SMP_PCP_ADDR_WIDTH-1 downto 0); S_AXI_SMP_PCP_AWADDR : in std_logic_vector(C_S_AXI_SMP_PCP_ADDR_WIDTH-1 downto 0); S_AXI_SMP_PCP_WDATA : in std_logic_vector(C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0); S_AXI_SMP_PCP_WSTRB : in std_logic_vector((C_S_AXI_SMP_PCP_DATA_WIDTH/8)-1 downto 0); pap_addr : in std_logic_vector(15 downto 0); pap_be : in std_logic_vector(C_PAP_DATA_WIDTH/8-1 downto 0); pap_be_n : in std_logic_vector(C_PAP_DATA_WIDTH/8-1 downto 0); pap_data_I : in std_logic_vector(C_PAP_DATA_WIDTH-1 downto 0); pap_gpio_I : in std_logic_vector(1 downto 0); phy0_RxDat : in std_logic_vector(1 downto 0); phy1_RxDat : in std_logic_vector(1 downto 0); phyMii0_RxDat : in std_logic_vector(3 downto 0); phyMii1_RxDat : in std_logic_vector(3 downto 0); pio_pconfig : in std_logic_vector(3 downto 0); pio_portInLatch : in std_logic_vector(3 downto 0); pio_portio_I : in std_logic_vector(31 downto 0); M_AXI_MAC_DMA_arvalid : out std_logic; M_AXI_MAC_DMA_awvalid : out std_logic; M_AXI_MAC_DMA_bready : out std_logic; M_AXI_MAC_DMA_md_error : out std_logic; M_AXI_MAC_DMA_rready : out std_logic; M_AXI_MAC_DMA_wlast : out std_logic; M_AXI_MAC_DMA_wvalid : out std_logic; S_AXI_MAC_PKT_ARREADY : out std_logic; S_AXI_MAC_PKT_AWREADY : out std_logic; S_AXI_MAC_PKT_BVALID : out std_logic; S_AXI_MAC_PKT_RVALID : out std_logic; S_AXI_MAC_PKT_WREADY : out std_logic; S_AXI_MAC_REG_ARREADY : out std_logic; S_AXI_MAC_REG_AWREADY : out std_logic; S_AXI_MAC_REG_BVALID : out std_logic; S_AXI_MAC_REG_RVALID : out std_logic; S_AXI_MAC_REG_WREADY : out std_logic; S_AXI_PDI_AP_ARREADY : out std_logic; S_AXI_PDI_AP_AWREADY : out std_logic; S_AXI_PDI_AP_BVALID : out std_logic; S_AXI_PDI_AP_RVALID : out std_logic; S_AXI_PDI_AP_WREADY : out std_logic; S_AXI_PDI_PCP_ARREADY : out std_logic; S_AXI_PDI_PCP_AWREADY : out std_logic; S_AXI_PDI_PCP_BVALID : out std_logic; S_AXI_PDI_PCP_RVALID : out std_logic; S_AXI_PDI_PCP_WREADY : out std_logic; S_AXI_SMP_PCP_ARREADY : out std_logic; S_AXI_SMP_PCP_AWREADY : out std_logic; S_AXI_SMP_PCP_BVALID : out std_logic; S_AXI_SMP_PCP_RVALID : out std_logic; S_AXI_SMP_PCP_WREADY : out std_logic; ap_asyncIrq : out std_logic; ap_asyncIrq_n : out std_logic; ap_syncIrq : out std_logic; ap_syncIrq_n : out std_logic; led_error : out std_logic; led_status : out std_logic; mac_irq : out std_logic; pap_ack : out std_logic; pap_ack_n : out std_logic; pap_data_T : out std_logic; phy0_Rst_n : out std_logic; phy0_SMIClk : out std_logic; phy0_SMIDat_O : out std_logic; phy0_SMIDat_T : out std_logic; phy0_TxEn : out std_logic; phy0_clk : out std_logic; phy1_Rst_n : out std_logic; phy1_SMIClk : out std_logic; phy1_SMIDat_O : out std_logic; phy1_SMIDat_T : out std_logic; phy1_TxEn : out std_logic; phy1_clk : out std_logic; phyMii0_TxEn : out std_logic; phyMii0_TxEr : out std_logic; phyMii1_TxEn : out std_logic; phyMii1_TxEr : out std_logic; phy_Rst_n : out std_logic; phy_SMIClk : out std_logic; phy_SMIDat_O : out std_logic; phy_SMIDat_T : out std_logic; pio_operational : out std_logic; spi_miso : out std_logic; tcp_irq : out std_logic; M_AXI_MAC_DMA_araddr : out std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0); M_AXI_MAC_DMA_arburst : out std_logic_vector(1 downto 0); M_AXI_MAC_DMA_arcache : out std_logic_vector(3 downto 0); M_AXI_MAC_DMA_arlen : out std_logic_vector(7 downto 0); M_AXI_MAC_DMA_arprot : out std_logic_vector(2 downto 0); M_AXI_MAC_DMA_arsize : out std_logic_vector(2 downto 0); M_AXI_MAC_DMA_awaddr : out std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0); M_AXI_MAC_DMA_awburst : out std_logic_vector(1 downto 0); M_AXI_MAC_DMA_awcache : out std_logic_vector(3 downto 0); M_AXI_MAC_DMA_awlen : out std_logic_vector(7 downto 0); M_AXI_MAC_DMA_awprot : out std_logic_vector(2 downto 0); M_AXI_MAC_DMA_awsize : out std_logic_vector(2 downto 0); M_AXI_MAC_DMA_wdata : out std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0); M_AXI_MAC_DMA_wstrb : out std_logic_vector((C_M_AXI_MAC_DMA_DATA_WIDTH/8)-1 downto 0); S_AXI_MAC_PKT_BRESP : out std_logic_vector(1 downto 0); S_AXI_MAC_PKT_RDATA : out std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0); S_AXI_MAC_PKT_RRESP : out std_logic_vector(1 downto 0); S_AXI_MAC_REG_BRESP : out std_logic_vector(1 downto 0); S_AXI_MAC_REG_RDATA : out std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0); S_AXI_MAC_REG_RRESP : out std_logic_vector(1 downto 0); S_AXI_PDI_AP_BRESP : out std_logic_vector(1 downto 0); S_AXI_PDI_AP_RDATA : out std_logic_vector(C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0); S_AXI_PDI_AP_RRESP : out std_logic_vector(1 downto 0); S_AXI_PDI_PCP_BRESP : out std_logic_vector(1 downto 0); S_AXI_PDI_PCP_RDATA : out std_logic_vector(C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0); S_AXI_PDI_PCP_RRESP : out std_logic_vector(1 downto 0); S_AXI_SMP_PCP_BRESP : out std_logic_vector(1 downto 0); S_AXI_SMP_PCP_RDATA : out std_logic_vector(C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0); S_AXI_SMP_PCP_RRESP : out std_logic_vector(1 downto 0); led_gpo : out std_logic_vector(7 downto 0); led_opt : out std_logic_vector(1 downto 0); led_phyAct : out std_logic_vector(1 downto 0); led_phyLink : out std_logic_vector(1 downto 0); pap_data_O : out std_logic_vector(C_PAP_DATA_WIDTH-1 downto 0); pap_gpio_O : out std_logic_vector(1 downto 0); pap_gpio_T : out std_logic_vector(1 downto 0); phy0_TxDat : out std_logic_vector(1 downto 0); phy1_TxDat : out std_logic_vector(1 downto 0); phyMii0_TxDat : out std_logic_vector(3 downto 0); phyMii1_TxDat : out std_logic_vector(3 downto 0); pio_portOutValid : out std_logic_vector(3 downto 0); pio_portio_O : out std_logic_vector(31 downto 0); pio_portio_T : out std_logic_vector(31 downto 0); test_port : out std_logic_vector(255 downto 0) := (others => '0') ); -- Entity declarations -- -- Click here to add additional declarations -- attribute SIGIS : string; -- Entity attributes -- attribute SIGIS of M_AXI_MAC_DMA_aclk : signal is "Clk"; attribute SIGIS of M_AXI_MAC_DMA_aresetn : signal is "Rst"; attribute SIGIS of S_AXI_MAC_PKT_ACLK : signal is "Clk"; attribute SIGIS of S_AXI_MAC_PKT_ARESETN : signal is "Rst"; attribute SIGIS of S_AXI_MAC_REG_ACLK : signal is "Clk"; attribute SIGIS of S_AXI_MAC_REG_ARESETN : signal is "Rst"; attribute SIGIS of S_AXI_PDI_AP_ACLK : signal is "Clk"; attribute SIGIS of S_AXI_PDI_AP_ARESETN : signal is "Rst"; attribute SIGIS of S_AXI_PDI_PCP_ACLK : signal is "Clk"; attribute SIGIS of S_AXI_PDI_PCP_ARESETN : signal is "Rst"; attribute SIGIS of S_AXI_SMP_PCP_ACLK : signal is "Clk"; attribute SIGIS of S_AXI_SMP_PCP_ARESETN : signal is "Rst"; attribute SIGIS of clk100 : signal is "Clk"; attribute SIGIS of phy0_clk : signal is "Clk"; attribute SIGIS of phy1_clk : signal is "Clk"; end axi_powerlink; architecture struct of axi_powerlink is ---- Architecture declarations ----- function get_max( a, b : integer) return integer is begin if a < b then return b; else return a; end if; end get_max; ---- Component declarations ----- component clkXing generic( gCsNum : natural := 2; gDataWidth : natural := 32 ); port ( iArst : in std_logic; iFastClk : in std_logic; iFastCs : in std_logic_vector(gCsNum-1 downto 0); iFastRNW : in std_logic; iSlowClk : in std_logic; iSlowRdAck : in std_logic; iSlowReaddata : in std_logic_vector(gDataWidth-1 downto 0); iSlowWrAck : in std_logic; oFastRdAck : out std_logic; oFastReaddata : out std_logic_vector(gDataWidth-1 downto 0); oFastWrAck : out std_logic; oSlowCs : out std_logic_vector(gCsNum-1 downto 0); oSlowRNW : out std_logic ); end component; component ipif_master_handler generic( C_MAC_DMA_IPIF_AWIDTH : integer := 32; C_MAC_DMA_IPIF_NATIVE_DWIDTH : integer := 32; dma_highadr_g : integer := 31; gen_rx_fifo_g : boolean := true; gen_tx_fifo_g : boolean := true; m_burstcount_width_g : integer := 4 ); port ( Bus2MAC_DMA_MstRd_d : in std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH-1 downto 0); Bus2MAC_DMA_MstRd_eof_n : in std_logic := '1'; Bus2MAC_DMA_MstRd_rem : in std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0); Bus2MAC_DMA_MstRd_sof_n : in std_logic := '1'; Bus2MAC_DMA_MstRd_src_dsc_n : in std_logic := '1'; Bus2MAC_DMA_MstRd_src_rdy_n : in std_logic := '1'; Bus2MAC_DMA_MstWr_dst_dsc_n : in std_logic := '1'; Bus2MAC_DMA_MstWr_dst_rdy_n : in std_logic := '1'; Bus2MAC_DMA_Mst_CmdAck : in std_logic := '0'; Bus2MAC_DMA_Mst_Cmd_Timeout : in std_logic := '0'; Bus2MAC_DMA_Mst_Cmplt : in std_logic := '0'; Bus2MAC_DMA_Mst_Error : in std_logic := '0'; Bus2MAC_DMA_Mst_Rearbitrate : in std_logic := '0'; MAC_DMA_CLK : in std_logic; MAC_DMA_Rst : in std_logic; m_address : in std_logic_vector(dma_highadr_g downto 0); m_burstcount : in std_logic_vector(m_burstcount_width_g-1 downto 0); m_burstcounter : in std_logic_vector(m_burstcount_width_g-1 downto 0); m_byteenable : in std_logic_vector(3 downto 0); m_read : in std_logic := '0'; m_write : in std_logic := '0'; m_writedata : in std_logic_vector(31 downto 0); MAC_DMA2Bus_MstRd_Req : out std_logic := '0'; MAC_DMA2Bus_MstRd_dst_dsc_n : out std_logic := '1'; MAC_DMA2Bus_MstRd_dst_rdy_n : out std_logic := '1'; MAC_DMA2Bus_MstWr_Req : out std_logic := '0'; MAC_DMA2Bus_MstWr_d : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH-1 downto 0); MAC_DMA2Bus_MstWr_eof_n : out std_logic := '1'; MAC_DMA2Bus_MstWr_rem : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0); MAC_DMA2Bus_MstWr_sof_n : out std_logic := '1'; MAC_DMA2Bus_MstWr_src_dsc_n : out std_logic := '1'; MAC_DMA2Bus_MstWr_src_rdy_n : out std_logic := '1'; MAC_DMA2Bus_Mst_Addr : out std_logic_vector(C_MAC_DMA_IPIF_AWIDTH-1 downto 0); MAC_DMA2Bus_Mst_BE : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0); MAC_DMA2Bus_Mst_Length : out std_logic_vector(11 downto 0); MAC_DMA2Bus_Mst_Lock : out std_logic := '0'; MAC_DMA2Bus_Mst_Reset : out std_logic := '0'; MAC_DMA2Bus_Mst_Type : out std_logic := '0'; m_clk : out std_logic; m_readdata : out std_logic_vector(31 downto 0); m_readdatavalid : out std_logic := '0'; m_waitrequest : out std_logic := '1' ); end component; component openMAC_16to32conv generic( bus_address_width : integer := 10; gEndian : string := "little" ); port ( bus_address : in std_logic_vector(bus_address_width-1 downto 0); bus_byteenable : in std_logic_vector(3 downto 0); bus_read : in std_logic; bus_select : in std_logic; bus_write : in std_logic; bus_writedata : in std_logic_vector(31 downto 0); clk : in std_logic; rst : in std_logic; s_readdata : in std_logic_vector(15 downto 0); s_waitrequest : in std_logic; bus_ack_rd : out std_logic; bus_ack_wr : out std_logic; bus_readdata : out std_logic_vector(31 downto 0); s_address : out std_logic_vector(bus_address_width-1 downto 0); s_byteenable : out std_logic_vector(1 downto 0); s_chipselect : out std_logic; s_read : out std_logic; s_write : out std_logic; s_writedata : out std_logic_vector(15 downto 0) ); end component; component powerlink generic( Simulate : integer := 0; endian_g : string := "little"; gNumSmi : integer range 1 to 2 := 2; genABuf1_g : integer := 1; genABuf2_g : integer := 1; genEvent_g : integer := 0; genInternalAp_g : integer := 1; genIoBuf_g : integer := 1; genLedGadget_g : integer := 0; genOnePdiClkDomain_g : integer := 0; genPdi_g : integer := 1; genSimpleIO_g : integer := 0; genSmiIO : integer := 1; genSpiAp_g : integer := 0; genTimeSync_g : integer := 0; gen_dma_observer_g : integer := 1; iAsyBuf1Size_g : integer := 100; iAsyBuf2Size_g : integer := 100; iBufSizeLOG2_g : integer := 10; iBufSize_g : integer := 1024; iPdiRev_g : integer := 21930; iRpdo0BufSize_g : integer := 100; iRpdo1BufSize_g : integer := 100; iRpdo2BufSize_g : integer := 100; iRpdos_g : integer := 3; iTpdoBufSize_g : integer := 100; iTpdos_g : integer := 1; m_burstcount_const_g : integer := 1; m_burstcount_width_g : integer := 4; m_data_width_g : integer := 16; m_rx_burst_size_g : integer := 16; m_rx_fifo_size_g : integer := 16; m_tx_burst_size_g : integer := 16; m_tx_fifo_size_g : integer := 16; papBigEnd_g : integer := 0; papDataWidth_g : integer := 8; papLowAct_g : integer := 0; pcpSysId : integer := 1; pioValLen_g : integer := 50; spiBigEnd_g : integer := 0; spiCPHA_g : integer := 0; spiCPOL_g : integer := 0; use2ndCmpTimer_g : integer := 1; usePulse2ndCmpTimer_g : integer := 1; pulseWidth2ndCmpTimer_g : integer := 9; use2ndPhy_g : integer := 1; useIntPacketBuf_g : integer := 1; useRmii_g : integer := 1; useRxIntPacketBuf_g : integer := 1 ); port ( ap_address : in std_logic_vector(12 downto 0); ap_byteenable : in std_logic_vector(3 downto 0); ap_chipselect : in std_logic; ap_read : in std_logic; ap_write : in std_logic; ap_writedata : in std_logic_vector(31 downto 0); clk50 : in std_logic; clkAp : in std_logic; clkEth : in std_logic; clkPcp : in std_logic; m_clk : in std_logic; m_readdata : in std_logic_vector(m_data_width_g-1 downto 0) := (others => '0'); m_readdatavalid : in std_logic := '0'; m_waitrequest : in std_logic; mac_address : in std_logic_vector(11 downto 0); mac_byteenable : in std_logic_vector(1 downto 0); mac_chipselect : in std_logic; mac_read : in std_logic; mac_write : in std_logic; mac_writedata : in std_logic_vector(15 downto 0); mbf_address : in std_logic_vector(ibufsizelog2_g-3 downto 0); mbf_byteenable : in std_logic_vector(3 downto 0); mbf_chipselect : in std_logic; mbf_read : in std_logic; mbf_write : in std_logic; mbf_writedata : in std_logic_vector(31 downto 0); pap_addr : in std_logic_vector(15 downto 0); pap_be : in std_logic_vector(papDataWidth_g/8-1 downto 0); pap_be_n : in std_logic_vector(papDataWidth_g/8-1 downto 0); pap_cs : in std_logic; pap_cs_n : in std_logic; pap_data_I : in std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0'); pap_gpio_I : in std_logic_vector(1 downto 0) := (others => '0'); pap_rd : in std_logic; pap_rd_n : in std_logic; pap_wr : in std_logic; pap_wr_n : in std_logic; pcp_address : in std_logic_vector(12 downto 0); pcp_byteenable : in std_logic_vector(3 downto 0); pcp_chipselect : in std_logic; pcp_read : in std_logic; pcp_write : in std_logic; pcp_writedata : in std_logic_vector(31 downto 0); phy0_RxDat : in std_logic_vector(1 downto 0); phy0_RxDv : in std_logic; phy0_RxErr : in std_logic; phy0_SMIDat_I : in std_logic := '1'; phy0_link : in std_logic := '0'; phy1_RxDat : in std_logic_vector(1 downto 0) := (others => '0'); phy1_RxDv : in std_logic; phy1_RxErr : in std_logic; phy1_SMIDat_I : in std_logic := '1'; phy1_link : in std_logic := '0'; phyMii0_RxClk : in std_logic; phyMii0_RxDat : in std_logic_vector(3 downto 0) := (others => '0'); phyMii0_RxDv : in std_logic; phyMii0_RxEr : in std_logic; phyMii0_TxClk : in std_logic; phyMii1_RxClk : in std_logic; phyMii1_RxDat : in std_logic_vector(3 downto 0) := (others => '0'); phyMii1_RxDv : in std_logic; phyMii1_RxEr : in std_logic; phyMii1_TxClk : in std_logic; phy_SMIDat_I : in std_logic := '1'; pio_pconfig : in std_logic_vector(3 downto 0); pio_portInLatch : in std_logic_vector(3 downto 0); pio_portio_I : in std_logic_vector(31 downto 0) := (others => '0'); pkt_clk : in std_logic; rst : in std_logic; rstAp : in std_logic; rstPcp : in std_logic; smp_address : in std_logic; smp_byteenable : in std_logic_vector(3 downto 0); smp_read : in std_logic; smp_write : in std_logic; smp_writedata : in std_logic_vector(31 downto 0); spi_clk : in std_logic; spi_mosi : in std_logic; spi_sel_n : in std_logic; tcp_address : in std_logic_vector(1 downto 0); tcp_byteenable : in std_logic_vector(3 downto 0); tcp_chipselect : in std_logic; tcp_read : in std_logic; tcp_write : in std_logic; tcp_writedata : in std_logic_vector(31 downto 0); ap_asyncIrq : out std_logic := '0'; ap_asyncIrq_n : out std_logic := '1'; ap_irq : out std_logic := '0'; ap_irq_n : out std_logic := '1'; ap_readdata : out std_logic_vector(31 downto 0) := (others => '0'); ap_syncIrq : out std_logic := '0'; ap_syncIrq_n : out std_logic := '1'; ap_waitrequest : out std_logic; led_error : out std_logic := '0'; led_gpo : out std_logic_vector(7 downto 0) := (others => '0'); led_opt : out std_logic_vector(1 downto 0) := (others => '0'); led_phyAct : out std_logic_vector(1 downto 0) := (others => '0'); led_phyLink : out std_logic_vector(1 downto 0) := (others => '0'); led_status : out std_logic := '0'; m_address : out std_logic_vector(31 downto 0) := (others => '0'); m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0); m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0); m_byteenable : out std_logic_vector(m_data_width_g/8-1 downto 0) := (others => '0'); m_read : out std_logic := '0'; m_write : out std_logic := '0'; m_writedata : out std_logic_vector(m_data_width_g-1 downto 0) := (others => '0'); mac_irq : out std_logic := '0'; mac_readdata : out std_logic_vector(15 downto 0) := (others => '0'); mac_waitrequest : out std_logic; mbf_readdata : out std_logic_vector(31 downto 0) := (others => '0'); mbf_waitrequest : out std_logic; pap_ack : out std_logic := '0'; pap_ack_n : out std_logic := '1'; pap_data_O : out std_logic_vector(papDataWidth_g-1 downto 0); pap_data_T : out std_logic; pap_gpio_O : out std_logic_vector(1 downto 0); pap_gpio_T : out std_logic_vector(1 downto 0); pcp_readdata : out std_logic_vector(31 downto 0) := (others => '0'); pcp_waitrequest : out std_logic; phy0_Rst_n : out std_logic := '1'; phy0_SMIClk : out std_logic := '0'; phy0_SMIDat_O : out std_logic; phy0_SMIDat_T : out std_logic; phy0_TxDat : out std_logic_vector(1 downto 0) := (others => '0'); phy0_TxEn : out std_logic := '0'; phy1_Rst_n : out std_logic := '1'; phy1_SMIClk : out std_logic := '0'; phy1_SMIDat_O : out std_logic; phy1_SMIDat_T : out std_logic; phy1_TxDat : out std_logic_vector(1 downto 0) := (others => '0'); phy1_TxEn : out std_logic := '0'; phyMii0_TxDat : out std_logic_vector(3 downto 0) := (others => '0'); phyMii0_TxEn : out std_logic := '0'; phyMii0_TxEr : out std_logic := '0'; phyMii1_TxDat : out std_logic_vector(3 downto 0) := (others => '0'); phyMii1_TxEn : out std_logic := '0'; phyMii1_TxEr : out std_logic := '0'; phy_Rst_n : out std_logic := '1'; phy_SMIClk : out std_logic := '0'; phy_SMIDat_O : out std_logic; phy_SMIDat_T : out std_logic; pio_operational : out std_logic := '0'; pio_portOutValid : out std_logic_vector(3 downto 0) := (others => '0'); pio_portio_O : out std_logic_vector(31 downto 0); pio_portio_T : out std_logic_vector(31 downto 0); smp_readdata : out std_logic_vector(31 downto 0) := (others => '0'); smp_waitrequest : out std_logic; spi_miso : out std_logic := '0'; tcp_irq : out std_logic := '0'; tcp_readdata : out std_logic_vector(31 downto 0) := (others => '0'); tcp_waitrequest : out std_logic; pap_data : inout std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0'); pap_gpio : inout std_logic_vector(1 downto 0) := (others => '0'); phy0_SMIDat : inout std_logic := '1'; phy1_SMIDat : inout std_logic := '1'; phy_SMIDat : inout std_logic := '1'; pio_portio : inout std_logic_vector(31 downto 0) := (others => '0') ); end component; component axi_lite_ipif generic( C_ARD_ADDR_RANGE_ARRAY : slv64_array_type := (X"0000_0000_7000_0000",X"0000_0000_7000_00FF",X"0000_0000_7000_0100",X"0000_0000_7000_01FF"); C_ARD_NUM_CE_ARRAY : integer_array_type := (4,12); C_DPHASE_TIMEOUT : integer range 0 to 512 := 8; C_FAMILY : string := "virtex6"; C_S_AXI_ADDR_WIDTH : integer := 32; C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32; C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0) := X"000001FF"; C_USE_WSTRB : integer := 0 ); port ( IP2Bus_Data : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); IP2Bus_Error : in std_logic; IP2Bus_RdAck : in std_logic; IP2Bus_WrAck : in std_logic; S_AXI_ACLK : in std_logic; S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_ARESETN : in std_logic; S_AXI_ARVALID : in std_logic; S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_BREADY : in std_logic; S_AXI_RREADY : in std_logic; S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); S_AXI_WVALID : in std_logic; Bus2IP_Addr : out std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); Bus2IP_BE : out std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); Bus2IP_CS : out std_logic_vector((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0); Bus2IP_Clk : out std_logic; Bus2IP_Data : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); Bus2IP_RNW : out std_logic; Bus2IP_RdCE : out std_logic_vector(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0); Bus2IP_Resetn : out std_logic; Bus2IP_WrCE : out std_logic_vector(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0); S_AXI_ARREADY : out std_logic; S_AXI_AWREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_WREADY : out std_logic ); end component; component axi_master_burst generic( C_ADDR_PIPE_DEPTH : integer range 1 to 14 := 1; C_FAMILY : string := "virtex6"; C_LENGTH_WIDTH : integer range 12 to 20 := 12; C_MAX_BURST_LEN : integer range 16 to 256 := 16; C_M_AXI_ADDR_WIDTH : integer range 32 to 32 := 32; C_M_AXI_DATA_WIDTH : integer range 32 to 256 := 32; C_NATIVE_DATA_WIDTH : integer range 32 to 128 := 32 ); port ( ip2bus_mst_addr : in std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0); ip2bus_mst_be : in std_logic_vector((C_NATIVE_DATA_WIDTH/8)-1 downto 0); ip2bus_mst_length : in std_logic_vector(C_LENGTH_WIDTH-1 downto 0); ip2bus_mst_lock : in std_logic; ip2bus_mst_reset : in std_logic; ip2bus_mst_type : in std_logic; ip2bus_mstrd_dst_dsc_n : in std_logic; ip2bus_mstrd_dst_rdy_n : in std_logic; ip2bus_mstrd_req : in std_logic; ip2bus_mstwr_d : in std_logic_vector(C_NATIVE_DATA_WIDTH-1 downto 0); ip2bus_mstwr_eof_n : in std_logic; ip2bus_mstwr_rem : in std_logic_vector((C_NATIVE_DATA_WIDTH/8)-1 downto 0); ip2bus_mstwr_req : in std_logic; ip2bus_mstwr_sof_n : in std_logic; ip2bus_mstwr_src_dsc_n : in std_logic; ip2bus_mstwr_src_rdy_n : in std_logic; m_axi_aclk : in std_logic; m_axi_aresetn : in std_logic; m_axi_arready : in std_logic; m_axi_awready : in std_logic; m_axi_bresp : in std_logic_vector(1 downto 0); m_axi_bvalid : in std_logic; m_axi_rdata : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0); m_axi_rlast : in std_logic; m_axi_rresp : in std_logic_vector(1 downto 0); m_axi_rvalid : in std_logic; m_axi_wready : in std_logic; bus2ip_mst_cmd_timeout : out std_logic; bus2ip_mst_cmdack : out std_logic; bus2ip_mst_cmplt : out std_logic; bus2ip_mst_error : out std_logic; bus2ip_mst_rearbitrate : out std_logic; bus2ip_mstrd_d : out std_logic_vector(C_NATIVE_DATA_WIDTH-1 downto 0); bus2ip_mstrd_eof_n : out std_logic; bus2ip_mstrd_rem : out std_logic_vector((C_NATIVE_DATA_WIDTH/8)-1 downto 0); bus2ip_mstrd_sof_n : out std_logic; bus2ip_mstrd_src_dsc_n : out std_logic; bus2ip_mstrd_src_rdy_n : out std_logic; bus2ip_mstwr_dst_dsc_n : out std_logic; bus2ip_mstwr_dst_rdy_n : out std_logic; m_axi_araddr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0); m_axi_arburst : out std_logic_vector(1 downto 0); m_axi_arcache : out std_logic_vector(3 downto 0); m_axi_arlen : out std_logic_vector(7 downto 0); m_axi_arprot : out std_logic_vector(2 downto 0); m_axi_arsize : out std_logic_vector(2 downto 0); m_axi_arvalid : out std_logic; m_axi_awaddr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0); m_axi_awburst : out std_logic_vector(1 downto 0); m_axi_awcache : out std_logic_vector(3 downto 0); m_axi_awlen : out std_logic_vector(7 downto 0); m_axi_awprot : out std_logic_vector(2 downto 0); m_axi_awsize : out std_logic_vector(2 downto 0); m_axi_awvalid : out std_logic; m_axi_bready : out std_logic; m_axi_rready : out std_logic; m_axi_wdata : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0); m_axi_wlast : out std_logic; m_axi_wstrb : out std_logic_vector((C_M_AXI_DATA_WIDTH/8)-1 downto 0); m_axi_wvalid : out std_logic; md_error : out std_logic ); end component; ---- Architecture declarations ----- constant C_ADDR_PAD_ZERO : std_logic_vector(31 downto 0) := (others => '0'); -- openMAC REG PLB Slave constant C_MAC_REG_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_MAC_REG_RNG0_BASEADDR; constant C_MAC_REG_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_MAC_REG_RNG0_HIGHADDR; constant C_MAC_REG_MINSIZE : std_logic_vector(31 downto 0) := conv_std_logic_vector(get_max(conv_integer(C_S_AXI_MAC_REG_RNG0_HIGHADDR), conv_integer(C_S_AXI_MAC_REG_RNG1_HIGHADDR)), 32); -- openMAC CMP PLB Slave constant C_MAC_CMP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_MAC_REG_RNG1_BASEADDR; constant C_MAC_CMP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_MAC_REG_RNG1_HIGHADDR; -- openMAC PKT PLB Slave constant C_MAC_PKT_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_MAC_PKT_BASEADDR; constant C_MAC_PKT_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_MAC_PKT_HIGHADDR; constant C_MAC_PKT_MINSIZE : std_logic_vector(31 downto 0) := C_S_AXI_MAC_PKT_HIGHADDR; -- SimpleIO Slave constant C_SMP_PCP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_SMP_PCP_BASEADDR; constant C_SMP_PCP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_SMP_PCP_HIGHADDR; constant C_SMP_PCP_MINSIZE : std_logic_vector(31 downto 0) := C_S_AXI_SMP_PCP_HIGHADDR; -- PDI PCP Slave constant C_PDI_PCP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_PDI_PCP_BASEADDR; constant C_PDI_PCP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_PDI_PCP_HIGHADDR; constant C_PDI_PCP_MINSIZE : std_logic_vector(31 downto 0) := C_S_AXI_PDI_PCP_HIGHADDR; -- AP PCP Slave constant C_PDI_AP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_PDI_AP_BASEADDR; constant C_PDI_AP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_PDI_AP_HIGHADDR; constant C_PDI_AP_MINSIZE : std_logic_vector(31 downto 0) := C_S_AXI_PDI_AP_HIGHADDR; -- POWERLINK IP-core constant C_MAC_PKT_EN : boolean := C_TX_INT_PKT or C_RX_INT_PKT; constant C_MAC_PKT_RX_EN : boolean := C_RX_INT_PKT; constant C_DMA_EN : boolean := not C_TX_INT_PKT or not C_RX_INT_PKT; constant C_PKT_BUF_EN : boolean := C_MAC_PKT_EN; constant C_M_BURSTCOUNT_WIDTH : integer := integer(ceil(log2(real(get_max(C_MAC_DMA_BURST_SIZE_RX,C_MAC_DMA_BURST_SIZE_TX)/4)))) + 1; --in dwords constant C_M_FIFO_SIZE_RX : integer := C_MAC_DMA_FIFO_SIZE_RX/4; --in dwords constant C_M_FIFO_SIZE_TX : integer := C_MAC_DMA_FIFO_SIZE_TX/4; --in dwords ---- Constants ----- constant VCC_CONSTANT : std_logic := '1'; constant GND_CONSTANT : std_logic := '0'; ---- Signal declarations used on the diagram ---- signal ap_chipselect : std_logic; signal ap_read : std_logic; signal ap_waitrequest : std_logic; signal ap_write : std_logic; signal bus2MAC_DMA_mstrd_eof_n : std_logic; signal bus2MAC_DMA_mstrd_sof_n : std_logic; signal bus2MAC_DMA_mstrd_src_dsc_n : std_logic; signal bus2MAC_DMA_mstrd_src_rdy_n : std_logic; signal bus2MAC_DMA_mstwr_dst_dsc_n : std_logic; signal bus2MAC_DMA_mstwr_dst_rdy_n : std_logic; signal bus2MAC_DMA_mst_cmdack : std_logic; signal bus2MAC_DMA_mst_cmd_timeout : std_logic; signal bus2MAC_DMA_mst_cmplt : std_logic; signal bus2MAC_DMA_mst_error : std_logic; signal bus2MAC_DMA_mst_rearbitrate : std_logic; signal Bus2MAC_PKT_Clk : std_logic; signal Bus2MAC_PKT_Reset : std_logic := '0'; signal Bus2MAC_PKT_Resetn : std_logic; signal Bus2MAC_PKT_RNW : std_logic; signal Bus2MAC_REG_Clk : std_logic; signal Bus2MAC_REG_Reset : std_logic := '0'; signal Bus2MAC_REG_Resetn : std_logic; signal Bus2MAC_REG_RNW : std_logic; signal Bus2MAC_REG_RNW_fast : std_logic; signal Bus2MAC_REG_RNW_n : std_logic; signal Bus2PDI_AP_Clk : std_logic; signal Bus2PDI_AP_Reset : std_logic := '0'; signal Bus2PDI_AP_Resetn : std_logic; signal Bus2PDI_AP_RNW : std_logic; signal Bus2PDI_PCP_Clk : std_logic; signal Bus2PDI_PCP_Reset : std_logic := '0'; signal Bus2PDI_PCP_Resetn : std_logic; signal Bus2PDI_PCP_RNW : std_logic; signal Bus2SMP_PCP_Clk : std_logic; signal Bus2SMP_PCP_Reset : std_logic := '0'; signal Bus2SMP_PCP_Resetn : std_logic; signal Bus2SMP_PCP_RNW : std_logic; signal clkAp : std_logic; signal clkPcp : std_logic; signal GND : std_logic; signal IP2Bus_Error_s : std_logic; signal IP2Bus_RdAck_fast : std_logic; signal IP2Bus_RdAck_s : std_logic; signal IP2Bus_WrAck_fast : std_logic; signal IP2Bus_WrAck_s : std_logic; signal mac_chipselect : std_logic; signal MAC_CMP2Bus_Error : std_logic; signal MAC_CMP2Bus_RdAck : std_logic; signal MAC_CMP2Bus_WrAck : std_logic; signal MAC_DMA2bus_mstrd_dst_dsc_n : std_logic; signal MAC_DMA2bus_mstrd_dst_rdy_n : std_logic; signal MAC_DMA2bus_mstrd_req : std_logic; signal MAC_DMA2bus_mstwr_eof_n : std_logic; signal MAC_DMA2bus_mstwr_req : std_logic; signal MAC_DMA2bus_mstwr_sof_n : std_logic; signal MAC_DMA2bus_mstwr_src_dsc_n : std_logic; signal MAC_DMA2bus_mstwr_src_rdy_n : std_logic; signal MAC_DMA2bus_mst_lock : std_logic; signal MAC_DMA2bus_mst_reset : std_logic; signal MAC_DMA2bus_mst_type : std_logic; signal MAC_DMA_areset : std_logic; signal mac_irq_s : std_logic; signal MAC_PKT2Bus_Error : std_logic; signal MAC_PKT2Bus_RdAck : std_logic; signal MAC_PKT2Bus_WrAck : std_logic; signal mac_read : std_logic; signal MAC_REG2Bus_Error : std_logic; signal MAC_REG2Bus_RdAck : std_logic; signal MAC_REG2Bus_WrAck : std_logic; signal mac_waitrequest : std_logic; signal mac_write : std_logic; signal mbf_chipselect : std_logic; signal mbf_read : std_logic; signal mbf_waitrequest : std_logic; signal mbf_write : std_logic; signal m_clk : std_logic; signal m_read : std_logic; signal m_readdatavalid : std_logic; signal m_waitrequest : std_logic; signal m_write : std_logic; signal NET38418 : std_ulogic; signal NET38470 : std_ulogic; signal pcp_chipselect : std_logic; signal pcp_read : std_logic; signal pcp_waitrequest : std_logic; signal pcp_write : std_logic; signal PDI_AP2Bus_Error : std_logic; signal PDI_AP2Bus_RdAck : std_logic; signal PDI_AP2Bus_WrAck : std_logic; signal PDI_PCP2Bus_Error : std_logic; signal PDI_PCP2Bus_RdAck : std_logic; signal PDI_PCP2Bus_WrAck : std_logic; signal pkt_clk : std_logic; signal rst : std_logic := '0'; signal rstAp : std_logic := '0'; signal rstPcp : std_logic := '0'; signal smp_address : std_logic; signal smp_chipselect : std_logic; signal SMP_PCP2Bus_Error : std_logic; signal SMP_PCP2Bus_RdAck : std_logic; signal SMP_PCP2Bus_WrAck : std_logic; signal smp_read : std_logic; signal smp_waitrequest : std_logic; signal smp_write : std_logic; signal tcp_chipselect : std_logic; signal tcp_irq_s : std_logic; signal tcp_read : std_logic; signal tcp_waitrequest : std_logic; signal tcp_write : std_logic; signal VCC : std_logic; signal ap_address : std_logic_vector (12 downto 0); signal ap_byteenable : std_logic_vector (3 downto 0); signal ap_readdata : std_logic_vector (31 downto 0); signal ap_writedata : std_logic_vector (31 downto 0); signal bus2MAC_DMA_mstrd_d : std_logic_vector (C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0); signal bus2MAC_DMA_mstrd_rem : std_logic_vector ((C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0); signal Bus2MAC_PKT_Addr : std_logic_vector (C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0); signal Bus2MAC_PKT_BE : std_logic_vector ((C_S_AXI_MAC_PKT_DATA_WIDTH/8)-1 downto 0); signal Bus2MAC_PKT_CS : std_logic_vector (0 downto 0); signal Bus2MAC_PKT_Data : std_logic_vector (C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0); signal Bus2MAC_REG_Addr : std_logic_vector (C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0); signal Bus2MAC_REG_BE : std_logic_vector ((C_S_AXI_MAC_REG_DATA_WIDTH/8)-1 downto 0); signal Bus2MAC_REG_CS : std_logic_vector (1 downto 0); signal Bus2MAC_REG_CS_fast : std_logic_vector (1 downto 0); signal Bus2MAC_REG_Data : std_logic_vector (C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0); signal Bus2PDI_AP_Addr : std_logic_vector (C_S_AXI_PDI_AP_ADDR_WIDTH-1 downto 0); signal Bus2PDI_AP_BE : std_logic_vector ((C_S_AXI_PDI_AP_DATA_WIDTH/8)-1 downto 0); signal Bus2PDI_AP_CS : std_logic_vector (0 downto 0); signal Bus2PDI_AP_Data : std_logic_vector (C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0); signal Bus2PDI_PCP_Addr : std_logic_vector (C_S_AXI_PDI_PCP_ADDR_WIDTH-1 downto 0); signal Bus2PDI_PCP_BE : std_logic_vector ((C_S_AXI_PDI_PCP_DATA_WIDTH/8)-1 downto 0); signal Bus2PDI_PCP_CS : std_logic_vector (0 downto 0); signal Bus2PDI_PCP_Data : std_logic_vector (C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0); signal Bus2SMP_PCP_Addr : std_logic_vector (C_S_AXI_SMP_PCP_ADDR_WIDTH-1 downto 0); signal Bus2SMP_PCP_BE : std_logic_vector ((C_S_AXI_SMP_PCP_DATA_WIDTH/8)-1 downto 0); signal Bus2SMP_PCP_CS : std_logic_vector (0 downto 0); signal Bus2SMP_PCP_Data : std_logic_vector (C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0); signal IP2Bus_Data_fast : std_logic_vector (C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0); signal IP2Bus_Data_s : std_logic_vector (C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0); signal mac_address : std_logic_vector (11 downto 0); signal mac_address_full : std_logic_vector (C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0); signal mac_byteenable : std_logic_vector (1 downto 0); signal MAC_CMP2Bus_Data : std_logic_vector (C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0); signal MAC_DMA2Bus_MstWr_d : std_logic_vector (C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0); signal MAC_DMA2bus_mstwr_rem : std_logic_vector ((C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0); signal MAC_DMA2bus_mst_addr : std_logic_vector (C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0); signal MAC_DMA2bus_mst_be : std_logic_vector ((C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0); signal MAC_DMA2bus_mst_length : std_logic_vector (C_M_AXI_MAC_DMA_LENGTH_WIDTH-1 downto 0); signal MAC_PKT2Bus_Data : std_logic_vector (C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0); signal mac_readdata : std_logic_vector (15 downto 0); signal MAC_REG2Bus_Data : std_logic_vector (C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0); signal mac_writedata : std_logic_vector (15 downto 0); signal mbf_address : std_logic_vector (C_MAC_PKT_SIZE_LOG2-3 downto 0); signal mbf_byteenable : std_logic_vector (3 downto 0); signal mbf_readdata : std_logic_vector (31 downto 0); signal mbf_writedata : std_logic_vector (31 downto 0); signal m_address : std_logic_vector (31 downto 0); signal m_burstcount : std_logic_vector (C_M_BURSTCOUNT_WIDTH-1 downto 0); signal m_burstcounter : std_logic_vector (C_M_BURSTCOUNT_WIDTH-1 downto 0); signal m_byteenable : std_logic_vector (3 downto 0); signal m_readdata : std_logic_vector (31 downto 0); signal m_writedata : std_logic_vector (31 downto 0); signal pcp_address : std_logic_vector (12 downto 0); signal pcp_byteenable : std_logic_vector (3 downto 0); signal pcp_readdata : std_logic_vector (31 downto 0); signal pcp_writedata : std_logic_vector (31 downto 0); signal PDI_AP2Bus_Data : std_logic_vector (C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0); signal PDI_PCP2Bus_Data : std_logic_vector (C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0); signal smp_byteenable : std_logic_vector (3 downto 0); signal SMP_PCP2Bus_Data : std_logic_vector (C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0); signal smp_readdata : std_logic_vector (31 downto 0); signal smp_writedata : std_logic_vector (31 downto 0); signal tcp_address : std_logic_vector (1 downto 0); signal tcp_byteenable : std_logic_vector (3 downto 0); signal tcp_readdata : std_logic_vector (31 downto 0); signal tcp_writedata : std_logic_vector (31 downto 0); begin ---- User Signal Assignments ---- -- connect mac reg with mac cmp or reg output signals with Bus2MAC_REG_CS select IP2Bus_Data_s <= MAC_CMP2Bus_Data when "01", MAC_REG2Bus_Data when others; --"10" and others are decoded to MAC_REG IP2Bus_WrAck_s <= MAC_REG2Bus_WrAck or MAC_CMP2Bus_WrAck; IP2Bus_RdAck_s <= MAC_REG2Bus_RdAck or MAC_CMP2Bus_RdAck; IP2Bus_Error_s <= MAC_REG2Bus_Error or MAC_CMP2Bus_Error; mac_address <= mac_address_full(mac_address'range); --mac_cmp assignments ---cmp_clk <= Bus2MAC_CMP_Clk; tcp_writedata <= Bus2MAC_REG_Data; tcp_read <= Bus2MAC_REG_RNW; tcp_write <= not Bus2MAC_REG_RNW; tcp_chipselect <= Bus2MAC_REG_CS(0); tcp_byteenable <= Bus2MAC_REG_BE; tcp_address <= Bus2MAC_REG_Addr(3 downto 2); MAC_CMP2Bus_Data <= tcp_readdata; MAC_CMP2Bus_RdAck <= tcp_chipselect and tcp_read and not tcp_waitrequest; MAC_CMP2Bus_WrAck <= tcp_chipselect and tcp_write and not tcp_waitrequest; MAC_CMP2Bus_Error <= '0'; --mac_pkt assignments pkt_clk <= Bus2MAC_PKT_Clk; Bus2MAC_PKT_Reset <= not Bus2MAC_PKT_Resetn; mbf_writedata <= Bus2MAC_PKT_Data; -- Bus2MAC_PKT_Data(7 downto 0) & Bus2MAC_PKT_Data(15 downto 8) & -- Bus2MAC_PKT_Data(23 downto 16) & Bus2MAC_PKT_Data(31 downto 24); mbf_read <= Bus2MAC_PKT_RNW; mbf_write <= not Bus2MAC_PKT_RNW; mbf_chipselect <= Bus2MAC_PKT_CS(0); mbf_byteenable <= Bus2MAC_PKT_BE; mbf_address <= Bus2MAC_PKT_Addr(C_MAC_PKT_SIZE_LOG2-1 downto 2); MAC_PKT2Bus_Data <= mbf_readdata; MAC_PKT2Bus_RdAck <= mbf_chipselect and mbf_read and not mbf_waitrequest; MAC_PKT2Bus_WrAck <= mbf_chipselect and mbf_write and not mbf_waitrequest; MAC_PKT2Bus_Error <= '0'; --test_port --test_port(181 downto 179) <= mac_chipselect & mac_write & mac_read; --test_port(178) <= mac_waitrequest; --test_port(177 downto 176) <= mac_byteenable; -- --test_port(171 downto 160) <= mac_address; --test_port(159 downto 144) <= mac_writedata; --test_port(143 downto 128) <= mac_readdata; -- --test_port(104 downto 102) <= Bus2MAC_REG_CS & Bus2MAC_REG_RNW; --test_port(101 downto 100) <= IP2Bus_WrAck_s & IP2Bus_RdAck_s; --test_port(99 downto 96) <= Bus2MAC_REG_BE; -- --test_port(95 downto 64) <= Bus2MAC_REG_Addr; --test_port(63 downto 32) <= Bus2MAC_REG_Data; --test_port(31 downto 0) <= IP2Bus_Data_s; test_port(255 downto 251) <= m_read & m_write & m_waitrequest & m_readdatavalid & MAC_DMA2Bus_Mst_Type; test_port(244 downto 240) <= MAC_DMA2Bus_MstWr_Req & MAC_DMA2Bus_MstWr_sof_n & MAC_DMA2Bus_MstWr_eof_n & MAC_DMA2Bus_MstWr_src_rdy_n & Bus2MAC_DMA_MstWr_dst_rdy_n; test_port(234 downto 230) <= MAC_DMA2Bus_MstRd_Req & Bus2MAC_DMA_MstRd_sof_n & Bus2MAC_DMA_MstRd_eof_n & Bus2MAC_DMA_MstRd_src_rdy_n & MAC_DMA2Bus_MstRd_dst_rdy_n; test_port(142 downto 140) <= Bus2MAC_DMA_Mst_Cmplt & Bus2MAC_DMA_Mst_Error & Bus2MAC_DMA_Mst_Cmd_Timeout; test_port(MAC_DMA2Bus_Mst_Length'length+120-1 downto 120) <= MAC_DMA2Bus_Mst_Length; test_port(m_burstcount'length+110-1 downto 110) <= m_burstcount; test_port(m_burstcounter'length+96-1 downto 96) <= m_burstcounter; test_port(95 downto 64) <= m_address; test_port(63 downto 32) <= m_writedata; test_port(31 downto 0) <= m_readdata; ---- Component instantiations ---- MAC_REG_16to32 : openMAC_16to32conv generic map ( bus_address_width => C_S_AXI_MAC_REG_ADDR_WIDTH, gEndian => "little" ) port map( bus_ack_rd => MAC_REG2Bus_RdAck, bus_ack_wr => MAC_REG2Bus_WrAck, bus_address => Bus2MAC_REG_Addr( C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0 ), bus_byteenable => Bus2MAC_REG_BE( (C_S_AXI_MAC_REG_DATA_WIDTH/8)-1 downto 0 ), bus_read => Bus2MAC_REG_RNW, bus_readdata => MAC_REG2Bus_Data( C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0 ), bus_select => Bus2MAC_REG_CS(1), bus_write => Bus2MAC_REG_RNW_n, bus_writedata => Bus2MAC_REG_Data( C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0 ), clk => clk50, rst => Bus2MAC_REG_Reset, s_address => mac_address_full( C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0 ), s_byteenable => mac_byteenable, s_chipselect => mac_chipselect, s_read => mac_read, s_readdata => mac_readdata, s_waitrequest => mac_waitrequest, s_write => mac_write, s_writedata => mac_writedata ); MAC_REG_AXI_SINGLE_SLAVE : axi_lite_ipif generic map ( C_ARD_ADDR_RANGE_ARRAY => (C_MAC_REG_BASE,C_MAC_REG_HIGH,C_MAC_CMP_BASE,C_MAC_CMP_HIGH), C_ARD_NUM_CE_ARRAY => (1,1), C_DPHASE_TIMEOUT => C_S_AXI_MAC_REG_DPHASE_TIMEOUT, C_FAMILY => C_FAMILY, C_S_AXI_ADDR_WIDTH => C_S_AXI_MAC_REG_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_MAC_REG_DATA_WIDTH, C_S_AXI_MIN_SIZE => C_MAC_REG_MINSIZE, C_USE_WSTRB => C_S_AXI_MAC_REG_USE_WSTRB ) port map( Bus2IP_Addr => Bus2MAC_REG_Addr( C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0 ), Bus2IP_BE => Bus2MAC_REG_BE( (C_S_AXI_MAC_REG_DATA_WIDTH/8)-1 downto 0 ), Bus2IP_CS => Bus2MAC_REG_CS_fast( 1 downto 0 ), Bus2IP_Clk => Bus2MAC_REG_Clk, Bus2IP_Data => Bus2MAC_REG_Data( C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0 ), Bus2IP_RNW => Bus2MAC_REG_RNW_fast, Bus2IP_RdCE => open, Bus2IP_Resetn => Bus2MAC_REG_Resetn, Bus2IP_WrCE => open, IP2Bus_Data => IP2Bus_Data_fast( C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0 ), IP2Bus_Error => IP2Bus_Error_s, IP2Bus_RdAck => IP2Bus_RdAck_fast, IP2Bus_WrAck => IP2Bus_WrAck_fast, S_AXI_ACLK => S_AXI_MAC_REG_ACLK, S_AXI_ARADDR => S_AXI_MAC_REG_ARADDR( C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0 ), S_AXI_ARESETN => S_AXI_MAC_REG_ARESETN, S_AXI_ARREADY => S_AXI_MAC_REG_ARREADY, S_AXI_ARVALID => S_AXI_MAC_REG_ARVALID, S_AXI_AWADDR => S_AXI_MAC_REG_AWADDR( C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0 ), S_AXI_AWREADY => S_AXI_MAC_REG_AWREADY, S_AXI_AWVALID => S_AXI_MAC_REG_AWVALID, S_AXI_BREADY => S_AXI_MAC_REG_BREADY, S_AXI_BRESP => S_AXI_MAC_REG_BRESP, S_AXI_BVALID => S_AXI_MAC_REG_BVALID, S_AXI_RDATA => S_AXI_MAC_REG_RDATA( C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0 ), S_AXI_RREADY => S_AXI_MAC_REG_RREADY, S_AXI_RRESP => S_AXI_MAC_REG_RRESP, S_AXI_RVALID => S_AXI_MAC_REG_RVALID, S_AXI_WDATA => S_AXI_MAC_REG_WDATA( C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0 ), S_AXI_WREADY => S_AXI_MAC_REG_WREADY, S_AXI_WSTRB => S_AXI_MAC_REG_WSTRB( (C_S_AXI_MAC_REG_DATA_WIDTH/8)-1 downto 0 ), S_AXI_WVALID => S_AXI_MAC_REG_WVALID ); THE_POWERLINK_IP_CORE : powerlink generic map ( Simulate => booleanToInteger(false), endian_g => "little", gNumSmi => C_NUM_SMI, genABuf1_g => booleanToInteger(C_PDI_GEN_ASYNC_BUF_0), genABuf2_g => booleanToInteger(C_PDI_GEN_ASYNC_BUF_1), genEvent_g => booleanToInteger(C_PDI_GEN_EVENT), genInternalAp_g => booleanToInteger(C_GEN_AXI_BUS_IF), genIoBuf_g => booleanToInteger(false), genLedGadget_g => booleanToInteger(C_PDI_GEN_LED), genOnePdiClkDomain_g => booleanToInteger(false), genPdi_g => booleanToInteger(C_GEN_PDI), genSimpleIO_g => booleanToInteger(C_GEN_SIMPLE_IO), genSmiIO => booleanToInteger(false), genSpiAp_g => booleanToInteger(C_GEN_SPI_IF), genTimeSync_g => booleanToInteger(C_PDI_GEN_TIME_SYNC), gen_dma_observer_g => booleanToInteger(C_OBSERVER_ENABLE), iAsyBuf1Size_g => C_PDI_ASYNC_BUF_0, iAsyBuf2Size_g => C_PDI_ASYNC_BUF_1, iBufSizeLOG2_g => C_MAC_PKT_SIZE_LOG2, iBufSize_g => C_MAC_PKT_SIZE, iPdiRev_g => C_PDI_REV, iRpdo0BufSize_g => C_RPDO_0_BUF_SIZE, iRpdo1BufSize_g => C_RPDO_1_BUF_SIZE, iRpdo2BufSize_g => C_RPDO_2_BUF_SIZE, iRpdos_g => C_NUM_RPDO, iTpdoBufSize_g => C_TPDO_BUF_SIZE, iTpdos_g => C_NUM_TPDO, m_burstcount_const_g => booleanToInteger(true), m_burstcount_width_g => C_M_BURSTCOUNT_WIDTH, m_data_width_g => 32, m_rx_burst_size_g => C_MAC_DMA_BURST_SIZE_RX/4, m_rx_fifo_size_g => C_M_FIFO_SIZE_RX, m_tx_burst_size_g => C_MAC_DMA_BURST_SIZE_TX/4, m_tx_fifo_size_g => C_M_FIFO_SIZE_TX, papBigEnd_g => booleanToInteger(false), papDataWidth_g => C_PAP_DATA_WIDTH, papLowAct_g => booleanToInteger(C_PAP_LOW_ACT), pcpSysId => C_PCP_SYS_ID, pioValLen_g => C_PIO_VAL_LENGTH, pulseWidth2ndCmpTimer_g => C_PULSE_WIDTH_2nd_CMP_TIMER, spiBigEnd_g => booleanToInteger(false), spiCPHA_g => booleanToInteger(C_SPI_CPHA), spiCPOL_g => booleanToInteger(C_SPI_CPOL), use2ndCmpTimer_g => booleanToInteger(C_MAC_GEN_SECOND_TIMER), use2ndPhy_g => booleanToInteger(C_USE_2ND_PHY), useIntPacketBuf_g => booleanToInteger(C_MAC_PKT_EN), usePulse2ndCmpTimer_g => booleanToInteger(C_USE_PULSE_2nd_CMP_TIMER), useRmii_g => booleanToInteger(C_USE_RMII), useRxIntPacketBuf_g => booleanToInteger(C_MAC_PKT_RX_EN) ) port map( ap_address => ap_address, ap_asyncIrq => ap_asyncIrq, ap_asyncIrq_n => ap_asyncIrq_n, ap_byteenable => ap_byteenable, ap_chipselect => ap_chipselect, ap_irq => open, ap_irq_n => open, ap_read => ap_read, ap_readdata => ap_readdata, ap_syncIrq => ap_syncIrq, ap_syncIrq_n => ap_syncIrq_n, ap_waitrequest => ap_waitrequest, ap_write => ap_write, ap_writedata => ap_writedata, clk50 => clk50, clkAp => clkAp, clkEth => clk100, clkPcp => clkPcp, led_error => led_error, led_gpo => led_gpo, led_opt => led_opt, led_phyAct => led_phyAct, led_phyLink => led_phyLink, led_status => led_status, m_address => m_address, m_burstcount => m_burstcount( C_M_BURSTCOUNT_WIDTH-1 downto 0 ), m_burstcounter => m_burstcounter( C_M_BURSTCOUNT_WIDTH-1 downto 0 ), m_byteenable => m_byteenable( 3 downto 0 ), m_clk => m_clk, m_read => m_read, m_readdata => m_readdata( 31 downto 0 ), m_readdatavalid => m_readdatavalid, m_waitrequest => m_waitrequest, m_write => m_write, m_writedata => m_writedata( 31 downto 0 ), mac_address => mac_address, mac_byteenable => mac_byteenable, mac_chipselect => mac_chipselect, mac_irq => mac_irq_s, mac_read => mac_read, mac_readdata => mac_readdata, mac_waitrequest => mac_waitrequest, mac_write => mac_write, mac_writedata => mac_writedata, mbf_address => mbf_address( C_MAC_PKT_SIZE_LOG2-3 downto 0 ), mbf_byteenable => mbf_byteenable, mbf_chipselect => mbf_chipselect, mbf_read => mbf_read, mbf_readdata => mbf_readdata, mbf_waitrequest => mbf_waitrequest, mbf_write => mbf_write, mbf_writedata => mbf_writedata, pap_ack => pap_ack, pap_ack_n => pap_ack_n, pap_addr => pap_addr, pap_be => pap_be( C_PAP_DATA_WIDTH/8-1 downto 0 ), pap_be_n => pap_be_n( C_PAP_DATA_WIDTH/8-1 downto 0 ), pap_cs => pap_cs, pap_cs_n => pap_cs_n, pap_data => open, pap_data_I => pap_data_I( C_PAP_DATA_WIDTH-1 downto 0 ), pap_data_O => pap_data_O( C_PAP_DATA_WIDTH-1 downto 0 ), pap_data_T => pap_data_T, pap_gpio => open, pap_gpio_I => pap_gpio_I, pap_gpio_O => pap_gpio_O, pap_gpio_T => pap_gpio_T, pap_rd => pap_rd, pap_rd_n => pap_rd_n, pap_wr => pap_wr, pap_wr_n => pap_wr_n, pcp_address => pcp_address, pcp_byteenable => pcp_byteenable, pcp_chipselect => pcp_chipselect, pcp_read => pcp_read, pcp_readdata => pcp_readdata, pcp_waitrequest => pcp_waitrequest, pcp_write => pcp_write, pcp_writedata => pcp_writedata, phy0_Rst_n => phy0_Rst_n, phy0_RxDat => phy0_RxDat, phy0_RxDv => phy0_RxDv, phy0_RxErr => phy0_RxErr, phy0_SMIClk => phy0_SMIClk, phy0_SMIDat => open, phy0_SMIDat_I => phy0_SMIDat_I, phy0_SMIDat_O => phy0_SMIDat_O, phy0_SMIDat_T => phy0_SMIDat_T, phy0_TxDat => phy0_TxDat, phy0_TxEn => phy0_TxEn, phy0_link => phy0_link, phy1_Rst_n => phy1_Rst_n, phy1_RxDat => phy1_RxDat, phy1_RxDv => phy1_RxDv, phy1_RxErr => phy1_RxErr, phy1_SMIClk => phy1_SMIClk, phy1_SMIDat => open, phy1_SMIDat_I => phy1_SMIDat_I, phy1_SMIDat_O => phy1_SMIDat_O, phy1_SMIDat_T => phy1_SMIDat_T, phy1_TxDat => phy1_TxDat, phy1_TxEn => phy1_TxEn, phy1_link => phy1_link, phyMii0_RxClk => phyMii0_RxClk, phyMii0_RxDat => phyMii0_RxDat, phyMii0_RxDv => phyMii0_RxDv, phyMii0_RxEr => phyMii0_RxEr, phyMii0_TxClk => phyMii0_TxClk, phyMii0_TxDat => phyMii0_TxDat, phyMii0_TxEn => phyMii0_TxEn, phyMii0_TxEr => phyMii0_TxEr, phyMii1_RxClk => phyMii1_RxClk, phyMii1_RxDat => phyMii1_RxDat, phyMii1_RxDv => phyMii1_RxDv, phyMii1_RxEr => phyMii1_RxEr, phyMii1_TxClk => phyMii1_TxClk, phyMii1_TxDat => phyMii1_TxDat, phyMii1_TxEn => phyMii1_TxEn, phyMii1_TxEr => phyMii1_TxEr, phy_Rst_n => phy_Rst_n, phy_SMIClk => phy_SMIClk, phy_SMIDat => open, phy_SMIDat_I => phy_SMIDat_I, phy_SMIDat_O => phy_SMIDat_O, phy_SMIDat_T => phy_SMIDat_T, pio_operational => pio_operational, pio_pconfig => pio_pconfig, pio_portInLatch => pio_portInLatch, pio_portOutValid => pio_portOutValid, pio_portio => open, pio_portio_I => pio_portio_I, pio_portio_O => pio_portio_O, pio_portio_T => pio_portio_T, pkt_clk => pkt_clk, rst => rst, rstAp => rstAp, rstPcp => rstPcp, smp_address => smp_address, smp_byteenable => smp_byteenable, smp_read => smp_read, smp_readdata => smp_readdata, smp_waitrequest => smp_waitrequest, smp_write => smp_write, smp_writedata => smp_writedata, spi_clk => spi_clk, spi_miso => spi_miso, spi_mosi => spi_mosi, spi_sel_n => spi_sel_n, tcp_address => tcp_address, tcp_byteenable => tcp_byteenable, tcp_chipselect => tcp_chipselect, tcp_irq => tcp_irq_s, tcp_read => tcp_read, tcp_readdata => tcp_readdata, tcp_waitrequest => tcp_waitrequest, tcp_write => tcp_write, tcp_writedata => tcp_writedata ); MAC_DMA_areset <= not(M_AXI_MAC_DMA_aresetn); Bus2MAC_REG_RNW_n <= not(Bus2MAC_REG_RNW); Bus2MAC_REG_Reset <= not(Bus2MAC_REG_Resetn); rstPcp <= Bus2SMP_PCP_Reset or Bus2PDI_PCP_Reset or Bus2MAC_PKT_Reset; rstAp <= Bus2PDI_AP_Reset; rst <= Bus2MAC_REG_Reset; macRegClkXing : clkXing generic map ( gCsNum => 2, gDataWidth => C_S_AXI_MAC_REG_DATA_WIDTH ) port map( iArst => Bus2MAC_REG_Reset, iFastClk => Bus2MAC_REG_Clk, iFastCs => Bus2MAC_REG_CS_fast( 1 downto 0 ), iFastRNW => Bus2MAC_REG_RNW_fast, iSlowClk => clk50, iSlowRdAck => IP2Bus_RdAck_s, iSlowReaddata => IP2Bus_Data_s( C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0 ), iSlowWrAck => IP2Bus_WrAck_s, oFastRdAck => IP2Bus_RdAck_fast, oFastReaddata => IP2Bus_Data_fast( C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0 ), oFastWrAck => IP2Bus_WrAck_fast, oSlowCs => Bus2MAC_REG_CS( 1 downto 0 ), oSlowRNW => Bus2MAC_REG_RNW ); ---- Power , ground assignment ---- GND <= GND_CONSTANT; VCC <= VCC_CONSTANT; MAC_REG2Bus_Error <= GND; ---- Terminal assignment ---- -- Output\buffer terminals mac_irq <= mac_irq_s; tcp_irq <= tcp_irq_s; ---- Generate statements ---- genMacDmaPlbBurst : if C_DMA_EN = TRUE generate begin MAC_DMA_AXI_BURST_MASTER : axi_master_burst generic map ( C_ADDR_PIPE_DEPTH => 1, C_FAMILY => C_FAMILY, C_LENGTH_WIDTH => C_M_AXI_MAC_DMA_LENGTH_WIDTH, C_MAX_BURST_LEN => C_M_AXI_MAC_DMA_MAX_BURST_LEN, C_M_AXI_ADDR_WIDTH => C_M_AXI_MAC_DMA_ADDR_WIDTH, C_M_AXI_DATA_WIDTH => C_M_AXI_MAC_DMA_DATA_WIDTH, C_NATIVE_DATA_WIDTH => C_M_AXI_MAC_DMA_NATIVE_DWIDTH ) port map( bus2ip_mst_cmd_timeout => bus2MAC_DMA_mst_cmd_timeout, bus2ip_mst_cmdack => bus2MAC_DMA_mst_cmdack, bus2ip_mst_cmplt => bus2MAC_DMA_mst_cmplt, bus2ip_mst_error => bus2MAC_DMA_mst_error, bus2ip_mst_rearbitrate => bus2MAC_DMA_mst_rearbitrate, bus2ip_mstrd_d => bus2MAC_DMA_mstrd_d( C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0 ), bus2ip_mstrd_eof_n => bus2MAC_DMA_mstrd_eof_n, bus2ip_mstrd_rem => bus2MAC_DMA_mstrd_rem( (C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0 ), bus2ip_mstrd_sof_n => bus2MAC_DMA_mstrd_sof_n, bus2ip_mstrd_src_dsc_n => bus2MAC_DMA_mstrd_src_dsc_n, bus2ip_mstrd_src_rdy_n => bus2MAC_DMA_mstrd_src_rdy_n, bus2ip_mstwr_dst_dsc_n => bus2MAC_DMA_mstwr_dst_dsc_n, bus2ip_mstwr_dst_rdy_n => bus2MAC_DMA_mstwr_dst_rdy_n, ip2bus_mst_addr => MAC_DMA2bus_mst_addr( C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0 ), ip2bus_mst_be => MAC_DMA2bus_mst_be( (C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0 ), ip2bus_mst_length => MAC_DMA2bus_mst_length( C_M_AXI_MAC_DMA_LENGTH_WIDTH-1 downto 0 ), ip2bus_mst_lock => MAC_DMA2bus_mst_lock, ip2bus_mst_reset => MAC_DMA2bus_mst_reset, ip2bus_mst_type => MAC_DMA2bus_mst_type, ip2bus_mstrd_dst_dsc_n => MAC_DMA2bus_mstrd_dst_dsc_n, ip2bus_mstrd_dst_rdy_n => MAC_DMA2bus_mstrd_dst_rdy_n, ip2bus_mstrd_req => MAC_DMA2bus_mstrd_req, ip2bus_mstwr_d => MAC_DMA2bus_mstwr_d( C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0 ), ip2bus_mstwr_eof_n => MAC_DMA2bus_mstwr_eof_n, ip2bus_mstwr_rem => MAC_DMA2bus_mstwr_rem( (C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0 ), ip2bus_mstwr_req => MAC_DMA2bus_mstwr_req, ip2bus_mstwr_sof_n => MAC_DMA2bus_mstwr_sof_n, ip2bus_mstwr_src_dsc_n => MAC_DMA2bus_mstwr_src_dsc_n, ip2bus_mstwr_src_rdy_n => MAC_DMA2bus_mstwr_src_rdy_n, m_axi_aclk => M_AXI_MAC_DMA_aclk, m_axi_araddr => M_AXI_MAC_DMA_araddr( C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0 ), m_axi_arburst => M_AXI_MAC_DMA_arburst, m_axi_arcache => M_AXI_MAC_DMA_arcache, m_axi_aresetn => M_AXI_MAC_DMA_aresetn, m_axi_arlen => M_AXI_MAC_DMA_arlen, m_axi_arprot => M_AXI_MAC_DMA_arprot, m_axi_arready => M_AXI_MAC_DMA_arready, m_axi_arsize => M_AXI_MAC_DMA_arsize, m_axi_arvalid => M_AXI_MAC_DMA_arvalid, m_axi_awaddr => M_AXI_MAC_DMA_awaddr( C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0 ), m_axi_awburst => M_AXI_MAC_DMA_awburst, m_axi_awcache => M_AXI_MAC_DMA_awcache, m_axi_awlen => M_AXI_MAC_DMA_awlen, m_axi_awprot => M_AXI_MAC_DMA_awprot, m_axi_awready => M_AXI_MAC_DMA_awready, m_axi_awsize => M_AXI_MAC_DMA_awsize, m_axi_awvalid => M_AXI_MAC_DMA_awvalid, m_axi_bready => M_AXI_MAC_DMA_bready, m_axi_bresp => M_AXI_MAC_DMA_bresp, m_axi_bvalid => M_AXI_MAC_DMA_bvalid, m_axi_rdata => M_AXI_MAC_DMA_rdata( C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0 ), m_axi_rlast => M_AXI_MAC_DMA_rlast, m_axi_rready => M_AXI_MAC_DMA_rready, m_axi_rresp => M_AXI_MAC_DMA_rresp, m_axi_rvalid => M_AXI_MAC_DMA_rvalid, m_axi_wdata => M_AXI_MAC_DMA_wdata( C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0 ), m_axi_wlast => M_AXI_MAC_DMA_wlast, m_axi_wready => M_AXI_MAC_DMA_wready, m_axi_wstrb => M_AXI_MAC_DMA_wstrb( (C_M_AXI_MAC_DMA_DATA_WIDTH/8)-1 downto 0 ), m_axi_wvalid => M_AXI_MAC_DMA_wvalid, md_error => M_AXI_MAC_DMA_md_error ); end generate genMacDmaPlbBurst; genThePlbMaster : if C_DMA_EN = TRUE generate begin THE_IPIF_MASTER_HANDLER : ipif_master_handler generic map ( C_MAC_DMA_IPIF_AWIDTH => C_M_AXI_MAC_DMA_ADDR_WIDTH, C_MAC_DMA_IPIF_NATIVE_DWIDTH => C_M_AXI_MAC_DMA_NATIVE_DWIDTH, dma_highadr_g => m_address'high, gen_rx_fifo_g => not C_RX_INT_PKT, gen_tx_fifo_g => not C_TX_INT_PKT, m_burstcount_width_g => C_M_BURSTCOUNT_WIDTH ) port map( Bus2MAC_DMA_MstRd_d => bus2MAC_DMA_mstrd_d( C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0 ), Bus2MAC_DMA_MstRd_eof_n => bus2MAC_DMA_mstrd_eof_n, Bus2MAC_DMA_MstRd_rem => bus2MAC_DMA_mstrd_rem( (C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0 ), Bus2MAC_DMA_MstRd_sof_n => bus2MAC_DMA_mstrd_sof_n, Bus2MAC_DMA_MstRd_src_dsc_n => bus2MAC_DMA_mstrd_src_dsc_n, Bus2MAC_DMA_MstRd_src_rdy_n => bus2MAC_DMA_mstrd_src_rdy_n, Bus2MAC_DMA_MstWr_dst_dsc_n => bus2MAC_DMA_mstwr_dst_dsc_n, Bus2MAC_DMA_MstWr_dst_rdy_n => bus2MAC_DMA_mstwr_dst_rdy_n, Bus2MAC_DMA_Mst_CmdAck => bus2MAC_DMA_mst_cmdack, Bus2MAC_DMA_Mst_Cmd_Timeout => bus2MAC_DMA_mst_cmd_timeout, Bus2MAC_DMA_Mst_Cmplt => bus2MAC_DMA_mst_cmplt, Bus2MAC_DMA_Mst_Error => bus2MAC_DMA_mst_error, Bus2MAC_DMA_Mst_Rearbitrate => bus2MAC_DMA_mst_rearbitrate, MAC_DMA2Bus_MstRd_Req => MAC_DMA2bus_mstrd_req, MAC_DMA2Bus_MstRd_dst_dsc_n => MAC_DMA2bus_mstrd_dst_dsc_n, MAC_DMA2Bus_MstRd_dst_rdy_n => MAC_DMA2bus_mstrd_dst_rdy_n, MAC_DMA2Bus_MstWr_Req => MAC_DMA2bus_mstwr_req, MAC_DMA2Bus_MstWr_d => MAC_DMA2Bus_MstWr_d( C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0 ), MAC_DMA2Bus_MstWr_eof_n => MAC_DMA2bus_mstwr_eof_n, MAC_DMA2Bus_MstWr_rem => MAC_DMA2bus_mstwr_rem( (C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0 ), MAC_DMA2Bus_MstWr_sof_n => MAC_DMA2bus_mstwr_sof_n, MAC_DMA2Bus_MstWr_src_dsc_n => MAC_DMA2bus_mstwr_src_dsc_n, MAC_DMA2Bus_MstWr_src_rdy_n => MAC_DMA2bus_mstwr_src_rdy_n, MAC_DMA2Bus_Mst_Addr => MAC_DMA2bus_mst_addr( C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0 ), MAC_DMA2Bus_Mst_BE => MAC_DMA2bus_mst_be( (C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0 ), MAC_DMA2Bus_Mst_Length => MAC_DMA2bus_mst_length( C_M_AXI_MAC_DMA_LENGTH_WIDTH-1 downto 0 ), MAC_DMA2Bus_Mst_Lock => MAC_DMA2bus_mst_lock, MAC_DMA2Bus_Mst_Reset => MAC_DMA2bus_mst_reset, MAC_DMA2Bus_Mst_Type => MAC_DMA2bus_mst_type, MAC_DMA_CLK => M_AXI_MAC_DMA_aclk, MAC_DMA_Rst => MAC_DMA_areset, m_address => m_address( 31 downto 0 ), m_burstcount => m_burstcount( C_M_BURSTCOUNT_WIDTH-1 downto 0 ), m_burstcounter => m_burstcounter( C_M_BURSTCOUNT_WIDTH-1 downto 0 ), m_byteenable => m_byteenable, m_clk => m_clk, m_read => m_read, m_readdata => m_readdata, m_readdatavalid => m_readdatavalid, m_waitrequest => m_waitrequest, m_write => m_write, m_writedata => m_writedata ); end generate genThePlbMaster; genMacPktPLbSingleSlave : if C_PKT_BUF_EN generate begin MAC_PKT_AXI_SINGLE_SLAVE : axi_lite_ipif generic map ( C_ARD_ADDR_RANGE_ARRAY => (C_MAC_PKT_BASE,C_MAC_PKT_HIGH), C_ARD_NUM_CE_ARRAY => (0=>1), C_DPHASE_TIMEOUT => C_S_AXI_MAC_PKT_DPHASE_TIMEOUT, C_FAMILY => C_FAMILY, C_S_AXI_ADDR_WIDTH => C_S_AXI_MAC_PKT_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_MAC_PKT_DATA_WIDTH, C_S_AXI_MIN_SIZE => C_MAC_PKT_MINSIZE, C_USE_WSTRB => C_S_AXI_MAC_PKT_USE_WSTRB ) port map( Bus2IP_Addr => Bus2MAC_PKT_Addr( C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0 ), Bus2IP_BE => Bus2MAC_PKT_BE( (C_S_AXI_MAC_PKT_DATA_WIDTH/8)-1 downto 0 ), Bus2IP_CS => Bus2MAC_PKT_CS( 0 downto 0 ), Bus2IP_Clk => Bus2MAC_PKT_Clk, Bus2IP_Data => Bus2MAC_PKT_Data( C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0 ), Bus2IP_RNW => Bus2MAC_PKT_RNW, Bus2IP_RdCE => open, Bus2IP_Resetn => Bus2MAC_PKT_Resetn, Bus2IP_WrCE => open, IP2Bus_Data => MAC_PKT2Bus_Data( C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0 ), IP2Bus_Error => MAC_PKT2Bus_Error, IP2Bus_RdAck => MAC_PKT2Bus_RdAck, IP2Bus_WrAck => MAC_PKT2Bus_WrAck, S_AXI_ACLK => S_AXI_MAC_PKT_ACLK, S_AXI_ARADDR => S_AXI_MAC_PKT_ARADDR( C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0 ), S_AXI_ARESETN => S_AXI_MAC_PKT_ARESETN, S_AXI_ARREADY => S_AXI_MAC_PKT_ARREADY, S_AXI_ARVALID => S_AXI_MAC_PKT_ARVALID, S_AXI_AWADDR => S_AXI_MAC_PKT_AWADDR( C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0 ), S_AXI_AWREADY => S_AXI_MAC_PKT_AWREADY, S_AXI_AWVALID => S_AXI_MAC_PKT_AWVALID, S_AXI_BREADY => S_AXI_MAC_PKT_BREADY, S_AXI_BRESP => S_AXI_MAC_PKT_BRESP, S_AXI_BVALID => S_AXI_MAC_PKT_BVALID, S_AXI_RDATA => S_AXI_MAC_PKT_RDATA( C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0 ), S_AXI_RREADY => S_AXI_MAC_PKT_RREADY, S_AXI_RRESP => S_AXI_MAC_PKT_RRESP, S_AXI_RVALID => S_AXI_MAC_PKT_RVALID, S_AXI_WDATA => S_AXI_MAC_PKT_WDATA( C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0 ), S_AXI_WREADY => S_AXI_MAC_PKT_WREADY, S_AXI_WSTRB => S_AXI_MAC_PKT_WSTRB( (C_S_AXI_MAC_PKT_DATA_WIDTH/8)-1 downto 0 ), S_AXI_WVALID => S_AXI_MAC_PKT_WVALID ); end generate genMacPktPLbSingleSlave; genPdiPcp : if (C_GEN_PDI) generate begin PDI_PCP_AXI_SINGLE_SLAVE : axi_lite_ipif generic map ( C_ARD_ADDR_RANGE_ARRAY => (C_PDI_PCP_BASE,C_PDI_PCP_HIGH), C_ARD_NUM_CE_ARRAY => (0=>1), C_DPHASE_TIMEOUT => C_S_AXI_PDI_PCP_DPHASE_TIMEOUT, C_FAMILY => C_FAMILY, C_S_AXI_ADDR_WIDTH => C_S_AXI_PDI_PCP_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_PDI_PCP_DATA_WIDTH, C_S_AXI_MIN_SIZE => C_PDI_PCP_MINSIZE, C_USE_WSTRB => C_S_AXI_PDI_PCP_USE_WSTRB ) port map( Bus2IP_Addr => Bus2PDI_PCP_Addr( C_S_AXI_PDI_PCP_ADDR_WIDTH-1 downto 0 ), Bus2IP_BE => Bus2PDI_PCP_BE( (C_S_AXI_PDI_PCP_DATA_WIDTH/8)-1 downto 0 ), Bus2IP_CS => Bus2PDI_PCP_CS( 0 downto 0 ), Bus2IP_Clk => Bus2PDI_PCP_Clk, Bus2IP_Data => Bus2PDI_PCP_Data( C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0 ), Bus2IP_RNW => Bus2PDI_PCP_RNW, Bus2IP_RdCE => open, Bus2IP_Resetn => Bus2PDI_PCP_Resetn, Bus2IP_WrCE => open, IP2Bus_Data => PDI_PCP2Bus_Data( C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0 ), IP2Bus_Error => PDI_PCP2Bus_Error, IP2Bus_RdAck => PDI_PCP2Bus_RdAck, IP2Bus_WrAck => PDI_PCP2Bus_WrAck, S_AXI_ACLK => S_AXI_PDI_PCP_ACLK, S_AXI_ARADDR => S_AXI_PDI_PCP_ARADDR( C_S_AXI_PDI_PCP_ADDR_WIDTH-1 downto 0 ), S_AXI_ARESETN => S_AXI_PDI_PCP_ARESETN, S_AXI_ARREADY => S_AXI_PDI_PCP_ARREADY, S_AXI_ARVALID => S_AXI_PDI_PCP_ARVALID, S_AXI_AWADDR => S_AXI_PDI_PCP_AWADDR( C_S_AXI_PDI_PCP_ADDR_WIDTH-1 downto 0 ), S_AXI_AWREADY => S_AXI_PDI_PCP_AWREADY, S_AXI_AWVALID => S_AXI_PDI_PCP_AWVALID, S_AXI_BREADY => S_AXI_PDI_PCP_BREADY, S_AXI_BRESP => S_AXI_PDI_PCP_BRESP, S_AXI_BVALID => S_AXI_PDI_PCP_BVALID, S_AXI_RDATA => S_AXI_PDI_PCP_RDATA( C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0 ), S_AXI_RREADY => S_AXI_PDI_PCP_RREADY, S_AXI_RRESP => S_AXI_PDI_PCP_RRESP, S_AXI_RVALID => S_AXI_PDI_PCP_RVALID, S_AXI_WDATA => S_AXI_PDI_PCP_WDATA( C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0 ), S_AXI_WREADY => S_AXI_PDI_PCP_WREADY, S_AXI_WSTRB => S_AXI_PDI_PCP_WSTRB( (C_S_AXI_PDI_PCP_DATA_WIDTH/8)-1 downto 0 ), S_AXI_WVALID => S_AXI_PDI_PCP_WVALID ); end generate genPdiPcp; genPcpPdiLink : if C_GEN_PDI generate begin --pdi_pcp assignments clkPcp <= Bus2PDI_PCP_Clk; Bus2PDI_PCP_Reset <= not Bus2PDI_PCP_Resetn; pcp_writedata <= Bus2PDI_PCP_Data; -- Bus2MAC_PKT_Data(7 downto 0) & Bus2MAC_PKT_Data(15 downto 8) & -- Bus2MAC_PKT_Data(23 downto 16) & Bus2MAC_PKT_Data(31 downto 24); pcp_read <= Bus2PDI_PCP_RNW; pcp_write <= not Bus2PDI_PCP_RNW; pcp_chipselect <= Bus2PDI_PCP_CS(0); pcp_byteenable <= Bus2PDI_PCP_BE; pcp_address <= Bus2PDI_PCP_Addr(14 downto 2); PDI_PCP2Bus_Data <= pcp_readdata; PDI_PCP2Bus_RdAck <= pcp_chipselect and pcp_read and not pcp_waitrequest; PDI_PCP2Bus_WrAck <= pcp_chipselect and pcp_write and not pcp_waitrequest; PDI_PCP2Bus_Error <= '0'; end generate genPcpPdiLink; genPdiAp : if (C_GEN_AXI_BUS_IF) generate begin PDI_AP_AXI_SINGLE_SLAVE : axi_lite_ipif generic map ( C_ARD_ADDR_RANGE_ARRAY => (C_PDI_AP_BASE,C_PDI_AP_HIGH), C_ARD_NUM_CE_ARRAY => (0=>1), C_DPHASE_TIMEOUT => C_S_AXI_PDI_AP_DPHASE_TIMEOUT, C_FAMILY => C_FAMILY, C_S_AXI_ADDR_WIDTH => C_S_AXI_PDI_AP_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_PDI_AP_DATA_WIDTH, C_S_AXI_MIN_SIZE => C_PDI_AP_MINSIZE, C_USE_WSTRB => C_S_AXI_PDI_AP_USE_WSTRB ) port map( Bus2IP_Addr => Bus2PDI_AP_Addr( C_S_AXI_PDI_AP_ADDR_WIDTH-1 downto 0 ), Bus2IP_BE => Bus2PDI_AP_BE( (C_S_AXI_PDI_AP_DATA_WIDTH/8)-1 downto 0 ), Bus2IP_CS => Bus2PDI_AP_CS( 0 downto 0 ), Bus2IP_Clk => Bus2PDI_AP_Clk, Bus2IP_Data => Bus2PDI_AP_Data( C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0 ), Bus2IP_RNW => Bus2PDI_AP_RNW, Bus2IP_RdCE => open, Bus2IP_Resetn => Bus2PDI_AP_Resetn, Bus2IP_WrCE => open, IP2Bus_Data => PDI_AP2Bus_Data( C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0 ), IP2Bus_Error => PDI_AP2Bus_Error, IP2Bus_RdAck => PDI_AP2Bus_RdAck, IP2Bus_WrAck => PDI_AP2Bus_WrAck, S_AXI_ACLK => S_AXI_PDI_AP_ACLK, S_AXI_ARADDR => S_AXI_PDI_AP_ARADDR( C_S_AXI_PDI_AP_ADDR_WIDTH-1 downto 0 ), S_AXI_ARESETN => S_AXI_PDI_AP_ARESETN, S_AXI_ARREADY => S_AXI_PDI_AP_ARREADY, S_AXI_ARVALID => S_AXI_PDI_AP_ARVALID, S_AXI_AWADDR => S_AXI_PDI_AP_AWADDR( C_S_AXI_PDI_AP_ADDR_WIDTH-1 downto 0 ), S_AXI_AWREADY => S_AXI_PDI_AP_AWREADY, S_AXI_AWVALID => S_AXI_PDI_AP_AWVALID, S_AXI_BREADY => S_AXI_PDI_AP_BREADY, S_AXI_BRESP => S_AXI_PDI_AP_BRESP, S_AXI_BVALID => S_AXI_PDI_AP_BVALID, S_AXI_RDATA => S_AXI_PDI_AP_RDATA( C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0 ), S_AXI_RREADY => S_AXI_PDI_AP_RREADY, S_AXI_RRESP => S_AXI_PDI_AP_RRESP, S_AXI_RVALID => S_AXI_PDI_AP_RVALID, S_AXI_WDATA => S_AXI_PDI_AP_WDATA( C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0 ), S_AXI_WREADY => S_AXI_PDI_AP_WREADY, S_AXI_WSTRB => S_AXI_PDI_AP_WSTRB( (C_S_AXI_PDI_AP_DATA_WIDTH/8)-1 downto 0 ), S_AXI_WVALID => S_AXI_PDI_AP_WVALID ); end generate genPdiAp; genApPdiLink : if C_GEN_PDI generate begin --ap_pcp assignments clkAp <= Bus2PDI_AP_Clk; Bus2PDI_AP_Reset <= not Bus2PDI_AP_Resetn; ap_writedata <= Bus2PDI_AP_Data; -- Bus2MAC_PKT_Data(7 downto 0) & Bus2MAC_PKT_Data(15 downto 8) & -- Bus2MAC_PKT_Data(23 downto 16) & Bus2MAC_PKT_Data(31 downto 24); ap_read <= Bus2PDI_AP_RNW; ap_write <= not Bus2PDI_AP_RNW; ap_chipselect <= Bus2PDI_AP_CS(0); ap_byteenable <= Bus2PDI_AP_BE; ap_address <= Bus2PDI_AP_Addr(14 downto 2); PDI_AP2Bus_Data <= ap_readdata; PDI_AP2Bus_RdAck <= ap_chipselect and ap_read and not ap_waitrequest; PDI_AP2Bus_WrAck <= ap_chipselect and ap_write and not ap_waitrequest; PDI_AP2Bus_Error <= '0'; end generate genApPdiLink; genSmpIo : if (C_GEN_SIMPLE_IO) generate begin SMP_IO_AXI_SINGLE_SLAVE : axi_lite_ipif generic map ( C_ARD_ADDR_RANGE_ARRAY => (C_SMP_PCP_BASE,C_SMP_PCP_HIGH), C_ARD_NUM_CE_ARRAY => (0=>1), C_DPHASE_TIMEOUT => C_S_AXI_SMP_PCP_DPHASE_TIMEOUT, C_FAMILY => C_FAMILY, C_S_AXI_ADDR_WIDTH => C_S_AXI_SMP_PCP_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_SMP_PCP_DATA_WIDTH, C_S_AXI_MIN_SIZE => C_SMP_PCP_MINSIZE, C_USE_WSTRB => C_S_AXI_SMP_PCP_USE_WSTRB ) port map( Bus2IP_Addr => Bus2SMP_PCP_Addr( C_S_AXI_SMP_PCP_ADDR_WIDTH-1 downto 0 ), Bus2IP_BE => Bus2SMP_PCP_BE( (C_S_AXI_SMP_PCP_DATA_WIDTH/8)-1 downto 0 ), Bus2IP_CS => Bus2SMP_PCP_CS( 0 downto 0 ), Bus2IP_Clk => Bus2SMP_PCP_Clk, Bus2IP_Data => Bus2SMP_PCP_Data( C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0 ), Bus2IP_RNW => Bus2SMP_PCP_RNW, Bus2IP_RdCE => open, Bus2IP_Resetn => Bus2SMP_PCP_Resetn, Bus2IP_WrCE => open, IP2Bus_Data => SMP_PCP2Bus_Data( C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0 ), IP2Bus_Error => SMP_PCP2Bus_Error, IP2Bus_RdAck => SMP_PCP2Bus_RdAck, IP2Bus_WrAck => SMP_PCP2Bus_WrAck, S_AXI_ACLK => S_AXI_SMP_PCP_ACLK, S_AXI_ARADDR => S_AXI_SMP_PCP_ARADDR( C_S_AXI_SMP_PCP_ADDR_WIDTH-1 downto 0 ), S_AXI_ARESETN => S_AXI_SMP_PCP_ARESETN, S_AXI_ARREADY => S_AXI_SMP_PCP_ARREADY, S_AXI_ARVALID => S_AXI_SMP_PCP_ARVALID, S_AXI_AWADDR => S_AXI_SMP_PCP_AWADDR( C_S_AXI_SMP_PCP_ADDR_WIDTH-1 downto 0 ), S_AXI_AWREADY => S_AXI_SMP_PCP_AWREADY, S_AXI_AWVALID => S_AXI_SMP_PCP_AWVALID, S_AXI_BREADY => S_AXI_SMP_PCP_BREADY, S_AXI_BRESP => S_AXI_SMP_PCP_BRESP, S_AXI_BVALID => S_AXI_SMP_PCP_BVALID, S_AXI_RDATA => S_AXI_SMP_PCP_RDATA( C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0 ), S_AXI_RREADY => S_AXI_SMP_PCP_RREADY, S_AXI_RRESP => S_AXI_SMP_PCP_RRESP, S_AXI_RVALID => S_AXI_SMP_PCP_RVALID, S_AXI_WDATA => S_AXI_SMP_PCP_WDATA( C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0 ), S_AXI_WREADY => S_AXI_SMP_PCP_WREADY, S_AXI_WSTRB => S_AXI_SMP_PCP_WSTRB( (C_S_AXI_SMP_PCP_DATA_WIDTH/8)-1 downto 0 ), S_AXI_WVALID => S_AXI_SMP_PCP_WVALID ); end generate genSmpIo; genSimpleIoSignals : if C_GEN_SIMPLE_IO generate begin --SMP_PCP assignments clkPcp <= Bus2SMP_PCP_Clk; Bus2SMP_PCP_Reset <= not Bus2SMP_PCP_Resetn; smp_writedata <= Bus2SMP_PCP_Data; smp_read <= Bus2SMP_PCP_RNW and Bus2SMP_PCP_CS(0); smp_write <= not Bus2SMP_PCP_RNW and Bus2SMP_PCP_CS(0); smp_chipselect <= Bus2SMP_PCP_CS(0); smp_byteenable <= Bus2SMP_PCP_BE; smp_address <= Bus2SMP_PCP_Addr(2); SMP_PCP2Bus_Data <= smp_readdata; SMP_PCP2Bus_RdAck <= smp_chipselect and smp_read and not smp_waitrequest; SMP_PCP2Bus_WrAck <= smp_chipselect and smp_write and not smp_waitrequest; SMP_PCP2Bus_Error <= '0'; end generate genSimpleIoSignals; oddr2_0 : if not C_INSTANCE_ODDR2 generate begin phy0_clk <= clk50; phy1_clk <= clk50; end generate oddr2_0; oddr2_1 : if C_INSTANCE_ODDR2 generate begin U10 : ODDR2 port map( C0 => clk50, C1 => NET38418, CE => VCC, D0 => VCC, D1 => GND, Q => phy0_clk, R => GND, S => GND ); U11 : ODDR2 port map( C0 => clk50, C1 => NET38470, CE => VCC, D0 => VCC, D1 => GND, Q => phy1_clk, R => GND, S => GND ); NET38470 <= not(clk50); NET38418 <= not(clk50); end generate oddr2_1; end struct;
gpl-2.0
39692f7d7bdc7e2534df6190e5458b5e
0.619827
2.896173
false
false
false
false
simonspa/pixel-dtb-firmware
dtb/gl_and4b.vhd
2
3,278
-- megafunction wizard: %LPM_AND% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: lpm_and -- ============================================================ -- File Name: gl_and4b.vhd -- Megafunction Name(s): -- lpm_and -- -- Simulation Library Files(s): -- lpm -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 9.0 Build 184 04/29/2009 SP 1 SJ Full Version -- ************************************************************ --Copyright (C) 1991-2009 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.lpm_components.all; ENTITY gl_and4b IS PORT ( data : IN STD_LOGIC_2D (3 DOWNTO 0, 0 DOWNTO 0); result : OUT STD_LOGIC ); END gl_and4b; ARCHITECTURE SYN OF gl_and4b IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC ; BEGIN sub_wire1 <= sub_wire0(0); result <= sub_wire1; lpm_and_component : lpm_and GENERIC MAP ( lpm_size => 4, lpm_type => "LPM_AND", lpm_width => 1 ) PORT MAP ( data => data, result => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: CompactSymbol NUMERIC "0" -- Retrieval info: PRIVATE: GateFunction NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix" -- Retrieval info: PRIVATE: InputAsBus NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: WidthInput NUMERIC "1" -- Retrieval info: PRIVATE: nInput NUMERIC "4" -- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4" -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_AND" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1" -- Retrieval info: USED_PORT: data 4 0 1 0 INPUT NODEFVAL data[3..0][0..0] -- Retrieval info: USED_PORT: result 0 0 0 0 OUTPUT NODEFVAL result -- Retrieval info: CONNECT: @data 4 0 1 0 data 4 0 1 0 -- Retrieval info: CONNECT: result 0 0 0 0 @result 0 0 1 0 -- Retrieval info: LIBRARY: lpm lpm.lpm_components.all -- Retrieval info: GEN_FILE: TYPE_NORMAL gl_and4b.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL gl_and4b.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL gl_and4b.cmp FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL gl_and4b.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL gl_and4b_inst.vhd FALSE -- Retrieval info: LIB_FILE: lpm
unlicense
69c84a3bd8f88af5ddc8ac4572707210
0.636364
3.737742
false
false
false
false
notti/dis_lu
vhdl/core.vhd
1
11,325
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; entity core is port( clk : in std_logic; rst : in std_logic; address : out std_logic_vector(7 downto 0); data : in std_logic_vector(7 downto 0); lcd_out : out std_logic_vector(7 downto 0); lcd_wr : out std_logic; rightInt : in std_logic; leftInt : in std_logic; pushInt : in std_logic; switch : in std_logic_vector(3 downto 0) ); end entity core; architecture beh of core is type state_type is (RESET, EXEC, FETCH_ARGUMENT, HLT); signal state : state_type; type alu_type is (MOV, ADD, SUB, SHL, SHR, NO_ALU); type reg_file is array (integer range <>) of std_logic_vector(7 downto 0); signal reg : reg_file(3 downto 0); signal reg_fixed : reg_file(3 downto 0); -- A, B, C, D, SWR signal PC_reg: std_logic_vector(7 downto 0); signal IR_reg: std_logic_vector(7 downto 0); signal carry : std_logic; signal zero : std_logic; signal hex_value : std_logic_vector(3 downto 0); signal hex_write : std_logic; signal out_write : std_logic; signal hex_ascii : std_logic_vector(7 downto 0); signal lcd_char : std_logic_vector(7 downto 0); signal leftInt_r : std_logic; signal rightInt_r : std_logic; signal pushInt_r : std_logic; begin reg_fixed(0) <= x"00"; reg_fixed(1) <= x"01"; reg_fixed(2)(3 downto 0) <= switch; reg_fixed(2)(7 downto 4) <= (others => '0'); reg_fixed(3) <= (others => '0'); core_proc: process(clk) variable result: unsigned(8 downto 0); variable alu_op : alu_type; variable arg1 : unsigned(8 downto 0); variable arg2 : unsigned(8 downto 0); variable target : std_logic_vector(2 downto 0); begin alu_op := NO_ALU; arg1 := (others => '0'); arg2 := (others => '0'); target := (others => '0'); result := (others => '0'); if rising_edge(clk) then if rst = '0' then state <= RESET; leftInt_r <= '0'; rightInt_r <= '0'; pushInt_r <= '0'; else if leftInt = '1' then leftInt_r <= '1'; end if; if rightInt = '1' then rightInt_r <= '1'; end if; if pushInt = '1' then pushInt_r <= '1'; end if; hex_write <= '0'; out_write <= '0'; case state is when RESET => reg(0) <= (others => '0'); reg(1) <= (others => '0'); reg(2) <= (others => '0'); reg(3) <= (others => '0'); PC_reg <= (others => '0'); IR_reg <= (others => '0'); carry <= '0'; zero <= '0'; hex_value <= (others => '0'); lcd_char <= (others => '0'); state <= EXEC; when EXEC => IR_reg <= data; PC_reg <= std_logic_vector(unsigned(PC_reg) + 1); if data(5 downto 3) = "111" or data(7 downto 4) = "1110" or data(7 downto 3) = "11111" then state <= FETCH_ARGUMENT; else if data(7 downto 6) = "00" then alu_op := MOV; elsif data(7 downto 6) = "01" then alu_op := ADD; elsif data(7 downto 6) = "10" then alu_op := SUB; elsif data(7 downto 3) = "11000" then alu_op := SHL; elsif data(7 downto 3) = "11001" then alu_op := SHR; elsif data(7 downto 3) = "11010" then -- OUTL hex_write <= '1'; if data(2) = '0' then hex_value <= reg(to_integer(unsigned(data(1 downto 0))))(3 downto 0); else hex_value <= reg_fixed(to_integer(unsigned(data(1 downto 0))))(3 downto 0); end if; elsif data(7 downto 3) = "11011" then -- OUTH hex_write <= '1'; if data(2) = '0' then hex_value <= reg(to_integer(unsigned(data(1 downto 0))))(7 downto 4); else hex_value <= reg_fixed(to_integer(unsigned(data(1 downto 0))))(7 downto 4); end if; else -- HLT state <= HLT; end if; end if; if data(2) = '0' then arg1 := "0" & unsigned(reg(to_integer(unsigned(data(1 downto 0))))); else arg1 := "0" & unsigned(reg_fixed(to_integer(unsigned(data(1 downto 0))))); end if; if data(5) = '0' then arg2 := "0" & unsigned(reg(to_integer(unsigned(data(4 downto 3))))); else arg2 := "0" & unsigned(reg_fixed(to_integer(unsigned(data(4 downto 3))))); end if; target := data(2 downto 0); when FETCH_ARGUMENT => PC_reg <= std_logic_vector(unsigned(PC_reg) + 1); if IR_reg(7 downto 6) = "00" then alu_op := MOV; elsif IR_reg(7 downto 6) = "01" then alu_op := ADD; elsif IR_reg(7 downto 6) = "10" then alu_op := SUB; elsif IR_reg(7 downto 0) = "11100001" then -- JZ if zero = '1' then PC_reg <= data; end if; elsif IR_reg(7 downto 0) = "11100010" then -- JNZ if zero = '0' then PC_reg <= data; end if; elsif IR_reg(7 downto 0) = "11100100" then -- JC if carry = '1' then PC_reg <= data; end if; elsif IR_reg(7 downto 0) = "11101000" then -- JNC if carry = '0' then PC_reg <= data; end if; elsif IR_reg(7 downto 0) = "11100000" then -- JMP PC_reg <= data; else -- OUT out_write <= '1'; lcd_char <= data; end if; state <= EXEC; if IR_reg(2) = '0' then arg1 := "0" & unsigned(reg(to_integer(unsigned(IR_reg(1 downto 0))))); else arg1 := "0" & unsigned(reg_fixed(to_integer(unsigned(IR_reg(1 downto 0))))); end if; arg2 := "0" & unsigned(data); target := IR_reg(2 downto 0); when HLT => if leftInt_r = '1' then PC_reg <= x"03"; leftInt_r <= '0'; state <= EXEC; elsif rightInt_r = '1' then PC_reg <= x"0C"; rightInt_r <= '0'; state <= EXEC; elsif pushInt_r = '1' then PC_reg <= x"15"; pushInt_r <= '0'; state <= EXEC; end if; end case; case alu_op is when MOV => result := arg2; when ADD | SUB=> if alu_op = ADD then result := arg1 + arg2; else result := arg1 - arg2; end if; if result = "000000000" then zero <= '1'; else zero <= '0'; end if; carry <= result(8); when SHL => result := arg1(7 downto 0) & "0"; if result = "000000000" then zero <= '1'; else zero <= '0'; end if; carry <= arg1(7); when SHR => result := "0" & arg1(8 downto 1); if result = "000000000" then zero <= '1'; else zero <= '0'; end if; carry <= arg1(0); when others => end case; if (not (alu_op = NO_ALU)) and target(2) = '0' then reg(to_integer(unsigned(target(1 downto 0)))) <= std_logic_vector(result(7 downto 0)); end if; end if; end if; end process; hex_ascii <= x"30" when hex_value = x"0" else x"31" when hex_value = x"1" else x"32" when hex_value = x"2" else x"33" when hex_value = x"3" else x"34" when hex_value = x"4" else x"35" when hex_value = x"5" else x"36" when hex_value = x"6" else x"37" when hex_value = x"7" else x"38" when hex_value = x"8" else x"39" when hex_value = x"9" else x"41" when hex_value = x"A" else x"42" when hex_value = x"B" else x"43" when hex_value = x"C" else x"44" when hex_value = x"D" else x"45" when hex_value = x"E" else x"46"; lcd_wr <= hex_write or out_write; lcd_out <= hex_ascii when hex_write = '1' else lcd_char; address <= PC_reg; end architecture beh;
mit
b158d37eea01896e16f06f5d96ba26ea
0.351258
4.668178
false
false
false
false
simonspa/pixel-dtb-firmware
dtb/lpm_or60.vhd
2
3,275
-- megafunction wizard: %LPM_OR% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: lpm_or -- ============================================================ -- File Name: lpm_or60.vhd -- Megafunction Name(s): -- lpm_or -- -- Simulation Library Files(s): -- lpm -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 9.1 Build 222 10/21/2009 SJ Full Version -- ************************************************************ --Copyright (C) 1991-2009 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.lpm_components.all; ENTITY lpm_or60 IS PORT ( data : IN STD_LOGIC_2D (59 DOWNTO 0, 0 DOWNTO 0); result : OUT STD_LOGIC ); END lpm_or60; ARCHITECTURE SYN OF lpm_or60 IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC ; BEGIN sub_wire1 <= sub_wire0(0); result <= sub_wire1; lpm_or_component : lpm_or GENERIC MAP ( lpm_size => 60, lpm_type => "LPM_OR", lpm_width => 1 ) PORT MAP ( data => data, result => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: CompactSymbol NUMERIC "0" -- Retrieval info: PRIVATE: GateFunction NUMERIC "1" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX" -- Retrieval info: PRIVATE: InputAsBus NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: WidthInput NUMERIC "1" -- Retrieval info: PRIVATE: nInput NUMERIC "60" -- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "60" -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_OR" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1" -- Retrieval info: USED_PORT: data 60 0 1 0 INPUT NODEFVAL data[59..0][0..0] -- Retrieval info: USED_PORT: result 0 0 0 0 OUTPUT NODEFVAL result -- Retrieval info: CONNECT: @data 60 0 1 0 data 60 0 1 0 -- Retrieval info: CONNECT: result 0 0 0 0 @result 0 0 1 0 -- Retrieval info: LIBRARY: lpm lpm.lpm_components.all -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_or60.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_or60.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_or60.cmp FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_or60.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_or60_inst.vhd FALSE -- Retrieval info: LIB_FILE: lpm
unlicense
c6d76433562b0a888c770ffb9a127446
0.636336
3.777393
false
false
false
false
simonspa/pixel-dtb-firmware
dtb/lpm_rom0.vhd
2
6,146
-- megafunction wizard: %LPM_ROM% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altsyncram -- ============================================================ -- File Name: lpm_rom0.vhd -- Megafunction Name(s): -- altsyncram -- -- Simulation Library Files(s): -- altera_mf -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 9.1 Build 222 10/21/2009 SJ Full Version -- ************************************************************ --Copyright (C) 1991-2009 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY lpm_rom0 IS PORT ( address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); clock : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END lpm_rom0; ARCHITECTURE SYN OF lpm_rom0 IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); COMPONENT altsyncram GENERIC ( clock_enable_input_a : STRING; clock_enable_output_a : STRING; init_file : STRING; intended_device_family : STRING; lpm_hint : STRING; lpm_type : STRING; numwords_a : NATURAL; operation_mode : STRING; outdata_aclr_a : STRING; outdata_reg_a : STRING; widthad_a : NATURAL; width_a : NATURAL; width_byteena_a : NATURAL ); PORT ( clock0 : IN STD_LOGIC ; address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT; BEGIN q <= sub_wire0(7 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( clock_enable_input_a => "BYPASS", clock_enable_output_a => "BYPASS", init_file => "UDP.mif", intended_device_family => "Arria GX", lpm_hint => "ENABLE_RUNTIME_MOD=NO", lpm_type => "altsyncram", numwords_a => 256, operation_mode => "ROM", outdata_aclr_a => "NONE", outdata_reg_a => "CLOCK0", widthad_a => 8, width_a => 8, width_byteena_a => 1 ) PORT MAP ( clock0 => clock, address_a => address, q_a => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" -- Retrieval info: PRIVATE: AclrByte NUMERIC "0" -- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: Clken NUMERIC "0" -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -- Retrieval info: PRIVATE: MIFfilename STRING "UDP.mif" -- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256" -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" -- Retrieval info: PRIVATE: RegOutput NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" -- Retrieval info: PRIVATE: WidthAddr NUMERIC "8" -- Retrieval info: PRIVATE: WidthData NUMERIC "8" -- Retrieval info: PRIVATE: rden NUMERIC "0" -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: INIT_FILE STRING "UDP.mif" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria GX" -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL address[7..0] -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock -- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0] -- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0 -- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0.cmp FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0_inst.vhd FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0_waveforms.html TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0_wave*.jpg FALSE -- Retrieval info: LIB_FILE: altera_mf
unlicense
8d8437ff0b04d020f0cad40c2c4b0e9c
0.670355
3.538284
false
false
false
false
systec-dk/openPOWERLINK_systec
Examples/ipcore/common/lib/src/addr_decoder.vhd
3
2,454
------------------------------------------------------------------------------- -- -- (c) B&R, 2011 -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity addr_decoder is generic( addrWidth_g : integer := 32; baseaddr_g : integer := 16#1000#; highaddr_g : integer := 16#1FFF# ); port( selin : in std_logic; addr : in std_logic_vector(addrWidth_g-1 downto 0); selout : out std_logic ); end addr_decoder; architecture rtl of addr_decoder is begin selout <= selin when addr >= conv_std_logic_vector(baseaddr_g, addr'length) and addr <= conv_std_logic_vector(highaddr_g, addr'length) else '0'; end rtl;
gpl-2.0
0037c54ecf1685339064bceb8b4b24d1
0.657294
4.382143
false
false
false
false
Mamoutova/memory_fault_injection
hdl/fi_mem_connector.vhd
1
4,251
--345678901234567890123456789012345678901234567890123456789012345678901234567890 -- 1 2 3 4 5 6 7 8 -- Title: Entity and RTL architecture of the processor-to-fi_mem_agent connector -- Engineer: Olga Mamoutova -- Company: SpbSTU -- Project: Fault injection -- File name: fi_mem_connector.vhd -------------------------------------------------------------------------------- -- Purpose: Connects array of memory fault injection agents to the [NIOS] processor -------------------------------------------------------------------------------- -- Simulator: Altera Quartus II -- Synthesis: Altera Quartus II -------------------------------------------------------------------------------- -- Revision: 1.0 -- Modification date: 22 Nov 2013 -- Notes: -- Limitation: -- Revision: 1.1 -- Modification date: 15 Dec 2013 -- Notes: minor improvements -- Limitation: -- Revision: 1.2 -- Modification date: 11 Jan 2014 -- Notes: correct work with iw paramter being zero -- IF ( (fi_A_i_rg(aw_max+iw-1 DOWNTO aw_max)=i) AND i>0 OR i=0)THEN -- Limitation: -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.ALL; --============================================================================== ENTITY fi_mem_connector IS GENERIC ( N : INTEGER := 4; -- number of fi agents iw : INTEGER := 2; -- width of fi index value dw_max : INTEGER := 8; -- maximum data width among fi_mem_agent blocks aw_max : INTEGER := 5 -- maximum address width among fi_mem_agent blocks ); PORT ( -- Combined signals of fault injection command - from the processor clk_i : IN STD_LOGIC; rst_i : IN STD_LOGIC; fi_i : IN STD_LOGIC; -- chipselect, active high fi_wr_i : IN STD_LOGIC; -- write, active high fi_A_i : IN STD_LOGIC_VECTOR(aw_max+iw-1 DOWNTO 0); -- address fi_Mask_i : IN STD_LOGIC_VECTOR(dw_max-1 DOWNTO 0); -- writedata fi_data_r_i : OUT STD_LOGIC_VECTOR(dw_max-1 DOWNTO 0); -- readdata - debug feature fi_ack_i : OUT STD_LOGIC; -- waitrequest_n, active low -- Array of signals of fault injection command - to array fi_mem_agent clk_o : OUT STD_LOGIC; rst_o : OUT STD_LOGIC; fi_o : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0); -- chipselect fi_wr_o : OUT STD_LOGIC; -- write fi_A_o : OUT STD_LOGIC_VECTOR(aw_max-1 DOWNTO 0); -- address fi_Mask_o : OUT STD_LOGIC_VECTOR(dw_max-1 DOWNTO 0); -- writedata fi_data_r_o : IN STD_LOGIC_VECTOR(dw_max*N-1 DOWNTO 0); -- readdata - debug feature fi_ack_o : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) -- waitrequest_n ); END fi_mem_connector; ARCHITECTURE rtl OF fi_mem_connector IS SIGNAL fi_A_i_rg : STD_LOGIC_VECTOR(aw_max+iw-1 DOWNTO 0); -- for readdata - debug feature BEGIN assert (N < 2**iw+1) report "N > 2**iw in fi_mem_connector" severity error; -- clk, reset clk_o <= clk_i; rst_o <= rst_i; -- chipselect -- select fi_o, addressed by iw msb bits of fi_A_i PROCESS(fi_A_i, fi_i) BEGIN FOR i IN 0 TO N-1 LOOP IF (((fi_A_i(aw_max+iw-1 DOWNTO aw_max)=i) AND (iw>0)) OR (iw=0)) AND fi_i='1' THEN fi_o(i) <= '1'; ELSE fi_o(i) <= '0'; END IF; END LOOP; END PROCESS; -- write fi_wr_o <= fi_wr_i; -- address fi_A_o <= fi_A_i(aw_max-1 DOWNTO 0); -- writedata fi_Mask_o <= fi_Mask_i; -- waitrequest_n PROCESS(fi_A_i, fi_ack_o) VARIABLE fi_ack_i_tmp : STD_LOGIC; BEGIN fi_ack_i_tmp := '1'; -- not active FOR i IN 0 TO N-1 LOOP fi_ack_i_tmp := fi_ack_i_tmp AND fi_ack_o(i); END LOOP; fi_ack_i <= fi_ack_i_tmp; END PROCESS; -- readdata - debug feature PROCESS(fi_A_i_rg, fi_data_r_o) BEGIN fi_data_r_i <= (OTHERS=>'0'); FOR i IN 0 TO N-1 LOOP IF ((fi_A_i_rg(aw_max+iw-1 DOWNTO aw_max)=i) AND (iw>0)) OR (iw=0) THEN fi_data_r_i <= fi_data_r_o(i*dw_max + dw_max -1 DOWNTO i*dw_max); END IF; END LOOP; END PROCESS; PROCESS(clk_i, rst_i, fi_A_i) BEGIN IF rst_i = '0' THEN fi_A_i_rg <= (OTHERS=>'0'); ELSIF clk_i'event AND clk_i = '1' THEN IF fi_i='1' THEN fi_A_i_rg <= fi_A_i; END IF; END IF; END PROCESS; END rtl;
mit
111af3551338243d0ef2dfd064cb4feb
0.557751
2.80409
false
false
false
false
OrganicMonkeyMotion/fpga_experiments
small_board/LABS/digital_logic/vhdl/lab2/part4/lpm_constant3.vhd
1
3,515
-- megafunction wizard: %LPM_CONSTANT% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: LPM_CONSTANT -- ============================================================ -- File Name: lpm_constant3.vhd -- Megafunction Name(s): -- LPM_CONSTANT -- -- Simulation Library Files(s): -- lpm -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition -- ************************************************************ --Copyright (C) 1991-2011 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.all; ENTITY lpm_constant3 IS PORT ( result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) ); END lpm_constant3; ARCHITECTURE SYN OF lpm_constant3 IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0); COMPONENT lpm_constant GENERIC ( lpm_cvalue : NATURAL; lpm_hint : STRING; lpm_type : STRING; lpm_width : NATURAL ); PORT ( result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) ); END COMPONENT; BEGIN result <= sub_wire0(0 DOWNTO 0); LPM_CONSTANT_component : LPM_CONSTANT GENERIC MAP ( lpm_cvalue => 0, lpm_hint => "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=I0", lpm_type => "LPM_CONSTANT", lpm_width => 1 ) PORT MAP ( result => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1" -- Retrieval info: PRIVATE: JTAG_ID STRING "I0" -- Retrieval info: PRIVATE: Radix NUMERIC "2" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: Value NUMERIC "0" -- Retrieval info: PRIVATE: nBit NUMERIC "1" -- Retrieval info: PRIVATE: new_diagram STRING "1" -- Retrieval info: LIBRARY: lpm lpm.lpm_components.all -- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0" -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=I0" -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1" -- Retrieval info: USED_PORT: result 0 0 1 0 OUTPUT NODEFVAL "result[0..0]" -- Retrieval info: CONNECT: result 0 0 1 0 @result 0 0 1 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3_inst.vhd FALSE -- Retrieval info: LIB_FILE: lpm
unlicense
4b32b57650a35af95ccfc2df260ca465
0.646657
3.804113
false
false
false
false
systec-dk/openPOWERLINK_systec
Examples/ipcore/common/openmac/src/openMAC_phyAct.vhd
3
3,980
------------------------------------------------------------------------------- -- -- (c) B&R, 2011 -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.math_real.log2; use ieee.math_real.ceil; entity OpenMAC_phyAct is generic( iBlinkFreq_g : integer := 6 -- [Hz] ); port( clk : in std_logic; rst : in std_logic; tx_en : in std_logic; rx_dv : in std_logic; act_led : out std_logic ); end OpenMAC_phyAct; architecture rtl of OpenMAC_phyAct is constant iMaxCnt : integer := 50e6 / iBlinkFreq_g; constant iLog2MaxCnt : integer := integer(ceil(log2(real(iMaxCnt)))); signal cnt : std_logic_vector(iLog2MaxCnt-1 downto 0); signal cnt_tc : std_logic; signal actTrig : std_logic; signal actEnable : std_logic; begin act_led <= cnt(cnt'high) when actEnable = '1' else '0'; ledCntr : process(clk, rst) begin if rst = '1' then actTrig <= '0'; actEnable <= '0'; elsif clk = '1' and clk'event then --monoflop, of course no default value! if actTrig = '1' and cnt_tc = '1' then --counter overflow and activity within last cycle actEnable <= '1'; elsif cnt_tc = '1' then --counter overflow but no activity actEnable <= '0'; end if; --monoflop, of course no default value! if cnt_tc = '1' then --count cycle over, reset trigger actTrig <= '0'; elsif tx_en = '1' or rx_dv = '1' then --activity within cycle actTrig <= '1'; end if; end if; end process; theFreeRunCnt : process(clk, rst) begin if rst = '1' then cnt <= (others => '0'); elsif clk = '1' and clk'event then --nice, it may count for ever! cnt <= cnt - 1; end if; end process; cnt_tc <= '1' when cnt = 0 else '0'; --"counter overflow" end rtl;
gpl-2.0
1b48b728ed76c2cd3a3bc9dad5deb9b4
0.571608
4.27957
false
false
false
false
OrganicMonkeyMotion/fpga_experiments
small_board/LABS/digital_logic/vhdl/lab1/part2/part2_VHDL/part2.vhd
1
3,648
--------------------------------------------------------------------------------------------------- -- DEEDS (Digital Electronics Education and Design Suite) -- VHDL Code generated on (6/6/2014, 9:53:06 PM) -- by the Digital Circuit Simulator(d-DcS) -- Ver. 1.80.100 (March 21, 2014) -- Copyright(c)2002-2014 University of Genoa, Italy -- Web Site: http://www.esng.dibe.unige.it/deeds --------------------------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.all; ENTITY part2 IS PORT( ---------------------------------------------------------------------------------> Inputs: iID0032: IN std_logic; iID0034: IN std_logic; iID0055: IN std_logic; iID0057: IN std_logic; iID0078: IN std_logic; iID0080: IN std_logic; iID0101: IN std_logic; iID0102: IN std_logic; iID0103: IN std_logic; ---------------------------------------------------------------------------------> Outputs: oID0035: OUT std_logic; oID0058: OUT std_logic; oID0081: OUT std_logic; oID0104: OUT std_logic --------------------------------------------------------------------------------- ); END part2; ARCHITECTURE structural OF part2 IS ----------------------------------------------------------------------------------> Components: COMPONENT NOT_gate IS PORT( I: IN std_logic; O: OUT std_logic ); END COMPONENT; -- COMPONENT AND2_gate IS PORT( I0,I1: IN std_logic; O: OUT std_logic ); END COMPONENT; -- COMPONENT OR2_gate IS PORT( I0,I1: IN std_logic; O: OUT std_logic ); END COMPONENT; ----------------------------------------------------------------------------------> Signals: SIGNAL S001: std_logic; SIGNAL S002: std_logic; SIGNAL S003: std_logic; SIGNAL S004: std_logic; SIGNAL S005: std_logic; SIGNAL S006: std_logic; SIGNAL S007: std_logic; SIGNAL S008: std_logic; SIGNAL S009: std_logic; SIGNAL S010: std_logic; SIGNAL S011: std_logic; SIGNAL S012: std_logic; SIGNAL S013: std_logic; SIGNAL S014: std_logic; SIGNAL S015: std_logic; SIGNAL S016: std_logic; SIGNAL S017: std_logic; SIGNAL S018: std_logic; SIGNAL S019: std_logic; SIGNAL S020: std_logic; SIGNAL S021: std_logic; SIGNAL S022: std_logic; BEGIN -- structural ----------------------------------------------------------------------------------> Input: S001 <= iID0032; S002 <= iID0034; S006 <= iID0055; S007 <= iID0057; S011 <= iID0078; S012 <= iID0080; S016 <= iID0101; S022 <= iID0102; S017 <= iID0103; ----------------------------------------------------------------------------------> Output: oID0035 <= S003; oID0058 <= S008; oID0081 <= S013; oID0104 <= S018; ----------------------------------------------------------------------------------> Component Mapping: C037: OR2_gate PORT MAP ( S005, S004, S003 ); C038: AND2_gate PORT MAP ( S022, S001, S004 ); C039: AND2_gate PORT MAP ( S002, S021, S005 ); C060: OR2_gate PORT MAP ( S010, S009, S008 ); C061: AND2_gate PORT MAP ( S022, S006, S009 ); C062: AND2_gate PORT MAP ( S007, S021, S010 ); C083: OR2_gate PORT MAP ( S015, S014, S013 ); C084: AND2_gate PORT MAP ( S022, S011, S014 ); C085: AND2_gate PORT MAP ( S012, S021, S015 ); C105: NOT_gate PORT MAP ( S022, S021 ); C106: OR2_gate PORT MAP ( S020, S019, S018 ); C107: AND2_gate PORT MAP ( S022, S016, S019 ); C108: AND2_gate PORT MAP ( S017, S021, S020 ); END structural;
unlicense
293181e4e57a48d1807a6ff67134d21a
0.475329
3.711089
false
false
false
false
OrganicMonkeyMotion/fpga_experiments
small_board/LABS/digital_logic/vhdl/lab1/part6a/DE1_displ.vhdl
1
2,295
-- Warning R1: No reset specified -- Created by fizzim.pl version $Revision: 5.0 on 2014:07:06 at 21:08:20 (www.fizzim.com) library ieee; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity DE1_disp is port ( DISPn : out STD_LOGIC_VECTOR(3 downto 0); HEX : out STD_LOGIC_VECTOR(6 downto 0); HEX0 : in STD_LOGIC_VECTOR(6 downto 0); HEX1 : in STD_LOGIC_VECTOR(6 downto 0); HEX2 : in STD_LOGIC_VECTOR(6 downto 0); HEX3 : in STD_LOGIC_VECTOR(6 downto 0); clk : in STD_LOGIC ); end DE1_disp; architecture fizzim of DE1_disp is -- state bits subtype state_type is STD_LOGIC_VECTOR(1 downto 0); constant state0: state_type:="00"; constant state1: state_type:="01"; constant state2: state_type:="10"; constant state3: state_type:="11"; signal state,nextstate: state_type; signal DISPn_internal: STD_LOGIC_VECTOR(3 downto 0); signal HEX_internal: STD_LOGIC_VECTOR(6 downto 0); -- comb always block begin COMB: process(state,HEX0(6 downto 0),HEX1(6 downto 0),HEX2(6 downto 0),HEX3(6 downto 0),clk,DISPn_internal(3 downto 0),HEX_internal(6 downto 0)) begin -- Warning I2: Neither implied_loopback nor default_state_is_x attribute is set on state machine - defaulting to implied_loopback to avoid latches being inferred nextstate <= state; -- default to hold value because implied_loopback is set case state is when state0 => DISPn_internal(3 downto 0) <= "1110"; HEX_internal(6 downto 0) <= HEX0(6 downto 0); nextstate <= state1; when state1 => DISPn_internal(3 downto 0) <= "1101"; HEX_internal(6 downto 0) <= HEX1(6 downto 0); nextstate <= state2; when state2 => DISPn_internal(3 downto 0) <= "1011"; HEX_internal(6 downto 0) <= HEX2(6 downto 0); nextstate <= state3; when state3 => DISPn_internal(3 downto 0) <= "0111"; HEX_internal(6 downto 0) <= HEX3(6 downto 0); nextstate <= state0; when others => end case; end process; -- Assign reg'd outputs to state bits -- Port renames for vhdl DISPn(3 downto 0) <= DISPn_internal(3 downto 0); HEX(6 downto 0) <= HEX_internal(6 downto 0); -- sequential always block FF: process(clk,nextstate) begin state <= nextstate; end process; end fizzim;
unlicense
5c655ba9a51a46ce89ea88fc438cc16b
0.662745
3.335756
false
false
false
false
systec-dk/openPOWERLINK_systec
Examples/ipcore/common/lib/src/global.vhd
3
4,026
------------------------------------------------------------------------------- -- Global package -- -- Copyright (C) 2012 B&R -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- -- ------------------------------------------------------------------------------- -- Version History ------------------------------------------------------------------------------- -- 2012-02-07 zelenkaj Derived from global package ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package Global is constant cActivated : std_logic := '1'; constant cInactivated : std_logic := '0'; constant cnActivated : std_logic := '0'; constant cnInactivated : std_logic := '1'; function LogDualis(cNumber : natural) return natural; function MAX (a : natural; b : natural) return natural; function MIN (a : natural; b : natural) return natural; function integerToBoolean (a : integer) return boolean; function booleanToInteger (a : boolean) return integer; end Global; package body Global is function LogDualis(cNumber : natural) return natural is variable vClimbUp : natural := 1; variable vResult : natural; begin while vClimbUp < cNumber loop vClimbUp := vClimbUp * 2; vResult := vResult+1; end loop; return vResult; end LogDualis; function MAX (a : natural; b : natural) return natural is variable vRes : natural; begin if a > b then vRes := a; else vRes := b; end if; return vRes; end function; function MIN (a : natural; b : natural) return natural is variable vRes : natural; begin if a < b then vRes := a; else vRes := b; end if; return vRes; end function; function integerToBoolean (a : integer) return boolean is variable vRes : boolean; begin if a = 0 then vRes := false; else vRes := true; end if; return vRes; end function; function booleanToInteger (a : boolean) return integer is variable vRes : integer; begin if a = false then vRes := 0; else vRes := 1; end if; return vRes; end function; end Global;
gpl-2.0
28dcba883f1ac664de903f1f015eb85d
0.590909
4.838942
false
false
false
false
notti/dis_lu
vhdl/debounce.vhd
1
1,352
library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library work; entity debounce is generic( CNT : integer := 5000 -- 30 ms at 50 MHz ); port( clk : in std_logic; input : in std_logic; output : out std_logic; riseedge : out std_logic; falledge : out std_logic ); end debounce; architecture beh of debounce is signal scnt : natural := 0; signal values : std_logic_vector(3 downto 0) := (others => '0'); signal io_out : std_logic; signal io_out_dly : std_logic; begin io_out <= '1' when values(2 downto 0) = "111" else '0'; output <= io_out; riseedge <= io_out and (not io_out_dly); falledge <= (not io_out) and io_out_dly; io_dly: process(clk) begin if rising_edge(clk) then io_out_dly <= io_out; end if; end process; shift_in: process(clk, scnt) begin if rising_edge(clk) and scnt = CNT then values <= input & values(3 downto 1); end if; end process; delay_cnt : process(clk) begin if rising_edge(clk) then if scnt = CNT then scnt <= 0; else scnt <= scnt + 1; end if; end if; end process; end architecture beh;
mit
3cfceb2b122c660fe9b11e1454833e21
0.526627
3.49354
false
false
false
false
Alix82/mip32vhdl
memory-rw.vhd
1
1,432
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; library work; use work.mips_constants.all; Entity memory_rw is Port (clk : in std_logic; inaluresult : in std_logic_vector(31 downto 0); memwritedata : in std_logic_vector(31 downto 0); memtoreg : in std_logic; memread : in std_logic; memwrite : in std_logic; o_memaddr : out std_logic_vector(31 downto 0); o_read : out std_logic; o_write : out std_logic; o_writedata : out std_logic_vector(31 downto 0) ); End; Architecture rtl of memory_rw is signal debug_addr : std_logic_vector(31 downto 0); begin process(clk) begin if rising_edge(clk) then if memread = '1' then debug_addr <= inaluresult; o_memaddr <= inaluresult; o_read <= '1'; else --o_memaddr <= (others => '0'); o_read <= '0'; end if; if memwrite = '1' then o_memaddr <= inaluresult; o_writedata <= memwritedata; o_write <= '1'; else --o_memaddr <= (others => '0'); o_writedata <= (others => '0'); o_write <= '0'; end if; end if; end process; end;
bsd-2-clause
e854304176f707e54fb996200afe9b10
0.47486
3.944904
false
false
false
false
systec-dk/openPOWERLINK_systec
Examples/ipcore/common/pdi/src/pdi_event.vhd
3
8,305
------------------------------------------------------------------------------- -- Process Data Interface (PDI) event handling -- -- Copyright (C) 2011 B&R -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; --the order of events: -- e.g. sw event = 1 and hw event = 2 -- event = (HW1 & HW0 & SW0) -- pcp only sets SW0, but can read SW0 -- ap ack all events entity pdiEvent is generic ( genOnePdiClkDomain_g : boolean := false; iSwEvent_g : integer := 1; iHwEvent_g : integer := 2 ); port ( --port A -> PCP clkA : in std_logic; rstA : in std_logic; eventSetA : in std_logic_vector(iSwEvent_g-1 downto 0); --to set event (pulse!) eventReadA : out std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0); --to read event set (can be acked by ap!!!) --port B -> AP clkB : in std_logic; rstB : in std_logic; eventAckB : in std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0); --to ack events (pulse!) eventReadB : out std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0); --to read event set --hw event set pulse (must be synchronous to clkB!) hwEventSetPulseB : in std_logic_vector(iHwEvent_g-1 downto 0) ); end entity pdiEvent; architecture rtl of pdiEvent is --in clk domain A signal eventA_s, --stores the events in A domain eventA_ackPulse --ack the event (by ap) : std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0); signal eventA_setPulse --sets the sw event only (by pcp) : std_logic_vector(iSwEvent_g-1 downto 0); signal hwEventA_setPulse --sets the hw event only : std_logic_vector(iHwEvent_g-1 downto 0); --in clk domain B signal eventB_s, --stores the events in B domain eventB_ackPulse --ack the event (by ap) : std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0); signal eventB_setPulse --sets the sw event only (by pcp) : std_logic_vector(iSwEvent_g-1 downto 0); begin --pcp eventReadA <= eventA_s; --eventA_s stores all events --eventA_ackPulse sends acks for all events --eventA_setPulse sends set for sw event only eventA_setPulse <= eventSetA; --hwEventA_setPulse sends set for hw event only process(clkA, rstA) variable event_var : std_logic_vector(eventA_s'range); begin if rstA = '1' then eventA_s <= (others => '0'); elsif clkA = '1' and clkA'event then --get event state to do magic event_var := eventA_s; --first let the ack does its work... event_var := event_var and not eventA_ackPulse; --second the sw events may overwrite the ack... event_var(iSwEvent_g-1 downto 0) := event_var(iSwEvent_g-1 downto 0) or eventA_setPulse(iSwEvent_g-1 downto 0); --last but not least, the hw events have its chance too event_var(iSwEvent_g+iHwEvent_g-1 downto iSwEvent_g) := event_var(iSwEvent_g+iHwEvent_g-1 downto iSwEvent_g) or hwEventA_setPulse(iHwEvent_g-1 downto 0); --and now, export it eventA_s <= event_var; end if; end process; --ap eventReadB <= eventB_s; --eventB_s stores all events --eventB_ackPulse sends acks for all events eventB_ackPulse <= eventAckB; --eventB_setPulse sends set for sw event only --hwEventSetPulseB sends set for hw event only process(clkB, rstB) variable event_var : std_logic_vector(eventB_s'range); begin if rstB = '1' then eventB_s <= (others => '0'); elsif clkB = '1' and clkB'event then --I know, its almost the same as for A, but for clarity... --get event state event_var := eventB_s; --doing ack event_var := event_var and not eventB_ackPulse; --sw events may overwrite event_var(iSwEvent_g-1 downto 0) := event_var(iSwEvent_g-1 downto 0) or eventB_setPulse(iSwEvent_g-1 downto 0); --hw events may overwrite too event_var(iSwEvent_g+iHwEvent_g-1 downto iSwEvent_g) := event_var(iSwEvent_g+iHwEvent_g-1 downto iSwEvent_g) or hwEventSetPulseB(iHwEvent_g-1 downto 0); --and let's export eventB_s <= event_var; end if; end process; --xing the domains a to b syncEventSetGen : for i in 0 to iSwEvent_g-1 generate --only the software events are transferred! syncEventSet : entity work.slow2fastSync generic map ( doSync_g => not genOnePdiClkDomain_g ) port map ( clkSrc => clkA, rstSrc => rstA, dataSrc => eventA_setPulse(i), clkDst => clkB, rstDst => rstB, dataDst => eventB_setPulse(i) ); end generate; --xing the domains b to a syncEventAckGen : for i in eventB_s'range generate --all events are transferred syncEventAck : entity work.slow2fastSync generic map ( doSync_g => not genOnePdiClkDomain_g ) port map ( clkSrc => clkB, rstSrc => rstB, dataSrc => eventB_ackPulse(i), clkDst => clkA, rstDst => rstA, dataDst => eventA_ackPulse(i) ); end generate; syncHwEventGen : for i in 0 to iHwEvent_g-1 generate --hw events are transferred syncEventAck : entity work.slow2fastSync generic map ( doSync_g => not genOnePdiClkDomain_g ) port map ( clkSrc => clkB, rstSrc => rstB, dataSrc => hwEventSetPulseB(i), clkDst => clkA, rstDst => rstA, dataDst => hwEventA_setPulse(i) ); end generate; end architecture rtl;
gpl-2.0
2e6ecff896ee876dc0b168942fb15361
0.558338
4.389535
false
false
false
false
systec-dk/openPOWERLINK_systec
Examples/ipcore/common/pdi/src/pdi_led.vhd
3
3,805
------------------------------------------------------------------------------- -- Process Data Interface (PDI) led gadget -- -- Copyright (C) 2011 B&R -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; --the led gadget can be set by three different sources -- source A, B and C -- the highest priority has C entity pdiLed is generic ( iLedWidth_g : integer := 8 ); port ( --src A srcAled : in std_logic_vector(iLedWidth_g-1 downto 0); srcAforce : in std_logic_vector(iLedWidth_g-1 downto 0); --src B srcBled : in std_logic_vector(iLedWidth_g-1 downto 0); srcBforce : in std_logic_vector(iLedWidth_g-1 downto 0); --src C srcCled : in std_logic_vector(iLedWidth_g-1 downto 0); srcCforce : in std_logic_vector(iLedWidth_g-1 downto 0); --led output ledOut : out std_logic_vector(iLedWidth_g-1 downto 0) ); end entity pdiLed; architecture rtl of pdiLed is begin theLedGadget : process(srcAled, srcAforce, srcBled, srcBforce, srcCled, srcCforce) variable tmp_led : std_logic_vector(ledOut'range); begin tmp_led := (others => '0'); for i in tmp_led'range loop --okay, src A may drive if forced if srcAforce(i) = '1' then tmp_led(i) := srcAled(i); end if; --same vaild for src B, but it overrules src A if srcBforce(i) = '1' then tmp_led(i) := srcBled(i); end if; --and the head of the logics => src C if srcCforce(i) = '1' then tmp_led(i) := srcCled(i); end if; end loop; --let's export and go for a coffee... ledOut <= tmp_led; end process; end architecture rtl;
gpl-2.0
7073be8ee4ac7de34030e608c5b3d567
0.583706
4.241918
false
false
false
false
simonspa/pixel-dtb-firmware
dtb/ram_init.vhd
2
14,501
-- megafunction wizard: %RAM initializer% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: ALTMEM_INIT -- ============================================================ -- File Name: ram_init.vhd -- Megafunction Name(s): -- ALTMEM_INIT -- -- Simulation Library Files(s): -- lpm -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version -- ************************************************************ --Copyright (C) 1991-2012 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. --altmem_init CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone III" INIT_TO_ZERO="YES" NUMWORDS=256 PORT_ROM_DATA_READY="PORT_UNUSED" ROM_READ_LATENCY=1 WIDTH=8 WIDTHAD=8 clock dataout init init_busy ram_address ram_wren --VERSION_BEGIN 12.1SP1 cbx_altmem_init 2013:01:31:18:04:58:SJ cbx_altsyncram 2013:01:31:18:04:59:SJ cbx_cycloneii 2013:01:31:18:04:59:SJ cbx_lpm_add_sub 2013:01:31:18:04:59:SJ cbx_lpm_compare 2013:01:31:18:04:59:SJ cbx_lpm_counter 2013:01:31:18:04:59:SJ cbx_lpm_decode 2013:01:31:18:04:59:SJ cbx_lpm_mux 2013:01:31:18:04:59:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_stratix 2013:01:31:18:04:59:SJ cbx_stratixii 2013:01:31:18:04:59:SJ cbx_stratixiii 2013:01:31:18:05:00:SJ cbx_stratixv 2013:01:31:18:05:00:SJ cbx_util_mgl 2013:01:31:18:04:59:SJ VERSION_END LIBRARY lpm; USE lpm.all; --synthesis_resources = lpm_compare 2 lpm_counter 2 reg 5 LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY ram_init_meminit_m6k IS PORT ( clock : IN STD_LOGIC; dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); init : IN STD_LOGIC; init_busy : OUT STD_LOGIC; ram_address : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); ram_wren : OUT STD_LOGIC ); END ram_init_meminit_m6k; ARCHITECTURE RTL OF ram_init_meminit_m6k IS SIGNAL capture_init : STD_LOGIC_VECTOR(0 DOWNTO 0) -- synopsys translate_off := (OTHERS => '0') -- synopsys translate_on ; SIGNAL prev_state : STD_LOGIC_VECTOR(1 DOWNTO 0) -- synopsys translate_off := (OTHERS => '0') -- synopsys translate_on ; SIGNAL wire_prev_state_w_lg_w_q_range41w43w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_prev_state_w_lg_w_q_range40w42w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_prev_state_w_q_range40w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_prev_state_w_q_range41w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_state_reg_d : STD_LOGIC_VECTOR (1 DOWNTO 0); SIGNAL state_reg : STD_LOGIC_VECTOR(1 DOWNTO 0) -- synopsys translate_off := (OTHERS => '0') -- synopsys translate_on ; SIGNAL wire_state_reg_sclr : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL wire_state_reg_sload : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL wire_state_reg_w_lg_w_q_range2w7w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_state_reg_w_lg_w_q_range1w3w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_state_reg_w_lg_w_q_range22w24w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_state_reg_w_lg_w_q_range31w33w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_state_reg_w_q_range1w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_state_reg_w_q_range2w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_state_reg_w_q_range22w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_state_reg_w_q_range31w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_addr_cmpr_aeb : STD_LOGIC; SIGNAL wire_addr_cmpr_alb : STD_LOGIC; SIGNAL wire_addr_cmpr_datab : STD_LOGIC_VECTOR (7 DOWNTO 0); SIGNAL wire_wait_cmpr_aeb : STD_LOGIC; SIGNAL wire_wait_cmpr_alb : STD_LOGIC; SIGNAL wire_gnd_vector : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_addr_ctr_cnt_en : STD_LOGIC; SIGNAL wire_addr_ctr_q : STD_LOGIC_VECTOR (7 DOWNTO 0); SIGNAL wire_wait_ctr_q : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_wait_ctr_sclr : STD_LOGIC; SIGNAL wire_w_lg_ram_addr_state44w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_init38w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL addrct_eq_numwords : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL addrct_lt_numwords : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL clken : STD_LOGIC; SIGNAL done_state : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL idle_state : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL ram_addr_state : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL ram_write_state : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL reset_state_machine : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL state_machine_clken : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL waitct_eq_latency : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL waitct_lt_latency : STD_LOGIC_VECTOR (0 DOWNTO 0); COMPONENT lpm_compare GENERIC ( LPM_PIPELINE : NATURAL := 0; LPM_REPRESENTATION : STRING := "UNSIGNED"; LPM_WIDTH : NATURAL; lpm_hint : STRING := "UNUSED"; lpm_type : STRING := "lpm_compare" ); PORT ( aclr : IN STD_LOGIC := '0'; aeb : OUT STD_LOGIC; agb : OUT STD_LOGIC; ageb : OUT STD_LOGIC; alb : OUT STD_LOGIC; aleb : OUT STD_LOGIC; aneb : OUT STD_LOGIC; clken : IN STD_LOGIC := '1'; clock : IN STD_LOGIC := '0'; dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0') ); END COMPONENT; COMPONENT lpm_counter GENERIC ( lpm_avalue : STRING := "0"; lpm_direction : STRING := "DEFAULT"; lpm_modulus : NATURAL := 0; lpm_port_updown : STRING := "PORT_CONNECTIVITY"; lpm_pvalue : STRING := "0"; lpm_svalue : STRING := "0"; lpm_width : NATURAL; lpm_type : STRING := "lpm_counter" ); PORT ( aclr : IN STD_LOGIC := '0'; aload : IN STD_LOGIC := '0'; aset : IN STD_LOGIC := '0'; cin : IN STD_LOGIC := '1'; clk_en : IN STD_LOGIC := '1'; clock : IN STD_LOGIC; cnt_en : IN STD_LOGIC := '1'; cout : OUT STD_LOGIC; data : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); eq : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); q : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0); sclr : IN STD_LOGIC := '0'; sload : IN STD_LOGIC := '0'; sset : IN STD_LOGIC := '0'; updown : IN STD_LOGIC := '1' ); END COMPONENT; BEGIN wire_gnd_vector <= "0"; wire_w_lg_init38w(0) <= init OR capture_init(0); addrct_eq_numwords(0) <= wire_addr_cmpr_aeb; addrct_lt_numwords(0) <= wire_addr_cmpr_alb; clken <= '1'; dataout <= (OTHERS => '0'); done_state(0) <= (state_reg(1) AND state_reg(0)); idle_state(0) <= ((NOT state_reg(1)) AND wire_state_reg_w_lg_w_q_range1w3w(0)); init_busy <= capture_init(0); ram_addr_state(0) <= ((NOT state_reg(1)) AND state_reg(0)); ram_address <= wire_addr_ctr_q; ram_wren <= ((NOT prev_state(1)) AND prev_state(0)); ram_write_state(0) <= wire_state_reg_w_lg_w_q_range2w7w(0); reset_state_machine(0) <= (ram_write_state(0) AND addrct_lt_numwords(0)); state_machine_clken(0) <= (clken AND (((idle_state(0) AND capture_init(0)) OR (done_state(0) AND waitct_eq_latency(0))) OR (capture_init(0) AND (((NOT (ram_addr_state(0) AND waitct_lt_latency(0))) OR (ram_addr_state(0) AND waitct_eq_latency(0))) OR (ram_write_state(0) AND addrct_eq_numwords(0)))))); waitct_eq_latency(0) <= wire_wait_cmpr_aeb; waitct_lt_latency(0) <= wire_wait_cmpr_alb; PROCESS (clock) BEGIN IF (clock = '1' AND clock'event) THEN IF (clken = '1') THEN capture_init(0) <= (wire_w_lg_init38w(0) AND (NOT done_state(0))); END IF; END IF; END PROCESS; PROCESS (clock) BEGIN IF (clock = '1' AND clock'event) THEN IF (clken = '1') THEN prev_state <= state_reg; END IF; END IF; END PROCESS; wire_prev_state_w_lg_w_q_range41w43w(0) <= wire_prev_state_w_q_range41w(0) AND wire_prev_state_w_lg_w_q_range40w42w(0); wire_prev_state_w_lg_w_q_range40w42w(0) <= NOT wire_prev_state_w_q_range40w(0); wire_prev_state_w_q_range40w(0) <= prev_state(0); wire_prev_state_w_q_range41w(0) <= prev_state(1); PROCESS (clock) BEGIN IF (clock = '1' AND clock'event) THEN IF (state_machine_clken(0) = '1') THEN IF (wire_state_reg_sclr(0) = '1') THEN state_reg(0) <= '0'; ELSIF (wire_state_reg_sload(0) = '1') THEN state_reg(0) <= '1'; ELSE state_reg(0) <= wire_state_reg_d(0); END IF; END IF; END IF; END PROCESS; PROCESS (clock) BEGIN IF (clock = '1' AND clock'event) THEN IF (state_machine_clken(0) = '1') THEN IF (wire_state_reg_sclr(1) = '1') THEN state_reg(1) <= '0'; ELSIF (wire_state_reg_sload(1) = '1') THEN state_reg(1) <= '1'; ELSE state_reg(1) <= wire_state_reg_d(1); END IF; END IF; END IF; END PROCESS; wire_state_reg_d <= ( wire_state_reg_w_lg_w_q_range31w33w & wire_state_reg_w_lg_w_q_range22w24w); wire_state_reg_sclr <= ( reset_state_machine & "0"); wire_state_reg_sload <= ( "0" & reset_state_machine); wire_state_reg_w_lg_w_q_range2w7w(0) <= wire_state_reg_w_q_range2w(0) AND wire_state_reg_w_lg_w_q_range1w3w(0); wire_state_reg_w_lg_w_q_range1w3w(0) <= NOT wire_state_reg_w_q_range1w(0); wire_state_reg_w_lg_w_q_range22w24w(0) <= NOT wire_state_reg_w_q_range22w(0); wire_state_reg_w_lg_w_q_range31w33w(0) <= wire_state_reg_w_q_range31w(0) XOR wire_state_reg_w_q_range22w(0); wire_state_reg_w_q_range1w(0) <= state_reg(0); wire_state_reg_w_q_range2w(0) <= state_reg(1); wire_state_reg_w_q_range22w(0) <= state_reg(0); wire_state_reg_w_q_range31w(0) <= state_reg(1); wire_addr_cmpr_datab <= (OTHERS => '1'); addr_cmpr : lpm_compare GENERIC MAP ( LPM_WIDTH => 8 ) PORT MAP ( aeb => wire_addr_cmpr_aeb, alb => wire_addr_cmpr_alb, dataa => wire_addr_ctr_q, datab => wire_addr_cmpr_datab ); wait_cmpr : lpm_compare GENERIC MAP ( LPM_WIDTH => 1 ) PORT MAP ( aeb => wire_wait_cmpr_aeb, alb => wire_wait_cmpr_alb, dataa => wire_wait_ctr_q, datab => wire_gnd_vector ); wire_addr_ctr_cnt_en <= wire_prev_state_w_lg_w_q_range41w43w(0); addr_ctr : lpm_counter GENERIC MAP ( lpm_direction => "UP", lpm_modulus => 256, lpm_port_updown => "PORT_UNUSED", lpm_width => 8 ) PORT MAP ( clk_en => clken, clock => clock, cnt_en => wire_addr_ctr_cnt_en, q => wire_addr_ctr_q, sclr => idle_state(0) ); wire_wait_ctr_sclr <= wire_w_lg_ram_addr_state44w(0); wire_w_lg_ram_addr_state44w(0) <= NOT ram_addr_state(0); wait_ctr : lpm_counter GENERIC MAP ( lpm_direction => "UP", lpm_modulus => 1, lpm_port_updown => "PORT_UNUSED", lpm_width => 1 ) PORT MAP ( clk_en => clken, clock => clock, cnt_en => ram_addr_state(0), q => wire_wait_ctr_q, sclr => wire_wait_ctr_sclr ); END RTL; --ram_init_meminit_m6k --VALID FILE LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY ram_init IS PORT ( clock : IN STD_LOGIC ; init : IN STD_LOGIC ; dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); init_busy : OUT STD_LOGIC ; ram_address : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); ram_wren : OUT STD_LOGIC ); END ram_init; ARCHITECTURE RTL OF ram_init IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC ; SIGNAL sub_wire2 : STD_LOGIC_VECTOR (7 DOWNTO 0); SIGNAL sub_wire3 : STD_LOGIC ; COMPONENT ram_init_meminit_m6k PORT ( clock : IN STD_LOGIC ; dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); init : IN STD_LOGIC ; init_busy : OUT STD_LOGIC ; ram_address : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); ram_wren : OUT STD_LOGIC ); END COMPONENT; BEGIN dataout <= sub_wire0(7 DOWNTO 0); init_busy <= sub_wire1; ram_address <= sub_wire2(7 DOWNTO 0); ram_wren <= sub_wire3; ram_init_meminit_m6k_component : ram_init_meminit_m6k PORT MAP ( clock => clock, init => init, dataout => sub_wire0, init_busy => sub_wire1, ram_address => sub_wire2, ram_wren => sub_wire3 ); END RTL; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: CONSTANT: INIT_FILE STRING "UNUSED" -- Retrieval info: CONSTANT: INIT_TO_ZERO STRING "YES" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altmem_init" -- Retrieval info: CONSTANT: NUMWORDS NUMERIC "256" -- Retrieval info: CONSTANT: PORT_ROM_DATA_READY STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: ROM_READ_LATENCY NUMERIC "1" -- Retrieval info: CONSTANT: WIDTH NUMERIC "8" -- Retrieval info: CONSTANT: WIDTHAD NUMERIC "8" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" -- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -- Retrieval info: USED_PORT: dataout 0 0 8 0 OUTPUT NODEFVAL "dataout[7..0]" -- Retrieval info: CONNECT: dataout 0 0 8 0 @dataout 0 0 8 0 -- Retrieval info: USED_PORT: init 0 0 0 0 INPUT NODEFVAL "init" -- Retrieval info: CONNECT: @init 0 0 0 0 init 0 0 0 0 -- Retrieval info: USED_PORT: init_busy 0 0 0 0 OUTPUT NODEFVAL "init_busy" -- Retrieval info: CONNECT: init_busy 0 0 0 0 @init_busy 0 0 0 0 -- Retrieval info: USED_PORT: ram_address 0 0 8 0 OUTPUT NODEFVAL "ram_address[7..0]" -- Retrieval info: CONNECT: ram_address 0 0 8 0 @ram_address 0 0 8 0 -- Retrieval info: USED_PORT: ram_wren 0 0 0 0 OUTPUT NODEFVAL "ram_wren" -- Retrieval info: CONNECT: ram_wren 0 0 0 0 @ram_wren 0 0 0 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_init.vhd TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_init.qip TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_init.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_init_inst.vhd TRUE TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_init.inc TRUE TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_init.cmp TRUE TRUE -- Retrieval info: LIB_FILE: lpm
unlicense
92a4130710ea480a74ec78352317470f
0.650162
2.709454
false
false
false
false
OrganicMonkeyMotion/fpga_experiments
bmax10/BeMicro_full_reference_project/top.vhd
1
9,665
-- top.vhd -- this VHDL design instatiates a Qsys system with a Nios II processor that has access to the many diffent peripherals -- on the BeMicro Max 10 board. -- -- There are many different software examples included in the software folder. library ieee; use ieee.std_logic_1164.all; entity top is port ( SYS_CLK : in std_logic := 'X'; -- clk USER_CLK : in std_logic; PB : in std_logic_vector(4 downto 1) := (others => 'X'); -- export USER_LED : out std_logic_vector(8 downto 1); -- export SDRAM_A : out std_logic_vector(12 downto 0); SDRAM_BA : out std_logic_vector(1 downto 0); SDRAM_CASN : out std_logic; SDRAM_CKE : out std_logic; SDRAM_CSN : out std_logic; SDRAM_DQ : inout std_logic_vector(15 downto 0); SDRAM_DQM : out std_logic_vector(1 downto 0); SDRAM_RASN : out std_logic; SDRAM_WEN : out std_logic; SDRAM_CLK : out std_logic; ADXL362_MISO : in std_logic; ADXL362_MOSI : out std_logic; ADXL362_SCLK : out std_logic; ADXL362_CSn : out std_logic; ADXL362_INT1 : in std_logic; ADXL362_INT2 : in std_logic; ADT7420_SCL : inout std_logic; ADT7420_SDA : inout std_logic; SFLASH_DCLK : out std_logic; SFLASH_CSn : out std_logic; SFLASH_DATA : in std_logic; -- input data from spi flash SFLASH_ASDI : out std_logic; -- this feeds out to the data input of the spi flash AD5681R_LDACn : out std_logic; AD5681R_RSTn : out std_logic; AD5681R_SCL : out std_logic; AD5681R_SDA : out std_logic; AD5681R_SYNCn : out std_logic ); end entity; architecture rtl of top is component nios_system is port ( clk_clk : in std_logic := 'X'; -- clk reset_reset_n : in std_logic := 'X'; -- reset_n button_pio_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export led_pio_export : out std_logic_vector(7 downto 0); -- export sdram_wire_addr : out std_logic_vector(11 downto 0); -- addr sdram_wire_ba : out std_logic_vector(1 downto 0); -- ba sdram_wire_cas_n : out std_logic; -- cas_n sdram_wire_cke : out std_logic; -- cke sdram_wire_cs_n : out std_logic; -- cs_n sdram_wire_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq sdram_wire_dqm : out std_logic_vector(1 downto 0); -- dqm sdram_wire_ras_n : out std_logic; -- ras_n sdram_wire_we_n : out std_logic; -- we_n spi_accelerometer_out_MISO : in std_logic := 'X'; -- MISO spi_accelerometer_out_MOSI : out std_logic; -- MOSI spi_accelerometer_out_SCLK : out std_logic; -- SCLK spi_accelerometer_out_SS_n : out std_logic; -- SS_n i2c_adt7420_export_scl_pad_io : inout std_logic := 'X'; -- scl_pad_io i2c_adt7420_export_sda_pad_io : inout std_logic := 'X'; -- sda_pad_io spi_ad5681_out_MISO : in std_logic := 'X'; -- MISO spi_ad5681_out_MOSI : out std_logic; -- MOSI spi_ad5681_out_SCLK : out std_logic; -- SCLK spi_ad5681_out_SS_n : out std_logic; -- SS_n sdram_clkout_clk : out std_logic; -- clk sdram_pll_areset_conduit_export : in std_logic := 'X'; -- export sdram_pll_locked_conduit_export : out std_logic; -- export adc_pll_areset_conduit_export : in std_logic := 'X'; -- export adc_pll_phasedone_conduit_export : out std_logic; -- export sdram_pll_phasedone_conduit_export : out std_logic; -- export bemicro_max10_serial_flash_controller_0_external_dclk : out std_logic; -- dclk bemicro_max10_serial_flash_controller_0_external_sce : out std_logic; -- sce bemicro_max10_serial_flash_controller_0_external_sdo : out std_logic; -- sdo bemicro_max10_serial_flash_controller_0_external_data0 : in std_logic; clk_adc_clk : in std_logic; adc_clk_reset_reset_n : in std_logic ); end component nios_system; signal async_reset_n : std_logic; signal reset_n : std_logic; signal pll_areset : std_logic; signal reset_sync_n : std_logic_vector(1 downto 0); signal led_export : std_logic_vector(8 downto 1); begin -- push_buttons are active low -- reset the Nios when PB4 and PB1 are pushed simultaneously async_reset_n <= '0' when PB(4) = '0' and PB(1) = '0' else '1'; --reset synchronizer -- this logic will asynchronously reset the whole system, yet -- will synchronously release reset process(SYS_CLK) begin if(async_reset_n = '0') then reset_sync_n <= "00"; -- clear 2-bit reset sync register else if rising_edge(SYS_CLK) then reset_sync_n(0) <= '1'; reset_sync_n(1) <= reset_sync_n(0); end if; end if; end process; reset_n <= reset_sync_n(1); pll_areset <= not reset_sync_n(1); u0 : component nios_system port map ( clk_clk => SYS_CLK, reset_reset_n => reset_n, button_pio_export => PB, led_pio_export => led_export, sdram_wire_addr => SDRAM_A(11 downto 0), sdram_wire_ba => SDRAM_BA, sdram_wire_cas_n => SDRAM_CASN, sdram_wire_cke => SDRAM_CKE, sdram_wire_cs_n => SDRAM_CSN, sdram_wire_dq => SDRAM_DQ, sdram_wire_dqm => SDRAM_DQM, sdram_wire_ras_n => SDRAM_RASN, sdram_wire_we_n => SDRAM_WEN, spi_accelerometer_out_MISO => ADXL362_MISO, spi_accelerometer_out_MOSI => ADXL362_MOSI, spi_accelerometer_out_SCLK => ADXL362_SCLK, spi_accelerometer_out_SS_n => ADXL362_CSn, i2c_adt7420_export_scl_pad_io => ADT7420_SCL, i2c_adt7420_export_sda_pad_io => ADT7420_SDA, spi_ad5681_out_MISO => '1', spi_ad5681_out_MOSI => AD5681R_SDA, spi_ad5681_out_SCLK => AD5681R_SCL, spi_ad5681_out_SS_n => AD5681R_SYNCn, sdram_clkout_clk => SDRAM_CLK, sdram_pll_areset_conduit_export => pll_areset, sdram_pll_locked_conduit_export => open, adc_pll_areset_conduit_export => pll_areset, adc_pll_phasedone_conduit_export => open, sdram_pll_phasedone_conduit_export => open, bemicro_max10_serial_flash_controller_0_external_dclk => SFLASH_DCLK, bemicro_max10_serial_flash_controller_0_external_sce => SFLASH_CSn, bemicro_max10_serial_flash_controller_0_external_sdo => SFLASH_ASDI, bemicro_max10_serial_flash_controller_0_external_data0 => SFLASH_DATA, clk_adc_clk => SYS_CLK, adc_clk_reset_reset_n => reset_n ); SDRAM_a(12) <= '0'; --extra address bit used for larger SDRAM devices --the leds are active low, need to invert USER_LED(8 downto 1) <= not led_export(8 downto 1); AD5681R_LDACn <= '1'; -- LDAC is used to transfer data from the DAC register to the output generating vout. this can also be done in sw AD5681R_RSTn <= reset_n; end rtl;
unlicense
ef92af58a05401d9eb82e62836c3715e
0.440041
3.919303
false
false
false
false
systec-dk/openPOWERLINK_systec
Examples/altera_nios2/SYSTEC_ECUcore-EP3C/design_nios2_directIO/niosII_openMac_clock_1.vhd
3
30,203
--Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your --use of Altera Corporation's design tools, logic functions and other --software and tools, and its AMPP partner logic functions, and any --output files any of the foregoing (including device programming or --simulation files), and any associated documentation or information are --expressly subject to the terms and conditions of the Altera Program --License Subscription Agreement or other applicable license agreement, --including, without limitation, that your use is for the sole purpose --of programming logic devices manufactured by Altera and sold by Altera --or its authorized distributors. Please refer to the applicable --agreement for further details. -- turn off superfluous VHDL processor warnings -- altera message_level Level1 -- altera message_off 10034 10035 10036 10037 10230 10240 10030 library altera; use altera.altera_europa_support_lib.all; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity niosII_openMac_clock_1_edge_to_pulse is port ( -- inputs: signal clock : IN STD_LOGIC; signal data_in : IN STD_LOGIC; signal reset_n : IN STD_LOGIC; -- outputs: signal data_out : OUT STD_LOGIC ); end entity niosII_openMac_clock_1_edge_to_pulse; architecture europa of niosII_openMac_clock_1_edge_to_pulse is signal data_in_d1 : STD_LOGIC; begin process (clock, reset_n) begin if reset_n = '0' then data_in_d1 <= std_logic'('0'); elsif clock'event and clock = '1' then data_in_d1 <= data_in; end if; end process; data_out <= data_in XOR data_in_d1; end europa; -- turn off superfluous VHDL processor warnings -- altera message_level Level1 -- altera message_off 10034 10035 10036 10037 10230 10240 10030 library altera; use altera.altera_europa_support_lib.all; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity niosII_openMac_clock_1_slave_FSM is port ( -- inputs: signal master_read_done_token : IN STD_LOGIC; signal master_write_done_token : IN STD_LOGIC; signal slave_clk : IN STD_LOGIC; signal slave_read : IN STD_LOGIC; signal slave_reset_n : IN STD_LOGIC; signal slave_write : IN STD_LOGIC; -- outputs: signal slave_read_request : OUT STD_LOGIC; signal slave_waitrequest : OUT STD_LOGIC; signal slave_write_request : OUT STD_LOGIC ); end entity niosII_openMac_clock_1_slave_FSM; architecture europa of niosII_openMac_clock_1_slave_FSM is signal internal_slave_read_request : STD_LOGIC; signal internal_slave_write_request : STD_LOGIC; signal next_slave_read_request : STD_LOGIC; signal next_slave_state : STD_LOGIC_VECTOR (2 DOWNTO 0); signal next_slave_write_request : STD_LOGIC; signal slave_state : STD_LOGIC_VECTOR (2 DOWNTO 0); begin process (slave_clk, slave_reset_n) begin if slave_reset_n = '0' then internal_slave_read_request <= std_logic'('0'); elsif slave_clk'event and slave_clk = '1' then if true then internal_slave_read_request <= next_slave_read_request; end if; end if; end process; process (slave_clk, slave_reset_n) begin if slave_reset_n = '0' then internal_slave_write_request <= std_logic'('0'); elsif slave_clk'event and slave_clk = '1' then if true then internal_slave_write_request <= next_slave_write_request; end if; end if; end process; process (slave_clk, slave_reset_n) begin if slave_reset_n = '0' then slave_state <= std_logic_vector'("001"); elsif slave_clk'event and slave_clk = '1' then if true then slave_state <= next_slave_state; end if; end if; end process; process (internal_slave_read_request, internal_slave_write_request, master_read_done_token, master_write_done_token, slave_read, slave_state, slave_write) begin case slave_state is -- synthesis parallel_case when std_logic_vector'("001") => --read request: go from IDLE state to READ_WAIT state if std_logic'(slave_read) = '1' then next_slave_state <= std_logic_vector'("010"); slave_waitrequest <= std_logic'('1'); next_slave_read_request <= NOT(internal_slave_read_request); next_slave_write_request <= internal_slave_write_request; elsif std_logic'(slave_write) = '1' then next_slave_state <= std_logic_vector'("100"); slave_waitrequest <= std_logic'('1'); next_slave_read_request <= internal_slave_read_request; next_slave_write_request <= NOT(internal_slave_write_request); else next_slave_state <= slave_state; slave_waitrequest <= std_logic'('0'); next_slave_read_request <= internal_slave_read_request; next_slave_write_request <= internal_slave_write_request; end if; -- when std_logic_vector'("001") when std_logic_vector'("010") => --stay in READ_WAIT state until master passes read done token if std_logic'(master_read_done_token) = '1' then next_slave_state <= std_logic_vector'("001"); slave_waitrequest <= std_logic'('0'); else next_slave_state <= std_logic_vector'("010"); slave_waitrequest <= std_logic'('1'); end if; next_slave_read_request <= internal_slave_read_request; next_slave_write_request <= internal_slave_write_request; -- when std_logic_vector'("010") when std_logic_vector'("100") => --stay in WRITE_WAIT state until master passes write done token if std_logic'(master_write_done_token) = '1' then next_slave_state <= std_logic_vector'("001"); slave_waitrequest <= std_logic'('0'); else next_slave_state <= std_logic_vector'("100"); slave_waitrequest <= std_logic'('1'); end if; next_slave_read_request <= internal_slave_read_request; next_slave_write_request <= internal_slave_write_request; -- when std_logic_vector'("100") when others => next_slave_state <= std_logic_vector'("001"); slave_waitrequest <= std_logic'('0'); next_slave_read_request <= internal_slave_read_request; next_slave_write_request <= internal_slave_write_request; -- when others end case; -- slave_state end process; --vhdl renameroo for output signals slave_read_request <= internal_slave_read_request; --vhdl renameroo for output signals slave_write_request <= internal_slave_write_request; end europa; -- turn off superfluous VHDL processor warnings -- altera message_level Level1 -- altera message_off 10034 10035 10036 10037 10230 10240 10030 library altera; use altera.altera_europa_support_lib.all; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity niosII_openMac_clock_1_master_FSM is port ( -- inputs: signal master_clk : IN STD_LOGIC; signal master_reset_n : IN STD_LOGIC; signal master_waitrequest : IN STD_LOGIC; signal slave_read_request_token : IN STD_LOGIC; signal slave_write_request_token : IN STD_LOGIC; -- outputs: signal master_read : OUT STD_LOGIC; signal master_read_done : OUT STD_LOGIC; signal master_write : OUT STD_LOGIC; signal master_write_done : OUT STD_LOGIC ); end entity niosII_openMac_clock_1_master_FSM; architecture europa of niosII_openMac_clock_1_master_FSM is signal internal_master_read1 : STD_LOGIC; signal internal_master_read_done : STD_LOGIC; signal internal_master_write1 : STD_LOGIC; signal internal_master_write_done : STD_LOGIC; signal master_state : STD_LOGIC_VECTOR (2 DOWNTO 0); signal next_master_read : STD_LOGIC; signal next_master_read_done : STD_LOGIC; signal next_master_state : STD_LOGIC_VECTOR (2 DOWNTO 0); signal next_master_write : STD_LOGIC; signal next_master_write_done : STD_LOGIC; begin process (master_clk, master_reset_n) begin if master_reset_n = '0' then internal_master_read_done <= std_logic'('0'); elsif master_clk'event and master_clk = '1' then if true then internal_master_read_done <= next_master_read_done; end if; end if; end process; process (master_clk, master_reset_n) begin if master_reset_n = '0' then internal_master_write_done <= std_logic'('0'); elsif master_clk'event and master_clk = '1' then if true then internal_master_write_done <= next_master_write_done; end if; end if; end process; process (master_clk, master_reset_n) begin if master_reset_n = '0' then internal_master_read1 <= std_logic'('0'); elsif master_clk'event and master_clk = '1' then if true then internal_master_read1 <= next_master_read; end if; end if; end process; process (master_clk, master_reset_n) begin if master_reset_n = '0' then internal_master_write1 <= std_logic'('0'); elsif master_clk'event and master_clk = '1' then if true then internal_master_write1 <= next_master_write; end if; end if; end process; process (master_clk, master_reset_n) begin if master_reset_n = '0' then master_state <= std_logic_vector'("001"); elsif master_clk'event and master_clk = '1' then if true then master_state <= next_master_state; end if; end if; end process; process (internal_master_read1, internal_master_read_done, internal_master_write1, internal_master_write_done, master_state, master_waitrequest, slave_read_request_token, slave_write_request_token) begin case master_state is -- synthesis parallel_case when std_logic_vector'("001") => --if read request token from slave then goto READ_WAIT state if std_logic'(slave_read_request_token) = '1' then next_master_state <= std_logic_vector'("010"); next_master_read <= std_logic'('1'); next_master_write <= std_logic'('0'); elsif std_logic'(slave_write_request_token) = '1' then next_master_state <= std_logic_vector'("100"); next_master_read <= std_logic'('0'); next_master_write <= std_logic'('1'); else next_master_state <= master_state; next_master_read <= std_logic'('0'); next_master_write <= std_logic'('0'); end if; next_master_read_done <= internal_master_read_done; next_master_write_done <= internal_master_write_done; -- when std_logic_vector'("001") when std_logic_vector'("010") => --stay in READ_WAIT state until master wait is deasserted if std_logic'(NOT(master_waitrequest)) = '1' then next_master_state <= std_logic_vector'("001"); next_master_read_done <= NOT(internal_master_read_done); next_master_read <= std_logic'('0'); else next_master_state <= std_logic_vector'("010"); next_master_read_done <= internal_master_read_done; next_master_read <= internal_master_read1; end if; next_master_write_done <= internal_master_write_done; next_master_write <= std_logic'('0'); -- when std_logic_vector'("010") when std_logic_vector'("100") => --stay in WRITE_WAIT state until slave wait is deasserted if std_logic'(NOT(master_waitrequest)) = '1' then next_master_state <= std_logic_vector'("001"); next_master_write <= std_logic'('0'); next_master_write_done <= NOT(internal_master_write_done); else next_master_state <= std_logic_vector'("100"); next_master_write <= internal_master_write1; next_master_write_done <= internal_master_write_done; end if; next_master_read_done <= internal_master_read_done; next_master_read <= std_logic'('0'); -- when std_logic_vector'("100") when others => next_master_state <= std_logic_vector'("001"); next_master_write <= std_logic'('0'); next_master_write_done <= internal_master_write_done; next_master_read <= std_logic'('0'); next_master_read_done <= internal_master_read_done; -- when others end case; -- master_state end process; --vhdl renameroo for output signals master_read <= internal_master_read1; --vhdl renameroo for output signals master_read_done <= internal_master_read_done; --vhdl renameroo for output signals master_write <= internal_master_write1; --vhdl renameroo for output signals master_write_done <= internal_master_write_done; end europa; -- turn off superfluous VHDL processor warnings -- altera message_level Level1 -- altera message_off 10034 10035 10036 10037 10230 10240 10030 library altera; use altera.altera_europa_support_lib.all; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity niosII_openMac_clock_1_bit_pipe is port ( -- inputs: signal clk1 : IN STD_LOGIC; signal clk2 : IN STD_LOGIC; signal data_in : IN STD_LOGIC; signal reset_clk1_n : IN STD_LOGIC; signal reset_clk2_n : IN STD_LOGIC; -- outputs: signal data_out : OUT STD_LOGIC ); end entity niosII_openMac_clock_1_bit_pipe; architecture europa of niosII_openMac_clock_1_bit_pipe is signal data_in_d1 : STD_LOGIC; attribute ALTERA_ATTRIBUTE : string; attribute ALTERA_ATTRIBUTE of data_in_d1 : signal is "{-to ""*""} CUT=ON ; PRESERVE_REGISTER=ON"; attribute ALTERA_ATTRIBUTE of data_out : signal is "PRESERVE_REGISTER=ON"; begin process (clk1, reset_clk1_n) begin if reset_clk1_n = '0' then data_in_d1 <= std_logic'('0'); elsif clk1'event and clk1 = '1' then data_in_d1 <= data_in; end if; end process; process (clk2, reset_clk2_n) begin if reset_clk2_n = '0' then data_out <= std_logic'('0'); elsif clk2'event and clk2 = '1' then data_out <= data_in_d1; end if; end process; end europa; -- turn off superfluous VHDL processor warnings -- altera message_level Level1 -- altera message_off 10034 10035 10036 10037 10230 10240 10030 library altera; use altera.altera_europa_support_lib.all; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; --Clock Domain Crossing AdapterniosII_openMac_clock_1 entity niosII_openMac_clock_1 is port ( -- inputs: signal master_clk : IN STD_LOGIC; signal master_endofpacket : IN STD_LOGIC; signal master_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0); signal master_reset_n : IN STD_LOGIC; signal master_waitrequest : IN STD_LOGIC; signal slave_address : IN STD_LOGIC_VECTOR (11 DOWNTO 0); signal slave_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0); signal slave_clk : IN STD_LOGIC; signal slave_nativeaddress : IN STD_LOGIC_VECTOR (9 DOWNTO 0); signal slave_read : IN STD_LOGIC; signal slave_reset_n : IN STD_LOGIC; signal slave_write : IN STD_LOGIC; signal slave_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0); -- outputs: signal master_address : OUT STD_LOGIC_VECTOR (11 DOWNTO 0); signal master_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); signal master_nativeaddress : OUT STD_LOGIC_VECTOR (9 DOWNTO 0); signal master_read : OUT STD_LOGIC; signal master_write : OUT STD_LOGIC; signal master_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); signal slave_endofpacket : OUT STD_LOGIC; signal slave_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); signal slave_waitrequest : OUT STD_LOGIC ); end entity niosII_openMac_clock_1; architecture europa of niosII_openMac_clock_1 is component altera_std_synchronizer is GENERIC ( depth : NATURAL ); PORT ( signal dout : OUT STD_LOGIC; signal clk : IN STD_LOGIC; signal reset_n : IN STD_LOGIC; signal din : IN STD_LOGIC ); end component altera_std_synchronizer; component niosII_openMac_clock_1_edge_to_pulse is port ( -- inputs: signal clock : IN STD_LOGIC; signal data_in : IN STD_LOGIC; signal reset_n : IN STD_LOGIC; -- outputs: signal data_out : OUT STD_LOGIC ); end component niosII_openMac_clock_1_edge_to_pulse; component niosII_openMac_clock_1_slave_FSM is port ( -- inputs: signal master_read_done_token : IN STD_LOGIC; signal master_write_done_token : IN STD_LOGIC; signal slave_clk : IN STD_LOGIC; signal slave_read : IN STD_LOGIC; signal slave_reset_n : IN STD_LOGIC; signal slave_write : IN STD_LOGIC; -- outputs: signal slave_read_request : OUT STD_LOGIC; signal slave_waitrequest : OUT STD_LOGIC; signal slave_write_request : OUT STD_LOGIC ); end component niosII_openMac_clock_1_slave_FSM; component niosII_openMac_clock_1_master_FSM is port ( -- inputs: signal master_clk : IN STD_LOGIC; signal master_reset_n : IN STD_LOGIC; signal master_waitrequest : IN STD_LOGIC; signal slave_read_request_token : IN STD_LOGIC; signal slave_write_request_token : IN STD_LOGIC; -- outputs: signal master_read : OUT STD_LOGIC; signal master_read_done : OUT STD_LOGIC; signal master_write : OUT STD_LOGIC; signal master_write_done : OUT STD_LOGIC ); end component niosII_openMac_clock_1_master_FSM; component niosII_openMac_clock_1_bit_pipe is port ( -- inputs: signal clk1 : IN STD_LOGIC; signal clk2 : IN STD_LOGIC; signal data_in : IN STD_LOGIC; signal reset_clk1_n : IN STD_LOGIC; signal reset_clk2_n : IN STD_LOGIC; -- outputs: signal data_out : OUT STD_LOGIC ); end component niosII_openMac_clock_1_bit_pipe; signal internal_master_read : STD_LOGIC; signal internal_master_write : STD_LOGIC; signal internal_slave_endofpacket : STD_LOGIC; signal internal_slave_waitrequest : STD_LOGIC; signal master_read_done : STD_LOGIC; signal master_read_done_sync : STD_LOGIC; signal master_read_done_token : STD_LOGIC; signal master_write_done : STD_LOGIC; signal master_write_done_sync : STD_LOGIC; signal master_write_done_token : STD_LOGIC; signal slave_address_d1 : STD_LOGIC_VECTOR (11 DOWNTO 0); signal slave_byteenable_d1 : STD_LOGIC_VECTOR (3 DOWNTO 0); signal slave_nativeaddress_d1 : STD_LOGIC_VECTOR (9 DOWNTO 0); signal slave_read_request : STD_LOGIC; signal slave_read_request_sync : STD_LOGIC; signal slave_read_request_token : STD_LOGIC; signal slave_readdata_p1 : STD_LOGIC_VECTOR (31 DOWNTO 0); signal slave_write_request : STD_LOGIC; signal slave_write_request_sync : STD_LOGIC; signal slave_write_request_token : STD_LOGIC; signal slave_writedata_d1 : STD_LOGIC_VECTOR (31 DOWNTO 0); attribute ALTERA_ATTRIBUTE : string; attribute ALTERA_ATTRIBUTE of master_address : signal is "PRESERVE_REGISTER=ON"; attribute ALTERA_ATTRIBUTE of master_byteenable : signal is "PRESERVE_REGISTER=ON"; attribute ALTERA_ATTRIBUTE of master_nativeaddress : signal is "PRESERVE_REGISTER=ON"; attribute ALTERA_ATTRIBUTE of master_writedata : signal is "PRESERVE_REGISTER=ON"; attribute ALTERA_ATTRIBUTE of slave_address_d1 : signal is "{-to ""*""} CUT=ON ; PRESERVE_REGISTER=ON"; attribute ALTERA_ATTRIBUTE of slave_byteenable_d1 : signal is "{-to ""*""} CUT=ON ; PRESERVE_REGISTER=ON"; attribute ALTERA_ATTRIBUTE of slave_nativeaddress_d1 : signal is "{-to ""*""} CUT=ON ; PRESERVE_REGISTER=ON"; attribute ALTERA_ATTRIBUTE of slave_readdata : signal is "{-from ""*""} CUT=ON"; attribute ALTERA_ATTRIBUTE of slave_writedata_d1 : signal is "{-to ""*""} CUT=ON ; PRESERVE_REGISTER=ON"; begin --in, which is an e_avalon_slave --out, which is an e_avalon_master the_altera_std_synchronizer : altera_std_synchronizer generic map( depth => 2 ) port map( clk => slave_clk, din => master_read_done, dout => master_read_done_sync, reset_n => slave_reset_n ); the_altera_std_synchronizer1 : altera_std_synchronizer generic map( depth => 2 ) port map( clk => slave_clk, din => master_write_done, dout => master_write_done_sync, reset_n => slave_reset_n ); --read_done_edge_to_pulse, which is an e_instance read_done_edge_to_pulse : niosII_openMac_clock_1_edge_to_pulse port map( data_out => master_read_done_token, clock => slave_clk, data_in => master_read_done_sync, reset_n => slave_reset_n ); --write_done_edge_to_pulse, which is an e_instance write_done_edge_to_pulse : niosII_openMac_clock_1_edge_to_pulse port map( data_out => master_write_done_token, clock => slave_clk, data_in => master_write_done_sync, reset_n => slave_reset_n ); --slave_FSM, which is an e_instance slave_FSM : niosII_openMac_clock_1_slave_FSM port map( slave_read_request => slave_read_request, slave_waitrequest => internal_slave_waitrequest, slave_write_request => slave_write_request, master_read_done_token => master_read_done_token, master_write_done_token => master_write_done_token, slave_clk => slave_clk, slave_read => slave_read, slave_reset_n => slave_reset_n, slave_write => slave_write ); the_altera_std_synchronizer2 : altera_std_synchronizer generic map( depth => 2 ) port map( clk => master_clk, din => slave_read_request, dout => slave_read_request_sync, reset_n => master_reset_n ); the_altera_std_synchronizer3 : altera_std_synchronizer generic map( depth => 2 ) port map( clk => master_clk, din => slave_write_request, dout => slave_write_request_sync, reset_n => master_reset_n ); --read_request_edge_to_pulse, which is an e_instance read_request_edge_to_pulse : niosII_openMac_clock_1_edge_to_pulse port map( data_out => slave_read_request_token, clock => master_clk, data_in => slave_read_request_sync, reset_n => master_reset_n ); --write_request_edge_to_pulse, which is an e_instance write_request_edge_to_pulse : niosII_openMac_clock_1_edge_to_pulse port map( data_out => slave_write_request_token, clock => master_clk, data_in => slave_write_request_sync, reset_n => master_reset_n ); --master_FSM, which is an e_instance master_FSM : niosII_openMac_clock_1_master_FSM port map( master_read => internal_master_read, master_read_done => master_read_done, master_write => internal_master_write, master_write_done => master_write_done, master_clk => master_clk, master_reset_n => master_reset_n, master_waitrequest => master_waitrequest, slave_read_request_token => slave_read_request_token, slave_write_request_token => slave_write_request_token ); --endofpacket_bit_pipe, which is an e_instance endofpacket_bit_pipe : niosII_openMac_clock_1_bit_pipe port map( data_out => internal_slave_endofpacket, clk1 => slave_clk, clk2 => master_clk, data_in => master_endofpacket, reset_clk1_n => slave_reset_n, reset_clk2_n => master_reset_n ); process (master_clk, master_reset_n) begin if master_reset_n = '0' then slave_readdata_p1 <= std_logic_vector'("00000000000000000000000000000000"); elsif master_clk'event and master_clk = '1' then if std_logic'((internal_master_read AND NOT master_waitrequest)) = '1' then slave_readdata_p1 <= master_readdata; end if; end if; end process; process (slave_clk, slave_reset_n) begin if slave_reset_n = '0' then slave_readdata <= std_logic_vector'("00000000000000000000000000000000"); elsif slave_clk'event and slave_clk = '1' then slave_readdata <= slave_readdata_p1; end if; end process; process (slave_clk, slave_reset_n) begin if slave_reset_n = '0' then slave_writedata_d1 <= std_logic_vector'("00000000000000000000000000000000"); elsif slave_clk'event and slave_clk = '1' then slave_writedata_d1 <= slave_writedata; end if; end process; process (master_clk, master_reset_n) begin if master_reset_n = '0' then master_writedata <= std_logic_vector'("00000000000000000000000000000000"); elsif master_clk'event and master_clk = '1' then master_writedata <= slave_writedata_d1; end if; end process; process (slave_clk, slave_reset_n) begin if slave_reset_n = '0' then slave_address_d1 <= std_logic_vector'("000000000000"); elsif slave_clk'event and slave_clk = '1' then slave_address_d1 <= slave_address; end if; end process; process (master_clk, master_reset_n) begin if master_reset_n = '0' then master_address <= std_logic_vector'("000000000000"); elsif master_clk'event and master_clk = '1' then master_address <= slave_address_d1; end if; end process; process (slave_clk, slave_reset_n) begin if slave_reset_n = '0' then slave_nativeaddress_d1 <= std_logic_vector'("0000000000"); elsif slave_clk'event and slave_clk = '1' then slave_nativeaddress_d1 <= slave_nativeaddress; end if; end process; process (master_clk, master_reset_n) begin if master_reset_n = '0' then master_nativeaddress <= std_logic_vector'("0000000000"); elsif master_clk'event and master_clk = '1' then master_nativeaddress <= slave_nativeaddress_d1; end if; end process; process (slave_clk, slave_reset_n) begin if slave_reset_n = '0' then slave_byteenable_d1 <= std_logic_vector'("0000"); elsif slave_clk'event and slave_clk = '1' then slave_byteenable_d1 <= slave_byteenable; end if; end process; process (master_clk, master_reset_n) begin if master_reset_n = '0' then master_byteenable <= std_logic_vector'("0000"); elsif master_clk'event and master_clk = '1' then master_byteenable <= slave_byteenable_d1; end if; end process; --vhdl renameroo for output signals master_read <= internal_master_read; --vhdl renameroo for output signals master_write <= internal_master_write; --vhdl renameroo for output signals slave_endofpacket <= internal_slave_endofpacket; --vhdl renameroo for output signals slave_waitrequest <= internal_slave_waitrequest; end europa;
gpl-2.0
dc0b9c95f1781720168a7b4ac1dd7e11
0.581234
4.014755
false
false
false
false
simonspa/pixel-dtb-firmware
dtb/NRZI_decoder.vhd
2
3,167
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity NRZI_decoder is port (clk: in std_logic; reset: in std_logic; enable: in std_logic; IN_NRZI_i :in std_logic_vector(4 downto 0); LastBit_i :in std_logic; OUT_5b_o :out std_logic_vector(4 downto 0); error: out std_logic); end NRZI_decoder; architecture Behaviorial of NRZI_decoder is begin process (clk, reset) begin if (reset = '1') then OUT_5b_o <= "00000"; elsif (rising_edge(clk)) then if (enable = '1') then case LastBit_i is when '0' => if IN_NRZI_i = "10100" then OUT_5b_o <= "11110"; error <= '0'; elsif IN_NRZI_i = "01110" then OUT_5b_o <= "01001"; error <= '0'; elsif IN_NRZI_i = "11000" then OUT_5b_o <= "10100"; error <= '0'; elsif IN_NRZI_i = "11001" then OUT_5b_o <= "10101"; error <= '0'; elsif IN_NRZI_i = "01100" then OUT_5b_o <= "01010"; error <= '0'; elsif IN_NRZI_i = "01101" then OUT_5b_o <= "01011"; error <= '0'; elsif IN_NRZI_i = "01011" then OUT_5b_o <= "01110"; error <= '0'; elsif IN_NRZI_i = "01010" then OUT_5b_o <= "01111"; error <= '0'; elsif IN_NRZI_i = "11100" then OUT_5b_o <= "10010"; error <= '0'; elsif IN_NRZI_i = "11101" then OUT_5b_o <= "10011"; error <= '0'; elsif IN_NRZI_i = "11011" then OUT_5b_o <= "10110"; error <= '0'; elsif IN_NRZI_i = "11010" then OUT_5b_o <= "10111"; error <= '0'; elsif IN_NRZI_i = "10011" then OUT_5b_o <= "11010"; error <= '0'; elsif IN_NRZI_i = "10010" then OUT_5b_o <= "11011"; error <= '0'; elsif IN_NRZI_i = "10111" then OUT_5b_o <= "11100"; error <= '0'; elsif IN_NRZI_i = "10110" then OUT_5b_o <= "11101"; error <= '0'; elsif IN_NRZI_i = "11111" then OUT_5b_o <= "10110"; error <= '0'; else error <= '1'; end if; when '1' => if IN_NRZI_i = "01011" then OUT_5b_o <= "11110"; error <= '0'; elsif IN_NRZI_i = "10001" then OUT_5b_o <= "01001"; error <= '0'; elsif IN_NRZI_i = "00111" then OUT_5b_o <= "10100"; error <= '0'; elsif IN_NRZI_i = "00110" then OUT_5b_o <= "10101"; error <= '0'; elsif IN_NRZI_i = "10011" then OUT_5b_o <= "01010"; error <= '0'; elsif IN_NRZI_i = "10010" then OUT_5b_o <= "01011"; error <= '0'; elsif IN_NRZI_i = "10100" then OUT_5b_o <= "01110"; error <= '0'; elsif IN_NRZI_i = "10101" then OUT_5b_o <= "01111"; error <= '0'; elsif IN_NRZI_i = "00011" then OUT_5b_o <= "10010"; error <= '0'; elsif IN_NRZI_i = "00010" then OUT_5b_o <= "10011"; error <= '0'; elsif IN_NRZI_i = "00100" then OUT_5b_o <= "10110"; error <= '0'; elsif IN_NRZI_i = "00101" then OUT_5b_o <= "10111"; error <= '0'; elsif IN_NRZI_i = "01100" then OUT_5b_o <= "11010"; error <= '0'; elsif IN_NRZI_i = "01101" then OUT_5b_o <= "11011"; error <= '0'; elsif IN_NRZI_i = "01000" then OUT_5b_o <= "11100"; error <= '0'; elsif IN_NRZI_i = "01001" then OUT_5b_o <= "11101"; error <= '0'; elsif IN_NRZI_i = "00000" then OUT_5b_o <= "10110"; error <= '0'; else error <= '1'; end if; end case; end if; --enable end if; end process; end Behaviorial;
unlicense
7ad6ffe520f2e653405b30f62dcb163c
0.549732
2.591653
false
false
false
false
egk696/VHDL_FSM_Visualizer
VHDL FSM Visualizer/Demo Files/video_composer_fsmd.vhd
1
5,480
USE WORK.ALL; USE work.package_MicroAssemblyCode.ALL; LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.std_logic_signed.all; USE IEEE.std_logic_arith.all; ENTITY VideoComposer_FSMD IS PORT ( Clk : IN STD_LOGIC; Reset : IN STD_LOGIC; Start : IN STD_LOGIC; Ready : OUT STD_LOGIC; ROM_address : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); DataIn : IN STD_LOGIC_VECTOR(7 DOWNTO 0); RAM_address : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); RAM_WE : OUT STD_LOGIC; DataOut : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END VideoComposer_fsmd; ARCHITECTURE behaviour OF videoComposer_FSMD IS CONSTANT ROM : Program_Type := ( --| IE | Dest | Src1 | Src2 | OpAlu | OpShift | OE | ('0', R0, R0, R0, OpXor, OpPass, '0'), -- Reset_State ('1', R1, Rx, Rx, OpXor, OpPass, '0'), -- S_Read_Red ('1', R2, R1, R1, OpAnd, OpPass, '1'), -- S_WriteRed_ReadGreen ('1', R3, R2, R2, OpAnd, OpPass, '1'), -- S_WriteGreen_ReadBlue ('0', R4, R3, R3, OpAdd, OpShiftL, '1'), -- R4<=4*R3 ('0', R7, Rx, Rx, OpInc, OpPass, '1'), --Create 00000001 in R6 ('0', R5, R3, R3, OpAnd, OpRotL, '1'), --keep r3 and RoL ('0', R5, R5, R3, OpOr, OpRotL, '1'), --join r5 with r3 and RoL ('0', R5, R5, R7, OpAnd, OpPass, '1'), --mask r5 with r7 ('0', R5, R5, Rx, OpDec, OpPass, '1'), --Decrease r5 by 1 ('0', R5, R5, Rx, OpInv, OpPass, '1'), --Invert r5 so if it overflows then 0xFF or else 0x00 ('0', R3, R4, R5, OpOr, OpPass, '1'), --Saturate (r5) or keep value (r4) ('0', Rx, R3, R3, OpAnd, OpPass, '1'), -- S_WriteBlue ('0', Rx, Rx, Rx, OpAnd, OpPass, '0') --S _Idle ); CONSTANT ProcBlueLastInstr : Integer := 11; COMPONENT dataPath GENERIC ( Size : INTEGER := 8; -- # bits in word ASize : INTEGER := 3 -- # bits in address ); PORT ( InPort : IN STD_LOGIC_VECTOR(Size-1 DOWNTO 0); OutPort : OUT STD_LOGIC_VECTOR(Size-1 DOWNTO 0); Clk : IN STD_LOGIC; Instr : IN Instruction_Type ); END COMPONENT; -- Datapath signals SIGNAL InPort : STD_LOGIC_VECTOR(Size-1 DOWNTO 0); SIGNAL OutPort : STD_LOGIC_VECTOR(Size-1 DOWNTO 0); SIGNAL instr : Instruction_type := ( '0' , Rx , Rx , Rx , OpX , OpX , '0' ); TYPE State_Type IS (reset_state, S_ReadRed, S_ReadGreenWriteRed, S_ReadBlueWriteGreen, S_ProcessBlue, S_WriteBlue, S_Idle); SIGNAL current_state, next_state : State_Type; -- Instr counter for the datapath SIGNAL current_counter, next_counter : INTEGER RANGE 0 to ROM'High:= 0; SIGNAL read_address,next_read_address,write_address,next_write_address: STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL next_WE,WE:STD_LOGIC:='0'; BEGIN instr <= ROM(current_counter); -- Moore Decoding of instr... COMB: PROCESS(current_state, current_counter, read_address, write_address, InPort,OutPort,DataIn) BEGIN InPort <= DataIn; next_state <= current_state; next_counter <= current_counter; Ready <= '0'; next_read_address<=read_address; next_write_address<=write_address; next_WE<='0'; CASE current_state IS WHEN reset_state => -- ROM Instr 0 next_read_address<=(others=>'0'); next_write_address<=(others=>'0'); next_WE<='0'; next_state<=S_ReadRed; next_counter <= 1; WHEN S_ReadRed => -- ROM Instr 1 next_state<=S_ReadGreenWriteRed; next_counter <= 2; next_read_address<=read_address+1; next_WE<='1'; -- Write during next state... WHEN S_ReadGreenWriteRed => -- ROM Instr 2 next_counter <= 3; next_state <= S_ReadBlueWriteGreen; next_read_address<=read_address+1; next_write_address<=write_address+1; next_WE<='1'; WHEN S_ReadBlueWriteGreen => -- ROM Instr 3 next_WE<='0'; --if you add states for processing the blue color turn it to '0' next_counter <= 4; next_state <= S_ProcessBlue; --S_WriteBlue; next_read_address<=read_address+1; next_write_address<=write_address+1; WHEN S_ProcessBlue => --Processing blue color EGK696 ROM Instr 4-10 ASSERT false report "processing blue " & Integer'Image(current_counter); if current_counter = ProcBlueLastInstr then next_WE <= '1'; next_state <= S_WriteBlue; else next_WE <= '0'; next_state <= S_ProcessBlue; end if; next_counter <= current_counter + 1; WHEN S_WriteBlue => -- ROM Instr 10 or 11 next_WE<='0'; next_write_address<=write_address+1; next_state <= S_Idle; WHEN S_Idle => if (read_address=57600) then Ready <= '1'; else next_state<=S_ReadRed; next_counter<=1; end if; WHEN OTHERS => ASSERT false report "illegal FSM state, testbench error" severity error; END CASE; END PROCESS; P_SYNCH: PROCESS(Clk,reset) BEGIN IF (reset='0') then current_state<=reset_state; current_counter<=0; WE<='0'; ELSIF rising_edge(Clk) THEN WE<=next_WE; read_address <= next_read_address; write_address <= next_write_address; current_state <= next_state; current_counter <= next_counter; END IF; END PROCESS; U_dataPath : dataPath GENERIC MAP(Size => Size, ASize => ASize) PORT MAP( InPort => InPort, OutPort => OutPort, Clk => Clk, Instr => instr); -- Ensure an late write in the first Write state when addresses are stable RAM_WE<=WE AND not(clk); RAM_ADDRESS<=write_address; ROM_ADDRESS<=read_address; DataOut<=OutPort; END behaviour;
lgpl-3.0
7f63b14150f1c5d069310907de07e99a
0.616241
2.830579
false
false
false
false
systec-dk/openPOWERLINK_systec
Examples/ipcore/common/openmac/src/openHUB.vhd
3
7,075
------------------------------------------------------------------------------- -- OpenHUB -- -- Copyright (C) 2009 B&R -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- -- Note: RxDv, RxDat0 and RxDat1 have to be synchron to CLK -- ReceivePort return currently active Port -- ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_unsigned.ALL; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; ENTITY OpenHUB IS GENERIC ( Ports : integer := 3 ); PORT ( Rst : IN std_logic; Clk : IN std_logic; RxDv : IN std_logic_vector(Ports DOWNTO 1); RxDat0, RxDat1 : IN std_logic_vector(Ports DOWNTO 1); TxEn : OUT std_logic_vector(Ports DOWNTO 1); TxDat0, TxDat1 : OUT std_logic_vector(Ports DOWNTO 1); internPort : IN integer RANGE 1 TO Ports := 1; TransmitMask : IN std_logic_vector(Ports DOWNTO 1) := (OTHERS => '1'); ReceivePort : OUT integer RANGE 0 TO Ports ); END ENTITY OpenHUB; ARCHITECTURE struct OF OpenHUB IS SIGNAL RxDvI, RxDvL : std_logic_vector(Ports DOWNTO 0); SIGNAL RxDatI0, RxDatL0 : std_logic_vector(Ports DOWNTO 0); SIGNAL RxDatI1, RxDatL1 : std_logic_vector(Ports DOWNTO 0); SIGNAL TxEnI : std_logic_vector(Ports DOWNTO 0); SIGNAL TxDatI0 : std_logic_vector(Ports DOWNTO 0); SIGNAL TxDatI1 : std_logic_vector(Ports DOWNTO 0); SIGNAL MasterAtCollNumber : integer RANGE 0 TO Ports; SIGNAL HubActive : boolean; SIGNAL CollStatus : boolean; SIGNAL TransmitMask_L : std_logic_vector(Ports DOWNTO 1); BEGIN RxDvI(Ports DOWNTO 0) <= RxDv(Ports DOWNTO 1) & '0'; RxDatI0(Ports DOWNTO 0) <= RxDat0(Ports DOWNTO 1) & '0'; RxDatI1(Ports DOWNTO 0) <= RxDat1(Ports DOWNTO 1) & '0'; TxEn(Ports DOWNTO 1) <= TxEnI(Ports DOWNTO 1); TxDat0(Ports DOWNTO 1) <= TxDatI0(Ports DOWNTO 1); TxDat1(Ports DOWNTO 1) <= TxDatI1(Ports DOWNTO 1); do: PROCESS (Rst, Clk) VARIABLE Active : boolean; VARIABLE Master : integer RANGE 0 TO Ports; VARIABLE Master_at_Coll : integer RANGE 0 TO Ports; VARIABLE Coll : boolean; VARIABLE RxDvM : std_logic_vector(Ports DOWNTO 0); BEGIN IF Rst = '1' THEN RxDvL <= (OTHERS => '0'); RxDatL0 <= (OTHERS => '0'); RxDatL1 <= (OTHERS => '0'); TxEnI <= (OTHERS => '0'); TxDatI0 <= (OTHERS => '0'); TxDatI1 <= (OTHERS => '0'); Active := false; Master := 0; Master_at_Coll := 0; Coll := false; TransmitMask_L <= (OTHERS => '1'); ELSIF rising_edge(Clk) THEN RxDvL <= RxDvI; RxDatL0 <= RxDatI0; RxDatL1 <= RxDatI1; IF Active = false THEN IF RxDvL /= 0 THEN FOR i IN 1 TO Ports LOOP IF RxDvL(i) = '1' AND (RxDatL0(i) = '1' OR RxDatL1(i) = '1') THEN Master := i; Active := true; EXIT; END IF; END LOOP; END IF; ELSE IF RxDvL(Master) = '0' AND RxDvI(Master) = '0' THEN Master := 0; END IF; IF RxDvL = 0 AND RxDvI = 0 THEN Active := false; END IF; END IF; IF Master = 0 THEN TxEnI <= (OTHERS => '0'); TxDatI0 <= (OTHERS => '0'); TxDatI1 <= (OTHERS => '0'); -- Overtake new TransmitMask only, when there is no active frame. TransmitMask_L <= TransmitMask; ELSE FOR i IN 1 TO Ports LOOP -- output received frame to every port IF i /= Master THEN -- but not to the port where it is coming from - "eh kloar!" -- only send data to active ports (=> TransmitMask is set to '1') or the internal Port (Mac) IF TransmitMask_L(i) = '1' OR Master = internPort THEN TxEnI(i) <= '1'; TxDatI0(i) <= RxDatL0(Master); TxDatI1(i) <= RxDatL1(Master); END IF; -- If there is a frame received and another is sent => collision! IF RxDvL(i) = '1' THEN Coll := true; Master_at_Coll := Master; END IF; END IF; END LOOP; END IF; IF Coll = true THEN TxEnI(Master_at_Coll) <= '1'; TxDatI0(Master_at_Coll) <= '1'; TxDatI1(Master_at_Coll) <= '0'; RxDvM := RxDvL; RxDvM(Master_at_Coll) := '0'; IF RxDvM = 0 THEN TxEnI(Master_at_Coll) <= '0'; TxDatI0(Master_at_Coll) <= '0'; TxDatI1(Master_at_Coll) <= '0'; Coll := false; Master_at_Coll := 0; END IF; END IF; END IF; HubActive <= Active; MasterAtCollNumber <= Master_at_Coll; CollStatus <= Coll; -- Output the Master Port - identifies the port (1...n) which has received the packet. -- If Master is 0, the Hub is inactive. ReceivePort <= Master; END PROCESS do; END struct;
gpl-2.0
551108e59ee96d1f9c73a9eee64c4a96
0.544452
4.246699
false
false
false
false
scottlbaker/PDP11-SOC
src/addr.vhd
1
1,893
--======================================================================== -- addr.vhd :: PDP-11 16-bit address adder -- -- (c) Scott L. Baker, Sierra Circuit Design --======================================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use work.my_types.all; entity ADDR is port ( SX : out std_logic_vector(15 downto 0); -- result bus BX : in std_logic_vector(15 downto 0); -- operand bus DISP : in std_logic_vector( 7 downto 0); -- displacement OP : in SX_OP_TYPE -- micro op ); end ADDR; architecture BEHAVIORAL of ADDR is --================================================================= -- Types, component, and signal definitions --================================================================= -- internal busses signal AX : std_logic_vector(15 downto 0); signal DSE : std_logic_vector( 6 downto 0); begin --================================================================ -- Start of the behavioral description --================================================================ --==================== -- Opcode Decoding --==================== OPCODE_DECODING: process(OP, DSE, DISP) begin case OP is when OP_REL => -- add relative offset AX <= DSE & DISP & '0'; when OP_DEC2 => -- decrement by 2 AX <= "1111111111111110"; when others => -- increment by 2 AX <= "0000000000000010"; end case; end process; DSE <= (others => DISP(7)); SX <= AX + BX; end BEHAVIORAL;
gpl-3.0
fa2d8d06f28a0b6432eac0d2a9675aee
0.377179
5.158038
false
false
false
false
simonspa/pixel-dtb-firmware
dtb/ram_dq_INST_ma.vhd
2
7,075
-- megafunction wizard: %RAM: 1-PORT% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altsyncram -- ============================================================ -- File Name: ram_dq_INST_ma.vhd -- Megafunction Name(s): -- altsyncram -- -- Simulation Library Files(s): -- altera_mf -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version -- ************************************************************ --Copyright (C) 1991-2012 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY ram_dq_INST_ma IS PORT ( address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); clock : IN STD_LOGIC := '1'; data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); wren : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END ram_dq_INST_ma; ARCHITECTURE SYN OF ram_dq_inst_ma IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); COMPONENT altsyncram GENERIC ( clock_enable_input_a : STRING; clock_enable_output_a : STRING; intended_device_family : STRING; lpm_hint : STRING; lpm_type : STRING; numwords_a : NATURAL; operation_mode : STRING; outdata_aclr_a : STRING; outdata_reg_a : STRING; power_up_uninitialized : STRING; read_during_write_mode_port_a : STRING; widthad_a : NATURAL; width_a : NATURAL; width_byteena_a : NATURAL ); PORT ( address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); clock0 : IN STD_LOGIC ; data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); wren_a : IN STD_LOGIC ; q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT; BEGIN q <= sub_wire0(7 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( clock_enable_input_a => "BYPASS", clock_enable_output_a => "BYPASS", intended_device_family => "Cyclone III", lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=N_ma", lpm_type => "altsyncram", numwords_a => 256, operation_mode => "SINGLE_PORT", outdata_aclr_a => "NONE", outdata_reg_a => "CLOCK0", power_up_uninitialized => "FALSE", read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", widthad_a => 8, width_a => 8, width_byteena_a => 1 ) PORT MAP ( address_a => address, clock0 => clock, data_a => data, wren_a => wren, q_a => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" -- Retrieval info: PRIVATE: AclrByte NUMERIC "0" -- Retrieval info: PRIVATE: AclrData NUMERIC "0" -- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: Clken NUMERIC "0" -- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1" -- Retrieval info: PRIVATE: JTAG_ID STRING "N_ma" -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -- Retrieval info: PRIVATE: MIFfilename STRING "" -- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256" -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" -- Retrieval info: PRIVATE: RegData NUMERIC "1" -- Retrieval info: PRIVATE: RegOutput NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" -- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" -- Retrieval info: PRIVATE: WidthAddr NUMERIC "8" -- Retrieval info: PRIVATE: WidthData NUMERIC "8" -- Retrieval info: PRIVATE: rden NUMERIC "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=N_ma" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" -- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" -- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" -- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" -- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" -- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 -- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_ma.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_ma.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_ma.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_ma.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_ma_inst.vhd FALSE -- Retrieval info: LIB_FILE: altera_mf
unlicense
35239f82b094997acb5c328694f2ba1c
0.672085
3.439475
false
false
false
false
amethystek/VHDL_SPACE_INVADER
random.vhd
1
467
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity random is port(CLK: in std_logic; D_IN: in std_logic; Q_OUT:out std_logic_vector(2 downto 0)); end random; architecture behave of random is signal Q1,Q2,Q3,Q4:std_logic; begin Q_OUT<=((Q1 XOR Q3)XOR(Q2 XOR Q4)) & Q1 & Q4; process(CLK) begin if rising_edge(CLK)then Q1<=D_IN; Q2<=Q1; Q3<=Q2; Q4<=Q3; end if; end process; end behave;
bsd-2-clause
26bbfefaeb1eeaff8c54a6a29c4f9dfd
0.683084
2.370558
false
false
false
false
egk696/VHDL_FSM_Visualizer
VHDL FSM Visualizer/Demo Files/moore_4s.vhd
1
1,452
-- A Moore machine's outputs are dependent only on the current state. -- The output is written only when the state changes. (State -- transitions are synchronous.) library ieee; use ieee.std_logic_1164.all; entity moore_4s is port( clk : in std_logic; data_in : in std_logic; reset : in std_logic; data_out : out std_logic_vector(1 downto 0) ); end entity; architecture rtl of moore_4s is -- Build an enumerated type for the state machine type state_type is (s0, s1, s2, s3); -- Register to hold the current state signal state : state_type; begin -- Logic to advance to the next state process (clk, reset) begin if reset = '1' then state <= s0; elsif (rising_edge(clk)) then case state is when s0=> if data_in = '1' then state <= s1; else state <= s3; end if; when s1=> if data_in = '1' then state <= s2; else state <= s1; end if; when s2=> if data_in = '1' then state <= s3; else state <= s2; end if; when s3 => if data_in = '1' then state <= s0; else state <= s3; end if; end case; end if; end process; -- Output depends solely on the current state process (state) begin case state is when s0 => data_out <= "00"; when s1 => data_out <= "01"; when s2 => data_out <= "10"; when s3 => data_out <= "11"; end case; end process; end rtl;
lgpl-3.0
44e38a22b0615eb133246efe246991e1
0.579201
2.830409
false
false
false
false
OrganicMonkeyMotion/fpga_experiments
small_board/LABS/digital_logic/vhdl/lab1/part3/part3b_VHDL/part3b.vhd
1
2,604
--------------------------------------------------------------------------------------------------- -- DEEDS (Digital Electronics Education and Design Suite) -- VHDL Code generated on (6/7/2014, 12:04:56 AM) -- by the Digital Circuit Simulator(d-DcS) -- Ver. 1.80.100 (March 21, 2014) -- Copyright(c)2002-2014 University of Genoa, Italy -- Web Site: http://www.esng.dibe.unige.it/deeds --------------------------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.all; ENTITY part3b IS PORT( ---------------------------------------------------------------------------------> Inputs: iID0003: IN std_logic_vector( 3 downto 0 ); iID0004: IN std_logic_vector( 3 downto 0 ); iID0009: IN std_logic; ---------------------------------------------------------------------------------> Outputs: oID0016: OUT std_logic; oID0017: OUT std_logic --------------------------------------------------------------------------------- ); END part3b; ARCHITECTURE structural OF part3b IS ----------------------------------------------------------------------------------> Components: COMPONENT Multiplexer_2_1 IS PORT( I0: IN std_logic; I1: IN std_logic; S0: IN std_logic; Q: OUT std_logic ); END COMPONENT; ----------------------------------------------------------------------------------> Signals: SIGNAL S001: std_logic; SIGNAL S002: std_logic; SIGNAL S003: std_logic; SIGNAL S004: std_logic; SIGNAL S005: std_logic; SIGNAL S006: std_logic; SIGNAL S007: std_logic; ----------------------------------------------------------------------------------> Not Connected Pins: SIGNAL nc3p2: std_logic; SIGNAL nc3p4: std_logic; SIGNAL nc4p2: std_logic; SIGNAL nc4p4: std_logic; BEGIN -- structural ----------------------------------------------------------------------------------> Input: S001 <= iID0003(0); nc3p2 <= iID0003(1); S002 <= iID0003(2); nc3p4 <= iID0003(3); S003 <= iID0004(0); nc4p2 <= iID0004(1); S004 <= iID0004(2); nc4p4 <= iID0004(3); S005 <= iID0009; ----------------------------------------------------------------------------------> Output: oID0016 <= S006; oID0017 <= S007; ----------------------------------------------------------------------------------> Component Mapping: C001: Multiplexer_2_1 PORT MAP ( S001, S002, S005, S006 ); C002: Multiplexer_2_1 PORT MAP ( S003, S004, S005, S007 ); END structural;
unlicense
1167fdc3232adb4b78f92a9d492ff8e1
0.397849
4.466552
false
false
false
false
systec-dk/openPOWERLINK_systec
Examples/ipcore/common/lib/src/slow2fastSync.vhd
3
3,754
------------------------------------------------------------------------------- -- -- (c) B&R, 2011 -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; ENTITY slow2fastSync IS GENERIC ( doSync_g : BOOLEAN := TRUE ); PORT ( dataSrc : IN STD_LOGIC; dataDst : OUT STD_LOGIC; clkSrc : IN STD_LOGIC; rstSrc : IN STD_LOGIC; clkDst : IN STD_LOGIC; rstDst : IN STD_LOGIC ); END ENTITY slow2fastSync; ARCHITECTURE rtl OF slow2fastSync IS signal toggle, toggleSync, pulse, dataDst_s : std_logic; begin dataDst <= dataDst_s when doSync_g = TRUE else dataSrc; genSync : IF doSync_g = TRUE GENERATE firstEdgeDet : entity work.edgeDet port map ( din => dataSrc, rising => pulse, falling => open, any => open, clk => clkSrc, rst => rstSrc ); process(clkSrc, rstSrc) begin if rstSrc = '1' then toggle <= '0'; elsif clkSrc = '1' and clkSrc'event then if pulse = '1' then toggle <= not toggle; end if; end if; end process; sync : entity work.sync port map ( din => toggle, dout => toggleSync, clk => clkDst, rst => rstDst ); secondEdgeDet : entity work.edgeDet port map ( din => toggleSync, rising => open, falling => open, any => dataDst_s, clk => clkDst, rst => rstDst ); END GENERATE; END ARCHITECTURE rtl;
gpl-2.0
88d26e18b2884cb047b0b7f7cd750766
0.537826
4.998668
false
false
false
false
notti/dis_lu
test/tb_rotkey.vhd
1
1,617
library IEEE; use IEEE.STD_LOGIC_1164.ALL; USE ieee.math_real.ALL; use IEEE.NUMERIC_STD.ALL; library std; use std.textio.all; library work; use work.all; entity tb_rotkey is end tb_rotkey; architecture behav of tb_rotkey is signal clk : std_logic := '0'; signal rotA : std_logic := '0'; signal rotB : std_logic := '0'; signal rotPush : std_logic := '0'; signal rotRightEvent : std_logic := '0'; signal rotLeftEvent : std_logic := '0'; signal rotPushEvent : std_logic := '0'; begin process begin clk <= '1', '0' after 10 ns; wait for 20 ns; end process; process begin wait for 1400 ns; rotPush <= '1'; wait for 1400 ns; rotPush <= '0'; wait for 1400 ns; rotA <= '1'; wait for 1400 ns; rotB <= '1'; wait for 1400 ns; rotA <= '0'; wait for 1400 ns; rotB <= '0'; wait for 2000 ns; rotB <= '1'; wait for 1400 ns; rotA <= '1'; wait for 1400 ns; rotB <= '0'; wait for 1400 ns; rotA <= '0'; wait for 3000 ns; assert false report "done" severity failure; wait; end process; rotkey: entity work.rotkey generic map( CNT => 15 -- 1500000 = 30 ms at 50 MHz; hier 300ns ) port map( clk => clk, rotA => rotA, rotB => rotB, rotPush => rotPush, rotRightEvent => rotRightEvent, rotLeftEvent => rotLeftEvent, rotPushEvent => rotPushEvent ); end behav;
mit
080ed93f629610978c65ca5a1a92f96c
0.516388
3.683371
false
false
false
false
simonspa/pixel-dtb-firmware
dtb/g_or2x4.vhd
2
4,025
-- megafunction wizard: %LPM_OR% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: lpm_or -- ============================================================ -- File Name: g_or2x4.vhd -- Megafunction Name(s): -- lpm_or -- -- Simulation Library Files(s): -- lpm -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 9.1 Build 350 03/24/2010 SP 2 SJ Full Version -- ************************************************************ --Copyright (C) 1991-2010 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.lpm_components.all; ENTITY g_or2x4 IS PORT ( data0x : IN STD_LOGIC_VECTOR (3 DOWNTO 0); data1x : IN STD_LOGIC_VECTOR (3 DOWNTO 0); result : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ); END g_or2x4; ARCHITECTURE SYN OF g_or2x4 IS -- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC_VECTOR (3 DOWNTO 0); SIGNAL sub_wire2 : STD_LOGIC_2D (1 DOWNTO 0, 3 DOWNTO 0); SIGNAL sub_wire3 : STD_LOGIC_VECTOR (3 DOWNTO 0); BEGIN sub_wire3 <= data0x(3 DOWNTO 0); result <= sub_wire0(3 DOWNTO 0); sub_wire1 <= data1x(3 DOWNTO 0); sub_wire2(1, 0) <= sub_wire1(0); sub_wire2(1, 1) <= sub_wire1(1); sub_wire2(1, 2) <= sub_wire1(2); sub_wire2(1, 3) <= sub_wire1(3); sub_wire2(0, 0) <= sub_wire3(0); sub_wire2(0, 1) <= sub_wire3(1); sub_wire2(0, 2) <= sub_wire3(2); sub_wire2(0, 3) <= sub_wire3(3); lpm_or_component : lpm_or GENERIC MAP ( lpm_size => 2, lpm_type => "LPM_OR", lpm_width => 4 ) PORT MAP ( data => sub_wire2, result => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: CompactSymbol NUMERIC "0" -- Retrieval info: PRIVATE: GateFunction NUMERIC "1" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX" -- Retrieval info: PRIVATE: InputAsBus NUMERIC "0" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: WidthInput NUMERIC "4" -- Retrieval info: PRIVATE: nInput NUMERIC "2" -- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2" -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_OR" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4" -- Retrieval info: USED_PORT: data0x 0 0 4 0 INPUT NODEFVAL data0x[3..0] -- Retrieval info: USED_PORT: data1x 0 0 4 0 INPUT NODEFVAL data1x[3..0] -- Retrieval info: USED_PORT: result 0 0 4 0 OUTPUT NODEFVAL result[3..0] -- Retrieval info: CONNECT: @data 1 0 4 0 data0x 0 0 4 0 -- Retrieval info: CONNECT: @data 1 1 4 0 data1x 0 0 4 0 -- Retrieval info: CONNECT: result 0 0 4 0 @result 0 0 4 0 -- Retrieval info: LIBRARY: lpm lpm.lpm_components.all -- Retrieval info: GEN_FILE: TYPE_NORMAL g_or2x4.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL g_or2x4.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL g_or2x4.cmp FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL g_or2x4.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL g_or2x4_inst.vhd FALSE -- Retrieval info: LIB_FILE: lpm
unlicense
3a78b7e8aca3c7fa101201f36b3be344
0.63205
3.296478
false
false
false
false
egk696/VHDL_FSM_Visualizer
VHDL FSM Visualizer/Demo Files/mealy_4s.vhd
1
1,944
-- A Mealy machine has outputs that depend on both the state and -- the inputs. When the inputs change, the outputs are updated -- immediately, without waiting for a clock edge. The outputs -- can be written more than once per state or per clock cycle. library ieee; use ieee.std_logic_1164.all; entity mealy_4s is port ( clk : in std_logic; data_in : in std_logic; reset : in std_logic; data_out : out std_logic_vector(1 downto 0) ); end entity; architecture rtl of mealy_4s is -- Build an enumerated type for the state machine type state_type is (s0, s1, s2, s3); -- Register to hold the current state signal state : state_type; begin process (clk, reset) begin if reset = '1' then state <= s0; elsif (rising_edge(clk)) then -- Determine the next state synchronously, based on -- the current state and the input case state is when s0=> if data_in = '1' then state <= s1; else state <= s0; end if; when s1=> if data_in = '1' then state <= s2; else state <= s1; end if; when s2=> if data_in = '1' then state <= s3; else state <= s2; end if; when s3=> if data_in = '1' then state <= s3; else state <= s1; end if; end case; end if; end process; -- Determine the output based only on the current state -- and the input (do not wait for a clock edge). process (state, data_in) begin case state is when s0=> if data_in = '1' then data_out <= "00"; else data_out <= "01"; end if; when s1=> if data_in = '1' then data_out <= "01"; else data_out <= "11"; end if; when s2=> if data_in = '1' then data_out <= "10"; else data_out <= "10"; end if; when s3=> if data_in = '1' then data_out <= "11"; else data_out <= "10"; end if; end case; end process; end rtl;
lgpl-3.0
7bda93409180bc6be26004a30c7f4add
0.575617
2.863034
false
false
false
false
Alix82/mip32vhdl
decoder.vhd
1
4,769
library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use ieee.std_logic_unsigned.all; library work; use work.mips_constants.all; Entity decoder is port(clk : in std_logic; instruction : in std_logic_vector(31 downto 0); pcD : in std_logic_vector(31 downto 0); discard : in std_logic; decoded : out std_logic_vector(11 downto 0); opcode : out std_logic_vector(5 downto 0); func : out std_logic_vector(5 downto 0); shamt : out std_logic_vector(4 downto 0); pcF : out std_logic_vector(31 downto 0); Reg1 : out std_logic_vector(4 downto 0); Reg2 : out std_logic_vector(4 downto 0); Reg3 : out std_logic_vector(4 downto 0); Fetch : out std_logic ); End decoder; Architecture rtl of decoder is signal n_decoded : integer := 0; begin process (clk) Variable decoded_o : std_logic_vector (7 downto 0); Variable op : std_logic_vector(5 downto 0); Variable lfunc : std_logic_vector(5 downto 0); Variable control_o : std_logic_vector(11 downto 0); Variable read_reg: std_logic; Variable instructionlocal : std_logic_vector(31 downto 0); begin if rising_edge(clk) then instructionlocal := X"00000000"; Fetch <= not discard; instructionlocal := Instruction; lfunc := instructionlocal(5 downto 0); op := instructionlocal(31 downto 26); control_o := "000000000000"; read_reg := '0'; -- linkbit := '0'; case op is when "000010" => control_o := "010000000000"; -- J label when "000011" => control_o := "010000000010"; read_reg := '1'; -- JAL label when "000000" => case lfunc is when "001000" => control_o := "010000000001"; -- JR when "010000" => control_o := "000001001000"; -- MFHI when "010010" => control_o := "000001001000"; -- MFLO when "100100" => control_o := "100001001000"; read_reg:='1'; -- add/addu, and/andu when "100000" => control_o := "100001001000"; read_reg:='1'; -- add/addu, and/andu when "100001" => control_o := "100001001000"; read_reg:='1'; -- add/addu, and/andu when others => control_o := "000000000000"; end case; when "001000" => control_o := "100001011000"; read_reg:='1'; -- addi when "001001" => control_o := "000001011000"; read_reg:='1'; -- addiu when "101011" => control_o := "000001110000"; read_reg:='1'; -- SW when "100011" => control_o := "000111011000"; read_reg:='1'; -- LW when "101000" => control_o := "000001110000"; read_reg:='1'; -- SB when "100000" => control_o := "000111011000"; read_reg:='1'; -- LB when "001111" => control_o := "000001011000"; read_reg:='1'; -- LUI when "001110" => control_o := "000001011000"; read_reg:='1'; -- XORI when "001101" => control_o := "000001011000"; read_reg:='1'; -- ORI when "000101" => control_o := "001001000000"; read_reg:='1'; -- BNE when "000100" => control_o := "001001000000"; read_reg:='1'; -- BEQ when "000001" => if instructionlocal(20) = '1' then control_o := "001001000110"; read_reg:='1'; -- BGEZAL/BLTZAL else control_o := "001001000100"; read_reg:='1'; -- BGEZ/BLTZ end if; when "000111" => control_o := "001001000100"; read_reg:='1';-- BGTZ when "000110" => control_o := "001001000100"; read_reg:='1';-- BGTZ when others => control_o := "000000000000"; --error := '1'; end case; --prevregwrite <= control_o(3); decoded <= control_o; n_decoded <= n_decoded + 1; opcode <= op; func <= lfunc; shamt <= instructionlocal(10 downto 6); reg1 <= instructionlocal(25 downto 21); reg2 <= instructionlocal(20 downto 16); reg3 <= instructionlocal(15 downto 11); pcF <= pcD; end if; end process; end;
bsd-2-clause
a36b788cc3a1bc6c5c455be50bd90360
0.475571
4.319746
false
false
false
false
simonspa/pixel-dtb-firmware
dtb/ram_dq_INST_mb.vhd
2
7,075
-- megafunction wizard: %RAM: 1-PORT% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altsyncram -- ============================================================ -- File Name: ram_dq_INST_mb.vhd -- Megafunction Name(s): -- altsyncram -- -- Simulation Library Files(s): -- altera_mf -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version -- ************************************************************ --Copyright (C) 1991-2012 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY ram_dq_INST_mb IS PORT ( address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); clock : IN STD_LOGIC := '1'; data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); wren : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END ram_dq_INST_mb; ARCHITECTURE SYN OF ram_dq_inst_mb IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); COMPONENT altsyncram GENERIC ( clock_enable_input_a : STRING; clock_enable_output_a : STRING; intended_device_family : STRING; lpm_hint : STRING; lpm_type : STRING; numwords_a : NATURAL; operation_mode : STRING; outdata_aclr_a : STRING; outdata_reg_a : STRING; power_up_uninitialized : STRING; read_during_write_mode_port_a : STRING; widthad_a : NATURAL; width_a : NATURAL; width_byteena_a : NATURAL ); PORT ( address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); clock0 : IN STD_LOGIC ; data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); wren_a : IN STD_LOGIC ; q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT; BEGIN q <= sub_wire0(7 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( clock_enable_input_a => "BYPASS", clock_enable_output_a => "BYPASS", intended_device_family => "Cyclone III", lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=N_mb", lpm_type => "altsyncram", numwords_a => 256, operation_mode => "SINGLE_PORT", outdata_aclr_a => "NONE", outdata_reg_a => "CLOCK0", power_up_uninitialized => "FALSE", read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", widthad_a => 8, width_a => 8, width_byteena_a => 1 ) PORT MAP ( address_a => address, clock0 => clock, data_a => data, wren_a => wren, q_a => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" -- Retrieval info: PRIVATE: AclrByte NUMERIC "0" -- Retrieval info: PRIVATE: AclrData NUMERIC "0" -- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: Clken NUMERIC "0" -- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1" -- Retrieval info: PRIVATE: JTAG_ID STRING "N_mb" -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -- Retrieval info: PRIVATE: MIFfilename STRING "" -- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256" -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" -- Retrieval info: PRIVATE: RegData NUMERIC "1" -- Retrieval info: PRIVATE: RegOutput NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" -- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" -- Retrieval info: PRIVATE: WidthAddr NUMERIC "8" -- Retrieval info: PRIVATE: WidthData NUMERIC "8" -- Retrieval info: PRIVATE: rden NUMERIC "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=N_mb" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" -- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" -- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" -- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" -- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" -- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 -- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_mb.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_mb.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_mb.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_mb.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_mb_inst.vhd FALSE -- Retrieval info: LIB_FILE: altera_mf
unlicense
433db85252e89b9a00364f4c42f867c9
0.672085
3.439475
false
false
false
false
OrganicMonkeyMotion/fpga_experiments
small_board/LABS/digital_logic/vhdl/lab2/part1/part1.vhd
1
2,022
LIBRARY ieee; USE ieee.std_logic_1164.all; -- simple module that connects the buttons on our Master 21EDA board. -- based on labs from Altera -- ftp://ftp.altera.com/up/pub/Altera_Material/11.1/Laboratory_Exercises/Digital_Logic/DE2/vhdl/lab2_VHDL.pdf ENTITY part1 IS PORT (SW : IN STD_LOGIC_VECTOR (3 DOWNTO 0); -- (3)=A, (2)=B, (1)=C, (0)=D LEDSEG : OUT STD_LOGIC_VECTOR (6 DOWNTO 0); ENABLE : OUT STD_LOGIC); -- segments of our displays END part1; ARCHITECTURE Behavior OF part1 IS BEGIN ENABLE <= '0'; -- SEG A : F0 = A B C D' + B' C D + A' C' + A' B' ; LEDSEG(0) <= (SW(3) AND SW(2) AND SW(1) AND NOT SW(0)) OR (NOT SW(2) AND SW(1) AND SW(0)) OR (NOT SW(3) AND NOT SW(1)) OR (NOT SW(3) AND NOT SW(2)); -- SEG B : F1 = B' C D' + A' C' + B' C' D + A' B' ; LEDSEG(1) <= (NOT SW(2) AND SW(1) AND NOT SW(0)) OR (NOT SW(3) AND NOT SW(1)) OR (NOT SW(2) AND NOT SW(1) AND SW (0)) OR (NOT SW(3) AND NOT SW(2)); -- SEG C : F2 = B C' D + A' B' + A' C' ; LEDSEG(2) <= (SW(2) AND NOT SW(1) AND SW(0)) OR (NOT SW(3) AND NOT SW(2)) OR (NOT SW(3) AND NOT SW(1)); -- SEG D : F3 = A' D' + B C D' + B' C D + B' C' D' + A' C' ; LEDSEG(3) <= (NOT SW(3) AND NOT SW(0)) OR (SW(2) AND SW(1) AND NOT SW(0)) OR (NOT SW(2) AND SW(1) AND SW(0)) OR (NOT SW(2) AND NOT SW(1) AND NOT SW(0)) OR (NOT SW(3) AND NOT SW(1)); -- SEG E : F4 = A' C' + B' C + D'; LEDSEG(4) <= (NOT SW(3) AND NOT SW(1)) OR (NOT SW(2) AND SW(1)) OR (NOT SW(0)); -- SEG F : F5 = A B D' + A' B' + B C' + C' D'; LEDSEG(5) <= (SW(3) AND SW(2) AND NOT SW(0)) OR (NOT SW(3) AND NOT SW(2)) OR (SW(2) AND NOT SW(1)) OR (NOT SW(1) AND NOT SW(0)); -- SED G : A B C + B' C' D' + A' C' + A' B' ; LEDSEG(6) <= (SW(3) AND SW(2) AND SW(1)) OR (NOT SW(2) AND NOT SW(1) AND NOT SW(0)) OR (NOT SW(3) AND NOT SW(1)) OR (NOT SW(3) AND NOT SW(2)); END Behavior;
unlicense
acee464a77d2941754780e212755d336
0.500989
2.412888
false
false
false
false
OrganicMonkeyMotion/fpga_experiments
small_board/LABS/digital_logic/vhdl/lab2/part5/lpm_constant1.vhd
2
3,515
-- megafunction wizard: %LPM_CONSTANT% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: LPM_CONSTANT -- ============================================================ -- File Name: lpm_constant1.vhd -- Megafunction Name(s): -- LPM_CONSTANT -- -- Simulation Library Files(s): -- lpm -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition -- ************************************************************ --Copyright (C) 1991-2011 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.all; ENTITY lpm_constant1 IS PORT ( result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) ); END lpm_constant1; ARCHITECTURE SYN OF lpm_constant1 IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0); COMPONENT lpm_constant GENERIC ( lpm_cvalue : NATURAL; lpm_hint : STRING; lpm_type : STRING; lpm_width : NATURAL ); PORT ( result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) ); END COMPONENT; BEGIN result <= sub_wire0(0 DOWNTO 0); LPM_CONSTANT_component : LPM_CONSTANT GENERIC MAP ( lpm_cvalue => 0, lpm_hint => "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=i2", lpm_type => "LPM_CONSTANT", lpm_width => 1 ) PORT MAP ( result => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1" -- Retrieval info: PRIVATE: JTAG_ID STRING "i2" -- Retrieval info: PRIVATE: Radix NUMERIC "2" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: Value NUMERIC "0" -- Retrieval info: PRIVATE: nBit NUMERIC "1" -- Retrieval info: PRIVATE: new_diagram STRING "1" -- Retrieval info: LIBRARY: lpm lpm.lpm_components.all -- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0" -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=i2" -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1" -- Retrieval info: USED_PORT: result 0 0 1 0 OUTPUT NODEFVAL "result[0..0]" -- Retrieval info: CONNECT: result 0 0 1 0 @result 0 0 1 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1_inst.vhd FALSE -- Retrieval info: LIB_FILE: lpm
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