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mike7c2/befunge_processor | div_gen_v3_0.vhd | 1 | 147,109 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: O.40d
-- \ \ Application: netgen
-- / / Filename: div_gen_v3_0.vhd
-- /___/ /\ Timestamp: Mon Dec 15 22:32:14 2014
-- \ \ / \
-- \___\/\___\
--
-- Command : -intstyle ise -w -sim -ofmt vhdl ./tmp/_cg/div_gen_v3_0.ngc ./tmp/_cg/div_gen_v3_0.vhd
-- Device : 3s500evq100-5
-- Input file : ./tmp/_cg/div_gen_v3_0.ngc
-- Output file : ./tmp/_cg/div_gen_v3_0.vhd
-- # of Entities : 1
-- Design Name : div_gen_v3_0
-- Xilinx : /opt/Xilinx/13.1/ISE_DS/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity div_gen_v3_0 is
port (
rfd : out STD_LOGIC;
clk : in STD_LOGIC := 'X';
dividend : in STD_LOGIC_VECTOR ( 7 downto 0 );
quotient : out STD_LOGIC_VECTOR ( 7 downto 0 );
divisor : in STD_LOGIC_VECTOR ( 7 downto 0 );
fractional : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end div_gen_v3_0;
architecture STRUCTURE of div_gen_v3_0 is
signal NlwRenamedSig_OI_rfd : STD_LOGIC;
signal blk00000003_sig00000272 : STD_LOGIC;
signal blk00000003_sig00000271 : STD_LOGIC;
signal blk00000003_sig00000270 : STD_LOGIC;
signal blk00000003_sig0000026f : STD_LOGIC;
signal blk00000003_sig0000026e : STD_LOGIC;
signal blk00000003_sig0000026d : STD_LOGIC;
signal blk00000003_sig0000026c : STD_LOGIC;
signal blk00000003_sig0000026b : STD_LOGIC;
signal blk00000003_sig0000026a : STD_LOGIC;
signal blk00000003_sig00000269 : STD_LOGIC;
signal blk00000003_sig00000268 : STD_LOGIC;
signal blk00000003_sig00000267 : STD_LOGIC;
signal blk00000003_sig00000266 : STD_LOGIC;
signal blk00000003_sig00000265 : STD_LOGIC;
signal blk00000003_sig00000264 : STD_LOGIC;
signal blk00000003_sig00000263 : STD_LOGIC;
signal blk00000003_sig00000262 : STD_LOGIC;
signal blk00000003_sig00000261 : STD_LOGIC;
signal blk00000003_sig00000260 : STD_LOGIC;
signal blk00000003_sig0000025f : STD_LOGIC;
signal blk00000003_sig0000025e : STD_LOGIC;
signal blk00000003_sig0000025d : STD_LOGIC;
signal blk00000003_sig0000025c : STD_LOGIC;
signal blk00000003_sig0000025b : STD_LOGIC;
signal blk00000003_sig0000025a : STD_LOGIC;
signal blk00000003_sig00000259 : STD_LOGIC;
signal blk00000003_sig00000258 : STD_LOGIC;
signal blk00000003_sig00000257 : STD_LOGIC;
signal blk00000003_sig00000256 : STD_LOGIC;
signal blk00000003_sig00000255 : STD_LOGIC;
signal blk00000003_sig00000254 : STD_LOGIC;
signal blk00000003_sig00000253 : STD_LOGIC;
signal blk00000003_sig00000252 : STD_LOGIC;
signal blk00000003_sig00000251 : STD_LOGIC;
signal blk00000003_sig00000250 : STD_LOGIC;
signal blk00000003_sig0000024f : STD_LOGIC;
signal blk00000003_sig0000024e : STD_LOGIC;
signal blk00000003_sig0000024d : STD_LOGIC;
signal blk00000003_sig0000024c : STD_LOGIC;
signal blk00000003_sig0000024b : STD_LOGIC;
signal blk00000003_sig0000024a : STD_LOGIC;
signal blk00000003_sig00000249 : STD_LOGIC;
signal blk00000003_sig00000248 : STD_LOGIC;
signal blk00000003_sig00000247 : STD_LOGIC;
signal blk00000003_sig00000246 : STD_LOGIC;
signal blk00000003_sig00000245 : STD_LOGIC;
signal blk00000003_sig00000244 : STD_LOGIC;
signal blk00000003_sig00000243 : STD_LOGIC;
signal blk00000003_sig00000242 : STD_LOGIC;
signal blk00000003_sig00000241 : STD_LOGIC;
signal blk00000003_sig00000240 : STD_LOGIC;
signal blk00000003_sig0000023f : STD_LOGIC;
signal blk00000003_sig0000023e : STD_LOGIC;
signal blk00000003_sig0000023d : STD_LOGIC;
signal blk00000003_sig0000023c : STD_LOGIC;
signal blk00000003_sig0000023b : STD_LOGIC;
signal blk00000003_sig0000023a : STD_LOGIC;
signal blk00000003_sig00000239 : STD_LOGIC;
signal blk00000003_sig00000238 : STD_LOGIC;
signal blk00000003_sig00000237 : STD_LOGIC;
signal blk00000003_sig00000236 : STD_LOGIC;
signal blk00000003_sig00000235 : STD_LOGIC;
signal blk00000003_sig00000234 : STD_LOGIC;
signal blk00000003_sig00000233 : STD_LOGIC;
signal blk00000003_sig00000232 : STD_LOGIC;
signal blk00000003_sig00000231 : STD_LOGIC;
signal blk00000003_sig00000230 : STD_LOGIC;
signal blk00000003_sig0000022f : STD_LOGIC;
signal blk00000003_sig0000022e : STD_LOGIC;
signal blk00000003_sig0000022d : STD_LOGIC;
signal blk00000003_sig0000022c : STD_LOGIC;
signal blk00000003_sig0000022b : STD_LOGIC;
signal blk00000003_sig0000022a : STD_LOGIC;
signal blk00000003_sig00000229 : STD_LOGIC;
signal blk00000003_sig00000228 : STD_LOGIC;
signal blk00000003_sig00000227 : STD_LOGIC;
signal blk00000003_sig00000226 : STD_LOGIC;
signal blk00000003_sig00000225 : STD_LOGIC;
signal blk00000003_sig00000224 : STD_LOGIC;
signal blk00000003_sig00000223 : STD_LOGIC;
signal blk00000003_sig00000222 : STD_LOGIC;
signal blk00000003_sig00000221 : STD_LOGIC;
signal blk00000003_sig00000220 : STD_LOGIC;
signal blk00000003_sig0000021f : STD_LOGIC;
signal blk00000003_sig0000021e : STD_LOGIC;
signal blk00000003_sig0000021d : STD_LOGIC;
signal blk00000003_sig0000021c : STD_LOGIC;
signal blk00000003_sig0000021b : STD_LOGIC;
signal blk00000003_sig0000021a : STD_LOGIC;
signal blk00000003_sig00000219 : STD_LOGIC;
signal blk00000003_sig00000218 : STD_LOGIC;
signal blk00000003_sig00000217 : STD_LOGIC;
signal blk00000003_sig00000216 : STD_LOGIC;
signal blk00000003_sig00000215 : STD_LOGIC;
signal blk00000003_sig00000214 : STD_LOGIC;
signal blk00000003_sig00000213 : STD_LOGIC;
signal blk00000003_sig00000212 : STD_LOGIC;
signal blk00000003_sig00000211 : STD_LOGIC;
signal blk00000003_sig00000210 : STD_LOGIC;
signal blk00000003_sig0000020f : STD_LOGIC;
signal blk00000003_sig0000020e : STD_LOGIC;
signal blk00000003_sig0000020d : STD_LOGIC;
signal blk00000003_sig0000020c : STD_LOGIC;
signal blk00000003_sig0000020b : STD_LOGIC;
signal blk00000003_sig0000020a : STD_LOGIC;
signal blk00000003_sig00000209 : STD_LOGIC;
signal blk00000003_sig00000208 : STD_LOGIC;
signal blk00000003_sig00000207 : STD_LOGIC;
signal blk00000003_sig00000206 : STD_LOGIC;
signal blk00000003_sig00000205 : STD_LOGIC;
signal blk00000003_sig00000204 : STD_LOGIC;
signal blk00000003_sig00000203 : STD_LOGIC;
signal blk00000003_sig00000202 : STD_LOGIC;
signal blk00000003_sig00000201 : STD_LOGIC;
signal blk00000003_sig00000200 : STD_LOGIC;
signal blk00000003_sig000001ff : STD_LOGIC;
signal blk00000003_sig000001fe : STD_LOGIC;
signal blk00000003_sig000001fd : STD_LOGIC;
signal blk00000003_sig000001fc : STD_LOGIC;
signal blk00000003_sig000001fb : STD_LOGIC;
signal blk00000003_sig000001fa : STD_LOGIC;
signal blk00000003_sig000001f9 : STD_LOGIC;
signal blk00000003_sig000001f8 : STD_LOGIC;
signal blk00000003_sig000001f7 : STD_LOGIC;
signal blk00000003_sig000001f6 : STD_LOGIC;
signal blk00000003_sig000001f5 : STD_LOGIC;
signal blk00000003_sig000001f4 : STD_LOGIC;
signal blk00000003_sig000001f3 : STD_LOGIC;
signal blk00000003_sig000001f2 : STD_LOGIC;
signal blk00000003_sig000001f1 : STD_LOGIC;
signal blk00000003_sig000001f0 : STD_LOGIC;
signal blk00000003_sig000001ef : STD_LOGIC;
signal blk00000003_sig000001ee : STD_LOGIC;
signal blk00000003_sig000001ed : STD_LOGIC;
signal blk00000003_sig000001ec : STD_LOGIC;
signal blk00000003_sig000001eb : STD_LOGIC;
signal blk00000003_sig000001ea : STD_LOGIC;
signal blk00000003_sig000001e9 : STD_LOGIC;
signal blk00000003_sig000001e8 : STD_LOGIC;
signal blk00000003_sig000001e7 : STD_LOGIC;
signal blk00000003_sig000001e6 : STD_LOGIC;
signal blk00000003_sig000001e5 : STD_LOGIC;
signal blk00000003_sig000001e4 : STD_LOGIC;
signal blk00000003_sig000001e3 : STD_LOGIC;
signal blk00000003_sig000001e2 : STD_LOGIC;
signal blk00000003_sig000001e1 : STD_LOGIC;
signal blk00000003_sig000001e0 : STD_LOGIC;
signal blk00000003_sig000001df : STD_LOGIC;
signal blk00000003_sig000001de : STD_LOGIC;
signal blk00000003_sig000001dd : STD_LOGIC;
signal blk00000003_sig000001dc : STD_LOGIC;
signal blk00000003_sig000001db : STD_LOGIC;
signal blk00000003_sig000001da : STD_LOGIC;
signal blk00000003_sig000001d9 : STD_LOGIC;
signal blk00000003_sig000001d8 : STD_LOGIC;
signal blk00000003_sig000001d7 : STD_LOGIC;
signal blk00000003_sig000001d6 : STD_LOGIC;
signal blk00000003_sig000001d5 : STD_LOGIC;
signal blk00000003_sig000001d4 : STD_LOGIC;
signal blk00000003_sig000001d3 : STD_LOGIC;
signal blk00000003_sig000001d2 : STD_LOGIC;
signal blk00000003_sig000001d1 : STD_LOGIC;
signal blk00000003_sig000001d0 : STD_LOGIC;
signal blk00000003_sig000001cf : STD_LOGIC;
signal blk00000003_sig000001ce : STD_LOGIC;
signal blk00000003_sig000001cd : STD_LOGIC;
signal blk00000003_sig000001cc : STD_LOGIC;
signal blk00000003_sig000001cb : STD_LOGIC;
signal blk00000003_sig000001ca : STD_LOGIC;
signal blk00000003_sig000001c9 : STD_LOGIC;
signal blk00000003_sig000001c8 : STD_LOGIC;
signal blk00000003_sig000001c7 : STD_LOGIC;
signal blk00000003_sig000001c6 : STD_LOGIC;
signal blk00000003_sig000001c5 : STD_LOGIC;
signal blk00000003_sig000001c4 : STD_LOGIC;
signal blk00000003_sig000001c3 : STD_LOGIC;
signal blk00000003_sig000001c2 : STD_LOGIC;
signal blk00000003_sig000001c1 : STD_LOGIC;
signal blk00000003_sig000001c0 : STD_LOGIC;
signal blk00000003_sig000001bf : STD_LOGIC;
signal blk00000003_sig000001be : STD_LOGIC;
signal blk00000003_sig000001bd : STD_LOGIC;
signal blk00000003_sig000001bc : STD_LOGIC;
signal blk00000003_sig000001bb : STD_LOGIC;
signal blk00000003_sig000001ba : STD_LOGIC;
signal blk00000003_sig000001b9 : STD_LOGIC;
signal blk00000003_sig000001b8 : STD_LOGIC;
signal blk00000003_sig000001b7 : STD_LOGIC;
signal blk00000003_sig000001b6 : STD_LOGIC;
signal blk00000003_sig000001b5 : STD_LOGIC;
signal blk00000003_sig000001b4 : STD_LOGIC;
signal blk00000003_sig000001b3 : STD_LOGIC;
signal blk00000003_sig000001b2 : STD_LOGIC;
signal blk00000003_sig000001b1 : STD_LOGIC;
signal blk00000003_sig000001b0 : STD_LOGIC;
signal blk00000003_sig000001af : STD_LOGIC;
signal blk00000003_sig000001ae : STD_LOGIC;
signal blk00000003_sig000001ad : STD_LOGIC;
signal blk00000003_sig000001ac : STD_LOGIC;
signal blk00000003_sig000001ab : STD_LOGIC;
signal blk00000003_sig000001aa : STD_LOGIC;
signal blk00000003_sig000001a9 : STD_LOGIC;
signal blk00000003_sig000001a8 : STD_LOGIC;
signal blk00000003_sig000001a7 : STD_LOGIC;
signal blk00000003_sig000001a6 : STD_LOGIC;
signal blk00000003_sig000001a5 : STD_LOGIC;
signal blk00000003_sig000001a4 : STD_LOGIC;
signal blk00000003_sig000001a3 : STD_LOGIC;
signal blk00000003_sig000001a2 : STD_LOGIC;
signal blk00000003_sig000001a1 : STD_LOGIC;
signal blk00000003_sig000001a0 : STD_LOGIC;
signal blk00000003_sig0000019f : STD_LOGIC;
signal blk00000003_sig0000019e : STD_LOGIC;
signal blk00000003_sig0000019d : STD_LOGIC;
signal blk00000003_sig0000019c : STD_LOGIC;
signal blk00000003_sig0000019b : STD_LOGIC;
signal blk00000003_sig0000019a : STD_LOGIC;
signal blk00000003_sig00000199 : STD_LOGIC;
signal blk00000003_sig00000198 : STD_LOGIC;
signal blk00000003_sig00000197 : STD_LOGIC;
signal blk00000003_sig00000196 : STD_LOGIC;
signal blk00000003_sig00000195 : STD_LOGIC;
signal blk00000003_sig00000194 : STD_LOGIC;
signal blk00000003_sig00000193 : STD_LOGIC;
signal blk00000003_sig00000192 : STD_LOGIC;
signal blk00000003_sig00000191 : STD_LOGIC;
signal blk00000003_sig00000190 : STD_LOGIC;
signal blk00000003_sig0000018f : STD_LOGIC;
signal blk00000003_sig0000018e : STD_LOGIC;
signal blk00000003_sig0000018d : STD_LOGIC;
signal blk00000003_sig0000018c : STD_LOGIC;
signal blk00000003_sig0000018b : STD_LOGIC;
signal blk00000003_sig0000018a : STD_LOGIC;
signal blk00000003_sig00000189 : STD_LOGIC;
signal blk00000003_sig00000188 : STD_LOGIC;
signal blk00000003_sig00000187 : STD_LOGIC;
signal blk00000003_sig00000186 : STD_LOGIC;
signal blk00000003_sig00000185 : STD_LOGIC;
signal blk00000003_sig00000184 : STD_LOGIC;
signal blk00000003_sig00000183 : STD_LOGIC;
signal blk00000003_sig00000182 : STD_LOGIC;
signal blk00000003_sig00000181 : STD_LOGIC;
signal blk00000003_sig00000180 : STD_LOGIC;
signal blk00000003_sig0000017f : STD_LOGIC;
signal blk00000003_sig0000017e : STD_LOGIC;
signal blk00000003_sig0000017d : STD_LOGIC;
signal blk00000003_sig0000017c : STD_LOGIC;
signal blk00000003_sig0000017b : STD_LOGIC;
signal blk00000003_sig0000017a : STD_LOGIC;
signal blk00000003_sig00000179 : STD_LOGIC;
signal blk00000003_sig00000178 : STD_LOGIC;
signal blk00000003_sig00000177 : STD_LOGIC;
signal blk00000003_sig00000176 : STD_LOGIC;
signal blk00000003_sig00000175 : STD_LOGIC;
signal blk00000003_sig00000174 : STD_LOGIC;
signal blk00000003_sig00000173 : STD_LOGIC;
signal blk00000003_sig00000172 : STD_LOGIC;
signal blk00000003_sig00000171 : STD_LOGIC;
signal blk00000003_sig00000170 : STD_LOGIC;
signal blk00000003_sig0000016f : STD_LOGIC;
signal blk00000003_sig0000016e : STD_LOGIC;
signal blk00000003_sig0000016d : STD_LOGIC;
signal blk00000003_sig0000016c : STD_LOGIC;
signal blk00000003_sig0000016b : STD_LOGIC;
signal blk00000003_sig0000016a : STD_LOGIC;
signal blk00000003_sig00000169 : STD_LOGIC;
signal blk00000003_sig00000168 : STD_LOGIC;
signal blk00000003_sig00000167 : STD_LOGIC;
signal blk00000003_sig00000166 : STD_LOGIC;
signal blk00000003_sig00000165 : STD_LOGIC;
signal blk00000003_sig00000164 : STD_LOGIC;
signal blk00000003_sig00000163 : STD_LOGIC;
signal blk00000003_sig00000162 : STD_LOGIC;
signal blk00000003_sig00000161 : STD_LOGIC;
signal blk00000003_sig00000160 : STD_LOGIC;
signal blk00000003_sig0000015f : STD_LOGIC;
signal blk00000003_sig0000015e : STD_LOGIC;
signal blk00000003_sig0000015d : STD_LOGIC;
signal blk00000003_sig0000015c : STD_LOGIC;
signal blk00000003_sig0000015b : STD_LOGIC;
signal blk00000003_sig0000015a : STD_LOGIC;
signal blk00000003_sig00000159 : STD_LOGIC;
signal blk00000003_sig00000158 : STD_LOGIC;
signal blk00000003_sig00000157 : STD_LOGIC;
signal blk00000003_sig00000156 : STD_LOGIC;
signal blk00000003_sig00000155 : STD_LOGIC;
signal blk00000003_sig00000154 : STD_LOGIC;
signal blk00000003_sig00000153 : STD_LOGIC;
signal blk00000003_sig00000152 : STD_LOGIC;
signal blk00000003_sig00000151 : STD_LOGIC;
signal blk00000003_sig00000150 : STD_LOGIC;
signal blk00000003_sig0000014f : STD_LOGIC;
signal blk00000003_sig0000014e : STD_LOGIC;
signal blk00000003_sig0000014d : STD_LOGIC;
signal blk00000003_sig0000014c : STD_LOGIC;
signal blk00000003_sig0000014b : STD_LOGIC;
signal blk00000003_sig0000014a : STD_LOGIC;
signal blk00000003_sig00000149 : STD_LOGIC;
signal blk00000003_sig00000148 : STD_LOGIC;
signal blk00000003_sig00000147 : STD_LOGIC;
signal blk00000003_sig00000146 : STD_LOGIC;
signal blk00000003_sig00000145 : STD_LOGIC;
signal blk00000003_sig00000144 : STD_LOGIC;
signal blk00000003_sig00000143 : STD_LOGIC;
signal blk00000003_sig00000142 : STD_LOGIC;
signal blk00000003_sig00000141 : STD_LOGIC;
signal blk00000003_sig00000140 : STD_LOGIC;
signal blk00000003_sig0000013f : STD_LOGIC;
signal blk00000003_sig0000013e : STD_LOGIC;
signal blk00000003_sig0000013d : STD_LOGIC;
signal blk00000003_sig0000013c : STD_LOGIC;
signal blk00000003_sig0000013b : STD_LOGIC;
signal blk00000003_sig0000013a : STD_LOGIC;
signal blk00000003_sig00000139 : STD_LOGIC;
signal blk00000003_sig00000138 : STD_LOGIC;
signal blk00000003_sig00000137 : STD_LOGIC;
signal blk00000003_sig00000136 : STD_LOGIC;
signal blk00000003_sig00000135 : STD_LOGIC;
signal blk00000003_sig00000134 : STD_LOGIC;
signal blk00000003_sig00000133 : STD_LOGIC;
signal blk00000003_sig00000132 : STD_LOGIC;
signal blk00000003_sig00000131 : STD_LOGIC;
signal blk00000003_sig00000130 : STD_LOGIC;
signal blk00000003_sig0000012f : STD_LOGIC;
signal blk00000003_sig0000012e : STD_LOGIC;
signal blk00000003_sig0000012d : STD_LOGIC;
signal blk00000003_sig0000012c : STD_LOGIC;
signal blk00000003_sig0000012b : STD_LOGIC;
signal blk00000003_sig0000012a : STD_LOGIC;
signal blk00000003_sig00000129 : STD_LOGIC;
signal blk00000003_sig00000128 : STD_LOGIC;
signal blk00000003_sig00000127 : STD_LOGIC;
signal blk00000003_sig00000126 : STD_LOGIC;
signal blk00000003_sig00000125 : STD_LOGIC;
signal blk00000003_sig00000124 : STD_LOGIC;
signal blk00000003_sig00000123 : STD_LOGIC;
signal blk00000003_sig00000122 : STD_LOGIC;
signal blk00000003_sig00000121 : STD_LOGIC;
signal blk00000003_sig00000120 : STD_LOGIC;
signal blk00000003_sig0000011f : STD_LOGIC;
signal blk00000003_sig0000011e : STD_LOGIC;
signal blk00000003_sig0000011d : STD_LOGIC;
signal blk00000003_sig0000011c : STD_LOGIC;
signal blk00000003_sig0000011b : STD_LOGIC;
signal blk00000003_sig0000011a : STD_LOGIC;
signal blk00000003_sig00000119 : STD_LOGIC;
signal blk00000003_sig00000118 : STD_LOGIC;
signal blk00000003_sig00000117 : STD_LOGIC;
signal blk00000003_sig00000116 : STD_LOGIC;
signal blk00000003_sig00000115 : STD_LOGIC;
signal blk00000003_sig00000114 : STD_LOGIC;
signal blk00000003_sig00000113 : STD_LOGIC;
signal blk00000003_sig00000112 : STD_LOGIC;
signal blk00000003_sig00000111 : STD_LOGIC;
signal blk00000003_sig00000110 : STD_LOGIC;
signal blk00000003_sig0000010f : STD_LOGIC;
signal blk00000003_sig0000010e : STD_LOGIC;
signal blk00000003_sig0000010d : STD_LOGIC;
signal blk00000003_sig0000010c : STD_LOGIC;
signal blk00000003_sig0000010b : STD_LOGIC;
signal blk00000003_sig0000010a : STD_LOGIC;
signal blk00000003_sig00000109 : STD_LOGIC;
signal blk00000003_sig00000108 : STD_LOGIC;
signal blk00000003_sig00000107 : STD_LOGIC;
signal blk00000003_sig00000106 : STD_LOGIC;
signal blk00000003_sig00000105 : STD_LOGIC;
signal blk00000003_sig00000104 : STD_LOGIC;
signal blk00000003_sig00000103 : STD_LOGIC;
signal blk00000003_sig00000102 : STD_LOGIC;
signal blk00000003_sig00000101 : STD_LOGIC;
signal blk00000003_sig00000100 : STD_LOGIC;
signal blk00000003_sig000000ff : STD_LOGIC;
signal blk00000003_sig000000fe : STD_LOGIC;
signal blk00000003_sig000000fd : STD_LOGIC;
signal blk00000003_sig000000fc : STD_LOGIC;
signal blk00000003_sig000000fb : STD_LOGIC;
signal blk00000003_sig000000fa : STD_LOGIC;
signal blk00000003_sig000000f9 : STD_LOGIC;
signal blk00000003_sig000000f8 : STD_LOGIC;
signal blk00000003_sig000000f7 : STD_LOGIC;
signal blk00000003_sig000000f6 : STD_LOGIC;
signal blk00000003_sig000000f5 : STD_LOGIC;
signal blk00000003_sig000000f4 : STD_LOGIC;
signal blk00000003_sig000000f3 : STD_LOGIC;
signal blk00000003_sig000000f2 : STD_LOGIC;
signal blk00000003_sig000000f1 : STD_LOGIC;
signal blk00000003_sig000000f0 : STD_LOGIC;
signal blk00000003_sig000000ef : STD_LOGIC;
signal blk00000003_sig000000ee : STD_LOGIC;
signal blk00000003_sig000000ed : STD_LOGIC;
signal blk00000003_sig000000ec : STD_LOGIC;
signal blk00000003_sig000000eb : STD_LOGIC;
signal blk00000003_sig000000ea : STD_LOGIC;
signal blk00000003_sig000000e9 : STD_LOGIC;
signal blk00000003_sig000000e8 : STD_LOGIC;
signal blk00000003_sig000000e7 : STD_LOGIC;
signal blk00000003_sig000000e6 : STD_LOGIC;
signal blk00000003_sig000000e5 : STD_LOGIC;
signal blk00000003_sig000000e4 : STD_LOGIC;
signal blk00000003_sig000000e3 : STD_LOGIC;
signal blk00000003_sig000000e2 : STD_LOGIC;
signal blk00000003_sig000000e1 : STD_LOGIC;
signal blk00000003_sig000000e0 : STD_LOGIC;
signal blk00000003_sig000000df : STD_LOGIC;
signal blk00000003_sig000000de : STD_LOGIC;
signal blk00000003_sig000000dd : STD_LOGIC;
signal blk00000003_sig000000dc : STD_LOGIC;
signal blk00000003_sig000000db : STD_LOGIC;
signal blk00000003_sig000000da : STD_LOGIC;
signal blk00000003_sig000000d9 : STD_LOGIC;
signal blk00000003_sig000000d8 : STD_LOGIC;
signal blk00000003_sig000000d7 : STD_LOGIC;
signal blk00000003_sig000000d6 : STD_LOGIC;
signal blk00000003_sig000000d5 : STD_LOGIC;
signal blk00000003_sig000000d4 : STD_LOGIC;
signal blk00000003_sig000000d3 : STD_LOGIC;
signal blk00000003_sig000000d2 : STD_LOGIC;
signal blk00000003_sig000000d1 : STD_LOGIC;
signal blk00000003_sig000000d0 : STD_LOGIC;
signal blk00000003_sig000000cf : STD_LOGIC;
signal blk00000003_sig000000ce : STD_LOGIC;
signal blk00000003_sig000000cd : STD_LOGIC;
signal blk00000003_sig000000cc : STD_LOGIC;
signal blk00000003_sig000000cb : STD_LOGIC;
signal blk00000003_sig000000ca : STD_LOGIC;
signal blk00000003_sig000000c9 : STD_LOGIC;
signal blk00000003_sig000000c8 : STD_LOGIC;
signal blk00000003_sig000000c7 : STD_LOGIC;
signal blk00000003_sig000000c6 : STD_LOGIC;
signal blk00000003_sig000000c5 : STD_LOGIC;
signal blk00000003_sig000000c4 : STD_LOGIC;
signal blk00000003_sig000000c3 : STD_LOGIC;
signal blk00000003_sig000000c2 : STD_LOGIC;
signal blk00000003_sig000000c1 : STD_LOGIC;
signal blk00000003_sig000000c0 : STD_LOGIC;
signal blk00000003_sig000000bf : STD_LOGIC;
signal blk00000003_sig000000be : STD_LOGIC;
signal blk00000003_sig000000bd : STD_LOGIC;
signal blk00000003_sig000000bc : STD_LOGIC;
signal blk00000003_sig000000bb : STD_LOGIC;
signal blk00000003_sig000000ba : STD_LOGIC;
signal blk00000003_sig000000b9 : STD_LOGIC;
signal blk00000003_sig000000b8 : STD_LOGIC;
signal blk00000003_sig000000b7 : STD_LOGIC;
signal blk00000003_sig000000b6 : STD_LOGIC;
signal blk00000003_sig000000b5 : STD_LOGIC;
signal blk00000003_sig000000b4 : STD_LOGIC;
signal blk00000003_sig000000b3 : STD_LOGIC;
signal blk00000003_sig000000b2 : STD_LOGIC;
signal blk00000003_sig000000b1 : STD_LOGIC;
signal blk00000003_sig000000b0 : STD_LOGIC;
signal blk00000003_sig000000af : STD_LOGIC;
signal blk00000003_sig000000ae : STD_LOGIC;
signal blk00000003_sig000000ad : STD_LOGIC;
signal blk00000003_sig000000ac : STD_LOGIC;
signal blk00000003_sig000000ab : STD_LOGIC;
signal blk00000003_sig000000aa : STD_LOGIC;
signal blk00000003_sig000000a9 : STD_LOGIC;
signal blk00000003_sig000000a8 : STD_LOGIC;
signal blk00000003_sig000000a7 : STD_LOGIC;
signal blk00000003_sig000000a6 : STD_LOGIC;
signal blk00000003_sig000000a5 : STD_LOGIC;
signal blk00000003_sig000000a4 : STD_LOGIC;
signal blk00000003_sig000000a3 : STD_LOGIC;
signal blk00000003_sig000000a2 : STD_LOGIC;
signal blk00000003_sig000000a1 : STD_LOGIC;
signal blk00000003_sig000000a0 : STD_LOGIC;
signal blk00000003_sig0000009f : STD_LOGIC;
signal blk00000003_sig0000009e : STD_LOGIC;
signal blk00000003_sig0000009d : STD_LOGIC;
signal blk00000003_sig0000009c : STD_LOGIC;
signal blk00000003_sig0000009b : STD_LOGIC;
signal blk00000003_sig0000009a : STD_LOGIC;
signal blk00000003_sig00000099 : STD_LOGIC;
signal blk00000003_sig00000098 : STD_LOGIC;
signal blk00000003_sig00000097 : STD_LOGIC;
signal blk00000003_sig00000096 : STD_LOGIC;
signal blk00000003_sig00000095 : STD_LOGIC;
signal blk00000003_sig00000094 : STD_LOGIC;
signal blk00000003_sig00000093 : STD_LOGIC;
signal blk00000003_sig00000092 : STD_LOGIC;
signal blk00000003_sig00000091 : STD_LOGIC;
signal blk00000003_sig00000090 : STD_LOGIC;
signal blk00000003_sig0000008f : STD_LOGIC;
signal blk00000003_sig0000008e : STD_LOGIC;
signal blk00000003_sig0000008d : STD_LOGIC;
signal blk00000003_sig0000008c : STD_LOGIC;
signal blk00000003_sig0000008b : STD_LOGIC;
signal blk00000003_sig0000008a : STD_LOGIC;
signal blk00000003_sig00000089 : STD_LOGIC;
signal blk00000003_sig00000088 : STD_LOGIC;
signal blk00000003_sig00000087 : STD_LOGIC;
signal blk00000003_sig00000086 : STD_LOGIC;
signal blk00000003_sig00000085 : STD_LOGIC;
signal blk00000003_sig00000084 : STD_LOGIC;
signal blk00000003_sig00000083 : STD_LOGIC;
signal blk00000003_sig00000082 : STD_LOGIC;
signal blk00000003_sig00000081 : STD_LOGIC;
signal blk00000003_sig00000080 : STD_LOGIC;
signal blk00000003_sig0000007f : STD_LOGIC;
signal blk00000003_sig0000007e : STD_LOGIC;
signal blk00000003_sig0000007d : STD_LOGIC;
signal blk00000003_sig0000007c : STD_LOGIC;
signal blk00000003_sig0000007b : STD_LOGIC;
signal blk00000003_sig0000007a : STD_LOGIC;
signal blk00000003_sig00000079 : STD_LOGIC;
signal blk00000003_sig00000078 : STD_LOGIC;
signal blk00000003_sig00000077 : STD_LOGIC;
signal blk00000003_sig00000076 : STD_LOGIC;
signal blk00000003_sig00000075 : STD_LOGIC;
signal blk00000003_sig00000074 : STD_LOGIC;
signal blk00000003_sig00000073 : STD_LOGIC;
signal blk00000003_sig00000072 : STD_LOGIC;
signal blk00000003_sig00000071 : STD_LOGIC;
signal blk00000003_sig00000070 : STD_LOGIC;
signal blk00000003_sig0000006f : STD_LOGIC;
signal blk00000003_sig0000006e : STD_LOGIC;
signal blk00000003_sig0000006d : STD_LOGIC;
signal blk00000003_sig0000006c : STD_LOGIC;
signal blk00000003_sig0000006b : STD_LOGIC;
signal blk00000003_sig0000006a : STD_LOGIC;
signal blk00000003_sig00000069 : STD_LOGIC;
signal blk00000003_sig00000068 : STD_LOGIC;
signal blk00000003_sig00000067 : STD_LOGIC;
signal blk00000003_sig00000066 : STD_LOGIC;
signal blk00000003_sig00000065 : STD_LOGIC;
signal blk00000003_sig00000064 : STD_LOGIC;
signal blk00000003_sig00000063 : STD_LOGIC;
signal blk00000003_sig00000062 : STD_LOGIC;
signal blk00000003_sig00000061 : STD_LOGIC;
signal blk00000003_sig00000060 : STD_LOGIC;
signal blk00000003_sig0000005f : STD_LOGIC;
signal blk00000003_sig0000005e : STD_LOGIC;
signal blk00000003_sig0000005d : STD_LOGIC;
signal blk00000003_sig0000005c : STD_LOGIC;
signal blk00000003_sig0000005b : STD_LOGIC;
signal blk00000003_sig0000005a : STD_LOGIC;
signal blk00000003_sig00000059 : STD_LOGIC;
signal blk00000003_sig00000058 : STD_LOGIC;
signal blk00000003_sig00000057 : STD_LOGIC;
signal blk00000003_sig00000056 : STD_LOGIC;
signal blk00000003_sig00000055 : STD_LOGIC;
signal blk00000003_sig00000054 : STD_LOGIC;
signal blk00000003_sig00000053 : STD_LOGIC;
signal blk00000003_sig00000052 : STD_LOGIC;
signal blk00000003_sig00000051 : STD_LOGIC;
signal blk00000003_sig00000050 : STD_LOGIC;
signal blk00000003_sig0000004f : STD_LOGIC;
signal blk00000003_sig0000004e : STD_LOGIC;
signal blk00000003_sig0000004d : STD_LOGIC;
signal blk00000003_sig0000004c : STD_LOGIC;
signal blk00000003_sig0000004b : STD_LOGIC;
signal blk00000003_sig0000004a : STD_LOGIC;
signal blk00000003_sig00000049 : STD_LOGIC;
signal blk00000003_sig00000048 : STD_LOGIC;
signal blk00000003_sig00000047 : STD_LOGIC;
signal blk00000003_sig00000046 : STD_LOGIC;
signal blk00000003_sig00000045 : STD_LOGIC;
signal blk00000003_sig00000044 : STD_LOGIC;
signal blk00000003_sig00000043 : STD_LOGIC;
signal blk00000003_sig00000042 : STD_LOGIC;
signal blk00000003_sig00000041 : STD_LOGIC;
signal blk00000003_sig00000040 : STD_LOGIC;
signal blk00000003_sig0000003f : STD_LOGIC;
signal blk00000003_sig0000003e : STD_LOGIC;
signal blk00000003_sig0000003d : STD_LOGIC;
signal blk00000003_sig0000003c : STD_LOGIC;
signal blk00000003_sig0000003b : STD_LOGIC;
signal blk00000003_sig0000003a : STD_LOGIC;
signal blk00000003_sig00000039 : STD_LOGIC;
signal blk00000003_sig00000038 : STD_LOGIC;
signal blk00000003_sig00000037 : STD_LOGIC;
signal blk00000003_sig00000036 : STD_LOGIC;
signal blk00000003_sig00000035 : STD_LOGIC;
signal blk00000003_sig00000034 : STD_LOGIC;
signal blk00000003_sig00000033 : STD_LOGIC;
signal blk00000003_sig00000032 : STD_LOGIC;
signal blk00000003_sig00000031 : STD_LOGIC;
signal blk00000003_sig00000030 : STD_LOGIC;
signal blk00000003_sig0000002f : STD_LOGIC;
signal blk00000003_sig0000002e : STD_LOGIC;
signal blk00000003_sig0000002d : STD_LOGIC;
signal blk00000003_sig0000002c : STD_LOGIC;
signal blk00000003_sig0000002b : STD_LOGIC;
signal blk00000003_sig0000002a : STD_LOGIC;
signal blk00000003_sig00000029 : STD_LOGIC;
signal blk00000003_sig00000028 : STD_LOGIC;
signal blk00000003_sig00000027 : STD_LOGIC;
signal blk00000003_sig00000026 : STD_LOGIC;
signal blk00000003_sig00000025 : STD_LOGIC;
signal blk00000003_sig00000024 : STD_LOGIC;
signal blk00000003_sig00000022 : STD_LOGIC;
signal NLW_blk00000001_P_UNCONNECTED : STD_LOGIC;
signal NLW_blk00000002_G_UNCONNECTED : STD_LOGIC;
signal dividend_0 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal divisor_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal quotient_2 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal fractional_3 : STD_LOGIC_VECTOR ( 7 downto 0 );
begin
dividend_0(7) <= dividend(7);
dividend_0(6) <= dividend(6);
dividend_0(5) <= dividend(5);
dividend_0(4) <= dividend(4);
dividend_0(3) <= dividend(3);
dividend_0(2) <= dividend(2);
dividend_0(1) <= dividend(1);
dividend_0(0) <= dividend(0);
quotient(7) <= quotient_2(7);
quotient(6) <= quotient_2(6);
quotient(5) <= quotient_2(5);
quotient(4) <= quotient_2(4);
quotient(3) <= quotient_2(3);
quotient(2) <= quotient_2(2);
quotient(1) <= quotient_2(1);
quotient(0) <= quotient_2(0);
divisor_1(7) <= divisor(7);
divisor_1(6) <= divisor(6);
divisor_1(5) <= divisor(5);
divisor_1(4) <= divisor(4);
divisor_1(3) <= divisor(3);
divisor_1(2) <= divisor(2);
divisor_1(1) <= divisor(1);
divisor_1(0) <= divisor(0);
rfd <= NlwRenamedSig_OI_rfd;
fractional(7) <= fractional_3(7);
fractional(6) <= fractional_3(6);
fractional(5) <= fractional_3(5);
fractional(4) <= fractional_3(4);
fractional(3) <= fractional_3(3);
fractional(2) <= fractional_3(2);
fractional(1) <= fractional_3(1);
fractional(0) <= fractional_3(0);
blk00000001 : VCC
port map (
P => NLW_blk00000001_P_UNCONNECTED
);
blk00000002 : GND
port map (
G => NLW_blk00000002_G_UNCONNECTED
);
blk00000003_blk00000264 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000272,
Q => blk00000003_sig000000dd
);
blk00000003_blk00000263 : SRL16
generic map(
INIT => X"0000"
)
port map (
A0 => blk00000003_sig00000022,
A1 => blk00000003_sig00000022,
A2 => blk00000003_sig00000022,
A3 => blk00000003_sig00000022,
CLK => clk,
D => blk00000003_sig0000026c,
Q => blk00000003_sig00000272
);
blk00000003_blk00000262 : SRL16
generic map(
INIT => X"0000"
)
port map (
A0 => NlwRenamedSig_OI_rfd,
A1 => blk00000003_sig00000022,
A2 => blk00000003_sig00000022,
A3 => blk00000003_sig00000022,
CLK => clk,
D => dividend_0(0),
Q => blk00000003_sig0000007f
);
blk00000003_blk00000261 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000271,
Q => blk00000003_sig000000e0
);
blk00000003_blk00000260 : SRL16
generic map(
INIT => X"0001"
)
port map (
A0 => blk00000003_sig00000022,
A1 => blk00000003_sig00000022,
A2 => blk00000003_sig00000022,
A3 => blk00000003_sig00000022,
CLK => clk,
D => divisor_1(0),
Q => blk00000003_sig00000271
);
blk00000003_blk0000025f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000270,
Q => blk00000003_sig00000266
);
blk00000003_blk0000025e : SRL16
generic map(
INIT => X"0000"
)
port map (
A0 => blk00000003_sig00000022,
A1 => NlwRenamedSig_OI_rfd,
A2 => NlwRenamedSig_OI_rfd,
A3 => blk00000003_sig00000022,
CLK => clk,
D => blk00000003_sig00000041,
Q => blk00000003_sig00000270
);
blk00000003_blk0000025d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000026f,
Q => blk00000003_sig00000264
);
blk00000003_blk0000025c : SRL16
generic map(
INIT => X"0000"
)
port map (
A0 => blk00000003_sig00000022,
A1 => NlwRenamedSig_OI_rfd,
A2 => NlwRenamedSig_OI_rfd,
A3 => blk00000003_sig00000022,
CLK => clk,
D => blk00000003_sig00000040,
Q => blk00000003_sig0000026f
);
blk00000003_blk0000025b : SRL16
generic map(
INIT => X"0000"
)
port map (
A0 => NlwRenamedSig_OI_rfd,
A1 => blk00000003_sig00000022,
A2 => blk00000003_sig00000022,
A3 => blk00000003_sig00000022,
CLK => clk,
D => blk00000003_sig0000026e,
Q => blk00000003_sig00000082
);
blk00000003_blk0000025a : MUXF5
port map (
I0 => dividend_0(3),
I1 => blk00000003_sig0000026d,
S => dividend_0(7),
O => blk00000003_sig0000026e
);
blk00000003_blk00000259 : LUT4
generic map(
INIT => X"5556"
)
port map (
I0 => dividend_0(3),
I1 => dividend_0(2),
I2 => dividend_0(1),
I3 => dividend_0(0),
O => blk00000003_sig0000026d
);
blk00000003_blk00000258 : MUXF5
port map (
I0 => divisor_1(3),
I1 => blk00000003_sig0000026b,
S => divisor_1(7),
O => blk00000003_sig0000026c
);
blk00000003_blk00000257 : LUT4
generic map(
INIT => X"5556"
)
port map (
I0 => divisor_1(3),
I1 => divisor_1(2),
I2 => divisor_1(1),
I3 => divisor_1(0),
O => blk00000003_sig0000026b
);
blk00000003_blk00000256 : INV
port map (
I => blk00000003_sig000000d9,
O => blk00000003_sig000000e4
);
blk00000003_blk00000255 : INV
port map (
I => blk00000003_sig000000da,
O => blk00000003_sig000000e7
);
blk00000003_blk00000254 : INV
port map (
I => blk00000003_sig000000db,
O => blk00000003_sig000000ea
);
blk00000003_blk00000253 : INV
port map (
I => blk00000003_sig000000dc,
O => blk00000003_sig000000ed
);
blk00000003_blk00000252 : INV
port map (
I => blk00000003_sig000000dd,
O => blk00000003_sig000000f0
);
blk00000003_blk00000251 : INV
port map (
I => blk00000003_sig000000de,
O => blk00000003_sig000000f3
);
blk00000003_blk00000250 : INV
port map (
I => blk00000003_sig000000df,
O => blk00000003_sig000000f6
);
blk00000003_blk0000024f : INV
port map (
I => blk00000003_sig0000004f,
O => blk00000003_sig00000088
);
blk00000003_blk0000024e : INV
port map (
I => blk00000003_sig0000004d,
O => blk00000003_sig0000008a
);
blk00000003_blk0000024d : INV
port map (
I => blk00000003_sig0000004b,
O => blk00000003_sig0000008c
);
blk00000003_blk0000024c : INV
port map (
I => blk00000003_sig00000049,
O => blk00000003_sig0000008e
);
blk00000003_blk0000024b : INV
port map (
I => blk00000003_sig00000047,
O => blk00000003_sig00000090
);
blk00000003_blk0000024a : INV
port map (
I => blk00000003_sig00000045,
O => blk00000003_sig00000092
);
blk00000003_blk00000249 : INV
port map (
I => blk00000003_sig00000043,
O => blk00000003_sig00000094
);
blk00000003_blk00000248 : INV
port map (
I => blk00000003_sig00000042,
O => blk00000003_sig000001fb
);
blk00000003_blk00000247 : INV
port map (
I => blk00000003_sig00000050,
O => blk00000003_sig000001d6
);
blk00000003_blk00000246 : INV
port map (
I => blk00000003_sig0000005a,
O => blk00000003_sig000001b1
);
blk00000003_blk00000245 : INV
port map (
I => blk00000003_sig00000063,
O => blk00000003_sig0000018c
);
blk00000003_blk00000244 : INV
port map (
I => blk00000003_sig0000006c,
O => blk00000003_sig00000167
);
blk00000003_blk00000243 : INV
port map (
I => blk00000003_sig00000075,
O => blk00000003_sig00000142
);
blk00000003_blk00000242 : INV
port map (
I => blk00000003_sig0000007e,
O => blk00000003_sig0000011d
);
blk00000003_blk00000241 : LUT3
generic map(
INIT => X"96"
)
port map (
I0 => blk00000003_sig00000264,
I1 => blk00000003_sig00000266,
I2 => blk00000003_sig0000008b,
O => blk00000003_sig00000239
);
blk00000003_blk00000240 : LUT3
generic map(
INIT => X"96"
)
port map (
I0 => blk00000003_sig00000264,
I1 => blk00000003_sig00000266,
I2 => blk00000003_sig0000008d,
O => blk00000003_sig0000023c
);
blk00000003_blk0000023f : LUT3
generic map(
INIT => X"96"
)
port map (
I0 => blk00000003_sig00000264,
I1 => blk00000003_sig00000266,
I2 => blk00000003_sig0000008f,
O => blk00000003_sig0000023f
);
blk00000003_blk0000023e : LUT3
generic map(
INIT => X"96"
)
port map (
I0 => blk00000003_sig00000264,
I1 => blk00000003_sig00000266,
I2 => blk00000003_sig00000091,
O => blk00000003_sig00000242
);
blk00000003_blk0000023d : LUT3
generic map(
INIT => X"96"
)
port map (
I0 => blk00000003_sig00000264,
I1 => blk00000003_sig00000266,
I2 => blk00000003_sig00000093,
O => blk00000003_sig00000245
);
blk00000003_blk0000023c : LUT3
generic map(
INIT => X"96"
)
port map (
I0 => blk00000003_sig00000264,
I1 => blk00000003_sig00000266,
I2 => blk00000003_sig00000095,
O => blk00000003_sig00000248
);
blk00000003_blk0000023b : LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => blk00000003_sig00000097,
I1 => blk00000003_sig00000266,
I2 => blk00000003_sig00000264,
I3 => blk00000003_sig0000024c,
O => blk00000003_sig0000024a
);
blk00000003_blk0000023a : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => blk00000003_sig0000022d,
I1 => blk00000003_sig00000264,
O => blk00000003_sig0000024e
);
blk00000003_blk00000239 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => blk00000003_sig0000022e,
I1 => blk00000003_sig00000264,
O => blk00000003_sig00000251
);
blk00000003_blk00000238 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => blk00000003_sig0000022f,
I1 => blk00000003_sig00000264,
O => blk00000003_sig00000254
);
blk00000003_blk00000237 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => blk00000003_sig00000230,
I1 => blk00000003_sig00000264,
O => blk00000003_sig00000257
);
blk00000003_blk00000236 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => blk00000003_sig00000231,
I1 => blk00000003_sig00000264,
O => blk00000003_sig0000025a
);
blk00000003_blk00000235 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => blk00000003_sig00000232,
I1 => blk00000003_sig00000264,
O => blk00000003_sig0000025d
);
blk00000003_blk00000234 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => blk00000003_sig00000233,
I1 => blk00000003_sig00000264,
O => blk00000003_sig00000260
);
blk00000003_blk00000233 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => blk00000003_sig00000234,
I1 => blk00000003_sig00000264,
O => blk00000003_sig00000265
);
blk00000003_blk00000232 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => blk00000003_sig00000089,
I1 => blk00000003_sig0000024c,
O => blk00000003_sig00000236
);
blk00000003_blk00000231 : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000200,
I1 => blk00000003_sig0000009a,
I2 => blk00000003_sig000001ff,
O => blk00000003_sig00000209
);
blk00000003_blk00000230 : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000201,
I1 => blk00000003_sig0000009c,
I2 => blk00000003_sig000001ff,
O => blk00000003_sig0000020c
);
blk00000003_blk0000022f : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000202,
I1 => blk00000003_sig0000009e,
I2 => blk00000003_sig000001ff,
O => blk00000003_sig0000020f
);
blk00000003_blk0000022e : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000203,
I1 => blk00000003_sig000000a0,
I2 => blk00000003_sig000001ff,
O => blk00000003_sig00000212
);
blk00000003_blk0000022d : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000204,
I1 => blk00000003_sig000000a2,
I2 => blk00000003_sig000001ff,
O => blk00000003_sig00000215
);
blk00000003_blk0000022c : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000205,
I1 => blk00000003_sig000000a4,
I2 => blk00000003_sig000001ff,
O => blk00000003_sig00000218
);
blk00000003_blk0000022b : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000206,
I1 => blk00000003_sig000000a6,
I2 => blk00000003_sig000001ff,
O => blk00000003_sig0000021b
);
blk00000003_blk0000022a : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000207,
I1 => blk00000003_sig000000a8,
I2 => blk00000003_sig000001ff,
O => blk00000003_sig00000228
);
blk00000003_blk00000229 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig000001f9,
I1 => blk00000003_sig00000042,
O => blk00000003_sig000001db
);
blk00000003_blk00000228 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001f2,
I1 => blk00000003_sig00000099,
I2 => blk00000003_sig00000042,
O => blk00000003_sig000001de
);
blk00000003_blk00000227 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001f3,
I1 => blk00000003_sig0000009b,
I2 => blk00000003_sig00000042,
O => blk00000003_sig000001e1
);
blk00000003_blk00000226 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001f4,
I1 => blk00000003_sig0000009d,
I2 => blk00000003_sig00000042,
O => blk00000003_sig000001e4
);
blk00000003_blk00000225 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001f5,
I1 => blk00000003_sig0000009f,
I2 => blk00000003_sig00000042,
O => blk00000003_sig000001e7
);
blk00000003_blk00000224 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001f6,
I1 => blk00000003_sig000000a1,
I2 => blk00000003_sig00000042,
O => blk00000003_sig000001ea
);
blk00000003_blk00000223 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001f7,
I1 => blk00000003_sig000000a3,
I2 => blk00000003_sig00000042,
O => blk00000003_sig000001ed
);
blk00000003_blk00000222 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001f8,
I1 => blk00000003_sig000000a5,
I2 => blk00000003_sig00000042,
O => blk00000003_sig000001f0
);
blk00000003_blk00000221 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000087,
I1 => blk00000003_sig000000a7,
I2 => blk00000003_sig00000042,
O => blk00000003_sig000001fc
);
blk00000003_blk00000220 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig000001d4,
I1 => blk00000003_sig00000050,
O => blk00000003_sig000001b6
);
blk00000003_blk0000021f : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001cd,
I1 => blk00000003_sig000000a9,
I2 => blk00000003_sig00000050,
O => blk00000003_sig000001b9
);
blk00000003_blk0000021e : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001ce,
I1 => blk00000003_sig000000aa,
I2 => blk00000003_sig00000050,
O => blk00000003_sig000001bc
);
blk00000003_blk0000021d : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001cf,
I1 => blk00000003_sig000000ab,
I2 => blk00000003_sig00000050,
O => blk00000003_sig000001bf
);
blk00000003_blk0000021c : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001d0,
I1 => blk00000003_sig000000ac,
I2 => blk00000003_sig00000050,
O => blk00000003_sig000001c2
);
blk00000003_blk0000021b : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001d1,
I1 => blk00000003_sig000000ad,
I2 => blk00000003_sig00000050,
O => blk00000003_sig000001c5
);
blk00000003_blk0000021a : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001d2,
I1 => blk00000003_sig000000ae,
I2 => blk00000003_sig00000050,
O => blk00000003_sig000001c8
);
blk00000003_blk00000219 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001d3,
I1 => blk00000003_sig000000af,
I2 => blk00000003_sig00000050,
O => blk00000003_sig000001cb
);
blk00000003_blk00000218 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000059,
I1 => blk00000003_sig000000b0,
I2 => blk00000003_sig00000050,
O => blk00000003_sig000001d7
);
blk00000003_blk00000217 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig000001af,
I1 => blk00000003_sig0000005a,
O => blk00000003_sig00000191
);
blk00000003_blk00000216 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001a8,
I1 => blk00000003_sig000000b1,
I2 => blk00000003_sig0000005a,
O => blk00000003_sig00000194
);
blk00000003_blk00000215 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001a9,
I1 => blk00000003_sig000000b2,
I2 => blk00000003_sig0000005a,
O => blk00000003_sig00000197
);
blk00000003_blk00000214 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001aa,
I1 => blk00000003_sig000000b3,
I2 => blk00000003_sig0000005a,
O => blk00000003_sig0000019a
);
blk00000003_blk00000213 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001ab,
I1 => blk00000003_sig000000b4,
I2 => blk00000003_sig0000005a,
O => blk00000003_sig0000019d
);
blk00000003_blk00000212 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001ac,
I1 => blk00000003_sig000000b5,
I2 => blk00000003_sig0000005a,
O => blk00000003_sig000001a0
);
blk00000003_blk00000211 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001ad,
I1 => blk00000003_sig000000b6,
I2 => blk00000003_sig0000005a,
O => blk00000003_sig000001a3
);
blk00000003_blk00000210 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001ae,
I1 => blk00000003_sig000000b7,
I2 => blk00000003_sig0000005a,
O => blk00000003_sig000001a6
);
blk00000003_blk0000020f : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000062,
I1 => blk00000003_sig000000b8,
I2 => blk00000003_sig0000005a,
O => blk00000003_sig000001b2
);
blk00000003_blk0000020e : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig0000018a,
I1 => blk00000003_sig00000063,
O => blk00000003_sig0000016c
);
blk00000003_blk0000020d : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000183,
I1 => blk00000003_sig000000b9,
I2 => blk00000003_sig00000063,
O => blk00000003_sig0000016f
);
blk00000003_blk0000020c : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000184,
I1 => blk00000003_sig000000ba,
I2 => blk00000003_sig00000063,
O => blk00000003_sig00000172
);
blk00000003_blk0000020b : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000185,
I1 => blk00000003_sig000000bb,
I2 => blk00000003_sig00000063,
O => blk00000003_sig00000175
);
blk00000003_blk0000020a : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000186,
I1 => blk00000003_sig000000bc,
I2 => blk00000003_sig00000063,
O => blk00000003_sig00000178
);
blk00000003_blk00000209 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000187,
I1 => blk00000003_sig000000bd,
I2 => blk00000003_sig00000063,
O => blk00000003_sig0000017b
);
blk00000003_blk00000208 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000188,
I1 => blk00000003_sig000000be,
I2 => blk00000003_sig00000063,
O => blk00000003_sig0000017e
);
blk00000003_blk00000207 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000189,
I1 => blk00000003_sig000000bf,
I2 => blk00000003_sig00000063,
O => blk00000003_sig00000181
);
blk00000003_blk00000206 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000006b,
I1 => blk00000003_sig000000c0,
I2 => blk00000003_sig00000063,
O => blk00000003_sig0000018d
);
blk00000003_blk00000205 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig00000165,
I1 => blk00000003_sig0000006c,
O => blk00000003_sig00000147
);
blk00000003_blk00000204 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000015e,
I1 => blk00000003_sig000000c1,
I2 => blk00000003_sig0000006c,
O => blk00000003_sig0000014a
);
blk00000003_blk00000203 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000015f,
I1 => blk00000003_sig000000c2,
I2 => blk00000003_sig0000006c,
O => blk00000003_sig0000014d
);
blk00000003_blk00000202 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000160,
I1 => blk00000003_sig000000c3,
I2 => blk00000003_sig0000006c,
O => blk00000003_sig00000150
);
blk00000003_blk00000201 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000161,
I1 => blk00000003_sig000000c4,
I2 => blk00000003_sig0000006c,
O => blk00000003_sig00000153
);
blk00000003_blk00000200 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000162,
I1 => blk00000003_sig000000c5,
I2 => blk00000003_sig0000006c,
O => blk00000003_sig00000156
);
blk00000003_blk000001ff : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000163,
I1 => blk00000003_sig000000c6,
I2 => blk00000003_sig0000006c,
O => blk00000003_sig00000159
);
blk00000003_blk000001fe : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000164,
I1 => blk00000003_sig000000c7,
I2 => blk00000003_sig0000006c,
O => blk00000003_sig0000015c
);
blk00000003_blk000001fd : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000074,
I1 => blk00000003_sig000000c8,
I2 => blk00000003_sig0000006c,
O => blk00000003_sig00000168
);
blk00000003_blk000001fc : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig00000140,
I1 => blk00000003_sig00000075,
O => blk00000003_sig00000122
);
blk00000003_blk000001fb : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000139,
I1 => blk00000003_sig000000c9,
I2 => blk00000003_sig00000075,
O => blk00000003_sig00000125
);
blk00000003_blk000001fa : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000013a,
I1 => blk00000003_sig000000ca,
I2 => blk00000003_sig00000075,
O => blk00000003_sig00000128
);
blk00000003_blk000001f9 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000013b,
I1 => blk00000003_sig000000cb,
I2 => blk00000003_sig00000075,
O => blk00000003_sig0000012b
);
blk00000003_blk000001f8 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000013c,
I1 => blk00000003_sig000000cc,
I2 => blk00000003_sig00000075,
O => blk00000003_sig0000012e
);
blk00000003_blk000001f7 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000013d,
I1 => blk00000003_sig000000cd,
I2 => blk00000003_sig00000075,
O => blk00000003_sig00000131
);
blk00000003_blk000001f6 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000013e,
I1 => blk00000003_sig000000ce,
I2 => blk00000003_sig00000075,
O => blk00000003_sig00000134
);
blk00000003_blk000001f5 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000013f,
I1 => blk00000003_sig000000cf,
I2 => blk00000003_sig00000075,
O => blk00000003_sig00000137
);
blk00000003_blk000001f4 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000007d,
I1 => blk00000003_sig000000d0,
I2 => blk00000003_sig00000075,
O => blk00000003_sig00000143
);
blk00000003_blk000001f3 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig0000011b,
I1 => blk00000003_sig0000007e,
O => blk00000003_sig000000fd
);
blk00000003_blk000001f2 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000114,
I1 => blk00000003_sig000000d1,
I2 => blk00000003_sig0000007e,
O => blk00000003_sig00000100
);
blk00000003_blk000001f1 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000115,
I1 => blk00000003_sig000000d2,
I2 => blk00000003_sig0000007e,
O => blk00000003_sig00000103
);
blk00000003_blk000001f0 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000116,
I1 => blk00000003_sig000000d3,
I2 => blk00000003_sig0000007e,
O => blk00000003_sig00000106
);
blk00000003_blk000001ef : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000117,
I1 => blk00000003_sig000000d4,
I2 => blk00000003_sig0000007e,
O => blk00000003_sig00000109
);
blk00000003_blk000001ee : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000118,
I1 => blk00000003_sig000000d5,
I2 => blk00000003_sig0000007e,
O => blk00000003_sig0000010c
);
blk00000003_blk000001ed : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000119,
I1 => blk00000003_sig000000d6,
I2 => blk00000003_sig0000007e,
O => blk00000003_sig0000010f
);
blk00000003_blk000001ec : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000011a,
I1 => blk00000003_sig000000d7,
I2 => blk00000003_sig0000007e,
O => blk00000003_sig00000112
);
blk00000003_blk000001eb : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000086,
I1 => blk00000003_sig000000d8,
I2 => blk00000003_sig0000007e,
O => blk00000003_sig0000011e
);
blk00000003_blk000001ea : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig00000098,
I1 => blk00000003_sig000000e0,
O => blk00000003_sig000000f9
);
blk00000003_blk000001e9 : LUT1
generic map(
INIT => X"1"
)
port map (
I0 => blk00000003_sig000001ff,
O => blk00000003_sig00000096
);
blk00000003_blk000001e8 : LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => blk00000003_sig00000269,
I1 => divisor_1(4),
I2 => divisor_1(5),
O => blk00000003_sig0000026a
);
blk00000003_blk000001e7 : LUT3
generic map(
INIT => X"04"
)
port map (
I0 => divisor_1(6),
I1 => divisor_1(7),
I2 => blk00000003_sig0000026a,
O => blk00000003_sig00000034
);
blk00000003_blk000001e6 : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => divisor_1(6),
I1 => divisor_1(7),
I2 => blk00000003_sig0000026a,
O => blk00000003_sig00000036
);
blk00000003_blk000001e5 : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => divisor_1(1),
I1 => divisor_1(7),
I2 => divisor_1(0),
O => blk00000003_sig0000003e
);
blk00000003_blk000001e4 : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => divisor_1(4),
I1 => divisor_1(7),
I2 => blk00000003_sig00000269,
O => blk00000003_sig0000003a
);
blk00000003_blk000001e3 : LUT4
generic map(
INIT => X"666A"
)
port map (
I0 => divisor_1(5),
I1 => divisor_1(7),
I2 => divisor_1(4),
I3 => blk00000003_sig00000269,
O => blk00000003_sig00000038
);
blk00000003_blk000001e2 : LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => divisor_1(1),
I1 => divisor_1(2),
I2 => divisor_1(0),
I3 => divisor_1(3),
O => blk00000003_sig00000269
);
blk00000003_blk000001e1 : LUT4
generic map(
INIT => X"666A"
)
port map (
I0 => divisor_1(2),
I1 => divisor_1(7),
I2 => divisor_1(1),
I3 => divisor_1(0),
O => blk00000003_sig0000003c
);
blk00000003_blk000001e0 : LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => blk00000003_sig00000267,
I1 => dividend_0(4),
I2 => dividend_0(5),
O => blk00000003_sig00000268
);
blk00000003_blk000001df : LUT3
generic map(
INIT => X"04"
)
port map (
I0 => dividend_0(6),
I1 => dividend_0(7),
I2 => blk00000003_sig00000268,
O => blk00000003_sig00000028
);
blk00000003_blk000001de : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => dividend_0(6),
I1 => dividend_0(7),
I2 => blk00000003_sig00000268,
O => blk00000003_sig0000002a
);
blk00000003_blk000001dd : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => dividend_0(1),
I1 => dividend_0(7),
I2 => dividend_0(0),
O => blk00000003_sig00000032
);
blk00000003_blk000001dc : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => dividend_0(4),
I1 => dividend_0(7),
I2 => blk00000003_sig00000267,
O => blk00000003_sig0000002e
);
blk00000003_blk000001db : LUT4
generic map(
INIT => X"666A"
)
port map (
I0 => dividend_0(5),
I1 => dividend_0(7),
I2 => dividend_0(4),
I3 => blk00000003_sig00000267,
O => blk00000003_sig0000002c
);
blk00000003_blk000001da : LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => dividend_0(1),
I1 => dividend_0(2),
I2 => dividend_0(0),
I3 => dividend_0(3),
O => blk00000003_sig00000267
);
blk00000003_blk000001d9 : LUT4
generic map(
INIT => X"666A"
)
port map (
I0 => dividend_0(2),
I1 => dividend_0(7),
I2 => dividend_0(1),
I3 => dividend_0(0),
O => blk00000003_sig00000030
);
blk00000003_blk000001d8 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => blk00000003_sig00000266,
I1 => blk00000003_sig00000264,
O => blk00000003_sig0000024c
);
blk00000003_blk000001d7 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000263,
Q => fractional_3(0)
);
blk00000003_blk000001d6 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000261,
Q => fractional_3(1)
);
blk00000003_blk000001d5 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000025e,
Q => fractional_3(2)
);
blk00000003_blk000001d4 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000025b,
Q => fractional_3(3)
);
blk00000003_blk000001d3 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000258,
Q => fractional_3(4)
);
blk00000003_blk000001d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000255,
Q => fractional_3(5)
);
blk00000003_blk000001d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000252,
Q => fractional_3(6)
);
blk00000003_blk000001d0 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000024f,
Q => fractional_3(7)
);
blk00000003_blk000001cf : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => blk00000003_sig00000264,
I1 => blk00000003_sig00000265,
O => blk00000003_sig00000262
);
blk00000003_blk000001ce : MUXCY
port map (
CI => blk00000003_sig00000022,
DI => blk00000003_sig00000264,
S => blk00000003_sig00000262,
O => blk00000003_sig0000025f
);
blk00000003_blk000001cd : XORCY
port map (
CI => blk00000003_sig00000022,
LI => blk00000003_sig00000262,
O => blk00000003_sig00000263
);
blk00000003_blk000001cc : MUXCY
port map (
CI => blk00000003_sig0000025f,
DI => blk00000003_sig00000022,
S => blk00000003_sig00000260,
O => blk00000003_sig0000025c
);
blk00000003_blk000001cb : XORCY
port map (
CI => blk00000003_sig0000025f,
LI => blk00000003_sig00000260,
O => blk00000003_sig00000261
);
blk00000003_blk000001ca : MUXCY
port map (
CI => blk00000003_sig0000025c,
DI => blk00000003_sig00000022,
S => blk00000003_sig0000025d,
O => blk00000003_sig00000259
);
blk00000003_blk000001c9 : XORCY
port map (
CI => blk00000003_sig0000025c,
LI => blk00000003_sig0000025d,
O => blk00000003_sig0000025e
);
blk00000003_blk000001c8 : MUXCY
port map (
CI => blk00000003_sig00000259,
DI => blk00000003_sig00000022,
S => blk00000003_sig0000025a,
O => blk00000003_sig00000256
);
blk00000003_blk000001c7 : XORCY
port map (
CI => blk00000003_sig00000259,
LI => blk00000003_sig0000025a,
O => blk00000003_sig0000025b
);
blk00000003_blk000001c6 : MUXCY
port map (
CI => blk00000003_sig00000256,
DI => blk00000003_sig00000022,
S => blk00000003_sig00000257,
O => blk00000003_sig00000253
);
blk00000003_blk000001c5 : XORCY
port map (
CI => blk00000003_sig00000256,
LI => blk00000003_sig00000257,
O => blk00000003_sig00000258
);
blk00000003_blk000001c4 : MUXCY
port map (
CI => blk00000003_sig00000253,
DI => blk00000003_sig00000022,
S => blk00000003_sig00000254,
O => blk00000003_sig00000250
);
blk00000003_blk000001c3 : XORCY
port map (
CI => blk00000003_sig00000253,
LI => blk00000003_sig00000254,
O => blk00000003_sig00000255
);
blk00000003_blk000001c2 : MUXCY
port map (
CI => blk00000003_sig00000250,
DI => blk00000003_sig00000022,
S => blk00000003_sig00000251,
O => blk00000003_sig0000024d
);
blk00000003_blk000001c1 : XORCY
port map (
CI => blk00000003_sig00000250,
LI => blk00000003_sig00000251,
O => blk00000003_sig00000252
);
blk00000003_blk000001c0 : XORCY
port map (
CI => blk00000003_sig0000024d,
LI => blk00000003_sig0000024e,
O => blk00000003_sig0000024f
);
blk00000003_blk000001bf : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000024b,
Q => quotient_2(0)
);
blk00000003_blk000001be : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000249,
Q => quotient_2(1)
);
blk00000003_blk000001bd : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000246,
Q => quotient_2(2)
);
blk00000003_blk000001bc : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000243,
Q => quotient_2(3)
);
blk00000003_blk000001bb : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000240,
Q => quotient_2(4)
);
blk00000003_blk000001ba : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000023d,
Q => quotient_2(5)
);
blk00000003_blk000001b9 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000023a,
Q => quotient_2(6)
);
blk00000003_blk000001b8 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000237,
Q => quotient_2(7)
);
blk00000003_blk000001b7 : MUXCY
port map (
CI => blk00000003_sig00000022,
DI => blk00000003_sig0000024c,
S => blk00000003_sig0000024a,
O => blk00000003_sig00000247
);
blk00000003_blk000001b6 : XORCY
port map (
CI => blk00000003_sig00000022,
LI => blk00000003_sig0000024a,
O => blk00000003_sig0000024b
);
blk00000003_blk000001b5 : MUXCY
port map (
CI => blk00000003_sig00000247,
DI => blk00000003_sig00000022,
S => blk00000003_sig00000248,
O => blk00000003_sig00000244
);
blk00000003_blk000001b4 : XORCY
port map (
CI => blk00000003_sig00000247,
LI => blk00000003_sig00000248,
O => blk00000003_sig00000249
);
blk00000003_blk000001b3 : MUXCY
port map (
CI => blk00000003_sig00000244,
DI => blk00000003_sig00000022,
S => blk00000003_sig00000245,
O => blk00000003_sig00000241
);
blk00000003_blk000001b2 : XORCY
port map (
CI => blk00000003_sig00000244,
LI => blk00000003_sig00000245,
O => blk00000003_sig00000246
);
blk00000003_blk000001b1 : MUXCY
port map (
CI => blk00000003_sig00000241,
DI => blk00000003_sig00000022,
S => blk00000003_sig00000242,
O => blk00000003_sig0000023e
);
blk00000003_blk000001b0 : XORCY
port map (
CI => blk00000003_sig00000241,
LI => blk00000003_sig00000242,
O => blk00000003_sig00000243
);
blk00000003_blk000001af : MUXCY
port map (
CI => blk00000003_sig0000023e,
DI => blk00000003_sig00000022,
S => blk00000003_sig0000023f,
O => blk00000003_sig0000023b
);
blk00000003_blk000001ae : XORCY
port map (
CI => blk00000003_sig0000023e,
LI => blk00000003_sig0000023f,
O => blk00000003_sig00000240
);
blk00000003_blk000001ad : MUXCY
port map (
CI => blk00000003_sig0000023b,
DI => blk00000003_sig00000022,
S => blk00000003_sig0000023c,
O => blk00000003_sig00000238
);
blk00000003_blk000001ac : XORCY
port map (
CI => blk00000003_sig0000023b,
LI => blk00000003_sig0000023c,
O => blk00000003_sig0000023d
);
blk00000003_blk000001ab : MUXCY
port map (
CI => blk00000003_sig00000238,
DI => blk00000003_sig00000022,
S => blk00000003_sig00000239,
O => blk00000003_sig00000235
);
blk00000003_blk000001aa : XORCY
port map (
CI => blk00000003_sig00000238,
LI => blk00000003_sig00000239,
O => blk00000003_sig0000023a
);
blk00000003_blk000001a9 : XORCY
port map (
CI => blk00000003_sig00000235,
LI => blk00000003_sig00000236,
O => blk00000003_sig00000237
);
blk00000003_blk000001a8 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000229,
Q => blk00000003_sig00000234
);
blk00000003_blk000001a7 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000021c,
Q => blk00000003_sig00000233
);
blk00000003_blk000001a6 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000219,
Q => blk00000003_sig00000232
);
blk00000003_blk000001a5 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000216,
Q => blk00000003_sig00000231
);
blk00000003_blk000001a4 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000213,
Q => blk00000003_sig00000230
);
blk00000003_blk000001a3 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000210,
Q => blk00000003_sig0000022f
);
blk00000003_blk000001a2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000020d,
Q => blk00000003_sig0000022e
);
blk00000003_blk000001a1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000020a,
Q => blk00000003_sig0000022d
);
blk00000003_blk000001a0 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000021e,
Q => blk00000003_sig0000022c
);
blk00000003_blk0000019f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000220,
Q => blk00000003_sig0000022b
);
blk00000003_blk0000019e : MULT_AND
port map (
I0 => blk00000003_sig000000a8,
I1 => blk00000003_sig000001ff,
LO => blk00000003_sig0000022a
);
blk00000003_blk0000019d : MULT_AND
port map (
I0 => blk00000003_sig000000a6,
I1 => blk00000003_sig000001ff,
LO => blk00000003_sig00000227
);
blk00000003_blk0000019c : MULT_AND
port map (
I0 => blk00000003_sig000000a4,
I1 => blk00000003_sig000001ff,
LO => blk00000003_sig00000226
);
blk00000003_blk0000019b : MULT_AND
port map (
I0 => blk00000003_sig000000a2,
I1 => blk00000003_sig000001ff,
LO => blk00000003_sig00000225
);
blk00000003_blk0000019a : MULT_AND
port map (
I0 => blk00000003_sig000000a0,
I1 => blk00000003_sig000001ff,
LO => blk00000003_sig00000224
);
blk00000003_blk00000199 : MULT_AND
port map (
I0 => blk00000003_sig0000009e,
I1 => blk00000003_sig000001ff,
LO => blk00000003_sig00000223
);
blk00000003_blk00000198 : MULT_AND
port map (
I0 => blk00000003_sig0000009c,
I1 => blk00000003_sig000001ff,
LO => blk00000003_sig00000222
);
blk00000003_blk00000197 : MULT_AND
port map (
I0 => blk00000003_sig0000009a,
I1 => blk00000003_sig000001ff,
LO => blk00000003_sig00000221
);
blk00000003_blk00000196 : MULT_AND
port map (
I0 => blk00000003_sig00000022,
I1 => blk00000003_sig000001ff,
LO => blk00000003_sig0000021f
);
blk00000003_blk00000195 : MUXCY
port map (
CI => blk00000003_sig00000022,
DI => blk00000003_sig0000022a,
S => blk00000003_sig00000228,
O => blk00000003_sig0000021a
);
blk00000003_blk00000194 : XORCY
port map (
CI => blk00000003_sig00000022,
LI => blk00000003_sig00000228,
O => blk00000003_sig00000229
);
blk00000003_blk00000193 : MUXCY
port map (
CI => blk00000003_sig0000021a,
DI => blk00000003_sig00000227,
S => blk00000003_sig0000021b,
O => blk00000003_sig00000217
);
blk00000003_blk00000192 : MUXCY
port map (
CI => blk00000003_sig00000217,
DI => blk00000003_sig00000226,
S => blk00000003_sig00000218,
O => blk00000003_sig00000214
);
blk00000003_blk00000191 : MUXCY
port map (
CI => blk00000003_sig00000214,
DI => blk00000003_sig00000225,
S => blk00000003_sig00000215,
O => blk00000003_sig00000211
);
blk00000003_blk00000190 : MUXCY
port map (
CI => blk00000003_sig00000211,
DI => blk00000003_sig00000224,
S => blk00000003_sig00000212,
O => blk00000003_sig0000020e
);
blk00000003_blk0000018f : MUXCY
port map (
CI => blk00000003_sig0000020e,
DI => blk00000003_sig00000223,
S => blk00000003_sig0000020f,
O => blk00000003_sig0000020b
);
blk00000003_blk0000018e : MUXCY
port map (
CI => blk00000003_sig0000020b,
DI => blk00000003_sig00000222,
S => blk00000003_sig0000020c,
O => blk00000003_sig00000208
);
blk00000003_blk0000018d : MUXCY
port map (
CI => blk00000003_sig00000208,
DI => blk00000003_sig00000221,
S => blk00000003_sig00000209,
O => blk00000003_sig0000021d
);
blk00000003_blk0000018c : MUXCY
port map (
CI => blk00000003_sig0000021d,
DI => blk00000003_sig0000021f,
S => blk00000003_sig00000022,
O => blk00000003_sig00000220
);
blk00000003_blk0000018b : XORCY
port map (
CI => blk00000003_sig0000021d,
LI => blk00000003_sig00000022,
O => blk00000003_sig0000021e
);
blk00000003_blk0000018a : XORCY
port map (
CI => blk00000003_sig0000021a,
LI => blk00000003_sig0000021b,
O => blk00000003_sig0000021c
);
blk00000003_blk00000189 : XORCY
port map (
CI => blk00000003_sig00000217,
LI => blk00000003_sig00000218,
O => blk00000003_sig00000219
);
blk00000003_blk00000188 : XORCY
port map (
CI => blk00000003_sig00000214,
LI => blk00000003_sig00000215,
O => blk00000003_sig00000216
);
blk00000003_blk00000187 : XORCY
port map (
CI => blk00000003_sig00000211,
LI => blk00000003_sig00000212,
O => blk00000003_sig00000213
);
blk00000003_blk00000186 : XORCY
port map (
CI => blk00000003_sig0000020e,
LI => blk00000003_sig0000020f,
O => blk00000003_sig00000210
);
blk00000003_blk00000185 : XORCY
port map (
CI => blk00000003_sig0000020b,
LI => blk00000003_sig0000020c,
O => blk00000003_sig0000020d
);
blk00000003_blk00000184 : XORCY
port map (
CI => blk00000003_sig00000208,
LI => blk00000003_sig00000209,
O => blk00000003_sig0000020a
);
blk00000003_blk00000183 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000fa,
Q => blk00000003_sig0000011a
);
blk00000003_blk00000182 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000f7,
Q => blk00000003_sig00000119
);
blk00000003_blk00000181 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000f4,
Q => blk00000003_sig00000118
);
blk00000003_blk00000180 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000f1,
Q => blk00000003_sig00000117
);
blk00000003_blk0000017f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000ee,
Q => blk00000003_sig00000116
);
blk00000003_blk0000017e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000eb,
Q => blk00000003_sig00000115
);
blk00000003_blk0000017d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000e8,
Q => blk00000003_sig00000114
);
blk00000003_blk0000017c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000e5,
Q => blk00000003_sig0000011b
);
blk00000003_blk0000017b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000e2,
Q => blk00000003_sig0000007e
);
blk00000003_blk0000017a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000011f,
Q => blk00000003_sig0000013f
);
blk00000003_blk00000179 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000113,
Q => blk00000003_sig0000013e
);
blk00000003_blk00000178 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000110,
Q => blk00000003_sig0000013d
);
blk00000003_blk00000177 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000010d,
Q => blk00000003_sig0000013c
);
blk00000003_blk00000176 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000010a,
Q => blk00000003_sig0000013b
);
blk00000003_blk00000175 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000107,
Q => blk00000003_sig0000013a
);
blk00000003_blk00000174 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000104,
Q => blk00000003_sig00000139
);
blk00000003_blk00000173 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000101,
Q => blk00000003_sig00000140
);
blk00000003_blk00000172 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000fe,
Q => blk00000003_sig00000075
);
blk00000003_blk00000171 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000144,
Q => blk00000003_sig00000164
);
blk00000003_blk00000170 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000138,
Q => blk00000003_sig00000163
);
blk00000003_blk0000016f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000135,
Q => blk00000003_sig00000162
);
blk00000003_blk0000016e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000132,
Q => blk00000003_sig00000161
);
blk00000003_blk0000016d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000012f,
Q => blk00000003_sig00000160
);
blk00000003_blk0000016c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000012c,
Q => blk00000003_sig0000015f
);
blk00000003_blk0000016b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000129,
Q => blk00000003_sig0000015e
);
blk00000003_blk0000016a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000126,
Q => blk00000003_sig00000165
);
blk00000003_blk00000169 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000123,
Q => blk00000003_sig0000006c
);
blk00000003_blk00000168 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000169,
Q => blk00000003_sig00000189
);
blk00000003_blk00000167 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000015d,
Q => blk00000003_sig00000188
);
blk00000003_blk00000166 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000015a,
Q => blk00000003_sig00000187
);
blk00000003_blk00000165 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000157,
Q => blk00000003_sig00000186
);
blk00000003_blk00000164 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000154,
Q => blk00000003_sig00000185
);
blk00000003_blk00000163 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000151,
Q => blk00000003_sig00000184
);
blk00000003_blk00000162 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000014e,
Q => blk00000003_sig00000183
);
blk00000003_blk00000161 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000014b,
Q => blk00000003_sig0000018a
);
blk00000003_blk00000160 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000148,
Q => blk00000003_sig00000063
);
blk00000003_blk0000015f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000018e,
Q => blk00000003_sig000001ae
);
blk00000003_blk0000015e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000182,
Q => blk00000003_sig000001ad
);
blk00000003_blk0000015d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000017f,
Q => blk00000003_sig000001ac
);
blk00000003_blk0000015c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000017c,
Q => blk00000003_sig000001ab
);
blk00000003_blk0000015b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000179,
Q => blk00000003_sig000001aa
);
blk00000003_blk0000015a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000176,
Q => blk00000003_sig000001a9
);
blk00000003_blk00000159 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000173,
Q => blk00000003_sig000001a8
);
blk00000003_blk00000158 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000170,
Q => blk00000003_sig000001af
);
blk00000003_blk00000157 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000016d,
Q => blk00000003_sig0000005a
);
blk00000003_blk00000156 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001b3,
Q => blk00000003_sig000001d3
);
blk00000003_blk00000155 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001a7,
Q => blk00000003_sig000001d2
);
blk00000003_blk00000154 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001a4,
Q => blk00000003_sig000001d1
);
blk00000003_blk00000153 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001a1,
Q => blk00000003_sig000001d0
);
blk00000003_blk00000152 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000019e,
Q => blk00000003_sig000001cf
);
blk00000003_blk00000151 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000019b,
Q => blk00000003_sig000001ce
);
blk00000003_blk00000150 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000198,
Q => blk00000003_sig000001cd
);
blk00000003_blk0000014f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000195,
Q => blk00000003_sig000001d4
);
blk00000003_blk0000014e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000192,
Q => blk00000003_sig00000050
);
blk00000003_blk0000014d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001d8,
Q => blk00000003_sig000001f8
);
blk00000003_blk0000014c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001cc,
Q => blk00000003_sig000001f7
);
blk00000003_blk0000014b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001c9,
Q => blk00000003_sig000001f6
);
blk00000003_blk0000014a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001c6,
Q => blk00000003_sig000001f5
);
blk00000003_blk00000149 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001c3,
Q => blk00000003_sig000001f4
);
blk00000003_blk00000148 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001c0,
Q => blk00000003_sig000001f3
);
blk00000003_blk00000147 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001bd,
Q => blk00000003_sig000001f2
);
blk00000003_blk00000146 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001ba,
Q => blk00000003_sig000001f9
);
blk00000003_blk00000145 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001b7,
Q => blk00000003_sig00000042
);
blk00000003_blk00000144 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001fd,
Q => blk00000003_sig00000207
);
blk00000003_blk00000143 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001f1,
Q => blk00000003_sig00000206
);
blk00000003_blk00000142 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001ee,
Q => blk00000003_sig00000205
);
blk00000003_blk00000141 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001eb,
Q => blk00000003_sig00000204
);
blk00000003_blk00000140 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001e8,
Q => blk00000003_sig00000203
);
blk00000003_blk0000013f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001e5,
Q => blk00000003_sig00000202
);
blk00000003_blk0000013e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001e2,
Q => blk00000003_sig00000201
);
blk00000003_blk0000013d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001df,
Q => blk00000003_sig00000200
);
blk00000003_blk0000013c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001dc,
Q => blk00000003_sig000001ff
);
blk00000003_blk0000013b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001fa,
Q => blk00000003_sig000001fe
);
blk00000003_blk0000013a : MUXCY
port map (
CI => blk00000003_sig000001fb,
DI => blk00000003_sig00000087,
S => blk00000003_sig000001fc,
O => blk00000003_sig000001ef
);
blk00000003_blk00000139 : XORCY
port map (
CI => blk00000003_sig000001fb,
LI => blk00000003_sig000001fc,
O => blk00000003_sig000001fd
);
blk00000003_blk00000138 : MUXCY
port map (
CI => blk00000003_sig000001da,
DI => blk00000003_sig000001f9,
S => blk00000003_sig000001db,
O => blk00000003_sig000001fa
);
blk00000003_blk00000137 : MUXCY
port map (
CI => blk00000003_sig000001ef,
DI => blk00000003_sig000001f8,
S => blk00000003_sig000001f0,
O => blk00000003_sig000001ec
);
blk00000003_blk00000136 : MUXCY
port map (
CI => blk00000003_sig000001ec,
DI => blk00000003_sig000001f7,
S => blk00000003_sig000001ed,
O => blk00000003_sig000001e9
);
blk00000003_blk00000135 : MUXCY
port map (
CI => blk00000003_sig000001e9,
DI => blk00000003_sig000001f6,
S => blk00000003_sig000001ea,
O => blk00000003_sig000001e6
);
blk00000003_blk00000134 : MUXCY
port map (
CI => blk00000003_sig000001e6,
DI => blk00000003_sig000001f5,
S => blk00000003_sig000001e7,
O => blk00000003_sig000001e3
);
blk00000003_blk00000133 : MUXCY
port map (
CI => blk00000003_sig000001e3,
DI => blk00000003_sig000001f4,
S => blk00000003_sig000001e4,
O => blk00000003_sig000001e0
);
blk00000003_blk00000132 : MUXCY
port map (
CI => blk00000003_sig000001e0,
DI => blk00000003_sig000001f3,
S => blk00000003_sig000001e1,
O => blk00000003_sig000001dd
);
blk00000003_blk00000131 : MUXCY
port map (
CI => blk00000003_sig000001dd,
DI => blk00000003_sig000001f2,
S => blk00000003_sig000001de,
O => blk00000003_sig000001da
);
blk00000003_blk00000130 : XORCY
port map (
CI => blk00000003_sig000001ef,
LI => blk00000003_sig000001f0,
O => blk00000003_sig000001f1
);
blk00000003_blk0000012f : XORCY
port map (
CI => blk00000003_sig000001ec,
LI => blk00000003_sig000001ed,
O => blk00000003_sig000001ee
);
blk00000003_blk0000012e : XORCY
port map (
CI => blk00000003_sig000001e9,
LI => blk00000003_sig000001ea,
O => blk00000003_sig000001eb
);
blk00000003_blk0000012d : XORCY
port map (
CI => blk00000003_sig000001e6,
LI => blk00000003_sig000001e7,
O => blk00000003_sig000001e8
);
blk00000003_blk0000012c : XORCY
port map (
CI => blk00000003_sig000001e3,
LI => blk00000003_sig000001e4,
O => blk00000003_sig000001e5
);
blk00000003_blk0000012b : XORCY
port map (
CI => blk00000003_sig000001e0,
LI => blk00000003_sig000001e1,
O => blk00000003_sig000001e2
);
blk00000003_blk0000012a : XORCY
port map (
CI => blk00000003_sig000001dd,
LI => blk00000003_sig000001de,
O => blk00000003_sig000001df
);
blk00000003_blk00000129 : XORCY
port map (
CI => blk00000003_sig000001da,
LI => blk00000003_sig000001db,
O => blk00000003_sig000001dc
);
blk00000003_blk00000128 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001d5,
Q => blk00000003_sig000001d9
);
blk00000003_blk00000127 : MUXCY
port map (
CI => blk00000003_sig000001d6,
DI => blk00000003_sig00000059,
S => blk00000003_sig000001d7,
O => blk00000003_sig000001ca
);
blk00000003_blk00000126 : XORCY
port map (
CI => blk00000003_sig000001d6,
LI => blk00000003_sig000001d7,
O => blk00000003_sig000001d8
);
blk00000003_blk00000125 : MUXCY
port map (
CI => blk00000003_sig000001b5,
DI => blk00000003_sig000001d4,
S => blk00000003_sig000001b6,
O => blk00000003_sig000001d5
);
blk00000003_blk00000124 : MUXCY
port map (
CI => blk00000003_sig000001ca,
DI => blk00000003_sig000001d3,
S => blk00000003_sig000001cb,
O => blk00000003_sig000001c7
);
blk00000003_blk00000123 : MUXCY
port map (
CI => blk00000003_sig000001c7,
DI => blk00000003_sig000001d2,
S => blk00000003_sig000001c8,
O => blk00000003_sig000001c4
);
blk00000003_blk00000122 : MUXCY
port map (
CI => blk00000003_sig000001c4,
DI => blk00000003_sig000001d1,
S => blk00000003_sig000001c5,
O => blk00000003_sig000001c1
);
blk00000003_blk00000121 : MUXCY
port map (
CI => blk00000003_sig000001c1,
DI => blk00000003_sig000001d0,
S => blk00000003_sig000001c2,
O => blk00000003_sig000001be
);
blk00000003_blk00000120 : MUXCY
port map (
CI => blk00000003_sig000001be,
DI => blk00000003_sig000001cf,
S => blk00000003_sig000001bf,
O => blk00000003_sig000001bb
);
blk00000003_blk0000011f : MUXCY
port map (
CI => blk00000003_sig000001bb,
DI => blk00000003_sig000001ce,
S => blk00000003_sig000001bc,
O => blk00000003_sig000001b8
);
blk00000003_blk0000011e : MUXCY
port map (
CI => blk00000003_sig000001b8,
DI => blk00000003_sig000001cd,
S => blk00000003_sig000001b9,
O => blk00000003_sig000001b5
);
blk00000003_blk0000011d : XORCY
port map (
CI => blk00000003_sig000001ca,
LI => blk00000003_sig000001cb,
O => blk00000003_sig000001cc
);
blk00000003_blk0000011c : XORCY
port map (
CI => blk00000003_sig000001c7,
LI => blk00000003_sig000001c8,
O => blk00000003_sig000001c9
);
blk00000003_blk0000011b : XORCY
port map (
CI => blk00000003_sig000001c4,
LI => blk00000003_sig000001c5,
O => blk00000003_sig000001c6
);
blk00000003_blk0000011a : XORCY
port map (
CI => blk00000003_sig000001c1,
LI => blk00000003_sig000001c2,
O => blk00000003_sig000001c3
);
blk00000003_blk00000119 : XORCY
port map (
CI => blk00000003_sig000001be,
LI => blk00000003_sig000001bf,
O => blk00000003_sig000001c0
);
blk00000003_blk00000118 : XORCY
port map (
CI => blk00000003_sig000001bb,
LI => blk00000003_sig000001bc,
O => blk00000003_sig000001bd
);
blk00000003_blk00000117 : XORCY
port map (
CI => blk00000003_sig000001b8,
LI => blk00000003_sig000001b9,
O => blk00000003_sig000001ba
);
blk00000003_blk00000116 : XORCY
port map (
CI => blk00000003_sig000001b5,
LI => blk00000003_sig000001b6,
O => blk00000003_sig000001b7
);
blk00000003_blk00000115 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001b0,
Q => blk00000003_sig000001b4
);
blk00000003_blk00000114 : MUXCY
port map (
CI => blk00000003_sig000001b1,
DI => blk00000003_sig00000062,
S => blk00000003_sig000001b2,
O => blk00000003_sig000001a5
);
blk00000003_blk00000113 : XORCY
port map (
CI => blk00000003_sig000001b1,
LI => blk00000003_sig000001b2,
O => blk00000003_sig000001b3
);
blk00000003_blk00000112 : MUXCY
port map (
CI => blk00000003_sig00000190,
DI => blk00000003_sig000001af,
S => blk00000003_sig00000191,
O => blk00000003_sig000001b0
);
blk00000003_blk00000111 : MUXCY
port map (
CI => blk00000003_sig000001a5,
DI => blk00000003_sig000001ae,
S => blk00000003_sig000001a6,
O => blk00000003_sig000001a2
);
blk00000003_blk00000110 : MUXCY
port map (
CI => blk00000003_sig000001a2,
DI => blk00000003_sig000001ad,
S => blk00000003_sig000001a3,
O => blk00000003_sig0000019f
);
blk00000003_blk0000010f : MUXCY
port map (
CI => blk00000003_sig0000019f,
DI => blk00000003_sig000001ac,
S => blk00000003_sig000001a0,
O => blk00000003_sig0000019c
);
blk00000003_blk0000010e : MUXCY
port map (
CI => blk00000003_sig0000019c,
DI => blk00000003_sig000001ab,
S => blk00000003_sig0000019d,
O => blk00000003_sig00000199
);
blk00000003_blk0000010d : MUXCY
port map (
CI => blk00000003_sig00000199,
DI => blk00000003_sig000001aa,
S => blk00000003_sig0000019a,
O => blk00000003_sig00000196
);
blk00000003_blk0000010c : MUXCY
port map (
CI => blk00000003_sig00000196,
DI => blk00000003_sig000001a9,
S => blk00000003_sig00000197,
O => blk00000003_sig00000193
);
blk00000003_blk0000010b : MUXCY
port map (
CI => blk00000003_sig00000193,
DI => blk00000003_sig000001a8,
S => blk00000003_sig00000194,
O => blk00000003_sig00000190
);
blk00000003_blk0000010a : XORCY
port map (
CI => blk00000003_sig000001a5,
LI => blk00000003_sig000001a6,
O => blk00000003_sig000001a7
);
blk00000003_blk00000109 : XORCY
port map (
CI => blk00000003_sig000001a2,
LI => blk00000003_sig000001a3,
O => blk00000003_sig000001a4
);
blk00000003_blk00000108 : XORCY
port map (
CI => blk00000003_sig0000019f,
LI => blk00000003_sig000001a0,
O => blk00000003_sig000001a1
);
blk00000003_blk00000107 : XORCY
port map (
CI => blk00000003_sig0000019c,
LI => blk00000003_sig0000019d,
O => blk00000003_sig0000019e
);
blk00000003_blk00000106 : XORCY
port map (
CI => blk00000003_sig00000199,
LI => blk00000003_sig0000019a,
O => blk00000003_sig0000019b
);
blk00000003_blk00000105 : XORCY
port map (
CI => blk00000003_sig00000196,
LI => blk00000003_sig00000197,
O => blk00000003_sig00000198
);
blk00000003_blk00000104 : XORCY
port map (
CI => blk00000003_sig00000193,
LI => blk00000003_sig00000194,
O => blk00000003_sig00000195
);
blk00000003_blk00000103 : XORCY
port map (
CI => blk00000003_sig00000190,
LI => blk00000003_sig00000191,
O => blk00000003_sig00000192
);
blk00000003_blk00000102 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000018b,
Q => blk00000003_sig0000018f
);
blk00000003_blk00000101 : MUXCY
port map (
CI => blk00000003_sig0000018c,
DI => blk00000003_sig0000006b,
S => blk00000003_sig0000018d,
O => blk00000003_sig00000180
);
blk00000003_blk00000100 : XORCY
port map (
CI => blk00000003_sig0000018c,
LI => blk00000003_sig0000018d,
O => blk00000003_sig0000018e
);
blk00000003_blk000000ff : MUXCY
port map (
CI => blk00000003_sig0000016b,
DI => blk00000003_sig0000018a,
S => blk00000003_sig0000016c,
O => blk00000003_sig0000018b
);
blk00000003_blk000000fe : MUXCY
port map (
CI => blk00000003_sig00000180,
DI => blk00000003_sig00000189,
S => blk00000003_sig00000181,
O => blk00000003_sig0000017d
);
blk00000003_blk000000fd : MUXCY
port map (
CI => blk00000003_sig0000017d,
DI => blk00000003_sig00000188,
S => blk00000003_sig0000017e,
O => blk00000003_sig0000017a
);
blk00000003_blk000000fc : MUXCY
port map (
CI => blk00000003_sig0000017a,
DI => blk00000003_sig00000187,
S => blk00000003_sig0000017b,
O => blk00000003_sig00000177
);
blk00000003_blk000000fb : MUXCY
port map (
CI => blk00000003_sig00000177,
DI => blk00000003_sig00000186,
S => blk00000003_sig00000178,
O => blk00000003_sig00000174
);
blk00000003_blk000000fa : MUXCY
port map (
CI => blk00000003_sig00000174,
DI => blk00000003_sig00000185,
S => blk00000003_sig00000175,
O => blk00000003_sig00000171
);
blk00000003_blk000000f9 : MUXCY
port map (
CI => blk00000003_sig00000171,
DI => blk00000003_sig00000184,
S => blk00000003_sig00000172,
O => blk00000003_sig0000016e
);
blk00000003_blk000000f8 : MUXCY
port map (
CI => blk00000003_sig0000016e,
DI => blk00000003_sig00000183,
S => blk00000003_sig0000016f,
O => blk00000003_sig0000016b
);
blk00000003_blk000000f7 : XORCY
port map (
CI => blk00000003_sig00000180,
LI => blk00000003_sig00000181,
O => blk00000003_sig00000182
);
blk00000003_blk000000f6 : XORCY
port map (
CI => blk00000003_sig0000017d,
LI => blk00000003_sig0000017e,
O => blk00000003_sig0000017f
);
blk00000003_blk000000f5 : XORCY
port map (
CI => blk00000003_sig0000017a,
LI => blk00000003_sig0000017b,
O => blk00000003_sig0000017c
);
blk00000003_blk000000f4 : XORCY
port map (
CI => blk00000003_sig00000177,
LI => blk00000003_sig00000178,
O => blk00000003_sig00000179
);
blk00000003_blk000000f3 : XORCY
port map (
CI => blk00000003_sig00000174,
LI => blk00000003_sig00000175,
O => blk00000003_sig00000176
);
blk00000003_blk000000f2 : XORCY
port map (
CI => blk00000003_sig00000171,
LI => blk00000003_sig00000172,
O => blk00000003_sig00000173
);
blk00000003_blk000000f1 : XORCY
port map (
CI => blk00000003_sig0000016e,
LI => blk00000003_sig0000016f,
O => blk00000003_sig00000170
);
blk00000003_blk000000f0 : XORCY
port map (
CI => blk00000003_sig0000016b,
LI => blk00000003_sig0000016c,
O => blk00000003_sig0000016d
);
blk00000003_blk000000ef : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000166,
Q => blk00000003_sig0000016a
);
blk00000003_blk000000ee : MUXCY
port map (
CI => blk00000003_sig00000167,
DI => blk00000003_sig00000074,
S => blk00000003_sig00000168,
O => blk00000003_sig0000015b
);
blk00000003_blk000000ed : XORCY
port map (
CI => blk00000003_sig00000167,
LI => blk00000003_sig00000168,
O => blk00000003_sig00000169
);
blk00000003_blk000000ec : MUXCY
port map (
CI => blk00000003_sig00000146,
DI => blk00000003_sig00000165,
S => blk00000003_sig00000147,
O => blk00000003_sig00000166
);
blk00000003_blk000000eb : MUXCY
port map (
CI => blk00000003_sig0000015b,
DI => blk00000003_sig00000164,
S => blk00000003_sig0000015c,
O => blk00000003_sig00000158
);
blk00000003_blk000000ea : MUXCY
port map (
CI => blk00000003_sig00000158,
DI => blk00000003_sig00000163,
S => blk00000003_sig00000159,
O => blk00000003_sig00000155
);
blk00000003_blk000000e9 : MUXCY
port map (
CI => blk00000003_sig00000155,
DI => blk00000003_sig00000162,
S => blk00000003_sig00000156,
O => blk00000003_sig00000152
);
blk00000003_blk000000e8 : MUXCY
port map (
CI => blk00000003_sig00000152,
DI => blk00000003_sig00000161,
S => blk00000003_sig00000153,
O => blk00000003_sig0000014f
);
blk00000003_blk000000e7 : MUXCY
port map (
CI => blk00000003_sig0000014f,
DI => blk00000003_sig00000160,
S => blk00000003_sig00000150,
O => blk00000003_sig0000014c
);
blk00000003_blk000000e6 : MUXCY
port map (
CI => blk00000003_sig0000014c,
DI => blk00000003_sig0000015f,
S => blk00000003_sig0000014d,
O => blk00000003_sig00000149
);
blk00000003_blk000000e5 : MUXCY
port map (
CI => blk00000003_sig00000149,
DI => blk00000003_sig0000015e,
S => blk00000003_sig0000014a,
O => blk00000003_sig00000146
);
blk00000003_blk000000e4 : XORCY
port map (
CI => blk00000003_sig0000015b,
LI => blk00000003_sig0000015c,
O => blk00000003_sig0000015d
);
blk00000003_blk000000e3 : XORCY
port map (
CI => blk00000003_sig00000158,
LI => blk00000003_sig00000159,
O => blk00000003_sig0000015a
);
blk00000003_blk000000e2 : XORCY
port map (
CI => blk00000003_sig00000155,
LI => blk00000003_sig00000156,
O => blk00000003_sig00000157
);
blk00000003_blk000000e1 : XORCY
port map (
CI => blk00000003_sig00000152,
LI => blk00000003_sig00000153,
O => blk00000003_sig00000154
);
blk00000003_blk000000e0 : XORCY
port map (
CI => blk00000003_sig0000014f,
LI => blk00000003_sig00000150,
O => blk00000003_sig00000151
);
blk00000003_blk000000df : XORCY
port map (
CI => blk00000003_sig0000014c,
LI => blk00000003_sig0000014d,
O => blk00000003_sig0000014e
);
blk00000003_blk000000de : XORCY
port map (
CI => blk00000003_sig00000149,
LI => blk00000003_sig0000014a,
O => blk00000003_sig0000014b
);
blk00000003_blk000000dd : XORCY
port map (
CI => blk00000003_sig00000146,
LI => blk00000003_sig00000147,
O => blk00000003_sig00000148
);
blk00000003_blk000000dc : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000141,
Q => blk00000003_sig00000145
);
blk00000003_blk000000db : MUXCY
port map (
CI => blk00000003_sig00000142,
DI => blk00000003_sig0000007d,
S => blk00000003_sig00000143,
O => blk00000003_sig00000136
);
blk00000003_blk000000da : XORCY
port map (
CI => blk00000003_sig00000142,
LI => blk00000003_sig00000143,
O => blk00000003_sig00000144
);
blk00000003_blk000000d9 : MUXCY
port map (
CI => blk00000003_sig00000121,
DI => blk00000003_sig00000140,
S => blk00000003_sig00000122,
O => blk00000003_sig00000141
);
blk00000003_blk000000d8 : MUXCY
port map (
CI => blk00000003_sig00000136,
DI => blk00000003_sig0000013f,
S => blk00000003_sig00000137,
O => blk00000003_sig00000133
);
blk00000003_blk000000d7 : MUXCY
port map (
CI => blk00000003_sig00000133,
DI => blk00000003_sig0000013e,
S => blk00000003_sig00000134,
O => blk00000003_sig00000130
);
blk00000003_blk000000d6 : MUXCY
port map (
CI => blk00000003_sig00000130,
DI => blk00000003_sig0000013d,
S => blk00000003_sig00000131,
O => blk00000003_sig0000012d
);
blk00000003_blk000000d5 : MUXCY
port map (
CI => blk00000003_sig0000012d,
DI => blk00000003_sig0000013c,
S => blk00000003_sig0000012e,
O => blk00000003_sig0000012a
);
blk00000003_blk000000d4 : MUXCY
port map (
CI => blk00000003_sig0000012a,
DI => blk00000003_sig0000013b,
S => blk00000003_sig0000012b,
O => blk00000003_sig00000127
);
blk00000003_blk000000d3 : MUXCY
port map (
CI => blk00000003_sig00000127,
DI => blk00000003_sig0000013a,
S => blk00000003_sig00000128,
O => blk00000003_sig00000124
);
blk00000003_blk000000d2 : MUXCY
port map (
CI => blk00000003_sig00000124,
DI => blk00000003_sig00000139,
S => blk00000003_sig00000125,
O => blk00000003_sig00000121
);
blk00000003_blk000000d1 : XORCY
port map (
CI => blk00000003_sig00000136,
LI => blk00000003_sig00000137,
O => blk00000003_sig00000138
);
blk00000003_blk000000d0 : XORCY
port map (
CI => blk00000003_sig00000133,
LI => blk00000003_sig00000134,
O => blk00000003_sig00000135
);
blk00000003_blk000000cf : XORCY
port map (
CI => blk00000003_sig00000130,
LI => blk00000003_sig00000131,
O => blk00000003_sig00000132
);
blk00000003_blk000000ce : XORCY
port map (
CI => blk00000003_sig0000012d,
LI => blk00000003_sig0000012e,
O => blk00000003_sig0000012f
);
blk00000003_blk000000cd : XORCY
port map (
CI => blk00000003_sig0000012a,
LI => blk00000003_sig0000012b,
O => blk00000003_sig0000012c
);
blk00000003_blk000000cc : XORCY
port map (
CI => blk00000003_sig00000127,
LI => blk00000003_sig00000128,
O => blk00000003_sig00000129
);
blk00000003_blk000000cb : XORCY
port map (
CI => blk00000003_sig00000124,
LI => blk00000003_sig00000125,
O => blk00000003_sig00000126
);
blk00000003_blk000000ca : XORCY
port map (
CI => blk00000003_sig00000121,
LI => blk00000003_sig00000122,
O => blk00000003_sig00000123
);
blk00000003_blk000000c9 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000011c,
Q => blk00000003_sig00000120
);
blk00000003_blk000000c8 : MUXCY
port map (
CI => blk00000003_sig0000011d,
DI => blk00000003_sig00000086,
S => blk00000003_sig0000011e,
O => blk00000003_sig00000111
);
blk00000003_blk000000c7 : XORCY
port map (
CI => blk00000003_sig0000011d,
LI => blk00000003_sig0000011e,
O => blk00000003_sig0000011f
);
blk00000003_blk000000c6 : MUXCY
port map (
CI => blk00000003_sig000000fc,
DI => blk00000003_sig0000011b,
S => blk00000003_sig000000fd,
O => blk00000003_sig0000011c
);
blk00000003_blk000000c5 : MUXCY
port map (
CI => blk00000003_sig00000111,
DI => blk00000003_sig0000011a,
S => blk00000003_sig00000112,
O => blk00000003_sig0000010e
);
blk00000003_blk000000c4 : MUXCY
port map (
CI => blk00000003_sig0000010e,
DI => blk00000003_sig00000119,
S => blk00000003_sig0000010f,
O => blk00000003_sig0000010b
);
blk00000003_blk000000c3 : MUXCY
port map (
CI => blk00000003_sig0000010b,
DI => blk00000003_sig00000118,
S => blk00000003_sig0000010c,
O => blk00000003_sig00000108
);
blk00000003_blk000000c2 : MUXCY
port map (
CI => blk00000003_sig00000108,
DI => blk00000003_sig00000117,
S => blk00000003_sig00000109,
O => blk00000003_sig00000105
);
blk00000003_blk000000c1 : MUXCY
port map (
CI => blk00000003_sig00000105,
DI => blk00000003_sig00000116,
S => blk00000003_sig00000106,
O => blk00000003_sig00000102
);
blk00000003_blk000000c0 : MUXCY
port map (
CI => blk00000003_sig00000102,
DI => blk00000003_sig00000115,
S => blk00000003_sig00000103,
O => blk00000003_sig000000ff
);
blk00000003_blk000000bf : MUXCY
port map (
CI => blk00000003_sig000000ff,
DI => blk00000003_sig00000114,
S => blk00000003_sig00000100,
O => blk00000003_sig000000fc
);
blk00000003_blk000000be : XORCY
port map (
CI => blk00000003_sig00000111,
LI => blk00000003_sig00000112,
O => blk00000003_sig00000113
);
blk00000003_blk000000bd : XORCY
port map (
CI => blk00000003_sig0000010e,
LI => blk00000003_sig0000010f,
O => blk00000003_sig00000110
);
blk00000003_blk000000bc : XORCY
port map (
CI => blk00000003_sig0000010b,
LI => blk00000003_sig0000010c,
O => blk00000003_sig0000010d
);
blk00000003_blk000000bb : XORCY
port map (
CI => blk00000003_sig00000108,
LI => blk00000003_sig00000109,
O => blk00000003_sig0000010a
);
blk00000003_blk000000ba : XORCY
port map (
CI => blk00000003_sig00000105,
LI => blk00000003_sig00000106,
O => blk00000003_sig00000107
);
blk00000003_blk000000b9 : XORCY
port map (
CI => blk00000003_sig00000102,
LI => blk00000003_sig00000103,
O => blk00000003_sig00000104
);
blk00000003_blk000000b8 : XORCY
port map (
CI => blk00000003_sig000000ff,
LI => blk00000003_sig00000100,
O => blk00000003_sig00000101
);
blk00000003_blk000000b7 : XORCY
port map (
CI => blk00000003_sig000000fc,
LI => blk00000003_sig000000fd,
O => blk00000003_sig000000fe
);
blk00000003_blk000000b6 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000f8,
Q => blk00000003_sig000000fb
);
blk00000003_blk000000b5 : MUXCY
port map (
CI => NlwRenamedSig_OI_rfd,
DI => blk00000003_sig00000098,
S => blk00000003_sig000000f9,
O => blk00000003_sig000000f5
);
blk00000003_blk000000b4 : XORCY
port map (
CI => NlwRenamedSig_OI_rfd,
LI => blk00000003_sig000000f9,
O => blk00000003_sig000000fa
);
blk00000003_blk000000b3 : MUXCY
port map (
CI => blk00000003_sig000000e1,
DI => blk00000003_sig00000022,
S => NlwRenamedSig_OI_rfd,
O => blk00000003_sig000000f8
);
blk00000003_blk000000b2 : MUXCY
port map (
CI => blk00000003_sig000000f5,
DI => blk00000003_sig00000022,
S => blk00000003_sig000000f6,
O => blk00000003_sig000000f2
);
blk00000003_blk000000b1 : MUXCY
port map (
CI => blk00000003_sig000000f2,
DI => blk00000003_sig00000022,
S => blk00000003_sig000000f3,
O => blk00000003_sig000000ef
);
blk00000003_blk000000b0 : MUXCY
port map (
CI => blk00000003_sig000000ef,
DI => blk00000003_sig00000022,
S => blk00000003_sig000000f0,
O => blk00000003_sig000000ec
);
blk00000003_blk000000af : MUXCY
port map (
CI => blk00000003_sig000000ec,
DI => blk00000003_sig00000022,
S => blk00000003_sig000000ed,
O => blk00000003_sig000000e9
);
blk00000003_blk000000ae : MUXCY
port map (
CI => blk00000003_sig000000e9,
DI => blk00000003_sig00000022,
S => blk00000003_sig000000ea,
O => blk00000003_sig000000e6
);
blk00000003_blk000000ad : MUXCY
port map (
CI => blk00000003_sig000000e6,
DI => blk00000003_sig00000022,
S => blk00000003_sig000000e7,
O => blk00000003_sig000000e3
);
blk00000003_blk000000ac : MUXCY
port map (
CI => blk00000003_sig000000e3,
DI => blk00000003_sig00000022,
S => blk00000003_sig000000e4,
O => blk00000003_sig000000e1
);
blk00000003_blk000000ab : XORCY
port map (
CI => blk00000003_sig000000f5,
LI => blk00000003_sig000000f6,
O => blk00000003_sig000000f7
);
blk00000003_blk000000aa : XORCY
port map (
CI => blk00000003_sig000000f2,
LI => blk00000003_sig000000f3,
O => blk00000003_sig000000f4
);
blk00000003_blk000000a9 : XORCY
port map (
CI => blk00000003_sig000000ef,
LI => blk00000003_sig000000f0,
O => blk00000003_sig000000f1
);
blk00000003_blk000000a8 : XORCY
port map (
CI => blk00000003_sig000000ec,
LI => blk00000003_sig000000ed,
O => blk00000003_sig000000ee
);
blk00000003_blk000000a7 : XORCY
port map (
CI => blk00000003_sig000000e9,
LI => blk00000003_sig000000ea,
O => blk00000003_sig000000eb
);
blk00000003_blk000000a6 : XORCY
port map (
CI => blk00000003_sig000000e6,
LI => blk00000003_sig000000e7,
O => blk00000003_sig000000e8
);
blk00000003_blk000000a5 : XORCY
port map (
CI => blk00000003_sig000000e3,
LI => blk00000003_sig000000e4,
O => blk00000003_sig000000e5
);
blk00000003_blk000000a4 : XORCY
port map (
CI => blk00000003_sig000000e1,
LI => NlwRenamedSig_OI_rfd,
O => blk00000003_sig000000e2
);
blk00000003_blk000000a3 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000003f,
Q => blk00000003_sig000000df
);
blk00000003_blk000000a2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000003d,
Q => blk00000003_sig000000de
);
blk00000003_blk000000a1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000003b,
Q => blk00000003_sig000000dc
);
blk00000003_blk000000a0 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000039,
Q => blk00000003_sig000000db
);
blk00000003_blk0000009f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000037,
Q => blk00000003_sig000000da
);
blk00000003_blk0000009e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000035,
Q => blk00000003_sig000000d9
);
blk00000003_blk0000009d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000e0,
Q => blk00000003_sig000000d8
);
blk00000003_blk0000009c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000df,
Q => blk00000003_sig000000d7
);
blk00000003_blk0000009b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000de,
Q => blk00000003_sig000000d6
);
blk00000003_blk0000009a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000dd,
Q => blk00000003_sig000000d5
);
blk00000003_blk00000099 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000dc,
Q => blk00000003_sig000000d4
);
blk00000003_blk00000098 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000db,
Q => blk00000003_sig000000d3
);
blk00000003_blk00000097 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000da,
Q => blk00000003_sig000000d2
);
blk00000003_blk00000096 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000d9,
Q => blk00000003_sig000000d1
);
blk00000003_blk00000095 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000d8,
Q => blk00000003_sig000000d0
);
blk00000003_blk00000094 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000d7,
Q => blk00000003_sig000000cf
);
blk00000003_blk00000093 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000d6,
Q => blk00000003_sig000000ce
);
blk00000003_blk00000092 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000d5,
Q => blk00000003_sig000000cd
);
blk00000003_blk00000091 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000d4,
Q => blk00000003_sig000000cc
);
blk00000003_blk00000090 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000d3,
Q => blk00000003_sig000000cb
);
blk00000003_blk0000008f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000d2,
Q => blk00000003_sig000000ca
);
blk00000003_blk0000008e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000d1,
Q => blk00000003_sig000000c9
);
blk00000003_blk0000008d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000d0,
Q => blk00000003_sig000000c8
);
blk00000003_blk0000008c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000cf,
Q => blk00000003_sig000000c7
);
blk00000003_blk0000008b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000ce,
Q => blk00000003_sig000000c6
);
blk00000003_blk0000008a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000cd,
Q => blk00000003_sig000000c5
);
blk00000003_blk00000089 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000cc,
Q => blk00000003_sig000000c4
);
blk00000003_blk00000088 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000cb,
Q => blk00000003_sig000000c3
);
blk00000003_blk00000087 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000ca,
Q => blk00000003_sig000000c2
);
blk00000003_blk00000086 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000c9,
Q => blk00000003_sig000000c1
);
blk00000003_blk00000085 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000c8,
Q => blk00000003_sig000000c0
);
blk00000003_blk00000084 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000c7,
Q => blk00000003_sig000000bf
);
blk00000003_blk00000083 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000c6,
Q => blk00000003_sig000000be
);
blk00000003_blk00000082 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000c5,
Q => blk00000003_sig000000bd
);
blk00000003_blk00000081 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000c4,
Q => blk00000003_sig000000bc
);
blk00000003_blk00000080 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000c3,
Q => blk00000003_sig000000bb
);
blk00000003_blk0000007f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000c2,
Q => blk00000003_sig000000ba
);
blk00000003_blk0000007e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000c1,
Q => blk00000003_sig000000b9
);
blk00000003_blk0000007d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000c0,
Q => blk00000003_sig000000b8
);
blk00000003_blk0000007c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000bf,
Q => blk00000003_sig000000b7
);
blk00000003_blk0000007b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000be,
Q => blk00000003_sig000000b6
);
blk00000003_blk0000007a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000bd,
Q => blk00000003_sig000000b5
);
blk00000003_blk00000079 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000bc,
Q => blk00000003_sig000000b4
);
blk00000003_blk00000078 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000bb,
Q => blk00000003_sig000000b3
);
blk00000003_blk00000077 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000ba,
Q => blk00000003_sig000000b2
);
blk00000003_blk00000076 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000b9,
Q => blk00000003_sig000000b1
);
blk00000003_blk00000075 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000b8,
Q => blk00000003_sig000000b0
);
blk00000003_blk00000074 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000b7,
Q => blk00000003_sig000000af
);
blk00000003_blk00000073 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000b6,
Q => blk00000003_sig000000ae
);
blk00000003_blk00000072 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000b5,
Q => blk00000003_sig000000ad
);
blk00000003_blk00000071 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000b4,
Q => blk00000003_sig000000ac
);
blk00000003_blk00000070 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000b3,
Q => blk00000003_sig000000ab
);
blk00000003_blk0000006f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000b2,
Q => blk00000003_sig000000aa
);
blk00000003_blk0000006e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000b1,
Q => blk00000003_sig000000a9
);
blk00000003_blk0000006d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000b0,
Q => blk00000003_sig000000a7
);
blk00000003_blk0000006c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000af,
Q => blk00000003_sig000000a5
);
blk00000003_blk0000006b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000ae,
Q => blk00000003_sig000000a3
);
blk00000003_blk0000006a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000ad,
Q => blk00000003_sig000000a1
);
blk00000003_blk00000069 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000ac,
Q => blk00000003_sig0000009f
);
blk00000003_blk00000068 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000ab,
Q => blk00000003_sig0000009d
);
blk00000003_blk00000067 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000aa,
Q => blk00000003_sig0000009b
);
blk00000003_blk00000066 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000a9,
Q => blk00000003_sig00000099
);
blk00000003_blk00000065 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000a7,
Q => blk00000003_sig000000a8
);
blk00000003_blk00000064 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000a5,
Q => blk00000003_sig000000a6
);
blk00000003_blk00000063 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000a3,
Q => blk00000003_sig000000a4
);
blk00000003_blk00000062 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000a1,
Q => blk00000003_sig000000a2
);
blk00000003_blk00000061 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000009f,
Q => blk00000003_sig000000a0
);
blk00000003_blk00000060 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000009d,
Q => blk00000003_sig0000009e
);
blk00000003_blk0000005f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000009b,
Q => blk00000003_sig0000009c
);
blk00000003_blk0000005e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000099,
Q => blk00000003_sig0000009a
);
blk00000003_blk0000005d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000033,
Q => blk00000003_sig00000080
);
blk00000003_blk0000005c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000031,
Q => blk00000003_sig00000081
);
blk00000003_blk0000005b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000002f,
Q => blk00000003_sig00000083
);
blk00000003_blk0000005a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000002d,
Q => blk00000003_sig00000084
);
blk00000003_blk00000059 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000002b,
Q => blk00000003_sig00000085
);
blk00000003_blk00000058 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000029,
Q => blk00000003_sig00000098
);
blk00000003_blk00000057 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000096,
Q => blk00000003_sig00000097
);
blk00000003_blk00000056 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000094,
Q => blk00000003_sig00000095
);
blk00000003_blk00000055 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000092,
Q => blk00000003_sig00000093
);
blk00000003_blk00000054 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000090,
Q => blk00000003_sig00000091
);
blk00000003_blk00000053 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000008e,
Q => blk00000003_sig0000008f
);
blk00000003_blk00000052 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000008c,
Q => blk00000003_sig0000008d
);
blk00000003_blk00000051 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000008a,
Q => blk00000003_sig0000008b
);
blk00000003_blk00000050 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000088,
Q => blk00000003_sig00000089
);
blk00000003_blk0000004f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000057,
Q => blk00000003_sig00000087
);
blk00000003_blk0000004e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000085,
Q => blk00000003_sig00000086
);
blk00000003_blk0000004d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000084,
Q => blk00000003_sig0000007c
);
blk00000003_blk0000004c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000083,
Q => blk00000003_sig0000007b
);
blk00000003_blk0000004b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000082,
Q => blk00000003_sig0000007a
);
blk00000003_blk0000004a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000081,
Q => blk00000003_sig00000079
);
blk00000003_blk00000049 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000080,
Q => blk00000003_sig00000078
);
blk00000003_blk00000048 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000007f,
Q => blk00000003_sig00000077
);
blk00000003_blk00000047 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000007e,
Q => blk00000003_sig00000076
);
blk00000003_blk00000046 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000007c,
Q => blk00000003_sig0000007d
);
blk00000003_blk00000045 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000007b,
Q => blk00000003_sig00000073
);
blk00000003_blk00000044 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000007a,
Q => blk00000003_sig00000072
);
blk00000003_blk00000043 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000079,
Q => blk00000003_sig00000071
);
blk00000003_blk00000042 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000078,
Q => blk00000003_sig00000070
);
blk00000003_blk00000041 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000077,
Q => blk00000003_sig0000006f
);
blk00000003_blk00000040 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000076,
Q => blk00000003_sig0000006e
);
blk00000003_blk0000003f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000075,
Q => blk00000003_sig0000006d
);
blk00000003_blk0000003e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000073,
Q => blk00000003_sig00000074
);
blk00000003_blk0000003d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000072,
Q => blk00000003_sig0000006a
);
blk00000003_blk0000003c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000071,
Q => blk00000003_sig00000069
);
blk00000003_blk0000003b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000070,
Q => blk00000003_sig00000068
);
blk00000003_blk0000003a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000006f,
Q => blk00000003_sig00000067
);
blk00000003_blk00000039 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000006e,
Q => blk00000003_sig00000066
);
blk00000003_blk00000038 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000006d,
Q => blk00000003_sig00000065
);
blk00000003_blk00000037 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000006c,
Q => blk00000003_sig00000064
);
blk00000003_blk00000036 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000006a,
Q => blk00000003_sig0000006b
);
blk00000003_blk00000035 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000069,
Q => blk00000003_sig00000061
);
blk00000003_blk00000034 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000068,
Q => blk00000003_sig00000060
);
blk00000003_blk00000033 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000067,
Q => blk00000003_sig0000005f
);
blk00000003_blk00000032 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000066,
Q => blk00000003_sig0000005e
);
blk00000003_blk00000031 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000065,
Q => blk00000003_sig0000005d
);
blk00000003_blk00000030 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000064,
Q => blk00000003_sig0000005c
);
blk00000003_blk0000002f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000063,
Q => blk00000003_sig0000005b
);
blk00000003_blk0000002e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000061,
Q => blk00000003_sig00000062
);
blk00000003_blk0000002d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000060,
Q => blk00000003_sig00000058
);
blk00000003_blk0000002c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000005f,
Q => blk00000003_sig00000056
);
blk00000003_blk0000002b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000005e,
Q => blk00000003_sig00000055
);
blk00000003_blk0000002a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000005d,
Q => blk00000003_sig00000054
);
blk00000003_blk00000029 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000005c,
Q => blk00000003_sig00000053
);
blk00000003_blk00000028 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000005b,
Q => blk00000003_sig00000052
);
blk00000003_blk00000027 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000005a,
Q => blk00000003_sig00000051
);
blk00000003_blk00000026 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000058,
Q => blk00000003_sig00000059
);
blk00000003_blk00000025 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000056,
Q => blk00000003_sig00000057
);
blk00000003_blk00000024 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000055,
Q => blk00000003_sig0000004e
);
blk00000003_blk00000023 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000054,
Q => blk00000003_sig0000004c
);
blk00000003_blk00000022 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000053,
Q => blk00000003_sig0000004a
);
blk00000003_blk00000021 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000052,
Q => blk00000003_sig00000048
);
blk00000003_blk00000020 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000051,
Q => blk00000003_sig00000046
);
blk00000003_blk0000001f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000050,
Q => blk00000003_sig00000044
);
blk00000003_blk0000001e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000004e,
Q => blk00000003_sig0000004f
);
blk00000003_blk0000001d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000004c,
Q => blk00000003_sig0000004d
);
blk00000003_blk0000001c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000004a,
Q => blk00000003_sig0000004b
);
blk00000003_blk0000001b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000048,
Q => blk00000003_sig00000049
);
blk00000003_blk0000001a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000046,
Q => blk00000003_sig00000047
);
blk00000003_blk00000019 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000044,
Q => blk00000003_sig00000045
);
blk00000003_blk00000018 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000042,
Q => blk00000003_sig00000043
);
blk00000003_blk00000017 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000027,
Q => blk00000003_sig00000041
);
blk00000003_blk00000016 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000026,
Q => blk00000003_sig00000040
);
blk00000003_blk00000015 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000003e,
Q => blk00000003_sig0000003f
);
blk00000003_blk00000014 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000003c,
Q => blk00000003_sig0000003d
);
blk00000003_blk00000013 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000003a,
Q => blk00000003_sig0000003b
);
blk00000003_blk00000012 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000038,
Q => blk00000003_sig00000039
);
blk00000003_blk00000011 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000036,
Q => blk00000003_sig00000037
);
blk00000003_blk00000010 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000034,
Q => blk00000003_sig00000035
);
blk00000003_blk0000000f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000032,
Q => blk00000003_sig00000033
);
blk00000003_blk0000000e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000030,
Q => blk00000003_sig00000031
);
blk00000003_blk0000000d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000002e,
Q => blk00000003_sig0000002f
);
blk00000003_blk0000000c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000002c,
Q => blk00000003_sig0000002d
);
blk00000003_blk0000000b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000002a,
Q => blk00000003_sig0000002b
);
blk00000003_blk0000000a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000028,
Q => blk00000003_sig00000029
);
blk00000003_blk00000009 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000025,
Q => blk00000003_sig00000027
);
blk00000003_blk00000008 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000024,
Q => blk00000003_sig00000026
);
blk00000003_blk00000007 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => divisor_1(7),
Q => blk00000003_sig00000025
);
blk00000003_blk00000006 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => dividend_0(7),
Q => blk00000003_sig00000024
);
blk00000003_blk00000005 : VCC
port map (
P => NlwRenamedSig_OI_rfd
);
blk00000003_blk00000004 : GND
port map (
G => blk00000003_sig00000022
);
end STRUCTURE;
-- synthesis translate_on
| unlicense | d3901cdc6dbea9ad1b2e27edc2c9ccfa | 0.61277 | 3.542917 | false | false | false | false |
chastell/art-decomp | kiss/tma_hot.vhd | 1 | 6,480 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity tma_hot is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(5 downto 0)
);
end tma_hot;
architecture behaviour of tma_hot is
constant I0: std_logic_vector(19 downto 0) := "10000000000000000000";
constant T1: std_logic_vector(19 downto 0) := "01000000000000000000";
constant R1: std_logic_vector(19 downto 0) := "00100000000000000000";
constant T3: std_logic_vector(19 downto 0) := "00010000000000000000";
constant T9: std_logic_vector(19 downto 0) := "00001000000000000000";
constant T4: std_logic_vector(19 downto 0) := "00000100000000000000";
constant T5: std_logic_vector(19 downto 0) := "00000010000000000000";
constant T6: std_logic_vector(19 downto 0) := "00000001000000000000";
constant T7: std_logic_vector(19 downto 0) := "00000000100000000000";
constant T8: std_logic_vector(19 downto 0) := "00000000010000000000";
constant I2: std_logic_vector(19 downto 0) := "00000000001000000000";
constant T2: std_logic_vector(19 downto 0) := "00000000000100000000";
constant R2: std_logic_vector(19 downto 0) := "00000000000010000000";
constant I1: std_logic_vector(19 downto 0) := "00000000000001000000";
constant R3: std_logic_vector(19 downto 0) := "00000000000000100000";
constant R4: std_logic_vector(19 downto 0) := "00000000000000010000";
constant R6: std_logic_vector(19 downto 0) := "00000000000000001000";
constant R8: std_logic_vector(19 downto 0) := "00000000000000000100";
constant R5: std_logic_vector(19 downto 0) := "00000000000000000010";
constant R7: std_logic_vector(19 downto 0) := "00000000000000000001";
signal current_state, next_state: std_logic_vector(19 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--------------------"; output <= "------";
case current_state is
when I0 =>
if std_match(input, "11110--") then next_state <= T1; output <= "000000";
elsif std_match(input, "101-1--") then next_state <= R1; output <= "000000";
end if;
when T1 =>
if std_match(input, "1110---") then next_state <= T3; output <= "100000";
elsif std_match(input, "100----") then next_state <= T9; output <= "100000";
elsif std_match(input, "101--1-") then next_state <= T9; output <= "100000";
end if;
when T3 =>
if std_match(input, "111----") then next_state <= T4; output <= "110000";
elsif std_match(input, "100----") then next_state <= T9; output <= "110000";
elsif std_match(input, "101--1-") then next_state <= T9; output <= "110000";
end if;
when T4 =>
if std_match(input, "111----") then next_state <= T5; output <= "001000";
elsif std_match(input, "100----") then next_state <= T9; output <= "001000";
elsif std_match(input, "101--1-") then next_state <= T9; output <= "001000";
end if;
when T5 =>
if std_match(input, "111-0--") then next_state <= T6; output <= "101000";
elsif std_match(input, "100----") then next_state <= T9; output <= "101000";
elsif std_match(input, "101-1--") then next_state <= T9; output <= "101000";
end if;
when T6 =>
if std_match(input, "101-0--") then next_state <= T7; output <= "011000";
elsif std_match(input, "101-1--") then next_state <= T8; output <= "011000";
elsif std_match(input, "100----") then next_state <= T9; output <= "011000";
end if;
when T7 =>
if std_match(input, "10-----") then next_state <= I2; output <= "111000";
end if;
when T8 =>
if std_match(input, "10-----") then next_state <= I2; output <= "000100";
end if;
when T9 =>
if std_match(input, "101-0--") then next_state <= T2; output <= "100100";
elsif std_match(input, "100----") then next_state <= T2; output <= "100100";
end if;
when T2 =>
if std_match(input, "10-----") then next_state <= T8; output <= "010100";
end if;
when R1 =>
if std_match(input, "101-1--") then next_state <= R2; output <= "100010";
elsif std_match(input, "100----") then next_state <= I1; output <= "100010";
elsif std_match(input, "101-0--") then next_state <= I2; output <= "100010";
end if;
when R2 =>
if std_match(input, "101-1--") then next_state <= R3; output <= "010010";
elsif std_match(input, "100----") then next_state <= I1; output <= "010010";
elsif std_match(input, "101-0--") then next_state <= I2; output <= "010010";
end if;
when R3 =>
if std_match(input, "101-1--") then next_state <= R4; output <= "110010";
elsif std_match(input, "101-0-0") then next_state <= R6; output <= "110010";
elsif std_match(input, "101-0-1") then next_state <= R8; output <= "110010";
elsif std_match(input, "100----") then next_state <= R5; output <= "110010";
end if;
when R4 =>
if std_match(input, "101-0-0") then next_state <= R6; output <= "001010";
elsif std_match(input, "101-0-1") then next_state <= R8; output <= "001010";
elsif std_match(input, "100----") then next_state <= R5; output <= "001010";
end if;
when R6 =>
if std_match(input, "101-0--") then next_state <= R7; output <= "011010";
elsif std_match(input, "101-1--") then next_state <= R5; output <= "011010";
elsif std_match(input, "100----") then next_state <= R5; output <= "011010";
end if;
when R7 =>
if std_match(input, "10-----") then next_state <= I2; output <= "111010";
end if;
when R8 =>
if std_match(input, "10-----") then next_state <= R5; output <= "000110";
end if;
when R5 =>
if std_match(input, "101----") then next_state <= I2; output <= "100110";
elsif std_match(input, "100----") then next_state <= I1; output <= "100110";
end if;
when I2 =>
if std_match(input, "-------") then next_state <= I0; output <= "000001";
end if;
when I1 =>
if std_match(input, "111-0--") then next_state <= I0; output <= "010111";
end if;
when others => next_state <= "--------------------"; output <= "------";
end case;
end process;
end behaviour;
| agpl-3.0 | 3a40b3220b1258e27a9652be5d06fbef | 0.583796 | 3.476395 | false | false | false | false |
es17m014/vhdl-counter | src/tb/cntr_tb.vhd | 1 | 2,436 | -------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : cntr_tb.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: Testbench for the counter
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 19.11.2017 0.1 Martin Angermair init
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity cntr_tb is
end cntr_tb;
architecture sim of cntr_tb is
component cntr is
port (
clk_i : in std_logic;
reset_i : in std_logic;
cntrup_i : in std_logic;
cntrdown_i : in std_logic;
cntrreset_i : in std_logic;
cntrhold_i : in std_logic;
digits_o : out std_logic_vector(13 downto 0));
end component;
signal clk_i : std_logic;
signal reset_i : std_logic;
signal cntrup_i : std_logic;
signal cntrdown_i : std_logic;
signal cntrreset_i : std_logic;
signal cntrhold_i : std_logic;
signal digits_o : std_logic_vector(13 downto 0);
begin
-- Generate system clock 100 MHz
p_clk : process
begin
clk_i <= '0';
wait for 5 ns;
clk_i <= '1';
wait for 5 ns;
end process;
-- component under test
p_cntr : cntr
port map (
clk_i => clk_i,
reset_i => reset_i,
cntrup_i => cntrup_i,
cntrdown_i => cntrdown_i,
cntrreset_i => cntrreset_i,
cntrhold_i => cntrhold_i,
digits_o => digits_o);
-- do the simulation
p_sim : process
begin
-- init run with counting up
reset_i <= '0';
cntrup_i <= '1';
cntrdown_i <= '0';
cntrreset_i <= '0';
cntrhold_i <= '0';
wait for 5 ms;
-- set and unset reset
reset_i <= '1';
wait for 50 ns;
reset_i <= '0';
wait for 10 ms;
-- change counting direction
cntrup_i <= '0';
cntrdown_i <= '1';
wait for 30 ms;
-- test hold
cntrhold_i <= '1';
wait for 5 ms;
cntrhold_i <= '0';
wait for 200 ms;
end process;
end sim; | mit | 5279d03357cb1d9db0737b450c2dfb5c | 0.470443 | 3.93538 | false | false | false | false |
chastell/art-decomp | kiss/ex7_hot.vhd | 1 | 4,287 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex7_hot is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end ex7_hot;
architecture behaviour of ex7_hot is
constant s1: std_logic_vector(9 downto 0) := "1000000000";
constant s7: std_logic_vector(9 downto 0) := "0100000000";
constant s0: std_logic_vector(9 downto 0) := "0010000000";
constant s2: std_logic_vector(9 downto 0) := "0001000000";
constant s5: std_logic_vector(9 downto 0) := "0000100000";
constant s3: std_logic_vector(9 downto 0) := "0000010000";
constant s8: std_logic_vector(9 downto 0) := "0000001000";
constant s4: std_logic_vector(9 downto 0) := "0000000100";
constant s6: std_logic_vector(9 downto 0) := "0000000010";
constant s9: std_logic_vector(9 downto 0) := "0000000001";
signal current_state, next_state: std_logic_vector(9 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----------"; output <= "--";
case current_state is
when s1 =>
if std_match(input, "00") then next_state <= s7; output <= "11";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "00";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s2 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s2; output <= "--";
elsif std_match(input, "10") then next_state <= s5; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s3 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "11";
elsif std_match(input, "10") then next_state <= s8; output <= "--";
elsif std_match(input, "11") then next_state <= s5; output <= "--";
end if;
when s4 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "00";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s1; output <= "11";
end if;
when s5 =>
if std_match(input, "00") then next_state <= s7; output <= "00";
elsif std_match(input, "01") then next_state <= s5; output <= "--";
elsif std_match(input, "10") then next_state <= s2; output <= "11";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s6 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s9; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s2; output <= "00";
end if;
when s7 =>
if std_match(input, "00") then next_state <= s4; output <= "--";
elsif std_match(input, "01") then next_state <= s4; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "00";
elsif std_match(input, "11") then next_state <= s5; output <= "--";
end if;
when s8 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s3; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s4; output <= "11";
end if;
when s9 =>
if std_match(input, "00") then next_state <= s6; output <= "11";
elsif std_match(input, "01") then next_state <= s3; output <= "00";
elsif std_match(input, "10") then next_state <= s0; output <= "00";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when others => next_state <= "----------"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | 6e8622893b9d6d912aec244395c4b48b | 0.56543 | 3.336187 | false | false | false | false |
Diego-HR/HL-Object-Oriented | QAMDemodulator/src/solution1/syn/vhdl/qam_dem_top_mounstrito_cos_lut.vhd | 4 | 31,540 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity qam_dem_top_mounstrito_cos_lut_rom is
generic(
dwidth : integer := 15;
awidth : integer := 10;
mem_size : integer := 1024
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of qam_dem_top_mounstrito_cos_lut_rom is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
signal mem : mem_array := (
0 to 6=> "111111111111111", 7 to 8=> "111111111111110", 9 => "111111111111101",
10 => "111111111111100", 11 => "111111111111011", 12 => "111111111111010",
13 => "111111111111001", 14 => "111111111111000", 15 => "111111111110111",
16 => "111111111110110", 17 => "111111111110101", 18 => "111111111110100",
19 => "111111111110010", 20 => "111111111110001", 21 => "111111111101111",
22 => "111111111101101", 23 => "111111111101100", 24 => "111111111101010",
25 => "111111111101000", 26 => "111111111100110", 27 => "111111111100100",
28 => "111111111100010", 29 => "111111111100000", 30 => "111111111011101",
31 => "111111111011011", 32 => "111111111011001", 33 => "111111111010110",
34 => "111111111010011", 35 => "111111111010001", 36 => "111111111001110",
37 => "111111111001011", 38 => "111111111001000", 39 => "111111111000101",
40 => "111111111000010", 41 => "111111110111111", 42 => "111111110111100",
43 => "111111110111001", 44 => "111111110110101", 45 => "111111110110010",
46 => "111111110101110", 47 => "111111110101011", 48 => "111111110100111",
49 => "111111110100011", 50 => "111111110100000", 51 => "111111110011100",
52 => "111111110011000", 53 => "111111110010100", 54 => "111111110010000",
55 => "111111110001011", 56 => "111111110000111", 57 => "111111110000011",
58 => "111111101111110", 59 => "111111101111010", 60 => "111111101110101",
61 => "111111101110001", 62 => "111111101101100", 63 => "111111101100111",
64 => "111111101100010", 65 => "111111101011101", 66 => "111111101011000",
67 => "111111101010011", 68 => "111111101001110", 69 => "111111101001001",
70 => "111111101000011", 71 => "111111100111110", 72 => "111111100111000",
73 => "111111100110011", 74 => "111111100101101", 75 => "111111100100111",
76 => "111111100100010", 77 => "111111100011100", 78 => "111111100010110",
79 => "111111100010000", 80 => "111111100001010", 81 => "111111100000011",
82 => "111111011111101", 83 => "111111011110111", 84 => "111111011110000",
85 => "111111011101010", 86 => "111111011100011", 87 => "111111011011101",
88 => "111111011010110", 89 => "111111011001111", 90 => "111111011001000",
91 => "111111011000001", 92 => "111111010111010", 93 => "111111010110011",
94 => "111111010101100", 95 => "111111010100101", 96 => "111111010011101",
97 => "111111010010110", 98 => "111111010001110", 99 => "111111010000111",
100 => "111111001111111", 101 => "111111001111000", 102 => "111111001110000",
103 => "111111001101000", 104 => "111111001100000", 105 => "111111001011000",
106 => "111111001010000", 107 => "111111001001000", 108 => "111111000111111",
109 => "111111000110111", 110 => "111111000101111", 111 => "111111000100110",
112 => "111111000011110", 113 => "111111000010101", 114 => "111111000001100",
115 => "111111000000011", 116 => "111110111111011", 117 => "111110111110010",
118 => "111110111101001", 119 => "111110111100000", 120 => "111110111010110",
121 => "111110111001101", 122 => "111110111000100", 123 => "111110110111010",
124 => "111110110110001", 125 => "111110110100111", 126 => "111110110011110",
127 => "111110110010100", 128 => "111110110001010", 129 => "111110110000001",
130 => "111110101110111", 131 => "111110101101101", 132 => "111110101100011",
133 => "111110101011000", 134 => "111110101001110", 135 => "111110101000100",
136 => "111110100111001", 137 => "111110100101111", 138 => "111110100100101",
139 => "111110100011010", 140 => "111110100001111", 141 => "111110100000101",
142 => "111110011111010", 143 => "111110011101111", 144 => "111110011100100",
145 => "111110011011001", 146 => "111110011001110", 147 => "111110011000010",
148 => "111110010110111", 149 => "111110010101100", 150 => "111110010100000",
151 => "111110010010101", 152 => "111110010001001", 153 => "111110001111110",
154 => "111110001110010", 155 => "111110001100110", 156 => "111110001011010",
157 => "111110001001110", 158 => "111110001000010", 159 => "111110000110110",
160 => "111110000101010", 161 => "111110000011110", 162 => "111110000010001",
163 => "111110000000101", 164 => "111101111111001", 165 => "111101111101100",
166 => "111101111011111", 167 => "111101111010011", 168 => "111101111000110",
169 => "111101110111001", 170 => "111101110101100", 171 => "111101110011111",
172 => "111101110010010", 173 => "111101110000101", 174 => "111101101111000",
175 => "111101101101010", 176 => "111101101011101", 177 => "111101101010000",
178 => "111101101000010", 179 => "111101100110100", 180 => "111101100100111",
181 => "111101100011001", 182 => "111101100001011", 183 => "111101011111101",
184 => "111101011101111", 185 => "111101011100001", 186 => "111101011010011",
187 => "111101011000101", 188 => "111101010110111", 189 => "111101010101000",
190 => "111101010011010", 191 => "111101010001100", 192 => "111101001111101",
193 => "111101001101110", 194 => "111101001100000", 195 => "111101001010001",
196 => "111101001000010", 197 => "111101000110011", 198 => "111101000100100",
199 => "111101000010101", 200 => "111101000000110", 201 => "111100111110111",
202 => "111100111100111", 203 => "111100111011000", 204 => "111100111001001",
205 => "111100110111001", 206 => "111100110101010", 207 => "111100110011010",
208 => "111100110001010", 209 => "111100101111010", 210 => "111100101101010",
211 => "111100101011011", 212 => "111100101001010", 213 => "111100100111010",
214 => "111100100101010", 215 => "111100100011010", 216 => "111100100001010",
217 => "111100011111001", 218 => "111100011101001", 219 => "111100011011000",
220 => "111100011001000", 221 => "111100010110111", 222 => "111100010100110",
223 => "111100010010101", 224 => "111100010000101", 225 => "111100001110100",
226 => "111100001100011", 227 => "111100001010001", 228 => "111100001000000",
229 => "111100000101111", 230 => "111100000011110", 231 => "111100000001100",
232 => "111011111111011", 233 => "111011111101001", 234 => "111011111011000",
235 => "111011111000110", 236 => "111011110110100", 237 => "111011110100010",
238 => "111011110010000", 239 => "111011101111110", 240 => "111011101101100",
241 => "111011101011010", 242 => "111011101001000", 243 => "111011100110110",
244 => "111011100100011", 245 => "111011100010001", 246 => "111011011111110",
247 => "111011011101100", 248 => "111011011011001", 249 => "111011011000111",
250 => "111011010110100", 251 => "111011010100001", 252 => "111011010001110",
253 => "111011001111011", 254 => "111011001101000", 255 => "111011001010101",
256 => "111011001000010", 257 => "111011000101110", 258 => "111011000011011",
259 => "111011000001000", 260 => "111010111110100", 261 => "111010111100001",
262 => "111010111001101", 263 => "111010110111001", 264 => "111010110100110",
265 => "111010110010010", 266 => "111010101111110", 267 => "111010101101010",
268 => "111010101010110", 269 => "111010101000010", 270 => "111010100101101",
271 => "111010100011001", 272 => "111010100000101", 273 => "111010011110000",
274 => "111010011011100", 275 => "111010011000111", 276 => "111010010110011",
277 => "111010010011110", 278 => "111010010001001", 279 => "111010001110101",
280 => "111010001100000", 281 => "111010001001011", 282 => "111010000110110",
283 => "111010000100001", 284 => "111010000001011", 285 => "111001111110110",
286 => "111001111100001", 287 => "111001111001011", 288 => "111001110110110",
289 => "111001110100000", 290 => "111001110001011", 291 => "111001101110101",
292 => "111001101011111", 293 => "111001101001010", 294 => "111001100110100",
295 => "111001100011110", 296 => "111001100001000", 297 => "111001011110010",
298 => "111001011011100", 299 => "111001011000101", 300 => "111001010101111",
301 => "111001010011001", 302 => "111001010000010", 303 => "111001001101100",
304 => "111001001010101", 305 => "111001000111111", 306 => "111001000101000",
307 => "111001000010001", 308 => "111000111111010", 309 => "111000111100011",
310 => "111000111001100", 311 => "111000110110101", 312 => "111000110011110",
313 => "111000110000111", 314 => "111000101110000", 315 => "111000101011000",
316 => "111000101000001", 317 => "111000100101010", 318 => "111000100010010",
319 => "111000011111010", 320 => "111000011100011", 321 => "111000011001011",
322 => "111000010110011", 323 => "111000010011011", 324 => "111000010000011",
325 => "111000001101011", 326 => "111000001010011", 327 => "111000000111011",
328 => "111000000100011", 329 => "111000000001011", 330 => "110111111110010",
331 => "110111111011010", 332 => "110111111000010", 333 => "110111110101001",
334 => "110111110010000", 335 => "110111101111000", 336 => "110111101011111",
337 => "110111101000110", 338 => "110111100101101", 339 => "110111100010100",
340 => "110111011111011", 341 => "110111011100010", 342 => "110111011001001",
343 => "110111010110000", 344 => "110111010010111", 345 => "110111001111101",
346 => "110111001100100", 347 => "110111001001010", 348 => "110111000110001",
349 => "110111000010111", 350 => "110110111111110", 351 => "110110111100100",
352 => "110110111001010", 353 => "110110110110000", 354 => "110110110010110",
355 => "110110101111100", 356 => "110110101100010", 357 => "110110101001000",
358 => "110110100101110", 359 => "110110100010100", 360 => "110110011111001",
361 => "110110011011111", 362 => "110110011000100", 363 => "110110010101010",
364 => "110110010001111", 365 => "110110001110101", 366 => "110110001011010",
367 => "110110000111111", 368 => "110110000100100", 369 => "110110000001001",
370 => "110101111101110", 371 => "110101111010011", 372 => "110101110111000",
373 => "110101110011101", 374 => "110101110000010", 375 => "110101101100110",
376 => "110101101001011", 377 => "110101100101111", 378 => "110101100010100",
379 => "110101011111000", 380 => "110101011011101", 381 => "110101011000001",
382 => "110101010100101", 383 => "110101010001001", 384 => "110101001101110",
385 => "110101001010010", 386 => "110101000110110", 387 => "110101000011010",
388 => "110100111111101", 389 => "110100111100001", 390 => "110100111000101",
391 => "110100110101001", 392 => "110100110001100", 393 => "110100101110000",
394 => "110100101010011", 395 => "110100100110111", 396 => "110100100011010",
397 => "110100011111101", 398 => "110100011100000", 399 => "110100011000100",
400 => "110100010100111", 401 => "110100010001010", 402 => "110100001101101",
403 => "110100001001111", 404 => "110100000110010", 405 => "110100000010101",
406 => "110011111111000", 407 => "110011111011010", 408 => "110011110111101",
409 => "110011110100000", 410 => "110011110000010", 411 => "110011101100100",
412 => "110011101000111", 413 => "110011100101001", 414 => "110011100001011",
415 => "110011011101101", 416 => "110011011010000", 417 => "110011010110010",
418 => "110011010010011", 419 => "110011001110101", 420 => "110011001010111",
421 => "110011000111001", 422 => "110011000011011", 423 => "110010111111100",
424 => "110010111011110", 425 => "110010111000000", 426 => "110010110100001",
427 => "110010110000010", 428 => "110010101100100", 429 => "110010101000101",
430 => "110010100100110", 431 => "110010100000111", 432 => "110010011101001",
433 => "110010011001010", 434 => "110010010101011", 435 => "110010010001011",
436 => "110010001101100", 437 => "110010001001101", 438 => "110010000101110",
439 => "110010000001111", 440 => "110001111101111", 441 => "110001111010000",
442 => "110001110110000", 443 => "110001110010001", 444 => "110001101110001",
445 => "110001101010001", 446 => "110001100110010", 447 => "110001100010010",
448 => "110001011110010", 449 => "110001011010010", 450 => "110001010110010",
451 => "110001010010010", 452 => "110001001110010", 453 => "110001001010010",
454 => "110001000110010", 455 => "110001000010001", 456 => "110000111110001",
457 => "110000111010001", 458 => "110000110110000", 459 => "110000110010000",
460 => "110000101101111", 461 => "110000101001110", 462 => "110000100101110",
463 => "110000100001101", 464 => "110000011101100", 465 => "110000011001011",
466 => "110000010101010", 467 => "110000010001001", 468 => "110000001101000",
469 => "110000001000111", 470 => "110000000100110", 471 => "110000000000101",
472 => "101111111100100", 473 => "101111111000010", 474 => "101111110100001",
475 => "101111110000000", 476 => "101111101011110", 477 => "101111100111101",
478 => "101111100011011", 479 => "101111011111001", 480 => "101111011010111",
481 => "101111010110110", 482 => "101111010010100", 483 => "101111001110010",
484 => "101111001010000", 485 => "101111000101110", 486 => "101111000001100",
487 => "101110111101010", 488 => "101110111001000", 489 => "101110110100101",
490 => "101110110000011", 491 => "101110101100001", 492 => "101110100111110",
493 => "101110100011100", 494 => "101110011111001", 495 => "101110011010111",
496 => "101110010110100", 497 => "101110010010001", 498 => "101110001101111",
499 => "101110001001100", 500 => "101110000101001", 501 => "101110000000110",
502 => "101101111100011", 503 => "101101111000000", 504 => "101101110011101",
505 => "101101101111010", 506 => "101101101010111", 507 => "101101100110011",
508 => "101101100010000", 509 => "101101011101101", 510 => "101101011001001",
511 => "101101010100110", 512 => "101101010000010", 513 => "101101001011111",
514 => "101101000111011", 515 => "101101000011000", 516 => "101100111110100",
517 => "101100111010000", 518 => "101100110101100", 519 => "101100110001000",
520 => "101100101100100", 521 => "101100101000000", 522 => "101100100011100",
523 => "101100011111000", 524 => "101100011010100", 525 => "101100010110000",
526 => "101100010001100", 527 => "101100001100111", 528 => "101100001000011",
529 => "101100000011110", 530 => "101011111111010", 531 => "101011111010101",
532 => "101011110110001", 533 => "101011110001100", 534 => "101011101100111",
535 => "101011101000011", 536 => "101011100011110", 537 => "101011011111001",
538 => "101011011010100", 539 => "101011010101111", 540 => "101011010001010",
541 => "101011001100101", 542 => "101011001000000", 543 => "101011000011011",
544 => "101010111110110", 545 => "101010111010000", 546 => "101010110101011",
547 => "101010110000110", 548 => "101010101100000", 549 => "101010100111011",
550 => "101010100010101", 551 => "101010011110000", 552 => "101010011001010",
553 => "101010010100100", 554 => "101010001111111", 555 => "101010001011001",
556 => "101010000110011", 557 => "101010000001101", 558 => "101001111100111",
559 => "101001111000001", 560 => "101001110011011", 561 => "101001101110101",
562 => "101001101001111", 563 => "101001100101001", 564 => "101001100000011",
565 => "101001011011100", 566 => "101001010110110", 567 => "101001010010000",
568 => "101001001101001", 569 => "101001001000011", 570 => "101001000011100",
571 => "101000111110101", 572 => "101000111001111", 573 => "101000110101000",
574 => "101000110000001", 575 => "101000101011011", 576 => "101000100110100",
577 => "101000100001101", 578 => "101000011100110", 579 => "101000010111111",
580 => "101000010011000", 581 => "101000001110001", 582 => "101000001001010",
583 => "101000000100011", 584 => "100111111111011", 585 => "100111111010100",
586 => "100111110101101", 587 => "100111110000101", 588 => "100111101011110",
589 => "100111100110111", 590 => "100111100001111", 591 => "100111011101000",
592 => "100111011000000", 593 => "100111010011000", 594 => "100111001110001",
595 => "100111001001001", 596 => "100111000100001", 597 => "100110111111001",
598 => "100110111010001", 599 => "100110110101001", 600 => "100110110000001",
601 => "100110101011001", 602 => "100110100110001", 603 => "100110100001001",
604 => "100110011100001", 605 => "100110010111001", 606 => "100110010010001",
607 => "100110001101000", 608 => "100110001000000", 609 => "100110000010111",
610 => "100101111101111", 611 => "100101111000111", 612 => "100101110011110",
613 => "100101101110101", 614 => "100101101001101", 615 => "100101100100100",
616 => "100101011111011", 617 => "100101011010011", 618 => "100101010101010",
619 => "100101010000001", 620 => "100101001011000", 621 => "100101000101111",
622 => "100101000000110", 623 => "100100111011101", 624 => "100100110110100",
625 => "100100110001011", 626 => "100100101100010", 627 => "100100100111001",
628 => "100100100001111", 629 => "100100011100110", 630 => "100100010111101",
631 => "100100010010011", 632 => "100100001101010", 633 => "100100001000000",
634 => "100100000010111", 635 => "100011111101101", 636 => "100011111000100",
637 => "100011110011010", 638 => "100011101110000", 639 => "100011101000111",
640 => "100011100011101", 641 => "100011011110011", 642 => "100011011001001",
643 => "100011010011111", 644 => "100011001110101", 645 => "100011001001011",
646 => "100011000100001", 647 => "100010111110111", 648 => "100010111001101",
649 => "100010110100011", 650 => "100010101111001", 651 => "100010101001111",
652 => "100010100100100", 653 => "100010011111010", 654 => "100010011010000",
655 => "100010010100101", 656 => "100010001111011", 657 => "100010001010000",
658 => "100010000100110", 659 => "100001111111011", 660 => "100001111010001",
661 => "100001110100110", 662 => "100001101111011", 663 => "100001101010001",
664 => "100001100100110", 665 => "100001011111011", 666 => "100001011010000",
667 => "100001010100101", 668 => "100001001111010", 669 => "100001001001111",
670 => "100001000100100", 671 => "100000111111001", 672 => "100000111001110",
673 => "100000110100011", 674 => "100000101111000", 675 => "100000101001101",
676 => "100000100100001", 677 => "100000011110110", 678 => "100000011001011",
679 => "100000010011111", 680 => "100000001110100", 681 => "100000001001000",
682 => "100000000011101", 683 => "011111111110001", 684 => "011111111000110",
685 => "011111110011010", 686 => "011111101101111", 687 => "011111101000011",
688 => "011111100010111", 689 => "011111011101100", 690 => "011111011000000",
691 => "011111010010100", 692 => "011111001101000", 693 => "011111000111100",
694 => "011111000010000", 695 => "011110111100100", 696 => "011110110111000",
697 => "011110110001100", 698 => "011110101100000", 699 => "011110100110100",
700 => "011110100001000", 701 => "011110011011100", 702 => "011110010101111",
703 => "011110010000011", 704 => "011110001010111", 705 => "011110000101010",
706 => "011101111111110", 707 => "011101111010010", 708 => "011101110100101",
709 => "011101101111001", 710 => "011101101001100", 711 => "011101100100000",
712 => "011101011110011", 713 => "011101011000110", 714 => "011101010011010",
715 => "011101001101101", 716 => "011101001000000", 717 => "011101000010011",
718 => "011100111100111", 719 => "011100110111010", 720 => "011100110001101",
721 => "011100101100000", 722 => "011100100110011", 723 => "011100100000110",
724 => "011100011011001", 725 => "011100010101100", 726 => "011100001111111",
727 => "011100001010010", 728 => "011100000100101", 729 => "011011111110111",
730 => "011011111001010", 731 => "011011110011101", 732 => "011011101110000",
733 => "011011101000010", 734 => "011011100010101", 735 => "011011011101000",
736 => "011011010111010", 737 => "011011010001101", 738 => "011011001011111",
739 => "011011000110010", 740 => "011011000000100", 741 => "011010111010111",
742 => "011010110101001", 743 => "011010101111011", 744 => "011010101001110",
745 => "011010100100000", 746 => "011010011110010", 747 => "011010011000100",
748 => "011010010010111", 749 => "011010001101001", 750 => "011010000111011",
751 => "011010000001101", 752 => "011001111011111", 753 => "011001110110001",
754 => "011001110000011", 755 => "011001101010101", 756 => "011001100100111",
757 => "011001011111001", 758 => "011001011001011", 759 => "011001010011101",
760 => "011001001101110", 761 => "011001001000000", 762 => "011001000010010",
763 => "011000111100100", 764 => "011000110110101", 765 => "011000110000111",
766 => "011000101011001", 767 => "011000100101010", 768 => "011000011111100",
769 => "011000011001101", 770 => "011000010011111", 771 => "011000001110000",
772 => "011000001000010", 773 => "011000000010011", 774 => "010111111100101",
775 => "010111110110110", 776 => "010111110000111", 777 => "010111101011001",
778 => "010111100101010", 779 => "010111011111011", 780 => "010111011001100",
781 => "010111010011110", 782 => "010111001101111", 783 => "010111001000000",
784 => "010111000010001", 785 => "010110111100010", 786 => "010110110110011",
787 => "010110110000100", 788 => "010110101010101", 789 => "010110100100110",
790 => "010110011110111", 791 => "010110011001000", 792 => "010110010011001",
793 => "010110001101010", 794 => "010110000111011", 795 => "010110000001100",
796 => "010101111011100", 797 => "010101110101101", 798 => "010101101111110",
799 => "010101101001111", 800 => "010101100011111", 801 => "010101011110000",
802 => "010101011000001", 803 => "010101010010001", 804 => "010101001100010",
805 => "010101000110010", 806 => "010101000000011", 807 => "010100111010011",
808 => "010100110100100", 809 => "010100101110100", 810 => "010100101000101",
811 => "010100100010101", 812 => "010100011100101", 813 => "010100010110110",
814 => "010100010000110", 815 => "010100001010110", 816 => "010100000100111",
817 => "010011111110111", 818 => "010011111000111", 819 => "010011110010111",
820 => "010011101101000", 821 => "010011100111000", 822 => "010011100001000",
823 => "010011011011000", 824 => "010011010101000", 825 => "010011001111000",
826 => "010011001001000", 827 => "010011000011000", 828 => "010010111101000",
829 => "010010110111000", 830 => "010010110001000", 831 => "010010101011000",
832 => "010010100101000", 833 => "010010011111000", 834 => "010010011001000",
835 => "010010010011000", 836 => "010010001100111", 837 => "010010000110111",
838 => "010010000000111", 839 => "010001111010111", 840 => "010001110100111",
841 => "010001101110110", 842 => "010001101000110", 843 => "010001100010110",
844 => "010001011100101", 845 => "010001010110101", 846 => "010001010000100",
847 => "010001001010100", 848 => "010001000100100", 849 => "010000111110011",
850 => "010000111000011", 851 => "010000110010010", 852 => "010000101100010",
853 => "010000100110001", 854 => "010000100000001", 855 => "010000011010000",
856 => "010000010011111", 857 => "010000001101111", 858 => "010000000111110",
859 => "010000000001110", 860 => "001111111011101", 861 => "001111110101100",
862 => "001111101111011", 863 => "001111101001011", 864 => "001111100011010",
865 => "001111011101001", 866 => "001111010111000", 867 => "001111010001000",
868 => "001111001010111", 869 => "001111000100110", 870 => "001110111110101",
871 => "001110111000100", 872 => "001110110010011", 873 => "001110101100010",
874 => "001110100110001", 875 => "001110100000001", 876 => "001110011010000",
877 => "001110010011111", 878 => "001110001101110", 879 => "001110000111101",
880 => "001110000001100", 881 => "001101111011010", 882 => "001101110101001",
883 => "001101101111000", 884 => "001101101000111", 885 => "001101100010110",
886 => "001101011100101", 887 => "001101010110100", 888 => "001101010000011",
889 => "001101001010001", 890 => "001101000100000", 891 => "001100111101111",
892 => "001100110111110", 893 => "001100110001101", 894 => "001100101011011",
895 => "001100100101010", 896 => "001100011111001", 897 => "001100011000111",
898 => "001100010010110", 899 => "001100001100101", 900 => "001100000110011",
901 => "001100000000010", 902 => "001011111010001", 903 => "001011110011111",
904 => "001011101101110", 905 => "001011100111100", 906 => "001011100001011",
907 => "001011011011010", 908 => "001011010101000", 909 => "001011001110111",
910 => "001011001000101", 911 => "001011000010100", 912 => "001010111100010",
913 => "001010110110001", 914 => "001010101111111", 915 => "001010101001101",
916 => "001010100011100", 917 => "001010011101010", 918 => "001010010111001",
919 => "001010010000111", 920 => "001010001010101", 921 => "001010000100100",
922 => "001001111110010", 923 => "001001111000001", 924 => "001001110001111",
925 => "001001101011101", 926 => "001001100101011", 927 => "001001011111010",
928 => "001001011001000", 929 => "001001010010110", 930 => "001001001100101",
931 => "001001000110011", 932 => "001001000000001", 933 => "001000111001111",
934 => "001000110011110", 935 => "001000101101100", 936 => "001000100111010",
937 => "001000100001000", 938 => "001000011010110", 939 => "001000010100100",
940 => "001000001110011", 941 => "001000001000001", 942 => "001000000001111",
943 => "000111111011101", 944 => "000111110101011", 945 => "000111101111001",
946 => "000111101000111", 947 => "000111100010101", 948 => "000111011100100",
949 => "000111010110010", 950 => "000111010000000", 951 => "000111001001110",
952 => "000111000011100", 953 => "000110111101010", 954 => "000110110111000",
955 => "000110110000110", 956 => "000110101010100", 957 => "000110100100010",
958 => "000110011110000", 959 => "000110010111110", 960 => "000110010001100",
961 => "000110001011010", 962 => "000110000101000", 963 => "000101111110110",
964 => "000101111000100", 965 => "000101110010010", 966 => "000101101100000",
967 => "000101100101101", 968 => "000101011111011", 969 => "000101011001001",
970 => "000101010010111", 971 => "000101001100101", 972 => "000101000110011",
973 => "000101000000001", 974 => "000100111001111", 975 => "000100110011101",
976 => "000100101101011", 977 => "000100100111000", 978 => "000100100000110",
979 => "000100011010100", 980 => "000100010100010", 981 => "000100001110000",
982 => "000100000111110", 983 => "000100000001100", 984 => "000011111011001",
985 => "000011110100111", 986 => "000011101110101", 987 => "000011101000011",
988 => "000011100010001", 989 => "000011011011110", 990 => "000011010101100",
991 => "000011001111010", 992 => "000011001001000", 993 => "000011000010110",
994 => "000010111100011", 995 => "000010110110001", 996 => "000010101111111",
997 => "000010101001101", 998 => "000010100011011", 999 => "000010011101000",
1000 => "000010010110110", 1001 => "000010010000100", 1002 => "000010001010010",
1003 => "000010000011111", 1004 => "000001111101101", 1005 => "000001110111011",
1006 => "000001110001001", 1007 => "000001101010110", 1008 => "000001100100100",
1009 => "000001011110010", 1010 => "000001011000000", 1011 => "000001010001101",
1012 => "000001001011011", 1013 => "000001000101001", 1014 => "000000111110111",
1015 => "000000111000100", 1016 => "000000110010010", 1017 => "000000101100000",
1018 => "000000100101110", 1019 => "000000011111011", 1020 => "000000011001001",
1021 => "000000010010111", 1022 => "000000001100101", 1023 => "000000000110010" );
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
p_rom_access: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= mem(CONV_INTEGER(addr0_tmp));
end if;
if (ce1 = '1') then
q1 <= mem(CONV_INTEGER(addr1_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity qam_dem_top_mounstrito_cos_lut is
generic (
DataWidth : INTEGER := 15;
AddressRange : INTEGER := 1024;
AddressWidth : INTEGER := 10);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of qam_dem_top_mounstrito_cos_lut is
component qam_dem_top_mounstrito_cos_lut_rom is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR);
end component;
begin
qam_dem_top_mounstrito_cos_lut_rom_U : component qam_dem_top_mounstrito_cos_lut_rom
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
q1 => q1);
end architecture;
| gpl-2.0 | 6f05214ff3e9eb853a54698f57e0c86d | 0.638744 | 4.212073 | false | false | false | false |
chastell/art-decomp | kiss/scf_rnd.vhd | 1 | 39,256 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity scf_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(26 downto 0);
output: out std_logic_vector(55 downto 0)
);
end scf_rnd;
architecture behaviour of scf_rnd is
constant state1: std_logic_vector(6 downto 0) := "0111101";
constant state3: std_logic_vector(6 downto 0) := "0000010";
constant state2: std_logic_vector(6 downto 0) := "0011011";
constant state4: std_logic_vector(6 downto 0) := "0111110";
constant state5: std_logic_vector(6 downto 0) := "1111111";
constant state7: std_logic_vector(6 downto 0) := "1010001";
constant state6: std_logic_vector(6 downto 0) := "0010110";
constant state9: std_logic_vector(6 downto 0) := "0001011";
constant state8: std_logic_vector(6 downto 0) := "1001111";
constant state17: std_logic_vector(6 downto 0) := "0011110";
constant state12: std_logic_vector(6 downto 0) := "1011011";
constant state10: std_logic_vector(6 downto 0) := "0101011";
constant state11: std_logic_vector(6 downto 0) := "1100001";
constant state15: std_logic_vector(6 downto 0) := "1110000";
constant state13: std_logic_vector(6 downto 0) := "1101111";
constant state29: std_logic_vector(6 downto 0) := "0001111";
constant state14: std_logic_vector(6 downto 0) := "1101011";
constant state59: std_logic_vector(6 downto 0) := "1011010";
constant state16: std_logic_vector(6 downto 0) := "0111000";
constant state18: std_logic_vector(6 downto 0) := "0110110";
constant state19: std_logic_vector(6 downto 0) := "1001000";
constant state21: std_logic_vector(6 downto 0) := "0000001";
constant state20: std_logic_vector(6 downto 0) := "0100100";
constant state22: std_logic_vector(6 downto 0) := "0111111";
constant state23: std_logic_vector(6 downto 0) := "0001001";
constant state24: std_logic_vector(6 downto 0) := "0101001";
constant state26: std_logic_vector(6 downto 0) := "0100110";
constant state25: std_logic_vector(6 downto 0) := "0111011";
constant state28: std_logic_vector(6 downto 0) := "1011100";
constant state27: std_logic_vector(6 downto 0) := "1100011";
constant state36: std_logic_vector(6 downto 0) := "1111000";
constant state34: std_logic_vector(6 downto 0) := "0100010";
constant state32: std_logic_vector(6 downto 0) := "1001001";
constant state30: std_logic_vector(6 downto 0) := "0011000";
constant state38: std_logic_vector(6 downto 0) := "1010110";
constant state31: std_logic_vector(6 downto 0) := "0100011";
constant state37: std_logic_vector(6 downto 0) := "1000011";
constant state55: std_logic_vector(6 downto 0) := "0110111";
constant state33: std_logic_vector(6 downto 0) := "0010011";
constant state57: std_logic_vector(6 downto 0) := "0110010";
constant state35: std_logic_vector(6 downto 0) := "1000111";
constant state43: std_logic_vector(6 downto 0) := "0001100";
constant state41: std_logic_vector(6 downto 0) := "0110101";
constant state39: std_logic_vector(6 downto 0) := "1010100";
constant state45: std_logic_vector(6 downto 0) := "0000000";
constant state40: std_logic_vector(6 downto 0) := "1000001";
constant state44: std_logic_vector(6 downto 0) := "1100111";
constant state50: std_logic_vector(6 downto 0) := "1011101";
constant state42: std_logic_vector(6 downto 0) := "1001011";
constant state48: std_logic_vector(6 downto 0) := "0101111";
constant state46: std_logic_vector(6 downto 0) := "1101101";
constant state47: std_logic_vector(6 downto 0) := "1011000";
constant state49: std_logic_vector(6 downto 0) := "0100101";
constant state52: std_logic_vector(6 downto 0) := "0100000";
constant state51: std_logic_vector(6 downto 0) := "0010001";
constant state54: std_logic_vector(6 downto 0) := "1111100";
constant state53: std_logic_vector(6 downto 0) := "1000100";
constant state56: std_logic_vector(6 downto 0) := "0110011";
constant state58: std_logic_vector(6 downto 0) := "1010111";
constant state67: std_logic_vector(6 downto 0) := "0000111";
constant state60: std_logic_vector(6 downto 0) := "1111010";
constant state65: std_logic_vector(6 downto 0) := "1111001";
constant state63: std_logic_vector(6 downto 0) := "1101000";
constant state61: std_logic_vector(6 downto 0) := "1100000";
constant state82: std_logic_vector(6 downto 0) := "0111001";
constant state62: std_logic_vector(6 downto 0) := "0000101";
constant state83: std_logic_vector(6 downto 0) := "0010100";
constant state64: std_logic_vector(6 downto 0) := "1001100";
constant state89: std_logic_vector(6 downto 0) := "1111011";
constant state66: std_logic_vector(6 downto 0) := "1010011";
constant state81: std_logic_vector(6 downto 0) := "1110100";
constant state80: std_logic_vector(6 downto 0) := "1001010";
constant state78: std_logic_vector(6 downto 0) := "1110011";
constant state76: std_logic_vector(6 downto 0) := "1000110";
constant state74: std_logic_vector(6 downto 0) := "1011001";
constant state72: std_logic_vector(6 downto 0) := "1100101";
constant state70: std_logic_vector(6 downto 0) := "1101110";
constant state68: std_logic_vector(6 downto 0) := "1110001";
constant state96: std_logic_vector(6 downto 0) := "0111100";
constant state69: std_logic_vector(6 downto 0) := "0100001";
constant state98: std_logic_vector(6 downto 0) := "0101000";
constant state71: std_logic_vector(6 downto 0) := "0011111";
constant state103: std_logic_vector(6 downto 0) := "0011010";
constant state73: std_logic_vector(6 downto 0) := "1111101";
constant state107: std_logic_vector(6 downto 0) := "1110110";
constant state75: std_logic_vector(6 downto 0) := "1010000";
constant state115: std_logic_vector(6 downto 0) := "0010000";
constant state77: std_logic_vector(6 downto 0) := "0100111";
constant state117: std_logic_vector(6 downto 0) := "0110000";
constant state79: std_logic_vector(6 downto 0) := "0000100";
constant state84: std_logic_vector(6 downto 0) := "1110010";
constant state86: std_logic_vector(6 downto 0) := "1111110";
constant state85: std_logic_vector(6 downto 0) := "0110100";
constant state88: std_logic_vector(6 downto 0) := "0110001";
constant state87: std_logic_vector(6 downto 0) := "0011001";
constant state91: std_logic_vector(6 downto 0) := "1101001";
constant state90: std_logic_vector(6 downto 0) := "1110101";
constant state92: std_logic_vector(6 downto 0) := "1001110";
constant state95: std_logic_vector(6 downto 0) := "1000010";
constant state93: std_logic_vector(6 downto 0) := "1101010";
constant state94: std_logic_vector(6 downto 0) := "1101100";
constant state97: std_logic_vector(6 downto 0) := "0010010";
constant state101: std_logic_vector(6 downto 0) := "1100010";
constant state99: std_logic_vector(6 downto 0) := "0101010";
constant state100: std_logic_vector(6 downto 0) := "1000000";
constant state102: std_logic_vector(6 downto 0) := "1100100";
constant state105: std_logic_vector(6 downto 0) := "0001000";
constant state104: std_logic_vector(6 downto 0) := "0011101";
constant state106: std_logic_vector(6 downto 0) := "0001010";
constant state112: std_logic_vector(6 downto 0) := "1010010";
constant state108: std_logic_vector(6 downto 0) := "1011110";
constant state110: std_logic_vector(6 downto 0) := "1011111";
constant state109: std_logic_vector(6 downto 0) := "0001101";
constant state111: std_logic_vector(6 downto 0) := "1100110";
constant state114: std_logic_vector(6 downto 0) := "1001101";
constant state113: std_logic_vector(6 downto 0) := "0101110";
constant state116: std_logic_vector(6 downto 0) := "0101100";
constant state118: std_logic_vector(6 downto 0) := "0101101";
constant state121: std_logic_vector(6 downto 0) := "0001110";
constant state119: std_logic_vector(6 downto 0) := "1010101";
constant state120: std_logic_vector(6 downto 0) := "0011100";
signal current_state, next_state: std_logic_vector(6 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-------"; output <= "--------------------------------------------------------";
if std_match(input, "0--------------------------") then next_state <= state1; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
else
case current_state is
when state1 =>
if std_match(input, "1--------------------------") then next_state <= state3; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state2 =>
if std_match(input, "1--------------------------") then next_state <= state1; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state3 =>
if std_match(input, "1--------------------------") then next_state <= state4; output <= "00000010010000001-0000000-00-0001001000010-0-----00-0---";
end if;
when state4 =>
if std_match(input, "1--------------------------") then next_state <= state5; output <= "00000010000000000-0000000-00-0000000110101-0-----00-0---";
end if;
when state5 =>
if std_match(input, "1--------------------------") then next_state <= state7; output <= "00000001000000000-0000000-00-0000000001000-0-----00-0---";
end if;
when state6 =>
if std_match(input, "1--------------------------") then next_state <= state2; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state7 =>
if std_match(input, "1-----0--------------------") then next_state <= state9; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----1--------------------") then next_state <= state8; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state8 =>
if std_match(input, "1--------------------------") then next_state <= state17; output <= "00000010000000000-0000000-00-0000000001000-0-----00-0---";
end if;
when state9 =>
if std_match(input, "1----0---------------------") then next_state <= state12; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----1---------------------") then next_state <= state10; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state10 =>
if std_match(input, "1--------------------------") then next_state <= state11; output <= "00000010000000000-0000001-00-0000000000001-0-----00-0---";
end if;
when state11 =>
if std_match(input, "1--------------------------") then next_state <= state12; output <= "00000000000000000-0000000-00-0000010000000-0-----00-0---";
end if;
when state12 =>
if std_match(input, "1---0----------------------") then next_state <= state15; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1---1----------------------") then next_state <= state13; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state13 =>
if std_match(input, "1--------------------------") then next_state <= state29; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state14 =>
if std_match(input, "1--------------------------") then next_state <= state17; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state15 =>
if std_match(input, "1--------------------------") then next_state <= state59; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state16 =>
if std_match(input, "1--------------------------") then next_state <= state17; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state17 =>
if std_match(input, "1--------------------------") then next_state <= state18; output <= "0000000000010100001000000-10-000000000000011-----00-0---";
end if;
when state18 =>
if std_match(input, "1--------------------------") then next_state <= state19; output <= "00100000000000000-0000000-00-0000000000000-0000--00-0---";
end if;
when state19 =>
if std_match(input, "1--0-----------------------") then next_state <= state21; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--1-----------------------") then next_state <= state20; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state20 =>
if std_match(input, "1--------------------------") then next_state <= state21; output <= "00000001000000000-0000000-00-0000000100000-0-----00-0---";
end if;
when state21 =>
if std_match(input, "1--------------------------") then next_state <= state22; output <= "01000000000100000-0000000-10-100000000000000000001001---";
end if;
when state22 =>
if std_match(input, "1--------------------------") then next_state <= state23; output <= "00010000000000000-0000000-00-0000000000000-0000--01-0---";
end if;
when state23 =>
if std_match(input, "1--------------------------") then next_state <= state24; output <= "00000000100000000-0000000-00-0000000000000-0---0000-0---";
end if;
when state24 =>
if std_match(input, "1-0------------------------") then next_state <= state26; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-1------------------------") then next_state <= state25; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state25 =>
if std_match(input, "1--------------------------") then next_state <= state26; output <= "00000001000000000-0000000-00-0000000010000-0-----00-0---";
end if;
when state26 =>
if std_match(input, "10-------------------------") then next_state <= state28; output <= "00000000010000010-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "11-------------------------") then next_state <= state27; output <= "00000000010000010-0000000-00-0000000000000-0-----00-0---";
end if;
when state27 =>
if std_match(input, "1--------------------------") then next_state <= state28; output <= "00000000000000000-0000000-00-0010000000000-0-----00-0---";
end if;
when state28 =>
if std_match(input, "1--------------------------") then next_state <= state7; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state29 =>
if std_match(input, "1------1-------------------") then next_state <= state36; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------01------------------") then next_state <= state36; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0011----------------") then next_state <= state36; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0010----------------") then next_state <= state34; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0001----------------") then next_state <= state32; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0000----------------") then next_state <= state30; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state30 =>
if std_match(input, "1--------------------------") then next_state <= state38; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state31 =>
if std_match(input, "1--------------------------") then next_state <= state37; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state32 =>
if std_match(input, "1--------------------------") then next_state <= state55; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state33 =>
if std_match(input, "1--------------------------") then next_state <= state37; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state34 =>
if std_match(input, "1--------------------------") then next_state <= state57; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state35 =>
if std_match(input, "1--------------------------") then next_state <= state37; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state36 =>
if std_match(input, "1--------------------------") then next_state <= state37; output <= "00000001000000000-0000000-00-0000000010000-0-----00-0---";
end if;
when state37 =>
if std_match(input, "1--------------------------") then next_state <= state14; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state38 =>
if std_match(input, "1----------1---------------") then next_state <= state43; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----------01--------------") then next_state <= state43; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----------001-------------") then next_state <= state43; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----------0001------------") then next_state <= state41; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----------0000------------") then next_state <= state39; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state39 =>
if std_match(input, "1--------------------------") then next_state <= state45; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state40 =>
if std_match(input, "1--------------------------") then next_state <= state44; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state41 =>
if std_match(input, "1--------------------------") then next_state <= state50; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state42 =>
if std_match(input, "1--------------------------") then next_state <= state44; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state43 =>
if std_match(input, "1--------------------------") then next_state <= state44; output <= "00000001000000000-0000000-00-0000000010000-0-----00-0---";
end if;
when state44 =>
if std_match(input, "1--------------------------") then next_state <= state31; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state45 =>
if std_match(input, "1--------------0-----------") then next_state <= state48; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--------------1-----------") then next_state <= state46; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state46 =>
if std_match(input, "1--------------------------") then next_state <= state47; output <= "0000000001000101001000000-00-0000000000000-0-----00-0---";
end if;
when state47 =>
if std_match(input, "1--------------------------") then next_state <= state49; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state48 =>
if std_match(input, "1--------------------------") then next_state <= state49; output <= "0000000000100000111001010-00-0000000000000-0-----00-0---";
end if;
when state49 =>
if std_match(input, "1--------------------------") then next_state <= state40; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state50 =>
if std_match(input, "1--------------0-----------") then next_state <= state52; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--------------1-----------") then next_state <= state51; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state51 =>
if std_match(input, "1--------------------------") then next_state <= state54; output <= "0000000000100000111001010-00-0000000000000-0-----00-0---";
end if;
when state52 =>
if std_match(input, "1--------------------------") then next_state <= state53; output <= "0000000000000101001000000-00-0000000000000-0-----00-0---";
end if;
when state53 =>
if std_match(input, "1--------------------------") then next_state <= state54; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state54 =>
if std_match(input, "1--------------------------") then next_state <= state42; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state55 =>
if std_match(input, "1--------------------------") then next_state <= state56; output <= "0000000000100000111001010-00-0000000000000-0-----00-0---";
end if;
when state56 =>
if std_match(input, "1--------------------------") then next_state <= state33; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state57 =>
if std_match(input, "1--------------------------") then next_state <= state58; output <= "00000000001000001-0001000-00-0000000000000-0-----00-0---";
end if;
when state58 =>
if std_match(input, "1--------------------------") then next_state <= state35; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state59 =>
if std_match(input, "1---------------0----------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1---------------1----------") then next_state <= state60; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state60 =>
if std_match(input, "1------1-------------------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------01------------------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0011----------------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0010----------------") then next_state <= state65; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0001----------------") then next_state <= state63; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0000----------------") then next_state <= state61; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state61 =>
if std_match(input, "1--------------------------") then next_state <= state82; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state62 =>
if std_match(input, "1--------------------------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state63 =>
if std_match(input, "1--------------------------") then next_state <= state83; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state64 =>
if std_match(input, "1--------------------------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state65 =>
if std_match(input, "1--------------------------") then next_state <= state89; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state66 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state67 =>
if std_match(input, "1------1-------------------") then next_state <= state80; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------011-----------------") then next_state <= state80; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0101----------------") then next_state <= state78; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0100----------------") then next_state <= state76; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0011----------------") then next_state <= state74; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0010----------------") then next_state <= state72; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0001----------------") then next_state <= state70; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0000----------------") then next_state <= state68; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state68 =>
if std_match(input, "1--------------------------") then next_state <= state96; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state69 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state70 =>
if std_match(input, "1--------------------------") then next_state <= state98; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state71 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state72 =>
if std_match(input, "1--------------------------") then next_state <= state103; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state73 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state74 =>
if std_match(input, "1--------------------------") then next_state <= state107; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state75 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state76 =>
if std_match(input, "1--------------------------") then next_state <= state115; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state77 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state78 =>
if std_match(input, "1--------------------------") then next_state <= state117; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state79 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state80 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000001000000000-0000000-00-0000000010000-0-----00-0---";
end if;
when state81 =>
if std_match(input, "1--------------------------") then next_state <= state16; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state82 =>
if std_match(input, "1--------------------------") then next_state <= state62; output <= "00000001000000000-0000000-00-0000000010000-0-----00-0---";
end if;
when state83 =>
if std_match(input, "1--------------------------") then next_state <= state84; output <= "00000001000000000-0000000-00-0000000001000-0-----00-0---";
end if;
when state84 =>
if std_match(input, "1--------------------------") then next_state <= state86; output <= "00001000000001001-0000000-00-0000000000000-0100--00-0---";
end if;
when state85 =>
if std_match(input, "1--------------------------") then next_state <= state64; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state86 =>
if std_match(input, "1----------------0---------") then next_state <= state88; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----------------1---------") then next_state <= state87; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state87 =>
if std_match(input, "1--------------------------") then next_state <= state16; output <= "00000001000000000-0000000-00-0000100001000-0-----00-0---";
end if;
when state88 =>
if std_match(input, "1--------------------------") then next_state <= state86; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state89 =>
if std_match(input, "1--------------------------") then next_state <= state91; output <= "00001001000000000-0000000-00-0001000001000-0-----00-0---";
end if;
when state90 =>
if std_match(input, "1--------------------------") then next_state <= state66; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state91 =>
if std_match(input, "1--------------------------") then next_state <= state92; output <= "00000010000000000-0000000-00-0000000000000-0010--00-0---";
end if;
when state92 =>
if std_match(input, "1--0-----------------------") then next_state <= state95; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--1-----------------------") then next_state <= state93; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state93 =>
if std_match(input, "1--------------------------") then next_state <= state94; output <= "00000000000100001-0000000-10-0000000000000-0-----00-0---";
end if;
when state94 =>
if std_match(input, "1--------------------------") then next_state <= state16; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state95 =>
if std_match(input, "1--------------------------") then next_state <= state91; output <= "00000000000000000-0000000-00-0010100000000-0-----00-0---";
end if;
when state96 =>
if std_match(input, "1--------------------------") then next_state <= state97; output <= "00000100000001000-0000000-00-000000000000011101111011101";
end if;
when state97 =>
if std_match(input, "1--------------------------") then next_state <= state69; output <= "001000010000000100101010010110100000000001-0-----00-0---";
end if;
when state98 =>
if std_match(input, "1--------------0-----------") then next_state <= state101; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--------------1-----------") then next_state <= state99; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state99 =>
if std_match(input, "1--------------------------") then next_state <= state100; output <= "00000100000001000-0000000-00-000000000000011101111011101";
end if;
when state100 =>
if std_match(input, "1--------------------------") then next_state <= state102; output <= "001000010000000100101010010110100000000001-0-----00-0---";
end if;
when state101 =>
if std_match(input, "1--------------------------") then next_state <= state102; output <= "00000100000001001-0000000-00-0000000001000-0100--00-0---";
end if;
when state102 =>
if std_match(input, "1--------------------------") then next_state <= state71; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state103 =>
if std_match(input, "1--------------0-----------") then next_state <= state105; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--------------1-----------") then next_state <= state104; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state104 =>
if std_match(input, "1--------------------------") then next_state <= state106; output <= "0000000000000101001000000-00-0000000000000-0-----00-0---";
end if;
when state105 =>
if std_match(input, "1--------------------------") then next_state <= state106; output <= "00000100000001001-0000000-00-0000000001000-0100--00-0---";
end if;
when state106 =>
if std_match(input, "1--------------------------") then next_state <= state73; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state107 =>
if std_match(input, "1--------------0-----------") then next_state <= state112; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--------------1-----------") then next_state <= state108; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state108 =>
if std_match(input, "1-----------------00000000-") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------1--------") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------01-------") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------001------") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------0001-----") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------00001----") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------000001---") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------0000001--") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------00000001-") then next_state <= state109; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state109 =>
if std_match(input, "1--------------------------") then next_state <= state112; output <= "0000000000001100101000000-00-0000000000000-0-----00-0100";
end if;
when state110 =>
if std_match(input, "1--------------------------") then next_state <= state111; output <= "0000010000000101001010000-0000100000000000111000110-0100";
end if;
when state111 =>
if std_match(input, "1--------------------------") then next_state <= state114; output <= "00000001000000000-0000100001-0000000000001-0-----00-0---";
end if;
when state112 =>
if std_match(input, "1--------------------------") then next_state <= state113; output <= "00000100000001001-0000000-00-0000000000000-0100--00-0---";
end if;
when state113 =>
if std_match(input, "1--------------------------") then next_state <= state114; output <= "00000001000000000-0000000-00-0000000001000-0-----00-0---";
end if;
when state114 =>
if std_match(input, "1--------------------------") then next_state <= state75; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state115 =>
if std_match(input, "1--------------------------") then next_state <= state116; output <= "00001000000010001-0010000-00-0000000000000-01011010-0101";
end if;
when state116 =>
if std_match(input, "1--------------------------") then next_state <= state77; output <= "10000001000000000-0000100-00-0001000001101-0-----00-0---";
end if;
when state117 =>
if std_match(input, "1--------------------------") then next_state <= state118; output <= "00000010000000000-0000000-00-0000000000000-0-----00-0011";
end if;
when state118 =>
if std_match(input, "1-------------------------0") then next_state <= state121; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-------------------------1") then next_state <= state119; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state119 =>
if std_match(input, "1--------------------------") then next_state <= state120; output <= "0000010000001000001000000-00-0000000000000111011010-0101";
end if;
when state120 =>
if std_match(input, "1--------------------------") then next_state <= state16; output <= "00010010000000010-000000000110100000000100-0-----00-0---";
end if;
when state121 =>
if std_match(input, "1--------------------------") then next_state <= state79; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when others => next_state <= "-------"; output <= "--------------------------------------------------------";
end case;
end if;
end process;
end behaviour;
| agpl-3.0 | 14545f8ab380202a1b197a00e0403b96 | 0.566767 | 4.06461 | false | false | false | false |
chastell/art-decomp | kiss/dk17_nov.vhd | 1 | 4,134 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk17_nov is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(2 downto 0)
);
end dk17_nov;
architecture behaviour of dk17_nov is
constant s10000000: std_logic_vector(2 downto 0) := "001";
constant s01000000: std_logic_vector(2 downto 0) := "101";
constant s00100000: std_logic_vector(2 downto 0) := "000";
constant s00010000: std_logic_vector(2 downto 0) := "011";
constant s00001000: std_logic_vector(2 downto 0) := "100";
constant s00000100: std_logic_vector(2 downto 0) := "110";
constant s00000010: std_logic_vector(2 downto 0) := "010";
constant s00000001: std_logic_vector(2 downto 0) := "111";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "---";
case current_state is
when s10000000 =>
if std_match(input, "00") then next_state <= s10000000; output <= "001";
elsif std_match(input, "01") then next_state <= s00010000; output <= "010";
elsif std_match(input, "10") then next_state <= s01000000; output <= "001";
elsif std_match(input, "11") then next_state <= s00001000; output <= "010";
end if;
when s01000000 =>
if std_match(input, "00") then next_state <= s00100000; output <= "000";
elsif std_match(input, "01") then next_state <= s00010000; output <= "000";
elsif std_match(input, "10") then next_state <= s00100000; output <= "010";
elsif std_match(input, "11") then next_state <= s00000100; output <= "000";
end if;
when s00100000 =>
if std_match(input, "00") then next_state <= s10000000; output <= "001";
elsif std_match(input, "01") then next_state <= s10000000; output <= "101";
elsif std_match(input, "10") then next_state <= s01000000; output <= "001";
elsif std_match(input, "11") then next_state <= s01000000; output <= "101";
end if;
when s00010000 =>
if std_match(input, "00") then next_state <= s00010000; output <= "100";
elsif std_match(input, "01") then next_state <= s00001000; output <= "101";
elsif std_match(input, "10") then next_state <= s00010000; output <= "010";
elsif std_match(input, "11") then next_state <= s00001000; output <= "101";
end if;
when s00001000 =>
if std_match(input, "00") then next_state <= s00100000; output <= "000";
elsif std_match(input, "01") then next_state <= s00010000; output <= "100";
elsif std_match(input, "10") then next_state <= s00100000; output <= "010";
elsif std_match(input, "11") then next_state <= s00100000; output <= "100";
end if;
when s00000100 =>
if std_match(input, "00") then next_state <= s00000010; output <= "000";
elsif std_match(input, "01") then next_state <= s00000001; output <= "000";
elsif std_match(input, "10") then next_state <= s00100000; output <= "010";
elsif std_match(input, "11") then next_state <= s00100000; output <= "100";
end if;
when s00000010 =>
if std_match(input, "00") then next_state <= s00010000; output <= "010";
elsif std_match(input, "01") then next_state <= s10000000; output <= "101";
elsif std_match(input, "10") then next_state <= s00001000; output <= "010";
elsif std_match(input, "11") then next_state <= s01000000; output <= "101";
end if;
when s00000001 =>
if std_match(input, "00") then next_state <= s00010000; output <= "100";
elsif std_match(input, "01") then next_state <= s00001000; output <= "100";
elsif std_match(input, "10") then next_state <= s00100000; output <= "010";
elsif std_match(input, "11") then next_state <= s00100000; output <= "100";
end if;
when others => next_state <= "---"; output <= "---";
end case;
end process;
end behaviour;
| agpl-3.0 | 07df1502899b1e5c8c1e6f768f103349 | 0.609821 | 3.479798 | false | false | false | false |
chastell/art-decomp | kiss/dk16_nov.vhd | 1 | 12,212 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk16_nov is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(2 downto 0)
);
end dk16_nov;
architecture behaviour of dk16_nov is
constant state_1: std_logic_vector(4 downto 0) := "00011";
constant state_2: std_logic_vector(4 downto 0) := "00100";
constant state_3: std_logic_vector(4 downto 0) := "01100";
constant state_4: std_logic_vector(4 downto 0) := "01110";
constant state_5: std_logic_vector(4 downto 0) := "00111";
constant state_6: std_logic_vector(4 downto 0) := "00010";
constant state_7: std_logic_vector(4 downto 0) := "10101";
constant state_8: std_logic_vector(4 downto 0) := "10110";
constant state_9: std_logic_vector(4 downto 0) := "00110";
constant state_10: std_logic_vector(4 downto 0) := "11011";
constant state_11: std_logic_vector(4 downto 0) := "01011";
constant state_12: std_logic_vector(4 downto 0) := "10000";
constant state_13: std_logic_vector(4 downto 0) := "00001";
constant state_14: std_logic_vector(4 downto 0) := "00101";
constant state_15: std_logic_vector(4 downto 0) := "00000";
constant state_16: std_logic_vector(4 downto 0) := "10010";
constant state_17: std_logic_vector(4 downto 0) := "01101";
constant state_18: std_logic_vector(4 downto 0) := "01000";
constant state_19: std_logic_vector(4 downto 0) := "01111";
constant state_20: std_logic_vector(4 downto 0) := "10111";
constant state_21: std_logic_vector(4 downto 0) := "01010";
constant state_22: std_logic_vector(4 downto 0) := "01001";
constant state_23: std_logic_vector(4 downto 0) := "11000";
constant state_24: std_logic_vector(4 downto 0) := "11010";
constant state_25: std_logic_vector(4 downto 0) := "11100";
constant state_26: std_logic_vector(4 downto 0) := "10100";
constant state_27: std_logic_vector(4 downto 0) := "11110";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "---";
case current_state is
when state_1 =>
if std_match(input, "00") then next_state <= state_3; output <= "001";
elsif std_match(input, "01") then next_state <= state_10; output <= "001";
elsif std_match(input, "10") then next_state <= state_11; output <= "001";
elsif std_match(input, "11") then next_state <= state_12; output <= "001";
end if;
when state_2 =>
if std_match(input, "00") then next_state <= state_1; output <= "001";
elsif std_match(input, "01") then next_state <= state_2; output <= "001";
elsif std_match(input, "10") then next_state <= state_8; output <= "001";
elsif std_match(input, "11") then next_state <= state_9; output <= "001";
end if;
when state_3 =>
if std_match(input, "00") then next_state <= state_4; output <= "001";
elsif std_match(input, "01") then next_state <= state_5; output <= "001";
elsif std_match(input, "10") then next_state <= state_6; output <= "001";
elsif std_match(input, "11") then next_state <= state_7; output <= "001";
end if;
when state_4 =>
if std_match(input, "00") then next_state <= state_4; output <= "010";
elsif std_match(input, "01") then next_state <= state_5; output <= "010";
elsif std_match(input, "10") then next_state <= state_6; output <= "010";
elsif std_match(input, "11") then next_state <= state_7; output <= "010";
end if;
when state_5 =>
if std_match(input, "00") then next_state <= state_1; output <= "010";
elsif std_match(input, "01") then next_state <= state_2; output <= "010";
elsif std_match(input, "10") then next_state <= state_16; output <= "010";
elsif std_match(input, "11") then next_state <= state_17; output <= "010";
end if;
when state_6 =>
if std_match(input, "00") then next_state <= state_3; output <= "010";
elsif std_match(input, "01") then next_state <= state_21; output <= "010";
elsif std_match(input, "10") then next_state <= state_10; output <= "010";
elsif std_match(input, "11") then next_state <= state_22; output <= "010";
end if;
when state_7 =>
if std_match(input, "00") then next_state <= state_9; output <= "010";
elsif std_match(input, "01") then next_state <= state_18; output <= "010";
elsif std_match(input, "10") then next_state <= state_19; output <= "010";
elsif std_match(input, "11") then next_state <= state_20; output <= "010";
end if;
when state_8 =>
if std_match(input, "00") then next_state <= state_15; output <= "010";
elsif std_match(input, "01") then next_state <= state_26; output <= "000";
elsif std_match(input, "10") then next_state <= state_13; output <= "010";
elsif std_match(input, "11") then next_state <= state_14; output <= "010";
end if;
when state_9 =>
if std_match(input, "00") then next_state <= state_1; output <= "000";
elsif std_match(input, "01") then next_state <= state_5; output <= "000";
elsif std_match(input, "10") then next_state <= state_6; output <= "000";
elsif std_match(input, "11") then next_state <= state_7; output <= "000";
end if;
when state_10 =>
if std_match(input, "00") then next_state <= state_14; output <= "000";
elsif std_match(input, "01") then next_state <= state_13; output <= "000";
elsif std_match(input, "10") then next_state <= state_1; output <= "000";
elsif std_match(input, "11") then next_state <= state_2; output <= "000";
end if;
when state_11 =>
if std_match(input, "00") then next_state <= state_3; output <= "000";
elsif std_match(input, "01") then next_state <= state_23; output <= "000";
elsif std_match(input, "10") then next_state <= state_24; output <= "000";
elsif std_match(input, "11") then next_state <= state_25; output <= "000";
end if;
when state_12 =>
if std_match(input, "00") then next_state <= state_20; output <= "000";
elsif std_match(input, "01") then next_state <= state_19; output <= "000";
elsif std_match(input, "10") then next_state <= state_18; output <= "000";
elsif std_match(input, "11") then next_state <= state_15; output <= "000";
end if;
when state_13 =>
if std_match(input, "00") then next_state <= state_3; output <= "101";
elsif std_match(input, "01") then next_state <= state_10; output <= "101";
elsif std_match(input, "10") then next_state <= state_11; output <= "101";
elsif std_match(input, "11") then next_state <= state_12; output <= "101";
end if;
when state_14 =>
if std_match(input, "00") then next_state <= state_1; output <= "101";
elsif std_match(input, "01") then next_state <= state_2; output <= "101";
elsif std_match(input, "10") then next_state <= state_8; output <= "101";
elsif std_match(input, "11") then next_state <= state_9; output <= "101";
end if;
when state_15 =>
if std_match(input, "00") then next_state <= state_4; output <= "101";
elsif std_match(input, "01") then next_state <= state_5; output <= "101";
elsif std_match(input, "10") then next_state <= state_6; output <= "101";
elsif std_match(input, "11") then next_state <= state_7; output <= "101";
end if;
when state_16 =>
if std_match(input, "00") then next_state <= state_20; output <= "000";
elsif std_match(input, "01") then next_state <= state_19; output <= "000";
elsif std_match(input, "10") then next_state <= state_13; output <= "010";
elsif std_match(input, "11") then next_state <= state_14; output <= "010";
end if;
when state_17 =>
if std_match(input, "00") then next_state <= state_15; output <= "010";
elsif std_match(input, "01") then next_state <= state_23; output <= "000";
elsif std_match(input, "10") then next_state <= state_18; output <= "000";
elsif std_match(input, "11") then next_state <= state_27; output <= "000";
end if;
when state_18 =>
if std_match(input, "00") then next_state <= state_4; output <= "100";
elsif std_match(input, "01") then next_state <= state_5; output <= "010";
elsif std_match(input, "10") then next_state <= state_6; output <= "100";
elsif std_match(input, "11") then next_state <= state_7; output <= "100";
end if;
when state_19 =>
if std_match(input, "00") then next_state <= state_18; output <= "100";
elsif std_match(input, "01") then next_state <= state_23; output <= "010";
elsif std_match(input, "10") then next_state <= state_24; output <= "100";
elsif std_match(input, "11") then next_state <= state_25; output <= "100";
end if;
when state_20 =>
if std_match(input, "00") then next_state <= state_19; output <= "100";
elsif std_match(input, "01") then next_state <= state_20; output <= "010";
elsif std_match(input, "10") then next_state <= state_9; output <= "100";
elsif std_match(input, "11") then next_state <= state_26; output <= "100";
end if;
when state_21 =>
if std_match(input, "00") then next_state <= state_2; output <= "100";
elsif std_match(input, "01") then next_state <= state_1; output <= "010";
elsif std_match(input, "10") then next_state <= state_13; output <= "100";
elsif std_match(input, "11") then next_state <= state_14; output <= "100";
end if;
when state_22 =>
if std_match(input, "00") then next_state <= state_3; output <= "000";
elsif std_match(input, "01") then next_state <= state_3; output <= "010";
elsif std_match(input, "10") then next_state <= state_15; output <= "100";
elsif std_match(input, "11") then next_state <= state_15; output <= "000";
end if;
when state_23 =>
if std_match(input, "00") then next_state <= state_2; output <= "100";
elsif std_match(input, "01") then next_state <= state_1; output <= "010";
elsif std_match(input, "10") then next_state <= state_13; output <= "010";
elsif std_match(input, "11") then next_state <= state_14; output <= "010";
end if;
when state_24 =>
if std_match(input, "00") then next_state <= state_14; output <= "000";
elsif std_match(input, "01") then next_state <= state_13; output <= "000";
elsif std_match(input, "10") then next_state <= state_13; output <= "100";
elsif std_match(input, "11") then next_state <= state_14; output <= "100";
end if;
when state_25 =>
if std_match(input, "00") then next_state <= state_15; output <= "010";
elsif std_match(input, "01") then next_state <= state_3; output <= "010";
elsif std_match(input, "10") then next_state <= state_15; output <= "000";
elsif std_match(input, "11") then next_state <= state_15; output <= "000";
end if;
when state_26 =>
if std_match(input, "00") then next_state <= state_20; output <= "000";
elsif std_match(input, "01") then next_state <= state_19; output <= "000";
elsif std_match(input, "10") then next_state <= state_18; output <= "000";
elsif std_match(input, "11") then next_state <= state_21; output <= "000";
end if;
when state_27 =>
if std_match(input, "00") then next_state <= state_15; output <= "010";
elsif std_match(input, "01") then next_state <= state_3; output <= "010";
elsif std_match(input, "10") then next_state <= state_13; output <= "100";
elsif std_match(input, "11") then next_state <= state_14; output <= "100";
end if;
when others => next_state <= "-----"; output <= "---";
end case;
end process;
end behaviour;
| agpl-3.0 | b95b8dcfeed833bb3188b44a00f5c215 | 0.585162 | 3.295197 | false | false | false | false |
ibm2030/IBM2030 | panel_LEDs.vhd | 1 | 10,199 | ---------------------------------------------------------------------------
-- Copyright © 2015 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: panel_LEDs.vhd
-- Creation Date: 16:08:00 16/06/2015
-- Description:
-- 360/30 Front Panel LED lamp drivers
-- This drives 256 front panel LEDs via Maxim SPI/I2C multiplexed drivers
-- There are two options:
-- MAX7219 8 x 8 multiplexed LEDs
-- MAX7951 Charlieplexed LEDs
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-09
-- Initial Release
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.Buses_package.all;
use work.Gates_package.EvenParity;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity panel_LEDs is
Generic (
Clock_divider : integer := 25; -- Default for 50MHz clock is 2, for 25MHz = 40ns = 20ns + 20ns. 25 gives 2MHz.
Number_LEDs : integer := 256
);
Port ( -- Lamp input vector
LEDs : in std_logic_vector(0 to Number_LEDs-1);
-- Other inputs
clk : in STD_LOGIC; -- 50MHz
-- Driver outputs
MAX7219_CLK : out std_logic;
MAX7219_DIN : out std_logic; -- LEDs 00-3F
MAX7219_LOAD : out std_logic; -- Data latched on rising edge
MAX6951_CLK : out std_logic;
MAX6951_DIN : out std_logic; --
MAX6951_CS0 : out std_logic; -- LEDs 00-3F Data latched on rising edge
MAX6951_CS1 : out std_logic; -- LEDs 40-7F Data latched on rising edge
MAX6951_CS2 : out std_logic; -- LEDs 80-BF Data latched on rising edge
MAX6951_CS3 : out std_logic -- LEDs C0-FF Data latched on rising edge
);
end panel_LEDs;
architecture Behavioral of panel_LEDs is
signal clk_out : std_logic := '0';
signal shift_reg64 : std_logic_vector(63 downto 0);
signal reg_counter : integer range 0 to 11 := 0;
signal bit_counter16 : integer range 0 to 16 := 0;
signal bit_counter64 : integer range 0 to 64 := 0;
-- MAX7219 data is 8b address and 8b data
-- Address is:
-- 00 No-op (unused)
-- 01 Digit 0 (in position 0)
-- ...
-- 08 Digit 7 (in position 7)
-- 09 Decode mode (fixed 00 in position 8)
-- 0A Intensity (fixed at 0F in position 9)
-- 0B Scan limit (fixed at 07 in position 10)
-- 0C Shutdown (fixed at 01 in position 11)
-- 0F Display test (fixed at 00 in position 12)
type registers7219 is array(0 to 3,0 to 12) of std_logic_vector(15 downto 0);
signal max7219_vector : registers7219 :=
(
0 => (
0 => "0000000100000000",
1 => "0000001000000000",
2 => "0000001100000000",
3 => "0000010000000000",
4 => "0000010100000000",
5 => "0000011000000000",
6 => "0000011100000000",
7 => "0000100000000000",
8 => "0000100100000000",
9 => "0000101000001111",
10 => "0000101100000111",
11 => "0000110000000001",
12 => "0000111100000000"
),
1 => (
0 => "0000000100000000",
1 => "0000001000000000",
2 => "0000001100000000",
3 => "0000010000000000",
4 => "0000010100000000",
5 => "0000011000000000",
6 => "0000011100000000",
7 => "0000100000000000",
8 => "0000100100000000",
9 => "0000101000001111",
10 => "0000101100000111",
11 => "0000110000000001",
12 => "0000111100000000"
),
2 => (
0 => "0000000100000000",
1 => "0000001000000000",
2 => "0000001100000000",
3 => "0000010000000000",
4 => "0000010100000000",
5 => "0000011000000000",
6 => "0000011100000000",
7 => "0000100000000000",
8 => "0000100100000000",
9 => "0000101000001111",
10 => "0000101100000111",
11 => "0000110000000001",
12 => "0000111100000000"
),
3 => (
0 => "0000000100000000",
1 => "0000001000000000",
2 => "0000001100000000",
3 => "0000010000000000",
4 => "0000010100000000",
5 => "0000011000000000",
6 => "0000011100000000",
7 => "0000100000000000",
8 => "0000100100000000",
9 => "0000101000001111",
10 => "0000101100000111",
11 => "0000110000000001",
12 => "0000111100000000"
)
);
-- MAX6951 data is 8b Address and 8b Data
-- Address is:
-- 00 No-op (unused)
-- 01 Decode mode (fixed at default)
-- 02 Intensity (fixed at 0F in position 8)
-- 03 Scan limit (fixed at 07 in position 9)
-- 04 Configuration (fixed at 01 in position 10)
-- 07 Display test (fixed at 00 in position 11)
-- 60 Digit 0 (in position 0)
-- ...
-- 67 Digit 7 (in position 0)
type registers6951 is array(0 to 3,0 to 11) of std_logic_vector(15 downto 0);
signal max6951_vector : registers6951 :=
(
0 => (
0 => "0110000000000000",
1 => "0110000100000000",
2 => "0110001000000000",
3 => "0110001100000000",
4 => "0110010000000000",
5 => "0110010100000000",
6 => "0110011000000000",
7 => "0110011100000000",
8 => "0000001000001111",
9 => "0000001100000111",
10 => "0000010000000001",
11 => "0000011100000000"
),
1 => (
0 => "0110000000000000",
1 => "0110000100000000",
2 => "0110001000000000",
3 => "0110001100000000",
4 => "0110010000000000",
5 => "0110010100000000",
6 => "0110011000000000",
7 => "0110011100000000",
8 => "0000001000001111",
9 => "0000001100000111",
10 => "0000010000000001",
11 => "0000011100000000"
),
2 => (
0 => "0110000000000000",
1 => "0110000100000000",
2 => "0110001000000000",
3 => "0110001100000000",
4 => "0110010000000000",
5 => "0110010100000000",
6 => "0110011000000000",
7 => "0110011100000000",
8 => "0000001000001111",
9 => "0000001100000111",
10 => "0000010000000001",
11 => "0000011100000000"
),
3 => (
0 => "0110000000000000",
1 => "0110000100000000",
2 => "0110001000000000",
3 => "0110001100000000",
4 => "0110010000000000",
5 => "0110010100000000",
6 => "0110011000000000",
7 => "0110011100000000",
8 => "0000001000001111",
9 => "0000001100000111",
10 => "0000010000000001",
11 => "0000011100000000"
)
);
begin
gen_clk : process (clk) is
variable divider : integer := Clock_divider;
begin
if rising_edge(clk) then
if (divider=0) then
divider := Clock_divider;
clk_out <= not clk_out;
MAX7219_CLK <= not clk_out;
MAX6951_CLK <= not clk_out;
else
divider := divider - 1;
end if;
end if;
end process;
max7219 : process (clk_out) is
begin
if falling_edge(clk_out) then
if bit_counter64=0 then
bit_counter64 <= 64;
case reg_counter is
when 0 to 7 =>
-- Mapping is:
-- b7 = DP = XX7
-- b6 = A = XX0
-- b5 = B = XX1
-- b4 = C = XX2
-- b3 = D = XX3
-- b2 = E = XX4
-- b1 = F = XX5
-- b0 = G = XX6
shift_reg64 <=
max7219_vector(3,reg_counter)(15 downto 8) & LEDs(reg_counter*8+192+7) & LEDs(reg_counter*8+192 to reg_counter*8+192+6) &
max7219_vector(2,reg_counter)(15 downto 8) & LEDs(reg_counter*8+128+7) & LEDs(reg_counter*8+128 to reg_counter*8+128+6) &
max7219_vector(1,reg_counter)(15 downto 8) & LEDs(reg_counter*8+ 64+7) & LEDs(reg_counter*8+ 64 to reg_counter*8+ 64+6) &
max7219_vector(0,reg_counter)(15 downto 8) & LEDs(reg_counter*8+ 0+7) & LEDs(reg_counter*8+ 0 to reg_counter*8+ 0+6);
when others =>
shift_reg64 <=
max7219_vector(3,reg_counter) &
max7219_vector(2,reg_counter) &
max7219_vector(1,reg_counter) &
max7219_vector(0,reg_counter);
end case;
if reg_counter=12 then
reg_counter <= 0;
else
reg_counter <= reg_counter + 1;
end if;
MAX7219_DIN <= '0';
MAX7219_Load <= '1';
else
bit_counter64 <= bit_counter64 - 1;
shift_reg64 <= shift_reg64(62 downto 0) & '0';
MAX7219_DIN <= shift_reg64(63);
MAX7219_Load <= '0';
end if;
end if;
end process;
max6951 : process (clk_out) is
variable dev_counter : integer range 0 to 3 := 3;
variable reg_counter : integer range 0 to 11 := 0;
variable bit_counter : integer range 0 to 16 := 16;
variable shift_reg : std_logic_vector(16 downto 0);
begin
if falling_edge(clk_out) then
if bit_counter=0 then
bit_counter := 16;
case reg_counter is
when 0 to 7 =>
shift_reg := '0' & max6951_vector(dev_counter,reg_counter)(15 downto 8) & LEDs(dev_counter*64+reg_counter*8 to dev_counter*64+reg_counter*8+7);
when others =>
shift_reg := '0' & max6951_vector(dev_counter,reg_counter);
end case;
if reg_counter=11 then
if dev_counter=0 then
dev_counter := 3;
else
dev_counter := dev_counter - 1;
end if;
reg_counter := 0;
else
reg_counter := reg_counter + 1;
end if;
else
bit_counter := bit_counter - 1;
shift_reg := shift_reg(15 downto 0) & '0';
end if;
if bit_counter=16 then
MAX6951_CS0 <= '1';
MAX6951_CS1 <= '1';
MAX6951_CS2 <= '1';
MAX6951_CS3 <= '1';
else
if dev_counter=0 then
MAX6951_CS0 <= '0';
else
MAX6951_CS0 <= '1';
end if;
if dev_counter=1 then
MAX6951_CS1 <= '0';
else
MAX6951_CS1 <= '1';
end if;
if dev_counter=2 then
MAX6951_CS2 <= '0';
else
MAX6951_CS2 <= '1';
end if;
if dev_counter=3 then
MAX6951_CS3 <= '0';
else
MAX6951_CS3 <= '1';
end if;
end if;
MAX6951_DIN <= shift_reg(16);
end if;
end process;
end behavioral;
| gpl-3.0 | 5b9dd837f37c1379fb5bb72169c54fde | 0.634572 | 3.172317 | false | false | false | false |
chastell/art-decomp | kiss/ex1_jed.vhd | 1 | 16,310 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex1_jed is
port(
clock: in std_logic;
input: in std_logic_vector(8 downto 0);
output: out std_logic_vector(18 downto 0)
);
end ex1_jed;
architecture behaviour of ex1_jed is
constant s1: std_logic_vector(4 downto 0) := "00111";
constant s2: std_logic_vector(4 downto 0) := "01001";
constant s4: std_logic_vector(4 downto 0) := "01111";
constant s3: std_logic_vector(4 downto 0) := "01101";
constant s5: std_logic_vector(4 downto 0) := "00110";
constant s6: std_logic_vector(4 downto 0) := "10100";
constant s7: std_logic_vector(4 downto 0) := "01011";
constant s8: std_logic_vector(4 downto 0) := "10110";
constant s9: std_logic_vector(4 downto 0) := "01100";
constant s10: std_logic_vector(4 downto 0) := "01110";
constant s11: std_logic_vector(4 downto 0) := "01000";
constant s12: std_logic_vector(4 downto 0) := "01010";
constant s13: std_logic_vector(4 downto 0) := "00010";
constant s14: std_logic_vector(4 downto 0) := "00001";
constant s15: std_logic_vector(4 downto 0) := "00100";
constant s16: std_logic_vector(4 downto 0) := "00000";
constant s17: std_logic_vector(4 downto 0) := "00101";
constant s18: std_logic_vector(4 downto 0) := "00011";
constant s19: std_logic_vector(4 downto 0) := "10010";
constant s20: std_logic_vector(4 downto 0) := "10000";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "-------------------";
case current_state is
when s1 =>
if std_match(input, "1011-----") then next_state <= s2; output <= "1111100000000000000";
elsif std_match(input, "11-------") then next_state <= s4; output <= "0000000000000000000";
elsif std_match(input, "1000-----") then next_state <= s3; output <= "1000011000000000000";
elsif std_match(input, "1010-----") then next_state <= s1; output <= "1000000000000000000";
elsif std_match(input, "1001-----") then next_state <= s2; output <= "1111100000000000000";
end if;
when s2 =>
if std_match(input, "-1--1----") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--1----") then next_state <= s6; output <= "0001000000000000000";
elsif std_match(input, "-0--0----") then next_state <= s2; output <= "0111100000000000000";
end if;
when s3 =>
if std_match(input, "-0-------") then next_state <= s7; output <= "0111101010000000000";
end if;
when s4 =>
if std_match(input, "-011-----") then next_state <= s2; output <= "1111100000000000000";
elsif std_match(input, "-000-----") then next_state <= s3; output <= "1000011000000000000";
elsif std_match(input, "-010-----") then next_state <= s1; output <= "1000000000000000000";
elsif std_match(input, "-001-----") then next_state <= s2; output <= "1111100000000000000";
end if;
when s5 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "----100--") then next_state <= s5; output <= "0001000000000000000";
elsif std_match(input, "----110--") then next_state <= s5; output <= "0001000001000000000";
elsif std_match(input, "----101--") then next_state <= s8; output <= "0000000000000000000";
elsif std_match(input, "----111--") then next_state <= s8; output <= "0000000001000000000";
end if;
when s6 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-00-11-1-") then next_state <= s9; output <= "0001101001111000000";
elsif std_match(input, "-0--11-0-") then next_state <= s6; output <= "0001000001000000000";
elsif std_match(input, "-01-11-1-") then next_state <= s10; output <= "0001100001111000000";
elsif std_match(input, "-00-10-1-") then next_state <= s9; output <= "0001101000111000000";
elsif std_match(input, "-0--10-0-") then next_state <= s6; output <= "0001000000000000000";
elsif std_match(input, "-01-10-1-") then next_state <= s10; output <= "0001100000111000000";
end if;
when s7 =>
if std_match(input, "-0--0----") then next_state <= s7; output <= "0111101000000000000";
elsif std_match(input, "-1--1----") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-00-1----") then next_state <= s11; output <= "0001001000000000000";
elsif std_match(input, "-01-1----") then next_state <= s12; output <= "0001000000000000000";
end if;
when s8 =>
if std_match(input, "-----1---") then next_state <= s1; output <= "0000000001000110000";
elsif std_match(input, "-----0---") then next_state <= s1; output <= "0000000000000110000";
end if;
when s9 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-01-11-1-") then next_state <= s13; output <= "0001100011001001000";
elsif std_match(input, "-0--11-0-") then next_state <= s9; output <= "0001001001001000000";
elsif std_match(input, "-00-11-1-") then next_state <= s14; output <= "0001101011001001000";
elsif std_match(input, "-01-10-1-") then next_state <= s13; output <= "0001100010001001000";
elsif std_match(input, "-0--10-0-") then next_state <= s9; output <= "0001001000001000000";
elsif std_match(input, "-00-10-1-") then next_state <= s14; output <= "0001101010001001000";
end if;
when s10 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-1-") then next_state <= s15; output <= "0001100001001001000";
elsif std_match(input, "-0--11-0-") then next_state <= s10; output <= "0001000001001000000";
elsif std_match(input, "-0--10-1-") then next_state <= s15; output <= "0001100000001001000";
elsif std_match(input, "-0--10-0-") then next_state <= s10; output <= "0001000000001000000";
end if;
when s11 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-00-11-11") then next_state <= s16; output <= "0001101011011000110";
elsif std_match(input, "-00-11-0-") then next_state <= s11; output <= "0001001001000000000";
elsif std_match(input, "-00-11-10") then next_state <= s16; output <= "0001101011011000010";
elsif std_match(input, "-01-11-11") then next_state <= s13; output <= "0001100011011000110";
elsif std_match(input, "-01-11-10") then next_state <= s13; output <= "0001100011011000010";
elsif std_match(input, "-01-11-0-") then next_state <= s12; output <= "0001000001000000000";
elsif std_match(input, "-00-10-11") then next_state <= s16; output <= "0001101010011000110";
elsif std_match(input, "-00-10-0-") then next_state <= s11; output <= "0001001000000000000";
elsif std_match(input, "-00-10-10") then next_state <= s16; output <= "0001101010011000010";
elsif std_match(input, "-01-10-11") then next_state <= s13; output <= "0001100010011000110";
elsif std_match(input, "-01-10-10") then next_state <= s13; output <= "0001100010011000010";
elsif std_match(input, "-01-10-0-") then next_state <= s12; output <= "0001000000000000000";
end if;
when s12 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-11") then next_state <= s15; output <= "0001100001011000110";
elsif std_match(input, "-0--11-0-") then next_state <= s12; output <= "0001000001000000000";
elsif std_match(input, "-0--11-10") then next_state <= s15; output <= "0001100001011000010";
elsif std_match(input, "-0--10-11") then next_state <= s15; output <= "0001100000011000110";
elsif std_match(input, "-0--10-0-") then next_state <= s12; output <= "0001000000000000000";
elsif std_match(input, "-0--10-10") then next_state <= s15; output <= "0001100000011000010";
end if;
when s13 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-11") then next_state <= s15; output <= "0001100001001000110";
elsif std_match(input, "-0--11-0-") then next_state <= s13; output <= "0001000001001000000";
elsif std_match(input, "-0--11-10") then next_state <= s15; output <= "0001100001001000010";
elsif std_match(input, "-0--10-11") then next_state <= s15; output <= "0001100000001000110";
elsif std_match(input, "-0--10-0-") then next_state <= s13; output <= "0001000000001000000";
elsif std_match(input, "-0--10-10") then next_state <= s15; output <= "0001100000001000010";
end if;
when s14 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-00-11-11") then next_state <= s16; output <= "0001101011001000110";
elsif std_match(input, "-0--11-0-") then next_state <= s14; output <= "0001001001001000000";
elsif std_match(input, "-00-11-10") then next_state <= s16; output <= "0001101011001000010";
elsif std_match(input, "-01-11-11") then next_state <= s13; output <= "0001100011001000110";
elsif std_match(input, "-01-11-10") then next_state <= s13; output <= "0001100011001000010";
elsif std_match(input, "-00-10-11") then next_state <= s16; output <= "0001101010001000110";
elsif std_match(input, "-0--10-0-") then next_state <= s14; output <= "0001001000001000000";
elsif std_match(input, "-00-10-10") then next_state <= s16; output <= "0001101010001000010";
elsif std_match(input, "-01-10-11") then next_state <= s13; output <= "0001100010001000110";
elsif std_match(input, "-01-10-10") then next_state <= s13; output <= "0001100010001000010";
end if;
when s15 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-1-") then next_state <= s17; output <= "0001000001001000001";
elsif std_match(input, "-0--11-0-") then next_state <= s15; output <= "0001000001001000000";
elsif std_match(input, "-0--10-1-") then next_state <= s17; output <= "0001000000001000001";
elsif std_match(input, "-0--10-0-") then next_state <= s15; output <= "0001000000001000000";
end if;
when s16 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-00-11-11") then next_state <= s16; output <= "0001101011001000110";
elsif std_match(input, "-0--11-0-") then next_state <= s16; output <= "0001001001001000000";
elsif std_match(input, "-00-11-10") then next_state <= s16; output <= "0001101011001000010";
elsif std_match(input, "-01-11-11") then next_state <= s13; output <= "0001100011001000110";
elsif std_match(input, "-01-11-10") then next_state <= s13; output <= "0001100011001000010";
elsif std_match(input, "-00-10-11") then next_state <= s16; output <= "0001101010001000110";
elsif std_match(input, "-0--10-0-") then next_state <= s16; output <= "0001001000001000000";
elsif std_match(input, "-00-10-10") then next_state <= s16; output <= "0001101010001000010";
elsif std_match(input, "-01-10-11") then next_state <= s13; output <= "0001100010001000110";
elsif std_match(input, "-01-10-10") then next_state <= s13; output <= "0001100010001000010";
end if;
when s17 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-0-") then next_state <= s17; output <= "0001000001001000001";
elsif std_match(input, "-0--11-1-") then next_state <= s18; output <= "0001000001001000001";
elsif std_match(input, "-0--10-0-") then next_state <= s17; output <= "0001000000001000001";
elsif std_match(input, "-0--10-1-") then next_state <= s18; output <= "0001000000001000001";
end if;
when s18 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-0-") then next_state <= s18; output <= "0001000001001000001";
elsif std_match(input, "-0--11-1-") then next_state <= s19; output <= "0011100001000000000";
elsif std_match(input, "-0--10-0-") then next_state <= s18; output <= "0001000000001000001";
elsif std_match(input, "-0--10-1-") then next_state <= s19; output <= "0011100000000000000";
end if;
when s19 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-0-") then next_state <= s19; output <= "0001000001000000000";
elsif std_match(input, "-0--11-1-") then next_state <= s20; output <= "0000000001000000000";
elsif std_match(input, "-0--10-0-") then next_state <= s19; output <= "0001000000000000000";
elsif std_match(input, "-0--10-1-") then next_state <= s20; output <= "0000000000000000000";
end if;
when s20 =>
if std_match(input, "-----1---") then next_state <= s1; output <= "0000000001000100000";
elsif std_match(input, "-----0---") then next_state <= s1; output <= "0000000000000100000";
end if;
when others => next_state <= "-----"; output <= "-------------------";
end case;
end process;
end behaviour;
| agpl-3.0 | 10a62c59ac5521320621d8926c5272e3 | 0.610791 | 3.630899 | false | false | false | false |
chastell/art-decomp | kiss/s820_jed.vhd | 1 | 29,266 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s820_jed is
port(
clock: in std_logic;
input: in std_logic_vector(17 downto 0);
output: out std_logic_vector(18 downto 0)
);
end s820_jed;
architecture behaviour of s820_jed is
constant s00000: std_logic_vector(4 downto 0) := "00000";
constant s01110: std_logic_vector(4 downto 0) := "11010";
constant s10000: std_logic_vector(4 downto 0) := "11001";
constant s10001: std_logic_vector(4 downto 0) := "01011";
constant s01111: std_logic_vector(4 downto 0) := "11101";
constant s00010: std_logic_vector(4 downto 0) := "10000";
constant s00001: std_logic_vector(4 downto 0) := "00001";
constant s00100: std_logic_vector(4 downto 0) := "00100";
constant s00011: std_logic_vector(4 downto 0) := "01101";
constant s00101: std_logic_vector(4 downto 0) := "00110";
constant s00110: std_logic_vector(4 downto 0) := "00011";
constant s11111: std_logic_vector(4 downto 0) := "10001";
constant s10111: std_logic_vector(4 downto 0) := "10011";
constant s01011: std_logic_vector(4 downto 0) := "00010";
constant s00111: std_logic_vector(4 downto 0) := "10010";
constant s11000: std_logic_vector(4 downto 0) := "10101";
constant s11011: std_logic_vector(4 downto 0) := "01000";
constant s11001: std_logic_vector(4 downto 0) := "10100";
constant s11010: std_logic_vector(4 downto 0) := "01010";
constant s11100: std_logic_vector(4 downto 0) := "01100";
constant s01100: std_logic_vector(4 downto 0) := "11000";
constant s01101: std_logic_vector(4 downto 0) := "11100";
constant s01000: std_logic_vector(4 downto 0) := "00111";
constant s01001: std_logic_vector(4 downto 0) := "00101";
constant s01010: std_logic_vector(4 downto 0) := "01001";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "-------------------";
case current_state is
when s00000 =>
if std_match(input, "-1---------------1") then next_state <= s00000; output <= "0000000000000110000";
elsif std_match(input, "-0-0------------11") then next_state <= s00000; output <= "0000000000000100001";
elsif std_match(input, "-0-0------------01") then next_state <= s00000; output <= "0000000000000100000";
elsif std_match(input, "-0-1------------01") then next_state <= s00000; output <= "0000000001000100000";
elsif std_match(input, "-0-1------------11") then next_state <= s00000; output <= "0000000000000100001";
elsif std_match(input, "-000------------00") then next_state <= s00000; output <= "0000000000000100000";
elsif std_match(input, "-010------------00") then next_state <= s01110; output <= "0000000000000100000";
elsif std_match(input, "-0-1------------00") then next_state <= s00000; output <= "0000000001000100000";
elsif std_match(input, "-1--------------00") then next_state <= s10000; output <= "0000000000000110000";
elsif std_match(input, "-0--------------10") then next_state <= s10001; output <= "0000000000000100001";
elsif std_match(input, "-1--------------10") then next_state <= s10000; output <= "0000000000000110000";
end if;
when s01110 =>
if std_match(input, "-----------------1") then next_state <= s00000; output <= "0000010000000000000";
elsif std_match(input, "-----------------0") then next_state <= s01111; output <= "0000010000000000000";
end if;
when s01111 =>
if std_match(input, "----------------11") then next_state <= s00000; output <= "0000000100000100000";
elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000000000100000";
elsif std_match(input, "----------------00") then next_state <= s00010; output <= "0000000000000100000";
elsif std_match(input, "----------------10") then next_state <= s00001; output <= "0000000100000100000";
end if;
when s00010 =>
if std_match(input, "--------------01-1") then next_state <= s00000; output <= "0000000000110000000";
elsif std_match(input, "--------------11-1") then next_state <= s00000; output <= "0000000000111000000";
elsif std_match(input, "---------------0-1") then next_state <= s00000; output <= "0000000000010000000";
elsif std_match(input, "--------------01-0") then next_state <= s00100; output <= "0000000000110000000";
elsif std_match(input, "--------------11-0") then next_state <= s00011; output <= "0000000000111000000";
elsif std_match(input, "---------------0-0") then next_state <= s00010; output <= "0000000000010000000";
end if;
when s00100 =>
if std_match(input, "----1------------1") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1------------0") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----0-0---------10") then next_state <= s00100; output <= "0000000000000001000";
elsif std_match(input, "----0-11-1-----110") then next_state <= s00100; output <= "0000000000000001000";
elsif std_match(input, "----0-1011-----110") then next_state <= s00100; output <= "0000000000000001000";
elsif std_match(input, "----0-1001-----110") then next_state <= s00101; output <= "0000000000000001000";
elsif std_match(input, "----0-1--0-----110") then next_state <= s00100; output <= "0000000000000001000";
elsif std_match(input, "----0-1--------010") then next_state <= s00100; output <= "0000000000000001000";
end if;
when s00001 =>
if std_match(input, "----------------01") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "----------------00") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "----------------11") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "----------------10") then next_state <= s00001; output <= "0000000000000000000";
end if;
when s00101 =>
if std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0----------010") then next_state <= s00101; output <= "0000000000000001000";
elsif std_match(input, "----0----------110") then next_state <= s00110; output <= "0000000000000001000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000000000001001";
end if;
when s00110 =>
if std_match(input, "----------------01") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1-----1----111") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----100--111") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0-----110--111") then next_state <= s00000; output <= "0000000000000001100";
elsif std_match(input, "----0-----1-1--111") then next_state <= s00000; output <= "0000000000000001100";
elsif std_match(input, "----1-----0-1--111") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----011--111") then next_state <= s00000; output <= "0000000000000001100";
elsif std_match(input, "----0-----001--111") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0-----0-0--111") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1-----0-0--111") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1------1----10") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0------1---010") then next_state <= s00110; output <= "0000000000000001000";
elsif std_match(input, "----0-----11---110") then next_state <= s11111; output <= "0000000000000001100";
elsif std_match(input, "----0-----011--110") then next_state <= s11111; output <= "0000000000000001100";
elsif std_match(input, "----0-----010--110") then next_state <= s10111; output <= "0000000000000001000";
elsif std_match(input, "----0------1----00") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----1------1----00") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----1------0-----0") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0------0---010") then next_state <= s00110; output <= "0000000000000001000";
elsif std_match(input, "----0------0---000") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----0------01--100") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----0-----001--110") then next_state <= s01011; output <= "0000000000000001000";
elsif std_match(input, "----0-----101--110") then next_state <= s11111; output <= "0000000000000001100";
elsif std_match(input, "----0-----000--110") then next_state <= s01011; output <= "0000000000000001000";
elsif std_match(input, "----0-----000--100") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----0-----100--110") then next_state <= s00111; output <= "0000000000000001000";
elsif std_match(input, "----0-----100--100") then next_state <= s00010; output <= "0000000000000001001";
end if;
when s11111 =>
if std_match(input, "-----------------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "1----------------0") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "0----------------0") then next_state <= s11111; output <= "0000000000000000000";
end if;
when s10111 =>
if std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0----------010") then next_state <= s10111; output <= "0000000000000001000";
elsif std_match(input, "----0--------1-110") then next_state <= s11000; output <= "0000000000000001000";
elsif std_match(input, "----0--------0-110") then next_state <= s11011; output <= "0000000000000001000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000000000001001";
end if;
when s11000 =>
if std_match(input, "----0----------111") then next_state <= s00000; output <= "1000000000000001000";
elsif std_match(input, "----0----------101") then next_state <= s00000; output <= "1000000000000001001";
elsif std_match(input, "----1----------1-1") then next_state <= s00000; output <= "1000000000000001001";
elsif std_match(input, "---------------001") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1----------1-0") then next_state <= s00001; output <= "1000000000000001001";
elsif std_match(input, "----1----------0-0") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "1000000000000001001";
elsif std_match(input, "----0----------110") then next_state <= s11001; output <= "1000000000000001000";
elsif std_match(input, "----0----------010") then next_state <= s11000; output <= "0000000000000001000";
end if;
when s11001 =>
if std_match(input, "---------------001") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "0100000000000001000";
elsif std_match(input, "----0----------101") then next_state <= s00000; output <= "0100000000000001001";
elsif std_match(input, "----1----------1-1") then next_state <= s00000; output <= "0100000000000001001";
elsif std_match(input, "----1----------0-0") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----1----------1-0") then next_state <= s00001; output <= "0100000000000001001";
elsif std_match(input, "----0----------110") then next_state <= s11010; output <= "0100000000000001000";
elsif std_match(input, "----0----------010") then next_state <= s11001; output <= "0000000000000001000";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "0100000000000001001";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000000000001001";
end if;
when s11010 =>
if std_match(input, "----------------01") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1------------0") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0----------010") then next_state <= s11010; output <= "0000000000000001000";
elsif std_match(input, "----0----------110") then next_state <= s11011; output <= "0000000000000001000";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000000000001001";
end if;
when s11011 =>
if std_match(input, "----1------------1") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-0---------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0-0---------01") then next_state <= s00000; output <= "0000000000000001010";
elsif std_match(input, "----0-10--------01") then next_state <= s00000; output <= "0000000000000001010";
elsif std_match(input, "----0-10--------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0-110-------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0-110-------01") then next_state <= s00000; output <= "0000000000000001010";
elsif std_match(input, "----0-1110------01") then next_state <= s00000; output <= "0000000000000001010";
elsif std_match(input, "----0-1110------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0-1111-----001") then next_state <= s00000; output <= "0000000000000001010";
elsif std_match(input, "----0-1111-----011") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0-1111-----1-1") then next_state <= s00000; output <= "0000000000000001010";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0-0--------010") then next_state <= s11011; output <= "0000000000000001000";
elsif std_match(input, "----0-0--------110") then next_state <= s11011; output <= "0000000000000001000";
elsif std_match(input, "----0-10-------010") then next_state <= s11011; output <= "0000000000000001000";
elsif std_match(input, "----0-10-------110") then next_state <= s11011; output <= "0000000000000001000";
elsif std_match(input, "----0-110------110") then next_state <= s11011; output <= "0000000000000001000";
elsif std_match(input, "----0-1110-----110") then next_state <= s11011; output <= "0000000000000001000";
elsif std_match(input, "----0-1111-----110") then next_state <= s11100; output <= "0000000000000001010";
elsif std_match(input, "----0-11-------010") then next_state <= s11011; output <= "0000000000000001000";
elsif std_match(input, "----0-----------00") then next_state <= s01100; output <= "0000000000000001010";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000000000001001";
end if;
when s11100 =>
if std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0-----------10") then next_state <= s11100; output <= "0000000000000001000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1-----------01") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----------00") then next_state <= s01100; output <= "0000000000000001000";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000000000001001";
end if;
when s01100 =>
if std_match(input, "-----0-----------0") then next_state <= s01101; output <= "0010100000000000000";
elsif std_match(input, "-----0-----------1") then next_state <= s00000; output <= "0010100000000000000";
elsif std_match(input, "-----1-----------0") then next_state <= s00010; output <= "0001100000000000000";
elsif std_match(input, "-----1-----------1") then next_state <= s00000; output <= "0001100000000000000";
end if;
when s01101 =>
if std_match(input, "-1---------------0") then next_state <= s10000; output <= "0000001010000010000";
elsif std_match(input, "-1---------------1") then next_state <= s00000; output <= "0000001010000010000";
elsif std_match(input, "-000-------------0") then next_state <= s01101; output <= "0000001010000000000";
elsif std_match(input, "-010-------------0") then next_state <= s01110; output <= "0000001010000000000";
elsif std_match(input, "-0-0-------------1") then next_state <= s00000; output <= "0000001010000000000";
elsif std_match(input, "-0-1--------------") then next_state <= s00000; output <= "0000001010000000000";
end if;
when s10000 =>
if std_match(input, "0----------------0") then next_state <= s10000; output <= "0000000000000000000";
elsif std_match(input, "0----------------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "1-----------------") then next_state <= s00000; output <= "0000000000000000000";
end if;
when s01011 =>
if std_match(input, "----1-----------01") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000000000001010";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1------------0") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0-----------00") then next_state <= s01100; output <= "0000000000000001010";
elsif std_match(input, "----0----------010") then next_state <= s01011; output <= "0000000000000001000";
elsif std_match(input, "----0----------110") then next_state <= s01011; output <= "0000000000000001000";
end if;
when s00111 =>
if std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0--------0-110") then next_state <= s01011; output <= "0000000000000001000";
elsif std_match(input, "----0--------1-110") then next_state <= s01000; output <= "0000000000000001000";
elsif std_match(input, "----0----------010") then next_state <= s00111; output <= "0000000000000001000";
elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000000000001001";
end if;
when s01000 =>
if std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0----------001") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1----------0-1") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0----------101") then next_state <= s00000; output <= "1000000000000001001";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "1000000000000001000";
elsif std_match(input, "----1----------1-1") then next_state <= s00000; output <= "1000000000000001001";
elsif std_match(input, "----0----------010") then next_state <= s01000; output <= "0000000000000001000";
elsif std_match(input, "----0----------110") then next_state <= s01001; output <= "1000000000000001000";
elsif std_match(input, "----1----------110") then next_state <= s00001; output <= "1000000000000001001";
elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----1----------100") then next_state <= s00001; output <= "1000000000000001001";
elsif std_match(input, "----1----------000") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "1000000000000001001";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000000000001001";
end if;
when s01001 =>
if std_match(input, "----0----------101") then next_state <= s00000; output <= "0100000000000001001";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "0100000000000001000";
elsif std_match(input, "----1----------1-1") then next_state <= s00000; output <= "0100000000000001001";
elsif std_match(input, "---------------001") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----1----------110") then next_state <= s00001; output <= "0100000000000001001";
elsif std_match(input, "----0----------010") then next_state <= s01001; output <= "0000000000000001000";
elsif std_match(input, "----0----------110") then next_state <= s01010; output <= "0100000000000001000";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "0100000000000001001";
elsif std_match(input, "----1----------100") then next_state <= s00001; output <= "0100000000000001001";
elsif std_match(input, "----1----------000") then next_state <= s00001; output <= "0000000000000001001";
end if;
when s01010 =>
if std_match(input, "----0----------010") then next_state <= s01010; output <= "0000000000000001000";
elsif std_match(input, "----0----------110") then next_state <= s01011; output <= "0000000000000001000";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----1-----------01") then next_state <= s00000; output <= "0000000000000001001";
end if;
when s00011 =>
if std_match(input, "----1----------111") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "---------------101") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0----------110") then next_state <= s00100; output <= "0000000000000001000";
elsif std_match(input, "----1----------110") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----1----------100") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "---------------001") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1----------0-0") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0----------010") then next_state <= s00011; output <= "0000000000000001000";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000000000001001";
end if;
when s10001 =>
if std_match(input, "-----------------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "----------------10") then next_state <= s10001; output <= "0000000000000000000";
elsif std_match(input, "----------------00") then next_state <= s00000; output <= "0000000000000000000";
end if;
when others => next_state <= "-----"; output <= "-------------------";
end case;
end process;
end behaviour;
| agpl-3.0 | cc20830efb1935d77be7387abc78cc7c | 0.582075 | 4.157102 | false | false | false | false |
mike7c2/befunge_processor | befunge_pc.vhd | 1 | 3,664 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:21:54 12/01/2014
-- Design Name:
-- Module Name: befunge_pc - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use ieee.STD_LOGIC_UNSIGNED;
--PC outputs x and y coordinates to read from grid
--dir input affects PC incrementing, it denotes the direction of execution in befunge_pc
--skip increments the pc twice to avoid a cell
--en, so that the operation of the pc can be clocked
entity befunge_pc is
generic(
grid_width : integer;
grid_height : integer
);
port(
clk : in std_logic;
reset : in std_logic;
pc_address : out integer range 0 to (grid_width*grid_height)-1;
dir : in std_logic_vector (1 downto 0);
skip : in std_logic;
en : in std_logic
);
end befunge_pc;
--dir:
--0 = right
--1 = down
--2 = left
--3 = up
architecture pc_v1 of befunge_pc is
signal pc_address_int : integer range 0 to (grid_width*grid_height)-1;
begin
pc_address <= pc_address_int;
process(reset,clk)
variable increment : integer range 1 to 2;
begin
if(reset = '1') then
pc_address_int <= 0;
increment := 1;
else
if rising_edge(clk) then
if ( en = '1' ) then
if ( skip = '1' ) then
increment := 2;
else
increment := 1;
end if;
if ( dir = "00" ) then --move right: add 1
pc_address_int <= pc_address_int + 1;
elsif ( dir = "01" ) then --move up: subtract grid_width
pc_address_int <= pc_address_int - 8;
elsif ( dir = "10" ) then --move left: subtract 1
pc_address_int <= pc_address_int - 1;
elsif (dir = "11") then --move down: add grid_width
pc_address_int <= pc_address_int + 8;
else --do nothing, laaaatchhh!!!!
pc_address_int <= pc_address_int;
end if;
end if;
end if;
end if;
end process;
end pc_v1;
architecture pc_v2 of befunge_pc is
signal pc_address_int : integer range 0 to (grid_width*grid_height)-1;
begin
pc_address <= pc_address_int;
process(reset,clk)
variable increment : integer range 1 to 2;
begin
if(reset = '1') then
pc_address_int <= 0;
increment := 1;
else
if rising_edge(clk) then
if ( en = '1' ) then
if ( skip = '1' ) then
increment := 2;
else
increment := 1;
end if;
if ( dir = "00" ) then --move right: add 1
pc_address_int <= pc_address_int + 1;
elsif ( dir = "01" ) then --move up: subtract grid_width
pc_address_int <= pc_address_int - 8;
elsif ( dir = "10" ) then --move left: subtract 1
pc_address_int <= pc_address_int - 1;
elsif (dir = "11") then --move down: add grid_width
pc_address_int <= pc_address_int + 8;
else --do nothing, laaaatchhh!!!!
pc_address_int <= pc_address_int;
end if;
end if;
end if;
end if;
end process;
end pc_v2;
| unlicense | 8084f4c08d37171941920d93a7866fb0 | 0.499181 | 3.602753 | false | false | false | false |
caiopo/battleship-vhdl | src/topo.vhd | 1 | 4,368 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity topo is
port ( SW : in std_logic_vector (17 downto 0);
HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7: out std_logic_vector(6 downto 0);
LEDR : out std_logic_vector (17 downto 0);
LEDG : out std_logic_vector (7 downto 0);
KEY: in std_logic_vector(3 downto 0);
clock_50: in std_logic
);
end topo;
architecture topo_stru of topo is
component contador_pontos is
port (compara, user, cont_match, clock, reset: in std_logic;
ledred, ledgrn: out std_logic_vector(7 downto 0)
);
end component;
component decod is
port (C: in std_logic_vector(3 downto 0);
S: out std_logic_vector(6 downto 0)
);
end component;
component vector_to_bcd is port(
input: in std_logic_vector(7 downto 0);
to_decod1, to_decod0: out std_logic_vector(3 downto 0)
);
end component;
component comparador is
port (compara, player, clock: in std_logic;
tiro: in std_logic_vector(13 downto 0);
address: in std_logic_vector(1 downto 0);
match: out std_logic
);
end component;
component fsm
port (dif: in std_logic_vector(1 downto 0);
clock, init, fire, reset: in std_logic;
memaddr: in std_logic_vector(1 downto 0);
linha: in std_logic_vector(13 downto 0);
displaycont: out std_logic_vector(7 downto 0);
displayaddr: out std_logic_vector(1 downto 0);
displaylinha: out std_logic_vector(13 downto 0);
user, compara: out std_logic;
difout: out std_logic_vector(1 downto 0)
);
end component;
signal jogador, comparar, tiro_match: std_logic;
signal dificuldade, addr_to_hex, jog_to_hex: std_logic_vector(1 downto 0);
signal to_contador: std_logic_vector(7 downto 0);
signal to_dec1, to_dec0, linha_to_decod: std_logic_vector(3 downto 0);
signal linha_to_number: std_logic_vector(13 downto 0);
begin
-- cria a fsm e designa os parametros. entradas: dificuldade, clock, init, fire, endereco de memoria, tiro
-- saidas: contador, endereco de memoria para o hex e comparador, linha de tiro para hex e comparador, jogador atual, enable do comparador e dificuldade
machine: fsm port map (SW(17 downto 16), clock_50, KEY(2), KEY(3), KEY(0), SW(15 downto 14), SW(13 downto 0), to_contador, addr_to_hex, linha_to_number, jogador, comparar, dificuldade);
-- entrega um vetor de 8 bits com o tempo restante para o conversor que transforma em 2 vetores de 4 bits com o mesmo valor em bcd
vector_bcd: vector_to_bcd port map (to_contador, to_dec1, to_dec0);
-- cria o comparador e liga ele aos seus parametros. entradas: enable, jogador atual, clock, linha de tiro e endereco de memoria
-- saidas: match
comp: comparador port map (comparar, jogador, clock_50, linha_to_number, addr_to_hex, tiro_match);
-- cria o contador de pontos e liga ele aos seus parametros. entradas: enable (caso esteja 1, ele "escuta" o que entra no match), jogador atual, match, clock e reset
-- saidas: ledr e ledg
pontuacao: contador_pontos port map (comparar, jogador, tiro_match, clock_50, KEY(0), LEDR(7 downto 0), LEDG(7 downto 0));
-- digito da unidade do contador para 7 segmentos
decod_hex0: decod port map(to_dec0, HEX0);
-- digito da dezena do contador para 7 segmentos
decod_hex1: decod port map(to_dec1, HEX1);
-- digito da dificuldade para 7 segmentos
decod_hex2: decod port map (("00"&dificuldade)+"1", HEX2);
-- "L"
HEX3 <= "1000111";
process(jogador) -- decodifica o std_logic que guarda o numero do jogado para 7 segmentos
begin
if jogador = '0' then
jog_to_hex <= "01";
else
jog_to_hex <= "10";
end if;
end process;
decod_hex4: decod port map ("00"&jog_to_hex, HEX4);
-- "U"
HEX5 <= "1000001";
process(linha_to_number) -- percorre os swiches 13 ao 0 para descobrir qual esta ativo, entao decodifica seu numero para 7 segmentos
variable i: integer;
variable position: integer;
begin
position := 0;
for i in 0 to 13 loop
if linha_to_number(i) = '1' then
position := i;
end if;
end loop;
linha_to_decod <= std_logic_vector(to_unsigned(position, linha_to_decod'length));
end process;
-- numero da coluna gerado pelo process acima
decod_hex6: decod port map (linha_to_decod, HEX6);
-- numero da linha da matriz escolhido pelos switches 15 e 14
decod_hex7: decod port map ("00"&addr_to_hex, HEX7);
end topo_stru; | mit | b76337579a5ff4e4dfbcbbd10d1216e3 | 0.699176 | 3.063114 | false | false | false | false |
thommyj/slotcar | de0/registerfile.vhd | 1 | 5,062 | --*****************************************************************************
--* Copyright (c) 2012 by Michael Fischer. All rights reserved.
--*
--* Redistribution and use in source and binary forms, with or without
--* modification, are permitted provided that the following conditions
--* are met:
--*
--* 1. Redistributions of source code must retain the above copyright
--* notice, this list of conditions and the following disclaimer.
--* 2. Redistributions in binary form must reproduce the above copyright
--* notice, this list of conditions and the following disclaimer in the
--* documentation and/or other materials provided with the distribution.
--* 3. Neither the name of the author nor the names of its contributors may
--* be used to endorse or promote products derived from this software
--* without specific prior written permiSS_asyncion.
--*
--* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
--* "AS IS" AND ANY EXPRESS_async OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
--* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS_async
--* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
--* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
--* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
--* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS_async
--* OF USE, DATA, OR PROFITS; OR BUSINESS_async INTERRUPTION) HOWEVER CAUSED
--* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
--* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
--* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSS_asyncIBILITY OF
--* SUCH DAMAGE.
--*
--*****************************************************************************
--* History:
--*
--* 14.07.2011 mifi First Version
--*****************************************************************************
--*****************************************************************************
--* DEFINE: Library *
--*****************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--*****************************************************************************
--* DEFINE: Entity *
--*****************************************************************************
entity registerfile is
port(
clk : in std_logic;
rst : in std_logic;
writer_data : in std_logic_vector(7 downto 0);
writer_address : in std_logic_vector(7 downto 0);
writer_enable : in std_logic;
writer2_data : in std_logic_vector(7 downto 0);
writer2_address: in std_logic_vector(7 downto 0);
writer2_enable : in std_logic;
reader_data : out std_logic_vector(7 downto 0);
reader_data_valid : out std_logic;
reader_read_req : in std_logic;
reader_address : in std_logic_vector(7 downto 0);
reader2_data : out std_logic_vector(7 downto 0);
reader2_data_valid : out std_logic;
reader2_read_req : in std_logic;
reader2_address : in std_logic_vector(7 downto 0)
);
end entity registerfile;
--*****************************************************************************
--* DEFINE: Architecture *
--****************************************************************************
architecture syn of registerfile is
--
-- Define all local signals (like static data) here
--
type registers_type is array(0 to 255) of std_logic_vector(7 downto 0); --9 + 14 bytes??
signal registers : registers_type;
begin
process(clk,rst)
begin
if(rst = '1') then
registers <= (others=> (others=>'0'));
reader_data_valid <= '0';
reader2_data_valid <= '0';
elsif rising_edge(clk) then
reader_data_valid <= '0';
reader2_data_valid <= '0';
if (reader_read_req = '1') then
reader_data <= registers(to_integer(unsigned(reader_address)));
reader_data_valid <= '1';
end if;
if (reader2_read_req = '1') then
reader2_data <= registers(to_integer(unsigned(reader2_address)));
reader2_data_valid <= '1';
end if;
if (writer_enable = '1') then
registers(to_integer(unsigned(writer_address))) <= writer_data;
--if reader request same address as writer is write to,
--shortcut data
if(reader_address = writer_address) then
reader_data <= writer_data;
end if;
if(reader2_address = writer_address) then
reader2_data <= writer_data;
end if;
elsif (writer2_enable = '1') then
registers(to_integer(unsigned(writer2_address))) <= writer2_data;
if(reader_address = writer2_address) then
reader_data <= writer2_data;
end if;
if(reader2_address = writer2_address) then
reader2_data <= writer2_data;
end if;
end if;
end if;
end process;
end architecture syn;
-- *** EOF ***
| mit | cc9c1b5d43a710095eca7bca455dfae4 | 0.559265 | 4.118796 | false | false | false | false |
chastell/art-decomp | kiss/tbk_nov.vhd | 1 | 133,046 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity tbk_nov is
port(
clock: in std_logic;
input: in std_logic_vector(5 downto 0);
output: out std_logic_vector(2 downto 0)
);
end tbk_nov;
architecture behaviour of tbk_nov is
constant st0: std_logic_vector(4 downto 0) := "00000";
constant st16: std_logic_vector(4 downto 0) := "01000";
constant st1: std_logic_vector(4 downto 0) := "10101";
constant st17: std_logic_vector(4 downto 0) := "01110";
constant st2: std_logic_vector(4 downto 0) := "11011";
constant st18: std_logic_vector(4 downto 0) := "01111";
constant st3: std_logic_vector(4 downto 0) := "11000";
constant st19: std_logic_vector(4 downto 0) := "01011";
constant st4: std_logic_vector(4 downto 0) := "11001";
constant st20: std_logic_vector(4 downto 0) := "01100";
constant st5: std_logic_vector(4 downto 0) := "10111";
constant st21: std_logic_vector(4 downto 0) := "01101";
constant st6: std_logic_vector(4 downto 0) := "11110";
constant st22: std_logic_vector(4 downto 0) := "01001";
constant st7: std_logic_vector(4 downto 0) := "11111";
constant st23: std_logic_vector(4 downto 0) := "00110";
constant st8: std_logic_vector(4 downto 0) := "11100";
constant st24: std_logic_vector(4 downto 0) := "00111";
constant st9: std_logic_vector(4 downto 0) := "10100";
constant st25: std_logic_vector(4 downto 0) := "00011";
constant st10: std_logic_vector(4 downto 0) := "11101";
constant st26: std_logic_vector(4 downto 0) := "00101";
constant st11: std_logic_vector(4 downto 0) := "10010";
constant st27: std_logic_vector(4 downto 0) := "00100";
constant st12: std_logic_vector(4 downto 0) := "10011";
constant st28: std_logic_vector(4 downto 0) := "00001";
constant st13: std_logic_vector(4 downto 0) := "11010";
constant st29: std_logic_vector(4 downto 0) := "10110";
constant st15: std_logic_vector(4 downto 0) := "10000";
constant st31: std_logic_vector(4 downto 0) := "01010";
constant st14: std_logic_vector(4 downto 0) := "10001";
constant st30: std_logic_vector(4 downto 0) := "00010";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "---";
case current_state is
when st0 =>
if std_match(input, "000000") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st0; output <= "000";
elsif std_match(input, "000010") then next_state <= st0; output <= "000";
elsif std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st1; output <= "000";
elsif std_match(input, "001000") then next_state <= st2; output <= "000";
elsif std_match(input, "010000") then next_state <= st3; output <= "000";
elsif std_match(input, "100000") then next_state <= st4; output <= "000";
elsif std_match(input, "000101") then next_state <= st5; output <= "000";
elsif std_match(input, "001001") then next_state <= st6; output <= "000";
elsif std_match(input, "010001") then next_state <= st7; output <= "000";
elsif std_match(input, "100001") then next_state <= st8; output <= "000";
elsif std_match(input, "000110") then next_state <= st9; output <= "000";
elsif std_match(input, "001010") then next_state <= st10; output <= "000";
elsif std_match(input, "010010") then next_state <= st11; output <= "000";
elsif std_match(input, "100010") then next_state <= st12; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st15; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st14; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st31; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st30; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st16 =>
if std_match(input, "000000") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st16; output <= "000";
elsif std_match(input, "000010") then next_state <= st16; output <= "000";
elsif std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st17; output <= "000";
elsif std_match(input, "001000") then next_state <= st18; output <= "000";
elsif std_match(input, "010000") then next_state <= st19; output <= "000";
elsif std_match(input, "100000") then next_state <= st20; output <= "000";
elsif std_match(input, "000101") then next_state <= st21; output <= "000";
elsif std_match(input, "001001") then next_state <= st22; output <= "000";
elsif std_match(input, "010001") then next_state <= st23; output <= "000";
elsif std_match(input, "100001") then next_state <= st24; output <= "000";
elsif std_match(input, "000110") then next_state <= st25; output <= "000";
elsif std_match(input, "001010") then next_state <= st26; output <= "000";
elsif std_match(input, "010010") then next_state <= st27; output <= "000";
elsif std_match(input, "100010") then next_state <= st28; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st15; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st14; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st31; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st30; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st1 =>
if std_match(input, "000000") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st1; output <= "000";
elsif std_match(input, "000010") then next_state <= st1; output <= "000";
elsif std_match(input, "000011") then next_state <= st1; output <= "000";
elsif std_match(input, "100011") then next_state <= st17; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st1; output <= "010";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st17 =>
if std_match(input, "000000") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st17; output <= "000";
elsif std_match(input, "000010") then next_state <= st17; output <= "000";
elsif std_match(input, "000011") then next_state <= st1; output <= "000";
elsif std_match(input, "100011") then next_state <= st17; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st17; output <= "010";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st2 =>
if std_match(input, "000000") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st2; output <= "000";
elsif std_match(input, "000010") then next_state <= st2; output <= "000";
elsif std_match(input, "000011") then next_state <= st2; output <= "000";
elsif std_match(input, "100011") then next_state <= st18; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st2; output <= "010";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st18 =>
if std_match(input, "000000") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st18; output <= "000";
elsif std_match(input, "000010") then next_state <= st18; output <= "000";
elsif std_match(input, "000011") then next_state <= st2; output <= "000";
elsif std_match(input, "100011") then next_state <= st18; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st18; output <= "010";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st3 =>
if std_match(input, "000000") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st3; output <= "000";
elsif std_match(input, "000010") then next_state <= st3; output <= "000";
elsif std_match(input, "000011") then next_state <= st3; output <= "000";
elsif std_match(input, "100011") then next_state <= st19; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st3; output <= "010";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st19 =>
if std_match(input, "000000") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st19; output <= "000";
elsif std_match(input, "000010") then next_state <= st19; output <= "000";
elsif std_match(input, "000011") then next_state <= st3; output <= "000";
elsif std_match(input, "100011") then next_state <= st19; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st19; output <= "010";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st4 =>
if std_match(input, "000000") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st4; output <= "000";
elsif std_match(input, "000010") then next_state <= st4; output <= "000";
elsif std_match(input, "000011") then next_state <= st4; output <= "000";
elsif std_match(input, "100011") then next_state <= st20; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st4; output <= "010";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st20 =>
if std_match(input, "000000") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st20; output <= "000";
elsif std_match(input, "000010") then next_state <= st20; output <= "000";
elsif std_match(input, "000011") then next_state <= st4; output <= "000";
elsif std_match(input, "100011") then next_state <= st20; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st20; output <= "010";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st5 =>
if std_match(input, "000001") then next_state <= st0; output <= "000";
elsif std_match(input, "000000") then next_state <= st5; output <= "000";
elsif std_match(input, "000010") then next_state <= st5; output <= "000";
elsif std_match(input, "000011") then next_state <= st5; output <= "000";
elsif std_match(input, "100011") then next_state <= st21; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st5; output <= "010";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st21 =>
if std_match(input, "000001") then next_state <= st16; output <= "000";
elsif std_match(input, "000000") then next_state <= st21; output <= "000";
elsif std_match(input, "000010") then next_state <= st21; output <= "000";
elsif std_match(input, "000011") then next_state <= st5; output <= "000";
elsif std_match(input, "100011") then next_state <= st21; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st21; output <= "010";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st6 =>
if std_match(input, "000001") then next_state <= st0; output <= "000";
elsif std_match(input, "000000") then next_state <= st6; output <= "000";
elsif std_match(input, "000010") then next_state <= st6; output <= "000";
elsif std_match(input, "000011") then next_state <= st6; output <= "000";
elsif std_match(input, "100011") then next_state <= st22; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st6; output <= "010";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st22 =>
if std_match(input, "000001") then next_state <= st16; output <= "000";
elsif std_match(input, "000000") then next_state <= st22; output <= "000";
elsif std_match(input, "000010") then next_state <= st22; output <= "000";
elsif std_match(input, "000011") then next_state <= st6; output <= "000";
elsif std_match(input, "100011") then next_state <= st22; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st22; output <= "010";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st7 =>
if std_match(input, "000001") then next_state <= st0; output <= "000";
elsif std_match(input, "000000") then next_state <= st7; output <= "000";
elsif std_match(input, "000010") then next_state <= st7; output <= "000";
elsif std_match(input, "000011") then next_state <= st7; output <= "000";
elsif std_match(input, "100011") then next_state <= st23; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st7; output <= "010";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st23 =>
if std_match(input, "000001") then next_state <= st16; output <= "000";
elsif std_match(input, "000000") then next_state <= st23; output <= "000";
elsif std_match(input, "000010") then next_state <= st23; output <= "000";
elsif std_match(input, "000011") then next_state <= st7; output <= "000";
elsif std_match(input, "100011") then next_state <= st23; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st23; output <= "010";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st8 =>
if std_match(input, "000001") then next_state <= st0; output <= "000";
elsif std_match(input, "000000") then next_state <= st8; output <= "000";
elsif std_match(input, "000010") then next_state <= st8; output <= "000";
elsif std_match(input, "000011") then next_state <= st8; output <= "000";
elsif std_match(input, "100011") then next_state <= st24; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st8; output <= "010";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st24 =>
if std_match(input, "000001") then next_state <= st16; output <= "000";
elsif std_match(input, "000000") then next_state <= st24; output <= "000";
elsif std_match(input, "000010") then next_state <= st24; output <= "000";
elsif std_match(input, "000011") then next_state <= st8; output <= "000";
elsif std_match(input, "100011") then next_state <= st24; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st24; output <= "010";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st9 =>
if std_match(input, "000010") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st9; output <= "000";
elsif std_match(input, "000000") then next_state <= st9; output <= "000";
elsif std_match(input, "000011") then next_state <= st9; output <= "000";
elsif std_match(input, "100011") then next_state <= st25; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st9; output <= "010";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st25 =>
if std_match(input, "000010") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st25; output <= "000";
elsif std_match(input, "000000") then next_state <= st25; output <= "000";
elsif std_match(input, "000011") then next_state <= st9; output <= "000";
elsif std_match(input, "100011") then next_state <= st25; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st25; output <= "010";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st10 =>
if std_match(input, "000010") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st10; output <= "000";
elsif std_match(input, "000000") then next_state <= st10; output <= "000";
elsif std_match(input, "000011") then next_state <= st10; output <= "000";
elsif std_match(input, "100011") then next_state <= st26; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st10; output <= "010";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st26 =>
if std_match(input, "000010") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st26; output <= "000";
elsif std_match(input, "000000") then next_state <= st26; output <= "000";
elsif std_match(input, "000011") then next_state <= st10; output <= "000";
elsif std_match(input, "100011") then next_state <= st26; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st26; output <= "010";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st11 =>
if std_match(input, "000010") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st11; output <= "000";
elsif std_match(input, "000000") then next_state <= st11; output <= "000";
elsif std_match(input, "000011") then next_state <= st11; output <= "000";
elsif std_match(input, "100011") then next_state <= st27; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st11; output <= "010";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st27 =>
if std_match(input, "000010") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st27; output <= "000";
elsif std_match(input, "000000") then next_state <= st27; output <= "000";
elsif std_match(input, "000011") then next_state <= st11; output <= "000";
elsif std_match(input, "100011") then next_state <= st27; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st27; output <= "010";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st12 =>
if std_match(input, "000010") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st12; output <= "000";
elsif std_match(input, "000000") then next_state <= st12; output <= "000";
elsif std_match(input, "000011") then next_state <= st12; output <= "000";
elsif std_match(input, "100011") then next_state <= st28; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st12; output <= "010";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st28 =>
if std_match(input, "000010") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st28; output <= "000";
elsif std_match(input, "000000") then next_state <= st28; output <= "000";
elsif std_match(input, "000011") then next_state <= st12; output <= "000";
elsif std_match(input, "100011") then next_state <= st28; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st28; output <= "010";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st13 =>
if std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st13; output <= "100";
elsif std_match(input, "000010") then next_state <= st13; output <= "100";
elsif std_match(input, "000000") then next_state <= st13; output <= "100";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st29 =>
if std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st29; output <= "100";
elsif std_match(input, "000010") then next_state <= st29; output <= "100";
elsif std_match(input, "000000") then next_state <= st29; output <= "100";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st15 =>
if std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st15; output <= "000";
elsif std_match(input, "000010") then next_state <= st15; output <= "000";
elsif std_match(input, "000000") then next_state <= st15; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st15; output <= "011";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st31; output <= "011";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st31 =>
if std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st31; output <= "000";
elsif std_match(input, "000010") then next_state <= st31; output <= "000";
elsif std_match(input, "000000") then next_state <= st31; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st15; output <= "011";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st31; output <= "011";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st14 =>
if std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st14; output <= "000";
elsif std_match(input, "000010") then next_state <= st14; output <= "000";
elsif std_match(input, "000000") then next_state <= st14; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st14; output <= "001";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st30; output <= "001";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st30 =>
if std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st30; output <= "000";
elsif std_match(input, "000010") then next_state <= st30; output <= "000";
elsif std_match(input, "000000") then next_state <= st30; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st14; output <= "001";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st30; output <= "001";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when others => next_state <= "-----"; output <= "---";
end case;
end process;
end behaviour;
| agpl-3.0 | d1219f65d60a4c085a99f56e6fe1b2ed | 0.590811 | 3.336744 | false | false | false | false |
mike7c2/befunge_processor | befunge_processor_tb.vhd | 1 | 2,374 | -- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
-- Component Declaration
component befunge_processor_v2 is
generic
(
grid_power : integer := 3;
word_size : integer := 8;
instruction_size : integer := 16;
stack_size : integer := 2048;
grid_width : integer := 80;
grid_height : integer := 25
);
port
(
FDE_OUT : OUT std_logic_vector(word_size-1 downto 0);
INSTRUCTION_OUT : OUT std_logic_vector(word_size-1 downto 0);
GRID_ADDRESS_OUT : OUT std_logic_vector((grid_power * 2)-1 downto 0);
clk,reset : in std_logic;
data_in : in std_logic_vector(word_size-1 downto 0);
data_out : out std_logic_vector(word_size-1 downto 0)
);
end component;
constant grid_power : integer := 3;
constant word_size : integer := 8;
constant instruction_size : integer := 16;
constant stack_size : integer := 2048;
constant grid_width : integer := 80;
constant grid_height : integer := 25;
signal clk,reset : std_logic;
signal data_in,data_out : std_logic_vector(word_size-1 downto 0);
signal FDE_OUT,INSTRUCTION_OUT : std_logic_vector(word_size-1 downto 0);
signal GRID_ADDRESS_OUT : std_logic_vector((grid_power * 2)-1 downto 0);
BEGIN
-- Component Instantiation
uut: befunge_processor_v2 generic map
(
grid_power => grid_power,
word_size => word_size,
instruction_size => instruction_size,
stack_size => stack_size,
grid_width => grid_width,
grid_height => grid_height
)
port map
(
FDE_OUT => FDE_OUT,
INSTRUCTION_OUT => INSTRUCTION_OUT,
GRID_ADDRESS_OUT => GRID_ADDRESS_OUT,
clk => clk,
reset => reset,
data_in => data_in,
data_out => data_out
);
-- Test Bench Statements
clock_process : PROCESS
BEGIN
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
END PROCESS clock_process;
reset_process : PROCESS
BEGIN
reset <= '1';
wait for 50 ns;
reset <= '0';
wait;
END PROCESS reset_process;
-- End Test Bench
END behavior;
| unlicense | 695a3b52afc70fcf3b8b8acdccbbd268 | 0.57877 | 3.292649 | false | true | false | false |
ibm2030/IBM2030 | FMD2030_5-06C-D.vhd | 1 | 14,952 | ---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-06C-D.vhd
-- Creation Date: 11/08/05
-- Description:
-- R Register and assembly, Main and Local (Auxiliary, Bump) Storage
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
-- Revision 1.1 2012-04-07
-- Implement external 64k + aux storage using StorageIn / StorageOut
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
use work.FLL;
ENTITY RREG_STG IS
port
(
-- Inputs
SALS : IN SALS_Bus;
CTRL : IN CTRL_REG;
SX2_RD_CYCLE : IN STD_LOGIC; -- 14D
SEL_T3 : IN STD_LOGIC;
GT_DETECTORS_TO_HR : IN STD_LOGIC; -- 14D
SEL_DATA_READY : IN STD_LOGIC; -- 03B
SEL_R_W_CTRL : IN STD_LOGIC; -- 12C
SX2_WR_CYCLE : IN STD_LOGIC; -- 14D
SX1_RD_CYCLE : IN STD_LOGIC; -- 12D
SX1_WR_CYCLE : IN STD_LOGIC; -- 12D
GT_DETECTORS_TO_GR : IN STD_LOGIC; -- 12D
EVEN_HR_0_7_BITS : IN STD_LOGIC; -- 13A
EVEN_GR_0_7_BITS : IN STD_LOGIC; -- 11A
HR_REG_0_7 : IN STD_LOGIC_VECTOR(0 TO 7); -- 13C
GR_REG_0_7 : IN STD_LOGIC_VECTOR(0 TO 7); -- 11C
DR_CORR_P_BIT : IN STD_LOGIC := '0'; -- HSMPX
HR_REG_P_BIT : IN STD_LOGIC; -- 13A
GR_REG_P_BIT : IN STD_LOGIC; -- 11A
STORE_HR : IN STD_LOGIC; -- 14D
STORE_GR : IN STD_LOGIC; -- 12D
STORE_R : IN STD_LOGIC; -- 03D
MEM_SELECT : IN STD_LOGIC; -- 03D
MAN_STORE_PWR : IN STD_LOGIC; -- 03D
E_SW_SEL_R : IN STD_LOGIC; -- 04C
GT_HSMPX_INTO_R_REG : IN STD_LOGIC := '0'; -- HSMPX
HSMPX_BUS : IN STD_LOGIC_VECTOR(0 to 8) := "000000000"; -- HSMPX
COMPUTE_CY_LCH : IN STD_LOGIC; -- 01C
CLOCK_OFF : IN STD_LOGIC; -- 08A
ALLOW_WRITE_1 : IN STD_LOGIC; -- 03D
PROT_LOC_CPU_OR_MPX : IN STD_LOGIC; -- 08B
USE_R : IN STD_LOGIC; -- 04D
MANUAL_DISPLAY : IN STD_LOGIC; -- 03D
MAN_STORE : IN STD_LOGIC; -- 03D
DATA_READY : IN STD_LOGIC; -- 03A
MACH_RST_SET_LCH_DLY : IN STD_LOGIC; -- 04B
SEL_SHARE_CYCLE : IN STD_LOGIC; -- 12D
MN_REG_CHK_SMPLD : IN STD_LOGIC; -- 07A
MEM_WRAP : IN STD_LOGIC; -- 03B
MAIN_STG : IN STD_LOGIC; -- 04D
MACH_RST_2A : IN STD_LOGIC; -- 06B
MACH_RST_6 : IN STD_LOGIC; -- 03D
ALLOW_WRITE : IN STD_LOGIC; -- 03D
-- STORAGE_BUS : IN STD_LOGIC_VECTOR(0 TO 8); -- 06D/07D -- Included here
CPU_SET_ALLOW_WR_LCH : IN STD_LOGIC; -- 03D
N1401_MODE : IN STD_LOGIC; -- 05A
MACH_RST_SW : IN STD_LOGIC; -- 03D
MN : IN STD_LOGIC_VECTOR(0 to 15); -- 07B
N_Z_BUS : IN STD_LOGIC_VECTOR(0 to 8);
USE_MAIN_MEM,USE_LOC_MAIN_MEM : IN STD_LOGIC; -- 05D
READ_1,READ_2,WRITE_1,WRITE_2 : IN STD_LOGIC := '0'; -- 05D Unused
PHASE_RD_1,PHASE_RD_2,PHASE_WR_1,PHASE_WR_2 : IN STD_LOGIC; -- 05D
-- Outputs
R_0 : OUT STD_LOGIC; -- 02A
R_REG_BUS : OUT STD_LOGIC_VECTOR(0 TO 8); -- 05C
P_8F_DETECTED : OUT STD_LOGIC; -- 03A
ALLOW_PROTECT : OUT STD_LOGIC; -- 03A7
STORE_BITS : OUT STD_LOGIC_VECTOR(0 TO 8); -- 11C
-- Interface to hardware
StorageIn : IN STORAGE_IN_INTERFACE;
StorageOut : OUT STORAGE_OUT_INTERFACE;
-- Clocks
-- P3 : IN STD_LOGIC;
T1,T2,T3,T4 : IN STD_LOGIC;
clk : IN STD_LOGIC
);
END RREG_STG;
ARCHITECTURE FMD OF RREG_STG IS
TYPE MAIN_STG_TYPE is ARRAY(0 to 1023) of STD_LOGIC_VECTOR(0 to 8);
-- TYPE MAIN_STG_TYPE is ARRAY(0 to 8191) of STD_LOGIC_VECTOR(0 to 8);
TYPE LOCAL_STG_TYPE is ARRAY(0 to 511) of STD_LOGIC_VECTOR(0 to 8);
SIGNAL SX1_STOR,SX2_STOR : STD_LOGIC;
SIGNAL INPUT_CORRECTED_P_BIT : STD_LOGIC;
SIGNAL GRP, HRP : STD_LOGIC;
SIGNAL INH_Z_BUS_SET_R : STD_LOGIC;
SIGNAL PROTECT_MEMORY : STD_LOGIC;
SIGNAL STORE_MAN : STD_LOGIC;
SIGNAL FORCE_Z_SET_R, FORCE_Z_SET_R2 : STD_LOGIC;
SIGNAL GT_R_1,GT_R : STD_LOGIC;
SIGNAL R_REG : STD_LOGIC_VECTOR(0 TO 8) := "000000001";
SIGNAL DET0F : STD_LOGIC;
SIGNAL GMWM_DETECTED : STD_LOGIC;
SIGNAL FORCE_MEM_SET_R,MEM_SET_R, MEM_SET_R2 : STD_LOGIC;
SIGNAL R_MUX,STORAGE_BUS : STD_LOGIC_VECTOR(0 to 8);
SIGNAL sALLOW_PROTECT : STD_LOGIC;
signal sSTORE_BITS : STD_LOGIC_VECTOR(0 to 8);
signal SX1_STOR_INPUT_DATA_Set,SX1_STOR_INPUT_DATA_Reset,SX2_STOR_INPUT_DATA_Set,SX2_STOR_INPUT_DATA_Reset,
PROT_MEM_Set,PROT_MEM_Reset,P_8F_DETECT_Set,P_8F_DETECT_Reset : STD_LOGIC;
SIGNAL LOCAL_STG_ARRAY : LOCAL_STG_TYPE;
SIGNAL MAIN_STG_ARRAY : MAIN_STG_TYPE := (
16#000# => "000000001", -- 00
16#001# => "000000010", -- 01
16#002# => "000000001", -- 00
16#003# => "000000001", -- 00
16#004# => "000000001", -- 00
16#005# => "000000001", -- 00
16#006# => "000000010", -- 01
16#007# => "000000001", -- 00
16#008# => "110100110", -- L
16#009# => "110100011", -- J
16#00A# => "111001100", -- W
16#00B# => "111100100", -- 2
16#00C# => "111100001", -- 0
16#00D# => "111100110", -- 3
16#00E# => "111100001", -- 0
-- The following program is from p73 of the System/360 programming tutorial
-- The "Indian" problem
-- Compound interest on $24 (price of Manhattan) at 3% for 338 years = $523998.22
16#100# => "000001011", -- 05 BALR 11,0
16#101# => "101100000", -- B0
16#102# => "111100100", -- F2
16#103# => "011000111", -- 63
16#104# => "101100000", -- B0
16#105# => "010010100", -- 4A
16#106# => "101100000", -- B0
16#107# => "010000000", -- 40
16#108# => "111100100", -- F2
16#109# => "000100101", -- 12
16#10A# => "101100000", -- B0
16#10B# => "010100010", -- 51
16#10C# => "101100000", -- B0
16#10D# => "010001001", -- 44
16#10E# => "111100100", -- F2
16#10F# => "011100101", -- 72
16#110# => "101100000", -- B0
16#111# => "010101101", -- 56
16#112# => "101100000", -- B0
16#113# => "010001111", -- 47
16#114# => "010011110", -- 4F
16#115# => "010000000", -- 40
16#116# => "101100000", -- B0
16#117# => "010101101", -- 56
16#118# => "111111001", -- FC
16#119# => "011000010", -- 61
16#11A# => "101100000", -- B0
16#11B# => "010010100", -- 4A
16#11C# => "101100000", -- B0
16#11D# => "010100010", -- 51
16#11E# => "111110101", -- FA
16#11F# => "011000010", -- 61
16#120# => "101100000", -- B0
16#121# => "010010100", -- 4A
16#122# => "101100000", -- B0
16#123# => "010111100", -- 5E
16#124# => "110100011", -- D1
16#125# => "000000001", -- 00
16#126# => "101100000", -- B0
16#127# => "010011110", -- 4F
16#128# => "101100000", -- B0
16#129# => "010100001", -- 50
16#12A# => "110100101", -- D2
16#12B# => "000001011", -- 05
16#12C# => "101100000", -- B0
16#12D# => "011000001", -- 60
16#12E# => "101100000", -- B0
16#12F# => "010010100", -- 4A
16#130# => "111110000", -- F8
16#131# => "011001011", -- 65
16#132# => "101100000", -- B0
16#133# => "010010100", -- 4A
16#134# => "101100000", -- B0
16#135# => "011000001", -- 60
16#136# => "010001100", -- 46
16#137# => "010000000", -- 40
16#138# => "101100000", -- B0
16#139# => "000101100", -- 16
16#13A# => "111100111", -- F3
16#13B# => "100001100", -- 86
16#13C# => "101100000", -- B0
16#13D# => "011001101", -- 66
16#13E# => "101100000", -- B0
16#13F# => "010010100", -- 4A
16#140# => "000001110", -- 07 BCR 15,11
16#141# => "111110110", -- FB
16#142# => "111100100", -- F2
16#143# => "111101000", -- F4
16#144# => "111100001", -- F0
16#145# => "110000001", -- C0
16#146# => "111100010", -- F1
16#147# => "111100001", -- F0
16#148# => "110000111", -- C3
16#149# => "111100111", -- F3
16#14A# => "111100111", -- F3
16#14B# => "110010000", -- C8
16#160# => "000001011", -- 05
16#161# => "000011001", -- 0C
others => "000000001"
);
signal dT1 : STD_LOGIC;
BEGIN
-- Fig 5-06C
SX2_STOR_INPUT_DATA_Set <= SX2_RD_CYCLE and SEL_T3;
SX2_STOR_INPUT_DATA_Reset <= (GT_DETECTORS_TO_HR and SEL_DATA_READY) or (not SEL_R_W_CTRL and not SX2_WR_CYCLE);
SX2_STOR_INPUT_DATA: entity FLL port map(SX2_STOR_INPUT_DATA_Set,SX2_STOR_INPUT_DATA_Reset,SX2_STOR); -- AE1G3,AE1L3
SX1_STOR_INPUT_DATA_Set <= SX1_RD_CYCLE and SEL_T3;
SX1_STOR_INPUT_DATA_Reset <= (GT_DETECTORS_TO_GR and SEL_DATA_READY) or (not SEL_R_W_CTRL and not SX1_WR_CYCLE);
SX1_STOR_INPUT_DATA: entity FLL port map(SX1_STOR_INPUT_DATA_Set,SX1_STOR_INPUT_DATA_Reset,SX1_STOR); -- AD2E4,AD2G4
INPUT_CORRECTED_P_BIT <= (SX2_STOR and EVEN_HR_0_7_BITS) or (SX1_STOR and EVEN_GR_0_7_BITS) or DR_CORR_P_BIT; -- AD2G4,AA1E7
HRP <= not SX2_STOR and HR_REG_P_BIT and STORE_HR; -- AA1F7
GRP <= not SX1_STOR and GR_REG_P_BIT and STORE_GR; -- AA1F7
sSTORE_BITS <= ((HR_REG_0_7 & INPUT_CORRECTED_P_BIT) and (0 TO 8 => STORE_HR)) or -- AA1G7
((GR_REG_0_7 & INPUT_CORRECTED_P_BIT) and (0 TO 8 => STORE_GR)) or -- AA1G6
("00000000" & HRP) or
("00000000" & GRP) or
(R_REG and (0 to 8 => STORE_R)); -- AA1G5
STORE_BITS <= sSTORE_BITS;
R_REG_BUS <= R_REG;
R_0 <= R_REG(0); -- AA3K6
INH_Z_BUS_SET_R <= CLOCK_OFF or (ALLOW_WRITE_1 and PROT_LOC_CPU_OR_MPX) or (USE_R and PROTECT_MEMORY); -- AB3D5
FORCE_Z_SET_R <= STORE_HR or STORE_GR or STORE_MAN or (not T1 and COMPUTE_CY_LCH and not INH_Z_BUS_SET_R) or (SALS.SALS_CM(1) and not INH_Z_BUS_SET_R); -- AA1F7,AA1J5
Delay_ZSetR: AR port map(FORCE_Z_SET_R,clk,FORCE_Z_SET_R2);
STORE_MAN <= (MEM_SELECT and MAN_STORE_PWR) or (MAN_STORE_PWR and E_SW_SEL_R); -- AA1H6
GT_R_1 <= '1' when STORE_MAN='1' or (CTRL.CTRL_CD="0111" and not INH_Z_BUS_SET_R='1') else '0'; -- AA1H7,AA1J4
GT_R <= (GT_R_1 and T4) or (GT_R_1 and MAN_STORE) or (DATA_READY and MEM_SET_R) or MACH_RST_SET_LCH_DLY; -- AA1G4
-- Temp debug replacing above line - without this the diags stop at B96 because ASCII latch never gets set
-- GT_R <= (GT_R_1 and T4) or (GT_R_1 and MAN_STORE) or (DATA_READY and MEM_SET_R and MANUAL_DISPLAY) or (DATA_READY and MEM_SET_R and P3) or MACH_RST_SET_LCH_DLY; -- AA1G4
RREG: PHV9 port map(R_MUX,GT_R,R_REG); -- AA1H4
sALLOW_PROTECT <= '1' when ((SALS.SALS_CM="010") or (SALS.SALS_CD="0111")) else '0'; -- AA2J3,AA2G5,AA2K4 ?? Extra inverter not required ??
ALLOW_PROTECT <= sALLOW_PROTECT;
PROT_MEM_Set <= MN_REG_CHK_SMPLD or (T2 and MEM_WRAP and MAIN_STG);
PROT_MEM_Reset <= MACH_RST_6 or (not ALLOW_WRITE and T4);
PROT_MEM: entity FLL port map(PROT_MEM_Set,PROT_MEM_Reset,PROTECT_MEMORY); -- AB3F5,AB3H6
-- If we have a protection violation, we must retain the location's value in R so that it can be written back, even if
-- R contained a new value destined for that location
FORCE_MEM_SET_R <= MANUAL_DISPLAY or (PROT_LOC_CPU_OR_MPX and sALLOW_PROTECT) or (USE_R and PROTECT_MEMORY and sALLOW_PROTECT); -- AA3L5
-- The following line determines whether the storage output data is actually gated into the R register
-- If you can understand this then you can understand anything in the 2030
-- By the time DATA_READY is active, the next CCROS word has been read in and it is this word which controls the gating
-- The next cycle after a storage read must always be a WRITE, COMPUTE or STORE (i.e. it can't be another READ)
-- If it is a STORE then the data is NOT gated to R, as R is about to be written into to storage
-- As the following cycle is not a read then the Alt CU decode is used, and if it is "GR" then the data is NOT gated to R (but to GR/HR instead)
-- However, if storage protection is activated, then the storage value is ALWAYS put into R so it can be rewritten by the subsequent WRITE or STORE
-- (this is what FORCE_MEM_SET_R does)
-- So MEM_SET_R<='1' when CU=X0|1X (i.e. not 01=GR) and CM/=X1X (i.e. not 010=STORE)
MEM_SET_R <= (FORCE_MEM_SET_R or SALS.SALS_CU(0) or not SALS.SALS_CU(1)) and (not SALS.SALS_CM(1) or FORCE_MEM_SET_R) and not SEL_SHARE_CYCLE; -- AA1J5
Delay_MemSetR: AR port map(MEM_SET_R,clk,MEM_SET_R2);
-- Input data (0 to 7) is inverted
R_MUX(0 to 7) <= ((0 to 7 => FORCE_Z_SET_R2) and not N_Z_BUS(0 to 7)) or ((0 to 7 => GT_HSMPX_INTO_R_REG) and HSMPX_BUS(0 to 7)) or ((0 to 7 => MEM_SET_R2) and STORAGE_BUS(0 to 7)); -- AA1G2 AA1H4
-- Input parity (8) is not inverted
R_MUX(8) <= (FORCE_Z_SET_R2 and N_Z_BUS(8)) or (GT_HSMPX_INTO_R_REG and HSMPX_BUS(8)) or (MEM_SET_R2 and STORAGE_BUS(8)) or MACH_RST_2A; -- AA1G2,AA1H4,AA1H2
-- Word Mark detection for 1401 usage
DET0F <= '1' when (STORAGE_BUS(1 to 7) = "0001111") and (DATA_READY='1') else '0'; -- AA1B7
GMWM: entity FLL port map(DET0F,CPU_SET_ALLOW_WR_LCH,GMWM_DETECTED); -- AA1F5
P_8F_DETECT_Set <= STORAGE_BUS(0) and MAIN_STG and N1401_MODE and DET0F;
P_8F_DETECT_Reset <= MACH_RST_SW or GMWM_DETECTED;
P_8F_DETECT: entity FLL port map(P_8F_DETECT_Set,P_8F_DETECT_Reset,P_8F_DETECTED); -- AA1F5
StorageOut.WriteData <= sSTORE_BITS;
StorageOut.MainStorage <= USE_MAIN_MEM;
StorageOut.ReadPulse <= PHASE_RD_1 and not DATA_READY; -- Drop ReadPulse when Data Ready goes active, this will latch input data
StorageOut.WritePulse <= PHASE_WR_1;
StorageOut.MSAR <= MN;
STORAGE_BUS <= StorageIn.ReadData when PHASE_RD_1='1' else "000000000"; -- Data is retained a bit after DATA_READY falls
STG_Wr: process (PHASE_WR_1)
begin
if (PHASE_WR_1'EVENT AND PHASE_WR_1='1') then
if (USE_MAIN_MEM='1') then
-- MAIN_STG_ARRAY(TO_INTEGER(UNSIGNED(MN(3 to 15)))) <= sSTORE_BITS;
else
-- LOCAL_STG_ARRAY(TO_INTEGER(UNSIGNED(MN(3) & MN(8 to 15)))) <= sSTORE_BITS;
end if;
end if;
end process;
STG_Rd: process (PHASE_RD_1,USE_MAIN_MEM,MAIN_STG_ARRAY,LOCAL_STG_ARRAY,MN,StorageIn.ReadData)
begin
if (PHASE_RD_1='1') then
if (USE_MAIN_MEM='1') then
-- STORAGE_BUS <= StorageIn.ReadData;
-- STORAGE_BUS <= MAIN_STG_ARRAY(TO_INTEGER(UNSIGNED(MN(3 to 15))));
else
-- STORAGE_BUS <= StorageIn.ReadData;
-- STORAGE_BUS <= LOCAL_STG_ARRAY(TO_INTEGER(UNSIGNED(MN(3) & MN(8 to 15))));
end if;
else
-- STORAGE_BUS <= "000000000";
end if;
end process;
END FMD;
| gpl-3.0 | d65eb441bd094de34783c8b81d1befa7 | 0.627809 | 2.62823 | false | false | false | false |
ibm2030/IBM2030 | FMD2030_5-03D.vhd | 1 | 9,132 | ---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-03D.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- Manual Controls - Front panel switches Display, Store & Reset
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY ManualControls IS
port
(
-- Inputs
E_SW_SEL_MAIN_STG,E_SW_SEL_AUX_STG : IN STD_LOGIC; -- 04C
E_CY_STOP_SMPL : IN STD_LOGIC; -- 03C
SEL_CHNL_DATA_XFER : IN STD_LOGIC; -- 12D
POWER_ON_RESET : IN STD_LOGIC; -- 14A
LOAD_KEY_SW : IN STD_LOGIC; -- 03C
CLOCK_OFF,CLOCK_ON : IN STD_LOGIC; -- 08A
WRITE_ECHO_1,WRITE_ECHO_2 : IN STD_LOGIC; -- 05D
READ_ECHO_1,READ_ECHO_2 : IN STD_LOGIC; -- 05D
CPU_READ_PWR : IN STD_LOGIC; -- 04D
SEL_AUX_RD_CALL : IN STD_LOGIC; -- 12C
SEL_WR_CALL : IN STD_LOGIC; -- 12C
ROAR_RESTT_STOR_BYPASS : IN STD_LOGIC;
RECYCLE_RST : IN STD_LOGIC; -- 04A
MAN_DSPLY_GUV_HUV : IN STD_LOGIC; -- 12C
CPU_WR_PWR : IN STD_LOGIC; -- 04D
LOAD_KEY_INLK : IN STD_LOGIC; -- 03C
POWER_OFF_SW : IN STD_LOGIC; -- 03C
IJ_SEL_SW,UV_SEL_SW : IN STD_LOGIC; -- 04C
SEL_AUX_WR_CALL : IN STD_LOGIC; -- 12C
USE_R : IN STD_LOGIC; -- 04D
SEL_T1 : IN STD_LOGIC;
CU_SALS : IN STD_LOGIC_VECTOR(0 to 1);
-- Switches
SW_DSPLY, SW_STORE,SW_SYS_RST : IN STD_LOGIC;
-- Outputs
MACH_RST_SW,MACH_RST_1,MACH_RST_3,MACH_RST_4,MACH_RST_5,MACH_RST_6,SYSTEM_RST_SW : OUT STD_LOGIC; -- Various
STG_MEM_SEL : OUT STD_LOGIC; -- 08D,04D,05B,06C
USE_MAN_DECODER_PWR : OUT STD_LOGIC; -- 04C,05C,05B
USE_MANUAL_DECODER : OUT STD_LOGIC; -- 04D,05B,04C,10C,07C,11C,05C
ALLOW_MAN_OPERATION : OUT STD_LOGIC; -- 03C,04A
MANUAL_DISPLAY : OUT STD_LOGIC; -- 06C,12C
MAN_STOR_OR_DSPLY : OUT STD_LOGIC; -- 04D,04A,06B,07B
MAN_STORE : OUT STD_LOGIC; -- 01C,06A,04B,06B,06C,01C,06A,04C
MAN_STORE_PWR : OUT STD_LOGIC; -- 05C,08B,06C,07B
STORE_S_REG_RST : OUT STD_LOGIC; -- 07B
CPU_SET_ALLOW_WR_LCH : OUT STD_LOGIC; -- 06C
MAN_RD_CALL : OUT STD_LOGIC; -- 05D,04D
GT_MAN_SET_MN : OUT STD_LOGIC; -- 07B
AUX_WRITE_CALL : OUT STD_LOGIC; -- 04B
ALLOW_WRITE : OUT STD_LOGIC; -- 05D,04A,06C,07A,04D,12C
ALLOW_WR_DLYD : OUT STD_LOGIC; -- 03A,04A,04D,12D,05D,03C,04B,06C,03B,04A
MANUAL_OPERATION : OUT STD_LOGIC; -- 03C
MAN_WRITE_CALL : OUT STD_LOGIC; -- 05D
STORE_R : OUT STD_LOGIC; -- 06C
-- Clocks
CONV_OSC : IN STD_LOGIC;
T1,T2 : IN STD_LOGIC;
Clk : IN STD_LOGIC -- 50MHz
);
END ManualControls;
ARCHITECTURE FMD OF ManualControls IS
signal AC1D4 : STD_LOGIC;
signal WRITE_ECHO,READ_ECHO : STD_LOGIC;
signal MAN_RD_INLK : STD_LOGIC;
signal MAN_RD_CALL_LCH : STD_LOGIC;
signal MAN_WR_CALL : STD_LOGIC;
signal MAN_WR_CALL_RST : STD_LOGIC;
signal sMACH_RST_SW,sMACH_RST_3,sSYSTEM_RST_SW : STD_LOGIC;
signal sSTG_MEM_SEL : STD_LOGIC;
signal sUSE_MANUAL_DECODER : STD_LOGIC;
signal sALLOW_MAN_OPERATION : STD_LOGIC;
signal sMANUAL_DISPLAY : STD_LOGIC;
signal sMAN_STOR_OR_DSPLY : STD_LOGIC;
signal sMAN_STORE,sMAN_STORE2 : STD_LOGIC;
signal sSTORE_S_REG_RST : STD_LOGIC;
signal sCPU_SET_ALLOW_WR_LCH : STD_LOGIC;
signal sMAN_RD_CALL : STD_LOGIC;
signal sALLOW_WRITE : STD_LOGIC;
signal sALLOW_WR : STD_LOGIC;
signal sSTORE_R : STD_LOGIC;
signal UMD_LCH_Set,UMD_LCH_Reset,MD_LCH_Set,MS_LCH_Set,AW_LCH_Set,AW_LCH_Reset,
MW_LCH_Set,MW_LCH_Reset,MRC_LCH_Set,MRC_LCH_Reset,SR_LCH_Set,SR_LCH_Reset : STD_LOGIC;
BEGIN
-- Fig 5-03D
-- USE MAN DECODER
sSTG_MEM_SEL <= E_SW_SEL_MAIN_STG or E_SW_SEL_AUX_STG; -- AC1H3
STG_MEM_SEL <= sSTG_MEM_SEL;
sALLOW_MAN_OPERATION <= (not E_CY_STOP_SMPL and not SEL_CHNL_DATA_XFER and CLOCK_OFF); -- AC1C4,AC1G3 ?? Removed a NOT here
ALLOW_MAN_OPERATION <= sALLOW_MAN_OPERATION;
UMD_LCH_Set <= (sALLOW_MAN_OPERATION and SW_DSPLY) or (sALLOW_MAN_OPERATION and SW_STORE);
UMD_LCH_Reset <= E_CY_STOP_SMPL or sMACH_RST_3;
UMD_LCH: entity work.FLL port map(UMD_LCH_Set,UMD_LCH_Reset, sUSE_MANUAL_DECODER); -- AC1G4
USE_MANUAL_DECODER <= sUSE_MANUAL_DECODER;
USE_MAN_DECODER_PWR <= not E_CY_STOP_SMPL and sUSE_MANUAL_DECODER; -- AC1J4
-- MAN DSPLY
AC1D4 <= (not E_CY_STOP_SMPL and not SEL_CHNL_DATA_XFER and CONV_OSC); -- AC1G2,AC1D4 -- Inverter removed ??
MD_LCH_Set <= CLOCK_OFF and SW_DSPLY and AC1D4;
MD_LCH: entity work.FLL port map(MD_LCH_Set,not SW_DSPLY,sMANUAL_DISPLAY); -- AC1G4 - FMD missing invert on Reset input ??
MANUAL_DISPLAY <= sMANUAL_DISPLAY;
-- MAN STORE R
sSTORE_S_REG_RST <= not CLOCK_ON and SW_STORE; -- AC1J6
STORE_S_REG_RST <= sSTORE_S_REG_RST;
MS_LCH_Set <= AC1D4 and sSTORE_S_REG_RST;
MS_LCH: entity work.FLL port map(MS_LCH_Set,not SW_STORE,sMAN_STORE); -- AC1E5
MAN_STORE <= sMAN_STORE;
-- MAN_STORE_PWR <= sMAN_STORE; -- AC1F3 -- Need to delay this a bit
MAN_STORE_DELAY: entity work.AR port map(sMAN_STORE,Clk,sMAN_STORE2); -- AC1F3
MAN_STORE2_DELAY: entity work.AR port map(sMAN_STORE2,Clk,MAN_STORE_PWR); -- AC1F3
sMAN_STOR_OR_DSPLY <= sMANUAL_DISPLAY or sMAN_STORE; -- AC1J2,AC1F3
MAN_STOR_OR_DSPLY <= sMAN_STOR_OR_DSPLY;
-- SYS RST
sSYSTEM_RST_SW <= SW_SYS_RST;
SYSTEM_RST_SW <= sSYSTEM_RST_SW;
sMACH_RST_SW <= SW_SYS_RST or POWER_ON_RESET or LOAD_KEY_SW;
MACH_RST_SW <= sMACH_RST_SW;
sMACH_RST_3 <= sMACH_RST_SW;
MACH_RST_1 <= sMACH_RST_3;
MACH_RST_3 <= sMACH_RST_3;
MACH_RST_4 <= sMACH_RST_3;
MACH_RST_5 <= sMACH_RST_3;
MACH_RST_6 <= sMACH_RST_3;
WRITE_ECHO <= WRITE_ECHO_1 or WRITE_ECHO_2; -- AA1J4
READ_ECHO <= READ_ECHO_1 or READ_ECHO_2; -- AA1K4
MAN_WR_CALL_RST <= WRITE_ECHO or sMACH_RST_3; -- AC1H3
sCPU_SET_ALLOW_WR_LCH <= (sMAN_STOR_OR_DSPLY and READ_ECHO) or (CPU_READ_PWR and T2); -- AA1K4 Wire-OR of negated signals
CPU_SET_ALLOW_WR_LCH <= sCPU_SET_ALLOW_WR_LCH;
-- ALLOW WR
AW_LCH_Set <= sCPU_SET_ALLOW_WR_LCH or SEL_AUX_RD_CALL;
AW_LCH_Reset <= sMACH_RST_3 or SEL_WR_CALL or MAN_WR_CALL or (ROAR_RESTT_STOR_BYPASS and RECYCLE_RST) or (CPU_WR_PWR and T2);
ALLOW_WRITE_LCH: entity work.FLL port map(AW_LCH_Set,AW_LCH_Reset,sALLOW_WRITE); -- AA1J2,AA1F6,AA1H3
ALLOW_WRITE <= sALLOW_WRITE;
DELAY_ALLOW_WR : entity work.AR port map (D=>sALLOW_WRITE,clk=>Clk,Q=>sALLOW_WR); -- AA1H2,AA1J7
ALLOW_WR_DLYD <= sALLOW_WR;
-- MAN WR CALL
MW_LCH_Set <= (sALLOW_WR and LOAD_KEY_INLK) or (sALLOW_WR and sSYSTEM_RST_SW) or (sALLOW_WR and POWER_OFF_SW) or (sMAN_STOR_OR_DSPLY and READ_ECHO);
MW_LCH_Reset <= CLOCK_ON or MAN_WR_CALL_RST;
MW_LCH: entity work.FLL port map(MW_LCH_Set,MW_LCH_Reset,MAN_WR_CALL); -- AC1J2,AC1F4,AC1H5
-- MAN RD INLK
MAN_RD_INLK_FL: entity work.FLL port map(MAN_RD_CALL_LCH,not sMAN_STOR_OR_DSPLY,MAN_RD_INLK); -- AC1F4
-- MAN RD CALL
MRC_LCH_Set <= sSTG_MEM_SEL and not MAN_RD_INLK and sMAN_STOR_OR_DSPLY;
MRC_LCH_Reset <= not sMAN_STOR_OR_DSPLY or READ_ECHO;
MAN_RD_CALL_FL: entity work.FLL port map(MRC_LCH_Set,MRC_LCH_Reset,MAN_RD_CALL_LCH); -- AC1J2,AC1E2
sMAN_RD_CALL <= MAN_RD_CALL_LCH and not sALLOW_WR; -- AC1J2
MAN_RD_CALL <= sMAN_RD_CALL;
GT_MAN_SET_MN <= (MAN_RD_CALL_LCH and sUSE_MANUAL_DECODER and not sALLOW_WR) or
(sMANUAL_DISPLAY and IJ_SEL_SW and not sALLOW_WR) or
(sMANUAL_DISPLAY and UV_SEL_SW and not sALLOW_WR)
or MAN_DSPLY_GUV_HUV; -- AC1H4,AC1G3
AUX_WRITE_CALL <= (CPU_WR_PWR and T2) or SEL_AUX_WR_CALL; -- AA1K4,AA1C3
MANUAL_OPERATION <= sMAN_RD_CALL or MAN_WR_CALL or MAN_WR_CALL_RST or READ_ECHO;
-- STORE R
SR_LCH_Set <= MAN_WR_CALL or (T1 and USE_R);
SR_LCH_Reset <= SEL_T1 or (T1 and not CU_SALS(0) and CU_SALS(1));
SR_LCH: entity work.FLL port map(SR_LCH_Set,SR_LCH_Reset,sSTORE_R); -- 06C
STORE_R <= sSTORE_R;
MAN_WRITE_CALL <= not READ_ECHO and MAN_WR_CALL and sSTORE_R; -- AC1G3
END FMD;
| gpl-3.0 | 8f44e88ccd5534d356fe32a80247a645 | 0.662615 | 2.605421 | false | false | false | false |
chastell/art-decomp | kiss/sand_jed.vhd | 1 | 20,706 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity sand_jed is
port(
clock: in std_logic;
input: in std_logic_vector(10 downto 0);
output: out std_logic_vector(8 downto 0)
);
end sand_jed;
architecture behaviour of sand_jed is
constant st0: std_logic_vector(4 downto 0) := "00101";
constant st5: std_logic_vector(4 downto 0) := "00010";
constant st1: std_logic_vector(4 downto 0) := "00001";
constant st2: std_logic_vector(4 downto 0) := "00011";
constant st4: std_logic_vector(4 downto 0) := "01001";
constant st3: std_logic_vector(4 downto 0) := "10001";
constant st31: std_logic_vector(4 downto 0) := "00110";
constant st25: std_logic_vector(4 downto 0) := "10011";
constant st19: std_logic_vector(4 downto 0) := "01011";
constant st6: std_logic_vector(4 downto 0) := "10010";
constant st29: std_logic_vector(4 downto 0) := "00111";
constant st23: std_logic_vector(4 downto 0) := "10110";
constant st17: std_logic_vector(4 downto 0) := "11010";
constant st13: std_logic_vector(4 downto 0) := "11000";
constant st27: std_logic_vector(4 downto 0) := "01010";
constant st21: std_logic_vector(4 downto 0) := "01100";
constant st15: std_logic_vector(4 downto 0) := "01110";
constant st12: std_logic_vector(4 downto 0) := "10000";
constant st10: std_logic_vector(4 downto 0) := "10100";
constant st7: std_logic_vector(4 downto 0) := "00100";
constant st8: std_logic_vector(4 downto 0) := "00000";
constant st9: std_logic_vector(4 downto 0) := "01000";
constant st11: std_logic_vector(4 downto 0) := "10101";
constant st14: std_logic_vector(4 downto 0) := "11100";
constant st16: std_logic_vector(4 downto 0) := "11110";
constant st18: std_logic_vector(4 downto 0) := "11011";
constant st20: std_logic_vector(4 downto 0) := "01101";
constant st22: std_logic_vector(4 downto 0) := "11101";
constant st24: std_logic_vector(4 downto 0) := "10111";
constant st26: std_logic_vector(4 downto 0) := "11001";
constant st28: std_logic_vector(4 downto 0) := "01111";
constant st30: std_logic_vector(4 downto 0) := "11111";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "---------";
case current_state is
when st0 =>
if std_match(input, "---------0-") then next_state <= st0; output <= "000001---";
elsif std_match(input, "----0----1-") then next_state <= st0; output <= "000001---";
elsif std_match(input, "----1---11-") then next_state <= st5; output <= "011001000";
elsif std_match(input, "----1---01-") then next_state <= st1; output <= "11-001000";
end if;
when st1 =>
if std_match(input, "0000---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0000---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "0001---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0001---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "0010---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0010---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "0011---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0011---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "0100---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0100---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "0101---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0101---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "0110---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0110---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "0111---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0111---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "1000---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "1000---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "1001---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "1001---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "1010---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "1010---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "1011---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "1011---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "1100---0---") then next_state <= st4; output <= "1010-0100";
elsif std_match(input, "1101---0---") then next_state <= st3; output <= "0000-0110";
elsif std_match(input, "1111--10---") then next_state <= st0; output <= "11-0---01";
elsif std_match(input, "1111--00---") then next_state <= st1; output <= "11-0-0000";
elsif std_match(input, "-------1---") then next_state <= st0; output <= "11-0-----";
end if;
when st2 =>
if std_match(input, "-------0-0-") then next_state <= st2; output <= "0000-0000";
elsif std_match(input, "-------0-10") then next_state <= st1; output <= "11-0-0000";
elsif std_match(input, "----0-00-11") then next_state <= st1; output <= "11-0-1000";
elsif std_match(input, "----1-00-11") then next_state <= st2; output <= "0000-0000";
elsif std_match(input, "------10-11") then next_state <= st0; output <= "11-0---01";
elsif std_match(input, "-------1---") then next_state <= st0; output <= "11-0-----";
end if;
when st3 =>
if std_match(input, "------10--1") then next_state <= st0; output <= "11-0---01";
elsif std_match(input, "-----010--0") then next_state <= st3; output <= "---0-0000";
elsif std_match(input, "-----110--0") then next_state <= st1; output <= "11-0-0000";
elsif std_match(input, "----1-00--1") then next_state <= st3; output <= "---0-0000";
elsif std_match(input, "----0-00--1") then next_state <= st1; output <= "11-0-1000";
elsif std_match(input, "------00--0") then next_state <= st1; output <= "11-0-0000";
elsif std_match(input, "-------1---") then next_state <= st0; output <= "11-0-----";
end if;
when st4 =>
if std_match(input, "------10-00") then next_state <= st4; output <= "0000-0000";
elsif std_match(input, "------10-01") then next_state <= st0; output <= "11-0---01";
elsif std_match(input, "------00-00") then next_state <= st1; output <= "11-0-0000";
elsif std_match(input, "----1-00--1") then next_state <= st4; output <= "---0-0000";
elsif std_match(input, "----0-00--1") then next_state <= st3; output <= "11-0-0000";
elsif std_match(input, "------10-1-") then next_state <= st1; output <= "11-0-0000";
elsif std_match(input, "-------1---") then next_state <= st0; output <= "11-0---00";
end if;
when st5 =>
if std_match(input, "0000-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "0000-----1-") then next_state <= st31; output <= "010110100";
elsif std_match(input, "0001-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "0001-----1-") then next_state <= st25; output <= "010110100";
elsif std_match(input, "0010-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "0010-----1-") then next_state <= st19; output <= "010110100";
elsif std_match(input, "0011-------") then next_state <= st6; output <= "000100100";
elsif std_match(input, "0100-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "0100-----1-") then next_state <= st29; output <= "010110100";
elsif std_match(input, "0101-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "0101-----1-") then next_state <= st23; output <= "010110100";
elsif std_match(input, "0110-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "0110-----1-") then next_state <= st17; output <= "010110100";
elsif std_match(input, "0111-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "0111-----1-") then next_state <= st13; output <= "010110100";
elsif std_match(input, "1000-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "1000-----1-") then next_state <= st27; output <= "010110100";
elsif std_match(input, "1001-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "1001-----1-") then next_state <= st21; output <= "010110100";
elsif std_match(input, "1010-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "1010-----1-") then next_state <= st15; output <= "010110100";
elsif std_match(input, "1011-------") then next_state <= st6; output <= "000100100";
elsif std_match(input, "1100-------") then next_state <= st12; output <= "101100100";
elsif std_match(input, "1101-------") then next_state <= st10; output <= "011100110";
elsif std_match(input, "1111-------") then next_state <= st7; output <= "011100000";
end if;
when st6 =>
if std_match(input, "----------0") then next_state <= st5; output <= "000100000";
elsif std_match(input, "----0-0---1") then next_state <= st5; output <= "000101000";
elsif std_match(input, "----1-0---1") then next_state <= st7; output <= "011101000";
end if;
when st7 =>
if std_match(input, "-----1---1-") then next_state <= st8; output <= "100000000";
elsif std_match(input, "-----0---1-") then next_state <= st0; output <= "10000--01";
elsif std_match(input, "---------0-") then next_state <= st7; output <= "000100000";
end if;
when st8 =>
if std_match(input, "0000-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "00000----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "00001----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "0001-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "00010----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "00011----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "0010-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "00100----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "00101----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "0011-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "00110----1-") then next_state <= st9; output <= "---000100";
elsif std_match(input, "00111----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "0100-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "01000----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "01001----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "0101-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "01010----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "01011----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "0110-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "01100----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "01101----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "0111-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "01110----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "01111----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "1000-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "10000----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "10001----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "1001-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "10010----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "10011----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "1010-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "10100----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "10101----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "1011-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "10110----1-") then next_state <= st9; output <= "---000100";
elsif std_match(input, "10111----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "1100-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "11000----1-") then next_state <= st9; output <= "---000100";
elsif std_match(input, "11001----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "1101-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "11010----1-") then next_state <= st9; output <= "---000100";
elsif std_match(input, "11011----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "1111-------") then next_state <= st8; output <= "000000000";
end if;
when st9 =>
if std_match(input, "----------1") then next_state <= st8; output <= "001001000";
elsif std_match(input, "----------0") then next_state <= st8; output <= "000000000";
end if;
when st10 =>
if std_match(input, "------1--10") then next_state <= st11; output <= "---000010";
elsif std_match(input, "------1--00") then next_state <= st10; output <= "000100000";
elsif std_match(input, "------1---1") then next_state <= st0; output <= "10000--01";
elsif std_match(input, "------0---0") then next_state <= st5; output <= "100100000";
elsif std_match(input, "----0-0---1") then next_state <= st5; output <= "100101000";
elsif std_match(input, "----1-0---1") then next_state <= st10; output <= "---101000";
end if;
when st11 =>
if std_match(input, "-----0-----") then next_state <= st11; output <= "---000000";
elsif std_match(input, "-----1-----") then next_state <= st5; output <= "011100000";
end if;
when st12 =>
if std_match(input, "------1--10") then next_state <= st5; output <= "001100000";
elsif std_match(input, "------1--00") then next_state <= st12; output <= "000100000";
elsif std_match(input, "------1---1") then next_state <= st7; output <= "01110--00";
elsif std_match(input, "------0---0") then next_state <= st5; output <= "100100000";
elsif std_match(input, "----0-0---1") then next_state <= st5; output <= "100101000";
elsif std_match(input, "----1-0---1") then next_state <= st12; output <= "---101000";
end if;
when st13 =>
if std_match(input, "---------0-") then next_state <= st13; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st14; output <= "001100000";
end if;
when st14 =>
if std_match(input, "---------0-") then next_state <= st14; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st15; output <= "010110000";
end if;
when st15 =>
if std_match(input, "---------0-") then next_state <= st15; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st16; output <= "001100000";
end if;
when st16 =>
if std_match(input, "---------0-") then next_state <= st16; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st17; output <= "010110000";
end if;
when st17 =>
if std_match(input, "---------0-") then next_state <= st17; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st18; output <= "001100000";
end if;
when st18 =>
if std_match(input, "---------0-") then next_state <= st18; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st19; output <= "010110000";
end if;
when st19 =>
if std_match(input, "---------0-") then next_state <= st19; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st20; output <= "001100000";
end if;
when st20 =>
if std_match(input, "---------0-") then next_state <= st20; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st21; output <= "010110000";
end if;
when st21 =>
if std_match(input, "---------0-") then next_state <= st21; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st22; output <= "001100000";
end if;
when st22 =>
if std_match(input, "---------0-") then next_state <= st22; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st23; output <= "010110000";
end if;
when st23 =>
if std_match(input, "---------0-") then next_state <= st23; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st24; output <= "001100000";
end if;
when st24 =>
if std_match(input, "---------0-") then next_state <= st24; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st25; output <= "010110000";
end if;
when st25 =>
if std_match(input, "---------0-") then next_state <= st25; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st26; output <= "001100000";
end if;
when st26 =>
if std_match(input, "---------0-") then next_state <= st26; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st27; output <= "010110000";
end if;
when st27 =>
if std_match(input, "---------0-") then next_state <= st27; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st28; output <= "001100000";
end if;
when st28 =>
if std_match(input, "---------0-") then next_state <= st28; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st29; output <= "010110000";
end if;
when st29 =>
if std_match(input, "---------0-") then next_state <= st29; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st30; output <= "001100000";
end if;
when st30 =>
if std_match(input, "---------0-") then next_state <= st30; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st31; output <= "010110000";
end if;
when st31 =>
if std_match(input, "---------0-") then next_state <= st31; output <= "000110000";
elsif std_match(input, "---------10") then next_state <= st5; output <= "100100000";
elsif std_match(input, "------1--11") then next_state <= st7; output <= "01110--00";
elsif std_match(input, "----0-0--11") then next_state <= st5; output <= "100101000";
elsif std_match(input, "----1-0--11") then next_state <= st7; output <= "011101000";
end if;
when others => next_state <= "-----"; output <= "---------";
end case;
end process;
end behaviour;
| agpl-3.0 | 0e09ca3525ddbfae2a010c258b55e0a0 | 0.56061 | 3.451575 | false | false | false | false |
chastell/art-decomp | kiss/train4_rnd.vhd | 1 | 2,066 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity train4_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(0 downto 0)
);
end train4_rnd;
architecture behaviour of train4_rnd is
constant st0: std_logic_vector(1 downto 0) := "01";
constant st1: std_logic_vector(1 downto 0) := "10";
constant st2: std_logic_vector(1 downto 0) := "11";
constant st3: std_logic_vector(1 downto 0) := "00";
signal current_state, next_state: std_logic_vector(1 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "00") then next_state <= st0; output <= "0";
elsif std_match(input, "10") then next_state <= st1; output <= "-";
elsif std_match(input, "01") then next_state <= st1; output <= "-";
end if;
when st1 =>
if std_match(input, "10") then next_state <= st1; output <= "1";
elsif std_match(input, "01") then next_state <= st1; output <= "1";
elsif std_match(input, "00") then next_state <= st2; output <= "1";
elsif std_match(input, "11") then next_state <= st2; output <= "1";
end if;
when st2 =>
if std_match(input, "00") then next_state <= st2; output <= "1";
elsif std_match(input, "11") then next_state <= st2; output <= "1";
elsif std_match(input, "01") then next_state <= st3; output <= "1";
elsif std_match(input, "10") then next_state <= st3; output <= "1";
end if;
when st3 =>
if std_match(input, "10") then next_state <= st3; output <= "1";
elsif std_match(input, "01") then next_state <= st3; output <= "1";
elsif std_match(input, "00") then next_state <= st0; output <= "-";
end if;
when others => next_state <= "--"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 | 22d21dd26c3750898c1e936d430079d7 | 0.587609 | 3.238245 | false | false | false | false |
es17m014/vhdl-counter | src/vhdl/bin2bcd.vhd | 1 | 1,642 | -------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : bin2bcd.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: Converts a binary vector into a bcd coded number
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 27.10.2017 0.1 Martin Angermair init
-- 19.11.2017 1.0 Martin Angermair final version
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
architecture rtl of bin2bcd is
begin
process(digits_i)
variable z: std_logic_vector(32 downto 0);
begin
for i in 0 to 32 loop
z(i) := '0';
end loop;
z(16 downto 3) := digits_i;
for i in 0 to 10 loop
if z(17 downto 14) > 4 then
z(17 downto 14) := z(17 downto 14) + 3;
end if;
if z(21 downto 18) > 4 then
z(21 downto 18) := z(21 downto 18) + 3;
end if;
if z(25 downto 22) > 4 then
z(25 downto 22) := z(25 downto 22) + 3;
end if;
if z(29 downto 26) > 4 then
z(29 downto 26) := z(29 downto 26) + 3;
end if;
z(32 downto 1) := z(31 downto 0);
end loop;
bcd_o <= z(30 downto 14);
end process;
end rtl; | mit | 24c4d5e649e11fd87a151e679698c38f | 0.4257 | 4.287206 | false | false | false | false |
chastell/art-decomp | kiss/pma_hot.vhd | 1 | 9,745 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity pma_hot is
port(
clock: in std_logic;
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0)
);
end pma_hot;
architecture behaviour of pma_hot is
constant s0: std_logic_vector(23 downto 0) := "100000000000000000000000";
constant s1: std_logic_vector(23 downto 0) := "010000000000000000000000";
constant s21: std_logic_vector(23 downto 0) := "001000000000000000000000";
constant s2: std_logic_vector(23 downto 0) := "000100000000000000000000";
constant s3: std_logic_vector(23 downto 0) := "000010000000000000000000";
constant s4: std_logic_vector(23 downto 0) := "000001000000000000000000";
constant s6: std_logic_vector(23 downto 0) := "000000100000000000000000";
constant s7: std_logic_vector(23 downto 0) := "000000010000000000000000";
constant s5: std_logic_vector(23 downto 0) := "000000001000000000000000";
constant s10: std_logic_vector(23 downto 0) := "000000000100000000000000";
constant s8: std_logic_vector(23 downto 0) := "000000000010000000000000";
constant s9: std_logic_vector(23 downto 0) := "000000000001000000000000";
constant s11: std_logic_vector(23 downto 0) := "000000000000100000000000";
constant s12: std_logic_vector(23 downto 0) := "000000000000010000000000";
constant s13: std_logic_vector(23 downto 0) := "000000000000001000000000";
constant s14: std_logic_vector(23 downto 0) := "000000000000000100000000";
constant s22: std_logic_vector(23 downto 0) := "000000000000000010000000";
constant s30: std_logic_vector(23 downto 0) := "000000000000000001000000";
constant s23: std_logic_vector(23 downto 0) := "000000000000000000100000";
constant s25: std_logic_vector(23 downto 0) := "000000000000000000010000";
constant s24: std_logic_vector(23 downto 0) := "000000000000000000001000";
constant s26: std_logic_vector(23 downto 0) := "000000000000000000000100";
constant s27: std_logic_vector(23 downto 0) := "000000000000000000000010";
constant s28: std_logic_vector(23 downto 0) := "000000000000000000000001";
signal current_state, next_state: std_logic_vector(23 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "------------------------"; output <= "--------";
case current_state is
when s0 =>
if std_match(input, "----1---") then next_state <= s1; output <= "00000000";
elsif std_match(input, "1---01--") then next_state <= s21; output <= "00000000";
end if;
when s1 =>
if std_match(input, "---0---1") then next_state <= s2; output <= "00001000";
elsif std_match(input, "---0--1-") then next_state <= s2; output <= "00001000";
elsif std_match(input, "1--1----") then next_state <= s3; output <= "00001000";
end if;
when s2 =>
if std_match(input, "1--1----") then next_state <= s3; output <= "00000100";
end if;
when s3 =>
if std_match(input, "1--1----") then next_state <= s4; output <= "10000000";
elsif std_match(input, "1--0---1") then next_state <= s6; output <= "10000000";
elsif std_match(input, "1--0--1-") then next_state <= s6; output <= "10000000";
elsif std_match(input, "1--0--00") then next_state <= s7; output <= "10000000";
end if;
when s4 =>
if std_match(input, "1--1----") then next_state <= s5; output <= "01000000";
elsif std_match(input, "1--0---1") then next_state <= s6; output <= "01000000";
elsif std_match(input, "1--0--1-") then next_state <= s6; output <= "01000000";
elsif std_match(input, "1--0--00") then next_state <= s7; output <= "01000000";
end if;
when s5 =>
if std_match(input, "1--1----") then next_state <= s5; output <= "11000000";
elsif std_match(input, "1--0---1") then next_state <= s6; output <= "11000000";
elsif std_match(input, "1--0--1-") then next_state <= s6; output <= "11000000";
elsif std_match(input, "1--0--00") then next_state <= s7; output <= "11000000";
end if;
when s6 =>
if std_match(input, "1-----01") then next_state <= s0; output <= "00100000";
elsif std_match(input, "1-----1-") then next_state <= s10; output <= "00100000";
end if;
when s7 =>
if std_match(input, "-1--1---") then next_state <= s8; output <= "11101010";
elsif std_match(input, "-1--0--1") then next_state <= s6; output <= "11101010";
elsif std_match(input, "-1--0-1-") then next_state <= s6; output <= "11101010";
end if;
when s8 =>
if std_match(input, "1--1----") then next_state <= s5; output <= "01110000";
elsif std_match(input, "---0---1") then next_state <= s9; output <= "01110000";
elsif std_match(input, "---0--1-") then next_state <= s9; output <= "01110000";
end if;
when s9 =>
if std_match(input, "1--1----") then next_state <= s5; output <= "11100100";
end if;
when s10 =>
if std_match(input, "1--10--0") then next_state <= s11; output <= "10101100";
elsif std_match(input, "1------1") then next_state <= s0; output <= "10101100";
elsif std_match(input, "1---1---") then next_state <= s0; output <= "10101100";
end if;
when s11 =>
if std_match(input, "-11-0--0") then next_state <= s12; output <= "11111101";
elsif std_match(input, "11-----1") then next_state <= s0; output <= "11111101";
elsif std_match(input, "1---1---") then next_state <= s0; output <= "11111101";
end if;
when s12 =>
if std_match(input, "---00--0") then next_state <= s13; output <= "10111100";
elsif std_match(input, "1------1") then next_state <= s0; output <= "10111100";
elsif std_match(input, "1---1---") then next_state <= s0; output <= "10111100";
end if;
when s13 =>
if std_match(input, "1-------") then next_state <= s14; output <= "11111100";
end if;
when s14 =>
if std_match(input, "1---0--0") then next_state <= s10; output <= "01100000";
elsif std_match(input, "1------1") then next_state <= s0; output <= "01100000";
elsif std_match(input, "1---1---") then next_state <= s0; output <= "01100000";
end if;
when s21 =>
if std_match(input, "1---0-00") then next_state <= s22; output <= "00011100";
elsif std_match(input, "1---1---") then next_state <= s30; output <= "00011100";
elsif std_match(input, "1-----1-") then next_state <= s30; output <= "00011100";
elsif std_match(input, "1------1") then next_state <= s30; output <= "00011100";
end if;
when s22 =>
if std_match(input, "1---0100") then next_state <= s23; output <= "10011100";
elsif std_match(input, "1---0000") then next_state <= s25; output <= "10011100";
elsif std_match(input, "1---1---") then next_state <= s30; output <= "10011100";
elsif std_match(input, "1-----1-") then next_state <= s30; output <= "10011100";
elsif std_match(input, "1------1") then next_state <= s30; output <= "10011100";
end if;
when s23 =>
if std_match(input, "1---0100") then next_state <= s24; output <= "01011100";
elsif std_match(input, "1---0000") then next_state <= s25; output <= "01011100";
elsif std_match(input, "1---1---") then next_state <= s30; output <= "01011100";
elsif std_match(input, "1-----1-") then next_state <= s30; output <= "01011100";
elsif std_match(input, "1------1") then next_state <= s30; output <= "01011100";
end if;
when s24 =>
if std_match(input, "1---0000") then next_state <= s25; output <= "11011100";
elsif std_match(input, "1---1---") then next_state <= s30; output <= "11011100";
elsif std_match(input, "1-----1-") then next_state <= s30; output <= "11011100";
elsif std_match(input, "1------1") then next_state <= s30; output <= "11011100";
end if;
when s25 =>
if std_match(input, "---10-00") then next_state <= s26; output <= "01111100";
elsif std_match(input, "1---1---") then next_state <= s30; output <= "01111100";
elsif std_match(input, "1-----1-") then next_state <= s30; output <= "01111100";
elsif std_match(input, "1------1") then next_state <= s30; output <= "01111100";
end if;
when s26 =>
if std_match(input, "011---00") then next_state <= s27; output <= "01111101";
elsif std_match(input, "1---1---") then next_state <= s30; output <= "01111101";
elsif std_match(input, "1-----1-") then next_state <= s30; output <= "01111101";
elsif std_match(input, "1------1") then next_state <= s30; output <= "01111101";
end if;
when s27 =>
if std_match(input, "0--00-00") then next_state <= s28; output <= "11101100";
elsif std_match(input, "1--00-00") then next_state <= s0; output <= "11101100";
elsif std_match(input, "1---1---") then next_state <= s30; output <= "11101100";
elsif std_match(input, "1-----1-") then next_state <= s30; output <= "11101100";
elsif std_match(input, "1------1") then next_state <= s30; output <= "11101100";
end if;
when s28 =>
if std_match(input, "1-------") then next_state <= s0; output <= "10111000";
end if;
when s30 =>
if std_match(input, "1-------") then next_state <= s0; output <= "00110000";
end if;
when others => next_state <= "------------------------"; output <= "--------";
end case;
end process;
end behaviour;
| agpl-3.0 | b496ab0e270756fac5af059248baec14 | 0.582863 | 3.467972 | false | false | false | false |
chastell/art-decomp | kiss/dk15_rnd.vhd | 1 | 3,716 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk15_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(2 downto 0);
output: out std_logic_vector(4 downto 0)
);
end dk15_rnd;
architecture behaviour of dk15_rnd is
constant state1: std_logic_vector(1 downto 0) := "01";
constant state2: std_logic_vector(1 downto 0) := "10";
constant state3: std_logic_vector(1 downto 0) := "11";
constant state4: std_logic_vector(1 downto 0) := "00";
signal current_state, next_state: std_logic_vector(1 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--"; output <= "-----";
case current_state is
when state1 =>
if std_match(input, "000") then next_state <= state1; output <= "00101";
elsif std_match(input, "001") then next_state <= state2; output <= "00010";
elsif std_match(input, "010") then next_state <= state3; output <= "00010";
elsif std_match(input, "011") then next_state <= state2; output <= "10001";
elsif std_match(input, "111") then next_state <= state3; output <= "10101";
elsif std_match(input, "100") then next_state <= state1; output <= "01001";
elsif std_match(input, "101") then next_state <= state2; output <= "01010";
elsif std_match(input, "110") then next_state <= state3; output <= "01010";
end if;
when state2 =>
if std_match(input, "000") then next_state <= state2; output <= "10010";
elsif std_match(input, "001") then next_state <= state2; output <= "10100";
elsif std_match(input, "010") then next_state <= state3; output <= "10010";
elsif std_match(input, "011") then next_state <= state2; output <= "10001";
elsif std_match(input, "111") then next_state <= state3; output <= "10101";
elsif std_match(input, "100") then next_state <= state3; output <= "01001";
elsif std_match(input, "101") then next_state <= state2; output <= "01010";
elsif std_match(input, "110") then next_state <= state3; output <= "01010";
end if;
when state3 =>
if std_match(input, "000") then next_state <= state1; output <= "00101";
elsif std_match(input, "001") then next_state <= state2; output <= "00010";
elsif std_match(input, "010") then next_state <= state3; output <= "00010";
elsif std_match(input, "011") then next_state <= state1; output <= "00100";
elsif std_match(input, "111") then next_state <= state1; output <= "00100";
elsif std_match(input, "100") then next_state <= state1; output <= "10100";
elsif std_match(input, "101") then next_state <= state2; output <= "01000";
elsif std_match(input, "110") then next_state <= state4; output <= "01010";
end if;
when state4 =>
if std_match(input, "000") then next_state <= state2; output <= "10010";
elsif std_match(input, "001") then next_state <= state2; output <= "10100";
elsif std_match(input, "010") then next_state <= state3; output <= "10010";
elsif std_match(input, "011") then next_state <= state1; output <= "00100";
elsif std_match(input, "111") then next_state <= state1; output <= "00100";
elsif std_match(input, "100") then next_state <= state1; output <= "01001";
elsif std_match(input, "101") then next_state <= state2; output <= "01010";
elsif std_match(input, "110") then next_state <= state3; output <= "10000";
end if;
when others => next_state <= "--"; output <= "-----";
end case;
end process;
end behaviour;
| agpl-3.0 | 2a934e4dd9a38b14ef6ebb4257777be4 | 0.609526 | 3.453532 | false | false | false | false |
ibm2030/IBM2030 | FMD2030_5-10D.vhd | 1 | 8,948 | ---------------------------------------------------------------------------
-- Copyright 2012 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-10D.vhd
-- Creation Date:
-- Description:
-- 1050 Typewriter Console attachment and CE section
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2012-04-07
-- Initial release
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
use work.all;
ENTITY n1050_ATTACH IS
port
(
-- Inputs
-- CE Cable
CE_CABLE_IN : IN CE_IN := ("00000000",'0','0','0','0','0','0','0','0','0','0');
-- CE DATA BUS From 1050 DATA section
PTT_BITS : IN STD_LOGIC_VECTOR(0 to 6);
DATA_REG : IN STD_LOGIC_VECTOR(0 to 7);
NPL_BITS : IN STD_LOGIC_VECTOR(0 to 7);
-- Other stuff
TE_LCH : IN STD_LOGIC; -- 10CB5
WRITE_UC : IN STD_LOGIC; -- 09CD6
XLATE_UC : IN STD_LOGIC; -- 09CB6
CPU_REQUEST_IN : IN STD_LOGIC; -- 10BD6
n1050_OP_IN : IN STD_LOGIC; -- 10BB5
HOME_RDR_STT_LCH : IN STD_LOGIC; -- 10BB3
RDR_ON_LCH : IN STD_LOGIC; -- 10BD3
MICRO_SHARE_LCH : IN STD_LOGIC; -- 10BC3
PROCEED_LCH : IN STD_LOGIC; -- 10BC3
TA_REG_POS_4 : IN STD_LOGIC; -- 10BE3
CR_LF : IN STD_LOGIC; -- 10BE3
TA_REG_POS_6 : IN STD_LOGIC; -- 10BE3
n1050_RST : IN STD_LOGIC; -- 10BE2
GT_WR_REG : IN STD_LOGIC; -- 10CB6
FORCE_LC_SHIFT : IN STD_LOGIC; -- 10CC6
FORCE_SHIFT_CHAR : IN STD_LOGIC; -- 10CC6
WR_STROBE : IN STD_LOGIC; -- 09CD2
PCH_1_HOME : IN STD_LOGIC; -- 09CD6
HOME_RDR_STOP : IN STD_LOGIC; -- 10BB3
TT2_POS_END : IN STD_LOGIC; -- 09CB5 - NOT IN FMD
TT5_POS_INTRV_REQ : IN STD_LOGIC; -- 10CD5
TT6_POS_ATTN : IN STD_LOGIC; -- 10BD6
CPU_LINES_ENTRY : IN CONN_1050; -- 10BE3
-- Outputs
-- CE Cable
CE_CABLE_OUT : OUT CE_OUT;
-- CE DATA BUS to 10C (1050 DATA)
CE_GT_TA_OR_TE : OUT STD_LOGIC; -- 10C
CE_DATA_ENTER_GT : OUT STD_LOGIC; -- 10BB1 10CA4 10C
CE_TE_DECODE : OUT STD_LOGIC; -- 10CA4 10C
CE_MODE_AND_TE_LCH : OUT STD_LOGIC;
n1050_CE_MODE : OUT STD_LOGIC; -- 10CB3 10BD5
-- Other stuff
CE_SEL_OUT : OUT STD_LOGIC; -- 10BD5
CE_TI_DECODE : OUT STD_LOGIC; -- 09CC5
CE_RUN_MODE : OUT STD_LOGIC; -- 09CC5
CE_TA_DECODE : OUT STD_LOGIC; -- 10BB1
CE_BUS : OUT STD_LOGIC_VECTOR(0 to 7); -- 10C
EXIT_MPLX_SHARE : OUT STD_LOGIC; -- 10BB5
CE_DATA_ENTER_NC : OUT STD_LOGIC;
-- TT3_POS_1050_OPER : OUT STD_LOGIC; -- 10BE2 10BB2 10BE2 10CE5 Moved to TT_BUS(3)
-- TT4_POS_HOME_STT : OUT STD_LOGIC; -- 10CD2 Moved to TT_BUS(4)
OUTPUT_SEL_AND_RDY : OUT STD_LOGIC; -- 10CD4
n1050_OPER : OUT STD_LOGIC; -- 10CC4 10CE4
PUNCH_BITS : OUT STD_LOGIC_VECTOR(0 to 6); -- 10CE1
READ_INTLK_RST : OUT STD_LOGIC; -- 10BA1
PUNCH_1_CLUTCH : OUT STD_LOGIC; -- 10CE1 10AC1
-- PCH_1_CLUTCH_1050 : OUT STD_LOGIC; -- 09CE1 10BA1 09CD5
REQUEST_KEY : OUT STD_LOGIC; -- 10BE4
RDR_1_CLUTCH : OUT STD_LOGIC;
-- In/Out TT bus
TT_BUS : INOUT STD_LOGIC_VECTOR(0 to 7);
GTD_TT3 : IN STD_LOGIC;
-- Hardware Serial Port
serialInput : in Serial_Input_Lines;
serialOutput : out Serial_Output_Lines;
-- Clocks
T1,T2,T3,T4 : IN STD_LOGIC;
P1,P2,P3,P4 : IN STD_LOGIC;
clk : IN STD_LOGIC
);
END n1050_ATTACH;
ARCHITECTURE FMD OF n1050_ATTACH IS
signal sCE_TA_DECODE, sCE_TE_DECODE : STD_LOGIC;
signal sCE_DATA_ENTER_GT : STD_LOGIC;
signal sn1050_CE_MODE : STD_LOGIC;
signal sPUNCH_1_CLUTCH : STD_LOGIC;
signal sRDR_1_CLUTCH : STD_LOGIC;
signal sOUTPUT_SEL_AND_RDY : STD_LOGIC;
signal TT1_POS_RDR_2_RDY, sTT3_POS_1050_OPER, sTT4_POS_HOME_STT : STD_LOGIC;
signal PCH_CONN_ENTRY : PCH_CONN;
signal RDR_1_CONN_EXIT : RDR_CONN;
signal CPU_LINES_EXIT : CONN_1050;
BEGIN
-- Fig 5-10D
sCE_TA_DECODE <= CE_CABLE_IN.CE_TA_DECODE;
CE_TA_DECODE <= sCE_TA_DECODE;
CE_GT_TA_OR_TE <= (CE_CABLE_IN.CE_TA_DECODE and sCE_DATA_ENTER_GT) or (sCE_TE_DECODE and sCE_DATA_ENTER_GT); -- AC2G5
sCE_DATA_ENTER_GT <= CE_CABLE_IN.CE_TI_OR_TE_RUN_MODE;
CE_DATA_ENTER_GT <= sCE_DATA_ENTER_GT;
-- CE cable entry
CE_BUS <= CE_CABLE_IN.CE_BIT; -- AC2M3
sCE_TE_DECODE <= CE_CABLE_IN.CE_TE_DECODE; -- AC2M2
CE_TE_DECODE <= sCE_TE_DECODE;
CE_SEL_OUT <= CE_CABLE_IN.CE_SEL_OUT; -- AC2M2
CE_TI_DECODE <= CE_CABLE_IN.CE_TI_DECODE; -- AC2M2
CE_RUN_MODE <= not CE_CABLE_IN.CE_MODE; -- AC2M2
CE_MODE_AND_TE_LCH <= (TE_LCH and sn1050_CE_MODE) or CE_CABLE_IN.CE_SEL_OUT; -- AC2E7
sn1050_CE_MODE <= CE_CABLE_IN.CE_MODE;
n1050_CE_MODE <= sn1050_CE_MODE;
EXIT_MPLX_SHARE <= CE_CABLE_IN.CE_EXIT_MPLX_SHARE;
CE_DATA_ENTER_NC <= CE_CABLE_IN.CE_DATA_ENTER_NC;
-- CE cable exit
CE_CABLE_OUT.PTT_BITS <= PTT_BITS;
CE_CABLE_OUT.DATA_REG <= DATA_REG;
CE_CABLE_OUT.RDR_1_CLUTCH <= sRDR_1_CLUTCH;
CE_CABLE_OUT.WRITE_UC <= WRITE_UC;
CE_CABLE_OUT.XLATE_UC <= XLATE_UC;
CE_CABLE_OUT.PUNCH_1_CLUTCH <= sPUNCH_1_CLUTCH;
CE_CABLE_OUT.NPL <= NPL_BITS;
CE_CABLE_OUT.OUTPUT_SEL_AND_RDY <= sOUTPUT_SEL_AND_RDY;
CE_CABLE_OUT.TT <= TT_BUS(0 to 2) & GTD_TT3 & TT_BUS(4 to 7);
CE_CABLE_OUT.CPU_REQUEST_IN <= CPU_REQUEST_IN;
CE_CABLE_OUT.n1050_OP_IN <= n1050_OP_IN;
CE_CABLE_OUT.HOME_RDR_STT_LCH <= HOME_RDR_STT_LCH;
CE_CABLE_OUT.RDR_ON_LCH <= RDR_ON_LCH;
CE_CABLE_OUT.MICRO_SHARE_LCH <= MICRO_SHARE_LCH;
CE_CABLE_OUT.PROCEED_LCH <= PROCEED_LCH;
CE_CABLE_OUT.TA_REG_POS_4 <= TA_REG_POS_4;
CE_CABLE_OUT.CR_LF <= CR_LF;
CE_CABLE_OUT.TA_REG_POS_6 <= TA_REG_POS_6;
CE_CABLE_OUT.n1050_RST <= n1050_RST;
-- RDR connection (output)
-- FORCE_LC_SHIFT and FORCE_SHIFT_CHAR makes 0111110 (downshift)
-- FORCE_SHIFT_CHAR makes 0001110 (upshift)
-- We remove this in favour of simple ASCII on the output
-- RDR_1_CONN_EXIT.RDR_BITS <= (PTT_BITS(0) and GT_WR_REG) -- C
-- & ((PTT_BITS(1) and GT_WR_REG) or FORCE_LC_SHIFT) -- B
-- & ((PTT_BITS(2) and GT_WR_REG) or FORCE_LC_SHIFT) -- A
-- & ((PTT_BITS(3) and GT_WR_REG) or FORCE_SHIFT_CHAR) -- 8
-- & ((PTT_BITS(4) and GT_WR_REG) or FORCE_SHIFT_CHAR) -- 4
-- & ((PTT_BITS(5) and GT_WR_REG) or FORCE_SHIFT_CHAR) -- 2
-- & (PTT_BITS(6) and GT_WR_REG); -- 1
RDR_1_CONN_EXIT.RDR_BITS <= PTT_BITS;
RDR_1_CONN_EXIT.RD_STROBE <= WR_STROBE;
CPU_LINES_EXIT <= CPU_LINES_ENTRY;
-- TT Bus
TT_BUS(1) <= TT1_POS_RDR_2_RDY;
TT_BUS(2) <= TT2_POS_END;
TT_BUS(3) <= sTT3_POS_1050_OPER;
-- TT3_POS_1050_OPER <= sTT3_POS_1050_OPER;
TT_BUS(4) <= sTT4_POS_HOME_STT;
-- TT4_POS_HOME_STT <= sTT4_POS_HOME_STT;
TT_BUS(5) <= TT5_POS_INTRV_REQ;
TT_BUS(6) <= TT6_POS_ATTN;
-- PCH connections (input)
PUNCH_BITS <= PCH_CONN_ENTRY.PCH_BITS; -- AC2L4
READ_INTLK_RST <= '1' when PCH_CONN_ENTRY.PCH_BITS="0000000" else '0'; -- AC2E3
sPUNCH_1_CLUTCH <= PCH_CONN_ENTRY.PCH_1_CLUTCH_1050; -- AC2M2 AC2J7
PUNCH_1_CLUTCH <= sPUNCH_1_CLUTCH;
-- PCH_1_CLUTCH_1050 <= sPUNCH_1_CLUTCH;
TT1_POS_RDR_2_RDY <= PCH_CONN_ENTRY.RDR_2_READY; -- AC2M5 AC2L5
sTT3_POS_1050_OPER <= PCH_CONN_ENTRY.CPU_CONNECTED; -- AC2J5
sTT4_POS_HOME_STT <= PCH_CONN_ENTRY.HOME_RDR_STT_LCH; -- AC2M5 AC2L5
-- TT4_POS_HOME_STT <= sTT4_POS_HOME_STT;
sOUTPUT_SEL_AND_RDY <= PCH_CONN_ENTRY.HOME_OUTPUT_DEV_RDY;
OUTPUT_SEL_AND_RDY <= sOUTPUT_SEL_AND_RDY;
sRDR_1_CLUTCH <= PCH_CONN_ENTRY.RDR_1_CLUTCH_1050; -- AC2M4
RDR_1_CLUTCH <= sRDR_1_CLUTCH;
n1050_OPER <= PCH_CONN_ENTRY.CPU_CONNECTED; -- FA1D4
REQUEST_KEY <=PCH_CONN_ENTRY.REQ_KEY; -- FA1D4
console : entity ibm1050 port map(
SerialIn => PCH_CONN_ENTRY,
SerialOut => RDR_1_CONN_EXIT,
SerialControl => CPU_LINES_EXIT,
serialInput => serialInput,
serialOutput => serialOutput,
clk => clk);
END FMD;
| gpl-3.0 | fe9576f46177c299780f21cb6c872d88 | 0.629861 | 2.543491 | false | false | false | false |
TheMassController/VHDL_experimenting | project/sevenSegment/seven_seg_pkg.vhd | 1 | 2,021 | library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
package seven_seg_pkg is
subtype seven_seg_kath_type is std_logic_vector(7 downto 0);
-- Four bits to represent the numbers 0 - f, one more bit for the dot
subtype digit_info_type is std_logic_vector(4 downto 0);
function hex_to_seven_seg (
hex_in : digit_info_type
) return seven_seg_kath_type;
end seven_seg_pkg;
package body seven_seg_pkg is
function hex_to_seven_seg (
hex_in : digit_info_type
) return seven_seg_kath_type is
variable retval : seven_seg_kath_type;
variable input : natural range 0 to 15;
begin
input := to_integer(unsigned(hex_in(3 downto 0)));
case input is
when 16#0# =>
retval := "11000000";
when 16#1# =>
retval := "11111001";
when 16#2# =>
retval := "10100100";
when 16#3# =>
retval := "10110000";
when 16#4# =>
retval := "10011001";
when 16#5# =>
retval := "10010010";
when 16#6# =>
retval := "10000010";
when 16#7# =>
retval := "11111000";
when 16#8# =>
retval := "10000000";
when 16#9# =>
retval := "10010000";
when 16#a# =>
retval := "10001000";
when 16#b# =>
retval := "10000011";
when 16#c# =>
retval := "11000110";
when 16#d# =>
retval := "10100001";
when 16#e# =>
retval := "10000110";
when 16#f# =>
retval := "10001110";
when others =>
retval := "00000000";
end case;
if hex_in(digit_info_type'high) = '1' then
retval(seven_seg_kath_type'high) := '0';
end if;
return retval;
end function;
end seven_seg_pkg;
| mit | 29e33cd22a613afafe871a12d61524bf | 0.471054 | 4.082828 | false | false | false | false |
chastell/art-decomp | kiss/ex5_hot.vhd | 1 | 3,881 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex5_hot is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end ex5_hot;
architecture behaviour of ex5_hot is
constant s1: std_logic_vector(8 downto 0) := "100000000";
constant s0: std_logic_vector(8 downto 0) := "010000000";
constant s7: std_logic_vector(8 downto 0) := "001000000";
constant s5: std_logic_vector(8 downto 0) := "000100000";
constant s4: std_logic_vector(8 downto 0) := "000010000";
constant s2: std_logic_vector(8 downto 0) := "000001000";
constant s3: std_logic_vector(8 downto 0) := "000000100";
constant s6: std_logic_vector(8 downto 0) := "000000010";
constant s8: std_logic_vector(8 downto 0) := "000000001";
signal current_state, next_state: std_logic_vector(8 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---------"; output <= "--";
case current_state is
when s1 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s7; output <= "00";
elsif std_match(input, "10") then next_state <= s5; output <= "11";
elsif std_match(input, "11") then next_state <= s4; output <= "--";
end if;
when s2 =>
if std_match(input, "00") then next_state <= s1; output <= "--";
elsif std_match(input, "01") then next_state <= s4; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "00";
end if;
when s3 =>
if std_match(input, "00") then next_state <= s3; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "00";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s7; output <= "11";
end if;
when s4 =>
if std_match(input, "00") then next_state <= s5; output <= "00";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s1; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s5 =>
if std_match(input, "00") then next_state <= s0; output <= "11";
elsif std_match(input, "01") then next_state <= s6; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "11";
elsif std_match(input, "11") then next_state <= s0; output <= "11";
end if;
when s6 =>
if std_match(input, "00") then next_state <= s0; output <= "11";
elsif std_match(input, "01") then next_state <= s5; output <= "--";
elsif std_match(input, "10") then next_state <= s1; output <= "11";
elsif std_match(input, "11") then next_state <= s0; output <= "11";
end if;
when s7 =>
if std_match(input, "00") then next_state <= s6; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "11";
elsif std_match(input, "10") then next_state <= s2; output <= "--";
elsif std_match(input, "11") then next_state <= s8; output <= "--";
end if;
when s8 =>
if std_match(input, "00") then next_state <= s3; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s1; output <= "00";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when others => next_state <= "---------"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | d2ce847dedb1cf555e683bc807efae8a | 0.567637 | 3.314261 | false | false | false | false |
es17m014/vhdl-counter | src/old/vhdl/io_ctrl_rtl.vhd | 1 | 3,575 | -------------------------------------------------------------------------------
-- Title : fulladder
-- Project : Fulladder
-------------------------------------------------------------------------------
-- File : io_ctl_rtl.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 20.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: This is the architecture struc of the fulladder VHDL
-- class example.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 20.10.2017 0.1 Martin Angermair init
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
architecture rtl of io_ctrl is
-- Add debouncer for one line
component debouncer is
port(
clk_i : in std_logic; --input clock
reset_i : in std_logic; --input reset
btn_i : in std_logic; --input signal to be debounced
deb_o : out std_logic); --debounced signal
end component debouncer;
-- Define the constant
constant C_ENTCOUNTVAL : std_logic_vector(16 downto 0) := "10010101111000000";
-- Declare the signals used for interconnection of the submodules.
signal s_enctr : std_logic_vector(16 downto 0);
signal s_hertz : std_logic;
signal swsync : std_logic_vector(15 downto 0);
signal pbsync : std_logic_vector(3 downto 0);
signal s_ss_sel : std_logic_vector(3 downto 0);
signal s_ss : std_logic_vector(7 downto 0);
-- temp signal for counter
signal temp : std_logic;
signal counter : integer range 0 to 500000-1 := 0;
begin
-----------------------------------------------------------------------------
--
-- Generate 1 Hz enable signal.
--
-----------------------------------------------------------------------------
p_slowen: process (clk_i, reset_i)
begin -- process p_slowen
if reset_i = '1' then
temp <= '0';
counter <= 0;
elsif rising_edge(clk_i) then -- rising clock edge
if (counter = 500000 - 1) then
temp <= not(temp);
counter <= 0;
else
counter <= counter + 1;
end if;
-- Enable signal is inactive per default.
-- As long as the terminal count is not reached: increment the counter.
-- When the terminal count is reached, set enable flag and reset the
-- counter.
end if;
end process p_slowen;
s_hertz <= temp;
-----------------------------------------------------------------------------
--
-- Debounce buttons and switches
--
-----------------------------------------------------------------------------
p_debounce: process (clk_i, reset_i)
begin -- process debounce
if reset_i = '1' then -- asynchronous reset (active high)
elsif rising_edge(clk_i) then -- rising clock edge
end if;
end process p_debounce;
swclean_o <= swsync;
pbclean_o <= pbsync;
-----------------------------------------------------------------------------
--
-- Display controller for the 7-segment display
--
-----------------------------------------------------------------------------
p_displaycontrol: process (clk_i, reset_i)
begin -- process displaycontrol
if reset_i = '1' then
elsif rising_edge(clk_i) then -- rising clock edge
end if;
end process p_displaycontrol;
ss_o <= s_ss;
ss_sel_o <= s_ss_sel;
end rtl;
| mit | 63b4a538c6a9a1e1b250f87f90557ffc | 0.477762 | 4.661017 | false | false | false | false |
TheMassController/VHDL_experimenting | project/main_file.vhd | 1 | 3,128 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
library work;
use work.bus_pkg.all;
entity main_file is
Port (
--JA_gpio : inout STD_LOGIC_VECTOR (3 downto 0);
--JB_gpio : inout STD_LOGIC_VECTOR (3 downto 0);
--JC_gpio : inout STD_LOGIC_VECTOR (3 downto 0);
--JD_gpio : inout STD_LOGIC_VECTOR (3 downto 0);
slide_switch : in STD_LOGIC_VECTOR (7 downto 0);
--push_button : in STD_LOGIC_VECTOR (3 downto 0);
led : out STD_LOGIC_VECTOR (7 downto 0);
seven_seg_kath : out STD_LOGIC_VECTOR (7 downto 0);
seven_seg_an : out STD_LOGIC_VECTOR (3 downto 0);
clk : in STD_LOGIC;
usb_db : inout std_logic_vector(7 downto 0);
usb_write : in std_logic;
usb_astb : in std_logic;
usb_dstb : in std_logic;
usb_wait : out std_logic
);
end main_file;
architecture Behavioral of main_file is
constant address_map : addr_range_and_mapping_array := (
address_range_and_map(
low => std_logic_vector(to_unsigned(0, bus_address_type'length)),
high => std_logic_vector(to_unsigned(3, bus_address_type'length))
),
address_range_and_map(
low => std_logic_vector(to_unsigned(4, bus_address_type'length))
));
signal rst : STD_LOGIC;
signal depp2demux : bus_mst2slv_type := BUS_MST2SLV_IDLE;
signal demux2depp : bus_slv2mst_type := BUS_SLV2MST_IDLE;
signal demux2ss : bus_mst2slv_type := BUS_MST2SLV_IDLE;
signal ss2demux : bus_slv2mst_type := BUS_SLV2MST_IDLE;
signal demux2mem : bus_mst2slv_type := BUS_MST2SLV_IDLE;
signal mem2demux : bus_slv2mst_type := BUS_SLV2MST_IDLE;
begin
rst <= '0';
concurrent : process(slide_switch)
begin
led <= slide_switch;
end process;
depp_slave_controller : entity work.depp_slave_controller
port map (
rst => rst,
clk => clk,
mst2slv => depp2demux,
slv2mst => demux2depp,
USB_DB => usb_db,
USB_WRITE => usb_write,
USB_ASTB => usb_astb,
USB_DSTB => usb_dstb,
USB_WAIT => usb_wait
);
demux : entity work.bus_demux
generic map (
ADDRESS_MAP => address_map
)
port map (
rst => rst,
mst2demux => depp2demux,
demux2mst => demux2depp,
demux2slv(0) => demux2ss,
demux2slv(1) => demux2mem,
slv2demux(0) => ss2demux,
slv2demux(1) => mem2demux
);
ss : entity work.seven_seg_controller
generic map (
hold_count => 200000,
digit_count => 4
)
port map (
clk => clk,
rst => rst,
mst2slv => demux2ss,
slv2mst => ss2demux,
digit_anodes => seven_seg_an,
kathode => seven_seg_kath
);
mem : entity work.bus_singleport_ram
generic map (
DEPTH_LOG2B => 11
)
port map (
rst => rst,
clk => clk,
mst2mem => demux2mem,
mem2mst => mem2demux
);
end Behavioral;
| mit | 6b80bc22a13b0ac7d2e08b3e15a3d44f | 0.556905 | 3.414847 | false | false | false | false |
TheMassController/VHDL_experimenting | project/deppSlave/depp_pkg.vhd | 1 | 4,222 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.math_real.all;
library work;
use work.bus_pkg.all;
package depp_pkg is
subtype depp_address_type is std_logic_vector(7 downto 0);
subtype depp_data_type is std_logic_vector(7 downto 0);
constant depp2bus_write_mask_length_ceil : natural := natural(ceil(real(bus_write_mask'length)/real(8)));
-- All registers are defined as inclusive start, inclusive end.
-- First the common registers, addr and data are available to both read and write
constant depp2bus_addr_reg_start : natural := 0;
constant depp2bus_addr_reg_len : natural := bus_address_type'length/8;
constant depp2bus_addr_reg_end : natural := depp2bus_addr_reg_start + depp2bus_addr_reg_len - 1;
constant depp2bus_writeData_reg_start : natural := depp2bus_addr_reg_start + depp2bus_addr_reg_len;
constant depp2bus_writeData_reg_len : natural := bus_data_type'length/8;
constant depp2bus_writeData_reg_end : natural := depp2bus_writeData_reg_start + depp2bus_writeData_reg_len - 1;
-- Writing to the readData register has no effect
constant depp2bus_readData_reg_start : natural := depp2bus_writeData_reg_end + 1;
constant depp2bus_readData_reg_len : natural := bus_data_type'length/8;
constant depp2bus_readData_reg_end : natural := depp2bus_readData_reg_start + depp2bus_readData_reg_len - 1;
constant depp2bus_write_mask_reg_start : natural := depp2bus_readData_reg_end + 1;
constant depp2bus_write_mask_reg_len : natural := depp2bus_write_mask_length_ceil;
constant depp2bus_write_mask_reg_end : natural := depp2bus_write_mask_reg_start + depp2bus_write_mask_reg_len - 1;
constant depp2bus_mode_register_start : natural := depp2bus_write_mask_reg_end + 1;
constant depp2bus_mode_register_end : natural := depp2bus_mode_register_start;
-- Writing to the fault register has no effect
constant depp2bus_fault_register_start : natural := depp2bus_mode_register_end + 1;
constant depp2bus_fault_register_end : natural := depp2bus_fault_register_start;
-- Reading from this register always returns 0
constant depp2bus_activation_register_start : natural := depp2bus_fault_register_end + 1;
constant depp2bus_activation_register_end : natural := depp2bus_activation_register_start;
-- The possible modes of the depp2bus device. This is about address increment rules (both depp and bus)
--
-- With fast write enabled, a write to depp2bus_writeData_reg_end will first execute normally and then trigger a write action on the bus.
-- After the write action, the bus address will be incremented by depp2bus_writeData_reg_len.
-- Moreover, any write to the writeData_reg will cause the depp address to increase by one, wrapping around to start when required.
-- One should set the start bus address and the writemask, then set the depp address to depp2bus_writeData_start and
-- then just keep writing the dstb.
constant depp_mode_fast_write_bit : natural := 0;
-- When fast read is enabled:
-- Any read from the readData reg will increment the depp address with wraparound after the read is completed.
-- Any read from readData_reg_start will first cause a bus read before executing the read.
-- The bus address is incremented by depp2bus_readData_reg_len after such an automatic read.
--
-- One should set the bus address, set the depp address to depp2bus_readData_reg_start and then keep on reading for as long as required.
constant depp_mode_fast_read_bit : natural := 1;
function depp_mode_fast_write_active(
depp_mode : depp_data_type
) return boolean;
function depp_mode_fast_read_active(
depp_mode : depp_data_type
) return boolean;
end depp_pkg;
package body depp_pkg is
function depp_mode_fast_write_active(
depp_mode : depp_data_type
) return boolean is
begin
return depp_mode(depp_mode_fast_write_bit) = '1';
end function;
function depp_mode_fast_read_active(
depp_mode : depp_data_type
) return boolean is
begin
return depp_mode(depp_mode_fast_read_bit) = '1';
end function;
end package body;
| mit | f10b1428714c0a997e23c3c543d6dc95 | 0.718854 | 3.596252 | false | false | false | false |
LucasMahieu/TP_secu | code/AES/vhd/vhd/aes_globals.vhd | 2 | 1,255 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
library WORK;
package globals is
-- CONFIGURATION CONSTANTS
constant C_INCLUDE_DECODING_LOGIC : boolean := true; -- Allow both enc and decryption
constant C_CTRL_SIGNAL_SIZE : integer := 1; -- 1 or 2
constant C_ERR_SIGNAL_SIZE : integer := 1; -- 1 or 2
constant RESET_ACTIVE : std_logic := '0';
--constant C_INCLUDE_PARITY : integer := 0; -- 0 false or 1 true
--constant C_CODE_SIZE : integer := C_INCLUDE_PARITY;
constant C_BROKEN : std_logic_vector( C_ERR_SIGNAL_SIZE-1 downto 0 ) := "1";
subtype T_ENABLE is std_logic_vector( C_CTRL_SIGNAL_SIZE-1 downto 0 );
constant C_ENABLE : T_ENABLE := "1"; -- "01"; --
constant C_DISABLE : T_ENABLE := "0"; -- "10"; --
subtype T_ENCDEC is std_logic_vector( C_CTRL_SIGNAL_SIZE-1 downto 0 );
constant C_DEC : T_ENCDEC := "1"; -- "01"; --
constant C_ENC : T_ENCDEC := "0"; -- "10"; --
subtype T_READY is std_logic_vector( C_CTRL_SIGNAL_SIZE-1 downto 0 );
constant C_READY : T_READY := "1"; -- "01"; --
constant C_BUSY : T_READY := "0"; -- "10"; --
end globals;
| mit | 8f27ac894018066a30be503406634937 | 0.581673 | 3.320106 | false | false | false | false |
chastell/art-decomp | kiss/scf_jed.vhd | 1 | 39,256 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity scf_jed is
port(
clock: in std_logic;
input: in std_logic_vector(26 downto 0);
output: out std_logic_vector(55 downto 0)
);
end scf_jed;
architecture behaviour of scf_jed is
constant state1: std_logic_vector(6 downto 0) := "0111101";
constant state3: std_logic_vector(6 downto 0) := "1110110";
constant state2: std_logic_vector(6 downto 0) := "0010001";
constant state4: std_logic_vector(6 downto 0) := "1000100";
constant state5: std_logic_vector(6 downto 0) := "0100110";
constant state7: std_logic_vector(6 downto 0) := "0011101";
constant state6: std_logic_vector(6 downto 0) := "1110001";
constant state9: std_logic_vector(6 downto 0) := "1010001";
constant state8: std_logic_vector(6 downto 0) := "1000001";
constant state17: std_logic_vector(6 downto 0) := "0001110";
constant state12: std_logic_vector(6 downto 0) := "0111100";
constant state10: std_logic_vector(6 downto 0) := "0110100";
constant state11: std_logic_vector(6 downto 0) := "1110101";
constant state15: std_logic_vector(6 downto 0) := "1011001";
constant state13: std_logic_vector(6 downto 0) := "1011101";
constant state29: std_logic_vector(6 downto 0) := "0110111";
constant state14: std_logic_vector(6 downto 0) := "1011111";
constant state59: std_logic_vector(6 downto 0) := "0010000";
constant state16: std_logic_vector(6 downto 0) := "0101100";
constant state18: std_logic_vector(6 downto 0) := "1101010";
constant state19: std_logic_vector(6 downto 0) := "1101001";
constant state21: std_logic_vector(6 downto 0) := "1101100";
constant state20: std_logic_vector(6 downto 0) := "1101101";
constant state22: std_logic_vector(6 downto 0) := "1101111";
constant state23: std_logic_vector(6 downto 0) := "1111110";
constant state24: std_logic_vector(6 downto 0) := "1100110";
constant state26: std_logic_vector(6 downto 0) := "0000000";
constant state25: std_logic_vector(6 downto 0) := "1000000";
constant state28: std_logic_vector(6 downto 0) := "1001110";
constant state27: std_logic_vector(6 downto 0) := "1000110";
constant state36: std_logic_vector(6 downto 0) := "0001101";
constant state34: std_logic_vector(6 downto 0) := "0001111";
constant state32: std_logic_vector(6 downto 0) := "0000101";
constant state30: std_logic_vector(6 downto 0) := "0000111";
constant state38: std_logic_vector(6 downto 0) := "1110100";
constant state31: std_logic_vector(6 downto 0) := "0000011";
constant state37: std_logic_vector(6 downto 0) := "1001100";
constant state55: std_logic_vector(6 downto 0) := "0010011";
constant state33: std_logic_vector(6 downto 0) := "0110110";
constant state57: std_logic_vector(6 downto 0) := "0110101";
constant state35: std_logic_vector(6 downto 0) := "0010010";
constant state43: std_logic_vector(6 downto 0) := "0101000";
constant state41: std_logic_vector(6 downto 0) := "0100000";
constant state39: std_logic_vector(6 downto 0) := "1101000";
constant state45: std_logic_vector(6 downto 0) := "1100001";
constant state40: std_logic_vector(6 downto 0) := "0000010";
constant state44: std_logic_vector(6 downto 0) := "0011000";
constant state50: std_logic_vector(6 downto 0) := "1001011";
constant state42: std_logic_vector(6 downto 0) := "1001111";
constant state48: std_logic_vector(6 downto 0) := "0011010";
constant state46: std_logic_vector(6 downto 0) := "0011011";
constant state47: std_logic_vector(6 downto 0) := "0110010";
constant state49: std_logic_vector(6 downto 0) := "0011001";
constant state52: std_logic_vector(6 downto 0) := "0010110";
constant state51: std_logic_vector(6 downto 0) := "0010111";
constant state54: std_logic_vector(6 downto 0) := "0001010";
constant state53: std_logic_vector(6 downto 0) := "1011010";
constant state56: std_logic_vector(6 downto 0) := "1010100";
constant state58: std_logic_vector(6 downto 0) := "1111000";
constant state67: std_logic_vector(6 downto 0) := "0001000";
constant state60: std_logic_vector(6 downto 0) := "0101010";
constant state65: std_logic_vector(6 downto 0) := "0001001";
constant state63: std_logic_vector(6 downto 0) := "0000001";
constant state61: std_logic_vector(6 downto 0) := "0001011";
constant state82: std_logic_vector(6 downto 0) := "1000111";
constant state62: std_logic_vector(6 downto 0) := "1111100";
constant state83: std_logic_vector(6 downto 0) := "1100100";
constant state64: std_logic_vector(6 downto 0) := "1111101";
constant state89: std_logic_vector(6 downto 0) := "0110001";
constant state66: std_logic_vector(6 downto 0) := "1001101";
constant state81: std_logic_vector(6 downto 0) := "0001100";
constant state80: std_logic_vector(6 downto 0) := "0101101";
constant state78: std_logic_vector(6 downto 0) := "0100101";
constant state76: std_logic_vector(6 downto 0) := "0100111";
constant state74: std_logic_vector(6 downto 0) := "0101001";
constant state72: std_logic_vector(6 downto 0) := "0101011";
constant state70: std_logic_vector(6 downto 0) := "0100001";
constant state68: std_logic_vector(6 downto 0) := "0101111";
constant state96: std_logic_vector(6 downto 0) := "0100011";
constant state69: std_logic_vector(6 downto 0) := "1100101";
constant state98: std_logic_vector(6 downto 0) := "0000110";
constant state71: std_logic_vector(6 downto 0) := "0100100";
constant state103: std_logic_vector(6 downto 0) := "1101011";
constant state73: std_logic_vector(6 downto 0) := "1100010";
constant state107: std_logic_vector(6 downto 0) := "1010000";
constant state75: std_logic_vector(6 downto 0) := "1011000";
constant state115: std_logic_vector(6 downto 0) := "1000101";
constant state77: std_logic_vector(6 downto 0) := "1001001";
constant state117: std_logic_vector(6 downto 0) := "1010010";
constant state79: std_logic_vector(6 downto 0) := "1111010";
constant state84: std_logic_vector(6 downto 0) := "1000010";
constant state86: std_logic_vector(6 downto 0) := "0000100";
constant state85: std_logic_vector(6 downto 0) := "1111011";
constant state88: std_logic_vector(6 downto 0) := "1110000";
constant state87: std_logic_vector(6 downto 0) := "0110000";
constant state91: std_logic_vector(6 downto 0) := "0111000";
constant state90: std_logic_vector(6 downto 0) := "0110011";
constant state92: std_logic_vector(6 downto 0) := "0111010";
constant state95: std_logic_vector(6 downto 0) := "1111111";
constant state93: std_logic_vector(6 downto 0) := "0111111";
constant state94: std_logic_vector(6 downto 0) := "1011011";
constant state97: std_logic_vector(6 downto 0) := "1100000";
constant state101: std_logic_vector(6 downto 0) := "1010101";
constant state99: std_logic_vector(6 downto 0) := "1010111";
constant state100: std_logic_vector(6 downto 0) := "1001010";
constant state102: std_logic_vector(6 downto 0) := "1001000";
constant state105: std_logic_vector(6 downto 0) := "1011110";
constant state104: std_logic_vector(6 downto 0) := "1010110";
constant state106: std_logic_vector(6 downto 0) := "0101110";
constant state112: std_logic_vector(6 downto 0) := "0011110";
constant state108: std_logic_vector(6 downto 0) := "0011111";
constant state110: std_logic_vector(6 downto 0) := "0011100";
constant state109: std_logic_vector(6 downto 0) := "0010100";
constant state111: std_logic_vector(6 downto 0) := "0100010";
constant state114: std_logic_vector(6 downto 0) := "1011100";
constant state113: std_logic_vector(6 downto 0) := "0010101";
constant state116: std_logic_vector(6 downto 0) := "1101110";
constant state118: std_logic_vector(6 downto 0) := "0111011";
constant state121: std_logic_vector(6 downto 0) := "1111001";
constant state119: std_logic_vector(6 downto 0) := "0111001";
constant state120: std_logic_vector(6 downto 0) := "0111110";
signal current_state, next_state: std_logic_vector(6 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-------"; output <= "--------------------------------------------------------";
if std_match(input, "0--------------------------") then next_state <= state1; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
else
case current_state is
when state1 =>
if std_match(input, "1--------------------------") then next_state <= state3; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state2 =>
if std_match(input, "1--------------------------") then next_state <= state1; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state3 =>
if std_match(input, "1--------------------------") then next_state <= state4; output <= "00000010010000001-0000000-00-0001001000010-0-----00-0---";
end if;
when state4 =>
if std_match(input, "1--------------------------") then next_state <= state5; output <= "00000010000000000-0000000-00-0000000110101-0-----00-0---";
end if;
when state5 =>
if std_match(input, "1--------------------------") then next_state <= state7; output <= "00000001000000000-0000000-00-0000000001000-0-----00-0---";
end if;
when state6 =>
if std_match(input, "1--------------------------") then next_state <= state2; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state7 =>
if std_match(input, "1-----0--------------------") then next_state <= state9; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----1--------------------") then next_state <= state8; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state8 =>
if std_match(input, "1--------------------------") then next_state <= state17; output <= "00000010000000000-0000000-00-0000000001000-0-----00-0---";
end if;
when state9 =>
if std_match(input, "1----0---------------------") then next_state <= state12; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----1---------------------") then next_state <= state10; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state10 =>
if std_match(input, "1--------------------------") then next_state <= state11; output <= "00000010000000000-0000001-00-0000000000001-0-----00-0---";
end if;
when state11 =>
if std_match(input, "1--------------------------") then next_state <= state12; output <= "00000000000000000-0000000-00-0000010000000-0-----00-0---";
end if;
when state12 =>
if std_match(input, "1---0----------------------") then next_state <= state15; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1---1----------------------") then next_state <= state13; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state13 =>
if std_match(input, "1--------------------------") then next_state <= state29; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state14 =>
if std_match(input, "1--------------------------") then next_state <= state17; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state15 =>
if std_match(input, "1--------------------------") then next_state <= state59; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state16 =>
if std_match(input, "1--------------------------") then next_state <= state17; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state17 =>
if std_match(input, "1--------------------------") then next_state <= state18; output <= "0000000000010100001000000-10-000000000000011-----00-0---";
end if;
when state18 =>
if std_match(input, "1--------------------------") then next_state <= state19; output <= "00100000000000000-0000000-00-0000000000000-0000--00-0---";
end if;
when state19 =>
if std_match(input, "1--0-----------------------") then next_state <= state21; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--1-----------------------") then next_state <= state20; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state20 =>
if std_match(input, "1--------------------------") then next_state <= state21; output <= "00000001000000000-0000000-00-0000000100000-0-----00-0---";
end if;
when state21 =>
if std_match(input, "1--------------------------") then next_state <= state22; output <= "01000000000100000-0000000-10-100000000000000000001001---";
end if;
when state22 =>
if std_match(input, "1--------------------------") then next_state <= state23; output <= "00010000000000000-0000000-00-0000000000000-0000--01-0---";
end if;
when state23 =>
if std_match(input, "1--------------------------") then next_state <= state24; output <= "00000000100000000-0000000-00-0000000000000-0---0000-0---";
end if;
when state24 =>
if std_match(input, "1-0------------------------") then next_state <= state26; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-1------------------------") then next_state <= state25; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state25 =>
if std_match(input, "1--------------------------") then next_state <= state26; output <= "00000001000000000-0000000-00-0000000010000-0-----00-0---";
end if;
when state26 =>
if std_match(input, "10-------------------------") then next_state <= state28; output <= "00000000010000010-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "11-------------------------") then next_state <= state27; output <= "00000000010000010-0000000-00-0000000000000-0-----00-0---";
end if;
when state27 =>
if std_match(input, "1--------------------------") then next_state <= state28; output <= "00000000000000000-0000000-00-0010000000000-0-----00-0---";
end if;
when state28 =>
if std_match(input, "1--------------------------") then next_state <= state7; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state29 =>
if std_match(input, "1------1-------------------") then next_state <= state36; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------01------------------") then next_state <= state36; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0011----------------") then next_state <= state36; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0010----------------") then next_state <= state34; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0001----------------") then next_state <= state32; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0000----------------") then next_state <= state30; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state30 =>
if std_match(input, "1--------------------------") then next_state <= state38; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state31 =>
if std_match(input, "1--------------------------") then next_state <= state37; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state32 =>
if std_match(input, "1--------------------------") then next_state <= state55; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state33 =>
if std_match(input, "1--------------------------") then next_state <= state37; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state34 =>
if std_match(input, "1--------------------------") then next_state <= state57; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state35 =>
if std_match(input, "1--------------------------") then next_state <= state37; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state36 =>
if std_match(input, "1--------------------------") then next_state <= state37; output <= "00000001000000000-0000000-00-0000000010000-0-----00-0---";
end if;
when state37 =>
if std_match(input, "1--------------------------") then next_state <= state14; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state38 =>
if std_match(input, "1----------1---------------") then next_state <= state43; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----------01--------------") then next_state <= state43; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----------001-------------") then next_state <= state43; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----------0001------------") then next_state <= state41; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----------0000------------") then next_state <= state39; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state39 =>
if std_match(input, "1--------------------------") then next_state <= state45; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state40 =>
if std_match(input, "1--------------------------") then next_state <= state44; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state41 =>
if std_match(input, "1--------------------------") then next_state <= state50; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state42 =>
if std_match(input, "1--------------------------") then next_state <= state44; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state43 =>
if std_match(input, "1--------------------------") then next_state <= state44; output <= "00000001000000000-0000000-00-0000000010000-0-----00-0---";
end if;
when state44 =>
if std_match(input, "1--------------------------") then next_state <= state31; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state45 =>
if std_match(input, "1--------------0-----------") then next_state <= state48; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--------------1-----------") then next_state <= state46; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state46 =>
if std_match(input, "1--------------------------") then next_state <= state47; output <= "0000000001000101001000000-00-0000000000000-0-----00-0---";
end if;
when state47 =>
if std_match(input, "1--------------------------") then next_state <= state49; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state48 =>
if std_match(input, "1--------------------------") then next_state <= state49; output <= "0000000000100000111001010-00-0000000000000-0-----00-0---";
end if;
when state49 =>
if std_match(input, "1--------------------------") then next_state <= state40; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state50 =>
if std_match(input, "1--------------0-----------") then next_state <= state52; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--------------1-----------") then next_state <= state51; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state51 =>
if std_match(input, "1--------------------------") then next_state <= state54; output <= "0000000000100000111001010-00-0000000000000-0-----00-0---";
end if;
when state52 =>
if std_match(input, "1--------------------------") then next_state <= state53; output <= "0000000000000101001000000-00-0000000000000-0-----00-0---";
end if;
when state53 =>
if std_match(input, "1--------------------------") then next_state <= state54; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state54 =>
if std_match(input, "1--------------------------") then next_state <= state42; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state55 =>
if std_match(input, "1--------------------------") then next_state <= state56; output <= "0000000000100000111001010-00-0000000000000-0-----00-0---";
end if;
when state56 =>
if std_match(input, "1--------------------------") then next_state <= state33; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state57 =>
if std_match(input, "1--------------------------") then next_state <= state58; output <= "00000000001000001-0001000-00-0000000000000-0-----00-0---";
end if;
when state58 =>
if std_match(input, "1--------------------------") then next_state <= state35; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state59 =>
if std_match(input, "1---------------0----------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1---------------1----------") then next_state <= state60; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state60 =>
if std_match(input, "1------1-------------------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------01------------------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0011----------------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0010----------------") then next_state <= state65; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0001----------------") then next_state <= state63; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0000----------------") then next_state <= state61; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state61 =>
if std_match(input, "1--------------------------") then next_state <= state82; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state62 =>
if std_match(input, "1--------------------------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state63 =>
if std_match(input, "1--------------------------") then next_state <= state83; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state64 =>
if std_match(input, "1--------------------------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state65 =>
if std_match(input, "1--------------------------") then next_state <= state89; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state66 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state67 =>
if std_match(input, "1------1-------------------") then next_state <= state80; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------011-----------------") then next_state <= state80; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0101----------------") then next_state <= state78; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0100----------------") then next_state <= state76; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0011----------------") then next_state <= state74; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0010----------------") then next_state <= state72; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0001----------------") then next_state <= state70; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0000----------------") then next_state <= state68; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state68 =>
if std_match(input, "1--------------------------") then next_state <= state96; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state69 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state70 =>
if std_match(input, "1--------------------------") then next_state <= state98; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state71 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state72 =>
if std_match(input, "1--------------------------") then next_state <= state103; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state73 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state74 =>
if std_match(input, "1--------------------------") then next_state <= state107; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state75 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state76 =>
if std_match(input, "1--------------------------") then next_state <= state115; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state77 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state78 =>
if std_match(input, "1--------------------------") then next_state <= state117; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state79 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state80 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000001000000000-0000000-00-0000000010000-0-----00-0---";
end if;
when state81 =>
if std_match(input, "1--------------------------") then next_state <= state16; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state82 =>
if std_match(input, "1--------------------------") then next_state <= state62; output <= "00000001000000000-0000000-00-0000000010000-0-----00-0---";
end if;
when state83 =>
if std_match(input, "1--------------------------") then next_state <= state84; output <= "00000001000000000-0000000-00-0000000001000-0-----00-0---";
end if;
when state84 =>
if std_match(input, "1--------------------------") then next_state <= state86; output <= "00001000000001001-0000000-00-0000000000000-0100--00-0---";
end if;
when state85 =>
if std_match(input, "1--------------------------") then next_state <= state64; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state86 =>
if std_match(input, "1----------------0---------") then next_state <= state88; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----------------1---------") then next_state <= state87; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state87 =>
if std_match(input, "1--------------------------") then next_state <= state16; output <= "00000001000000000-0000000-00-0000100001000-0-----00-0---";
end if;
when state88 =>
if std_match(input, "1--------------------------") then next_state <= state86; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state89 =>
if std_match(input, "1--------------------------") then next_state <= state91; output <= "00001001000000000-0000000-00-0001000001000-0-----00-0---";
end if;
when state90 =>
if std_match(input, "1--------------------------") then next_state <= state66; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state91 =>
if std_match(input, "1--------------------------") then next_state <= state92; output <= "00000010000000000-0000000-00-0000000000000-0010--00-0---";
end if;
when state92 =>
if std_match(input, "1--0-----------------------") then next_state <= state95; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--1-----------------------") then next_state <= state93; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state93 =>
if std_match(input, "1--------------------------") then next_state <= state94; output <= "00000000000100001-0000000-10-0000000000000-0-----00-0---";
end if;
when state94 =>
if std_match(input, "1--------------------------") then next_state <= state16; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state95 =>
if std_match(input, "1--------------------------") then next_state <= state91; output <= "00000000000000000-0000000-00-0010100000000-0-----00-0---";
end if;
when state96 =>
if std_match(input, "1--------------------------") then next_state <= state97; output <= "00000100000001000-0000000-00-000000000000011101111011101";
end if;
when state97 =>
if std_match(input, "1--------------------------") then next_state <= state69; output <= "001000010000000100101010010110100000000001-0-----00-0---";
end if;
when state98 =>
if std_match(input, "1--------------0-----------") then next_state <= state101; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--------------1-----------") then next_state <= state99; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state99 =>
if std_match(input, "1--------------------------") then next_state <= state100; output <= "00000100000001000-0000000-00-000000000000011101111011101";
end if;
when state100 =>
if std_match(input, "1--------------------------") then next_state <= state102; output <= "001000010000000100101010010110100000000001-0-----00-0---";
end if;
when state101 =>
if std_match(input, "1--------------------------") then next_state <= state102; output <= "00000100000001001-0000000-00-0000000001000-0100--00-0---";
end if;
when state102 =>
if std_match(input, "1--------------------------") then next_state <= state71; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state103 =>
if std_match(input, "1--------------0-----------") then next_state <= state105; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--------------1-----------") then next_state <= state104; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state104 =>
if std_match(input, "1--------------------------") then next_state <= state106; output <= "0000000000000101001000000-00-0000000000000-0-----00-0---";
end if;
when state105 =>
if std_match(input, "1--------------------------") then next_state <= state106; output <= "00000100000001001-0000000-00-0000000001000-0100--00-0---";
end if;
when state106 =>
if std_match(input, "1--------------------------") then next_state <= state73; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state107 =>
if std_match(input, "1--------------0-----------") then next_state <= state112; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--------------1-----------") then next_state <= state108; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state108 =>
if std_match(input, "1-----------------00000000-") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------1--------") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------01-------") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------001------") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------0001-----") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------00001----") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------000001---") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------0000001--") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------00000001-") then next_state <= state109; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state109 =>
if std_match(input, "1--------------------------") then next_state <= state112; output <= "0000000000001100101000000-00-0000000000000-0-----00-0100";
end if;
when state110 =>
if std_match(input, "1--------------------------") then next_state <= state111; output <= "0000010000000101001010000-0000100000000000111000110-0100";
end if;
when state111 =>
if std_match(input, "1--------------------------") then next_state <= state114; output <= "00000001000000000-0000100001-0000000000001-0-----00-0---";
end if;
when state112 =>
if std_match(input, "1--------------------------") then next_state <= state113; output <= "00000100000001001-0000000-00-0000000000000-0100--00-0---";
end if;
when state113 =>
if std_match(input, "1--------------------------") then next_state <= state114; output <= "00000001000000000-0000000-00-0000000001000-0-----00-0---";
end if;
when state114 =>
if std_match(input, "1--------------------------") then next_state <= state75; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state115 =>
if std_match(input, "1--------------------------") then next_state <= state116; output <= "00001000000010001-0010000-00-0000000000000-01011010-0101";
end if;
when state116 =>
if std_match(input, "1--------------------------") then next_state <= state77; output <= "10000001000000000-0000100-00-0001000001101-0-----00-0---";
end if;
when state117 =>
if std_match(input, "1--------------------------") then next_state <= state118; output <= "00000010000000000-0000000-00-0000000000000-0-----00-0011";
end if;
when state118 =>
if std_match(input, "1-------------------------0") then next_state <= state121; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-------------------------1") then next_state <= state119; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state119 =>
if std_match(input, "1--------------------------") then next_state <= state120; output <= "0000010000001000001000000-00-0000000000000111011010-0101";
end if;
when state120 =>
if std_match(input, "1--------------------------") then next_state <= state16; output <= "00010010000000010-000000000110100000000100-0-----00-0---";
end if;
when state121 =>
if std_match(input, "1--------------------------") then next_state <= state79; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when others => next_state <= "-------"; output <= "--------------------------------------------------------";
end case;
end if;
end process;
end behaviour;
| agpl-3.0 | 3f1d428e062c711360805ca5573ba958 | 0.566767 | 4.06461 | false | false | false | false |
chastell/art-decomp | kiss/styr_rnd.vhd | 1 | 18,712 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity styr_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(8 downto 0);
output: out std_logic_vector(9 downto 0)
);
end styr_rnd;
architecture behaviour of styr_rnd is
constant st0: std_logic_vector(4 downto 0) := "11101";
constant st12: std_logic_vector(4 downto 0) := "00010";
constant st10: std_logic_vector(4 downto 0) := "11011";
constant st1: std_logic_vector(4 downto 0) := "11110";
constant st2: std_logic_vector(4 downto 0) := "11111";
constant st8: std_logic_vector(4 downto 0) := "10001";
constant st3: std_logic_vector(4 downto 0) := "10110";
constant st7: std_logic_vector(4 downto 0) := "01011";
constant st4: std_logic_vector(4 downto 0) := "01111";
constant st5: std_logic_vector(4 downto 0) := "00001";
constant st6: std_logic_vector(4 downto 0) := "10000";
constant st29: std_logic_vector(4 downto 0) := "11010";
constant st9: std_logic_vector(4 downto 0) := "11000";
constant st28: std_logic_vector(4 downto 0) := "01000";
constant st11: std_logic_vector(4 downto 0) := "00100";
constant st13: std_logic_vector(4 downto 0) := "01001";
constant st14: std_logic_vector(4 downto 0) := "00110";
constant st15: std_logic_vector(4 downto 0) := "11100";
constant st16: std_logic_vector(4 downto 0) := "00011";
constant st22: std_logic_vector(4 downto 0) := "10111";
constant st19: std_logic_vector(4 downto 0) := "10011";
constant st17: std_logic_vector(4 downto 0) := "10010";
constant st18: std_logic_vector(4 downto 0) := "00111";
constant st20: std_logic_vector(4 downto 0) := "01100";
constant st21: std_logic_vector(4 downto 0) := "10101";
constant st25: std_logic_vector(4 downto 0) := "10100";
constant st23: std_logic_vector(4 downto 0) := "00000";
constant st24: std_logic_vector(4 downto 0) := "01101";
constant st26: std_logic_vector(4 downto 0) := "00101";
constant st27: std_logic_vector(4 downto 0) := "11001";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "----------";
case current_state is
when st0 =>
if std_match(input, "1-0000---") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-10-----") then next_state <= st12; output <= "0000------";
elsif std_match(input, "1-1-0----") then next_state <= st12; output <= "0000------";
elsif std_match(input, "1-0010---") then next_state <= st10; output <= "1000----10";
elsif std_match(input, "1-0011---") then next_state <= st10; output <= "1000----11";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-010----") then next_state <= st10; output <= "1000----01";
elsif std_match(input, "1-0001---") then next_state <= st1; output <= "1010100110";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st1 =>
if std_match(input, "------0--") then next_state <= st2; output <= "0110010000";
elsif std_match(input, "------1--") then next_state <= st8; output <= "0110100100";
end if;
when st2 =>
if std_match(input, "1-00000--") then next_state <= st2; output <= "010000--00";
elsif std_match(input, "1-10-----") then next_state <= st2; output <= "010000--00";
elsif std_match(input, "1-1-0----") then next_state <= st2; output <= "010000--00";
elsif std_match(input, "1-0010---") then next_state <= st3; output <= "010000--00";
elsif std_match(input, "1-0011---") then next_state <= st2; output <= "010100--00";
elsif std_match(input, "11-11----") then next_state <= st0; output <= "0010100000";
elsif std_match(input, "10-11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-010----") then next_state <= st2; output <= "010000--00";
elsif std_match(input, "1-0001---") then next_state <= st1; output <= "0110000100";
elsif std_match(input, "1-00001--") then next_state <= st7; output <= "010000--00";
elsif std_match(input, "01-------") then next_state <= st0; output <= "0010100000";
elsif std_match(input, "00-------") then next_state <= st0; output <= "0000------";
end if;
when st3 =>
if std_match(input, "1-0000---") then next_state <= st3; output <= "010000--00";
elsif std_match(input, "1-10-----") then next_state <= st3; output <= "010000--00";
elsif std_match(input, "1-1-0----") then next_state <= st3; output <= "010000--00";
elsif std_match(input, "1-0010---") then next_state <= st4; output <= "0110001000";
elsif std_match(input, "1-0011---") then next_state <= st3; output <= "010100--00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-010----") then next_state <= st3; output <= "010000--00";
elsif std_match(input, "1-0001---") then next_state <= st5; output <= "0110001100";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st4 =>
if std_match(input, "---------") then next_state <= st6; output <= "0110010000";
end if;
when st5 =>
if std_match(input, "---------") then next_state <= st1; output <= "0110010100";
end if;
when st6 =>
if std_match(input, "1-00000--") then next_state <= st6; output <= "010000--00";
elsif std_match(input, "1-10-----") then next_state <= st6; output <= "010000--00";
elsif std_match(input, "1-1-0----") then next_state <= st6; output <= "010000--00";
elsif std_match(input, "1-0010---") then next_state <= st4; output <= "0110001000";
elsif std_match(input, "1-0011---") then next_state <= st6; output <= "010100--00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-010----") then next_state <= st6; output <= "010000--00";
elsif std_match(input, "1-0001---") then next_state <= st1; output <= "0110000100";
elsif std_match(input, "1-00001--") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st7 =>
if std_match(input, "1-0000---") then next_state <= st7; output <= "110000--00";
elsif std_match(input, "1-10-----") then next_state <= st7; output <= "110000--00";
elsif std_match(input, "1-1-0----") then next_state <= st7; output <= "110000--00";
elsif std_match(input, "1-0010---") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "1-0011---") then next_state <= st7; output <= "110100--00";
elsif std_match(input, "11-11----") then next_state <= st0; output <= "0010100000";
elsif std_match(input, "10-11----") then next_state <= st0; output <= "0010------";
elsif std_match(input, "1-010----") then next_state <= st7; output <= "110000--00";
elsif std_match(input, "1-0001---") then next_state <= st8; output <= "0110100100";
elsif std_match(input, "01-------") then next_state <= st0; output <= "0010100000";
elsif std_match(input, "00-------") then next_state <= st0; output <= "0000------";
end if;
when st29 =>
if std_match(input, "1-0000---") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "1-10-----") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "1-1-0----") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "1-0010---") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "1-0011---") then next_state <= st29; output <= "110100--00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-010----") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "1-0001---") then next_state <= st8; output <= "0110100100";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st8 =>
if std_match(input, "---------") then next_state <= st9; output <= "0110010000";
end if;
when st9 =>
if std_match(input, "1-00000--") then next_state <= st9; output <= "010000--00";
elsif std_match(input, "1-10-----") then next_state <= st9; output <= "010000--00";
elsif std_match(input, "1-1-0----") then next_state <= st9; output <= "010000--00";
elsif std_match(input, "1-001----") then next_state <= st9; output <= "010000--00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0010100000";
elsif std_match(input, "1-010----") then next_state <= st9; output <= "010000--00";
elsif std_match(input, "1-00001--") then next_state <= st28; output <= "010010--00";
elsif std_match(input, "1-0001---") then next_state <= st8; output <= "0110000100";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0010100000";
end if;
when st28 =>
if std_match(input, "1-0000---") then next_state <= st28; output <= "110000--00";
elsif std_match(input, "1-10-----") then next_state <= st28; output <= "110000--00";
elsif std_match(input, "1-1-0----") then next_state <= st28; output <= "110000--00";
elsif std_match(input, "1-001----") then next_state <= st28; output <= "110000--00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0010100000";
elsif std_match(input, "1-010----") then next_state <= st10; output <= "110000--00";
elsif std_match(input, "1-0001---") then next_state <= st8; output <= "0110000100";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0010100000";
end if;
when st10 =>
if std_match(input, "1--0---00") then next_state <= st10; output <= "0000----00";
elsif std_match(input, "1---0--00") then next_state <= st10; output <= "0000----00";
elsif std_match(input, "1--0---10") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1---0--10") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1--0----1") then next_state <= st11; output <= "0000----00";
elsif std_match(input, "1---0---1") then next_state <= st11; output <= "0000----00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st11 =>
if std_match(input, "1--011-0-") then next_state <= st11; output <= "0000----00";
elsif std_match(input, "1---0--0-") then next_state <= st11; output <= "0000----00";
elsif std_match(input, "1--010-0-") then next_state <= st10; output <= "0100----00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1---0--1-") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1--0---1-") then next_state <= st0; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st12 =>
if std_match(input, "1--011---") then next_state <= st12; output <= "0000------";
elsif std_match(input, "1--10----") then next_state <= st12; output <= "0000------";
elsif std_match(input, "1--000---") then next_state <= st12; output <= "0000------";
elsif std_match(input, "1-0001---") then next_state <= st10; output <= "1000----01";
elsif std_match(input, "1--010---") then next_state <= st13; output <= "0000------";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st13 =>
if std_match(input, "1--000---") then next_state <= st13; output <= "0000------";
elsif std_match(input, "1--01----") then next_state <= st13; output <= "0000------";
elsif std_match(input, "1--001---") then next_state <= st14; output <= "0000----01";
elsif std_match(input, "1--10----") then next_state <= st14; output <= "0000----01";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st14 =>
if std_match(input, "1--000---") then next_state <= st14; output <= "0000----00";
elsif std_match(input, "1--01----") then next_state <= st14; output <= "0000----00";
elsif std_match(input, "1--10----") then next_state <= st14; output <= "0000----00";
elsif std_match(input, "1--001---") then next_state <= st15; output <= "0010100100";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st15 =>
if std_match(input, "--1------") then next_state <= st16; output <= "0010010000";
elsif std_match(input, "--0------") then next_state <= st22; output <= "0010010000";
end if;
when st16 =>
if std_match(input, "1--000---") then next_state <= st16; output <= "000000--00";
elsif std_match(input, "1--001---") then next_state <= st19; output <= "0010000100";
elsif std_match(input, "1--010---") then next_state <= st17; output <= "000000--00";
elsif std_match(input, "1--011---") then next_state <= st16; output <= "000000--00";
elsif std_match(input, "1--1-----") then next_state <= st16; output <= "000000--00";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st17 =>
if std_match(input, "1--000---") then next_state <= st17; output <= "000000--00";
elsif std_match(input, "1--001---") then next_state <= st18; output <= "0010001100";
elsif std_match(input, "1--010---") then next_state <= st20; output <= "0010001000";
elsif std_match(input, "1--011---") then next_state <= st17; output <= "000000--00";
elsif std_match(input, "1--1-----") then next_state <= st17; output <= "000000--00";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st18 =>
if std_match(input, "---------") then next_state <= st19; output <= "0010010100";
end if;
when st19 =>
if std_match(input, "---------") then next_state <= st16; output <= "0010010000";
end if;
when st20 =>
if std_match(input, "---------") then next_state <= st21; output <= "0010010000";
end if;
when st21 =>
if std_match(input, "1--000---") then next_state <= st21; output <= "000000--00";
elsif std_match(input, "1--001---") then next_state <= st19; output <= "0010000100";
elsif std_match(input, "1--010---") then next_state <= st20; output <= "0010001000";
elsif std_match(input, "1--011---") then next_state <= st21; output <= "000000--00";
elsif std_match(input, "1--1-----") then next_state <= st21; output <= "000000--00";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st22 =>
if std_match(input, "1-0000---") then next_state <= st22; output <= "000000--00";
elsif std_match(input, "1-0001---") then next_state <= st25; output <= "0010000100";
elsif std_match(input, "1-0010---") then next_state <= st23; output <= "000000--00";
elsif std_match(input, "1-0011---") then next_state <= st10; output <= "1000----11";
elsif std_match(input, "1-010----") then next_state <= st22; output <= "000000--00";
elsif std_match(input, "1-011----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-1------") then next_state <= st12; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st23 =>
if std_match(input, "1-0000---") then next_state <= st23; output <= "000000--00";
elsif std_match(input, "1-0001---") then next_state <= st24; output <= "0010001100";
elsif std_match(input, "1-0010---") then next_state <= st26; output <= "0010001000";
elsif std_match(input, "1-0011---") then next_state <= st10; output <= "1000----11";
elsif std_match(input, "1-010----") then next_state <= st23; output <= "000000--00";
elsif std_match(input, "1-011----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-1------") then next_state <= st12; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st24 =>
if std_match(input, "---------") then next_state <= st25; output <= "0010010100";
end if;
when st25 =>
if std_match(input, "---------") then next_state <= st22; output <= "0010010000";
end if;
when st26 =>
if std_match(input, "---------") then next_state <= st27; output <= "0010010000";
end if;
when st27 =>
if std_match(input, "1-0000---") then next_state <= st27; output <= "000000--00";
elsif std_match(input, "1-0001---") then next_state <= st25; output <= "0010000100";
elsif std_match(input, "1-0010---") then next_state <= st26; output <= "0010001000";
elsif std_match(input, "1-0011---") then next_state <= st10; output <= "1000----11";
elsif std_match(input, "1-010----") then next_state <= st27; output <= "000000--00";
elsif std_match(input, "1-011----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-1------") then next_state <= st12; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when others => next_state <= "-----"; output <= "----------";
end case;
end process;
end behaviour;
| agpl-3.0 | 149b25d6c702e176ca3c18c3b2bd7a1a | 0.553068 | 3.430247 | false | false | false | false |
TheMassController/VHDL_experimenting | project/bus/bus_demux.vhd | 1 | 1,823 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.bus_pkg.all;
entity bus_demux is
generic (
ADDRESS_MAP : addr_range_and_mapping_array;
OOR_FAULT_CODE : bus_data_type := (others => '1')
);
port (
rst : in std_logic;
mst2demux : in bus_mst2slv_type;
demux2mst : out bus_slv2mst_type;
demux2slv : out bus_mst2slv_array(ADDRESS_MAP'range);
slv2demux : in bus_slv2mst_array(ADDRESS_MAP'range)
);
end bus_demux;
architecture behaviourial of bus_demux is
begin
combinatoral : process(mst2demux, slv2demux, rst)
variable none_selected : boolean := true;
variable selected_slv : natural range 0 to ADDRESS_MAP'high := 0;
begin
demux2mst <= BUS_SLV2MST_IDLE;
for i in 0 to ADDRESS_MAP'high loop
demux2slv(i) <= BUS_MST2SLV_IDLE;
end loop;
none_selected := true;
selected_slv := 0;
if rst /= '1' and bus_requesting(mst2demux) = '1' then
for i in 0 to ADDRESS_MAP'high loop
if bus_addr_in_range(mst2demux.address, ADDRESS_MAP(i).addr_range) then
none_selected := false;
selected_slv := i;
end if;
end loop;
if none_selected then
demux2mst.fault <= '1';
demux2mst.readData <= OOR_FAULT_CODE;
else
demux2slv(selected_slv) <= mst2demux;
demux2slv(selected_slv).address <= bus_apply_addr_map(mst2demux.address, ADDRESS_MAP(selected_slv).mapping);
demux2mst <= slv2demux(selected_slv);
end if;
end if;
end process;
end architecture;
| mit | 6f64841bd21afbf88005f2cf6a3124c3 | 0.553483 | 3.668008 | false | false | false | false |
chastell/art-decomp | kiss/cse_nov.vhd | 1 | 10,008 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity cse_nov is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(6 downto 0)
);
end cse_nov;
architecture behaviour of cse_nov is
constant st0: std_logic_vector(3 downto 0) := "0000";
constant st1: std_logic_vector(3 downto 0) := "1101";
constant st2: std_logic_vector(3 downto 0) := "0101";
constant st3: std_logic_vector(3 downto 0) := "1100";
constant st4: std_logic_vector(3 downto 0) := "0100";
constant st5: std_logic_vector(3 downto 0) := "1111";
constant st6: std_logic_vector(3 downto 0) := "0110";
constant st7: std_logic_vector(3 downto 0) := "0010";
constant st8: std_logic_vector(3 downto 0) := "1010";
constant st9: std_logic_vector(3 downto 0) := "1110";
constant st10: std_logic_vector(3 downto 0) := "1000";
constant st11: std_logic_vector(3 downto 0) := "1001";
constant st12: std_logic_vector(3 downto 0) := "1011";
constant st13: std_logic_vector(3 downto 0) := "0001";
constant st14: std_logic_vector(3 downto 0) := "0111";
constant st15: std_logic_vector(3 downto 0) := "0011";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "-------";
case current_state is
when st0 =>
if std_match(input, "1-000--") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "1-11---") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "1-1-1--") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "10010--") then next_state <= st1; output <= "1100-10";
elsif std_match(input, "10011--") then next_state <= st9; output <= "0010001";
elsif std_match(input, "10001--") then next_state <= st6; output <= "0000-01";
elsif std_match(input, "10100--") then next_state <= st8; output <= "0000--0";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000-00";
end if;
when st1 =>
if std_match(input, "101----") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "10010--") then next_state <= st1; output <= "0100-00";
elsif std_match(input, "1000---") then next_state <= st2; output <= "0000-00";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000-10";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000-10";
end if;
when st2 =>
if std_match(input, "10010--") then next_state <= st1; output <= "1100-00";
elsif std_match(input, "10011--") then next_state <= st5; output <= "0001000";
elsif std_match(input, "10000--") then next_state <= st2; output <= "0000-00";
elsif std_match(input, "10001--") then next_state <= st3; output <= "1000-00";
elsif std_match(input, "101----") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "0-----0") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "0-----1") then next_state <= st0; output <= "0000-10";
elsif std_match(input, "-1----0") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "-1----1") then next_state <= st0; output <= "0000-10";
end if;
when st3 =>
if std_match(input, "10001--") then next_state <= st3; output <= "0000-00";
elsif std_match(input, "100-0--") then next_state <= st4; output <= "0000-00";
elsif std_match(input, "101----") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000-10";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000-10";
end if;
when st4 =>
if std_match(input, "101----") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "10010--") then next_state <= st1; output <= "1100-00";
elsif std_match(input, "1000---") then next_state <= st4; output <= "0000-00";
elsif std_match(input, "10011--") then next_state <= st5; output <= "0001000";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000-00";
end if;
when st5 =>
if std_match(input, "10-1---") then next_state <= st5; output <= "0000-00";
elsif std_match(input, "10-0---") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
end if;
when st6 =>
if std_match(input, "10--1--") then next_state <= st6; output <= "0000-00";
elsif std_match(input, "101----") then next_state <= st6; output <= "0000-00";
elsif std_match(input, "100-0--") then next_state <= st7; output <= "0000-00";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000-00";
end if;
when st7 =>
if std_match(input, "100--0-") then next_state <= st7; output <= "0000-00";
elsif std_match(input, "101--0-") then next_state <= st6; output <= "0000-01";
elsif std_match(input, "10---1-") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000-00";
end if;
when st8 =>
if std_match(input, "10-00--") then next_state <= st8; output <= "0000-00";
elsif std_match(input, "10010--") then next_state <= st9; output <= "0010101";
elsif std_match(input, "10-01--") then next_state <= st10; output <= "0000-10";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "10-11--") then next_state <= st0; output <= "0000--0";
end if;
when st9 =>
if std_match(input, "10-1---") then next_state <= st9; output <= "0000000";
elsif std_match(input, "10-0---") then next_state <= st7; output <= "0000000";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
end if;
when st10 =>
if std_match(input, "10-0---") then next_state <= st10; output <= "0000-00";
elsif std_match(input, "10-10--") then next_state <= st11; output <= "0000100";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "10-11--") then next_state <= st0; output <= "0000--0";
end if;
when st11 =>
if std_match(input, "10-10--") then next_state <= st11; output <= "0000000";
elsif std_match(input, "10-0---") then next_state <= st12; output <= "0000000";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "10-11--") then next_state <= st0; output <= "0000--0";
end if;
when st12 =>
if std_match(input, "10-0---") then next_state <= st12; output <= "0000000";
elsif std_match(input, "10-10--") then next_state <= st13; output <= "1000000";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "10-11--") then next_state <= st0; output <= "0000--0";
end if;
when st13 =>
if std_match(input, "10-10--") then next_state <= st13; output <= "0000000";
elsif std_match(input, "10-01--") then next_state <= st13; output <= "0000000";
elsif std_match(input, "10100--") then next_state <= st14; output <= "0000000";
elsif std_match(input, "10000--") then next_state <= st15; output <= "0000000";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
end if;
when st14 =>
if std_match(input, "--111--") then next_state <= st14; output <= "0000000";
elsif std_match(input, "--100--") then next_state <= st14; output <= "0000000";
elsif std_match(input, "--110--") then next_state <= st13; output <= "1000000";
elsif std_match(input, "--101--") then next_state <= st13; output <= "1000000";
elsif std_match(input, "--0----") then next_state <= st0; output <= "0001000";
end if;
when st15 =>
if std_match(input, "10000--") then next_state <= st15; output <= "0000000";
elsif std_match(input, "10010--") then next_state <= st13; output <= "1000000";
elsif std_match(input, "10001--") then next_state <= st13; output <= "1000000";
elsif std_match(input, "101----") then next_state <= st8; output <= "0001000";
elsif std_match(input, "0------") then next_state <= st0; output <= "0001000";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0001000";
elsif std_match(input, "10011--") then next_state <= st0; output <= "0001000";
end if;
when others => next_state <= "----"; output <= "-------";
end case;
end process;
end behaviour;
| agpl-3.0 | edcbb23ce829ad22cf7e2f2f046799d1 | 0.565248 | 3.317203 | false | false | false | false |
chastell/art-decomp | kiss/scf_nov.vhd | 1 | 39,256 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity scf_nov is
port(
clock: in std_logic;
input: in std_logic_vector(26 downto 0);
output: out std_logic_vector(55 downto 0)
);
end scf_nov;
architecture behaviour of scf_nov is
constant state1: std_logic_vector(6 downto 0) := "1000101";
constant state2: std_logic_vector(6 downto 0) := "1100001";
constant state3: std_logic_vector(6 downto 0) := "1111101";
constant state4: std_logic_vector(6 downto 0) := "1110101";
constant state5: std_logic_vector(6 downto 0) := "0010111";
constant state6: std_logic_vector(6 downto 0) := "1001101";
constant state7: std_logic_vector(6 downto 0) := "1101001";
constant state8: std_logic_vector(6 downto 0) := "1100111";
constant state9: std_logic_vector(6 downto 0) := "1100100";
constant state10: std_logic_vector(6 downto 0) := "1011101";
constant state11: std_logic_vector(6 downto 0) := "1000001";
constant state12: std_logic_vector(6 downto 0) := "1101111";
constant state13: std_logic_vector(6 downto 0) := "1110100";
constant state14: std_logic_vector(6 downto 0) := "0101101";
constant state15: std_logic_vector(6 downto 0) := "0101001";
constant state16: std_logic_vector(6 downto 0) := "1101101";
constant state17: std_logic_vector(6 downto 0) := "1010101";
constant state18: std_logic_vector(6 downto 0) := "1101110";
constant state19: std_logic_vector(6 downto 0) := "1110001";
constant state20: std_logic_vector(6 downto 0) := "0001110";
constant state21: std_logic_vector(6 downto 0) := "1100011";
constant state22: std_logic_vector(6 downto 0) := "0010000";
constant state23: std_logic_vector(6 downto 0) := "1101100";
constant state24: std_logic_vector(6 downto 0) := "0010011";
constant state25: std_logic_vector(6 downto 0) := "0001101";
constant state26: std_logic_vector(6 downto 0) := "1111110";
constant state27: std_logic_vector(6 downto 0) := "1100000";
constant state28: std_logic_vector(6 downto 0) := "0010101";
constant state29: std_logic_vector(6 downto 0) := "0010001";
constant state30: std_logic_vector(6 downto 0) := "0101111";
constant state31: std_logic_vector(6 downto 0) := "1001010";
constant state32: std_logic_vector(6 downto 0) := "1011110";
constant state33: std_logic_vector(6 downto 0) := "0001010";
constant state34: std_logic_vector(6 downto 0) := "0000001";
constant state35: std_logic_vector(6 downto 0) := "1011010";
constant state36: std_logic_vector(6 downto 0) := "1101010";
constant state37: std_logic_vector(6 downto 0) := "1111111";
constant state38: std_logic_vector(6 downto 0) := "0100000";
constant state39: std_logic_vector(6 downto 0) := "1011111";
constant state40: std_logic_vector(6 downto 0) := "0111010";
constant state41: std_logic_vector(6 downto 0) := "1000000";
constant state42: std_logic_vector(6 downto 0) := "0111110";
constant state43: std_logic_vector(6 downto 0) := "0101010";
constant state44: std_logic_vector(6 downto 0) := "0111111";
constant state45: std_logic_vector(6 downto 0) := "1110000";
constant state46: std_logic_vector(6 downto 0) := "0001111";
constant state47: std_logic_vector(6 downto 0) := "0011101";
constant state48: std_logic_vector(6 downto 0) := "0011001";
constant state49: std_logic_vector(6 downto 0) := "1101000";
constant state50: std_logic_vector(6 downto 0) := "0000110";
constant state51: std_logic_vector(6 downto 0) := "0011000";
constant state52: std_logic_vector(6 downto 0) := "0110001";
constant state53: std_logic_vector(6 downto 0) := "0011011";
constant state54: std_logic_vector(6 downto 0) := "1011100";
constant state55: std_logic_vector(6 downto 0) := "0100011";
constant state56: std_logic_vector(6 downto 0) := "1011011";
constant state57: std_logic_vector(6 downto 0) := "0100100";
constant state58: std_logic_vector(6 downto 0) := "1011000";
constant state59: std_logic_vector(6 downto 0) := "0100111";
constant state60: std_logic_vector(6 downto 0) := "1011001";
constant state61: std_logic_vector(6 downto 0) := "1100110";
constant state62: std_logic_vector(6 downto 0) := "0100101";
constant state63: std_logic_vector(6 downto 0) := "0001100";
constant state64: std_logic_vector(6 downto 0) := "1100101";
constant state65: std_logic_vector(6 downto 0) := "1110011";
constant state66: std_logic_vector(6 downto 0) := "0100010";
constant state67: std_logic_vector(6 downto 0) := "0001011";
constant state68: std_logic_vector(6 downto 0) := "0110100";
constant state69: std_logic_vector(6 downto 0) := "0000010";
constant state70: std_logic_vector(6 downto 0) := "1010110";
constant state71: std_logic_vector(6 downto 0) := "1000010";
constant state72: std_logic_vector(6 downto 0) := "1001001";
constant state73: std_logic_vector(6 downto 0) := "0010010";
constant state74: std_logic_vector(6 downto 0) := "0111100";
constant state75: std_logic_vector(6 downto 0) := "0110010";
constant state76: std_logic_vector(6 downto 0) := "1000011";
constant state77: std_logic_vector(6 downto 0) := "1010010";
constant state78: std_logic_vector(6 downto 0) := "0111101";
constant state79: std_logic_vector(6 downto 0) := "1110010";
constant state80: std_logic_vector(6 downto 0) := "1100010";
constant state81: std_logic_vector(6 downto 0) := "0011100";
constant state82: std_logic_vector(6 downto 0) := "0100110";
constant state83: std_logic_vector(6 downto 0) := "1010011";
constant state84: std_logic_vector(6 downto 0) := "0101000";
constant state85: std_logic_vector(6 downto 0) := "1010111";
constant state86: std_logic_vector(6 downto 0) := "1001000";
constant state87: std_logic_vector(6 downto 0) := "0011111";
constant state88: std_logic_vector(6 downto 0) := "0011010";
constant state89: std_logic_vector(6 downto 0) := "0111011";
constant state90: std_logic_vector(6 downto 0) := "1000100";
constant state91: std_logic_vector(6 downto 0) := "0111000";
constant state92: std_logic_vector(6 downto 0) := "1000111";
constant state93: std_logic_vector(6 downto 0) := "0111001";
constant state94: std_logic_vector(6 downto 0) := "0011110";
constant state95: std_logic_vector(6 downto 0) := "1000110";
constant state96: std_logic_vector(6 downto 0) := "0110110";
constant state97: std_logic_vector(6 downto 0) := "1111001";
constant state98: std_logic_vector(6 downto 0) := "0001000";
constant state99: std_logic_vector(6 downto 0) := "1110111";
constant state100: std_logic_vector(6 downto 0) := "0001001";
constant state101: std_logic_vector(6 downto 0) := "1110110";
constant state102: std_logic_vector(6 downto 0) := "0000111";
constant state103: std_logic_vector(6 downto 0) := "1111000";
constant state104: std_logic_vector(6 downto 0) := "0000100";
constant state105: std_logic_vector(6 downto 0) := "1101011";
constant state106: std_logic_vector(6 downto 0) := "0000101";
constant state107: std_logic_vector(6 downto 0) := "1111010";
constant state108: std_logic_vector(6 downto 0) := "0000011";
constant state109: std_logic_vector(6 downto 0) := "1111100";
constant state110: std_logic_vector(6 downto 0) := "0000000";
constant state111: std_logic_vector(6 downto 0) := "0010100";
constant state112: std_logic_vector(6 downto 0) := "1111011";
constant state113: std_logic_vector(6 downto 0) := "0010110";
constant state114: std_logic_vector(6 downto 0) := "0110111";
constant state115: std_logic_vector(6 downto 0) := "1001100";
constant state116: std_logic_vector(6 downto 0) := "0110101";
constant state117: std_logic_vector(6 downto 0) := "1001110";
constant state118: std_logic_vector(6 downto 0) := "0110011";
constant state119: std_logic_vector(6 downto 0) := "1010000";
constant state120: std_logic_vector(6 downto 0) := "0101110";
constant state121: std_logic_vector(6 downto 0) := "1001011";
signal current_state, next_state: std_logic_vector(6 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-------"; output <= "--------------------------------------------------------";
if std_match(input, "0--------------------------") then next_state <= state1; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
else
case current_state is
when state1 =>
if std_match(input, "1--------------------------") then next_state <= state3; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state2 =>
if std_match(input, "1--------------------------") then next_state <= state1; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state3 =>
if std_match(input, "1--------------------------") then next_state <= state4; output <= "00000010010000001-0000000-00-0001001000010-0-----00-0---";
end if;
when state4 =>
if std_match(input, "1--------------------------") then next_state <= state5; output <= "00000010000000000-0000000-00-0000000110101-0-----00-0---";
end if;
when state5 =>
if std_match(input, "1--------------------------") then next_state <= state7; output <= "00000001000000000-0000000-00-0000000001000-0-----00-0---";
end if;
when state6 =>
if std_match(input, "1--------------------------") then next_state <= state2; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state7 =>
if std_match(input, "1-----0--------------------") then next_state <= state9; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----1--------------------") then next_state <= state8; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state8 =>
if std_match(input, "1--------------------------") then next_state <= state17; output <= "00000010000000000-0000000-00-0000000001000-0-----00-0---";
end if;
when state9 =>
if std_match(input, "1----0---------------------") then next_state <= state12; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----1---------------------") then next_state <= state10; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state10 =>
if std_match(input, "1--------------------------") then next_state <= state11; output <= "00000010000000000-0000001-00-0000000000001-0-----00-0---";
end if;
when state11 =>
if std_match(input, "1--------------------------") then next_state <= state12; output <= "00000000000000000-0000000-00-0000010000000-0-----00-0---";
end if;
when state12 =>
if std_match(input, "1---0----------------------") then next_state <= state15; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1---1----------------------") then next_state <= state13; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state13 =>
if std_match(input, "1--------------------------") then next_state <= state29; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state14 =>
if std_match(input, "1--------------------------") then next_state <= state17; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state15 =>
if std_match(input, "1--------------------------") then next_state <= state59; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state16 =>
if std_match(input, "1--------------------------") then next_state <= state17; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state17 =>
if std_match(input, "1--------------------------") then next_state <= state18; output <= "0000000000010100001000000-10-000000000000011-----00-0---";
end if;
when state18 =>
if std_match(input, "1--------------------------") then next_state <= state19; output <= "00100000000000000-0000000-00-0000000000000-0000--00-0---";
end if;
when state19 =>
if std_match(input, "1--0-----------------------") then next_state <= state21; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--1-----------------------") then next_state <= state20; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state20 =>
if std_match(input, "1--------------------------") then next_state <= state21; output <= "00000001000000000-0000000-00-0000000100000-0-----00-0---";
end if;
when state21 =>
if std_match(input, "1--------------------------") then next_state <= state22; output <= "01000000000100000-0000000-10-100000000000000000001001---";
end if;
when state22 =>
if std_match(input, "1--------------------------") then next_state <= state23; output <= "00010000000000000-0000000-00-0000000000000-0000--01-0---";
end if;
when state23 =>
if std_match(input, "1--------------------------") then next_state <= state24; output <= "00000000100000000-0000000-00-0000000000000-0---0000-0---";
end if;
when state24 =>
if std_match(input, "1-0------------------------") then next_state <= state26; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-1------------------------") then next_state <= state25; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state25 =>
if std_match(input, "1--------------------------") then next_state <= state26; output <= "00000001000000000-0000000-00-0000000010000-0-----00-0---";
end if;
when state26 =>
if std_match(input, "10-------------------------") then next_state <= state28; output <= "00000000010000010-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "11-------------------------") then next_state <= state27; output <= "00000000010000010-0000000-00-0000000000000-0-----00-0---";
end if;
when state27 =>
if std_match(input, "1--------------------------") then next_state <= state28; output <= "00000000000000000-0000000-00-0010000000000-0-----00-0---";
end if;
when state28 =>
if std_match(input, "1--------------------------") then next_state <= state7; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state29 =>
if std_match(input, "1------1-------------------") then next_state <= state36; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------01------------------") then next_state <= state36; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0011----------------") then next_state <= state36; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0010----------------") then next_state <= state34; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0001----------------") then next_state <= state32; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0000----------------") then next_state <= state30; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state30 =>
if std_match(input, "1--------------------------") then next_state <= state38; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state31 =>
if std_match(input, "1--------------------------") then next_state <= state37; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state32 =>
if std_match(input, "1--------------------------") then next_state <= state55; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state33 =>
if std_match(input, "1--------------------------") then next_state <= state37; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state34 =>
if std_match(input, "1--------------------------") then next_state <= state57; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state35 =>
if std_match(input, "1--------------------------") then next_state <= state37; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state36 =>
if std_match(input, "1--------------------------") then next_state <= state37; output <= "00000001000000000-0000000-00-0000000010000-0-----00-0---";
end if;
when state37 =>
if std_match(input, "1--------------------------") then next_state <= state14; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state38 =>
if std_match(input, "1----------1---------------") then next_state <= state43; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----------01--------------") then next_state <= state43; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----------001-------------") then next_state <= state43; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----------0001------------") then next_state <= state41; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----------0000------------") then next_state <= state39; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state39 =>
if std_match(input, "1--------------------------") then next_state <= state45; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state40 =>
if std_match(input, "1--------------------------") then next_state <= state44; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state41 =>
if std_match(input, "1--------------------------") then next_state <= state50; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state42 =>
if std_match(input, "1--------------------------") then next_state <= state44; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state43 =>
if std_match(input, "1--------------------------") then next_state <= state44; output <= "00000001000000000-0000000-00-0000000010000-0-----00-0---";
end if;
when state44 =>
if std_match(input, "1--------------------------") then next_state <= state31; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state45 =>
if std_match(input, "1--------------0-----------") then next_state <= state48; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--------------1-----------") then next_state <= state46; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state46 =>
if std_match(input, "1--------------------------") then next_state <= state47; output <= "0000000001000101001000000-00-0000000000000-0-----00-0---";
end if;
when state47 =>
if std_match(input, "1--------------------------") then next_state <= state49; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state48 =>
if std_match(input, "1--------------------------") then next_state <= state49; output <= "0000000000100000111001010-00-0000000000000-0-----00-0---";
end if;
when state49 =>
if std_match(input, "1--------------------------") then next_state <= state40; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state50 =>
if std_match(input, "1--------------0-----------") then next_state <= state52; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--------------1-----------") then next_state <= state51; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state51 =>
if std_match(input, "1--------------------------") then next_state <= state54; output <= "0000000000100000111001010-00-0000000000000-0-----00-0---";
end if;
when state52 =>
if std_match(input, "1--------------------------") then next_state <= state53; output <= "0000000000000101001000000-00-0000000000000-0-----00-0---";
end if;
when state53 =>
if std_match(input, "1--------------------------") then next_state <= state54; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state54 =>
if std_match(input, "1--------------------------") then next_state <= state42; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state55 =>
if std_match(input, "1--------------------------") then next_state <= state56; output <= "0000000000100000111001010-00-0000000000000-0-----00-0---";
end if;
when state56 =>
if std_match(input, "1--------------------------") then next_state <= state33; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state57 =>
if std_match(input, "1--------------------------") then next_state <= state58; output <= "00000000001000001-0001000-00-0000000000000-0-----00-0---";
end if;
when state58 =>
if std_match(input, "1--------------------------") then next_state <= state35; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state59 =>
if std_match(input, "1---------------0----------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1---------------1----------") then next_state <= state60; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state60 =>
if std_match(input, "1------1-------------------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------01------------------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0011----------------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0010----------------") then next_state <= state65; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0001----------------") then next_state <= state63; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0000----------------") then next_state <= state61; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state61 =>
if std_match(input, "1--------------------------") then next_state <= state82; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state62 =>
if std_match(input, "1--------------------------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state63 =>
if std_match(input, "1--------------------------") then next_state <= state83; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state64 =>
if std_match(input, "1--------------------------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state65 =>
if std_match(input, "1--------------------------") then next_state <= state89; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state66 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state67 =>
if std_match(input, "1------1-------------------") then next_state <= state80; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------011-----------------") then next_state <= state80; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0101----------------") then next_state <= state78; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0100----------------") then next_state <= state76; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0011----------------") then next_state <= state74; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0010----------------") then next_state <= state72; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0001----------------") then next_state <= state70; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0000----------------") then next_state <= state68; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state68 =>
if std_match(input, "1--------------------------") then next_state <= state96; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state69 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state70 =>
if std_match(input, "1--------------------------") then next_state <= state98; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state71 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state72 =>
if std_match(input, "1--------------------------") then next_state <= state103; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state73 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state74 =>
if std_match(input, "1--------------------------") then next_state <= state107; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state75 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state76 =>
if std_match(input, "1--------------------------") then next_state <= state115; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state77 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state78 =>
if std_match(input, "1--------------------------") then next_state <= state117; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state79 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state80 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000001000000000-0000000-00-0000000010000-0-----00-0---";
end if;
when state81 =>
if std_match(input, "1--------------------------") then next_state <= state16; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state82 =>
if std_match(input, "1--------------------------") then next_state <= state62; output <= "00000001000000000-0000000-00-0000000010000-0-----00-0---";
end if;
when state83 =>
if std_match(input, "1--------------------------") then next_state <= state84; output <= "00000001000000000-0000000-00-0000000001000-0-----00-0---";
end if;
when state84 =>
if std_match(input, "1--------------------------") then next_state <= state86; output <= "00001000000001001-0000000-00-0000000000000-0100--00-0---";
end if;
when state85 =>
if std_match(input, "1--------------------------") then next_state <= state64; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state86 =>
if std_match(input, "1----------------0---------") then next_state <= state88; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----------------1---------") then next_state <= state87; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state87 =>
if std_match(input, "1--------------------------") then next_state <= state16; output <= "00000001000000000-0000000-00-0000100001000-0-----00-0---";
end if;
when state88 =>
if std_match(input, "1--------------------------") then next_state <= state86; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state89 =>
if std_match(input, "1--------------------------") then next_state <= state91; output <= "00001001000000000-0000000-00-0001000001000-0-----00-0---";
end if;
when state90 =>
if std_match(input, "1--------------------------") then next_state <= state66; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state91 =>
if std_match(input, "1--------------------------") then next_state <= state92; output <= "00000010000000000-0000000-00-0000000000000-0010--00-0---";
end if;
when state92 =>
if std_match(input, "1--0-----------------------") then next_state <= state95; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--1-----------------------") then next_state <= state93; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state93 =>
if std_match(input, "1--------------------------") then next_state <= state94; output <= "00000000000100001-0000000-10-0000000000000-0-----00-0---";
end if;
when state94 =>
if std_match(input, "1--------------------------") then next_state <= state16; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state95 =>
if std_match(input, "1--------------------------") then next_state <= state91; output <= "00000000000000000-0000000-00-0010100000000-0-----00-0---";
end if;
when state96 =>
if std_match(input, "1--------------------------") then next_state <= state97; output <= "00000100000001000-0000000-00-000000000000011101111011101";
end if;
when state97 =>
if std_match(input, "1--------------------------") then next_state <= state69; output <= "001000010000000100101010010110100000000001-0-----00-0---";
end if;
when state98 =>
if std_match(input, "1--------------0-----------") then next_state <= state101; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--------------1-----------") then next_state <= state99; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state99 =>
if std_match(input, "1--------------------------") then next_state <= state100; output <= "00000100000001000-0000000-00-000000000000011101111011101";
end if;
when state100 =>
if std_match(input, "1--------------------------") then next_state <= state102; output <= "001000010000000100101010010110100000000001-0-----00-0---";
end if;
when state101 =>
if std_match(input, "1--------------------------") then next_state <= state102; output <= "00000100000001001-0000000-00-0000000001000-0100--00-0---";
end if;
when state102 =>
if std_match(input, "1--------------------------") then next_state <= state71; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state103 =>
if std_match(input, "1--------------0-----------") then next_state <= state105; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--------------1-----------") then next_state <= state104; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state104 =>
if std_match(input, "1--------------------------") then next_state <= state106; output <= "0000000000000101001000000-00-0000000000000-0-----00-0---";
end if;
when state105 =>
if std_match(input, "1--------------------------") then next_state <= state106; output <= "00000100000001001-0000000-00-0000000001000-0100--00-0---";
end if;
when state106 =>
if std_match(input, "1--------------------------") then next_state <= state73; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state107 =>
if std_match(input, "1--------------0-----------") then next_state <= state112; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--------------1-----------") then next_state <= state108; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state108 =>
if std_match(input, "1-----------------00000000-") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------1--------") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------01-------") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------001------") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------0001-----") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------00001----") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------000001---") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------0000001--") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------00000001-") then next_state <= state109; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state109 =>
if std_match(input, "1--------------------------") then next_state <= state112; output <= "0000000000001100101000000-00-0000000000000-0-----00-0100";
end if;
when state110 =>
if std_match(input, "1--------------------------") then next_state <= state111; output <= "0000010000000101001010000-0000100000000000111000110-0100";
end if;
when state111 =>
if std_match(input, "1--------------------------") then next_state <= state114; output <= "00000001000000000-0000100001-0000000000001-0-----00-0---";
end if;
when state112 =>
if std_match(input, "1--------------------------") then next_state <= state113; output <= "00000100000001001-0000000-00-0000000000000-0100--00-0---";
end if;
when state113 =>
if std_match(input, "1--------------------------") then next_state <= state114; output <= "00000001000000000-0000000-00-0000000001000-0-----00-0---";
end if;
when state114 =>
if std_match(input, "1--------------------------") then next_state <= state75; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state115 =>
if std_match(input, "1--------------------------") then next_state <= state116; output <= "00001000000010001-0010000-00-0000000000000-01011010-0101";
end if;
when state116 =>
if std_match(input, "1--------------------------") then next_state <= state77; output <= "10000001000000000-0000100-00-0001000001101-0-----00-0---";
end if;
when state117 =>
if std_match(input, "1--------------------------") then next_state <= state118; output <= "00000010000000000-0000000-00-0000000000000-0-----00-0011";
end if;
when state118 =>
if std_match(input, "1-------------------------0") then next_state <= state121; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-------------------------1") then next_state <= state119; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state119 =>
if std_match(input, "1--------------------------") then next_state <= state120; output <= "0000010000001000001000000-00-0000000000000111011010-0101";
end if;
when state120 =>
if std_match(input, "1--------------------------") then next_state <= state16; output <= "00010010000000010-000000000110100000000100-0-----00-0---";
end if;
when state121 =>
if std_match(input, "1--------------------------") then next_state <= state79; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when others => next_state <= "-------"; output <= "--------------------------------------------------------";
end case;
end if;
end process;
end behaviour;
| agpl-3.0 | 89c3d6ae5c07248204abcad8cecec837 | 0.566767 | 4.06461 | false | false | false | false |
chastell/art-decomp | kiss/s27_hot.vhd | 1 | 3,893 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s27_hot is
port(
clock: in std_logic;
input: in std_logic_vector(3 downto 0);
output: out std_logic_vector(0 downto 0)
);
end s27_hot;
architecture behaviour of s27_hot is
constant s000: std_logic_vector(5 downto 0) := "100000";
constant s001: std_logic_vector(5 downto 0) := "010000";
constant s101: std_logic_vector(5 downto 0) := "001000";
constant s100: std_logic_vector(5 downto 0) := "000100";
constant s010: std_logic_vector(5 downto 0) := "000010";
constant s011: std_logic_vector(5 downto 0) := "000001";
signal current_state, next_state: std_logic_vector(5 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "------"; output <= "-";
case current_state is
when s000 =>
if std_match(input, "010-") then next_state <= s001; output <= "1";
elsif std_match(input, "011-") then next_state <= s000; output <= "1";
elsif std_match(input, "110-") then next_state <= s101; output <= "1";
elsif std_match(input, "111-") then next_state <= s100; output <= "1";
elsif std_match(input, "10-0") then next_state <= s100; output <= "1";
elsif std_match(input, "00-0") then next_state <= s000; output <= "1";
elsif std_match(input, "-0-1") then next_state <= s010; output <= "0";
end if;
when s001 =>
if std_match(input, "0-0-") then next_state <= s001; output <= "1";
elsif std_match(input, "0-1-") then next_state <= s000; output <= "1";
elsif std_match(input, "1-0-") then next_state <= s101; output <= "1";
elsif std_match(input, "1-1-") then next_state <= s100; output <= "1";
end if;
when s101 =>
if std_match(input, "0-0-") then next_state <= s001; output <= "1";
elsif std_match(input, "0-1-") then next_state <= s000; output <= "1";
elsif std_match(input, "1-0-") then next_state <= s101; output <= "1";
elsif std_match(input, "1-1-") then next_state <= s100; output <= "1";
end if;
when s100 =>
if std_match(input, "010-") then next_state <= s001; output <= "1";
elsif std_match(input, "011-") then next_state <= s000; output <= "1";
elsif std_match(input, "00--") then next_state <= s000; output <= "1";
elsif std_match(input, "111-") then next_state <= s100; output <= "1";
elsif std_match(input, "110-") then next_state <= s101; output <= "1";
elsif std_match(input, "10--") then next_state <= s100; output <= "1";
end if;
when s010 =>
if std_match(input, "0-1-") then next_state <= s010; output <= "0";
elsif std_match(input, "000-") then next_state <= s010; output <= "0";
elsif std_match(input, "010-") then next_state <= s011; output <= "0";
elsif std_match(input, "1101") then next_state <= s101; output <= "1";
elsif std_match(input, "1111") then next_state <= s100; output <= "1";
elsif std_match(input, "10-1") then next_state <= s010; output <= "0";
elsif std_match(input, "1100") then next_state <= s101; output <= "1";
elsif std_match(input, "1110") then next_state <= s100; output <= "1";
elsif std_match(input, "10-0") then next_state <= s100; output <= "1";
end if;
when s011 =>
if std_match(input, "0-0-") then next_state <= s011; output <= "0";
elsif std_match(input, "0-1-") then next_state <= s010; output <= "0";
elsif std_match(input, "1-1-") then next_state <= s100; output <= "1";
elsif std_match(input, "1-0-") then next_state <= s101; output <= "1";
end if;
when others => next_state <= "------"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 | d817cc8bb1a0ab71e0f02184b1d3c734 | 0.577447 | 3.20148 | false | false | false | false |
chastell/art-decomp | kiss/s510_rnd.vhd | 1 | 13,167 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s510_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(18 downto 0);
output: out std_logic_vector(6 downto 0)
);
end s510_rnd;
architecture behaviour of s510_rnd is
constant s000000: std_logic_vector(5 downto 0) := "111101";
constant s010010: std_logic_vector(5 downto 0) := "000010";
constant s010011: std_logic_vector(5 downto 0) := "011011";
constant s000100: std_logic_vector(5 downto 0) := "111110";
constant s000001: std_logic_vector(5 downto 0) := "111111";
constant s100101: std_logic_vector(5 downto 0) := "010001";
constant s100100: std_logic_vector(5 downto 0) := "010110";
constant s000010: std_logic_vector(5 downto 0) := "001011";
constant s000011: std_logic_vector(5 downto 0) := "001111";
constant s011100: std_logic_vector(5 downto 0) := "011110";
constant s011101: std_logic_vector(5 downto 0) := "101011";
constant s000111: std_logic_vector(5 downto 0) := "100001";
constant s000101: std_logic_vector(5 downto 0) := "110000";
constant s010000: std_logic_vector(5 downto 0) := "101111";
constant s010001: std_logic_vector(5 downto 0) := "011010";
constant s001000: std_logic_vector(5 downto 0) := "111000";
constant s001001: std_logic_vector(5 downto 0) := "110110";
constant s010100: std_logic_vector(5 downto 0) := "001000";
constant s010101: std_logic_vector(5 downto 0) := "000001";
constant s001010: std_logic_vector(5 downto 0) := "100100";
constant s001011: std_logic_vector(5 downto 0) := "001001";
constant s011000: std_logic_vector(5 downto 0) := "101001";
constant s011001: std_logic_vector(5 downto 0) := "100110";
constant s011010: std_logic_vector(5 downto 0) := "111011";
constant s011011: std_logic_vector(5 downto 0) := "011100";
constant s001100: std_logic_vector(5 downto 0) := "100011";
constant s001101: std_logic_vector(5 downto 0) := "100010";
constant s011110: std_logic_vector(5 downto 0) := "011000";
constant s011111: std_logic_vector(5 downto 0) := "000011";
constant s100000: std_logic_vector(5 downto 0) := "110111";
constant s100001: std_logic_vector(5 downto 0) := "010011";
constant s100010: std_logic_vector(5 downto 0) := "110010";
constant s100011: std_logic_vector(5 downto 0) := "000111";
constant s001110: std_logic_vector(5 downto 0) := "001100";
constant s001111: std_logic_vector(5 downto 0) := "110101";
constant s100110: std_logic_vector(5 downto 0) := "010100";
constant s100111: std_logic_vector(5 downto 0) := "000000";
constant s101000: std_logic_vector(5 downto 0) := "100111";
constant s101001: std_logic_vector(5 downto 0) := "011101";
constant s101010: std_logic_vector(5 downto 0) := "101101";
constant s101011: std_logic_vector(5 downto 0) := "100101";
constant s101100: std_logic_vector(5 downto 0) := "100000";
constant s101101: std_logic_vector(5 downto 0) := "111100";
constant s101110: std_logic_vector(5 downto 0) := "000100";
constant s010110: std_logic_vector(5 downto 0) := "110011";
constant s010111: std_logic_vector(5 downto 0) := "010111";
constant s000110: std_logic_vector(5 downto 0) := "111010";
signal current_state, next_state: std_logic_vector(5 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "------"; output <= "-------";
case current_state is
when s000000 =>
if std_match(input, "-------------------") then next_state <= s010010; output <= "0011100";
end if;
when s010010 =>
if std_match(input, "--1----------------") then next_state <= s010011; output <= "0000100";
elsif std_match(input, "--0----------------") then next_state <= s010010; output <= "0000100";
end if;
when s010011 =>
if std_match(input, "-------------------") then next_state <= s000100; output <= "0001101";
end if;
when s000100 =>
if std_match(input, "---11--------------") then next_state <= s000001; output <= "0000101";
elsif std_match(input, "---10--------------") then next_state <= s000000; output <= "0000101";
elsif std_match(input, "---0---------------") then next_state <= s000100; output <= "0000101";
end if;
when s000001 =>
if std_match(input, "-------------------") then next_state <= s100101; output <= "0011000";
end if;
when s100101 =>
if std_match(input, "-----1-------------") then next_state <= s100100; output <= "0000000";
elsif std_match(input, "-----0-------------") then next_state <= s100101; output <= "0000000";
end if;
when s100100 =>
if std_match(input, "-------------------") then next_state <= s000010; output <= "0001001";
end if;
when s000010 =>
if std_match(input, "------0------------") then next_state <= s000010; output <= "0000001";
elsif std_match(input, "------10-----------") then next_state <= s000001; output <= "0000001";
elsif std_match(input, "------11-----------") then next_state <= s000011; output <= "0000001";
end if;
when s000011 =>
if std_match(input, "-------------------") then next_state <= s011100; output <= "0011100";
end if;
when s011100 =>
if std_match(input, "--1----------------") then next_state <= s011101; output <= "0000100";
elsif std_match(input, "--0----------------") then next_state <= s011100; output <= "0000100";
end if;
when s011101 =>
if std_match(input, "-------------------") then next_state <= s000111; output <= "0001101";
end if;
when s000111 =>
if std_match(input, "---0---------------") then next_state <= s000111; output <= "0000101";
elsif std_match(input, "---1----0----------") then next_state <= s000011; output <= "0000101";
elsif std_match(input, "---1----1----------") then next_state <= s000101; output <= "0000101";
end if;
when s000101 =>
if std_match(input, "-------------------") then next_state <= s010000; output <= "0001100";
end if;
when s010000 =>
if std_match(input, "--1----------------") then next_state <= s010001; output <= "0000100";
elsif std_match(input, "--0----------------") then next_state <= s010000; output <= "0000100";
end if;
when s010001 =>
if std_match(input, "-------------------") then next_state <= s001000; output <= "0001101";
end if;
when s001000 =>
if std_match(input, "---------0---------") then next_state <= s001000; output <= "0000101";
elsif std_match(input, "---------1---------") then next_state <= s001001; output <= "0000101";
end if;
when s001001 =>
if std_match(input, "-------------------") then next_state <= s010100; output <= "0011100";
end if;
when s010100 =>
if std_match(input, "----------0--------") then next_state <= s010100; output <= "0000100";
elsif std_match(input, "----------1--------") then next_state <= s010101; output <= "0000100";
end if;
when s010101 =>
if std_match(input, "-------------------") then next_state <= s001010; output <= "0001101";
end if;
when s001010 =>
if std_match(input, "-----------00------") then next_state <= s001010; output <= "0000101";
elsif std_match(input, "-----------10------") then next_state <= s001001; output <= "0000101";
elsif std_match(input, "-----------01------") then next_state <= s001010; output <= "0000101";
elsif std_match(input, "-----------11------") then next_state <= s001011; output <= "0000101";
end if;
when s001011 =>
if std_match(input, "-------------------") then next_state <= s011000; output <= "0101100";
end if;
when s011000 =>
if std_match(input, "----------0--------") then next_state <= s011000; output <= "0000100";
elsif std_match(input, "----------1--------") then next_state <= s011001; output <= "0000100";
end if;
when s011001 =>
if std_match(input, "-------------------") then next_state <= s011010; output <= "0001101";
end if;
when s011010 =>
if std_match(input, "-------------0-----") then next_state <= s011010; output <= "0000101";
elsif std_match(input, "-------------1-----") then next_state <= s011011; output <= "0000101";
end if;
when s011011 =>
if std_match(input, "-------------------") then next_state <= s001100; output <= "0001111";
end if;
when s001100 =>
if std_match(input, "--------------0----") then next_state <= s001100; output <= "0000111";
elsif std_match(input, "--------------1----") then next_state <= s001101; output <= "0000111";
end if;
when s001101 =>
if std_match(input, "-------------------") then next_state <= s011110; output <= "0001101";
end if;
when s011110 =>
if std_match(input, "---------------1---") then next_state <= s011111; output <= "0000101";
elsif std_match(input, "---------------0---") then next_state <= s011110; output <= "0000101";
end if;
when s011111 =>
if std_match(input, "-------------------") then next_state <= s100000; output <= "0011100";
end if;
when s100000 =>
if std_match(input, "----------1--------") then next_state <= s100001; output <= "0000100";
elsif std_match(input, "----------0--------") then next_state <= s100000; output <= "0000100";
end if;
when s100001 =>
if std_match(input, "-------------------") then next_state <= s100010; output <= "0001101";
end if;
when s100010 =>
if std_match(input, "------0------------") then next_state <= s100010; output <= "0000101";
elsif std_match(input, "------1------------") then next_state <= s100011; output <= "0000101";
end if;
when s100011 =>
if std_match(input, "-------------------") then next_state <= s001110; output <= "0001111";
end if;
when s001110 =>
if std_match(input, "----------------00-") then next_state <= s001110; output <= "0000111";
elsif std_match(input, "----------------10-") then next_state <= s001101; output <= "0000111";
elsif std_match(input, "----------------01-") then next_state <= s001110; output <= "0000111";
elsif std_match(input, "----------------11-") then next_state <= s001111; output <= "0000111";
end if;
when s001111 =>
if std_match(input, "-------------------") then next_state <= s100110; output <= "0001101";
end if;
when s100110 =>
if std_match(input, "---------------1---") then next_state <= s100111; output <= "0000101";
elsif std_match(input, "---------------0---") then next_state <= s100110; output <= "0000101";
end if;
when s100111 =>
if std_match(input, "-------------------") then next_state <= s101000; output <= "0001100";
end if;
when s101000 =>
if std_match(input, "----------0--------") then next_state <= s101000; output <= "0000100";
elsif std_match(input, "----------1--------") then next_state <= s101001; output <= "0000100";
end if;
when s101001 =>
if std_match(input, "-------------------") then next_state <= s101010; output <= "0001101";
end if;
when s101010 =>
if std_match(input, "------0------------") then next_state <= s101010; output <= "0000101";
elsif std_match(input, "------1------------") then next_state <= s101011; output <= "0000101";
end if;
when s101011 =>
if std_match(input, "-------------------") then next_state <= s101100; output <= "0001111";
end if;
when s101100 =>
if std_match(input, "------------------1") then next_state <= s101101; output <= "0000111";
elsif std_match(input, "------------------0") then next_state <= s101100; output <= "0000111";
end if;
when s101101 =>
if std_match(input, "-------------------") then next_state <= s101110; output <= "1000111";
end if;
when s101110 =>
if std_match(input, "-------------------") then next_state <= s010110; output <= "1000111";
end if;
when s010110 =>
if std_match(input, "1------------------") then next_state <= s010111; output <= "0000000";
elsif std_match(input, "0------------------") then next_state <= s010110; output <= "0000000";
end if;
when s010111 =>
if std_match(input, "-------------------") then next_state <= s000110; output <= "0101100";
end if;
when s000110 =>
if std_match(input, "-1-----------------") then next_state <= s000000; output <= "0000100";
elsif std_match(input, "-0-----------------") then next_state <= s000110; output <= "0000100";
end if;
when others => next_state <= "------"; output <= "-------";
end case;
end process;
end behaviour;
| agpl-3.0 | a362196f9c660860216e9aba3ec47a3f | 0.536189 | 3.970748 | false | false | false | false |
chastell/art-decomp | kiss/dk14_rnd.vhd | 1 | 6,084 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk14_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(2 downto 0);
output: out std_logic_vector(4 downto 0)
);
end dk14_rnd;
architecture behaviour of dk14_rnd is
constant state_1: std_logic_vector(2 downto 0) := "101";
constant state_3: std_logic_vector(2 downto 0) := "010";
constant state_2: std_logic_vector(2 downto 0) := "011";
constant state_4: std_logic_vector(2 downto 0) := "110";
constant state_5: std_logic_vector(2 downto 0) := "111";
constant state_6: std_logic_vector(2 downto 0) := "001";
constant state_7: std_logic_vector(2 downto 0) := "000";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "-----";
case current_state is
when state_1 =>
if std_match(input, "000") then next_state <= state_3; output <= "00010";
elsif std_match(input, "100") then next_state <= state_4; output <= "00010";
elsif std_match(input, "111") then next_state <= state_3; output <= "01010";
elsif std_match(input, "110") then next_state <= state_4; output <= "01010";
elsif std_match(input, "011") then next_state <= state_3; output <= "01000";
elsif std_match(input, "001") then next_state <= state_5; output <= "00010";
elsif std_match(input, "101") then next_state <= state_5; output <= "01010";
elsif std_match(input, "010") then next_state <= state_6; output <= "01000";
end if;
when state_2 =>
if std_match(input, "000") then next_state <= state_1; output <= "01001";
elsif std_match(input, "100") then next_state <= state_2; output <= "01001";
elsif std_match(input, "111") then next_state <= state_3; output <= "00100";
elsif std_match(input, "110") then next_state <= state_5; output <= "00100";
elsif std_match(input, "011") then next_state <= state_2; output <= "00101";
elsif std_match(input, "001") then next_state <= state_1; output <= "00101";
elsif std_match(input, "101") then next_state <= state_1; output <= "00001";
elsif std_match(input, "010") then next_state <= state_2; output <= "00001";
end if;
when state_3 =>
if std_match(input, "000") then next_state <= state_3; output <= "10010";
elsif std_match(input, "100") then next_state <= state_4; output <= "10010";
elsif std_match(input, "111") then next_state <= state_3; output <= "01010";
elsif std_match(input, "110") then next_state <= state_4; output <= "01010";
elsif std_match(input, "011") then next_state <= state_3; output <= "01000";
elsif std_match(input, "001") then next_state <= state_5; output <= "10010";
elsif std_match(input, "101") then next_state <= state_5; output <= "01010";
elsif std_match(input, "010") then next_state <= state_6; output <= "01000";
end if;
when state_4 =>
if std_match(input, "000") then next_state <= state_3; output <= "00010";
elsif std_match(input, "100") then next_state <= state_4; output <= "00010";
elsif std_match(input, "111") then next_state <= state_3; output <= "00100";
elsif std_match(input, "110") then next_state <= state_5; output <= "00100";
elsif std_match(input, "011") then next_state <= state_3; output <= "10100";
elsif std_match(input, "001") then next_state <= state_5; output <= "00010";
elsif std_match(input, "101") then next_state <= state_5; output <= "10100";
elsif std_match(input, "010") then next_state <= state_7; output <= "10000";
end if;
when state_5 =>
if std_match(input, "000") then next_state <= state_1; output <= "01001";
elsif std_match(input, "100") then next_state <= state_2; output <= "01001";
elsif std_match(input, "111") then next_state <= state_1; output <= "10001";
elsif std_match(input, "110") then next_state <= state_1; output <= "10101";
elsif std_match(input, "011") then next_state <= state_2; output <= "00101";
elsif std_match(input, "001") then next_state <= state_1; output <= "00101";
elsif std_match(input, "101") then next_state <= state_2; output <= "10001";
elsif std_match(input, "010") then next_state <= state_2; output <= "10101";
end if;
when state_6 =>
if std_match(input, "000") then next_state <= state_1; output <= "01001";
elsif std_match(input, "100") then next_state <= state_2; output <= "01001";
elsif std_match(input, "111") then next_state <= state_1; output <= "10001";
elsif std_match(input, "110") then next_state <= state_1; output <= "10101";
elsif std_match(input, "011") then next_state <= state_3; output <= "10100";
elsif std_match(input, "001") then next_state <= state_5; output <= "10100";
elsif std_match(input, "101") then next_state <= state_2; output <= "10001";
elsif std_match(input, "010") then next_state <= state_2; output <= "10101";
end if;
when state_7 =>
if std_match(input, "000") then next_state <= state_3; output <= "10010";
elsif std_match(input, "100") then next_state <= state_4; output <= "10010";
elsif std_match(input, "111") then next_state <= state_1; output <= "10001";
elsif std_match(input, "110") then next_state <= state_1; output <= "10101";
elsif std_match(input, "011") then next_state <= state_3; output <= "10100";
elsif std_match(input, "001") then next_state <= state_5; output <= "10010";
elsif std_match(input, "101") then next_state <= state_2; output <= "10001";
elsif std_match(input, "010") then next_state <= state_2; output <= "10101";
end if;
when others => next_state <= "---"; output <= "-----";
end case;
end process;
end behaviour;
| agpl-3.0 | ea1afff99cb999381957ea3a743fc09e | 0.599277 | 3.368771 | false | false | false | false |
chastell/art-decomp | kiss/kirkman_jed.vhd | 1 | 35,882 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity kirkman_jed is
port(
clock: in std_logic;
input: in std_logic_vector(11 downto 0);
output: out std_logic_vector(5 downto 0)
);
end kirkman_jed;
architecture behaviour of kirkman_jed is
constant rst0: std_logic_vector(3 downto 0) := "0100";
constant bit1: std_logic_vector(3 downto 0) := "0101";
constant bit2: std_logic_vector(3 downto 0) := "0111";
constant bit3: std_logic_vector(3 downto 0) := "0001";
constant bit4: std_logic_vector(3 downto 0) := "1101";
constant bit5: std_logic_vector(3 downto 0) := "1110";
constant bit6: std_logic_vector(3 downto 0) := "1010";
constant bit7: std_logic_vector(3 downto 0) := "1011";
constant bit8: std_logic_vector(3 downto 0) := "1000";
constant bit9: std_logic_vector(3 downto 0) := "1111";
constant bitA: std_logic_vector(3 downto 0) := "1001";
constant bitB: std_logic_vector(3 downto 0) := "1100";
constant bitC: std_logic_vector(3 downto 0) := "0010";
constant bitD: std_logic_vector(3 downto 0) := "0000";
constant bitE: std_logic_vector(3 downto 0) := "0110";
constant bitF: std_logic_vector(3 downto 0) := "0011";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "------";
if std_match(input, "--------1---") then next_state <= rst0; output <= "1-----";
else
case current_state is
when rst0 =>
if std_match(input, "--------0000") then next_state <= rst0; output <= "0----0";
elsif std_match(input, "--------0001") then next_state <= bit1; output <= "0---00";
elsif std_match(input, "-----0--0111") then next_state <= bit1; output <= "0--010";
elsif std_match(input, "-----1--0111") then next_state <= bit1; output <= "0--110";
elsif std_match(input, "--------0010") then next_state <= bit1; output <= "0---00";
elsif std_match(input, "--------0100") then next_state <= bit1; output <= "0---00";
end if;
when bit1 =>
if std_match(input, "--------0001") then next_state <= bit2; output <= "0---10";
elsif std_match(input, "-----0--0111") then next_state <= bit2; output <= "0--010";
elsif std_match(input, "-----1--0111") then next_state <= bit2; output <= "0--110";
elsif std_match(input, "--------0010") then next_state <= bit2; output <= "0---00";
elsif std_match(input, "--------0100") then next_state <= bit2; output <= "0---00";
end if;
when bit2 =>
if std_match(input, "--------0001") then next_state <= bit3; output <= "0---00";
elsif std_match(input, "-----0--0111") then next_state <= bit3; output <= "0--000";
elsif std_match(input, "-----1--0111") then next_state <= bit3; output <= "0--100";
elsif std_match(input, "--------0010") then next_state <= bit3; output <= "0---10";
elsif std_match(input, "--------0100") then next_state <= bit3; output <= "0---10";
end if;
when bit3 =>
if std_match(input, "0-------0001") then next_state <= bit4; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bit4; output <= "1---10";
elsif std_match(input, "-00--00-0111") then next_state <= bit4; output <= "100000";
elsif std_match(input, "-01--00-0111") then next_state <= bit4; output <= "100010";
elsif std_match(input, "-10--00-0111") then next_state <= bit4; output <= "100010";
elsif std_match(input, "-11--00-0111") then next_state <= bit4; output <= "110000";
elsif std_match(input, "-00--01-0111") then next_state <= bit4; output <= "101000";
elsif std_match(input, "-01--01-0111") then next_state <= bit4; output <= "100010";
elsif std_match(input, "-10--01-0111") then next_state <= bit4; output <= "100010";
elsif std_match(input, "-11--01-0111") then next_state <= bit4; output <= "111000";
elsif std_match(input, "-----10-0111") then next_state <= bit4; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bit4; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bit4; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bit4; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bit4; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bit4; output <= "1---10";
end if;
when bit4 =>
if std_match(input, "0-------0001") then next_state <= bit5; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bit5; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bit5; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bit5; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bit5; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bit5; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bit5; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bit5; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bit5; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bit5; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bit5; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bit5; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bit5; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bit5; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bit5; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bit5; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bit5; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bit5; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bit5; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bit5; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bit5; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bit5; output <= "1---10";
end if;
when bit5 =>
if std_match(input, "0-------0001") then next_state <= bit6; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bit6; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bit6; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bit6; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bit6; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bit6; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bit6; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bit6; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bit6; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bit6; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bit6; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bit6; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bit6; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bit6; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bit6; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bit6; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bit6; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bit6; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bit6; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bit6; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bit6; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bit6; output <= "1---10";
end if;
when bit6 =>
if std_match(input, "0-------0001") then next_state <= bit7; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bit7; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bit7; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bit7; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bit7; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bit7; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bit7; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bit7; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bit7; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bit7; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bit7; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bit7; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bit7; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bit7; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bit7; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bit7; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bit7; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bit7; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bit7; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bit7; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bit7; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bit7; output <= "1---10";
end if;
when bit7 =>
if std_match(input, "0-------0001") then next_state <= bit8; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bit8; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bit8; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bit8; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bit8; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bit8; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bit8; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bit8; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bit8; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bit8; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bit8; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bit8; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bit8; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bit8; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bit8; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bit8; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bit8; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bit8; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bit8; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bit8; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bit8; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bit8; output <= "1---10";
end if;
when bit8 =>
if std_match(input, "0-------0001") then next_state <= bit9; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bit9; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bit9; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bit9; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bit9; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bit9; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bit9; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bit9; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bit9; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bit9; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bit9; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bit9; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bit9; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bit9; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bit9; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bit9; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bit9; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bit9; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bit9; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bit9; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bit9; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bit9; output <= "1---10";
end if;
when bit9 =>
if std_match(input, "0-------0001") then next_state <= bitA; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bitA; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bitA; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bitA; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bitA; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bitA; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bitA; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bitA; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bitA; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bitA; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bitA; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bitA; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bitA; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bitA; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bitA; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bitA; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bitA; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bitA; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bitA; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bitA; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bitA; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bitA; output <= "1---10";
end if;
when bitA =>
if std_match(input, "0-------0001") then next_state <= bitB; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bitB; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bitB; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bitB; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bitB; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bitB; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bitB; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bitB; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bitB; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bitB; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bitB; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bitB; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bitB; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bitB; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bitB; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bitB; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bitB; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bitB; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bitB; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bitB; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bitB; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bitB; output <= "1---10";
end if;
when bitB =>
if std_match(input, "--------0001") then next_state <= bitC; output <= "0---00";
elsif std_match(input, "--0000--0111") then next_state <= bitC; output <= "000000";
elsif std_match(input, "--0100--0111") then next_state <= bitC; output <= "000010";
elsif std_match(input, "--1000--0111") then next_state <= bitC; output <= "000010";
elsif std_match(input, "--1100--0111") then next_state <= bitC; output <= "010000";
elsif std_match(input, "--0010--0111") then next_state <= bitC; output <= "001000";
elsif std_match(input, "--0110--0111") then next_state <= bitC; output <= "000010";
elsif std_match(input, "--1010--0111") then next_state <= bitC; output <= "000010";
elsif std_match(input, "--1110--0111") then next_state <= bitC; output <= "011000";
elsif std_match(input, "-----1--0111") then next_state <= bitC; output <= "0--100";
elsif std_match(input, "--------0010") then next_state <= bitC; output <= "0---00";
elsif std_match(input, "--------0100") then next_state <= bitC; output <= "0---00";
end if;
when bitC =>
if std_match(input, "--------0001") then next_state <= bitD; output <= "0---00";
elsif std_match(input, "--0000--0111") then next_state <= bitD; output <= "000000";
elsif std_match(input, "--0100--0111") then next_state <= bitD; output <= "000010";
elsif std_match(input, "--1000--0111") then next_state <= bitD; output <= "000010";
elsif std_match(input, "--1100--0111") then next_state <= bitD; output <= "010000";
elsif std_match(input, "--0010--0111") then next_state <= bitD; output <= "001000";
elsif std_match(input, "--0110--0111") then next_state <= bitD; output <= "000010";
elsif std_match(input, "--1010--0111") then next_state <= bitD; output <= "000010";
elsif std_match(input, "--1110--0111") then next_state <= bitD; output <= "011000";
elsif std_match(input, "-----1--0111") then next_state <= bitD; output <= "0--100";
elsif std_match(input, "--------0010") then next_state <= bitD; output <= "0---00";
elsif std_match(input, "--------0100") then next_state <= bitD; output <= "0---00";
end if;
when bitD =>
if std_match(input, "--------0001") then next_state <= bitE; output <= "0---00";
elsif std_match(input, "--0000--0111") then next_state <= bitE; output <= "000000";
elsif std_match(input, "--0100--0111") then next_state <= bitE; output <= "000010";
elsif std_match(input, "--1000--0111") then next_state <= bitE; output <= "000010";
elsif std_match(input, "--1100--0111") then next_state <= bitE; output <= "010000";
elsif std_match(input, "--0010--0111") then next_state <= bitE; output <= "001000";
elsif std_match(input, "--0110--0111") then next_state <= bitE; output <= "000010";
elsif std_match(input, "--1010--0111") then next_state <= bitE; output <= "000010";
elsif std_match(input, "--1110--0111") then next_state <= bitE; output <= "011000";
elsif std_match(input, "-----1--0111") then next_state <= bitE; output <= "0--100";
elsif std_match(input, "--------0010") then next_state <= bitE; output <= "0---00";
elsif std_match(input, "--------0100") then next_state <= bitE; output <= "0---00";
end if;
when bitE =>
if std_match(input, "--------0001") then next_state <= bitF; output <= "0---01";
elsif std_match(input, "--0000--0111") then next_state <= bitF; output <= "000001";
elsif std_match(input, "--0100--0111") then next_state <= bitF; output <= "000011";
elsif std_match(input, "--1000--0111") then next_state <= bitF; output <= "000011";
elsif std_match(input, "--1100--0111") then next_state <= bitF; output <= "010001";
elsif std_match(input, "--0010--0111") then next_state <= bitF; output <= "001100";
elsif std_match(input, "--0110--0111") then next_state <= bitF; output <= "000011";
elsif std_match(input, "--1010--0111") then next_state <= bitF; output <= "000011";
elsif std_match(input, "--1110--0111") then next_state <= bitF; output <= "011001";
elsif std_match(input, "-----1--0111") then next_state <= bitF; output <= "0--001";
elsif std_match(input, "--------0010") then next_state <= bitF; output <= "0---01";
elsif std_match(input, "--------0100") then next_state <= bitF; output <= "0---01";
end if;
when bitF =>
if std_match(input, "--------0001") then next_state <= rst0; output <= "0---00";
elsif std_match(input, "---0-0--0111") then next_state <= rst0; output <= "0--000";
elsif std_match(input, "---1-0--0111") then next_state <= rst0; output <= "0--010";
elsif std_match(input, "-----1--0111") then next_state <= rst0; output <= "0--100";
elsif std_match(input, "--------0010") then next_state <= rst0; output <= "0---00";
elsif std_match(input, "--------0100") then next_state <= rst0; output <= "0---00";
end if;
when others => next_state <= "----"; output <= "------";
end case;
end if;
end process;
end behaviour;
| agpl-3.0 | 3f9f1c122993a77653a9a7a938622abd | 0.592135 | 3.521641 | false | false | false | false |
chastell/art-decomp | kiss/cse_jed.vhd | 1 | 10,008 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity cse_jed is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(6 downto 0)
);
end cse_jed;
architecture behaviour of cse_jed is
constant st0: std_logic_vector(3 downto 0) := "0100";
constant st1: std_logic_vector(3 downto 0) := "0110";
constant st9: std_logic_vector(3 downto 0) := "1110";
constant st6: std_logic_vector(3 downto 0) := "0101";
constant st8: std_logic_vector(3 downto 0) := "0001";
constant st2: std_logic_vector(3 downto 0) := "0011";
constant st5: std_logic_vector(3 downto 0) := "1100";
constant st3: std_logic_vector(3 downto 0) := "1101";
constant st4: std_logic_vector(3 downto 0) := "1111";
constant st7: std_logic_vector(3 downto 0) := "0111";
constant st10: std_logic_vector(3 downto 0) := "1001";
constant st11: std_logic_vector(3 downto 0) := "1010";
constant st12: std_logic_vector(3 downto 0) := "1011";
constant st13: std_logic_vector(3 downto 0) := "0000";
constant st14: std_logic_vector(3 downto 0) := "1000";
constant st15: std_logic_vector(3 downto 0) := "0010";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "-------";
case current_state is
when st0 =>
if std_match(input, "1-000--") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "1-11---") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "1-1-1--") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "10010--") then next_state <= st1; output <= "1100-10";
elsif std_match(input, "10011--") then next_state <= st9; output <= "0010001";
elsif std_match(input, "10001--") then next_state <= st6; output <= "0000-01";
elsif std_match(input, "10100--") then next_state <= st8; output <= "0000--0";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000-00";
end if;
when st1 =>
if std_match(input, "101----") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "10010--") then next_state <= st1; output <= "0100-00";
elsif std_match(input, "1000---") then next_state <= st2; output <= "0000-00";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000-10";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000-10";
end if;
when st2 =>
if std_match(input, "10010--") then next_state <= st1; output <= "1100-00";
elsif std_match(input, "10011--") then next_state <= st5; output <= "0001000";
elsif std_match(input, "10000--") then next_state <= st2; output <= "0000-00";
elsif std_match(input, "10001--") then next_state <= st3; output <= "1000-00";
elsif std_match(input, "101----") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "0-----0") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "0-----1") then next_state <= st0; output <= "0000-10";
elsif std_match(input, "-1----0") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "-1----1") then next_state <= st0; output <= "0000-10";
end if;
when st3 =>
if std_match(input, "10001--") then next_state <= st3; output <= "0000-00";
elsif std_match(input, "100-0--") then next_state <= st4; output <= "0000-00";
elsif std_match(input, "101----") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000-10";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000-10";
end if;
when st4 =>
if std_match(input, "101----") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "10010--") then next_state <= st1; output <= "1100-00";
elsif std_match(input, "1000---") then next_state <= st4; output <= "0000-00";
elsif std_match(input, "10011--") then next_state <= st5; output <= "0001000";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000-00";
end if;
when st5 =>
if std_match(input, "10-1---") then next_state <= st5; output <= "0000-00";
elsif std_match(input, "10-0---") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
end if;
when st6 =>
if std_match(input, "10--1--") then next_state <= st6; output <= "0000-00";
elsif std_match(input, "101----") then next_state <= st6; output <= "0000-00";
elsif std_match(input, "100-0--") then next_state <= st7; output <= "0000-00";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000-00";
end if;
when st7 =>
if std_match(input, "100--0-") then next_state <= st7; output <= "0000-00";
elsif std_match(input, "101--0-") then next_state <= st6; output <= "0000-01";
elsif std_match(input, "10---1-") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000-00";
end if;
when st8 =>
if std_match(input, "10-00--") then next_state <= st8; output <= "0000-00";
elsif std_match(input, "10010--") then next_state <= st9; output <= "0010101";
elsif std_match(input, "10-01--") then next_state <= st10; output <= "0000-10";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "10-11--") then next_state <= st0; output <= "0000--0";
end if;
when st9 =>
if std_match(input, "10-1---") then next_state <= st9; output <= "0000000";
elsif std_match(input, "10-0---") then next_state <= st7; output <= "0000000";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
end if;
when st10 =>
if std_match(input, "10-0---") then next_state <= st10; output <= "0000-00";
elsif std_match(input, "10-10--") then next_state <= st11; output <= "0000100";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "10-11--") then next_state <= st0; output <= "0000--0";
end if;
when st11 =>
if std_match(input, "10-10--") then next_state <= st11; output <= "0000000";
elsif std_match(input, "10-0---") then next_state <= st12; output <= "0000000";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "10-11--") then next_state <= st0; output <= "0000--0";
end if;
when st12 =>
if std_match(input, "10-0---") then next_state <= st12; output <= "0000000";
elsif std_match(input, "10-10--") then next_state <= st13; output <= "1000000";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "10-11--") then next_state <= st0; output <= "0000--0";
end if;
when st13 =>
if std_match(input, "10-10--") then next_state <= st13; output <= "0000000";
elsif std_match(input, "10-01--") then next_state <= st13; output <= "0000000";
elsif std_match(input, "10100--") then next_state <= st14; output <= "0000000";
elsif std_match(input, "10000--") then next_state <= st15; output <= "0000000";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
end if;
when st14 =>
if std_match(input, "--111--") then next_state <= st14; output <= "0000000";
elsif std_match(input, "--100--") then next_state <= st14; output <= "0000000";
elsif std_match(input, "--110--") then next_state <= st13; output <= "1000000";
elsif std_match(input, "--101--") then next_state <= st13; output <= "1000000";
elsif std_match(input, "--0----") then next_state <= st0; output <= "0001000";
end if;
when st15 =>
if std_match(input, "10000--") then next_state <= st15; output <= "0000000";
elsif std_match(input, "10010--") then next_state <= st13; output <= "1000000";
elsif std_match(input, "10001--") then next_state <= st13; output <= "1000000";
elsif std_match(input, "101----") then next_state <= st8; output <= "0001000";
elsif std_match(input, "0------") then next_state <= st0; output <= "0001000";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0001000";
elsif std_match(input, "10011--") then next_state <= st0; output <= "0001000";
end if;
when others => next_state <= "----"; output <= "-------";
end case;
end process;
end behaviour;
| agpl-3.0 | c991123660718f0ac414b1be8eb40482 | 0.565248 | 3.317203 | false | false | false | false |
ibm2030/IBM2030 | ibm2030.vhd | 1 | 27,369 | ---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: ibm2030.vhd
-- Creation Date: 21:17:39 2005-04-18
-- Description:
-- Top-level System360/30, including CPU, Panel Lamps and Panel Switches
-- Does not yet include I/O
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-09
-- Initial release - no I/O
-- Revision 1.1 2012-04-07
-- 1050 Serial console added
-- External main and aux storage, with pre-loading from platform flash
--
---------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE work.Buses_package.all;
use UNISIM.vcomponents.all;
use work.all;
entity ibm2030 is
Port ( -- Physical I/O on Digilent S3 Board
-- Seven-segment displays
ssd : out std_logic_vector(7 downto 0); -- 7-segment segment cathodes - active=0, a=bit0, g=bit6, dp=bit7
ssdan : out std_logic_vector(3 downto 0); -- 7-segment digit anodes - active=0, RHS=bit0
-- Discrete LEDs
led : out std_logic_vector(7 downto 0); -- 8 LEDs
-- Pushbuttons and switches
pb : in std_logic_vector(3 downto 0); -- 4 pushbuttons
sw : in std_logic_vector(7 downto 0); -- 8 slide switches
-- Connections to scanned front panel switches
pa_io1,pa_io2,pa_io3,pa_io4 : in std_logic := '0'; -- 4 digital inputs
pa_io5,pa_io6,pa_io7,pa_io8,pa_io9,
pa_io10,pa_io11,pa_io12,pa_io13,pa_io14 : out std_logic; -- 10 digital switch scanning outputs
pa_io15,pa_io16,pa_io17,pa_io18,ma2_db0,ma2_db1,
ma2_db2,ma2_db3,ma2_db4,ma2_db5: in std_logic := '0'; -- 10 digital switch scan inputs
-- ma2_db6,ma2_db7,ma2_astb,ma2_dstb,ma2_write, ma2_wait, ma2_reset, ma2_int : in std_logic := '0'; -- 8 digital inputs (not used)
-- Keyboard connection
-- ps2_clk : inout std_logic; -- Keyboard/Mouse clock (not used)
-- ps2_data : inout std_logic; -- Keyboard/Mouse data (not used)
-- Video output
vga_r,vga_g,vga_b,vga_hs,vga_vs : out std_logic; -- VGA output RGB+Sync
-- Panel switches input
MAX7318_SCL : out std_logic;
MAX7318_SDA : inout std_logic;
-- Panel lights output
MAX7219_CLK,MAX7219_LOAD,MAX7219_DIN : out std_logic;
-- MAX6951 is charlieplexed LED mux (miniature panel)
MAX6951_CLK,MAX6951_CS0,MAX6951_CS1,MAX6951_CS2,MAX6951_CS3,MAX6951_DIN : out std_logic;
-- Static RAM interface
sramaddr : out std_logic_vector(17 downto 0);
srama : inout std_logic_vector(8 downto 0);
sramace : out std_logic;
sramwe : out std_logic;
sramoe : out std_logic;
sramaub : out std_logic;
sramalb : out std_logic;
-- Serial I/O
serialRx : in std_logic;
serialTx : out std_logic := '1';
-- 50Mhz clock
clk : in std_logic;
-- Configuration PROM interface
din : in std_logic;
reset_prom : out std_logic;
rclk : out std_logic);
end ibm2030;
architecture FMD of ibm2030 is
-- Indicator outputs from CPU
signal WX_IND : std_logic_vector(0 to 12);
signal W_IND_P : std_logic;
signal X_IND_P : std_logic;
signal IND_SALS : SALS_BUS;
signal IND_EX,IND_CY_MATCH,IND_ALLOW_WR,IND_1050_INTRV,IND_1050_REQ,IND_MPX,IND_SEL_CHNL : STD_LOGIC;
signal IND_MSDR : STD_LOGIC_VECTOR(0 to 7);
signal IND_MSDR_P : STD_LOGIC;
signal IND_OPNL_IN : STD_LOGIC;
signal IND_ADDR_IN : STD_LOGIC;
signal IND_STATUS_IN : STD_LOGIC;
signal IND_SERV_IN : STD_LOGIC;
signal IND_SEL_OUT : STD_LOGIC;
signal IND_ADDR_OUT : STD_LOGIC;
signal IND_CMMD_OUT : STD_LOGIC;
signal IND_SERV_OUT : STD_LOGIC;
signal IND_SUPPR_OUT : STD_LOGIC;
signal IND_FO : STD_LOGIC_VECTOR(0 to 7);
signal IND_FO_P: STD_LOGIC;
signal IND_A : STD_LOGIC_VECTOR(0 to 8);
signal IND_B : STD_LOGIC_VECTOR(0 to 8);
signal IND_ALU : STD_LOGIC_VECTOR(0 to 8);
signal IND_M : STD_LOGIC_VECTOR(0 to 8);
signal IND_N : STD_LOGIC_VECTOR(0 to 8);
signal IND_MAIN_STG : STD_LOGIC;
signal IND_LOC_STG : STD_LOGIC;
signal IND_COMP_MODE : STD_LOGIC;
signal IND_CHK_A_REG : STD_LOGIC;
signal IND_CHK_B_REG : STD_LOGIC;
signal IND_CHK_STOR_ADDR : STD_LOGIC;
signal IND_CHK_CTRL_REG : STD_LOGIC;
signal IND_CHK_ROS_SALS : STD_LOGIC;
signal IND_CHK_ROS_ADDR : STD_LOGIC;
signal IND_CHK_STOR_DATA : STD_LOGIC;
signal IND_CHK_ALU : STD_LOGIC;
signal IND_SYST : STD_LOGIC;
signal IND_MAN : STD_LOGIC;
signal IND_WAIT : STD_LOGIC;
signal IND_TEST : STD_LOGIC;
signal IND_LOAD : STD_LOGIC;
signal IND_LP : STD_LOGIC;
-- SX
signal IND_COUNT : STD_LOGIC_VECTOR(0 to 15) := "0000000000000000";
signal IND_COUNT_LP, IND_COUNT_HP : STD_LOGIC := '1';
signal IND_SX1_DATA : STD_LOGIC_VECTOR(0 to 7) := "00000000";
signal IND_SX1_DATAP : STD_LOGIC := '1';
signal IND_SX1_COMMAND: STD_LOGIC_VECTOR(0 to 7) := "00000000";
signal IND_SX1_KEY: STD_LOGIC_VECTOR(0 to 3) := "0000";
signal IND_SX1_KEYP : STD_LOGIC := '1';
signal IND_SX1_PCI, IND_SX1_SKIP, IND_SX1_SLI, IND_SX1_CD, IND_SX1_CC : STD_LOGIC;
signal IND_SX1_DA_CHK, IND_SX1_PROT_CHK, IND_SX1_PROG_CHK, IND_SX1_IL_CHK, IND_SX1_CHNLDATA_CHK, IND_SX1_IF_CHK, IND_SX1_CHNLCTRL_CHK : STD_LOGIC;
signal IND_SX1_STATIN_TAG, IND_SX1_ADRIN_TAG, IND_SX1_OPIN_TAG, IND_SX1_SUPOUT_TAG, IND_SX1_SERVOUT_TAG, IND_SX1_CMMDOUT_TAG, IND_SX1_ADROUT_TAG, IND_SX1_SELOUT_TAG : STD_LOGIC;
-- Switch inputs to CPU
signal SW_START,SW_LOAD,SW_SET_IC,SW_STOP,SW_POWER_OFF : STD_LOGIC;
signal SW_INH_CF_STOP,SW_PROC,SW_SCAN : STD_LOGIC;
signal SW_SINGLE_CYCLE,SW_INSTRUCTION_STEP,SW_RATE_SW_PROCESS : STD_LOGIC;
signal SW_LAMP_TEST,SW_DSPLY,SW_STORE,SW_SYS_RST : STD_LOGIC;
signal SW_CHK_RST,SW_ROAR_RST,SW_CHK_RESTART,SW_DIAGNOSTIC : STD_LOGIC;
signal SW_CHK_STOP,SW_CHK_SW_PROCESS,SW_CHK_SW_DISABLE,SW_ROAR_RESTT_STOR_BYPASS : STD_LOGIC;
signal SW_ROAR_RESTT,SW_ROAR_RESTT_WITHOUT_RST,SW_EARLY_ROAR_STOP,SW_ROAR_STOP : STD_LOGIC;
signal SW_ROAR_SYNC,SW_ADDR_COMP_PROC,SW_SAR_DLYD_STOP,SW_SAR_STOP,SW_SAR_RESTART : STD_LOGIC;
signal SW_INTRP_TIMER, SW_CONS_INTRP : STD_LOGIC;
signal SW_A,SW_B,SW_C,SW_D,SW_F,SW_G,SW_H,SW_J : STD_LOGIC_VECTOR(0 to 3);
signal SW_AP,SW_BP,SW_CP,SW_DP,SW_FP,SW_GP,SW_HP,SW_JP : STD_LOGIC;
signal E_SW : E_SW_BUS_Type;
-- Misc stuff
signal StorageIn : STORAGE_IN_INTERFACE; -- CPU interface to storage
signal StorageOut : STORAGE_OUT_INTERFACE; -- CPU interface to storage
signal SerialIn : PCH_CONN;
signal SerialOut : RDR_CONN;
signal SerialControl : CONN_1050;
signal SerialBusUngated : STD_LOGIC_VECTOR(7 downto 0);
signal RxDataAvailable : STD_LOGIC;
signal RxAck, PunchGate : STD_LOGIC;
signal SO : Serial_Output_Lines;
signal SwSlow : STD_LOGIC := '0'; -- Set to '1' to slow clock down to 1Hz, not used
signal N60_CY_TIMER_PULSE : STD_LOGIC; -- Used for the Interval Timer
signal Clock1ms : STD_LOGIC; -- 1kHz clock for single-shots etc.
signal DEBUG : DEBUG_BUS; -- Passed to all modeles to probe signals
signal LED_vector : std_logic_vector(0 to 255);
signal Switch_vector : std_logic_vector(0 to 63);
begin
cpu : entity work.cpu port map (
WX_IND => WX_IND,
W_IND_P => W_IND_P,
X_IND_P => X_IND_P,
IND_SALS => IND_SALS,
IND_EX => IND_EX,
IND_CY_MATCH => IND_CY_MATCH,
IND_ALLOW_WR => IND_ALLOW_WR,
IND_1050_INTRV => IND_1050_INTRV,
IND_1050_REQ => IND_1050_REQ,
IND_MPX => IND_MPX,
IND_SEL_CHNL => IND_SEL_CHNL,
IND_MSDR => IND_MSDR,
IND_MSDR_P => IND_MSDR_P,
IND_OPNL_IN => IND_OPNL_IN,
IND_ADDR_IN => IND_ADDR_IN,
IND_STATUS_IN => IND_STATUS_IN,
IND_SERV_IN => IND_SERV_IN,
IND_SEL_OUT => IND_SEL_OUT,
IND_ADDR_OUT => IND_ADDR_OUT,
IND_CMMD_OUT => IND_CMMD_OUT,
IND_SERV_OUT => IND_SERV_OUT,
IND_SUPPR_OUT => IND_SUPPR_OUT,
IND_FO => IND_FO,
IND_FO_P => IND_FO_P,
IND_A => IND_A,
IND_B => IND_B,
IND_ALU => IND_ALU,
IND_M => IND_M,
IND_N => IND_N,
IND_MAIN_STG => IND_MAIN_STG,
IND_LOC_STG => IND_LOC_STG,
IND_COMP_MODE => IND_COMP_MODE,
IND_CHK_A_REG => IND_CHK_A_REG,
IND_CHK_B_REG => IND_CHK_B_REG,
IND_CHK_STOR_ADDR => IND_CHK_STOR_ADDR,
IND_CHK_CTRL_REG => IND_CHK_CTRL_REG,
IND_CHK_ROS_SALS => IND_CHK_ROS_SALS,
IND_CHK_ROS_ADDR => IND_CHK_ROS_ADDR,
IND_CHK_STOR_DATA => IND_CHK_STOR_DATA,
IND_CHK_ALU => IND_CHK_ALU,
IND_LOAD => IND_LOAD,
IND_WAIT => IND_WAIT,
IND_TEST => IND_TEST,
IND_MAN => IND_MAN,
IND_SYST => IND_SYST,
SW_START => SW_START,
SW_LOAD => SW_LOAD,
SW_SET_IC => SW_SET_IC,
SW_STOP => SW_STOP,
SW_POWER_OFF => SW_POWER_OFF,
SW_INH_CF_STOP => SW_INH_CF_STOP,
SW_PROC => SW_PROC,
SW_SCAN => SW_SCAN,
SW_SINGLE_CYCLE => SW_SINGLE_CYCLE,
SW_INSTRUCTION_STEP => SW_INSTRUCTION_STEP,
SW_RATE_SW_PROCESS => SW_RATE_SW_PROCESS,
SW_LAMP_TEST => SW_LAMP_TEST,
SW_DSPLY => SW_DSPLY,
SW_STORE => SW_STORE,
SW_SYS_RST => SW_SYS_RST,
SW_CHK_RST => SW_CHK_RST,
SW_ROAR_RST => SW_ROAR_RST,
SW_CHK_RESTART => SW_CHK_RESTART,
SW_DIAGNOSTIC => SW_DIAGNOSTIC,
SW_CHK_STOP => SW_CHK_STOP,
SW_CHK_SW_PROCESS => SW_CHK_SW_PROCESS,
SW_CHK_SW_DISABLE => SW_CHK_SW_DISABLE,
SW_ROAR_RESTT_STOR_BYPASS => SW_ROAR_RESTT_STOR_BYPASS,
SW_ROAR_RESTT => SW_ROAR_RESTT,
SW_ROAR_RESTT_WITHOUT_RST => SW_ROAR_RESTT_WITHOUT_RST,
SW_EARLY_ROAR_STOP => SW_EARLY_ROAR_STOP,
SW_ROAR_STOP => SW_ROAR_STOP,
SW_ROAR_SYNC => SW_ROAR_SYNC,
SW_ADDR_COMP_PROC => SW_ADDR_COMP_PROC,
SW_SAR_DLYD_STOP => SW_SAR_DLYD_STOP,
SW_SAR_STOP => SW_SAR_STOP,
SW_SAR_RESTART => SW_SAR_RESTART,
SW_INTRP_TIMER => SW_INTRP_TIMER,
SW_CONS_INTRP => SW_CONS_INTRP,
SW_A => SW_A,
SW_B => SW_B,
SW_C => SW_C,
SW_D => SW_D,
SW_F => SW_F,
SW_G => SW_G,
SW_H => SW_H,
SW_J => SW_J,
SW_AP => SW_AP,
SW_BP => SW_BP,
SW_CP => SW_CP,
SW_DP => SW_DP,
SW_FP => SW_FP,
SW_GP => SW_GP,
SW_HP => SW_HP,
SW_JP => SW_JP,
E_SW => E_SW,
-- Storage interface
StorageIn => StorageIn,
StorageOut => StorageOut,
-- Serial interface for 1050
serialInput.SerialRx => SerialRx,
serialInput.DCD => '1',
serialInput.DSR => '1',
serialInput.RI => '0',
serialInput.CTS => '1',
serialOutput => SO,
-- Multiplexor interface not connected to anything yet
MPX_BUS_O => open,
MPX_BUS_I => (others=>'0'),
MPX_TAGS_O => open,
MPX_TAGS_I => (others=>'0'),
DEBUG => DEBUG, -- Used to pass debug signals up to the top level for output
N60_CY_TIMER_PULSE => N60_CY_TIMER_PULSE, -- Actually 50Hz
Clock1ms => Clock1ms,
SwSlow => SwSlow,
clk => clk -- 50Mhz clock
);
frontPanel : entity vga_panel port map (
Clock50 => clk,
Red => vga_r, Green => vga_g, Blue => vga_b,
HS => vga_hs, VS => vga_vs,
Indicators( 0) => '0', -- Constant
Indicators( 1) => IND_SALS.SALS_PN,
Indicators( 2 to 7) => IND_SALS.SALS_CN,
Indicators( 8) => IND_SALS.SALS_PA,
Indicators( 9) => IND_LP,
Indicators( 10) => W_IND_P,
Indicators( 11 to 15) => WX_IND(0 to 4),
Indicators( 16) => X_IND_P,
Indicators( 17 to 24) => WX_IND(5 to 12),
Indicators( 25) => IND_SALS.SALS_PS,
Indicators( 26 to 29) => IND_SALS.SALS_CH,
Indicators( 30 to 33) => IND_SALS.SALS_CL,
Indicators( 34) => IND_SALS.SALS_AA,
Indicators( 35 to 38) => IND_SALS.SALS_CA,
Indicators( 39 to 40) => IND_SALS.SALS_CB,
Indicators( 41 to 43) => IND_SALS.SALS_CM,
Indicators( 44 to 45) => IND_SALS.SALS_CU,
Indicators( 46) => IND_SALS.SALS_AK,
Indicators( 47) => IND_SALS.SALS_PK,
Indicators( 48 to 51) => IND_SALS.SALS_CK,
Indicators( 52) => IND_SALS.SALS_PC,
Indicators( 53 to 56) => IND_SALS.SALS_CD,
Indicators( 57 to 59) => IND_SALS.SALS_CF,
Indicators( 60 to 61) => IND_SALS.SALS_CG,
Indicators( 62 to 63) => IND_SALS.SALS_CV,
Indicators( 64 to 66) => IND_SALS.SALS_CC,
Indicators( 67) => IND_SALS.SALS_SA,
Indicators( 68 to 71) => IND_SALS.SALS_CS,
-- Skip 18 + 9 + 9 + 5 + 9 + 6 = 56 for SX1 (72 to 127)
Indicators( 72 to 127) => "00000000000000000000000000000000000000000000000000000000",
-- If we had SX2 there would be another 56 here
-- MPX
Indicators( 128) => IND_OPNL_IN,
Indicators( 129) => IND_ADDR_IN,
Indicators( 130) => IND_STATUS_IN,
Indicators( 131) => IND_SERV_IN,
Indicators( 132) => IND_SEL_OUT,
Indicators( 133) => IND_ADDR_OUT,
Indicators( 134) => IND_CMMD_OUT,
Indicators( 135) => IND_SERV_OUT,
Indicators( 136) => IND_SUPPR_OUT,
Indicators( 137) => IND_FO_P,
Indicators(138 to 145) => IND_FO,
-- MSAR
Indicators( 146) => IND_MAIN_STG,
Indicators( 147) => IND_M(8),
Indicators(148 to 155) => IND_M(0 to 7),
Indicators( 156) => IND_N(8),
Indicators(157 to 164) => IND_N(0 to 7),
Indicators( 165) => IND_LOC_STG,
-- MSDR
Indicators( 166) => IND_MSDR_P,
Indicators(167 to 174) => IND_MSDR,
-- ALU
Indicators( 175) => IND_ALU(8),
Indicators(176 to 183) => IND_ALU(0 to 7),
Indicators( 184) => IND_EX,
Indicators( 185) => IND_CY_MATCH,
Indicators( 186) => IND_ALLOW_WR,
Indicators( 187) => IND_CHK_STOR_ADDR,
Indicators( 188) => IND_CHK_STOR_DATA,
Indicators( 189) => IND_1050_INTRV,
Indicators( 190) => IND_1050_REQ,
Indicators( 191) => IND_CHK_B_REG,
Indicators( 192) => IND_CHK_A_REG,
Indicators( 193) => IND_CHK_ALU,
-- A,B
Indicators( 194) => IND_A(8),
Indicators(195 to 202) => IND_A(0 to 7),
Indicators( 203) => IND_B(8),
Indicators(204 to 211) => IND_B(0 to 7),
Indicators( 212) => IND_MPX,
Indicators( 213) => IND_SEL_CHNL,
Indicators( 214) => IND_COMP_MODE,
Indicators( 215) => IND_CHK_ROS_ADDR,
Indicators( 216) => IND_CHK_ROS_SALS,
Indicators( 217) => IND_CHK_CTRL_REG,
-- The following indicators mimic the 8 Hex rotary switches to make it easier to set them
Indicators(218 to 221) => SW_A(0 to 3),
Indicators(222 to 225) => SW_B(0 to 3),
Indicators(226 to 229) => SW_C(0 to 3),
Indicators(230 to 233) => SW_D(0 to 3),
Indicators(234 to 237) => SW_F(0 to 3),
Indicators(238 to 241) => SW_G(0 to 3),
Indicators(242 to 245) => SW_H(0 to 3),
Indicators(246 to 249) => SW_J(0 to 3)
);
-- LEDs are set here
led(0) <= IND_LOAD;
led(1) <= IND_TEST;
led(2) <= IND_WAIT;
led(3) <= IND_MAN;
led(4) <= IND_SYST;
led(5) <= '0';
led(6) <= '0';
led(7) <= DEBUG.Probe;
IND_LP <= SW_LAMP_TEST;
-- Temporary Selector Channel indicators
IND_COUNT_LP <= '1';
IND_COUNT_HP <= '1';
IND_COUNT <= (others => SW_LAMP_TEST);
IND_SX1_DATA <= (others => SW_LAMP_TEST);
IND_SX1_DATAP <= SW_LAMP_TEST;
IND_SX1_COMMAND <= (others => SW_LAMP_TEST);
IND_SX1_KEY <= (others => SW_LAMP_TEST);
IND_SX1_KEYP <= SW_LAMP_TEST;
IND_SX1_PCI <= SW_LAMP_TEST;
IND_SX1_SKIP <= SW_LAMP_TEST;
IND_SX1_SLI <= SW_LAMP_TEST;
IND_SX1_CD <= SW_LAMP_TEST;
IND_SX1_CC <= SW_LAMP_TEST;
IND_SX1_DA_CHK <= SW_LAMP_TEST;
IND_SX1_PROT_CHK <= SW_LAMP_TEST;
IND_SX1_PROG_CHK <= SW_LAMP_TEST;
IND_SX1_IL_CHK <= SW_LAMP_TEST;
IND_SX1_CHNLDATA_CHK <= SW_LAMP_TEST;
IND_SX1_STATIN_TAG <= SW_LAMP_TEST;
IND_SX1_ADRIN_TAG <= SW_LAMP_TEST;
IND_SX1_OPIN_TAG <= SW_LAMP_TEST;
IND_SX1_SUPOUT_TAG <= SW_LAMP_TEST;
IND_SX1_SERVOUT_TAG <= SW_LAMP_TEST;
IND_SX1_CMMDOUT_TAG <= SW_LAMP_TEST;
IND_SX1_ADROUT_TAG <= SW_LAMP_TEST;
IND_SX1_SELOUT_TAG <= SW_LAMP_TEST;
IND_SX1_IF_CHK <= SW_LAMP_TEST;
IND_SX1_CHNLCTRL_CHK <= SW_LAMP_TEST;
frontPanel_switches: entity switches port map (
-- Hardware switch inputs and scan outputs
SwA_scan => pa_io5,
SwB_scan => pa_io6,
SwC_scan => pa_io7,
SwD_scan => pa_io8,
SwE_scan => pa_io9,
SwF_scan => pa_io10,
SwG_scan => pa_io11,
SwH_scan => pa_io12,
SwJ_scan => pa_io13,
SwAC_scan => pa_io14,
Hex_in(0) => pa_io1,
Hex_in(1) => pa_io2,
Hex_in(2) => pa_io3,
Hex_in(3) => pa_io4,
SW_E_INNER => pa_io15,
SW_E_OUTER => pa_io16,
RawSw_Proc_Inh_CF_Stop => pa_io17,
RawSw_Proc_Scan => pa_io18,
RawSw_Rate_Single_Cycle => ma2_db1,
RawSw_Rate_Instruction_Step => ma2_db0,
RawSw_Chk_Chk_Restart => ma2_db5,
RawSw_Chk_Diagnostic => ma2_db2,
RawSw_Chk_Stop => ma2_db4,
RawSw_Chk_Disable => ma2_db3,
sw => sw,
pb => pb,
-- Switches fed to CPU
SwA => SW_A, SwAP => SW_AP,
SwB => SW_B, SwBP => SW_BP,
SwC => SW_C, SwCP => SW_CP,
SwD => SW_D, SwDP => SW_DP,
SwE => E_SW,
SwF => SW_F, SwFP => SW_FP,
SwG => SW_G, SwGP => SW_GP,
SwH => SW_H, SwHP => SW_HP,
SwJ => SW_J, SwJP => SW_JP,
Sw_PowerOff => SW_POWER_OFF,
Sw_Interrupt => SW_CONS_INTRP,
Sw_Load => SW_LOAD,
Sw_SystemReset => SW_SYS_RST,
Sw_RoarReset => SW_ROAR_RST,
Sw_Start => SW_START,
Sw_SetIC => SW_SET_IC,
Sw_CheckReset => SW_CHK_RST,
Sw_Stop => SW_STOP,
Sw_IntTmr => SW_INTRP_TIMER,
Sw_Store => SW_STORE,
Sw_LampTest => SW_LAMP_TEST,
Sw_Display => SW_DSPLY,
Sw_Proc_Inh_CF_Stop => SW_INH_CF_STOP,
Sw_Proc_Proc => SW_PROC,
Sw_Proc_Scan => SW_SCAN,
Sw_Rate_Single_Cycle => SW_SINGLE_CYCLE,
Sw_Rate_Instruction_Step => SW_INSTRUCTION_STEP,
Sw_Rate_Process => SW_RATE_SW_PROCESS,
Sw_Chk_Chk_Restart => SW_CHK_RESTART,
Sw_Chk_Diagnostic => SW_DIAGNOSTIC,
Sw_Chk_Stop => SW_CHK_STOP,
Sw_Chk_Process => SW_CHK_SW_PROCESS,
Sw_Chk_Disable => SW_CHK_SW_DISABLE,
Sw_ROAR_RESTT_STOR_BYPASS => SW_ROAR_RESTT_STOR_BYPASS,
Sw_ROAR_RESTT => SW_ROAR_RESTT,
Sw_ROAR_RESTT_WITHOUT_RST => SW_ROAR_RESTT_WITHOUT_RST,
Sw_EARLY_ROAR_STOP => SW_EARLY_ROAR_STOP,
Sw_ROAR_STOP => SW_ROAR_STOP,
Sw_ROAR_SYNC => SW_ROAR_SYNC,
Sw_ADDR_COMP_PROC => SW_ADDR_COMP_PROC,
Sw_SAR_DLYD_STOP => SW_SAR_DLYD_STOP,
Sw_SAR_STOP => SW_SAR_STOP,
Sw_SAR_RESTART => SW_SAR_RESTART,
-- MAX7318
SCL => MAX7318_SCL,
SDA => MAX7318_SDA,
-- Clocks etc.
clk => clk, -- 50MHz clock
status_lamps(4) => IND_LOAD,
status_lamps(3) => IND_TEST,
status_lamps(2) => IND_WAIT,
status_lamps(1) => IND_MAN,
status_lamps(0) => IND_SYST,
-- Clock1ms => Clock1ms,
Timer => N60_CY_TIMER_PULSE -- Output from Switches is actually 50Hz
);
core_storage : entity storage port map(
phys_address => sramaddr(16 downto 0),
phys_data => srama(8 downto 0),
phys_CE => sramace,
phys_OE => sramoe,
phys_WE => sramwe,
phys_UB => sramaub,
phys_LB => sramalb,
-- Interface to config ROM
din => din,
reset_prom => reset_prom,
cclk => rclk,
-- Storage interface to CPU
StorageIn => StorageIn,
StorageOut => StorageOut,
-- Debug => Debug,
-- Other inputs
clk => clk
);
sramaddr(17) <= '0';
LED_vector <= (
0 => IND_SALS.SALS_PA,
1 => IND_SALS.SALS_CN(5),
2 => IND_SALS.SALS_CN(4),
3 => IND_SALS.SALS_CN(3),
4 => IND_SALS.SALS_CN(2),
5 => IND_SALS.SALS_CN(1),
6 => IND_SALS.SALS_CN(0),
7 => IND_SALS.SALS_PN,
8 => X_IND_P,
9 => WX_IND(4),
10 => WX_IND(3),
11 => WX_IND(2),
12 => WX_IND(1),
13 => WX_IND(0),
14 => W_IND_P,
15 => IND_LP,
16 => WX_IND(12),
17 => WX_IND(11),
18 => WX_IND(10),
19 => WX_IND(9),
20 => WX_IND(8),
21 => WX_IND(7),
22 => WX_IND(6),
23 => WX_IND(5),
24 => IND_SALS.SALS_CL(2),
25 => IND_SALS.SALS_CL(1),
26 => IND_SALS.SALS_CL(0),
27 => IND_SALS.SALS_CH(3),
28 => IND_SALS.SALS_CH(2),
29 => IND_SALS.SALS_CH(1),
30 => IND_SALS.SALS_CH(0),
31 => IND_SALS.SALS_PS,
32 => IND_SALS.SALS_CB(1),
33 => IND_SALS.SALS_CB(0),
34 => IND_SALS.SALS_CA(3),
35 => IND_SALS.SALS_CA(2),
36 => IND_SALS.SALS_CA(1),
37 => IND_SALS.SALS_CA(0),
38 => IND_SALS.SALS_AA,
39 => IND_SALS.SALS_CL(3),
40 => IND_SALS.SALS_CK(0),
41 => IND_SALS.SALS_PK,
42 => IND_SALS.SALS_AK,
43 => IND_SALS.SALS_CU(1),
44 => IND_SALS.SALS_CU(0),
45 => IND_SALS.SALS_CM(2),
46 => IND_SALS.SALS_CM(1),
47 => IND_SALS.SALS_CM(0),
48 => IND_SALS.SALS_CD(3),
49 => IND_SALS.SALS_CD(2),
50 => IND_SALS.SALS_CD(1),
51 => IND_SALS.SALS_CD(0),
52 => IND_SALS.SALS_PC,
53 => IND_SALS.SALS_CK(3),
54 => IND_SALS.SALS_CK(2),
55 => IND_SALS.SALS_CK(1),
56 => IND_SALS.SALS_CC(0),
57 => IND_SALS.SALS_CV(1),
58 => IND_SALS.SALS_CV(0),
59 => IND_SALS.SALS_CG(1),
60 => IND_SALS.SALS_CG(0),
61 => IND_SALS.SALS_CF(2),
62 => IND_SALS.SALS_CF(1),
63 => IND_SALS.SALS_CF(0),
64 => IND_COUNT_HP, -- Count-P
65 => IND_SALS.SALS_CS(3),
66 => IND_SALS.SALS_CS(2),
67 => IND_SALS.SALS_CS(1),
68 => IND_SALS.SALS_CS(0),
69 => IND_SALS.SALS_SA,
70 => IND_SALS.SALS_CC(2),
71 => IND_SALS.SALS_CC(1),
-- Count 72-87,95
72 => IND_COUNT(8),
73 => IND_COUNT(6),
74 => IND_COUNT(5),
75 => IND_COUNT(4),
76 => IND_COUNT(3),
77 => IND_COUNT(2),
78 => IND_COUNT(1),
79 => IND_COUNT(0),
80 => IND_COUNT(15),
81 => IND_COUNT(14),
82 => IND_COUNT(13),
83 => IND_COUNT(12),
84 => IND_COUNT(11),
85 => IND_COUNT(10),
86 => IND_COUNT(9),
87 => IND_COUNT_LP,
95 => IND_COUNT(0),
-- SX1
88 => IND_SX1_DATA(5),
89 => IND_SX1_DATA(4),
90 => IND_SX1_DATA(3),
91 => IND_SX1_DATA(2),
92 => IND_SX1_DATA(1),
93 => IND_SX1_DATA(0),
94 => IND_SX1_DATAP,
96 => IND_SX1_COMMAND(4),
97 => IND_SX1_KEY(3),
98 => IND_SX1_KEY(2),
99 => IND_SX1_KEY(1),
100 => IND_SX1_KEY(0),
101 => IND_SX1_KEYP,
102 => IND_SX1_DATA(7),
103 => IND_SX1_DATA(6),
104 => IND_SX1_PCI,
105 => IND_SX1_SKIP,
106 => IND_SX1_SLI,
107 => IND_SX1_CD,
108 => IND_SX1_CC,
109 => IND_SX1_COMMAND(7),
110 => IND_SX1_COMMAND(6),
111 => IND_SX1_COMMAND(5),
112 => IND_SX1_DA_CHK,
113 => IND_SX1_PROT_CHK,
114 => IND_SX1_PROG_CHK,
115 => IND_SX1_IL_CHK,
116 => IND_SX1_CHNLDATA_CHK,
117 => IND_SX1_STATIN_TAG,
118 => IND_SX1_ADRIN_TAG,
119 => IND_SX1_OPIN_TAG,
120 => '0', -- LED5
121 => IND_SX1_SUPOUT_TAG,
122 => IND_SX1_SERVOUT_TAG,
123 => IND_SX1_CMMDOUT_TAG,
124 => IND_SX1_ADROUT_TAG,
125 => IND_SX1_SELOUT_TAG,
126 => IND_SX1_IF_CHK,
127 => IND_SX1_CHNLCTRL_CHK,
-- SX2 128-150. 162-167
-- Temporary indicators 152-159
152 => IND_LOAD,
153 => IND_TEST,
154 => IND_WAIT,
155 => IND_MAN,
156 => IND_SYST,
157 => '1', -- Power
158 => '1',
159 => '1',
160 => IND_ADDR_IN,
161 => IND_OPNL_IN,
-- 162-167 in SX2
168 => IND_FO_P,
169 => IND_SUPPR_OUT,
170 => IND_SERV_OUT,
171 => IND_CMMD_OUT,
172 => IND_ADDR_OUT,
173 => IND_SEL_OUT,
174 => IND_SERV_IN,
175 => IND_STATUS_IN,
176 => IND_FO(7),
177 => IND_FO(6),
178 => IND_FO(5),
179 => IND_FO(4),
180 => IND_FO(3),
181 => IND_FO(2),
182 => IND_FO(1),
183 => IND_FO(0),
184 => IND_M(6),
185 => IND_M(5),
186 => IND_M(4),
187 => IND_M(3),
188 => IND_M(2),
189 => IND_M(1),
190 => IND_M(0),
191 => IND_M(8),
192 => IND_N(5),
193 => IND_N(4),
194 => IND_N(3),
195 => IND_N(2),
196 => IND_N(1),
197 => IND_N(0),
198 => IND_N(8),
199 => IND_M(7),
200 => IND_MSDR(2),
201 => IND_MSDR(1),
202 => IND_MSDR(0),
203 => IND_MSDR_P,
204 => IND_LOC_STG,
205 => IND_MAIN_STG,
206 => IND_N(7),
207 => IND_N(6),
208 => IND_ALU(1),
209 => IND_ALU(0),
210 => IND_ALU(8),
211 => IND_MSDR(7),
212 => IND_MSDR(6),
213 => IND_MSDR(5),
214 => IND_MSDR(4),
215 => IND_MSDR(3),
216 => IND_B(0),
217 => IND_B(8),
218 => IND_ALU(7),
219 => IND_ALU(6),
220 => IND_ALU(5),
221 => IND_ALU(4),
222 => IND_ALU(3),
223 => IND_ALU(2),
224 => IND_A(8),
225 => IND_B(7),
226 => IND_B(6),
227 => IND_B(5),
228 => IND_B(4),
229 => IND_B(3),
230 => IND_B(2),
231 => IND_B(1),
232 => IND_A(7),
233 => IND_A(6),
234 => IND_A(5),
235 => IND_A(4),
236 => IND_A(3),
237 => IND_A(2),
238 => IND_A(1),
239 => IND_A(0),
240 => IND_CHK_B_REG,
241 => IND_1050_REQ,
242 => IND_1050_INTRV,
243 => IND_CHK_STOR_DATA,
244 => IND_CHK_STOR_ADDR,
245 => IND_ALLOW_WR,
246 => IND_CY_MATCH,
247 => IND_EX,
248 => IND_CHK_CTRL_REG,
249 => IND_CHK_ROS_SALS,
250 => IND_CHK_ROS_ADDR,
251 => IND_COMP_MODE,
252 => IND_SEL_CHNL,
253 => IND_MPX,
254 => IND_CHK_ALU,
255 => IND_CHK_A_REG,
others => '0');
front_panel_LEDs : entity panel_LEDs
generic map(
clock_divider => 2,
number_LEDs => 256
)
port map(
clk => clk,
LEDs => LED_vector,
-- MAX7219 is standard LED mux (full-size panel)
MAX7219_CLK => MAX7219_CLK,
MAX7219_LOAD => MAX7219_LOAD,
MAX7219_DIN => MAX7219_DIN,
-- MAX6951 is charlieplexed LED mux (miniature panel)
MAX6951_CLK => MAX6951_CLK,
MAX6951_CS0 => MAX6951_CS0,
MAX6951_CS1 => MAX6951_CS1,
MAX6951_CS2 => MAX6951_CS2,
MAX6951_CS3 => MAX6951_CS3,
MAX6951_DIN => MAX6951_DIN
);
number_LEDs : entity segment_LEDs
port map(
clk => clk,
number(15 downto 13) => "000",
number(12 downto 0) => WX_IND(0 to 12),
anodes => ssdan,
cathodes => ssd
);
DEBUG.Selection <= CONV_INTEGER(unsigned(SW_J));
SerialTx <= SO.SerialTx;
-- with DEBUG.Selection select
-- DEBUG.Probe <=
-- SerialBusUngated(0) when 0, SerialBusUngated(1) when 1, SerialBusUngated(2) when 2, SerialBusUngated(3) when 3,
-- SerialBusUngated(4) when 4, SerialBusUngated(5) when 5, SerialBusUngated(6) when 6, SerialBusUngated(7) when 7,
-- RxDataAvailable when others;
end FMD;
| gpl-3.0 | f298f04e86ffee5db84dca910caedea0 | 0.586028 | 2.562161 | false | false | false | false |
chastell/art-decomp | kiss/tma_rnd.vhd | 1 | 6,129 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity tma_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(5 downto 0)
);
end tma_rnd;
architecture behaviour of tma_rnd is
constant I0: std_logic_vector(4 downto 0) := "11101";
constant T1: std_logic_vector(4 downto 0) := "00010";
constant R1: std_logic_vector(4 downto 0) := "11011";
constant T3: std_logic_vector(4 downto 0) := "11110";
constant T9: std_logic_vector(4 downto 0) := "11111";
constant T4: std_logic_vector(4 downto 0) := "10001";
constant T5: std_logic_vector(4 downto 0) := "10110";
constant T6: std_logic_vector(4 downto 0) := "01011";
constant T7: std_logic_vector(4 downto 0) := "01111";
constant T8: std_logic_vector(4 downto 0) := "00001";
constant I2: std_logic_vector(4 downto 0) := "10000";
constant T2: std_logic_vector(4 downto 0) := "11010";
constant R2: std_logic_vector(4 downto 0) := "11000";
constant I1: std_logic_vector(4 downto 0) := "01000";
constant R3: std_logic_vector(4 downto 0) := "00100";
constant R4: std_logic_vector(4 downto 0) := "01001";
constant R6: std_logic_vector(4 downto 0) := "00110";
constant R8: std_logic_vector(4 downto 0) := "11100";
constant R5: std_logic_vector(4 downto 0) := "00011";
constant R7: std_logic_vector(4 downto 0) := "10111";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "------";
case current_state is
when I0 =>
if std_match(input, "11110--") then next_state <= T1; output <= "000000";
elsif std_match(input, "101-1--") then next_state <= R1; output <= "000000";
end if;
when T1 =>
if std_match(input, "1110---") then next_state <= T3; output <= "100000";
elsif std_match(input, "100----") then next_state <= T9; output <= "100000";
elsif std_match(input, "101--1-") then next_state <= T9; output <= "100000";
end if;
when T3 =>
if std_match(input, "111----") then next_state <= T4; output <= "110000";
elsif std_match(input, "100----") then next_state <= T9; output <= "110000";
elsif std_match(input, "101--1-") then next_state <= T9; output <= "110000";
end if;
when T4 =>
if std_match(input, "111----") then next_state <= T5; output <= "001000";
elsif std_match(input, "100----") then next_state <= T9; output <= "001000";
elsif std_match(input, "101--1-") then next_state <= T9; output <= "001000";
end if;
when T5 =>
if std_match(input, "111-0--") then next_state <= T6; output <= "101000";
elsif std_match(input, "100----") then next_state <= T9; output <= "101000";
elsif std_match(input, "101-1--") then next_state <= T9; output <= "101000";
end if;
when T6 =>
if std_match(input, "101-0--") then next_state <= T7; output <= "011000";
elsif std_match(input, "101-1--") then next_state <= T8; output <= "011000";
elsif std_match(input, "100----") then next_state <= T9; output <= "011000";
end if;
when T7 =>
if std_match(input, "10-----") then next_state <= I2; output <= "111000";
end if;
when T8 =>
if std_match(input, "10-----") then next_state <= I2; output <= "000100";
end if;
when T9 =>
if std_match(input, "101-0--") then next_state <= T2; output <= "100100";
elsif std_match(input, "100----") then next_state <= T2; output <= "100100";
end if;
when T2 =>
if std_match(input, "10-----") then next_state <= T8; output <= "010100";
end if;
when R1 =>
if std_match(input, "101-1--") then next_state <= R2; output <= "100010";
elsif std_match(input, "100----") then next_state <= I1; output <= "100010";
elsif std_match(input, "101-0--") then next_state <= I2; output <= "100010";
end if;
when R2 =>
if std_match(input, "101-1--") then next_state <= R3; output <= "010010";
elsif std_match(input, "100----") then next_state <= I1; output <= "010010";
elsif std_match(input, "101-0--") then next_state <= I2; output <= "010010";
end if;
when R3 =>
if std_match(input, "101-1--") then next_state <= R4; output <= "110010";
elsif std_match(input, "101-0-0") then next_state <= R6; output <= "110010";
elsif std_match(input, "101-0-1") then next_state <= R8; output <= "110010";
elsif std_match(input, "100----") then next_state <= R5; output <= "110010";
end if;
when R4 =>
if std_match(input, "101-0-0") then next_state <= R6; output <= "001010";
elsif std_match(input, "101-0-1") then next_state <= R8; output <= "001010";
elsif std_match(input, "100----") then next_state <= R5; output <= "001010";
end if;
when R6 =>
if std_match(input, "101-0--") then next_state <= R7; output <= "011010";
elsif std_match(input, "101-1--") then next_state <= R5; output <= "011010";
elsif std_match(input, "100----") then next_state <= R5; output <= "011010";
end if;
when R7 =>
if std_match(input, "10-----") then next_state <= I2; output <= "111010";
end if;
when R8 =>
if std_match(input, "10-----") then next_state <= R5; output <= "000110";
end if;
when R5 =>
if std_match(input, "101----") then next_state <= I2; output <= "100110";
elsif std_match(input, "100----") then next_state <= I1; output <= "100110";
end if;
when I2 =>
if std_match(input, "-------") then next_state <= I0; output <= "000001";
end if;
when I1 =>
if std_match(input, "111-0--") then next_state <= I0; output <= "010111";
end if;
when others => next_state <= "-----"; output <= "------";
end case;
end process;
end behaviour;
| agpl-3.0 | 550641fe0214ea4af256dcd45e8f6789 | 0.564856 | 3.300485 | false | false | false | false |
TheMassController/VHDL_experimenting | project/common/data_safe.vhd | 1 | 682 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity data_safe_8_bit is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
read : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(7 DOWNTO 0);
data_out : out STD_LOGIC_VECTOR(7 DOWNTO 0)
);
end data_safe_8_bit;
architecture behavioral of data_safe_8_bit is
begin
process(clk, rst)
begin
if rst = '1' then
data_out <= (others => '0');
elsif rising_edge(clk) then
if (read = '1') then
data_out <= data_in;
end if;
end if;
end process;
end behavioral;
| mit | 59a4a5248daa3b378b00fa23cdd9a069 | 0.524927 | 3.427136 | false | false | false | false |
chastell/art-decomp | kiss/ex3_hot.vhd | 1 | 4,287 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex3_hot is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end ex3_hot;
architecture behaviour of ex3_hot is
constant s1: std_logic_vector(9 downto 0) := "1000000000";
constant s2: std_logic_vector(9 downto 0) := "0100000000";
constant s4: std_logic_vector(9 downto 0) := "0010000000";
constant s3: std_logic_vector(9 downto 0) := "0001000000";
constant s0: std_logic_vector(9 downto 0) := "0000100000";
constant s7: std_logic_vector(9 downto 0) := "0000010000";
constant s8: std_logic_vector(9 downto 0) := "0000001000";
constant s6: std_logic_vector(9 downto 0) := "0000000100";
constant s5: std_logic_vector(9 downto 0) := "0000000010";
constant s9: std_logic_vector(9 downto 0) := "0000000001";
signal current_state, next_state: std_logic_vector(9 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----------"; output <= "--";
case current_state is
when s1 =>
if std_match(input, "00") then next_state <= s2; output <= "--";
elsif std_match(input, "01") then next_state <= s4; output <= "01";
elsif std_match(input, "10") then next_state <= s3; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "10";
end if;
when s3 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s7; output <= "--";
elsif std_match(input, "10") then next_state <= s8; output <= "--";
end if;
when s4 =>
if std_match(input, "00") then next_state <= s2; output <= "--";
elsif std_match(input, "01") then next_state <= s1; output <= "--";
elsif std_match(input, "11") then next_state <= s6; output <= "--";
elsif std_match(input, "10") then next_state <= s5; output <= "--";
end if;
when s5 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s6; output <= "--";
end if;
when s6 =>
if std_match(input, "00") then next_state <= s1; output <= "00";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s2; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "11";
end if;
when s7 =>
if std_match(input, "00") then next_state <= s5; output <= "11";
elsif std_match(input, "01") then next_state <= s2; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
end if;
when s8 =>
if std_match(input, "00") then next_state <= s5; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s1; output <= "00";
end if;
when s9 =>
if std_match(input, "00") then next_state <= s5; output <= "--";
elsif std_match(input, "01") then next_state <= s3; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
end if;
when s2 =>
if std_match(input, "00") then next_state <= s6; output <= "--";
elsif std_match(input, "01") then next_state <= s9; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
end if;
when others => next_state <= "----------"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | 795d6727227fa8430235053eb3f17887 | 0.562165 | 3.372935 | false | false | false | false |
TheMassController/VHDL_experimenting | project/deppSlave/test/depp_slave_controller_tb.vhd | 1 | 18,940 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library vunit_lib;
context vunit_lib.vunit_context;
context vunit_lib.vc_context;
library src;
use src.bus_pkg.all;
use src.depp_pkg.all;
library tb;
use tb.depp_tb_pkg.all;
entity depp_slave_controller_tb is
generic (
runner_cfg : string);
end entity;
architecture tb of depp_slave_controller_tb is
constant clk_period : time := 20 ns;
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal depp_db : std_logic_vector(7 downto 0) := (others => '0');
signal depp_write : std_logic := '1';
signal depp_astb : std_logic := '1';
signal depp_dstb : std_logic := '1';
signal depp_wait : std_logic;
signal mst2slv : bus_mst2slv_type := BUS_MST2SLV_IDLE;
signal slv2mst : bus_slv2mst_type := BUS_SLV2MST_IDLE;
begin
clk <= not clk after (clk_period/2);
main : process
variable address : bus_address_type;
variable writeData : bus_data_type;
variable readData : bus_data_type;
variable readData_out : bus_data_type;
variable writeMask : bus_write_mask;
variable deppMode : depp_data_type;
variable deppAddr : depp_address_type;
variable expectedState : depp_slave_state_type := DEPP_SLAVE_STATE_TYPE_IDLE;
variable actualState : depp_slave_state_type := DEPP_SLAVE_STATE_TYPE_IDLE;
begin
test_runner_setup(runner, runner_cfg);
while test_suite loop
if run("Simple write") then
slv2mst <= BUS_SLV2MST_IDLE;
depp_db <= (others => 'Z');
-- Initial situation:
wait for clk_period;
check_equal('0', depp_wait);
wait until falling_edge(clk);
-- Start setting the output
address := std_logic_vector(to_unsigned(125, address'length));
writeData := std_logic_vector(to_unsigned(14, writeData'length));
writeMask := (others => '1');
depp_tb_bus_prepare_write(
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
address => address,
writeData => writeData,
writeMask => writeMask
);
-- Start the write
depp_tb_bus_start_transaction(
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
doRead => false
);
wait for 2*clk_period;
check_equal(mst2slv.address, address);
check_equal(mst2slv.writeData, writeData);
check_equal(mst2slv.writeMask, writeMask);
check_equal(mst2slv.writeEnable, '1');
check_equal(mst2slv.readEnable, '0');
check_equal(depp_wait, '0');
-- Wait a while, then finish normally
wait for 26*clk_period;
wait until falling_edge(clk);
slv2mst.ack <= '1';
wait for clk_period;
check_equal(mst2slv.writeEnable, '0');
check_equal(mst2slv.readEnable, '0');
check_equal(depp_wait, '1');
depp_tb_bus_finish_write_transaction(
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait
);
expectedState.address := address;
expectedState.writeData := writeData;
expectedState.writeMask := writeMask;
depp_tb_slave_check_state (
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
actualState => actualState
);
check(actualState = expectedState);
end if;
if run("Simple read") then
slv2mst <= BUS_SLV2MST_IDLE;
depp_db <= (others => 'Z');
-- Initial situation:
wait for clk_period;
check_equal('0', depp_wait);
wait until falling_edge(clk);
-- Start setting the output
address := std_logic_vector(to_unsigned(35, address'length));
writeData := (others => '0');
writeMask := (others => '0');
readData := std_logic_vector(to_unsigned(149, writeData'length));
depp_tb_bus_prepare_read(
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
address => address
);
-- Start the read
depp_tb_bus_start_transaction(
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
doRead => true
);
wait for 2*clk_period;
check_equal(mst2slv.address, address);
check_equal(mst2slv.writeData, writeData);
check_equal(mst2slv.writeMask, writeMask);
check_equal(mst2slv.writeEnable, '0');
check_equal(mst2slv.readEnable, '1');
check_equal(depp_wait, '0');
wait for 26*clk_period;
wait until falling_edge(clk);
slv2mst.ack <= '1';
slv2mst.readData <= readData;
wait for clk_period;
check_equal(mst2slv.writeEnable, '0');
check_equal(mst2slv.readEnable, '0');
check_equal(depp_wait, '1');
depp_tb_bus_finish_write_transaction(
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait
);
expectedState.address := address;
expectedState.writeData := writeData;
expectedState.readData := readData;
expectedState.writeMask := writeMask;
depp_tb_slave_check_state (
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
actualState => actualState
);
check(actualState = expectedState);
end if;
if run("Write returns error") then
slv2mst <= BUS_SLV2MST_IDLE;
depp_db <= (others => 'Z');
-- Initial situation:
wait for clk_period;
check_equal('0', depp_wait);
wait until falling_edge(clk);
-- Start setting the output
address := std_logic_vector(to_unsigned(114, address'length));
writeData := std_logic_vector(to_unsigned(25, writeData'length));
readData := (others => '1');
writeMask := (others => '1');
depp_tb_bus_prepare_write(
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
address => address,
writeData => writeData,
writeMask => writeMask
);
-- Start the write
depp_tb_bus_start_transaction(
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
doRead => false
);
wait for 2*clk_period;
check_equal(mst2slv.address, address);
check_equal(mst2slv.writeData, writeData);
check_equal(mst2slv.writeMask, writeMask);
check_equal(mst2slv.writeEnable, '1');
check_equal(mst2slv.readEnable, '0');
check_equal(depp_wait, '0');
-- Wait a while, then finish normally
wait for 26*clk_period;
wait until falling_edge(clk);
slv2mst.fault <= '1';
slv2mst.readData <= readData;
wait for clk_period;
check_equal(mst2slv.writeEnable, '0');
check_equal(mst2slv.readEnable, '0');
check_equal(depp_wait, '1');
depp_tb_bus_finish_write_transaction(
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait
);
expectedState.address := address;
expectedState.writeData := writeData;
expectedState.writeMask := writeMask;
expectedState.readData := readData;
expectedState.fault := true;
depp_tb_slave_check_state (
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
actualState => actualState
);
check(actualState = expectedState);
end if;
if run("Sequential write mode") then
slv2mst <= BUS_SLV2MST_IDLE;
address := (others => '0');
writeData := (others => '0');
readData := (others => '0');
writeMask := (others => '0');
deppMode := (others => '0');
deppMode(depp_mode_fast_write_bit) := '1';
deppAddr := std_logic_vector(to_unsigned(depp2bus_mode_register_start, deppAddr'length));
-- Initial situation:
wait for clk_period;
check_equal('0', depp_wait);
-- Enable sequential write mode
depp_tb_depp_write_to_address(
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
addr => deppAddr,
data => deppMode
);
-- Set the start address
depp_tb_bus_set_address (
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
address => address
);
deppAddr := std_logic_vector(to_unsigned(depp2bus_writeData_reg_start, deppAddr'length));
depp_tb_depp_set_address (
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
addr => deppAddr
);
for i in 0 to 20 loop
writeData := std_logic_vector(to_unsigned(i, writeData'length));
address := std_logic_vector(to_unsigned(i*depp2bus_writeData_reg_len, address'length));
for j in 0 to depp2bus_writeData_reg_len - 1 loop
depp_tb_depp_set_data(
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
data => writeData((j+1)*8 - 1 downto j*8),
expect_completion => (j /= depp2bus_writeData_reg_len - 1)
);
end loop;
wait until mst2slv.writeEnable = '1';
check_equal(mst2slv.address, address);
check_equal(mst2slv.writeData, writeData);
check_equal(mst2slv.writeMask, writeMask);
check_equal(mst2slv.writeEnable, '1');
check_equal(mst2slv.readEnable, '0');
check_equal(depp_wait, '0');
slv2mst.ack <= '1';
depp_tb_bus_finish_write_transaction(
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait
);
slv2mst.ack <= '0';
end loop;
end if;
if run("Sequential read mode") then
slv2mst <= BUS_SLV2MST_IDLE;
address := (others => '0');
writeData := (others => '0');
readData := (others => '0');
writeMask := (others => '0');
deppMode := (others => '0');
deppMode(depp_mode_fast_read_bit) := '1';
deppAddr := std_logic_vector(to_unsigned(depp2bus_mode_register_start, deppAddr'length));
-- Initial situation:
wait for clk_period;
check_equal('0', depp_wait);
-- Enable sequential read mode
depp_tb_depp_write_to_address(
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
addr => deppAddr,
data => deppMode
);
-- Set the start address
depp_tb_bus_set_address (
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
address => address
);
-- Set the depp address
deppAddr := std_logic_vector(to_unsigned(depp2bus_readData_reg_start, deppAddr'length));
depp_tb_depp_set_address (
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
addr => deppAddr
);
-- Now start reading
for i in 0 to 20 loop
readData := std_logic_vector(to_unsigned(i, writeData'length));
address := std_logic_vector(to_unsigned(i*depp2bus_readData_reg_len, address'length));
depp_tb_depp_get_data(
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
data => readData_out(7 downto 0),
expect_completion => false
);
wait until mst2slv.readEnable = '1';
check_equal(mst2slv.address, address);
check_equal(mst2slv.writeEnable, '0');
check_equal(mst2slv.readEnable, '1');
check_equal(depp_wait, '0');
slv2mst.readData <= readData;
slv2mst.ack <= '1';
depp_tb_bus_finish_read_transaction(
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
data => readData_out(7 downto 0)
);
slv2mst.ack <= '0';
for j in 1 to depp2bus_readData_reg_len - 1 loop
depp_tb_depp_get_data(
clk => clk,
usb_db => depp_db,
usb_write => depp_write,
usb_astb => depp_astb,
usb_dstb => depp_dstb,
usb_wait => depp_wait,
data => readData_out((j+1)*8 - 1 downto j*8),
expect_completion => true
);
end loop;
check_equal(readData, readData_out);
end loop;
end if;
end loop;
wait until rising_edge(clk) or falling_edge(clk);
test_runner_cleanup(runner);
wait;
end process;
test_runner_watchdog(runner, 10 ms);
controller : entity src.depp_slave_controller
port map (
rst => rst,
clk => clk,
mst2slv => mst2slv,
slv2mst => slv2mst,
USB_DB => depp_db,
USB_WRITE => depp_write,
USB_ASTB => depp_astb,
USB_DSTB => depp_dstb,
USB_WAIT => depp_wait
);
end tb;
| mit | 7c1aaa01e0a8a46787ac76ce347912a2 | 0.429303 | 4.738554 | false | false | false | false |
LucasMahieu/TP_secu | code/AES/vhd/vhd/GF_Inv.vhd | 2 | 1,081 | -- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
-- Component Declaration
entity gf_inv is
port ( a_in : std_logic_vector (3 downto 0);
d : out std_logic_vector (3 downto 0));
end gf_inv;
-- Architecture of the Component
architecture a_gf_inv of gf_inv is
begin
process (a_in)
begin
case a_in is
when "0000" => d <= "0000";
when "0001" => d <= "0001";
when "0010" => d <= "1001";
when "0011" => d <= "1110";
when "0100" => d <= "1101";
when "0101" => d <= "1011";
when "0110" => d <= "0111";
when "0111" => d <= "0110";
when "1000" => d <= "1111";
when "1001" => d <= "0010";
when "1010" => d <= "1100";
when "1011" => d <= "0101";
when "1100" => d <= "1010";
when "1101" => d <= "0100";
when "1110" => d <= "0011";
when "1111" => d <= "1000";
when others => null;
end case;
end process;
end a_gf_inv;
| mit | 13f8f26d8f90c366dc70eb5ba0c9c1a2 | 0.441258 | 3.57947 | false | false | false | false |
caiopo/battleship-vhdl | src/vector_to_bcd.vhd | 1 | 2,933 | library ieee;
use ieee.std_logic_1164.all;
entity vector_to_bcd is port(
input: in std_logic_vector(7 downto 0);
to_decod1, to_decod0: out std_logic_vector(3 downto 0)
);
end vector_to_bcd;
architecture behv of vector_to_bcd is
signal total: std_logic_vector(7 downto 0);
signal dec1, dec0: std_logic_vector(3 downto 0);
begin
-- converte um vetor de 8 bits em dois vetores de 4 bits em bcd
process(input)
begin
case input is
when "00000000" =>
dec1 <= "0000";
dec0 <= "0000";
when "00000001" =>
dec1 <= "0000";
dec0 <= "0001";
when "00000010" =>
dec1 <= "0000";
dec0 <= "0010";
when "00000011" =>
dec1 <= "0000";
dec0 <= "0011";
when "00000100" =>
dec1 <= "0000";
dec0 <= "0100";
when "00000101" =>
dec1 <= "0000";
dec0 <= "0101";
when "00000110" =>
dec1 <= "0000";
dec0 <= "0110";
when "00000111" =>
dec1 <= "0000";
dec0 <= "0111";
when "00001000" =>
dec1 <= "0000";
dec0 <= "1000";
when "00001001" =>
dec1 <= "0000";
dec0 <= "1001";
when "00001010" =>
dec1 <= "0001";
dec0 <= "0000";
when "00001011" =>
dec1 <= "0001";
dec0 <= "0001";
when "00001100" =>
dec1 <= "0001";
dec0 <= "0010";
when "00001101" =>
dec1 <= "0001";
dec0 <= "0011";
when "00001110" =>
dec1 <= "0001";
dec0 <= "0100";
when "00001111" =>
dec1 <= "0001";
dec0 <= "0101";
when "00010000" =>
dec1 <= "0001";
dec0 <= "0110";
when "00010001" =>
dec1 <= "0001";
dec0 <= "0111";
when "00010010" =>
dec1 <= "0001";
dec0 <= "1000";
when "00010011" =>
dec1 <= "0001";
dec0 <= "1001";
when "00010100" =>
dec1 <= "0010";
dec0 <= "0000";
when "00010101" =>
dec1 <= "0010";
dec0 <= "0001";
when "00010110" =>
dec1 <= "0010";
dec0 <= "0010";
when "00010111" =>
dec1 <= "0010";
dec0 <= "0011";
when "00011000" =>
dec1 <= "0010";
dec0 <= "0100";
when "00011001" =>
dec1 <= "0010";
dec0 <= "0101";
when "00011010" =>
dec1 <= "0010";
dec0 <= "0110";
when "00011011" =>
dec1 <= "0010";
dec0 <= "0111";
when "00011100" =>
dec1 <= "0010";
dec0 <= "1000";
when "00011101" =>
dec1 <= "0010";
dec0 <= "1001";
when "00011110" =>
dec1 <= "0011";
dec0 <= "0000";
when "00011111" =>
dec1 <= "0011";
dec0 <= "0001";
when "00100000" =>
dec1 <= "0011";
dec0 <= "0010";
when others =>
dec1 <= "1110";
dec0 <= "1110";
end case;
to_decod0 <= dec0;
to_decod1 <= dec1;
end process;
end behv; | mit | 8263bac854723059b4e4d6004833cb2a | 0.449369 | 2.995914 | false | false | false | false |
chastell/art-decomp | kiss/s1488_nov.vhd | 1 | 31,464 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s1488_nov is
port(
clock: in std_logic;
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(18 downto 0)
);
end s1488_nov;
architecture behaviour of s1488_nov is
constant s000000: std_logic_vector(5 downto 0) := "000000";
constant s001110: std_logic_vector(5 downto 0) := "100001";
constant s011000: std_logic_vector(5 downto 0) := "010100";
constant s010100: std_logic_vector(5 downto 0) := "101111";
constant s010011: std_logic_vector(5 downto 0) := "000111";
constant s000100: std_logic_vector(5 downto 0) := "101110";
constant s100011: std_logic_vector(5 downto 0) := "011100";
constant s110011: std_logic_vector(5 downto 0) := "110110";
constant s000111: std_logic_vector(5 downto 0) := "111111";
constant s101011: std_logic_vector(5 downto 0) := "111101";
constant s001111: std_logic_vector(5 downto 0) := "011101";
constant s010110: std_logic_vector(5 downto 0) := "110111";
constant s111100: std_logic_vector(5 downto 0) := "000001";
constant s101100: std_logic_vector(5 downto 0) := "111100";
constant s010111: std_logic_vector(5 downto 0) := "011010";
constant s001100: std_logic_vector(5 downto 0) := "101101";
constant s010001: std_logic_vector(5 downto 0) := "010111";
constant s110110: std_logic_vector(5 downto 0) := "101100";
constant s011111: std_logic_vector(5 downto 0) := "011111";
constant s101110: std_logic_vector(5 downto 0) := "001101";
constant s010101: std_logic_vector(5 downto 0) := "001111";
constant s111110: std_logic_vector(5 downto 0) := "001100";
constant s000011: std_logic_vector(5 downto 0) := "010011";
constant s111010: std_logic_vector(5 downto 0) := "011001";
constant s100000: std_logic_vector(5 downto 0) := "100111";
constant s101000: std_logic_vector(5 downto 0) := "000110";
constant s010010: std_logic_vector(5 downto 0) := "100110";
constant s011110: std_logic_vector(5 downto 0) := "010101";
constant s000010: std_logic_vector(5 downto 0) := "110101";
constant s001010: std_logic_vector(5 downto 0) := "011000";
constant s111000: std_logic_vector(5 downto 0) := "110100";
constant s001000: std_logic_vector(5 downto 0) := "010110";
constant s100100: std_logic_vector(5 downto 0) := "100101";
constant s001011: std_logic_vector(5 downto 0) := "111110";
constant s110100: std_logic_vector(5 downto 0) := "100100";
constant s011011: std_logic_vector(5 downto 0) := "111011";
constant s100110: std_logic_vector(5 downto 0) := "000101";
constant s011101: std_logic_vector(5 downto 0) := "011110";
constant s110000: std_logic_vector(5 downto 0) := "001110";
constant s000110: std_logic_vector(5 downto 0) := "000100";
constant s011010: std_logic_vector(5 downto 0) := "010010";
constant s110010: std_logic_vector(5 downto 0) := "101011";
constant s011100: std_logic_vector(5 downto 0) := "011011";
constant s101010: std_logic_vector(5 downto 0) := "101010";
constant s100010: std_logic_vector(5 downto 0) := "101001";
constant s111011: std_logic_vector(5 downto 0) := "111010";
constant s100111: std_logic_vector(5 downto 0) := "101000";
constant s010000: std_logic_vector(5 downto 0) := "100000";
signal current_state, next_state: std_logic_vector(5 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "------"; output <= "-------------------";
case current_state is
when s000000 =>
if std_match(input, "0-11----") then next_state <= s000000; output <= "0100011010010010111";
elsif std_match(input, "0-01----") then next_state <= s000000; output <= "0000000011000100000";
elsif std_match(input, "1-11----") then next_state <= s001110; output <= "0100011010010010111";
elsif std_match(input, "1-01----") then next_state <= s000000; output <= "0000000011000100000";
elsif std_match(input, "--00----") then next_state <= s000000; output <= "0000000010000110000";
elsif std_match(input, "--10----") then next_state <= s000000; output <= "0000000000000000000";
end if;
when s001110 =>
if std_match(input, "00------") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "01--1---") then next_state <= s000000; output <= "0010100010001110000";
elsif std_match(input, "01--0---") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1---0---") then next_state <= s011000; output <= "0000001010001010000";
elsif std_match(input, "10--1---") then next_state <= s011000; output <= "0000001010001010000";
elsif std_match(input, "11--1---") then next_state <= s010000; output <= "0010100010001110000";
end if;
when s011000 =>
if std_match(input, "0-10-010") then next_state <= s000000; output <= "0000010000000000000";
elsif std_match(input, "0-10-000") then next_state <= s000000; output <= "0000010000000000001";
elsif std_match(input, "0-10-100") then next_state <= s000000; output <= "0000010000000000101";
elsif std_match(input, "0-10-110") then next_state <= s000000; output <= "0000010000000000100";
elsif std_match(input, "0-11-1-0") then next_state <= s000000; output <= "0000011000011011101";
elsif std_match(input, "0-11-0-0") then next_state <= s000000; output <= "0000011000011011001";
elsif std_match(input, "0-00-100") then next_state <= s000000; output <= "0000000000001111101";
elsif std_match(input, "0-00-110") then next_state <= s000000; output <= "0000000000001111100";
elsif std_match(input, "0-00-000") then next_state <= s000000; output <= "0000000000001111001";
elsif std_match(input, "0-00-010") then next_state <= s000000; output <= "0000000000001111000";
elsif std_match(input, "0-01-100") then next_state <= s000000; output <= "0000010001001101101";
elsif std_match(input, "0-01-110") then next_state <= s000000; output <= "0000010001001101100";
elsif std_match(input, "0-01-010") then next_state <= s000000; output <= "0000010001001101000";
elsif std_match(input, "0-01-000") then next_state <= s000000; output <= "0000010001001101001";
elsif std_match(input, "0-----01") then next_state <= s000000; output <= "0000001100111010011";
elsif std_match(input, "0-----11") then next_state <= s000000; output <= "0000001100111010010";
elsif std_match(input, "1-----11") then next_state <= s010100; output <= "0000001100111010010";
elsif std_match(input, "1-----01") then next_state <= s010100; output <= "0000001100111010011";
elsif std_match(input, "1-01-100") then next_state <= s010100; output <= "0000010001001101101";
elsif std_match(input, "1-01-110") then next_state <= s010100; output <= "0000010001001101100";
elsif std_match(input, "1-01-000") then next_state <= s010100; output <= "0000010001001101001";
elsif std_match(input, "1-01-010") then next_state <= s010100; output <= "0000010001001101000";
elsif std_match(input, "1-11-1-0") then next_state <= s110011; output <= "0000011000011011101";
elsif std_match(input, "1-11-0-0") then next_state <= s110011; output <= "0000011000011011001";
elsif std_match(input, "1-00-100") then next_state <= s010100; output <= "0000000000001111101";
elsif std_match(input, "1-00-110") then next_state <= s010100; output <= "0000000000001111100";
elsif std_match(input, "1-00-000") then next_state <= s010100; output <= "0000000000001111001";
elsif std_match(input, "1-00-010") then next_state <= s010100; output <= "0000000000001111000";
elsif std_match(input, "1-10-000") then next_state <= s010100; output <= "0000010000000000001";
elsif std_match(input, "1-10-010") then next_state <= s010100; output <= "0000010000000000000";
elsif std_match(input, "1-10-110") then next_state <= s010100; output <= "0000010000000000100";
elsif std_match(input, "1-10-100") then next_state <= s010100; output <= "0000010000000000101";
end if;
when s010100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1-------") then next_state <= s010011; output <= "0000001010001010000";
end if;
when s010011 =>
if std_match(input, "1----0--") then next_state <= s000100; output <= "0000001010000110011";
elsif std_match(input, "1----1--") then next_state <= s000100; output <= "0000001010000110111";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000001010000110011";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001010000110111";
end if;
when s000100 =>
if std_match(input, "11---01-") then next_state <= s100011; output <= "0000001010001010000";
elsif std_match(input, "01---01-") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "11--111-") then next_state <= s010110; output <= "0000001010001010000";
elsif std_match(input, "11--011-") then next_state <= s010111; output <= "0000001010001010000";
elsif std_match(input, "01---11-") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "10----1-") then next_state <= s010111; output <= "0000001010001010000";
elsif std_match(input, "00----1-") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "0-----0-") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1-----0-") then next_state <= s010111; output <= "0000001010001010000";
end if;
when s100011 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001000011011001";
elsif std_match(input, "1-------") then next_state <= s110011; output <= "0000001000011011001";
end if;
when s110011 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1-------") then next_state <= s000111; output <= "0000001010001010000";
end if;
when s000111 =>
if std_match(input, "0----0--") then next_state <= s000000; output <= "0000001000011011010";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001000011011110";
elsif std_match(input, "1----1--") then next_state <= s101011; output <= "0000001000011011110";
elsif std_match(input, "1----0--") then next_state <= s101011; output <= "0000001000011011010";
end if;
when s101011 =>
if std_match(input, "1-------") then next_state <= s001111; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s001111 =>
if std_match(input, "1----0--") then next_state <= s000100; output <= "0001000000101011011";
elsif std_match(input, "1----1--") then next_state <= s000100; output <= "0001000000101011111";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0001000000101011111";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0001000000101011011";
end if;
when s010110 =>
if std_match(input, "1----1--") then next_state <= s111100; output <= "0100001010010010111";
elsif std_match(input, "1-11-0--") then next_state <= s110011; output <= "0000011000011011001";
elsif std_match(input, "1-01-0--") then next_state <= s101100; output <= "0000010001001101000";
elsif std_match(input, "1-00-0--") then next_state <= s101100; output <= "0000000000001111000";
elsif std_match(input, "1-10-0--") then next_state <= s101100; output <= "0000010000000000000";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0100001010010010111";
elsif std_match(input, "0-10-0--") then next_state <= s000000; output <= "0000010000000000000";
elsif std_match(input, "0-11-0--") then next_state <= s000000; output <= "0000011000011011001";
elsif std_match(input, "0-00-0--") then next_state <= s000000; output <= "0000000000001111000";
elsif std_match(input, "0-01-0--") then next_state <= s000000; output <= "0000010001001101000";
end if;
when s111100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001110001010000";
elsif std_match(input, "1-------") then next_state <= s100011; output <= "0000001110001010000";
end if;
when s101100 =>
if std_match(input, "1-------") then next_state <= s010110; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s010111 =>
if std_match(input, "1----0--") then next_state <= s001100; output <= "0000000000110010010";
elsif std_match(input, "1----1--") then next_state <= s001100; output <= "0000000000110010110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000110010010";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000000110010110";
end if;
when s001100 =>
if std_match(input, "1----0--") then next_state <= s010001; output <= "0000001010001010000";
elsif std_match(input, "1----1--") then next_state <= s011011; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s010001 =>
if std_match(input, "0----0--") then next_state <= s000000; output <= "0000001000011110011";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001000011110111";
elsif std_match(input, "1----1--") then next_state <= s110110; output <= "0000001000011110111";
elsif std_match(input, "1----0--") then next_state <= s110110; output <= "0000001000011110011";
end if;
when s110110 =>
if std_match(input, "1-------") then next_state <= s011111; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s011111 =>
if std_match(input, "0----11-") then next_state <= s000000; output <= "0000000000110111111";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000000000110111110";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000110111010";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000110111011";
elsif std_match(input, "1----00-") then next_state <= s101110; output <= "0000000000110111010";
elsif std_match(input, "1----01-") then next_state <= s101110; output <= "0000000000110111011";
elsif std_match(input, "1----10-") then next_state <= s101110; output <= "0000000000110111110";
elsif std_match(input, "1----11-") then next_state <= s101110; output <= "0000000000110111111";
end if;
when s101110 =>
if std_match(input, "1-------") then next_state <= s010101; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s010101 =>
if std_match(input, "1----1--") then next_state <= s111110; output <= "0000001000001111101";
elsif std_match(input, "1----0--") then next_state <= s111110; output <= "0000001000001111001";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000001000001111001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001000001111101";
end if;
when s111110 =>
if std_match(input, "00--1-0-") then next_state <= s000000; output <= "1000001010001010000";
elsif std_match(input, "01--1-0-") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "0---0-0-") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "0---0-1-") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "0---1-1-") then next_state <= s000000; output <= "1000001010001010000";
elsif std_match(input, "10--0---") then next_state <= s000011; output <= "0000001010001010000";
elsif std_match(input, "10--1--1") then next_state <= s111010; output <= "1000001010001010000";
elsif std_match(input, "10--1--0") then next_state <= s011010; output <= "1000001010001010000";
elsif std_match(input, "11--1-11") then next_state <= s111010; output <= "1000001010001010000";
elsif std_match(input, "11--0-11") then next_state <= s000011; output <= "0000001010001010000";
elsif std_match(input, "11--1-10") then next_state <= s011010; output <= "1000001010001010000";
elsif std_match(input, "11--0-10") then next_state <= s000011; output <= "0000001010001010000";
elsif std_match(input, "11--1-00") then next_state <= s111011; output <= "0000001010001010000";
elsif std_match(input, "11--1-01") then next_state <= s000011; output <= "0000001010001010000";
elsif std_match(input, "11--0-0-") then next_state <= s000011; output <= "0000001010001010000";
end if;
when s000011 =>
if std_match(input, "1----0-1") then next_state <= s001110; output <= "0000001010010010011";
elsif std_match(input, "1----0-0") then next_state <= s001110; output <= "0000001010010110011";
elsif std_match(input, "1----1--") then next_state <= s001110; output <= "0000001010010010111";
elsif std_match(input, "0----0-1") then next_state <= s000000; output <= "0000001010010010011";
elsif std_match(input, "0----1-1") then next_state <= s000000; output <= "0000001010010010111";
elsif std_match(input, "0----0-0") then next_state <= s000000; output <= "0000001010010110011";
elsif std_match(input, "0----1-0") then next_state <= s000000; output <= "0000001010010010111";
end if;
when s111010 =>
if std_match(input, "1-------") then next_state <= s100000; output <= "0000001010010010011";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010010010011";
end if;
when s100000 =>
if std_match(input, "00--1---") then next_state <= s000000; output <= "0000101010001010000";
elsif std_match(input, "01--1---") then next_state <= s000000; output <= "0000001110001010000";
elsif std_match(input, "11--1---") then next_state <= s101000; output <= "0000001110001010000";
elsif std_match(input, "10--1---") then next_state <= s110000; output <= "0000101010001010000";
elsif std_match(input, "11--0---") then next_state <= s101000; output <= "0000001110001010000";
elsif std_match(input, "01--0---") then next_state <= s000000; output <= "0000001110001010000";
elsif std_match(input, "00--0---") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "10--0---") then next_state <= s011110; output <= "0000001010001010000";
end if;
when s101000 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001010000110011";
elsif std_match(input, "1-------") then next_state <= s010010; output <= "0000001010000110011";
end if;
when s010010 =>
if std_match(input, "1---0---") then next_state <= s011110; output <= "0000001010001010000";
elsif std_match(input, "0---0---") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "0---1---") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1---1---") then next_state <= s001010; output <= "0000001010001010000";
end if;
when s011110 =>
if std_match(input, "0-00-00-") then next_state <= s000000; output <= "0000000000001111000";
elsif std_match(input, "0-00-01-") then next_state <= s000000; output <= "0000000000001111001";
elsif std_match(input, "0-10-01-") then next_state <= s000000; output <= "0000010000000000001";
elsif std_match(input, "0-10-00-") then next_state <= s000000; output <= "0000010000000000000";
elsif std_match(input, "0--0-1--") then next_state <= s000000; output <= "0000001010010010111";
elsif std_match(input, "0--1-1--") then next_state <= s000000; output <= "0000001010010010111";
elsif std_match(input, "0-11-0--") then next_state <= s000000; output <= "0000011000011011001";
elsif std_match(input, "0-01-00-") then next_state <= s000000; output <= "0000010001001101000";
elsif std_match(input, "0-01-01-") then next_state <= s000000; output <= "0000010001001101001";
elsif std_match(input, "1-0--1--") then next_state <= s100000; output <= "0000001010010010111";
elsif std_match(input, "1-00-00-") then next_state <= s000010; output <= "0000000000001111000";
elsif std_match(input, "1-00-01-") then next_state <= s000010; output <= "0000000000001111001";
elsif std_match(input, "1-01-01-") then next_state <= s000010; output <= "0000010001001101001";
elsif std_match(input, "1-01-00-") then next_state <= s000010; output <= "0000010001001101000";
elsif std_match(input, "1-10-1--") then next_state <= s100000; output <= "0000001010010010111";
elsif std_match(input, "1-10-01-") then next_state <= s000010; output <= "0000010000000000001";
elsif std_match(input, "1-10-00-") then next_state <= s000010; output <= "0000010000000000000";
elsif std_match(input, "1-11-1--") then next_state <= s100000; output <= "0000001010010010111";
elsif std_match(input, "1-11-0--") then next_state <= s110011; output <= "0000011000011011001";
end if;
when s000010 =>
if std_match(input, "1----0--") then next_state <= s011110; output <= "0001001010001010000";
elsif std_match(input, "1----1--") then next_state <= s011110; output <= "0000001010001010000";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0001001010001010000";
end if;
when s001010 =>
if std_match(input, "0----0--") then next_state <= s000000; output <= "0000001010100010001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001000011011101";
elsif std_match(input, "1----0--") then next_state <= s111000; output <= "0000001010100010001";
elsif std_match(input, "1----1--") then next_state <= s100100; output <= "0000001000011011101";
end if;
when s111000 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1---01--") then next_state <= s001010; output <= "0000001010001010000";
elsif std_match(input, "1---00--") then next_state <= s001000; output <= "0000001010001010000";
elsif std_match(input, "1---1---") then next_state <= s001000; output <= "0000001010001010000";
end if;
when s001000 =>
if std_match(input, "1----0--") then next_state <= s100100; output <= "0000001000011011001";
elsif std_match(input, "1----1--") then next_state <= s100100; output <= "0000001000011011101";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000001000011011001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001000011011101";
end if;
when s100100 =>
if std_match(input, "1-------") then next_state <= s001011; output <= "0001001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0001001010001010000";
end if;
when s001011 =>
if std_match(input, "1----0--") then next_state <= s110100; output <= "0000001000011011010";
elsif std_match(input, "1----1--") then next_state <= s110100; output <= "0000001000011011110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000001000011011010";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001000011011110";
end if;
when s110100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0001001010001010000";
elsif std_match(input, "1-------") then next_state <= s011011; output <= "0001001010001010000";
end if;
when s011011 =>
if std_match(input, "0----10-") then next_state <= s000000; output <= "0000001000011010111";
elsif std_match(input, "0----11-") then next_state <= s000000; output <= "0000001000011010110";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000001000011010010";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000001000011010011";
elsif std_match(input, "1----01-") then next_state <= s100110; output <= "0000001000011010010";
elsif std_match(input, "1----00-") then next_state <= s100110; output <= "0000001000011010011";
elsif std_match(input, "1----11-") then next_state <= s100110; output <= "0000001000011010110";
elsif std_match(input, "1----10-") then next_state <= s100110; output <= "0000001000011010111";
end if;
when s100110 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1-------") then next_state <= s011101; output <= "0000001010001010000";
end if;
when s011101 =>
if std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000110011000";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000110011001";
elsif std_match(input, "0----11-") then next_state <= s000000; output <= "0000000000110011101";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000000000110011100";
elsif std_match(input, "1----11-") then next_state <= s101110; output <= "0000000000110011101";
elsif std_match(input, "1----10-") then next_state <= s101110; output <= "0000000000110011100";
elsif std_match(input, "1----00-") then next_state <= s101110; output <= "0000000000110011000";
elsif std_match(input, "1----01-") then next_state <= s101110; output <= "0000000000110011001";
end if;
when s110000 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001000001111001";
elsif std_match(input, "1-------") then next_state <= s000110; output <= "0000001000001111001";
end if;
when s000110 =>
if std_match(input, "0----0--") then next_state <= s000000; output <= "0001001010001010000";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0100001010001010000";
elsif std_match(input, "1---01--") then next_state <= s011000; output <= "0100001010001010000";
elsif std_match(input, "1---00--") then next_state <= s011000; output <= "0001001010001010000";
elsif std_match(input, "1---11--") then next_state <= s011110; output <= "0100001010001010000";
elsif std_match(input, "1---10--") then next_state <= s011110; output <= "0001001010001010000";
end if;
when s011010 =>
if std_match(input, "1----1--") then next_state <= s100000; output <= "0000001010010010111";
elsif std_match(input, "1----00-") then next_state <= s110010; output <= "0000001010100010001";
elsif std_match(input, "1----01-") then next_state <= s110010; output <= "0000001010100010000";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000001010100010001";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000001010100010000";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001010010010111";
end if;
when s110010 =>
if std_match(input, "1----00-") then next_state <= s011100; output <= "0000001010001010000";
elsif std_match(input, "1----01-") then next_state <= s011010; output <= "0000001010001010000";
elsif std_match(input, "1----10-") then next_state <= s011010; output <= "0000001010001010000";
elsif std_match(input, "1----11-") then next_state <= s011100; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s011100 =>
if std_match(input, "0----11-") then next_state <= s000000; output <= "0000001000111010111";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000001000111010110";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000001000111010011";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000001000111010010";
elsif std_match(input, "1----10-") then next_state <= s101010; output <= "0000001000111010110";
elsif std_match(input, "1----11-") then next_state <= s101010; output <= "0000001000111010111";
elsif std_match(input, "1----01-") then next_state <= s100010; output <= "0000001000111010011";
elsif std_match(input, "1----00-") then next_state <= s100010; output <= "0000001000111010010";
end if;
when s101010 =>
if std_match(input, "1-------") then next_state <= s111010; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s100010 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1-------") then next_state <= s011010; output <= "0000001010001010000";
end if;
when s111011 =>
if std_match(input, "1----0--") then next_state <= s100111; output <= "0000001010010110011";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000001010010110011";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0010101010010010111";
elsif std_match(input, "1----1--") then next_state <= s010000; output <= "0010101010010010111";
end if;
when s100111 =>
if std_match(input, "1-------") then next_state <= s111011; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s010000 =>
if std_match(input, "--------") then next_state <= s000000; output <= "0000001000011010010";
end if;
when others => next_state <= "------"; output <= "-------------------";
end case;
end process;
end behaviour;
| agpl-3.0 | cd933f5c55aec26594ee3c3b5d1a0b7d | 0.625795 | 3.832866 | false | false | false | false |
ibm2030/IBM2030 | Testbench_panel_Switches.vhd | 1 | 2,525 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:36:53 11/26/2015
-- Design Name:
-- Module Name: C:/Users/lwilkinson/Documents/Xilinx/IBM2030GIT/Testbench_panel_Switches.vhd
-- Project Name: IBM2030
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: panel_Switches
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Testbench_panel_Switches IS
END Testbench_panel_Switches;
ARCHITECTURE behavior OF Testbench_panel_Switches IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT panel_Switches
PORT(
LEDs : IN std_logic_vector(0 to 4);
clk : IN std_logic;
Switches : OUT std_logic_vector(0 to 63);
SCL : OUT std_logic;
SDA : INOUT std_logic
);
END COMPONENT;
--Inputs
signal LEDs : std_logic_vector(0 to 4) := (others => '0');
signal clk : std_logic := '0';
--BiDirs
signal MAX7318_SDA : std_logic;
--Outputs
signal Switches : std_logic_vector(0 to 63);
signal MAX7318_SCL : std_logic;
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: panel_Switches PORT MAP (
LEDs => LEDs,
clk => clk,
Switches => Switches,
SCL => MAX7318_SCL,
SDA => MAX7318_SDA
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait for 10ms;
wait;
end process;
END;
| gpl-3.0 | 934439b66ff54b68e6d0b3f776682df6 | 0.601188 | 3.976378 | false | true | false | false |
chastell/art-decomp | kiss/keyb_nov.vhd | 1 | 16,319 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity keyb_nov is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(1 downto 0)
);
end keyb_nov;
architecture behaviour of keyb_nov is
constant st0: std_logic_vector(4 downto 0) := "00000";
constant st1: std_logic_vector(4 downto 0) := "00100";
constant st2: std_logic_vector(4 downto 0) := "01100";
constant st3: std_logic_vector(4 downto 0) := "00001";
constant st4: std_logic_vector(4 downto 0) := "00101";
constant st5: std_logic_vector(4 downto 0) := "01101";
constant st6: std_logic_vector(4 downto 0) := "00111";
constant st7: std_logic_vector(4 downto 0) := "00110";
constant st8: std_logic_vector(4 downto 0) := "01110";
constant st9: std_logic_vector(4 downto 0) := "00011";
constant st10: std_logic_vector(4 downto 0) := "00010";
constant st11: std_logic_vector(4 downto 0) := "01000";
constant st12: std_logic_vector(4 downto 0) := "01001";
constant st13: std_logic_vector(4 downto 0) := "01111";
constant st14: std_logic_vector(4 downto 0) := "01010";
constant st15: std_logic_vector(4 downto 0) := "10101";
constant st16: std_logic_vector(4 downto 0) := "01011";
constant st17: std_logic_vector(4 downto 0) := "11010";
constant st18: std_logic_vector(4 downto 0) := "10100";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "--";
case current_state is
when st0 =>
if std_match(input, "---0000") then next_state <= st1; output <= "1-";
elsif std_match(input, "---0100") then next_state <= st2; output <= "1-";
elsif std_match(input, "---0010") then next_state <= st2; output <= "1-";
elsif std_match(input, "---0001") then next_state <= st2; output <= "1-";
elsif std_match(input, "---1100") then next_state <= st3; output <= "1-";
elsif std_match(input, "---1000") then next_state <= st3; output <= "1-";
elsif std_match(input, "---011-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---01-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---101-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---10-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---111-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---11-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st1 =>
if std_match(input, "0000000") then next_state <= st4; output <= "1-";
elsif std_match(input, "1000000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0100000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0010000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0001000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000100") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000010") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000001") then next_state <= st5; output <= "0-";
elsif std_match(input, "11-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "1-1----") then next_state <= st0; output <= "-0";
elsif std_match(input, "1--1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "1---1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "1----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "1-----1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-11----") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1-1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1--1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1---1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1----1") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1-1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1--1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1---1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---11--") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st2 =>
if std_match(input, "0000000") then next_state <= st5; output <= "--";
elsif std_match(input, "1------") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1----") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st3 =>
if std_match(input, "0000000") then next_state <= st6; output <= "1-";
elsif std_match(input, "0011000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000100") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000010") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000001") then next_state <= st5; output <= "0-";
elsif std_match(input, "1------") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "--01---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--10---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--111--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st4 =>
if std_match(input, "-000000") then next_state <= st7; output <= "1-";
elsif std_match(input, "-100000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-010000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-001000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000100") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000010") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000001") then next_state <= st8; output <= "0-";
elsif std_match(input, "-11----") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1-1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1--1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1---1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1----1") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1-1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1--1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1---1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---11--") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st5 =>
if std_match(input, "-000000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1----") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st6 =>
if std_match(input, "-011000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000100") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000010") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000001") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000000") then next_state <= st9; output <= "1-";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "--01---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--10---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--111--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st7 =>
if std_match(input, "--00000") then next_state <= st10; output <= "1-";
elsif std_match(input, "--10000") then next_state <= st11; output <= "0-";
elsif std_match(input, "--01000") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00100") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00010") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00001") then next_state <= st11; output <= "0-";
elsif std_match(input, "--11---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1-1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1--1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1---1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---11--") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st8 =>
if std_match(input, "--00000") then next_state <= st11; output <= "0-";
elsif std_match(input, "--1----") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st9 =>
if std_match(input, "--00000") then next_state <= st12; output <= "--";
elsif std_match(input, "--11000") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00100") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00010") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00001") then next_state <= st11; output <= "0-";
elsif std_match(input, "--01---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--10---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--111--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st10 =>
if std_match(input, "----000") then next_state <= st13; output <= "1-";
elsif std_match(input, "----100") then next_state <= st14; output <= "0-";
elsif std_match(input, "----010") then next_state <= st14; output <= "0-";
elsif std_match(input, "----001") then next_state <= st14; output <= "0-";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st11 =>
if std_match(input, "----000") then next_state <= st14; output <= "0-";
elsif std_match(input, "----1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st12 =>
if std_match(input, "-----00") then next_state <= st14; output <= "--";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st13 =>
if std_match(input, "-----00") then next_state <= st15; output <= "1-";
elsif std_match(input, "-----10") then next_state <= st16; output <= "0-";
elsif std_match(input, "-----01") then next_state <= st16; output <= "0-";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st14 =>
if std_match(input, "-----00") then next_state <= st16; output <= "0-";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st15 =>
if std_match(input, "------0") then next_state <= st17; output <= "--";
elsif std_match(input, "------1") then next_state <= st18; output <= "0-";
end if;
when st16 =>
if std_match(input, "------0") then next_state <= st18; output <= "0-";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st17 =>
if std_match(input, "-------") then next_state <= st0; output <= "-0";
end if;
when st18 =>
if std_match(input, "-------") then next_state <= st0; output <= "-1";
end if;
when others => next_state <= "-----"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | 63ad19569f965fc14a886a9d372e6827 | 0.541026 | 3.343372 | false | false | false | false |
chastell/art-decomp | kiss/s1488_rnd.vhd | 1 | 31,464 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s1488_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(18 downto 0)
);
end s1488_rnd;
architecture behaviour of s1488_rnd is
constant s000000: std_logic_vector(5 downto 0) := "111101";
constant s001110: std_logic_vector(5 downto 0) := "000010";
constant s011000: std_logic_vector(5 downto 0) := "011011";
constant s010000: std_logic_vector(5 downto 0) := "111110";
constant s010100: std_logic_vector(5 downto 0) := "111111";
constant s110011: std_logic_vector(5 downto 0) := "010001";
constant s010011: std_logic_vector(5 downto 0) := "010110";
constant s000100: std_logic_vector(5 downto 0) := "001011";
constant s100011: std_logic_vector(5 downto 0) := "001111";
constant s010110: std_logic_vector(5 downto 0) := "011110";
constant s010111: std_logic_vector(5 downto 0) := "101011";
constant s000111: std_logic_vector(5 downto 0) := "100001";
constant s101011: std_logic_vector(5 downto 0) := "110000";
constant s001111: std_logic_vector(5 downto 0) := "101111";
constant s111100: std_logic_vector(5 downto 0) := "011010";
constant s101100: std_logic_vector(5 downto 0) := "111000";
constant s001100: std_logic_vector(5 downto 0) := "110110";
constant s010001: std_logic_vector(5 downto 0) := "001000";
constant s011011: std_logic_vector(5 downto 0) := "000001";
constant s110110: std_logic_vector(5 downto 0) := "100100";
constant s011111: std_logic_vector(5 downto 0) := "001001";
constant s101110: std_logic_vector(5 downto 0) := "101001";
constant s010101: std_logic_vector(5 downto 0) := "100110";
constant s111110: std_logic_vector(5 downto 0) := "111011";
constant s000011: std_logic_vector(5 downto 0) := "011100";
constant s111010: std_logic_vector(5 downto 0) := "100011";
constant s011010: std_logic_vector(5 downto 0) := "100010";
constant s111011: std_logic_vector(5 downto 0) := "011000";
constant s100000: std_logic_vector(5 downto 0) := "000011";
constant s101000: std_logic_vector(5 downto 0) := "110111";
constant s110000: std_logic_vector(5 downto 0) := "010011";
constant s011110: std_logic_vector(5 downto 0) := "110010";
constant s010010: std_logic_vector(5 downto 0) := "000111";
constant s001010: std_logic_vector(5 downto 0) := "001100";
constant s000010: std_logic_vector(5 downto 0) := "110101";
constant s111000: std_logic_vector(5 downto 0) := "010100";
constant s100100: std_logic_vector(5 downto 0) := "000000";
constant s001000: std_logic_vector(5 downto 0) := "100111";
constant s001011: std_logic_vector(5 downto 0) := "011101";
constant s110100: std_logic_vector(5 downto 0) := "101101";
constant s100110: std_logic_vector(5 downto 0) := "100101";
constant s011101: std_logic_vector(5 downto 0) := "100000";
constant s000110: std_logic_vector(5 downto 0) := "111100";
constant s110010: std_logic_vector(5 downto 0) := "000100";
constant s011100: std_logic_vector(5 downto 0) := "110011";
constant s101010: std_logic_vector(5 downto 0) := "010111";
constant s100010: std_logic_vector(5 downto 0) := "111010";
constant s100111: std_logic_vector(5 downto 0) := "111001";
signal current_state, next_state: std_logic_vector(5 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "------"; output <= "-------------------";
case current_state is
when s000000 =>
if std_match(input, "0-11----") then next_state <= s000000; output <= "0100011010010010111";
elsif std_match(input, "0-01----") then next_state <= s000000; output <= "0000000011000100000";
elsif std_match(input, "1-11----") then next_state <= s001110; output <= "0100011010010010111";
elsif std_match(input, "1-01----") then next_state <= s000000; output <= "0000000011000100000";
elsif std_match(input, "--00----") then next_state <= s000000; output <= "0000000010000110000";
elsif std_match(input, "--10----") then next_state <= s000000; output <= "0000000000000000000";
end if;
when s001110 =>
if std_match(input, "00------") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "01--1---") then next_state <= s000000; output <= "0010100010001110000";
elsif std_match(input, "01--0---") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1---0---") then next_state <= s011000; output <= "0000001010001010000";
elsif std_match(input, "10--1---") then next_state <= s011000; output <= "0000001010001010000";
elsif std_match(input, "11--1---") then next_state <= s010000; output <= "0010100010001110000";
end if;
when s011000 =>
if std_match(input, "0-10-010") then next_state <= s000000; output <= "0000010000000000000";
elsif std_match(input, "0-10-000") then next_state <= s000000; output <= "0000010000000000001";
elsif std_match(input, "0-10-100") then next_state <= s000000; output <= "0000010000000000101";
elsif std_match(input, "0-10-110") then next_state <= s000000; output <= "0000010000000000100";
elsif std_match(input, "0-11-1-0") then next_state <= s000000; output <= "0000011000011011101";
elsif std_match(input, "0-11-0-0") then next_state <= s000000; output <= "0000011000011011001";
elsif std_match(input, "0-00-100") then next_state <= s000000; output <= "0000000000001111101";
elsif std_match(input, "0-00-110") then next_state <= s000000; output <= "0000000000001111100";
elsif std_match(input, "0-00-000") then next_state <= s000000; output <= "0000000000001111001";
elsif std_match(input, "0-00-010") then next_state <= s000000; output <= "0000000000001111000";
elsif std_match(input, "0-01-100") then next_state <= s000000; output <= "0000010001001101101";
elsif std_match(input, "0-01-110") then next_state <= s000000; output <= "0000010001001101100";
elsif std_match(input, "0-01-010") then next_state <= s000000; output <= "0000010001001101000";
elsif std_match(input, "0-01-000") then next_state <= s000000; output <= "0000010001001101001";
elsif std_match(input, "0-----01") then next_state <= s000000; output <= "0000001100111010011";
elsif std_match(input, "0-----11") then next_state <= s000000; output <= "0000001100111010010";
elsif std_match(input, "1-----11") then next_state <= s010100; output <= "0000001100111010010";
elsif std_match(input, "1-----01") then next_state <= s010100; output <= "0000001100111010011";
elsif std_match(input, "1-01-100") then next_state <= s010100; output <= "0000010001001101101";
elsif std_match(input, "1-01-110") then next_state <= s010100; output <= "0000010001001101100";
elsif std_match(input, "1-01-000") then next_state <= s010100; output <= "0000010001001101001";
elsif std_match(input, "1-01-010") then next_state <= s010100; output <= "0000010001001101000";
elsif std_match(input, "1-11-1-0") then next_state <= s110011; output <= "0000011000011011101";
elsif std_match(input, "1-11-0-0") then next_state <= s110011; output <= "0000011000011011001";
elsif std_match(input, "1-00-100") then next_state <= s010100; output <= "0000000000001111101";
elsif std_match(input, "1-00-110") then next_state <= s010100; output <= "0000000000001111100";
elsif std_match(input, "1-00-000") then next_state <= s010100; output <= "0000000000001111001";
elsif std_match(input, "1-00-010") then next_state <= s010100; output <= "0000000000001111000";
elsif std_match(input, "1-10-000") then next_state <= s010100; output <= "0000010000000000001";
elsif std_match(input, "1-10-010") then next_state <= s010100; output <= "0000010000000000000";
elsif std_match(input, "1-10-110") then next_state <= s010100; output <= "0000010000000000100";
elsif std_match(input, "1-10-100") then next_state <= s010100; output <= "0000010000000000101";
end if;
when s010100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1-------") then next_state <= s010011; output <= "0000001010001010000";
end if;
when s010011 =>
if std_match(input, "1----0--") then next_state <= s000100; output <= "0000001010000110011";
elsif std_match(input, "1----1--") then next_state <= s000100; output <= "0000001010000110111";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000001010000110011";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001010000110111";
end if;
when s000100 =>
if std_match(input, "11---01-") then next_state <= s100011; output <= "0000001010001010000";
elsif std_match(input, "01---01-") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "11--111-") then next_state <= s010110; output <= "0000001010001010000";
elsif std_match(input, "11--011-") then next_state <= s010111; output <= "0000001010001010000";
elsif std_match(input, "01---11-") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "10----1-") then next_state <= s010111; output <= "0000001010001010000";
elsif std_match(input, "00----1-") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "0-----0-") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1-----0-") then next_state <= s010111; output <= "0000001010001010000";
end if;
when s100011 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001000011011001";
elsif std_match(input, "1-------") then next_state <= s110011; output <= "0000001000011011001";
end if;
when s110011 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1-------") then next_state <= s000111; output <= "0000001010001010000";
end if;
when s000111 =>
if std_match(input, "0----0--") then next_state <= s000000; output <= "0000001000011011010";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001000011011110";
elsif std_match(input, "1----1--") then next_state <= s101011; output <= "0000001000011011110";
elsif std_match(input, "1----0--") then next_state <= s101011; output <= "0000001000011011010";
end if;
when s101011 =>
if std_match(input, "1-------") then next_state <= s001111; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s001111 =>
if std_match(input, "1----0--") then next_state <= s000100; output <= "0001000000101011011";
elsif std_match(input, "1----1--") then next_state <= s000100; output <= "0001000000101011111";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0001000000101011111";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0001000000101011011";
end if;
when s010110 =>
if std_match(input, "1----1--") then next_state <= s111100; output <= "0100001010010010111";
elsif std_match(input, "1-11-0--") then next_state <= s110011; output <= "0000011000011011001";
elsif std_match(input, "1-01-0--") then next_state <= s101100; output <= "0000010001001101000";
elsif std_match(input, "1-00-0--") then next_state <= s101100; output <= "0000000000001111000";
elsif std_match(input, "1-10-0--") then next_state <= s101100; output <= "0000010000000000000";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0100001010010010111";
elsif std_match(input, "0-10-0--") then next_state <= s000000; output <= "0000010000000000000";
elsif std_match(input, "0-11-0--") then next_state <= s000000; output <= "0000011000011011001";
elsif std_match(input, "0-00-0--") then next_state <= s000000; output <= "0000000000001111000";
elsif std_match(input, "0-01-0--") then next_state <= s000000; output <= "0000010001001101000";
end if;
when s111100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001110001010000";
elsif std_match(input, "1-------") then next_state <= s100011; output <= "0000001110001010000";
end if;
when s101100 =>
if std_match(input, "1-------") then next_state <= s010110; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s010111 =>
if std_match(input, "1----0--") then next_state <= s001100; output <= "0000000000110010010";
elsif std_match(input, "1----1--") then next_state <= s001100; output <= "0000000000110010110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000110010010";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000000110010110";
end if;
when s001100 =>
if std_match(input, "1----0--") then next_state <= s010001; output <= "0000001010001010000";
elsif std_match(input, "1----1--") then next_state <= s011011; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s010001 =>
if std_match(input, "0----0--") then next_state <= s000000; output <= "0000001000011110011";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001000011110111";
elsif std_match(input, "1----1--") then next_state <= s110110; output <= "0000001000011110111";
elsif std_match(input, "1----0--") then next_state <= s110110; output <= "0000001000011110011";
end if;
when s110110 =>
if std_match(input, "1-------") then next_state <= s011111; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s011111 =>
if std_match(input, "0----11-") then next_state <= s000000; output <= "0000000000110111111";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000000000110111110";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000110111010";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000110111011";
elsif std_match(input, "1----00-") then next_state <= s101110; output <= "0000000000110111010";
elsif std_match(input, "1----01-") then next_state <= s101110; output <= "0000000000110111011";
elsif std_match(input, "1----10-") then next_state <= s101110; output <= "0000000000110111110";
elsif std_match(input, "1----11-") then next_state <= s101110; output <= "0000000000110111111";
end if;
when s101110 =>
if std_match(input, "1-------") then next_state <= s010101; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s010101 =>
if std_match(input, "1----1--") then next_state <= s111110; output <= "0000001000001111101";
elsif std_match(input, "1----0--") then next_state <= s111110; output <= "0000001000001111001";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000001000001111001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001000001111101";
end if;
when s111110 =>
if std_match(input, "00--1-0-") then next_state <= s000000; output <= "1000001010001010000";
elsif std_match(input, "01--1-0-") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "0---0-0-") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "0---0-1-") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "0---1-1-") then next_state <= s000000; output <= "1000001010001010000";
elsif std_match(input, "10--0---") then next_state <= s000011; output <= "0000001010001010000";
elsif std_match(input, "10--1--1") then next_state <= s111010; output <= "1000001010001010000";
elsif std_match(input, "10--1--0") then next_state <= s011010; output <= "1000001010001010000";
elsif std_match(input, "11--1-11") then next_state <= s111010; output <= "1000001010001010000";
elsif std_match(input, "11--0-11") then next_state <= s000011; output <= "0000001010001010000";
elsif std_match(input, "11--1-10") then next_state <= s011010; output <= "1000001010001010000";
elsif std_match(input, "11--0-10") then next_state <= s000011; output <= "0000001010001010000";
elsif std_match(input, "11--1-00") then next_state <= s111011; output <= "0000001010001010000";
elsif std_match(input, "11--1-01") then next_state <= s000011; output <= "0000001010001010000";
elsif std_match(input, "11--0-0-") then next_state <= s000011; output <= "0000001010001010000";
end if;
when s000011 =>
if std_match(input, "1----0-1") then next_state <= s001110; output <= "0000001010010010011";
elsif std_match(input, "1----0-0") then next_state <= s001110; output <= "0000001010010110011";
elsif std_match(input, "1----1--") then next_state <= s001110; output <= "0000001010010010111";
elsif std_match(input, "0----0-1") then next_state <= s000000; output <= "0000001010010010011";
elsif std_match(input, "0----1-1") then next_state <= s000000; output <= "0000001010010010111";
elsif std_match(input, "0----0-0") then next_state <= s000000; output <= "0000001010010110011";
elsif std_match(input, "0----1-0") then next_state <= s000000; output <= "0000001010010010111";
end if;
when s111010 =>
if std_match(input, "1-------") then next_state <= s100000; output <= "0000001010010010011";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010010010011";
end if;
when s100000 =>
if std_match(input, "00--1---") then next_state <= s000000; output <= "0000101010001010000";
elsif std_match(input, "01--1---") then next_state <= s000000; output <= "0000001110001010000";
elsif std_match(input, "11--1---") then next_state <= s101000; output <= "0000001110001010000";
elsif std_match(input, "10--1---") then next_state <= s110000; output <= "0000101010001010000";
elsif std_match(input, "11--0---") then next_state <= s101000; output <= "0000001110001010000";
elsif std_match(input, "01--0---") then next_state <= s000000; output <= "0000001110001010000";
elsif std_match(input, "00--0---") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "10--0---") then next_state <= s011110; output <= "0000001010001010000";
end if;
when s101000 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001010000110011";
elsif std_match(input, "1-------") then next_state <= s010010; output <= "0000001010000110011";
end if;
when s010010 =>
if std_match(input, "1---0---") then next_state <= s011110; output <= "0000001010001010000";
elsif std_match(input, "0---0---") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "0---1---") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1---1---") then next_state <= s001010; output <= "0000001010001010000";
end if;
when s011110 =>
if std_match(input, "0-00-00-") then next_state <= s000000; output <= "0000000000001111000";
elsif std_match(input, "0-00-01-") then next_state <= s000000; output <= "0000000000001111001";
elsif std_match(input, "0-10-01-") then next_state <= s000000; output <= "0000010000000000001";
elsif std_match(input, "0-10-00-") then next_state <= s000000; output <= "0000010000000000000";
elsif std_match(input, "0--0-1--") then next_state <= s000000; output <= "0000001010010010111";
elsif std_match(input, "0--1-1--") then next_state <= s000000; output <= "0000001010010010111";
elsif std_match(input, "0-11-0--") then next_state <= s000000; output <= "0000011000011011001";
elsif std_match(input, "0-01-00-") then next_state <= s000000; output <= "0000010001001101000";
elsif std_match(input, "0-01-01-") then next_state <= s000000; output <= "0000010001001101001";
elsif std_match(input, "1-0--1--") then next_state <= s100000; output <= "0000001010010010111";
elsif std_match(input, "1-00-00-") then next_state <= s000010; output <= "0000000000001111000";
elsif std_match(input, "1-00-01-") then next_state <= s000010; output <= "0000000000001111001";
elsif std_match(input, "1-01-01-") then next_state <= s000010; output <= "0000010001001101001";
elsif std_match(input, "1-01-00-") then next_state <= s000010; output <= "0000010001001101000";
elsif std_match(input, "1-10-1--") then next_state <= s100000; output <= "0000001010010010111";
elsif std_match(input, "1-10-01-") then next_state <= s000010; output <= "0000010000000000001";
elsif std_match(input, "1-10-00-") then next_state <= s000010; output <= "0000010000000000000";
elsif std_match(input, "1-11-1--") then next_state <= s100000; output <= "0000001010010010111";
elsif std_match(input, "1-11-0--") then next_state <= s110011; output <= "0000011000011011001";
end if;
when s000010 =>
if std_match(input, "1----0--") then next_state <= s011110; output <= "0001001010001010000";
elsif std_match(input, "1----1--") then next_state <= s011110; output <= "0000001010001010000";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0001001010001010000";
end if;
when s001010 =>
if std_match(input, "0----0--") then next_state <= s000000; output <= "0000001010100010001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001000011011101";
elsif std_match(input, "1----0--") then next_state <= s111000; output <= "0000001010100010001";
elsif std_match(input, "1----1--") then next_state <= s100100; output <= "0000001000011011101";
end if;
when s111000 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1---01--") then next_state <= s001010; output <= "0000001010001010000";
elsif std_match(input, "1---00--") then next_state <= s001000; output <= "0000001010001010000";
elsif std_match(input, "1---1---") then next_state <= s001000; output <= "0000001010001010000";
end if;
when s001000 =>
if std_match(input, "1----0--") then next_state <= s100100; output <= "0000001000011011001";
elsif std_match(input, "1----1--") then next_state <= s100100; output <= "0000001000011011101";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000001000011011001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001000011011101";
end if;
when s100100 =>
if std_match(input, "1-------") then next_state <= s001011; output <= "0001001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0001001010001010000";
end if;
when s001011 =>
if std_match(input, "1----0--") then next_state <= s110100; output <= "0000001000011011010";
elsif std_match(input, "1----1--") then next_state <= s110100; output <= "0000001000011011110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000001000011011010";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001000011011110";
end if;
when s110100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0001001010001010000";
elsif std_match(input, "1-------") then next_state <= s011011; output <= "0001001010001010000";
end if;
when s011011 =>
if std_match(input, "0----10-") then next_state <= s000000; output <= "0000001000011010111";
elsif std_match(input, "0----11-") then next_state <= s000000; output <= "0000001000011010110";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000001000011010010";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000001000011010011";
elsif std_match(input, "1----01-") then next_state <= s100110; output <= "0000001000011010010";
elsif std_match(input, "1----00-") then next_state <= s100110; output <= "0000001000011010011";
elsif std_match(input, "1----11-") then next_state <= s100110; output <= "0000001000011010110";
elsif std_match(input, "1----10-") then next_state <= s100110; output <= "0000001000011010111";
end if;
when s100110 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1-------") then next_state <= s011101; output <= "0000001010001010000";
end if;
when s011101 =>
if std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000110011000";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000110011001";
elsif std_match(input, "0----11-") then next_state <= s000000; output <= "0000000000110011101";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000000000110011100";
elsif std_match(input, "1----11-") then next_state <= s101110; output <= "0000000000110011101";
elsif std_match(input, "1----10-") then next_state <= s101110; output <= "0000000000110011100";
elsif std_match(input, "1----00-") then next_state <= s101110; output <= "0000000000110011000";
elsif std_match(input, "1----01-") then next_state <= s101110; output <= "0000000000110011001";
end if;
when s110000 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001000001111001";
elsif std_match(input, "1-------") then next_state <= s000110; output <= "0000001000001111001";
end if;
when s000110 =>
if std_match(input, "0----0--") then next_state <= s000000; output <= "0001001010001010000";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0100001010001010000";
elsif std_match(input, "1---01--") then next_state <= s011000; output <= "0100001010001010000";
elsif std_match(input, "1---00--") then next_state <= s011000; output <= "0001001010001010000";
elsif std_match(input, "1---11--") then next_state <= s011110; output <= "0100001010001010000";
elsif std_match(input, "1---10--") then next_state <= s011110; output <= "0001001010001010000";
end if;
when s011010 =>
if std_match(input, "1----1--") then next_state <= s100000; output <= "0000001010010010111";
elsif std_match(input, "1----00-") then next_state <= s110010; output <= "0000001010100010001";
elsif std_match(input, "1----01-") then next_state <= s110010; output <= "0000001010100010000";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000001010100010001";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000001010100010000";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001010010010111";
end if;
when s110010 =>
if std_match(input, "1----00-") then next_state <= s011100; output <= "0000001010001010000";
elsif std_match(input, "1----01-") then next_state <= s011010; output <= "0000001010001010000";
elsif std_match(input, "1----10-") then next_state <= s011010; output <= "0000001010001010000";
elsif std_match(input, "1----11-") then next_state <= s011100; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s011100 =>
if std_match(input, "0----11-") then next_state <= s000000; output <= "0000001000111010111";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000001000111010110";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000001000111010011";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000001000111010010";
elsif std_match(input, "1----10-") then next_state <= s101010; output <= "0000001000111010110";
elsif std_match(input, "1----11-") then next_state <= s101010; output <= "0000001000111010111";
elsif std_match(input, "1----01-") then next_state <= s100010; output <= "0000001000111010011";
elsif std_match(input, "1----00-") then next_state <= s100010; output <= "0000001000111010010";
end if;
when s101010 =>
if std_match(input, "1-------") then next_state <= s111010; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s100010 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1-------") then next_state <= s011010; output <= "0000001010001010000";
end if;
when s111011 =>
if std_match(input, "1----0--") then next_state <= s100111; output <= "0000001010010110011";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000001010010110011";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0010101010010010111";
elsif std_match(input, "1----1--") then next_state <= s010000; output <= "0010101010010010111";
end if;
when s100111 =>
if std_match(input, "1-------") then next_state <= s111011; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s010000 =>
if std_match(input, "--------") then next_state <= s000000; output <= "0000001000011010010";
end if;
when others => next_state <= "------"; output <= "-------------------";
end case;
end process;
end behaviour;
| agpl-3.0 | c5ff5d1e0b309118039647b5932991b0 | 0.625795 | 3.832866 | false | false | false | false |
ibm2030/IBM2030 | FMD2030_5-07A2.vhd | 1 | 7,476 | ---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-07A2.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- Check Register Indicators
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY ChkRegInd IS
port
(
-- Inputs
LAMP_TEST : IN STD_LOGIC; -- 04A
GT_CA_TO_W_REG : IN STD_LOGIC; -- 02B
USE_ALT_CA_DECODER : IN STD_LOGIC; -- 02B
USE_BASIC_CA_DECO : IN STD_LOGIC; -- 02B
CA_SALS : IN STD_LOGIC_VECTOR(0 to 3); -- 01C
ROS_SCAN : IN STD_LOGIC; -- 03C
MACH_CHK_PULSE : IN STD_LOGIC; -- 03A
GT_D_REG_TO_A_BUS : IN STD_LOGIC; -- 05C
MACH_RST_SW : IN STD_LOGIC; -- 03D
ANY_PRIORITY_LCH : IN STD_LOGIC; -- 03A
SET_IND_ROSAR : IN STD_LOGIC; -- 01A
MACH_RST_6 : IN STD_LOGIC; -- 03D
WX_CHK : IN STD_LOGIC; -- 01A
A_REG_PC,B_REG_PC : IN STD_LOGIC; -- 06A
N2ND_ERROR_STOP : IN STD_LOGIC; -- 03C
ALLOW_WRITE : IN STD_LOGIC; -- 03D
CTRL_REG_CHK : IN STD_LOGIC; -- 01A
SALS_PC : IN STD_LOGIC; -- 01A
R_REG_PC : IN STD_LOGIC; -- 05A
ALU_CHK : IN STD_LOGIC; -- 06A
CHK_SW_PROC_SW : IN STD_LOGIC; -- 04A
SUPPR_MACH_CHK_TRAP : IN STD_LOGIC; -- 03A
CPU_WR_IN_R_REG : IN STD_LOGIC; -- 03D
GT_Q_REG_TO_A_BUS : IN STD_LOGIC; -- 07C
STACK_PC : IN STD_LOGIC; -- 08B
MEM_PROT_REQUEST : IN STD_LOGIC; -- 03A
SEL_CHNL_CHK : IN STD_LOGIC; -- 11A
MACH_CHK_RST : IN STD_LOGIC; -- 04A
AK_SAL_BIT : IN STD_LOGIC; -- 01C
CK_SALS : IN STD_LOGIC_VECTOR(0 to 3); -- 01C
MN_PC : IN STD_LOGIC;
N1401_MODE : IN STD_LOGIC;
-- Outputs
SUPPR_A_REG_CHK : OUT STD_LOGIC; -- 03A
ALLOW_PC_SALS : OUT STD_LOGIC; -- 01B
MN_REG_CHK_SMPLD : OUT STD_LOGIC; -- 06C
FIRST_MACH_CHK,FIRST_MACH_CHK_REQ : OUT STD_LOGIC; -- 03A,03C
ANY_MACH_CHK : OUT STD_LOGIC; -- 01A,03C,04A
IND_MC_A_REG,IND_MC_B_REG,IND_MC_STOR_ADDR,IND_MC_CTRL_REG,IND_MC_ROS_SALS,IND_MC_ROS_ADDR,IND_MC_STOR_DATA,IND_MC_ALU : OUT STD_LOGIC;
MC : OUT STD_LOGIC_VECTOR(0 to 7);
-- Clocks
T1,T2,T3,T4 : IN STD_LOGIC;
P1 : IN STD_LOGIC;
clk : IN STD_LOGIC
);
END ChkRegInd;
ARCHITECTURE FMD OF ChkRegInd IS
signal W_REG_CHK : STD_LOGIC;
signal RST_MACH_CHK : STD_LOGIC;
signal MC_REG : STD_LOGIC_VECTOR(0 to 8);
signal SETMC : STD_LOGIC_VECTOR(0 to 7);
signal SET1ST : STD_LOGIC;
signal CAX1X1,CA0X11,CAX11X,CA1XXX : STD_LOGIC;
signal N_ALLOW_PC_SALS : STD_LOGIC;
signal ALLOW_A_REG_CHK : STD_LOGIC;
signal sSUPPR_A_REG_CHK : STD_LOGIC;
signal sALLOW_PC_SALS : STD_LOGIC;
signal sMN_REG_CHK_SMPLD : STD_LOGIC;
signal sANY_MACH_CHK : STD_LOGIC;
signal sMC : STD_LOGIC_VECTOR(0 to 7);
signal SUPR_A_REG_CHK_Set,SUPR_A_REG_CHK_Reset,ALLW_A_REG_CHK_Set,ALLW_A_REG_CHK_Reset,NOT_ALLOW_PC_SALS_Set : STD_LOGIC;
signal REG_MC_Set,REG_MC_Reset : STD_LOGIC_VECTOR(0 to 8);
BEGIN
-- Fig 5-07A
SUPR_A_REG_CHK_Set <= MACH_CHK_PULSE and T2;
SUPR_A_REG_CHK_Reset <= (GT_D_REG_TO_A_BUS and T1) or MACH_RST_SW;
SUPR_A_REG_CHK: FLE port map(SUPR_A_REG_CHK_Set,SUPR_A_REG_CHK_Reset,clk,sSUPPR_A_REG_CHK); -- AB3H3,AB3J4,AB3H4
SUPPR_A_REG_CHK <= sSUPPR_A_REG_CHK;
CAX1X1 <= CA_SALS(1) and CA_SALS(3); -- AB3G3
CA0X11 <= not CA_SALS(0) and CA_SALS(2) and CA_SALS(3); -- AB3J5
CAX11X <= CA_SALS(1) and CA_SALS(2); -- AB3F3
CA1XXX <= CA_SALS(0); -- AB3K5
-- MDM has USE_ALT with CAX1X1 which would check the Q reg which has no valid parity. Using USE_BASIC checks H reg instead
ALLW_A_REG_CHK_Set <= (P1 and USE_BASIC_CA_DECO and not GT_CA_TO_W_REG and CAX1X1) or -- AB3G3 ?? MDM has USE_ALT here ??
(USE_ALT_CA_DECODER and not GT_CA_TO_W_REG and CA0X11 and P1) or -- AB3J5
(CAX11X and not GT_CA_TO_W_REG and USE_BASIC_CA_DECO and P1) or -- AB3F3
(USE_BASIC_CA_DECO and CA1XXX and P1); -- AB3K5
ALLW_A_REG_CHK_Reset <= T1 or ROS_SCAN or sSUPPR_A_REG_CHK or ANY_PRIORITY_LCH;
ALLW_A_REG_CHK: entity work.FLL port map(ALLW_A_REG_CHK_Set,ALLW_A_REG_CHK_Reset,ALLOW_A_REG_CHK); -- AB3K5,AB3B6,AB3J4
NOT_ALLOW_PC_SALS_Set <= (SET_IND_ROSAR and T4) or MACH_RST_6;
NOT_ALLOW_PC_SALS: entity work.FLL port map(NOT_ALLOW_PC_SALS_Set,not T3,N_ALLOW_PC_SALS); -- AB3F6,AB3D7,AB3E5
sALLOW_PC_SALS <= not N_ALLOW_PC_SALS;
ALLOW_PC_SALS <= sALLOW_PC_SALS;
W_REG_CHK <= WX_CHK and not MACH_CHK_PULSE; -- AB3F6,AB3B6
RST_MACH_CHK <= T1 and AK_SAL_BIT when CK_SALS="1011" else '0'; -- AB3E7,AB3H5
SETMC(0) <= ALLOW_A_REG_CHK and A_REG_PC and T3; -- AB3G4
SETMC(1) <= B_REG_PC and not N2ND_ERROR_STOP and T3; -- AB3G4
sMN_REG_CHK_SMPLD <= MN_PC and ALLOW_WRITE and T3; -- AB3G4
MN_REG_CHK_SMPLD <= sMN_REG_CHK_SMPLD;
SETMC(2) <= sMN_REG_CHK_SMPLD; -- AB3G4
SETMC(3) <= sALLOW_PC_SALS and T2 and CTRL_REG_CHK; -- AB3G5
SETMC(4) <= SALS_PC and sALLOW_PC_SALS and T2; -- AB3G5
SETMC(5) <= T2 and W_REG_CHK; -- AB3G5
SETMC(6) <= (T2 and R_REG_PC and (CPU_WR_IN_R_REG or N1401_MODE)) or
((not N2ND_ERROR_STOP or (GT_Q_REG_TO_A_BUS and not GT_CA_TO_W_REG)) and T2 and STACK_PC and MEM_PROT_REQUEST); -- AB3G6
SETMC(7) <= ALU_CHK and T4; -- AB3G6
sANY_MACH_CHK <= SETMC(0) or SETMC(1) or SETMC(2) or SETMC(3) or SETMC(4) or SETMC(5) or SETMC(6) or SETMC(7) or SEL_CHNL_CHK; -- AB3G4,AB3G5,AB3J4,AB3D7,AB3F4
ANY_MACH_CHK <= sANY_MACH_CHK;
SET1ST <= CHK_SW_PROC_SW and not SUPPR_MACH_CHK_TRAP and sANY_MACH_CHK; -- AB3G6
REG_MC_Set <= SETMC & SET1ST;
REG_MC_Reset <= (0 to 7 => MACH_CHK_RST or RST_MACH_CHK,8 => (T1 and MACH_CHK_PULSE) or MACH_CHK_RST or RST_MACH_CHK); -- AB3G7,AB3H6-removed??
REG_MC: FLVL port map(REG_MC_Set,REG_MC_Reset,MC_REG); -- AB3G4,AB3G5,AB3G6
sMC <= MC_REG(0 to 7);
MC <= sMC;
FIRST_MACH_CHK <= MC_REG(8);
FIRST_MACH_CHK_REQ <= MC_REG(8); -- AB3F6
IND_MC_A_REG <= sMC(0) or LAMP_TEST;
IND_MC_B_REG <= sMC(1) or LAMP_TEST;
IND_MC_STOR_ADDR <= sMC(2) or LAMP_TEST;
IND_MC_CTRL_REG <= sMC(3) or LAMP_TEST;
IND_MC_ROS_SALS <= sMC(4) or LAMP_TEST;
IND_MC_ROS_ADDR <= sMC(5) or LAMP_TEST;
IND_MC_STOR_DATA <= sMC(6) or LAMP_TEST;
IND_MC_ALU <= sMC(7) or LAMP_TEST;
end FMD;
| gpl-3.0 | fcc4851bfd234fbe7f593a2b04216f33 | 0.640717 | 2.482896 | false | false | false | false |
ibm2030/IBM2030 | 7seg_LEDs.vhd | 1 | 3,697 | ---------------------------------------------------------------------------
-- Copyright © 2015 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: 7seg_LEDs.vhd
-- Creation Date: 19:50:00 30/11/2015
-- Description:
-- 360/30 7-segment LED drivers
-- This drives the 7-segment display on the Digilent S3BOARD
--
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2015-11-30
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity segment_LEDs is
Generic (
Clock_divider : integer := 50000 -- Default for 50MHz clock is 1kHz
);
Port ( -- Input vector
number : in std_logic_vector(15 downto 0) := (others=>'0'); -- 15-13=LHS 3-0=RHS
dp : in std_logic_vector(3 downto 0) := (others=>'0'); -- 1 for ON
-- Other inputs
clk : in STD_LOGIC; -- 50MHz
-- Driver outputs
anodes : out std_logic_vector(3 downto 0); -- 3=LHS 0=RHS
cathodes : out std_logic_vector(7 downto 0) -- 7=dp 6=g 5=f 4=e 3=d 2=c 1=b 0=a
);
end segment_LEDS;
architecture Behavioral of segment_LEDS is
signal clk_out : std_logic := '0';
type segmentArrayType is array(0 to 15) of std_logic_vector(6 downto 0);
signal segments : segmentArrayType := (
0 => "1000000",
1 => "1111001",
2 => "0100100",
3 => "0110000",
4 => "0011001",
5 => "0010010",
6 => "0000010",
7 => "1111000",
8 => "0000000",
9 => "0010000",
10 => "0001000",
11 => "0000011",
12 => "1000110",
13 => "0100001",
14 => "0000110",
15 => "0001110"
);
type digitArrayType is array(0 to 3) of std_logic_vector(3 downto 0);
signal digits : digitArrayType := (
0 => "1110",
1 => "1101",
2 => "1011",
3 => "0111"
);
signal digit : integer range 0 to 3 := 0;
begin
gen_clk : process (clk) is
variable divider : integer := Clock_divider;
begin
if rising_edge(clk) then
if (divider=0) then
divider := Clock_divider;
clk_out <= not clk_out;
else
divider := divider - 1;
end if;
end if;
end process;
scan : process (clk_out) is
begin
if rising_edge(clk_out) then
if (digit=3) then
digit <= 0;
else
digit <= digit + 1;
end if;
anodes <= digits(digit);
cathodes <= not dp(digit) & segments(to_integer(unsigned(number(digit*4+3 downto digit*4))));
end if;
end process;
end behavioral;
| gpl-3.0 | a4695f76fff18479b7b73b73ee83999e | 0.615905 | 3.260141 | false | false | false | false |
chastell/art-decomp | kiss/shiftreg_rnd.vhd | 1 | 2,558 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity shiftreg_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(0 downto 0)
);
end shiftreg_rnd;
architecture behaviour of shiftreg_rnd is
constant st0: std_logic_vector(2 downto 0) := "101";
constant st4: std_logic_vector(2 downto 0) := "010";
constant st1: std_logic_vector(2 downto 0) := "011";
constant st2: std_logic_vector(2 downto 0) := "110";
constant st5: std_logic_vector(2 downto 0) := "111";
constant st3: std_logic_vector(2 downto 0) := "001";
constant st6: std_logic_vector(2 downto 0) := "000";
constant st7: std_logic_vector(2 downto 0) := "100";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "0") then next_state <= st0; output <= "0";
elsif std_match(input, "1") then next_state <= st4; output <= "0";
end if;
when st1 =>
if std_match(input, "0") then next_state <= st0; output <= "1";
elsif std_match(input, "1") then next_state <= st4; output <= "1";
end if;
when st2 =>
if std_match(input, "0") then next_state <= st1; output <= "0";
elsif std_match(input, "1") then next_state <= st5; output <= "0";
end if;
when st3 =>
if std_match(input, "0") then next_state <= st1; output <= "1";
elsif std_match(input, "1") then next_state <= st5; output <= "1";
end if;
when st4 =>
if std_match(input, "0") then next_state <= st2; output <= "0";
elsif std_match(input, "1") then next_state <= st6; output <= "0";
end if;
when st5 =>
if std_match(input, "0") then next_state <= st2; output <= "1";
elsif std_match(input, "1") then next_state <= st6; output <= "1";
end if;
when st6 =>
if std_match(input, "0") then next_state <= st3; output <= "0";
elsif std_match(input, "1") then next_state <= st7; output <= "0";
end if;
when st7 =>
if std_match(input, "0") then next_state <= st3; output <= "1";
elsif std_match(input, "1") then next_state <= st7; output <= "1";
end if;
when others => next_state <= "---"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 | 4b7b21a253080a9782b72630d8a98ace | 0.577404 | 3.193508 | false | false | false | false |
ibm2030/IBM2030 | FMD2030_5-10B.vhd | 1 | 12,682 | ---------------------------------------------------------------------------
-- Copyright 2012 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-10B.vhd
-- Creation Date:
-- Description:
-- 1050 Typewriter Console tag signal generation
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2012-04-07
-- Initial release
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
use work.FLL;
ENTITY n1050_TAGS IS
port
(
-- Inputs
RD_OR_RD_INQ : IN STD_LOGIC; -- 09CC5
Y_TIME : IN STD_LOGIC; -- 10AXX
RD_INLK_RST : IN STD_LOGIC; -- 10DC5
WRITE_LCH_RST : IN STD_LOGIC; -- 09CE2
PCH_1_CLUTCH : IN STD_LOGIC; -- 10DD5
TT2_POS_END : IN STD_LOGIC; -- 09CB5
WRITE_LCH : IN STD_LOGIC; -- 09CD2
Z_TIME : IN STD_LOGIC; -- 10AXX
CE_DATA_ENTER_GT : IN STD_LOGIC; -- 10DA2
CE_TA_DECODE : IN STD_LOGIC; -- 10DA1
GT_1050_TAGS_OUT : IN STD_LOGIC; -- 10CE2
RECYCLE_RESET : IN STD_LOGIC; -- 04CA5
-- CE_MODE : IN STD_LOGIC; -- ---A6
CE_RESET : IN STD_LOGIC; -- 10DC2
RUN : IN STD_LOGIC; -- 09CE6
TT3_POS_1050_OPER : IN STD_LOGIC; -- 10DD4
TAGS_OUT_BUS : IN STD_LOGIC_VECTOR(0 to 7); -- 10CD1
n1050_CE_MODE : IN STD_LOGIC; -- 10DB3
P_1050_SEL_IN : IN STD_LOGIC; -- 08DC1
P_1050_SEL_OUT : IN STD_LOGIC; -- 08DD6
MPX_OPN_LCH_GT : IN STD_LOGIC; -- 08CE3
CK_SAL_P_BIT : IN STD_LOGIC; -- 01CXX
EXIT_MPLX_SHARE : IN STD_LOGIC; -- 10DB3
ADDR_OUT : IN STD_LOGIC; -- 08DA5
RD_SHARE_REQ : IN STD_LOGIC; -- 09CC6
RD_SHARE_REQ_LCH : IN STD_LOGIC; -- 09CC6
SUPPRESS_OUT : IN STD_LOGIC; -- 08DD6
WR_SHARE_REQ : IN STD_LOGIC; -- 10CA6
CE_SEL_O : IN STD_LOGIC; -- 10DB2
INTRV_REQ : IN STD_LOGIC; -- 10CD6
RDY_SHARE : IN STD_LOGIC; -- 10CE6
UNGATED_RUN : IN STD_LOGIC; -- 09CE6
REQUEST_KEY : IN STD_LOGIC; -- 10DE5
-- Outputs
n1050_RST_LCH : OUT STD_LOGIC; -- 10DF2 09CD1 10CA5 09CE5
HOME_RDR_START_LCH : OUT STD_LOGIC; -- 09CE4 09CE1 10DE2
HOME_RDR_STOP : OUT STD_LOGIC; -- 10DC5
PROCEED_LCH : OUT STD_LOGIC; -- 09CE4 10CC2 10DE2
MICRO_SHARE_LCH : OUT STD_LOGIC; -- 10DE2
RDR_ON_LCH : OUT STD_LOGIC; -- 09CE4 10DE2 09CE1
TA_REG_POS_4 : OUT STD_LOGIC; -- 10DE2
AUDIBLE_ALARM : OUT STD_LOGIC; -- 14AXX
CR_LF : OUT STD_LOGIC; -- 10AC1 10DE2
TA_REG_POS_6_ATTENTION_RST : OUT STD_LOGIC; -- ---D4 10DE2 10CE5
CPU_LINES_TO_1050 : OUT CONN_1050; -- 10DE3
SHARE_REQ_RST : OUT STD_LOGIC; -- 09CC5 10CE4 10CA5
T_REQUEST : OUT STD_LOGIC; -- 07BD3 06BA3 07BB3
CPU_REQUEST_IN : OUT STD_LOGIC; -- 10DE3
n1050_OP_IN : OUT STD_LOGIC; -- 08DD4 10CA4
n1050_REQ_IN : OUT STD_LOGIC; -- 08DD2
TT6_POS_ATTN : OUT STD_LOGIC; -- 10DC4 04AB6
n1050_INSTALLED : OUT STD_LOGIC; -- 08DC1
n1050_SEL_O : OUT STD_LOGIC; -- 08DD5
TA_REG_SET : OUT STD_LOGIC; -- 10CB4
RD_CLK_INLK_LCH : OUT STD_LOGIC; -- 10AC1
RESTORE : OUT STD_LOGIC; -- 10CD4
RST_ATTACH : OUT STD_LOGIC; -- 09C 10A 10C
DEBUG : INOUT DEBUG_BUS;
-- Clocks
clk : IN STD_LOGIC;
Clock1ms : IN STD_LOGIC;
Clock60Hz : IN STD_LOGIC;
T1,T2,T3,T4 : IN STD_LOGIC;
P1,P2,P3,P4 : IN STD_LOGIC
);
END n1050_TAGS;
ARCHITECTURE FMD OF n1050_TAGS IS
signal RD_CLK_INLK_SET, sRD_CLK_INLK_LCH : STD_LOGIC;
signal n1050_RST_RESET, n1050_RST_SET, s1050_RST_LCH : STD_LOGIC;
signal sRST_ATTACH : STD_LOGIC;
signal sTA_REG_SET, TA_REG_RST : STD_LOGIC;
signal SET_HOME_RDR_STT : STD_LOGIC;
signal sHOME_RDR_START_LCH : STD_LOGIC;
signal SET_PROCEED : STD_LOGIC;
signal sPROCEED_LCH : STD_LOGIC;
signal MICRO_SHARE_REQ : STD_LOGIC;
signal SET_MICRO_SHARE : STD_LOGIC;
signal sMICRO_SHARE_LCH : STD_LOGIC;
signal SET_RDR_2 : STD_LOGIC;
signal sRDR_ON_LCH : STD_LOGIC;
signal MS5000_IN : STD_LOGIC;
signal sTA_REG_POS_4 : STD_LOGIC;
signal MS1000_IN : STD_LOGIC;
signal sCR_LF : STD_LOGIC;
signal sTA_REG_POS_6_ATTENTION_RST : STD_LOGIC;
signal n1050_SEL_OUT : STD_LOGIC;
signal n1050_SEL_IN : STD_LOGIC;
signal SEL_O_DLY : STD_LOGIC;
signal SET_SEL_O_DET, RESET_SEL_O_DET : STD_LOGIC;
signal SEL_O_DET : STD_LOGIC;
signal SET_1050_OP_IN, RESET_1050_OP_IN : STD_LOGIC;
signal sn1050_OP_IN : STD_LOGIC;
signal SET_SEL_O_DLY, RESET_SEL_O_DLY : STD_LOGIC;
signal MPX_LCH_OFF : STD_LOGIC;
signal CPU_SEL_O_OR_SEL_IN : STD_LOGIC;
signal SET_1050_EXIT_SHARE_REQ : STD_LOGIC;
signal n1050_EXIT_SHARE_REQ : STD_LOGIC;
signal sCPU_REQUEST_IN : STD_LOGIC;
signal SET_PREPARE_TO_SHARE, RESET_PREPARE_TO_SHARE : STD_LOGIC;
signal PREPARE_TO_SHARE : STD_LOGIC;
signal SET_ATTN_INTLK, RESET_ATTN_INTLK : STD_LOGIC;
signal ATTN_INTLK : STD_LOGIC := '1';
signal SS20_IN, SS20 : STD_LOGIC;
signal SET_ATTN,RESET_ATTN : STD_LOGIC;
signal sTT6_POS_ATTN : STD_LOGIC := '0';
signal sRESTORE : STD_LOGIC;
BEGIN
-- Fig 5-10B
RD_CLK_INLK_SET <= RD_OR_RD_INQ and Y_TIME; -- AC3E3
RD_CLK_INLK: entity FLL port map(RD_CLK_INLK_SET,RD_INLK_RST,sRD_CLK_INLK_LCH); -- AC3E3, AC3F2
RD_CLK_INLK_LCH <= sRD_CLK_INLK_LCH;
n1050_RST_RESET <= not sRD_CLK_INLK_LCH and not WRITE_LCH_RST; -- AC2J5
n1050_RST_SET <= TAGS_OUT_BUS(7) and sTA_REG_SET; -- AC2K5
n1050_RST : entity FLL port map(n1050_RST_SET, n1050_RST_RESET, s1050_RST_LCH); -- AC2K5 AC2E2
n1050_RST_LCH <= s1050_RST_LCH;
CPU_LINES_TO_1050.n1050_RST_LCH <= s1050_RST_LCH;
CPU_LINES_TO_1050.n1050_RESET <= ((((sRD_CLK_INLK_LCH and not PCH_1_CLUTCH) or (WRITE_LCH and Z_TIME)) and s1050_RST_LCH) or sRST_ATTACH) and TT3_POS_1050_OPER; -- AC2H4 AC2G3 AC2K3 AC2K6
sTA_REG_SET <= (CE_DATA_ENTER_GT and CE_TA_DECODE) or (P3 and GT_1050_TAGS_OUT); -- AC2K3
TA_REG_SET <= sTA_REG_SET;
TA_REG_RST <= (CE_DATA_ENTER_GT and CE_TA_DECODE) or (T3 and GT_1050_TAGS_OUT) or sRST_ATTACH; -- AC2J2
sRST_ATTACH <= (RECYCLE_RESET and not n1050_CE_MODE) or CE_RESET; -- AC2H3 AC2H5 AC2K2
RST_ATTACH <= sRST_ATTACH;
MS16: SS port map(Clock1ms,16,RUN,sRESTORE); -- 16ms Single-shot AC2L2
CPU_LINES_TO_1050.RESTORE <= sRESTORE;
RESTORE <= sRESTORE;
SET_HOME_RDR_STT <= TAGS_OUT_BUS(0) and sTA_REG_SET;
HOME_RDR_STT_FL: entity FLL port map(SET_HOME_RDR_STT,TA_REG_RST,sHOME_RDR_START_LCH); -- AC2H3 AC2K4
HOME_RDR_START_LCH <= sHOME_RDR_START_LCH;
CPU_LINES_TO_1050.HOME_RDR_START <= sHOME_RDR_START_LCH and TT3_POS_1050_OPER and not sPROCEED_LCH; -- AC2L6
HOME_RDR_STOP <= TT3_POS_1050_OPER and not RUN; -- AC2K6
SET_PROCEED <= TAGS_OUT_BUS(3) and sTA_REG_SET;
PROCEED_FL: entity FLL port map(SET_PROCEED,TA_REG_RST,sPROCEED_LCH); -- AC2D6 AC2K7
PROCEED_LCH <= sPROCEED_LCH;
CPU_LINES_TO_1050.PROCEED <= sPROCEED_LCH and not RD_SHARE_REQ_LCH and not MICRO_SHARE_REQ; -- AC2K6
MICRO_SHARE_REQ <= (not SUPPRESS_OUT and sMICRO_SHARE_LCH) or (sPROCEED_LCH and sMICRO_SHARE_LCH); -- AC2K7
SET_MICRO_SHARE <= TAGS_OUT_BUS(2) and sTA_REG_SET;
MICRO_SHARE_FL: entity FLL port map(SET_MICRO_SHARE,TA_REG_RST,sMICRO_SHARE_LCH); -- AC2H3 AC2K4
MICRO_SHARE_LCH <= sMICRO_SHARE_LCH;
SET_RDR_2 <= TAGS_OUT_BUS(1) and sTA_REG_SET;
RDR_2_FL: entity FLL port map(SET_RDR_2,TA_REG_RST,sRDR_ON_LCH); -- AC2H3 AC2K4
RDR_ON_LCH <= sRDR_ON_LCH;
CPU_LINES_TO_1050.RDR_2_HOLD <= ((sRDR_ON_LCH or not RD_SHARE_REQ) and TT3_POS_1050_OPER) -- AC2J5 AC2K6
or (sRDR_ON_LCH and TT2_POS_END) or not WRITE_LCH; -- AC2L6 AC2H4
MS5000_IN <= sTA_REG_SET and TAGS_OUT_BUS(4);
MS5000: SS port map(Clock60Hz,300,MS5000_IN, sTA_REG_POS_4); -- AC2G3 AC3G6 AC3F2 5s single-shot
TA_REG_POS_4 <= sTA_REG_POS_4;
AUDIBLE_ALARM <= sTA_REG_POS_4; -- AC3H5
MS1000_IN <= (sRST_ATTACH and TT3_POS_1050_OPER) or (sTA_REG_SET and TAGS_OUT_BUS(5)); -- AC2K7
MS1000: SS port map(clk,5000000,MS1000_IN, sCR_LF); -- AC2L2 AC2D6 1s single-shot : 100ms (5000000) is enough
CR_LF <= sCR_LF;
CPU_LINES_TO_1050.CARR_RETURN_AND_LINE_FEED <= sCR_LF; -- AC2L6
sTA_REG_POS_6_ATTENTION_RST <= sTA_REG_SET and TAGS_OUT_BUS(6); -- AC2H4
TA_REG_POS_6_ATTENTION_RST <= sTA_REG_POS_6_ATTENTION_RST;
n1050_SEL_OUT <= not P_1050_SEL_IN or (n1050_CE_MODE and not sn1050_OP_IN) or (CPU_SEL_O_OR_SEL_IN and SEL_O_DLY); -- AC3E7 AC3D7
n1050_SEL_IN <= not P_1050_SEL_OUT or (n1050_CE_MODE and not sn1050_OP_IN) or (CPU_SEL_O_OR_SEL_IN and SEL_O_DLY); -- AC3D7 AC3E7
SET_SEL_O_DET <= T1 and CPU_SEL_O_OR_SEL_IN;
RESET_SEL_O_DET <= not CPU_SEL_O_OR_SEL_IN or sRST_ATTACH;
SEL_O_DET_FL: entity FLL port map(SET_SEL_O_DET,RESET_SEL_O_DET,SEL_O_DET); -- AC3E6
SET_SEL_O_DLY <= T3 and SEL_O_DET and not sn1050_OP_IN;
RESET_SEL_O_DLY <= sRST_ATTACH or not CPU_SEL_O_OR_SEL_IN;
SEL_O_DLY_FL: entity FLL port map(SET_SEL_O_DLY,RESET_SEL_O_DLY,SEL_O_DLY); -- AC3E6
SET_1050_OP_IN <= (CPU_SEL_O_OR_SEL_IN and PREPARE_TO_SHARE) or (n1050_CE_MODE and PREPARE_TO_SHARE);
RESET_1050_OP_IN <= MPX_LCH_OFF or sRST_ATTACH; -- ??
n1050_OP_IN_FL: entity FLL port map(SET_1050_OP_IN,RESET_1050_OP_IN,sn1050_OP_IN);
n1050_OP_IN <= sn1050_OP_IN;
SET_1050_EXIT_SHARE_REQ <= MPX_OPN_LCH_GT and not CK_SAL_P_BIT; -- AC3C7
n1050_EXIT_SHARE_REQ_FL : entity FLL port map(SET_1050_EXIT_SHARE_REQ,T1,n1050_EXIT_SHARE_REQ); -- AC3C6 AC3E4
SHARE_REQ_RST <= (n1050_EXIT_SHARE_REQ and not n1050_CE_MODE and T4) or EXIT_MPLX_SHARE; -- AC3E4
MPX_LCH_OFF <= EXIT_MPLX_SHARE or (n1050_EXIT_SHARE_REQ and not n1050_CE_MODE and T4); -- AC3E4
T_REQUEST <= not n1050_CE_MODE and sCPU_REQUEST_IN; -- AC3D6 ?? Not sure about sCPU_REQUEST_IN - diagram is missing this!
CPU_SEL_O_OR_SEL_IN <= n1050_SEL_OUT or n1050_SEL_IN; -- AC3D7 AC3E7 AC3B6
sCPU_REQUEST_IN <= MICRO_SHARE_REQ or RD_SHARE_REQ_LCH or WR_SHARE_REQ or INTRV_REQ or RDY_SHARE
or (not sMICRO_SHARE_LCH and UNGATED_RUN and sTT6_POS_ATTN); -- AC3F7 AC3D6
CPU_REQUEST_IN <= sCPU_REQUEST_IN;
SET_PREPARE_TO_SHARE <= (not CPU_SEL_O_OR_SEL_IN and n1050_CE_MODE and not ADDR_OUT and sCPU_REQUEST_IN) or (sCPU_REQUEST_IN and CE_SEL_O); -- AC3C7 AC3E2
RESET_PREPARE_TO_SHARE <= not sCPU_REQUEST_IN or sRST_ATTACH;
PREPARE_TO_SHARE_FL: entity FLL port map(SET_PREPARE_TO_SHARE,RESET_PREPARE_TO_SHARE,PREPARE_TO_SHARE); -- AC3E6
n1050_REQ_IN <= sCPU_REQUEST_IN and not n1050_CE_MODE;
RESET_ATTN <= sTA_REG_POS_6_ATTENTION_RST or sRST_ATTACH; -- AC3B7 AC3B4
SS20_IN <= TT3_POS_1050_OPER and REQUEST_KEY; -- AC3D6
SS20_SS: SS port map(Clock1ms,20,SS20_IN,SS20); -- 20ms single-shot AC3G6
SET_ATTN_INTLK <= RESET_ATTN or sTT6_POS_ATTN;
RESET_ATTN_INTLK <= SS20 and REQUEST_KEY; -- AC3B6 AC3C7 - Typo, AC3C7 should be N?
ATTN_INTLK_FL: entity FLL port map(SET_ATTN_INTLK,RESET_ATTN_INTLK,ATTN_INTLK); -- AC3C6 AC3D6 - ?? Not sure about this
SET_ATTN <= ATTN_INTLK and RESET_ATTN_INTLK;
-- ATTN_FL: FLL port map(SET_ATTN,RESET_ATTN,sTT6_POS_ATTN); -- AC3C6 AC3C7
sTT6_POS_ATTN <= '0'; -- ?? Temporarily disable 1050 REQ function
TT6_POS_ATTN <= sTT6_POS_ATTN;
n1050_INSTALLED <= '1'; -- AC3D7, AC3E7
n1050_SEL_O <= n1050_SEL_OUT; -- Propagate SELECT OUT untouched
with DEBUG.Selection select
DEBUG.Probe <=
sCPU_REQUEST_IN when 0,
MICRO_SHARE_REQ when 1,
RD_SHARE_REQ_LCH when 2,
WR_SHARE_REQ when 3,
INTRV_REQ when 4,
RDY_SHARE when 5,
sMICRO_SHARE_LCH when 6,
UNGATED_RUN when 7,
RD_OR_RD_INQ when 8,
sRD_CLK_INLK_LCH when 9,
WRITE_LCH when 10,
TT2_POS_END WHEN 11,
sCR_LF when 12,
Z_TIME when 13,
sRDR_ON_LCH when 14,
sPROCEED_LCH when 15,
'1' when others;
END FMD;
| gpl-3.0 | 06ba5a4114528277754fd73977fed62d | 0.662041 | 2.498916 | false | false | false | false |
chastell/art-decomp | kiss/planet_nov.vhd | 1 | 16,521 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity planet_nov is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(18 downto 0)
);
end planet_nov;
architecture behaviour of planet_nov is
constant st0: std_logic_vector(5 downto 0) := "001111";
constant st1: std_logic_vector(5 downto 0) := "000000";
constant st2: std_logic_vector(5 downto 0) := "100001";
constant st3: std_logic_vector(5 downto 0) := "110011";
constant st4: std_logic_vector(5 downto 0) := "001101";
constant st5: std_logic_vector(5 downto 0) := "111101";
constant st6: std_logic_vector(5 downto 0) := "000010";
constant st7: std_logic_vector(5 downto 0) := "111100";
constant st8: std_logic_vector(5 downto 0) := "001100";
constant st9: std_logic_vector(5 downto 0) := "111011";
constant st10: std_logic_vector(5 downto 0) := "111010";
constant st11: std_logic_vector(5 downto 0) := "000011";
constant st12: std_logic_vector(5 downto 0) := "001011";
constant st13: std_logic_vector(5 downto 0) := "111110";
constant st14: std_logic_vector(5 downto 0) := "111111";
constant st15: std_logic_vector(5 downto 0) := "000100";
constant st16: std_logic_vector(5 downto 0) := "111001";
constant st17: std_logic_vector(5 downto 0) := "001010";
constant st18: std_logic_vector(5 downto 0) := "111000";
constant st19: std_logic_vector(5 downto 0) := "110010";
constant st20: std_logic_vector(5 downto 0) := "000101";
constant st21: std_logic_vector(5 downto 0) := "101110";
constant st22: std_logic_vector(5 downto 0) := "001001";
constant st23: std_logic_vector(5 downto 0) := "000110";
constant st24: std_logic_vector(5 downto 0) := "001000";
constant st25: std_logic_vector(5 downto 0) := "000111";
constant st26: std_logic_vector(5 downto 0) := "110000";
constant st27: std_logic_vector(5 downto 0) := "010001";
constant st28: std_logic_vector(5 downto 0) := "101111";
constant st29: std_logic_vector(5 downto 0) := "000001";
constant st30: std_logic_vector(5 downto 0) := "010000";
constant st31: std_logic_vector(5 downto 0) := "110001";
constant st32: std_logic_vector(5 downto 0) := "011110";
constant st33: std_logic_vector(5 downto 0) := "101101";
constant st34: std_logic_vector(5 downto 0) := "001110";
constant st35: std_logic_vector(5 downto 0) := "010010";
constant st36: std_logic_vector(5 downto 0) := "110111";
constant st37: std_logic_vector(5 downto 0) := "101100";
constant st38: std_logic_vector(5 downto 0) := "110100";
constant st39: std_logic_vector(5 downto 0) := "010011";
constant st40: std_logic_vector(5 downto 0) := "101011";
constant st41: std_logic_vector(5 downto 0) := "010100";
constant st42: std_logic_vector(5 downto 0) := "101010";
constant st43: std_logic_vector(5 downto 0) := "110110";
constant st44: std_logic_vector(5 downto 0) := "010101";
constant st45: std_logic_vector(5 downto 0) := "110101";
constant st46: std_logic_vector(5 downto 0) := "101001";
constant st47: std_logic_vector(5 downto 0) := "010110";
signal current_state, next_state: std_logic_vector(5 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "------"; output <= "-------------------";
case current_state is
when st0 =>
if std_match(input, "-------") then next_state <= st1; output <= "001011101000000---0";
end if;
when st1 =>
if std_match(input, "----01-") then next_state <= st1; output <= "--------0000000---0";
elsif std_match(input, "----10-") then next_state <= st1; output <= "--------0100000---1";
elsif std_match(input, "----00-") then next_state <= st1; output <= "1000----1000000---1";
elsif std_match(input, "----11-") then next_state <= st2; output <= "1000111110011001000";
end if;
when st2 =>
if std_match(input, "------0") then next_state <= st3; output <= "1010010010000000000";
elsif std_match(input, "---0---") then next_state <= st3; output <= "1010010010000000000";
elsif std_match(input, "---1--1") then next_state <= st0; output <= "1010----1010010---1";
end if;
when st3 =>
if std_match(input, "11-----") then next_state <= st4; output <= "001111101000000-010";
elsif std_match(input, "10-----") then next_state <= st4; output <= "0011111110000000-10";
elsif std_match(input, "0-0-01-") then next_state <= st4; output <= "--------000010000-0";
elsif std_match(input, "0-0-10-") then next_state <= st4; output <= "--------010010000-1";
elsif std_match(input, "0-0-11-") then next_state <= st42; output <= "011011011000100---0";
elsif std_match(input, "0-0-00-") then next_state <= st4; output <= "0110----100000000-1";
elsif std_match(input, "0-1-01-") then next_state <= st4; output <= "--------00011000000";
elsif std_match(input, "0-1-10-") then next_state <= st4; output <= "--------01011000001";
elsif std_match(input, "0-1-11-") then next_state <= st42; output <= "011011011001100--00";
elsif std_match(input, "0-1-00-") then next_state <= st4; output <= "0110----10010000001";
end if;
when st4 =>
if std_match(input, "-------") then next_state <= st5; output <= "1010010010000000000";
end if;
when st5 =>
if std_match(input, "--0----") then next_state <= st6; output <= "1000011110000000001";
elsif std_match(input, "--1----") then next_state <= st6; output <= "1000011110010000001";
end if;
when st6 =>
if std_match(input, "-1----0") then next_state <= st7; output <= "101001001000000-000";
elsif std_match(input, "-110--1") then next_state <= st7; output <= "101001001000000-000";
elsif std_match(input, "-10---1") then next_state <= st41; output <= "101001001000000--00";
elsif std_match(input, "-111--1") then next_state <= st38; output <= "101001001000000--00";
elsif std_match(input, "-0-----") then next_state <= st7; output <= "1010010010000000-00";
end if;
when st7 =>
if std_match(input, "--1----") then next_state <= st8; output <= "0001101010010000000";
elsif std_match(input, "--0----") then next_state <= st8; output <= "0001101010000000000";
end if;
when st8 =>
if std_match(input, "--0----") then next_state <= st10; output <= "1010010010000000000";
elsif std_match(input, "--1----") then next_state <= st9; output <= "1010010010000000000";
end if;
when st9 =>
if std_match(input, "-11----") then next_state <= st11; output <= "001011101001000-000";
elsif std_match(input, "-01----") then next_state <= st11; output <= "0010111110010000-00";
elsif std_match(input, "-10----") then next_state <= st11; output <= "001011101000000-000";
elsif std_match(input, "-00----") then next_state <= st11; output <= "0010111110000000-00";
end if;
when st10 =>
if std_match(input, "--1----") then next_state <= st12; output <= "0010----10010000001";
elsif std_match(input, "--0----") then next_state <= st12; output <= "0010----10000000001";
end if;
when st11 =>
if std_match(input, "-------") then next_state <= st13; output <= "1010010010000000000";
end if;
when st12 =>
if std_match(input, "-------") then next_state <= st14; output <= "1010010010000000000";
end if;
when st13 =>
if std_match(input, "-11----") then next_state <= st15; output <= "010110011001000-000";
elsif std_match(input, "-10----") then next_state <= st15; output <= "010110011000000-000";
elsif std_match(input, "-01----") then next_state <= st15; output <= "0101100010010000-00";
elsif std_match(input, "-00----") then next_state <= st15; output <= "0101100010000000-00";
end if;
when st14 =>
if std_match(input, "--1----") then next_state <= st15; output <= "0101----10010000001";
elsif std_match(input, "--0----") then next_state <= st15; output <= "0101----10000000001";
end if;
when st15 =>
if std_match(input, "-------") then next_state <= st16; output <= "1010010010000000000";
end if;
when st16 =>
if std_match(input, "--1----") then next_state <= st17; output <= "0110010110010000001";
elsif std_match(input, "--0----") then next_state <= st17; output <= "0110010110000000001";
end if;
when st17 =>
if std_match(input, "---0---") then next_state <= st18; output <= "1010010010000000000";
elsif std_match(input, "01-1---") then next_state <= st19; output <= "101001001000001-0-0";
elsif std_match(input, "00-1--0") then next_state <= st19; output <= "1010010010000010--0";
elsif std_match(input, "00-1--1") then next_state <= st46; output <= "101001001000000---0";
elsif std_match(input, "11-1---") then next_state <= st24; output <= "101001001000001-000";
elsif std_match(input, "10-1--0") then next_state <= st24; output <= "1010010010000010-00";
elsif std_match(input, "10-1--1") then next_state <= st18; output <= "1010010010000000-00";
end if;
when st18 =>
if std_match(input, "--1----") then next_state <= st2; output <= "1000111110010000000";
elsif std_match(input, "0-0----") then next_state <= st2; output <= "1000----10000000001";
elsif std_match(input, "1-0----") then next_state <= st2; output <= "1000111110000000000";
end if;
when st19 =>
if std_match(input, "-10----") then next_state <= st20; output <= "100101001000000-0-0";
elsif std_match(input, "-00----") then next_state <= st20; output <= "1001010110000000--0";
elsif std_match(input, "--1----") then next_state <= st25; output <= "100011111001000--00";
end if;
when st20 =>
if std_match(input, "-10----") then next_state <= st19; output <= "101001001000000-0-0";
elsif std_match(input, "-11----") then next_state <= st21; output <= "101001001000000-0-0";
elsif std_match(input, "-01----") then next_state <= st19; output <= "1010010010000000--0";
elsif std_match(input, "-00----") then next_state <= st21; output <= "1010010010000000--0";
end if;
when st21 =>
if std_match(input, "-10----") then next_state <= st22; output <= "001111111000000-0-0";
elsif std_match(input, "-11----") then next_state <= st23; output <= "001111111001000--00";
elsif std_match(input, "-00----") then next_state <= st22; output <= "0011111010000000--0";
elsif std_match(input, "-01----") then next_state <= st23; output <= "001111101001000--00";
end if;
when st22 =>
if std_match(input, "-------") then next_state <= st19; output <= "10100100100000000-0";
end if;
when st23 =>
if std_match(input, "-------") then next_state <= st24; output <= "101001001000000--00";
end if;
when st24 =>
if std_match(input, "-------") then next_state <= st25; output <= "100011111000000--00";
end if;
when st25 =>
if std_match(input, "---0--0") then next_state <= st26; output <= "101001001000000---0";
elsif std_match(input, "---1--0") then next_state <= st28; output <= "101001001000010--00";
elsif std_match(input, "------1") then next_state <= st30; output <= "101001001000000--10";
end if;
when st26 =>
if std_match(input, "--0-01-") then next_state <= st27; output <= "--------0000100---0";
elsif std_match(input, "--0-10-") then next_state <= st27; output <= "--------0100100---1";
elsif std_match(input, "--0-00-") then next_state <= st27; output <= "0110----1000000---1";
elsif std_match(input, "--0-11-") then next_state <= st42; output <= "011011011000100---0";
elsif std_match(input, "--1----") then next_state <= st25; output <= "100011111001000--00";
end if;
when st27 =>
if std_match(input, "-------") then next_state <= st26; output <= "101001001000000---0";
end if;
when st28 =>
if std_match(input, "-------") then next_state <= st29; output <= "011001011000000--01";
end if;
when st29 =>
if std_match(input, "---1---") then next_state <= st26; output <= "101001001000000---0";
elsif std_match(input, "--10---") then next_state <= st3; output <= "1010010010000001000";
elsif std_match(input, "--00---") then next_state <= st3; output <= "1010010010000000100";
end if;
when st30 =>
if std_match(input, "-------") then next_state <= st31; output <= "100001111000000---1";
end if;
when st31 =>
if std_match(input, "---0---") then next_state <= st26; output <= "101001001000000---0";
elsif std_match(input, "---1---") then next_state <= st32; output <= "101001001000000---0";
end if;
when st32 =>
if std_match(input, "--0----") then next_state <= st33; output <= "100101011000000---0";
elsif std_match(input, "--1----") then next_state <= st35; output <= "011011011001000--00";
end if;
when st33 =>
if std_match(input, "--10---") then next_state <= st32; output <= "101001001000000---0";
elsif std_match(input, "--0----") then next_state <= st34; output <= "101001001000000---0";
elsif std_match(input, "---1---") then next_state <= st34; output <= "101001001000000---0";
end if;
when st34 =>
if std_match(input, "--1----") then next_state <= st35; output <= "011011011001000--00";
elsif std_match(input, "--0----") then next_state <= st35; output <= "011011011000000---0";
end if;
when st35 =>
if std_match(input, "-------") then next_state <= st36; output <= "101001001000000--00";
end if;
when st36 =>
if std_match(input, "--0----") then next_state <= st37; output <= "011011101000000--00";
elsif std_match(input, "--1----") then next_state <= st37; output <= "011011101001000--00";
end if;
when st37 =>
if std_match(input, "-------") then next_state <= st9; output <= "1010010010000000100";
end if;
when st38 =>
if std_match(input, "--0-01-") then next_state <= st39; output <= "--------0000100---0";
elsif std_match(input, "--0-10-") then next_state <= st39; output <= "--------0100100---1";
elsif std_match(input, "--0-11-") then next_state <= st42; output <= "011011011000100---0";
elsif std_match(input, "--0-00-") then next_state <= st39; output <= "0110----1000000---1";
elsif std_match(input, "--1----") then next_state <= st40; output <= "100011111001000--00";
end if;
when st39 =>
if std_match(input, "-------") then next_state <= st38; output <= "101001001000000---0";
end if;
when st40 =>
if std_match(input, "-------") then next_state <= st41; output <= "101001001000000--10";
end if;
when st41 =>
if std_match(input, "-------") then next_state <= st42; output <= "011011011000000---0";
end if;
when st42 =>
if std_match(input, "-------") then next_state <= st43; output <= "101001001000000--00";
end if;
when st43 =>
if std_match(input, "--0----") then next_state <= st44; output <= "011011101000000--00";
elsif std_match(input, "--1----") then next_state <= st44; output <= "011011101001000--00";
end if;
when st44 =>
if std_match(input, "-------") then next_state <= st45; output <= "101001001000000--00";
end if;
when st45 =>
if std_match(input, "--0----") then next_state <= st6; output <= "0111001110000000100";
elsif std_match(input, "--1----") then next_state <= st6; output <= "0111001110010000100";
end if;
when st46 =>
if std_match(input, "--0----") then next_state <= st47; output <= "1000----1000000---1";
elsif std_match(input, "--1----") then next_state <= st0; output <= "100011111011010---0";
end if;
when st47 =>
if std_match(input, "-------") then next_state <= st46; output <= "101001001000000---0";
end if;
when others => next_state <= "------"; output <= "-------------------";
end case;
end process;
end behaviour;
| agpl-3.0 | c825fac6686ed0698ff74a53d8988132 | 0.579384 | 3.597779 | false | false | false | false |
mike7c2/befunge_processor | befunge_alu.vhd | 1 | 4,106 |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
entity befunge_alu is
generic(
word_size : integer := 8
);
port(
clk : in std_logic;
reset : in std_logic;
a : in std_logic_vector(word_size-1 downto 0);
b : in std_logic_vector(word_size-1 downto 0);
result : out std_logic_vector(word_size-1 downto 0);
op : in std_logic_vector(2 downto 0);
en : in std_logic;
working : out std_logic
);
end befunge_alu;
architecture alu_v1 of befunge_alu is
constant zero : std_logic_vector(word_size - 1 downto 0) := (others => '0');
signal en_shadow : std_logic;
signal div_rfd : std_logic;
signal div_quotient : std_logic_vector(word_size-1 downto 0);
signal div_remainder : std_logic_vector(word_size-1 downto 0);
component div_gen_v3_0 is
port (
rfd : out STD_LOGIC;
clk : in STD_LOGIC := 'X';
dividend : in STD_LOGIC_VECTOR ( 7 downto 0 );
quotient : out STD_LOGIC_VECTOR ( 7 downto 0 );
divisor : in STD_LOGIC_VECTOR ( 7 downto 0 );
fractional : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component;
begin
divider : div_gen_v3_0
port map
(
div_rfd,
clk,
b,
div_quotient,
a,
div_remainder
);
process(reset,clk)
variable result_int : std_logic_vector((word_size * 2) -1 downto 0);
variable div_wait : integer range 0 to 12;
variable div_or_mod : std_logic;
begin
if(reset = '1') then
result <= (others => '0');
en_shadow <= '0';
working <= '0';--This flag should be used to stall the cpu for multi cycle instructions (mod and div)
div_wait := 0;
div_or_mod := '0';
else
if rising_edge(clk) then
en_shadow <= en;
if ( en = '1' and en_shadow = '0' ) then
working <= '1';
if ( op = "000" ) then -- + add
result <= std_logic_vector(Unsigned(a) + Unsigned(b));
elsif ( op = "001" ) then -- - subract
result <= std_logic_vector(Unsigned(a) - Unsigned(b));
elsif ( op = "010" ) then -- * multiply
result_int := std_logic_vector(Unsigned(a) * Unsigned(b));
result <= result_int(word_size-1 downto 0);
elsif ( op = "011" ) then -- / divide (hard!)
div_wait := 12;
div_or_mod := '0';
-- result <= std_logic_vector(Unsigned(a) / Unsigned(b));
elsif ( op = "100" ) then -- % modulue (hard!)
div_wait := 12;
div_or_mod := '1';
--result <= std_logic_vector(Unsigned(a) % Unsigned(b));
elsif ( op = "101" ) then -- ! not
if (a /= zero) then
result <= (others => '0');
else
result <= "00000001";
end if;
elsif ( op = "110" ) then -- ' greater than
result <= (others => '0');
end if;
elsif (div_wait = 1) then
if (div_or_mod = '0') then
result <= div_quotient;
else
result <= div_remainder;
end if;
div_wait := div_wait - 1;
elsif (div_wait > 0) then
div_wait := div_wait -1;
elsif (div_wait = 0) then
working <= '0';
end if;
end if;
end if;
end process;
end alu_v1; | unlicense | 424aa0c7039496cd08ec11d51b85ab8a | 0.42377 | 4.1643 | false | false | false | false |
es17m014/vhdl-counter | src/old/tb/tb_bcd_driver.vhd | 1 | 3,182 | -- --------------------------------------------------------------
-- Title : Testbench for design "BCD driver"
-- Project :
-- --------------------------------------------------------------
-- File : tb_bcd_driver.vhd
-- Author : Martin Angermair
-- Company : FH Technikum Wien
-- Last update : 2017-10-28
-- Standard : VHDL'87
-- --------------------------------------------------------------
-- Description :
-- --------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 28.10.2017 1.0 Martin Angerair init
-- --------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity tb_bcd_driver is
end tb_bcd_driver;
-------------------------------------------------------------------------------
architecture sim of tb_bcd_driver is
component seven_segment_driver
generic (g_refresh_rate : positive);
port ( clk_i : in std_logic; -- 100Mhz clock on Basys 3 FPGA board
reset_i : in std_logic; -- reset_i
dig0_i : in std_logic_vector(7 downto 0); -- first digit value
dig1_i : in std_logic_vector(7 downto 0); -- second digit value
dig2_i : in std_logic_vector(7 downto 0); -- third digit value
dig3_i : in std_logic_vector(7 downto 0); -- fourth digit value
ss_sel_o : out std_logic_vector(3 downto 0); -- 4 anode signals
ss_o : out std_logic_vector(7 downto 0));
end component;
-- component ports
signal clk_i : std_logic := '0';
signal reset_i : std_logic := '0';
signal dig0_i : std_logic_vector(7 downto 0) := "00001111";
signal dig1_i : std_logic_vector(7 downto 0) := "00110011";
signal dig2_i : std_logic_vector(7 downto 0) := "11001100";
signal dig3_i : std_logic_vector(7 downto 0) := "11110000";
signal ss_sel_o : std_logic_vector(3 downto 0);
signal ss_o : std_logic_vector(7 downto 0);
begin -- sim
-- component instantiation
DUT: seven_segment_driver generic map (
g_refresh_rate => 3)
port map (
clk_i => clk_i,
reset_i => reset_i,
dig0_i => dig0_i,
dig1_i => dig1_i,
dig2_i => dig2_i,
dig3_i => dig3_i,
ss_sel_o => ss_sel_o,
ss_o => ss_o);
-- clock generation
clk_i <= not clk_i after 5 ns;
reset_i <= '1' after 10 ns;
-- compare enable signals
-- a_en1_check: assert s_en_1_check = s_en_1_o report "Wrong enable generation by DUT_8" severity error;
-- a_en2_check: assert s_en_2_check = s_en_2_o report "Wrong enable generation by DUT_32" severity error;
end sim;
-------------------------------------------------------------------------------
configuration tb_bcd_driver_sim_cfg of tb_bcd_driver is
for sim
end for;
end tb_bcd_driver_sim_cfg;
-------------------------------------------------------------------------------
| mit | 3e5e6ba09011feb5eaead70c71a57fa0 | 0.45066 | 3.8523 | false | false | false | false |
chastell/art-decomp | kiss/s1494_jed.vhd | 1 | 31,360 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s1494_jed is
port(
clock: in std_logic;
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(18 downto 0)
);
end s1494_jed;
architecture behaviour of s1494_jed is
constant s000000: std_logic_vector(5 downto 0) := "000000";
constant s001110: std_logic_vector(5 downto 0) := "000001";
constant s011000: std_logic_vector(5 downto 0) := "111000";
constant s010000: std_logic_vector(5 downto 0) := "101001";
constant s010100: std_logic_vector(5 downto 0) := "100000";
constant s110011: std_logic_vector(5 downto 0) := "010000";
constant s010011: std_logic_vector(5 downto 0) := "101110";
constant s000100: std_logic_vector(5 downto 0) := "011000";
constant s010111: std_logic_vector(5 downto 0) := "100010";
constant s010110: std_logic_vector(5 downto 0) := "100011";
constant s100011: std_logic_vector(5 downto 0) := "100110";
constant s001100: std_logic_vector(5 downto 0) := "110010";
constant s011011: std_logic_vector(5 downto 0) := "101100";
constant s010001: std_logic_vector(5 downto 0) := "001110";
constant s100110: std_logic_vector(5 downto 0) := "000100";
constant s011101: std_logic_vector(5 downto 0) := "111010";
constant s101110: std_logic_vector(5 downto 0) := "001000";
constant s010101: std_logic_vector(5 downto 0) := "010110";
constant s111110: std_logic_vector(5 downto 0) := "000101";
constant s000011: std_logic_vector(5 downto 0) := "100100";
constant s111011: std_logic_vector(5 downto 0) := "100101";
constant s011010: std_logic_vector(5 downto 0) := "101000";
constant s111010: std_logic_vector(5 downto 0) := "100001";
constant s100111: std_logic_vector(5 downto 0) := "001011";
constant s110010: std_logic_vector(5 downto 0) := "001010";
constant s100000: std_logic_vector(5 downto 0) := "000011";
constant s011100: std_logic_vector(5 downto 0) := "101010";
constant s101010: std_logic_vector(5 downto 0) := "001100";
constant s100010: std_logic_vector(5 downto 0) := "000110";
constant s101000: std_logic_vector(5 downto 0) := "110011";
constant s011110: std_logic_vector(5 downto 0) := "110000";
constant s110000: std_logic_vector(5 downto 0) := "111001";
constant s010010: std_logic_vector(5 downto 0) := "001101";
constant s001010: std_logic_vector(5 downto 0) := "110001";
constant s100100: std_logic_vector(5 downto 0) := "001001";
constant s111000: std_logic_vector(5 downto 0) := "011001";
constant s001011: std_logic_vector(5 downto 0) := "110110";
constant s110100: std_logic_vector(5 downto 0) := "010100";
constant s001000: std_logic_vector(5 downto 0) := "010001";
constant s000010: std_logic_vector(5 downto 0) := "000010";
constant s000111: std_logic_vector(5 downto 0) := "101101";
constant s101011: std_logic_vector(5 downto 0) := "011010";
constant s001111: std_logic_vector(5 downto 0) := "011100";
constant s000110: std_logic_vector(5 downto 0) := "101011";
constant s110110: std_logic_vector(5 downto 0) := "110100";
constant s011111: std_logic_vector(5 downto 0) := "111100";
constant s111100: std_logic_vector(5 downto 0) := "010011";
constant s101100: std_logic_vector(5 downto 0) := "010010";
signal current_state, next_state: std_logic_vector(5 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "------"; output <= "-------------------";
case current_state is
when s000000 =>
if std_match(input, "0-01----") then next_state <= s000000; output <= "1000000001000000001";
elsif std_match(input, "0-00----") then next_state <= s000000; output <= "1000000000100000001";
elsif std_match(input, "0-10----") then next_state <= s000000; output <= "0000000000000000000";
elsif std_match(input, "0-11----") then next_state <= s000000; output <= "0001001100111110001";
elsif std_match(input, "1-01----") then next_state <= s000000; output <= "1000000001000000001";
elsif std_match(input, "1-00----") then next_state <= s000000; output <= "1000000000100000001";
elsif std_match(input, "1-11----") then next_state <= s001110; output <= "0001001100111110001";
elsif std_match(input, "1-10----") then next_state <= s000000; output <= "0000000000000000000";
end if;
when s001110 =>
if std_match(input, "1---0---") then next_state <= s011000; output <= "0000000000100100101";
elsif std_match(input, "11--1---") then next_state <= s010000; output <= "1000010010100000101";
elsif std_match(input, "10--1---") then next_state <= s011000; output <= "0000000000100100101";
elsif std_match(input, "00------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "01--1---") then next_state <= s000000; output <= "1000010010100000101";
elsif std_match(input, "01--0---") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s011000 =>
if std_match(input, "0-00-000") then next_state <= s000000; output <= "1000000000110000110";
elsif std_match(input, "0-00-010") then next_state <= s000000; output <= "1000000000100000110";
elsif std_match(input, "0-00-110") then next_state <= s000000; output <= "1000000100100000110";
elsif std_match(input, "0-00-100") then next_state <= s000000; output <= "1000000100110000110";
elsif std_match(input, "0-01-100") then next_state <= s000000; output <= "1000001101010000110";
elsif std_match(input, "0-01-110") then next_state <= s000000; output <= "1000001101000000110";
elsif std_match(input, "0-01-010") then next_state <= s000000; output <= "1000001001000000110";
elsif std_match(input, "0-01-000") then next_state <= s000000; output <= "1000001001010000110";
elsif std_match(input, "0-0---01") then next_state <= s000000; output <= "0100000000111111100";
elsif std_match(input, "0-0---11") then next_state <= s000000; output <= "0100000000101111100";
elsif std_match(input, "0-10-000") then next_state <= s000000; output <= "0000001000010000000";
elsif std_match(input, "0-10-010") then next_state <= s000000; output <= "0000001000000000000";
elsif std_match(input, "0-11-0-0") then next_state <= s000000; output <= "0000001000110110110";
elsif std_match(input, "0-10-110") then next_state <= s000000; output <= "0000001100000000000";
elsif std_match(input, "0-10-100") then next_state <= s000000; output <= "0000001100010000000";
elsif std_match(input, "0-11-1-0") then next_state <= s000000; output <= "0000001100110110110";
elsif std_match(input, "0-1---01") then next_state <= s000000; output <= "0100000000111111100";
elsif std_match(input, "0-1---11") then next_state <= s000000; output <= "0100000000101111100";
elsif std_match(input, "1--1--01") then next_state <= s010100; output <= "0100000000111111100";
elsif std_match(input, "1--1--11") then next_state <= s010100; output <= "0100000000101111100";
elsif std_match(input, "1-11-0-0") then next_state <= s110011; output <= "0000001000110110110";
elsif std_match(input, "1-11-1-0") then next_state <= s110011; output <= "0000001100110110110";
elsif std_match(input, "1-01-110") then next_state <= s010100; output <= "1000001101000000110";
elsif std_match(input, "1-01-100") then next_state <= s010100; output <= "1000001101010000110";
elsif std_match(input, "1-01-010") then next_state <= s010100; output <= "1000001001000000110";
elsif std_match(input, "1-01-000") then next_state <= s010100; output <= "1000001001010000110";
elsif std_match(input, "1--0--11") then next_state <= s010100; output <= "0100000000101111100";
elsif std_match(input, "1--0--01") then next_state <= s010100; output <= "0100000000111111100";
elsif std_match(input, "1-10-100") then next_state <= s010100; output <= "0000001100010000000";
elsif std_match(input, "1-10-110") then next_state <= s010100; output <= "0000001100000000000";
elsif std_match(input, "1-10-000") then next_state <= s010100; output <= "0000001000010000000";
elsif std_match(input, "1-10-010") then next_state <= s010100; output <= "0000001000000000000";
elsif std_match(input, "1-00-110") then next_state <= s010100; output <= "1000000100100000110";
elsif std_match(input, "1-00-100") then next_state <= s010100; output <= "1000000100110000110";
elsif std_match(input, "1-00-000") then next_state <= s010100; output <= "1000000000110000110";
elsif std_match(input, "1-00-010") then next_state <= s010100; output <= "1000000000100000110";
end if;
when s010100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s010011; output <= "0000000000100100101";
end if;
when s010011 =>
if std_match(input, "0----0--") then next_state <= s000000; output <= "1000000000111100001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "1000000100111100001";
elsif std_match(input, "1----1--") then next_state <= s000100; output <= "1000000100111100001";
elsif std_match(input, "1----0--") then next_state <= s000100; output <= "1000000000111100001";
end if;
when s000100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "10---11-") then next_state <= s010111; output <= "0000000000100100101";
elsif std_match(input, "11--011-") then next_state <= s010111; output <= "0000000000100100101";
elsif std_match(input, "11--111-") then next_state <= s010110; output <= "0000000000100100101";
elsif std_match(input, "11---01-") then next_state <= s100011; output <= "0000000000100100101";
elsif std_match(input, "10---01-") then next_state <= s010111; output <= "0000000000100100101";
elsif std_match(input, "1-----0-") then next_state <= s010111; output <= "0000000000100100101";
end if;
when s010111 =>
if std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100101011000";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000101011000";
elsif std_match(input, "1----0--") then next_state <= s001100; output <= "0000000000101011000";
elsif std_match(input, "1----1--") then next_state <= s001100; output <= "0000000100101011000";
end if;
when s001100 =>
if std_match(input, "1----1--") then next_state <= s011011; output <= "0000000000100100101";
elsif std_match(input, "1----0--") then next_state <= s010001; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s011011 =>
if std_match(input, "0----11-") then next_state <= s000000; output <= "0000000100101110100";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000000100111110100";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000101110100";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000111110100";
elsif std_match(input, "1----11-") then next_state <= s100110; output <= "0000000100101110100";
elsif std_match(input, "1----10-") then next_state <= s100110; output <= "0000000100111110100";
elsif std_match(input, "1----01-") then next_state <= s100110; output <= "0000000000101110100";
elsif std_match(input, "1----00-") then next_state <= s100110; output <= "0000000000111110100";
end if;
when s100110 =>
if std_match(input, "1-------") then next_state <= s011101; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s011101 =>
if std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000110011010";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000100011010";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000000100100011010";
elsif std_match(input, "0----11-") then next_state <= s000000; output <= "0000000100110011010";
elsif std_match(input, "1----11-") then next_state <= s101110; output <= "0000000100110011010";
elsif std_match(input, "1----10-") then next_state <= s101110; output <= "0000000100100011010";
elsif std_match(input, "1----01-") then next_state <= s101110; output <= "0000000000110011010";
elsif std_match(input, "1----00-") then next_state <= s101110; output <= "0000000000100011010";
end if;
when s101110 =>
if std_match(input, "1-------") then next_state <= s010101; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s010101 =>
if std_match(input, "1----0--") then next_state <= s111110; output <= "1000000000110100110";
elsif std_match(input, "1----1--") then next_state <= s111110; output <= "1000000100110100110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "1000000000110100110";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "1000000100110100110";
end if;
when s111110 =>
if std_match(input, "01----0-") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "00--1-0-") then next_state <= s000000; output <= "0000100000100100101";
elsif std_match(input, "00--0-0-") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "11----01") then next_state <= s000011; output <= "0000000000100100101";
elsif std_match(input, "11--0-00") then next_state <= s000011; output <= "0000000000100100101";
elsif std_match(input, "11--1-00") then next_state <= s111011; output <= "0000000000100100101";
elsif std_match(input, "10--0-0-") then next_state <= s000011; output <= "0000000000100100101";
elsif std_match(input, "10--1-00") then next_state <= s011010; output <= "0000100000100100101";
elsif std_match(input, "10--1-01") then next_state <= s111010; output <= "0000100000100100101";
elsif std_match(input, "0---1-1-") then next_state <= s000000; output <= "0000100000100100101";
elsif std_match(input, "0---0-1-") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1---0-1-") then next_state <= s000011; output <= "0000000000100100101";
elsif std_match(input, "1---1-10") then next_state <= s011010; output <= "0000100000100100101";
elsif std_match(input, "1---1-11") then next_state <= s111010; output <= "0000100000100100101";
end if;
when s000011 =>
if std_match(input, "0----0-1") then next_state <= s000000; output <= "0000000000111110001";
elsif std_match(input, "0----1-1") then next_state <= s000000; output <= "0000000100111110001";
elsif std_match(input, "0----0-0") then next_state <= s000000; output <= "1000000000111110001";
elsif std_match(input, "0----1-0") then next_state <= s000000; output <= "0000000100111110001";
elsif std_match(input, "1----0-1") then next_state <= s001110; output <= "0000000000111110001";
elsif std_match(input, "1----1-1") then next_state <= s001110; output <= "0000000100111110001";
elsif std_match(input, "1----0-0") then next_state <= s001110; output <= "1000000000111110001";
elsif std_match(input, "1----1-0") then next_state <= s001110; output <= "0000000100111110001";
end if;
when s111011 =>
if std_match(input, "1----0--") then next_state <= s100111; output <= "1000000000111110001";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "1000000000111110001";
elsif std_match(input, "1----1--") then next_state <= s010000; output <= "0000010110111110001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000010110111110001";
end if;
when s100111 =>
if std_match(input, "1-------") then next_state <= s111011; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s010000 =>
if std_match(input, "--------") then next_state <= s000000; output <= "0000000000101110100";
end if;
when s011010 =>
if std_match(input, "1----01-") then next_state <= s110010; output <= "0000000000100101001";
elsif std_match(input, "1----00-") then next_state <= s110010; output <= "0000000000110101001";
elsif std_match(input, "1----1--") then next_state <= s100000; output <= "0000000100111110001";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000100101001";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000110101001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100111110001";
end if;
when s110010 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1----00-") then next_state <= s011100; output <= "0000000000100100101";
elsif std_match(input, "1----01-") then next_state <= s011010; output <= "0000000000100100101";
elsif std_match(input, "1----11-") then next_state <= s011100; output <= "0000000000100100101";
elsif std_match(input, "1----10-") then next_state <= s011010; output <= "0000000000100100101";
end if;
when s011100 =>
if std_match(input, "1----10-") then next_state <= s101010; output <= "0000000100101111100";
elsif std_match(input, "1----11-") then next_state <= s101010; output <= "0000000100111111100";
elsif std_match(input, "1----00-") then next_state <= s100010; output <= "0000000000101111100";
elsif std_match(input, "1----01-") then next_state <= s100010; output <= "0000000000111111100";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000000100101111100";
elsif std_match(input, "0----11-") then next_state <= s000000; output <= "0000000100111111100";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000101111100";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000111111100";
end if;
when s101010 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s111010; output <= "0000000000100100101";
end if;
when s111010 =>
if std_match(input, "1-------") then next_state <= s100000; output <= "0000000000111110001";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000111110001";
end if;
when s100000 =>
if std_match(input, "11------") then next_state <= s101000; output <= "0100000000100100101";
elsif std_match(input, "01------") then next_state <= s000000; output <= "0100000000100100101";
elsif std_match(input, "00--0---") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "00--1---") then next_state <= s000000; output <= "0000010000100100101";
elsif std_match(input, "10--0---") then next_state <= s011110; output <= "0000000000100100101";
elsif std_match(input, "10--1---") then next_state <= s110000; output <= "0000010000100100101";
end if;
when s101000 =>
if std_match(input, "1-------") then next_state <= s010010; output <= "1000000000111100001";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "1000000000111100001";
end if;
when s010010 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1---1---") then next_state <= s001010; output <= "0000000000100100101";
elsif std_match(input, "1---0---") then next_state <= s011110; output <= "0000000000100100101";
end if;
when s001010 =>
if std_match(input, "1----1--") then next_state <= s100100; output <= "0000000100110110110";
elsif std_match(input, "1----0--") then next_state <= s111000; output <= "0000000000110101001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100110110110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000110101001";
end if;
when s100100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0010000000100100101";
elsif std_match(input, "1-------") then next_state <= s001011; output <= "0010000000100100101";
end if;
when s001011 =>
if std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000101110110";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100101110110";
elsif std_match(input, "1----0--") then next_state <= s110100; output <= "0000000000101110110";
elsif std_match(input, "1----1--") then next_state <= s110100; output <= "0000000100101110110";
end if;
when s110100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0010000000100100101";
elsif std_match(input, "1-------") then next_state <= s011011; output <= "0010000000100100101";
end if;
when s111000 =>
if std_match(input, "1----0--") then next_state <= s001000; output <= "0000000000100100101";
elsif std_match(input, "1---11--") then next_state <= s001000; output <= "0000000000100100101";
elsif std_match(input, "1---01--") then next_state <= s001010; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s001000 =>
if std_match(input, "1----1--") then next_state <= s100100; output <= "0000000100110110110";
elsif std_match(input, "1----0--") then next_state <= s100100; output <= "0000000000110110110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000110110110";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100110110110";
end if;
when s011110 =>
if std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100111110001";
elsif std_match(input, "0-11-0--") then next_state <= s000000; output <= "0000001000110110110";
elsif std_match(input, "0-10-00-") then next_state <= s000000; output <= "0000001000000000000";
elsif std_match(input, "0-10-01-") then next_state <= s000000; output <= "0000001000010000000";
elsif std_match(input, "0-00-00-") then next_state <= s000000; output <= "1000000000100000110";
elsif std_match(input, "0-00-01-") then next_state <= s000000; output <= "1000000000110000110";
elsif std_match(input, "0-01-01-") then next_state <= s000000; output <= "1000001001010000110";
elsif std_match(input, "0-01-00-") then next_state <= s000000; output <= "1000001001000000110";
elsif std_match(input, "1----1--") then next_state <= s100000; output <= "0000000100111110001";
elsif std_match(input, "1-00-00-") then next_state <= s000010; output <= "1000000000100000110";
elsif std_match(input, "1-00-01-") then next_state <= s000010; output <= "1000000000110000110";
elsif std_match(input, "1-01-01-") then next_state <= s000010; output <= "1000001001010000110";
elsif std_match(input, "1-01-00-") then next_state <= s000010; output <= "1000001001000000110";
elsif std_match(input, "1-11-0--") then next_state <= s110011; output <= "0000001000110110110";
elsif std_match(input, "1-10-00-") then next_state <= s000010; output <= "0000001000000000000";
elsif std_match(input, "1-10-01-") then next_state <= s000010; output <= "0000001000010000000";
end if;
when s000010 =>
if std_match(input, "1----0--") then next_state <= s011110; output <= "0010000000100100101";
elsif std_match(input, "1----1--") then next_state <= s011110; output <= "0000000000100100101";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0010000000100100101";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s110011 =>
if std_match(input, "1-------") then next_state <= s000111; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s000111 =>
if std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100101110110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000101110110";
elsif std_match(input, "1----1--") then next_state <= s101011; output <= "0000000100101110110";
elsif std_match(input, "1----0--") then next_state <= s101011; output <= "0000000000101110110";
end if;
when s101011 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s001111; output <= "0000000000100100101";
end if;
when s001111 =>
if std_match(input, "1----1--") then next_state <= s000100; output <= "0010000100111001110";
elsif std_match(input, "1----0--") then next_state <= s000100; output <= "0010000000111001110";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0010000100111001110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0010000000111001110";
end if;
when s110000 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "1000000000110100110";
elsif std_match(input, "1-------") then next_state <= s000110; output <= "1000000000110100110";
end if;
when s000110 =>
if std_match(input, "1---01--") then next_state <= s011000; output <= "0001000000100100101";
elsif std_match(input, "1---00--") then next_state <= s011000; output <= "0010000000100100101";
elsif std_match(input, "1---10--") then next_state <= s011110; output <= "0010000000100100101";
elsif std_match(input, "1---11--") then next_state <= s011110; output <= "0001000000100100101";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0010000000100100101";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0001000000100100101";
end if;
when s100010 =>
if std_match(input, "1-------") then next_state <= s011010; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s010001 =>
if std_match(input, "1----0--") then next_state <= s110110; output <= "1000000000111110100";
elsif std_match(input, "1----1--") then next_state <= s110110; output <= "1000000100111110100";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "1000000100111110100";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "1000000000111110100";
end if;
when s110110 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s011111; output <= "0000000000100100101";
end if;
when s011111 =>
if std_match(input, "0----11-") then next_state <= s000000; output <= "1000000100111011010";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "1000000100101011010";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "1000000000101011010";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "1000000000111011010";
elsif std_match(input, "1----10-") then next_state <= s101110; output <= "1000000100101011010";
elsif std_match(input, "1----11-") then next_state <= s101110; output <= "1000000100111011010";
elsif std_match(input, "1----00-") then next_state <= s101110; output <= "1000000000101011010";
elsif std_match(input, "1----01-") then next_state <= s101110; output <= "1000000000111011010";
end if;
when s010110 =>
if std_match(input, "1----1--") then next_state <= s111100; output <= "0001000100111110001";
elsif std_match(input, "1-00-0--") then next_state <= s101100; output <= "1000000000100000110";
elsif std_match(input, "1-01-0--") then next_state <= s101100; output <= "1000001001000000110";
elsif std_match(input, "1-10-0--") then next_state <= s101100; output <= "0000001000000000000";
elsif std_match(input, "1-11-0--") then next_state <= s110011; output <= "0000001000110110110";
elsif std_match(input, "0-00-0--") then next_state <= s000000; output <= "1000000000100000110";
elsif std_match(input, "0-01-0--") then next_state <= s000000; output <= "1000001001000000110";
elsif std_match(input, "0-0--1--") then next_state <= s000000; output <= "0001000100111110001";
elsif std_match(input, "0-1--1--") then next_state <= s000000; output <= "0001000100111110001";
elsif std_match(input, "0-10-0--") then next_state <= s000000; output <= "0000001000000000000";
elsif std_match(input, "0-11-0--") then next_state <= s000000; output <= "0000001000110110110";
end if;
when s111100 =>
if std_match(input, "1-------") then next_state <= s100011; output <= "0100000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0100000000100100101";
end if;
when s100011 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000110110110";
elsif std_match(input, "1-------") then next_state <= s110011; output <= "0000000000110110110";
end if;
when s101100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s010110; output <= "0000000000100100101";
end if;
when others => next_state <= "------"; output <= "-------------------";
end case;
end process;
end behaviour;
| agpl-3.0 | c720575503f3a23fa98388de1c1b8ea8 | 0.625829 | 3.830931 | false | false | false | false |
chastell/art-decomp | kiss/kirkman_nov.vhd | 1 | 35,900 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity kirkman_nov is
port(
clock: in std_logic;
input: in std_logic_vector(11 downto 0);
output: out std_logic_vector(5 downto 0)
);
end kirkman_nov;
architecture behaviour of kirkman_nov is
constant rst0: std_logic_vector(4 downto 0) := "00000";
constant bit1: std_logic_vector(4 downto 0) := "00001";
constant bit2: std_logic_vector(4 downto 0) := "00010";
constant bit3: std_logic_vector(4 downto 0) := "01011";
constant bit4: std_logic_vector(4 downto 0) := "01101";
constant bit5: std_logic_vector(4 downto 0) := "01110";
constant bit6: std_logic_vector(4 downto 0) := "01111";
constant bit7: std_logic_vector(4 downto 0) := "01000";
constant bit8: std_logic_vector(4 downto 0) := "01001";
constant bit9: std_logic_vector(4 downto 0) := "01010";
constant bitA: std_logic_vector(4 downto 0) := "01100";
constant bitB: std_logic_vector(4 downto 0) := "00100";
constant bitC: std_logic_vector(4 downto 0) := "00101";
constant bitD: std_logic_vector(4 downto 0) := "00110";
constant bitE: std_logic_vector(4 downto 0) := "00111";
constant bitF: std_logic_vector(4 downto 0) := "00011";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "------";
if std_match(input, "--------1---") then next_state <= rst0; output <= "1-----";
else
case current_state is
when rst0 =>
if std_match(input, "--------0000") then next_state <= rst0; output <= "0----0";
elsif std_match(input, "--------0001") then next_state <= bit1; output <= "0---00";
elsif std_match(input, "-----0--0111") then next_state <= bit1; output <= "0--010";
elsif std_match(input, "-----1--0111") then next_state <= bit1; output <= "0--110";
elsif std_match(input, "--------0010") then next_state <= bit1; output <= "0---00";
elsif std_match(input, "--------0100") then next_state <= bit1; output <= "0---00";
end if;
when bit1 =>
if std_match(input, "--------0001") then next_state <= bit2; output <= "0---10";
elsif std_match(input, "-----0--0111") then next_state <= bit2; output <= "0--010";
elsif std_match(input, "-----1--0111") then next_state <= bit2; output <= "0--110";
elsif std_match(input, "--------0010") then next_state <= bit2; output <= "0---00";
elsif std_match(input, "--------0100") then next_state <= bit2; output <= "0---00";
end if;
when bit2 =>
if std_match(input, "--------0001") then next_state <= bit3; output <= "0---00";
elsif std_match(input, "-----0--0111") then next_state <= bit3; output <= "0--000";
elsif std_match(input, "-----1--0111") then next_state <= bit3; output <= "0--100";
elsif std_match(input, "--------0010") then next_state <= bit3; output <= "0---10";
elsif std_match(input, "--------0100") then next_state <= bit3; output <= "0---10";
end if;
when bit3 =>
if std_match(input, "0-------0001") then next_state <= bit4; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bit4; output <= "1---10";
elsif std_match(input, "-00--00-0111") then next_state <= bit4; output <= "100000";
elsif std_match(input, "-01--00-0111") then next_state <= bit4; output <= "100010";
elsif std_match(input, "-10--00-0111") then next_state <= bit4; output <= "100010";
elsif std_match(input, "-11--00-0111") then next_state <= bit4; output <= "110000";
elsif std_match(input, "-00--01-0111") then next_state <= bit4; output <= "101000";
elsif std_match(input, "-01--01-0111") then next_state <= bit4; output <= "100010";
elsif std_match(input, "-10--01-0111") then next_state <= bit4; output <= "100010";
elsif std_match(input, "-11--01-0111") then next_state <= bit4; output <= "111000";
elsif std_match(input, "-----10-0111") then next_state <= bit4; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bit4; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bit4; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bit4; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bit4; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bit4; output <= "1---10";
end if;
when bit4 =>
if std_match(input, "0-------0001") then next_state <= bit5; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bit5; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bit5; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bit5; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bit5; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bit5; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bit5; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bit5; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bit5; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bit5; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bit5; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bit5; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bit5; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bit5; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bit5; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bit5; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bit5; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bit5; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bit5; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bit5; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bit5; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bit5; output <= "1---10";
end if;
when bit5 =>
if std_match(input, "0-------0001") then next_state <= bit6; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bit6; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bit6; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bit6; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bit6; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bit6; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bit6; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bit6; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bit6; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bit6; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bit6; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bit6; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bit6; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bit6; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bit6; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bit6; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bit6; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bit6; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bit6; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bit6; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bit6; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bit6; output <= "1---10";
end if;
when bit6 =>
if std_match(input, "0-------0001") then next_state <= bit7; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bit7; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bit7; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bit7; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bit7; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bit7; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bit7; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bit7; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bit7; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bit7; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bit7; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bit7; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bit7; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bit7; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bit7; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bit7; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bit7; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bit7; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bit7; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bit7; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bit7; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bit7; output <= "1---10";
end if;
when bit7 =>
if std_match(input, "0-------0001") then next_state <= bit8; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bit8; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bit8; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bit8; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bit8; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bit8; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bit8; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bit8; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bit8; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bit8; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bit8; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bit8; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bit8; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bit8; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bit8; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bit8; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bit8; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bit8; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bit8; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bit8; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bit8; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bit8; output <= "1---10";
end if;
when bit8 =>
if std_match(input, "0-------0001") then next_state <= bit9; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bit9; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bit9; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bit9; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bit9; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bit9; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bit9; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bit9; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bit9; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bit9; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bit9; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bit9; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bit9; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bit9; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bit9; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bit9; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bit9; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bit9; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bit9; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bit9; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bit9; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bit9; output <= "1---10";
end if;
when bit9 =>
if std_match(input, "0-------0001") then next_state <= bitA; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bitA; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bitA; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bitA; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bitA; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bitA; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bitA; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bitA; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bitA; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bitA; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bitA; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bitA; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bitA; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bitA; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bitA; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bitA; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bitA; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bitA; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bitA; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bitA; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bitA; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bitA; output <= "1---10";
end if;
when bitA =>
if std_match(input, "0-------0001") then next_state <= bitB; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bitB; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bitB; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bitB; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bitB; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bitB; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bitB; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bitB; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bitB; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bitB; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bitB; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bitB; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bitB; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bitB; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bitB; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bitB; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bitB; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bitB; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bitB; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bitB; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bitB; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bitB; output <= "1---10";
end if;
when bitB =>
if std_match(input, "--------0001") then next_state <= bitC; output <= "0---00";
elsif std_match(input, "--0000--0111") then next_state <= bitC; output <= "000000";
elsif std_match(input, "--0100--0111") then next_state <= bitC; output <= "000010";
elsif std_match(input, "--1000--0111") then next_state <= bitC; output <= "000010";
elsif std_match(input, "--1100--0111") then next_state <= bitC; output <= "010000";
elsif std_match(input, "--0010--0111") then next_state <= bitC; output <= "001000";
elsif std_match(input, "--0110--0111") then next_state <= bitC; output <= "000010";
elsif std_match(input, "--1010--0111") then next_state <= bitC; output <= "000010";
elsif std_match(input, "--1110--0111") then next_state <= bitC; output <= "011000";
elsif std_match(input, "-----1--0111") then next_state <= bitC; output <= "0--100";
elsif std_match(input, "--------0010") then next_state <= bitC; output <= "0---00";
elsif std_match(input, "--------0100") then next_state <= bitC; output <= "0---00";
end if;
when bitC =>
if std_match(input, "--------0001") then next_state <= bitD; output <= "0---00";
elsif std_match(input, "--0000--0111") then next_state <= bitD; output <= "000000";
elsif std_match(input, "--0100--0111") then next_state <= bitD; output <= "000010";
elsif std_match(input, "--1000--0111") then next_state <= bitD; output <= "000010";
elsif std_match(input, "--1100--0111") then next_state <= bitD; output <= "010000";
elsif std_match(input, "--0010--0111") then next_state <= bitD; output <= "001000";
elsif std_match(input, "--0110--0111") then next_state <= bitD; output <= "000010";
elsif std_match(input, "--1010--0111") then next_state <= bitD; output <= "000010";
elsif std_match(input, "--1110--0111") then next_state <= bitD; output <= "011000";
elsif std_match(input, "-----1--0111") then next_state <= bitD; output <= "0--100";
elsif std_match(input, "--------0010") then next_state <= bitD; output <= "0---00";
elsif std_match(input, "--------0100") then next_state <= bitD; output <= "0---00";
end if;
when bitD =>
if std_match(input, "--------0001") then next_state <= bitE; output <= "0---00";
elsif std_match(input, "--0000--0111") then next_state <= bitE; output <= "000000";
elsif std_match(input, "--0100--0111") then next_state <= bitE; output <= "000010";
elsif std_match(input, "--1000--0111") then next_state <= bitE; output <= "000010";
elsif std_match(input, "--1100--0111") then next_state <= bitE; output <= "010000";
elsif std_match(input, "--0010--0111") then next_state <= bitE; output <= "001000";
elsif std_match(input, "--0110--0111") then next_state <= bitE; output <= "000010";
elsif std_match(input, "--1010--0111") then next_state <= bitE; output <= "000010";
elsif std_match(input, "--1110--0111") then next_state <= bitE; output <= "011000";
elsif std_match(input, "-----1--0111") then next_state <= bitE; output <= "0--100";
elsif std_match(input, "--------0010") then next_state <= bitE; output <= "0---00";
elsif std_match(input, "--------0100") then next_state <= bitE; output <= "0---00";
end if;
when bitE =>
if std_match(input, "--------0001") then next_state <= bitF; output <= "0---01";
elsif std_match(input, "--0000--0111") then next_state <= bitF; output <= "000001";
elsif std_match(input, "--0100--0111") then next_state <= bitF; output <= "000011";
elsif std_match(input, "--1000--0111") then next_state <= bitF; output <= "000011";
elsif std_match(input, "--1100--0111") then next_state <= bitF; output <= "010001";
elsif std_match(input, "--0010--0111") then next_state <= bitF; output <= "001100";
elsif std_match(input, "--0110--0111") then next_state <= bitF; output <= "000011";
elsif std_match(input, "--1010--0111") then next_state <= bitF; output <= "000011";
elsif std_match(input, "--1110--0111") then next_state <= bitF; output <= "011001";
elsif std_match(input, "-----1--0111") then next_state <= bitF; output <= "0--001";
elsif std_match(input, "--------0010") then next_state <= bitF; output <= "0---01";
elsif std_match(input, "--------0100") then next_state <= bitF; output <= "0---01";
end if;
when bitF =>
if std_match(input, "--------0001") then next_state <= rst0; output <= "0---00";
elsif std_match(input, "---0-0--0111") then next_state <= rst0; output <= "0--000";
elsif std_match(input, "---1-0--0111") then next_state <= rst0; output <= "0--010";
elsif std_match(input, "-----1--0111") then next_state <= rst0; output <= "0--100";
elsif std_match(input, "--------0010") then next_state <= rst0; output <= "0---00";
elsif std_match(input, "--------0100") then next_state <= rst0; output <= "0---00";
end if;
when others => next_state <= "-----"; output <= "------";
end case;
end if;
end process;
end behaviour;
| agpl-3.0 | b01167ef0632d72f3cad836942574574 | 0.592284 | 3.523408 | false | false | false | false |
chastell/art-decomp | kiss/beecount_hot.vhd | 1 | 3,554 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity beecount_hot is
port(
clock: in std_logic;
input: in std_logic_vector(2 downto 0);
output: out std_logic_vector(3 downto 0)
);
end beecount_hot;
architecture behaviour of beecount_hot is
constant st0: std_logic_vector(6 downto 0) := "1000000";
constant st1: std_logic_vector(6 downto 0) := "0100000";
constant st4: std_logic_vector(6 downto 0) := "0010000";
constant st2: std_logic_vector(6 downto 0) := "0001000";
constant st3: std_logic_vector(6 downto 0) := "0000100";
constant st5: std_logic_vector(6 downto 0) := "0000010";
constant st6: std_logic_vector(6 downto 0) := "0000001";
signal current_state, next_state: std_logic_vector(6 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-------"; output <= "----";
case current_state is
when st0 =>
if std_match(input, "000") then next_state <= st0; output <= "0101";
elsif std_match(input, "100") then next_state <= st1; output <= "0101";
elsif std_match(input, "010") then next_state <= st4; output <= "0101";
elsif std_match(input, "--1") then next_state <= st0; output <= "1010";
end if;
when st1 =>
if std_match(input, "100") then next_state <= st1; output <= "0101";
elsif std_match(input, "0-0") then next_state <= st0; output <= "0101";
elsif std_match(input, "110") then next_state <= st2; output <= "0101";
elsif std_match(input, "--1") then next_state <= st0; output <= "1010";
end if;
when st2 =>
if std_match(input, "110") then next_state <= st2; output <= "0101";
elsif std_match(input, "100") then next_state <= st1; output <= "0101";
elsif std_match(input, "010") then next_state <= st3; output <= "0101";
elsif std_match(input, "--1") then next_state <= st0; output <= "1010";
end if;
when st3 =>
if std_match(input, "010") then next_state <= st3; output <= "0101";
elsif std_match(input, "110") then next_state <= st2; output <= "0101";
elsif std_match(input, "000") then next_state <= st0; output <= "0110";
elsif std_match(input, "--1") then next_state <= st0; output <= "1010";
end if;
when st4 =>
if std_match(input, "010") then next_state <= st4; output <= "0101";
elsif std_match(input, "-00") then next_state <= st0; output <= "0101";
elsif std_match(input, "110") then next_state <= st5; output <= "0101";
elsif std_match(input, "--1") then next_state <= st0; output <= "1010";
end if;
when st5 =>
if std_match(input, "110") then next_state <= st5; output <= "0101";
elsif std_match(input, "010") then next_state <= st4; output <= "0101";
elsif std_match(input, "100") then next_state <= st6; output <= "0101";
elsif std_match(input, "--1") then next_state <= st0; output <= "1010";
end if;
when st6 =>
if std_match(input, "100") then next_state <= st6; output <= "0101";
elsif std_match(input, "110") then next_state <= st5; output <= "0101";
elsif std_match(input, "000") then next_state <= st0; output <= "1001";
elsif std_match(input, "--1") then next_state <= st0; output <= "1010";
end if;
when others => next_state <= "-------"; output <= "----";
end case;
end process;
end behaviour;
| agpl-3.0 | 99920b8a04e5d8c70204b8d43920d05a | 0.587507 | 3.343368 | false | false | false | false |
chastell/art-decomp | kiss/cse_hot.vhd | 1 | 10,241 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity cse_hot is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(6 downto 0)
);
end cse_hot;
architecture behaviour of cse_hot is
constant st0: std_logic_vector(15 downto 0) := "1000000000000000";
constant st1: std_logic_vector(15 downto 0) := "0100000000000000";
constant st9: std_logic_vector(15 downto 0) := "0010000000000000";
constant st6: std_logic_vector(15 downto 0) := "0001000000000000";
constant st8: std_logic_vector(15 downto 0) := "0000100000000000";
constant st2: std_logic_vector(15 downto 0) := "0000010000000000";
constant st5: std_logic_vector(15 downto 0) := "0000001000000000";
constant st3: std_logic_vector(15 downto 0) := "0000000100000000";
constant st4: std_logic_vector(15 downto 0) := "0000000010000000";
constant st7: std_logic_vector(15 downto 0) := "0000000001000000";
constant st10: std_logic_vector(15 downto 0) := "0000000000100000";
constant st11: std_logic_vector(15 downto 0) := "0000000000010000";
constant st12: std_logic_vector(15 downto 0) := "0000000000001000";
constant st13: std_logic_vector(15 downto 0) := "0000000000000100";
constant st14: std_logic_vector(15 downto 0) := "0000000000000010";
constant st15: std_logic_vector(15 downto 0) := "0000000000000001";
signal current_state, next_state: std_logic_vector(15 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----------------"; output <= "-------";
case current_state is
when st0 =>
if std_match(input, "1-000--") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "1-11---") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "1-1-1--") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "10010--") then next_state <= st1; output <= "1100-10";
elsif std_match(input, "10011--") then next_state <= st9; output <= "0010001";
elsif std_match(input, "10001--") then next_state <= st6; output <= "0000-01";
elsif std_match(input, "10100--") then next_state <= st8; output <= "0000--0";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000-00";
end if;
when st1 =>
if std_match(input, "101----") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "10010--") then next_state <= st1; output <= "0100-00";
elsif std_match(input, "1000---") then next_state <= st2; output <= "0000-00";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000-10";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000-10";
end if;
when st2 =>
if std_match(input, "10010--") then next_state <= st1; output <= "1100-00";
elsif std_match(input, "10011--") then next_state <= st5; output <= "0001000";
elsif std_match(input, "10000--") then next_state <= st2; output <= "0000-00";
elsif std_match(input, "10001--") then next_state <= st3; output <= "1000-00";
elsif std_match(input, "101----") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "0-----0") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "0-----1") then next_state <= st0; output <= "0000-10";
elsif std_match(input, "-1----0") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "-1----1") then next_state <= st0; output <= "0000-10";
end if;
when st3 =>
if std_match(input, "10001--") then next_state <= st3; output <= "0000-00";
elsif std_match(input, "100-0--") then next_state <= st4; output <= "0000-00";
elsif std_match(input, "101----") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000-10";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000-10";
end if;
when st4 =>
if std_match(input, "101----") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "10010--") then next_state <= st1; output <= "1100-00";
elsif std_match(input, "1000---") then next_state <= st4; output <= "0000-00";
elsif std_match(input, "10011--") then next_state <= st5; output <= "0001000";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000-00";
end if;
when st5 =>
if std_match(input, "10-1---") then next_state <= st5; output <= "0000-00";
elsif std_match(input, "10-0---") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
end if;
when st6 =>
if std_match(input, "10--1--") then next_state <= st6; output <= "0000-00";
elsif std_match(input, "101----") then next_state <= st6; output <= "0000-00";
elsif std_match(input, "100-0--") then next_state <= st7; output <= "0000-00";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000-00";
end if;
when st7 =>
if std_match(input, "100--0-") then next_state <= st7; output <= "0000-00";
elsif std_match(input, "101--0-") then next_state <= st6; output <= "0000-01";
elsif std_match(input, "10---1-") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000-00";
end if;
when st8 =>
if std_match(input, "10-00--") then next_state <= st8; output <= "0000-00";
elsif std_match(input, "10010--") then next_state <= st9; output <= "0010101";
elsif std_match(input, "10-01--") then next_state <= st10; output <= "0000-10";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "10-11--") then next_state <= st0; output <= "0000--0";
end if;
when st9 =>
if std_match(input, "10-1---") then next_state <= st9; output <= "0000000";
elsif std_match(input, "10-0---") then next_state <= st7; output <= "0000000";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
end if;
when st10 =>
if std_match(input, "10-0---") then next_state <= st10; output <= "0000-00";
elsif std_match(input, "10-10--") then next_state <= st11; output <= "0000100";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "10-11--") then next_state <= st0; output <= "0000--0";
end if;
when st11 =>
if std_match(input, "10-10--") then next_state <= st11; output <= "0000000";
elsif std_match(input, "10-0---") then next_state <= st12; output <= "0000000";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "10-11--") then next_state <= st0; output <= "0000--0";
end if;
when st12 =>
if std_match(input, "10-0---") then next_state <= st12; output <= "0000000";
elsif std_match(input, "10-10--") then next_state <= st13; output <= "1000000";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "10-11--") then next_state <= st0; output <= "0000--0";
end if;
when st13 =>
if std_match(input, "10-10--") then next_state <= st13; output <= "0000000";
elsif std_match(input, "10-01--") then next_state <= st13; output <= "0000000";
elsif std_match(input, "10100--") then next_state <= st14; output <= "0000000";
elsif std_match(input, "10000--") then next_state <= st15; output <= "0000000";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
end if;
when st14 =>
if std_match(input, "--111--") then next_state <= st14; output <= "0000000";
elsif std_match(input, "--100--") then next_state <= st14; output <= "0000000";
elsif std_match(input, "--110--") then next_state <= st13; output <= "1000000";
elsif std_match(input, "--101--") then next_state <= st13; output <= "1000000";
elsif std_match(input, "--0----") then next_state <= st0; output <= "0001000";
end if;
when st15 =>
if std_match(input, "10000--") then next_state <= st15; output <= "0000000";
elsif std_match(input, "10010--") then next_state <= st13; output <= "1000000";
elsif std_match(input, "10001--") then next_state <= st13; output <= "1000000";
elsif std_match(input, "101----") then next_state <= st8; output <= "0001000";
elsif std_match(input, "0------") then next_state <= st0; output <= "0001000";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0001000";
elsif std_match(input, "10011--") then next_state <= st0; output <= "0001000";
end if;
when others => next_state <= "----------------"; output <= "-------";
end case;
end process;
end behaviour;
| agpl-3.0 | 2320a45286d393d88a0a0a8914e1fb2e | 0.572796 | 3.394432 | false | false | false | false |
chastell/art-decomp | kiss/dk17_rnd.vhd | 1 | 4,134 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk17_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(2 downto 0)
);
end dk17_rnd;
architecture behaviour of dk17_rnd is
constant s10000000: std_logic_vector(2 downto 0) := "101";
constant s01000000: std_logic_vector(2 downto 0) := "010";
constant s00100000: std_logic_vector(2 downto 0) := "011";
constant s00010000: std_logic_vector(2 downto 0) := "110";
constant s00001000: std_logic_vector(2 downto 0) := "111";
constant s00000100: std_logic_vector(2 downto 0) := "001";
constant s00000010: std_logic_vector(2 downto 0) := "000";
constant s00000001: std_logic_vector(2 downto 0) := "100";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "---";
case current_state is
when s10000000 =>
if std_match(input, "00") then next_state <= s10000000; output <= "001";
elsif std_match(input, "01") then next_state <= s00010000; output <= "010";
elsif std_match(input, "10") then next_state <= s01000000; output <= "001";
elsif std_match(input, "11") then next_state <= s00001000; output <= "010";
end if;
when s01000000 =>
if std_match(input, "00") then next_state <= s00100000; output <= "000";
elsif std_match(input, "01") then next_state <= s00010000; output <= "000";
elsif std_match(input, "10") then next_state <= s00100000; output <= "010";
elsif std_match(input, "11") then next_state <= s00000100; output <= "000";
end if;
when s00100000 =>
if std_match(input, "00") then next_state <= s10000000; output <= "001";
elsif std_match(input, "01") then next_state <= s10000000; output <= "101";
elsif std_match(input, "10") then next_state <= s01000000; output <= "001";
elsif std_match(input, "11") then next_state <= s01000000; output <= "101";
end if;
when s00010000 =>
if std_match(input, "00") then next_state <= s00010000; output <= "100";
elsif std_match(input, "01") then next_state <= s00001000; output <= "101";
elsif std_match(input, "10") then next_state <= s00010000; output <= "010";
elsif std_match(input, "11") then next_state <= s00001000; output <= "101";
end if;
when s00001000 =>
if std_match(input, "00") then next_state <= s00100000; output <= "000";
elsif std_match(input, "01") then next_state <= s00010000; output <= "100";
elsif std_match(input, "10") then next_state <= s00100000; output <= "010";
elsif std_match(input, "11") then next_state <= s00100000; output <= "100";
end if;
when s00000100 =>
if std_match(input, "00") then next_state <= s00000010; output <= "000";
elsif std_match(input, "01") then next_state <= s00000001; output <= "000";
elsif std_match(input, "10") then next_state <= s00100000; output <= "010";
elsif std_match(input, "11") then next_state <= s00100000; output <= "100";
end if;
when s00000010 =>
if std_match(input, "00") then next_state <= s00010000; output <= "010";
elsif std_match(input, "01") then next_state <= s10000000; output <= "101";
elsif std_match(input, "10") then next_state <= s00001000; output <= "010";
elsif std_match(input, "11") then next_state <= s01000000; output <= "101";
end if;
when s00000001 =>
if std_match(input, "00") then next_state <= s00010000; output <= "100";
elsif std_match(input, "01") then next_state <= s00001000; output <= "100";
elsif std_match(input, "10") then next_state <= s00100000; output <= "010";
elsif std_match(input, "11") then next_state <= s00100000; output <= "100";
end if;
when others => next_state <= "---"; output <= "---";
end case;
end process;
end behaviour;
| agpl-3.0 | 0ee2bd5dc1a4ee36922c37d6bda75659 | 0.609821 | 3.479798 | false | false | false | false |
chastell/art-decomp | kiss/train11_rnd.vhd | 1 | 3,530 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity train11_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(0 downto 0)
);
end train11_rnd;
architecture behaviour of train11_rnd is
constant st0: std_logic_vector(3 downto 0) := "1101";
constant st1: std_logic_vector(3 downto 0) := "0010";
constant st2: std_logic_vector(3 downto 0) := "1011";
constant st3: std_logic_vector(3 downto 0) := "1110";
constant st5: std_logic_vector(3 downto 0) := "1111";
constant st7: std_logic_vector(3 downto 0) := "0001";
constant st9: std_logic_vector(3 downto 0) := "0110";
constant st4: std_logic_vector(3 downto 0) := "0000";
constant st6: std_logic_vector(3 downto 0) := "1010";
constant st8: std_logic_vector(3 downto 0) := "1000";
constant st10: std_logic_vector(3 downto 0) := "0100";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "00") then next_state <= st0; output <= "0";
elsif std_match(input, "10") then next_state <= st1; output <= "-";
elsif std_match(input, "01") then next_state <= st2; output <= "-";
end if;
when st1 =>
if std_match(input, "10") then next_state <= st1; output <= "1";
elsif std_match(input, "00") then next_state <= st3; output <= "1";
elsif std_match(input, "11") then next_state <= st5; output <= "1";
end if;
when st2 =>
if std_match(input, "01") then next_state <= st2; output <= "1";
elsif std_match(input, "00") then next_state <= st7; output <= "1";
elsif std_match(input, "11") then next_state <= st9; output <= "1";
end if;
when st3 =>
if std_match(input, "00") then next_state <= st3; output <= "1";
elsif std_match(input, "01") then next_state <= st4; output <= "1";
end if;
when st4 =>
if std_match(input, "01") then next_state <= st4; output <= "1";
elsif std_match(input, "00") then next_state <= st0; output <= "-";
end if;
when st5 =>
if std_match(input, "11") then next_state <= st5; output <= "1";
elsif std_match(input, "01") then next_state <= st6; output <= "1";
end if;
when st6 =>
if std_match(input, "01") then next_state <= st6; output <= "1";
elsif std_match(input, "00") then next_state <= st0; output <= "-";
end if;
when st7 =>
if std_match(input, "00") then next_state <= st7; output <= "1";
elsif std_match(input, "10") then next_state <= st8; output <= "1";
end if;
when st8 =>
if std_match(input, "10") then next_state <= st8; output <= "1";
elsif std_match(input, "00") then next_state <= st0; output <= "-";
end if;
when st9 =>
if std_match(input, "11") then next_state <= st9; output <= "1";
elsif std_match(input, "10") then next_state <= st10; output <= "1";
end if;
when st10 =>
if std_match(input, "10") then next_state <= st10; output <= "1";
elsif std_match(input, "00") then next_state <= st0; output <= "-";
end if;
when others => next_state <= "----"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 | c4f5ed8093fdcd5e049812a3fb031e8b | 0.572521 | 3.232601 | false | false | false | false |
chastell/art-decomp | kiss/bbara_rnd.vhd | 1 | 6,275 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity bbara_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(3 downto 0);
output: out std_logic_vector(1 downto 0)
);
end bbara_rnd;
architecture behaviour of bbara_rnd is
constant st0: std_logic_vector(3 downto 0) := "1101";
constant st1: std_logic_vector(3 downto 0) := "0010";
constant st4: std_logic_vector(3 downto 0) := "1011";
constant st2: std_logic_vector(3 downto 0) := "1110";
constant st3: std_logic_vector(3 downto 0) := "1111";
constant st7: std_logic_vector(3 downto 0) := "0001";
constant st5: std_logic_vector(3 downto 0) := "0110";
constant st6: std_logic_vector(3 downto 0) := "0000";
constant st8: std_logic_vector(3 downto 0) := "1010";
constant st9: std_logic_vector(3 downto 0) := "1000";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "--";
case current_state is
when st0 =>
if std_match(input, "--01") then next_state <= st0; output <= "00";
elsif std_match(input, "--10") then next_state <= st0; output <= "00";
elsif std_match(input, "--00") then next_state <= st0; output <= "00";
elsif std_match(input, "0011") then next_state <= st0; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when st1 =>
if std_match(input, "--01") then next_state <= st1; output <= "00";
elsif std_match(input, "--10") then next_state <= st1; output <= "00";
elsif std_match(input, "--00") then next_state <= st1; output <= "00";
elsif std_match(input, "0011") then next_state <= st0; output <= "00";
elsif std_match(input, "-111") then next_state <= st2; output <= "00";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when st2 =>
if std_match(input, "--01") then next_state <= st2; output <= "00";
elsif std_match(input, "--10") then next_state <= st2; output <= "00";
elsif std_match(input, "--00") then next_state <= st2; output <= "00";
elsif std_match(input, "0011") then next_state <= st1; output <= "00";
elsif std_match(input, "-111") then next_state <= st3; output <= "00";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when st3 =>
if std_match(input, "--01") then next_state <= st3; output <= "10";
elsif std_match(input, "--10") then next_state <= st3; output <= "10";
elsif std_match(input, "--00") then next_state <= st3; output <= "10";
elsif std_match(input, "0011") then next_state <= st7; output <= "00";
elsif std_match(input, "-111") then next_state <= st3; output <= "10";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when st4 =>
if std_match(input, "--01") then next_state <= st4; output <= "00";
elsif std_match(input, "--10") then next_state <= st4; output <= "00";
elsif std_match(input, "--00") then next_state <= st4; output <= "00";
elsif std_match(input, "0011") then next_state <= st0; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st5; output <= "00";
end if;
when st5 =>
if std_match(input, "--01") then next_state <= st5; output <= "00";
elsif std_match(input, "--10") then next_state <= st5; output <= "00";
elsif std_match(input, "--00") then next_state <= st5; output <= "00";
elsif std_match(input, "0011") then next_state <= st4; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st6; output <= "00";
end if;
when st6 =>
if std_match(input, "--01") then next_state <= st6; output <= "01";
elsif std_match(input, "--10") then next_state <= st6; output <= "01";
elsif std_match(input, "--00") then next_state <= st6; output <= "01";
elsif std_match(input, "0011") then next_state <= st7; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st6; output <= "01";
end if;
when st7 =>
if std_match(input, "--01") then next_state <= st7; output <= "00";
elsif std_match(input, "--10") then next_state <= st7; output <= "00";
elsif std_match(input, "--00") then next_state <= st7; output <= "00";
elsif std_match(input, "0011") then next_state <= st8; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when st8 =>
if std_match(input, "--01") then next_state <= st8; output <= "00";
elsif std_match(input, "--10") then next_state <= st8; output <= "00";
elsif std_match(input, "--00") then next_state <= st8; output <= "00";
elsif std_match(input, "0011") then next_state <= st9; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when st9 =>
if std_match(input, "--01") then next_state <= st9; output <= "00";
elsif std_match(input, "--10") then next_state <= st9; output <= "00";
elsif std_match(input, "--00") then next_state <= st9; output <= "00";
elsif std_match(input, "0011") then next_state <= st0; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when others => next_state <= "----"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | 1b49ef01700100d2ae9e2f166edfdf1c | 0.571474 | 3.280188 | false | false | false | false |
chastell/art-decomp | kiss/tbk_rnd.vhd | 1 | 133,046 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity tbk_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(5 downto 0);
output: out std_logic_vector(2 downto 0)
);
end tbk_rnd;
architecture behaviour of tbk_rnd is
constant st0: std_logic_vector(4 downto 0) := "11101";
constant st16: std_logic_vector(4 downto 0) := "00010";
constant st1: std_logic_vector(4 downto 0) := "11011";
constant st2: std_logic_vector(4 downto 0) := "11110";
constant st3: std_logic_vector(4 downto 0) := "11111";
constant st4: std_logic_vector(4 downto 0) := "10001";
constant st5: std_logic_vector(4 downto 0) := "10110";
constant st6: std_logic_vector(4 downto 0) := "01011";
constant st7: std_logic_vector(4 downto 0) := "01111";
constant st8: std_logic_vector(4 downto 0) := "00001";
constant st9: std_logic_vector(4 downto 0) := "10000";
constant st10: std_logic_vector(4 downto 0) := "11010";
constant st11: std_logic_vector(4 downto 0) := "11000";
constant st12: std_logic_vector(4 downto 0) := "01000";
constant st13: std_logic_vector(4 downto 0) := "00100";
constant st15: std_logic_vector(4 downto 0) := "01001";
constant st14: std_logic_vector(4 downto 0) := "00110";
constant st29: std_logic_vector(4 downto 0) := "11100";
constant st31: std_logic_vector(4 downto 0) := "00011";
constant st30: std_logic_vector(4 downto 0) := "10111";
constant st17: std_logic_vector(4 downto 0) := "10011";
constant st18: std_logic_vector(4 downto 0) := "10010";
constant st19: std_logic_vector(4 downto 0) := "00111";
constant st20: std_logic_vector(4 downto 0) := "01100";
constant st21: std_logic_vector(4 downto 0) := "10101";
constant st22: std_logic_vector(4 downto 0) := "10100";
constant st23: std_logic_vector(4 downto 0) := "00000";
constant st24: std_logic_vector(4 downto 0) := "01101";
constant st25: std_logic_vector(4 downto 0) := "00101";
constant st26: std_logic_vector(4 downto 0) := "11001";
constant st27: std_logic_vector(4 downto 0) := "01010";
constant st28: std_logic_vector(4 downto 0) := "01110";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "---";
case current_state is
when st0 =>
if std_match(input, "000000") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st0; output <= "000";
elsif std_match(input, "000010") then next_state <= st0; output <= "000";
elsif std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st1; output <= "000";
elsif std_match(input, "001000") then next_state <= st2; output <= "000";
elsif std_match(input, "010000") then next_state <= st3; output <= "000";
elsif std_match(input, "100000") then next_state <= st4; output <= "000";
elsif std_match(input, "000101") then next_state <= st5; output <= "000";
elsif std_match(input, "001001") then next_state <= st6; output <= "000";
elsif std_match(input, "010001") then next_state <= st7; output <= "000";
elsif std_match(input, "100001") then next_state <= st8; output <= "000";
elsif std_match(input, "000110") then next_state <= st9; output <= "000";
elsif std_match(input, "001010") then next_state <= st10; output <= "000";
elsif std_match(input, "010010") then next_state <= st11; output <= "000";
elsif std_match(input, "100010") then next_state <= st12; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st15; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st14; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st31; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st30; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st16 =>
if std_match(input, "000000") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st16; output <= "000";
elsif std_match(input, "000010") then next_state <= st16; output <= "000";
elsif std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st17; output <= "000";
elsif std_match(input, "001000") then next_state <= st18; output <= "000";
elsif std_match(input, "010000") then next_state <= st19; output <= "000";
elsif std_match(input, "100000") then next_state <= st20; output <= "000";
elsif std_match(input, "000101") then next_state <= st21; output <= "000";
elsif std_match(input, "001001") then next_state <= st22; output <= "000";
elsif std_match(input, "010001") then next_state <= st23; output <= "000";
elsif std_match(input, "100001") then next_state <= st24; output <= "000";
elsif std_match(input, "000110") then next_state <= st25; output <= "000";
elsif std_match(input, "001010") then next_state <= st26; output <= "000";
elsif std_match(input, "010010") then next_state <= st27; output <= "000";
elsif std_match(input, "100010") then next_state <= st28; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st15; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st14; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st31; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st30; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st1 =>
if std_match(input, "000000") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st1; output <= "000";
elsif std_match(input, "000010") then next_state <= st1; output <= "000";
elsif std_match(input, "000011") then next_state <= st1; output <= "000";
elsif std_match(input, "100011") then next_state <= st17; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st1; output <= "010";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st17 =>
if std_match(input, "000000") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st17; output <= "000";
elsif std_match(input, "000010") then next_state <= st17; output <= "000";
elsif std_match(input, "000011") then next_state <= st1; output <= "000";
elsif std_match(input, "100011") then next_state <= st17; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st17; output <= "010";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st2 =>
if std_match(input, "000000") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st2; output <= "000";
elsif std_match(input, "000010") then next_state <= st2; output <= "000";
elsif std_match(input, "000011") then next_state <= st2; output <= "000";
elsif std_match(input, "100011") then next_state <= st18; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st2; output <= "010";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st18 =>
if std_match(input, "000000") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st18; output <= "000";
elsif std_match(input, "000010") then next_state <= st18; output <= "000";
elsif std_match(input, "000011") then next_state <= st2; output <= "000";
elsif std_match(input, "100011") then next_state <= st18; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st18; output <= "010";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st3 =>
if std_match(input, "000000") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st3; output <= "000";
elsif std_match(input, "000010") then next_state <= st3; output <= "000";
elsif std_match(input, "000011") then next_state <= st3; output <= "000";
elsif std_match(input, "100011") then next_state <= st19; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st3; output <= "010";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st19 =>
if std_match(input, "000000") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st19; output <= "000";
elsif std_match(input, "000010") then next_state <= st19; output <= "000";
elsif std_match(input, "000011") then next_state <= st3; output <= "000";
elsif std_match(input, "100011") then next_state <= st19; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st19; output <= "010";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st4 =>
if std_match(input, "000000") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st4; output <= "000";
elsif std_match(input, "000010") then next_state <= st4; output <= "000";
elsif std_match(input, "000011") then next_state <= st4; output <= "000";
elsif std_match(input, "100011") then next_state <= st20; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st4; output <= "010";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st20 =>
if std_match(input, "000000") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st20; output <= "000";
elsif std_match(input, "000010") then next_state <= st20; output <= "000";
elsif std_match(input, "000011") then next_state <= st4; output <= "000";
elsif std_match(input, "100011") then next_state <= st20; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st20; output <= "010";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st5 =>
if std_match(input, "000001") then next_state <= st0; output <= "000";
elsif std_match(input, "000000") then next_state <= st5; output <= "000";
elsif std_match(input, "000010") then next_state <= st5; output <= "000";
elsif std_match(input, "000011") then next_state <= st5; output <= "000";
elsif std_match(input, "100011") then next_state <= st21; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st5; output <= "010";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st21 =>
if std_match(input, "000001") then next_state <= st16; output <= "000";
elsif std_match(input, "000000") then next_state <= st21; output <= "000";
elsif std_match(input, "000010") then next_state <= st21; output <= "000";
elsif std_match(input, "000011") then next_state <= st5; output <= "000";
elsif std_match(input, "100011") then next_state <= st21; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st21; output <= "010";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st6 =>
if std_match(input, "000001") then next_state <= st0; output <= "000";
elsif std_match(input, "000000") then next_state <= st6; output <= "000";
elsif std_match(input, "000010") then next_state <= st6; output <= "000";
elsif std_match(input, "000011") then next_state <= st6; output <= "000";
elsif std_match(input, "100011") then next_state <= st22; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st6; output <= "010";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st22 =>
if std_match(input, "000001") then next_state <= st16; output <= "000";
elsif std_match(input, "000000") then next_state <= st22; output <= "000";
elsif std_match(input, "000010") then next_state <= st22; output <= "000";
elsif std_match(input, "000011") then next_state <= st6; output <= "000";
elsif std_match(input, "100011") then next_state <= st22; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st22; output <= "010";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st7 =>
if std_match(input, "000001") then next_state <= st0; output <= "000";
elsif std_match(input, "000000") then next_state <= st7; output <= "000";
elsif std_match(input, "000010") then next_state <= st7; output <= "000";
elsif std_match(input, "000011") then next_state <= st7; output <= "000";
elsif std_match(input, "100011") then next_state <= st23; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st7; output <= "010";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st23 =>
if std_match(input, "000001") then next_state <= st16; output <= "000";
elsif std_match(input, "000000") then next_state <= st23; output <= "000";
elsif std_match(input, "000010") then next_state <= st23; output <= "000";
elsif std_match(input, "000011") then next_state <= st7; output <= "000";
elsif std_match(input, "100011") then next_state <= st23; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st23; output <= "010";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st8 =>
if std_match(input, "000001") then next_state <= st0; output <= "000";
elsif std_match(input, "000000") then next_state <= st8; output <= "000";
elsif std_match(input, "000010") then next_state <= st8; output <= "000";
elsif std_match(input, "000011") then next_state <= st8; output <= "000";
elsif std_match(input, "100011") then next_state <= st24; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st8; output <= "010";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st24 =>
if std_match(input, "000001") then next_state <= st16; output <= "000";
elsif std_match(input, "000000") then next_state <= st24; output <= "000";
elsif std_match(input, "000010") then next_state <= st24; output <= "000";
elsif std_match(input, "000011") then next_state <= st8; output <= "000";
elsif std_match(input, "100011") then next_state <= st24; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st24; output <= "010";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st9 =>
if std_match(input, "000010") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st9; output <= "000";
elsif std_match(input, "000000") then next_state <= st9; output <= "000";
elsif std_match(input, "000011") then next_state <= st9; output <= "000";
elsif std_match(input, "100011") then next_state <= st25; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st9; output <= "010";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st25 =>
if std_match(input, "000010") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st25; output <= "000";
elsif std_match(input, "000000") then next_state <= st25; output <= "000";
elsif std_match(input, "000011") then next_state <= st9; output <= "000";
elsif std_match(input, "100011") then next_state <= st25; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st25; output <= "010";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st10 =>
if std_match(input, "000010") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st10; output <= "000";
elsif std_match(input, "000000") then next_state <= st10; output <= "000";
elsif std_match(input, "000011") then next_state <= st10; output <= "000";
elsif std_match(input, "100011") then next_state <= st26; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st10; output <= "010";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st26 =>
if std_match(input, "000010") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st26; output <= "000";
elsif std_match(input, "000000") then next_state <= st26; output <= "000";
elsif std_match(input, "000011") then next_state <= st10; output <= "000";
elsif std_match(input, "100011") then next_state <= st26; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st26; output <= "010";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st11 =>
if std_match(input, "000010") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st11; output <= "000";
elsif std_match(input, "000000") then next_state <= st11; output <= "000";
elsif std_match(input, "000011") then next_state <= st11; output <= "000";
elsif std_match(input, "100011") then next_state <= st27; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st11; output <= "010";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st27 =>
if std_match(input, "000010") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st27; output <= "000";
elsif std_match(input, "000000") then next_state <= st27; output <= "000";
elsif std_match(input, "000011") then next_state <= st11; output <= "000";
elsif std_match(input, "100011") then next_state <= st27; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st27; output <= "010";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st12 =>
if std_match(input, "000010") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st12; output <= "000";
elsif std_match(input, "000000") then next_state <= st12; output <= "000";
elsif std_match(input, "000011") then next_state <= st12; output <= "000";
elsif std_match(input, "100011") then next_state <= st28; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st12; output <= "010";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st28 =>
if std_match(input, "000010") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st28; output <= "000";
elsif std_match(input, "000000") then next_state <= st28; output <= "000";
elsif std_match(input, "000011") then next_state <= st12; output <= "000";
elsif std_match(input, "100011") then next_state <= st28; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st28; output <= "010";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st13 =>
if std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st13; output <= "100";
elsif std_match(input, "000010") then next_state <= st13; output <= "100";
elsif std_match(input, "000000") then next_state <= st13; output <= "100";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st29 =>
if std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st29; output <= "100";
elsif std_match(input, "000010") then next_state <= st29; output <= "100";
elsif std_match(input, "000000") then next_state <= st29; output <= "100";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st15 =>
if std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st15; output <= "000";
elsif std_match(input, "000010") then next_state <= st15; output <= "000";
elsif std_match(input, "000000") then next_state <= st15; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st15; output <= "011";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st31; output <= "011";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st31 =>
if std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st31; output <= "000";
elsif std_match(input, "000010") then next_state <= st31; output <= "000";
elsif std_match(input, "000000") then next_state <= st31; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st15; output <= "011";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st31; output <= "011";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st14 =>
if std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st14; output <= "000";
elsif std_match(input, "000010") then next_state <= st14; output <= "000";
elsif std_match(input, "000000") then next_state <= st14; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st14; output <= "001";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st30; output <= "001";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st30 =>
if std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st30; output <= "000";
elsif std_match(input, "000010") then next_state <= st30; output <= "000";
elsif std_match(input, "000000") then next_state <= st30; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st14; output <= "001";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st30; output <= "001";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when others => next_state <= "-----"; output <= "---";
end case;
end process;
end behaviour;
| agpl-3.0 | 4f8ced30871310bc97df802cbb944ab7 | 0.590811 | 3.336744 | false | false | false | false |
es17m014/vhdl-counter | src/vhdl/x7seg.vhd | 1 | 2,369 | -------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : x7seg.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: 7 Segment display test with 1 kHz refreshrate
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 24.10.2017 0.1 Martin Angermair init
-- 19.11.2017 1.0 Martin Angermair final version
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
architecture rtl of x7seg is
component gen_counter is
generic(N : integer := 8);
port(
clk_i : in std_logic;
reset_i : in std_logic;
count_o : out std_logic_vector(N-1 downto 0));
end component;
component mux44to1 is
port (
digits_i : in std_logic_vector(15 downto 0);
sel_i : in std_logic_vector(1 downto 0);
digit_o : out std_logic_vector(3 downto 0));
end component;
component ancode is
port (
sel_i : in std_logic_vector(1 downto 0);
aen_i : in std_logic_vector(3 downto 0);
ss_sel_o : out std_logic_vector(3 downto 0));
end component;
component hex7seg is
port(
digit_i : in std_logic_vector(3 downto 0);
ss_o : out std_logic_vector(6 downto 0));
end component;
signal s_sel : std_logic_vector(1 downto 0);
signal s_digit : std_logic_vector(3 downto 0);
signal s_count : std_logic_vector(1 downto 0);
begin
s_sel <= s_count;
ss_o(7) <= '1'; -- turn off the decimal point
p_gen_counter: gen_counter
generic map (
N => 2)
port map (
clk_i => clk_i,
reset_i => reset_i,
count_o => s_count);
p_mux44to1: mux44to1
port map (
digits_i => digits_i,
sel_i => s_sel,
digit_o => s_digit);
p_ancode: ancode
port map (
sel_i => s_sel,
aen_i => aen_i,
ss_sel_o => ss_sel_o);
p_hex7seg: hex7seg
port map (
digit_i => s_digit,
ss_o => ss_o(6 downto 0));
end rtl; | mit | 5999c6e00765b931efdccbca92984534 | 0.491769 | 3.695788 | false | false | false | false |
chastell/art-decomp | kiss/kirkman_hot.vhd | 1 | 36,115 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity kirkman_hot is
port(
clock: in std_logic;
input: in std_logic_vector(11 downto 0);
output: out std_logic_vector(5 downto 0)
);
end kirkman_hot;
architecture behaviour of kirkman_hot is
constant rst0: std_logic_vector(15 downto 0) := "1000000000000000";
constant bit1: std_logic_vector(15 downto 0) := "0100000000000000";
constant bit2: std_logic_vector(15 downto 0) := "0010000000000000";
constant bit3: std_logic_vector(15 downto 0) := "0001000000000000";
constant bit4: std_logic_vector(15 downto 0) := "0000100000000000";
constant bit5: std_logic_vector(15 downto 0) := "0000010000000000";
constant bit6: std_logic_vector(15 downto 0) := "0000001000000000";
constant bit7: std_logic_vector(15 downto 0) := "0000000100000000";
constant bit8: std_logic_vector(15 downto 0) := "0000000010000000";
constant bit9: std_logic_vector(15 downto 0) := "0000000001000000";
constant bitA: std_logic_vector(15 downto 0) := "0000000000100000";
constant bitB: std_logic_vector(15 downto 0) := "0000000000010000";
constant bitC: std_logic_vector(15 downto 0) := "0000000000001000";
constant bitD: std_logic_vector(15 downto 0) := "0000000000000100";
constant bitE: std_logic_vector(15 downto 0) := "0000000000000010";
constant bitF: std_logic_vector(15 downto 0) := "0000000000000001";
signal current_state, next_state: std_logic_vector(15 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----------------"; output <= "------";
if std_match(input, "--------1---") then next_state <= rst0; output <= "1-----";
else
case current_state is
when rst0 =>
if std_match(input, "--------0000") then next_state <= rst0; output <= "0----0";
elsif std_match(input, "--------0001") then next_state <= bit1; output <= "0---00";
elsif std_match(input, "-----0--0111") then next_state <= bit1; output <= "0--010";
elsif std_match(input, "-----1--0111") then next_state <= bit1; output <= "0--110";
elsif std_match(input, "--------0010") then next_state <= bit1; output <= "0---00";
elsif std_match(input, "--------0100") then next_state <= bit1; output <= "0---00";
end if;
when bit1 =>
if std_match(input, "--------0001") then next_state <= bit2; output <= "0---10";
elsif std_match(input, "-----0--0111") then next_state <= bit2; output <= "0--010";
elsif std_match(input, "-----1--0111") then next_state <= bit2; output <= "0--110";
elsif std_match(input, "--------0010") then next_state <= bit2; output <= "0---00";
elsif std_match(input, "--------0100") then next_state <= bit2; output <= "0---00";
end if;
when bit2 =>
if std_match(input, "--------0001") then next_state <= bit3; output <= "0---00";
elsif std_match(input, "-----0--0111") then next_state <= bit3; output <= "0--000";
elsif std_match(input, "-----1--0111") then next_state <= bit3; output <= "0--100";
elsif std_match(input, "--------0010") then next_state <= bit3; output <= "0---10";
elsif std_match(input, "--------0100") then next_state <= bit3; output <= "0---10";
end if;
when bit3 =>
if std_match(input, "0-------0001") then next_state <= bit4; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bit4; output <= "1---10";
elsif std_match(input, "-00--00-0111") then next_state <= bit4; output <= "100000";
elsif std_match(input, "-01--00-0111") then next_state <= bit4; output <= "100010";
elsif std_match(input, "-10--00-0111") then next_state <= bit4; output <= "100010";
elsif std_match(input, "-11--00-0111") then next_state <= bit4; output <= "110000";
elsif std_match(input, "-00--01-0111") then next_state <= bit4; output <= "101000";
elsif std_match(input, "-01--01-0111") then next_state <= bit4; output <= "100010";
elsif std_match(input, "-10--01-0111") then next_state <= bit4; output <= "100010";
elsif std_match(input, "-11--01-0111") then next_state <= bit4; output <= "111000";
elsif std_match(input, "-----10-0111") then next_state <= bit4; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bit4; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bit4; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bit4; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bit4; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bit4; output <= "1---10";
end if;
when bit4 =>
if std_match(input, "0-------0001") then next_state <= bit5; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bit5; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bit5; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bit5; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bit5; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bit5; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bit5; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bit5; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bit5; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bit5; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bit5; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bit5; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bit5; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bit5; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bit5; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bit5; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bit5; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bit5; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bit5; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bit5; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bit5; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bit5; output <= "1---10";
end if;
when bit5 =>
if std_match(input, "0-------0001") then next_state <= bit6; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bit6; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bit6; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bit6; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bit6; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bit6; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bit6; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bit6; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bit6; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bit6; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bit6; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bit6; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bit6; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bit6; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bit6; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bit6; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bit6; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bit6; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bit6; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bit6; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bit6; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bit6; output <= "1---10";
end if;
when bit6 =>
if std_match(input, "0-------0001") then next_state <= bit7; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bit7; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bit7; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bit7; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bit7; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bit7; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bit7; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bit7; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bit7; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bit7; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bit7; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bit7; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bit7; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bit7; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bit7; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bit7; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bit7; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bit7; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bit7; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bit7; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bit7; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bit7; output <= "1---10";
end if;
when bit7 =>
if std_match(input, "0-------0001") then next_state <= bit8; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bit8; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bit8; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bit8; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bit8; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bit8; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bit8; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bit8; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bit8; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bit8; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bit8; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bit8; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bit8; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bit8; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bit8; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bit8; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bit8; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bit8; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bit8; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bit8; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bit8; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bit8; output <= "1---10";
end if;
when bit8 =>
if std_match(input, "0-------0001") then next_state <= bit9; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bit9; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bit9; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bit9; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bit9; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bit9; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bit9; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bit9; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bit9; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bit9; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bit9; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bit9; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bit9; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bit9; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bit9; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bit9; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bit9; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bit9; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bit9; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bit9; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bit9; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bit9; output <= "1---10";
end if;
when bit9 =>
if std_match(input, "0-------0001") then next_state <= bitA; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bitA; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bitA; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bitA; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bitA; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bitA; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bitA; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bitA; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bitA; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bitA; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bitA; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bitA; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bitA; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bitA; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bitA; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bitA; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bitA; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bitA; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bitA; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bitA; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bitA; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bitA; output <= "1---10";
end if;
when bitA =>
if std_match(input, "0-------0001") then next_state <= bitB; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bitB; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bitB; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bitB; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bitB; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bitB; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bitB; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bitB; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bitB; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bitB; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bitB; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bitB; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bitB; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bitB; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bitB; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bitB; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bitB; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bitB; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bitB; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bitB; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bitB; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bitB; output <= "1---10";
end if;
when bitB =>
if std_match(input, "--------0001") then next_state <= bitC; output <= "0---00";
elsif std_match(input, "--0000--0111") then next_state <= bitC; output <= "000000";
elsif std_match(input, "--0100--0111") then next_state <= bitC; output <= "000010";
elsif std_match(input, "--1000--0111") then next_state <= bitC; output <= "000010";
elsif std_match(input, "--1100--0111") then next_state <= bitC; output <= "010000";
elsif std_match(input, "--0010--0111") then next_state <= bitC; output <= "001000";
elsif std_match(input, "--0110--0111") then next_state <= bitC; output <= "000010";
elsif std_match(input, "--1010--0111") then next_state <= bitC; output <= "000010";
elsif std_match(input, "--1110--0111") then next_state <= bitC; output <= "011000";
elsif std_match(input, "-----1--0111") then next_state <= bitC; output <= "0--100";
elsif std_match(input, "--------0010") then next_state <= bitC; output <= "0---00";
elsif std_match(input, "--------0100") then next_state <= bitC; output <= "0---00";
end if;
when bitC =>
if std_match(input, "--------0001") then next_state <= bitD; output <= "0---00";
elsif std_match(input, "--0000--0111") then next_state <= bitD; output <= "000000";
elsif std_match(input, "--0100--0111") then next_state <= bitD; output <= "000010";
elsif std_match(input, "--1000--0111") then next_state <= bitD; output <= "000010";
elsif std_match(input, "--1100--0111") then next_state <= bitD; output <= "010000";
elsif std_match(input, "--0010--0111") then next_state <= bitD; output <= "001000";
elsif std_match(input, "--0110--0111") then next_state <= bitD; output <= "000010";
elsif std_match(input, "--1010--0111") then next_state <= bitD; output <= "000010";
elsif std_match(input, "--1110--0111") then next_state <= bitD; output <= "011000";
elsif std_match(input, "-----1--0111") then next_state <= bitD; output <= "0--100";
elsif std_match(input, "--------0010") then next_state <= bitD; output <= "0---00";
elsif std_match(input, "--------0100") then next_state <= bitD; output <= "0---00";
end if;
when bitD =>
if std_match(input, "--------0001") then next_state <= bitE; output <= "0---00";
elsif std_match(input, "--0000--0111") then next_state <= bitE; output <= "000000";
elsif std_match(input, "--0100--0111") then next_state <= bitE; output <= "000010";
elsif std_match(input, "--1000--0111") then next_state <= bitE; output <= "000010";
elsif std_match(input, "--1100--0111") then next_state <= bitE; output <= "010000";
elsif std_match(input, "--0010--0111") then next_state <= bitE; output <= "001000";
elsif std_match(input, "--0110--0111") then next_state <= bitE; output <= "000010";
elsif std_match(input, "--1010--0111") then next_state <= bitE; output <= "000010";
elsif std_match(input, "--1110--0111") then next_state <= bitE; output <= "011000";
elsif std_match(input, "-----1--0111") then next_state <= bitE; output <= "0--100";
elsif std_match(input, "--------0010") then next_state <= bitE; output <= "0---00";
elsif std_match(input, "--------0100") then next_state <= bitE; output <= "0---00";
end if;
when bitE =>
if std_match(input, "--------0001") then next_state <= bitF; output <= "0---01";
elsif std_match(input, "--0000--0111") then next_state <= bitF; output <= "000001";
elsif std_match(input, "--0100--0111") then next_state <= bitF; output <= "000011";
elsif std_match(input, "--1000--0111") then next_state <= bitF; output <= "000011";
elsif std_match(input, "--1100--0111") then next_state <= bitF; output <= "010001";
elsif std_match(input, "--0010--0111") then next_state <= bitF; output <= "001100";
elsif std_match(input, "--0110--0111") then next_state <= bitF; output <= "000011";
elsif std_match(input, "--1010--0111") then next_state <= bitF; output <= "000011";
elsif std_match(input, "--1110--0111") then next_state <= bitF; output <= "011001";
elsif std_match(input, "-----1--0111") then next_state <= bitF; output <= "0--001";
elsif std_match(input, "--------0010") then next_state <= bitF; output <= "0---01";
elsif std_match(input, "--------0100") then next_state <= bitF; output <= "0---01";
end if;
when bitF =>
if std_match(input, "--------0001") then next_state <= rst0; output <= "0---00";
elsif std_match(input, "---0-0--0111") then next_state <= rst0; output <= "0--000";
elsif std_match(input, "---1-0--0111") then next_state <= rst0; output <= "0--010";
elsif std_match(input, "-----1--0111") then next_state <= rst0; output <= "0--100";
elsif std_match(input, "--------0010") then next_state <= rst0; output <= "0---00";
elsif std_match(input, "--------0100") then next_state <= rst0; output <= "0---00";
end if;
when others => next_state <= "----------------"; output <= "------";
end case;
end if;
end process;
end behaviour;
| agpl-3.0 | 36307378654d3d4a73952cf40b26c6f9 | 0.594102 | 3.544509 | false | false | false | false |
chastell/art-decomp | kiss/kirkman_rnd.vhd | 1 | 35,882 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity kirkman_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(11 downto 0);
output: out std_logic_vector(5 downto 0)
);
end kirkman_rnd;
architecture behaviour of kirkman_rnd is
constant rst0: std_logic_vector(3 downto 0) := "1101";
constant bit1: std_logic_vector(3 downto 0) := "0010";
constant bit2: std_logic_vector(3 downto 0) := "1011";
constant bit3: std_logic_vector(3 downto 0) := "1110";
constant bit4: std_logic_vector(3 downto 0) := "1111";
constant bit5: std_logic_vector(3 downto 0) := "0001";
constant bit6: std_logic_vector(3 downto 0) := "0110";
constant bit7: std_logic_vector(3 downto 0) := "0000";
constant bit8: std_logic_vector(3 downto 0) := "1010";
constant bit9: std_logic_vector(3 downto 0) := "1000";
constant bitA: std_logic_vector(3 downto 0) := "0100";
constant bitB: std_logic_vector(3 downto 0) := "1001";
constant bitC: std_logic_vector(3 downto 0) := "1100";
constant bitD: std_logic_vector(3 downto 0) := "0011";
constant bitE: std_logic_vector(3 downto 0) := "0111";
constant bitF: std_logic_vector(3 downto 0) := "0101";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "------";
if std_match(input, "--------1---") then next_state <= rst0; output <= "1-----";
else
case current_state is
when rst0 =>
if std_match(input, "--------0000") then next_state <= rst0; output <= "0----0";
elsif std_match(input, "--------0001") then next_state <= bit1; output <= "0---00";
elsif std_match(input, "-----0--0111") then next_state <= bit1; output <= "0--010";
elsif std_match(input, "-----1--0111") then next_state <= bit1; output <= "0--110";
elsif std_match(input, "--------0010") then next_state <= bit1; output <= "0---00";
elsif std_match(input, "--------0100") then next_state <= bit1; output <= "0---00";
end if;
when bit1 =>
if std_match(input, "--------0001") then next_state <= bit2; output <= "0---10";
elsif std_match(input, "-----0--0111") then next_state <= bit2; output <= "0--010";
elsif std_match(input, "-----1--0111") then next_state <= bit2; output <= "0--110";
elsif std_match(input, "--------0010") then next_state <= bit2; output <= "0---00";
elsif std_match(input, "--------0100") then next_state <= bit2; output <= "0---00";
end if;
when bit2 =>
if std_match(input, "--------0001") then next_state <= bit3; output <= "0---00";
elsif std_match(input, "-----0--0111") then next_state <= bit3; output <= "0--000";
elsif std_match(input, "-----1--0111") then next_state <= bit3; output <= "0--100";
elsif std_match(input, "--------0010") then next_state <= bit3; output <= "0---10";
elsif std_match(input, "--------0100") then next_state <= bit3; output <= "0---10";
end if;
when bit3 =>
if std_match(input, "0-------0001") then next_state <= bit4; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bit4; output <= "1---10";
elsif std_match(input, "-00--00-0111") then next_state <= bit4; output <= "100000";
elsif std_match(input, "-01--00-0111") then next_state <= bit4; output <= "100010";
elsif std_match(input, "-10--00-0111") then next_state <= bit4; output <= "100010";
elsif std_match(input, "-11--00-0111") then next_state <= bit4; output <= "110000";
elsif std_match(input, "-00--01-0111") then next_state <= bit4; output <= "101000";
elsif std_match(input, "-01--01-0111") then next_state <= bit4; output <= "100010";
elsif std_match(input, "-10--01-0111") then next_state <= bit4; output <= "100010";
elsif std_match(input, "-11--01-0111") then next_state <= bit4; output <= "111000";
elsif std_match(input, "-----10-0111") then next_state <= bit4; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bit4; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bit4; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bit4; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bit4; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bit4; output <= "1---10";
end if;
when bit4 =>
if std_match(input, "0-------0001") then next_state <= bit5; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bit5; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bit5; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bit5; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bit5; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bit5; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bit5; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bit5; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bit5; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bit5; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bit5; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bit5; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bit5; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bit5; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bit5; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bit5; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bit5; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bit5; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bit5; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bit5; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bit5; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bit5; output <= "1---10";
end if;
when bit5 =>
if std_match(input, "0-------0001") then next_state <= bit6; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bit6; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bit6; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bit6; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bit6; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bit6; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bit6; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bit6; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bit6; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bit6; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bit6; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bit6; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bit6; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bit6; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bit6; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bit6; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bit6; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bit6; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bit6; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bit6; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bit6; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bit6; output <= "1---10";
end if;
when bit6 =>
if std_match(input, "0-------0001") then next_state <= bit7; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bit7; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bit7; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bit7; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bit7; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bit7; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bit7; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bit7; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bit7; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bit7; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bit7; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bit7; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bit7; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bit7; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bit7; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bit7; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bit7; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bit7; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bit7; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bit7; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bit7; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bit7; output <= "1---10";
end if;
when bit7 =>
if std_match(input, "0-------0001") then next_state <= bit8; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bit8; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bit8; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bit8; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bit8; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bit8; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bit8; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bit8; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bit8; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bit8; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bit8; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bit8; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bit8; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bit8; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bit8; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bit8; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bit8; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bit8; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bit8; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bit8; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bit8; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bit8; output <= "1---10";
end if;
when bit8 =>
if std_match(input, "0-------0001") then next_state <= bit9; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bit9; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bit9; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bit9; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bit9; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bit9; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bit9; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bit9; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bit9; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bit9; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bit9; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bit9; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bit9; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bit9; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bit9; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bit9; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bit9; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bit9; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bit9; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bit9; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bit9; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bit9; output <= "1---10";
end if;
when bit9 =>
if std_match(input, "0-------0001") then next_state <= bitA; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bitA; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bitA; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bitA; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bitA; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bitA; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bitA; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bitA; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bitA; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bitA; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bitA; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bitA; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bitA; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bitA; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bitA; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bitA; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bitA; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bitA; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bitA; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bitA; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bitA; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bitA; output <= "1---10";
end if;
when bitA =>
if std_match(input, "0-------0001") then next_state <= bitB; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bitB; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bitB; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bitB; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bitB; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bitB; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bitB; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bitB; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bitB; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bitB; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bitB; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bitB; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bitB; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bitB; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bitB; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bitB; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bitB; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bitB; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bitB; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bitB; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bitB; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bitB; output <= "1---10";
end if;
when bitB =>
if std_match(input, "--------0001") then next_state <= bitC; output <= "0---00";
elsif std_match(input, "--0000--0111") then next_state <= bitC; output <= "000000";
elsif std_match(input, "--0100--0111") then next_state <= bitC; output <= "000010";
elsif std_match(input, "--1000--0111") then next_state <= bitC; output <= "000010";
elsif std_match(input, "--1100--0111") then next_state <= bitC; output <= "010000";
elsif std_match(input, "--0010--0111") then next_state <= bitC; output <= "001000";
elsif std_match(input, "--0110--0111") then next_state <= bitC; output <= "000010";
elsif std_match(input, "--1010--0111") then next_state <= bitC; output <= "000010";
elsif std_match(input, "--1110--0111") then next_state <= bitC; output <= "011000";
elsif std_match(input, "-----1--0111") then next_state <= bitC; output <= "0--100";
elsif std_match(input, "--------0010") then next_state <= bitC; output <= "0---00";
elsif std_match(input, "--------0100") then next_state <= bitC; output <= "0---00";
end if;
when bitC =>
if std_match(input, "--------0001") then next_state <= bitD; output <= "0---00";
elsif std_match(input, "--0000--0111") then next_state <= bitD; output <= "000000";
elsif std_match(input, "--0100--0111") then next_state <= bitD; output <= "000010";
elsif std_match(input, "--1000--0111") then next_state <= bitD; output <= "000010";
elsif std_match(input, "--1100--0111") then next_state <= bitD; output <= "010000";
elsif std_match(input, "--0010--0111") then next_state <= bitD; output <= "001000";
elsif std_match(input, "--0110--0111") then next_state <= bitD; output <= "000010";
elsif std_match(input, "--1010--0111") then next_state <= bitD; output <= "000010";
elsif std_match(input, "--1110--0111") then next_state <= bitD; output <= "011000";
elsif std_match(input, "-----1--0111") then next_state <= bitD; output <= "0--100";
elsif std_match(input, "--------0010") then next_state <= bitD; output <= "0---00";
elsif std_match(input, "--------0100") then next_state <= bitD; output <= "0---00";
end if;
when bitD =>
if std_match(input, "--------0001") then next_state <= bitE; output <= "0---00";
elsif std_match(input, "--0000--0111") then next_state <= bitE; output <= "000000";
elsif std_match(input, "--0100--0111") then next_state <= bitE; output <= "000010";
elsif std_match(input, "--1000--0111") then next_state <= bitE; output <= "000010";
elsif std_match(input, "--1100--0111") then next_state <= bitE; output <= "010000";
elsif std_match(input, "--0010--0111") then next_state <= bitE; output <= "001000";
elsif std_match(input, "--0110--0111") then next_state <= bitE; output <= "000010";
elsif std_match(input, "--1010--0111") then next_state <= bitE; output <= "000010";
elsif std_match(input, "--1110--0111") then next_state <= bitE; output <= "011000";
elsif std_match(input, "-----1--0111") then next_state <= bitE; output <= "0--100";
elsif std_match(input, "--------0010") then next_state <= bitE; output <= "0---00";
elsif std_match(input, "--------0100") then next_state <= bitE; output <= "0---00";
end if;
when bitE =>
if std_match(input, "--------0001") then next_state <= bitF; output <= "0---01";
elsif std_match(input, "--0000--0111") then next_state <= bitF; output <= "000001";
elsif std_match(input, "--0100--0111") then next_state <= bitF; output <= "000011";
elsif std_match(input, "--1000--0111") then next_state <= bitF; output <= "000011";
elsif std_match(input, "--1100--0111") then next_state <= bitF; output <= "010001";
elsif std_match(input, "--0010--0111") then next_state <= bitF; output <= "001100";
elsif std_match(input, "--0110--0111") then next_state <= bitF; output <= "000011";
elsif std_match(input, "--1010--0111") then next_state <= bitF; output <= "000011";
elsif std_match(input, "--1110--0111") then next_state <= bitF; output <= "011001";
elsif std_match(input, "-----1--0111") then next_state <= bitF; output <= "0--001";
elsif std_match(input, "--------0010") then next_state <= bitF; output <= "0---01";
elsif std_match(input, "--------0100") then next_state <= bitF; output <= "0---01";
end if;
when bitF =>
if std_match(input, "--------0001") then next_state <= rst0; output <= "0---00";
elsif std_match(input, "---0-0--0111") then next_state <= rst0; output <= "0--000";
elsif std_match(input, "---1-0--0111") then next_state <= rst0; output <= "0--010";
elsif std_match(input, "-----1--0111") then next_state <= rst0; output <= "0--100";
elsif std_match(input, "--------0010") then next_state <= rst0; output <= "0---00";
elsif std_match(input, "--------0100") then next_state <= rst0; output <= "0---00";
end if;
when others => next_state <= "----"; output <= "------";
end case;
end if;
end process;
end behaviour;
| agpl-3.0 | 24da80ba264815d08b1dabbcf4cd5ec6 | 0.592135 | 3.521641 | false | false | false | false |
chastell/art-decomp | kiss/mc_rnd.vhd | 1 | 1,790 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity mc_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(2 downto 0);
output: out std_logic_vector(4 downto 0)
);
end mc_rnd;
architecture behaviour of mc_rnd is
constant HG: std_logic_vector(1 downto 0) := "01";
constant HY: std_logic_vector(1 downto 0) := "10";
constant FG: std_logic_vector(1 downto 0) := "11";
constant FY: std_logic_vector(1 downto 0) := "00";
signal current_state, next_state: std_logic_vector(1 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--"; output <= "-----";
case current_state is
when HG =>
if std_match(input, "0--") then next_state <= HG; output <= "00010";
elsif std_match(input, "-0-") then next_state <= HG; output <= "00010";
elsif std_match(input, "11-") then next_state <= HY; output <= "10010";
end if;
when HY =>
if std_match(input, "--0") then next_state <= HY; output <= "00110";
elsif std_match(input, "--1") then next_state <= FG; output <= "10110";
end if;
when FG =>
if std_match(input, "10-") then next_state <= FG; output <= "01000";
elsif std_match(input, "0--") then next_state <= FY; output <= "11000";
elsif std_match(input, "-1-") then next_state <= FY; output <= "11000";
end if;
when FY =>
if std_match(input, "--0") then next_state <= FY; output <= "01001";
elsif std_match(input, "--1") then next_state <= HG; output <= "11001";
end if;
when others => next_state <= "--"; output <= "-----";
end case;
end process;
end behaviour;
| agpl-3.0 | 9f97b9091972186846f76692f27bc96d | 0.584916 | 3.396584 | false | false | false | false |
chastell/art-decomp | kiss/bbsse_nov.vhd | 1 | 6,983 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity bbsse_nov is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(6 downto 0)
);
end bbsse_nov;
architecture behaviour of bbsse_nov is
constant st0: std_logic_vector(3 downto 0) := "1100";
constant st1: std_logic_vector(3 downto 0) := "0000";
constant st2: std_logic_vector(3 downto 0) := "0111";
constant st3: std_logic_vector(3 downto 0) := "0001";
constant st4: std_logic_vector(3 downto 0) := "0110";
constant st5: std_logic_vector(3 downto 0) := "0011";
constant st6: std_logic_vector(3 downto 0) := "0101";
constant st7: std_logic_vector(3 downto 0) := "0100";
constant st8: std_logic_vector(3 downto 0) := "1011";
constant st9: std_logic_vector(3 downto 0) := "1010";
constant st10: std_logic_vector(3 downto 0) := "0010";
constant st11: std_logic_vector(3 downto 0) := "1101";
constant st12: std_logic_vector(3 downto 0) := "1001";
constant st13: std_logic_vector(3 downto 0) := "1000";
constant st14: std_logic_vector(3 downto 0) := "1111";
constant st15: std_logic_vector(3 downto 0) := "1110";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "-------";
case current_state is
when st0 =>
if std_match(input, "0------") then next_state <= st0; output <= "0000000";
elsif std_match(input, "10----0") then next_state <= st1; output <= "00110-0";
elsif std_match(input, "10----1") then next_state <= st1; output <= "00010-0";
elsif std_match(input, "11----0") then next_state <= st11; output <= "0011010";
elsif std_match(input, "11----1") then next_state <= st11; output <= "0001010";
end if;
when st1 =>
if std_match(input, "100----") then next_state <= st1; output <= "00000-0";
elsif std_match(input, "101-1--") then next_state <= st4; output <= "10000-0";
elsif std_match(input, "101-0--") then next_state <= st2; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st2 =>
if std_match(input, "10-----") then next_state <= st3; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st3 =>
if std_match(input, "10--0--") then next_state <= st2; output <= "10000-0";
elsif std_match(input, "10--1--") then next_state <= st4; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st4 =>
if std_match(input, "10-----") then next_state <= st5; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st5 =>
if std_match(input, "10-1---") then next_state <= st4; output <= "10000-0";
elsif std_match(input, "10--1--") then next_state <= st4; output <= "10000-0";
elsif std_match(input, "10-00--") then next_state <= st6; output <= "0100010";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st6 =>
if std_match(input, "10---0-") then next_state <= st6; output <= "0100000";
elsif std_match(input, "10---1-") then next_state <= st7; output <= "01000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st7 =>
if std_match(input, "10-----") then next_state <= st8; output <= "0000010";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st8 =>
if std_match(input, "10---0-") then next_state <= st8; output <= "0000000";
elsif std_match(input, "10---1-") then next_state <= st9; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st9 =>
if std_match(input, "10-----") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st10 =>
if std_match(input, "1001---") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "10-01--") then next_state <= st1; output <= "00010-0";
elsif std_match(input, "10-00--") then next_state <= st6; output <= "0100010";
elsif std_match(input, "1011---") then next_state <= st9; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st11 =>
if std_match(input, "0----0-") then next_state <= st11; output <= "000--00";
elsif std_match(input, "11---0-") then next_state <= st11; output <= "0000000";
elsif std_match(input, "0----1-") then next_state <= st0; output <= "000---1";
elsif std_match(input, "10-----") then next_state <= st1; output <= "00000-0";
elsif std_match(input, "11---1-") then next_state <= st12; output <= "00001-0";
end if;
when st12 =>
if std_match(input, "11-----") then next_state <= st12; output <= "00001-0";
elsif std_match(input, "10-----") then next_state <= st1; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
end if;
when st13 =>
if std_match(input, "0------") then next_state <= st11; output <= "000--10";
end if;
when st14 =>
if std_match(input, "0------") then next_state <= st11; output <= "000--10";
end if;
when st15 =>
if std_match(input, "0------") then next_state <= st11; output <= "000--10";
end if;
when others => next_state <= "----"; output <= "-------";
end case;
end process;
end behaviour;
| agpl-3.0 | 44cf826c717d873eeca870c51b93f170 | 0.561363 | 3.323655 | false | false | false | false |
ibm2030/IBM2030 | clock_management.vhd | 1 | 4,697 | --*****************************************************************************************
--**
--** Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are
--** provided to you "as is". Xilinx and its licensors make and you
--** receive no warranties or conditions, express, implied, statutory
--** or otherwise, and Xilinx specifically disclaims any implied
--** warranties of merchantability, non-infringement, or fitness for a
--** particular purpose. Xilinx does not warrant that the functions
--** contained in these designs will meet your requirements, or that the
--** operation of these designs will be uninterrupted or error free, or
--** that defects in the Designs will be corrected. Furthermore, Xilinx
--** does not warrant or make any representations regarding use or the
--** results of the use of the designs in terms of correctness, accuracy,
--** reliability, or otherwise.
--**
--** LIMITATION OF LIABILITY. In no event will Xilinx or its licensors be
--** liable for any loss of data, lost profits, cost or procurement of
--** substitute goods or services, or for any special, incidental,
--** consequential, or indirect damages arising from the use or operation
--** of the designs or accompanying documentation, however caused and on
--** any theory of liability. This limitation will apply even if Xilinx
--** has been advised of the possibility of such damage. This limitation
--** shall apply not-withstanding the failure of the essential purpose of
--** any limited remedies herein.
--**
--*****************************************************************************************
-- MODULE : clock_management.vhd
-- AUTHOR : Stephan Neuhold
-- VERSION : v1.00
--
--
-- REVISION HISTORY:
-- -----------------
-- No revisions
--
--
-- FUNCTION DESCRIPTION:
-- ---------------------
-- This module generates an enable signal for
-- the shift register and comparator. It also
-- generates the clock signal that is connected
-- to the PROM.
-- The enable and clock signals are generated
-- based on the "frequency" generic entered for
-- the system clock.
-- The clock signal is only generated at the
-- appropriate times. All other states the clock
-- signal is kept at a logic high. The PROMs
-- address counter only increments on a rising
-- edge of this clock.
--***************************
--* Library declarations
--***************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
--***********************
--* Entity declaration
--***********************
entity clock_management is
generic(
length : integer := 5;
frequency : integer := 50
);
port(
clock : in std_logic;
enable : in std_logic;
read_enable : out std_logic;
cclk : out std_logic
);
end clock_management;
architecture Behavioral of clock_management is
signal cclk_int : std_logic := '1';
signal enable_cclk : std_logic;
signal SRL_length : std_logic_vector(3 downto 0);
signal temp : integer := (frequency / 20) - 1;
begin
--***************************************************
--* The length of the SRL16 is based on the system
--* clock frequency entered. This frequency is then
--* "divided" down to approximately 10MHz.
--***************************************************
SRL_length <= conv_std_logic_vector(temp, length - 1);
Divider0: SRL16
generic map(
init => X"0001"
)
port map(
clk => clock,
d => enable_cclk,
a0 => SRL_length(0),
a1 => SRL_length(1),
a2 => SRL_length(2),
a3 => SRL_length(3),
q => enable_cclk
);
--***************************************************
--* This process generates the enable signal for
--* the shift register and the comparator. It also
--* generates the clock signal used to increment
--* the PROMs address counter.
--***************************************************
process(clock, enable_cclk, enable, cclk_int)
begin
if rising_edge(clock) then
if (enable = '1') then
if (enable_cclk = '1') then
cclk_int <= not cclk_int;
end if;
if (enable_cclk = '1' and cclk_int = '1') then
read_enable <= '1';
else
read_enable <= '0';
end if;
else
cclk_int <= '1';
end if;
end if;
cclk <= cclk_int;
end process;
end Behavioral;
| gpl-3.0 | 3d4086127f0bdd8ebd11baeb4d8154c1 | 0.559293 | 4.105769 | false | false | false | false |
LucasMahieu/TP_secu | code/AES/vhd/vhd/X2Time.vhd | 2 | 589 |
-- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
-- Component Declaration
entity x2time is port (
b_in : in std_logic_vector (7 downto 0);
b_out : out std_logic_vector (7 downto 0) ) ;
end x2time;
-- Architecture of the Component
architecture a_x2time of x2time is
begin
b_out(7) <= b_in(5);
b_out(6) <= b_in(4);
b_out(5) <= b_in(3) xor b_in(7);
b_out(4) <= b_in(2) xor b_in(6) xor b_in(7);
b_out(3) <= b_in(1) xor b_in(6);
b_out(2) <= b_in(0) xor b_in(7);
b_out(1) <= b_in(6) xor b_in(7);
b_out(0) <= b_in(6);
end a_x2time;
| mit | f0aa2c9360ffaa1c47e50cbc30087b95 | 0.573854 | 2.291829 | false | false | false | false |
chastell/art-decomp | kiss/ex4_jed.vhd | 1 | 3,706 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex4_jed is
port(
clock: in std_logic;
input: in std_logic_vector(5 downto 0);
output: out std_logic_vector(8 downto 0)
);
end ex4_jed;
architecture behaviour of ex4_jed is
constant s1: std_logic_vector(3 downto 0) := "1100";
constant s3: std_logic_vector(3 downto 0) := "0001";
constant s2: std_logic_vector(3 downto 0) := "1011";
constant s5: std_logic_vector(3 downto 0) := "0010";
constant s7: std_logic_vector(3 downto 0) := "0101";
constant s11: std_logic_vector(3 downto 0) := "0111";
constant s12: std_logic_vector(3 downto 0) := "1000";
constant s8: std_logic_vector(3 downto 0) := "0011";
constant s4: std_logic_vector(3 downto 0) := "1001";
constant s13: std_logic_vector(3 downto 0) := "0000";
constant s14: std_logic_vector(3 downto 0) := "1010";
constant s6: std_logic_vector(3 downto 0) := "0100";
constant s9: std_logic_vector(3 downto 0) := "0110";
constant s10: std_logic_vector(3 downto 0) := "1101";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "---------";
case current_state is
when s1 =>
if std_match(input, "1-----") then next_state <= s3; output <= "110000000";
end if;
when s3 =>
if std_match(input, "1-----") then next_state <= s2; output <= "000000000";
end if;
when s2 =>
if std_match(input, "1-----") then next_state <= s5; output <= "001000000";
end if;
when s5 =>
if std_match(input, "1-----") then next_state <= s7; output <= "000000000";
end if;
when s7 =>
if std_match(input, "10----") then next_state <= s7; output <= "000000000";
elsif std_match(input, "11----") then next_state <= s11; output <= "100110000";
end if;
when s11 =>
if std_match(input, "1-----") then next_state <= s12; output <= "100100000";
end if;
when s12 =>
if std_match(input, "1-1---") then next_state <= s8; output <= "000001100";
elsif std_match(input, "1-0---") then next_state <= s8; output <= "000000100";
end if;
when s8 =>
if std_match(input, "1-0---") then next_state <= s3; output <= "110000000";
elsif std_match(input, "1-10--") then next_state <= s3; output <= "110000000";
elsif std_match(input, "1-11--") then next_state <= s4; output <= "110000000";
end if;
when s4 =>
if std_match(input, "1---1-") then next_state <= s13; output <= "000000010";
elsif std_match(input, "1---0-") then next_state <= s13; output <= "000000000";
end if;
when s13 =>
if std_match(input, "1-----") then next_state <= s14; output <= "001000010";
end if;
when s14 =>
if std_match(input, "1-----") then next_state <= s6; output <= "000000000";
end if;
when s6 =>
if std_match(input, "10----") then next_state <= s6; output <= "000000000";
elsif std_match(input, "11----") then next_state <= s9; output <= "100110000";
end if;
when s9 =>
if std_match(input, "1-----") then next_state <= s10; output <= "100100000";
end if;
when s10 =>
if std_match(input, "1----1") then next_state <= s3; output <= "110000101";
elsif std_match(input, "1----0") then next_state <= s4; output <= "110000100";
end if;
when others => next_state <= "----"; output <= "---------";
end case;
end process;
end behaviour;
| agpl-3.0 | 7340a3043ba8a5caa1e1ba0e50ba2917 | 0.568268 | 3.338739 | false | false | false | false |
chastell/art-decomp | kiss/ex2_nov.vhd | 1 | 7,775 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex2_nov is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end ex2_nov;
architecture behaviour of ex2_nov is
constant s1: std_logic_vector(4 downto 0) := "11110";
constant s2: std_logic_vector(4 downto 0) := "10100";
constant s3: std_logic_vector(4 downto 0) := "11001";
constant s4: std_logic_vector(4 downto 0) := "01110";
constant s5: std_logic_vector(4 downto 0) := "11111";
constant s6: std_logic_vector(4 downto 0) := "10001";
constant s7: std_logic_vector(4 downto 0) := "10010";
constant s8: std_logic_vector(4 downto 0) := "11100";
constant s9: std_logic_vector(4 downto 0) := "10011";
constant s10: std_logic_vector(4 downto 0) := "11101";
constant s11: std_logic_vector(4 downto 0) := "10000";
constant s12: std_logic_vector(4 downto 0) := "01011";
constant s13: std_logic_vector(4 downto 0) := "01101";
constant s14: std_logic_vector(4 downto 0) := "11011";
constant s15: std_logic_vector(4 downto 0) := "11010";
constant s16: std_logic_vector(4 downto 0) := "10110";
constant s17: std_logic_vector(4 downto 0) := "10101";
constant s18: std_logic_vector(4 downto 0) := "10111";
constant s0: std_logic_vector(4 downto 0) := "00000";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "--";
case current_state is
when s1 =>
if std_match(input, "00") then next_state <= s2; output <= "--";
elsif std_match(input, "01") then next_state <= s4; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s3; output <= "--";
end if;
when s2 =>
if std_match(input, "00") then next_state <= s6; output <= "--";
elsif std_match(input, "01") then next_state <= s9; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "11";
end if;
when s3 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s7; output <= "--";
elsif std_match(input, "11") then next_state <= s8; output <= "--";
end if;
when s4 =>
if std_match(input, "00") then next_state <= s2; output <= "--";
elsif std_match(input, "01") then next_state <= s1; output <= "--";
elsif std_match(input, "10") then next_state <= s6; output <= "--";
elsif std_match(input, "11") then next_state <= s5; output <= "--";
end if;
when s5 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s6; output <= "--";
end if;
when s6 =>
if std_match(input, "00") then next_state <= s1; output <= "00";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s2; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "11";
end if;
when s7 =>
if std_match(input, "00") then next_state <= s5; output <= "11";
elsif std_match(input, "01") then next_state <= s2; output <= "00";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s8 =>
if std_match(input, "00") then next_state <= s5; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s1; output <= "00";
end if;
when s9 =>
if std_match(input, "00") then next_state <= s5; output <= "--";
elsif std_match(input, "01") then next_state <= s3; output <= "11";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s10 =>
if std_match(input, "00") then next_state <= s11; output <= "--";
elsif std_match(input, "01") then next_state <= s13; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s12; output <= "--";
end if;
when s11 =>
if std_match(input, "00") then next_state <= s15; output <= "--";
elsif std_match(input, "01") then next_state <= s18; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s12 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s16; output <= "--";
elsif std_match(input, "11") then next_state <= s17; output <= "--";
end if;
when s13 =>
if std_match(input, "00") then next_state <= s11; output <= "--";
elsif std_match(input, "01") then next_state <= s10; output <= "00";
elsif std_match(input, "10") then next_state <= s15; output <= "--";
elsif std_match(input, "11") then next_state <= s14; output <= "--";
end if;
when s14 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s15; output <= "--";
end if;
when s15 =>
if std_match(input, "00") then next_state <= s10; output <= "00";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s11; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "11";
end if;
when s16 =>
if std_match(input, "00") then next_state <= s14; output <= "11";
elsif std_match(input, "01") then next_state <= s11; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s17 =>
if std_match(input, "00") then next_state <= s14; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s10; output <= "00";
end if;
when s18 =>
if std_match(input, "00") then next_state <= s14; output <= "--";
elsif std_match(input, "01") then next_state <= s12; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "11";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when others => next_state <= "-----"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | 0910fdd2a57ca02dd594f793f5b3a71a | 0.552154 | 3.338343 | false | false | false | false |
es17m014/vhdl-counter | src/vhdl/cntr.vhd | 1 | 2,277 | -------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : cntr.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: This contains the counter logic
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 27.10.2017 0.1 Martin Angermair init
-- 19.11.2017 1.0 Martin Angermair final version
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
architecture rtl of cntr is
constant C_COUNT_1HZ : integer := 50000000; -- 1 HZ clock for counting
-- constant C_COUNT_1HZ : integer := 50000; -- for easier testing
component clk_gen is
port(
clk_i : in std_logic;
reset_i : in std_logic;
count_val_i : in integer;
signal_o : out std_logic);
end component;
signal s_count : std_logic_vector(13 downto 0) := (others => '0');
signal s_clk_1Hz : std_logic;
begin
p_clk_1Hz : clk_gen
port map (
clk_i => clk_i,
reset_i => reset_i,
count_val_i => C_COUNT_1HZ,
signal_o => s_clk_1HZ
);
process(s_clk_1HZ, reset_i, cntrreset_i, cntrhold_i, cntrup_i, cntrdown_i)
begin
if reset_i = '1' or cntrreset_i = '1' then
s_count <= (others => '0');
elsif rising_edge(s_clk_1HZ) then
if cntrhold_i = '1' then
s_count <= s_count;
elsif cntrup_i = '1' then
if s_count = "10011100001111" then
s_count <= (others => '0');
else
s_count <= s_count + 1;
end if;
elsif cntrdown_i = '1' then
if s_count = "00000000000000" then
s_count <= "10011100001111";
else
s_count <= s_count - 1;
end if;
else
-- stop countig till direction is set
end if;
end if;
end process;
digits_o <= s_count;
end rtl; | mit | 0baab2ca4c8840cc0e7de04b953f8228 | 0.472552 | 3.953125 | false | false | false | false |
chastell/art-decomp | kiss/dk512_rnd.vhd | 1 | 4,539 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk512_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(2 downto 0)
);
end dk512_rnd;
architecture behaviour of dk512_rnd is
constant state_1: std_logic_vector(3 downto 0) := "1101";
constant state_8: std_logic_vector(3 downto 0) := "0010";
constant state_2: std_logic_vector(3 downto 0) := "1011";
constant state_4: std_logic_vector(3 downto 0) := "1110";
constant state_3: std_logic_vector(3 downto 0) := "1111";
constant state_5: std_logic_vector(3 downto 0) := "0001";
constant state_6: std_logic_vector(3 downto 0) := "0110";
constant state_13: std_logic_vector(3 downto 0) := "0000";
constant state_7: std_logic_vector(3 downto 0) := "1010";
constant state_9: std_logic_vector(3 downto 0) := "1000";
constant state_10: std_logic_vector(3 downto 0) := "0100";
constant state_11: std_logic_vector(3 downto 0) := "1001";
constant state_12: std_logic_vector(3 downto 0) := "1100";
constant state_14: std_logic_vector(3 downto 0) := "0011";
constant state_15: std_logic_vector(3 downto 0) := "0111";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "---";
case current_state is
when state_1 =>
if std_match(input, "0") then next_state <= state_8; output <= "000";
elsif std_match(input, "1") then next_state <= state_9; output <= "000";
end if;
when state_2 =>
if std_match(input, "0") then next_state <= state_4; output <= "000";
elsif std_match(input, "1") then next_state <= state_3; output <= "000";
end if;
when state_3 =>
if std_match(input, "0") then next_state <= state_5; output <= "000";
elsif std_match(input, "1") then next_state <= state_6; output <= "000";
end if;
when state_4 =>
if std_match(input, "0") then next_state <= state_8; output <= "000";
elsif std_match(input, "1") then next_state <= state_11; output <= "000";
end if;
when state_5 =>
if std_match(input, "0") then next_state <= state_8; output <= "000";
elsif std_match(input, "1") then next_state <= state_12; output <= "000";
end if;
when state_6 =>
if std_match(input, "0") then next_state <= state_13; output <= "000";
elsif std_match(input, "1") then next_state <= state_14; output <= "000";
end if;
when state_7 =>
if std_match(input, "0") then next_state <= state_4; output <= "000";
elsif std_match(input, "1") then next_state <= state_15; output <= "000";
end if;
when state_8 =>
if std_match(input, "0") then next_state <= state_1; output <= "001";
elsif std_match(input, "1") then next_state <= state_2; output <= "001";
end if;
when state_9 =>
if std_match(input, "0") then next_state <= state_4; output <= "000";
elsif std_match(input, "1") then next_state <= state_3; output <= "001";
end if;
when state_10 =>
if std_match(input, "0") then next_state <= state_1; output <= "010";
elsif std_match(input, "1") then next_state <= state_2; output <= "010";
end if;
when state_11 =>
if std_match(input, "0") then next_state <= state_3; output <= "010";
elsif std_match(input, "1") then next_state <= state_4; output <= "010";
end if;
when state_12 =>
if std_match(input, "0") then next_state <= state_4; output <= "100";
elsif std_match(input, "1") then next_state <= state_3; output <= "001";
end if;
when state_13 =>
if std_match(input, "0") then next_state <= state_5; output <= "100";
elsif std_match(input, "1") then next_state <= state_6; output <= "100";
end if;
when state_14 =>
if std_match(input, "0") then next_state <= state_3; output <= "100";
elsif std_match(input, "1") then next_state <= state_7; output <= "100";
end if;
when state_15 =>
if std_match(input, "0") then next_state <= state_4; output <= "000";
elsif std_match(input, "1") then next_state <= state_6; output <= "000";
end if;
when others => next_state <= "----"; output <= "---";
end case;
end process;
end behaviour;
| agpl-3.0 | a3ba852fcba44eec43ac68d54473f866 | 0.582287 | 3.251433 | false | false | false | false |
TheMassController/VHDL_experimenting | project/common/txt_util.vhd | 1 | 14,536 | library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package txt_util is
-- prints a message to the screen
procedure print(text: string);
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
-- converts std_logic into a character
function chr(sl: std_logic) return character;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string;
-- converts std_logic_vector into a string (binary base)
function str(slv: std_logic_vector) return string;
-- converts boolean into a string
function str(b: boolean) return string;
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int: integer) return character;
-- converts integer into string using specified base
function str(int: integer; base: integer) return string;
-- converts integer to string, using base 10
function str(int: integer) return string;
-- convert std_logic_vector into a string in hex format
function hstr(slv: std_logic_vector) return string;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character;
-- convert a character to lower case
function to_lower(c: character) return character;
-- convert a string to upper case
function to_upper(s: string) return string;
-- convert a string to lower case
function to_lower(s: string) return string;
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c: character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector;
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string);
-- print string to a file and start new line
procedure print(file out_file: TEXT;
new_string: in string);
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character);
end txt_util;
package body txt_util is
-- prints text to the screen
procedure print(text: string) is
variable msg_line: line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
-- prints text to the screen when active
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end print;
-- converts std_logic into a character
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
function str(b: boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end str;
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int: integer) return character is
variable c: character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int: integer; base: integer) return string is
variable temp: string(1 to 10);
variable num: integer;
variable abs_int: integer;
variable len: integer := 1;
variable power: integer := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop ; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop ; -- side.
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end str;
-- convert integer to string, using base 10
function str(int: integer) return string is
begin
return str(int, 10) ;
end str;
-- converts a std_logic_vector into a hex string.
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character is
variable u: character;
begin
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
return u;
end to_upper;
-- convert a character to lower case
function to_lower(c: character) return character is
variable l: character;
begin
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
return l;
end to_lower;
-- convert a string to upper case
function to_upper(s: string) return string is
variable uppercase: string (s'range);
begin
for i in s'range loop
uppercase(i):= to_upper(s(i));
end loop;
return uppercase;
end to_upper;
-- convert a string to lower case
function to_lower(s: string) return string is
variable lowercase: string (s'range);
begin
for i in s'range loop
lowercase(i):= to_lower(s(i));
end loop;
return lowercase;
end to_lower;
-- functions to convert strings into other types
-- converts a character into a std_logic
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
begin
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
end case;
return sl;
end to_std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
----------------
-- file I/O --
----------------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string) is
variable l: line;
variable c: character;
variable is_string: boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
-- print string to a file
procedure print(file out_file: TEXT;
new_string: in string) is
variable l: line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character) is
variable l: line;
begin
write(l, char);
writeline(out_file, l);
end print;
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
--procedure str_write(file out_file: TEXT;
-- new_string: in string) is
-- begin
--
-- for i in new_string'range loop
-- print(out_file, new_string(i));
-- if new_string(i) = LF then -- end of string
-- exit;
-- end if;
-- end loop;
--
--end str_write;
end txt_util;
| mit | d6eba10d4cf4a99d7e7ea535d7df7b95 | 0.472207 | 3.80225 | false | false | false | false |
ibm2030/IBM2030 | FMD2030_5-05C.vhd | 1 | 9,810 | ---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-05C.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- I,J,U,V,T,G,L & D registers and A,B bus assembly
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY RegsABAssm IS
port
(
-- Inputs
-- A_BUS_IN : INOUT STD_LOGIC_VECTOR(0 to 8); -- 8 is P
SALS : IN SALS_BUS;
MACH_RST_SET_LCH : IN STD_LOGIC; -- 03B
SEL_SHARE_CYCLE : IN STD_LOGIC; -- ?
USE_MAN_DECODER : IN STD_LOGIC; -- 03D
MAN_STOR_PWR : IN STD_LOGIC; -- 03D
USE_MAN_DECODER_PWR : IN STD_LOGIC; -- 03D
FG_SWS : IN STD_LOGIC_VECTOR(0 to 7); -- 04C
FG_SW_P : IN STD_LOGIC;
HJ_SWS : IN STD_LOGIC_VECTOR(0 to 7); -- 8 is P
HJ_SW_P : IN STD_LOGIC;
USE_BASIC_CA_DECODER : IN STD_LOGIC; -- 02A
USE_ALT_CA_DECODER : IN STD_LOGIC; -- 02B
MPX_BUS : IN STD_LOGIC_VECTOR(0 to 8); -- 08C 8 is P
FT0,FT3,FT5,FT6 : IN STD_LOGIC; -- 08D
FT1 : IN STD_LOGIC; -- 07C
FT2,FT7 : IN STD_LOGIC; -- 08C
FT4 : IN STD_LOGIC; -- 03C
E_SW_SEL_BUS : IN E_SW_BUS_TYPE; -- 04C
CD_CTRL_REG : IN STD_LOGIC_VECTOR(0 to 3);
CD_REG_2 : IN STD_LOGIC; -- 04C Unused
MACH_RST_2A_B : IN STD_LOGIC; -- 06B
Z_BUS : IN STD_LOGIC_VECTOR(0 to 8); -- 06B 8 is P
R_REG : IN STD_LOGIC_VECTOR(0 to 8); -- 06C 8 is P
-- Outputs
USE_CPU_DECODER : OUT STD_LOGIC; -- 05B,04D
GATED_CA_BITS : OUT STD_LOGIC_VECTOR(0 to 3); -- 07C,10C
GT_J_TO_A,GT_D_TO_A : OUT STD_LOGIC; -- 03C
I,J,U,V,T,G,L : OUT STD_LOGIC_VECTOR(0 to 8); -- 8 is P
A_BUS : OUT STD_LOGIC_VECTOR(0 to 8); -- 06B 8 is P
B_BUS_OUT : OUT STD_LOGIC_VECTOR(0 to 8); -- 06B 8 is P
-- Clocks
T4 : IN STD_LOGIC
);
END RegsABAssm;
ARCHITECTURE FMD OF RegsABAssm IS
alias CA : STD_LOGIC_VECTOR(0 to 3) is SALS.SALS_CA;
alias CK : STD_LOGIC_VECTOR(0 to 3) is SALS.SALS_CK;
alias CB : STD_LOGIC_VECTOR(0 to 1) is SALS.SALS_CB;
alias AK_SAL_BIT : STD_LOGIC is SALS.SALS_AK;
signal GT_HJ_SWS_TO_B_BUS : STD_LOGIC;
signal GT_R_TO_B,GT_L_TO_B,GT_D_TO_B,GT_CK_TO_B : STD_LOGIC;
signal GT_FG_TO_A, GT_MPX_TAGS_TO_A, GT_MPX_BUS_TO_A,GT_I_TO_A,GT_U_TO_A, GT_V_TO_A,GT_T_TO_A,GT_G_TO_A,GT_L_TO_A,GT_R_TO_A : STD_LOGIC;
signal LCH_I,LCH_J,LCH_U,LCH_V,LCH_T,LCH_G,LCH_L,LCH_D : STD_LOGIC;
signal sUSE_CPU_DECODER : STD_LOGIC;
signal sGATED_CA_BITS : STD_LOGIC_VECTOR(0 to 3);
signal sGT_J_TO_A, sGT_D_TO_A : STD_LOGIC;
signal sI,sJ,sU,sV,sT,sG,sL,sD : STD_LOGIC_VECTOR(0 to 8);
BEGIN
-- Fig 5-05C
sUSE_CPU_DECODER <= not MACH_RST_SET_LCH and not SEL_SHARE_CYCLE and not USE_MAN_DECODER; -- AB3C5
USE_CPU_DECODER <= sUSE_CPU_DECODER;
sGATED_CA_BITS <= CA and (0 to 3 => sUSE_CPU_DECODER); -- AA2J6,AA2J2
GATED_CA_BITS <= sGATED_CA_BITS;
GT_HJ_SWS_TO_B_BUS <= (not CK(0) and CK(1) and not CK(2) and not CK(3) and AK_SAL_BIT) or (MAN_STOR_PWR and USE_MAN_DECODER_PWR); -- AB3H7
GT_R_TO_B <= not CB(0) and not CB(1) and not GT_HJ_SWS_TO_B_BUS and sUSE_CPU_DECODER;
GT_L_TO_B <= not CB(0) and CB(1) and not GT_HJ_SWS_TO_B_BUS and sUSE_CPU_DECODER;
GT_D_TO_B <= CB(0) and not CB(1) and not GT_HJ_SWS_TO_B_BUS and sUSE_CPU_DECODER;
GT_CK_TO_B <= CB(0) and CB(1) and not GT_HJ_SWS_TO_B_BUS and sUSE_CPU_DECODER;
B_BUS_OUT <= ((0 to 8 => GT_R_TO_B) and R_REG) or -- AB1K5
((0 to 8 => GT_L_TO_B) and sL) or -- AB1K5
((0 to 8 => GT_D_TO_B) and sD) or -- AB1K5
((0 to 8 => GT_CK_TO_B) and CK & CK & '1') or -- AB1L5
((0 to 8 => GT_HJ_SWS_TO_B_BUS) and HJ_SWS & HJ_SW_P); -- AB1L5
GT_FG_TO_A <= '1' when sGATED_CA_BITS="0001" and USE_ALT_CA_DECODER='1' else '0'; -- AB1F5
GT_MPX_TAGS_TO_A <= '1' when (sGATED_CA_BITS="0000" and USE_BASIC_CA_DECODER='1' and sUSE_CPU_DECODER='1') or (E_SW_SEL_BUS.FT_SEL='1' and USE_MAN_DECODER_PWR='1') else '0'; -- AA2C6 ?? and sUSE_CPU_DECODER required to prevent FT (CA=0000) from being put on A bus when not wanted
GT_MPX_BUS_TO_A <= '1' when (sGATED_CA_BITS="0110" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.FI_SEL='1') else '0'; -- AB3C3
GT_I_TO_A <= '1' when (sGATED_CA_BITS="1111" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.I_SEL='1') else '0'; -- AB1F4
sGT_J_TO_A <= '1' when (sGATED_CA_BITS="1110" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.J_SEL='1') else '0'; -- AB1F4
GT_J_TO_A <= sGT_J_TO_A;
GT_U_TO_A <= '1' when (sGATED_CA_BITS="1101" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.U_SEL='1') else '0'; -- AB1F4
GT_V_TO_A <= '1' when (sGATED_CA_BITS="1100" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.V_SEL='1') else '0'; -- AB1F4
GT_T_TO_A <= '1' when (sGATED_CA_BITS="1011" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.T_SEL='1') else '0'; -- AB1F4
GT_G_TO_A <= '1' when (sGATED_CA_BITS="1010" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.G_SEL='1') else '0'; -- AB1F4
GT_L_TO_A <= '1' when (sGATED_CA_BITS="1001" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.L_SEL='1') else '0'; -- AB3C3
sGT_D_TO_A <= '1' when (sGATED_CA_BITS="1000" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.D_SEL='1') else '0'; -- AB3C3
GT_D_TO_A <= sGT_D_TO_A;
GT_R_TO_A <= '1' when (sGATED_CA_BITS="0111" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.R_SEL='1') else '0'; -- AB3C3
A_BUS <= not(FG_SWS & FG_SW_P) when GT_FG_TO_A='1' else
not(FT0 & FT1 & FT2 & FT3 & FT4 & FT5 & FT6 & FT7 & '0') when GT_MPX_TAGS_TO_A='1' else
not MPX_BUS when GT_MPX_BUS_TO_A='1' else
not sI when GT_I_TO_A='1' else
not sJ when sGT_J_TO_A='1' else
not sU when GT_U_TO_A='1' else
not sV when GT_V_TO_A='1' else
not sT when GT_T_TO_A='1' else
not sG when GT_G_TO_A='1' else
not sL when GT_L_TO_A='1' else
not sD when sGT_D_TO_A='1' else
not R_REG when GT_R_TO_A='1' else
"111111111";
-- A_BUS_OUT <= A_BUS_IN or
-- ((0 to 8 => GT_FG_TO_A) and FG_SWS & FG_SW_P) or -- AB1D6
-- ((0 to 8 => GT_MPX_TAGS_TO_A) and FT0 & FT1 & FT2 & FT3 & FT4 & FT5 & FT6 & FT7 & '0') or -- AB1D6
-- ((0 to 8 => GT_MPX_BUS_TO_A) and MPX_BUS) or -- AB1D6
-- ((0 to 8 => GT_I_TO_A) and sI) or -- AB1F4
-- ((0 to 8 => sGT_J_TO_A) and sJ) or -- AB1F4
-- ((0 to 8 => GT_U_TO_A) and sU) or -- AB1F4
-- ((0 to 8 => GT_V_TO_A) and sV) or -- AB1C7
-- ((0 to 8 => GT_T_TO_A) and sT) or -- AB1C7
-- ((0 to 8 => GT_G_TO_A) and sG) or -- AB1C7
-- ((0 to 8 => GT_L_TO_A) and sL) or -- AB3C3
-- ((0 to 8 => sGT_D_TO_A) and sD) or -- AB3C3
-- ((0 to 8 => GT_R_TO_A) and R_REG); -- AB3C3
LCH_I <= '1' when (CD_CTRL_REG="1111" and T4='1') or (E_SW_SEL_BUS.I_SEL='1' and MAN_STOR_PWR='1') or MACH_RST_2A_B='1' else '0'; -- AB1G5
LCH_J <= '1' when (CD_CTRL_REG="1110" and T4='1') or (E_SW_SEL_BUS.J_SEL='1' and MAN_STOR_PWR='1') or MACH_RST_2A_B='1' else '0'; -- AB1G5
LCH_U <= '1' when (CD_CTRL_REG="1101" and T4='1') or (E_SW_SEL_BUS.U_SEL='1' and MAN_STOR_PWR='1') or MACH_RST_2A_B='1' else '0'; -- AB1G5
LCH_V <= '1' when (CD_CTRL_REG="1100" and T4='1') or (E_SW_SEL_BUS.V_SEL='1' and MAN_STOR_PWR='1') or MACH_RST_2A_B='1' else '0'; -- AB1H5
LCH_T <= '1' when (CD_CTRL_REG="1011" and T4='1') or (E_SW_SEL_BUS.T_SEL='1' and MAN_STOR_PWR='1') or MACH_RST_2A_B='1' else '0'; -- AB1H5
LCH_G <= '1' when (CD_CTRL_REG="1010" and T4='1') or (E_SW_SEL_BUS.G_SEL='1' and MAN_STOR_PWR='1') or MACH_RST_2A_B='1' else '0'; -- AB1H5
LCH_L <= '1' when (CD_CTRL_REG="1001" and T4='1') or (E_SW_SEL_BUS.L_SEL='1' and MAN_STOR_PWR='1') or MACH_RST_2A_B='1' else '0'; -- AB1J2
LCH_D <= '1' when (CD_CTRL_REG="1000" and T4='1') or (E_SW_SEL_BUS.D_SEL='1' and MAN_STOR_PWR='1') or MACH_RST_2A_B='1' else '0'; -- AB1J2
I_REG: PHV9 port map(Z_BUS,LCH_I,sI); -- AB1G3
I <= sI;
J_REG: PHV9 port map(Z_BUS,LCH_J,sJ); -- AB1G4
J <= sJ;
U_REG: PHV9 port map(Z_BUS,LCH_U,sU); -- AB1H3
U <= sU;
V_REG: PHV9 port map(Z_BUS,LCH_V,sV); -- AB1H4
V <= sV;
T_REG: PHV9 port map(Z_BUS,LCH_T,sT); -- AB1J4
T <= sT;
G_REG: PHV9 port map(Z_BUS,LCH_G,sG); -- AB1K4
G <= sG;
L_REG: PHV9 port map(Z_BUS,LCH_L,sL); -- AB1J2
L <= sL;
D_REG: PHV9 port map(Z_BUS,LCH_D,sD); -- AB1K3
END FMD;
| gpl-3.0 | 34f604f46a2ba693b50df5181d99edc0 | 0.595923 | 2.291521 | false | false | false | false |
chastell/art-decomp | kiss/dk27_jed.vhd | 1 | 2,406 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk27_jed is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(1 downto 0)
);
end dk27_jed;
architecture behaviour of dk27_jed is
constant START: std_logic_vector(2 downto 0) := "111";
constant state6: std_logic_vector(2 downto 0) := "011";
constant state2: std_logic_vector(2 downto 0) := "110";
constant state5: std_logic_vector(2 downto 0) := "001";
constant state3: std_logic_vector(2 downto 0) := "000";
constant state4: std_logic_vector(2 downto 0) := "010";
constant state7: std_logic_vector(2 downto 0) := "101";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "--";
case current_state is
when START =>
if std_match(input, "0") then next_state <= state6; output <= "00";
elsif std_match(input, "1") then next_state <= state4; output <= "00";
end if;
when state2 =>
if std_match(input, "0") then next_state <= state5; output <= "00";
elsif std_match(input, "1") then next_state <= state3; output <= "00";
end if;
when state3 =>
if std_match(input, "0") then next_state <= state5; output <= "00";
elsif std_match(input, "1") then next_state <= state7; output <= "00";
end if;
when state4 =>
if std_match(input, "0") then next_state <= state6; output <= "00";
elsif std_match(input, "1") then next_state <= state6; output <= "10";
end if;
when state5 =>
if std_match(input, "0") then next_state <= START; output <= "10";
elsif std_match(input, "1") then next_state <= state2; output <= "10";
end if;
when state6 =>
if std_match(input, "0") then next_state <= START; output <= "01";
elsif std_match(input, "1") then next_state <= state2; output <= "01";
end if;
when state7 =>
if std_match(input, "0") then next_state <= state5; output <= "00";
elsif std_match(input, "1") then next_state <= state6; output <= "10";
end if;
when others => next_state <= "---"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | c9958e3127fb3eacd8fcd79edb69e579 | 0.594347 | 3.323204 | false | false | false | false |
digital-sound-antiques/vm2413 | TemporalMixer.vhd | 2 | 4,150 | --
-- TemporalMixer.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity TemporalMixer is
port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
rhythm : in std_logic;
maddr : out SLOT_TYPE;
mdata : in SIGNED_LI_TYPE;
mo : out std_logic_vector(9 downto 0);
ro : out std_logic_vector(9 downto 0)
);
end TemporalMixer;
architecture RTL of TemporalMixer is
signal mmute, rmute : std_logic;
begin
process (clk, reset)
begin
if reset = '1' then
mo <= (others =>'0');
ro <= (others =>'0');
maddr <= 0;
mmute <= '1';
rmute <= '1';
elsif clk'event and clk = '1' then if clkena='1' then
if stage = 0 then
mo <= "1000000000";
ro <= "1000000000";
if rhythm = '0' then
case slot is
when 0 => maddr <= 1; mmute <='0'; -- CH0
when 1 => maddr <= 3; mmute <='0'; -- CH1
when 2 => maddr <= 5; mmute <='0'; -- CH2
when 3 => mmute <= '1';
when 4 => mmute <= '1';
when 5 => mmute <= '1';
when 6 => maddr <= 7; mmute<='0'; -- CH3
when 7 => maddr <= 9; mmute<='0'; -- CH4
when 8 => maddr <= 11; mmute<='0'; -- CH5
when 9 => mmute <= '1';
when 10 => mmute <= '1';
when 11 => mmute <= '1';
when 12 => maddr <= 13; mmute<='0'; -- CH6
when 13 => maddr <= 15; mmute<='0'; -- CH7
when 14 => maddr <= 17; mmute<='0'; -- CH8
when 15 => mmute <= '1';
when 16 => mmute <= '1';
when 17 => mmute <= '1';
end case;
rmute <= '1';
else
case slot is
when 0 => maddr <= 1; mmute <='0'; rmute <='1'; -- CH0
when 1 => maddr <= 3; mmute <='0'; rmute <='1'; -- CH1
when 2 => maddr <= 5; mmute <='0'; rmute <='1'; -- CH2
when 3 => mmute <='1'; maddr <= 15; rmute <='0'; -- SD
when 4 => mmute <='1'; maddr <= 17; rmute <='0'; -- CYM
when 5 => mmute <='1'; rmute <='1';
when 6 => maddr <= 7; mmute <='0'; rmute <='1'; -- CH3
when 7 => maddr <= 9; mmute <='0'; rmute <='1'; -- CH4
when 8 => maddr <= 11;mmute <='0'; rmute <='1'; -- CH5
when 9 => mmute <='1'; maddr <= 14; rmute <='0'; -- HH
when 10 => mmute <='1'; maddr <= 16; rmute <='0'; -- TOM
when 11 => mmute <='1'; maddr <= 13; rmute <='0'; -- BD
when 12 => mmute <='1'; maddr <= 15; rmute <='0'; -- SD
when 13 => mmute <='1'; maddr <= 17; rmute <='0'; -- CYM
when 14 => mmute <='1'; maddr <= 14; rmute <='0'; -- HH
when 15 => mmute <='1'; maddr <= 16; rmute <='0'; -- TOM
when 16 => mmute <='1'; maddr <= 13; rmute <='0'; -- BD
when 17 => mmute <='1'; rmute <='1';
end case;
end if;
else
if mmute = '0' then
if mdata.sign = '0' then
mo <= "1000000000" + mdata.value;
else
mo <= "1000000000" - mdata.value;
end if;
else
mo <= "1000000000";
end if;
if rmute = '0' then
if mdata.sign = '0' then
ro <= "1000000000" + mdata.value;
else
ro <= "1000000000" - mdata.value;
end if;
else
ro <= "1000000000";
end if;
end if;
end if; end if;
end process;
end RTL; | mit | 18d568e384d6758284c1be1f9ab21cdb | 0.377831 | 4.036965 | false | false | false | false |
chastell/art-decomp | kiss/planet_jed.vhd | 1 | 16,521 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity planet_jed is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(18 downto 0)
);
end planet_jed;
architecture behaviour of planet_jed is
constant st0: std_logic_vector(5 downto 0) := "000010";
constant st1: std_logic_vector(5 downto 0) := "110101";
constant st2: std_logic_vector(5 downto 0) := "011101";
constant st3: std_logic_vector(5 downto 0) := "000011";
constant st4: std_logic_vector(5 downto 0) := "010101";
constant st42: std_logic_vector(5 downto 0) := "010100";
constant st5: std_logic_vector(5 downto 0) := "111010";
constant st6: std_logic_vector(5 downto 0) := "010011";
constant st7: std_logic_vector(5 downto 0) := "001111";
constant st41: std_logic_vector(5 downto 0) := "001101";
constant st38: std_logic_vector(5 downto 0) := "011111";
constant st8: std_logic_vector(5 downto 0) := "011100";
constant st10: std_logic_vector(5 downto 0) := "110100";
constant st9: std_logic_vector(5 downto 0) := "110110";
constant st11: std_logic_vector(5 downto 0) := "010110";
constant st12: std_logic_vector(5 downto 0) := "011010";
constant st13: std_logic_vector(5 downto 0) := "110011";
constant st14: std_logic_vector(5 downto 0) := "111111";
constant st15: std_logic_vector(5 downto 0) := "010111";
constant st16: std_logic_vector(5 downto 0) := "111110";
constant st17: std_logic_vector(5 downto 0) := "011000";
constant st18: std_logic_vector(5 downto 0) := "101111";
constant st19: std_logic_vector(5 downto 0) := "000111";
constant st46: std_logic_vector(5 downto 0) := "100101";
constant st24: std_logic_vector(5 downto 0) := "100111";
constant st20: std_logic_vector(5 downto 0) := "000001";
constant st25: std_logic_vector(5 downto 0) := "000000";
constant st21: std_logic_vector(5 downto 0) := "000101";
constant st22: std_logic_vector(5 downto 0) := "000100";
constant st23: std_logic_vector(5 downto 0) := "000110";
constant st26: std_logic_vector(5 downto 0) := "001011";
constant st28: std_logic_vector(5 downto 0) := "100011";
constant st30: std_logic_vector(5 downto 0) := "101011";
constant st27: std_logic_vector(5 downto 0) := "010000";
constant st29: std_logic_vector(5 downto 0) := "110010";
constant st31: std_logic_vector(5 downto 0) := "101101";
constant st32: std_logic_vector(5 downto 0) := "011011";
constant st33: std_logic_vector(5 downto 0) := "001100";
constant st35: std_logic_vector(5 downto 0) := "011110";
constant st34: std_logic_vector(5 downto 0) := "001001";
constant st36: std_logic_vector(5 downto 0) := "101000";
constant st37: std_logic_vector(5 downto 0) := "010010";
constant st39: std_logic_vector(5 downto 0) := "010001";
constant st40: std_logic_vector(5 downto 0) := "110001";
constant st43: std_logic_vector(5 downto 0) := "110000";
constant st44: std_logic_vector(5 downto 0) := "011001";
constant st45: std_logic_vector(5 downto 0) := "101010";
constant st47: std_logic_vector(5 downto 0) := "001000";
signal current_state, next_state: std_logic_vector(5 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "------"; output <= "-------------------";
case current_state is
when st0 =>
if std_match(input, "-------") then next_state <= st1; output <= "001011101000000---0";
end if;
when st1 =>
if std_match(input, "----01-") then next_state <= st1; output <= "--------0000000---0";
elsif std_match(input, "----10-") then next_state <= st1; output <= "--------0100000---1";
elsif std_match(input, "----00-") then next_state <= st1; output <= "1000----1000000---1";
elsif std_match(input, "----11-") then next_state <= st2; output <= "1000111110011001000";
end if;
when st2 =>
if std_match(input, "------0") then next_state <= st3; output <= "1010010010000000000";
elsif std_match(input, "---0---") then next_state <= st3; output <= "1010010010000000000";
elsif std_match(input, "---1--1") then next_state <= st0; output <= "1010----1010010---1";
end if;
when st3 =>
if std_match(input, "11-----") then next_state <= st4; output <= "001111101000000-010";
elsif std_match(input, "10-----") then next_state <= st4; output <= "0011111110000000-10";
elsif std_match(input, "0-0-01-") then next_state <= st4; output <= "--------000010000-0";
elsif std_match(input, "0-0-10-") then next_state <= st4; output <= "--------010010000-1";
elsif std_match(input, "0-0-11-") then next_state <= st42; output <= "011011011000100---0";
elsif std_match(input, "0-0-00-") then next_state <= st4; output <= "0110----100000000-1";
elsif std_match(input, "0-1-01-") then next_state <= st4; output <= "--------00011000000";
elsif std_match(input, "0-1-10-") then next_state <= st4; output <= "--------01011000001";
elsif std_match(input, "0-1-11-") then next_state <= st42; output <= "011011011001100--00";
elsif std_match(input, "0-1-00-") then next_state <= st4; output <= "0110----10010000001";
end if;
when st4 =>
if std_match(input, "-------") then next_state <= st5; output <= "1010010010000000000";
end if;
when st5 =>
if std_match(input, "--0----") then next_state <= st6; output <= "1000011110000000001";
elsif std_match(input, "--1----") then next_state <= st6; output <= "1000011110010000001";
end if;
when st6 =>
if std_match(input, "-1----0") then next_state <= st7; output <= "101001001000000-000";
elsif std_match(input, "-110--1") then next_state <= st7; output <= "101001001000000-000";
elsif std_match(input, "-10---1") then next_state <= st41; output <= "101001001000000--00";
elsif std_match(input, "-111--1") then next_state <= st38; output <= "101001001000000--00";
elsif std_match(input, "-0-----") then next_state <= st7; output <= "1010010010000000-00";
end if;
when st7 =>
if std_match(input, "--1----") then next_state <= st8; output <= "0001101010010000000";
elsif std_match(input, "--0----") then next_state <= st8; output <= "0001101010000000000";
end if;
when st8 =>
if std_match(input, "--0----") then next_state <= st10; output <= "1010010010000000000";
elsif std_match(input, "--1----") then next_state <= st9; output <= "1010010010000000000";
end if;
when st9 =>
if std_match(input, "-11----") then next_state <= st11; output <= "001011101001000-000";
elsif std_match(input, "-01----") then next_state <= st11; output <= "0010111110010000-00";
elsif std_match(input, "-10----") then next_state <= st11; output <= "001011101000000-000";
elsif std_match(input, "-00----") then next_state <= st11; output <= "0010111110000000-00";
end if;
when st10 =>
if std_match(input, "--1----") then next_state <= st12; output <= "0010----10010000001";
elsif std_match(input, "--0----") then next_state <= st12; output <= "0010----10000000001";
end if;
when st11 =>
if std_match(input, "-------") then next_state <= st13; output <= "1010010010000000000";
end if;
when st12 =>
if std_match(input, "-------") then next_state <= st14; output <= "1010010010000000000";
end if;
when st13 =>
if std_match(input, "-11----") then next_state <= st15; output <= "010110011001000-000";
elsif std_match(input, "-10----") then next_state <= st15; output <= "010110011000000-000";
elsif std_match(input, "-01----") then next_state <= st15; output <= "0101100010010000-00";
elsif std_match(input, "-00----") then next_state <= st15; output <= "0101100010000000-00";
end if;
when st14 =>
if std_match(input, "--1----") then next_state <= st15; output <= "0101----10010000001";
elsif std_match(input, "--0----") then next_state <= st15; output <= "0101----10000000001";
end if;
when st15 =>
if std_match(input, "-------") then next_state <= st16; output <= "1010010010000000000";
end if;
when st16 =>
if std_match(input, "--1----") then next_state <= st17; output <= "0110010110010000001";
elsif std_match(input, "--0----") then next_state <= st17; output <= "0110010110000000001";
end if;
when st17 =>
if std_match(input, "---0---") then next_state <= st18; output <= "1010010010000000000";
elsif std_match(input, "01-1---") then next_state <= st19; output <= "101001001000001-0-0";
elsif std_match(input, "00-1--0") then next_state <= st19; output <= "1010010010000010--0";
elsif std_match(input, "00-1--1") then next_state <= st46; output <= "101001001000000---0";
elsif std_match(input, "11-1---") then next_state <= st24; output <= "101001001000001-000";
elsif std_match(input, "10-1--0") then next_state <= st24; output <= "1010010010000010-00";
elsif std_match(input, "10-1--1") then next_state <= st18; output <= "1010010010000000-00";
end if;
when st18 =>
if std_match(input, "--1----") then next_state <= st2; output <= "1000111110010000000";
elsif std_match(input, "0-0----") then next_state <= st2; output <= "1000----10000000001";
elsif std_match(input, "1-0----") then next_state <= st2; output <= "1000111110000000000";
end if;
when st19 =>
if std_match(input, "-10----") then next_state <= st20; output <= "100101001000000-0-0";
elsif std_match(input, "-00----") then next_state <= st20; output <= "1001010110000000--0";
elsif std_match(input, "--1----") then next_state <= st25; output <= "100011111001000--00";
end if;
when st20 =>
if std_match(input, "-10----") then next_state <= st19; output <= "101001001000000-0-0";
elsif std_match(input, "-11----") then next_state <= st21; output <= "101001001000000-0-0";
elsif std_match(input, "-01----") then next_state <= st19; output <= "1010010010000000--0";
elsif std_match(input, "-00----") then next_state <= st21; output <= "1010010010000000--0";
end if;
when st21 =>
if std_match(input, "-10----") then next_state <= st22; output <= "001111111000000-0-0";
elsif std_match(input, "-11----") then next_state <= st23; output <= "001111111001000--00";
elsif std_match(input, "-00----") then next_state <= st22; output <= "0011111010000000--0";
elsif std_match(input, "-01----") then next_state <= st23; output <= "001111101001000--00";
end if;
when st22 =>
if std_match(input, "-------") then next_state <= st19; output <= "10100100100000000-0";
end if;
when st23 =>
if std_match(input, "-------") then next_state <= st24; output <= "101001001000000--00";
end if;
when st24 =>
if std_match(input, "-------") then next_state <= st25; output <= "100011111000000--00";
end if;
when st25 =>
if std_match(input, "---0--0") then next_state <= st26; output <= "101001001000000---0";
elsif std_match(input, "---1--0") then next_state <= st28; output <= "101001001000010--00";
elsif std_match(input, "------1") then next_state <= st30; output <= "101001001000000--10";
end if;
when st26 =>
if std_match(input, "--0-01-") then next_state <= st27; output <= "--------0000100---0";
elsif std_match(input, "--0-10-") then next_state <= st27; output <= "--------0100100---1";
elsif std_match(input, "--0-00-") then next_state <= st27; output <= "0110----1000000---1";
elsif std_match(input, "--0-11-") then next_state <= st42; output <= "011011011000100---0";
elsif std_match(input, "--1----") then next_state <= st25; output <= "100011111001000--00";
end if;
when st27 =>
if std_match(input, "-------") then next_state <= st26; output <= "101001001000000---0";
end if;
when st28 =>
if std_match(input, "-------") then next_state <= st29; output <= "011001011000000--01";
end if;
when st29 =>
if std_match(input, "---1---") then next_state <= st26; output <= "101001001000000---0";
elsif std_match(input, "--10---") then next_state <= st3; output <= "1010010010000001000";
elsif std_match(input, "--00---") then next_state <= st3; output <= "1010010010000000100";
end if;
when st30 =>
if std_match(input, "-------") then next_state <= st31; output <= "100001111000000---1";
end if;
when st31 =>
if std_match(input, "---0---") then next_state <= st26; output <= "101001001000000---0";
elsif std_match(input, "---1---") then next_state <= st32; output <= "101001001000000---0";
end if;
when st32 =>
if std_match(input, "--0----") then next_state <= st33; output <= "100101011000000---0";
elsif std_match(input, "--1----") then next_state <= st35; output <= "011011011001000--00";
end if;
when st33 =>
if std_match(input, "--10---") then next_state <= st32; output <= "101001001000000---0";
elsif std_match(input, "--0----") then next_state <= st34; output <= "101001001000000---0";
elsif std_match(input, "---1---") then next_state <= st34; output <= "101001001000000---0";
end if;
when st34 =>
if std_match(input, "--1----") then next_state <= st35; output <= "011011011001000--00";
elsif std_match(input, "--0----") then next_state <= st35; output <= "011011011000000---0";
end if;
when st35 =>
if std_match(input, "-------") then next_state <= st36; output <= "101001001000000--00";
end if;
when st36 =>
if std_match(input, "--0----") then next_state <= st37; output <= "011011101000000--00";
elsif std_match(input, "--1----") then next_state <= st37; output <= "011011101001000--00";
end if;
when st37 =>
if std_match(input, "-------") then next_state <= st9; output <= "1010010010000000100";
end if;
when st38 =>
if std_match(input, "--0-01-") then next_state <= st39; output <= "--------0000100---0";
elsif std_match(input, "--0-10-") then next_state <= st39; output <= "--------0100100---1";
elsif std_match(input, "--0-11-") then next_state <= st42; output <= "011011011000100---0";
elsif std_match(input, "--0-00-") then next_state <= st39; output <= "0110----1000000---1";
elsif std_match(input, "--1----") then next_state <= st40; output <= "100011111001000--00";
end if;
when st39 =>
if std_match(input, "-------") then next_state <= st38; output <= "101001001000000---0";
end if;
when st40 =>
if std_match(input, "-------") then next_state <= st41; output <= "101001001000000--10";
end if;
when st41 =>
if std_match(input, "-------") then next_state <= st42; output <= "011011011000000---0";
end if;
when st42 =>
if std_match(input, "-------") then next_state <= st43; output <= "101001001000000--00";
end if;
when st43 =>
if std_match(input, "--0----") then next_state <= st44; output <= "011011101000000--00";
elsif std_match(input, "--1----") then next_state <= st44; output <= "011011101001000--00";
end if;
when st44 =>
if std_match(input, "-------") then next_state <= st45; output <= "101001001000000--00";
end if;
when st45 =>
if std_match(input, "--0----") then next_state <= st6; output <= "0111001110000000100";
elsif std_match(input, "--1----") then next_state <= st6; output <= "0111001110010000100";
end if;
when st46 =>
if std_match(input, "--0----") then next_state <= st47; output <= "1000----1000000---1";
elsif std_match(input, "--1----") then next_state <= st0; output <= "100011111011010---0";
end if;
when st47 =>
if std_match(input, "-------") then next_state <= st46; output <= "101001001000000---0";
end if;
when others => next_state <= "------"; output <= "-------------------";
end case;
end process;
end behaviour;
| agpl-3.0 | 74db22500bd09bbad3972d81d207b6bd | 0.579384 | 3.597779 | false | false | false | false |
LucasMahieu/TP_secu | code/AES/vhd/vhd/GFMapInv.vhd | 2 | 853 |
-- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
-- Component Declaration
entity gfmapinv is port (
-- ah -> High Data Input (4 std_logic)
-- al -> Low Data Input (4 std_logic)
-- a -> Data Output (remapped back) (8 std_logic)
ah, al : in std_logic_vector (3 downto 0);
a : out std_logic_vector (7 downto 0) );
end gfmapinv;
-- Architecture of the Component
architecture a_gfmapinv of gfmapinv is
begin
-- Inverse Mapping Process
a(0) <= al(0) xor ah(0);
a(1) <= ah(0) xor ah(1) xor ah(3);
a(2) <= al(1) xor ah(3) xor ah(0) xor ah(1);
a(3) <= ah(0) xor ah(1) xor al(1) xor ah(2);
a(4) <= al(1) xor ah(3) xor ah(0) xor ah(1) xor al(3);
a(5) <= ah(0) xor ah(1) xor al(2);
a(6) <= al(1) xor ah(3) xor al(2) xor al(3) xor ah(0);
a(7) <= ah(0) xor ah(1) xor al(2) xor ah(3);
end a_gfmapinv;
| mit | 4893654e05bd5ed1c1acd8da612f2150 | 0.590856 | 2.516224 | false | false | false | false |
chastell/art-decomp | kiss/pma_rnd.vhd | 1 | 9,226 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity pma_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0)
);
end pma_rnd;
architecture behaviour of pma_rnd is
constant s0: std_logic_vector(4 downto 0) := "11101";
constant s1: std_logic_vector(4 downto 0) := "00010";
constant s21: std_logic_vector(4 downto 0) := "11011";
constant s2: std_logic_vector(4 downto 0) := "11110";
constant s3: std_logic_vector(4 downto 0) := "11111";
constant s4: std_logic_vector(4 downto 0) := "10001";
constant s6: std_logic_vector(4 downto 0) := "10110";
constant s7: std_logic_vector(4 downto 0) := "01011";
constant s5: std_logic_vector(4 downto 0) := "01111";
constant s10: std_logic_vector(4 downto 0) := "00001";
constant s8: std_logic_vector(4 downto 0) := "10000";
constant s9: std_logic_vector(4 downto 0) := "11010";
constant s11: std_logic_vector(4 downto 0) := "11000";
constant s12: std_logic_vector(4 downto 0) := "01000";
constant s13: std_logic_vector(4 downto 0) := "00100";
constant s14: std_logic_vector(4 downto 0) := "01001";
constant s22: std_logic_vector(4 downto 0) := "00110";
constant s30: std_logic_vector(4 downto 0) := "11100";
constant s23: std_logic_vector(4 downto 0) := "00011";
constant s25: std_logic_vector(4 downto 0) := "10111";
constant s24: std_logic_vector(4 downto 0) := "10011";
constant s26: std_logic_vector(4 downto 0) := "10010";
constant s27: std_logic_vector(4 downto 0) := "00111";
constant s28: std_logic_vector(4 downto 0) := "01100";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "--------";
case current_state is
when s0 =>
if std_match(input, "----1---") then next_state <= s1; output <= "00000000";
elsif std_match(input, "1---01--") then next_state <= s21; output <= "00000000";
end if;
when s1 =>
if std_match(input, "---0---1") then next_state <= s2; output <= "00001000";
elsif std_match(input, "---0--1-") then next_state <= s2; output <= "00001000";
elsif std_match(input, "1--1----") then next_state <= s3; output <= "00001000";
end if;
when s2 =>
if std_match(input, "1--1----") then next_state <= s3; output <= "00000100";
end if;
when s3 =>
if std_match(input, "1--1----") then next_state <= s4; output <= "10000000";
elsif std_match(input, "1--0---1") then next_state <= s6; output <= "10000000";
elsif std_match(input, "1--0--1-") then next_state <= s6; output <= "10000000";
elsif std_match(input, "1--0--00") then next_state <= s7; output <= "10000000";
end if;
when s4 =>
if std_match(input, "1--1----") then next_state <= s5; output <= "01000000";
elsif std_match(input, "1--0---1") then next_state <= s6; output <= "01000000";
elsif std_match(input, "1--0--1-") then next_state <= s6; output <= "01000000";
elsif std_match(input, "1--0--00") then next_state <= s7; output <= "01000000";
end if;
when s5 =>
if std_match(input, "1--1----") then next_state <= s5; output <= "11000000";
elsif std_match(input, "1--0---1") then next_state <= s6; output <= "11000000";
elsif std_match(input, "1--0--1-") then next_state <= s6; output <= "11000000";
elsif std_match(input, "1--0--00") then next_state <= s7; output <= "11000000";
end if;
when s6 =>
if std_match(input, "1-----01") then next_state <= s0; output <= "00100000";
elsif std_match(input, "1-----1-") then next_state <= s10; output <= "00100000";
end if;
when s7 =>
if std_match(input, "-1--1---") then next_state <= s8; output <= "11101010";
elsif std_match(input, "-1--0--1") then next_state <= s6; output <= "11101010";
elsif std_match(input, "-1--0-1-") then next_state <= s6; output <= "11101010";
end if;
when s8 =>
if std_match(input, "1--1----") then next_state <= s5; output <= "01110000";
elsif std_match(input, "---0---1") then next_state <= s9; output <= "01110000";
elsif std_match(input, "---0--1-") then next_state <= s9; output <= "01110000";
end if;
when s9 =>
if std_match(input, "1--1----") then next_state <= s5; output <= "11100100";
end if;
when s10 =>
if std_match(input, "1--10--0") then next_state <= s11; output <= "10101100";
elsif std_match(input, "1------1") then next_state <= s0; output <= "10101100";
elsif std_match(input, "1---1---") then next_state <= s0; output <= "10101100";
end if;
when s11 =>
if std_match(input, "-11-0--0") then next_state <= s12; output <= "11111101";
elsif std_match(input, "11-----1") then next_state <= s0; output <= "11111101";
elsif std_match(input, "1---1---") then next_state <= s0; output <= "11111101";
end if;
when s12 =>
if std_match(input, "---00--0") then next_state <= s13; output <= "10111100";
elsif std_match(input, "1------1") then next_state <= s0; output <= "10111100";
elsif std_match(input, "1---1---") then next_state <= s0; output <= "10111100";
end if;
when s13 =>
if std_match(input, "1-------") then next_state <= s14; output <= "11111100";
end if;
when s14 =>
if std_match(input, "1---0--0") then next_state <= s10; output <= "01100000";
elsif std_match(input, "1------1") then next_state <= s0; output <= "01100000";
elsif std_match(input, "1---1---") then next_state <= s0; output <= "01100000";
end if;
when s21 =>
if std_match(input, "1---0-00") then next_state <= s22; output <= "00011100";
elsif std_match(input, "1---1---") then next_state <= s30; output <= "00011100";
elsif std_match(input, "1-----1-") then next_state <= s30; output <= "00011100";
elsif std_match(input, "1------1") then next_state <= s30; output <= "00011100";
end if;
when s22 =>
if std_match(input, "1---0100") then next_state <= s23; output <= "10011100";
elsif std_match(input, "1---0000") then next_state <= s25; output <= "10011100";
elsif std_match(input, "1---1---") then next_state <= s30; output <= "10011100";
elsif std_match(input, "1-----1-") then next_state <= s30; output <= "10011100";
elsif std_match(input, "1------1") then next_state <= s30; output <= "10011100";
end if;
when s23 =>
if std_match(input, "1---0100") then next_state <= s24; output <= "01011100";
elsif std_match(input, "1---0000") then next_state <= s25; output <= "01011100";
elsif std_match(input, "1---1---") then next_state <= s30; output <= "01011100";
elsif std_match(input, "1-----1-") then next_state <= s30; output <= "01011100";
elsif std_match(input, "1------1") then next_state <= s30; output <= "01011100";
end if;
when s24 =>
if std_match(input, "1---0000") then next_state <= s25; output <= "11011100";
elsif std_match(input, "1---1---") then next_state <= s30; output <= "11011100";
elsif std_match(input, "1-----1-") then next_state <= s30; output <= "11011100";
elsif std_match(input, "1------1") then next_state <= s30; output <= "11011100";
end if;
when s25 =>
if std_match(input, "---10-00") then next_state <= s26; output <= "01111100";
elsif std_match(input, "1---1---") then next_state <= s30; output <= "01111100";
elsif std_match(input, "1-----1-") then next_state <= s30; output <= "01111100";
elsif std_match(input, "1------1") then next_state <= s30; output <= "01111100";
end if;
when s26 =>
if std_match(input, "011---00") then next_state <= s27; output <= "01111101";
elsif std_match(input, "1---1---") then next_state <= s30; output <= "01111101";
elsif std_match(input, "1-----1-") then next_state <= s30; output <= "01111101";
elsif std_match(input, "1------1") then next_state <= s30; output <= "01111101";
end if;
when s27 =>
if std_match(input, "0--00-00") then next_state <= s28; output <= "11101100";
elsif std_match(input, "1--00-00") then next_state <= s0; output <= "11101100";
elsif std_match(input, "1---1---") then next_state <= s30; output <= "11101100";
elsif std_match(input, "1-----1-") then next_state <= s30; output <= "11101100";
elsif std_match(input, "1------1") then next_state <= s30; output <= "11101100";
end if;
when s28 =>
if std_match(input, "1-------") then next_state <= s0; output <= "10111000";
end if;
when s30 =>
if std_match(input, "1-------") then next_state <= s0; output <= "00110000";
end if;
when others => next_state <= "-----"; output <= "--------";
end case;
end process;
end behaviour;
| agpl-3.0 | a437c2ae996c7f4e9f32d4650ad6ff88 | 0.563516 | 3.307996 | false | false | false | false |
chastell/art-decomp | kiss/ex6_hot.vhd | 1 | 4,281 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex6_hot is
port(
clock: in std_logic;
input: in std_logic_vector(4 downto 0);
output: out std_logic_vector(7 downto 0)
);
end ex6_hot;
architecture behaviour of ex6_hot is
constant s1: std_logic_vector(7 downto 0) := "10000000";
constant s3: std_logic_vector(7 downto 0) := "01000000";
constant s2: std_logic_vector(7 downto 0) := "00100000";
constant s4: std_logic_vector(7 downto 0) := "00010000";
constant s5: std_logic_vector(7 downto 0) := "00001000";
constant s6: std_logic_vector(7 downto 0) := "00000100";
constant s7: std_logic_vector(7 downto 0) := "00000010";
constant s8: std_logic_vector(7 downto 0) := "00000001";
signal current_state, next_state: std_logic_vector(7 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--------"; output <= "--------";
case current_state is
when s1 =>
if std_match(input, "11---") then next_state <= s3; output <= "10111000";
elsif std_match(input, "00---") then next_state <= s2; output <= "11000000";
elsif std_match(input, "10---") then next_state <= s4; output <= "00101000";
end if;
when s2 =>
if std_match(input, "0-0--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "--1--") then next_state <= s5; output <= "00001110";
elsif std_match(input, "110--") then next_state <= s3; output <= "10111000";
elsif std_match(input, "100--") then next_state <= s4; output <= "00101000";
end if;
when s3 =>
if std_match(input, "10---") then next_state <= s4; output <= "00111000";
elsif std_match(input, "00---") then next_state <= s2; output <= "11010000";
elsif std_match(input, "11---") then next_state <= s3; output <= "10111000";
elsif std_match(input, "01---") then next_state <= s6; output <= "00110101";
end if;
when s4 =>
if std_match(input, "010--") then next_state <= s6; output <= "00100101";
elsif std_match(input, "--1--") then next_state <= s7; output <= "00101000";
elsif std_match(input, "110--") then next_state <= s3; output <= "10111000";
elsif std_match(input, "000--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "100--") then next_state <= s4; output <= "00101000";
end if;
when s5 =>
if std_match(input, "1-10-") then next_state <= s8; output <= "10000100";
elsif std_match(input, "--0--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "--11-") then next_state <= s8; output <= "10000100";
elsif std_match(input, "0-10-") then next_state <= s5; output <= "00001110";
end if;
when s6 =>
if std_match(input, "----1") then next_state <= s2; output <= "11000001";
elsif std_match(input, "10--0") then next_state <= s4; output <= "00101001";
elsif std_match(input, "00--0") then next_state <= s2; output <= "11000001";
elsif std_match(input, "11--0") then next_state <= s3; output <= "10111001";
elsif std_match(input, "01--0") then next_state <= s6; output <= "00100101";
end if;
when s7 =>
if std_match(input, "--0--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "101--") then next_state <= s7; output <= "00101000";
elsif std_match(input, "011--") then next_state <= s6; output <= "00100101";
elsif std_match(input, "111--") then next_state <= s3; output <= "10111000";
elsif std_match(input, "001--") then next_state <= s2; output <= "11000000";
end if;
when s8 =>
if std_match(input, "101--") then next_state <= s7; output <= "00101000";
elsif std_match(input, "--0--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "0-1--") then next_state <= s8; output <= "10000100";
elsif std_match(input, "111--") then next_state <= s3; output <= "10111000";
end if;
when others => next_state <= "--------"; output <= "--------";
end case;
end process;
end behaviour;
| agpl-3.0 | ad04635b6863c650a575c8bb12a90f57 | 0.582107 | 3.419329 | false | false | false | false |
berickson1/ECE492 | Quartus/BioLock.vhd | 1 | 20,628 | -- g9 - BioLock
-- Top level system file
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.vital_primitives.all;
use work.DE2_CONSTANTS.all;
entity BioLock is
port (
-- Reset and Clock
KEY : in std_logic_vector (0 downto 0);
CLOCK_50 : in std_logic;
CLOCK_27 : in std_logic;
-- Off Chip
GPIO_1 : inout std_logic_vector(35 downto 0);
CCD_DATA : in std_logic_vector(11 downto 0);
-- Switches
SW : in std_logic_vector (17 downto 0);
-- Green LEDs On Board
LEDG : out DE2_LED_GREEN;
-- LCD On Board
LCD_BLON : out std_logic;
LCD_ON : out std_logic;
LCD_DATA : inout DE2_LCD_DATA_BUS;
LCD_RS : out std_logic;
LCD_EN : out std_logic;
LCD_RW : out std_logic;
-- SDRAM On Board
DRAM_ADDR : out DE2_SDRAM_ADDR_BUS;
DRAM_BA_0 : out std_logic;
DRAM_BA_1 : out std_logic;
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
DRAM_DQ : inout DE2_SDRAM_DATA_BUS;
DRAM_LDQM : out std_logic;
DRAM_UDQM : out std_logic;
DRAM_RAS_N : out std_logic;
DRAM_WE_N : out std_logic;
-- SRAM On Board
SRAM_ADDR : out DE2_SRAM_ADDR_BUS;
SRAM_DQ : inout DE2_SRAM_DATA_BUS;
SRAM_WE_N : out std_logic;
SRAM_OE_N : out std_logic;
SRAM_UB_N : out std_logic;
SRAM_LB_N : out std_logic;
SRAM_CE_N : out std_logic;
-- Ethernet
ENET_CLK : out std_logic;
ENET_CMD : out std_logic;
ENET_CS_N : out std_logic;
ENET_INT : in std_logic;
ENET_RD_N : out std_logic;
ENET_WR_N : out std_logic;
ENET_RST_N : out std_logic;
ENET_DATA : inout std_logic_vector(15 downto 0);
-- SD Card
SD_CLK : out std_logic;
SD_CMD : inout std_logic;
SD_DAT : inout std_logic;
SD_DAT3 : inout std_logic;
-- Flash memory
FL_ADDR : out std_logic_vector (21 downto 0);
FL_CE_N : out std_logic_vector (0 downto 0);
FL_OE_N : out std_logic_vector (0 downto 0);
FL_DQ : inout std_logic_vector (7 downto 0);
FL_RST_N : out std_logic_vector (0 downto 0);
FL_WE_N : out std_logic_vector (0 downto 0);
-- Audio
AUD_ADCDAT: IN STD_LOGIC;
AUD_ADCLRCK: INOUT STD_LOGIC;
AUD_BCLK: INOUT STD_LOGIC;
AUD_DACDAT: OUT STD_LOGIC;
AUD_DACLRCK: INOUT STD_LOGIC;
AUD_XCK : OUT STD_LOGIC;
-- I2C
I2C_SCLK : out std_logic;
I2C_SDAT : inout std_logic
);
end BioLock;
architecture structure of BioLock is
component nios_system is
port (
clk_clk : in std_logic := 'X'; -- clk
clk_0_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n -- export
switches_external_connection_export : in std_logic_vector(17 downto 0) := (others => 'X'); -- export
green_leds_external_connection_export : out std_logic_vector(7 downto 0); -- export
character_lcd_0_external_interface_DATA : inout std_logic_vector(7 downto 0) := (others => 'X'); -- DATA
character_lcd_0_external_interface_ON : out std_logic; -- ON
character_lcd_0_external_interface_BLON : out std_logic; -- BLON
character_lcd_0_external_interface_EN : out std_logic; -- EN
character_lcd_0_external_interface_RS : out std_logic; -- RS
character_lcd_0_external_interface_RW : out std_logic; -- RW
altpll_0_c0_clk : out std_logic; -- clk
altpll_0_c2_clk : out std_logic; -- clk
altpll_1_c0_clk : out std_logic; -- clk
serial_external_connection_rxd : in std_logic := 'X'; -- rxd
serial_external_connection_txd : out std_logic; -- txd
sdram_0_wire_addr : out std_logic_vector(11 downto 0); -- addr
sdram_0_wire_ba : out std_logic_vector(1 downto 0); -- ba
sdram_0_wire_cas_n : out std_logic; -- cas_n
sdram_0_wire_cke : out std_logic; -- cke
sdram_0_wire_cs_n : out std_logic; -- cs_n
sdram_0_wire_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
sdram_0_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
sdram_0_wire_ras_n : out std_logic; -- ras_n
sdram_0_wire_we_n : out std_logic; -- we_n
sram_0_external_interface_DQ : inout std_logic_vector(15 downto 0) := (others => 'X'); -- DQ
sram_0_external_interface_ADDR : out std_logic_vector(17 downto 0); -- ADDR
sram_0_external_interface_LB_N : out std_logic; -- LB_N
sram_0_external_interface_UB_N : out std_logic; -- UB_N
sram_0_external_interface_CE_N : out std_logic; -- CE_N
sram_0_external_interface_OE_N : out std_logic; -- OE_N
sram_0_external_interface_WE_N : out std_logic; -- WE_N
dm9000a_if_0_s1_export_DATA : inout std_logic_vector(15 downto 0) := (others => 'X'); -- DATA
dm9000a_if_0_s1_export_CMD : out std_logic; -- CMD
dm9000a_if_0_s1_export_RD_N : out std_logic; -- RD_N
dm9000a_if_0_s1_export_WR_N : out std_logic; -- WR_N
dm9000a_if_0_s1_export_CS_N : out std_logic; -- CS_N
dm9000a_if_0_s1_export_RST_N : out std_logic; -- RST_N
dm9000a_if_0_s1_export_INT : in std_logic := 'X'; -- INT
dm9000a_if_0_s1_export_CLK : out std_logic;
sdcard_external_MISO : in std_logic := 'X'; -- MISO
sdcard_external_MOSI : out std_logic; -- MOSI
sdcard_external_SCLK : out std_logic; -- SCLK
sdcard_external_SS_n : out std_logic; -- SS_n
--Camera
camera_external_interface_SDAT : inout std_logic := 'X'; -- SDAT
camera_external_interface_SCLK : out std_logic; -- SCLK
d5m_decoder_external_interface_PIXEL_CLK : in std_logic := 'X'; -- PIXEL_CLK
d5m_decoder_external_interface_LINE_VALID : in std_logic := 'X'; -- LINE_VALID
d5m_decoder_external_interface_FRAME_VALID : in std_logic := 'X'; -- FRAME_VALID
d5m_decoder_external_interface_PIXEL_DATA : in std_logic_vector(11 downto 0) := (others => 'X'); -- PIXEL_DATA
camera_trigger_external_connection_export : out std_logic; -- export
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_read_n_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_read_n_out
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_data_out : inout std_logic_vector(7 downto 0) := (others => 'X'); -- generic_tristate_controller_0_tcm_data_out
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_chipselect_n_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_chipselect_n_out
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_write_n_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_write_n_out
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_address_out : out std_logic_vector(21 downto 0); -- generic_tristate_controller_0_tcm_address_out
solenoid_controller_external_connection_export : out std_logic; -- export := 'X' -- rxd
audio_out_external_interface_SDAT : inout std_logic := 'X'; -- SDAT
audio_out_external_interface_SCLK : out std_logic; -- SCLK
audio_external_interface_BCLK : in std_logic := 'X'; -- BCLK
audio_external_interface_DACDAT : out std_logic; -- DACDAT
audio_external_interface_DACLRCK : in std_logic := 'X' -- DACLRCK
);
end component nios_system;
-- signals to match provided IP core to specific SDRAM chip of our system
signal BA : std_logic_vector (1 downto 0);
signal DQM : std_logic_vector (1 downto 0);
begin
GPIO_1(17) <= '1'; --reset
GPIO_1(16) <= CLOCK_27;
DRAM_BA_1 <= BA(1);
DRAM_BA_0 <= BA(0);
DRAM_UDQM <= DQM(1);
DRAM_LDQM <= DQM(0);
FL_RST_N <= "1";
u0 : component nios_system
port map (
reset_reset_n => KEY(0), -- reset.reset_n
switches_external_connection_export => SW(17 downto 0), -- switches_external_connection.export
green_leds_external_connection_export => LEDG, -- green_leds_external_connection.export
character_lcd_0_external_interface_DATA => LCD_DATA, -- character_lcd_0_external_interface.DATA
character_lcd_0_external_interface_ON => LCD_ON, -- .ON
character_lcd_0_external_interface_BLON => LCD_BLON, -- .BLON
character_lcd_0_external_interface_EN => LCD_EN, -- .EN
character_lcd_0_external_interface_RS => LCD_RS, -- .RS
character_lcd_0_external_interface_RW => LCD_RW, -- .RW
altpll_0_c0_clk => DRAM_CLK, -- altpll_0_c0.clk
altpll_0_c2_clk => ENET_CLK, -- altpll_0_c2.clk
altpll_1_c0_clk => AUD_XCK, -- altpll_1_c0.clk
serial_external_connection_rxd => GPIO_1(26), -- GREEN serial_external_connection.rxd
serial_external_connection_txd => GPIO_1(28), -- WHITE .txd
sdram_0_wire_addr => DRAM_ADDR, -- sdram_0_wire.addr
sdram_0_wire_ba => BA, -- .ba
sdram_0_wire_cas_n => DRAM_CAS_N, -- .cas_n
sdram_0_wire_cke => DRAM_CKE, -- .cke
sdram_0_wire_cs_n => DRAM_CS_N, -- .cs_n
sdram_0_wire_dq => DRAM_DQ, -- .dq
sdram_0_wire_dqm => DQM, -- .dqm
sdram_0_wire_ras_n => DRAM_RAS_N, -- .ras_n
sdram_0_wire_we_n => DRAM_WE_N, -- .we_n
clk_clk => CLOCK_50, -- clk.clk
clk_0_clk => CLOCK_27, -- clk_0.clk
sram_0_external_interface_DQ => SRAM_DQ, -- sram_0_external_interface.DQ
sram_0_external_interface_ADDR => SRAM_ADDR, -- .ADDR
sram_0_external_interface_LB_N => SRAM_LB_N, -- .LB_N
sram_0_external_interface_UB_N => SRAM_UB_N, -- .UB_N
sram_0_external_interface_CE_N => SRAM_CE_N, -- .CE_N
sram_0_external_interface_OE_N => SRAM_OE_N, -- .OE_N
sram_0_external_interface_WE_N => SRAM_WE_N, -- .WE_N
dm9000a_if_0_s1_export_DATA => ENET_DATA, -- dm9000a_if_0_s1_export.DATA
dm9000a_if_0_s1_export_CMD => ENET_CMD, -- .CMD
dm9000a_if_0_s1_export_RD_N => ENET_RD_N, -- .RD_N
dm9000a_if_0_s1_export_WR_N => ENET_WR_N, -- .WR_N
dm9000a_if_0_s1_export_CS_N => ENET_CS_N, -- .CS_N
dm9000a_if_0_s1_export_RST_N => ENET_RST_N, -- .RST_N
dm9000a_if_0_s1_export_INT => ENET_INT, -- .INT
--dm9000a_if_0_s1_export_CLK => ENET_CLK, -- .CLK
sdcard_external_MISO => SD_DAT, -- sdcard_external.MISO
sdcard_external_MOSI => SD_CMD, -- .MOSI
sdcard_external_SCLK => SD_CLK, -- .SCLK
sdcard_external_SS_n => SD_DAT3, -- .SS_n
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_read_n_out => FL_OE_N, -- tristate_conduit_bridge_0_out.generic_tristate_controller_0_tcm_read_n_out
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_data_out => FL_DQ, -- .generic_tristate_controller_0_tcm_data_out
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_chipselect_n_out => FL_CE_N, -- .generic_tristate_controller_0_tcm_chipselect_n_out
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_write_n_out => FL_WE_N, -- .generic_tristate_controller_0_tcm_write_n_out
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_address_out => FL_ADDR, -- .generic_tristate_controller_0_tcm_address_out
camera_external_interface_SDAT => GPIO_1(23), -- camera_external_interface.SDAT
camera_external_interface_SCLK => GPIO_1(24), -- .SCLK
d5m_decoder_external_interface_PIXEL_CLK => GPIO_1(0), -- d5m_decoder_external_interface.PIXEL_CLK
d5m_decoder_external_interface_LINE_VALID => GPIO_1(21), -- .LINE_VALID
d5m_decoder_external_interface_FRAME_VALID => GPIO_1(22), -- .FRAME_VALID
d5m_decoder_external_interface_PIXEL_DATA => CCD_DATA,
camera_trigger_external_connection_export => GPIO_1(19), -- camera_trigger_external_connection.export
solenoid_controller_external_connection_export => GPIO_1(30),
audio_out_external_interface_SDAT => I2C_SDAT, -- audio_out_external_interface.SDAT
audio_out_external_interface_SCLK => I2C_SCLK, -- .SCLK
audio_external_interface_BCLK => AUD_BCLK, -- audio_external_interface.BCLK
audio_external_interface_DACDAT => AUD_DACDAT, -- .DACDAT
audio_external_interface_DACLRCK => AUD_DACLRCK -- .DACLRCK
);
end structure;
library ieee;
--DE2 Constants
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.vital_primitives.all;
package DE2_CONSTANTS is
subtype DE2_LCD_DATA_BUS is std_logic_vector(7 downto 0);
subtype DE2_LED_GREEN is std_logic_vector(7 downto 0);
subtype DE2_SRAM_ADDR_BUS is std_logic_vector(17 downto 0);
subtype DE2_SRAM_DATA_BUS is std_logic_vector(15 downto 0);
subtype DE2_SDRAM_ADDR_BUS is std_logic_vector(11 downto 0);
subtype DE2_SDRAM_DATA_BUS is std_logic_vector(15 downto 0);
end DE2_CONSTANTS;
| gpl-2.0 | d3dd33f346c4b31e4eefd5c297f9579d | 0.392525 | 4.288565 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/openmac/src/openmac-rtl-ea.vhd | 1 | 69,475 | -------------------------------------------------------------------------------
--! @file openmac-rtl-ea.vhd
--
--! @brief openMAC core
--
--! @details This is the openMAC core file implementing the MAC functionality.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2009
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity openmac is
generic (
--! Dma address high bit
gDmaHighAddr : in integer := 16;
--! Enable MAC timer
gTimerEnable : in boolean := false;
--! Enable Timer triggered Tx
gTimerTrigTx : in boolean := false;
--! Enable Auto-response delay
gAutoTxDel : in boolean := false
);
port (
--! Reset
iRst : in std_logic;
--! Clock (RMII, 50 MHz)
iClk : in std_logic;
--! Write to RAM or content (low-active)
inWrite : in std_logic;
--! Select RAM (descriptor and Rx filter)
iSelectRam : in std_logic;
--! Select content (Tx/Rx status/control registers)
iSelectCont : in std_logic;
--! Byteenable (low-active)
inByteenable : in std_logic_vector(1 downto 0);
--! Address for RAM or content
iAddress : in std_logic_vector(10 downto 1);
--! Writedata to RAM or content
iWritedata : in std_logic_vector(15 downto 0);
--! Readdata from RAM or content
oReaddata : out std_logic_vector(15 downto 0);
--! Tx interrupt request (low-active)
onTxIrq : out std_logic;
--! Rx interrupt request (low-active)
onRxIrq : out std_logic;
--! Tx begin interrupt request (low-active)
onTxBegIrq : out std_logic;
--! DMA read transfer for frame done
oDmaReadDone : out std_logic;
--! DMA write transfer for frame done
oDmaWriteDone : out std_logic;
--! DMA request strobe
oDmaReq : out std_logic;
--! DMA write strobe (low-active)
onDmaWrite : out std_logic;
--! DMA acknowledge input
iDmaAck : in std_logic;
--! DMA request overflow flag
oDmaReqOverflow : out std_logic;
--! DMA read request length
oDmaReadLength : out std_logic_vector(11 downto 0);
--! DMA address
oDmaAddress : out std_logic_vector(gDmaHighAddr downto 1);
--! DMA writedata
oDmaWritedata : out std_logic_vector(15 downto 0);
--! DMA readdata
iDmaReaddata : in std_logic_vector(15 downto 0);
--! RMII Rx data
iRxData : in std_logic_vector(1 downto 0);
--! RMII Rx data valid
iRxDv : in std_logic;
--! RMII Tx data
oTxData : out std_logic_vector(1 downto 0);
--! RMII Tx enable
oTxEn : out std_logic;
--! Hub Rx port (connect to openHUB)
iHubRxPort : in std_logic_vector(1 downto 0);
--! MAC Time
oMacTime : out std_logic_vector(31 downto 0)
);
end entity openmac;
architecture struct OF openmac is
signal Rx_Dv : std_logic;
signal R_Req : std_logic;
signal Auto_Desc : std_logic_vector( 3 downto 0);
signal Zeit : std_logic_vector(31 downto 0);
signal Tx_Dma_Req : std_logic;
signal Rx_Dma_Req : std_logic;
signal Tx_Dma_Ack : std_logic;
signal Rx_Dma_Ack : std_logic;
signal Tx_Ram_Dat : std_logic_vector(15 downto 0);
signal Rx_Ram_Dat : std_logic_vector(15 downto 0);
signal Tx_Dma_Len : std_logic_vector(11 downto 0);
signal Tx_Reg : std_logic_vector(15 downto 0);
signal Rx_Reg : std_logic_vector(15 downto 0);
signal Dma_Tx_Addr : std_logic_vector(oDmaAddress'range);
signal Dma_Rx_Addr : std_logic_vector(oDmaAddress'range);
signal Dma_Req_s : std_logic;
signal Dma_Rw_s : std_logic;
signal halfDuplex : std_logic; -- cActivated ... MAC in half-duplex mode
signal Tx_Active : std_logic; -- cActivated ... TX = Data or CRC
signal Tx_Dma_Very1stOverflow : std_logic; -- cActivated ... very first TX DMA overflow
signal Tx_Col : std_logic;
signal Sel_Tx_Ram : std_logic;
signal Sel_Tx_Reg : std_logic;
signal Tx_LatchH : std_logic_vector(7 downto 0);
signal Tx_LatchL : std_logic_vector(7 downto 0);
begin
oReaddata <= Tx_Ram_Dat when iSelectRam = '1' and Sel_Tx_Ram = '1' else
Rx_Ram_Dat when iSelectRam = '1' else
Tx_Reg when iSelectCont = '1' and Sel_Tx_Reg = '1' else
Rx_Reg;
oMacTime <= Zeit;
oDmaReadLength <= Tx_Dma_Len + 4;
b_DmaObserver : block
signal dmaObserverCounter, dmaObserverCounterNext : std_logic_vector(2 downto 0);
constant cDmaObserverCounterHalf : std_logic_vector(dmaObserverCounter'range) := "110"; --every 8th cycle
constant cDmaObserverCounterFull : std_logic_vector(dmaObserverCounter'range) := "010"; --every 4th cycle
begin
process(iClk, iRst)
begin
if iRst = '1' then
dmaObserverCounter <= (others => cInactivated);
elsif rising_edge(iClk) then
dmaObserverCounter <= dmaObserverCounterNext;
end if;
end process;
oDmaReqOverflow <= --very first TX Dma transfer
Dma_Req_s when Tx_Dma_Very1stOverflow = cActivated and Tx_Active = cInactivated else
--RX Dma transfers and TX Dma transfers without the very first
Dma_Req_s when dmaObserverCounterNext = cDmaObserverCounterHalf and halfDuplex = cActivated else
Dma_Req_s when dmaObserverCounterNext = cDmaObserverCounterFull and halfDuplex = cInactivated else
cInactivated;
dmaObserverCounterNext <= --increment counter if DMA Read req (TX) during data and crc
dmaObserverCounter + 1 when Dma_Req_s = cActivated and Dma_Rw_s = cActivated
and Tx_Active = cActivated else
--increment counter if DMA Write req (RX)
dmaObserverCounter + 1 when Dma_Req_s = cActivated and Dma_Rw_s = cInactivated else
(others => cInactivated); --reset DmaObserverCounter if no oDmaReq
end block;
b_Dma: block
signal Rx_Dma : std_logic;
signal Tx_Dma : std_logic;
begin
oDmaReq <= Dma_Req_s;
Dma_Req_s <= '1' when (Tx_Dma_Req = '1' and Tx_Dma_Ack = '0') or Rx_Dma_Req = '1' else '0';
onDmaWrite <= Dma_Rw_s;
Dma_Rw_s <= '1' when (Rx_Dma = '0' and Tx_Dma_Req = '1' and Tx_Dma_Ack = '0') or Tx_Dma = '1' else '0';
oDmaAddress <= Dma_Tx_Addr when (Rx_Dma = '0' and Tx_Dma_Req = '1' and Tx_Dma_Ack = '0') or Tx_Dma = '1' else Dma_Rx_Addr;
Rx_Dma_Ack <= '1' when Rx_Dma = '1' and iDmaAck = '1' else '0';
pDmaArb: process( iClk, iRst ) is
begin
if iRst = '1' then
Rx_Dma <= '0'; Tx_Dma <= '0'; Tx_Dma_Ack <= '0';
Tx_LatchH <= (others => '0'); Tx_LatchL <= (others => '0');
Zeit <= (others => '0');
elsif rising_edge( iClk ) then
if gTimerEnable then
Zeit <= Zeit + 1;
end if;
Sel_Tx_Ram <= iAddress(8);
Sel_Tx_Reg <= not iAddress(3);
if iDmaAck = '0' then
if Rx_Dma = '0' and Tx_Dma_Req = '1' and Tx_Dma_Ack = '0' then Tx_Dma <= '1';
elsif Tx_Dma = '0' and Rx_Dma_Req = '1' then Rx_Dma <= '1';
end if;
else
if Rx_Dma = '1' and Tx_Dma_Req = '1' and Tx_Dma_Ack = '0' then Tx_Dma <= '1'; Rx_Dma <= '0';
elsif Tx_Dma = '1' and Rx_Dma_Req = '1' then Tx_Dma <= '0'; Rx_Dma <= '1';
else Tx_Dma <= '0'; Rx_Dma <= '0';
end if;
end if;
if Tx_Dma = '1' and iDmaAck = '1' then Tx_Dma_Ack <= '1';
else Tx_Dma_Ack <= '0';
end if;
if Tx_Dma_Ack = '1' then Tx_LatchL <= iDmaReaddata(15 downto 8);
Tx_LatchH <= iDmaReaddata( 7 downto 0);
end if;
end if;
end process pDmaArb;
end block b_Dma;
b_Full_Tx : block
type tTxState is (
sIdle,
sBop,
sPre,
sTxd,
sCrc,
sCol,
sJam
);
signal Sm_Tx : tTxState;
signal Start_Tx : std_logic;
signal ClrCol : std_logic;
signal Tx_On : std_logic;
signal Dibl_Cnt : std_logic_vector(1 downto 0);
signal F_End : std_logic;
signal Was_Col : std_logic;
signal Block_Col : std_logic;
signal Ipg_Cnt : std_logic_vector(7 downto 0);
signal Tx_Timer : std_logic_vector(7 downto 0);
alias Ipg : std_logic is Ipg_Cnt(7);
alias Tx_Time : std_logic is Tx_Timer(7);
signal Tx_Ipg : std_logic_vector(5 downto 0);
signal Tx_Count : std_logic_vector(11 downto 0);
signal Tx_En : std_logic;
signal F_Val : std_logic;
signal Tx_Half : std_logic;
signal Tx_Sr : std_logic_vector(7 downto 0);
signal F_TxB : std_logic_vector(7 downto 0);
signal Crc : std_logic_vector(31 downto 0);
signal CrcDin : std_logic_vector(1 downto 0);
signal Tx_Dat : std_logic_vector(1 downto 0);
signal Col_Cnt : std_logic_vector(3 downto 0);
signal Auto_Coll : std_logic;
signal Rnd_Num : std_logic_vector(9 downto 0);
signal Retry_Cnt : std_logic_vector(9 downto 0);
signal Max_Retry : std_logic_vector(3 downto 0);
begin
oTxEn <= Tx_En;
oTxData <= Tx_Dat;
halfDuplex <= Tx_Half;
Tx_Active <= cActivated when Sm_Tx = sTxd or Sm_Tx = sCrc else cInactivated;
pTxSm: process ( iClk, iRst ) is
begin
if iRst = '1' then
Sm_Tx <= sIdle;
elsif rising_edge( iClk ) then
if Sm_Tx = sIdle or Sm_Tx = sBop or Dibl_Cnt = "11" then
case Sm_Tx is
when sIdle => if Start_Tx = '1'
and (Tx_Half = '0' or Rx_Dv = '0')
and Ipg = '0' then Sm_Tx <= sBop; end if;
when sBop => Sm_Tx <= sPre;
when sPre => if Tx_Time = '1' then Sm_Tx <= sTxd; end if;
when sTxd => if Was_Col = '1' then Sm_Tx <= sCol;
elsif Tx_Count = 0 then Sm_Tx <= sCrc; end if;
when sCol => Sm_Tx <= sJam;
when sJam => if Tx_Time = '1' then Sm_Tx <= sIdle;
end if;
when sCrc => if Was_Col = '1' then Sm_Tx <= sCol;
elsif Tx_Time = '1' then Sm_Tx <= sIdle; end if;
when others => NULL;
end case;
end if;
end if;
end process pTxSm;
pTxCtl: process ( iClk, iRst ) is
variable vPreload : std_logic_vector(Tx_Timer'range);
variable vLoad : std_logic;
begin
if iRst = '1' then
Tx_Dat <= "00"; Tx_En <= '0'; Dibl_Cnt <= "00"; F_End <= '0'; F_Val <= '0'; Tx_Col <= '0'; Was_Col <= '0'; Block_Col <= '0';
Ipg_Cnt <= (others => '0'); Tx_Timer <= (others => '0'); Tx_Sr <= (others => '0');
elsif rising_edge( iClk ) then
if Sm_Tx = sBop then Dibl_Cnt <= "00";
else Dibl_Cnt <= Dibl_Cnt + 1;
end if;
if Tx_En = '1' then Ipg_Cnt <= "1" & conv_std_logic_vector( 44, 7);
elsif Rx_Dv = '1' and Tx_Half = '1' then Ipg_Cnt <= "10" & Tx_Ipg;
elsif Ipg = '1' then Ipg_Cnt <= Ipg_Cnt - 1;
end if;
if Dibl_Cnt = "11" and Sm_Tx = sCrc and Tx_Time = '1' then F_End <= '1';
elsif Dibl_Cnt = "11" and Sm_Tx = sCol then
if Col_Cnt = (Max_Retry - 1) then F_End <= '1';
elsif Col_Cnt < x"E" then Tx_Col <= '1';
else F_End <= '1';
end if;
else F_End <= '0';
Tx_Col <= '0';
end if;
if Tx_Half = '1' and Rx_Dv = '1'
and (Sm_Tx = sPre or Sm_Tx = sTxd) then Was_Col <= '1';
elsif Sm_Tx = sCol then Was_Col <= '0';
end if;
if Sm_Tx = sCol then Block_Col <= '1';
elsif Auto_Coll = '1' then Block_Col <= '0';
elsif Retry_Cnt = 0 then Block_Col <= '0';
end if;
if Dibl_Cnt = "10" and Sm_Tx = sPre and Tx_Time = '1' then F_Val <= '1';
elsif Dibl_Cnt = "10" and Sm_Tx = sTxd then F_Val <= '1';
else F_Val <= '0';
end if;
vLoad := '0';
if Sm_Tx = sBop then vPreload := x"06"; vLoad := '1';
elsif Sm_Tx = sTxd then vPreload := x"02"; vLoad := '1';
elsif Sm_Tx = sCol then vPreload := x"01"; vLoad := '1';
elsif Tx_Time = '1' then vPreload := x"3e"; vLoad := '1';
end if;
if Dibl_Cnt = "11" or Sm_Tx = sBop then
if vLoad = '1' then Tx_Timer <= vPreload;
else Tx_Timer <= Tx_Timer - 1;
end if;
end if;
if F_Val = '1' then Tx_Sr <= F_TxB;
else Tx_Sr <= "00" & Tx_Sr(7 downto 2);
end if;
if Sm_Tx = sPre then Tx_En <= '1';
elsif Sm_Tx = sIdle or (Sm_Tx = sJam and Tx_Time = '1') then Tx_En <= '0';
end if;
if Sm_Tx = sPre and Tx_Time = '1' and Dibl_Cnt = "11" then Tx_Dat <= "11";
elsif Sm_Tx = sPre then Tx_Dat <= "01";
elsif Sm_Tx = sTxd then Tx_Dat <= CrcDin;
elsif Sm_Tx = sCrc then Tx_Dat <= not Crc(30) & not Crc(31);
elsif Sm_Tx = sCol or Sm_Tx = sJam then Tx_Dat <= "11";
else Tx_Dat <= "00";
end if;
end if;
end process pTxCtl;
pBackDel: process ( iClk, iRst ) is
begin
if iRst = '1' then
Rnd_Num <= (others => '0');
Col_Cnt <= (others => '0');
Retry_Cnt <= (others => '0');
elsif rising_edge( iClk ) then
Rnd_Num <= Rnd_Num(8 downto 0) & (Rnd_Num(9) xor not Rnd_Num(2));
if ClrCol = '1' then Col_Cnt <= x"0";
elsif Dibl_Cnt = "11" and Sm_Tx = sCol then Col_Cnt <= Col_Cnt + 1;
end if;
if Dibl_Cnt = "11" then
if Tx_On = '0' or Auto_Coll = '1' then Retry_Cnt <= (others => '0');
elsif Sm_Tx = sCol then
for i in 0 to 9 loop
if Col_Cnt >= i then Retry_Cnt(i) <= Rnd_Num(i);
else Retry_Cnt(i) <= '0';
end if;
end loop;
elsif Sm_Tx /= sJam and Tx_Time = '1' and Retry_Cnt /= 0 then Retry_Cnt <= Retry_Cnt - 1;
end if;
end if;
end if;
end process pBackDel;
CrcDin <= Tx_Sr(1 downto 0);
Calc: process ( iClk, Crc, CrcDin, Sm_Tx ) is
variable H : std_logic_vector(1 downto 0);
begin
H(0) := Crc(31) xor CrcDin(0);
H(1) := Crc(30) xor CrcDin(1);
if rising_edge( iClk ) then
if Sm_Tx = sPre then Crc <= x"FFFFFFFF";
elsif Sm_Tx = sCrc then Crc <= Crc(29 downto 0) & "00";
else
Crc( 0) <= H(1);
Crc( 1) <= H(0) xor H(1);
Crc( 2) <= Crc( 0) xor H(0) xor H(1);
Crc( 3) <= Crc( 1) xor H(0) ;
Crc( 4) <= Crc( 2) xor H(1);
Crc( 5) <= Crc( 3) xor H(0) xor H(1);
Crc( 6) <= Crc( 4) xor H(0) ;
Crc( 7) <= Crc( 5) xor H(1);
Crc( 8) <= Crc( 6) xor H(0) xor H(1);
Crc( 9) <= Crc( 7) xor H(0) ;
Crc(10) <= Crc( 8) xor H(1);
Crc(11) <= Crc( 9) xor H(0) xor H(1);
Crc(12) <= Crc(10) xor H(0) xor H(1);
Crc(13) <= Crc(11) xor H(0) ;
Crc(14) <= Crc(12) ;
Crc(15) <= Crc(13) ;
Crc(16) <= Crc(14) xor H(1);
Crc(17) <= Crc(15) xor H(0) ;
Crc(18) <= Crc(16) ;
Crc(19) <= Crc(17) ;
Crc(20) <= Crc(18) ;
Crc(21) <= Crc(19) ;
Crc(22) <= Crc(20) xor H(1);
Crc(23) <= Crc(21) xor H(0) xor H(1);
Crc(24) <= Crc(22) xor H(0) ;
Crc(25) <= Crc(23) ;
Crc(26) <= Crc(24) xor H(1);
Crc(27) <= Crc(25) xor H(0) ;
Crc(28) <= Crc(26) ;
Crc(29) <= Crc(27) ;
Crc(30) <= Crc(28) ;
Crc(31) <= Crc(29) ;
end if;
end if;
end process Calc;
bTxDesc: block
type tDescState is (
sIdle,
sLen,
sTimL,
sTimH,
sAdrH,
sAdrL,
sReq,
sBegL,
sBegH,
sDel,
sData,
sStat,
sColl
);
signal Dsm : tDescState;
signal Tx_Dsm_Next : tDescState;
signal DescRam_Out : std_logic_vector(15 downto 0);
signal DescRam_In : std_logic_vector(15 downto 0);
alias TX_LEN : std_logic_vector(11 downto 0) is DescRam_Out(11 downto 0);
alias TX_OWN : std_logic is DescRam_Out(8);
alias TX_LAST : std_logic is DescRam_Out(9);
alias TX_READY : std_logic is DescRam_Out(10);
alias TX_BEGDEL : std_logic is DescRam_Out(12);
alias TX_BEGON : std_logic is DescRam_Out(13);
alias TX_TIME : std_logic is DescRam_Out(14);
alias TX_RETRY : std_logic_vector( 3 downto 0) is DescRam_Out(3 downto 0);
signal Ram_Be : std_logic_vector( 1 downto 0);
signal Ram_Wr : std_logic;
signal Desc_We : std_logic;
signal Desc_Addr : std_logic_vector( 7 downto 0);
signal DescIdx : std_logic_vector( 2 downto 0);
signal Last_Desc : std_logic;
signal ZeitL : std_logic_vector(15 downto 0);
signal Tx_Ie : std_logic;
signal Tx_Wait : std_logic;
signal Tx_BegInt : std_logic;
signal Tx_BegSet : std_logic;
signal Tx_Early : std_logic;
signal Tx_Del : std_logic;
signal Ext_Tx : std_logic;
signal Ext_Ack : std_logic;
signal Tx_Desc : std_logic_vector( 3 downto 0);
signal Tx_Desc_One : std_logic_vector( 3 downto 0);
signal Ext_Desc : std_logic_vector( 3 downto 0);
signal Tx_Icnt : std_logic_vector( 4 downto 0);
signal Tx_SoftInt : std_logic;
signal Sel_TxH : std_logic;
signal Sel_TxL : std_logic;
signal H_Byte : std_logic;
signal Tx_Buf : std_logic_vector( 7 downto 0);
signal Tx_Idle : std_logic;
signal TxInt : std_logic;
signal Tx_Beg : std_logic;
signal Tx_Sync : std_logic;
signal Tx_Ident : std_logic_vector( 1 downto 0);
signal Tx_Cmp_High : std_logic_vector(15 downto 0);
signal Start_TxS : std_logic;
signal Tx_Dma_Out : std_logic;
signal Tx_Del_Cnt : std_logic_vector(32 downto 0);
alias Tx_Del_End : std_logic is Tx_Del_Cnt(Tx_Del_Cnt'high);
signal Tx_Del_Run : std_logic;
signal Tx_Done : std_logic;
begin
oDmaReadDone <= Tx_Done;
Tx_Done <= '1' when Dsm = sStat or Dsm = sColl else '0';
Tx_Dma_Very1stOverflow <= cActivated when Dibl_Cnt = "01" and Sm_Tx = sPre and Tx_Timer(7) = '1' else cInactivated;
Ram_Wr <= '1' when inWrite = '0' and iSelectRam = '1' and iAddress(10) = '1' else '0';
Ram_Be(1) <= '1' when inWrite = '1' or inByteenable(1) = '0' else '0';
Ram_Be(0) <= '1' when inWrite = '1' or inByteenable(0) = '0' else '0';
DescIdx <= "000" when Desc_We = '0' and Tx_Dsm_Next = sIdle else
"000" when Desc_We = '1' and Dsm = sIdle else
"001" when Desc_We = '0' and Tx_Dsm_Next = sLen else
"001" when Desc_We = '1' and Dsm = sLen else
"010" when Desc_We = '0' and Tx_Dsm_Next = sAdrH else
"010" when Desc_We = '1' and Dsm = sAdrH else
"011" when Desc_We = '0' and Tx_Dsm_Next = sAdrL else
"011" when Desc_We = '1' and Dsm = sAdrL else
"100" when Desc_We = '0' and Tx_Dsm_Next = sBegH else
"100" when Desc_We = '1' and Dsm = sBegH else
"101" when Desc_We = '0' and Tx_Dsm_Next = sBegL else
"101" when Desc_We = '1' and Dsm = sBegL else
"110" when Desc_We = '0' and Tx_Dsm_Next = sTimH else
"110" when Desc_We = '1' and Dsm = sTimH else
"111" when Desc_We = '0' and Tx_Dsm_Next = sTimL else
"111" when Desc_We = '1' and Dsm = sTimL else
"111" when Desc_We = '0' and Tx_Dsm_Next = sData else
"111" when Desc_We = '1' and Dsm = sData else
"000";
Desc_We <= '1' when Dsm = sTimL or Dsm = sTimH or Dsm = sStat else '0';
Desc_Addr <= '1' & Tx_Desc & DescIdx when Ext_Tx = '0' else
'1' & Ext_Desc & DescIdx;
gTxTime: if gTimerEnable generate
DescRam_In <= Zeit(15 downto 0) when Dsm = sTimH else
ZeitL when Dsm = sTimL else
x"000" & "01" & Tx_Ident when Dsm = sBegL else
Tx_Dma_Out & Tx_Sync & "00" & "0100" & "00" & "0" & "0" & Col_Cnt;
end generate;
gnTxTime: if not gTimerEnable generate
DescRam_In <= x"000" & "01" & Tx_Ident when Dsm = sBegL else
Tx_Dma_Out & Tx_Sync & "00" & "0100" & "00" & "0" & "0" & Col_Cnt;
end generate;
--! This DPRAM holds the Tx descriptor accessible by the host and the DMA.
TXRAM : entity work.dpRamOpenmac
generic map (
gWordWidth => iWritedata'length,
gNumberOfWords => 256,
gInitFile => "UNUSED"
)
port map (
iClk_A => iClk,
iEnable_A => cActivated,
iWriteEnable_A => Ram_Wr,
iAddress_A => iAddress(8 downto 1),
iByteenable_A => Ram_Be,
iWritedata_A => iWritedata,
oReaddata_A => Tx_Ram_Dat,
iClk_B => iClk,
iEnable_B => cActivated,
iWriteEnable_B => Desc_We,
iByteenable_B => (others => cActivated),
iAddress_B => Desc_Addr,
iWritedata_B => DescRam_In,
oReaddata_B => DescRam_Out
);
assert not( gTimerTrigTx and not gTimerEnable )
report "Time Triggered Tx needs Timer!"
severity failure;
pTxSm: process( Dsm,
Tx_On, TX_OWN, Retry_Cnt, Ext_Tx, Tx_Wait,
Tx_Sync, Sm_Tx, F_End, Tx_Col, Ext_Ack, Tx_Del, Tx_Beg, Tx_Half, Tx_Del_End,
iRxDv )
begin
Tx_Dsm_Next <= Dsm;
case Dsm is
when sIdle => if Tx_On = '1' and TX_OWN = '1' and Retry_Cnt = 0 then
if (Ext_Tx = '1' and Ext_Ack = '0') or Tx_Wait = '0' then
Tx_Dsm_Next <= sAdrH; --sLen;
end if;
end if;
when sLen => if Tx_Sync = '0' then Tx_Dsm_Next <= sReq; --sAdrH;
else Tx_Dsm_Next <= sBegH;
end if;
when sBegH => Tx_Dsm_Next <= sBegL;
when sBegL => if Tx_On = '0' then Tx_Dsm_Next <= sIdle;
elsif Tx_Sync = '0' then
if Tx_Del = '1' then Tx_Dsm_Next <= sDel;
elsif Sm_Tx = sPre then
Tx_Dsm_Next <= sTimH;
end if;
elsif Tx_Sync = '1' and Tx_Beg = '1' and Tx_Half = '1' and iRxDv = '1' then
Tx_Dsm_Next <= sColl;
elsif Tx_Beg = '1' then Tx_Dsm_Next <= sReq;
end if;
when sDel => if Tx_On = '0' then Tx_Dsm_Next <= sIdle; --avoid FSM hang
elsif Tx_Del_End = '1' then Tx_Dsm_Next <= sTimH;
end if;
when sAdrH => Tx_Dsm_Next <= sAdrL;
when sAdrL => Tx_Dsm_Next <= sLen; --sReq;
--leaving sAdrL and entering sReq leads to the very first Tx_Dma_Req
-- this enables early dma req at the beginning of IPG (auto-resp)
when sReq => if Tx_On = '0' then Tx_Dsm_Next <= sIdle;
elsif Tx_Del = '1' then Tx_Dsm_Next <= sBegH;
elsif Tx_Sync = '0' then Tx_Dsm_Next <= sBegL;
elsif Sm_Tx = sBop then Tx_Dsm_Next <= sTimH;
end if;
when sTimH => Tx_Dsm_Next <= sTimL;
when sTimL => Tx_Dsm_Next <= sData;
when sData => if F_End = '1' then Tx_Dsm_Next <= sStat;
elsif Tx_Col = '1' then Tx_Dsm_Next <= sColl;
end if;
when sStat => Tx_Dsm_Next <= sIdle;
when sColl => if sm_tx = sIdle then
if Tx_Sync = '1' then Tx_Dsm_Next <= sStat;
else Tx_Dsm_Next <= sIdle;
end if;
end if;
when others =>
end case;
end process pTxSm;
pTxSmClk : process(iRst, iClk)
begin
if iRst = cActivated then
Dsm <= sIdle;
elsif rising_edge(iClk) then
Dsm <= Tx_Dsm_Next;
end if;
end process pTxSmClk;
pTxControl: process( iRst, iClk )
begin
if iRst = '1' then
Last_Desc <= '0'; Start_TxS <= '0'; Tx_Dma_Req <= '0'; H_Byte <= '0';
Tx_Beg <= '0'; Tx_BegSet <= '0'; Tx_Early <= '0'; Auto_Coll <= '0'; Tx_Dma_Out <= '0';
Ext_Tx <= '0'; Ext_Ack <= '0'; ClrCol <= '0'; Ext_Desc <= (others => '0'); Tx_Sync <= '0'; Max_Retry <= (others => '0');
ZeitL <= (others => '0'); Tx_Count <= (others => '0'); Tx_Ident <= "00";
Dma_Tx_Addr <= (others => '0'); Tx_Cmp_High <= (others => '0');
Tx_Del_Run <= '0';
Tx_Del <= '0'; Tx_Del_Cnt <= (others => '0'); Tx_Dma_Len <= (others => '0');
elsif rising_edge( iClk ) then
if gTimerTrigTx = true then
if Tx_Sync = '1' and Dsm = sBegL and (DescRam_Out & Tx_Cmp_High ) = Zeit then Tx_Beg <= '1';
else Tx_Beg <= '0';
end if;
end if;
if Dsm = sStat and Desc_We = '1' then ClrCol <= '1';
else ClrCol <= '0';
end if;
if gTimerEnable then
if Dsm = sTimH then ZeitL <= Zeit(31 downto 16);
end if;
end if;
if Ext_Ack = '0' and R_Req = '1' then Ext_Desc <= Auto_Desc;
Ext_Ack <= '1';
elsif Ext_Tx = '1' or Tx_On = '0' then Ext_Ack <= '0';
end if;
if Dsm = sIdle and Ext_Ack = '1' then Ext_Tx <= '1';
elsif Dsm = sStat or Tx_Col = '1' or Tx_On = '0' then Ext_Tx <= '0';
end if;
if (F_End = '1' or Tx_On = '0'
or (Tx_Col = '1' and Ext_Tx = '1' )
or dsm = sColl ) then Start_TxS <= '0';
Auto_Coll <= Auto_Coll or (Tx_Col and Ext_Tx);
elsif Dsm = sReq and Tx_Del = '0' then Start_TxS <= '1';
elsif Dsm = sDel and Tx_Del_End = '1' then Start_TxS <= '1';
elsif Sm_Tx = sIdle then Auto_Coll <= '0';
end if;
if Dsm = sIdle then Last_Desc <= TX_LAST;
end if;
if Dsm = sLen then Tx_Count <= TX_LEN; Tx_Dma_Len <= TX_LEN; --add CRC
elsif F_Val = '1' then Tx_Count <= Tx_Count - 1;
end if;
if Dsm = sBegH then Tx_Cmp_High <= DescRam_Out;
end if;
if Dsm = sIdle and Tx_On = '1' and TX_OWN = '1' and Retry_Cnt = 0 then
if Ext_Tx = '1' or Tx_Wait = '0' then
if gTimerTrigTx then Tx_Sync <= TX_TIME;
else Tx_Sync <= '0';
end if;
Max_Retry <= TX_RETRY;
Tx_Early <= TX_BEGON;
if gAutoTxDel = true then Tx_Del <= TX_BEGDEL;
end if;
end if;
elsif Dsm = sTimH then Tx_BegSet <= Tx_Early;
elsif Dsm = sTimL then Tx_BegSet <= '0';
elsif Dsm = sIdle then Tx_Del <= '0';
end if;
if gAutoTxDel = true and Tx_Del = '1' then
if Dsm = sBegH then Tx_Del_Cnt(Tx_Del_Cnt'high) <= '0';
Tx_Del_Cnt(15 downto 0) <= DescRam_Out;
elsif Dsm = sBegL then Tx_Del_Cnt(31 downto 16) <= DescRam_Out;
elsif Dsm = sDel and Tx_Del_Run = '1' then Tx_Del_Cnt <= Tx_Del_Cnt - 1;
end if;
if Tx_Del_Run = '0' and Dsm = sDel then Tx_Del_Run <= '1'; --don't consider Ipg
elsif Tx_Del_End = '1' then Tx_Del_Run <= '0';
end if;
end if;
if Dsm = sAdrL then --Dma_Tx_Addr(15 downto 1) <= DescRam_Out(15 downto 1);
Dma_Tx_Addr(oDmaAddress'high downto 16) <= DescRam_Out(oDmaAddress'high-16 downto 0);
Tx_Ident <= DescRam_Out(15 downto 14);
elsif Tx_Dma_Ack = '1' then Dma_Tx_Addr(15 downto 1) <= Dma_Tx_Addr(15 downto 1) + 1;
end if;
if Dsm = sAdrH then Dma_Tx_Addr(15 downto 1) <= DescRam_Out(15 downto 1);
-- Dma_Tx_Addr(oDmaAddress'high downto 16) <= DescRam_Out(oDmaAddress'high-16 downto 0);
-- Tx_Ident <= DescRam_Out(15 downto 14);
elsif Tx_Dma_Ack = '1' and Dma_Tx_Addr(15 downto 1) = x"FFF" & "111" then
Dma_Tx_Addr(oDmaAddress'high downto 16) <= Dma_Tx_Addr(oDmaAddress'high downto 16) + 1;
end if;
if DSM = sAdrL
or (F_Val = '1' and H_Byte = '0') then Tx_Dma_Req <= '1';
elsif Tx_Dma_Ack = '1' then Tx_Dma_Req <= '0';
end if;
if Sm_Tx = sBop then H_Byte <= '0';
elsif F_Val = '1' then H_Byte <= not H_Byte;
end if;
if F_Val = '1' then Tx_Buf <= Tx_LatchL;
end if;
if H_Byte = '0' and F_Val = '1' and Tx_Dma_Req = '1' then Tx_Dma_Out <= '1';
elsif Sm_Tx = sBop then Tx_Dma_Out <= '0';
end if;
end if;
end process pTxControl;
Start_Tx <= '1' when Start_TxS = '1' and Block_Col = '0' else
'1' when not gAutoTxDel and not gTimerTrigTx and R_Req = '1' else
'0';
F_TxB <= Tx_LatchH when H_Byte = '0' else
Tx_Buf;
onTxIrq <= '1' when (Tx_Icnt = 0 and Tx_SoftInt = '0') or Tx_Ie = '0' else '0';
Tx_Idle <= '1' when Sm_Tx = sIdle and Dsm = sIdle else '0';
Tx_Reg(15 downto 4) <= Tx_Ie & Tx_SoftInt & Tx_Half & Tx_Wait & (Tx_Icnt(4) or Tx_Icnt(3)) & Tx_Icnt(2 downto 0)
& Tx_On & Tx_BegInt & Tx_Idle & "0" ;
Tx_Reg( 3 downto 0) <= Tx_Desc;
Sel_TxH <= '1' when inWrite = '0' and iSelectCont = '1' and iAddress(3) = '0' and Ram_Be(1) = '1' else '0';
Sel_TxL <= '1' when inWrite = '0' and iSelectCont = '1' and iAddress(3) = '0' and Ram_Be(0) = '1' else '0';
Tx_Desc <= Tx_Desc_One;
Tx_SoftInt <= '0';
pTxRegs: process( iRst, iClk )
begin
if iRst = '1' then
Tx_On <= '0'; Tx_Ie <= '0'; Tx_Half <= '0'; Tx_Wait <= '0'; onTxBegIrq <= '0';
Tx_Desc_One <= (others => '0');
Tx_Icnt <= (others => '0'); TxInt <= '0'; Tx_BegInt <= '0';
Tx_Ipg <= conv_std_logic_vector( 42, 6);
elsif rising_edge( iClk ) then
if Sel_TxL = '1' then
if iAddress(2 downto 1) = "00" then Tx_On <= iWritedata( 7);
elsif iAddress(2 downto 1) = "01" and iWritedata( 7) = '1' then Tx_On <= '1';
elsif iAddress(2 downto 1) = "10" and iWritedata( 7) = '1' then Tx_On <= '0';
end if;
end if;
if Tx_BegSet = '1' and Tx_Ie = '1' then Tx_BegInt <= '1';
elsif Sel_TxL = '1' and iAddress(2 downto 1) = "01" and iWritedata( 6) = '1' then Tx_BegInt <= '1';
elsif Sel_TxL = '1' and iAddress(2 downto 1) = "10" and iWritedata( 6) = '1' then Tx_BegInt <= '0';
end if;
onTxBegIrq <= not Tx_BegInt;
if Sel_TxL = '1' and iAddress(2 downto 1) = "11" then Tx_Desc_One <= iWritedata( 3 downto 0);
elsif Dsm = sStat and Ext_Tx = '0' then
if Last_Desc = '1' then Tx_Desc_One <= x"0";
else Tx_Desc_One <= Tx_Desc + 1;
end if;
end if;
if Sel_TxH = '1' then
if iAddress(2 downto 1) = "00" then Tx_Ie <= iWritedata(15);
elsif iAddress(2 downto 1) = "01" and iWritedata(15) = '1' then Tx_Ie <= '1';
elsif iAddress(2 downto 1) = "10" and iWritedata(15) = '1' then Tx_Ie <= '0';
end if;
end if;
if Sel_TxH = '1' then
if iAddress(2 downto 1) = "00" then Tx_Half <= iWritedata(13);
elsif iAddress(2 downto 1) = "01" and iWritedata(13) = '1' then Tx_Half <= '1';
elsif iAddress(2 downto 1) = "10" and iWritedata(13) = '1' then Tx_Half <= '0';
end if;
end if;
if Sel_TxH = '1' then
if iAddress(2 downto 1) = "00" then Tx_Wait <= iWritedata(12);
elsif iAddress(2 downto 1) = "01" and iWritedata(12) = '1' then Tx_Wait <= '1';
elsif iAddress(2 downto 1) = "10" and iWritedata(12) = '1' then Tx_Wait <= '0';
end if;
end if;
if Sel_TxH = '1' then
if iAddress(2 downto 1) = "11" and iWritedata(14) = '1' then Tx_Ipg <= iWritedata(13 downto 8);
end if;
end if;
if Tx_Ie = '1' and Dsm = sStat and Desc_We = '1' then TxInt <= '1';
else TxInt <= '0';
end if;
if Sel_TxH = '1' and iAddress(2 downto 1) = "10" and iWritedata(8) = '1'
and Tx_Icnt /= 0 then Tx_Icnt <= Tx_Icnt - not TxInt;
elsif TxInt = '1' and Tx_Icnt /= "11111" then Tx_Icnt <= Tx_Icnt + 1;
end if;
end if;
end process pTxRegs;
end block bTxDesc;
end block b_Full_Tx;
b_Full_Rx: block
type tRxState is (
sIdle,
sSof,
sRxd
);
signal Sm_Rx : tRxState;
signal Rx_Dat : std_logic_vector(1 downto 0);
signal Rx_DatL : std_logic_vector(1 downto 0);
signal Tx_Timer : std_logic_vector(7 downto 0);
signal Dibl_Cnt : std_logic_vector(1 downto 0);
signal Crc : std_logic_vector(31 downto 0);
signal nCrc : std_logic_vector(31 downto 0);
signal CrcDin : std_logic_vector(1 downto 0);
signal F_Err : std_logic;
signal P_Err : std_logic;
signal N_Err : std_logic;
signal A_Err : std_logic;
signal F_End : std_logic;
signal F_Val : std_logic;
signal Rx_Beg : std_logic;
signal Rx_Sr : std_logic_vector(7 downto 0);
signal nCrc_Ok : std_logic;
signal Crc_Ok : std_logic;
signal WrDescStat : std_logic;
signal PreCount : std_logic_vector(4 downto 0);
signal PreBeg : std_logic;
signal PreErr : std_logic;
signal Rx_DvL : std_logic;
signal Diag : std_logic;
begin
Rx_Beg <= '1' when Rx_Dv = '1' and Sm_Rx = sSof and Rx_Dat = "11" else '0';
nCrc_Ok <= '1' when nCrc = x"C704DD7B" else '0';
rxsm: process ( iClk, iRst ) is
begin
if iRst = '1' then
Sm_Rx <= sIdle;
elsif rising_edge( iClk ) then
if Sm_Rx = sIdle or Sm_Rx = sRxd or Sm_Rx = sSof or Dibl_Cnt = "11" then
case Sm_Rx is
when sIdle => if Rx_Dv = '1' then Sm_Rx <= sSof; end if;
when sSof => if Rx_Dat = "11" then Sm_Rx <= sRxd;
elsif Rx_Dv = '0' then Sm_Rx <= sIdle; end if;
when sRxd => if Rx_Dv = '0' then Sm_Rx <= sIdle; end if;
when others => NULL;
end case;
end if;
end if;
end process rxsm;
pRxCtl: process ( iClk, iRst ) is
variable vPreload : std_logic_vector(Tx_Timer'range);
variable vLoad : std_logic;
begin
if iRst = '1' then
Rx_DatL <= "00"; Rx_Dat <= "00"; Rx_Dv <= '0'; Dibl_Cnt <= "00"; PreCount <= (others => '0');
F_End <= '0'; F_Err <= '0'; F_Val <= '0'; Crc_Ok <= '0';
A_Err <= '0'; N_Err <= '0'; P_Err <= '0'; PreBeg <= '0'; PreErr <= '0';
elsif rising_edge( iClk ) then
Rx_DatL <= iRxData;
Rx_Dat <= Rx_DatL;
if Rx_Dv = '0' and iRxDv = '1' then Rx_Dv <= '1';
elsif Rx_Dv = '1' and iRxDv = '0' and Dibl_Cnt(0) = '1' then Rx_Dv <= '0';
end if;
if Rx_Beg = '1' then Dibl_Cnt <= "00";
else Dibl_Cnt <= Dibl_Cnt + 1;
end if;
Crc_Ok <= nCrc_Ok;
if (Sm_Rx = sRxd and Rx_Dv = '0') then F_End <= '1';
F_Err <= not Crc_Ok;
else F_End <= '0';
end if;
if Dibl_Cnt = "11" and Sm_Rx = sRxd then F_Val <= '1';
else F_Val <= '0';
end if;
if WrDescStat = '1' then A_Err <= '0';
elsif F_End = '1' and Dibl_Cnt /= 1 then A_Err <= '1';
end if;
if Rx_Dv = '0' or Rx_Dat(0) = '0' then PreCount <= (others => '1');
else PreCount <= PreCount - 1;
end if;
if Rx_Dv = '0' then PreBeg <= '0';
elsif Rx_Dat = "01" then PreBeg <= '1';
end if;
if WrDescStat = '1' then N_Err <= '0';
elsif Sm_Rx = sSof and Rx_Dv = '0' then N_Err <= '1';
end if;
if Rx_DvL = '0' then PreErr <= '0';
elsif PreBeg = '0' and (Rx_Dat = "10" or Rx_Dat = "11") then PreErr <= '1';
elsif PreBeg = '1' and (Rx_Dat = "10" or Rx_Dat = "00") then PreErr <= '1';
end if;
if WrDescStat = '1' then P_Err <= '0';
elsif Rx_Beg = '1' and PreErr = '1' then P_Err <= '1';
elsif Rx_Beg = '1' and PreCount /= 0 then P_Err <= '1';
end if;
Rx_Sr <= Rx_Dat(1) & Rx_Dat(0) & Rx_Sr(7 downto 2);
Rx_DvL <= Rx_Dv;
end if;
end process pRxCtl;
CrcDin <= Rx_Dat;
Calc: process ( iClk, Crc, nCrc, CrcDin, Sm_Rx ) is
variable H : std_logic_vector(1 downto 0);
begin
H(0) := Crc(31) xor CrcDin(0);
H(1) := Crc(30) xor CrcDin(1);
if Sm_Rx = sSof then nCrc <= x"FFFFFFFF";
else
nCrc( 0) <= H(1);
nCrc( 1) <= H(0) xor H(1);
nCrc( 2) <= Crc( 0) xor H(0) xor H(1);
nCrc( 3) <= Crc( 1) xor H(0) ;
nCrc( 4) <= Crc( 2) xor H(1);
nCrc( 5) <= Crc( 3) xor H(0) xor H(1);
nCrc( 6) <= Crc( 4) xor H(0) ;
nCrc( 7) <= Crc( 5) xor H(1);
nCrc( 8) <= Crc( 6) xor H(0) xor H(1);
nCrc( 9) <= Crc( 7) xor H(0) ;
nCrc(10) <= Crc( 8) xor H(1);
nCrc(11) <= Crc( 9) xor H(0) xor H(1);
nCrc(12) <= Crc(10) xor H(0) xor H(1);
nCrc(13) <= Crc(11) xor H(0) ;
nCrc(14) <= Crc(12) ;
nCrc(15) <= Crc(13) ;
nCrc(16) <= Crc(14) xor H(1);
nCrc(17) <= Crc(15) xor H(0) ;
nCrc(18) <= Crc(16) ;
nCrc(19) <= Crc(17) ;
nCrc(20) <= Crc(18) ;
nCrc(21) <= Crc(19) ;
nCrc(22) <= Crc(20) xor H(1);
nCrc(23) <= Crc(21) xor H(0) xor H(1);
nCrc(24) <= Crc(22) xor H(0) ;
nCrc(25) <= Crc(23) ;
nCrc(26) <= Crc(24) xor H(1);
nCrc(27) <= Crc(25) xor H(0) ;
nCrc(28) <= Crc(26) ;
nCrc(29) <= Crc(27) ;
nCrc(30) <= Crc(28) ;
nCrc(31) <= Crc(29) ;
end if;
if rising_edge( iClk ) then
Crc <= nCrc;
end if;
end process Calc;
bRxDesc: block
type tDescState is (
sIdle,
sLen,
sTimL,
sTimH,
sAdrH,
sAdrL,
sData,
sOdd,
sStat,
sLenW
);
signal Dsm : tDescState;
signal Rx_Dsm_Next : tDescState;
signal Rx_Buf : std_logic_vector(7 downto 0);
signal Rx_LatchH : std_logic_vector(7 downto 0);
signal Rx_LatchL : std_logic_vector(7 downto 0);
signal Rx_Ovr : std_logic;
signal DescRam_Out : std_logic_vector(15 downto 0);
signal DescRam_In : std_logic_vector(15 downto 0);
alias RX_LEN : std_logic_vector(11 downto 0) is DescRam_Out(11 downto 0);
alias RX_OWN : std_logic is DescRam_Out(8);
alias RX_LAST : std_logic is DescRam_Out(9);
signal Ram_Be : std_logic_vector(1 downto 0);
signal Ram_Wr : std_logic;
signal Desc_We : std_logic;
signal Desc_Addr : std_logic_vector(7 downto 0);
signal ZeitL : std_logic_vector(15 downto 0);
signal Rx_On : std_logic;
signal Rx_Ie : std_logic;
signal Sel_RxH : std_logic;
signal Sel_RxL : std_logic;
signal Rx_Desc : std_logic_vector(3 downto 0);
signal Match_Desc : std_logic_vector(3 downto 0);
signal Rx_Icnt : std_logic_vector(4 downto 0);
signal Rx_Lost : std_logic;
signal Last_Desc : std_logic;
signal Answer_Tx : std_logic;
signal DescIdx : std_logic_vector( 2 downto 0);
signal Rx_Count : std_logic_vector(11 downto 0);
signal Rx_Limit : std_logic_vector(11 downto 0);
signal Match : std_logic;
signal Filt_Cmp : std_logic;
signal Rx_Idle : std_logic;
signal RxInt : std_logic;
signal Hub_Rx_L : std_logic_vector(1 downto 0);
signal Rx_Dma_Out : std_logic;
signal Rx_Done : std_logic;
begin
process(iRst, iClk)
variable doPulse : std_logic;
begin
if iRst = cActivated then
Rx_Done <= cInactivated;
doPulse := cInactivated;
elsif rising_edge(iClk) then
Rx_Done <= cInactivated;
if Dsm /= sIdle and Rx_Dsm_Next = sIdle then
-- RX is done
doPulse := cActivated;
end if;
if doPulse = cActivated and Rx_Dma_Req = cInactivated and Rx_Count = 0 then
-- RX is done and there is no dma request
Rx_Done <= cActivated;
doPulse := cInactivated;
end if;
end if;
end process;
oDmaWriteDone <= Rx_Done;
WrDescStat <= '1' when Dsm = sStat else '0';
Ram_Wr <= '1' when inWrite = '0' and iSelectRam = '1' and iAddress(10) = '1' else '0';
Ram_Be(1) <= '1' when inWrite = '1' or inByteenable(1) = '0' else '0';
Ram_Be(0) <= '1' when inWrite = '1' or inByteenable(0) = '0' else '0';
DescIdx <= "001" when Desc_We = '0' and (Rx_Dsm_Next = sLen or Rx_Dsm_Next = sLenW) else
"001" when Desc_We = '1' and (Dsm = sLen or Dsm = sLenW) else
"010" when Desc_We = '0' and Rx_Dsm_Next = sAdrH else
"010" when Desc_We = '1' and Dsm = sAdrH else
"011" when Desc_We = '0' and Rx_Dsm_Next = sAdrL else
"011" when Desc_We = '1' and Dsm = sAdrL else
"110" when Desc_We = '0' and Rx_Dsm_Next = sTimH else
"110" when Desc_We = '1' and Dsm = sTimH else
"111" when Desc_We = '0' and Rx_Dsm_Next = sTimL else
"111" when Desc_We = '1' and Dsm = sTimL else
"000";
Desc_We <= '1' when Dsm = sTimL or Dsm = sTimH else
'1' when (Dsm = sLenW or Dsm = sStat) and Match = '1' else '0';
Desc_Addr <= "0" & Rx_Desc & DescIdx;
gRxTime: if gTimerEnable generate
DescRam_In <= Zeit(15 downto 0) when Dsm = sTimH else
ZeitL when Dsm = sTimL else
x"0" & Rx_Count when Dsm = sLenW else
Rx_Dma_Out & '0' & "0" & A_Err & Hub_Rx_L & "00" & Match_Desc & N_Err & P_Err & Rx_Ovr & F_Err;
end generate;
ngRxTime: if not gTimerEnable generate
DescRam_In <= x"0" & Rx_Count when Dsm = sLenW else
Rx_Dma_Out & '0' & "0" & A_Err & Hub_Rx_L & "00" & Match_Desc & N_Err & P_Err & Rx_Ovr & F_Err;
end generate;
--! This DPRAM holds the Rx descriptor accessible by the host and the DMA.
RXRAM : entity work.dpRamOpenmac
generic map (
gWordWidth => iWritedata'length,
gNumberOfWords => 256,
gInitFile => "UNUSED"
)
port map (
iClk_A => iClk,
iEnable_A => cActivated,
iWriteEnable_A => Ram_Wr,
iAddress_A => iAddress(8 downto 1),
iByteenable_A => Ram_Be,
iWritedata_A => iWritedata,
oReaddata_A => Rx_Ram_Dat,
iClk_B => iClk,
iEnable_B => cActivated,
iWriteEnable_B => Desc_We,
iByteenable_B => (others => cActivated),
iAddress_B => Desc_Addr,
iWritedata_B => DescRam_In,
oReaddata_B => DescRam_Out
);
pRxSm: process( Dsm,
Rx_Beg, Rx_On, RX_OWN, F_End, F_Err, Diag, Rx_Count )
begin
Rx_Dsm_Next <= Dsm;
case Dsm is
when sIdle => if Rx_Beg = '1' and Rx_On = '1' and RX_OWN = '1' then
Rx_Dsm_Next <= sLen;
end if;
when sLen => Rx_Dsm_Next <= sAdrH;
when sAdrH => Rx_Dsm_Next <= sAdrL;
when sAdrL => Rx_Dsm_Next <= sTimH;
when sTimH => Rx_Dsm_Next <= sTimL;
when sTimL => Rx_Dsm_Next <= sData;
when sData => if F_End = '1' then
if F_Err = '0'
or Diag = '1' then Rx_Dsm_Next <= sStat;
else Rx_Dsm_Next <= sIdle;
end if;
end if;
when sStat => Rx_Dsm_Next <= sLenW;
when sLenW => if Rx_Count(0) = '0' then
Rx_Dsm_Next <= sIdle;
else Rx_Dsm_Next <= sOdd;
end if;
when sOdd => Rx_Dsm_Next <= sIdle;
when others =>
end case;
end process pRxSm;
pRxSmClk : process(iRst, iClk)
begin
if iRst = cActivated then
Dsm <= sIdle;
elsif rising_edge(iClk) then
Dsm <= Rx_Dsm_Next;
end if;
end process pRxSmClk;
pRxControl: process( iRst, iClk )
begin
if iRst = '1' then
Rx_Ovr <= '0'; Rx_Dma_Req <= '0'; Last_Desc <= '0'; Rx_Dma_Out <= '0';
Rx_Count <= (others => '0');
Rx_Buf <= (others => '0'); Rx_LatchL <= (others => '0'); Rx_LatchH <= (others => '0');
Dma_Rx_Addr <= (others => '0');
elsif rising_edge( iClk ) then
if gTimerEnable then
if Dsm = sTimH then ZeitL <= Zeit(31 downto 16);
end if;
end if;
if Dsm = sIdle then Rx_Count <= (others => '0');
Last_Desc <= RX_LAST;
elsif F_Val = '1' then Rx_Count <= Rx_Count + 1;
end if;
if Dsm = sLen then Rx_Limit <= RX_LEN;
Hub_Rx_L <= iHubRxPort;
end if;
if F_Val = '1' then Rx_Buf <= Rx_Sr;
end if;
if (F_Val = '1' and Rx_Count(0) = '1') or Dsm = sStat then Rx_LatchH <= Rx_Buf;
Rx_LatchL <= Rx_Sr;
if Rx_Dma_Req = '1' and Sm_Rx /= sIdle then Rx_Dma_Out <= '1';
end if;
elsif Dsm = sLen then Rx_Dma_Out <= '0';
end if;
if Dsm = sLen then Rx_Ovr <= '0';
elsif F_Val = '1' and Rx_Limit = Rx_Count then Rx_Ovr <= '1';
end if;
if Dsm = sAdrL then --Dma_Rx_Addr(15 downto 1) <= DescRam_Out(15 downto 1);
Dma_Rx_Addr(oDmaAddress'high downto 16) <= DescRam_Out(oDmaAddress'high-16 downto 0);
elsif Rx_Dma_Ack = '1' then Dma_Rx_Addr(15 downto 1) <= Dma_Rx_Addr(15 downto 1) + 1;
end if;
if Dsm = sAdrH then Dma_Rx_Addr(15 downto 1) <= DescRam_Out(15 downto 1);
--Dma_Rx_Addr(oDmaAddress'high downto 16) <= DescRam_Out(oDmaAddress'high-16 downto 0);
elsif Rx_Dma_Ack = '1' and Dma_Rx_Addr(15 downto 1) = x"FFF" & "111" then
Dma_Rx_Addr(oDmaAddress'high downto 16) <= Dma_Rx_Addr(oDmaAddress'high downto 16) + 1;
end if;
if Filt_Cmp = '0' and Match ='0' then Rx_Dma_Req <= '0';
elsif (Dsm = sOdd and Rx_Ovr = '0')
or (Dsm = sData and Rx_Ovr = '0' and F_Val = '1' and Rx_Count(0) = '1') then Rx_Dma_Req <= '1';
elsif Rx_Dma_Ack = '1' then Rx_Dma_Req <= '0';
end if;
end if;
end process pRxControl;
oDmaWritedata <= Rx_LatchL & Rx_LatchH; --Rx_LatchH & Rx_LatchL;
onRxIrq <= '1' when Rx_Icnt = 0 or Rx_Ie = '0' else '0';
Rx_Idle <= '1' when Sm_Rx = sIdle else '0';
Rx_Reg(15 downto 4) <= Rx_Ie & '0' & "0" & '0' & (Rx_Icnt(4) or Rx_Icnt(3)) & Rx_Icnt(2 downto 0)
& Rx_On & "0" & Rx_Idle & Rx_Lost;
Rx_Reg( 3 downto 0) <= Rx_Desc;
bFilter: block
signal Ram_Addr : std_logic_vector(7 downto 0);
signal Ram_BeH : std_logic_vector(1 downto 0);
signal Ram_BeL : std_logic_vector(1 downto 0);
signal Ram_Wr : std_logic;
signal Filter_Addr : std_logic_vector(6 downto 0);
signal Filter_Out_H : std_logic_vector(31 downto 0);
signal Filter_Out_L : std_logic_vector(31 downto 0);
alias DIRON_0 : std_logic is Filter_Out_H(11);
alias DIRON_1 : std_logic is Filter_Out_H(27);
alias DIRON_2 : std_logic is Filter_Out_L(11);
alias DIRON_3 : std_logic is Filter_Out_L(27);
alias TX_0 : std_logic is Filter_Out_H(7);
alias TX_1 : std_logic is Filter_Out_H(23);
alias TX_2 : std_logic is Filter_Out_L(7);
alias TX_3 : std_logic is Filter_Out_L(23);
alias ON_0 : std_logic is Filter_Out_H(6);
alias ON_1 : std_logic is Filter_Out_H(22);
alias ON_2 : std_logic is Filter_Out_L(6);
alias ON_3 : std_logic is Filter_Out_L(22);
alias DESC_0 : std_logic_vector(3 downto 0) is Filter_Out_H(3 downto 0);
alias DESC_1 : std_logic_vector(3 downto 0) is Filter_Out_H(19 downto 16);
alias DESC_2 : std_logic_vector(3 downto 0) is Filter_Out_L(3 downto 0);
alias DESC_3 : std_logic_vector(3 downto 0) is Filter_Out_L(19 downto 16);
signal Byte_Cnt : std_logic_vector(4 downto 0) := (others => '0');
signal Erg0 : std_logic_vector(7 downto 0);
signal Erg1 : std_logic_vector(7 downto 0);
signal Erg2 : std_logic_vector(7 downto 0);
signal Erg3 : std_logic_vector(7 downto 0);
signal Mat_Reg : std_logic_vector(15 downto 0);
signal Filt_Idx : std_logic_vector(1 downto 0);
signal Mat_Sel : std_logic_vector(3 downto 0);
signal M_Prio : std_logic_vector(2 downto 0);
alias Found : std_logic is M_Prio(2);
begin
Ram_Addr <= iAddress(9 downto 8) & iAddress(5 downto 1) & iAddress(6);
Ram_Wr <= '1' when inWrite = '0' and iSelectRam = '1' and iAddress(10) = '0' else '0';
Ram_BeH(1) <= '1' when inWrite = '1' or (inByteenable(1) = '0' and iAddress(7) = '0') else '0';
Ram_BeH(0) <= '1' when inWrite = '1' or (inByteenable(0) = '0' and iAddress(7) = '0') else '0';
Ram_BeL(1) <= '1' when inWrite = '1' or (inByteenable(1) = '0' and iAddress(7) = '1') else '0';
Ram_BeL(0) <= '1' when inWrite = '1' or (inByteenable(0) = '0' and iAddress(7) = '1') else '0';
Filter_Addr <= Dibl_Cnt & Byte_Cnt;
--! This simplex DPRAM holds the higher dword for the Rx packet filters.
FILTERRAMHIGH : entity work.dpRamSplx
generic map (
gWordWidthA => iWritedata'length,
gByteenableWidthA => Ram_BeH'length,
gNumberOfWordsA => 256,
gWordWidthB => Filter_Out_H'length,
gNumberOfWordsB => 128,
gInitFile => "UNUSED"
)
port map (
iClk_A => iClk,
iEnable_A => cActivated,
iWriteEnable_A => Ram_Wr,
iAddress_A => Ram_Addr,
iByteenable_A => Ram_BeH,
iWritedata_A => iWritedata,
iClk_B => iClk,
iEnable_B => cActivated,
iAddress_B => Filter_Addr,
oReaddata_B => Filter_Out_H
);
--! This simplex DPRAM holds the lower dword for the Rx packet filters.
FILTERRAMLOW : entity work.dpRamSplx
generic map (
gWordWidthA => iWritedata'length,
gByteenableWidthA => Ram_BeL'length,
gNumberOfWordsA => 256,
gWordWidthB => Filter_Out_H'length,
gNumberOfWordsB => 128,
gInitFile => "UNUSED"
)
port map (
iClk_A => iClk,
iEnable_A => cActivated,
iWriteEnable_A => Ram_Wr,
iAddress_A => Ram_Addr,
iByteenable_A => Ram_BeL,
iWritedata_A => iWritedata,
iClk_B => iClk,
iEnable_B => cActivated,
iAddress_B => Filter_Addr,
oReaddata_B => Filter_Out_L
);
Erg0 <= (Rx_Buf xor Filter_Out_H( 7 downto 0)) and Filter_Out_H(15 downto 8);
Erg1 <= (Rx_Buf xor Filter_Out_H(23 downto 16)) and Filter_Out_H(31 downto 24);
Erg2 <= (Rx_Buf xor Filter_Out_L( 7 downto 0)) and Filter_Out_L(15 downto 8);
Erg3 <= (Rx_Buf xor Filter_Out_L(23 downto 16)) and Filter_Out_L(31 downto 24);
genMatSel: for i in 0 to 3 generate
Mat_Sel(i) <= Mat_Reg( 0 + i) when Filt_Idx = "00" else
Mat_Reg( 4 + i) when Filt_Idx = "01" else
Mat_Reg( 8 + i) when Filt_Idx = "10" else
Mat_Reg(12 + i); -- when Filt_Idx = "11";
end generate;
M_Prio <= "000" when Filt_Cmp = '0' or Match = '1' else
"100" when Mat_Sel(0) = '1' and On_0 = '1' and (DIRON_0 = '0') else
"101" when Mat_Sel(1) = '1' and On_1 = '1' and (DIRON_1 = '0') else
"110" when Mat_Sel(2) = '1' and On_2 = '1' and (DIRON_2 = '0') else
"111" when Mat_Sel(3) = '1' and On_3 = '1' and (DIRON_3 = '0') else
"000";
pFilter: process( iRst, iClk )
begin
if iRst = '1' then
Filt_Idx <= "00"; Match <= '0';
Filt_Cmp <= '0'; Mat_Reg <= (others => '0'); Byte_Cnt <= (others =>'0');
Match_Desc <= (others => '0');Auto_Desc <= (others =>'0'); Answer_Tx <= '0';
elsif rising_edge( iClk ) then
Filt_Idx <= Dibl_Cnt;
if Dibl_Cnt = "11" and Rx_Count(5) = '0' then Byte_Cnt <= Rx_Count(Byte_Cnt'range);
end if;
if Dsm = sTiml then Filt_Cmp <= '1';
elsif Rx_Dv = '0' or (F_Val = '1' and Rx_Count(5) = '1') then Filt_Cmp <= '0';
end if;
if Dsm = sTimL then Mat_Reg <= (others => '1');
else
for i in 0 to 3 loop
if Erg0 /= 0 and conv_integer(Filt_Idx) = i then Mat_Reg(4*i + 0) <= '0'; end if;
if Erg1 /= 0 and conv_integer(Filt_Idx) = i then Mat_Reg(4*i + 1) <= '0'; end if;
if Erg2 /= 0 and conv_integer(Filt_Idx) = i then Mat_Reg(4*i + 2) <= '0'; end if;
if Erg3 /= 0 and conv_integer(Filt_Idx) = i then Mat_Reg(4*i + 3) <= '0'; end if;
end loop;
end if;
if Dsm = sTimL then Match <= '0';
elsif Found = '1' then Match <= '1'; Match_Desc <= Filt_Idx & M_Prio(1 downto 0);
if M_Prio(1 downto 0) = "00" then Answer_Tx <= TX_0; Auto_Desc <= DESC_0;
elsif M_Prio(1 downto 0) = "01" then Answer_Tx <= TX_1; Auto_Desc <= DESC_1;
elsif M_Prio(1 downto 0) = "10" then Answer_Tx <= TX_2; Auto_Desc <= DESC_2;
elsif M_Prio(1 downto 0) = "11" then Answer_Tx <= TX_3; Auto_Desc <= DESC_3;
end if;
elsif F_End = '1' then Answer_Tx <= '0';
end if;
end if;
end process pFilter;
R_Req <= Answer_Tx when F_End = '1' and F_Err = '0' else '0';
end block bFilter;
Sel_RxH <= '1' when inWrite = '0' and iSelectCont = '1' and iAddress(3) = '1' and inByteenable(1) = '0' else '0';
Sel_RxL <= '1' when inWrite = '0' and iSelectCont = '1' and iAddress(3) = '1' and inByteenable(0) = '0' else '0';
pRxRegs: process( iRst, iClk )
begin
if iRst = '1' then
Rx_Desc <= (others => '0'); Rx_On <= '0';
Rx_Ie <= '0'; Rx_Lost <= '0'; Rx_Icnt <= (others => '0'); RxInt <= '0'; Diag <= '0';
elsif rising_edge( iClk ) then
if Sel_RxH = '1' then
if iAddress(2 downto 1) = "00" then Rx_Ie <= iWritedata(15);
elsif iAddress(2 downto 1) = "01" and iWritedata(15) = '1' then Rx_Ie <= '1';
elsif iAddress(2 downto 1) = "10" and iWritedata(15) = '1' then Rx_Ie <= '0';
end if;
end if;
if Sel_RxH = '1' then
if iAddress(2 downto 1) = "00" then Diag <= iWritedata(12);
elsif iAddress(2 downto 1) = "01" and iWritedata(12) = '1' then Diag <= '1';
elsif iAddress(2 downto 1) = "10" and iWritedata(12) = '1' then Diag <= '0';
end if;
end if;
if Sel_RxL = '1' then
if iAddress(2 downto 1) = "00" then Rx_On <= iWritedata( 7);
elsif iAddress(2 downto 1) = "01" and iWritedata( 7) = '1' then Rx_On <= '1';
elsif iAddress(2 downto 1) = "10" and iWritedata( 7) = '1' then Rx_On <= '0';
end if;
end if;
if Rx_Beg = '1' and (RX_OWN = '0' or Rx_On = '0') then Rx_Lost <= '1';
elsif Sel_RxL = '1' and iAddress(2 downto 1) = "10" and iWritedata( 4) = '1' then Rx_Lost <= '0';
end if;
if Sel_RxL = '1' and iAddress(2 downto 1) = "11" then Rx_Desc <= iWritedata( 3 downto 0);
elsif Dsm = sLenW and Desc_We = '1' then
if Last_Desc = '1' then Rx_Desc <= x"0";
else Rx_Desc <= Rx_Desc + 1;
end if;
end if;
if Rx_Ie = '1' and Desc_We = '1' and Dsm = sStat then RxInt <= '1';
else RxInt <= '0';
end if;
if Sel_RxH = '1' and iAddress(2 downto 1) = "10" and iWritedata(8) = '1'
and Rx_Icnt /= 0 then Rx_Icnt <= Rx_Icnt - not RxInt;
elsif RxInt = '1' and Rx_Icnt /= "11111" then Rx_Icnt <= Rx_Icnt + 1;
end if;
end if;
end process pRxRegs;
end block bRxDesc;
end block b_Full_Rx;
end architecture struct; | gpl-2.0 | 78161b1fa3f76a14228d61e1c17661e3 | 0.437654 | 3.657156 | false | false | false | false |
cnplab/blockmon | fw-combo/src/IPFIX/comp/gen_demux.vhd | 1 | 3,697 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- demux.vhd: Generic demultiplexer
-- Copyright (C) 2006 CESNET
-- Author(s): Martin Kosek <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: demux.vhd 14 2007-07-31 06:44:05Z kosek $
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- library containing log2 function
use work.math_pack.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity GEN_DEMUX is
generic(
DATA_WIDTH : integer;
DEMUX_WIDTH : integer; -- demultiplexer width (number of outputs)
DEF_VALUE : std_logic := '0' -- default value for unselected outputs
);
port(
DATA_IN : in std_logic_vector(DATA_WIDTH-1 downto 0);
SEL : in std_logic_vector(log2(DEMUX_WIDTH)-1 downto 0);
DATA_OUT : out std_logic_vector(DATA_WIDTH*DEMUX_WIDTH-1 downto 0)
);
end entity GEN_DEMUX;
-- ----------------------------------------------------------------------------
-- Architecture declaration
-- ----------------------------------------------------------------------------
architecture full of GEN_DEMUX is
begin
gen_demuxp: process(SEL, DATA_IN)
begin
DATA_OUT <= (others => DEF_VALUE);
for i in 0 to DEMUX_WIDTH-1 loop
if(conv_std_logic_vector(i, log2(DEMUX_WIDTH)) = SEL) then
DATA_OUT((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH) <= DATA_IN;
end if;
end loop;
end process;
end architecture full;
| bsd-3-clause | 88802b052218f0eb906369f484fa3c6b | 0.594536 | 4.481212 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/altera/memory/src/dpRam-rtl-a.vhd | 3 | 3,645 | --! @file dpRam-bhv-a.vhd
--
--! @brief Dual Port Ram Register Transfer Level Architecture
--
--! @details This is the DPRAM intended for synthesis on Altera platforms only.
--! Timing as follows [clk-cycles]: write=0 / read=1
--
-------------------------------------------------------------------------------
-- Architecture : rtl
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! use altera_mf library
library altera_mf;
use altera_mf.altera_mf_components.all;
architecture rtl of dpRam is
begin
altsyncram_component : altsyncram
generic map (
operation_mode => "BIDIR_DUAL_PORT",
intended_device_family => "Cyclone IV",
init_file => gInitFile,
numwords_a => gNumberOfWords,
numwords_b => gNumberOfWords,
widthad_a => logDualis(gNumberOfWords),
widthad_b => logDualis(gNumberOfWords),
width_a => gWordWidth,
width_b => gWordWidth,
width_byteena_a => gWordWidth/8,
width_byteena_b => gWordWidth/8
)
port map (
clock0 => iClk_A,
clocken0 => iEnable_A,
wren_a => iWriteEnable_A,
address_a => iAddress_A,
byteena_a => iByteenable_A,
data_a => iWritedata_A,
q_a => oReaddata_A,
clock1 => iClk_B,
clocken1 => iEnable_B,
wren_b => iWriteEnable_B,
address_b => iAddress_B,
byteena_b => iByteenable_B,
data_b => iWritedata_B,
q_b => oReaddata_B
);
end architecture rtl;
| gpl-2.0 | 24ea7550d0725fc8fa30ccc38bbed95f | 0.569547 | 4.758486 | false | false | false | false |
cnplab/blockmon | fw-combo/src/netcope-sim/models/mi_bfm.vhd | 1 | 6,184 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
--
-- mi_bfm.vhd : MI32 simulation component
-- Copyright (C) 2008 CESNET
-- Author(s): Jakub Sochor <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: mi_bfm.vhd 12021 2011-04-15 08:23:45Z kastovsky $
--
-- TODO:
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
use work.mi_bfm_pkg.all;
use work.math_pack.all;
-- ----------------------------------------------------------------------------
-- ENTITY DECLARATION --
-- ----------------------------------------------------------------------------
entity MI_BFM is
port(
-- Common interface -----------------------------------------------------
CLK : in std_logic;
RESET : in std_logic;
-- Output MI interfaces -------------------------------------------------
MI32_DWR : out std_logic_vector(31 downto 0);
MI32_ADDR : out std_logic_vector(31 downto 0);
MI32_BE : out std_logic_vector(3 downto 0);
MI32_DRD : in std_logic_vector(31 downto 0);
MI32_RD : out std_logic;
MI32_WR : out std_logic;
MI32_ARDY : in std_logic;
MI32_DRDY : in std_logic
);
end entity MI_BFM;
architecture MI_BFM_ARCH of MI_BFM is
signal commandStatus : TCommandStatus := ('0', '0', 'Z');
procedure SendTransaction(variable trans : inout TTransaction;
signal CLK : in std_logic;
signal MI32_DWR : out std_logic_vector(31 downto 0);
signal MI32_ADDR : out std_logic_vector(31 downto 0);
signal MI32_BE : out std_logic_vector(3 downto 0);
signal MI32_WR : out std_logic;
signal MI32_RD : out std_logic;
signal MI32_DRD : in std_logic_vector(31 downto 0);
signal MI32_DRDY : in std_logic;
signal MI32_ARDY : in std_logic) is
begin
if (trans.DIRECTION = READ) then
wait until (CLK'event and CLK = '1');
MI32_ADDR <= trans.ADDR;
MI32_BE <= trans.BE;
MI32_RD <= '1';
wait until (CLK'event and CLK = '1' and MI32_ARDY = '1');
MI32_RD <= '0';
MI32_ADDR <= (others => '0');
MI32_BE <= (others => '0');
wait until (CLK'event and CLK = '1' and MI32_DRDY = '1');
trans.DATA := MI32_DRD;
wait until (CLK'event and CLK = '1');
else
MI32_ADDR <= trans.ADDR;
MI32_BE <= trans.BE;
MI32_DWR <= trans.DATA;
MI32_WR <= '1';
while (MI32_ARDY = '0') loop
wait until MI32_ARDY = '1';
end loop;
wait until (CLK'event and CLK = '0');
wait until (CLK'event and CLK = '1');
MI32_WR <= '0';
MI32_ADDR <= (others => '0');
MI32_DWR <= (others => '0');
MI32_BE <= (others => '0');
end if;
end procedure;
begin
status.REQ_ACK <= commandStatus.REQ_ACK;
status.BUSY <= commandStatus.BUSY;
commandStatus.REQ <= status.REQ;
sim: process
variable transaction : TTransaction;
begin
MI32_DWR <= (others => '0');
MI32_ADDR <= (others => '0');
MI32_BE <= (others => '0');
MI32_RD <= '0';
MI32_WR <= '0';
loop
commandStatus.BUSY <= '0';
wait until commandStatus.REQ = '1';
commandStatus.BUSY <= '1';
commandStatus.REQ_ACK <= '1';
ReadTransaction(transaction);
SendTransaction(transaction, CLK, MI32_DWR, MI32_ADDR, MI32_BE, MI32_WR, MI32_RD, MI32_DRD, MI32_DRDY, MI32_ARDY);
WriteTransaction(transaction);
commandStatus.REQ_ACK <= '0';
commandStatus.BUSY <= '0';
end loop;
end process;
end architecture;
| bsd-3-clause | a720f7a74504e74052d36cdd46dae9ee | 0.535576 | 4.209666 | false | false | false | false |
cnplab/blockmon | fw-combo/src/netcope-sim/models/ib_bfm_pkg.vhd | 1 | 36,491 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- storage_init_pkg.vhd: Storage Init PKG
-- Copyright (C) 2006 CESNET
-- Author(s): Petr Kobiersky <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: ib_bfm_pkg.vhd 12021 2011-04-15 08:23:45Z kastovsky $
--
-- TODO:
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use IEEE.numeric_std.all;
use std.textio.all;
-- ----------------------------------------------------------------------------
-- Internal Bus BFM Package
-- ----------------------------------------------------------------------------
PACKAGE ib_bfm_pkg IS
CONSTANT MAX_TRANS_LENGTH : integer := 4095;
CONSTANT MAX_WRITE_LENGTH : integer := 4096;
CONSTANT MAX_INIT_DATA : integer := 4096;
-----------------------------------------------------------------------------
-- DATA TYPES
-----------------------------------------------------------------------------
-- Internal Bus Operation Type
TYPE IbOpType IS (LocalRead, LocalWrite, Completition, G2LR, L2GW, FileLogging, TranscriptLogging,
InitMemory, InitMemoryFromAddr, ShowMemory);
-- File Name Type
TYPE FileNameType IS RECORD
Len : integer;
Arr : string(1 to 256);
END RECORD;
TYPE DataType IS ARRAY (0 TO MAX_INIT_DATA/8) of std_logic_vector(63 downto 0);
-- Operation parameters
TYPE DiCmdType IS RECORD
SrcAddr : std_logic_vector(31 downto 0); -- Source Address
DstAddr : std_logic_vector(31 downto 0); -- Destination Address
LocalAddr : std_logic_vector(31 downto 0); -- Local Address (for GlobalTransactions)
GlobalAddr : std_logic_vector(63 downto 0); -- Global Address (for GlobalTransactions)
Length : integer; -- Length
Tag : integer; -- Tag
Data : DataType; -- Data
LastFlag : std_logic; -- Completition Last Flag
Enable : boolean;
FileName : FileNameType;
MemAddr : integer;
END RECORD;
-- Command record
TYPE IbCmdVType IS
RECORD
CmdOp : IbOpType; -- Operation
Di : DiCmdType; -- Operation input parameters
END RECORD;
-- Command REQ/ACK record
TYPE IbCmdType IS
RECORD
Req : std_logic;
ReqAck : std_logic;
Ack : std_logic;
END RECORD;
----------------------------------------------------------------------------
-- SIGNAL FOR SETTINGS BFM REQUESTS
----------------------------------------------------------------------------
SIGNAL IbCmd : IbCmdType := ('0', 'Z', 'Z');
----------------------------------------------------------------------------
-- BFM FUNCTIONS
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Functions is called by IB BFM model to obtain command parameters
PROCEDURE ReadIbCmdV (VARIABLE LclIbCmdV : OUT IbCmdVType);
----------------------------------------------------------------------------
-- Functions is called by IB BFM model to return results
PROCEDURE WriteIbCmdV (VARIABLE LclIbCmdV : IN IbCmdVType);
-----------------------------------------------------------------------------
-- Converts string type into the FileNameType
FUNCTION ConvFileName(FileName : string) RETURN FileNameType;
-----------------------------------------------------------------------------
-- Converts FileNameType into the string
FUNCTION ConvFileName(FileName : FileNameType) return string;
----------------------------------------------------------------------------
-- USER FUNCTIONS
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Local Read Transaction
PROCEDURE IBLocalRead (
CONSTANT SrcAddr : IN std_logic_vector(31 downto 0); -- Address from where are data readed
CONSTANT DstAddr : IN std_logic_vector(31 downto 0); -- Destination address of completition transaction
CONSTANT Length : IN integer; -- Number of bytes to be readed
CONSTANT Tag : IN integer; -- Transaction Tag
SIGNAL IbCmd : INOUT IbCmdType -- Command record
);
-----------------------------------------------------------------------
-- Local Write Transaction
PROCEDURE IBLocalWrite (
CONSTANT DstAddr : IN std_logic_vector(31 downto 0); -- Destination addres of write transaction
CONSTANT SrcAddr : IN std_logic_vector(31 downto 0); -- From where are write transaction generated
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT Tag : IN integer; -- Transaction Tag
CONSTANT Data : IN std_logic_vector(63 downto 0); -- Data to be writen
SIGNAL IbCmd : INOUT IbCmdType -- Command record
);
-----------------------------------------------------------------------
-- Local Write Transaction with Data from File
PROCEDURE IBLocalWriteFile (
CONSTANT DstAddr : IN std_logic_vector(31 downto 0); -- Destination addres of write transaction
CONSTANT SrcAddr : IN std_logic_vector(31 downto 0); -- From where are write transaction generated
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT Tag : IN integer; -- Transaction Tag
CONSTANT FileName : IN string; -- Filename from where are data writen (64 bit hexa values)
SIGNAL IbCmd : INOUT IbCmdType -- Command record
);
-----------------------------------------------------------------------
-- Local Write Transaction
PROCEDURE IBLocalWrite32 (
CONSTANT DstAddr : IN std_logic_vector(31 downto 0); -- Destination addres of write transaction
CONSTANT SrcAddr : IN std_logic_vector(31 downto 0); -- From where are write transaction generated
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT Tag : IN integer; -- Transaction Tag
CONSTANT Data : IN std_logic_vector(31 downto 0); -- Data to be writen
SIGNAL IbCmd : INOUT IbCmdType -- Command record
);
-----------------------------------------------------------------------
-- Local Write Transaction with Data from File
PROCEDURE IBLocalWriteFile32 (
CONSTANT DstAddr : IN std_logic_vector(31 downto 0); -- Destination addres of write transaction
CONSTANT SrcAddr : IN std_logic_vector(31 downto 0); -- From where are write transaction generated
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT Tag : IN integer; -- Transaction Tag
CONSTANT FileName : IN string; -- Filename from where are data writen (32 bit hexa values)
SIGNAL IbCmd : INOUT IbCmdType -- Command record
);
-----------------------------------------------------------------------
-- Completition Transaction
PROCEDURE IBCompletition (
CONSTANT DstAddr : IN std_logic_vector(31 downto 0); -- Destination addres of write transaction
CONSTANT SrcAddr : IN std_logic_vector(31 downto 0); -- From where are write transaction generated
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT Tag : IN integer; -- Transaction Tag
CONSTANT Data : IN std_logic_vector(63 downto 0); -- Data to be writen
SIGNAL IbCmd : INOUT IbCmdType -- Command record
);
-----------------------------------------------------------------------
-- Completition Transaction with Data from File
PROCEDURE IBCompletitionFile (
CONSTANT DstAddr : IN std_logic_vector(31 downto 0); -- Destination addres of write transaction
CONSTANT SrcAddr : IN std_logic_vector(31 downto 0); -- From where are write transaction generated
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT Tag : IN integer; -- Transaction Tag
CONSTANT FileName : IN string; -- Filename from where are data writen (64 bit hexa values)
SIGNAL IbCmd : INOUT IbCmdType -- Command record
);
-----------------------------------------------------------------------
-- Not Last Completition Transaction (op_done is not generated)
PROCEDURE IBNotLastCompletition (
CONSTANT DstAddr : IN std_logic_vector(31 downto 0); -- Destination addres of write transaction
CONSTANT SrcAddr : IN std_logic_vector(31 downto 0); -- From where are write transaction generated
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT Tag : IN integer; -- Transaction Tag
CONSTANT Data : IN std_logic_vector(63 downto 0); -- Data to be writen
SIGNAL IbCmd : INOUT IbCmdType -- Command record
);
-----------------------------------------------------------------------
-- Not Last Completition Transaction with Data from File (op_done is not generated)
PROCEDURE IBNotLastCompletitionFile (
CONSTANT DstAddr : IN std_logic_vector(31 downto 0); -- Destination addres of write transaction
CONSTANT SrcAddr : IN std_logic_vector(31 downto 0); -- From where are write transaction generated
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT Tag : IN integer; -- Transaction Tag
CONSTANT FileName : IN string; -- Filename from where are data writen (64 bit hexa values)
SIGNAL IbCmd : INOUT IbCmdType -- Command record
);
-----------------------------------------------------------------------
-- Enable Transcript Logging
PROCEDURE SetTranscriptLogging (
CONSTANT Enable : IN boolean; -- Enable/Disable
SIGNAL IbCmd : INOUT IbCmdType -- Command record
);
-----------------------------------------------------------------------
-- Enable File Logging
PROCEDURE SetFileLogging (
CONSTANT Enable : IN boolean; -- Enable/Disable
SIGNAL IbCmd : INOUT IbCmdType -- Command record
);
-----------------------------------------------------------------------
-- Init HostPC Memory
PROCEDURE InitMemory (
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT FileName : IN string; -- Filename from where are data writen (64 bit hexa values)
SIGNAL IbCmd : INOUT IbCmdType -- Command record
);
-----------------------------------------------------------------------
-- Init HostPC Memory Starting From Given Address
PROCEDURE InitMemoryFromAddr (
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT Address : IN integer; -- Where to write data
CONSTANT FileName : IN string; -- Filename from where are data writen (64 bit hexa values)
SIGNAL IbCmd : INOUT IbCmdType -- Command record
);
-----------------------------------------------------------------------
-- Show content of Memory
PROCEDURE ShowMemory (
SIGNAL IbCmd : INOUT IbCmdType -- Command record
);
END ib_bfm_pkg;
-- ----------------------------------------------------------------------------
-- Internal Bus BFM Package BODY
-- ----------------------------------------------------------------------------
PACKAGE BODY ib_bfm_pkg IS
-----------------------------------------------------------------------------
-- Command shared variable
SHARED VARIABLE IbCmdV : IbCmdVType;
-----------------------------------------------------------------------------
-- Functions is called by IB BFM model to obtain command parameters
PROCEDURE ReadIbCmdV (VARIABLE LclIbCmdV : OUT IbCmdVType) IS
BEGIN
LclIbCmdV := IbCmdV;
END;
-----------------------------------------------------------------------------
-- Functions is called by IB BFM model to return results
PROCEDURE WriteIbCmdV (VARIABLE LclIbCmdV : IN IbCmdVType) IS
BEGIN
IbCmdV := LclIbCmdV;
END;
-----------------------------------------------------------------------------
-- Converts string type into the FileNameType
FUNCTION ConvFileName(FileName : string) RETURN FileNameType IS
VARIABLE result : FileNameType;
BEGIN
result.Len := FileName'length;
result.Arr(1 to result.len) := FileName;
RETURN result;
END;
-----------------------------------------------------------------------------
-- Converts FileNameType into the string
FUNCTION ConvFileName(FileName : FileNameType) return string is
BEGIN
RETURN FileName.arr(1 to FileName.len);
END;
-- ----------------------------------------------------------------
-- Count Number of lines in file
FUNCTION FileLineCount(FileName : IN string) RETURN integer IS
FILE in_file : text;
VARIABLE in_line : line;
VARIABLE readFlag : boolean;
VARIABLE data : std_logic_vector(63 downto 0);
VARIABLE i : integer;
BEGIN
i:=0;
file_open(in_file, FileName, READ_MODE);
while not (endfile(in_file)) loop
readline(in_file, in_line);
i:=i+1;
end loop;
file_close(in_file);
RETURN i;
END;
-----------------------------------------------------------------------------
-- Local Read Transaction
PROCEDURE IBLocalRead (
CONSTANT SrcAddr : IN std_logic_vector(31 downto 0); -- Address from where are data readed
CONSTANT DstAddr : IN std_logic_vector(31 downto 0); -- Destination address of completition transaction
CONSTANT Length : IN integer; -- Number of bytes to be readed
CONSTANT Tag : IN integer; -- Transaction Tag
SIGNAL IbCmd : INOUT IbCmdType -- Command record
) IS
BEGIN
assert (length <= MAX_TRANS_LENGTH) report "Transaction length exceed 4095 bytes IB limit" severity ERROR;
IbCmdV.CmdOp := LocalRead;
IbCmdV.Di.SrcAddr := SrcAddr;
IbCmdV.Di.DstAddr := DstAddr;
IbCmdV.Di.Length := Length;
IbCmdV.Di.Tag := Tag;
-- Req toggles each time we want the BFM to do a new check.
IbCmd.Req <= '1';
WAIT ON IbCmd.ReqAck;
IbCmd.Req <= '0';
WAIT ON IbCmd.Ack;
END;
-----------------------------------------------------------------------------
-- Local Write Transaction
PROCEDURE IBLocalWrite (
CONSTANT DstAddr : IN std_logic_vector(31 downto 0); -- Destination addres of write transaction
CONSTANT SrcAddr : IN std_logic_vector(31 downto 0); -- From where are write transaction generated
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT Tag : IN integer; -- Transaction Tag
CONSTANT Data : IN std_logic_vector(63 downto 0); -- Data to be writen
SIGNAL IbCmd : INOUT IbCmdType -- Command record
) IS
BEGIN
assert (length <= MAX_TRANS_LENGTH) report "Transaction length exceed 4095 bytes IB limit" severity ERROR;
IbCmdV.CmdOp := LocalWrite;
IbCmdV.Di.SrcAddr := SrcAddr;
IbCmdV.Di.DstAddr := DstAddr;
IbCmdV.Di.Length := Length;
IbCmdV.Di.Tag := Tag;
IbCmdV.Di.Data(0) := Data;
-- Req toggles each time we want the BFM to do a new check.
IbCmd.Req <= '1';
WAIT ON IbCmd.ReqAck;
IbCmd.Req <= '0';
WAIT ON IbCmd.Ack;
END;
-----------------------------------------------------------------------------
-- Local Write File Transaction
PROCEDURE IBLocalWriteFile (
CONSTANT DstAddr : IN std_logic_vector(31 downto 0); -- Destination addres of write transaction
CONSTANT SrcAddr : IN std_logic_vector(31 downto 0); -- From where are write transaction generated
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT Tag : IN integer; -- Transaction Tag
CONSTANT FileName : IN string; -- Filename from where are data writen (64 bit hexa values)
SIGNAL IbCmd : INOUT IbCmdType -- Command record
) IS
file in_file : text;
variable in_line : line;
variable readFlag : boolean;
variable len : integer;
variable i : integer;
variable j : integer;
variable split_cnt : integer;
variable split_len : integer;
BEGIN
if (Length = 0) then
len := FileLineCount(FileName)*8;
else
len := Length;
end if;
if (len <= MAX_WRITE_LENGTH) then
IbCmdV.CmdOp := LocalWrite;
IbCmdV.Di.SrcAddr := SrcAddr;
IbCmdV.Di.DstAddr := DstAddr;
IbCmdV.Di.Length := len;
IbCmdV.Di.Tag := Tag;
file_open(in_file, FileName, READ_MODE);
i:=0;
while (i < len) loop
readline(in_file, in_line);
hread(in_line, IbCmdV.Di.Data(i/8), readFlag);
assert readFlag report "IBLocalWriteFile read error" severity ERROR;
i:=i+8;
end loop;
file_close(in_file);
-- Req toggles each time we want the BFM to do a new check.
IbCmd.Req <= '1';
WAIT ON IbCmd.ReqAck;
IbCmd.Req <= '0';
WAIT ON IbCmd.Ack;
else -- Split transactions
file_open(in_file, FileName, READ_MODE);
split_cnt := (len / MAX_WRITE_LENGTH);
if (len > (MAX_WRITE_LENGTH*split_cnt)) then
split_cnt := split_cnt+1;
end if;
i:=0;
WHILE (split_cnt > 0) loop
if (len > MAX_WRITE_LENGTH) then
split_len := MAX_WRITE_LENGTH;
else
split_len := len;
end if;
IbCmdV.CmdOp := LocalWrite;
IbCmdV.Di.SrcAddr := SrcAddr;
IbCmdV.Di.DstAddr := DstAddr+(i*MAX_WRITE_LENGTH);
IbCmdV.Di.Length := split_len;
IbCmdV.Di.Tag := Tag;
j:=0;
while (j < split_len) loop
readline(in_file, in_line);
hread(in_line, IbCmdV.Di.Data(j/8), readFlag);
assert readFlag report "IBLocalWriteFile read error" severity ERROR;
j:=j+8;
end loop;
i:=i+1;
split_cnt:=split_cnt-1;
len:=len-MAX_WRITE_LENGTH;
-- Req toggles each time we want the BFM to do a new check.
IbCmd.Req <= '1';
WAIT ON IbCmd.ReqAck;
IbCmd.Req <= '0';
WAIT ON IbCmd.Ack;
END LOOP;
file_close(in_file);
END IF;
END;
-----------------------------------------------------------------------------
-- Local Write Transaction
PROCEDURE IBLocalWrite32 (
CONSTANT DstAddr : IN std_logic_vector(31 downto 0); -- Destination addres of write transaction
CONSTANT SrcAddr : IN std_logic_vector(31 downto 0); -- From where are write transaction generated
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT Tag : IN integer; -- Transaction Tag
CONSTANT Data : IN std_logic_vector(31 downto 0); -- Data to be writen
SIGNAL IbCmd : INOUT IbCmdType -- Command record
) IS
BEGIN
assert (length <= MAX_TRANS_LENGTH) report "Transaction length exceed 4095 bytes IB limit" severity ERROR;
IbCmdV.CmdOp := LocalWrite;
IbCmdV.Di.SrcAddr := SrcAddr;
IbCmdV.Di.DstAddr := DstAddr;
IbCmdV.Di.Length := Length;
IbCmdV.Di.Tag := Tag;
IbCmdV.Di.Data(0) := X"00000000" & Data;
-- Req toggles each time we want the BFM to do a new check.
IbCmd.Req <= '1';
WAIT ON IbCmd.ReqAck;
IbCmd.Req <= '0';
WAIT ON IbCmd.Ack;
END;
-----------------------------------------------------------------------------
-- Local Write File Transaction
PROCEDURE IBLocalWriteFile32 (
CONSTANT DstAddr : IN std_logic_vector(31 downto 0); -- Destination addres of write transaction
CONSTANT SrcAddr : IN std_logic_vector(31 downto 0); -- From where are write transaction generated
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT Tag : IN integer; -- Transaction Tag
CONSTANT FileName : IN string; -- Filename from where are data writen (32 bit hexa values)
SIGNAL IbCmd : INOUT IbCmdType -- Command record
) IS
file in_file : text;
variable in_line : line;
variable data32a : std_logic_vector(31 downto 0);
variable data32b : std_logic_vector(31 downto 0);
variable readFlag : boolean;
variable len : integer;
variable i : integer;
variable j : integer;
variable split_cnt : integer;
variable split_len : integer;
BEGIN
if (Length = 0) then
len := FileLineCount(FileName)*4;
else
len := Length;
end if;
if (len <= MAX_WRITE_LENGTH) then
IbCmdV.CmdOp := LocalWrite;
IbCmdV.Di.SrcAddr := SrcAddr;
IbCmdV.Di.DstAddr := DstAddr;
IbCmdV.Di.Length := Len;
IbCmdV.Di.Tag := Tag;
file_open(in_file, FileName, READ_MODE);
i:=0;
while (i < len) loop
readline(in_file, in_line);
hread(in_line, data32a, readFlag);
assert readFlag report "IBLocalWriteFile32 read error" severity ERROR;
if ((i + 4) < len) then
readline(in_file, in_line);
hread(in_line, data32b, readFlag);
assert readFlag report "IBLocalWriteFile32 read error" severity ERROR;
else
data32b:=X"00000000";
end if;
IbCmdV.Di.Data(i/8):= data32b&data32a;
i:=i+8;
end loop;
file_close(in_file);
-- Req toggles each time we want the BFM to do a new check.
IbCmd.Req <= '1';
WAIT ON IbCmd.ReqAck;
IbCmd.Req <= '0';
WAIT ON IbCmd.Ack;
else
file_open(in_file, FileName, READ_MODE);
split_cnt := (len / MAX_WRITE_LENGTH);
if (len > (MAX_WRITE_LENGTH*split_cnt)) then
split_cnt := split_cnt+1;
end if;
i:=0;
WHILE (split_cnt > 0) loop
if (len > MAX_WRITE_LENGTH) then
split_len := MAX_WRITE_LENGTH;
else
split_len := len;
end if;
IbCmdV.CmdOp := LocalWrite;
IbCmdV.Di.SrcAddr := SrcAddr;
IbCmdV.Di.DstAddr := DstAddr+(i*MAX_WRITE_LENGTH);
IbCmdV.Di.Length := split_len;
IbCmdV.Di.Tag := Tag;
j := 0;
while (j < split_len) loop
readline(in_file, in_line);
hread(in_line, data32a, readFlag);
assert readFlag report "IBLocalWriteFile32 read error" severity ERROR;
if ((j + 4) < len) then
readline(in_file, in_line);
hread(in_line, data32b, readFlag);
assert readFlag report "IBLocalWriteFile32 read error" severity ERROR;
else
data32b:=X"00000000";
end if;
IbCmdV.Di.Data(j/8):= data32b&data32a;
j:=j+8;
end loop;
i:=i+1;
split_cnt:=split_cnt-1;
len:=len-MAX_WRITE_LENGTH;
-- Req toggles each time we want the BFM to do a new check.
IbCmd.Req <= '1';
WAIT ON IbCmd.ReqAck;
IbCmd.Req <= '0';
WAIT ON IbCmd.Ack;
END LOOP;
file_close(in_file);
end if;
END;
-----------------------------------------------------------------------
-- Completition Transaction
PROCEDURE IBCompletition (
CONSTANT DstAddr : IN std_logic_vector(31 downto 0); -- Destination addres of write transaction
CONSTANT SrcAddr : IN std_logic_vector(31 downto 0); -- From where are write transaction generated
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT Tag : IN integer; -- Transaction Tag
CONSTANT Data : IN std_logic_vector(63 downto 0); -- Data to be writen
SIGNAL IbCmd : INOUT IbCmdType -- Command record
) IS
BEGIN
assert (length <= MAX_TRANS_LENGTH) report "Transaction length exceed 4095 bytes IB limit" severity ERROR;
IbCmdV.CmdOp := Completition;
IbCmdV.Di.SrcAddr := SrcAddr;
IbCmdV.Di.DstAddr := DstAddr;
IbCmdV.Di.Length := Length;
IbCmdV.Di.Tag := Tag;
IbCmdV.Di.Data(0) := Data;
IbCmdV.Di.LastFlag := '1';
-- Req toggles each time we want the BFM to do a new check.
IbCmd.Req <= '1';
WAIT ON IbCmd.ReqAck;
IbCmd.Req <= '0';
WAIT ON IbCmd.Ack;
END;
-----------------------------------------------------------------------
-- Completition Transaction with Data from File
PROCEDURE IBCompletitionFile (
CONSTANT DstAddr : IN std_logic_vector(31 downto 0); -- Destination addres of write transaction
CONSTANT SrcAddr : IN std_logic_vector(31 downto 0); -- From where are write transaction generated
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT Tag : IN integer; -- Transaction Tag
CONSTANT FileName : IN string; -- Filename from where are data writen (64 bit hexa values)
SIGNAL IbCmd : INOUT IbCmdType -- Command record
) IS
file in_file : text;
variable in_line : line;
variable readFlag : boolean;
variable len : integer;
variable i : integer;
BEGIN
if (Length = 0) then
len := FileLineCount(FileName)*8;
else
len := Length;
end if;
assert (len <= MAX_TRANS_LENGTH) report "Transaction length exceed 4095 bytes IB limit" severity ERROR;
IbCmdV.CmdOp := Completition;
IbCmdV.Di.SrcAddr := SrcAddr;
IbCmdV.Di.DstAddr := DstAddr;
IbCmdV.Di.Length := len;
IbCmdV.Di.Tag := Tag;
IbCmdV.Di.LastFlag := '1';
file_open(in_file, FileName, READ_MODE);
i:=0;
while (i < len) loop
readline(in_file, in_line);
hread(in_line, IbCmdV.Di.Data(i/8), readFlag);
assert readFlag report "IBCompletitionFile read error" severity ERROR;
i:=i+8;
end loop;
file_close(in_file);
-- Req toggles each time we want the BFM to do a new check.
IbCmd.Req <= '1';
WAIT ON IbCmd.ReqAck;
IbCmd.Req <= '0';
WAIT ON IbCmd.Ack;
END;
-----------------------------------------------------------------------
-- Not Last Completition Transaction (op_done is not generated)
PROCEDURE IBNotLastCompletition (
CONSTANT DstAddr : IN std_logic_vector(31 downto 0); -- Destination addres of write transaction
CONSTANT SrcAddr : IN std_logic_vector(31 downto 0); -- From where are write transaction generated
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT Tag : IN integer; -- Transaction Tag
CONSTANT Data : IN std_logic_vector(63 downto 0); -- Data to be writen
SIGNAL IbCmd : INOUT IbCmdType -- Command record
) IS
BEGIN
assert (length <= MAX_TRANS_LENGTH) report "Transaction length exceed 4095 bytes IB limit" severity ERROR;
IbCmdV.CmdOp := Completition;
IbCmdV.Di.SrcAddr := SrcAddr;
IbCmdV.Di.DstAddr := DstAddr;
IbCmdV.Di.Length := Length;
IbCmdV.Di.Tag := Tag;
IbCmdV.Di.Data(0) := Data;
IbCmdV.Di.LastFlag := '0';
-- Req toggles each time we want the BFM to do a new check.
IbCmd.Req <= '1';
WAIT ON IbCmd.ReqAck;
IbCmd.Req <= '0';
WAIT ON IbCmd.Ack;
END;
-----------------------------------------------------------------------
-- Not Last Completition Transaction with Data from File (op_done is not generated)
PROCEDURE IBNotLastCompletitionFile (
CONSTANT DstAddr : IN std_logic_vector(31 downto 0); -- Destination addres of write transaction
CONSTANT SrcAddr : IN std_logic_vector(31 downto 0); -- From where are write transaction generated
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT Tag : IN integer; -- Transaction Tag
CONSTANT FileName : IN string; -- Filename from where are data writen (64 bit hexa values)
SIGNAL IbCmd : INOUT IbCmdType -- Command record
) IS
file in_file : text;
variable in_line : line;
variable readFlag : boolean;
variable len : integer;
variable i : integer;
BEGIN
if (Length = 0) then
len := FileLineCount(FileName)*8;
else
len := Length;
end if;
assert (len <= MAX_TRANS_LENGTH) report "Transaction length exceed 4095 bytes IB limit" severity ERROR;
IbCmdV.CmdOp := Completition;
IbCmdV.Di.SrcAddr := SrcAddr;
IbCmdV.Di.DstAddr := DstAddr;
IbCmdV.Di.Length := len;
IbCmdV.Di.Tag := Tag;
IbCmdV.Di.LastFlag := '0';
file_open(in_file, FileName, READ_MODE);
i:=0;
while (i < len) loop
readline(in_file, in_line);
hread(in_line, IbCmdV.Di.Data(i/8), readFlag);
assert readFlag report "IBNotLastCompletitionFile read error" severity ERROR;
i:=i+8;
end loop;
file_close(in_file);
-- Req toggles each time we want the BFM to do a new check.
IbCmd.Req <= '1';
WAIT ON IbCmd.ReqAck;
IbCmd.Req <= '0';
WAIT ON IbCmd.Ack;
END;
-----------------------------------------------------------------------
-- Enable Transcript Logging
PROCEDURE SetTranscriptLogging (
CONSTANT Enable : IN boolean; -- Enable/Disable
SIGNAL IbCmd : INOUT IbCmdType -- Command record
) IS
BEGIN
IbCmdV.CmdOp := TranscriptLogging;
IbCmdV.Di.Enable := Enable;
-- Req toggles each time we want the BFM to do a new check.
IbCmd.Req <= '1';
WAIT ON IbCmd.ReqAck;
IbCmd.Req <= '0';
WAIT ON IbCmd.Ack;
END;
-----------------------------------------------------------------------
-- Enable File Logging
PROCEDURE SetFileLogging (
CONSTANT Enable : IN boolean; -- Enable/Disable
SIGNAL IbCmd : INOUT IbCmdType -- Command record
) IS
BEGIN
IbCmdV.CmdOp := FileLogging;
IbCmdV.Di.Enable := Enable;
-- Req toggles each time we want the BFM to do a new check.
IbCmd.Req <= '1';
WAIT ON IbCmd.ReqAck;
IbCmd.Req <= '0';
WAIT ON IbCmd.Ack;
END;
-----------------------------------------------------------------------
-- Init HostPC Memory
PROCEDURE InitMemory (
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT FileName : IN string; -- Filename from where are data writen (64 bit hexa values)
SIGNAL IbCmd : INOUT IbCmdType -- Command record
) IS
file in_file : text;
variable in_line : line;
variable readFlag : boolean;
variable len : integer;
variable i : integer;
BEGIN
if (Length = 0) then
len := FileLineCount(FileName)*8;
else
len := Length;
end if;
assert (len <= MAX_INIT_DATA) report "Transaction length exceed 4096 bytes memory init limit" severity ERROR;
IbCmdV.CmdOp := InitMemory;
IbCmdV.Di.Length := Length;
IbCmdV.Di.MemAddr := 0;
file_open(in_file, FileName, READ_MODE);
i:=0;
while (i < len) loop
readline(in_file, in_line);
hread(in_line, IbCmdV.Di.Data(i/8), readFlag);
assert readFlag report "InitMemory read error" severity ERROR;
i:=i+8;
end loop;
file_close(in_file);
-- Req toggles each time we want the BFM to do a new check.
IbCmd.Req <= '1';
WAIT ON IbCmd.ReqAck;
IbCmd.Req <= '0';
WAIT ON IbCmd.Ack;
END;
-----------------------------------------------------------------------
-- Init HostPC Memory Starting From Given Address
PROCEDURE InitMemoryFromAddr (
CONSTANT Length : IN integer; -- Length of writen data
CONSTANT Address : IN integer; -- Where to write data
CONSTANT FileName : IN string; -- Filename from where are data writen (64 bit hexa values)
SIGNAL IbCmd : INOUT IbCmdType -- Command record
) IS
file in_file : text;
variable in_line : line;
variable readFlag : boolean;
variable len : integer;
variable i : integer;
BEGIN
if (Length = 0) then
len := FileLineCount(FileName)*8;
else
len := Length;
end if;
assert (len <= MAX_INIT_DATA) report "Transaction length exceed 4096 bytes memory init limit" severity ERROR;
IbCmdV.CmdOp := InitMemoryFromAddr;
IbCmdV.Di.Length := Length;
IbCmdV.Di.MemAddr := Address;
file_open(in_file, FileName, READ_MODE);
i:=0;
while (i < len) loop
readline(in_file, in_line);
hread(in_line, IbCmdV.Di.Data((i)/8), readFlag);
assert readFlag report "InitMemoryFromAddr read error" severity ERROR;
i:=i+8;
end loop;
file_close(in_file);
-- Req toggles each time we want the BFM to do a new check.
IbCmd.Req <= '1';
WAIT ON IbCmd.ReqAck;
IbCmd.Req <= '0';
WAIT ON IbCmd.Ack;
END;
-----------------------------------------------------------------------
-- Show content of Memory
PROCEDURE ShowMemory (
SIGNAL IbCmd : INOUT IbCmdType -- Command record
) IS
BEGIN
IbCmdV.CmdOp := ShowMemory;
-- Req toggles each time we want the BFM to do a new check.
IbCmd.Req <= '1';
WAIT ON IbCmd.ReqAck;
IbCmd.Req <= '0';
WAIT ON IbCmd.Ack;
END;
END ib_bfm_pkg;
| bsd-3-clause | ae6d781cf68afc0fcfd2ed8eaceb11a4 | 0.538379 | 4.779437 | false | false | false | false |
cnplab/blockmon | fw-combo/src/IPFIX/comp/fl_pipe.vhd | 1 | 6,038 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
--
-- pipe.vhd: FrameLink Pipeline
-- Copyright (C) 2008 CESNET
-- Author(s): Martin Kosek <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: pipe.vhd 4097 2008-07-29 07:59:45Z xvozen00 $
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.math_pack.all;
-- ----------------------------------------------------------------------------
-- ENTITY DECLARATION
-- ----------------------------------------------------------------------------
entity FL_PIPE is
generic(
-- FrameLink Data Width
DATA_WIDTH : integer:= 64;
USE_OUTREG : boolean:= false
);
port(
-- Common interface
CLK : in std_logic;
RESET : in std_logic;
-- Input interface
RX_SOF_N : in std_logic;
RX_SOP_N : in std_logic;
RX_EOP_N : in std_logic;
RX_EOF_N : in std_logic;
RX_SRC_RDY_N : in std_logic;
RX_DST_RDY_N : out std_logic;
RX_DATA : in std_logic_vector(DATA_WIDTH-1 downto 0);
RX_REM : in std_logic_vector(abs(log2(DATA_WIDTH/8)-1) downto 0);
-- Output interface
TX_SOF_N : out std_logic;
TX_EOP_N : out std_logic;
TX_SOP_N : out std_logic;
TX_EOF_N : out std_logic;
TX_SRC_RDY_N : out std_logic;
TX_DST_RDY_N : in std_logic;
TX_DATA : out std_logic_vector(DATA_WIDTH-1 downto 0);
TX_REM : out std_logic_vector(abs(log2(DATA_WIDTH/8)-1) downto 0)
);
end entity FL_PIPE;
-- ----------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
-- ----------------------------------------------------------------------------
architecture fl_pipe_arch of FL_PIPE is
-- function added by xvozen00 (with change on lines 75 - added 'abs')
-- to replace log2(DATA_WIDTH/8) and handle DATA_WIDTH = 8
function REM_WIDTH
return integer is
begin
if ((DATA_WIDTH/8) <= 1) then return 2;
else return log2(DATA_WIDTH/8);
end if;
end function;
constant PIPE_WIDTH : integer := DATA_WIDTH+REM_WIDTH+4;
signal pipe_in_data : std_logic_vector(PIPE_WIDTH-1 downto 0);
signal pipe_in_src_rdy : std_logic;
signal pipe_in_dst_rdy : std_logic;
signal pipe_out_data : std_logic_vector(PIPE_WIDTH-1 downto 0);
signal pipe_out_src_rdy : std_logic;
signal pipe_out_dst_rdy : std_logic;
begin
pipe_in_data <= RX_SOF_N & RX_SOP_N & RX_EOP_N & RX_EOF_N & RX_REM & RX_DATA;
pipe_in_src_rdy <= not RX_SRC_RDY_N;
RX_DST_RDY_N <= not pipe_in_dst_rdy;
TX_SOF_N <= pipe_out_data(DATA_WIDTH+REM_WIDTH+3);
TX_SOP_N <= pipe_out_data(DATA_WIDTH+REM_WIDTH+2);
TX_EOP_N <= pipe_out_data(DATA_WIDTH+REM_WIDTH+1);
TX_EOF_N <= pipe_out_data(DATA_WIDTH+REM_WIDTH+0);
TX_DATA <= pipe_out_data(DATA_WIDTH-1 downto 0);
TX_REM <= pipe_out_data(DATA_WIDTH+REM_WIDTH-1
downto DATA_WIDTH);
TX_SRC_RDY_N <= not pipe_out_src_rdy;
pipe_out_dst_rdy <= not TX_DST_RDY_N;
-- -------------------------------------------------------------------------
-- PIPE --
-- -------------------------------------------------------------------------
PIPE : entity work.PIPE
generic map(
DATA_WIDTH => PIPE_WIDTH,
USE_OUTREG => USE_OUTREG
)
port map(
CLK => CLK,
RESET => RESET,
IN_DATA => pipe_in_data,
IN_SRC_RDY => pipe_in_src_rdy,
IN_DST_RDY => pipe_in_dst_rdy,
OUT_DATA => pipe_out_data,
OUT_SRC_RDY => pipe_out_src_rdy,
OUT_DST_RDY => pipe_out_dst_rdy
);
end fl_pipe_arch;
| bsd-3-clause | 0bc554898a4cc8faf025388857178da2 | 0.539583 | 3.863084 | false | false | false | false |
cnplab/blockmon | fw-combo/src/IPFIX/comp/mi32_fsm_master.vhd | 1 | 4,226 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- fsm_master.vhd: FSM controlling asynchronous transfer at master side
-- Copyright (C) 2006 CESNET
-- Author(s): Viktor Pus <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: fsm_master.vhd 14 2007-07-31 06:44:05Z kosek $
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity MI32_ASYNC_FSMM is
port(
RESET : in std_logic;
CLK : in std_logic;
RD : in std_logic;
WR : in std_logic;
ACK : in std_logic;
REQ : out std_logic;
ARDY : out std_logic;
DONE : out std_logic
);
end entity MI32_ASYNC_FSMM;
-- ----------------------------------------------------------------------------
-- Architecture
-- ----------------------------------------------------------------------------
architecture full of MI32_ASYNC_FSMM is
type t_fsmm is (wait_for_op, wait_for_ack, wait_for_nack);
signal fsm : t_fsmm;
signal fsm_next : t_fsmm;
signal sig_req : std_logic;
signal sig_ardy : std_logic;
begin
fsm_p : process(CLK, RESET)
begin
if RESET = '1' then
fsm <= wait_for_op;
elsif CLK'event and CLK = '1' then
fsm <= fsm_next;
end if;
end process;
fsm_next_p : process(fsm, RD, WR, ACK)
begin
fsm_next <= fsm;
case fsm is
when wait_for_op =>
if RD = '1' or WR = '1' then
fsm_next <= wait_for_ack;
end if;
when wait_for_ack =>
if ACK = '1' then
fsm_next <= wait_for_nack;
end if;
when wait_for_nack =>
if ACK = '0' then
fsm_next <= wait_for_op;
end if;
end case;
end process;
REQ <= '1' when fsm = wait_for_ack else
'0';
ARDY <= '1' when fsm = wait_for_op else
'0';
DONE <= '1' when fsm = wait_for_ack and ACK = '1' else
'0';
end architecture full;
| bsd-3-clause | 2cbf6ee2fbd0faa0d930283451e650a9 | 0.559867 | 4.21336 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/boards/terasic-de2-115/common/ipcore/pll.vhd | 8 | 19,524 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll;
ARCHITECTURE SYN OF pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire8_bv(0 DOWNTO 0) <= "0";
sub_wire8 <= To_stdlogicvector(sub_wire8_bv);
sub_wire5 <= sub_wire0(2);
sub_wire4 <= sub_wire0(0);
sub_wire2 <= sub_wire0(3);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
c3 <= sub_wire2;
locked <= sub_wire3;
c0 <= sub_wire4;
c2 <= sub_wire5;
sub_wire6 <= inclk0;
sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 2,
clk1_phase_shift => "0",
clk2_divide_by => 2,
clk2_duty_cycle => 50,
clk2_multiply_by => 1,
clk2_phase_shift => "0",
clk3_divide_by => 1,
clk3_duty_cycle => 50,
clk3_multiply_by => 2,
clk3_phase_shift => "-2000",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_USED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
inclk => sub_wire7,
clk => sub_wire0,
locked => sub_wire3
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "2"
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "25.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "100.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "-2.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ns"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "-2000"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| gpl-2.0 | c93e85d20e750cb04319b864003df408 | 0.699805 | 3.267068 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/lib/src/syncTog-rtl-ea.vhd | 3 | 4,874 | -------------------------------------------------------------------------------
--! @file syncTog-rtl-ea.vhd
--
--! @brief Synchronizer with toggling signal
--
--! @details This is a synchronizer that transfers an incoming signal to the
--! target clock domain with toggling signal levels.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity syncTog is
generic (
--! Stages
gStages : natural := 2;
--! Initialization level
gInit : std_logic := cInactivated
);
port (
--! Source reset
iSrc_rst : in std_logic;
--! Source clock
iSrc_clk : in std_logic;
--! Source data
iSrc_data : in std_logic;
--! Destination reset
iDst_rst : in std_logic;
--! Destination clock
iDst_clk : in std_logic;
--! Destination data
oDst_data : out std_logic
);
end syncTog;
architecture rtl of syncTog is
--! Source pulse
signal srcPulse : std_logic;
--! Transfer toggle
signal metaToggle : std_logic;
--! Transferred toggle
signal toggle : std_logic;
--! Destination pulse
signal dstPulse : std_logic;
begin
-- Output map
oDst_data <= dstPulse;
--! This is the first edge detector generating a single pulse.
FIRST_EDGE : entity libcommon.edgedetector
port map (
iArst => iSrc_rst,
iClk => iSrc_clk,
iEnable => cActivated,
iData => iSrc_data,
oRising => srcPulse,
oFalling => open,
oAny => open
);
--! This process generates a toggling signal, controled by the rising edge
--! of the first edge detector.
GEN_TOGGLE : process(iSrc_rst, iSrc_clk)
begin
if iSrc_rst = cActivated then
metaToggle <= cInactivated;
elsif rising_edge(iSrc_clk) then
if srcPulse = cActivated then
metaToggle <= not metaToggle;
end if;
end if;
end process GEN_TOGGLE;
--! This synchronizer transfers the metaToggle to the destination clock
--! domain.
SYNC : entity libcommon.synchronizer
generic map (
gStages => gStages,
gInit => gInit
)
port map (
iArst => iDst_rst,
iClk => iDst_clk,
iAsync => metaToggle,
oSync => toggle
);
--! The second edge detector detects any edge of the synchronized toggle.
SECOND_EDGE : entity libcommon.edgedetector
port map (
iArst => iDst_rst,
iClk => iDst_clk,
iEnable => cActivated,
iData => toggle,
oRising => open,
oFalling => open,
oAny => dstPulse
);
end rtl;
| gpl-2.0 | 8d8c6db2c747fd97ed08c4f69f8edfbd | 0.575503 | 4.797244 | false | false | false | false |
cnplab/blockmon | fw-combo/src/generator/comp/lfsr_parallel.vhd | 1 | 4,296 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- lfsr_parallel.vhd : LFSR based parallel output pseudorandom generator module
-- Copyright (C) 2009 CESNET
-- Author(s): Pavol Korcek <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: lfsr_parallel.vhd 12095 2009-11-24 15:12:11Z kastovsky $
--
library ieee;
use ieee.std_logic_1164.all;
use work.lfsr_pkg.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity lfsr_parallel is
generic (
LFSR_LENGTH : integer := 16; -- internal LFSR width
TAPS : LFSR_TAPS :=(16,15,13,4) -- polynomial
);
port (
CLK : in std_logic; -- clock signal
S_EN : in std_logic; -- shift enable
F_EN : in std_logic; -- fill enable
DIN : in std_logic_vector(LFSR_LENGTH-1 downto 0); -- seed
DOUT : out std_logic_vector(LFSR_LENGTH-1 downto 0) -- data out
);
end entity lfsr_parallel;
-- ----------------------------------------------------------------------------
-- Architecture declaration
-- ----------------------------------------------------------------------------
architecture beh of lfsr_parallel is
signal reg : std_logic_vector((LFSR_LENGTH-1) downto 0);
begin
lfsr1 : process (CLK)
variable fb : std_logic;
begin
if (CLK'event and CLK ='1') then
-- rising edge
if S_EN='1' then
-- shift enable
-- compute new bit (xor)
fb := '0';
for j in TAPS'range loop
if fb=reg(TAPS(j)-1) then
fb := '0';
else
fb := '1';
end if;
end loop; -- j
for k in reg'left downto 1 loop
reg(k) <= reg(k-1);
end loop; -- k
reg(0) <= fb;
elsif F_EN ='1' then
-- for insert seed
reg <= DIN;
end if;
DOUT <= reg;
end if;
end process lfsr1;
end architecture beh;
| bsd-3-clause | fbfc980d237978d7ffa0918bb80cffef | 0.534916 | 4.684842 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/lib/src/edgedetectorRtl.vhd | 3 | 4,148 | -------------------------------------------------------------------------------
--! @file edgedetectorRtl.vhd
--
--! @brief Edge detector
--
--! @details This is an edge detector circuit providing any, rising and falling
--! edge outputs.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity edgedetector is
port (
--! Asynchronous reset
iArst : in std_logic;
--! Clock
iClk : in std_logic;
--! Enable detection
iEnable : in std_logic;
--! Data to be sampled
iData : in std_logic;
--! Rising edge detected (unregistered)
oRising : out std_logic;
--! Falling edge detected (unregistered)
oFalling : out std_logic;
--! Any edge detected (unregistered)
oAny : out std_logic
);
end edgedetector;
architecture rtl of edgedetector is
--! Register to delay input by one clock cycle
signal reg : std_logic;
--! Register next
signal reg_next : std_logic;
--! Second register
signal reg_l : std_logic;
--! Second register next
signal reg_l_next : std_logic;
begin
-- assign input data to register
reg_next <= iData;
--! Detection
comb : process (
iEnable,
reg,
reg_l
)
begin
-- default
oRising <= cInactivated;
oFalling <= cInactivated;
oAny <= cInactivated;
if iEnable = cActivated then
-- rising edge
if reg_l = cInactivated and reg = cActivated then
oRising <= cActivated;
oAny <= cActivated;
end if;
-- falling edge
if reg_l = cActivated and reg = cInactivated then
oFalling <= cActivated;
oAny <= cActivated;
end if;
end if;
end process;
reg_l_next <= reg;
--! Clock process
regClk : process(iArst, iClk)
begin
if iArst = cActivated then
reg <= cInactivated;
reg_l <= cInactivated;
elsif rising_edge(iClk) then
reg <= reg_next;
reg_l <= reg_l_next;
end if;
end process;
end rtl;
| gpl-2.0 | f3d74e8036f77244373d788a4687705c | 0.590887 | 4.800926 | false | false | false | false |
cnplab/blockmon | fw-combo/src/IPFIX/comp/fl_transformer_down.vhd | 1 | 11,034 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- transformer_down.vhd: Implementation of DOWN architecture of FrameLink
-- Transformer component.
-- Copyright (C) 2006 CESNET
-- Author(s): Martin Louda <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: transformer_down.vhd 1659 2008-03-07 09:20:09Z sandin $
--
-- TODO:
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- library containing log2 function
use work.math_pack.all;
-- ------------------------------------------------------------------------
-- Entity declaration
-- ------------------------------------------------------------------------
entity FL_TRANSFORMER_DOWN is
generic(
-- FrameLink data buses width
-- only 8, 16, 32, 64 and 128 supported
-- !! RX_DATA_WIDTH > TX_DATA_WIDTH !!
RX_DATA_WIDTH : integer;
TX_DATA_WIDTH : integer
);
port(
CLK : in std_logic;
RESET : in std_logic;
-- RX interface
RX_DATA : in std_logic_vector(RX_DATA_WIDTH-1 downto 0);
RX_REM : in std_logic_vector(log2(RX_DATA_WIDTH/8)-1 downto 0);
RX_SOF_N : in std_logic;
RX_EOF_N : in std_logic;
RX_SOP_N : in std_logic;
RX_EOP_N : in std_logic;
RX_SRC_RDY_N : in std_logic;
RX_DST_RDY_N : out std_logic;
-- TX interface
TX_DATA : out std_logic_vector(TX_DATA_WIDTH-1 downto 0);
TX_REM : out std_logic_vector(log2(TX_DATA_WIDTH/8)-1 downto 0);
TX_SOF_N : out std_logic;
TX_EOF_N : out std_logic;
TX_SOP_N : out std_logic;
TX_EOP_N : out std_logic;
TX_SRC_RDY_N : out std_logic;
TX_DST_RDY_N : in std_logic
);
end entity FL_TRANSFORMER_DOWN;
-- ------------------------------------------------------------------------
-- Architecture declaration
-- ------------------------------------------------------------------------
architecture full_down of FL_TRANSFORMER_DOWN is
signal dst_rdy : std_logic;
signal valid_bytes : std_logic_vector(log2(RX_DATA_WIDTH/8)-1 downto 0);
signal reg_valid_bytes : std_logic_vector(log2(RX_DATA_WIDTH/8)-1 downto 0);
signal valid_count : std_logic_vector(log2(RX_DATA_WIDTH/8)-1 downto 0);
signal lblk : std_logic;
signal flag_sop : std_logic;
signal flag_eop : std_logic;
signal eop_n : std_logic;
signal sig_eop : std_logic;
signal flag_eof : std_logic;
signal sig_eof : std_logic;
signal got_valid : std_logic;
signal cnt_byte : std_logic_vector(log2(RX_DATA_WIDTH/8)-1 downto 0);
signal cnt_data : std_logic_vector(log2(RX_DATA_WIDTH/TX_DATA_WIDTH)-1 downto 0);
signal reg_data : std_logic_vector(RX_DATA_WIDTH-1 downto 0)
:= (others => '0');
signal reg_rem : std_logic_vector(log2(TX_DATA_WIDTH/8)-1 downto 0)
:= (others => '0');
signal aux_rem : std_logic_vector(log2(TX_DATA_WIDTH/8)-1 downto 0);
signal data_strobe : std_logic;
signal gen_mux_in : std_logic_vector(RX_DATA_WIDTH-1 downto 0);
signal src_rdy_n : std_logic;
signal first_word : std_logic;
begin
assert (RX_DATA_WIDTH > TX_DATA_WIDTH)
report "FL_TRANSFORMER: Bad use of DOWN architecture - RX_DATA_WIDTH must be greater than TX_DATA_WIDTH."
severity error;
-- output ports
TX_SOF_N <= RX_SOF_N or (not dst_rdy);
TX_SOP_N <= RX_SOP_N or (not dst_rdy);
TX_EOP_N <= eop_n;
TX_EOF_N <= not (lblk and (sig_eof or flag_eof));
TX_SRC_RDY_N <= src_rdy_n;
RX_DST_RDY_N <= TX_DST_RDY_N or not first_word;
TX_REM <= aux_rem
when data_strobe = '1'
else reg_rem;
first_word <= '1'
when conv_integer(cnt_data) = 0
else '0';
dst_rdy <= first_word;
aux_rem <= (others => '1')
when conv_integer(RX_REM(log2(RX_DATA_WIDTH/8)-1 downto log2(TX_DATA_WIDTH/8))) > 0
else RX_REM(log2(TX_DATA_WIDTH/8)-1 downto 0);
eop_n <= not (lblk and (sig_eop or flag_eop));
sig_eop <= dst_rdy and (not RX_EOP_N) and (not RX_SRC_RDY_N);
sig_eof <= dst_rdy and (not RX_EOF_N) and (not RX_SRC_RDY_N);
src_rdy_n <= '1'
when (RX_SRC_RDY_N = '1') and (dst_rdy = '1')
else RX_SRC_RDY_N and (not flag_sop) and (not flag_eop);
data_strobe <= dst_rdy and not RX_SRC_RDY_N;
gen_mux_in <= RX_DATA
when data_strobe = '1'
else reg_data;
-- ---------------------------------------------------------------------
-- Components
-- ---------------------------------------------------------------------
GEN_MUX_U: entity work.GEN_MUX
generic map(
DATA_WIDTH => TX_DATA_WIDTH,
MUX_WIDTH => RX_DATA_WIDTH/TX_DATA_WIDTH
)
port map(
DATA_IN => gen_mux_in,
SEL => cnt_data,
DATA_OUT => TX_DATA
);
-- ---------------------------------------------------------------------
-- Main logic
-- ---------------------------------------------------------------------
valid_bytes <= RX_REM
when (RX_EOP_N = '0') and (TX_DST_RDY_N = '0')
else conv_std_logic_vector((RX_DATA_WIDTH/8)-1, log2(RX_DATA_WIDTH/8));
valid_count <= valid_bytes
when dst_rdy = '1'
else reg_valid_bytes;
got_valid <= '1'
when not (valid_count > cnt_byte)
else '0';
-- last block identification
lblk <= got_valid
when (RX_SRC_RDY_N = '0') or (flag_sop = '1')
else '1';
cnt_bytep: process(RESET, CLK)
begin
if (CLK'event AND CLK = '1') then
if (RESET = '1') then
cnt_byte <= conv_std_logic_vector((TX_DATA_WIDTH/8)-1, log2(RX_DATA_WIDTH/8));
else
if (TX_DST_RDY_N = '0' and src_rdy_n = '0') then
if (lblk = '1') then
cnt_byte <= conv_std_logic_vector((TX_DATA_WIDTH/8)-1, log2(RX_DATA_WIDTH/8));
else
cnt_byte <= cnt_byte + conv_std_logic_vector((TX_DATA_WIDTH/8), log2(RX_DATA_WIDTH/8));
end if;
end if;
end if;
end if;
end process;
cnt_datap: process(RESET, CLK)
begin
if (CLK'event AND CLK = '1') then
if (RESET = '1') then
cnt_data <= (others => '0');
else
if ((TX_DST_RDY_N = '0') and (src_rdy_n = '0')) then
if (lblk = '1') then
cnt_data <= (others => '0');
else
cnt_data <= cnt_data + 1;
end if;
end if;
end if;
end if;
end process;
-- ---------------------------------------------------------------------
-- Registers
-- ---------------------------------------------------------------------
reg_valid_bytesp: process(RESET, CLK)
begin
if (CLK'event AND CLK = '1') then
if (RESET = '1') then
reg_valid_bytes <= (others => '0');
else
if ((dst_rdy = '1') and ((RX_SRC_RDY_N = '0') or (flag_sop = '1'))) then
reg_valid_bytes <= valid_bytes;
end if;
end if;
end if;
end process;
reg_datap: process(CLK)
begin
if (CLK'event AND CLK = '1') then
if (data_strobe = '1') then
reg_data <= RX_DATA;
end if;
end if;
end process;
reg_remp: process(CLK)
begin
if (CLK'event AND CLK = '1') then
if (data_strobe = '1') then
reg_rem <= RX_REM(log2(TX_DATA_WIDTH/8)-1 downto 0);
end if;
end if;
end process;
flag_sopp: process(RESET, CLK)
begin
if (CLK'event AND CLK = '1') then
if (RESET = '1') then
flag_sop <= '0';
else
if ((RX_SOP_N = '0') and (RX_SRC_RDY_N = '0')) then
flag_sop <= '1';
elsif (eop_n = '0') then
flag_sop <= '0';
end if;
end if;
end if;
end process;
flag_eopp: process(RESET, CLK)
begin
if (CLK'event AND CLK = '1') then
if (RESET = '1') then
flag_eop <= '0';
else
if (lblk = '1' and TX_DST_RDY_N = '0') then
flag_eop <= '0';
elsif (sig_eop = '1') then
flag_eop <= '1';
end if;
end if;
end if;
end process;
flag_eofp: process(RESET, CLK)
begin
if (CLK'event AND CLK = '1') then
if (RESET = '1') then
flag_eof <= '0';
else
if (lblk = '1' and TX_DST_RDY_N = '0') then
flag_eof <= '0';
elsif (sig_eof = '1') then
flag_eof <= '1';
end if;
end if;
end if;
end process;
end architecture full_down;
| bsd-3-clause | 9b820f7325a992b735111d1b5f740071 | 0.506707 | 3.643989 | false | false | false | false |
cnplab/blockmon | fw-combo/src/IPFIX/comp/pipe_arch.vhd | 1 | 7,398 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
--
-- pipe_arch.vhd : Internal Bus Pipeline
-- Copyright (C) 2008 CESNET
-- Author(s): Tomas Malek <[email protected]>
-- Vaclav Bartos <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: pipe_arch.vhd 14522 2010-07-20 13:54:06Z xkosar02 $
--
-- TODO:
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
-- ----------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION -- Internal Bus Pipeline --
-- ----------------------------------------------------------------------------
architecture pipe_arch of PIPE is
-- -------------------------------------------------------------------------
-- Signal declaration --
-- -------------------------------------------------------------------------
type fsm_states is (S_0, S_1, S_2, S_RESET);
signal present_state, next_state : fsm_states;
signal ce,addr : std_logic;
signal dout : std_logic_vector(DATA_WIDTH-1 downto 0);
signal reg_dout : std_logic_vector(DATA_WIDTH-1 downto 0);
signal dout_rdy : std_logic;
signal reg_dout_rdy : std_logic;
signal outreg_we : std_logic;
begin
NOT_FAKE: if (FAKE_PIPE = false) generate
-- -------------------------------------------------------------------------
-- DATA PATH --
-- -------------------------------------------------------------------------
SH_REG_DATA_WIDTH : for i in 0 to DATA_WIDTH-1 generate
begin
SH_REG_DATA : entity work.SH_REG_ELEM
port map(
CLK => CLK,
CE => ce,
ADDR(0) => addr,
ADDR(3 downto 1) => "000",
DIN => IN_DATA(i),
DOUT => dout(i)
);
end generate;
-- without output registers
OUTREG_NO : if (USE_OUTREG = false) generate
outreg_we <= OUT_DST_RDY;
OUT_DATA <= dout;
OUT_SRC_RDY <= dout_rdy;
end generate;
-- with output registers
OUTREG_YES : if (USE_OUTREG = true) generate
reg_doutp: process(CLK)
begin
if (CLK'event and CLK = '1') then
if (outreg_we = '1') then
reg_dout <= dout;
end if;
end if;
end process;
reg_dout_rdyp: process(CLK)
begin
if (CLK'event and CLK = '1') then
if (RESET = '1') then
reg_dout_rdy <= '0';
elsif (outreg_we = '1') then
reg_dout_rdy <= dout_rdy;
end if;
end if;
end process;
outreg_we <= OUT_DST_RDY or not reg_dout_rdy;
OUT_DATA <= reg_dout;
OUT_SRC_RDY <= reg_dout_rdy;
end generate;
-- -------------------------------------------------------------------------
-- CONTROL FSM --
-- -------------------------------------------------------------------------
-- synchronize logic -------------------------------------------------------
synchlogp : process(CLK)
begin
if (CLK'event and CLK = '1') then
if (RESET = '1') then
present_state <= S_RESET;
else
present_state <= next_state;
end if;
end if;
end process;
-- next state logic --------------------------------------------------------
nextstatelogicp : process(present_state,IN_SRC_RDY,outreg_we)
begin
next_state <= present_state;
case (present_state) is
when S_0 =>
if (IN_SRC_RDY = '1') then
next_state <= S_1;
end if;
when S_1 =>
if (IN_SRC_RDY = '1') and (outreg_we = '0') then
next_state <= S_2;
elsif (outreg_we = '1') and (IN_SRC_RDY = '0') then
next_state <= S_0;
end if;
when S_2 =>
if (outreg_we = '1') then
next_state <= S_1;
end if;
when S_RESET =>
next_state <= S_0;
end case;
end process;
-- output logic ------------------------------------------------------------
outputlogicp : process(present_state,IN_SRC_RDY)
begin
case (present_state) is
when S_0 =>
ce <= IN_SRC_RDY;
addr <= '0';
dout_rdy <= '0';
IN_DST_RDY <= '1';
when S_1 =>
ce <= IN_SRC_RDY;
addr <= '0';
dout_rdy <= '1';
IN_DST_RDY <= '1';
when S_2 =>
ce <= '0';
addr <= '1';
dout_rdy <= '1';
IN_DST_RDY <= '0';
when S_RESET =>
ce <= '0';
addr <= 'X';
dout_rdy <= '0';
IN_DST_RDY <= '0';
end case;
end process;
end generate;
FAKE: if (FAKE_PIPE = true) generate
OUT_DATA <= IN_DATA;
OUT_SRC_RDY <= IN_SRC_RDY;
IN_DST_RDY <= OUT_DST_RDY;
end generate;
end pipe_arch;
| bsd-3-clause | b7066a659c81f4c361963e8d27a0e7a1 | 0.463639 | 4.382701 | false | false | false | false |
ARC-Lab-UF/window_gen | src/window_gen.vhd | 1 | 26,670 | -- Copyright (c) University of Florida
--
-- This file is part of window_gen.
--
-- window_gen is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- window_gen is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with window_gen. If not, see <http://www.gnu.org/licenses/>.
-- Greg Stitt
-- University of Florida
-- Description: This entity generates configurable-sized windows from a
-- sequential stream of data. The generator provides a FIFO-like interface
-- with empty and read (ren) signals. Instead of providing a write enable,
-- the generator uses an input_valid signal that allows the user to specify when
-- inputs are valid. The generator provides a ready output that informs the
-- user when inputs are accepted. On any rising clock edge where the user
-- asserts input_valid while the generator asserts ready, the generator will
-- store that input.
--
-- The generator supports dynamically configurable image sizes and window sizes.
-- Static configuration options include a maximum image and window size, in
-- addition to the number of parallel inputs and outputs, which also
-- specifies the maximum number of windows produced each cycle. Note that
-- the generator requires an additional parallel input for each parallel window
-- output. The generator could potentially be extended to allow for more inputs
-- than outputs, but this extension would cause the internal buffering to fill
-- up faster than the outputs could empty it. If the user can provide more
-- inputs than the number of desired parallel windows, it would be best to use
-- a FIFO on the input stream to stall the stream before entering the generator.
--
-- The generator currently outputs windows that are "fully immersed" within
-- the image. Some applications (e.g., convolution) slide windows outside the
-- boundaries of the image. To achieve this functionality, pad the original
-- image and increase the specified image size accordingly. The generator will
-- then create the corresponding windows that exceed the boundaries of the
-- original image with the desired padding values.
-- Limitations: requires the specified image to be larger than the maximum
-- window size. This limitation should only affect applications with very small
-- images or very large windows. If this limitation is a problem, pad the image
-- to match the maximum window size.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.math_custom.all;
-------------------------------------------------------------------------------
-- Generics Description
-- PARALLEL_IO : Specifies the number of inputs read at a time, in addition to
-- the number of windows generated in parallel. The number of
-- inputs and outputs has to be the same. It is not possible
-- to generate more outputs than the number of provided inputs.
-- If more inputs can be provided each cycle than the desired
-- number of parallel window outputs, use a FIFO to stall the
-- input stream.
-- MAX_WINDOW_ROWS : The maximum number of rows in a generated window
-- MAX_WINDOW_COLS : The maximum number of cols in a generated window
-- MAX_IMAGE_ROWS : The maximum number of rows in an input image/stream
-- MAX_IMAGE_COLS : The maximum number of cols in an input image/stream
-- DATA_WIDTH : The width in bits of each element of the input stream.
-- INPUT0_AT_MSB : Parallel inputs can be delivered with the first
-- input (INPUT0) at the MSB or the first input stored at
-- the LSB. e.g., for PARALLEL_IO = 4:
-- in0 & in1 & in2 & in3 (for INPUT0_AT_MSB = true)
-- or alternatively:
-- in3 & in2 & in1 & in0 (for INPUT0_AT_MSN = false)
-- If providing the input stream from a memory, it is likely
-- that false is an appropriate setting.
-- (default = false)
-- BLOCK_EXTRA_INPUT : boolean that specifies whether or not the buffer should
-- prevent extra inputs from being stored by deasserting
-- the ready signal after reading all inputs. This
-- options simplifies the processing of multiple images
-- (e.g. video) because there is an period of time between
-- when the last pixel of an image enters the generator
-- and when the generator is ready to accept a new image.
-- If false, the user has to track the number of pixels in
-- the input stream to ensure that pixels from the next
-- image are not sent to the generator until the generator
-- has asserted done.
-- If true, the window generator simplifies
-- external logic because it will deassert ready after
-- reading the entire image, which will inform the user
-- that the generator is not ready for the next image.
-- We recommend setting this value to true, which simplies
-- control at the cost of a small amount of logic and
-- a multiplier.
-- (default = true)
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Port Descriptions (all control signals are active high)
-- clk: Clock
-- rst: Asynchronous reset
-- go : Starts the generation of windows using the specified image and window
-- sizes
-- ready : Asserted by the generator to specify that it is ready to accept
-- input. If the user asserts input_valid on a rising edge where ready
-- is also asserted, then the generator will store that input and the
-- user can move to the next input. Any inputs provided when ready is
-- not asserted will not be stored into the generator. Therefore, the
-- user should not move to the next output when ready = '0'.
-- read_enable : The user should assert when reading a window(s) from the
-- generator. There is no delay for a read. The window is
-- already on the output port. This signal simply tells the
-- buffer to generate the next window. In the case of
-- PARALLEL_IO > 1, asserting read_enable reads PARALLEL_IO
-- windows.
-- empty : '1' when the buffer has at least one valid window, '0' otherwise
-- image_rows : the number of rows in the input image. Must be <=
-- MAX_IMAGE_ROWS and >= MAX_WINDOW_ROWS
-- image_cols : the number of cols in the input image. Must be <=
-- MAX_IMAGE_COLS and >= MAX_WINDOW_COLS
-- window_rows : the number of rows in the generated window. Must be <=
-- MAX_WINDOW_ROWS
-- window_cols : the number of rows in the generated window. Must be <=
-- MAX_WINDOW_COLS
-- input : The current DATA_WIDTH-bit element of the input stream, or
-- PARALLEL_IO inputs in the case of PARALLEL_IO > 1. Note that the
-- order of parallel inputs can be configured with the INPUT0_AT_MSB
-- option.
-- input_valid : should be asserted by the user when "input" is valid. In the
-- case of PARALLEL_IO > 1, this specifies that PARALLEL_IO
-- inputs are valid.
-- output : A generated window, or PARALLEL_IO windows when PARALLEL_IO > 1.
-- The output always produces a maximum-sized window. When smaller
-- windows are requested, ignore the elements outside the requested
-- window. In the case of PARALLEL_IO > 1, the number of rows in the
-- output is MAX_WINDOW_ROWS+PARALLEL_IO-1 to account for the multiple
-- windows. The first window starts in column 0, the second in column
-- 1, etc. All windows start in row 0.
--
-- Note that the output is "vectorized" into a 1D vector to avoid
-- limitations of pre-2008 VHDL. The top-left element of the first
-- window (0,0) is stored in the highest bits of the vector. The rest
-- of the elements appear in row-major order.
--
-- We have provided a basic template (template.vhd) to demonstrate
-- how to more conveniently access the window outputs.
-- window_valid : Specifies which of the PARALLEL_IO windows on the output
-- signal are valid. When PARALLEL_IO > 1, there will be
-- situations where some windows are invalid due to various
-- situations (e.g., windows exceeding the current row of the
-- image). The MSB corresponds to the earliest window (the one
-- starting in column 0 of the output), and the LSB corresponds
-- to the latest window (the one starting in column
-- PARALLEL_IO-1 of the output)
-- done : Asserted by the generator when all windows have been generated
-- (but not read from the buffer). In other words, if there are less than
-- PARALLEL_IO windows left to generate, and there are the same number
-- of valid windows left in the buffer, done will be asserted.
-------------------------------------------------------------------------------
entity window_gen is
generic (
PARALLEL_IO : positive;
MAX_WINDOW_ROWS : positive;
MAX_WINDOW_COLS : positive;
MAX_IMAGE_ROWS : positive;
MAX_IMAGE_COLS : positive;
DATA_WIDTH : positive;
INPUT0_AT_MSB : boolean := false;
BLOCK_EXTRA_INPUT : boolean := true);
port (
clk : in std_logic;
rst : in std_logic;
go : in std_logic;
ready : out std_logic;
read_enable : in std_logic;
empty : out std_logic;
image_rows : in std_logic_vector(bitsNeeded(MAX_IMAGE_ROWS)-1 downto 0);
image_cols : in std_logic_vector(bitsNeeded(MAX_IMAGE_COLS)-1 downto 0);
window_rows : in std_logic_vector(bitsNeeded(MAX_WINDOW_ROWS)-1 downto 0);
window_cols : in std_logic_vector(bitsNeeded(MAX_WINDOW_COLS)-1 downto 0);
input : in std_logic_vector(DATA_WIDTH*PARALLEL_IO-1 downto 0);
input_valid : in std_logic;
output : out std_logic_vector(MAX_WINDOW_ROWS*(MAX_WINDOW_COLS+PARALLEL_IO-1)*DATA_WIDTH-1 downto 0);
window_valid : out std_logic_vector(PARALLEL_IO-1 downto 0);
done : out std_logic);
end window_gen;
architecture STR of window_gen is
signal window_buffer_rst : std_logic;
signal window_buffer_empty : std_logic;
signal window_buffer_is_edge : std_logic_vector(PARALLEL_IO-1 downto 0);
signal window_buffer_output : std_logic_vector(DATA_WIDTH*PARALLEL_IO*MAX_WINDOW_ROWS-1 downto 0);
signal window_buffer_done : std_logic;
signal coalescer_rst : std_logic;
signal coalescer_read_request : std_logic;
signal coalescer_input_ready : std_logic;
signal fifo_vr_rst : std_logic;
signal fifo_vr_rd : std_logic;
signal fifo_vr_rd_amount : std_logic_vector(bitsNeeded(parallel_io)-1 downto 0);
-- signal fifo_vr_empty : std_logic;
signal fifo_vr_full : std_logic;
signal fifo_vr_output : std_logic_vector(parallel_io*data_width-1 downto 0);
signal fifo_vr_count : std_logic_vector(bitsNeeded(parallel_io)-1 downto 0);
signal cols_remaining, col : integer range 0 to MAX_IMAGE_COLS;
signal rd_amount : integer range 0 to PARALLEL_IO;
signal ready_s : std_logic;
signal read_input_s : std_logic;
signal window_buffer_input_ready : std_logic;
signal valid_rd : std_logic;
signal coalescer_empty : std_logic;
signal coalescer_done : std_logic;
signal r_done, done_s : std_logic;
type state_type is (S_WAIT_FOR_GO, S_COMPUTE_BUFFER_SIZE, S_WAIT_FOR_DONE, S_WAIT_GO_CLEAR);
constant MAX_BUFFER_SIZE : positive := positive(ceil(real(MAX_IMAGE_COLS)/real(PARALLEL_IO)));
signal r_div_count, div_count_s : unsigned(image_cols'length-1 downto 0);
signal r_buffer_size, buffer_size_s : unsigned(bitsNeeded(MAX_BUFFER_SIZE)-1 downto 0);
signal r_image_rows, image_rows_s : std_logic_vector(bitsNeeded(MAX_IMAGE_ROWS)-1 downto 0);
signal r_image_cols, image_cols_s : std_logic_vector(bitsNeeded(MAX_IMAGE_COLS)-1 downto 0);
signal r_window_rows, window_rows_s : std_logic_vector(bitsNeeded(MAX_WINDOW_ROWS)-1 downto 0);
signal r_window_cols, window_cols_s : std_logic_vector(bitsNeeded(MAX_WINDOW_COLS)-1 downto 0);
signal r_buffer_size_ready, buffer_size_ready_s : std_logic;
signal r_active, active_s : std_logic;
signal state, next_state : state_type;
signal block_input : std_logic;
begin
---------------------------------------------------------------------
-- Control
-- State machine that waits for go, saves the image and row
-- sizes in regsiters, computes the appropriate buffer size based on
-- the image size, and then waits for all windows to be generated
-- before asserting done
--------------------------------------------------------------------
process(clk, rst)
begin
if (rst = '1') then
r_image_rows <= (others => '0');
r_image_cols <= (others => '0');
r_window_rows <= (others => '0');
r_window_cols <= (others => '0');
r_div_count <= (others => '0');
r_buffer_size <= (others => '0');
r_buffer_size_ready <= '0';
r_active <= '0';
r_done <= '0';
state <= S_WAIT_FOR_GO;
elsif (rising_edge(clk)) then
r_image_rows <= image_rows_s;
r_image_cols <= image_cols_s;
r_window_rows <= window_rows_s;
r_window_cols <= window_cols_s;
r_div_count <= div_count_s;
r_buffer_size <= buffer_size_s;
r_buffer_size_ready <= buffer_size_ready_s;
r_active <= active_s;
r_done <= done_s;
state <= next_state;
end if;
end process;
process(rst, state, go, r_div_count, r_buffer_size, r_image_rows, r_image_cols, r_window_rows, r_window_cols, r_done, r_buffer_size_ready, r_active, image_rows, image_cols, window_rows, window_cols, coalescer_done)
begin
fifo_vr_rst <= rst;
window_buffer_rst <= rst;
coalescer_rst <= rst;
image_rows_s <= r_image_rows;
image_cols_s <= r_image_cols;
window_rows_s <= r_window_rows;
window_cols_s <= r_window_cols;
div_count_s <= r_div_count;
buffer_size_s <= r_buffer_size;
buffer_size_ready_s <= r_buffer_size_ready;
active_s <= r_active;
done_s <= r_done;
next_state <= state;
case state is
when S_WAIT_FOR_GO =>
active_s <= '0';
buffer_size_s <= to_unsigned(0, buffer_size_s'length);
if (go = '1') then
-- register inputs to avoid problems if user changes
-- them during execution
image_rows_s <= image_rows;
image_cols_s <= image_cols;
window_rows_s <= window_rows;
window_cols_s <= window_cols;
-- reset all helper entities
fifo_vr_rst <= '1';
window_buffer_rst <= '1';
coalescer_rst <= '1';
-- immediately change the done signal on go
done_s <= '0';
-- initialize divider computation
div_count_s <= unsigned(image_cols);
buffer_size_ready_s <= '0';
next_state <= S_COMPUTE_BUFFER_SIZE;
end if;
-- calculate the size of each row buffer
-- r_buffer_size = ceil(image_cols % PARALLEL_IO);
-- This state uses subtraction to avoid a divider. Although this
-- code delays the start of the buffer, it only has to be done
-- once for a complete slide of the window across the image.
-- TODO: this isn't needed when PARALLEL_IO is a power of two,
-- which should be added as an if generate
when S_COMPUTE_BUFFER_SIZE =>
active_s <= '1';
if (r_div_count >= PARALLEL_IO) then
div_count_s <= r_div_count - PARALLEL_IO;
buffer_size_s <= r_buffer_size + 1;
elsif (r_div_count > 0) then
buffer_size_s <= r_buffer_size + 1;
next_state <= S_WAIT_FOR_DONE;
else
next_state <= S_WAIT_FOR_DONE;
end if;
when S_WAIT_FOR_DONE =>
-- flag specifying completion of the buffer size computation
buffer_size_ready_s <= '1';
-- waiting until all windows have been generated
if (coalescer_done = '1') then
done_s <= '1';
active_s <= '0';
next_state <= S_WAIT_GO_CLEAR;
end if;
when S_WAIT_GO_CLEAR =>
-- ensures that the generator won't start again if go is
-- continually asserted. It will only restart after go is
-- deasserted for at least one cycle and then reasserted.
if (go = '0') then
next_state <= S_WAIT_FOR_GO;
end if;
end case;
end process;
-- the generator is ready when the vr fifo isn't full, the buffer size has
-- been computed, and the block_input flag isn't asserted.
ready_s <= not fifo_vr_full and r_buffer_size_ready and not block_input;
ready <= ready_s;
-- the vr fifo should read the input anytime there is a valid input and
-- the generator is ready
read_input_s <= input_valid and ready_s;
--------------------------------------------------------------------
-- FIFO_VR
-- writes PARALLEL_IO inputs at a time and reads a variable amount up to
-- PARALLEL_IO depending on location of the current inputs in the image.
-- e.g. If reading PARALLEL_IO inputs exceeds the current row of the image,
-- this entity enables fewer elements to be read.
--------------------------------------------------------------------
U_FIFO_VR : entity work.fifo_vr
generic map (
data_width => DATA_WIDTH,
parallel_io => PARALLEL_IO,
input0_at_MSB => INPUT0_AT_MSB,
output0_at_MSB => true)
port map (
clk => clk,
rst => fifo_vr_rst,
rd => fifo_vr_rd,
rd_amount => fifo_vr_rd_amount,
wr => read_input_s,
-- empty => fifo_vr_empty,
empty => open,
full => fifo_vr_full,
input => input,
output => fifo_vr_output,
count => fifo_vr_count,
-- count => open,
valid_out => open
);
U_BLOCK_INPUT : if BLOCK_EXTRA_INPUT = true generate
-- track writes into fifo_vr
-- This is needed to know when to block the input
process(clk, fifo_vr_rst)
-- slight hack: use variables to avoid unused signal warnings when
-- generics disable this process
constant MAX_IN_COUNT : positive := positive(ceil(real(MAX_IMAGE_COLS*MAX_IMAGE_ROWS)/real(PARALLEL_IO))) * PARALLEL_IO;
variable in_count : integer range 0 to MAX_IN_COUNT;
begin
if (fifo_vr_rst = '1') then
in_count := 0;
block_input <= '0';
elsif (rising_edge(clk)) then
if (read_input_s = '1') then
-- NOTE: can cause harmless latch warning when
-- PARALLEL_IO is even because in_count(0) will always
-- be 0.
in_count := in_count + PARALLEL_IO;
if (in_count >= unsigned(r_image_cols)*unsigned(r_image_rows)) then
block_input <= '1';
end if;
end if;
end if;
end process;
end generate;
U_NO_BLOCK_INPUT : if BLOCK_EXTRA_INPUT = false generate
block_input <= '0';
end generate;
-- track the current column index for each read from fifo_vr
-- This is needed to know how many columns remain in the current row
process(clk, rst)
begin
if (rst = '1') then
col <= 0;
elsif (rising_edge(clk)) then
if (fifo_vr_rd = '1') then
if (col + rd_amount < unsigned(r_image_cols)) then
col <= col + rd_amount;
else
-- reset the column for the next row
col <= 0;
end if;
end if;
end if;
end process;
-- determine columns remaining in current row
cols_remaining <= to_integer(unsigned(r_image_cols)) - col;
-- always read PARALLEL_IO inputs, unless that exceeds the end of a row
rd_amount <= PARALLEL_IO when cols_remaining >= PARALLEL_IO else cols_remaining;
-- assert(rd_amount <= unsigned(fifo_vr_count)) report "ERROR: FIFO_VR reading more data than is available.";
-- convert rd_amount to slv for fifo_vr input
fifo_vr_rd_amount <= std_logic_vector(to_unsigned(rd_amount, fifo_vr_rd_amount'length));
-- the input to the window_buffer is ready anytime the variable FIFO has
-- enough data to read. It is important not to just check for empty because
-- the fifo_vr might have data, but not as much as the window_buffer expects
-- window_buffer_input_ready <= not fifo_vr_empty and (unsigned(fifo_vr_count) >= rd_amount);
window_buffer_input_ready <= '1' when unsigned(fifo_vr_count) >= rd_amount else '0';
--------------------------------------------------------------------
-- WG_BUFFER (Window Buffer)
-- array of fifos, one for each row of the window where each fifo is the
-- size of a row (the number of columns) in the image when PARALLEL_IO = 1.
-- When PARALLEL_IO > 1, each FIFO has ceil(image_cols%PARALLEL_IO)
-- elements because each FIFO entry stores PARALLEL_IO inputs.
--------------------------------------------------------------------
U_BUFFER : entity work.wg_buffer
generic map (
PARALLEL_IO => PARALLEL_IO,
DATA_WIDTH => DATA_WIDTH,
MAX_WINDOW_ROWS => MAX_WINDOW_ROWS,
MAX_WINDOW_COLS => MAX_WINDOW_COLS,
MAX_IMAGE_ROWS => MAX_IMAGE_ROWS,
MAX_IMAGE_COLS => MAX_IMAGE_COLS,
MAX_BUFFER_SIZE => MAX_BUFFER_SIZE)
port map (
clk => clk,
rst => window_buffer_rst,
active => r_active,
ren => coalescer_read_request,
input_ready => window_buffer_input_ready,
read_input => fifo_vr_rd,
empty => window_buffer_empty,
is_edge => window_buffer_is_edge,
buffer_size => std_logic_vector(r_buffer_size),
image_rows => r_image_rows,
image_cols => r_image_cols,
window_rows => r_window_rows,
window_cols => r_window_cols,
input => fifo_vr_output,
output => window_buffer_output,
done => window_buffer_done);
--------------------------------------------------------------------
-- WB_COALESCER (Window Coalescer)
-- 2D register buffer that coalesces columns from the window buffer
-- into complete windows
--------------------------------------------------------------------
-- the coalescer input is ready any time the window_buffer is not empty,
-- which corresponds to there being at least one element in each FIFO (i.e.
-- one full column of the next window)
coalescer_input_ready <= not window_buffer_empty;
U_COALESCE : entity work.wg_coalescer
generic map (
PARALLEL_IO => PARALLEL_IO,
NUM_ROWS => MAX_WINDOW_ROWS,
NUM_COLS => MAX_WINDOW_COLS,
DATA_WIDTH => DATA_WIDTH)
port map (
clk => clk,
rst => coalescer_rst,
ren => valid_rd,
read_input => coalescer_read_request,
empty => coalescer_empty,
input => window_buffer_output,
input_ready => coalescer_input_ready,
input_done => window_buffer_done,
is_edge => window_buffer_is_edge,
output => output,
window_valid => window_valid,
done => coalescer_done);
-- a user read is valid when the coalescer isn't empty;
valid_rd <= read_enable and not coalescer_empty;
-- the window buffer is empty when the register buffer is empty
empty <= coalescer_empty;
done <= done_s;
end STR;
| gpl-3.0 | c385a01b9338081d6a1ac09ebda78e1c | 0.557218 | 4.238042 | false | false | false | false |
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