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cnplab/blockmon | fw-combo/src/netcope-sim/testbench.vhd | 1 | 19,706 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- testbench.vhd: Testbench for the Application entity
-- Copyright (C) 2009 CESNET
-- Author(s): Viktor Pus <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: testbench.vhd 12037 2011-04-15 13:17:09Z kastovsky $
--
-- TODO:
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.ib_pkg.all;
use work.ib_bfm_pkg.all;
use work.mi_bfm_pkg.all;
use work.fl_bfm_pkg.all;
use work.fl_bfm_rdy_pkg.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity testbench is
end entity testbench;
-- ----------------------------------------------------------------------------
-- Architecture declaration
-- ----------------------------------------------------------------------------
architecture behavioral of testbench is
constant MEMORY_BASE_ADDR : std_logic_vector(63 downto 0) := X"0000000000000000";
constant MEMORY_SIZE : integer := 16#94000#;
-- ----------------------------------------------------------------------
-- CLOCKs and RESET
-- ----------------------------------------------------------------------
-- CLK:
signal clk : std_logic;
-- reset
signal reset : std_logic;
-- ----------------------------------------------------------------------
-- Interconnection system
-- ----------------------------------------------------------------------
-- Internal Bus interface (Fast)
signal ib_up_data : std_logic_vector(63 downto 0);
signal ib_up_sop_n : std_logic;
signal ib_up_eop_n : std_logic;
signal ib_up_src_rdy_n : std_logic;
signal ib_up_dst_rdy_n : std_logic;
signal ib_down_data : std_logic_vector(63 downto 0);
signal ib_down_sop_n : std_logic;
signal ib_down_eop_n : std_logic;
signal ib_down_src_rdy_n : std_logic;
signal ib_down_dst_rdy_n : std_logic;
-- MI32
signal mi32_dwr : std_logic_vector(31 downto 0);
signal mi32_addr : std_logic_vector(31 downto 0);
signal mi32_rd : std_logic;
signal mi32_wr : std_logic;
signal mi32_be : std_logic_vector(3 downto 0);
signal mi32_drd : std_logic_vector(31 downto 0);
signal mi32_ardy : std_logic;
signal mi32_drdy : std_logic;
-- Timestamp for pacodag
signal ts : std_logic_vector(63 downto 0);
signal ts_dv : std_logic;
signal ts_clk : std_logic;
-- ----------------------------------------------------------------------
-- Experiment FrameLink interface signals
-- ----------------------------------------------------------------------
-- NETWORK -> APPLICATION
signal network_rx0_data : std_logic_vector(63 downto 0);
signal network_rx0_drem : std_logic_vector(2 downto 0);
signal network_rx0_sof_n : std_logic;
signal network_rx0_eof_n : std_logic;
signal network_rx0_sop_n : std_logic;
signal network_rx0_eop_n : std_logic;
signal network_rx0_src_rdy_n : std_logic;
signal network_rx0_dst_rdy_n : std_logic;
signal network_rx1_data : std_logic_vector(63 downto 0);
signal network_rx1_drem : std_logic_vector(2 downto 0);
signal network_rx1_sof_n : std_logic;
signal network_rx1_eof_n : std_logic;
signal network_rx1_sop_n : std_logic;
signal network_rx1_eop_n : std_logic;
signal network_rx1_src_rdy_n : std_logic;
signal network_rx1_dst_rdy_n : std_logic;
-- APPLICATION -> NETWORK
signal network_tx0_data : std_logic_vector(63 downto 0);
signal network_tx0_drem : std_logic_vector(2 downto 0);
signal network_tx0_sof_n : std_logic;
signal network_tx0_eof_n : std_logic;
signal network_tx0_sop_n : std_logic;
signal network_tx0_eop_n : std_logic;
signal network_tx0_src_rdy_n : std_logic;
signal network_tx0_dst_rdy_n : std_logic;
signal network_tx1_data : std_logic_vector(63 downto 0);
signal network_tx1_drem : std_logic_vector(2 downto 0);
signal network_tx1_sof_n : std_logic;
signal network_tx1_eof_n : std_logic;
signal network_tx1_sop_n : std_logic;
signal network_tx1_eop_n : std_logic;
signal network_tx1_src_rdy_n : std_logic;
signal network_tx1_dst_rdy_n : std_logic;
-- DMA interface
-- APPLICATION -> DMA
signal dma_rx0_data : std_logic_vector(63 downto 0);
signal dma_rx0_drem : std_logic_vector(2 downto 0);
signal dma_rx0_sof_n : std_logic;
signal dma_rx0_eof_n : std_logic;
signal dma_rx0_sop_n : std_logic;
signal dma_rx0_eop_n : std_logic;
signal dma_rx0_src_rdy_n : std_logic;
signal dma_rx0_dst_rdy_n : std_logic;
signal dma_rx1_data : std_logic_vector(63 downto 0);
signal dma_rx1_drem : std_logic_vector(2 downto 0);
signal dma_rx1_sof_n : std_logic;
signal dma_rx1_eof_n : std_logic;
signal dma_rx1_sop_n : std_logic;
signal dma_rx1_eop_n : std_logic;
signal dma_rx1_src_rdy_n : std_logic;
signal dma_rx1_dst_rdy_n : std_logic;
-- DMA -> APPLICATION
signal dma_tx0_data : std_logic_vector(63 downto 0);
signal dma_tx0_drem : std_logic_vector(2 downto 0);
signal dma_tx0_sof_n : std_logic;
signal dma_tx0_eof_n : std_logic;
signal dma_tx0_sop_n : std_logic;
signal dma_tx0_eop_n : std_logic;
signal dma_tx0_src_rdy_n : std_logic;
signal dma_tx0_dst_rdy_n : std_logic;
signal dma_tx1_data : std_logic_vector(63 downto 0);
signal dma_tx1_drem : std_logic_vector(2 downto 0);
signal dma_tx1_sof_n : std_logic;
signal dma_tx1_eof_n : std_logic;
signal dma_tx1_sop_n : std_logic;
signal dma_tx1_eop_n : std_logic;
signal dma_tx1_src_rdy_n : std_logic;
signal dma_tx1_dst_rdy_n : std_logic;
-- ----------------------------------------------------------------------
-- Time constants
-- ----------------------------------------------------------------------
constant clkper : time := 8 ns;
constant reset_time : time := 10*clkper;
-- ----------------------------------------------------------------------------
-- Architecture body
-- ----------------------------------------------------------------------------
begin
UUT : entity work.application
port map(
CLK => clk,
RESET => reset,
-- network interface
-- NETWORK -> APPLICATION
IBUF0_TX_DATA => network_rx0_data,
IBUF0_TX_REM => network_rx0_drem,
IBUF0_TX_SOF_N => network_rx0_sof_n,
IBUF0_TX_EOF_N => network_rx0_eof_n,
IBUF0_TX_SOP_N => network_rx0_sop_n,
IBUF0_TX_EOP_N => network_rx0_eop_n,
IBUF0_TX_SRC_RDY_N => network_rx0_src_rdy_n,
IBUF0_TX_DST_RDY_N => network_rx0_dst_rdy_n,
IBUF1_TX_DATA => network_rx1_data,
IBUF1_TX_REM => network_rx1_drem,
IBUF1_TX_SOF_N => network_rx1_sof_n,
IBUF1_TX_EOF_N => network_rx1_eof_n,
IBUF1_TX_SOP_N => network_rx1_sop_n,
IBUF1_TX_EOP_N => network_rx1_eop_n,
IBUF1_TX_SRC_RDY_N => network_rx1_src_rdy_n,
IBUF1_TX_DST_RDY_N => network_rx1_dst_rdy_n,
-- APPLICATION -> NETWORK
OBUF0_RX_DATA => network_tx0_data,
OBUF0_RX_REM => network_tx0_drem,
OBUF0_RX_SOF_N => network_tx0_sof_n,
OBUF0_RX_EOF_N => network_tx0_eof_n,
OBUF0_RX_SOP_N => network_tx0_sop_n,
OBUF0_RX_EOP_N => network_tx0_eop_n,
OBUF0_RX_SRC_RDY_N => network_tx0_src_rdy_n,
OBUF0_RX_DST_RDY_N => network_tx0_dst_rdy_n,
OBUF1_RX_DATA => network_tx1_data,
OBUF1_RX_REM => network_tx1_drem,
OBUF1_RX_SOF_N => network_tx1_sof_n,
OBUF1_RX_EOF_N => network_tx1_eof_n,
OBUF1_RX_SOP_N => network_tx1_sop_n,
OBUF1_RX_EOP_N => network_tx1_eop_n,
OBUF1_RX_SRC_RDY_N => network_tx1_src_rdy_n,
OBUF1_RX_DST_RDY_N => network_tx1_dst_rdy_n,
-- DMA interface
-- APPLICATION -> DMA
RX0_DATA => dma_tx0_data,
RX0_DREM => dma_tx0_drem,
RX0_SOF_N => dma_tx0_sof_n,
RX0_EOF_N => dma_tx0_eof_n,
RX0_SOP_N => dma_tx0_sop_n,
RX0_EOP_N => dma_tx0_eop_n,
RX0_SRC_RDY_N => dma_tx0_src_rdy_n,
RX0_DST_RDY_N => dma_tx0_dst_rdy_n,
RX1_DATA => dma_tx1_data,
RX1_DREM => dma_tx1_drem,
RX1_SOF_N => dma_tx1_sof_n,
RX1_EOF_N => dma_tx1_eof_n,
RX1_SOP_N => dma_tx1_sop_n,
RX1_EOP_N => dma_tx1_eop_n,
RX1_SRC_RDY_N => dma_tx1_src_rdy_n,
RX1_DST_RDY_N => dma_tx1_dst_rdy_n,
-- DMA -> APPLICATION
TX0_DATA => dma_rx0_data,
TX0_DREM => dma_rx0_drem,
TX0_SOF_N => dma_rx0_sof_n,
TX0_EOF_N => dma_rx0_eof_n,
TX0_SOP_N => dma_rx0_sop_n,
TX0_EOP_N => dma_rx0_eop_n,
TX0_SRC_RDY_N => dma_rx0_src_rdy_n,
TX0_DST_RDY_N => dma_rx0_dst_rdy_n,
TX1_DATA => dma_rx1_data,
TX1_DREM => dma_rx1_drem,
TX1_SOF_N => dma_rx1_sof_n,
TX1_EOF_N => dma_rx1_eof_n,
TX1_SOP_N => dma_rx1_sop_n,
TX1_EOP_N => dma_rx1_eop_n,
TX1_SRC_RDY_N => dma_rx1_src_rdy_n,
TX1_DST_RDY_N => dma_rx1_dst_rdy_n,
-- internal bus
IB_DOWN_DATA => ib_down_data,
IB_DOWN_SOF_N => ib_down_sop_n,
IB_DOWN_EOF_N => ib_down_eop_n,
IB_DOWN_SRC_RDY_N => ib_down_src_rdy_n,
IB_DOWN_DST_RDY_N => ib_down_dst_rdy_n,
IB_UP_DATA => ib_up_data,
IB_UP_SOF_N => ib_up_sop_n,
IB_UP_EOF_N => ib_up_eop_n,
IB_UP_SRC_RDY_N => ib_up_src_rdy_n,
IB_UP_DST_RDY_N => ib_up_dst_rdy_n,
-- mi32 bus
MI32_DWR => mi32_dwr,
MI32_ADDR => mi32_addr,
MI32_RD => mi32_rd,
MI32_WR => mi32_wr,
MI32_BE => mi32_be,
MI32_DRD => mi32_drd,
MI32_ARDY => mi32_ardy,
MI32_DRDY => mi32_drdy,
-- Timestamps for pacodag
TS => ts,
TS_DV => ts_dv,
TS_CLK => ts_clk,
-- PACODAG interface (no simulation model available)
IBUF0_CTRL_CLK => clk,
IBUF0_CTRL_DATA => open,
IBUF0_CTRL_REM => open,
IBUF0_CTRL_SRC_RDY_N => open,
IBUF0_CTRL_SOP_N => open,
IBUF0_CTRL_EOP_N => open,
IBUF0_CTRL_DST_RDY_N => '0',
IBUF0_CTRL_RDY => open,
IBUF1_CTRL_CLK => clk,
IBUF1_CTRL_DATA => open,
IBUF1_CTRL_REM => open,
IBUF1_CTRL_SRC_RDY_N => open,
IBUF1_CTRL_SOP_N => open,
IBUF1_CTRL_EOP_N => open,
IBUF1_CTRL_DST_RDY_N => '0',
IBUF1_CTRL_RDY => open,
-- IBUF status interface (no status information available)
IBUF0_SOP => '0',
IBUF0_PAYLOAD_LEN => X"0100",
IBUF0_FRAME_ERROR => '0',
IBUF0_CRC_CHECK_FAILED => '0',
IBUF0_MAC_CHECK_FAILED => '0',
IBUF0_LEN_BELOW_MIN => '0',
IBUF0_LEN_OVER_MTU => '0',
IBUF0_STAT_DV => '1',
IBUF1_SOP => '0',
IBUF1_PAYLOAD_LEN => X"0100",
IBUF1_FRAME_ERROR => '0',
IBUF1_CRC_CHECK_FAILED => '0',
IBUF1_MAC_CHECK_FAILED => '0',
IBUF1_LEN_BELOW_MIN => '0',
IBUF1_LEN_OVER_MTU => '0',
IBUF1_STAT_DV => '1'
);
-- CLK generator
clk_gen_p: process
begin
clk <= '1';
wait for clkper/2;
clk <= '0';
wait for clkper/2;
end process;
-- Internal Bus simulation component
IB_BFM_I : entity work.IB_BFM
generic map(
MEMORY_BASE_ADDR => MEMORY_BASE_ADDR,
MEMORY_SIZE => MEMORY_SIZE
)
port map(
-- Common interface
CLK => clk,
-- Internal Bus Interface
IB_DOWN_DATA => ib_down_data,
IB_DOWN_SOF_N => ib_down_sop_n,
IB_DOWN_EOF_N => ib_down_eop_n,
IB_DOWN_SRC_RDY_N => ib_down_src_rdy_n,
IB_DOWN_DST_RDY_N => ib_down_dst_rdy_n,
IB_UP_DATA => ib_up_data,
IB_UP_SOF_N => ib_up_sop_n,
IB_UP_EOF_N => ib_up_eop_n,
IB_UP_SRC_RDY_N => ib_up_src_rdy_n,
IB_UP_DST_RDY_N => ib_up_dst_rdy_n
);
-- MI32 Bus simulation component
MI_BFM_I : entity work.MI_BFM
port map (
CLK => clk,
RESET => reset,
MI32_DWR => mi32_dwr,
MI32_ADDR => mi32_addr,
MI32_BE => mi32_be,
MI32_RD => mi32_rd,
MI32_WR => mi32_wr,
MI32_ARDY => mi32_ardy,
MI32_DRD => mi32_drd,
MI32_DRDY => mi32_drdy
);
-- FrameLink simulation component
FL_BFM_NET_RX0 : entity work.FL_BFM
generic map (
DATA_WIDTH => 64,
FL_BFM_ID => 0)
port map (
-- Common interface
RESET => reset,
CLK => clk,
TX_DATA => network_rx0_data,
TX_REM => network_rx0_drem,
TX_SOF_N => network_rx0_sof_n,
TX_EOF_N => network_rx0_eof_n,
TX_SOP_N => network_rx0_sop_n,
TX_EOP_N => network_rx0_eop_n,
TX_SRC_RDY_N=> network_rx0_src_rdy_n,
TX_DST_RDY_N=> network_rx0_dst_rdy_n);
-- FrameLink simulation component
FL_BFM_NET_RX1 : entity work.FL_BFM
generic map (
DATA_WIDTH => 64,
FL_BFM_ID => 1)
port map (
-- Common interface
RESET => reset,
CLK => clk,
TX_DATA => network_rx1_data,
TX_REM => network_rx1_drem,
TX_SOF_N => network_rx1_sof_n,
TX_EOF_N => network_rx1_eof_n,
TX_SOP_N => network_rx1_sop_n,
TX_EOP_N => network_rx1_eop_n,
TX_SRC_RDY_N=> network_rx1_src_rdy_n,
TX_DST_RDY_N=> network_rx1_dst_rdy_n);
-- FrameLink simulation component
FL_BFM_DMA_TX0 : entity work.FL_BFM
generic map (
DATA_WIDTH => 64,
FL_BFM_ID => 2)
port map (
-- Common interface
RESET => reset,
CLK => clk,
TX_DATA => dma_tx0_data,
TX_REM => dma_tx0_drem,
TX_SOF_N => dma_tx0_sof_n,
TX_EOF_N => dma_tx0_eof_n,
TX_SOP_N => dma_tx0_sop_n,
TX_EOP_N => dma_tx0_eop_n,
TX_SRC_RDY_N=> dma_tx0_src_rdy_n,
TX_DST_RDY_N=> dma_tx0_dst_rdy_n);
-- FrameLink simulation component
FL_BFM_DMA_TX1 : entity work.FL_BFM
generic map (
DATA_WIDTH => 64,
FL_BFM_ID => 3)
port map (
-- Common interface
RESET => reset,
CLK => clk,
TX_DATA => dma_tx1_data,
TX_REM => dma_tx1_drem,
TX_SOF_N => dma_tx1_sof_n,
TX_EOF_N => dma_tx1_eof_n,
TX_SOP_N => dma_tx1_sop_n,
TX_EOP_N => dma_tx1_eop_n,
TX_SRC_RDY_N=> dma_tx1_src_rdy_n,
TX_DST_RDY_N=> dma_tx1_dst_rdy_n);
-----------------------------------------------------------------------------
-- Main testbench process
-----------------------------------------------------------------------------
tb : process
variable mi32_data : std_logic_vector(31 downto 0);
begin
-- Set Destination Ready signals to active
dma_rx0_dst_rdy_n <= '0';
dma_rx1_dst_rdy_n <= '0';
network_tx0_dst_rdy_n <= '0';
network_tx1_dst_rdy_n <= '0';
-- Reset the design
reset <= '1';
wait for reset_time;
reset <= '0';
wait for 5*clkper;
IBLocalWrite(X"02300000", -- DST Addr
X"FFFFFFF0", -- SRC Addr
8, -- Length (Bytes)
220, -- Tag
X"FEDCBA9876543210", -- Data
IbCmd); -- Command record
wait for 5*clkper;
IBLocalWrite(X"02300008", -- DST Addr
X"FFFFFFF0", -- SRC Addr
8, -- Length (Bytes)
220, -- Tag
X"1111222233334444", -- Data
IbCmd); -- Command record
wait for 5*clkper;
IBLocalRead( X"02300000", -- SRC Addr
X"FFFFFFF0", -- DST Addr
16, -- Length (Bytes)
220, -- Tag
IbCmd); -- Command record
wait for 5*clkper;
-- Recieve ICMP packet from network interface 0
FLWriteFile("./packets/icmp_net0.txt", EVER, flCmd_0, 0);
-- Recieve ICMP packet from network interface 1
FLWriteFile("./packets/icmp_net1.txt", EVER, flCmd_1, 1);
-- Dma module sending ICMP packet to interface 0, toggling SRC_RDY_N
FLWriteFile("./packets/icmp_dma.txt", ONOFF, flCmd_2, 2);
-- Dma module sending ICMP packet to interface 1, random SRC_RDY_N
FLWriteFile("./packets/icmp_dma.txt", RND, flCmd_3, 3);
-- Write 4 bytes through MI32 Bus
MI32Write(X"00080000", -- address
X"01234567", -- data
"1111", -- byte enables
status);
wait for 5*clkper;
-- Read 4 bytes through MI32 Bus
MI32Read(X"00080000", -- address
mi32_data, -- output data
"1111", -- byte enables
status);
wait for 5*clkper;
-- Read 4 bytes through MI32 Bus
MI32Read(X"00080800", -- address
mi32_data, -- output data
"1111", -- byte enables
status);
wait for 5*clkper;
-- Read 4 bytes through MI32 Bus
MI32Read(X"00080804", -- address
mi32_data, -- output data
"1111", -- byte enables
status);
wait;
end process;
end architecture;
| bsd-3-clause | 3e369983ef404459044d6ba441c7ad86 | 0.527707 | 3.184551 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/openmac/src/openmacTop-rtl-ea.vhd | 1 | 68,936 | -------------------------------------------------------------------------------
--! @file openmacTop-rtl-ea.vhd
--
--! @brief OpenMAC toplevel file including openMAC, openHUB and openFILTER
--
--! @details This is the openMAC toplevel file including the MAC layer IP-Cores.
--! Additional components are provided for packet buffer storage.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
--! Work library
library work;
--! use openmac package
use work.openmacPkg.all;
entity openmacTop is
generic (
-----------------------------------------------------------------------
-- Phy configuration
-----------------------------------------------------------------------
--! Number of Phy ports
gPhyPortCount : natural := 2;
--! Phy port interface type (Rmii or Mii)
gPhyPortType : natural := cPhyPortRmii;
--! Number of SMI phy ports
gSmiPortCount : natural := 1;
-----------------------------------------------------------------------
-- General configuration
-----------------------------------------------------------------------
--! Endianness ("little" or "big")
gEndianness : string := "little";
--! Enable packet activity generator (e.g. connect to LED)
gEnableActivity : natural := cFalse;
--! Enable DMA observer circuit
gEnableDmaObserver : natural := cFalse;
-----------------------------------------------------------------------
-- DMA configuration
-----------------------------------------------------------------------
--! DMA address width (byte-addressing)
gDmaAddrWidth : natural := 32;
--! DMA data width
gDmaDataWidth : natural := 16;
--! DMA burst count width
gDmaBurstCountWidth : natural := 4;
--! DMA write burst length (Rx packets) [words]
gDmaWriteBurstLength : natural := 16;
--! DMA read burst length (Tx packets) [words]
gDmaReadBurstLength : natural := 16;
--! DMA write FIFO length (Rx packets) [words]
gDmaWriteFifoLength : natural := 16;
--! DMA read FIFO length (Tx packets) [words]
gDmaReadFifoLength : natural := 16;
-----------------------------------------------------------------------
-- Packet buffer configuration
-----------------------------------------------------------------------
--! Packet buffer location for Tx packets
gPacketBufferLocTx : natural := cPktBufLocal;
--! Packet buffer location for Rx packets
gPacketBufferLocRx : natural := cPktBufLocal;
--! Packet buffer log2(size) [log2(bytes)]
gPacketBufferLog2Size : natural := 10;
-----------------------------------------------------------------------
-- MAC timer configuration
-----------------------------------------------------------------------
--! Number of timers
gTimerCount : natural := 2;
--! Enable timer pulse width control
gTimerEnablePulseWidth : natural := cFalse;
--! Timer pulse width register width
gTimerPulseRegWidth : natural := 10
);
port (
-----------------------------------------------------------------------
-- Clock and reset signal pairs
-----------------------------------------------------------------------
--! Main clock used for openMAC, openHUB and openFILTER (freq = 50 MHz)
iClk : in std_logic;
--! Main reset used for openMAC, openHUB and openFILTER
iRst : in std_logic;
--! DMA master clock
iDmaClk : in std_logic;
--! DMA master reset
iDmaRst : in std_logic;
--! Packet buffer clock
iPktBufClk : in std_logic;
--! Packet buffer reset
iPktBufRst : in std_logic;
--! Twice main clock used for Rmii Tx path
iClk2x : in std_logic;
-----------------------------------------------------------------------
-- MAC REG memory mapped slave
-----------------------------------------------------------------------
--! MM slave MAC REGISTER chipselect
iMacReg_chipselect : in std_logic;
--! MM slave MAC REGISTER write
iMacReg_write : in std_logic;
--! MM slave MAC REGISTER read
iMacReg_read : in std_logic;
--! MM slave MAC REGISTER waitrequest
oMacReg_waitrequest : out std_logic;
--! MM slave MAC REGISTER byteenable
iMacReg_byteenable : in std_logic_vector(cMacRegDataWidth/cByteLength-1 downto 0);
--! MM slave MAC REGISTER address
iMacReg_address : in std_logic_vector(cMacRegAddrWidth-1 downto 0);
--! MM slave MAC REGISTER writedata
iMacReg_writedata : in std_logic_vector(cMacRegDataWidth-1 downto 0);
--! MM slave MAC REGISTER readdata
oMacReg_readdata : out std_logic_vector(cMacRegDataWidth-1 downto 0);
-----------------------------------------------------------------------
-- MAC TIMER memory mapped slave
-----------------------------------------------------------------------
--! MM slave MAC TIMER chipselect
iMacTimer_chipselect : in std_logic;
--! MM slave MAC TIMER write
iMacTimer_write : in std_logic;
--! MM slave MAC TIMER read
iMacTimer_read : in std_logic;
--! MM slave MAC TIMER waitrequest
oMacTimer_waitrequest : out std_logic;
--! MM slave MAC TIMER address
iMacTimer_address : in std_logic_vector(cMacTimerAddrWidth-1 downto 0);
--! MM slave MAC TIMER writedata
iMacTimer_writedata : in std_logic_vector(cMacTimerDataWidth-1 downto 0);
--! MM slave MAC TIMER readdata
oMacTimer_readdata : out std_logic_vector(cMacTimerDataWidth-1 downto 0);
-----------------------------------------------------------------------
-- MAC PACKET BUFFER memory mapped slave
-----------------------------------------------------------------------
--! MM slave MAC PACKET BUFFER chipselect
iPktBuf_chipselect : in std_logic;
--! MM slave MAC PACKET BUFFER write
iPktBuf_write : in std_logic;
--! MM slave MAC PACKET BUFFER read
iPktBuf_read : in std_logic;
--! MM slave MAC PACKET BUFFER waitrequest
oPktBuf_waitrequest : out std_logic;
--! MM slave MAC PACKET BUFFER byteenable
iPktBuf_byteenable : in std_logic_vector(cPktBufDataWidth/cByteLength-1 downto 0);
--! MM slave MAC PACKET BUFFER address (width given by gPacketBufferLog2Size)
iPktBuf_address : in std_logic_vector(gPacketBufferLog2Size-1 downto 0);
--! MM slave MAC PACKET BUFFER writedata
iPktBuf_writedata : in std_logic_vector(cPktBufDataWidth-1 downto 0);
--! MM slave MAC PACKET BUFFER readdata
oPktBuf_readdata : out std_logic_vector(cPktBufDataWidth-1 downto 0);
-----------------------------------------------------------------------
-- MAC DMA memory mapped master
-----------------------------------------------------------------------
--! MM master MAC DMA write
oDma_write : out std_logic;
--! MM master MAC DMA read
oDma_read : out std_logic;
--! MM master MAC DMA waitrequest
iDma_waitrequest : in std_logic;
--! MM master MAC DMA readdatavalid
iDma_readdatavalid : in std_logic;
--! MM master MAC DMA byteenable
oDma_byteenable : out std_logic_vector(gDmaDataWidth/cByteLength-1 downto 0);
--! MM master MAC DMA address
oDma_address : out std_logic_vector(gDmaAddrWidth-1 downto 0);
--! MM master MAC DMA burstcount
oDma_burstcount : out std_logic_vector(gDmaBurstCountWidth-1 downto 0);
--! MM master MAC DMA burstcounter (holds current burst count value)
oDma_burstcounter : out std_logic_vector(gDmaBurstCountWidth-1 downto 0);
--! MM master MAC DMA writedata
oDma_writedata : out std_logic_vector(gDmaDataWidth-1 downto 0);
--! MM master MAC DMA readdata
iDma_readdata : in std_logic_vector(gDmaDataWidth-1 downto 0);
-----------------------------------------------------------------------
-- Interrupts
-----------------------------------------------------------------------
--! MAC TIMER interrupt
oMacTimer_interrupt : out std_logic;
--! MAC Tx interrupt
oMacTx_interrupt : out std_logic;
--! MAC Rx interrupt
oMacRx_interrupt : out std_logic;
-----------------------------------------------------------------------
-- Rmii Phy ports
-----------------------------------------------------------------------
--! Rmii Rx ports
iRmii_Rx : in tRmiiPathArray(gPhyPortCount-1 downto 0);
--! Rmii Rx error ports
iRmii_RxError : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Rmii Tx ports
oRmii_Tx : out tRmiiPathArray(gPhyPortCount-1 downto 0);
-----------------------------------------------------------------------
-- Mii Phy ports
-----------------------------------------------------------------------
--! Mii Rx ports
iMii_Rx : in tMiiPathArray(gPhyPortCount-1 downto 0);
--! Mii Rx error ports
iMii_RxError : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Rx Clocks
iMii_RxClk : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Tx ports
oMii_Tx : out tMiiPathArray(gPhyPortCount-1 downto 0);
--! Mii Tx Clocks
iMii_TxClk : in std_logic_vector(gPhyPortCount-1 downto 0);
-----------------------------------------------------------------------
-- Phy management interface
-----------------------------------------------------------------------
--! Phy reset (low-active)
onPhy_reset : out std_logic_vector(gSmiPortCount-1 downto 0);
--! SMI clock
oSmi_clk : out std_logic_vector(gSmiPortCount-1 downto 0);
--! SMI data output enable (tri-state buffer)
oSmi_data_outEnable : out std_logic;
--! SMI data output (tri-state buffer)
oSmi_data_out : out std_logic_vector(gSmiPortCount-1 downto 0);
--! SMI data input (tri-state buffer)
iSmi_data_in : in std_logic_vector(gSmiPortCount-1 downto 0);
-----------------------------------------------------------------------
-- Other ports
-----------------------------------------------------------------------
--! Packet activity (enabled with gEnableActivity)
oActivity : out std_logic;
--! MAC TIMER outputs
oMacTimer : out std_logic_vector(gTimerCount-1 downto 0)
);
end openmacTop;
architecture rtl of openmacTop is
---------------------------------------------------------------------------
-- Constants
---------------------------------------------------------------------------
--! Lowest index of Phy port
constant cPhyPortLow : natural := cHubIntPort+1;
--! Highest index of Phy port
constant cPhyPortHigh : natural := gPhyPortCount+1;
--! Enable packet buffer interface
constant cEnablePacketBuffer : boolean := (
gPacketBufferLocRx = cPktBufLocal or gPacketBufferLocTx = cPktBufLocal
);
--! Enable dma interface
constant cEnableDma : boolean := (
gPacketBufferLocRx = cPktBufExtern or gPacketBufferLocTx = cPktBufExtern
);
--! Fixed openMAC DMA address width
constant cDmaAddrWidth : natural := 32;
---------------------------------------------------------------------------
-- Component types
---------------------------------------------------------------------------
--! openMAC port type
type tOpenMacPort is record
rst : std_logic;
clk : std_logic;
nReg_write : std_logic;
reg_selectRam : std_logic;
reg_selectCont : std_logic;
nReg_byteenable : std_logic_vector(1 downto 0);
reg_address : std_logic_vector(10 downto 1);
reg_writedata : std_logic_vector(15 downto 0);
reg_readdata : std_logic_vector(15 downto 0);
nTxInterrupt : std_logic;
nRxInterrupt : std_logic;
dma_readDone : std_logic;
dma_writeDone : std_logic;
dma_request : std_logic;
nDma_write : std_logic;
dma_acknowledge : std_logic;
dma_requestOverflow : std_logic;
dma_readLength : std_logic_vector(11 downto 0);
dma_address : std_logic_vector(cDmaAddrWidth-1 downto 1);
dma_writedata : std_logic_vector(15 downto 0);
dma_readdata : std_logic_vector(15 downto 0);
rmii : tRmii;
hubRxPort : std_logic_vector(1 downto 0);
macTime : std_logic_vector(cMacTimeWidth-1 downto 0);
end record;
--! Phy management port type
type tPhyMgmtPort is record
rst : std_logic;
clk : std_logic;
address : std_logic_vector(3 downto 1);
chipselect : std_logic;
nByteenable : std_logic_vector(1 downto 0);
nWrite : std_logic;
writedata : std_logic_vector(15 downto 0);
readdata : std_logic_vector(15 downto 0);
smiClk : std_logic;
smiDataIn : std_logic;
smiDataOut : std_logic;
smiDataOutEnable : std_logic;
nPhyReset : std_logic;
end record;
--! openMAC TIMER port type
type tOpenMacTimerPort is record
rst : std_logic;
clk : std_logic;
write : std_logic;
address : std_logic_vector(3 downto 2);
writedata : std_logic_vector(31 downto 0);
readdata : std_logic_vector(31 downto 0);
macTime : std_logic_vector(cMacTimeWidth-1 downto 0);
interrupt : std_logic;
toggle : std_logic;
end record;
--! openHUB port type
type tOpenHubPort is record
rst : std_logic;
clk : std_logic;
rx : tRmiiPathArray(cPhyPortHigh downto cHubIntPort);
tx : tRmiiPathArray(cPhyPortHigh downto cHubIntPort);
internPort : integer range cHubIntPort to cPhyPortHigh;
transmitMask : std_logic_vector(cPhyPortHigh downto cHubIntPort);
receivePort : integer range 0 to cPhyPortHigh;
end record;
--! openFILTER port type
type tOpenFilterPort is record
rst : std_logic;
clk : std_logic;
rxIn : tRmiiPathArray(cPhyPortHigh downto cPhyPortLow);
rxOut : tRmiiPathArray(cPhyPortHigh downto cPhyPortLow);
txIn : tRmiiPathArray(cPhyPortHigh downto cPhyPortLow);
txOut : tRmiiPathArray(cPhyPortHigh downto cPhyPortLow);
rxError : std_logic_vector(cPhyPortHigh downto cPhyPortLow);
end record;
--! RMII-to-MII converter port type
type tConvRmiiToMiiPort is record
rst : std_logic;
clk : std_logic;
rmiiTx : tRmiiPathArray(cPhyPortHigh downto cPhyPortLow);
rmiiRx : tRmiiPathArray(cPhyPortHigh downto cPhyPortLow);
miiTx : tMiiPathArray(cPhyPortHigh downto cPhyPortLow);
miiTxClk : std_logic_vector(cPhyPortHigh downto cPhyPortLow);
miiRx : tMiiPathArray(cPhyPortHigh downto cPhyPortLow);
miiRxError : std_logic_vector(cPhyPortHigh downto cPhyPortLow);
miiRxClk : std_logic_vector(cPhyPortHigh downto cPhyPortLow);
end record;
--! Packet Buffer single port type
type tPacketBufferSinglePort is record
clk : std_logic;
rst : std_logic;
enable : std_logic;
write : std_logic;
address : std_logic_vector(gPacketBufferLog2Size-1 downto logDualis(cPktBufDataWidth/cByteLength));
byteenable : std_logic_vector(cPktBufDataWidth/cByteLength-1 downto 0);
writedata : std_logic_vector(cPktBufDataWidth-1 downto 0);
readdata : std_logic_vector(cPktBufDataWidth-1 downto 0);
end record;
--! Packet Buffer dual port type (port to DMA and host)
type tPacketBufferPort is record
dma : tPacketBufferSinglePort;
dma_ack : std_logic;
dma_highWordSel : std_logic;
host : tPacketBufferSinglePort;
end record;
--! DMA port type
type tDmaMaster_dmaPort is record
clk : std_logic;
rst : std_logic; --FIXME: Rename in openMAC_DMAmaster
reqWrite : std_logic;
reqRead : std_logic;
reqOverflow : std_logic;
ackWrite : std_logic;
ackRead : std_logic;
readError : std_logic;
readLength : std_logic_vector(11 downto 0);
writeError : std_logic;
address : std_logic_vector(gDmaAddrWidth-1 downto 1);
writedata : std_logic_vector(15 downto 0);
readdata : std_logic_vector(15 downto 0);
end record;
--! Master port type
type tDmaMaster_masterPort is record
clk : std_logic;
rst : std_logic; --FIXME: Add to openMAC_DMAmaster
write : std_logic;
read : std_logic;
readdatavalid : std_logic;
waitrequest : std_logic;
address : std_logic_vector(gDmaAddrWidth-1 downto 0);
byteenable : std_logic_vector(gDmaDataWidth/cByteLength-1 downto 0);
burstcount : std_logic_vector(gDmaBurstCountWidth-1 downto 0);
burstcounter : std_logic_vector(gDmaBurstCountWidth-1 downto 0);
writedata : std_logic_vector(gDmaDataWidth-1 downto 0);
readdata : std_logic_vector(gDmaDataWidth-1 downto 0);
end record;
--! DMA Master port type
type tDmaMasterPort is record
dma : tDmaMaster_dmaPort;
master : tDmaMaster_masterPort;
mac_rxOff : std_logic;
mac_txOff : std_logic;
end record;
--! Activity port type
type tActivityPort is record
clk : std_logic;
rst : std_logic;
txEnable : std_logic;
rxDataValid : std_logic;
activity : std_logic;
end record;
---------------------------------------------------------------------------
-- Configuration
---------------------------------------------------------------------------
-- MAC TIMER
--! Function to convert number of timers into generate boolean for
--! second timer.
function macTimer_gen2ndTimer (timerCnt : natural) return boolean is
variable vRet_tmp : boolean;
begin
--default
vRet_tmp := FALSE;
case timerCnt is
when 1 =>
vRet_tmp := FALSE;
when 2 =>
vRet_tmp := TRUE;
when others =>
assert (FALSE)
report "The MAC TIMER only supports 1 and 2 timers!"
severity failure;
end case;
return vRet_tmp;
end function macTimer_gen2ndTimer;
--! MAC Timer generate second compare timer
constant cMacTimer_2ndTimer : boolean := macTimer_gen2ndTimer(gTimerCount);
---------------------------------------------------------------------------
-- Memory map
---------------------------------------------------------------------------
--! Select vector for MacReg
signal selVector_macReg : std_logic_vector(cMemMapCount-1 downto 0);
--! Alias for select DMA Error
alias sel_dmaError : std_logic is selVector_macReg(cMemMapIndex_dmaError);
--! Alias for select IRQ Table
alias sel_irqTable : std_logic is selVector_macReg(cMemMapIndex_irqTable);
--! Alias for select SMI
alias sel_smi : std_logic is selVector_macReg(cMemMapIndex_smi);
--! Alias for select MAC RAM
alias sel_macRam : std_logic is selVector_macReg(cMemMapIndex_macRam);
--! Alias for select MAC Filter
alias sel_macFilter : std_logic is selVector_macReg(cMemMapIndex_macFilter);
--! Alias for select MAC Content
alias sel_macCont : std_logic is selVector_macReg(cMemMapIndex_macCont);
--! Acknowledge vector for MacReg
signal ackVector : tMemAccessAckArray(cMemAccessDelayCount-1 downto 0);
--! Alias for acknowledge PKT BUF
alias ack_pktBuf : tMemAccessAck is ackVector(cMemAccessDelayIndex_pktBuf);
--! Alias for acknowledge MAC TIMER
alias ack_macTimer : tMemAccessAck is ackVector(cMemAccessDelayIndex_macTimer);
--! Alias for acknowledge MAC REG
alias ack_macReg : tMemAccessAck is ackVector(cMemAccessDelayIndex_macReg);
---------------------------------------------------------------------------
-- Interrupt signals
---------------------------------------------------------------------------
--! Interrupt table vector
signal irqTable : tMacRegIrqTable;
---------------------------------------------------------------------------
-- DMA error signals
---------------------------------------------------------------------------
--! DMA error table
signal dmaErrorTable : tMacDmaErrorTable;
---------------------------------------------------------------------------
-- RMII registers for latching input and output path (improves timing)
---------------------------------------------------------------------------
--! Rmii Rx paths
signal rmiiRxPath_reg : tRmiiPathArray(gPhyPortCount-1 downto 0)
:= (others => cRmiiPathInit); -- avoid warnings
--! Rmii Rx error paths
signal rmiiRxPathError_reg : std_logic_vector(gPhyPortCount-1 downto 0)
:= (others => cInactivated); -- avoid warnings
--! Rmii Tx paths
signal rmiiTxPath_reg : tRmiiPathArray(gPhyPortCount-1 downto 0)
:= (others => cRmiiPathInit); -- avoid warnings
---------------------------------------------------------------------------
-- MII signals
---------------------------------------------------------------------------
--! Mii Tx paths
signal miiTxPath : tMiiPathArray(gPhyPortCount-1 downto 0);
---------------------------------------------------------------------------
-- Instances
---------------------------------------------------------------------------
--! Instance openMAC port
signal inst_openmac : tOpenMacPort;
--! Instance phy management port
signal inst_phyMgmt : tPhyMgmtPort;
--! Instance openMAC TIMER port
signal inst_openmacTimer : tOpenMacTimerPort;
--! Instance openHUB port
signal inst_openhub : tOpenHubPort;
--! Instances openFILTER port
signal inst_openfilter : tOpenFilterPort;
--! Instances RMII-to-MII converter port
signal inst_convRmiiToMii : tConvRmiiToMiiPort;
--! Instance Packet buffer port
signal inst_pktBuffer : tPacketBufferPort;
--! Instance DMA master port
signal inst_dmaMaster : tDmaMasterPort;
--! Instance activity port
signal inst_activity : tActivityPort;
begin
---------------------------------------------------------------------------
-- Assign toplevel
---------------------------------------------------------------------------
--! In this block the entity's output ports are assigned to internals.
TOPLEVELMAP : block
begin
--! This process assigns the oMacReg_readdata port to the selected
--! memory.
ASSIGN_MACREG_RDDATA : process (
selVector_macReg,
irqTable,
dmaErrorTable,
iMacReg_byteenable,
inst_openmac.reg_readdata,
inst_phyMgmt.readdata
)
begin
--default assignment
oMacReg_readdata <= (others => cInactivated);
if sel_macRam = cActivated or sel_macCont = cActivated then
oMacReg_readdata <= inst_openmac.reg_readdata;
-- swap bytes if big endian and selected word
if gEndianness = "big" and iMacReg_byteenable = "11" then
oMacReg_readdata <= byteSwap(inst_openmac.reg_readdata);
end if;
elsif sel_smi = cActivated then
oMacReg_readdata <= inst_phyMgmt.readdata;
-- swap bytes if big endian and selected word
if gEndianness = "big" and iMacReg_byteenable = "11" then
oMacReg_readdata <= byteSwap(inst_phyMgmt.readdata);
end if;
elsif sel_irqTable = cActivated then
oMacReg_readdata <= irqTable;
-- swap bytes if big endian
if gEndianness = "big" then
oMacReg_readdata <= byteSwap(irqTable);
end if;
elsif sel_dmaError = cActivated then
oMacReg_readdata <= dmaErrorTable;
-- swap byte if big endian
if gEndianness = "big" then
oMacReg_readdata <= byteSwap(dmaErrorTable);
end if;
end if;
end process ASSIGN_MACREG_RDDATA;
oMacReg_waitrequest <= not(ack_macReg.write or ack_macReg.read);
oMacTimer_readdata <= inst_openmacTimer.readdata;
oMacTimer_waitrequest <= not(ack_macTimer.write or ack_macTimer.read);
oPktBuf_readdata <= inst_pktBuffer.host.readdata when cEnablePacketBuffer else
(others => cInactivated);
oPktBuf_waitrequest <= not(ack_pktBuf.write or ack_pktBuf.read) when cEnablePacketBuffer else
cActivated;
oDma_address <= inst_dmaMaster.master.address when cEnableDma else
(others => cInactivated);
oDma_burstcount <= inst_dmaMaster.master.burstcount when cEnableDma else
(others => cInactivated);
oDma_burstcounter <= inst_dmaMaster.master.burstcounter when cEnableDma else
(others => cInactivated);
oDma_byteenable <= inst_dmaMaster.master.byteenable when cEnableDma else
(others => cInactivated);
oDma_read <= inst_dmaMaster.master.read when cEnableDma else
cInactivated;
oDma_write <= inst_dmaMaster.master.write when cEnableDma else
cInactivated;
oDma_writedata <= inst_dmaMaster.master.writedata when cEnableDma else
(others => cInactivated);
oMacTimer_interrupt <= inst_openmacTimer.interrupt;
oMacTx_interrupt <= not inst_openmac.nTxInterrupt;
oMacRx_interrupt <= not inst_openmac.nRxInterrupt;
oRmii_Tx <= rmiiTxPath_reg when gPhyPortType = cPhyPortRmii else
(others => cRmiiPathInit);
oMii_Tx <= miiTxPath when gPhyPortType = cPhyPortMii else
(others => cMiiPathInit);
oSmi_clk <= (others => inst_phyMgmt.smiClk);
oSmi_data_out <= (others => inst_phyMgmt.smiDataOut);
oSmi_data_outEnable <= inst_phyMgmt.smiDataOutEnable;
onPhy_reset <= (others => inst_phyMgmt.nPhyReset);
oActivity <= inst_activity.activity when gEnableActivity = cTrue else
cInactivated;
ASSIGNMACTIMER : process (
inst_openmacTimer
)
begin
for i in oMacTimer'range loop
if i = 0 then
oMacTimer(i) <= inst_openmacTimer.interrupt;
elsif i = 1 then
oMacTimer(i) <= inst_openmacTimer.toggle;
else
-- unsupported timer assigned to zero
oMacTimer(i) <= cInactivated;
end if;
end loop;
end process ASSIGNMACTIMER;
end block TOPLEVELMAP;
---------------------------------------------------------------------------
-- Assign instances
---------------------------------------------------------------------------
--! In this block the instances are assigned.
INSTANCEMAP : block
begin
-----------------------------------------------------------------------
-- The openMAC
-----------------------------------------------------------------------
inst_openmac.rst <= iRst;
inst_openmac.clk <= iClk;
inst_openmac.nReg_write <= not iMacReg_write;
inst_openmac.reg_selectRam <= sel_macRam;
inst_openmac.reg_selectCont <= sel_macCont;
inst_openmac.nReg_byteenable <= not iMacReg_byteenable;
inst_openmac.reg_address <= iMacReg_address(inst_openmac.reg_address'range);
--! This process assignes the register writedata. Additionally the DMA
--! read path and the request acknowlegde signals are assigned from the
--! configured sources (packet buffer vs. DMA).
ASSIGN_MAC : process (
iMacReg_writedata,
iMacReg_byteenable,
inst_pktBuffer,
inst_dmaMaster
)
--! DMA ack variable for or'ing all those acks.
variable vAck_tmp : std_logic;
--! Alias for packet buffer high word
alias pktBufRead_high : std_logic_vector(15 downto 0) is
inst_pktBuffer.dma.readdata(cPktBufDataWidth-1 downto cPktBufDataWidth/2);
--! Alias for packet buffer low word
alias pktBufRead_low : std_logic_vector(15 downto 0) is
inst_pktBuffer.dma.readdata(cPktBufDataWidth/2-1 downto 0);
begin
-- no defaults, so take care!
-------------------------------------------------------------------
-- writedata is directly assigned, or byte-swapped
inst_openmac.reg_writedata <= iMacReg_writedata;
-- swap bytes if big endian and selected word
if gEndianness = "big" and iMacReg_byteenable = "11" then
inst_openmac.reg_writedata <= byteSwap(iMacReg_writedata);
end if;
-------------------------------------------------------------------
-------------------------------------------------------------------
-- Initialize the ack variable to zero, then or it with all sources.
vAck_tmp := cInactivated;
-- Assign read acknowledge.
case gPacketBufferLocTx is
when cPktBufExtern =>
-- Tx packets come from DMA master
vAck_tmp := vAck_tmp or inst_dmaMaster.dma.ackRead;
when cPktBufLocal =>
-- Tx packets come from packet buffer
vAck_tmp := vAck_tmp or inst_pktBuffer.dma_ack;
when others =>
assert (FALSE)
report "The Tx packet buffer location is unknown! Don't know how to ack!"
severity failure;
end case;
-- Assign write acknowledge.
case gPacketBufferLocRx is
when cPktBufExtern =>
-- Rx packets go to DMA master
vAck_tmp := vAck_tmp or inst_dmaMaster.dma.ackWrite;
when cPktBufLocal =>
-- Rx packets go to packet buffer
vAck_tmp := vAck_tmp or inst_pktBuffer.dma_ack;
when others =>
assert (FALSE)
report "The Rx packet buffer location is unknown! Don't know how to ack!"
severity failure;
end case;
-- Assign the variable state to the signal.
inst_openmac.dma_acknowledge <= vAck_tmp;
-------------------------------------------------------------------
-------------------------------------------------------------------
-- Decide on the readdata source for the DMA.
case gPacketBufferLocTx is
when cPktBufExtern =>
-- Tx packet come from DMA master
inst_openmac.dma_readdata <= inst_dmaMaster.dma.readdata;
when cPktBufLocal =>
-- Tx packets come from packet buffer, but select the right word
if inst_pktBuffer.dma_highWordSel = cActivated then
inst_openmac.dma_readdata <= pktBufRead_high;
else
inst_openmac.dma_readdata <= pktBufRead_low;
end if;
when others =>
assert (FALSE)
report "The Tx packet buffer location is unknown! Don't know the source!"
severity failure;
end case;
end process ASSIGN_MAC;
-- Note that internal port is crossed!
inst_openmac.rmii.rx <= inst_openhub.tx(cHubIntPort);
-- Clip the hub receive port to two bits
inst_openmac.hubRxPort <= std_logic_vector(
resize(
to_unsigned(inst_openhub.receivePort, logDualis(cPhyPortHigh)),
inst_openmac.hubRxPort'length)
);
-- Assign interrupts to irq Table
irqTable <= (
cMacRegIrqTable_macRx => not inst_openmac.nRxInterrupt,
cMacRegIrqTable_macTx => not inst_openmac.nTxInterrupt,
others => cInactivated
);
-----------------------------------------------------------------------
-- The phy management
-----------------------------------------------------------------------
inst_phyMgmt.clk <= iClk;
inst_phyMgmt.rst <= iRst;
inst_phyMgmt.address <= iMacReg_address(inst_phyMgmt.address'range);
inst_phyMgmt.chipselect <= sel_smi;
inst_phyMgmt.nByteenable <= not iMacReg_byteenable;
inst_phyMgmt.nWrite <= not iMacReg_write;
inst_phyMgmt.writedata <= iMacReg_writedata when gEndianness = "little" else
iMacReg_writedata when gEndianness = "big" and iMacReg_byteenable /= "11" else
byteSwap(iMacReg_writedata);
inst_phyMgmt.smiDataIn <= reduceAnd(iSmi_data_in);
-----------------------------------------------------------------------
-- The openMAC timer
-----------------------------------------------------------------------
inst_openmacTimer.clk <= iClk;
inst_openmacTimer.rst <= iRst;
inst_openmacTimer.write <= iMacTimer_write and iMacTimer_chipselect;
inst_openmacTimer.address <= iMacTimer_address(inst_openmacTimer.address'range);
inst_openmacTimer.writedata <= iMacTimer_writedata;
-- this is the mac time
inst_openmacTimer.macTime <= inst_openmac.macTime;
-----------------------------------------------------------------------
-- The openHUB
-----------------------------------------------------------------------
inst_openhub.rst <= iRst;
inst_openhub.clk <= iClk;
inst_openhub.internPort <= cHubIntPort;
-- Enable all ports
inst_openhub.transmitMask <= (others => cActivated);
--! This process simply assigns the hub ports.
ASSIGN_HUB : process (
inst_openmac.rmii.tx,
inst_openfilter
)
begin
-- no defaults, so take care!
-- Loop through phy ports and internal hub port (MAC).
for i in cPhyPortHigh downto cHubIntPort loop
-- Assign internal port to mac, others to filter.
if i = cHubIntPort then
-- Note that internal port is crossed!
inst_openhub.rx(i) <= inst_openmac.rmii.tx;
else
inst_openhub.rx(i) <= inst_openfilter.rxOut(i);
end if;
end loop;
end process ASSIGN_HUB;
-----------------------------------------------------------------------
-- The openFILTER(s)
-----------------------------------------------------------------------
inst_openfilter.rst <= iRst;
inst_openfilter.clk <= iClk;
--! This process assigns the phy ports to the generated filters.
ASSIGN_FILTERS : process (
inst_convRmiiToMii,
inst_openhub,
rmiiRxPath_reg,
rmiiRxPathError_reg
)
begin
-- no defaults, so take care!
-- Loop through phy ports only (internal hub port is skipped).
for i in cPhyPortHigh downto cPhyPortLow loop
-- assign from phy or RMII-to-MII converter
case gPhyPortType is
when cPhyPortRmii =>
inst_openfilter.rxIn(i) <= rmiiRxPath_reg(i-(cPhyPortLow));
inst_openfilter.rxError(i) <= rmiiRxPathError_reg(i-(cPhyPortLow));
when cPhyPortMii =>
inst_openfilter.rxIn(i) <= inst_convRmiiToMii.rmiiRx(i);
-- Filter Rx error is always zero, since converter already dumps packets!
inst_openfilter.rxError(i) <= cInactivated;
when others =>
assert (FALSE)
report "Wrong phy port type in ASSIGN_FILTERS!"
severity failure;
end case;
-- assign from hub
inst_openfilter.txIn(i) <= inst_openhub.tx(i);
end loop;
end process ASSIGN_FILTERS;
-----------------------------------------------------------------------
-- The RMII-to-MII converter(s)
-----------------------------------------------------------------------
inst_convRmiiToMii.clk <= iClk;
inst_convRmiiToMii.rst <= iRst;
inst_convRmiiToMii.rmiiTx <= inst_openfilter.txOut;
inst_convRmiiToMii.miiRx <= iMii_Rx;
inst_convRmiiToMii.miiRxError <= iMii_RxError;
inst_convRmiiToMii.miiRxClk <= iMii_RxClk;
inst_convRmiiToMii.miiTxClk <= iMii_TxClk;
-----------------------------------------------------------------------
-- The PACKET BUFFER
-----------------------------------------------------------------------
-- Assign DMA port side
inst_pktBuffer.dma.clk <= inst_openmac.clk;
inst_pktBuffer.dma.rst <= inst_openmac.rst;
inst_pktBuffer.dma.enable <= cActivated;
-- Note: DMA has data width of 16 bit and Packet Buffer DPRAM hsa 32 bit.
-- => Conversion necessary!
assert ((cPktBufDataWidth = 32) and (inst_openmac.dma_writedata'length = 16))
report "Revise DMA to packet store path. Implementation is fixed to 32/16!"
severity failure;
--! This process assigns the openMAC DMA ports to the packet buffer.
ASSIGN_DMAPORT : process (
inst_openmac
)
--! This variable is assigned to the DMA's word address
variable vDmaAddrWord_tmp : std_logic_vector(inst_openmac.dma_address'range);
--! This variable is assigned to the DMA's dword address
variable vDmaAddrDword_tmp : std_logic_vector(vDmaAddrWord_tmp'left downto 2);
begin
-- no defaults, so take care!
-- Assign DMA address to variables
vDmaAddrWord_tmp := inst_openmac.dma_address;
vDmaAddrDword_tmp := vDmaAddrWord_tmp(vDmaAddrDword_tmp'range); -- only assigned LEFT downto 2
-- Packet buffer address is for 32 bit (dwords)
inst_pktBuffer.dma.address <= std_logic_vector(resize(
unsigned(vDmaAddrDword_tmp),
inst_pktBuffer.dma.address'length)
);
-- DMA writes words, so duplicate words to packet buffer
inst_pktBuffer.dma.writedata <= inst_openmac.dma_writedata & inst_openmac.dma_writedata;
-- Packet buffer write strobe is logically and'd of request and write
-- Also the packet location is considered!
if (inst_openmac.dma_request = cActivated and
inst_openmac.nDma_write = cnActivated and
gPacketBufferLocRx = cPktBufLocal) then
inst_pktBuffer.dma.write <= cActivated;
else
inst_pktBuffer.dma.write <= cInactivated;
end if;
-- Duplicated words are present at writeport, select DMA's word addr bit
if vDmaAddrWord_tmp(vDmaAddrWord_tmp'right) = cActivated then
-- select high word
inst_pktBuffer.dma.byteenable <= "1100";
else
-- select low word
inst_pktBuffer.dma.byteenable <= "0011";
end if;
end process ASSIGN_DMAPORT;
-- Assign Host port side
inst_pktBuffer.host.clk <= iPktBufClk;
inst_pktBuffer.host.rst <= iPktBufRst;
inst_pktBuffer.host.enable <= cActivated;
inst_pktBuffer.host.write <= iPktBuf_chipselect and iPktBuf_write;
inst_pktBuffer.host.byteenable <= iPktBuf_byteenable;
inst_pktBuffer.host.address <= iPktBuf_address(inst_pktBuffer.host.address'range);
inst_pktBuffer.host.writedata <= iPktBuf_writedata;
-----------------------------------------------------------------------
-- The DMA master
-----------------------------------------------------------------------
inst_dmaMaster.dma.clk <= inst_openmac.clk;
inst_dmaMaster.dma.rst <= inst_openmac.rst;
inst_dmaMaster.dma.reqWrite <= inst_openmac.dma_request and not inst_openmac.nDma_write;
inst_dmaMaster.dma.reqRead <= inst_openmac.dma_request and inst_openmac.nDma_write;
inst_dmaMaster.dma.reqOverflow <= inst_openmac.dma_requestOverflow;
inst_dmaMaster.dma.readLength <= inst_openmac.dma_readLength;
inst_dmaMaster.dma.address <= std_logic_vector(resize(
unsigned(inst_openmac.dma_address),
inst_dmaMaster.dma.address'length)
);
inst_dmaMaster.dma.writedata <= inst_openmac.dma_writedata;
inst_dmaMaster.master.clk <= iDmaClk;
inst_dmaMaster.master.rst <= iDmaRst;
inst_dmaMaster.master.readdatavalid <= iDma_readdatavalid;
inst_dmaMaster.master.waitrequest <= iDma_waitrequest;
inst_dmaMaster.master.readdata <= iDma_readdata;
inst_dmaMaster.mac_rxOff <= inst_openmac.dma_writeDone;
inst_dmaMaster.mac_txOff <= inst_openmac.dma_readDone;
-- Assign DMA error table
dmaErrorTable <= (
cMacDmaErrorTable_read => inst_dmaMaster.dma.readError,
cMacDmaErrorTable_write => inst_dmaMaster.dma.writeError,
others => cInactivated
);
-----------------------------------------------------------------------
-- The activity generator
-----------------------------------------------------------------------
inst_activity.clk <= inst_openmac.clk;
inst_activity.rst <= inst_openmac.rst;
inst_activity.rxDataValid <= inst_openmac.rmii.rx.enable;
inst_activity.txEnable <= inst_openmac.rmii.tx.enable;
end block INSTANCEMAP;
---------------------------------------------------------------------------
-- Component instatiations
---------------------------------------------------------------------------
--! The openMAC core instance implements the MAC-layer.
--! All features are enabled to provide time-triggered packet Tx and
--! dynamic response delay.
THEOPENMAC : entity work.openmac
generic map (
gDmaHighAddr => cDmaAddrWidth-1,
gTimerEnable => TRUE,
gTimerTrigTx => TRUE,
gAutoTxDel => TRUE
)
port map (
iRst => inst_openmac.rst,
iClk => inst_openmac.clk,
inWrite => inst_openmac.nReg_write,
iSelectRam => inst_openmac.reg_selectRam,
iSelectCont => inst_openmac.reg_selectCont,
inByteenable => inst_openmac.nReg_byteenable,
iAddress => inst_openmac.reg_address,
iWritedata => inst_openmac.reg_writedata,
oReaddata => inst_openmac.reg_readdata,
onTxIrq => inst_openmac.nTxInterrupt,
onRxIrq => inst_openmac.nRxInterrupt,
onTxBegIrq => open, --unused interrupt
oDmaReadDone => inst_openmac.dma_readDone,
oDmaWriteDone => inst_openmac.dma_writeDone,
oDmaReq => inst_openmac.dma_request,
onDmaWrite => inst_openmac.nDma_write,
iDmaAck => inst_openmac.dma_acknowledge,
oDmaReqOverflow => inst_openmac.dma_requestOverflow,
oDmaReadLength => inst_openmac.dma_readLength,
oDmaAddress => inst_openmac.dma_address,
oDmaWritedata => inst_openmac.dma_writedata,
iDmaReaddata => inst_openmac.dma_readdata,
iRxData => inst_openmac.rmii.rx.data,
iRxDv => inst_openmac.rmii.rx.enable,
oTxData => inst_openmac.rmii.tx.data,
oTxEn => inst_openmac.rmii.tx.enable,
iHubRxPort => inst_openmac.hubRxPort,
oMacTime => inst_openmac.macTime
);
--! The phy management core is an SMI master to communication with the
--! phys.
THEPHYMGMT : entity work.phyMgmt
port map (
iRst => inst_phyMgmt.rst,
iClk => inst_phyMgmt.clk,
iAddress => inst_phyMgmt.address,
iSelect => inst_phyMgmt.chipselect,
inByteenable => inst_phyMgmt.nByteenable,
inWrite => inst_phyMgmt.nWrite,
iWritedata => inst_phyMgmt.writedata,
oReaddata => inst_phyMgmt.readdata,
oSmiClk => inst_phyMgmt.smiClk,
iSmiDataIn => inst_phyMgmt.smiDataIn,
oSmiDataOut => inst_phyMgmt.smiDataOut,
oSmiDataOutEnable => inst_phyMgmt.smiDataOutEnable,
onPhyReset => inst_phyMgmt.nPhyReset
);
--! The openMAC timer instance provides hardware timers referencing to the
--! openMAC's MAC Time (Mac_Zeit).
THEOPENMACTIMER : entity work.openmacTimer
generic map (
gMacTimeWidth => cMacTimeWidth,
gMacTimer_2ndTimer => cMacTimer_2ndTimer,
gTimerPulseRegWidth => gTimerPulseRegWidth,
gTimerEnablePulseWidth => (gTimerEnablePulseWidth /= cFalse)
)
port map (
iRst => inst_openmacTimer.rst,
iClk => inst_openmacTimer.clk,
iWrite => inst_openmacTimer.write,
iAddress => inst_openmacTimer.address,
iWritedata => inst_openmacTimer.writedata,
oReaddata => inst_openmacTimer.readdata,
iMacTime => inst_openmacTimer.macTime,
oIrq => inst_openmacTimer.interrupt,
oToggle => inst_openmacTimer.toggle
);
---------------------------------------------------------------------------
-- Conditional component instatiations
---------------------------------------------------------------------------
--! Generate address decoders for MAC REG memory map.
GENMACREG_ADDRDEC : for i in cMemMapTable'range generate
THEADDRDEC : entity libcommon.addrDecode
generic map (
gAddrWidth => iMacReg_address'length,
gBaseAddr => cMemMapTable(i).base,
gHighAddr => cMemMapTable(i).high
)
port map (
iEnable => iMacReg_chipselect,
iAddress => iMacReg_address,
oSelect => selVector_macReg(i)
);
end generate GENMACREG_ADDRDEC;
--! Generate write/read acknowlegde for MAC REG, MAC TIMER and PKT BUFFER.
GENMACREG_ACK : for i in cMemAccessDelayTable'range generate
signal selAndWrite : std_logic;
signal selAndRead : std_logic;
signal ackRst : std_logic;
signal ackClk : std_logic;
begin
--! Assign the corresponding clock and reset signals.
ASSIGN_CLKRST : process (
iClk,
iPktBufClk,
iRst,
iPktBufRst
)
begin
-- no defaults, so take care!
case i is
when cMemAccessDelayIndex_pktBuf =>
ackClk <= iPktBufClk;
ackRst <= iPktBufRst;
when cMemAccessDelayIndex_macTimer =>
ackClk <= iClk;
ackRst <= iRst;
when cMemAccessDelayIndex_macReg =>
ackClk <= iClk;
ackRst <= iRst;
when others =>
assert (FALSE)
report "Unknown access delay index. Don't know which ackClk/ackRst to use!"
severity failure;
end case;
end process ASSIGN_CLKRST;
--! This process assigns the selAndWrite and selAndRead signals used
--! to enable the acknowledge generators.
ASSIGN_SELANDRW : process (
iPktBuf_chipselect,
iPktBuf_write,
iPktBuf_read,
iMacTimer_chipselect,
iMacTimer_write,
iMacTimer_read,
iMacReg_chipselect,
iMacReg_write,
iMacReg_read
)
begin
--default
selAndWrite <= cInactivated;
selAndRead <= cInactivated;
case i is
when cMemAccessDelayIndex_pktBuf =>
selAndWrite <= iPktBuf_chipselect and iPktBuf_write;
selAndRead <= iPktBuf_chipselect and iPktBuf_read;
when cMemAccessDelayIndex_macTimer =>
selAndWrite <= iMacTimer_chipselect and iMacTimer_write;
selAndRead <= iMacTimer_chipselect and iMacTimer_read;
when cMemAccessDelayIndex_macReg =>
selAndWrite <= iMacReg_chipselect and iMacReg_write;
selAndRead <= iMacReg_chipselect and iMacReg_read;
when others =>
assert (FALSE)
report "For generate overrun! Check cMemAccessDelayTable!"
severity failure;
end case;
end process ASSIGN_SELANDRW;
--! Generate ack delay for writes.
GENWR_ACKDELAY : if cMemAccessDelayTable(i).write > 0 generate
THE_CNT : entity libcommon.cnt
generic map (
gCntWidth => logDualis(cMemAccessDelayTable(i).write + 1),
gTcntVal => cMemAccessDelayTable(i).write
)
port map (
iArst => ackRst,
iClk => ackClk,
iEnable => selAndWrite,
iSrst => cInactivated,
oCnt => open,
oTcnt => ackVector(i).write
);
end generate GENWR_ACKDELAY;
--! Generate no ack delay for writes.
GENWR_NOACKDELAY : if cMemAccessDelayTable(i).write = 0 generate
ackVector(i).write <= selAndWrite;
end generate GENWR_NOACKDELAY;
--! Generate ack delay for reads.
GENRD_ACKDELAY : if cMemAccessDelayTable(i).read > 0 generate
THE_CNT : entity libcommon.cnt
generic map (
gCntWidth => logDualis(cMemAccessDelayTable(i).read + 1),
gTcntVal => cMemAccessDelayTable(i).read
)
port map (
iArst => ackRst,
iClk => ackClk,
iEnable => selAndRead,
iSrst => cInactivated,
oCnt => open,
oTcnt => ackVector(i).read
);
end generate GENRD_ACKDELAY;
--! generate no ack delay for reads.
GENRD_NOACKDELAY : if cMemAccessDelayTable(i).read = 0 generate
ackVector(i).read <= selAndRead;
end generate GENRD_NOACKDELAY;
end generate GENMACREG_ACK;
--! The openHUB instance is only needed if more than one phy port is
--! configured.
GEN_HUB : if gPhyPortCount > 1 generate
THEOPENHUB : entity work.openhub
generic map (
gPortCount => gPhyPortCount+1 -- plus MAC port
)
port map (
iRst => inst_openhub.rst,
iClk => inst_openhub.clk,
iRx => inst_openhub.rx,
oTx => inst_openhub.tx,
iIntPort => inst_openhub.internPort,
iTxMask => inst_openhub.transmitMask,
oRxPort => inst_openhub.receivePort
);
end generate GEN_HUB;
--! In case of HUB bypass assign inst_openhub although!
GEN_HUBBYPASS : if gPhyPortCount = 1 generate
--! Port number for external phy port
constant cExtPort : natural := cPhyPortLow;
--! Port number for internal MAC port
constant cIntPort : natural := cHubIntPort;
begin
inst_openhub.tx(cExtPort) <= inst_openhub.rx(cIntPort);
inst_openhub.tx(cIntPort) <= inst_openhub.rx(cExtPort);
inst_openhub.receivePort <= cExtPort;
end generate GEN_HUBBYPASS;
--! Generate openFILTER instances for every phy port.
GEN_FILTER : for i in cPhyPortHigh downto cPhyPortLow generate
THEOPENFILTER : entity work.openfilter
port map (
iRst => inst_openfilter.rst,
iClk => inst_openfilter.clk,
iRx => inst_openfilter.rxIn(i),
oRx => inst_openfilter.rxOut(i),
iTx => inst_openfilter.txIn(i),
oTx => inst_openfilter.txOut(i),
iRxError => inst_openfilter.rxError(i)
);
end generate GEN_FILTER;
--! Generate MII signals for every phy port. Note that this includes
--! the RMII-to-MII converter.
GEN_MII : if gPhyPortType = cPhyPortMii generate
GEN_CONVERTER : for i in cPhyPortHigh downto cPhyPortLow generate
-- convert phy port to filter index range
miiTxPath(i-cHubIntPort-1) <= inst_convRmiiToMii.miiTx(i);
THERMII2MIICONVERTER : entity work.convRmiiToMii
port map (
iRst => inst_convRmiiToMii.rst,
iClk => inst_convRmiiToMii.clk,
iRmiiTx => inst_convRmiiToMii.rmiiTx(i),
oRmiiRx => inst_convRmiiToMii.rmiiRx(i),
iMiiRxClk => inst_convRmiiToMii.miiRxClk(i),
iMiiRx => inst_convRmiiToMii.miiRx(i),
iMiiRxError => inst_convRmiiToMii.miiRxError(i),
iMiiTxClk => inst_convRmiiToMii.miiTxClk(i),
oMiiTx => inst_convRmiiToMii.miiTx(i)
);
end generate GEN_CONVERTER;
end generate GEN_MII;
--! Generate RMII signals for every phy port. The Rx path is latched with
--! iClk and the Tx path is lactehd with iClk2x.
GEN_RMII : if gPhyPortType = cPhyPortRmii generate
--! Latch Rx signals before they come to internals.
LATCHRXPATH : process(iRst, iClk)
begin
if iRst = cActivated then
rmiiRxPathError_reg <= (others => cInactivated);
rmiiRxPath_reg <= (others => cRmiiPathInit);
elsif rising_edge(iClk) then
rmiiRxPathError_reg <= iRmii_RxError;
rmiiRxPath_reg <= iRmii_Rx;
end if;
end process LATCHRXPATH;
--! Latch Tx signals with falling edge before they leave.
LATCHTXPATH : process(iRst, iClk2x)
begin
if iRst = cActivated then
rmiiTxPath_reg <= (others => cRmiiPathInit);
elsif falling_edge(iClk2x) then
-- convert phy port to filter index range
for i in gPhyPortCount-1 downto 0 loop
rmiiTxPath_reg(i) <= inst_openfilter.txOut(i+cPhyPortLow);
end loop;
end if;
end process LATCHTXPATH;
end generate GEN_RMII;
--! Generate PACKET BUFFER DPRAM if Rx or Tx packets are stored localy.
GEN_PKTBUFFER : if (gPacketBufferLocTx = cPktBufLocal or
gPacketBufferLocRx = cPktBufLocal) generate
--! Packet buffer number of words (e.g. 1024 byte => 256 dword)
constant cNumberOfWords : natural := 2**(gPacketBufferLog2Size - logDualis(cPktBufDataWidth/cByteLength));
--! DMA path reset
signal dmaRst : std_logic;
--! DMA path clock
signal dmaClk : std_logic;
begin
--! This is the packet buffer DPRAM storing Tx and/or Rx packets.
--! Port A is connected to the openMAC DMA and port B is connected to
--! the memory mapped slave port (host).
THEPKTBUF : entity work.dpRam
generic map (
gWordWidth => cPktBufDataWidth,
gNumberOfWords => cNumberOfWords,
gInitFile => "UNUSED"
)
port map (
iClk_A => inst_pktBuffer.dma.clk,
iEnable_A => inst_pktBuffer.dma.enable,
iWriteEnable_A => inst_pktBuffer.dma.write,
iAddress_A => inst_pktBuffer.dma.address,
iByteenable_A => inst_pktBuffer.dma.byteenable,
iWritedata_A => inst_pktBuffer.dma.writedata,
oReaddata_A => inst_pktBuffer.dma.readdata,
iClk_B => inst_pktBuffer.host.clk,
iEnable_B => inst_pktBuffer.host.enable,
iWriteEnable_B => inst_pktBuffer.host.write,
iByteenable_B => inst_pktBuffer.host.byteenable,
iAddress_B => inst_pktBuffer.host.address,
iWritedata_B => inst_pktBuffer.host.writedata,
oReaddata_B => inst_pktBuffer.host.readdata
);
dmaRst <= inst_pktBuffer.dma.rst;
dmaClk <= inst_pktBuffer.dma.clk;
--! This process generates the DMA acknowlegde pulse. It is generated
--! for read and/or write requests with same delay.
DMAACKPULSE : process(dmaRst, dmaClk)
begin
if dmaRst = cActivated then
inst_pktBuffer.dma_ack <= cInactivated;
elsif rising_edge(dmaClk) then
-- generate pulse => default
inst_pktBuffer.dma_ack <= cInactivated;
if (inst_openmac.dma_request = cActivated and
inst_pktBuffer.dma_ack = cInactivated) then
-- Check if it is a write or read
if inst_openmac.nDma_write = cnActivated then
-- It is a write (Rx packet), check generic...
if gPacketBufferLocRx = cPktBufLocal then
inst_pktBuffer.dma_ack <= cActivated;
end if;
else
-- It is a read (Tx packet), check generic...
if gPacketBufferLocTx = cPktBufLocal then
inst_pktBuffer.dma_ack <= cActivated;
end if;
end if;
end if;
end if;
end process DMAACKPULSE;
--! This process stores the DMA high word select for DMA read path.
--! Note: This workaround is needed since data is latched after dma ack.
DMAHIGHWORDSEL : process(dmaRst, dmaClk)
begin
if dmaRst = cActivated then
inst_pktBuffer.dma_highWordSel <= cInactivated;
elsif rising_edge(dmaClk) then
if inst_openmac.dma_request = cActivated and inst_openmac.nDma_write = cnInactivated then
inst_pktBuffer.dma_highWordSel <= inst_openmac.dma_address(1);
end if;
end if;
end process DMAHIGHWORDSEL;
end generate GEN_PKTBUFFER;
--! Generate DMA Master instances if Rx or Tx packets are stored externally.
GEN_DMAMASTER : if (gPacketBufferLocTx = cPktBufExtern or
gPacketBufferLocRx = cPktBufExtern) generate
--! This is the DMA master handling the Tx and/or Rx packet transfers
--! to/from the interconnect.
THEDMAMASTER: entity work.openMAC_DMAmaster
generic map (
dma_highadr_g => gDmaAddrWidth-1,
fifo_data_width_g => gDmaDataWidth,
gen_dma_observer_g => (gEnableDmaObserver /= cFalse),
gen_rx_fifo_g => (gPacketBufferLocRx = cPktBufExtern),
gen_tx_fifo_g => (gPacketBufferLocTx = cPktBufExtern),
m_burstcount_const_g => TRUE, --TODO: check if okay
m_burstcount_width_g => gDmaBurstCountWidth,
m_rx_burst_size_g => gDmaWriteBurstLength,
rx_fifo_word_size_g => gDmaWriteFifoLength,
m_tx_burst_size_g => gDmaReadBurstLength,
tx_fifo_word_size_g => gDmaReadFifoLength,
simulate => FALSE
)
port map (
dma_clk => inst_dmaMaster.dma.clk,
rst => inst_dmaMaster.dma.rst,
dma_req_wr => inst_dmaMaster.dma.reqWrite,
dma_req_rd => inst_dmaMaster.dma.reqRead,
dma_req_overflow => inst_dmaMaster.dma.reqOverflow,
dma_ack_wr => inst_dmaMaster.dma.ackWrite,
dma_ack_rd => inst_dmaMaster.dma.ackRead,
dma_rd_err => inst_dmaMaster.dma.readError,
dma_rd_len => inst_dmaMaster.dma.readLength,
dma_wr_err => inst_dmaMaster.dma.writeError,
dma_addr => inst_dmaMaster.dma.address,
dma_dout => inst_dmaMaster.dma.writedata,
dma_din => inst_dmaMaster.dma.readdata,
m_clk => inst_dmaMaster.master.clk,
--FIXME: m_rst => inst_dmaMaster.master.rst,
m_write => inst_dmaMaster.master.write,
m_read => inst_dmaMaster.master.read,
m_readdatavalid => inst_dmaMaster.master.readdatavalid,
m_waitrequest => inst_dmaMaster.master.waitrequest,
m_address => inst_dmaMaster.master.address,
m_byteenable => inst_dmaMaster.master.byteenable,
m_burstcount => inst_dmaMaster.master.burstcount,
m_burstcounter => inst_dmaMaster.master.burstcounter,
m_writedata => inst_dmaMaster.master.writedata,
m_readdata => inst_dmaMaster.master.readdata,
mac_rx_off => inst_dmaMaster.mac_rxOff,
mac_tx_off => inst_dmaMaster.mac_txOff
);
end generate GEN_DMAMASTER;
--! Generate MAC activity, which can be used for LED control.
GEN_ACTIVITY : if gEnableActivity = cTrue generate
--! The activity generate uses the Tx enable and Rx data valid signal
--! to detect a packet run.
THEACTIVITY : entity work.phyActGen
generic map (
gActivityFreq => cActivityFreq,
gClkFreq => cClkFreq
)
port map (
iRst => inst_activity.rst,
iClk => inst_activity.clk,
iTxEnable => inst_activity.txEnable,
iRxValid => inst_activity.rxDataValid,
oActivity => inst_activity.activity
);
end generate GEN_ACTIVITY;
end rtl;
| gpl-2.0 | 4643cd799a20080cc76e3f0b80d1c395 | 0.506078 | 5.348852 | false | false | false | false |
cnplab/blockmon | fw-combo/src/IPFIX/comp/sh_reg_elem.vhd | 1 | 5,202 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
--
-- sh_reg_elem.vhd: Shift Register Element
-- Copyright (C) 2003 CESNET
-- Author(s): Martinek Tomas <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: sh_reg_elem.vhd 24 2007-07-31 11:19:09Z kosek $
--
-- TODO:
--
--
library IEEE;
use IEEE.std_logic_1164.all;
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity sh_reg_elem is
generic(
SH_INIT : std_logic_vector(15 downto 0) := X"0000"
);
port(
CLK : in std_logic;
DIN : in std_logic;
CE : in std_logic;
ADDR : in std_logic_vector(3 downto 0);
DOUT : out std_logic
);
end entity sh_reg_elem;
-- ----------------------------------------------------------------------------
-- Architecture declaration
-- ----------------------------------------------------------------------------
architecture behavioral of sh_reg_elem is
-- component declaration
component SRL16E
generic(
INIT : bit_vector(15 downto 0) := X"0000"
);
port (
D : in std_logic;
CE : in std_logic;
CLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic
);
end component;
function stdlogic2hstring(value: in std_logic_vector) return string is
variable quad : std_logic_vector(0 to 3);
constant ne : integer := value'length/4;
variable bv : std_logic_vector(0 to value'length-1) := value;
variable s : string(1 to ne);
begin
for i in 0 to ne-1 loop
quad := bv(4*i to 4*i+3);
case quad is
when X"0" => s(i+1) := '0';
when X"1" => s(i+1) := '1';
when X"2" => s(i+1) := '2';
when X"3" => s(i+1) := '3';
when X"4" => s(i+1) := '4';
when X"5" => s(i+1) := '5';
when X"6" => s(i+1) := '6';
when X"7" => s(i+1) := '7';
when X"8" => s(i+1) := '8';
when X"9" => s(i+1) := '9';
when X"A" => s(i+1) := 'A';
when X"B" => s(i+1) := 'B';
when X"C" => s(i+1) := 'C';
when X"D" => s(i+1) := 'D';
when X"E" => s(i+1) := 'E';
when X"F" => s(i+1) := 'F';
when others => s(i+1) := '0';
end case;
end loop;
return s;
end function;
attribute INIT: string;
attribute INIT of U_SRL16E: label is stdlogic2hstring(SH_INIT);
-- ----------------------------------------------------------------------------
begin
U_SRL16E: SRL16E
generic map(
INIT => to_bitvector(SH_INIT)
)
port map (
D => DIN,
CE => CE,
CLK => CLK,
A0 => ADDR(0),
A1 => ADDR(1),
A2 => ADDR(2),
A3 => ADDR(3),
Q => DOUT
);
end architecture behavioral;
-- ----------------------------------------------------------------------------
| bsd-3-clause | 27e4e893c354a1009b09f58f143b41d5 | 0.514225 | 3.85619 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/lib/src/addrDecodeRtl.vhd | 3 | 4,086 | -------------------------------------------------------------------------------
--! @file addrDecodeRtl.vhd
--
--! @brief Address Decoder for generating select signal
--
--! @details This address decoder generates a select signal depending on the
--! provided base- and high-addresses by using smaller/greater logic.
--! Additionally a strob is generated if the base or high address is selected.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity addrDecode is
generic (
--! Address bus width
gAddrWidth : natural := 32;
--! Decode space base address
gBaseAddr : natural := 16#1000#;
--! Decode space high address
gHighAddr : natural := 16#1FFF#
);
port (
--! Enable decoding
iEnable : in std_logic;
--! Address bus
iAddress : in std_logic_vector(gAddrWidth-1 downto 0);
--! Select output
oSelect : out std_logic
);
end addrDecode;
architecture rtl of addrDecode is
--! Address to be decoded
signal address : unsigned(gAddrWidth-1 downto 0);
--! Address is in range
signal addressInRange : std_logic;
--! Base address used for comparison
constant cBase : unsigned(gAddrWidth-1 downto 0) :=
to_unsigned(gBaseAddr, gAddrWidth);
--! High address used for comparison
constant cHigh : unsigned(gAddrWidth-1 downto 0) :=
to_unsigned(gHighAddr, gAddrWidth);
begin
-- check generics
assert (gBaseAddr < gHighAddr)
report "Base address should be smaller than High address!" severity failure;
-- connect ports to signals
oSelect <= addressInRange;
address <= unsigned(iAddress);
--! Decode input address logic
combAddrDec : process (
iEnable,
address
)
begin
--default assignments of process outputs
addressInRange <= cInactivated;
if iEnable = cActivated then
if (cBase <= address) and (address <= cHigh) then
addressInRange <= cActivated;
end if;
end if;
end process;
end rtl;
| gpl-2.0 | 3e5d88b4ba42fc311101814ece715f08 | 0.629956 | 4.88756 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/fifo/src/fifoRead-rtl-ea.vhd | 3 | 5,816 | -------------------------------------------------------------------------------
--! @file fifoRead-rtl-ea.vhd
--
--! @brief FIFO read controller
--
--! @details This is a FIFO read controller.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity fifoRead is
generic (
gAddrWidth : natural := 4
);
port (
iClk : in std_logic;
iRst : in std_logic;
iRead : in std_logic;
iWrPointer : in std_logic_vector(gAddrWidth downto 0);
oEmpty : out std_logic;
oFull : out std_logic;
oPointer : out std_logic_vector(gAddrWidth downto 0);
oAddress : out std_logic_vector(gAddrWidth-1 downto 0);
oUsedWord : out std_logic_vector(gAddrWidth-1 downto 0)
);
end fifoRead;
architecture rtl of fifoRead is
signal r_ptr_reg : std_logic_vector(gAddrWidth downto 0);
signal r_ptr_next : std_logic_vector(gAddrWidth downto 0);
signal gray1 : std_logic_vector(gAddrWidth downto 0);
signal bin : std_logic_vector(gAddrWidth downto 0);
signal bin1 : std_logic_vector(gAddrWidth downto 0);
signal raddr_all : std_logic_vector(gAddrWidth-1 downto 0);
signal raddr_msb : std_logic;
signal waddr_msb : std_logic;
signal empty_flag : std_logic;
signal full_flag : std_logic;
signal r_elements_wr : std_logic_vector(gAddrWidth downto 0);
signal r_elements_rd : std_logic_vector(gAddrWidth downto 0);
signal r_elements_diff : std_logic_vector(gAddrWidth downto 0);
signal r_elements_reg : std_logic_vector(gAddrWidth-1 downto 0);
signal r_elements_next : std_logic_vector(gAddrWidth-1 downto 0);
begin
--! Clock process for registers.
regProc : process(iRst, iClk)
begin
if iRst = cActivated then
r_ptr_reg <= (others => cInactivated);
r_elements_reg <= (others => cInactivated);
elsif rising_edge(iClk) then
r_ptr_reg <= r_ptr_next;
r_elements_reg <= r_elements_next;
end if;
end process;
-- (gAddrWidth+1)-bit Gray counter
bin <= r_ptr_reg xor (cInactivated & bin(gAddrWidth downto 1));
bin1 <= std_logic_vector(unsigned(bin) + 1);
gray1 <= bin1 xor (cInactivated & bin1(gAddrWidth downto 1));
-- update read pointer
r_ptr_next <= gray1 when iRead = cActivated and empty_flag = cInactivated else
r_ptr_reg;
-- gAddrWidth-bit Gray counter
raddr_msb <= r_ptr_reg(gAddrWidth) xor r_ptr_reg(gAddrWidth-1);
raddr_all <= raddr_msb & r_ptr_reg(gAddrWidth-2 downto 0);
waddr_msb <= iWrPointer(gAddrWidth) xor iWrPointer(gAddrWidth-1);
-- check for FIFO read empty
empty_flag <= cActivated when iWrPointer(gAddrWidth) = r_ptr_reg(gAddrWidth) and
iWrPointer(gAddrWidth-2 downto 0) = r_ptr_reg(gAddrWidth-2 downto 0) and
raddr_msb = waddr_msb else
cInactivated;
-- check for FIFO read full
full_flag <= cActivated when iWrPointer(gAddrWidth) /= r_ptr_reg(gAddrWidth) and
iWrPointer(gAddrWidth-2 downto 0) = r_ptr_reg(gAddrWidth-2 downto 0) and
raddr_msb = waddr_msb else
cInactivated;
-- convert gray value to bin and obtain difference
r_elements_wr <= bin;
r_elements_rd <= iWrPointer xor (cInactivated & r_elements_rd(gAddrWidth downto 1));
r_elements_diff <= std_logic_vector(unsigned(r_elements_rd) - unsigned(r_elements_wr));
r_elements_next <= r_elements_diff(r_elements_next'range);
-- output
oAddress <= raddr_all;
oPointer <= r_ptr_reg;
oUsedWord <= r_elements_reg;
oEmpty <= empty_flag;
oFull <= full_flag;
end rtl;
| gpl-2.0 | a651f571dca6609458bf9ed120a63adf | 0.619326 | 4.15132 | false | false | false | false |
pkerling/Chips-Demo | source/reset_generator.vhd | 1 | 851 | library ieee;
use ieee.std_logic_1164.all;
entity reset_generator is
generic(
-- 20 ms at 125 MHz clock
-- Minimum 88E1111 reset pulse width: 10 ms
RESET_DELAY : positive := 2500000
);
port(
clock_i : in std_ulogic;
locked_i : in std_ulogic;
reset_o : out std_ulogic
);
end entity;
architecture rtl of reset_generator is
signal reset_cnt : natural range 0 to RESET_DELAY := 0;
begin
reset_proc : process(clock_i, locked_i)
begin
if locked_i = '1' then
if rising_edge(clock_i) then
-- When locked, wait for RESET_DELAY ticks, then deassert reset
if reset_cnt < RESET_DELAY then
reset_cnt <= reset_cnt + 1;
reset_o <= '1';
else
reset_o <= '0';
end if;
end if;
else
-- Keep in reset when not locked
reset_cnt <= 0;
reset_o <= '1';
end if;
end process;
end architecture;
| mit | 1f8bf90f06dc3d9f9a185882901e8736 | 0.638073 | 2.894558 | false | false | false | false |
ARC-Lab-UF/window_gen | src/wg_buffer.vhd | 1 | 18,796 | -- Copyright (c) University of Florida
--
-- This file is part of window_gen.
--
-- window_gen is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- window_gen is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with window_gen. If not, see <http://www.gnu.org/licenses/>.
-- Greg Stitt
-- Patrick Cooke
-- University of Florida
-- Description: This entity defines an array of FIFOs that are used to buffer
-- rows of an image. The buffer uses MAX_WINDOW_ROWS RAMs,
-- where each RAM has MAX_IMAGE_COLS words that are DATA_WIDTH bits wide. The
-- array maintaints a front position across all FIFOs, which represent the next
-- column of elements needed by the window buffer.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.math_custom.all;
use work.window_gen_pkg.all;
-------------------------------------------------------------------------------
-- Generics Description
-- PARALLEL_IO : Specifies the number of inputs provided at a time,
-- which also defines the number of columns output
-- from the entity.
-- DATA_WIDTH : The width in bits of each element.
-- MAX_WINDOW_ROWS : The maximum number of rows in a generated window
-- MAX_WINDOW_COLS : The maximum number of cols in a generated window
-- MAX_IMAGE_ROWS : The maximum number of rows in an input image/stream
-- MAX_IMAGE_COLS : The maximum number of cols in an input image/stream
-- MAX_BUFFER_SIZE : The maximum buffer size (should be computed by the window
-- generator)
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Port Descriptions (all control signals are active high)
-- clk : clock
-- rst : asynchronous reset
-- active : '1' if the buffer is still in the process of generating windows
-- ren : '1' to pop front values from each fifo
-- input_ready : specifies when "input" is valid
-- read_input : informs the source of the stream that the buffer is accepting data
-- empty : '1' when the buffer has a valid window, '0' otherwise
-- is_edge : '1' if the current input is the edge (left column) of a window
-- buffer_size : actual size/words of the buffer, varies based on image_cols and
-- PARALLEL_IO
-- image_rows : the number of cols in the input image
-- image_cols : the number of cols in the input image
-- window_rows : the number of rows in the window
-- window_cols : the number of cols in the window
-- input : the next PARALLEL_IO inputs
-- output : the next PARALLEL_IO columns needed to create window
-- done : '1' when the entire image has been processed and all columns needed
-- by windows have been output
-------------------------------------------------------------------------------
entity wg_buffer is
generic (
PARALLEL_IO : positive;
DATA_WIDTH : positive;
MAX_WINDOW_ROWS : positive;
MAX_WINDOW_COLS : positive;
MAX_IMAGE_ROWS : positive;
MAX_IMAGE_COLS : positive;
MAX_BUFFER_SIZE : positive);
port (
clk : in std_logic;
rst : in std_logic;
active : in std_logic;
ren : in std_logic;
input_ready : in std_logic;
read_input : out std_logic;
empty : out std_logic;
is_edge : out std_logic_vector(PARALLEL_IO-1 downto 0);
buffer_size : in std_logic_vector(bitsNeeded(MAX_BUFFER_SIZE)-1 downto 0);
image_rows : in std_logic_vector(bitsNeeded(MAX_IMAGE_ROWS)-1 downto 0);
image_cols : in std_logic_vector(bitsNeeded(MAX_IMAGE_COLS)-1 downto 0);
window_rows : in std_logic_vector(bitsNeeded(MAX_WINDOW_ROWS)-1 downto 0);
window_cols : in std_logic_vector(bitsNeeded(MAX_WINDOW_COLS)-1 downto 0);
input : in std_logic_vector(DATA_WIDTH*PARALLEL_IO-1 downto 0);
output : out std_logic_vector(MAX_WINDOW_ROWS*PARALLEL_IO*DATA_WIDTH-1 downto 0);
done : out std_logic);
end wg_buffer;
architecture RTL of wg_buffer is
type fifo_output is array (0 to MAX_WINDOW_ROWS-1) of std_logic_vector(PARALLEL_IO*DATA_WIDTH-1 downto 0);
type fifo_array is array (0 to MAX_WINDOW_ROWS-1, 0 to PARALLEL_IO-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
-- converts from fifo_array to std_logic_vector
function vectorizeOutput(output_array : fifo_array) return std_logic_vector is
variable temp : std_logic_vector(MAX_WINDOW_ROWS*PARALLEL_IO*DATA_WIDTH-1 downto 0);
begin
for i in 0 to MAX_WINDOW_ROWS-1 loop
for j in 0 to PARALLEL_IO-1 loop
setVectorElement(output_array(i, j), temp, i, j, MAX_WINDOW_ROWS, PARALLEL_IO, DATA_WIDTH);
end loop;
end loop;
return temp;
end function;
constant MAX_WINDOW_ROWS_BITS : positive := bitsNeeded(MAX_WINDOW_ROWS-1);
-- the FIFO needs an address space going from 0 to MAX_BUFFER_SIZE-1
constant FIFO_ADDR_BITS : positive := bitsNeeded(MAX_BUFFER_SIZE-1);
-- pointers to the front and back FIFOs
-- Writes always go the the back FIFO. The front represents the first row
-- of the current windows
signal front : unsigned(MAX_WINDOW_ROWS_BITS-1 downto 0);
signal back : unsigned(MAX_WINDOW_ROWS_BITS-1 downto 0);
signal fifo_rdata : fifo_output;
signal fifo_rdata_array : fifo_array;
signal fifo_wen : std_logic_vector(MAX_WINDOW_ROWS-1 downto 0);
signal fifo_ren : std_logic;
signal fifo_pop : std_logic_vector(MAX_WINDOW_ROWS-1 downto 0);
-- signal fifo_empty : std_logic_vector(MAX_WINDOW_ROWS-1 downto 0);
signal fifo_read_empty : std_logic_vector(MAX_WINDOW_ROWS-1 downto 0);
signal fifo_read_reset : std_logic_vector(MAX_WINDOW_ROWS-1 downto 0);
signal fifo_full : std_logic_vector(MAX_WINDOW_ROWS-1 downto 0);
-- specifies when an request read is valid
signal valid_read : std_logic;
-- asserted when the array needs the next input
signal get_next_input : std_logic;
-- asserted when the front pointer changes, which corresponds to a new
-- top row for generated windows
signal front_changed : std_logic;
-- the output array from all the FIFOs, which corresponds to an element
-- from MAX_WINDOW_ROWS different rows.
signal output_array : fifo_array;
-- keep track of the current row and col of the input image
signal in_row : integer range 0 to MAX_IMAGE_ROWS + MAX_WINDOW_ROWS;
signal in_col : integer range 0 to MAX_BUFFER_SIZE*PARALLEL_IO;
-- keep track of the current row and col of the image being used to output
-- the current window
signal out_row : integer range 0 to MAX_IMAGE_ROWS + MAX_WINDOW_ROWS;
signal out_col : integer range 0 to MAX_BUFFER_SIZE*PARALLEL_IO;
-- misc control signals (see description below
signal input_done : std_logic;
signal output_done : std_logic;
signal stall_pop : std_logic;
signal almost_done : std_logic;
signal continue : std_logic;
signal image_loaded : std_logic;
signal windows_per_row : unsigned(bitsNeeded(MAX_IMAGE_COLS)-1 downto 0);
signal done_s : std_logic;
signal is_edge_s : std_logic_vector(PARALLEL_IO-1 downto 0);
begin
-- the array of fifos that acts as a circular buffer
U_FIFOS : for i in 0 to MAX_WINDOW_ROWS-1 generate
U_FIFO : entity work.wg_fifo
generic map (
DATA_WIDTH => DATA_WIDTH*PARALLEL_IO,
ADDR_WIDTH => FIFO_ADDR_BITS,
SIZE_WIDTH => bitsNeeded(MAX_BUFFER_SIZE))
port map (
clk => clk,
rst => rst,
wen => fifo_wen(i),
wdata => input,
ren => fifo_ren,
pop => fifo_pop(i),
read_reset => fifo_read_reset(i),
read_empty => fifo_read_empty(i),
rdata => fifo_rdata(i),
empty => open,
full => fifo_full(i),
size => buffer_size);
end generate U_FIFOS;
-- put the PARALLEL_IO outputs stored in each FIFO word into separate array
-- elements
process(fifo_rdata)
begin
for i in 0 to MAX_WINDOW_ROWS-1 loop
for j in 0 to PARALLEL_IO-1 loop
fifo_rdata_array(i, PARALLEL_IO-j-1) <= fifo_rdata(i)(DATA_WIDTH*(j+1)-1 downto DATA_WIDTH*j);
end loop;
end loop;
end process;
--------------------------------------------------------------------------
-- Control logic for front and back pointers, and window edges
U_FRONT_CONTROL : entity work.wg_fifo_edge_control generic map (
PARALLEL_IO => PARALLEL_IO,
MAX_BUFFER_SIZE => MAX_BUFFER_SIZE,
MAX_WINDOW_ROWS => MAX_WINDOW_ROWS,
MAX_IMAGE_COLS => MAX_IMAGE_COLS)
port map (
clk => clk,
rst => rst,
en => valid_read,
edge => front,
changed => front_changed,
is_window_edge => is_edge_s,
buffer_size => buffer_size,
windows_per_row => std_logic_vector(windows_per_row));
U_BACK_CONTROL : entity work.wg_fifo_edge_control generic map (
PARALLEL_IO => PARALLEL_IO,
MAX_BUFFER_SIZE => MAX_BUFFER_SIZE,
MAX_WINDOW_ROWS => MAX_WINDOW_ROWS,
MAX_IMAGE_COLS => MAX_IMAGE_COLS)
port map (
clk => clk,
rst => rst,
en => get_next_input,
edge => back,
changed => open,
is_window_edge => open,
buffer_size => buffer_size,
windows_per_row => std_logic_vector(windows_per_row));
--------------------------------------------------------------------------
-- Logic for accessing FIFOs as a circular array
process(front, back, fifo_full, input, input_ready, ren, fifo_read_empty, fifo_rdata_array, get_next_input, front_changed, stall_pop)
variable any_empty : std_logic;
variable valid_read_temp : std_logic;
-- initialized only to remove simulation warnings at time 0
variable front_mod : unsigned(MAX_WINDOW_ROWS_BITS downto 0) := (others => '0');
begin
-- handle writes
for i in 0 to MAX_WINDOW_ROWS-1 loop
-- enable the wen on the current back fifo if valid_write
if (to_unsigned(i, MAX_WINDOW_ROWS_BITS) = back) then
if (get_next_input = '1') then
fifo_wen(i) <= '1';
else
fifo_wen(i) <= '0';
end if;
else
fifo_wen(i) <= '0';
end if;
end loop;
-- "or" all fifo empty signals together
any_empty := '0';
for i in 0 to MAX_WINDOW_ROWS-1 loop
any_empty := any_empty or fifo_read_empty(i); -- changed from fifo_empty
end loop;
-- if any of the FIFOs are empty, the array is empty (no valid output)
empty <= any_empty;
-- a read is valid if ren is set and none of the fifos are empty
valid_read_temp := ren and not any_empty;
valid_read <= valid_read_temp;
-- read from all the fifos
if (valid_read_temp = '1') then
fifo_ren <= '1';
else
fifo_ren <= '0';
end if;
for i in 0 to MAX_WINDOW_ROWS-1 loop
-- align the rdata outputs so front is always the first output
front_mod := ("0"&front) + i;
if (front_mod >= MAX_WINDOW_ROWS) then
front_mod := front_mod - MAX_WINDOW_ROWS;
end if;
-- causes a harmless XST warning for non power of 2 dimensions
-- can be fixed by making a variable that is the next higher power
-- of 2 and setting the unused bits to 0 (Although this may cause
-- other warnings)
for j in 0 to PARALLEL_IO-1 loop
output_array(i, j) <= fifo_rdata_array(to_integer(front_mod(MAX_WINDOW_ROWS_BITS-1 downto 0)), j);
end loop;
-- pop from the front during a valid read because that row will not
-- be needed by any later windows. The exception is the window
-- slides past the bottom row of the image (stall_pop='1'), in
-- which case the circuit reuses previous rows as placeholders.
if (valid_read_temp = '1') then
if (i = front and stall_pop = '0') then
fifo_pop(i) <= '1';
else
fifo_pop(i) <= '0';
end if;
else
fifo_pop(i) <= '0';
end if;
-- if front changes, do a read reset of each fifo so that
-- the subsequent accesses start at the beginning of each row
if (front_changed = '1') then
fifo_read_reset(i) <= '1';
else
fifo_read_reset(i) <= '0';
end if;
end loop;
end process;
--------------------------------------------------------------------------
-- determine completion of inputs and outputs
process (clk, rst)
begin
if rst = '1' then
in_row <= 0;
in_col <= 0;
out_row <= 0;
out_col <= 0;
elsif (rising_edge(clk)) then
-- in the case of new inputs, updated the row/col pointers
if (continue = '1' and input_done = '0') then
if (in_col >= unsigned(image_cols)-PARALLEL_IO or PARALLEL_IO > unsigned(image_cols)) then
in_col <= 0;
in_row <= in_row + 1;
else
in_col <= in_col + PARALLEL_IO;
end if;
end if;
-- in the case of new outputs, updated the row/col pointers
if (valid_read = '1') then
if (out_col >= unsigned(image_cols)-PARALLEL_IO or PARALLEL_IO > unsigned(image_cols)) then
out_col <= 0;
out_row <= out_row + 1;
else
out_col <= out_col + PARALLEL_IO;
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------
-- misc control logic
windows_per_row <= resize(unsigned(image_cols)-unsigned(window_cols)+1, windows_per_row'length);
-- get the next input when that input is available and the back fifo isn't
-- full.
-- causes a harmless XST warning for non power of 2 dimensions
-- an be fixed by making a variable that is the next higher power of 2
-- and setting the unused bits to 0 (Although this may cause "unused"
-- warnings)
get_next_input <= input_ready and not fifo_full(to_integer(back));
read_input <= get_next_input;
-- "continue" with window generation when getting the input or when there
-- is a valid read after the entire image has been loaded, which is
-- necessary for sliding the window past the bottom boundary of the image
continue <= get_next_input or (valid_read and image_loaded);
-- full <= fifo_full(to_integer(back));
-- the entire image is loaded after storing image_rows of inputs
image_loaded <= '1' when in_row >= unsigned(image_rows) else '0';
-- stall pops from the fifo array when the output has reached the last
-- MAX_WINDOW_ROWS rows of the image. This is necessary because the final
-- rows for a window smaller than the maximum size must access rows of the
-- image that don't exist. By delaying pops from the FIFO, this allows for
-- data in earlier rows to be reused as the extra rows.
stall_pop <= '1' when out_row >= unsigned(image_rows) - MAX_WINDOW_ROWS and almost_done = '0' and input_done = '0' else '0';
-- The entity is "almost done" generating windows when the window is in the
-- last possible row of the image (image_rows-window_rows) where the window
-- can still be fully immersed in the image. The main purpose of this signal
-- is to clear the stall_pop flag, so that pops from the FIFO can continue.
almost_done <= '1' when out_row >= unsigned(image_rows) - unsigned(window_rows) and input_done = '0' else '0';
-- The entity has all of the required data to generate all windows when
-- image_rows+MAX_WINDOW_ROWS-window_rows have been stored in the fifo
-- array. Note that MAX_WINDOWS_ROWS-window_rows corresponds to extra rows
-- not in the original image, which are needed to slide the maximum sized
-- window across the additional rows needed by the smaller, actual window
input_done <= '1' when in_row >= unsigned(image_rows) + MAX_WINDOW_ROWS - unsigned(window_rows) else '0';
-- outputs are completely done when the output row exceeds the final row
-- needed for the top of a window
output_done <= '1' when out_row > unsigned(image_rows) - unsigned(window_rows) else '0';
-- "and active" prevents done from being asserted before circuit has started
done_s <= output_done and active;
done <= done_s;
-- make sure is_edge isn't valid after done
process(is_edge_s, done_s)
begin
if (done_s = '0') then
is_edge <= is_edge_s;
else
is_edge <= (others => '0');
end if;
end process;
-- convert the output array into a big vector to avoid problems with
-- unconstrained arrays
output <= vectorizeOutput(output_array);
end RTL;
| gpl-3.0 | b636e68ff398a8622709cd8a5398b1d7 | 0.567834 | 4.10662 | false | false | false | false |
pkerling/Chips-Demo | source/chips_mac_adaptor.vhd | 1 | 5,004 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ethernet_mac;
use ethernet_mac.ethernet_types.all;
use ethernet_mac.framing_common.all;
entity chips_mac_adaptor is
port(
-- Common clock for MAC and chips
clock_i : in std_ulogic;
reset_i : in std_ulogic;
-- MAC FIFO interface
tx_data_o : out t_ethernet_data;
tx_wr_en_o : out std_ulogic;
tx_full_i : in std_ulogic;
rx_empty_i : in std_ulogic;
rx_rd_en_o : out std_ulogic;
rx_data_i : in t_ethernet_data;
-- Chips interface
chips_tx_i : in std_logic_vector(15 downto 0);
chips_tx_stb_i : in std_logic;
chips_tx_ack_o : out std_logic;
chips_rx_o : out std_logic_vector(15 downto 0);
chips_rx_stb_o : out std_logic;
chips_rx_ack_i : in std_logic
);
end entity;
architecture rtl of chips_mac_adaptor is
type t_tx_state is (
TX_IDLE,
TX_WRITE_SIZE_LO_BYTE,
TX_FORWARD_HI_BYTE,
TX_FORWARD_LO_BYTE
);
signal tx_state : t_tx_state := TX_IDLE;
type t_rx_state is (
RX_IDLE,
RX_READ_HI_BYTE,
RX_READ_LO_BYTE,
RX_WAIT_ACK
);
signal rx_state : t_rx_state := RX_IDLE;
signal tx_lo_byte_buf : t_ethernet_data := (others => '0');
signal tx_forward_bytes_remaining : natural range 0 to MAX_PACKET_LENGTH := 0;
begin
tx_chips_to_ethernet_copy_proc : process(clock_i)
begin
if rising_edge(clock_i) then
-- Default output values
chips_tx_ack_o <= '0';
tx_wr_en_o <= '0';
if reset_i = '1' then
tx_state <= TX_IDLE;
else
case tx_state is
when TX_IDLE =>
chips_tx_ack_o <= not tx_full_i;
if chips_tx_stb_i = '1' then
-- Read and forward data size
tx_data_o <= t_ethernet_data(chips_tx_i(15 downto 8));
tx_wr_en_o <= '1';
tx_lo_byte_buf <= t_ethernet_data(chips_tx_i(7 downto 0));
tx_state <= TX_WRITE_SIZE_LO_BYTE;
tx_forward_bytes_remaining <= to_integer(unsigned(chips_tx_i));
end if;
when TX_WRITE_SIZE_LO_BYTE =>
tx_data_o <= tx_lo_byte_buf;
tx_wr_en_o <= '1';
tx_state <= TX_FORWARD_HI_BYTE;
when TX_FORWARD_HI_BYTE =>
chips_tx_ack_o <= not tx_full_i;
if chips_tx_stb_i = '1' then
-- Write data
tx_forward_bytes_remaining <= tx_forward_bytes_remaining - 1;
tx_data_o <= t_ethernet_data(chips_tx_i(15 downto 8));
tx_wr_en_o <= '1';
-- Capture for next state (chips may change the value so it needs to be buffered)
tx_lo_byte_buf <= t_ethernet_data(chips_tx_i(7 downto 0));
if tx_forward_bytes_remaining = 1 then
-- This was the last one
tx_state <= TX_IDLE;
else
tx_state <= TX_FORWARD_LO_BYTE;
end if;
end if;
when TX_FORWARD_LO_BYTE =>
-- Write data
tx_forward_bytes_remaining <= tx_forward_bytes_remaining - 1;
tx_data_o <= tx_lo_byte_buf;
tx_wr_en_o <= '1';
if tx_forward_bytes_remaining = 1 then
-- This was the last one
tx_state <= TX_IDLE;
else
-- Set ACK so the data can already be present in the next cycle
-- (assuming chips is fast enough)
chips_tx_ack_o <= not tx_full_i;
tx_state <= TX_FORWARD_HI_BYTE;
end if;
end case;
end if;
end if;
end process;
rx_ethernet_to_chips_copy_proc : process(clock_i)
begin
if rising_edge(clock_i) then
chips_rx_stb_o <= '0';
rx_rd_en_o <= '0';
if reset_i = '1' then
rx_state <= RX_IDLE;
else
case rx_state is
when RX_IDLE =>
if rx_empty_i = '0' then
rx_state <= RX_READ_HI_BYTE;
rx_rd_en_o <= '1';
end if;
when RX_READ_HI_BYTE =>
chips_rx_o(15 downto 8) <= std_logic_vector(rx_data_i);
if rx_empty_i = '0' then
rx_state <= RX_READ_LO_BYTE;
rx_rd_en_o <= '1';
else
-- This was the end of the packet
rx_state <= RX_IDLE;
end if;
when RX_READ_LO_BYTE =>
chips_rx_o(7 downto 0) <= std_logic_vector(rx_data_i);
-- Signal data available
chips_rx_stb_o <= '1';
rx_state <= RX_WAIT_ACK;
if rx_empty_i = '1' then
-- We have overrun the buffer ->
-- The packet is received completely and is of uneven length
-- Zero out the unused bits
chips_rx_o(7 downto 0) <= (others => '0');
end if;
when RX_WAIT_ACK =>
-- Continue signaling as long as data is not ACKed
chips_rx_stb_o <= not chips_rx_ack_i;
if chips_rx_ack_i = '1' then
if rx_empty_i = '1' then
-- No more data to read
rx_state <= RX_IDLE;
else
-- Continue and read next byte
rx_state <= RX_READ_HI_BYTE;
rx_rd_en_o <= '1';
end if;
end if;
end case;
end if;
end if;
end process;
end architecture;
| mit | 760bffc791308aa3678ec69a7ce791f1 | 0.552158 | 2.817568 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/openmac/src/phyActGen-rtl-ea.vhd | 3 | 5,137 | -------------------------------------------------------------------------------
--! @file phyActGen-rtl-ea.vhd
--
--! @brief Phy activity generator
--
--! @details The phy activity generator generates a free-running clock-synchronous
--! packet activity signal. This signal can be used to drive an LED.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity phyActGen is
generic (
--! Generated activity frequency of oActivity [Hz]
gActivityFreq : natural := 6;
--! Clock frequency of iClk [Hz]
gClkFreq : natural := 50e6
);
port (
--! Reset
iRst : in std_logic;
--! Clock
iClk : in std_logic;
--! MAC Tx enable signal
iTxEnable : in std_logic;
--! MAC Rx data valid signal
iRxValid : in std_logic;
--! Generated activity signal
oActivity : out std_logic
);
end phyActGen;
architecture rtl of phyActGen is
--! Obtain maximum counter value to achieve activity frequency
constant cCntMaxValue : natural := gClkFreq / gActivityFreq;
--! Obtain counter width
constant cCntWidth : natural := logDualis(cCntMaxValue);
--! The counter
signal counter : std_logic_vector(cCntWidth-1 downto 0);
--! Constant for counter value zero
constant cCntIsZero : std_logic_vector(counter'range) := (others => cInactivated);
--! Terminal counter
signal counterTc : std_logic;
--! Trigger activity in next cycle due to packet activity
signal triggerActivity : std_logic;
--! Enable activity
signal enableActivity : std_logic;
begin
oActivity <= counter(counter'high) when enableActivity = cActivated else
cInactivated;
ledCntr : process(iRst, iClk)
begin
if iRst = cActivated then
triggerActivity <= cInactivated;
enableActivity <= cInactivated;
elsif rising_edge(iClk) then
--monoflop, of course no default value!
if triggerActivity = cActivated and counterTc = cActivated then
--counter overflow and activity within last cycle
enableActivity <= cActivated;
elsif counterTc = cActivated then
--counter overflow but no activity
enableActivity <= cInactivated;
end if;
--monoflop, of course no default value!
if counterTc = cActivated then
--count cycle over, reset trigger
triggerActivity <= cInactivated;
elsif iTxEnable = cActivated or iRxValid = cActivated then
--activity within cycle
triggerActivity <= cActivated;
end if;
end if;
end process;
theFreeRunCnt : process(iClk, iRst)
begin
if iRst = cActivated then
counter <= (others => cInactivated);
elsif iClk = cActivated and iClk'event then
counter <= std_logic_vector(unsigned(counter) - 1);
end if;
end process;
counterTc <= cActivated when counter = cCntIsZero else
cInactivated;
end rtl;
| gpl-2.0 | 8ad09b0d65f45505f7815062e06d0ec5 | 0.616702 | 4.972894 | false | false | false | false |
ARC-Lab-UF/window_gen | src/fifo_vr.vhd | 1 | 10,499 | -- Copyright (c) University of Florida
--
-- This file is part of window_gen.
--
-- window_gen is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- window_gen is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with window_gen. If not, see <http://www.gnu.org/licenses/>.
-- Greg Stitt
-- University of Florida
-- Description:
-- fifo_vr (variable read)
-- This entity implements a fifo that writes a fixed (but configurable)
-- number of inputs in parallel, while allowing a variable number of outputs
-- to be read each cycle.
--
-- The entity is useful for streams of data where upstream components always
-- produce a fixed amount of data, but downstream components may need to
-- read a variable amount of data. e.g., when streaming an image sequentially
-- from memory into an FPGA, the memory might provide four pixels per cycle.
-- If the circuit buffers each row into separate on-chip memories, then at the
-- end of a row, the circuit may need to read less than four pixels if the # of
-- columns is not a multiple of four. In this case, the buffer enables the
-- memory to continually write four pixels per cycle, while the downstream
-- circuit reads as much as needed.
--
-- The size of the fifo is fixed because its main purpose is to dynamically
-- read varying amounts of data from a stream. If a typical FIFO is needed for
-- buffering, the user should connect that FIFO to the input of this
-- entity.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.math_custom.all;
-------------------------------------------------------------------------------
-- Generic Descriptions
-- data_width : The width of a single element to read from the FIFO
-- parallel_io : The number of parallel inputs written every cycle, which
-- is also the max number of outputs that can be read each
-- cycle.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Port Descriptions (all control signals are active high)
-- clk: clock
-- rst: asynchronous reset
-- rd : read data from the buffer (does nothing when empty is asserted)
-- rd_amount : The amount of elements to read from the buffer when rd is
-- asserted. Note that if rd_amount is larger than the actual
-- amount of elements in the fifo, the fifo returns only what
-- it has stored. e.g., If the fifo has 2 elements and rd_amount
-- is 3 when rd is asserted, the fifo will output two valid
-- elements and a third junk element.
-- wr : write num_inputs inputs into the buffer (does nothing when
-- full is asserted)
-- empty : asserted when the buffer is empty (has 0 elements in fifo)
-- full : asserted when there isn't room to write num_inputs inputs.
-- input : num_inputs input values, concatenated into a big std_logic_vector
-- output : max_outputs outputs. When rd_amount < max_outputs, the higher bits
-- contains valid datas.
-- count : the number of valid data_width elements in the fifo
-- valid_out : individual valid bits for each output
-------------------------------------------------------------------------------
entity fifo_vr is
generic (
data_width : positive;
parallel_io : positive;
input0_at_MSB : boolean := false;
output0_at_MSB : boolean := false);
port (
clk : in std_logic;
rst : in std_logic;
rd : in std_logic;
rd_amount : in std_logic_vector(bitsNeeded(parallel_io)-1 downto 0);
wr : in std_logic;
empty : out std_logic;
full : out std_logic;
input : in std_logic_vector(parallel_io*data_width-1 downto 0);
output : out std_logic_vector(parallel_io*data_width-1 downto 0);
count : out std_logic_vector(bitsNeeded(parallel_io)-1 downto 0);
valid_out : out std_logic_vector(parallel_io-1 downto 0));
end fifo_vr;
architecture DEFAULT of fifo_vr is
type data_array is array (natural range <>) of std_logic_vector(data_width-1 downto 0);
signal count_s : unsigned(bitsNeeded(parallel_io)-1 downto 0);
signal front : integer range 0 to parallel_io-1;
signal regs : data_array(0 to parallel_io*2-1);
signal valid_wr : std_logic;
signal valid_rd : std_logic;
signal full_s : std_logic;
signal empty_s : std_logic;
signal valid : std_logic_vector(0 to parallel_io*2-1);
signal valid_out_s : std_logic_vector(0 to parallel_io-1);
signal inputs : data_array(0 to parallel_io-1);
signal window_reset : std_logic;
signal rd_amount_s : integer range 0 to parallel_io;
begin
-- the buffer is empty any of the valid bits in the lower half are '0'
empty_s <= not valid(0);
empty <= empty_s;
-- the buffer is full when any of the valid bits in the upper half are
-- asserted, but not when there is a valid read that resets the window
full_s <= valid(parallel_io) and not (valid_rd and window_reset) and
not empty_s;
full <= full_s;
-- check for valid rd/wr to avoid data loss
valid_wr <= wr and not full_s;
valid_rd <= rd and not empty_s;
count <= std_logic_vector(count_s);
valid_out <= valid_out_s;
-- the window position is reset any time front extends past the first half
window_reset <= '0' when front + rd_amount_s < parallel_io else '1';
-- devectorize the input vector into an array based on the whether or not
-- the first input is at the MSB or LDB
U_INPUT0_AT_MSB : if (INPUT0_AT_MSB) generate
process(input)
begin
for i in 0 to parallel_io-1 loop
inputs(i) <= input(input'length-i*data_width-1 downto input'length-(i+1)*data_width);
end loop;
end process;
end generate;
U_INPUT0_AT_LSB : if (INPUT0_AT_MSB = false) generate
process(input)
begin
for i in 0 to parallel_io-1 loop
inputs(i) <= input((i+1)*data_width-1 downto i*data_width);
end loop;
end process;
end generate;
-- calculate the number of valid bits in the output
process(valid_out_s)
variable temp : unsigned(bitsNeeded(parallel_io)-1 downto 0);
begin
-- calculate the number of valid outputs
temp := (others => '0');
for i in 0 to parallel_io-1 loop
if (valid_out_s(i) = '1') then
temp := temp + 1;
end if;
end loop;
count_s <= temp;
end process;
-- make sure rd_amount can't exceed number of valid outputs
process(rd_amount, count_s)
begin
if (unsigned(rd_amount) > count_s) then
rd_amount_s <= to_integer(unsigned(count_s));
else
rd_amount_s <= to_integer(unsigned(rd_amount));
end if;
end process;
-- align the output with a parallel_io-element window starting at front
process(regs, front, valid)
variable index : integer range 0 to parallel_io*2-2;
begin
for i in 0 to parallel_io-1 loop
-- no need for mod because window gets reset to avoid extending
-- past end of the buffer
index := front + i;
-- set the corresponding output bits for the current register
if (OUTPUT0_AT_MSB) then
-- the first output starts at the highest index, whereas
-- the stored register values start at the lowest index
output(output'length-data_width*i-1 downto output'length-data_width*(i+1)) <= regs(index);
-- align the output valid bits;
valid_out_s(i) <= valid(index);
else
output((i+1)*data_width-1 downto i*data_width) <= regs(index);
valid_out_s(parallel_io-i-1) <= valid(index);
end if;
end loop;
end process;
process(clk, rst)
begin
if (rst = '1') then
for i in 0 to parallel_io*2-1 loop
regs(i) <= (others => '0');
valid(i) <= '0';
end loop;
front <= 0;
elsif (rising_edge(clk)) then
-- during a read, slide the front of the window so the next output
-- is aligned properly.
if (valid_rd = '1') then
if (window_reset = '0') then
front <= front + rd_amount_s;
else
front <= front + rd_amount_s - parallel_io;
end if;
end if;
-- check if the bottom half is empty. All parallel_io valid bits
-- of each half should be the same, so only the first bit has to be
-- checked
if (valid(0) = '0' or
(valid_rd = '1' and window_reset = '1')) then
-- move the top half to the bottom.
for i in 0 to parallel_io-1 loop
regs(i) <= regs(i+parallel_io);
valid(i) <= valid(i+parallel_io);
end loop;
-- reset the valid bits for the top half
for i in parallel_io to parallel_io*2-1 loop
valid(i) <= '0';
end loop;
end if;
-- write new data to the top half of buffer
if (valid_wr = '1') then
for i in 0 to parallel_io-1 loop
regs(i+parallel_io) <= inputs(i);
valid(i+parallel_io) <= '1';
end loop;
end if;
end if;
end process;
end DEFAULT;
| gpl-3.0 | 52515e3ff88e16ac258d35e5f9a53a64 | 0.56834 | 4.075699 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/memory/src/dpRamSplx-e.vhd | 3 | 3,791 | -------------------------------------------------------------------------------
--! @file dpRamSplx-e.vhd
--
--! @brief Simplex Dual Port Ram Entity
--
--! @details This is the Simplex DPRAM entity.
--! The DPRAM has one write and one read port only.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity dpRamSplx is
generic (
--! Word width port A [bit]
gWordWidthA : natural := 16;
--! Byteenable width port A [bit]
gByteenableWidthA : natural := 2;
--! Number of words (reference is port A)
gNumberOfWordsA : natural := 1024;
--! Word width port B [bit]
gWordWidthB : natural := 32;
--! Number of words (reference is port B)
gNumberOfWordsB : natural := 512;
--! Initialization file
gInitFile : string := "UNUSED"
);
port (
-- PORT A
--! Clock of port A
iClk_A : in std_logic;
--! Enable of port A
iEnable_A : in std_logic;
--! Write enable of port A
iWriteEnable_A : in std_logic;
--! Address of port A
iAddress_A : in std_logic_vector(logDualis(gNumberOfWordsA)-1 downto 0);
--! Byteenable of port A
iByteenable_A : in std_logic_vector(gByteenableWidthA-1 downto 0);
--! Writedata of port A
iWritedata_A : in std_logic_vector(gWordWidthA-1 downto 0);
-- PORT B
--! Clock of port B
iClk_B : in std_logic;
--! Enable of port B
iEnable_B : in std_logic;
--! Address of port B
iAddress_B : in std_logic_vector(logDualis(gNumberOfWordsB)-1 downto 0);
--! Readdata of port B
oReaddata_B : out std_logic_vector(gWordWidthB-1 downto 0)
);
end dpRamSplx;
| gpl-2.0 | 3385e494ca8acb75d41b6cb2234afb76 | 0.598523 | 4.561974 | false | false | false | false |
beltagymohamed/FIR-Filter-using-adders-to-meet-tight-constraints-VHDL | fir_sol.vhd | 1 | 5,180 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
library work;
use work.array_t.all;
entity fir_sol is
Port (
Reset : in STD_LOGIC;
Clk : in STD_LOGIC;
Input : in array32_t(0 to 9);
Output : out STD_LOGIC_VECTOR (31 downto 0)
);
end fir_sol;
architecture Structural of fir_sol is
-- adding the components to the Design --
component adder
Port ( A : in STD_LOGIC_VECTOR (31 downto 0);
B : in STD_LOGIC_VECTOR (31 downto 0);
O : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component reg
Port ( Reset : in STD_LOGIC;
Clk : in STD_LOGIC;
Load : in STD_LOGIC;
Din : in STD_LOGIC_VECTOR (31 downto 0);
Dout : out STD_LOGIC_VECTOR (31 downto 0));
end component;
signal mout : array32_t(0 to 30);-- just a big array i will use as much as i need from it , for the first one i will use from 0to 2 and for the second input i will use fro 3to 5 and like that a multiples of 3
signal aout : array32_t(0 to 25);
begin
-- the equivlant to multiplication of X(0)*b(0) where b(0) = 3 which is 11 in binary that mean shift X(0) by two and add to X(0)
--std_logic_vector(unsigned(inputA) srl to_integer(unsigned(inputB)));
mout(1)<=std_logic_vector(unsigned(Input(0)) sll 1);
add0: adder port map (
A => mout(1),
B => Input(0),
O => aout(0)
);
-- the same for a(1)but with 23 = 11001 left shift by 3 and 4 and 0
mout(3)<=std_logic_vector(unsigned(Input(1)) sll 3);
mout(4)<=std_logic_vector(unsigned(Input(1)) sll 4);
add1: adder port map (
A => mout(3),
B => mout(4),
O => mout(5)
);
add2: adder port map (
A => mout(5),
B => Input(1),
O => aout(1)
);
-- the same for a(2)but with 96 = 110 0000 left shift by 5 and 6
mout(6)<=std_logic_vector(unsigned(Input(2)) sll 5);
mout(7)<=std_logic_vector(unsigned(Input(2)) sll 6);
add3: adder port map (
A => mout(6),
B => mout(7),
O => aout(2)
);
-- the same for a(3)but with 384 = 1 1000 0000 left shift by 7 and 8
mout(9)<=std_logic_vector(unsigned(Input(3)) sll 7);
mout(10)<=std_logic_vector(unsigned(Input(3)) sll 8);
add4: adder port map (
A => mout(9),
B => mout(10),
O => aout(3)
);
-- the same for a(4)but with 3073 = 1100 0000 0001 left shift by 10 and 11 and add a(4)
mout(12)<=std_logic_vector(unsigned(Input(4)) sll 10);
mout(13)<=std_logic_vector(unsigned(Input(4)) sll 11);
add5: adder port map (
A => mout(12),
B => mout(13),
O => mout(14)
);
add6: adder port map (
A => mout(14),
B => Input(4),
O => aout(4)
);
-- the same for a(5)but with 3073 = 1100 0000 0001 left shift by 10 and 11 and add a(5)
mout(15)<=std_logic_vector(unsigned(Input(5)) sll 10);
mout(16)<=std_logic_vector(unsigned(Input(5)) sll 11);
add7: adder port map (
A => mout(15),
B => mout(16),
O => mout(17)
);
add8: adder port map (
A => mout(17),
B => Input(5),
O => aout(5)
);
-- the same for a(6)but with 384 = 1 1000 0000 left shift by 7 and 8
mout(18)<=std_logic_vector(unsigned(Input(6)) sll 7);
mout(19)<=std_logic_vector(unsigned(Input(6)) sll 8);
add9: adder port map (
A => mout(18),
B => mout(19),
O => aout(6)
);
-- the same for a(7)but with 96 = 110 0000 left shift by 5 and 6
mout(21)<=std_logic_vector(unsigned(Input(7)) sll 5);
mout(22)<=std_logic_vector(unsigned(Input(7)) sll 6);
add10: adder port map (
A => mout(21),
B => mout(22),
O => aout(7)
);
-- the same for a(8)but with 25 = 11001 left shift by 3 and 4 and 0
mout(24)<=std_logic_vector(unsigned(Input(8)) sll 3);
mout(25)<=std_logic_vector(unsigned(Input(8)) sll 4);
add11: adder port map (
A => mout(24),
B => mout(25),
O => mout(26)
);
add112: adder port map (
A => mout(26),
B => Input(8),
O => aout(8)
);
-- the same for a(9)but with 3 = 11 left shift by 1 and 0
mout(27)<=std_logic_vector(unsigned(Input(9)) sll 1);
add12: adder port map (
A => mout(27),
B => Input(9),
O => aout(9)
);
---adding the whole results
add13: adder port map (
A => aout(0),
B => aout(1),
O => aout(10)
);
add14: adder port map (
A => aout(2),
B => aout(3),
O => aout(11)
);
add15: adder port map (
A => aout(4),
B => aout(5),
O => aout(12)
);
add115: adder port map (
A => aout(6),
B => aout(7),
O => aout(13)
);
add16:adder port map (
A => aout(8),
B => aout(9),
O => aout(14)
);
add117: adder port map (
A => aout(10),
B => aout(11),
O => aout(15)
);
add118: adder port map (
A => aout(12),
B => aout(13),
O => aout(16)
);
add17: adder port map (
A => aout(15),
B => aout(16),
O => aout(17)
);
add18: adder port map (
A => aout(14),
B => aout(17),
O => aout(18)
);
reg3:reg port map (
Reset => Reset,
Clk => Clk ,
Load =>'1',
Din => aout(18),
Dout => aout(20)
);
Output<=aout(20);
end Structural;
| mit | ab1967d9bf57117dee4c31c0bf24e089 | 0.562355 | 2.702139 | false | false | false | false |
cnplab/blockmon | fw-combo/src/CBF/timer.vhd | 1 | 1,320 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity timer is
port ( clock : in std_logic;
reset : in std_logic;
TIMEDEC: in std_logic_vector(31 downto 0);
decrement: out std_logic
);
end timer;
architecture Behavioral of timer is
signal timestampL: STD_LOGIC_VECTOR (7 downto 0);
signal timestampH: STD_LOGIC_VECTOR (31 downto 0);
begin
timestamp : process (clock, reset)
begin
if reset = '1' then
timestampL <= (others =>'0');
timestampH <= (others =>'0');
decrement <='0';
elsif clock'event and clock = '1' then
timestampL <= timestampL +'1';
if timestampL=x"7D" then --ogni 125 colpi di clock
timestampL<=x"00";
timestampH<=timestampH+1; --quindi timestampH conta i micro-secondi
end if;
if (timestampL=x"7D") and (timestampH = TIMEDEC) then
timestampH<=(others =>'0');
end if;
if (timestampL=x"7D") and (timestampH = TIMEDEC) and (TIMEDEC/=x"00000000") then
decrement<='1';
else
decrement<='0';
end if; -- decremento ogni 1024*1024 micro secondi
end if;
end process;
end Behavioral;
| bsd-3-clause | 37971244b5ca202b8ae59079da864258 | 0.575 | 3.75 | false | false | false | false |
cnplab/blockmon | fw-combo/src/IPFIX/comp/dec1fn2b.vhd | 1 | 3,393 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
--
-- dec1fn_enable.vhd: Decoder 1 from n with ENABLE
-- Copyright (C) 2007 CESNET
-- Author(s): Martin Kosek <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
--
-- TODO:
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use work.math_pack.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity dec1fn2b is
generic(
ITEMS : integer := 8
);
port(
ADDR : out std_logic_vector(log2(ITEMS)-1 downto 0);
ENABLE : in std_logic;
DI : in std_logic_vector(ITEMS-1 downto 0)
);
end entity dec1fn2b;
-- ----------------------------------------------------------------------------
-- Architecture declaration
-- ----------------------------------------------------------------------------
architecture behavioral of dec1fn2b is
begin
process(DI, ENABLE)
begin
ADDR <= (others => '0');
if ENABLE = '1' then
for i in 0 to (ITEMS-1) loop
if (DI(i) = '1') then
ADDR <= conv_std_logic_vector(i, log2(ITEMS));
end if;
end loop;
end if;
end process;
end architecture behavioral;
| bsd-3-clause | ea00f38aa0027f8fb155430563fb969a | 0.579723 | 4.585135 | false | false | false | false |
cnplab/blockmon | fw-combo/src/CBF/CBFBase.vhd | 1 | 12,683 | --ENTITY of filter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.utils.ALL;
entity CBFfilter is
Port(
clock : in STD_LOGIC;
reset : in STD_LOGIC;
src_ip : in STD_LOGIC_VECTOR(31 downto 0);
dst_ip : in STD_LOGIC_VECTOR(31 downto 0);
src_port : in STD_LOGIC_VECTOR(15 downto 0);
dst_port : in STD_LOGIC_VECTOR(15 downto 0);
decrement : in STD_LOGIC;
start : in STD_LOGIC;
Address_CBF_dump : in STD_LOGIC_VECTOR (10 downto 0);
dump : in STD_LOGIC;
Threshold : in STD_LOGIC_VECTOR (31 downto 0);
Data_CBF_dump : out STD_LOGIC_VECTOR (31 downto 0);
osip : out STD_LOGIC_VECTOR(31 downto 0); -- SRC IP of the last flow over the threshold
odip : out STD_LOGIC_VECTOR(31 downto 0); -- DST IP of the last flow over the threshold
oport : out STD_LOGIC_VECTOR(31 downto 0); -- SRC & DST PORT of the last flow over the threshold
counter_item : out STD_LOGIC_VECTOR(31 downto 0);
max_sip : out STD_LOGIC_VECTOR(31 downto 0); -- SRC IP of the biggest flow
max_dip : out STD_LOGIC_VECTOR(31 downto 0); -- DST IP of the biggest flow
max_port : out STD_LOGIC_VECTOR(31 downto 0); -- SRC & DST PORT of the biggest flow
max_count : out STD_LOGIC_VECTOR(31 downto 0);
counter_overflow : out STD_LOGIC_VECTOR(31 downto 0)
);
end CBFfilter;
--ARCHITECTURE of filter
architecture Behavioral of CBFfilter is
type stato_filtro is (IDLE,CLEAN,ZERO_CLEAN,READ0,READ1,READ2,READ3,LAST_READ,WRITE0,WRITE1,DEC0,DEC1,DEC2,DUMP_STATE);
type HH is array(3 downto 0) of STD_LOGIC_VECTOR (10 downto 0);
type ADDR is array(3 downto 0) of STD_LOGIC_VECTOR (10 downto 0);
type CV is array(3 downto 0) of STD_LOGIC_VECTOR (15 downto 0);
type CBF is array(2047 downto 0) of STD_LOGIC_VECTOR (15 downto 0); --2048 count;
signal max_val : STD_LOGIC_VECTOR(15 downto 0); -- the value of the bigger flow
signal flow : STD_LOGIC_VECTOR(95 downto 0); -- the flow currently examined
signal int_counter_item : STD_LOGIC_VECTOR(31 downto 0); -- counts the total number of stored item
signal int_counter_overflow : STD_LOGIC_VECTOR(31 downto 0); -- count the number of overflows
signal H : HH; -- vector of hash values
signal addr_w : ADDR; -- vector of address to be updated
signal count_val : STD_LOGIC_VECTOR (15 downto 0); -- value of the counter for the current flow
signal countBF : CBF; -- memory of the CBF
signal Htot_UNI : STD_LOGIC_VECTOR (43 downto 0); -- total hash
signal stato : stato_filtro; -- FSM curent state
signal n_val : STD_LOGIC_VECTOR (2 downto 0); -- number of conter to be updated
signal decrementing : STD_LOGIC; -- the CBF is in decrementing
signal write_enable : STD_LOGIC; -- write to the CBF RAM
signal overflow : STD_LOGIC; -- checks if the current flow is over the threshold
signal HADDR : STD_LOGIC_VECTOR (10 downto 0); -- address for the CBF memory
signal HCOUNT_VAL_TRF : STD_LOGIC_VECTOR (15 downto 0); -- HCOUNT_VAL_ToReadFrom
signal HCOUNT_VAL_TWI : STD_LOGIC_VECTOR (15 downto 0); -- HCOUNT_VAL_ToWriteInto
signal i : integer range 0 to 2047;
signal j : integer range 0 to 2047;
signal k : integer range 0 to 2047;
signal w : integer range 0 to 3;
signal input_hash : STD_LOGIC_VECTOR(131 downto 0);
begin
counter_item<= int_counter_item;
counter_overflow<= int_counter_overflow;
input_hash<= x"f2a650193" & src_ip & dst_ip & src_port & dst_port;
-------------------------------------------
-- computing hash using ror and xor
-------------------------------------------
Htot_UNI <= (myror(input_hash(131 downto 88),11)) xor (myror(input_hash(87 downto 44), 7)) xor input_hash(43 downto 0);
--Htot_UNI <= (input_hash(131 downto 88) ror 11) xor (input_hash(87 downto 44) ror 7) xor input_hash(43 downto 0);
process (clock, reset)
begin
if reset = '1' then
flow<= (others =>'0');
elsif clock' event and clock='1' then
if start = '1' then
flow<= src_ip & dst_ip & src_port & dst_port;
end if;
end if;
end process;
process (clock, reset)
begin
if reset = '1' then
write_enable <= '0';
HCOUNT_VAL_TRF <= (others => '0');
addr_w(0) <= (others => '0');
addr_w(1) <= (others => '0');
addr_w(2) <= (others => '0');
addr_w(3) <= (others => '0');
count_val <= (others => '0');
H(0) <= (others => '0');
H(1) <= (others => '0');
H(2) <= (others => '0');
H(3) <= (others => '0');
n_val <= (others => '0');
stato <= ZERO_CLEAN;
decrementing <= '0';
overflow <= '0';
osip <= (others => '0');
odip <= (others => '0');
oport <= (others => '0');
int_counter_overflow <= (others => '0');
int_counter_item<= (others => '0');
i <= 0;
elsif clock' event and clock='1' then
if decrement='1' and stato /= CLEAN then
decrementing <= '1';
end if;
write_enable <= '0';
if start = '1' and stato /= CLEAN then
H(0) <= Htot_UNI(10 downto 0);
H(1) <= Htot_UNI(21 downto 11);
H(2) <= Htot_UNI(32 downto 22);
H(3) <= Htot_UNI(43 downto 33);
-- conta il numero di item inserite nel CBF
int_counter_item<= int_counter_item +1;
stato <= READ0;
end if;
--------------------------------------
-- Stati di reset dei contatori
--- stati ZERO_CLEAN e CLEAN
--------------------------------------
if stato = ZERO_CLEAN then --"01111"
i <= 0;
write_enable <= '1';
HCOUNT_VAL_TRF <= (others => '0');
stato <= CLEAN;
end if;
if stato = CLEAN then --"11111"
if i <= 2046 then
i <= i + 1;
HCOUNT_VAL_TRF <= (others => '0');
write_enable <= '1';
else
stato <= IDLE; --"01110"
write_enable <= '0';
i <= 0;
end if;
end if;
--------------------------------------
-- Stati di lettura dei contatori
--- stato >= 0 e <= 4
--------------------------------------
if stato = READ0 then
--HADDR <= H(0);
stato <= READ1;
end if;
if stato = READ1 then
--HADDR <= H(1);
stato <= READ2;
count_val <= HCOUNT_VAL_TWI;
addr_w(0) <= H(0);
n_val <= "001";
if(HCOUNT_VAL_TWI >= Threshold) then
overflow <= '1';
else
overflow <= '0';
end if;
end if;
if stato = READ2 then
stato <= READ3;
--HADDR <= H(2);
--count_val <= HCOUNT_VAL_TWI;
if(HCOUNT_VAL_TWI < Threshold) then
overflow <= '0';
end if;
--multiple counters with value = TWI
if count_val = HCOUNT_VAL_TWI then
addr_w(1) <= H(1);
n_val <= "010";
end if;
--this counter has the minimum value
if count_val > HCOUNT_VAL_TWI then
count_val <= HCOUNT_VAL_TWI;
addr_w(0) <= H(1);
n_val <= "001";
end if;
end if;
if stato = READ3 then
stato <= LAST_READ;
--HADDR <= H(3);
if(HCOUNT_VAL_TWI < Threshold) then
overflow <= '0';
end if;
--multiple counters with value = TWI
if count_val = HCOUNT_VAL_TWI then
if n_val = "001" then
addr_w(1) <= H(2);
n_val <= "010";
end if;
if n_val = "010" then
addr_w(2) <= H(2);
n_val <= "011";
end if;
end if;
--this counter has the minimum value
if count_val > HCOUNT_VAL_TWI then
count_val <= HCOUNT_VAL_TWI;
addr_w(0) <= H(2);
n_val <= "001";
end if;
end if;
--stop letture ed ultimo confronto
if stato = LAST_READ then
j <= 0;
stato <= WRITE0;
if(HCOUNT_VAL_TWI < Threshold) then
overflow <= '0';
end if;
--multiple counters with value = TWI
if count_val = HCOUNT_VAL_TWI then
if n_val = "001" then
addr_w(1) <= H(3);
n_val <= "010";
end if;
if n_val = "010" then
addr_w(2) <= H(3);
n_val <= "011";
end if;
if n_val = "011" then
addr_w(3) <= H(3);
n_val <= "100";
end if;
end if;
--this counter has the minimum value
if count_val > HCOUNT_VAL_TWI then
count_val <= HCOUNT_VAL_TWI;
addr_w(0) <= H(3);
n_val <= "001";
end if;
end if;
--------------------------------------
-- Stati di scrittura dei contatori
--- stato = 5,21
--------------------------------------
if stato = WRITE0 then
stato <= WRITE1; --"10101";
HCOUNT_VAL_TRF <= count_val + 1;
j <= 0; --number of counters to be incremented
write_enable <= '1';
if (count_val+1)>max_val then
max_val<=count_val+1;
max_sip<=flow(95 downto 64); --src_ip
max_dip<=flow(63 downto 32); --dst_ip;
max_port<=flow(31 downto 0); --src_port & dst_port;
max_count<=x"0000"&(count_val+1);
end if;
if(overflow = '1') then
--stato <= IDLE; -- go to IDLE only for saturate behaviour
--conta il numero di overflow
int_counter_overflow <= int_counter_overflow + 1;
-- store the flow over the threshold
osip<=flow(95 downto 64); --src_ip
odip<=flow(63 downto 32); --dst_ip;
oport<=flow(31 downto 0); --src_port & dst_port;
report "overflow src ip: " & integer'image(conv_integer(src_ip(31 downto 24))) & "." &
integer'image(conv_integer(src_ip(23 downto 16))) & "." &
integer'image(conv_integer(src_ip(15 downto 8))) & "." &
integer'image(conv_integer(src_ip(7 downto 0))) & LF ;
report "overflow dst ip: " & integer'image(conv_integer(dst_ip(31 downto 24))) & "." &
integer'image(conv_integer(dst_ip(23 downto 16))) & "." &
integer'image(conv_integer(dst_ip(15 downto 8))) & "." &
integer'image(conv_integer(dst_ip(7 downto 0))) & LF ;
report "overflow src port " & integer'image(conv_integer(src_port)) & LF ;
report "overflow dst port " & integer'image(conv_integer(dst_port)) & LF ;
--elsif(overflow=0)
-- here increment only if the value are below the Threshold, otherwise the counters saturate
--stato <= WRITE1; --"10101";
--HCOUNT_VAL_TRF <= count_val + 1;
--j <= 0; --number of counters to be incremented
--write_enable <= '1';
end if;
end if;
if stato = WRITE1 then
stato <= WRITE1;
--loop for all the conunters(n_val) to be incremented
if(j+1 < conv_integer(n_val)) then
HCOUNT_VAL_TRF <= count_val + 1;
j <= j + 1;
write_enable <= '1';
else
stato <= IDLE; --"01110";
j <= 0;
write_enable <= '0';
end if;
end if;
--IDLE STATE
if stato = IDLE then --"01110"
overflow <= '0';
write_enable <= '0';
if decrementing = '1' then
if i <= 2046 then
i <= i + 1;
stato <= DEC0;
else
decrementing<= '0';
stato <= IDLE; -- "01110";
i <= 0;
end if;
elsif dump='1' then
stato <= DUMP_STATE;
end if;
end if;
if stato = DUMP_STATE then
if dump='0' then
stato <= IDLE;
end if;
end if;
--decrementing state
if stato = DEC0 then
stato <= DEC1;
write_enable <= '0';
end if;
if stato = DEC1 then
stato <= DEC2;
if(conv_integer(HCOUNT_VAL_TWI) > 0) then
write_enable <= '1';
HCOUNT_VAL_TRF <= HCOUNT_VAL_TWI - 1;
end if;
end if;
--needed to write decremented value on the CBF
if stato = DEC2 then
write_enable <= '0';
stato <= IDLE; -- "01110";
end if;
end if;
end process;
HADDR <=H(0) when stato=READ0 else
H(1) when stato=READ1 else
H(2) when stato=READ2 else
H(3) when stato=READ3 else
addr_w(j) when stato=LAST_READ else
addr_w(j) when stato=WRITE0 else
addr_w(j) when stato=WRITE1 else
Address_CBF_dump when stato=DUMP_STATE else
Address_CBF_dump when stato=IDLE and dump='1' else -- hack:when dump=1 and IDLE risparmia un cilo ci clock
conv_std_logic_vector(i,11);
--with stato select
--HADDR <=H(0) when READ0,
--H(1) when READ1,
--H(2) when READ2,
--H(3) when READ3,
--addr_w(j) when LAST_READ,
--addr_w(j) when WRITE0,
--addr_w(j) when WRITE1,
--Address_CBF_dump when DUMP_STATE, -- hack:when dump=1 and IDLE risparmia un cilo ci clock
--conv_std_logic_vector(i,11) when others;
process(clock)
begin
if clock'event and clock = '1' then
HCOUNT_VAL_TWI <= countBF(conv_integer(HADDR));
if (write_enable = '1') then
countBF(conv_integer(HADDR)) <= HCOUNT_VAL_TRF;
HCOUNT_VAL_TWI <= HCOUNT_VAL_TRF; -- needed to synth block RAM
end if;
end if;
end process;
------------------------------
-- forniamo il valore memorizzato dal CBF per l'operazione di DUMP
Data_CBF_dump<= x"0000" & HCOUNT_VAL_TWI;
end Behavioral;
| bsd-3-clause | 172e8b41c1f07da5fbf15d33a48bc5ee | 0.570764 | 2.955721 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/openmac/src/mmSlaveConv-rtl-ea.vhd | 3 | 13,904 | -------------------------------------------------------------------------------
--! @file mmSlaveConv-rtl-ea.vhd
--
--! @brief Memory mapped slave interface converter
--
--! @details The slave interface converter is fixed to a 16 bit memory mapped
--! slave, connected to a 32 bit master. The conversion also considers
--! little/big endian (gEndian).
--! Note: Tested with openmacTop entity only!
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity mmSlaveConv is
generic (
--! Endianness of interconnect
gEndian : string := "little";
--! Memory mapped master address width
gMasterAddrWidth : natural := 10
);
port (
--! Reset
iRst : in std_logic;
--! Clock
iClk : in std_logic;
-- Memory mapped master input
--! Master select
iMaster_select : in std_logic;
--! Master write
iMaster_write : in std_logic;
--! Master read
iMaster_read : in std_logic;
--! Master byteenable
iMaster_byteenable : in std_logic_vector(3 downto 0);
--! Master writedata
iMaster_writedata : in std_logic_vector(31 downto 0);
--! Master readdata
oMaster_readdata : out std_logic_vector(31 downto 0);
--! Master address (byte address)
iMaster_address : in std_logic_vector(gMasterAddrWidth-1 downto 0);
--! Master write acknowledge
oMaster_WriteAck : out std_logic;
--! Master read acknowledge
oMaster_ReadAck : out std_logic;
-- Memory mapped slave output
--! Slave select
oSlave_select : out std_logic;
--! Slave write
oSlave_write : out std_logic;
--! Slave read
oSlave_read : out std_logic;
--! Slave address (word address)
oSlave_address : out std_logic_vector(gMasterAddrWidth-1 downto 0);
--! Slave byteenable
oSlave_byteenable : out std_logic_vector(1 downto 0);
--! Slave readdata
iSlave_readdata : in std_logic_vector(15 downto 0);
--! Slave writedata
oSlave_writedata : out std_logic_vector(15 downto 0);
--! Slave acknowledge
iSlave_ack : in std_logic
);
end mmSlaveConv;
architecture rtl of mmSlaveConv is
--! Access fsm_reg type
type tAccessFsm is (
sIdle,
sDoAccess
);
--! Access type
type tAccess is (
sNone,
sDword,
sWord
);
--! Access fsm_reg current state
signal fsm_reg : tAccessFsm;
--! Access fsm_reg next state
signal fsm_next : tAccessFsm;
--! Current master access type
signal masterAccess : tAccess;
--! Counter width
constant cCounterWidth : natural := 2;
--! Counter register
signal counter_reg : std_logic_vector(cCounterWidth-1 downto 0);
--! Next counter register
signal counter_next : std_logic_vector(cCounterWidth-1 downto 0);
--! Counter register load value
signal counter_loadValue : std_logic_vector(cCounterWidth-1 downto 0);
--! Load counter register with counter_loadValue
signal counter_load : std_logic;
--! Decrement counter value by one
signal counter_decrement : std_logic;
--! counter_reg is zero
signal counter_isZero : std_logic;
--! counter_reg is one
signal counter_isOne : std_logic;
--! counter_reg is two
signal counter_isTwo : std_logic;
--! Master acknowledge
signal masterAck : std_logic;
--! Register to store slave readdata word
signal wordStore_reg : std_logic_vector(iSlave_readdata'range);
--! Next value of slave readdata word register
signal wordStore_next : std_logic_vector(wordStore_reg'range);
begin
---------------------------------------------------------------------------
-- Assign outputs
---------------------------------------------------------------------------
oSlave_select <= iMaster_select;
oSlave_write <= iMaster_write and iMaster_select;
oSlave_read <= iMaster_read and iMaster_select;
oMaster_WriteAck <= masterAck and iMaster_write and iMaster_select;
oMaster_ReadAck <= masterAck and iMaster_read and iMaster_select;
--! This process assigns the master readdata port controlled by the current
--! conversion state.
assignMasterPath : process (
iSlave_readdata, wordStore_reg,
masterAccess
)
begin
if masterAccess = sDword then
oMaster_readdata <= iSlave_readdata & wordStore_reg;
else
oMaster_readdata <= iSlave_readdata & iSlave_readdata;
end if;
end process assignMasterPath;
--! This process assigns the slave address, byteenable and writedata controlled
--! by the current conversion state.
assignSlavePath : process (
iMaster_address, iMaster_byteenable, iMaster_writedata,
counter_reg, counter_isOne,
masterAccess
)
begin
-----------------------------------------------------------------------
-- Slave address
-----------------------------------------------------------------------
--default assignment
oSlave_address <= iMaster_address;
if masterAccess = sDword then
case to_integer(unsigned(counter_reg)) is
when 0 | 2 =>
-- First word of dword access
if gEndian = "little" then
oSlave_address(1) <= cInactivated;
else
oSlave_address(1) <= cActivated;
end if;
when 1 =>
-- Second word of dword access
if gEndian = "little" then
oSlave_address(1) <= cActivated;
else
oSlave_address(1) <= cInactivated;
end if;
when others =>
null; --allowed due to default assignment
end case;
end if;
-----------------------------------------------------------------------
-- Slave byteenable
-----------------------------------------------------------------------
if masterAccess = sDword then
oSlave_byteenable <= (others => cActivated);
else
oSlave_byteenable <= iMaster_byteenable(3 downto 2) or iMaster_byteenable(1 downto 0);
end if;
-----------------------------------------------------------------------
-- Slave writedata
-----------------------------------------------------------------------
if (masterAccess = sDword and counter_isOne = cActivated) or iMaster_address(1) = cActivated then
oSlave_writedata <= iMaster_writedata(31 downto 16);
else
oSlave_writedata <= iMaster_writedata(15 downto 0);
end if;
end process assignSlavePath;
--! This process assigns the registers.
regProc : process(iRst, iClk)
begin
if iRst = cActivated then
counter_reg <= (others => cInactivated);
fsm_reg <= sIdle;
wordStore_reg <= (others => cInactivated);
elsif rising_edge(iClk) then
counter_reg <= counter_next;
fsm_reg <= fsm_next;
wordStore_reg <= wordStore_next;
end if;
end process;
--! This process assigns the register next signals.
assignRegNext : process (
iSlave_readdata, iSlave_ack,
wordStore_reg, fsm_reg, counter_reg,
counter_load, counter_loadValue, counter_decrement, counter_isZero,
counter_isTwo, masterAccess
)
begin
-- default assignments
wordStore_next <= wordStore_reg;
fsm_next <= fsm_reg;
counter_next <= counter_reg;
-----------------------------------------------------------------------
-- Counter
-----------------------------------------------------------------------
if counter_load = cActivated then
counter_next <= counter_loadValue;
elsif counter_decrement = cActivated and masterAccess = sDword then
counter_next <= std_logic_vector(unsigned(counter_reg) - 1);
end if;
-----------------------------------------------------------------------
-- Access FSM
-----------------------------------------------------------------------
if counter_isZero = cActivated then
case fsm_reg is
when sIdle =>
if masterAccess = sDword then
fsm_next <= sDoAccess;
end if;
when sDoAccess =>
if masterAccess = sNone then
fsm_next <= sIdle;
end if;
end case;
end if;
-----------------------------------------------------------------------
-- Store slave readdata word
-----------------------------------------------------------------------
if iSlave_ack = cActivated and masterAccess = sDword and counter_isTwo = cActivated then
wordStore_next <= iSlave_readdata;
end if;
end process assignRegNext;
counter_decrement <= iSlave_ack and iMaster_select;
--! This process assigns internal control signals.
assignInternal : process (
iSlave_ack,
iMaster_select, iMaster_byteenable, iMaster_read,
counter_reg, counter_isOne, masterAccess, fsm_reg, fsm_next
)
begin
-----------------------------------------------------------------------
-- Master acknowledge
-----------------------------------------------------------------------
if iSlave_ack = cActivated and masterAccess = sDword and counter_isOne = cActivated then
masterAck <= cActivated;
elsif iSlave_ack = cActivated and masterAccess = sWord then
masterAck <= cActivated;
else
masterAck <= cInactivated;
end if;
-----------------------------------------------------------------------
-- Master access state
-----------------------------------------------------------------------
if iMaster_select = cInactivated then
masterAccess <= sNone;
elsif iMaster_byteenable = "1111" then
masterAccess <= sDword;
else
masterAccess <= sWord;
end if;
-----------------------------------------------------------------------
-- Counter
-----------------------------------------------------------------------
--default
counter_isZero <= cInactivated;
counter_isOne <= cInactivated;
counter_isTwo <= cInactivated;
-- assign counter_is* signals
case to_integer(unsigned(counter_reg)) is
when 0 =>
counter_isZero <= cActivated;
when 1 =>
counter_isOne <= cActivated;
when 2 =>
counter_isTwo <= cActivated;
when others =>
null; --is allowed due to default assignment
end case;
-- assign counter load
if fsm_next = sDoAccess and fsm_reg = sIdle then
counter_load <= cActivated;
else
counter_load <= cInactivated;
end if;
-- assign counter load value
if iMaster_byteenable = "1111" and iMaster_read = cActivated then
counter_loadValue <= "10";
else
counter_loadValue <= "01";
end if;
end process assignInternal;
end rtl;
| gpl-2.0 | 5353fb18c71e971bf9489ac36a99bf1c | 0.510357 | 5.376643 | false | false | false | false |
ARC-Lab-UF/window_gen | src/wg_coalescer.vhd | 1 | 10,849 | -- Copyright (c) University of Florida
--
-- This file is part of window_gen.
--
-- window_gen is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- window_gen is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with window_gen. If not, see <http://www.gnu.org/licenses/>.
-- Greg Stitt
-- Patrick Cooke
-- University of Florida
-- Description: This entity accepts a sequence of window columns and coalesces
-- them into a complete window(s). The entity implements a set of shift
-- registers equal to the size of a window. The wg_coalescer reads the next
-- columns of multiple rows, shifts the previous values over, and stores the
-- next data to generate a new window. In other words, this entity slides the
-- window by one column at a time while reusing previous data. The inputs and
-- outputs are "first-word fall through" so that the next window(s) is output
-- before ren is asserted. ren basically pops the current window(s) from the
-- buffer.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.math_custom.all;
use work.window_gen_pkg.all;
-------------------------------------------------------------------------------
-- Generics Description
-- PARALLEL_IO : Specifies the number of input columns provided at a time,
-- which also defines the maximum number of windows output
-- from the entity.
-- NUM_ROWS : The maximum number of rows in a generated window
-- NUM_COLS : The maximum number of cols in a generated window
-- DATA_WIDTH : The width in bits of each element.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Port Descriptions (all control signals are active high)
-- clk: clock
-- rst: asynchronous reset
-- ren : '1' to pop window(s) from buffer
-- read_input : informs the source of the stream that the entity is accepting
-- data
-- empty : '1' when the entity has no valid window output, '0' otherwise
-- input : the current column(s) of input. The exact number of columns is
-- specified by the configuration option PARALLEL_IO.
-- input_ready : specifies when "input" is valid
-- input_done : '1' when all inputs have been passed to the entity
-- is_edge : '1' if the current input is the starting (left) edge/column of a
-- window. One bit for each of PARALLEL_IO input columns.
-- output : PARALLEL_IO window(s)
-- window_valid : '1' when an output window is valid, '0' otherwise. One bit
-- for each of the PARALLEL_IO windows. The next window in the
-- output sequence is always represented by the MSB. The window
-- that is PARALLEL_IO-1 windows away in the sequence is
-- represented by the LSB.
-- done : '1' when the coalescer has created all windows after input_done is
-- asserted. Note that the coalescer these windows have not
-- necessarily been read by the user yet.
-------------------------------------------------------------------------------
entity wg_coalescer is
generic (
PARALLEL_IO : positive;
NUM_ROWS : positive;
NUM_COLS : positive;
DATA_WIDTH : positive);
port (
clk : in std_logic;
rst : in std_logic;
ren : in std_logic;
read_input : out std_logic;
empty : out std_logic;
input : in std_logic_vector(NUM_ROWS*PARALLEL_IO*DATA_WIDTH-1 downto 0);
input_ready : in std_logic;
input_done : in std_logic;
is_edge : in std_logic_vector(PARALLEL_IO-1 downto 0);
output : out std_logic_vector(NUM_ROWS*(NUM_COLS+PARALLEL_IO-1)*DATA_WIDTH-1 downto 0);
window_valid : out std_logic_vector(PARALLEL_IO-1 downto 0);
done : out std_logic);
end wg_coalescer;
architecture RTL of wg_coalescer is
-------------------------------------------------------------------------
-- constants and types
-- the buffer increases the number of columns to the next multiple of
-- PARALLEL_IO to ensure that new writes don't overlap with existing data
constant BUFFER_COLS : positive := positive(ceil(real(NUM_COLS+PARALLEL_IO-1)/real(PARALLEL_IO)))*PARALLEL_IO;
-- The number of output columns has to account for the extra windows when
-- PARALLEL_IO > 1
constant OUTPUT_COLS : positive := NUM_COLS+PARALLEL_IO-1;
-- array used to store PARALLEL_IO inputs from each row of the fifo array
-- (i.e. window buffer)
type input_array_t is array (0 to NUM_ROWS-1, 0 to PARALLEL_IO-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
-- 2D array that stores PARALLEL_IO windows in addition to the next
-- PARALLEL_IO inputs
type rbuf is array (integer range 0 to NUM_ROWS-1, integer range 0 to BUFFER_COLS-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
-------------------------------------------------------------------------
-- Functions for converting I/O to/from vector/array format
-- Converts vectorized input into 2D array
function devectorizeInput(input : std_logic_vector) return input_array_t is
variable temp : input_array_t;
begin
for i in NUM_ROWS-1 downto 0 loop
for j in 0 to PARALLEL_IO-1 loop
temp(i, j) := getVectorElement(input, i, j, NUM_ROWS, PARALLEL_IO, DATA_WIDTH);
end loop;
end loop;
return temp;
end function;
-- Converts register buffer into std_logic_vector used as output
function vectorizeOutput(input : rbuf) return std_logic_vector is
variable temp : std_logic_vector(NUM_ROWS*OUTPUT_COLS*DATA_WIDTH-1 downto 0);
begin
for i in 0 to NUM_ROWS-1 loop
for j in 0 to OUTPUT_COLS-1 loop
setVectorElement(input(i, j), temp, i, j, NUM_ROWS, OUTPUT_COLS, DATA_WIDTH);
end loop;
end loop;
return temp;
end function;
-------------------------------------------------------------------------
-- internal signals
-- the register buffer
signal regs : rbuf;
-- asserted when there is a valid read for a window
signal get_next_window : std_logic;
-- asserted when an element in the row with the corresponding index is the
-- top left element (i.e. the edge) of a generated window
signal is_edge_s : std_logic_vector(0 to BUFFER_COLS-1);
-- array that stores the inputs in devectorized form
signal input_array : input_array_t;
begin
--------------------------------------------------------------------
-- Create the buffer of registers and shifting logic
process(clk, rst)
begin
if (rst = '1') then
for i in 0 to NUM_ROWS-1 loop
for j in 0 to BUFFER_COLS-1 loop
regs(i, j) <= std_logic_vector(to_unsigned(0, DATA_WIDTH));
end loop;
end loop;
for i in 0 to BUFFER_COLS-1 loop
is_edge_s(i) <= '0';
end loop;
elsif (rising_edge(clk)) then
if (get_next_window = '1') then
-- shift all registers to next window
for i in 0 to NUM_ROWS-1 loop
-- the top PARALLEL_IO regs get loaded directly, so don't
-- shift anything into them
for j in 0 to BUFFER_COLS-PARALLEL_IO-1 loop
regs(i, j) <= regs(i, j+PARALLEL_IO);
end loop;
end loop;
-- shift all edge status bits
for j in 0 to BUFFER_COLS-PARALLEL_IO-1 loop
is_edge_s(j) <= is_edge_s(j+PARALLEL_IO);
end loop;
-- load in the new inputs
for i in 0 to NUM_ROWS-1 loop
for j in 0 to PARALLEL_IO-1 loop
regs(i, BUFFER_COLS-PARALLEL_IO+j) <= input_array(i, j);
end loop;
end loop;
-- load in the new edge bits
for j in 0 to PARALLEL_IO-1 loop
is_edge_s(j+BUFFER_COLS-PARALLEL_IO) <= input_ready and is_edge(PARALLEL_IO-j-1);
end loop;
end if;
end if;
end process;
--------------------------------------------------------------------
-- control logic
-- convert input vector into 2D array
input_array <= devectorizeInput(input);
-- convert reg buffer into std_logic_vector output
output <= vectorizeOutput(regs);
-- get the next window (by shifting the buffer), but only at valid times:
-- 1) When the user requests a read (not checked for valid)
-- 2) When the current (0,0) element is not the edge of a window (skip it)
-- In both cases, a new input has to be ready and the input not done
get_next_window <= (ren or not is_edge_s(0)) and (input_ready or input_done);
-- read an input from the fifo_array/window_buffer everytime we get a new window
read_input <= get_next_window;
-- empty when there is no input available (nothing to shift in) or when a
-- window is not available
empty <= (not input_ready and not input_done) or (not is_edge_s(0));
-- empty <= (not input_ready and not input_done) or (not is_edge_s(PARALLEL_IO-1));
-- output valid status of PARALLEL_IO windows
-- MSB is the first window, LSB is the last
process(is_edge_s)
begin
for i in 0 to PARALLEL_IO-1 loop
window_valid(PARALLEL_IO-i-1) <= is_edge_s(i);
end loop;
end process;
-- determine when reg_buffer has output all windows
process(is_edge_s, input_done)
begin
-- done when there are no more inputs and all the windows currently in
-- the buffer are gone
if (input_done = '1' and is_edge_s = std_logic_vector(to_unsigned(0,is_edge_s'length))) then
done <= '1';
else
done <= '0';
end if;
end process;
end RTL;
| gpl-3.0 | b43fff3fe9901e1070b2ec5065db257a | 0.568716 | 4.171088 | false | false | false | false |
pkerling/Chips-Demo | source/gigabee.vhd | 1 | 13,495 | --------------------------------------------------------------------------------
---
--- CHIPS - 2.0 Simple Web App Demo
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: [email protected]
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--------------------------------------------------------------------------------
---
---
--- +-------------+ +--------------+
--- | SERVER | | USER DESIGN |
--- +-------------+ +--------------+
--- | | | |
--- | >-----> |
--- | | | |
--- | <-----< >-------> LEDS
--- | | | |
--- | | | |
--- | | | |
--- | | +----^----v----+
--- | | | |
--- | | +----^----v----+
--- | | | UART |
--- | | +--------------+
--- | | | >-------> RS232-TX
--- | | | |
--- +---v-----^---+ | <-------< RS232-RX
--- | | +--------------+
--- +---v-----^---+
--- | ETHERNET |
--- | MAC |
--- +-------------+
--- | |
--- | |
---[RXCLK] ----->+ +------> [TXCLK]
--- | |
--- 125MHZ ----->+ +------> [GTXCLK]
--- | |
--- [RXD] ----->+ +------> [TXD]
--- | |
--- [RXDV] ----->+ +------> [TXEN]
--- | |
--- [RXER] ----->+ +------> [TXER]
--- | |
--- | |
--- +-------------+
---
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library ethernet_mac;
use ethernet_mac.ethernet_types.all;
entity GigaBee is
port(
CLK_IN : in std_logic;
--PHY INTERFACE
PHY_RESET : out std_logic;
RXDV : in std_logic;
RXER : in std_logic;
RXCLK : in std_logic;
RXD : in std_logic_vector(7 downto 0);
TXCLK : in std_logic;
GTXCLK : out std_logic;
TXD : out std_logic_vector(7 downto 0);
TXEN : out std_logic;
TXER : out std_logic;
MDC : out std_logic;
MDIO : inout std_logic;
--LEDS
GPIO_LEDS : out std_logic_vector(3 downto 0);
--RS232 INTERFACE
--Note that the TE0603 does not have an IC for serial I/O by default
RS232_RX : in std_logic;
RS232_TX : out std_logic
);
end entity GigaBee;
architecture RTL of GigaBee is
component SERVER is
port(
CLK : in std_logic;
RST : in std_logic;
--ETH RX STREAM
INPUT_ETH_RX : in std_logic_vector(15 downto 0);
INPUT_ETH_RX_STB : in std_logic;
INPUT_ETH_RX_ACK : out std_logic;
--ETH TX STREAM
output_eth_tx : out std_logic_vector(15 downto 0);
OUTPUT_ETH_TX_STB : out std_logic;
OUTPUT_ETH_TX_ACK : in std_logic;
--SOCKET RX STREAM
INPUT_SOCKET : in std_logic_vector(15 downto 0);
INPUT_SOCKET_STB : in std_logic;
INPUT_SOCKET_ACK : out std_logic;
--SOCKET TX STREAM
OUTPUT_SOCKET : out std_logic_vector(15 downto 0);
OUTPUT_SOCKET_STB : out std_logic;
OUTPUT_SOCKET_ACK : in std_logic
);
end component;
component USER_DESIGN is
port(
CLK : in std_logic;
RST : in std_logic;
OUTPUT_LEDS : out std_logic_vector(15 downto 0);
OUTPUT_LEDS_STB : out std_logic;
OUTPUT_LEDS_ACK : in std_logic;
INPUT_SPEED : in std_logic_vector(15 downto 0);
INPUT_SPEED_STB : in std_logic;
INPUT_SPEED_ACK : out std_logic;
--SOCKET RX STREAM
INPUT_SOCKET : in std_logic_vector(15 downto 0);
INPUT_SOCKET_STB : in std_logic;
INPUT_SOCKET_ACK : out std_logic;
--SOCKET TX STREAM
OUTPUT_SOCKET : out std_logic_vector(15 downto 0);
OUTPUT_SOCKET_STB : out std_logic;
OUTPUT_SOCKET_ACK : in std_logic;
--RS232 RX STREAM
INPUT_RS232_RX : in std_logic_vector(15 downto 0);
INPUT_RS232_RX_STB : in std_logic;
INPUT_RS232_RX_ACK : out std_logic;
--RS232 TX STREAM
OUTPUT_RS232_TX : out std_logic_vector(15 downto 0);
OUTPUT_RS232_TX_STB : out std_logic;
OUTPUT_RS232_TX_ACK : in std_logic
);
end component;
--clock tree signals
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal CLK_50 : std_logic;
signal CLK_125 : std_logic;
signal INTERNAL_RST : std_logic;
signal LOCKED : std_logic;
signal OUTPUT_LEDS : std_logic_vector(15 downto 0);
signal OUTPUT_LEDS_STB : std_logic;
signal OUTPUT_LEDS_ACK : std_logic;
signal INPUT_SPEED : std_logic_vector(15 downto 0);
signal INPUT_SPEED_STB : std_logic;
signal INPUT_SPEED_ACK : std_logic;
--ETH RX STREAM
signal ETH_RX : std_logic_vector(15 downto 0);
signal ETH_RX_STB : std_logic;
signal ETH_RX_ACK : std_logic;
--ETH TX STREAM
signal ETH_TX : std_logic_vector(15 downto 0);
signal ETH_TX_STB : std_logic;
signal ETH_TX_ACK : std_logic;
--RS232 RX STREAM
signal INPUT_RS232_RX : std_logic_vector(15 downto 0);
signal INPUT_RS232_RX_STB : std_logic;
signal INPUT_RS232_RX_ACK : std_logic;
--RS232 TX STREAM
signal OUTPUT_RS232_TX : std_logic_vector(15 downto 0);
signal OUTPUT_RS232_TX_STB : std_logic;
signal OUTPUT_RS232_TX_ACK : std_logic;
--SOCKET RX STREAM
signal INPUT_SOCKET : std_logic_vector(15 downto 0);
signal INPUT_SOCKET_STB : std_logic;
signal INPUT_SOCKET_ACK : std_logic;
--SOCKET TX STREAM
signal OUTPUT_SOCKET : std_logic_vector(15 downto 0);
signal OUTPUT_SOCKET_STB : std_logic;
signal OUTPUT_SOCKET_ACK : std_logic;
-- Ethernet MAC
signal TXD_INTERNAL : std_ulogic_vector(7 downto 0);
signal LINK_UP : std_ulogic;
signal SPEED : t_ethernet_speed;
signal RX_RESET : std_ulogic;
signal RX_EMPTY : std_ulogic;
signal RX_RD_EN : std_ulogic;
signal RX_DATA : t_ethernet_data;
signal TX_RESET : std_ulogic;
signal TX_DATA : t_ethernet_data;
signal TX_WR_EN : std_ulogic;
signal TX_FULL : std_ulogic;
begin
TXD <= std_logic_vector(TXD_INTERNAL);
ethernet_with_fifos_inst : entity ethernet_mac.ethernet_with_fifos
generic map(
MIIM_PHY_ADDRESS => "00111",
MIIM_RESET_WAIT_TICKS => 1250000 -- 10 ms at 125 MHz clock, minimum: 5 ms
)
port map(
clock_125_i => clk0,
reset_i => INTERNAL_RST,
mii_tx_clk_i => TXCLK,
mii_tx_er_o => TXER,
mii_tx_en_o => TXEN,
mii_txd_o => TXD_INTERNAL,
mii_rx_clk_i => RXCLK,
mii_rx_er_i => RXER,
mii_rx_dv_i => RXDV,
mii_rxd_i => std_ulogic_vector(RXD),
gmii_gtx_clk_o => GTXCLK,
rgmii_rx_ctl_i => '0',
miim_clock_i => CLK_125,
mdc_o => MDC,
mdio_io => MDIO,
link_up_o => LINK_UP,
speed_o => SPEED,
tx_clock_i => CLK_50,
tx_reset_o => TX_RESET,
tx_data_i => TX_DATA,
tx_wr_en_i => TX_WR_EN,
tx_full_o => TX_FULL,
rx_clock_i => CLK_50,
rx_reset_o => RX_RESET,
rx_empty_o => RX_EMPTY,
rx_rd_en_i => RX_RD_EN,
rx_data_o => RX_DATA
-- Force 1000 Mbps/GMII in simulation only
-- pragma translate_off
, speed_override_i => SPEED_1000MBPS
-- pragma translate_on
);
SERVER_INST_1 : SERVER port map(
CLK => CLK_50,
RST => TX_RESET,
--ETH RX STREAM
INPUT_ETH_RX => ETH_RX,
INPUT_ETH_RX_STB => ETH_RX_STB,
INPUT_ETH_RX_ACK => ETH_RX_ACK,
--ETH TX STREAM
OUTPUT_ETH_TX => ETH_TX,
OUTPUT_ETH_TX_STB => ETH_TX_STB,
OUTPUT_ETH_TX_ACK => ETH_TX_ACK,
--SOCKET STREAM
INPUT_SOCKET => INPUT_SOCKET,
INPUT_SOCKET_STB => INPUT_SOCKET_STB,
INPUT_SOCKET_ACK => INPUT_SOCKET_ACK,
--SOCKET STREAM
OUTPUT_SOCKET => OUTPUT_SOCKET,
OUTPUT_SOCKET_STB => OUTPUT_SOCKET_STB,
OUTPUT_SOCKET_ACK => OUTPUT_SOCKET_ACK
);
USER_DESIGN_INST_1 : USER_DESIGN port map(
CLK => CLK_50,
RST => TX_RESET,
OUTPUT_LEDS => OUTPUT_LEDS,
OUTPUT_LEDS_STB => OUTPUT_LEDS_STB,
OUTPUT_LEDS_ACK => OUTPUT_LEDS_ACK,
INPUT_SPEED => INPUT_SPEED,
INPUT_SPEED_STB => INPUT_SPEED_STB,
INPUT_SPEED_ACK => INPUT_SPEED_ACK,
--RS232 RX STREAM
INPUT_RS232_RX => INPUT_RS232_RX,
INPUT_RS232_RX_STB => INPUT_RS232_RX_STB,
INPUT_RS232_RX_ACK => INPUT_RS232_RX_ACK,
--RS232 TX STREAM
OUTPUT_RS232_TX => OUTPUT_RS232_TX,
OUTPUT_RS232_TX_STB => OUTPUT_RS232_TX_STB,
OUTPUT_RS232_TX_ACK => OUTPUT_RS232_TX_ACK,
--SOCKET STREAM
INPUT_SOCKET => OUTPUT_SOCKET,
INPUT_SOCKET_STB => OUTPUT_SOCKET_STB,
INPUT_SOCKET_ACK => OUTPUT_SOCKET_ACK,
--SOCKET STREAM
OUTPUT_SOCKET => INPUT_SOCKET,
OUTPUT_SOCKET_STB => INPUT_SOCKET_STB,
OUTPUT_SOCKET_ACK => INPUT_SOCKET_ACK
);
mac_adaptor_inst : entity work.chips_mac_adaptor
port map(
clock_i => CLK_50,
reset_i => TX_RESET,
tx_data_o => tx_data,
tx_wr_en_o => tx_wr_en,
tx_full_i => tx_full,
rx_empty_i => rx_empty,
rx_rd_en_o => rx_rd_en,
rx_data_i => rx_data,
chips_tx_i => ETH_TX,
chips_tx_stb_i => ETH_TX_STB,
chips_tx_ack_o => ETH_TX_ACK,
chips_rx_o => ETH_RX,
chips_rx_stb_o => ETH_RX_STB,
chips_rx_ack_i => ETH_RX_ACK
);
SERIAL_OUTPUT_INST_1 : entity work.serial_output generic map(
CLOCK_FREQUENCY => 50000000,
BAUD_RATE => 115200
) port map(
CLK => CLK_50,
RST => INTERNAL_RST,
TX => RS232_TX,
IN1 => OUTPUT_RS232_TX(7 downto 0),
IN1_STB => OUTPUT_RS232_TX_STB,
IN1_ACK => OUTPUT_RS232_TX_ACK
);
SERIAL_INPUT_INST_1 : entity work.SERIAL_INPUT generic map(
CLOCK_FREQUENCY => 50000000,
BAUD_RATE => 115200
) port map(
CLK => CLK_50,
RST => INTERNAL_RST,
RX => RS232_RX,
OUT1 => INPUT_RS232_RX(7 downto 0),
OUT1_STB => INPUT_RS232_RX_STB,
OUT1_ACK => INPUT_RS232_RX_ACK
);
INPUT_RS232_RX(15 downto 8) <= (others => '0');
process
begin
wait until rising_edge(CLK_50);
if OUTPUT_LEDS_STB = '1' then
GPIO_LEDS <= not OUTPUT_LEDS(3 downto 0);
end if;
OUTPUT_LEDS_ACK <= '1';
INPUT_SPEED_STB <= '1';
INPUT_SPEED(15 downto 2) <= (others => '0');
INPUT_SPEED(1 downto 0) <= std_logic_vector(SPEED);
end process;
--GPIO_LEDS <= (not link_up) & (not std_logic_vector(speed)) & (not RX_RESET);
reset_generator_inst : entity work.reset_generator
-- pragma translate_off
generic map(
RESET_DELAY => 10
)
-- pragma translate_on
port map(
clock_i => CLK_125,
locked_i => LOCKED,
reset_o => INTERNAL_RST
);
-------------------------
-- Output Output
-- Clock Freq (MHz)
-------------------------
-- CLK_OUT1 50.000
-- CLK_OUT3 125.000
----------------------------------
-- Input Clock Input Freq (MHz)
----------------------------------
-- primary 125.000
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map(O => clkin1,
I => CLK_IN);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst : DCM_SP
generic map(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 5,
CLKFX_MULTIPLY => 2,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 8.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map(
-- Input clock
CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => LOCKED,
STATUS => open,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
PHY_RESET <= not INTERNAL_RST;
-- Output buffering
-------------------------------------
clkfb <= CLK_125;
BUFG_INST2 : BUFG
port map(O => CLK_125,
I => clk0);
BUFG_INST3 : BUFG
port map(O => CLK_50,
I => clkfx);
end architecture RTL;
| mit | 46acbc5284f625dcaf2975275828612b | 0.490774 | 3.135455 | false | false | false | false |
cnplab/blockmon | fw-combo/src/IPFIX/comp/sh_reg.vhd | 1 | 4,483 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
--
-- sh_reg.vhd: Shift Register
-- Copyright (C) 2003 CESNET
-- Author(s): Martinek Tomas <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: sh_reg.vhd 24 2007-07-31 11:19:09Z kosek $
--
-- TODO:
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity sh_reg is
generic(
NUM_BITS : integer := 16;
INIT : std_logic_vector(15 downto 0) := X"0000";
INIT_EXT00 : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
CLK : in std_logic;
DIN : in std_logic;
CE : in std_logic;
DOUT : out std_logic
);
end entity sh_reg;
-- ----------------------------------------------------------------------------
-- Architecture declaration
-- ----------------------------------------------------------------------------
architecture behavioral of sh_reg is
constant NUM_ELEMS : integer := (NUM_BITS+15)/16;
type t_vector4 is array (0 to NUM_ELEMS-1) of std_logic_vector(3 downto 0);
type t_vector_dw is array (0 to NUM_ELEMS) of std_logic;
signal regsh_do : t_vector_dw;
signal regsh_addr : t_vector4;
begin
regsh_do(0) <= DIN;
SH_REG_XU : for i in 0 to NUM_ELEMS-1 generate
-- addr generation
regsh_addr(i) <= "1111" when (i < NUM_ELEMS-1) else
conv_std_logic_vector((NUM_BITS mod 16)+15, 4);
init_16p: if i = 0 generate
SH_REG_U : entity work.sh_reg_elem
generic map(
SH_INIT => INIT
)
port map(
CLK => CLK,
DIN => regsh_do(i),
CE => CE,
ADDR => regsh_addr(i),
DOUT => regsh_do(i+1)
);
end generate;
init_ext00p: if i > 0 generate
SH_REG_U : entity work.sh_reg_elem
generic map(
SH_INIT => INIT_EXT00((i*16)-1 downto (i-1)*16)
)
port map(
CLK => CLK,
DIN => regsh_do(i),
CE => CE,
ADDR => regsh_addr(i),
DOUT => regsh_do(i+1)
);
end generate;
end generate;
DOUT <= regsh_do(NUM_ELEMS);
end architecture behavioral;
| bsd-3-clause | 38c07f0025892b328e629314728ac911 | 0.555432 | 4.154773 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/lib/src/global.vhd | 3 | 6,547 | -------------------------------------------------------------------------------
-- Global package
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package Global is
constant cActivated : std_logic := '1';
constant cInactivated : std_logic := '0';
constant cnActivated : std_logic := '0';
constant cnInactivated : std_logic := '1';
constant cByteLength : natural := 8;
constant cWordLength : natural := 2 * cByteLength;
constant cFalse : natural := 0;
constant cTrue : natural := 1;
function LogDualis(cNumber : natural) return natural;
function maximum (a : natural; b : natural) return natural;
function minimum (a : natural; b : natural) return natural;
function integerToBoolean (a : integer) return boolean;
function booleanToInteger (a : boolean) return integer;
function byteSwap (iVector : std_logic_vector) return std_logic_vector;
function wordSwap (iVector : std_logic_vector) return std_logic_vector;
function reduceOr (iVector : std_logic_vector) return std_logic;
function reduceAnd (iVector : std_logic_vector) return std_logic;
end Global;
package body Global is
function LogDualis(cNumber : natural) return natural is
variable vClimbUp : natural := 1;
variable vResult : natural := 0;
begin
while vClimbUp < cNumber loop
vClimbUp := vClimbUp * 2;
vResult := vResult+1;
end loop;
return vResult;
end LogDualis;
function maximum (a : natural; b : natural) return natural is
variable vRes : natural;
begin
if a > b then
vRes := a;
else
vRes := b;
end if;
return vRes;
end function;
function minimum (a : natural; b : natural) return natural is
variable vRes : natural;
begin
if a < b then
vRes := a;
else
vRes := b;
end if;
return vRes;
end function;
function integerToBoolean (a : integer) return boolean is
variable vRes : boolean;
begin
if a = cFalse then
vRes := false;
else
vRes := true;
end if;
return vRes;
end function;
function booleanToInteger (a : boolean) return integer is
variable vRes : integer;
begin
if a = false then
vRes := cFalse;
else
vRes := cTrue;
end if;
return vRes;
end function;
function byteSwap (iVector : std_logic_vector) return std_logic_vector is
variable vResult : std_logic_vector(iVector'range);
variable vLeftIndex : natural;
variable vRightIndex : natural;
begin
assert ((iVector'length mod cByteLength) = 0)
report "Byte swapping can't be done with that vector!"
severity failure;
for i in iVector'length / cByteLength downto 1 loop
vLeftIndex := i;
vRightIndex := iVector'length / cByteLength - i + 1;
vResult(vLeftIndex * cByteLength - 1 downto (vLeftIndex-1) * cByteLength) :=
iVector(vRightIndex * cByteLength - 1 downto (vRightIndex-1) * cByteLength);
end loop;
return vResult;
end function;
function wordSwap (iVector : std_logic_vector) return std_logic_vector is
variable vResult : std_logic_vector(iVector'range);
variable vLeftIndex : natural;
variable vRightIndex : natural;
begin
assert ((iVector'length mod cWordLength) = 0)
report "Word swapping can't be done with that vector!"
severity failure;
for i in iVector'length / cWordLength downto 1 loop
vLeftIndex := i;
vRightIndex := iVector'length / cWordLength - i + 1;
vResult(vLeftIndex * cWordLength - 1 downto (vLeftIndex-1) * cWordLength) :=
iVector(vRightIndex * cWordLength - 1 downto (vRightIndex-1) * cWordLength);
end loop;
return vResult;
end function;
function reduceOr (iVector : std_logic_vector) return std_logic is
variable vRes_tmp : std_logic;
begin
-- initialize result variable
vRes_tmp := cInactivated;
for i in iVector'range loop
vRes_tmp := vRes_tmp or iVector(i);
end loop;
return vRes_tmp;
end function;
function reduceAnd (iVector : std_logic_vector) return std_logic is
variable vRes_tmp : std_logic;
begin
-- initialize result variable
vRes_tmp := cActivated;
for i in iVector'range loop
vRes_tmp := vRes_tmp and iVector(i);
end loop;
return vRes_tmp;
end function;
end Global; | gpl-2.0 | 5a3791c80bf4628ebaebdc4d0ddb906d | 0.617077 | 4.587947 | false | false | false | false |
cnplab/blockmon | fw-combo/src/netcope-sim/models/mi_bfm_pkg.vhd | 1 | 5,784 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- fl_bfm_pkg.vhd: Support package for bfm_sim
-- Copyright (C) 2007 CESNET
-- Author(s): Vlastimil Kosar <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: mi_bfm_pkg.vhd 12021 2011-04-15 08:23:45Z kastovsky $
--
-- TODO:
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use IEEE.numeric_std.all;
use std.textio.all;
-- ----------------------------------------------------------------------------
-- MI SIM Package
-- ----------------------------------------------------------------------------
package mi_bfm_pkg is
type TTransactionDirection is (READ, WRITE);
type TTransaction is record
DATA : std_logic_vector(31 downto 0);
ADDR : std_logic_vector(31 downto 0);
BE : std_logic_vector(3 downto 0);
DIRECTION : TTransactionDirection;
end record;
type TCommandStatus is record
BUSY : std_logic;
REQ_ACK : std_logic;
REQ : std_logic;
end record;
signal status : TCommandStatus := ('0', '0', '0');
-- internaly used to synchronize model
procedure WriteTransaction(variable trans : in TTransaction);
procedure ReadTransaction(variable trans : out TTransaction);
-- write data on address addr with byte enables be. status_cnt have to be status(x) and mi_sim_id have to be x
procedure MI32Write(constant addr : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant be : in std_logic_vector(3 downto 0);
signal status : inout TCommandStatus);
-- read data from address addr with byte enables be. status_cnt have to be status(x) and mi_sim_id have to be x
procedure MI32Read(constant addr : in std_logic_vector(31 downto 0);
variable data : inout std_logic_vector(31 downto 0);
constant be : in std_logic_vector(3 downto 0);
signal status : inout TCommandStatus);
end mi_bfm_pkg;
-- ----------------------------------------------------------------------------
-- MI SIM PKG BODY
-- ----------------------------------------------------------------------------
package body mi_bfm_pkg is
shared variable transaction : TTransaction;
procedure ReadTransaction(variable trans : out TTransaction) is
begin
trans := transaction;
end procedure;
procedure WriteTransaction(variable trans : in TTransaction) is
begin
transaction := trans;
end procedure;
procedure MI32Write(constant addr : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant be : in std_logic_vector(3 downto 0);
signal status : inout TCommandStatus) is
begin
transaction.ADDR := addr;
transaction.DATA := data;
transaction.BE := be;
transaction.DIRECTION := WRITE;
status.REQ <= '1';
wait on status.REQ_ACK;
status.REQ <= '0';
wait until status.BUSY = '0';
end procedure;
procedure MI32Read(constant addr : in std_logic_vector(31 downto 0);
variable data : inout std_logic_vector(31 downto 0);
constant be : in std_logic_vector(3 downto 0);
signal status : inout TCommandStatus) is
begin
transaction.ADDR := addr;
transaction.BE := be;
transaction.DIRECTION := READ;
status.REQ <= '1';
wait on status.REQ_ACK;
status.REQ <= '0';
wait until status.BUSY = '0';
data := transaction.data;
end procedure;
end mi_bfm_pkg;
| bsd-3-clause | 578eccea1e4d9eb3e8c2f3c875853196 | 0.603216 | 4.501167 | false | false | false | false |
cnplab/blockmon | fw-combo/src/IPFIX/comp/barrel_shifter.vhd | 1 | 4,067 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
--
-- barrel_shifter.vhd Barrel shifter with generic data width
-- Copyright (C) 2009 CESNET
-- Author(s): Vaclav Bartos <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id$
--
-- TODO:
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.math_pack.all;
-- ----------------------------------------------------------------------------
-- ENTITY DECLARATION -- Barrel shifter --
-- ----------------------------------------------------------------------------
entity BARREL_SHIFTER is
generic (
DATA_WIDTH : integer := 64;
-- set true to shift left, false to shift right
SHIFT_LEFT : boolean := true
);
port (
-- Input interface ------------------------------------------------------
DATA_IN : in std_logic_vector(DATA_WIDTH-1 downto 0);
DATA_OUT : out std_logic_vector(DATA_WIDTH-1 downto 0);
SEL : in std_logic_vector(log2(DATA_WIDTH/8)-1 downto 0)
);
end BARREL_SHIFTER;
-- ----------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION --
-- ----------------------------------------------------------------------------
architecture barrel_shifter_arch of BARREL_SHIFTER is
begin
multiplexors: for i in 0 to DATA_WIDTH/8-1 generate
process (DATA_IN, SEL)
variable sel_aux: integer;
begin
if (SHIFT_LEFT) then
sel_aux := conv_integer('0'&SEL);
else
sel_aux := conv_integer('0'&(0-SEL));
end if;
DATA_OUT(i*8+7 downto i*8) <=
DATA_IN(
((DATA_WIDTH/8-sel_aux+i) mod (DATA_WIDTH/8))*8 + 7
downto
((DATA_WIDTH/8-sel_aux+i) mod (DATA_WIDTH/8))*8
);
end process;
end generate;
end barrel_shifter_arch;
| bsd-3-clause | a93f5c1291db9241fa6257c82aea9e7d | 0.552496 | 4.642694 | false | false | false | false |
emusan/novena_bare | src/novena_bare.vhd | 1 | 753 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.ALL;
entity novena_bare is
generic(
clk_freq: integer := 50_000_000
);
port(
led: out std_logic;
clk_n: in std_logic;
clk_p: in std_logic
);
end novena_bare;
architecture Behavioral of novena_bare is
signal count_1s: integer range 0 to clk_freq := 0;
signal enable_led: std_logic := '0';
signal clk: std_logic;
begin
IBUFGDS_inst: IBUFGDS port map ( O => clk, I => clk_p, IB => clk_n );
process(clk)
begin
if(rising_edge(clk)) then
count_1s <= count_1s + 1;
if(count_1s = clk_freq) then
count_1s <= 0;
enable_led <= not enable_led;
end if;
end if;
end process;
led <= enable_led;
end Behavioral;
| mit | a44474d2f8080e7ed18304406af4cdd5 | 0.658699 | 2.623693 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/lib/src/registerFileRtl.vhd | 3 | 5,435 | -------------------------------------------------------------------------------
--! @file registerFileRtl.vhd
--
--! @brief Register table file implementation
--
--! @details This implementation is a simple dual ported memory implemented in
--! using register resources.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity registerFile is
generic (
gRegCount : natural := 8
);
port (
iClk : in std_logic;
iRst : in std_logic;
iWriteA : in std_logic;
iWriteB : in std_logic;
iByteenableA: in std_logic_vector;
iByteenableB: in std_logic_vector;
iAddrA : in std_logic_vector(LogDualis(gRegCount)-1 downto 0);
iAddrB : in std_logic_vector(LogDualis(gRegCount)-1 downto 0);
iWritedataA : in std_logic_vector;
oReaddataA : out std_logic_vector;
iWritedataB : in std_logic_vector;
oReaddataB : out std_logic_vector
);
end registerFile;
architecture Rtl of registerFile is
constant cByte : natural := 8;
type tRegSet is
array (natural range <>) of std_logic_vector(iWritedataA'range);
signal regFile, regFile_next : tRegSet(gRegCount-1 downto 0);
begin
--register set
reg : process(iClk)
begin
if rising_edge(iClk) then
if iRst = cActivated then
--clear register file
regFile <= (others => (others => '0'));
else
regFile <= regFile_next;
end if;
end if;
end process;
--write data into Register File with respect to address
--note: a overrules b
regFileWrite : process(
iWriteA, iWriteB, iAddrA, iAddrB,
iByteenableA, iByteenableB,
iWritedataA, iWritedataB, regFile)
variable vWritedata : std_logic_vector(iWritedataA'range);
begin
--default
regFile_next <= regFile;
vWritedata := (others => cInactivated);
if iWriteB = cActivated then
--read out register content first
vWritedata := regFile(to_integer(unsigned(iAddrB)));
--then consider byteenable
for i in iWritedataB'range loop
if iByteenableB(i/cByte) = cActivated then
--if byte is enabled assign it
vWritedata(i) := iWritedataB(i);
end if;
end loop;
--write to address the masked writedata
regFile_next(to_integer(unsigned(iAddrB))) <= vWritedata;
end if;
if iWriteA = cActivated then
--read out register content first
vWritedata := regFile(to_integer(unsigned(iAddrA)));
--then consider byteenable
for i in iWritedataA'range loop
if iByteenableA(i/cByte) = cActivated then
--if byte is enabled assign it
vWritedata(i) := iWritedataA(i);
end if;
end loop;
--write to address the masked writedata
regFile_next(to_integer(unsigned(iAddrA))) <= vWritedata;
end if;
end process;
--read data from Register File with respect to iAddrRead
regFileRead : process(iAddrA, iAddrB, regFile)
begin
--read from address
oReaddataA <= regFile(to_integer(unsigned(iAddrA)));
oReaddataB <= regFile(to_integer(unsigned(iAddrB)));
end process;
end Rtl;
| gpl-2.0 | 6204e4a746047b05cff41a0483df4085 | 0.603312 | 4.673259 | false | false | false | false |
cnplab/blockmon | fw-combo/src/IPFIX/comp/fl_transformer.vhd | 1 | 5,492 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- transformer.vhd: Implementation of FrameLink Transformer component.
-- Copyright (C) 2006 CESNET
-- Author(s): Martin Louda <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: transformer.vhd 14 2007-07-31 06:44:05Z kosek $
--
-- TODO:
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- library containing log2 function
use work.math_pack.all;
-- ------------------------------------------------------------------------
-- Architecture declaration
-- ------------------------------------------------------------------------
architecture full of FL_TRANSFORMER is
begin
-- ---------------------------------------------------------------------
-- Main logic
-- ---------------------------------------------------------------------
-- data widths are equal
GEN_ARCH_EQUAL:
if (RX_DATA_WIDTH = TX_DATA_WIDTH) generate
TX_DATA <= RX_DATA;
TX_REM <= RX_REM;
TX_SOF_N <= RX_SOF_N;
TX_EOF_N <= RX_EOF_N;
TX_SOP_N <= RX_SOP_N;
TX_EOP_N <= RX_EOP_N;
TX_SRC_RDY_N <= RX_SRC_RDY_N;
RX_DST_RDY_N <= TX_DST_RDY_N;
end generate;
-- RX data width > TX data width
GEN_ARCH_DOWN:
if (RX_DATA_WIDTH > TX_DATA_WIDTH) generate
FL_TRANSFORMER_DOWN_U: entity work.FL_TRANSFORMER_DOWN
generic map(
RX_DATA_WIDTH => RX_DATA_WIDTH,
TX_DATA_WIDTH => TX_DATA_WIDTH
)
port map(
CLK => CLK,
RESET => RESET,
--
RX_DATA => RX_DATA,
RX_REM => RX_REM,
RX_SOF_N => RX_SOF_N,
RX_EOF_N => RX_EOF_N,
RX_SOP_N => RX_SOP_N,
RX_EOP_N => RX_EOP_N,
RX_SRC_RDY_N => RX_SRC_RDY_N,
RX_DST_RDY_N => RX_DST_RDY_N,
--
TX_DATA => TX_DATA,
TX_REM => TX_REM,
TX_SOF_N => TX_SOF_N,
TX_EOF_N => TX_EOF_N,
TX_SOP_N => TX_SOP_N,
TX_EOP_N => TX_EOP_N,
TX_SRC_RDY_N => TX_SRC_RDY_N,
TX_DST_RDY_N => TX_DST_RDY_N
);
end generate;
-- RX data width < TX data width
GEN_ARCH_UP:
if (RX_DATA_WIDTH < TX_DATA_WIDTH) generate
FL_TRANSFORMER_UP_U: entity work.FL_TRANSFORMER_UP
generic map(
RX_DATA_WIDTH => RX_DATA_WIDTH,
TX_DATA_WIDTH => TX_DATA_WIDTH
)
port map(
CLK => CLK,
RESET => RESET,
--
RX_DATA => RX_DATA,
RX_REM => RX_REM,
RX_SOF_N => RX_SOF_N,
RX_EOF_N => RX_EOF_N,
RX_SOP_N => RX_SOP_N,
RX_EOP_N => RX_EOP_N,
RX_SRC_RDY_N => RX_SRC_RDY_N,
RX_DST_RDY_N => RX_DST_RDY_N,
--
TX_DATA => TX_DATA,
TX_REM => TX_REM,
TX_SOF_N => TX_SOF_N,
TX_EOF_N => TX_EOF_N,
TX_SOP_N => TX_SOP_N,
TX_EOP_N => TX_EOP_N,
TX_SRC_RDY_N => TX_SRC_RDY_N,
TX_DST_RDY_N => TX_DST_RDY_N
);
end generate;
end architecture full;
| bsd-3-clause | 594651ebdc8fb1f5afa08f22aee3a41d | 0.502549 | 3.917261 | false | false | false | false |
augustollenz/pwm-controller | testbench/pwm_tb.vhd | 1 | 849 | library ieee;
use ieee.std_logic_1164.all;
entity pwm_tb is
end pwm_tb;
architecture behavior of pwm_tb is
component pwm
port (
clk: in std_logic;
reset: in std_logic;
output: out std_logic
);
end component;
constant clk_period: time := 1 us;
signal clk, reset, output: std_logic := '0';
begin
uut: pwm port map (clk => clk, reset => reset, output => output);
clk_process: process
begin
clk <= '0';
wait for clk_period / 2;
clk <= '1';
wait for clk_period / 2;
end process;
stimulus_process: process
begin
wait for 10 us;
reset <= '1';
wait for 1000 ms;
reset <= '0';
assert false report "simulation completed" severity note;
wait;
end process;
end behavior;
| unlicense | 8214c8e4611dedaf65865729c492348a | 0.547703 | 3.894495 | false | false | false | false |
eggcar/time-holdover-cycloneIV-board-old | TimeHoldOver_Qsys/TimeHoldOver_Qsys_inst.vhd | 1 | 13,558 | component TimeHoldOver_Qsys is
port (
clk_clk : in std_logic := 'X'; -- clk
epcs_flash_controller_dclk : out std_logic; -- dclk
epcs_flash_controller_sce : out std_logic; -- sce
epcs_flash_controller_sdo : out std_logic; -- sdo
epcs_flash_controller_data0 : in std_logic := 'X'; -- data0
on_chip_rst_and_pps_switch_export : out std_logic_vector(8 downto 0); -- export
io_update_ctrl_export : out std_logic; -- export
ocxo_lock_export : in std_logic := 'X'; -- export
pps_interrupt_export : in std_logic := 'X'; -- export
reset_reset_n : in std_logic := 'X'; -- reset_n
sdram_controller_addr : out std_logic_vector(11 downto 0); -- addr
sdram_controller_ba : out std_logic_vector(1 downto 0); -- ba
sdram_controller_cas_n : out std_logic; -- cas_n
sdram_controller_cke : out std_logic; -- cke
sdram_controller_cs_n : out std_logic; -- cs_n
sdram_controller_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
sdram_controller_dqm : out std_logic_vector(1 downto 0); -- dqm
sdram_controller_ras_n : out std_logic; -- ras_n
sdram_controller_we_n : out std_logic; -- we_n
timer_ecc_fault_itr_export : in std_logic := 'X'; -- export
timer_interface_coe_sec_cnt_set_data_out : out std_logic_vector(192 downto 0); -- coe_sec_cnt_set_data_out
timer_interface_coe_sec_cnt_get_data_in : in std_logic_vector(191 downto 0) := (others => 'X'); -- coe_sec_cnt_get_data_in
timer_interface_coe_ns_cnt_set_data_out : out std_logic_vector(96 downto 0); -- coe_ns_cnt_set_data_out
timer_interface_coe_ns_cnt_get_data_in : in std_logic_vector(95 downto 0) := (others => 'X'); -- coe_ns_cnt_get_data_in
timer_interface_coe_ctrl_cnt_set_out : out std_logic_vector(24 downto 0); -- coe_ctrl_cnt_set_out
timer_interface_coe_ctrl_cnt_get_in : in std_logic_vector(23 downto 0) := (others => 'X'); -- coe_ctrl_cnt_get_in
timer_interface_coe_err_cnt_in : in std_logic_vector(23 downto 0) := (others => 'X'); -- coe_err_cnt_in
timer_interface_coe_utc_time_in : in std_logic_vector(55 downto 0) := (others => 'X'); -- coe_utc_time_in
timer_interface_coe_time_zone_set_out : out std_logic_vector(8 downto 0); -- coe_time_zone_set_out
timer_interface_coe_time_zone_get_in : in std_logic_vector(7 downto 0) := (others => 'X'); -- coe_time_zone_get_in
timer_interface_coe_leap_cnt_set_out : out std_logic_vector(16 downto 0); -- coe_leap_cnt_set_out
timer_interface_coe_leap_cnt_get_in : in std_logic_vector(15 downto 0) := (others => 'X'); -- coe_leap_cnt_get_in
timer_interface_coe_leap_occur_set_out : out std_logic_vector(64 downto 0); -- coe_leap_occur_set_out
timer_interface_coe_leap_occur_get_in : in std_logic_vector(63 downto 0) := (others => 'X'); -- coe_leap_occur_get_in
timer_interface_coe_dst_ingress_set_out : out std_logic_vector(64 downto 0); -- coe_dst_ingress_set_out
timer_interface_coe_dst_ingress_get_in : in std_logic_vector(63 downto 0) := (others => 'X'); -- coe_dst_ingress_get_in
timer_interface_coe_dst_engress_set_out : out std_logic_vector(64 downto 0); -- coe_dst_engress_set_out
timer_interface_coe_dst_engress_get_in : in std_logic_vector(63 downto 0) := (others => 'X'); -- coe_dst_engress_get_in
timer_interface_coe_leap_direct_get_in : in std_logic_vector(7 downto 0) := (others => 'X'); -- coe_leap_direct_get_in
timer_interface_coe_leap_direct_set_out : out std_logic_vector(8 downto 0); -- coe_leap_direct_set_out
timer_interface_coe_io_update_in : in std_logic := 'X'; -- coe_io_update_in
timer_interface_coe_time_quality_get_in : in std_logic_vector(7 downto 0) := (others => 'X'); -- coe_time_quality_get_in
timer_interface_coe_time_quality_set_out : out std_logic_vector(8 downto 0); -- coe_time_quality_set_out
uart_0_external_connection_rxd : in std_logic := 'X'; -- rxd
uart_0_external_connection_txd : out std_logic; -- txd
uart_1_external_connection_rxd : in std_logic := 'X'; -- rxd
uart_1_external_connection_txd : out std_logic; -- txd
uart_2_external_connection_rxd : in std_logic := 'X'; -- rxd
uart_2_external_connection_txd : out std_logic; -- txd
uart_3_external_connection_rxd : in std_logic := 'X'; -- rxd
uart_3_external_connection_txd : out std_logic -- txd
);
end component TimeHoldOver_Qsys;
u0 : component TimeHoldOver_Qsys
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
epcs_flash_controller_dclk => CONNECTED_TO_epcs_flash_controller_dclk, -- epcs_flash_controller.dclk
epcs_flash_controller_sce => CONNECTED_TO_epcs_flash_controller_sce, -- .sce
epcs_flash_controller_sdo => CONNECTED_TO_epcs_flash_controller_sdo, -- .sdo
epcs_flash_controller_data0 => CONNECTED_TO_epcs_flash_controller_data0, -- .data0
on_chip_rst_and_pps_switch_export => CONNECTED_TO_on_chip_rst_and_pps_switch_export, -- on_chip_rst_and_pps_switch.export
io_update_ctrl_export => CONNECTED_TO_io_update_ctrl_export, -- io_update_ctrl.export
ocxo_lock_export => CONNECTED_TO_ocxo_lock_export, -- ocxo_lock.export
pps_interrupt_export => CONNECTED_TO_pps_interrupt_export, -- pps_interrupt.export
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
sdram_controller_addr => CONNECTED_TO_sdram_controller_addr, -- sdram_controller.addr
sdram_controller_ba => CONNECTED_TO_sdram_controller_ba, -- .ba
sdram_controller_cas_n => CONNECTED_TO_sdram_controller_cas_n, -- .cas_n
sdram_controller_cke => CONNECTED_TO_sdram_controller_cke, -- .cke
sdram_controller_cs_n => CONNECTED_TO_sdram_controller_cs_n, -- .cs_n
sdram_controller_dq => CONNECTED_TO_sdram_controller_dq, -- .dq
sdram_controller_dqm => CONNECTED_TO_sdram_controller_dqm, -- .dqm
sdram_controller_ras_n => CONNECTED_TO_sdram_controller_ras_n, -- .ras_n
sdram_controller_we_n => CONNECTED_TO_sdram_controller_we_n, -- .we_n
timer_ecc_fault_itr_export => CONNECTED_TO_timer_ecc_fault_itr_export, -- timer_ecc_fault_itr.export
timer_interface_coe_sec_cnt_set_data_out => CONNECTED_TO_timer_interface_coe_sec_cnt_set_data_out, -- timer_interface.coe_sec_cnt_set_data_out
timer_interface_coe_sec_cnt_get_data_in => CONNECTED_TO_timer_interface_coe_sec_cnt_get_data_in, -- .coe_sec_cnt_get_data_in
timer_interface_coe_ns_cnt_set_data_out => CONNECTED_TO_timer_interface_coe_ns_cnt_set_data_out, -- .coe_ns_cnt_set_data_out
timer_interface_coe_ns_cnt_get_data_in => CONNECTED_TO_timer_interface_coe_ns_cnt_get_data_in, -- .coe_ns_cnt_get_data_in
timer_interface_coe_ctrl_cnt_set_out => CONNECTED_TO_timer_interface_coe_ctrl_cnt_set_out, -- .coe_ctrl_cnt_set_out
timer_interface_coe_ctrl_cnt_get_in => CONNECTED_TO_timer_interface_coe_ctrl_cnt_get_in, -- .coe_ctrl_cnt_get_in
timer_interface_coe_err_cnt_in => CONNECTED_TO_timer_interface_coe_err_cnt_in, -- .coe_err_cnt_in
timer_interface_coe_utc_time_in => CONNECTED_TO_timer_interface_coe_utc_time_in, -- .coe_utc_time_in
timer_interface_coe_time_zone_set_out => CONNECTED_TO_timer_interface_coe_time_zone_set_out, -- .coe_time_zone_set_out
timer_interface_coe_time_zone_get_in => CONNECTED_TO_timer_interface_coe_time_zone_get_in, -- .coe_time_zone_get_in
timer_interface_coe_leap_cnt_set_out => CONNECTED_TO_timer_interface_coe_leap_cnt_set_out, -- .coe_leap_cnt_set_out
timer_interface_coe_leap_cnt_get_in => CONNECTED_TO_timer_interface_coe_leap_cnt_get_in, -- .coe_leap_cnt_get_in
timer_interface_coe_leap_occur_set_out => CONNECTED_TO_timer_interface_coe_leap_occur_set_out, -- .coe_leap_occur_set_out
timer_interface_coe_leap_occur_get_in => CONNECTED_TO_timer_interface_coe_leap_occur_get_in, -- .coe_leap_occur_get_in
timer_interface_coe_dst_ingress_set_out => CONNECTED_TO_timer_interface_coe_dst_ingress_set_out, -- .coe_dst_ingress_set_out
timer_interface_coe_dst_ingress_get_in => CONNECTED_TO_timer_interface_coe_dst_ingress_get_in, -- .coe_dst_ingress_get_in
timer_interface_coe_dst_engress_set_out => CONNECTED_TO_timer_interface_coe_dst_engress_set_out, -- .coe_dst_engress_set_out
timer_interface_coe_dst_engress_get_in => CONNECTED_TO_timer_interface_coe_dst_engress_get_in, -- .coe_dst_engress_get_in
timer_interface_coe_leap_direct_get_in => CONNECTED_TO_timer_interface_coe_leap_direct_get_in, -- .coe_leap_direct_get_in
timer_interface_coe_leap_direct_set_out => CONNECTED_TO_timer_interface_coe_leap_direct_set_out, -- .coe_leap_direct_set_out
timer_interface_coe_io_update_in => CONNECTED_TO_timer_interface_coe_io_update_in, -- .coe_io_update_in
timer_interface_coe_time_quality_get_in => CONNECTED_TO_timer_interface_coe_time_quality_get_in, -- .coe_time_quality_get_in
timer_interface_coe_time_quality_set_out => CONNECTED_TO_timer_interface_coe_time_quality_set_out, -- .coe_time_quality_set_out
uart_0_external_connection_rxd => CONNECTED_TO_uart_0_external_connection_rxd, -- uart_0_external_connection.rxd
uart_0_external_connection_txd => CONNECTED_TO_uart_0_external_connection_txd, -- .txd
uart_1_external_connection_rxd => CONNECTED_TO_uart_1_external_connection_rxd, -- uart_1_external_connection.rxd
uart_1_external_connection_txd => CONNECTED_TO_uart_1_external_connection_txd, -- .txd
uart_2_external_connection_rxd => CONNECTED_TO_uart_2_external_connection_rxd, -- uart_2_external_connection.rxd
uart_2_external_connection_txd => CONNECTED_TO_uart_2_external_connection_txd, -- .txd
uart_3_external_connection_rxd => CONNECTED_TO_uart_3_external_connection_rxd, -- uart_3_external_connection.rxd
uart_3_external_connection_txd => CONNECTED_TO_uart_3_external_connection_txd -- .txd
);
| agpl-3.0 | e1302b1319b22c1990b0afdc5153c247 | 0.49882 | 3.682238 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/openmac/src/openmacPkg-p.vhd | 1 | 14,025 | -------------------------------------------------------------------------------
--! @file openmacPkg-p.vhd
--
--! @brief OpenMAC package
--
--! @details This is the openMAC package providing common types.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
package openmacPkg is
---------------------------------------------------------------------------
-- Configuration
---------------------------------------------------------------------------
--! Packet buffer is internal (e.g. memory blocks)
constant cPktBufLocal : natural := 1;
--! Packet buffer is external
constant cPktBufExtern : natural := 2;
--! Phy port(s) are Rmii
constant cPhyPortRmii : natural := 1;
--! Phy port(s) are Mii
constant cPhyPortMii : natural := 2;
---------------------------------------------------------------------------
-- (R)MII types and constants
---------------------------------------------------------------------------
--! RMII data width
constant cRmiiDataWidth : natural := 2;
--! MII data width
constant cMiiDataWidth : natural := 4;
--! RMII path
type tRmiiPath is record
enable : std_logic;
data : std_logic_vector(cRmiiDataWidth-1 downto 0);
end record;
--! MII path
type tMiiPath is record
enable : std_logic;
data : std_logic_vector(cMiiDataWidth-1 downto 0);
end record;
--! RMII path array
type tRmiiPathArray is array (natural range <>) of tRmiiPath;
--! MII path array
type tMiiPathArray is array (natural range <>) of tMiiPath;
--! RMII link
type tRmii is record
rx : tRmiiPath;
tx : tRmiiPath;
end record;
--! MII link
type tMii is record
rx : tMiiPath;
tx : tMiiPath;
end record;
--! RMII link array
type tRmiiArray is array (natural range <>) of tRmii;
--! MII link array
type tMiiArray is array (natural range <>) of tMii;
--! RMII path initialization
constant cRmiiPathInit : tRmiiPath := (
enable => cInactivated,
data => (others => cInactivated)
);
--! MII path initialization
constant cMiiPathInit : tMiiPath := (
enable => cInactivated,
data => (others => cInactivated)
);
--! RMII link initialization
constant cRmiiInit : tRmii := (
rx => cRmiiPathInit,
tx => cRmiiPathInit
);
--! MII link initialization
constant cMiiInit : tMii := (
rx => cMiiPathInit,
tx => cMiiPathInit
);
--! Functio to get tRmiiPathArray enables.
function rmiiGetEnable ( iArray : tRmiiPathArray ) return std_logic_vector;
--! Procedure to convert tRmiiPathArray to std_logic_vector.
procedure rmiiPathArrayToStdLogicVector (
signal iVector : in tRmiiPathArray;
signal oEnable : out std_logic_vector;
signal oData : out std_logic_vector
);
--! Procedure to convert std_logic_vector to tRmiiPathArray
procedure stdLogicVectorToRmiiPathArray (
signal iEnable : in std_logic_vector;
signal iData : in std_logic_vector;
signal oVector : out tRmiiPathArray
);
--! Procedure to convert tMiiPathArray to std_logic_vector.
procedure miiPathArrayToStdLogicVector (
signal iVector : in tMiiPathArray;
signal oEnable : out std_logic_vector;
signal oData : out std_logic_vector
);
--! Procedure to convert std_logic_vector to tMiiPathArray
procedure stdLogicVectorToMiiPathArray (
signal iEnable : in std_logic_vector;
signal iData : in std_logic_vector;
signal oVector : out tMiiPathArray
);
---------------------------------------------------------------------------
-- Memory mapping
---------------------------------------------------------------------------
--! Memory range type
type tMemRange is record
base : natural;
high : natural;
end record;
--! openMAC memory mapping type
type tMemMap is array (natural range <>) of tMemRange;
--! openMAC memory map count
constant cMemMapCount : natural := 6;
--! openMAC memory map index for DMA Error
constant cMemMapIndex_dmaError : natural := 5;
--! openMAC memory map index for IRQ Table
constant cMemMapIndex_irqTable : natural := 4;
--! openMAC memory map index for SMI
constant cMemMapIndex_smi : natural := 3;
--! openMAC memory map index for MAC RAM
constant cMemMapIndex_macRam : natural := 2;
--! openMAC memory map index for MAC Filter
constant cMemMapIndex_macFilter : natural := 1;
--! openMAC memory map index for MAC Content
constant cMemMapIndex_macCont : natural := 0;
--! openMAC memory mapping table
constant cMemMapTable : tMemMap(cMemMapCount-1 downto 0) := (
(base => 16#1020#, high => 16#102F#), -- DMA error
(base => 16#1010#, high => 16#101F#), -- IRQ table
(base => 16#1000#, high => 16#100F#), -- SMI
(base => 16#0800#, high => 16#0FFF#), -- MAC ram
(base => 16#0800#, high => 16#0BFF#), -- MAC filter
(base => 16#0000#, high => 16#03FF#) -- MAC content
);
---------------------------------------------------------------------------
-- Access delay
---------------------------------------------------------------------------
--! Access delay type
type tMemAccessDelay is record
write : natural;
read : natural;
end record;
--! Access delay type
type tMemAccessDelayArray is array (natural range <>) of tMemAccessDelay;
--! Access delay count
constant cMemAccessDelayCount : natural := 3;
--! Access delay index for PKT BUFFER
constant cMemAccessDelayIndex_pktBuf : natural := 2;
--! Access delay index for MAC TIMER
constant cMemAccessDelayIndex_macTimer : natural := 1;
--! Access delay index for MAC REG
constant cMemAccessDelayIndex_macReg : natural := 0;
--! Access delay table
constant cMemAccessDelayTable : tMemAccessDelayArray(cMemAccessDelayCount-1 downto 0) := (
(write => 0, read => 1), -- PKT BUFFER
(write => 0, read => 1), -- MAC TIMER
(write => 0, read => 1) -- MAC REG
);
--! Access acknowlegde type
type tMemAccessAck is record
write : std_logic;
read : std_logic;
end record;
--! Access acknowledge array type
type tMemAccessAckArray is array (natural range <>) of tMemAccessAck;
---------------------------------------------------------------------------
-- Constants for openmac
---------------------------------------------------------------------------
--! MAC REGISTER address width
constant cMacRegAddrWidth : natural := 13;
--! MAC REGISTER data width
constant cMacRegDataWidth : natural := 16;
--! MAC TIMER address width
constant cMacTimerAddrWidth : natural := 4;
--! MAC TIMER data width
constant cMacTimerDataWidth : natural := 32;
--! MAC PACKET BUFFER data width
constant cPktBufDataWidth : natural := 32;
--! MAC TIME width
constant cMacTimeWidth : natural := 32;
---------------------------------------------------------------------------
-- Constants for activity blinking
---------------------------------------------------------------------------
--! The activity blink frequency [Hz]
constant cActivityFreq : natural := 6;
--! Clock frequency of iClk [Hz]
constant cClkFreq : natural := 50e6;
---------------------------------------------------------------------------
-- Constants for openhub
---------------------------------------------------------------------------
--! Internal port number
constant cHubIntPort : natural := 1;
---------------------------------------------------------------------------
-- Interrupt table
---------------------------------------------------------------------------
--! Interrupt table subtype
subtype tMacRegIrqTable is std_logic_vector(cMacRegDataWidth-1 downto 0);
--! MAC Tx interrupt offset
constant cMacRegIrqTable_macTx : natural := 0;
--! MAC Rx interrupt offset
constant cMacRegIrqTable_macRx : natural := 1;
---------------------------------------------------------------------------
-- DMA Error table
---------------------------------------------------------------------------
--! DMA error table subtype
subtype tMacDmaErrorTable is std_logic_vector(cMacRegDataWidth-1 downto 0);
--! DMA error write (Rx packet transfer)
constant cMacDmaErrorTable_write : natural := 0;
--! DMA error read (Tx packet transfer)
constant cMacDmaErrorTable_read : natural := 8;
end package openmacPkg;
package body openmacPkg is
--! Functio to get tRmiiPathArray enables.
function rmiiGetEnable ( iArray : tRmiiPathArray ) return std_logic_vector is
variable vRes_tmp : std_logic_vector(iArray'range);
begin
vRes_tmp := (others => cInactivated);
for i in iArray'range loop
vRes_tmp(i) := iArray(i).enable;
end loop;
return vRes_tmp;
end function;
--! Procedure to convert tRmiiPathArray to std_logic_vector.
procedure rmiiPathArrayToStdLogicVector (
signal iVector : in tRmiiPathArray;
signal oEnable : out std_logic_vector;
signal oData : out std_logic_vector
) is
variable vVector_tmp : tRmiiPathArray(iVector'length-1 downto 0);
begin
vVector_tmp := iVector;
for i in vVector_tmp'range loop
oEnable(i) <= vVector_tmp(i).enable;
for j in cRmiiDataWidth-1 downto 0 loop
oData(i*cRmiiDataWidth+j) <= vVector_tmp(i).data(j);
end loop;
end loop;
end procedure;
--! Procedure to convert std_logic_vector to tRmiiPathArray
procedure stdLogicVectorToRmiiPathArray (
signal iEnable : in std_logic_vector;
signal iData : in std_logic_vector;
signal oVector : out tRmiiPathArray
) is
variable vVector_tmp : tRmiiPathArray(iEnable'length-1 downto 0);
begin
for i in vVector_tmp'range loop
vVector_tmp(i).enable := iEnable(i);
for j in cRmiiDataWidth-1 downto 0 loop
vVector_tmp(i).data(j) := iData(i*cRmiiDataWidth+j);
end loop;
end loop;
oVector <= vVector_tmp;
end procedure;
--! Procedure to convert tMiiPathArray to std_logic_vector.
procedure miiPathArrayToStdLogicVector (
signal iVector : in tMiiPathArray;
signal oEnable : out std_logic_vector;
signal oData : out std_logic_vector
) is
variable vVector_tmp : tMiiPathArray(iVector'length-1 downto 0);
begin
vVector_tmp := iVector;
for i in vVector_tmp'range loop
oEnable(i) <= vVector_tmp(i).enable;
for j in cMiiDataWidth-1 downto 0 loop
oData(i*cMiiDataWidth+j) <= vVector_tmp(i).data(j);
end loop;
end loop;
end procedure;
--! Procedure to convert std_logic_vector to tMiiPathArray
procedure stdLogicVectorToMiiPathArray (
signal iEnable : in std_logic_vector;
signal iData : in std_logic_vector;
signal oVector : out tMiiPathArray
) is
variable vVector_tmp : tMiiPathArray(iEnable'length-1 downto 0);
begin
for i in vVector_tmp'range loop
vVector_tmp(i).enable := iEnable(i);
for j in cMiiDataWidth-1 downto 0 loop
vVector_tmp(i).data(j) := iData(i*cMiiDataWidth+j);
end loop;
end loop;
oVector <= vVector_tmp;
end procedure;
end package body openmacPkg;
| gpl-2.0 | c14ff0337320f5a6a90e5b677c784980 | 0.554225 | 5.035907 | false | false | false | false |
cnplab/blockmon | fw-combo/src/IPFIX/comp/mi32_fsm_slave.vhd | 1 | 4,180 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- fsm_slave.vhd: FSM controlling asynchronous transfer at slave side
-- Copyright (C) 2006 CESNET
-- Author(s): Viktor Pus <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: fsm_slave.vhd 13034 2010-03-02 16:03:47Z pus $
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity MI32_ASYNC_FSMS is
port(
RESET : in std_logic;
CLK : in std_logic;
REQ : in std_logic;
DRDY : in std_logic;
ARDY : in std_logic;
ACK : out std_logic;
EN : out std_logic
);
end entity MI32_ASYNC_FSMS;
-- ----------------------------------------------------------------------------
-- Architecture
-- ----------------------------------------------------------------------------
architecture full of MI32_ASYNC_FSMS is
type t_fsmm is (wait_for_req, wait_for_drdy, wait_for_nreq);
signal fsm : t_fsmm;
signal fsm_next : t_fsmm;
begin
fsm_p : process(CLK, RESET)
begin
if RESET = '1' then
fsm <= wait_for_req;
elsif CLK'event and CLK = '1' then
fsm <= fsm_next;
end if;
end process;
fsm_next_p : process(fsm, REQ, DRDY, ARDY)
begin
fsm_next <= fsm;
case fsm is
when wait_for_req =>
if REQ = '1' and ARDY = '1' then
if DRDY = '1' then
fsm_next <= wait_for_nreq;
else
fsm_next <= wait_for_drdy;
end if;
end if;
when wait_for_drdy =>
if DRDY = '1' then
fsm_next <= wait_for_nreq;
end if;
when wait_for_nreq =>
if REQ = '0' then
fsm_next <= wait_for_req;
end if;
end case;
end process;
ACK <= '1' when fsm = wait_for_nreq else
'0';
EN <= '1' when fsm = wait_for_req and REQ = '1' else
'0';
end architecture full;
| bsd-3-clause | e885fb2badcb132eccc4633080332946 | 0.559091 | 4.265306 | false | false | false | false |
cnplab/blockmon | fw-combo/src/IPFIX/comp/first_one_detector.vhd | 1 | 7,128 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- first_one_detector.vhd: This component finds the first 'one' in the std_logic_vector
-- Copyright (C) 2006 CESNET, Liberouter project
-- Author(s): Jan Pazdera <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: first_one_detector.vhd 14001 2010-06-10 12:33:24Z xkoran01 $
--
-- TODO: -
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.numeric_std.all;
use std.textio.all;
-- pragma translate_off
library unisim;
use unisim.vcomponents.ALL;
-- pragma translate_on
use work.math_pack.all;
-- -------------------------------------------------------------
-- Entity :
-- -------------------------------------------------------------
entity first_one_detector is
generic (
DATA_WIDTH : integer
);
port (
-- Input
MASK : in std_logic_vector(DATA_WIDTH-1 downto 0);
-- Output
FIRST_ONE_ONEHOT : out std_logic_vector(DATA_WIDTH-1 downto 0); -- Position of the first 'one' in ONEHOT coding
FIRST_ONE_BINARY : out std_logic_vector(max(log2(DATA_WIDTH)-1, 0) downto 0); -- Position of the first 'one' in BINARY coding
FIRST_ONE_PRESENT : out std_logic -- Deasserted if no 'one' is present in input MASK
);
end first_one_detector;
-- -------------------------------------------------------------
-- Architecture :
-- -------------------------------------------------------------
architecture behavioral of first_one_detector is
type t_or_input is array (max(log2(DATA_WIDTH)-1, 0) downto 0) of std_logic_vector(DATA_WIDTH/2 downto 0);
type t_or_output is array (max(log2(DATA_WIDTH)-1, 0) downto 0) of std_logic_vector((DATA_WIDTH/2) downto 0);
signal qtr_first_one : std_logic_vector(((DATA_WIDTH-2)/3)+1 downto 0);
signal first_one_i : std_logic_vector(DATA_WIDTH-1 downto 0);
signal first_one_b : std_logic_vector(max(log2(DATA_WIDTH)-1, 0) downto 0);
signal first_one_or_input : t_or_input;
signal first_one_or_output : t_or_output;
begin
width_one_gen: if (DATA_WIDTH = 1) generate
first_one_i(0) <= MASK(0);
first_one_b(0) <= '0';
qtr_first_one(((DATA_WIDTH-2)/3)+1) <= MASK(0);
end generate;
width_greater_one_gen: if (DATA_WIDTH > 1) generate
-- -------------------------------------------------------------
-- qtr_first_one signal generation
qtr_first_one(0) <= MASK(0);
zero_module_gen: if ((DATA_WIDTH-1) mod 3 = 0) generate
qtr_first_one_gen: for i in 0 to ((DATA_WIDTH-2)/3) generate
qtr_first_one(i+1) <= qtr_first_one(i) or MASK((3*i) + 1) or MASK((3*i) + 2) or MASK((3*i) + 3);
end generate;
end generate;
one_module_gen: if ((DATA_WIDTH-1) mod 3 = 1) generate
qtr_first_one_gen: for i in 0 to ((DATA_WIDTH-2)/3) generate
non_last_i_gen: if (i < ((DATA_WIDTH-2)/3)) generate
qtr_first_one(i+1) <= qtr_first_one(i) or MASK((3*i) + 1) or MASK((3*i) + 2) or MASK((3*i) + 3);
end generate;
last_i_gen: if (i = ((DATA_WIDTH-2)/3)) generate
qtr_first_one(i+1) <= qtr_first_one(i) or MASK((3*i) + 1);
end generate;
end generate;
end generate;
two_module_gen: if ((DATA_WIDTH-1) mod 3 = 2) generate
qtr_first_one_gen: for i in 0 to ((DATA_WIDTH-2)/3) generate
non_last_i_gen: if (i < ((DATA_WIDTH-2)/3)) generate
qtr_first_one(i+1) <= qtr_first_one(i) or MASK((3*i) + 1) or MASK((3*i) + 2) or MASK((3*i) + 3);
end generate;
last_i_gen: if (i = ((DATA_WIDTH-2)/3)) generate
qtr_first_one(i+1) <= qtr_first_one(i) or MASK((3*i) + 1) or MASK((3*i) + 2);
end generate;
end generate;
end generate;
-- -------------------------------------------------------------
-- first_one_i signal generation
first_one_i(0) <= MASK(0);
first_one_i_gen: for i in 1 to (DATA_WIDTH - 1) generate
zero_module_gen: if ((i-1) mod 3 = 0) generate
first_one_i(i) <= (not qtr_first_one((i-1)/3)) and MASK(i);
end generate;
one_module_gen: if ((i-1) mod 3 = 1) generate
first_one_i(i) <= (not qtr_first_one((i-1)/3)) and (not first_one_i(i-1)) and MASK(i);
end generate;
two_module_gen: if ((i-1) mod 3 = 2) generate
first_one_i(i) <= (not qtr_first_one((i-1)/3)) and (not first_one_i(i-1)) and (not first_one_i(i-2)) and MASK(i);
end generate;
end generate;
end generate;
-- Encoder providing correct translation from ONEHOT to BINARY encoding
encoder_i : entity work.GEN_ENC
generic map (
ITEMS => DATA_WIDTH
)
port map (
DI => first_one_i,
ADDR => first_one_b
);
-- -------------------------------------------------------------
-- Output mapping
FIRST_ONE_ONEHOT <= first_one_i;
FIRST_ONE_BINARY <= first_one_b;
FIRST_ONE_PRESENT <= qtr_first_one(((DATA_WIDTH-2)/3)+1);
end behavioral;
| bsd-3-clause | ce84c78c1d38c8df6ba2210925e2bf29 | 0.57688 | 3.549801 | false | false | false | false |
chiggs/oc_mkjpeg | design/iramif/IRAMIF.vhd | 2 | 2,403 | -------------------------------------------------------------------------------
-- File Name : IRamIF.vhd
--
-- Project : JPEG_ENC
--
-- Module : IRamIF
--
-- Content : IMAGE RAM Interface
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity IRamIF is
port
(
CLK : in std_logic;
RST : in std_logic;
-- IMAGE RAM
iram_addr : out std_logic_vector(19 downto 0);
iram_rdata : in std_logic_vector(23 downto 0);
-- FDCT
jpg_iram_rden : in std_logic;
jpg_iram_rdaddr : in std_logic_vector(31 downto 0);
jpg_iram_data : out std_logic_vector(23 downto 0)
);
end entity IRamIF;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of IRamIF is
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
jpg_iram_data <= iram_rdata;
-------------------------------------------------------------------
--
-------------------------------------------------------------------
p_if : process(CLK, RST)
begin
if RST = '1' then
iram_addr <= (others => '0');
elsif CLK'event and CLK = '1' then
-- host has access
iram_addr <= jpg_iram_rdaddr(iram_addr'range);
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- | lgpl-3.0 | f8d1143730a1fd457f6ae1547cd6fd19 | 0.275905 | 5.804348 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | staging/fpga/boards/altera/SYSTEC_ECUcore-EP3C/design_nios2_directIO/niosII_openMac_clock_3.vhd | 8 | 29,330 | --Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity niosII_openMac_clock_3_edge_to_pulse is
port (
-- inputs:
signal clock : IN STD_LOGIC;
signal data_in : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal data_out : OUT STD_LOGIC
);
end entity niosII_openMac_clock_3_edge_to_pulse;
architecture europa of niosII_openMac_clock_3_edge_to_pulse is
signal data_in_d1 : STD_LOGIC;
begin
process (clock, reset_n)
begin
if reset_n = '0' then
data_in_d1 <= std_logic'('0');
elsif clock'event and clock = '1' then
data_in_d1 <= data_in;
end if;
end process;
data_out <= data_in XOR data_in_d1;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity niosII_openMac_clock_3_slave_FSM is
port (
-- inputs:
signal master_read_done_token : IN STD_LOGIC;
signal master_write_done_token : IN STD_LOGIC;
signal slave_clk : IN STD_LOGIC;
signal slave_read : IN STD_LOGIC;
signal slave_reset_n : IN STD_LOGIC;
signal slave_write : IN STD_LOGIC;
-- outputs:
signal slave_read_request : OUT STD_LOGIC;
signal slave_waitrequest : OUT STD_LOGIC;
signal slave_write_request : OUT STD_LOGIC
);
end entity niosII_openMac_clock_3_slave_FSM;
architecture europa of niosII_openMac_clock_3_slave_FSM is
signal internal_slave_read_request : STD_LOGIC;
signal internal_slave_write_request : STD_LOGIC;
signal next_slave_read_request : STD_LOGIC;
signal next_slave_state : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal next_slave_write_request : STD_LOGIC;
signal slave_state : STD_LOGIC_VECTOR (2 DOWNTO 0);
begin
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
internal_slave_read_request <= std_logic'('0');
elsif slave_clk'event and slave_clk = '1' then
if true then
internal_slave_read_request <= next_slave_read_request;
end if;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
internal_slave_write_request <= std_logic'('0');
elsif slave_clk'event and slave_clk = '1' then
if true then
internal_slave_write_request <= next_slave_write_request;
end if;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
slave_state <= std_logic_vector'("001");
elsif slave_clk'event and slave_clk = '1' then
if true then
slave_state <= next_slave_state;
end if;
end if;
end process;
process (internal_slave_read_request, internal_slave_write_request, master_read_done_token, master_write_done_token, slave_read, slave_state, slave_write)
begin
case slave_state is -- synthesis parallel_case
when std_logic_vector'("001") =>
--read request: go from IDLE state to READ_WAIT state
if std_logic'(slave_read) = '1' then
next_slave_state <= std_logic_vector'("010");
slave_waitrequest <= std_logic'('1');
next_slave_read_request <= NOT(internal_slave_read_request);
next_slave_write_request <= internal_slave_write_request;
elsif std_logic'(slave_write) = '1' then
next_slave_state <= std_logic_vector'("100");
slave_waitrequest <= std_logic'('1');
next_slave_read_request <= internal_slave_read_request;
next_slave_write_request <= NOT(internal_slave_write_request);
else
next_slave_state <= slave_state;
slave_waitrequest <= std_logic'('0');
next_slave_read_request <= internal_slave_read_request;
next_slave_write_request <= internal_slave_write_request;
end if;
-- when std_logic_vector'("001")
when std_logic_vector'("010") =>
--stay in READ_WAIT state until master passes read done token
if std_logic'(master_read_done_token) = '1' then
next_slave_state <= std_logic_vector'("001");
slave_waitrequest <= std_logic'('0');
else
next_slave_state <= std_logic_vector'("010");
slave_waitrequest <= std_logic'('1');
end if;
next_slave_read_request <= internal_slave_read_request;
next_slave_write_request <= internal_slave_write_request;
-- when std_logic_vector'("010")
when std_logic_vector'("100") =>
--stay in WRITE_WAIT state until master passes write done token
if std_logic'(master_write_done_token) = '1' then
next_slave_state <= std_logic_vector'("001");
slave_waitrequest <= std_logic'('0');
else
next_slave_state <= std_logic_vector'("100");
slave_waitrequest <= std_logic'('1');
end if;
next_slave_read_request <= internal_slave_read_request;
next_slave_write_request <= internal_slave_write_request;
-- when std_logic_vector'("100")
when others =>
next_slave_state <= std_logic_vector'("001");
slave_waitrequest <= std_logic'('0');
next_slave_read_request <= internal_slave_read_request;
next_slave_write_request <= internal_slave_write_request;
-- when others
end case; -- slave_state
end process;
--vhdl renameroo for output signals
slave_read_request <= internal_slave_read_request;
--vhdl renameroo for output signals
slave_write_request <= internal_slave_write_request;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity niosII_openMac_clock_3_master_FSM is
port (
-- inputs:
signal master_clk : IN STD_LOGIC;
signal master_reset_n : IN STD_LOGIC;
signal master_waitrequest : IN STD_LOGIC;
signal slave_read_request_token : IN STD_LOGIC;
signal slave_write_request_token : IN STD_LOGIC;
-- outputs:
signal master_read : OUT STD_LOGIC;
signal master_read_done : OUT STD_LOGIC;
signal master_write : OUT STD_LOGIC;
signal master_write_done : OUT STD_LOGIC
);
end entity niosII_openMac_clock_3_master_FSM;
architecture europa of niosII_openMac_clock_3_master_FSM is
signal internal_master_read1 : STD_LOGIC;
signal internal_master_read_done : STD_LOGIC;
signal internal_master_write1 : STD_LOGIC;
signal internal_master_write_done : STD_LOGIC;
signal master_state : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal next_master_read : STD_LOGIC;
signal next_master_read_done : STD_LOGIC;
signal next_master_state : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal next_master_write : STD_LOGIC;
signal next_master_write_done : STD_LOGIC;
begin
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
internal_master_read_done <= std_logic'('0');
elsif master_clk'event and master_clk = '1' then
if true then
internal_master_read_done <= next_master_read_done;
end if;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
internal_master_write_done <= std_logic'('0');
elsif master_clk'event and master_clk = '1' then
if true then
internal_master_write_done <= next_master_write_done;
end if;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
internal_master_read1 <= std_logic'('0');
elsif master_clk'event and master_clk = '1' then
if true then
internal_master_read1 <= next_master_read;
end if;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
internal_master_write1 <= std_logic'('0');
elsif master_clk'event and master_clk = '1' then
if true then
internal_master_write1 <= next_master_write;
end if;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
master_state <= std_logic_vector'("001");
elsif master_clk'event and master_clk = '1' then
if true then
master_state <= next_master_state;
end if;
end if;
end process;
process (internal_master_read1, internal_master_read_done, internal_master_write1, internal_master_write_done, master_state, master_waitrequest, slave_read_request_token, slave_write_request_token)
begin
case master_state is -- synthesis parallel_case
when std_logic_vector'("001") =>
--if read request token from slave then goto READ_WAIT state
if std_logic'(slave_read_request_token) = '1' then
next_master_state <= std_logic_vector'("010");
next_master_read <= std_logic'('1');
next_master_write <= std_logic'('0');
elsif std_logic'(slave_write_request_token) = '1' then
next_master_state <= std_logic_vector'("100");
next_master_read <= std_logic'('0');
next_master_write <= std_logic'('1');
else
next_master_state <= master_state;
next_master_read <= std_logic'('0');
next_master_write <= std_logic'('0');
end if;
next_master_read_done <= internal_master_read_done;
next_master_write_done <= internal_master_write_done;
-- when std_logic_vector'("001")
when std_logic_vector'("010") =>
--stay in READ_WAIT state until master wait is deasserted
if std_logic'(NOT(master_waitrequest)) = '1' then
next_master_state <= std_logic_vector'("001");
next_master_read_done <= NOT(internal_master_read_done);
next_master_read <= std_logic'('0');
else
next_master_state <= std_logic_vector'("010");
next_master_read_done <= internal_master_read_done;
next_master_read <= internal_master_read1;
end if;
next_master_write_done <= internal_master_write_done;
next_master_write <= std_logic'('0');
-- when std_logic_vector'("010")
when std_logic_vector'("100") =>
--stay in WRITE_WAIT state until slave wait is deasserted
if std_logic'(NOT(master_waitrequest)) = '1' then
next_master_state <= std_logic_vector'("001");
next_master_write <= std_logic'('0');
next_master_write_done <= NOT(internal_master_write_done);
else
next_master_state <= std_logic_vector'("100");
next_master_write <= internal_master_write1;
next_master_write_done <= internal_master_write_done;
end if;
next_master_read_done <= internal_master_read_done;
next_master_read <= std_logic'('0');
-- when std_logic_vector'("100")
when others =>
next_master_state <= std_logic_vector'("001");
next_master_write <= std_logic'('0');
next_master_write_done <= internal_master_write_done;
next_master_read <= std_logic'('0');
next_master_read_done <= internal_master_read_done;
-- when others
end case; -- master_state
end process;
--vhdl renameroo for output signals
master_read <= internal_master_read1;
--vhdl renameroo for output signals
master_read_done <= internal_master_read_done;
--vhdl renameroo for output signals
master_write <= internal_master_write1;
--vhdl renameroo for output signals
master_write_done <= internal_master_write_done;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity niosII_openMac_clock_3_bit_pipe is
port (
-- inputs:
signal clk1 : IN STD_LOGIC;
signal clk2 : IN STD_LOGIC;
signal data_in : IN STD_LOGIC;
signal reset_clk1_n : IN STD_LOGIC;
signal reset_clk2_n : IN STD_LOGIC;
-- outputs:
signal data_out : OUT STD_LOGIC
);
end entity niosII_openMac_clock_3_bit_pipe;
architecture europa of niosII_openMac_clock_3_bit_pipe is
signal data_in_d1 : STD_LOGIC;
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of data_in_d1 : signal is "{-to ""*""} CUT=ON ; PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of data_out : signal is "PRESERVE_REGISTER=ON";
begin
process (clk1, reset_clk1_n)
begin
if reset_clk1_n = '0' then
data_in_d1 <= std_logic'('0');
elsif clk1'event and clk1 = '1' then
data_in_d1 <= data_in;
end if;
end process;
process (clk2, reset_clk2_n)
begin
if reset_clk2_n = '0' then
data_out <= std_logic'('0');
elsif clk2'event and clk2 = '1' then
data_out <= data_in_d1;
end if;
end process;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--Clock Domain Crossing AdapterniosII_openMac_clock_3
entity niosII_openMac_clock_3 is
port (
-- inputs:
signal master_clk : IN STD_LOGIC;
signal master_endofpacket : IN STD_LOGIC;
signal master_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal master_reset_n : IN STD_LOGIC;
signal master_waitrequest : IN STD_LOGIC;
signal slave_address : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal slave_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal slave_clk : IN STD_LOGIC;
signal slave_nativeaddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal slave_read : IN STD_LOGIC;
signal slave_reset_n : IN STD_LOGIC;
signal slave_write : IN STD_LOGIC;
signal slave_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- outputs:
signal master_address : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal master_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal master_nativeaddress : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal master_read : OUT STD_LOGIC;
signal master_write : OUT STD_LOGIC;
signal master_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal slave_endofpacket : OUT STD_LOGIC;
signal slave_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal slave_waitrequest : OUT STD_LOGIC
);
end entity niosII_openMac_clock_3;
architecture europa of niosII_openMac_clock_3 is
component altera_std_synchronizer is
GENERIC (
depth : NATURAL
);
PORT (
signal dout : OUT STD_LOGIC;
signal clk : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal din : IN STD_LOGIC
);
end component altera_std_synchronizer;
component niosII_openMac_clock_3_edge_to_pulse is
port (
-- inputs:
signal clock : IN STD_LOGIC;
signal data_in : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal data_out : OUT STD_LOGIC
);
end component niosII_openMac_clock_3_edge_to_pulse;
component niosII_openMac_clock_3_slave_FSM is
port (
-- inputs:
signal master_read_done_token : IN STD_LOGIC;
signal master_write_done_token : IN STD_LOGIC;
signal slave_clk : IN STD_LOGIC;
signal slave_read : IN STD_LOGIC;
signal slave_reset_n : IN STD_LOGIC;
signal slave_write : IN STD_LOGIC;
-- outputs:
signal slave_read_request : OUT STD_LOGIC;
signal slave_waitrequest : OUT STD_LOGIC;
signal slave_write_request : OUT STD_LOGIC
);
end component niosII_openMac_clock_3_slave_FSM;
component niosII_openMac_clock_3_master_FSM is
port (
-- inputs:
signal master_clk : IN STD_LOGIC;
signal master_reset_n : IN STD_LOGIC;
signal master_waitrequest : IN STD_LOGIC;
signal slave_read_request_token : IN STD_LOGIC;
signal slave_write_request_token : IN STD_LOGIC;
-- outputs:
signal master_read : OUT STD_LOGIC;
signal master_read_done : OUT STD_LOGIC;
signal master_write : OUT STD_LOGIC;
signal master_write_done : OUT STD_LOGIC
);
end component niosII_openMac_clock_3_master_FSM;
component niosII_openMac_clock_3_bit_pipe is
port (
-- inputs:
signal clk1 : IN STD_LOGIC;
signal clk2 : IN STD_LOGIC;
signal data_in : IN STD_LOGIC;
signal reset_clk1_n : IN STD_LOGIC;
signal reset_clk2_n : IN STD_LOGIC;
-- outputs:
signal data_out : OUT STD_LOGIC
);
end component niosII_openMac_clock_3_bit_pipe;
signal internal_master_read : STD_LOGIC;
signal internal_master_write : STD_LOGIC;
signal internal_slave_endofpacket : STD_LOGIC;
signal internal_slave_waitrequest : STD_LOGIC;
signal master_read_done : STD_LOGIC;
signal master_read_done_sync : STD_LOGIC;
signal master_read_done_token : STD_LOGIC;
signal master_write_done : STD_LOGIC;
signal master_write_done_sync : STD_LOGIC;
signal master_write_done_token : STD_LOGIC;
signal slave_address_d1 : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal slave_byteenable_d1 : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal slave_nativeaddress_d1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal slave_read_request : STD_LOGIC;
signal slave_read_request_sync : STD_LOGIC;
signal slave_read_request_token : STD_LOGIC;
signal slave_readdata_p1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal slave_write_request : STD_LOGIC;
signal slave_write_request_sync : STD_LOGIC;
signal slave_write_request_token : STD_LOGIC;
signal slave_writedata_d1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of master_address : signal is "PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of master_byteenable : signal is "PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of master_nativeaddress : signal is "PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of master_writedata : signal is "PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of slave_address_d1 : signal is "{-to ""*""} CUT=ON ; PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of slave_byteenable_d1 : signal is "{-to ""*""} CUT=ON ; PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of slave_nativeaddress_d1 : signal is "{-to ""*""} CUT=ON ; PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of slave_readdata : signal is "{-from ""*""} CUT=ON";
attribute ALTERA_ATTRIBUTE of slave_writedata_d1 : signal is "{-to ""*""} CUT=ON ; PRESERVE_REGISTER=ON";
begin
--in, which is an e_avalon_slave
--out, which is an e_avalon_master
the_altera_std_synchronizer : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => slave_clk,
din => master_read_done,
dout => master_read_done_sync,
reset_n => slave_reset_n
);
the_altera_std_synchronizer1 : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => slave_clk,
din => master_write_done,
dout => master_write_done_sync,
reset_n => slave_reset_n
);
--read_done_edge_to_pulse, which is an e_instance
read_done_edge_to_pulse : niosII_openMac_clock_3_edge_to_pulse
port map(
data_out => master_read_done_token,
clock => slave_clk,
data_in => master_read_done_sync,
reset_n => slave_reset_n
);
--write_done_edge_to_pulse, which is an e_instance
write_done_edge_to_pulse : niosII_openMac_clock_3_edge_to_pulse
port map(
data_out => master_write_done_token,
clock => slave_clk,
data_in => master_write_done_sync,
reset_n => slave_reset_n
);
--slave_FSM, which is an e_instance
slave_FSM : niosII_openMac_clock_3_slave_FSM
port map(
slave_read_request => slave_read_request,
slave_waitrequest => internal_slave_waitrequest,
slave_write_request => slave_write_request,
master_read_done_token => master_read_done_token,
master_write_done_token => master_write_done_token,
slave_clk => slave_clk,
slave_read => slave_read,
slave_reset_n => slave_reset_n,
slave_write => slave_write
);
the_altera_std_synchronizer2 : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => master_clk,
din => slave_read_request,
dout => slave_read_request_sync,
reset_n => master_reset_n
);
the_altera_std_synchronizer3 : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => master_clk,
din => slave_write_request,
dout => slave_write_request_sync,
reset_n => master_reset_n
);
--read_request_edge_to_pulse, which is an e_instance
read_request_edge_to_pulse : niosII_openMac_clock_3_edge_to_pulse
port map(
data_out => slave_read_request_token,
clock => master_clk,
data_in => slave_read_request_sync,
reset_n => master_reset_n
);
--write_request_edge_to_pulse, which is an e_instance
write_request_edge_to_pulse : niosII_openMac_clock_3_edge_to_pulse
port map(
data_out => slave_write_request_token,
clock => master_clk,
data_in => slave_write_request_sync,
reset_n => master_reset_n
);
--master_FSM, which is an e_instance
master_FSM : niosII_openMac_clock_3_master_FSM
port map(
master_read => internal_master_read,
master_read_done => master_read_done,
master_write => internal_master_write,
master_write_done => master_write_done,
master_clk => master_clk,
master_reset_n => master_reset_n,
master_waitrequest => master_waitrequest,
slave_read_request_token => slave_read_request_token,
slave_write_request_token => slave_write_request_token
);
--endofpacket_bit_pipe, which is an e_instance
endofpacket_bit_pipe : niosII_openMac_clock_3_bit_pipe
port map(
data_out => internal_slave_endofpacket,
clk1 => slave_clk,
clk2 => master_clk,
data_in => master_endofpacket,
reset_clk1_n => slave_reset_n,
reset_clk2_n => master_reset_n
);
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
slave_readdata_p1 <= std_logic_vector'("00000000000000000000000000000000");
elsif master_clk'event and master_clk = '1' then
if std_logic'((internal_master_read AND NOT master_waitrequest)) = '1' then
slave_readdata_p1 <= master_readdata;
end if;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
slave_readdata <= std_logic_vector'("00000000000000000000000000000000");
elsif slave_clk'event and slave_clk = '1' then
slave_readdata <= slave_readdata_p1;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
slave_writedata_d1 <= std_logic_vector'("00000000000000000000000000000000");
elsif slave_clk'event and slave_clk = '1' then
slave_writedata_d1 <= slave_writedata;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
master_writedata <= std_logic_vector'("00000000000000000000000000000000");
elsif master_clk'event and master_clk = '1' then
master_writedata <= slave_writedata_d1;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
slave_address_d1 <= std_logic_vector'("0000");
elsif slave_clk'event and slave_clk = '1' then
slave_address_d1 <= slave_address;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
master_address <= std_logic_vector'("0000");
elsif master_clk'event and master_clk = '1' then
master_address <= slave_address_d1;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
slave_nativeaddress_d1 <= std_logic_vector'("00");
elsif slave_clk'event and slave_clk = '1' then
slave_nativeaddress_d1 <= slave_nativeaddress;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
master_nativeaddress <= std_logic_vector'("00");
elsif master_clk'event and master_clk = '1' then
master_nativeaddress <= slave_nativeaddress_d1;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
slave_byteenable_d1 <= std_logic_vector'("0000");
elsif slave_clk'event and slave_clk = '1' then
slave_byteenable_d1 <= slave_byteenable;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
master_byteenable <= std_logic_vector'("0000");
elsif master_clk'event and master_clk = '1' then
master_byteenable <= slave_byteenable_d1;
end if;
end process;
--vhdl renameroo for output signals
master_read <= internal_master_read;
--vhdl renameroo for output signals
master_write <= internal_master_write;
--vhdl renameroo for output signals
slave_endofpacket <= internal_slave_endofpacket;
--vhdl renameroo for output signals
slave_waitrequest <= internal_slave_waitrequest;
end europa;
| gpl-2.0 | f19b6f3a277006aa247386ab0b54539d | 0.597341 | 3.92795 | false | false | false | false |
chiggs/oc_mkjpeg | tb/vhdl/HostBFM.vhd | 1 | 16,219 | -------------------------------------------------------------------------------
-- File Name : HostBFM.vhd
--
-- Project : JPEG_ENC
--
-- Module : HostBFM
--
-- Content : Host BFM (Xilinx OPB v2.1)
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_TEXTIO.ALL;
library STD;
use STD.TEXTIO.ALL;
library work;
use work.GPL_V2_Image_Pkg.ALL;
use WORK.MDCT_PKG.all;
use WORK.MDCTTB_PKG.all;
use work.JPEG_PKG.all;
entity HostBFM is
port
(
CLK : in std_logic;
RST : in std_logic;
-- OPB
OPB_ABus : out std_logic_vector(31 downto 0);
OPB_BE : out std_logic_vector(3 downto 0);
OPB_DBus_in : out std_logic_vector(31 downto 0);
OPB_RNW : out std_logic;
OPB_select : out std_logic;
OPB_DBus_out : in std_logic_vector(31 downto 0);
OPB_XferAck : in std_logic;
OPB_retry : in std_logic;
OPB_toutSup : in std_logic;
OPB_errAck : in std_logic;
-- HOST DATA
iram_wdata : out std_logic_vector(C_PIXEL_BITS-1 downto 0);
iram_wren : out std_logic;
fifo_almost_full : in std_logic;
sim_done : out std_logic
);
end entity HostBFM;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of HostBFM is
signal num_comps : integer;
signal addr_inc : integer := 0;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- code
-------------------------------------------------------------------
p_code : process
-----------------------------------------------------------------
-- HOST WRITE
-----------------------------------------------------------------
procedure host_write
(
signal clk : in std_logic;
constant C_ADDR : in unsigned(31 downto 0);
constant C_WDATA : in unsigned(31 downto 0);
signal OPB_ABus : out std_logic_vector(31 downto 0);
signal OPB_BE : out std_logic_vector(3 downto 0);
signal OPB_DBus_in : out std_logic_vector(31 downto 0);
signal OPB_RNW : out std_logic;
signal OPB_select : out std_logic;
signal OPB_XferAck : in std_logic
) is
begin
OPB_ABus <= (others => '0');
OPB_BE <= (others => '0');
OPB_DBus_in <= (others => '0');
OPB_RNW <= '0';
OPB_select <= '0';
wait until rising_edge(clk);
OPB_select <= '1';
OPB_ABus <= std_logic_vector(C_ADDR);
OPB_RNW <= '0';
OPB_BE <= X"F";
OPB_DBus_in <= std_logic_vector(C_WDATA);
wait until rising_edge(clk);
while OPB_XferAck /= '1' loop
wait until rising_edge(clk);
end loop;
OPB_ABus <= (others => '0');
OPB_BE <= (others => '0');
OPB_DBus_in <= (others => '0');
OPB_RNW <= '0';
OPB_select <= '0';
assert false
report CR&"Host write access, address = " & HexImage(C_ADDR) & ",data written = " & HexImage(C_WDATA) &CR
severity note;
wait until rising_edge(clk);
end procedure host_write;
-----------------------------------------------------------------
-- HOST READ
-----------------------------------------------------------------
procedure host_read
(
signal clk : in std_logic;
constant C_ADDR : in unsigned(31 downto 0);
variable RDATA : out unsigned(31 downto 0);
signal OPB_ABus : out std_logic_vector(31 downto 0);
signal OPB_BE : out std_logic_vector(3 downto 0);
signal OPB_DBus_out : in std_logic_vector(31 downto 0);
signal OPB_RNW : out std_logic;
signal OPB_select : out std_logic;
signal OPB_XferAck : in std_logic
)
is
variable data_r : std_logic_vector(31 downto 0);
begin
OPB_ABus <= (others => '0');
OPB_BE <= (others => '0');
OPB_DBus_in <= (others => '0');
OPB_RNW <= '0';
OPB_select <= '0';
wait until rising_edge(clk);
OPB_select <= '1';
OPB_ABus <= std_logic_vector(C_ADDR);
OPB_RNW <= '1';
OPB_BE <= X"F";
wait until rising_edge(clk);
while OPB_XferAck /= '1' loop
wait until rising_edge(clk);
end loop;
RDATA := unsigned(OPB_DBus_out);
data_r := OPB_DBus_out;
OPB_ABus <= (others => '0');
OPB_BE <= (others => '0');
OPB_DBus_in <= (others => '0');
OPB_RNW <= '0';
OPB_select <= '0';
assert false
report CR&"Host read access, address = " & HexImage(C_ADDR) & ",data read = " & HexImage(data_r) &CR
severity note;
wait until rising_edge(clk);
end procedure host_read;
--------------------------------------
-- read text image data
--------------------------------------
procedure read_image is
file infile : TEXT open read_mode is "test.txt";
constant N : integer := 8;
constant MAX_COMPS : integer := 3;
variable inline : LINE;
variable tmp_int : INTEGER := 0;
variable y_size : INTEGER := 0;
variable x_size : INTEGER := 0;
variable matrix : I_MATRIX_TYPE;
variable x_blk_cnt : INTEGER := 0;
variable y_blk_cnt : INTEGER := 0;
variable n_lines_arr : N_LINES_TYPE;
variable line_n : INTEGER := 0;
variable pix_n : INTEGER := 0;
variable x_n : INTEGER := 0;
variable y_n : INTEGER := 0;
variable data_word : unsigned(31 downto 0);
variable image_line : STD_LOGIC_VECTOR(0 to MAX_COMPS*MAX_IMAGE_SIZE_X*IP_W-1);
constant C_IMAGE_RAM_BASE : unsigned(31 downto 0) := X"0010_0000";
variable x_cnt : integer;
variable data_word2 : unsigned(31 downto 0);
variable num_comps_v : integer;
begin
READLINE(infile,inline);
READ(inline,num_comps_v);
READLINE(infile,inline);
READ(inline,y_size);
READLINE(infile,inline);
READ(inline,x_size);
num_comps <= num_comps_v;
if y_size rem N > 0 then
assert false
report "ERROR: Image height dimension is not multiply of 8!"
severity Failure;
end if;
if x_size rem N > 0 then
assert false
report "ERROR: Image width dimension is not multiply of 8!"
severity Failure;
end if;
if x_size > C_MAX_LINE_WIDTH then
assert false
report "ERROR: Image width bigger than C_MAX_LINE_WIDTH in JPEG_PKG.VHD! " &
"Increase C_MAX_LINE_WIDTH accordingly"
severity Failure;
end if;
addr_inc <= 0;
-- image size
host_write(CLK, X"0000_0004", to_unsigned(x_size,16) & to_unsigned(y_size,16),
OPB_ABus, OPB_BE, OPB_DBus_in, OPB_RNW, OPB_select, OPB_XferAck);
iram_wren <= '0';
for y_n in 0 to y_size-1 loop
READLINE(infile,inline);
HREAD(inline,image_line(0 to num_comps*x_size*IP_W-1));
x_cnt := 0;
for x_n in 0 to x_size-1 loop
data_word := X"00" & UNSIGNED(image_line(x_cnt to x_cnt+num_comps*IP_W-1));
if C_PIXEL_BITS = 24 then
data_word2(7 downto 0) := data_word(23 downto 16);
data_word2(15 downto 8) := data_word(15 downto 8);
data_word2(23 downto 16) := data_word(7 downto 0);
else
data_word2(4 downto 0) := data_word(23 downto 19);
data_word2(10 downto 5) := data_word(15 downto 10);
data_word2(15 downto 11) := data_word(7 downto 3);
end if;
iram_wren <= '0';
iram_wdata <= (others => 'X');
while(fifo_almost_full = '1') loop
wait until rising_edge(clk);
end loop;
--for i in 0 to 4 loop
-- wait until rising_edge(clk);
--end loop;
iram_wren <= '1';
iram_wdata <= std_logic_vector(data_word2(C_PIXEL_BITS-1 downto 0));
wait until rising_edge(clk);
x_cnt := x_cnt + num_comps*IP_W;
addr_inc <= addr_inc + 1;
end loop;
end loop;
iram_wren <= '0';
end read_image;
------------------
type ROMQ_TYPE is array (0 to 64-1)
of unsigned(7 downto 0);
constant qrom_lum : ROMQ_TYPE :=
(
-- 100%
--others => X"01"
-- 85%
X"05", X"03", X"04", X"04",
X"04", X"03", X"05", X"04",
X"04", X"04", X"05", X"05",
X"05", X"06", X"07", X"0C",
X"08", X"07", X"07", X"07",
X"07", X"0F", X"0B", X"0B",
X"09", X"0C", X"11", X"0F",
X"12", X"12", X"11", X"0F",
X"11", X"11", X"13", X"16",
X"1C", X"17", X"13", X"14",
X"1A", X"15", X"11", X"11",
X"18", X"21", X"18", X"1A",
X"1D", X"1D", X"1F", X"1F",
X"1F", X"13", X"17", X"22",
X"24", X"22", X"1E", X"24",
X"1C", X"1E", X"1F", X"1E"
-- 100%
--others => X"01"
-- 75%
--X"08", X"06", X"06", X"07", X"06", X"05", X"08", X"07", X"07", X"07", X"09", X"09", X"08", X"0A", X"0C", X"14",
--X"0D", X"0C", X"0B", X"0B", X"0C", X"19", X"12", X"13", X"0F", X"14", X"1D", X"1A", X"1F", X"1E", X"1D", X"1A",
--X"1C", X"1C", X"20", X"24", X"2E", X"27", X"20", X"22", X"2C", X"23", X"1C", X"1C", X"28", X"37", X"29", X"2C",
--X"30", X"31", X"34", X"34", X"34", X"1F", X"27", X"39", X"3D", X"38", X"32", X"3C", X"2E", X"33", X"34", X"32"
-- 15 %
--X"35", X"25", X"28", X"2F",
--X"28", X"21", X"35", X"2F",
--X"2B", X"2F", X"3C", X"39",
--X"35", X"3F", X"50", X"85",
--X"57", X"50", X"49", X"49",
--X"50", X"A3", X"75", X"7B",
--X"61", X"85", X"C1", X"AA",
--X"CB", X"C8", X"BE", X"AA",
--X"BA", X"B7", X"D5", X"F0",
--X"FF", X"FF", X"D5", X"E2",
--X"FF", X"E6", X"B7", X"BA",
--X"FF", X"FF", X"FF", X"FF",
--X"FF", X"FF", X"FF", X"FF",
--X"FF", X"CE", X"FF", X"FF",
--X"FF", X"FF", X"FF", X"FF",
--X"FF", X"FF", X"FF", X"FF"
-- 50%
--X"10", X"0B", X"0C", X"0E", X"0C", X"0A", X"10", X"0E",
--X"0D", X"0E", X"12", X"11", X"10", X"13", X"18", X"28",
--X"1A", X"18", X"16", X"16", X"18", X"31", X"23", X"25",
--X"1D", X"28", X"3A", X"33", X"3D", X"3C", X"39", X"33",
--X"38", X"37", X"40", X"48", X"5C", X"4E", X"40", X"44",
--X"57", X"45", X"37", X"38", X"50", X"6D", X"51", X"57",
--X"5F", X"62", X"67", X"68", X"67", X"3E", X"4D", X"71",
--X"79", X"70", X"64", X"78", X"5C", X"65", X"67", X"63"
);
constant qrom_chr : ROMQ_TYPE :=
(
-- 50% for chrominance
X"11", X"12", X"12", X"18", X"15", X"18", X"2F", X"1A",
X"1A", X"2F", X"63", X"42", X"38", X"42", X"63", X"63",
X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63",
X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63",
X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63",
X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63",
X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63",
X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63"
-- 75% chrominance
--X"09", X"09", X"09", X"0C", X"0B", X"0C", X"18", X"0D",
--X"0D", X"18", X"32", X"21", X"1C", X"21", X"32", X"32",
--X"32", X"32", X"32", X"32", X"32", X"32", X"32", X"32",
--X"32", X"32", X"32", X"32", X"32", X"32", X"32", X"32",
--X"32", X"32", X"32", X"32", X"32", X"32", X"32", X"32",
--X"32", X"32", X"32", X"32", X"32", X"32", X"32", X"32",
--X"32", X"32", X"32", X"32", X"32", X"32", X"32", X"32",
--X"32", X"32", X"32", X"32", X"32", X"32", X"32", X"32"
--X"08", X"06", X"06", X"07", X"06", X"05", X"08", X"07", X"07", X"07", X"09", X"09", X"08", X"0A", X"0C", X"14",
--X"0D", X"0C", X"0B", X"0B", X"0C", X"19", X"12", X"13", X"0F", X"14", X"1D", X"1A", X"1F", X"1E", X"1D", X"1A",
--X"1C", X"1C", X"20", X"24", X"2E", X"27", X"20", X"22", X"2C", X"23", X"1C", X"1C", X"28", X"37", X"29", X"2C",
--X"30", X"31", X"34", X"34", X"34", X"1F", X"27", X"39", X"3D", X"38", X"32", X"3C", X"2E", X"33", X"34", X"32"
--others => X"01"
);
variable data_read : unsigned(31 downto 0);
variable data_write : unsigned(31 downto 0);
variable addr : unsigned(31 downto 0);
------------------------------------------------------------------------------
-- BEGIN
------------------------------------------------------------------------------
begin
sim_done <= '0';
iram_wren <= '0';
while RST /= '0' loop
wait until rising_edge(clk);
end loop;
for i in 0 to 100 loop
wait until rising_edge(clk);
end loop;
host_read(CLK, X"0000_0000", data_read,
OPB_ABus, OPB_BE, OPB_DBus_out, OPB_RNW, OPB_select, OPB_XferAck);
host_read(CLK, X"0000_0004", data_read,
OPB_ABus, OPB_BE, OPB_DBus_out, OPB_RNW, OPB_select, OPB_XferAck);
-- write luminance quantization table
for i in 0 to 64-1 loop
data_write := X"0000_00" & qrom_lum(i);
addr := X"0000_0100" + to_unsigned(4*i,32);
host_write(CLK, addr, data_write,
OPB_ABus, OPB_BE, OPB_DBus_in, OPB_RNW, OPB_select, OPB_XferAck);
end loop;
-- write chrominance quantization table
for i in 0 to 64-1 loop
data_write := X"0000_00" & qrom_chr(i);
addr := X"0000_0200" + to_unsigned(4*i,32);
host_write(CLK, addr, data_write,
OPB_ABus, OPB_BE, OPB_DBus_in, OPB_RNW, OPB_select, OPB_XferAck);
end loop;
data_write := to_unsigned(1,32) + shift_left(to_unsigned(3,32),1);
-- SOF & num_comps
host_write(CLK, X"0000_0000", data_write,
OPB_ABus, OPB_BE, OPB_DBus_in, OPB_RNW, OPB_select, OPB_XferAck);
-- write BUF_FIFO with bitmap
read_image;
-- wait until JPEG encoding is done
host_read(CLK, X"0000_000C", data_read,
OPB_ABus, OPB_BE, OPB_DBus_out, OPB_RNW, OPB_select, OPB_XferAck);
while data_read /= 2 loop
host_read(CLK, X"0000_000C", data_read,
OPB_ABus, OPB_BE, OPB_DBus_out, OPB_RNW, OPB_select, OPB_XferAck);
end loop;
sim_done <= '1';
wait;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- | lgpl-3.0 | ad996b53fa7707bdb1c3c499ace28329 | 0.422221 | 3.157905 | false | false | false | false |
ARC-Lab-UF/window_gen | src/window_gen_tb.vhd | 1 | 26,923 | -- Copyright (c) University of Florida
--
-- This file is part of window_gen.
--
-- window_gen is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- window_gen is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with window_gen. If not, see <http://www.gnu.org/licenses/>.
-- Eric Schwartz
-- Greg Stitt
-- University of Florida
-- Description: This entity provides a testbench for the window generator with
-- a variety of simulation parameters. See the generic descriptions below.
-- TODO: Add a worst-case timeout in case the done signal is never received.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_textio.all;
use work.math_custom.all;
use work.window_gen_pkg.all;
use work.tb_pkg.all;
-------------------------------------------------------------------------------
-- Generics Description
--
-- (WIDOW GENERATOR CONFIGRATION OPTIONS)
-- PARALLEL_IO : Specifies the number of inputs read at a time, in addition to
-- the number of windows generated in parallel. The number of
-- inputs and outputs has to be the same. It is not possible
-- to generate more outputs than the number of provided inputs.
-- If more inputs can be provided each cycle than the desired
-- number of parallel window outputs, use a FIFO to stall the
-- input stream.
-- MAX_WINDOW_ROWS : The maximum number of rows in a generated window
-- MAX_WINDOW_COLS : The maximum number of cols in a generated window
-- MAX_IMAGE_ROWS : The maximum number of rows in an input image/stream
-- MAX_IMAGE_COLS : The maximum number of cols in an input image/stream
-- DATA_WIDTH : The width in bits of each element of the input stream.
-- INPUT0_AT_MSB : Parallel inputs can be delivered with the first
-- input (INPUT0) at the MSB or the first input stored at
-- the LSB. e.g., for PARALLEL_IO = 4:
-- in0 & in1 & in2 & in3 (for INPUT0_AT_MSB = true)
-- or alternatively:
-- in3 & in2 & in1 & in0 (for INPUT0_AT_MSN = false)
-- If providing the input stream from a memory, it is likely
-- that INPUT0_AT_MSN is appropriate setting.
-- (default = false)
-- BLOCK_EXTRA_INPUT : boolean that specifies whether or not the buffer should
-- prevent extra inputs from being stored by deasserting
-- the ready signal after reading all inputs. This
-- options simplifies the processing of multiple images
-- (e.g. video) because there is an period of time between
-- when the last pixel of an image enters the generator
-- and when the generator is ready to accept a new image.
-- If false, the user has to track the number of pixels in
-- the input stream to ensure that pixels from the next
-- image are not sent to the generator until the generator
-- has asserted done.
-- If true, the window generator simplifies
-- external logic because it will deassert ready after
-- reading the entire image, which will inform the user
-- that the generator is not ready for the next image.
-- We recommend setting this value to true, which simplies
-- control at the cost of a small amount of logic and
-- a multiplier.
-- (default = true)
--
-- (ACTUAL INPUT SIZES)
-- IROWS : the actual number of image rows for the simulation
-- ICOLS : the actual number of image cols for the simulation
-- WROWS : the actual number of window rows for the simulation
-- WCOLS : the actual number of window cols for the simulation
--
-- (PARAMETERS FOR READ AND WRITE TIMINGS DURIGN SIMULATION)
-- DELAY_PROP_WRITE : The probability of a write data (i.e. inputs) not being
-- available when the generator is ready.
-- Valid range: 0.0 to 1.0.
-- MIN_RW_DELAY : When a write is delayed, this is the minimum number of cycles
-- for the delay.
-- MAX_RW_DELAY : When a write is delayed, this is the maximum number of cycles
-- for the delay.
-- DELAY_PROP_READ : The probability of a read being delay when output window
-- are available.
-- Valid range: 0.0 to 1.0.
-- MIN_RD_DELAY : When a read is delayed, this is the minimum number of cycles
-- for the delay.
-- MAX_RD_DELAY : When a read is delayed, this is the maximum number of cycles
-- for the delay.
--
-- (MISC SIMULATION PARAMETERS)
-- CLK_PERIOD : The clock period used for the generator
-- NUM_IMAGES : The number of images to test
-- CHANGE_DIMENSION : If true, this will randomly select different image
-- dimensions for each image.
--
-- (DEBUGGING AND PERFORMANCE ANALYSIS)
-- TEST_NAME : A string specifying the name of one instance of the testbench.
-- Useful when instantiating this test within a larger set of tests.
-- PRINT_STATUS : If true, enables reports during the simulation. Useful to
-- determine the current point of the simulation.
-- LOG_EN : It true, prints performance information to a log file.
-- LOG_FILE : The name of the log file. Ignored if LOG_EN = false.
-------------------------------------------------------------------------------
entity window_gen_tb is
generic(
-- window generator generics
PARALLEL_IO : positive := 3;
MAX_WINDOW_ROWS : positive := 5;
MAX_WINDOW_COLS : positive := 5;
MAX_IMAGE_ROWS : positive := 80;
MAX_IMAGE_COLS : positive := 80;
DATA_WIDTH : positive := 16;
INPUT0_AT_MSB : boolean := true;
BLOCK_EXTRA_INPUT : boolean := true;
-- Actual input sizes
IROWS : in positive := 20;
ICOLS : in positive := 20;
WROWS : in positive := 5;
WCOLS : in positive := 5;
-- parameters for read and writing timings in testbench
DELAY_PROB_WRITE : real := 0.1;
MIN_WR_DELAY : natural := 0;
MAX_WR_DELAY : natural := 10;
DELAY_PROB_READ : real := 0.1;
MIN_RD_DELAY : natural := 0;
MAX_RD_DELAY : natural := 10;
-- misc simulation parameters
CLK_PERIOD : time := 10 ns;
NUM_IMAGES : positive := 5;
CHANGE_DIMENSION : boolean := false;
-- debugging and performance analysis
TEST_NAME : string := "DEFAULT_TEST";
PRINT_STATUS : in boolean := false;
LOG_EN : in boolean := false;
LOG_FILE : in string := "sim_times.txt"
);
end window_gen_tb;
architecture TB of window_gen_tb is
type window_t is array(0 to MAX_WINDOW_ROWS-1, 0 to MAX_WINDOW_COLS-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
type window_array_t is array (0 to PARALLEL_IO-1) of window_t;
signal stop_clk : std_logic := '0';
signal sim_done : std_logic := '0';
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal go : std_logic := '0';
signal input_valid : std_logic := '0';
signal ready : std_logic;
signal read_enable : std_logic := '0';
signal empty : std_logic;
signal image_rows : std_logic_vector(bitsNeeded(MAX_IMAGE_ROWS)-1 downto 0) := (others => '0');
signal image_cols : std_logic_vector(bitsNeeded(MAX_IMAGE_COLS)-1 downto 0) := (others => '0');
signal window_rows : std_logic_vector(bitsNeeded(MAX_WINDOW_ROWS)-1 downto 0) := (others => '0');
signal window_cols : std_logic_vector(bitsNeeded(MAX_WINDOW_COLS)-1 downto 0) := (others => '0');
signal input : std_logic_vector(DATA_WIDTH*PARALLEL_IO-1 downto 0) := (others => '0');
signal output : std_logic_vector(MAX_WINDOW_ROWS*(MAX_WINDOW_COLS+PARALLEL_IO-1)*DATA_WIDTH-1 downto 0);
signal window_valid : std_logic_vector(PARALLEL_IO-1 downto 0);
signal done : std_logic;
signal in_count_s, count_s, write_count_s : std_logic_vector(DATA_WIDTH-1 downto 0);
signal windows_per_row : positive;
signal total_windows : positive;
signal images_completed_s : natural := 0;
signal active : std_logic := '0';
signal i_rows : positive;
signal i_cols : positive;
signal w_rows : positive;
signal w_cols : positive;
-- used for viewing output in simulation
signal window_array : window_array_t;
signal correct_array : window_array_t;
signal delay_read : std_logic := '0';
-----------------------------------------------------------------------
-- Procedure devectorizeWindow
-- Description: convert a 1D vectorized representation of an output window
-- into a corresponding 2D array for easier processing. Note
-- that this always determines a window of size
-- MAX_WINDOW_ROWS X MAX_WINDOW_COLS. For smaller windows,
-- just ignore the extra rows and columns.
--
-- Parameters:
-- vector : The 1D-vectorized version of the 2D array, stored in row-major
-- order. Index (0,0) starts at the MSB in the vector, with the
-- LSB storing the end of index (total_rows-1, total_cols-1)
-- window : the window as a 2D array (window_t)
-- index : In case multiple windows are specified in the output, index
-- specifies which one to get
--
-- Preconditions: index < PARALLEL_IO, vector must be the
-- appropriate size with data stored as described above.
-----------------------------------------------------------------------
procedure devectorizeWindow(signal vector : std_logic_vector;
window : out window_t;
index : natural) is
begin
for i in 0 to MAX_WINDOW_ROWS-1 loop
for j in index to MAX_WINDOW_COLS+index-1 loop
window(i, j-index) := getVectorElement(vector, i, j, MAX_WINDOW_ROWS, MAX_WINDOW_COLS+PARALLEL_IO-1, DATA_WIDTH);
-- window(i, j) <= (others => '0');
end loop;
end loop;
end devectorizeWindow;
-----------------------------------------------------------------------
-- Function getCorrectWindow
-- Description: This function generates the correct window based on the
-- specified output window count. The current implementation
-- assumes that the input uses sequential values starting at 0.
--
-- Parameters:
-- window_count : Specifies the output window (starting at 0)
-- image_cols : the number of columns in the image being tested
-- window_rows : the number of rows in the window being tested
-- window_cols : the number of columns in the window being tested
--
-- Preconditions: image_cols >= window_cols
-----------------------------------------------------------------------
function getCorrectWindow(window_count : natural;
signal image_cols : positive;
signal window_rows : positive;
signal window_cols : positive) return window_t is
variable window : window_t;
variable windows_per_row : integer;
variable start_row : integer;
variable start_col : integer;
begin
assert(image_cols >= window_cols);
windows_per_row := image_cols-window_cols+1;
start_row := window_count / windows_per_row;
start_col := window_count mod windows_per_row;
for i in start_row to start_row+window_rows-1 loop
for j in start_col to start_col+window_cols-1 loop
-- report "count=" & integer'image(window_count) & " i=" & integer'image(i) & " j=" & integer'image(j);
window(i-start_row, j-start_col) := std_logic_vector(to_unsigned(i*image_cols + j, DATA_WIDTH));
end loop;
end loop;
return window;
end getCorrectWindow;
-----------------------------------------------------------------------
-- Function areWindowsEqual
-- Description: Returns true if the specified windows are equal, false
-- otherwise
--
-- Parameters:
-- w1 : the first window to compare
-- w2 : the second window to compare
-- rows : the number of rows in the windows being compared
-- cols : the number of columns in the windows being compared
-----------------------------------------------------------------------
function areWindowsEqual(w1 : window_t;
w2 : window_t;
signal rows : positive;
signal cols : positive) return boolean is
begin
for i in 0 to rows-1 loop
for j in 0 to cols-1 loop
if (w1(i, j) /= w2(i, j)) then
-- report "ERROR: (" & integer'image(i) & "," & integer'image(j) & ") " & integer'image(to_integer(unsigned(w1(i,j)))) & " != " & integer'image(to_integer(unsigned(w2(i,j))));
return false;
end if;
end loop;
end loop;
return true;
end areWindowsEqual;
begin
UUT : entity work.window_gen
generic map(
PARALLEL_IO => PARALLEL_IO,
MAX_WINDOW_ROWS => MAX_WINDOW_ROWS,
MAX_WINDOW_COLS => MAX_WINDOW_COLS,
MAX_IMAGE_ROWS => MAX_IMAGE_ROWS,
MAX_IMAGE_COLS => MAX_IMAGE_COLS,
DATA_WIDTH => DATA_WIDTH,
INPUT0_AT_MSB => INPUT0_AT_MSB,
BLOCK_EXTRA_INPUT => BLOCK_EXTRA_INPUT
)
port map(
clk => clk,
rst => rst,
go => go,
ready => ready,
read_enable => read_enable,
empty => empty,
image_rows => image_rows,
image_cols => image_cols,
window_rows => window_rows,
window_cols => window_cols,
input => input,
input_valid => input_valid,
output => output,
window_valid => window_valid,
done => done
);
-- generate the clock until the simulation finishes
clk <= not clk after CLK_PERIOD/2 when (stop_clk = '0') else '0';
-- Send inputs to window buffer. All inputs are consecutive starting at 0
-- to make checking for correct outputs easier
process
variable in_count, write_count : integer;
variable packed_input : std_logic_vector(PARALLEL_IO*DATA_WIDTH-1 downto 0);
variable s1, s2, s3, s4 : positive; -- seed values
variable im_rows, im_cols : integer;
variable start_time, sim_time : time := 0 ns;
variable file_line : line;
variable line_var : line;
file text_file : text;
begin
if (LOG_EN) then
file_open(text_file, LOG_FILE, append_mode);
end if;
--Reset the entity
rst <= '1';
go <= '0';
active <= '0';
-- Loop through the process until NUM_IMAGES has been completed,
-- waiting for 'done' at the end of each iteration
while(images_completed_s < NUM_IMAGES) loop
i_rows <= IROWS;
i_cols <= ICOLS;
w_rows <= WROWS;
w_cols <= WCOLS;
-- Randomly change image dimensions if CHANGE_DIMENSION = true
if(images_completed_s > 0 and CHANGE_DIMENSION = true) then
randomInt(s3, s4, MAX_WINDOW_ROWS, MAX_IMAGE_ROWS, im_rows);
randomInt(s3, s4, MAX_WINDOW_COLS, MAX_IMAGE_COLS, im_cols);
i_rows <= im_rows;
i_cols <= im_cols;
end if;
-- determine when the generator should be done
wait until rising_edge(clk);
windows_per_row <= i_cols-w_cols+1;
wait until rising_edge(clk);
total_windows <= windows_per_row*(i_rows-w_rows+1);
-- specify the genertor input dimensiosn
image_rows <= std_logic_vector(to_unsigned(i_rows, image_rows'length));
image_cols <= std_logic_vector(to_unsigned(i_cols, image_cols'length));
window_rows <= std_logic_vector(to_unsigned(w_rows, window_rows'length));
window_cols <= std_logic_vector(to_unsigned(w_cols, window_cols'length));
for i in 0 to 5 loop
wait until rising_edge(clk);
end loop;
if (PRINT_STATUS) then
report "IMAGE IS PROCESSING: " & TEST_NAME & ": rows = " & integer'image(i_rows) & ", cols = " & integer'image(i_cols) & ".";
end if;
rst <= '0';
go <= '0';
wait until rising_edge(clk);
-- start the buffer with the specified inputs
go <= '1';
active <= '1';
start_time := now;
wait until rising_edge(clk);
in_count := 0;
write_count := 0;
while (in_count < i_rows*i_cols) loop
-- Randomize delay before sending the next input
input_valid <= '0';
randDelay(s1, s2, clk, DELAY_PROB_WRITE, MIN_WR_DELAY, MAX_WR_DELAY);
-- pack PARALLEL_IO inputs into a group based on the specified
-- input ordering
if (INPUT0_AT_MSB) then
for i in PARALLEL_IO-1 downto 0 loop
packed_input((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH) := std_logic_vector(to_unsigned(in_count, DATA_WIDTH));
in_count := in_count + 1;
in_count_s <= std_logic_vector(to_unsigned(in_count, in_count_s'length));
end loop;
else
for i in 0 to PARALLEL_IO-1 loop
packed_input((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH) := std_logic_vector(to_unsigned(in_count, DATA_WIDTH));
in_count := in_count + 1;
in_count_s <= std_logic_vector(to_unsigned(in_count, in_count_s'length));
end loop;
end if;
-- send input to generator
input <= packed_input;
input_valid <= '1';
write_count := write_count + 1;
write_count_s <= std_logic_vector(to_unsigned(write_count, write_count_s'length));
-- wait until the generator reads the input
wait until ready = '1' and rising_edge(clk);
-- Change the dimensions to make sure this doesn't affect
-- correctness during exection, the generator should only see
-- changes when go is first asserted.
randomInt(s3, s4, MAX_WINDOW_ROWS, MAX_IMAGE_ROWS, im_rows);
randomInt(s3, s4, MAX_WINDOW_COLS, MAX_IMAGE_COLS, im_cols);
image_rows <= std_logic_vector(to_unsigned(im_rows, image_rows'length));
image_cols <= std_logic_vector(to_unsigned(im_cols, image_cols'length));
end loop;
if (done = '0') then wait until done = '1'; end if;
active <= '0';
-- Allow time for the images_completed signal to update so that another iteration isnt wrongly performed
for i in 0 to 10 loop
wait until rising_edge(clk);
end loop;
end loop;
-- wait for entire simulation to complete
if (sim_done = '0') then wait until sim_done = '1'; end if;
-- write simulation info to log
sim_time := now - start_time;
if (LOG_EN) then
write(line_var, TEST_NAME);
write(line_var, string'(","));
write(line_var, integer'image(PARALLEL_IO));
write(line_var, string'(","));
write(line_var, integer'image(MAX_WINDOW_ROWS));
write(line_var, string'(","));
write(line_var, integer'image(MAX_WINDOW_COLS));
write(line_var, string'(","));
write(line_var, integer'image(MAX_IMAGE_ROWS));
write(line_var, string'(","));
write(line_var, integer'image(MAX_IMAGE_COLS));
write(line_var, string'(","));
write(line_var, DATA_WIDTH);
write(line_var, string'(","));
write(line_var, integer'image(i_rows));
write(line_var, string'(","));
write(line_var, integer'image(i_cols));
write(line_var, string'(","));
write(line_var, integer'image(w_rows));
write(line_var, string'(","));
write(line_var, integer'image(w_cols));
write(line_var, string'(","));
write(line_var, DELAY_PROB_WRITE);
write(line_var, string'(","));
write(line_var, DELAY_PROB_READ);
write(line_var, string'(","));
write(line_var, sim_time);
writeline(text_file, line_var);
file_close(text_file);
end if;
stop_clk <= '1';
report "SIMULATION DONE!!!!";
wait;
end process;
-- Randomize a read delay to test buffer filling up and having to stall
process
variable s1, s2 : positive;
variable should_delay : boolean;
begin
delay_read <= '1';
randDelay(s1, s2, clk, DELAY_PROB_READ, MIN_RD_DELAY, MAX_RD_DELAY);
delay_read <= '0';
wait until rising_edge(clk);
end process;
-- reads any time the buffer isn't empty and not being delayed.
read_enable <= not empty and not delay_read and active;
-- check if the outputs are correct
process
variable actual_window : window_t;
variable correct_window : window_t;
variable output_count : natural := 0;
variable s1, s2 : positive;
variable images_completed : natural := 0;
begin
-- if read_enable is asserted on a rising clock edge the current
-- window that is being output from the generator should be correct.
-- Note that the output changes immediately after the rising clock
-- edge, so we can't have any wait statements before the check.
wait until rising_edge(clk);
if (read_enable = '1') then
-- check all PARALLEL_IO windows
for i in 0 to PARALLEL_IO-1 loop
-- if the window is valid, check it, otherwise ignore it
if (window_valid(PARALLEL_IO-i-1) = '1') then
-- get 2D array version of window
devectorizeWindow(output, actual_window, i);
-- enable output to be seen in simulation
window_array(i) <= actual_window;
-- get correct window based on output_count
correct_window := getCorrectWindow(output_count, i_cols, w_rows, w_cols);
-- enable correct window to be seen in simulation
correct_array(i) <= correct_window;
-- check if the window is correct
if (areWindowsEqual(actual_window, correct_window, w_rows, w_cols) = false) then
report "ERROR: Window " & integer'image(i) & " is incorrect." severity failure;
end if;
output_count := output_count + 1;
count_s <= std_logic_vector(to_unsigned(output_count, count_s'length));
end if;
end loop;
end if;
-- check for correct done status
if (output_count = total_windows) then
wait until rising_edge(clk);
images_completed := images_completed+1;
assert(done = '1') report "ERROR: Done not asserted upon completion - " & TEST_NAME & ": rows = " & integer'image(i_rows) & ", cols = " & integer'image(i_cols) & "." severity failure;
output_count := 0;
if (PRINT_STATUS) then
report "IMAGE PROCESSED SUCCESSFULLY: " & TEST_NAME & ": rows = " & integer'image(i_rows) & ", cols = " & integer'image(i_cols) & ".";
end if;
if(images_completed = NUM_IMAGES) then
sim_done <= '1';
end if;
else
if (active = '1') then
assert(done = '0') report "ERROR: Done asserted before completion - " & TEST_NAME & ": " & integer'image(i_rows) & ", cols = " & integer'image(i_cols) & "." severity failure;
end if;
end if;
images_completed_s <= images_completed;
end process;
-- check to make sure that lower window_valid bits are never asserted when
-- higher bits aren't asserted.
process
begin
while(sim_done = '0') loop
for i in 0 to PARALLEL_IO-2 loop
if(window_valid(i) = '1' and window_valid(i+1) = '0') then
report "ERROR - lower_window valid bits are '1' when upper bits are '0'!" severity failure;
end if;
wait until rising_edge(clk);
end loop;
end loop;
wait;
end process;
end TB;
| gpl-3.0 | 2049e702ad9bd0350920ff425e78ef11 | 0.535787 | 4.24787 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/lib/src/cntRtl.vhd | 3 | 3,851 | -------------------------------------------------------------------------------
--! @file cntRtl.vhd
--
--! @brief Terminal Counter
--
--! @details The terminal counter is a synchronous counter configured
--! by several generics.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity cnt is
generic (
--! Width of counter
gCntWidth : natural := 32;
--! Value that triggers the counter reset
gTcntVal : natural := 1000
);
port (
iArst : in std_logic;
iClk : in std_logic;
iEnable : in std_logic;
iSrst : in std_logic;
oCnt : out std_logic_vector(gCntWidth-1 downto 0);
oTcnt : out std_logic
);
end entity;
architecture rtl of cnt is
constant cTcntVal : std_logic_vector(gCntWidth-1 downto 0) :=
std_logic_vector(to_unsigned(gTcntVal, gCntWidth));
signal cnt, cnt_next : std_logic_vector(gCntWidth-1 downto 0);
signal tc : std_logic;
begin
-- handle wrong generics
assert (gTcntVal > 0)
report "Terminal count value of 0 makes no sense!"
severity failure;
regClk : process(iArst, iClk)
begin
if iArst = cActivated then
cnt <= (others => cInactivated);
elsif rising_edge(iClk) then
cnt <= cnt_next;
end if;
end process;
tc <= cActivated when cnt = cTcntVal else
cInactivated;
oCnt <= cnt;
oTcnt <= tc;
comb : process(iSrst, iEnable, cnt, tc)
begin
--default
cnt_next <= cnt;
if iSrst = cActivated then
cnt_next <= (others => cInactivated);
elsif iEnable = cActivated then
if tc = cActivated then
cnt_next <= (others => cInactivated);
else
cnt_next <= std_logic_vector(unsigned(cnt) + 1);
end if;
end if;
end process;
end architecture;
| gpl-2.0 | ec70f37e55e4568da3c898c4d60ef2e4 | 0.61075 | 4.514654 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | staging/fpga/boards/altera/SYSTEC_ECUcore-EP3C/design_nios2_directIO/niosII_openMac_burst_0.vhd | 4 | 41,369 | --Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
--synthesis translate_off
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity niosII_openMac_burst_0_fifo_module_fifo_ram_module is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal rdaddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal rdclken : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal wraddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal wrclock : IN STD_LOGIC;
signal wren : IN STD_LOGIC;
-- outputs:
signal q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end entity niosII_openMac_burst_0_fifo_module_fifo_ram_module;
architecture europa of niosII_openMac_burst_0_fifo_module_fifo_ram_module is
signal internal_q : STD_LOGIC_VECTOR (31 DOWNTO 0);
TYPE mem_array is ARRAY( 3 DOWNTO 0) of STD_LOGIC_VECTOR(31 DOWNTO 0);
signal read_address : STD_LOGIC_VECTOR (1 DOWNTO 0);
begin
process (wrclock, clk) -- MG
VARIABLE rd_address_internal : STD_LOGIC_VECTOR (1 DOWNTO 0) := (others => '0');
VARIABLE wr_address_internal : STD_LOGIC_VECTOR (1 DOWNTO 0) := (others => '0');
variable Marc_Gaucherons_Memory_Variable : mem_array; -- MG
begin
-- Write data
if wrclock'event and wrclock = '1' then
wr_address_internal := wraddress;
if wren = '1' then
Marc_Gaucherons_Memory_Variable(CONV_INTEGER(UNSIGNED(wr_address_internal))) := data;
end if;
end if;
-- read data
q <= Marc_Gaucherons_Memory_Variable(CONV_INTEGER(UNSIGNED(rd_address_internal)));
IF clk'event AND clk = '1' AND rdclken = '1' THEN
rd_address_internal := rdaddress;
END IF;
end process;
end europa;
--synthesis translate_on
--synthesis read_comments_as_HDL on
--library altera;
--use altera.altera_europa_support_lib.all;
--
--library ieee;
--use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
--
--entity niosII_openMac_burst_0_fifo_module_fifo_ram_module is
-- port (
--
-- signal clk : IN STD_LOGIC;
-- signal data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- signal rdaddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-- signal rdclken : IN STD_LOGIC;
-- signal reset_n : IN STD_LOGIC;
-- signal wraddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-- signal wrclock : IN STD_LOGIC;
-- signal wren : IN STD_LOGIC;
--
--
-- signal q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
-- );
--end entity niosII_openMac_burst_0_fifo_module_fifo_ram_module;
--
--
--architecture europa of niosII_openMac_burst_0_fifo_module_fifo_ram_module is
-- component lpm_ram_dp is
--GENERIC (
-- lpm_file : STRING;
-- lpm_hint : STRING;
-- lpm_indata : STRING;
-- lpm_outdata : STRING;
-- lpm_rdaddress_control : STRING;
-- lpm_width : NATURAL;
-- lpm_widthad : NATURAL;
-- lpm_wraddress_control : STRING;
-- suppress_memory_conversion_warnings : STRING
-- );
-- PORT (
-- signal q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
-- signal rdaddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-- signal wren : IN STD_LOGIC;
-- signal rdclock : IN STD_LOGIC;
-- signal wrclock : IN STD_LOGIC;
-- signal wraddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-- signal data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- signal rdclken : IN STD_LOGIC
-- );
-- end component lpm_ram_dp;
-- signal internal_q : STD_LOGIC_VECTOR (31 DOWNTO 0);
-- TYPE mem_array is ARRAY( 3 DOWNTO 0) of STD_LOGIC_VECTOR(31 DOWNTO 0);
-- signal read_address : STD_LOGIC_VECTOR (1 DOWNTO 0);
--
--begin
--
-- process (rdaddress)
-- begin
-- read_address <= rdaddress;
--
-- end process;
--
-- lpm_ram_dp_component : lpm_ram_dp
-- generic map(
-- lpm_file => "UNUSED",
-- lpm_hint => "USE_EAB=OFF",
-- lpm_indata => "REGISTERED",
-- lpm_outdata => "UNREGISTERED",
-- lpm_rdaddress_control => "REGISTERED",
-- lpm_width => 32,
-- lpm_widthad => 2,
-- lpm_wraddress_control => "REGISTERED",
-- suppress_memory_conversion_warnings => "ON"
-- )
-- port map(
-- data => data,
-- q => internal_q,
-- rdaddress => read_address,
-- rdclken => rdclken,
-- rdclock => clk,
-- wraddress => wraddress,
-- wrclock => wrclock,
-- wren => wren
-- );
--
--
-- q <= internal_q;
--end europa;
--
--synthesis read_comments_as_HDL off
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity niosII_openMac_burst_0_fifo_module is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal clk_en : IN STD_LOGIC;
signal fifo_read : IN STD_LOGIC;
signal fifo_wr_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_write : IN STD_LOGIC;
signal flush_fifo : IN STD_LOGIC;
signal inc_pending_data : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal fifo_datavalid : OUT STD_LOGIC;
signal fifo_empty : OUT STD_LOGIC;
signal fifo_full : OUT STD_LOGIC;
signal fifo_rd_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal p1_fifo_empty : OUT STD_LOGIC
);
end entity niosII_openMac_burst_0_fifo_module;
architecture europa of niosII_openMac_burst_0_fifo_module is
component niosII_openMac_burst_0_fifo_module_fifo_ram_module is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal rdaddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal rdclken : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal wraddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal wrclock : IN STD_LOGIC;
signal wren : IN STD_LOGIC;
-- outputs:
signal q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component niosII_openMac_burst_0_fifo_module_fifo_ram_module;
signal estimated_rdaddress : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal estimated_wraddress : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal fifo_dec : STD_LOGIC;
signal fifo_inc : STD_LOGIC;
signal fifo_ram_q : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal internal_fifo_empty : STD_LOGIC;
signal internal_fifo_full : STD_LOGIC;
signal internal_p1_fifo_empty : STD_LOGIC;
signal last_write_collision : STD_LOGIC;
signal last_write_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal module_input : STD_LOGIC;
signal p1_estimated_wraddress : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal p1_fifo_full : STD_LOGIC;
signal p1_wraddress : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal rdaddress : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal rdaddress_reg : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal wraddress : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal write_collision : STD_LOGIC;
begin
p1_wraddress <= A_EXT (A_WE_StdLogicVector((std_logic'((fifo_write)) = '1'), ((std_logic_vector'("0000000000000000000000000000000") & (wraddress)) - std_logic_vector'("000000000000000000000000000000001")), (std_logic_vector'("0000000000000000000000000000000") & (wraddress))), 2);
process (clk, reset_n)
begin
if reset_n = '0' then
wraddress <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
if std_logic'(clk_en) = '1' then
if std_logic'(flush_fifo) = '1' then
wraddress <= std_logic_vector'("00");
else
wraddress <= p1_wraddress;
end if;
end if;
end if;
end process;
rdaddress <= A_EXT (A_WE_StdLogicVector((std_logic'(flush_fifo) = '1'), std_logic_vector'("000000000000000000000000000000000"), A_WE_StdLogicVector((std_logic'(fifo_read) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (rdaddress_reg)) - std_logic_vector'("000000000000000000000000000000001"))), (std_logic_vector'("0000000000000000000000000000000") & (rdaddress_reg)))), 2);
process (clk, reset_n)
begin
if reset_n = '0' then
rdaddress_reg <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
rdaddress_reg <= rdaddress;
end if;
end process;
fifo_datavalid <= NOT internal_fifo_empty;
fifo_inc <= fifo_write AND NOT fifo_read;
fifo_dec <= fifo_read AND NOT fifo_write;
estimated_rdaddress <= A_EXT (((std_logic_vector'("0000000000000000000000000000000") & (rdaddress_reg)) - std_logic_vector'("000000000000000000000000000000001")), 2);
p1_estimated_wraddress <= A_EXT (A_WE_StdLogicVector((std_logic'((inc_pending_data)) = '1'), ((std_logic_vector'("0000000000000000000000000000000") & (estimated_wraddress)) - std_logic_vector'("000000000000000000000000000000001")), (std_logic_vector'("0000000000000000000000000000000") & (estimated_wraddress))), 2);
process (clk, reset_n)
begin
if reset_n = '0' then
estimated_wraddress <= A_REP(std_logic'('1'), 2);
elsif clk'event and clk = '1' then
if std_logic'(clk_en) = '1' then
if std_logic'(flush_fifo) = '1' then
estimated_wraddress <= A_REP(std_logic'('1'), 2);
else
estimated_wraddress <= p1_estimated_wraddress;
end if;
end if;
end if;
end process;
internal_p1_fifo_empty <= flush_fifo OR ((((NOT fifo_inc AND internal_fifo_empty)) OR ((fifo_dec AND to_std_logic(((wraddress = estimated_rdaddress)))))));
process (clk, reset_n)
begin
if reset_n = '0' then
internal_fifo_empty <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'(clk_en) = '1' then
internal_fifo_empty <= internal_p1_fifo_empty;
end if;
end if;
end process;
p1_fifo_full <= NOT flush_fifo AND ((((NOT fifo_dec AND internal_fifo_full)) OR ((inc_pending_data AND to_std_logic(((estimated_wraddress = rdaddress)))))));
process (clk, reset_n)
begin
if reset_n = '0' then
internal_fifo_full <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(clk_en) = '1' then
internal_fifo_full <= p1_fifo_full;
end if;
end if;
end process;
write_collision <= fifo_write AND to_std_logic(((wraddress = rdaddress)));
process (clk, reset_n)
begin
if reset_n = '0' then
last_write_data <= std_logic_vector'("00000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(write_collision) = '1' then
last_write_data <= fifo_wr_data;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
last_write_collision <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(write_collision) = '1' then
last_write_collision <= Vector_To_Std_Logic(-SIGNED(std_logic_vector'("00000000000000000000000000000001")));
elsif std_logic'(fifo_read) = '1' then
last_write_collision <= std_logic'('0');
end if;
end if;
end process;
fifo_rd_data <= A_WE_StdLogicVector((std_logic'(last_write_collision) = '1'), last_write_data, fifo_ram_q);
--niosII_openMac_burst_0_fifo_module_fifo_ram, which is an e_ram
niosII_openMac_burst_0_fifo_module_fifo_ram : niosII_openMac_burst_0_fifo_module_fifo_ram_module
port map(
q => fifo_ram_q,
clk => clk,
data => fifo_wr_data,
rdaddress => rdaddress,
rdclken => module_input,
reset_n => reset_n,
wraddress => wraddress,
wrclock => clk,
wren => fifo_write
);
module_input <= std_logic'('1');
--vhdl renameroo for output signals
fifo_empty <= internal_fifo_empty;
--vhdl renameroo for output signals
fifo_full <= internal_fifo_full;
--vhdl renameroo for output signals
p1_fifo_empty <= internal_p1_fifo_empty;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
--
--Burst adapter parameters:
--adapter is mastered by: powerlink_0/MAC_DMA
--adapter masters: SRAM_0/avalon_tristate_slave
--asp_debug: 0
--byteaddr_width: 23
--ceil_data_width: 32
--data_width: 32
--dbs_shift: -1
--dbs_upstream_burstcount_width: 3
--downstream_addr_shift: 2
--downstream_burstcount_width: 1
--downstream_max_burstcount: 1
--downstream_pipeline: 0
--dynamic_slave: 1
--master_always_burst_max_burst: 0
--master_burst_on_burst_boundaries_only: 0
--master_data_width: 16
--master_interleave: 0
--master_linewrap_bursts: 0
--nativeaddr_width: 21
--slave_always_burst_max_burst: 0
--slave_burst_on_burst_boundaries_only: 0
--slave_interleave: 0
--slave_linewrap_bursts: 0
--upstream_burstcount: upstream_burstcount
--upstream_burstcount_width: 3
--upstream_max_burstcount: 4
--zero_address_width: 0
entity niosII_openMac_burst_0 is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal downstream_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal downstream_readdatavalid : IN STD_LOGIC;
signal downstream_waitrequest : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal upstream_address : IN STD_LOGIC_VECTOR (22 DOWNTO 0);
signal upstream_burstcount : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal upstream_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal upstream_debugaccess : IN STD_LOGIC;
signal upstream_nativeaddress : IN STD_LOGIC_VECTOR (20 DOWNTO 0);
signal upstream_read : IN STD_LOGIC;
signal upstream_write : IN STD_LOGIC;
signal upstream_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- outputs:
signal downstream_address : OUT STD_LOGIC_VECTOR (20 DOWNTO 0);
signal downstream_arbitrationshare : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
signal downstream_burstcount : OUT STD_LOGIC;
signal downstream_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal downstream_debugaccess : OUT STD_LOGIC;
signal downstream_nativeaddress : OUT STD_LOGIC_VECTOR (20 DOWNTO 0);
signal downstream_read : OUT STD_LOGIC;
signal downstream_write : OUT STD_LOGIC;
signal downstream_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal upstream_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal upstream_readdatavalid : OUT STD_LOGIC;
signal upstream_waitrequest : OUT STD_LOGIC
);
end entity niosII_openMac_burst_0;
architecture europa of niosII_openMac_burst_0 is
component niosII_openMac_burst_0_fifo_module is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal clk_en : IN STD_LOGIC;
signal fifo_read : IN STD_LOGIC;
signal fifo_wr_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_write : IN STD_LOGIC;
signal flush_fifo : IN STD_LOGIC;
signal inc_pending_data : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal fifo_datavalid : OUT STD_LOGIC;
signal fifo_empty : OUT STD_LOGIC;
signal fifo_full : OUT STD_LOGIC;
signal fifo_rd_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal p1_fifo_empty : OUT STD_LOGIC
);
end component niosII_openMac_burst_0_fifo_module;
signal address_offset : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal atomic_counter : STD_LOGIC;
signal current_upstream_address : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal current_upstream_burstcount : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal current_upstream_read : STD_LOGIC;
signal current_upstream_write : STD_LOGIC;
signal data_counter : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal dbs_adjusted_upstream_burstcount : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal downstream_address_base : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal downstream_burstdone : STD_LOGIC;
signal enable_state_change : STD_LOGIC;
signal fifo_datavalid : STD_LOGIC;
signal fifo_empty : STD_LOGIC;
signal fifo_full : STD_LOGIC;
signal fifo_rd_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_read : STD_LOGIC;
signal fifo_wr_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_write : STD_LOGIC;
signal flush_fifo : STD_LOGIC;
signal full_width_rdv_counter : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal internal_downstream_burstcount : STD_LOGIC;
signal internal_downstream_byteenable : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal internal_downstream_read : STD_LOGIC;
signal internal_downstream_write : STD_LOGIC;
signal internal_upstream_readdatavalid : STD_LOGIC;
signal internal_upstream_waitrequest : STD_LOGIC;
signal max_burst_size : STD_LOGIC;
signal module_input1 : STD_LOGIC;
signal negative_dbs_rdv_counter : STD_LOGIC;
signal negative_dbs_read_expression : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal p1_atomic_counter : STD_LOGIC;
signal p1_fifo_empty : STD_LOGIC;
signal p1_state_busy : STD_LOGIC;
signal p1_state_idle : STD_LOGIC;
signal pending_register_enable : STD_LOGIC;
signal pending_upstream_read : STD_LOGIC;
signal pending_upstream_read_reg : STD_LOGIC;
signal pending_upstream_write : STD_LOGIC;
signal pending_upstream_write_reg : STD_LOGIC;
signal quantized_burst_base : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal quantized_burst_limit : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal read_address_offset : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal read_update_count : STD_LOGIC;
signal read_write_dbs_adjusted_upstream_burstcount : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal registered_read_write_dbs_adjusted_upstream_burstcount : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal registered_upstream_address : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal registered_upstream_burstcount : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal registered_upstream_nativeaddress : STD_LOGIC_VECTOR (20 DOWNTO 0);
signal registered_upstream_read : STD_LOGIC;
signal registered_upstream_write : STD_LOGIC;
signal state_busy : STD_LOGIC;
signal state_idle : STD_LOGIC;
signal sync_nativeaddress : STD_LOGIC;
signal transactions_remaining : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal transactions_remaining_reg : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal update_count : STD_LOGIC;
signal upstream_burstdone : STD_LOGIC;
signal upstream_read_run : STD_LOGIC;
signal upstream_write_run : STD_LOGIC;
signal write_address_offset : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal write_update_count : STD_LOGIC;
begin
sync_nativeaddress <= or_reduce(upstream_nativeaddress);
--downstream, which is an e_avalon_master
--upstream, which is an e_avalon_slave
upstream_burstdone <= A_WE_StdLogic((std_logic'(current_upstream_read) = '1'), ((to_std_logic(((transactions_remaining = (std_logic_vector'("00") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount)))))) AND internal_downstream_read) AND NOT downstream_waitrequest), ((to_std_logic((((std_logic_vector'("000000000000000000000000000000") & (transactions_remaining)) = (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(atomic_counter))) + std_logic_vector'("000000000000000000000000000000001")))))) AND internal_downstream_write) AND NOT downstream_waitrequest));
p1_atomic_counter <= Vector_To_Std_Logic(((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(atomic_counter))) + (std_logic_vector'("0") & ((A_WE_StdLogicVector((std_logic'(internal_downstream_read) = '1'), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount))), std_logic_vector'("00000000000000000000000000000001")))))));
downstream_burstdone <= (((internal_downstream_read OR internal_downstream_write)) AND NOT downstream_waitrequest) AND to_std_logic(((std_logic'(p1_atomic_counter) = std_logic'(internal_downstream_burstcount))));
quantized_burst_base <= A_EXT (((std_logic_vector'("000000000") & (upstream_address)) AND NOT std_logic_vector'("00000000000000000000000000000011")), 23);
quantized_burst_limit <= A_EXT (((std_logic_vector'("0") & ((((((std_logic_vector'("0") & (((std_logic_vector'("0") & ((((std_logic_vector'("000000000") & (upstream_address)) AND NOT std_logic_vector'("00000000000000000000000000000001"))))) + (std_logic_vector'("00000000000000000000000000000") & ((upstream_burstcount & A_ToStdLogicVector(std_logic'('0')))))))) - std_logic_vector'("0000000000000000000000000000000001"))) OR std_logic_vector'("0000000000000000000000000000000011"))))) + std_logic_vector'("00000000000000000000000000000000001")), 23);
negative_dbs_read_expression <= A_EXT (A_SRL((((std_logic_vector'("0") & (quantized_burst_limit)) - (std_logic_vector'("0") & (quantized_burst_base)))),std_logic_vector'("00000000000000000000000000000010")), 3);
dbs_adjusted_upstream_burstcount <= A_WE_StdLogicVector((std_logic'(pending_register_enable) = '1'), read_write_dbs_adjusted_upstream_burstcount, registered_read_write_dbs_adjusted_upstream_burstcount);
read_write_dbs_adjusted_upstream_burstcount <= A_WE_StdLogicVector((std_logic'(upstream_read) = '1'), negative_dbs_read_expression, upstream_burstcount);
process (clk, reset_n)
begin
if reset_n = '0' then
registered_read_write_dbs_adjusted_upstream_burstcount <= std_logic_vector'("000");
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_read_write_dbs_adjusted_upstream_burstcount <= read_write_dbs_adjusted_upstream_burstcount;
end if;
end if;
end process;
p1_state_idle <= ((state_idle AND NOT upstream_read) AND NOT upstream_write) OR ((((state_busy AND to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (data_counter)) = std_logic_vector'("00000000000000000000000000000000"))))) AND p1_fifo_empty) AND NOT pending_upstream_read) AND NOT pending_upstream_write);
p1_state_busy <= (state_idle AND ((upstream_read OR upstream_write))) OR (state_busy AND ((((to_std_logic(NOT (((std_logic_vector'("00000000000000000000000000000") & (data_counter)) = std_logic_vector'("00000000000000000000000000000000")))) OR NOT p1_fifo_empty) OR pending_upstream_read) OR pending_upstream_write)));
enable_state_change <= NOT ((internal_downstream_read OR internal_downstream_write)) OR NOT downstream_waitrequest;
process (clk, reset_n)
begin
if reset_n = '0' then
pending_upstream_read_reg <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((upstream_read AND state_idle)) = '1' then
pending_upstream_read_reg <= Vector_To_Std_Logic(-SIGNED(std_logic_vector'("00000000000000000000000000000001")));
elsif std_logic'(downstream_readdatavalid) = '1' then
pending_upstream_read_reg <= std_logic'('0');
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
pending_upstream_write_reg <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(upstream_burstdone) = '1' then
pending_upstream_write_reg <= std_logic'('0');
elsif std_logic'((upstream_write AND ((state_idle OR NOT internal_upstream_waitrequest)))) = '1' then
pending_upstream_write_reg <= Vector_To_Std_Logic(-SIGNED(std_logic_vector'("00000000000000000000000000000001")));
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
state_idle <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'(enable_state_change) = '1' then
state_idle <= p1_state_idle;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
state_busy <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(enable_state_change) = '1' then
state_busy <= p1_state_busy;
end if;
end if;
end process;
pending_upstream_read <= pending_upstream_read_reg;
pending_upstream_write <= pending_upstream_write_reg AND NOT upstream_burstdone;
pending_register_enable <= state_idle OR ((((upstream_read OR upstream_write)) AND NOT internal_upstream_waitrequest));
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_read <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_read <= upstream_read;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_write <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_write <= upstream_write;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_burstcount <= std_logic_vector'("000");
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_burstcount <= upstream_burstcount;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_address <= std_logic_vector'("00000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_address <= upstream_address;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_nativeaddress <= std_logic_vector'("000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_nativeaddress <= upstream_nativeaddress;
end if;
end if;
end process;
current_upstream_read <= registered_upstream_read AND NOT(internal_downstream_write);
current_upstream_write <= registered_upstream_write;
current_upstream_address <= registered_upstream_address;
current_upstream_burstcount <= A_WE_StdLogicVector((std_logic'(pending_register_enable) = '1'), upstream_burstcount, registered_upstream_burstcount);
process (clk, reset_n)
begin
if reset_n = '0' then
atomic_counter <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((internal_downstream_read OR internal_downstream_write)) AND NOT downstream_waitrequest)) = '1' then
atomic_counter <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(downstream_burstdone) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(p1_atomic_counter)))));
end if;
end if;
end process;
read_update_count <= current_upstream_read AND NOT downstream_waitrequest;
write_update_count <= (current_upstream_write AND internal_downstream_write) AND downstream_burstdone;
update_count <= read_update_count OR write_update_count;
transactions_remaining <= A_WE_StdLogicVector((std_logic'(((state_idle AND ((upstream_read OR upstream_write))))) = '1'), dbs_adjusted_upstream_burstcount, transactions_remaining_reg);
process (clk, reset_n)
begin
if reset_n = '0' then
transactions_remaining_reg <= std_logic_vector'("000");
elsif clk'event and clk = '1' then
transactions_remaining_reg <= A_EXT (A_WE_StdLogicVector((std_logic'(((state_idle AND ((upstream_read OR upstream_write))))) = '1'), (std_logic_vector'("0") & (dbs_adjusted_upstream_burstcount)), A_WE_StdLogicVector((std_logic'(update_count) = '1'), ((std_logic_vector'("0") & (transactions_remaining_reg)) - (std_logic_vector'("000") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount)))), (std_logic_vector'("0") & (transactions_remaining_reg)))), 3);
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
data_counter <= std_logic_vector'("000");
elsif clk'event and clk = '1' then
data_counter <= A_EXT (A_WE_StdLogicVector((std_logic'(((state_idle AND upstream_read) AND NOT internal_upstream_waitrequest)) = '1'), (std_logic_vector'("000000000000000000000000000000") & (dbs_adjusted_upstream_burstcount)), A_WE_StdLogicVector((std_logic'(downstream_readdatavalid) = '1'), ((std_logic_vector'("000000000000000000000000000000") & (data_counter)) - std_logic_vector'("000000000000000000000000000000001")), (std_logic_vector'("000000000000000000000000000000") & (data_counter)))), 3);
end if;
end process;
max_burst_size <= std_logic'('1');
internal_downstream_burstcount <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(current_upstream_read) = '1'), (std_logic_vector'("00000000000000000000000000000") & ((A_WE_StdLogicVector(((transactions_remaining>(std_logic_vector'("00") & (A_TOSTDLOGICVECTOR(max_burst_size))))), (std_logic_vector'("00") & (A_TOSTDLOGICVECTOR(max_burst_size))), transactions_remaining)))), std_logic_vector'("00000000000000000000000000000001")));
downstream_arbitrationshare <= A_WE_StdLogicVector((std_logic'(current_upstream_read) = '1'), (dbs_adjusted_upstream_burstcount), dbs_adjusted_upstream_burstcount);
process (clk, reset_n)
begin
if reset_n = '0' then
write_address_offset <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
write_address_offset <= A_EXT (A_WE_StdLogicVector((std_logic'((state_idle AND upstream_write)) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("00000000000000000000000000000") & (A_WE_StdLogicVector((std_logic'(((((internal_downstream_write AND NOT downstream_waitrequest) AND downstream_burstdone) AND or_reduce(internal_downstream_byteenable(3 DOWNTO 2))))) = '1'), ((std_logic_vector'("0") & (write_address_offset)) + (std_logic_vector'("00") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount)))), (std_logic_vector'("0") & (write_address_offset)))))), 2);
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
read_address_offset <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
read_address_offset <= A_EXT (A_WE_StdLogicVector((std_logic'((state_idle AND upstream_read)) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("00000000000000000000000000000") & (A_WE_StdLogicVector((std_logic'(((internal_downstream_read AND NOT downstream_waitrequest))) = '1'), ((std_logic_vector'("0") & (read_address_offset)) + (std_logic_vector'("00") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount)))), (std_logic_vector'("0") & (read_address_offset)))))), 2);
end if;
end process;
downstream_nativeaddress <= A_SRL(registered_upstream_nativeaddress,std_logic_vector'("00000000000000000000000000000001"));
address_offset <= A_WE_StdLogicVector((std_logic'(current_upstream_read) = '1'), read_address_offset, write_address_offset);
downstream_address_base <= current_upstream_address;
downstream_address <= A_EXT (((std_logic_vector'("0") & (downstream_address_base)) + (std_logic_vector'("00000000000000000000") & ((address_offset & std_logic_vector'("00"))))), 21);
process (clk, reset_n)
begin
if reset_n = '0' then
internal_downstream_read <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((NOT internal_downstream_read OR NOT downstream_waitrequest)) = '1' then
internal_downstream_read <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'((state_idle AND upstream_read)) = '1'), std_logic_vector'("00000000000000000000000000000001"), A_WE_StdLogicVector(((transactions_remaining = (std_logic_vector'("00") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount))))), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(internal_downstream_read))))));
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
negative_dbs_rdv_counter <= std_logic'('0');
elsif clk'event and clk = '1' then
negative_dbs_rdv_counter <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'((((state_idle AND upstream_read) AND NOT internal_upstream_waitrequest))) = '1'), (std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(upstream_address(1)))), A_WE_StdLogicVector((std_logic'(fifo_datavalid) = '1'), ((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(negative_dbs_rdv_counter))) + std_logic_vector'("000000000000000000000000000000001")), (std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(negative_dbs_rdv_counter))))));
end if;
end process;
fifo_read <= NOT fifo_empty AND to_std_logic((((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(negative_dbs_rdv_counter))) = std_logic_vector'("00000000000000000000000000000001"))) OR (((((std_logic_vector'("000000000000000000000000000000") & (full_width_rdv_counter)) + std_logic_vector'("000000000000000000000000000000001"))) = (std_logic_vector'("000000000000000000000000000000") & (current_upstream_burstcount)))))));
fifo_write <= downstream_readdatavalid;
fifo_wr_data <= downstream_readdata;
flush_fifo <= std_logic'('0');
--the_niosII_openMac_burst_0_fifo_module, which is an e_instance
the_niosII_openMac_burst_0_fifo_module : niosII_openMac_burst_0_fifo_module
port map(
fifo_datavalid => fifo_datavalid,
fifo_empty => fifo_empty,
fifo_full => fifo_full,
fifo_rd_data => fifo_rd_data,
p1_fifo_empty => p1_fifo_empty,
clk => clk,
clk_en => module_input1,
fifo_read => fifo_read,
fifo_wr_data => fifo_wr_data,
fifo_write => fifo_write,
flush_fifo => flush_fifo,
inc_pending_data => fifo_write,
reset_n => reset_n
);
module_input1 <= std_logic'('1');
process (clk, reset_n)
begin
if reset_n = '0' then
full_width_rdv_counter <= std_logic_vector'("000");
elsif clk'event and clk = '1' then
full_width_rdv_counter <= A_EXT (A_WE_StdLogicVector((std_logic'((((state_idle AND upstream_read) AND NOT internal_upstream_waitrequest))) = '1'), std_logic_vector'("000000000000000000000000000000000"), A_WE_StdLogicVector((std_logic'(internal_upstream_readdatavalid) = '1'), ((std_logic_vector'("000000000000000000000000000000") & (full_width_rdv_counter)) + std_logic_vector'("000000000000000000000000000000001")), (std_logic_vector'("000000000000000000000000000000") & (full_width_rdv_counter)))), 3);
end if;
end process;
internal_upstream_readdatavalid <= fifo_datavalid;
upstream_readdata <= A_WE_StdLogicVector(((std_logic_vector'("00000000000000000000000000000000") = (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(negative_dbs_rdv_counter))))), Std_Logic_Vector'(fifo_rd_data(15 DOWNTO 0) & fifo_rd_data(15 DOWNTO 0)), Std_Logic_Vector'(fifo_rd_data(31 DOWNTO 16) & fifo_rd_data(31 DOWNTO 16)));
internal_downstream_byteenable <= upstream_byteenable;
internal_downstream_write <= ((upstream_write AND state_busy) AND NOT(pending_upstream_read)) AND fifo_empty;
downstream_writedata <= upstream_writedata;
upstream_read_run <= state_idle AND upstream_read;
upstream_write_run <= ((state_busy AND upstream_write) AND NOT downstream_waitrequest) AND NOT(internal_downstream_read);
internal_upstream_waitrequest <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(((upstream_read OR current_upstream_read))) = '1'), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT upstream_read_run))), A_WE_StdLogicVector((std_logic'(current_upstream_write) = '1'), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT upstream_write_run))), std_logic_vector'("00000000000000000000000000000001"))));
downstream_debugaccess <= upstream_debugaccess;
--vhdl renameroo for output signals
downstream_burstcount <= internal_downstream_burstcount;
--vhdl renameroo for output signals
downstream_byteenable <= internal_downstream_byteenable;
--vhdl renameroo for output signals
downstream_read <= internal_downstream_read;
--vhdl renameroo for output signals
downstream_write <= internal_downstream_write;
--vhdl renameroo for output signals
upstream_readdatavalid <= internal_upstream_readdatavalid;
--vhdl renameroo for output signals
upstream_waitrequest <= internal_upstream_waitrequest;
--synthesis translate_off
process (clk)
VARIABLE write_line : line;
begin
if clk'event and clk = '1' then
if std_logic'((fifo_full AND fifo_write)) = '1' then
write(write_line, now);
write(write_line, string'(": "));
write(write_line, string'("simulation assertion failed: niosII_openMac_burst_0: illegal write into full fifo."));
write(output, write_line.all);
deallocate (write_line);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--synthesis translate_on
end europa;
| gpl-2.0 | 81722b6f2e8f847e8295e4cd0fa75c7e | 0.629457 | 3.964067 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/xilinx/memory/src/dpRamSplxNbe-rtl-a.vhd | 3 | 3,991 | -------------------------------------------------------------------------------
--! @file dpRamSplxNbe-a.vhd
--
--! @brief Simplex Dual Port Ram without byteenables
--
--! @details This is the Simplex DPRAM without byteenables for Xilinx platforms.
--! The DPRAM has one write and one read port only.
--! Timing as follows [clk-cycles]: write=0 / read=1
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
architecture rtl of dpRamSplxNbe is
--! Address width (used to generate size depending on address width)
constant cAddrWidth : natural := iAddress_A'length;
--! RAM size
constant cRamSize : natural := 2**cAddrWidth;
--! Type for data port
subtype tDataPort is std_logic_vector(gWordWidth-1 downto 0);
--! RAM type with given size
type tRam is array (cRamSize-1 downto 0) of tDataPort;
--! Shared variable to model and synthesize a DPR
shared variable vDpram : tRam := (others => (others => cInactivated));
--! Port B readport
signal readdataB : tDataPort;
begin
-- assign readdata to ports
oReaddata_B <= readdataB;
--! This process describes port A of the DPRAM. The write process considers
--! iWriteEnable_A.
PORTA : process(iClk_A)
begin
if rising_edge(iClk_A) then
if iEnable_A = cActivated then
if iWriteEnable_A = cActivated then
-- write byte to DPRAM
vDpram(to_integer(unsigned(iAddress_A))) := iWritedata_A;
end if; --writeenable
end if; --enable
end if;
end process PORTA;
--! This process describes port B of the DPRAM. The read process is done
--! with every rising iClk_B edge.
PORTB : process(iClk_B)
begin
if rising_edge(iClk_B) then
if iEnable_B = cActivated then
-- read word from DPRAM
readdataB <= vDpram(to_integer(unsigned(iAddress_B)));
end if; --enable
end if;
end process PORTB;
end architecture rtl;
| gpl-2.0 | 73b1351fdce4340e52d273f296bf6055 | 0.632423 | 4.695294 | false | false | false | false |
cnplab/blockmon | fw-combo/src/IPFIX/comp/sh_reg_bus.vhd | 1 | 4,842 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
--
-- sh_reg_bus.vhd: Shift Register Bus
-- Copyright (C) 2003 CESNET
-- Author(s): Martinek Tomas <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: sh_reg_bus.vhd 24 2007-07-31 11:19:09Z kosek $
--
-- TODO:
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity sh_reg_bus is
generic(
NUM_BITS : integer := 16;
INIT : std_logic_vector(15 downto 0) := X"0000";
INIT_EXT00 : std_logic_vector(63 downto 0) := X"0000000000000000";
DATA_WIDTH : integer := 1
);
port(
CLK : in std_logic;
DIN : in std_logic_vector(DATA_WIDTH-1 downto 0);
CE : in std_logic;
DOUT : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end entity sh_reg_bus;
-- ----------------------------------------------------------------------------
-- Architecture declaration
-- ----------------------------------------------------------------------------
architecture behavioral of sh_reg_bus is
constant NUM_ELEMS : integer := (NUM_BITS+15)/16;
type t_vector4 is array (0 to NUM_ELEMS-1) of std_logic_vector(3 downto 0);
type t_vector_dw is array (0 to NUM_ELEMS) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal regsh_do : t_vector_dw;
signal regsh_addr : t_vector4;
begin
regsh_do(0) <= DIN;
SH_REG_XU : for i in 0 to NUM_ELEMS-1 generate
-- addr generation
regsh_addr(i) <= "1111" when (i < NUM_ELEMS-1) else
conv_std_logic_vector((NUM_BITS mod 16)+15, 4);
-- data width generation
SH_DATA_WIDTH : for j in 0 to DATA_WIDTH-1 generate
init_16p: if i = 0 generate
SH_REG_U : entity work.sh_reg_elem
generic map(
SH_INIT => INIT
)
port map(
CLK => CLK,
DIN => regsh_do(i)(j),
CE => CE,
ADDR => regsh_addr(i),
DOUT => regsh_do(i+1)(j)
);
end generate;
init_ext00p: if i > 0 generate
SH_REG_U : entity work.sh_reg_elem
generic map(
SH_INIT => INIT_EXT00((i*16)-1 downto (i-1)*16)
)
port map(
CLK => CLK,
DIN => regsh_do(i)(j),
CE => CE,
ADDR => regsh_addr(i),
DOUT => regsh_do(i+1)(j)
);
end generate;
end generate;
end generate;
DOUT <= regsh_do(NUM_ELEMS);
end architecture behavioral;
| bsd-3-clause | 71ae76010dacceeec8f3a99420cee21e | 0.550599 | 4.156223 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/altera/openmac/src/alteraOpenmacTop-rtl-ea.vhd | 1 | 20,965 | -------------------------------------------------------------------------------
--! @file alteraOpenmacTop-rtl-ea.vhd
--
--! @brief OpenMAC toplevel for Altera
--
--! @details This is the openMAC toplevel for Altera platform.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
--! Work library
library work;
--! use openmac package
use work.openmacPkg.all;
entity alteraOpenmacTop is
generic (
-----------------------------------------------------------------------
-- Phy configuration
-----------------------------------------------------------------------
--! Number of Phy ports
gPhyPortCount : natural := 2;
--! Phy port interface type (Rmii or Mii)
gPhyPortType : natural := cPhyPortRmii;
--! Number of SMI phy ports
gSmiPortCount : natural := 1;
-----------------------------------------------------------------------
-- General configuration
-----------------------------------------------------------------------
--! Endianness ("little" or "big")
gEndianness : string := "little";
--! Enable packet activity generator (e.g. connect to LED)
gEnableActivity : natural := cFalse;
--! Enable DMA observer circuit
gEnableDmaObserver : natural := cFalse;
-----------------------------------------------------------------------
-- DMA configuration
-----------------------------------------------------------------------
--! DMA address width (byte-addressing)
gDmaAddrWidth : natural := 32;
--! DMA data width
gDmaDataWidth : natural := 16;
--! DMA burst count width
gDmaBurstCountWidth : natural := 4;
--! DMA write burst length (Rx packets) [words]
gDmaWriteBurstLength : natural := 16;
--! DMA read burst length (Tx packets) [words]
gDmaReadBurstLength : natural := 16;
--! DMA write FIFO length (Rx packets) [words]
gDmaWriteFifoLength : natural := 16;
--! DMA read FIFO length (Tx packets) [words]
gDmaReadFifoLength : natural := 16;
-----------------------------------------------------------------------
-- Packet buffer configuration
-----------------------------------------------------------------------
--! Packet buffer location for Tx packets
gPacketBufferLocTx : natural := cPktBufLocal;
--! Packet buffer location for Rx packets
gPacketBufferLocRx : natural := cPktBufLocal;
--! Packet buffer log2(size) [log2(bytes)]
gPacketBufferLog2Size : natural := 10;
-----------------------------------------------------------------------
-- MAC timer configuration
-----------------------------------------------------------------------
--! Number of timers
gTimerCount : natural := 2;
--! Enable timer pulse width control
gTimerEnablePulseWidth : natural := cFalse;
--! Timer pulse width register width
gTimerPulseRegWidth : natural := 10
);
port (
-----------------------------------------------------------------------
-- Clock and reset signal pairs
-----------------------------------------------------------------------
--! Main clock used for openMAC, openHUB and openFILTER (freq = 50 MHz)
csi_mainClk_clock : in std_logic;
--! Main reset used for openMAC, openHUB and openFILTER
rsi_mainRst_reset : in std_logic;
--! DMA master clock
csi_dmaClk_clock : in std_logic;
--! DMA master reset
rsi_dmaRst_reset : in std_logic;
--! Packet buffer clock
csi_pktClk_clock : in std_logic;
--! Packet buffer reset
rsi_pktRst_reset : in std_logic;
--! Twice main clock used for Rmii Tx path
csi_mainClkx2_clock : in std_logic;
-----------------------------------------------------------------------
-- MAC REG memory mapped slave
-----------------------------------------------------------------------
--! MM slave MAC REGISTER chipselect
avs_macReg_chipselect : in std_logic;
--! MM slave MAC REGISTER write
avs_macReg_write : in std_logic;
--! MM slave MAC REGISTER read
avs_macReg_read : in std_logic;
--! MM slave MAC REGISTER waitrequest
avs_macReg_waitrequest : out std_logic;
--! MM slave MAC REGISTER byteenable
avs_macReg_byteenable : in std_logic_vector(cMacRegDataWidth/cByteLength-1 downto 0);
--! MM slave MAC REGISTER address
avs_macReg_address : in std_logic_vector(cMacRegAddrWidth-1 downto 1);
--! MM slave MAC REGISTER writedata
avs_macReg_writedata : in std_logic_vector(cMacRegDataWidth-1 downto 0);
--! MM slave MAC REGISTER readdata
avs_macReg_readdata : out std_logic_vector(cMacRegDataWidth-1 downto 0);
-----------------------------------------------------------------------
-- MAC TIMER memory mapped slave
-----------------------------------------------------------------------
--! MM slave MAC TIMER chipselect
avs_macTimer_chipselect : in std_logic;
--! MM slave MAC TIMER write
avs_macTimer_write : in std_logic;
--! MM slave MAC TIMER read
avs_macTimer_read : in std_logic;
--! MM slave MAC TIMER waitrequest
avs_macTimer_waitrequest : out std_logic;
--! MM slave MAC TIMER address
avs_macTimer_address : in std_logic_vector(cMacTimerAddrWidth-1 downto 2);
--! MM slave MAC TIMER writedata
avs_macTimer_writedata : in std_logic_vector(cMacTimerDataWidth-1 downto 0);
--! MM slave MAC TIMER readdata
avs_macTimer_readdata : out std_logic_vector(cMacTimerDataWidth-1 downto 0);
-----------------------------------------------------------------------
-- MAC PACKET BUFFER memory mapped slave
-----------------------------------------------------------------------
--! MM slave MAC PACKET BUFFER chipselect
avs_pktBuf_chipselect : in std_logic;
--! MM slave MAC PACKET BUFFER write
avs_pktBuf_write : in std_logic;
--! MM slave MAC PACKET BUFFER read
avs_pktBuf_read : in std_logic;
--! MM slave MAC PACKET BUFFER waitrequest
avs_pktBuf_waitrequest : out std_logic;
--! MM slave MAC PACKET BUFFER byteenable
avs_pktBuf_byteenable : in std_logic_vector(cPktBufDataWidth/8-1 downto 0);
--! MM slave MAC PACKET BUFFER address (width given by gPacketBufferLog2Size)
avs_pktBuf_address : in std_logic_vector(gPacketBufferLog2Size-1 downto 2);
--! MM slave MAC PACKET BUFFER writedata
avs_pktBuf_writedata : in std_logic_vector(cPktBufDataWidth-1 downto 0);
--! MM slave MAC PACKET BUFFER readdata
avs_pktBuf_readdata : out std_logic_vector(cPktBufDataWidth-1 downto 0);
-----------------------------------------------------------------------
-- MAC DMA memory mapped master
-----------------------------------------------------------------------
--! MM master MAC DMA write
avm_dma_write : out std_logic;
--! MM master MAC DMA read
avm_dma_read : out std_logic;
--! MM master MAC DMA waitrequest
avm_dma_waitrequest : in std_logic;
--! MM master MAC DMA readdatavalid
avm_dma_readdatavalid : in std_logic;
--! MM master MAC DMA byteenable
avm_dma_byteenable : out std_logic_vector(gDmaDataWidth/8-1 downto 0);
--! MM master MAC DMA address
avm_dma_address : out std_logic_vector(gDmaAddrWidth-1 downto 0);
--! MM master MAC DMA burstcount
avm_dma_burstcount : out std_logic_vector(gDmaBurstCountWidth-1 downto 0);
--! MM master MAC DMA writedata
avm_dma_writedata : out std_logic_vector(gDmaDataWidth-1 downto 0);
--! MM master MAC DMA readdata
avm_dma_readdata : in std_logic_vector(gDmaDataWidth-1 downto 0);
-----------------------------------------------------------------------
-- Interrupts
-----------------------------------------------------------------------
--! MAC TIMER interrupt
ins_timerIrq_irq : out std_logic;
--! MAC interrupt
ins_macIrq_irq : out std_logic;
-----------------------------------------------------------------------
-- Rmii Phy ports
-----------------------------------------------------------------------
--! Rmii Rx Crs data valid ports
coe_rmii_rxCrsDataValid : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Rmii Rx data ports
coe_rmii_rxData : in std_logic_vector(gPhyPortCount*2-1 downto 0);
--! Rmii Rx error ports
coe_rmii_rxError : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Rmii Tx enable ports
coe_rmii_txEnable : out std_logic_vector(gPhyPortCount-1 downto 0);
--! Rmii Tx data ports
coe_rmii_txData : out std_logic_vector(gPhyPortCount*2-1 downto 0);
-----------------------------------------------------------------------
-- Mii Phy ports
-----------------------------------------------------------------------
--! Mii Rx data valid ports
coe_mii_rxDataValid : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Rx data ports
coe_mii_rxData : in std_logic_vector(gPhyPortCount*4-1 downto 0);
--! Mii Rx error ports
coe_mii_rxError : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Rx Clocks
coe_mii_rxClk : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Tx enable ports
coe_mii_txEnable : out std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Tx data ports
coe_mii_txData : out std_logic_vector(gPhyPortCount*4-1 downto 0);
--! Mii Tx Clocks
coe_mii_txClk : in std_logic_vector(gPhyPortCount-1 downto 0);
-----------------------------------------------------------------------
-- Phy management interface
-----------------------------------------------------------------------
--! Phy reset (low-active)
coe_smi_nPhyRst : out std_logic_vector(gSmiPortCount-1 downto 0);
--! SMI clock
coe_smi_clk : out std_logic_vector(gSmiPortCount-1 downto 0);
--! SMI data I/OI (tri-state buffer)
coe_smi_dio : inout std_logic_vector(gSmiPortCount-1 downto 0);
-----------------------------------------------------------------------
-- Other ports
-----------------------------------------------------------------------
--! Packet activity (enabled with gEnableActivity)
coe_pktActivity : out std_logic;
--! MAC TIMER outputs
coe_macTimerOut : out std_logic_vector(gTimerCount-1 downto 0)
);
end alteraOpenmacTop;
architecture rtl of alteraOpenmacTop is
--! Byte address of macReg
signal macReg_address : std_logic_vector(avs_macReg_address'left downto 0);
--! Byte address of macTimer
signal macTimer_address : std_logic_vector(avs_macTimer_address'left downto 0);
--! Byte address of pktBuf
signal pktBuf_address : std_logic_vector(avs_pktBuf_address'left downto 0);
--! Mac Tx interrupt
signal macTx_interrupt : std_logic;
--! Mac Rx interrupt
signal macRx_interrupt : std_logic;
--! Rmii Tx path
signal rmiiTx : tRmiiPathArray(gPhyPortCount-1 downto 0);
--! Rmii Rx path
signal rmiiRx : tRmiiPathArray(gPhyPortCount-1 downto 0);
--! Mii Tx path
signal miiTx : tMiiPathArray(gPhyPortCount-1 downto 0);
--! Mii Rx path
signal miiRx : tMiiPathArray(gPhyPortCount-1 downto 0);
--! Smi tri-state-buffer input
signal smi_data_in : std_logic_vector(gSmiPortCount-1 downto 0);
--! Smi tri-state-buffer output
signal smi_data_out : std_logic_vector(gSmiPortCount-1 downto 0);
--! Smi tri-state-buffer output enable
signal smi_data_outEnable : std_logic;
begin
---------------------------------------------------------------------------
-- Map outputs
---------------------------------------------------------------------------
-- Mac interrupts are or'd to single line.
ins_macIrq_irq <= macTx_interrupt or macRx_interrupt;
-- Phy Tx path
rmiiPathArrayToStdLogicVector(
iVector => rmiiTx,
oEnable => coe_rmii_txEnable,
oData => coe_rmii_txData
);
miiPathArrayToStdLogicVector(
iVector => miiTx,
oEnable => coe_mii_txEnable,
oData => coe_mii_txData
);
---------------------------------------------------------------------------
-- Map inputs
---------------------------------------------------------------------------
-- Assign byte addresses.
macReg_address <= avs_macReg_address & "0"; --word to byte
macTimer_address <= avs_macTimer_address & "00"; --dword to byte
pktBuf_address <= avs_pktBuf_address & "00"; --dword to byte
-- Phy Rx path
stdLogicVectorToRmiiPathArray(
iEnable => coe_rmii_rxCrsDataValid,
iData => coe_rmii_rxData,
oVector => rmiiRx
);
stdLogicVectorToMiiPathArray(
iEnable => coe_mii_rxDataValid,
iData => coe_mii_rxData,
oVector => miiRx
);
---------------------------------------------------------------------------
-- Map IOs
---------------------------------------------------------------------------
-- Assign SMI IO buffers
coe_smi_dio <= smi_data_out when smi_data_outEnable = cActivated else
(others => 'Z');
-- Simply assign the input vector.
smi_data_in <= coe_smi_dio;
--! This is the openMAC toplevel instantiation.
THEOPENMACTOP : entity work.openmacTop
generic map (
gPhyPortCount => gPhyPortCount,
gPhyPortType => gPhyPortType,
gSmiPortCount => gSmiPortCount,
gEndianness => gEndianness,
gEnableActivity => gEnableActivity,
gEnableDmaObserver => gEnableDmaObserver,
gDmaAddrWidth => gDmaAddrWidth,
gDmaDataWidth => gDmaDataWidth,
gDmaBurstCountWidth => gDmaBurstCountWidth,
gDmaWriteBurstLength => gDmaWriteBurstLength,
gDmaReadBurstLength => gDmaReadBurstLength,
gDmaWriteFifoLength => gDmaWriteFifoLength,
gDmaReadFifoLength => gDmaReadFifoLength,
gPacketBufferLocTx => gPacketBufferLocTx,
gPacketBufferLocRx => gPacketBufferLocRx,
gPacketBufferLog2Size => gPacketBufferLog2Size,
gTimerCount => gTimerCount,
gTimerEnablePulseWidth => gTimerEnablePulseWidth,
gTimerPulseRegWidth => gTimerPulseRegWidth
)
port map (
iClk => csi_mainClk_clock,
iRst => rsi_mainRst_reset,
iDmaClk => csi_dmaClk_clock,
iDmaRst => rsi_dmaRst_reset,
iPktBufClk => csi_pktClk_clock,
iPktBufRst => rsi_pktRst_reset,
iClk2x => csi_mainClkx2_clock,
iMacReg_chipselect => avs_macReg_chipselect,
iMacReg_write => avs_macReg_write,
iMacReg_read => avs_macReg_read,
oMacReg_waitrequest => avs_macReg_waitrequest,
iMacReg_byteenable => avs_macReg_byteenable,
iMacReg_address => macReg_address,
iMacReg_writedata => avs_macReg_writedata,
oMacReg_readdata => avs_macReg_readdata,
iMacTimer_chipselect => avs_macTimer_chipselect,
iMacTimer_write => avs_macTimer_write,
iMacTimer_read => avs_macTimer_read,
oMacTimer_waitrequest => avs_macTimer_waitrequest,
iMacTimer_address => macTimer_address,
iMacTimer_writedata => avs_macTimer_writedata,
oMacTimer_readdata => avs_macTimer_readdata,
iPktBuf_chipselect => avs_pktBuf_chipselect,
iPktBuf_write => avs_pktBuf_write,
iPktBuf_read => avs_pktBuf_read,
oPktBuf_waitrequest => avs_pktBuf_waitrequest,
iPktBuf_byteenable => avs_pktBuf_byteenable,
iPktBuf_address => pktBuf_address,
iPktBuf_writedata => avs_pktBuf_writedata,
oPktBuf_readdata => avs_pktBuf_readdata,
oDma_write => avm_dma_write,
oDma_read => avm_dma_read,
iDma_waitrequest => avm_dma_waitrequest,
iDma_readdatavalid => avm_dma_readdatavalid,
oDma_byteenable => avm_dma_byteenable,
oDma_address => avm_dma_address,
oDma_burstcount => avm_dma_burstcount,
oDma_burstcounter => open, --current burst counter state unused
oDma_writedata => avm_dma_writedata,
iDma_readdata => avm_dma_readdata,
oMacTimer_interrupt => ins_timerIrq_irq,
oMacTx_interrupt => macTx_interrupt,
oMacRx_interrupt => macRx_interrupt,
iRmii_Rx => rmiiRx,
iRmii_RxError => coe_rmii_rxError,
oRmii_Tx => rmiiTx,
iMii_Rx => miiRx,
iMii_RxError => coe_mii_rxError,
iMii_RxClk => coe_mii_rxClk,
oMii_Tx => miiTx,
iMii_TxClk => coe_mii_txClk,
onPhy_reset => coe_smi_nPhyRst,
oSmi_clk => coe_smi_clk,
oSmi_data_outEnable => smi_data_outEnable,
oSmi_data_out => smi_data_out,
iSmi_data_in => smi_data_in,
oActivity => coe_pktActivity,
oMacTimer => coe_macTimerOut
);
end rtl;
| gpl-2.0 | 0af7646e9a4bde56a162e32d910aeea4 | 0.498641 | 5.286183 | false | false | false | false |
cnplab/blockmon | fw-combo/src/IPFIX/combov2_user_const.vhd | 1 | 5,818 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- combov2_user_const.vhd: User constants for NetCOPE on ComboV2
-- Copyright (C) 2008 CESNET
-- Author(s): Viktor Pus <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id$
--
library IEEE;
use IEEE.std_logic_1164.all;
package combov2_user_const is
-- -------------------------------------------------------------------------
-- constant PCIE_EP_IFC_125 : boolean := true;-- true=125 MHz endpoint, false=250 MHz -- now this is obsolete
-- -------------------------------------------------------------------------
-- Clock frequencies setting
-- -------------------------------------------------------------------------
constant CLK_MULT : integer := 9; -- Fvco = 62.5 MHz x CLK_MULT
constant CLK_ICS_DIV : integer := 3; -- CLK_ICS freq. = Fvco / CLK_ICS_DIV
constant CLK_USER0_DIV : integer := 5; -- CLK_USER0 freq. = Fvco / CLK_USER0_DIV
constant CLK_USER1_DIV : integer := 5; -- CLK_USER1 freq. = Fvco / CLK_USER1_DIV
constant CLK_USER2_DIV : integer := 5; -- CLK_USER2 freq. = Fvco / CLK_USER2_DIV
constant CLK_USER3_DIV : integer := 5; -- CLK_USER3 freq. = Fvco / CLK_USER3_DIV
constant CLK_USER4_DIV : integer := 5; -- CLK_USER4 freq. = Fvco / CLK_USER4_DIV
-- -------------------------------------------------------------------------
-- Design identification ---------------------------------------------------
constant ID_PROJECT : std_logic_vector( 15 downto 0):= X"F101";
constant ID_SW_MAJOR : std_logic_vector( 7 downto 0):= X"03";
constant ID_SW_MINOR : std_logic_vector( 7 downto 0):= X"0C";
constant ID_HW_MAJOR : std_logic_vector( 15 downto 0):= X"0007";
constant ID_HW_MINOR : std_logic_vector( 15 downto 0):= X"0000";
-- F l e x i b l e _ F l o w M o n\0
constant ID_PROJECT_TEXT : std_logic_vector(255 downto 0) :=
X"466C657869626C655F466C6F774D6F6E00000000000000000000000000000000";
constant ID_TX_CHANNELS : std_logic_vector( 7 downto 0):= X"00";
constant ID_RX_CHANNELS : std_logic_vector( 7 downto 0):= X"08";
-- -------------------------------------------------------------------------
-- Network Module setting (constant INBANDFCS) is done in NetCOPE's network module
-- -------------------------------------------------------------------------
-- DMA Module setting
-- straight zero copy DMA - Non-generic version
-- constant DMA_TYPE : String := "SZE";
-- straight zero copy DMA - Generic version
constant DMA_TYPE : String := "GEN";
-- packet DMA through linux kernel stack
-- constant DMA_TYPE : String := "PAC";
-- -------------------------------------------------------------------------
-- Timestamp unit setting
-- Set to false if you don't need timestamps
-- Synchronize your choice with ../top/combov2/Makefile (USE_TIMESTAMP)
constant TIMESTAMP_UNIT : boolean := true;
-- constant TIMESTAMP_UNIT : boolean := false;
-- -------------------------------------------------------------------------
-- Support for JUMBO packets
-- (un)comment all three lines together
-- Synchronize your choice with ../top/combov2/Makefile (JUMBO)
constant JUMBO : boolean := true;
constant MAX_MTU_RX : std_logic_vector(31 downto 0) := X"00003FE0";
constant MAX_MTU_TX : std_logic_vector(31 downto 0) := X"00003FE0";
-- constant JUMBO : boolean := false;
-- constant MAX_MTU_RX : std_logic_vector(31 downto 0) := X"00000FE0";
-- constant MAX_MTU_TX : std_logic_vector(31 downto 0) := X"00000FE0";
end combov2_user_const;
package body combov2_user_const is
end combov2_user_const;
| bsd-3-clause | e4f2409e5734f89632f033a36db1febb | 0.567893 | 4.284242 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/xilinx/hostinterface/src/axi_hostinterface-rtl-ea.vhd | 1 | 34,979 | -------------------------------------------------------------------------------
--! @file axi_hostinterface.vhd
--
--! @brief toplevel of host interface for Xilinx FPGA
--
--! @details This toplevel interfaces to Xilinx specific implementation.
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2014, Bernecker+Rainer Industrie-Elektronik Ges.m.b.H. (B&R)
-- Copyright (c) 2014, Kalycito Infotech Private Limited
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--! Use standard ieee library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Use work library
library work;
--! Common library
library libcommon;
--! Use global library
use libcommon.global.all;
entity axi_hostinterface is
generic (
--! PCP AXI Slave Data Width
C_S_AXI_DATA_WIDTH : integer := 32;
--! PCP AXI Slave Address width
C_S_AXI_ADDR_WIDTH : integer := 32;
--! PCP AXI Min Address range size (64Kb limited by scripts)
C_S_AXI_MIN_SIZE : std_logic_vector := X"0001FFFF";
--! PCP AXI Slave Base Address
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
--! PCP AXI Slave High Address
C_HIGHADDR : std_logic_vector := X"00000000";
--! PCP AXI IP Family
C_FAMILY : string := "virtex6";
--! Host AXI Slave Data Width
C_S_HOST_AXI_DATA_WIDTH : integer := 32;
--! Host AXI Address Width
C_S_HOST_AXI_ADDR_WIDTH : integer := 32;
--! HOST AXI Min Address range size
C_S_HOST_AXI_MIN_SIZE : std_logic_vector := X"0001FFFF";
--! HOST AXI Slave Base Address
C_HOST_BASEADDR : std_logic_vector := X"FFFFFFFF";
--! HOST AXI Slave High Address
C_HOST_HIGHADDR : std_logic_vector := X"00000000";
--! HOST AXI IP Family
C_HOST_FAMILY : string := "virtex6";
--! Master Bridge Address Width
C_M_AXI_ADDR_WIDTH : integer := 32;
--! Master Bridge Data Width
C_M_AXI_DATA_WIDTH : integer := 32;
--! Host Interface Version major
gVersionMajor : natural := 16#FF#;
--! Host Interface Version minor
gVersionMinor : natural := 16#FF#;
--! Host Interface Version revision
gVersionRevision : natural := 16#FF#;
--! Host Interface Version count
gVersionCount : natural := 0;
--! Host Interface Base address Dynamic Buffer 0
gBaseDynBuf0 : natural := 16#00800#;
--! Host Interface Base address Dynamic Buffer 1
gBaseDynBuf1 : natural := 16#01000#;
--! Host Interface Base address Error Counter
gBaseErrCntr : natural := 16#01800#;
--! Host Interface Base address TX NMT Queue
gBaseTxNmtQ : natural := 16#02800#;
--! Host Interface Base address TX Generic Queue
gBaseTxGenQ : natural := 16#03800#;
--! Host Interface Base address TX SyncRequest Queue
gBaseTxSynQ : natural := 16#04800#;
--! Host Interface Base address TX Virtual Ethernet Queue
gBaseTxVetQ : natural := 16#05800#;
--! Host Interface Base address RX Virtual Ethernet Queue
gBaseRxVetQ : natural := 16#06800#;
--! Host Interface Base address Kernel-to-User Queue
gBaseK2UQ : natural := 16#07000#;
--! Host Interface Base address User-to-Kernel Queue
gBaseU2KQ : natural := 16#09000#;
--! Host Interface Base address Pdo
gBasePdo : natural := 16#0B000#;
--! Host Interface Base address Reserved (-1 = high address of Rpdo)
gBaseRes : natural := 16#0E000#;
--! Select Host Interface Type (0 = Avalon, 1 = Parallel)
gHostIfType : natural := 0;
--! Data width of parallel interface (16/32)
gParallelDataWidth : natural := 16;
--! Address and Data bus are multiplexed (0 = FALSE, otherwise = TRUE)
gParallelMultiplex : natural := 0
);
port (
--! AXI PCP slave PCP clock
S_AXI_PCP_ACLK : in std_logic;
--! AXI PCP slave PCP Reset Active low
S_AXI_PCP_ARESETN : in std_logic;
--! AXI PCP slave PCP Address
S_AXI_PCP_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
--! AXI PCP slave PCP Address Valid
S_AXI_PCP_AWVALID : in std_logic;
--! AXI PCP slave Write Data
S_AXI_PCP_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
--! AXI PCP slave Write Strobe
S_AXI_PCP_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
--! AXI PCP slave Write Valid
S_AXI_PCP_WVALID : in std_logic;
--! AXI PCP slave Write Response Ready
S_AXI_PCP_BREADY : in std_logic;
--! AXI PCP slave Write Response Valid
S_AXI_PCP_BVALID : out std_logic;
--! AXI PCP slave Write Response
S_AXI_PCP_BRESP : out std_logic_vector(1 downto 0);
--! AXI PCP slave Read Address
S_AXI_PCP_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
--! AXI PCP slave Address Valid
S_AXI_PCP_ARVALID : in std_logic;
--! AXI PCP slave Read Ready
S_AXI_PCP_RREADY : in std_logic;
--! AXI PCP slave Read Address Ready
S_AXI_PCP_ARREADY : out std_logic;
--! AXI PCP slave Read Data
S_AXI_PCP_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
--! AXI PCP slave Read Response
S_AXI_PCP_RRESP : out std_logic_vector(1 downto 0);
--! AXI PCP slave Read Valid
S_AXI_PCP_RVALID : out std_logic;
--! AXI PCP slave Write ready
S_AXI_PCP_WREADY : out std_logic;
--! AXI PCP slave Write Address Ready
S_AXI_PCP_AWREADY : out std_logic;
-- Host Interface AXI
--! AXI Host Slave Clock
S_AXI_HOST_ACLK : in std_logic;
--! AXI Host Slave Reset active low
S_AXI_HOST_ARESETN : in std_logic;
--! AXI Host Slave Write Address
S_AXI_HOST_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
--! AXI Host Slave Write Address valid
S_AXI_HOST_AWVALID : in std_logic;
--! AXI Host Slave Write Data
S_AXI_HOST_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
--! AXI Host Slave Write strobe
S_AXI_HOST_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
--! AXI Host Slave write Valid
S_AXI_HOST_WVALID : in std_logic;
--! AXI Host Slave Response Ready
S_AXI_HOST_BREADY : in std_logic;
--! AXI Host Slave Read Address
S_AXI_HOST_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
--! AXI Host Slave Read Address Valid
S_AXI_HOST_ARVALID : in std_logic;
--! AXI Host Slave Read Ready
S_AXI_HOST_RREADY : in std_logic;
--! AXI Host Slave Read Address Ready
S_AXI_HOST_ARREADY : out std_logic;
--! AXI Host SlaveRead Data
S_AXI_HOST_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
--! AXI Host Slave Read Response
S_AXI_HOST_RRESP : out std_logic_vector(1 downto 0);
--! AXI Host Slave Read Valid
S_AXI_HOST_RVALID : out std_logic;
--! AXI Host Slave Write Ready
S_AXI_HOST_WREADY : out std_logic;
--! AXI Host Slave Write Response
S_AXI_HOST_BRESP : out std_logic_vector(1 downto 0);
--! AXI Host Slave Write Response Valid
S_AXI_HOST_BVALID : out std_logic;
--! AXI Host Slave Write Address Ready
S_AXI_HOST_AWREADY : out std_logic;
-- Master Bridge Ports
--! AXI Bridge Master Clock
M_AXI_ACLK : in std_logic;
--! AXI Bridge Master Reset Active low
M_AXI_ARESETN : in std_logic;
--! AXI Bridge Master Write Address
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
--! AXI Bridge Master Write Address Write protection
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
--! AXI Bridge Master Write Address Valid
M_AXI_AWVALID : out std_logic;
--! AXI Bridge Master Write Ready
M_AXI_AWREADY : in std_logic;
--! AXI Bridge Master Write Data
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
--! AXI Bridge Master Write Strobe
M_AXI_WSTRB : out std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
--! AXI Bridge Master Write Valid
M_AXI_WVALID : out std_logic;
--! AXI Bridge Master Write Last to support AXI4 feature
M_AXI_WLAST : out std_logic;
--! AXI Bridge Master Write Ready
M_AXI_WREADY : in std_logic;
--! AXI Bridge Master Response
M_AXI_BRESP : in std_logic_vector(1 downto 0);
--! AXI Bridge Master Response Valid
M_AXI_BVALID : in std_logic;
--! AXI Bridge Master Response Ready
M_AXI_BREADY : out std_logic;
--! AXI Bridge Master Read Address
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
--! AXI Bridge Master Read Protection
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
--! AXI Bridge Master Read Address Valid
M_AXI_ARVALID : out std_logic;
--! AXI Bridge Master Read Address Ready
M_AXI_ARREADY : in std_logic;
--! AXI Bridge Master Read Data
M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
--! AXI Bridge Master Read Response
M_AXI_RRESP : in std_logic_vector(1 downto 0);
--! AXI Bridge Master Read Valid
M_AXI_RVALID : in std_logic;
--! AXI Bridge Master Read Ready
M_AXI_RREADY : out std_logic;
-- Misc ports
--! HostInterface Interrupt receiver
irqSync_irq : in std_logic;
--! HostInterface Interrupt sender
irqOut_irq : out std_logic;
--! External Sync Source
iExtSync_exsync : in std_logic;
-- Parallel Host Interface
--! Parallel Interface Chip select
iParHost_chipselect : in std_logic;
--! Parallel Interface Read Signal
iParHost_read : in std_logic;
--! Parallel Interface Write Signal
iParHost_write : in std_logic;
--! Parallel Interface Address Latch enable (Multiplexed only)
iParHost_addressLatchEnable : in std_logic;
--! Parallel Interface High active Acknowledge
oParHost_acknowledge : out std_logic;
--! Parallel Interface Byte enables
iParHost_byteenable : in std_logic_vector(gParallelDataWidth/8-1 downto 0);
--! Parallel Interface Address bus (De-multiplexed, word-address)
iParHost_address : in std_logic_vector(15 downto 0);
-- Data bus IO
--! Parallel Interface Data bus input (De-multiplexed)
iParHost_data_io : in std_logic_vector(gParallelDataWidth-1 downto 0);
--! Parallel Interface Data bus output (De-multiplexed)
oParHost_data_io : out std_logic_vector(gParallelDataWidth-1 downto 0);
--! Parallel Interface Data bus tri-state enable (De-multiplexed)
oParHost_data_io_tri : out std_logic;
-- Address/data bus IO
--! Parallel Interface Address/Data bus input (Multiplexed, word-address))
iParHost_addressData_io : in std_logic_vector(gParallelDataWidth-1 downto 0);
--! Parallel Interface Address/Data bus output (Multiplexed, word-address))
oParHost_addressData_io : out std_logic_vector(gParallelDataWidth-1 downto 0);
--! Parallel Interface Address/Data bus tri-state Enable(Multiplexed, word-address))
oParHost_addressData_tri : out std_logic
);
--! Declaration for Maximum Fan out attribute
attribute MAX_FANOUT : string;
--! Declaration for Class of special signals
attribute SIGIS : string;
--! Maximum fan out for PCP clock
attribute MAX_FANOUT of S_AXI_PCP_ACLK : signal is "10000";
--! Maximum fan out for PCP Reset
attribute MAX_FANOUT of S_AXI_PCP_ARESETN : signal is "10000";
--! PCP clock is declared under clock group
attribute SIGIS of S_AXI_PCP_ACLK : signal is "Clk";
--! PCP Reset is declared under Reset group
attribute SIGIS of S_AXI_PCP_ARESETN : signal is "Rst";
--! Maximum fan out for Host clock
attribute MAX_FANOUT of S_AXI_HOST_ACLK : signal is "10000";
--! Maximum fan out for Host Reset
attribute MAX_FANOUT of S_AXI_HOST_ARESETN : signal is "10000";
--! Host clock is declared under clock group
attribute SIGIS of S_AXI_HOST_ACLK : signal is "Clk";
--! Host Reset is declared under Reset group
attribute SIGIS of S_AXI_HOST_ARESETN : signal is "Rst";
--! Maximum fan out for Bridge clock
attribute MAX_FANOUT of M_AXI_ACLK : signal is "10000";
--! Maximum fan out for Bridge Reset
attribute MAX_FANOUT of M_AXI_ARESETN : signal is "10000";
--! Bridge clock is declared under clock group
attribute SIGIS of M_AXI_ACLK : signal is "Clk";
--! Bridge Reset is declared under Reset group
attribute SIGIS of M_AXI_ARESETN : signal is "Rst";
end entity axi_hostinterface;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture rtl of axi_hostinterface is
--! Use memory blocks or registers for translation address storage (registers = 0, memory blocks /= 0)
constant cBridgeUseMemBlock : natural := cTrue;
--TODO: Export Non-secure transitions signals to top level
--! Non-secure Write signal for PCP Slave interface
signal S_AXI_PCP_AWPROT : std_logic_vector(2 downto 0);
--! Non-secure Read signal for PCP Slave interface
signal S_AXI_PCP_ARPROT : std_logic_vector(2 downto 0);
--! Non-secure Write signal for Host Slave Interface
signal S_AXI_HOST_AWPROT : std_logic_vector(2 downto 0);
--! Non-Secure Read signal for Host Slave interface
signal S_AXI_HOST_ARPROT : std_logic_vector(2 downto 0);
--Signals for wrapper to PCP Host Interface
--! Avalon slave Address for PCP
signal AvsPcpAddress : std_logic_vector(31 downto 0);
--! Avalon slave byte enable for PCP
signal AvsPcpByteenable : std_logic_vector(3 downto 0);
--! Avalon slave Read signal for PCP
signal AvsPcpRead : std_logic;
--! Avalon slave Write signal for PCP
signal AvsPcpWrite : std_logic;
--! Avalon slave Write Data for PCP
signal AvsPcpWritedata : std_logic_vector(31 downto 0);
--! Avalon slave Read Data for PCP
signal AvsPcpReaddata : std_logic_vector(31 downto 0);
--! Avalon slave wait request for PCP
signal AvsPcpWaitrequest : std_logic;
-- Avalon Master Bridge signals to AXI master
--! Avalon master Address for Bridge Interface
signal avm_hostBridge_address : std_logic_vector(29 downto 0);
--! Avalon master Byte Enable for Bridge Interface
signal avm_hostBridge_byteenable : std_logic_vector(3 downto 0);
--! Avalon master Read signal for Bridge Interface
signal avm_hostBridge_read : std_logic;
--! Avalon master Read Data signal for Bridge Interface
signal avm_hostBridge_readdata : std_logic_vector(31 downto 0);
--! Avalon master write signal for Bridge Interface
signal avm_hostBridge_write : std_logic;
--! Avalon master write data for Bridge Interface
signal avm_hostBridge_writedata : std_logic_vector(31 downto 0);
--! Avalon master wait request for Bridge Interface
signal avm_hostBridge_waitrequest : std_logic;
-- Host Interface Internal Bus (For Internal Host Processor)
--! Avalon slave Address for Host processor
signal AvsHostAddress : std_logic_vector(31 downto 0);
--! Avalon slave Byte enable for Host processor
signal AvsHostByteenable : std_logic_vector(3 downto 0);
--! Avalon slave Read signal for Host processor
signal AvsHostRead : std_logic;
--! Avalon slave Write signal for Host processor
signal AvsHostWrite : std_logic;
--! Avalon slave write data for Host processor
signal AvsHostWritedata : std_logic_vector(31 downto 0);
--! Avalon slave Read data for Host processor
signal AvsHostReaddata : std_logic_vector(31 downto 0);
--! Avalon Slave wait request for Host Processor
signal AvsHostWaitrequest : std_logic;
-- Common signals used for different host source (internal/External)
--! Host Processor (External/Internal) Address
signal host_address : std_logic_vector(16 downto 2);
--! Host Processor (External/Internal) Byte enable
signal host_byteenable : std_logic_vector(3 downto 0);
--! Host Processor (External/Internal) Read signal
signal host_Read : std_logic;
--! Host Processor (External/Internal) Read Data
signal host_readdata : std_logic_vector(31 downto 0);
--! Host Processor (External/Internal) write signal
signal host_write : std_logic;
--! Host Processor (External/Internal) write data
signal host_writedata : std_logic_vector(31 downto 0);
--! Host Processor (External/Internal) wait request
signal host_waitrequest : std_logic;
--! Clock signal for host interface and axi-wrappers
signal hostif_clock : std_logic;
--! Active high Reset for host interface
signal hostif_reset : std_logic;
--! Word aligned address for Bridge signal
signal AxiLiteBridgeAddress : std_logic_vector(31 downto 0);
begin
-- clock signal host interface IP core
hostif_clock <= S_AXI_PCP_ACLK;
-- Active high for rest for Host interface IP core
hostif_reset <= not S_AXI_PCP_ARESETN;
---------------------------------------------------------------------------
-- Host Interface IP
---------------------------------------------------------------------------
--! The Host Interface IP core
theHostInterface: entity work.hostInterface
generic map (
gVersionMajor => gVersionMajor,
gVersionMinor => gVersionMinor,
gVersionRevision => gVersionRevision,
gVersionCount => gVersionCount,
gBridgeUseMemBlock => cBridgeUseMemBlock,
gBaseDynBuf0 => gBaseDynBuf0,
gBaseDynBuf1 => gBaseDynBuf1,
gBaseErrCntr => gBaseErrCntr,
gBaseTxNmtQ => gBaseTxNmtQ,
gBaseTxGenQ => gBaseTxGenQ,
gBaseTxSynQ => gBaseTxSynQ,
gBaseTxVetQ => gBaseTxVetQ,
gBaseRxVetQ => gBaseRxVetQ,
gBaseK2UQ => gBaseK2UQ,
gBaseU2KQ => gBaseU2KQ,
gBasePdo => gBasePdo,
gBaseRes => gBaseRes,
--FIXME: Assign address width depending on memory span!
gHostAddrWidth => host_address'left+1
)
port map (
iClk => hostif_clock,
iRst => hostif_reset,
iHostAddress => host_address,
iHostByteenable => host_byteenable,
iHostRead => host_Read,
oHostReaddata => host_readdata,
iHostWrite => host_write,
iHostWritedata => host_writedata,
oHostWaitrequest => host_waitrequest,
iPcpAddress => AvsPcpAddress(10 downto 2),
iPcpByteenable => AvsPcpByteenable,
iPcpRead => AvsPcpRead,
oPcpReaddata => AvsPcpReaddata,
iPcpWrite => AvsPcpWrite,
iPcpWritedata => AvsPcpWritedata,
oPcpWaitrequest => AvsPcpWaitrequest,
oHostBridgeAddress => avm_hostBridge_address,
oHostBridgeByteenable => avm_hostBridge_byteenable,
oHostBridgeRead => avm_hostBridge_read,
iHostBridgeReaddata => avm_hostBridge_readdata,
oHostBridgeWrite => avm_hostBridge_write,
oHostBridgeWritedata => avm_hostBridge_writedata,
iHostBridgeWaitrequest => avm_hostBridge_waitrequest,
iIrqIntSync => irqSync_irq,
iIrqExtSync => iExtSync_exsync,
oIrq => irqOut_irq
);
---------------------------------------------------------------------------
-- PCP AXI-lite Slave Interface Wrapper
---------------------------------------------------------------------------
--! AXI-lite slave wrapper for PCP interface of HostinterfaceIP core
AXI_LITE_SLAVE_PCP: entity work.axiLiteSlaveWrapper
generic map (
gBaseAddr => C_BASEADDR,
gHighAddr => C_HIGHADDR,
gAddrWidth => 32,
gDataWidth => 32
)
port map (
-- System Signals
iAclk => S_AXI_PCP_ACLK,
inAReset => S_AXI_PCP_ARESETN,
-- Slave Interface Write Address Ports
iAwaddr => S_AXI_PCP_AWADDR,
iAwprot => S_AXI_PCP_AWPROT,
iAwvalid => S_AXI_PCP_AWVALID,
oAwready => S_AXI_PCP_AWREADY,
-- Slave Interface Write Data Ports
iWdata => S_AXI_PCP_WDATA,
iWstrb => S_AXI_PCP_WSTRB,
iWvalid => S_AXI_PCP_WVALID,
oWready => S_AXI_PCP_WREADY,
-- Slave Interface Write Response Ports
oBresp => S_AXI_PCP_BRESP,
oBvalid => S_AXI_PCP_BVALID,
iBready => S_AXI_PCP_BREADY,
-- Slave Interface Read Address Ports
iAraddr => S_AXI_PCP_ARADDR,
iArprot => S_AXI_PCP_ARPROT,
iArvalid => S_AXI_PCP_ARVALID,
oArready => S_AXI_PCP_ARREADY,
-- Slave Interface Read Data Ports
oRdata => S_AXI_PCP_RDATA,
oRresp => S_AXI_PCP_RRESP,
oRvalid => S_AXI_PCP_RVALID,
iRready => S_AXI_PCP_RREADY,
--Avalon Interface
oAvsAddress => AvsPcpAddress,
oAvsByteenable => AvsPcpByteenable,
oAvsRead => AvsPcpRead,
oAvsWrite => AvsPcpWrite,
oAvsWritedata => AvsPcpWritedata,
iAvsReaddata => AvsPcpReaddata,
iAvsWaitrequest => AvsPcpWaitrequest
);
---------------------------------------------------------------------------
-- Bridge AXI-lite Master Interface Wrapper
---------------------------------------------------------------------------
--! AXI-Lite Master Wrapper for Memory Interface of HostinterfaceIP Core
AXI_LITE_MASTER_BRIDGE: entity work.axiLiteMasterWrapper
generic map (
gAddrWidth => C_M_AXI_ADDR_WIDTH,
gDataWidth => C_M_AXI_DATA_WIDTH
)
port map (
-- System Signals
iAclk => M_AXI_ACLK,
inAReset => M_AXI_ARESETN,
-- Master Interface Write Address
oAwaddr => M_AXI_AWADDR,
oAwprot => M_AXI_AWPROT,
oAwvalid => M_AXI_AWVALID,
iAwready => M_AXI_AWREADY,
-- Master Interface Write Data
oWdata => M_AXI_WDATA,
oWstrb => M_AXI_WSTRB,
oWvalid => M_AXI_WVALID,
iWready => M_AXI_WREADY,
oWlast => M_AXI_WLAST,
-- Master Interface Write Response
iBresp => M_AXI_BRESP,
iBvalid => M_AXI_BVALID,
oBready => M_AXI_BREADY,
-- Master Interface Read Address
oAraddr => M_AXI_ARADDR,
oArprot => M_AXI_ARPROT,
oArvalid => M_AXI_ARVALID,
iArready => M_AXI_ARREADY,
-- Master Interface Read Data
iRdata => M_AXI_RDATA,
iRresp => M_AXI_RRESP,
iRvalid => M_AXI_RVALID,
oRready => M_AXI_RREADY,
-- Avalon master
iAvalonClk => hostif_clock,
iAvalonReset => hostif_reset,
iAvalonRead => avm_hostBridge_read,
iAvalonWrite => avm_hostBridge_write,
iAvalonAddr => AxiLiteBridgeAddress,
iAvalonBE => avm_hostBridge_byteenable,
oAvalonWaitReq => avm_hostBridge_waitrequest,
oAvalonReadValid => open,
oAvalonReadData => avm_hostBridge_readdata,
iAvalonWriteData => avm_hostBridge_writedata
);
--TODO: Try to use full memory range, now its allowed only up to 0x3FFFFFFF
--Convert 30bit address from Avalon master to 32 bit for AXI
AxiLiteBridgeAddress <= "00" & avm_hostBridge_address;
---------------------------------------------------------------------------
-- HOST AXI-lite Slave Interface Wrapper
---------------------------------------------------------------------------
-- Generate AXI-lite slave Interface for Internal Processor Interface
genAxiHost : if gHostIfType = 0 generate
begin
--! AXI-lite slave wrapper for internal processor
AXI_LITE_SLAVE_HOST: entity work.axiLiteSlaveWrapper
generic map (
gBaseAddr => C_HOST_BASEADDR,
gHighAddr => C_HOST_HIGHADDR,
gAddrWidth => 32,
gDataWidth => 32
)
port map (
-- System Signals
iAclk => S_AXI_HOST_ACLK,
inAReset => S_AXI_HOST_ARESETN,
-- Slave Interface Write Address Ports
iAwaddr => S_AXI_HOST_AWADDR,
iAwprot => S_AXI_HOST_AWPROT,
iAwvalid => S_AXI_HOST_AWVALID,
oAwready => S_AXI_HOST_AWREADY,
-- Slave Interface Write Data Ports
iWdata => S_AXI_HOST_WDATA,
iWstrb => S_AXI_HOST_WSTRB,
iWvalid => S_AXI_HOST_WVALID,
oWready => S_AXI_HOST_WREADY,
-- Slave Interface Write Response Ports
oBresp => S_AXI_HOST_BRESP,
oBvalid => S_AXI_HOST_BVALID,
iBready => S_AXI_HOST_BREADY,
-- Slave Interface Read Address Ports
iAraddr => S_AXI_HOST_ARADDR,
iArprot => S_AXI_HOST_ARPROT,
iArvalid => S_AXI_HOST_ARVALID,
oArready => S_AXI_HOST_ARREADY,
-- Slave Interface Read Data Ports
oRdata => S_AXI_HOST_RDATA,
oRresp => S_AXI_HOST_RRESP,
oRvalid => S_AXI_HOST_RVALID,
iRready => S_AXI_HOST_RREADY,
--Avalon Interface
oAvsAddress => AvsHostAddress,
oAvsByteenable => AvsHostByteenable,
oAvsRead => AvsHostRead,
oAvsWrite => AvsHostWrite,
oAvsWritedata => AvsHostWritedata,
iAvsReaddata => AvsHostReaddata,
iAvsWaitrequest => AvsHostWaitrequest
);
-- Interface signals are hand over to common signals used for
-- both external and internal processor
host_address <= AvsHostAddress(16 downto 2);
host_byteenable <= AvsHostByteenable;
host_Read <= AvsHostRead;
host_write <= AvsHostWrite;
host_writedata <= AvsHostWritedata;
AvsHostWaitrequest <= host_waitrequest;
AvsHostReaddata <= host_readdata;
end generate genAxiHost;
---------------------------------------------------------------------------
-- Parallel Interface External Host Processor
---------------------------------------------------------------------------
-- Generate Parallel Interface for External Processor Interface
genParallel : if gHostIfType = 1 generate
--! Host Data input signal for parallel Interface
signal hostData_i : std_logic_vector(gParallelDataWidth-1 downto 0);
--! Host Data output signal for Parallel Interface
signal hostData_o : std_logic_vector(gParallelDataWidth-1 downto 0);
--! Host Data Enable for switch between input and out for a tri-state buffer
signal hostData_en : std_logic;
--! AddressData input signal for Multiplexed address/data
signal hostAddressData_i : std_logic_vector(gParallelDataWidth-1 downto 0);
--! AddressData output signal for Multiplexed address/data
signal hostAddressData_o : std_logic_vector(gParallelDataWidth-1 downto 0);
--! AddressData Enable for switch between address and data for a tri-state buffer
signal hostAddressData_en: std_logic;
begin
--! Parallel interface For communicating with external Processor
theParallelInterface : entity work.parallelInterface
generic map (
gDataWidth => gParallelDataWidth,
gMultiplex => gParallelMultiplex
)
port map (
iParHostChipselect => iParHost_chipselect,
iParHostRead => iParHost_read,
iParHostWrite => iParHost_write,
iParHostAddressLatchEnable => iParHost_addressLatchEnable,
oParHostAcknowledge => oParHost_acknowledge,
iParHostByteenable => iParHost_byteenable,
iParHostAddress => iParHost_address,
oParHostData => hostData_o,
iParHostData => hostData_i,
oParHostDataEnable => hostData_en,
oParHostAddressData => hostAddressData_o,
iParHostAddressData => hostAddressData_i,
oParHostAddressDataEnable => hostAddressData_en,
iClk => hostif_clock,
iRst => hostif_reset,
oHostAddress => host_address,
oHostByteenable => host_byteenable,
oHostRead => host_Read,
iHostReaddata => host_readdata,
oHostWrite => host_write,
oHostWritedata => host_writedata,
iHostWaitrequest => host_waitrequest
);
-- Added for Xilinx Design for enabling tri-state IO Buffers
-- '1' for In '0' for Out
hostData_i <= iParHost_data_io;
oParHost_data_io <= hostData_o;
oParHost_data_io_tri <= not hostData_en;
-- Added for Xilinx Design for enabling tri-state IO Buffers
hostAddressData_i <= iParHost_addressData_io;
oParHost_addressData_io <= hostAddressData_o;
oParHost_addressData_tri <= not hostAddressData_en;
end generate genParallel;
end rtl;
| gpl-2.0 | 78b48b3e19bb6671a3c47f302bd95787 | 0.543726 | 4.72817 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | staging/fpga/boards/altera/SYSTEC_ECUcore-EP3C/design_nios2_directIO/niosII_openMac_clock_2.vhd | 8 | 29,264 | --Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
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--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity niosII_openMac_clock_2_edge_to_pulse is
port (
-- inputs:
signal clock : IN STD_LOGIC;
signal data_in : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal data_out : OUT STD_LOGIC
);
end entity niosII_openMac_clock_2_edge_to_pulse;
architecture europa of niosII_openMac_clock_2_edge_to_pulse is
signal data_in_d1 : STD_LOGIC;
begin
process (clock, reset_n)
begin
if reset_n = '0' then
data_in_d1 <= std_logic'('0');
elsif clock'event and clock = '1' then
data_in_d1 <= data_in;
end if;
end process;
data_out <= data_in XOR data_in_d1;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity niosII_openMac_clock_2_slave_FSM is
port (
-- inputs:
signal master_read_done_token : IN STD_LOGIC;
signal master_write_done_token : IN STD_LOGIC;
signal slave_clk : IN STD_LOGIC;
signal slave_read : IN STD_LOGIC;
signal slave_reset_n : IN STD_LOGIC;
signal slave_write : IN STD_LOGIC;
-- outputs:
signal slave_read_request : OUT STD_LOGIC;
signal slave_waitrequest : OUT STD_LOGIC;
signal slave_write_request : OUT STD_LOGIC
);
end entity niosII_openMac_clock_2_slave_FSM;
architecture europa of niosII_openMac_clock_2_slave_FSM is
signal internal_slave_read_request : STD_LOGIC;
signal internal_slave_write_request : STD_LOGIC;
signal next_slave_read_request : STD_LOGIC;
signal next_slave_state : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal next_slave_write_request : STD_LOGIC;
signal slave_state : STD_LOGIC_VECTOR (2 DOWNTO 0);
begin
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
internal_slave_read_request <= std_logic'('0');
elsif slave_clk'event and slave_clk = '1' then
if true then
internal_slave_read_request <= next_slave_read_request;
end if;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
internal_slave_write_request <= std_logic'('0');
elsif slave_clk'event and slave_clk = '1' then
if true then
internal_slave_write_request <= next_slave_write_request;
end if;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
slave_state <= std_logic_vector'("001");
elsif slave_clk'event and slave_clk = '1' then
if true then
slave_state <= next_slave_state;
end if;
end if;
end process;
process (internal_slave_read_request, internal_slave_write_request, master_read_done_token, master_write_done_token, slave_read, slave_state, slave_write)
begin
case slave_state is -- synthesis parallel_case
when std_logic_vector'("001") =>
--read request: go from IDLE state to READ_WAIT state
if std_logic'(slave_read) = '1' then
next_slave_state <= std_logic_vector'("010");
slave_waitrequest <= std_logic'('1');
next_slave_read_request <= NOT(internal_slave_read_request);
next_slave_write_request <= internal_slave_write_request;
elsif std_logic'(slave_write) = '1' then
next_slave_state <= std_logic_vector'("100");
slave_waitrequest <= std_logic'('1');
next_slave_read_request <= internal_slave_read_request;
next_slave_write_request <= NOT(internal_slave_write_request);
else
next_slave_state <= slave_state;
slave_waitrequest <= std_logic'('0');
next_slave_read_request <= internal_slave_read_request;
next_slave_write_request <= internal_slave_write_request;
end if;
-- when std_logic_vector'("001")
when std_logic_vector'("010") =>
--stay in READ_WAIT state until master passes read done token
if std_logic'(master_read_done_token) = '1' then
next_slave_state <= std_logic_vector'("001");
slave_waitrequest <= std_logic'('0');
else
next_slave_state <= std_logic_vector'("010");
slave_waitrequest <= std_logic'('1');
end if;
next_slave_read_request <= internal_slave_read_request;
next_slave_write_request <= internal_slave_write_request;
-- when std_logic_vector'("010")
when std_logic_vector'("100") =>
--stay in WRITE_WAIT state until master passes write done token
if std_logic'(master_write_done_token) = '1' then
next_slave_state <= std_logic_vector'("001");
slave_waitrequest <= std_logic'('0');
else
next_slave_state <= std_logic_vector'("100");
slave_waitrequest <= std_logic'('1');
end if;
next_slave_read_request <= internal_slave_read_request;
next_slave_write_request <= internal_slave_write_request;
-- when std_logic_vector'("100")
when others =>
next_slave_state <= std_logic_vector'("001");
slave_waitrequest <= std_logic'('0');
next_slave_read_request <= internal_slave_read_request;
next_slave_write_request <= internal_slave_write_request;
-- when others
end case; -- slave_state
end process;
--vhdl renameroo for output signals
slave_read_request <= internal_slave_read_request;
--vhdl renameroo for output signals
slave_write_request <= internal_slave_write_request;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity niosII_openMac_clock_2_master_FSM is
port (
-- inputs:
signal master_clk : IN STD_LOGIC;
signal master_reset_n : IN STD_LOGIC;
signal master_waitrequest : IN STD_LOGIC;
signal slave_read_request_token : IN STD_LOGIC;
signal slave_write_request_token : IN STD_LOGIC;
-- outputs:
signal master_read : OUT STD_LOGIC;
signal master_read_done : OUT STD_LOGIC;
signal master_write : OUT STD_LOGIC;
signal master_write_done : OUT STD_LOGIC
);
end entity niosII_openMac_clock_2_master_FSM;
architecture europa of niosII_openMac_clock_2_master_FSM is
signal internal_master_read1 : STD_LOGIC;
signal internal_master_read_done : STD_LOGIC;
signal internal_master_write1 : STD_LOGIC;
signal internal_master_write_done : STD_LOGIC;
signal master_state : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal next_master_read : STD_LOGIC;
signal next_master_read_done : STD_LOGIC;
signal next_master_state : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal next_master_write : STD_LOGIC;
signal next_master_write_done : STD_LOGIC;
begin
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
internal_master_read_done <= std_logic'('0');
elsif master_clk'event and master_clk = '1' then
if true then
internal_master_read_done <= next_master_read_done;
end if;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
internal_master_write_done <= std_logic'('0');
elsif master_clk'event and master_clk = '1' then
if true then
internal_master_write_done <= next_master_write_done;
end if;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
internal_master_read1 <= std_logic'('0');
elsif master_clk'event and master_clk = '1' then
if true then
internal_master_read1 <= next_master_read;
end if;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
internal_master_write1 <= std_logic'('0');
elsif master_clk'event and master_clk = '1' then
if true then
internal_master_write1 <= next_master_write;
end if;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
master_state <= std_logic_vector'("001");
elsif master_clk'event and master_clk = '1' then
if true then
master_state <= next_master_state;
end if;
end if;
end process;
process (internal_master_read1, internal_master_read_done, internal_master_write1, internal_master_write_done, master_state, master_waitrequest, slave_read_request_token, slave_write_request_token)
begin
case master_state is -- synthesis parallel_case
when std_logic_vector'("001") =>
--if read request token from slave then goto READ_WAIT state
if std_logic'(slave_read_request_token) = '1' then
next_master_state <= std_logic_vector'("010");
next_master_read <= std_logic'('1');
next_master_write <= std_logic'('0');
elsif std_logic'(slave_write_request_token) = '1' then
next_master_state <= std_logic_vector'("100");
next_master_read <= std_logic'('0');
next_master_write <= std_logic'('1');
else
next_master_state <= master_state;
next_master_read <= std_logic'('0');
next_master_write <= std_logic'('0');
end if;
next_master_read_done <= internal_master_read_done;
next_master_write_done <= internal_master_write_done;
-- when std_logic_vector'("001")
when std_logic_vector'("010") =>
--stay in READ_WAIT state until master wait is deasserted
if std_logic'(NOT(master_waitrequest)) = '1' then
next_master_state <= std_logic_vector'("001");
next_master_read_done <= NOT(internal_master_read_done);
next_master_read <= std_logic'('0');
else
next_master_state <= std_logic_vector'("010");
next_master_read_done <= internal_master_read_done;
next_master_read <= internal_master_read1;
end if;
next_master_write_done <= internal_master_write_done;
next_master_write <= std_logic'('0');
-- when std_logic_vector'("010")
when std_logic_vector'("100") =>
--stay in WRITE_WAIT state until slave wait is deasserted
if std_logic'(NOT(master_waitrequest)) = '1' then
next_master_state <= std_logic_vector'("001");
next_master_write <= std_logic'('0');
next_master_write_done <= NOT(internal_master_write_done);
else
next_master_state <= std_logic_vector'("100");
next_master_write <= internal_master_write1;
next_master_write_done <= internal_master_write_done;
end if;
next_master_read_done <= internal_master_read_done;
next_master_read <= std_logic'('0');
-- when std_logic_vector'("100")
when others =>
next_master_state <= std_logic_vector'("001");
next_master_write <= std_logic'('0');
next_master_write_done <= internal_master_write_done;
next_master_read <= std_logic'('0');
next_master_read_done <= internal_master_read_done;
-- when others
end case; -- master_state
end process;
--vhdl renameroo for output signals
master_read <= internal_master_read1;
--vhdl renameroo for output signals
master_read_done <= internal_master_read_done;
--vhdl renameroo for output signals
master_write <= internal_master_write1;
--vhdl renameroo for output signals
master_write_done <= internal_master_write_done;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity niosII_openMac_clock_2_bit_pipe is
port (
-- inputs:
signal clk1 : IN STD_LOGIC;
signal clk2 : IN STD_LOGIC;
signal data_in : IN STD_LOGIC;
signal reset_clk1_n : IN STD_LOGIC;
signal reset_clk2_n : IN STD_LOGIC;
-- outputs:
signal data_out : OUT STD_LOGIC
);
end entity niosII_openMac_clock_2_bit_pipe;
architecture europa of niosII_openMac_clock_2_bit_pipe is
signal data_in_d1 : STD_LOGIC;
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of data_in_d1 : signal is "{-to ""*""} CUT=ON ; PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of data_out : signal is "PRESERVE_REGISTER=ON";
begin
process (clk1, reset_clk1_n)
begin
if reset_clk1_n = '0' then
data_in_d1 <= std_logic'('0');
elsif clk1'event and clk1 = '1' then
data_in_d1 <= data_in;
end if;
end process;
process (clk2, reset_clk2_n)
begin
if reset_clk2_n = '0' then
data_out <= std_logic'('0');
elsif clk2'event and clk2 = '1' then
data_out <= data_in_d1;
end if;
end process;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--Clock Domain Crossing AdapterniosII_openMac_clock_2
entity niosII_openMac_clock_2 is
port (
-- inputs:
signal master_clk : IN STD_LOGIC;
signal master_endofpacket : IN STD_LOGIC;
signal master_readdata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal master_reset_n : IN STD_LOGIC;
signal master_waitrequest : IN STD_LOGIC;
signal slave_address : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal slave_byteenable : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal slave_clk : IN STD_LOGIC;
signal slave_nativeaddress : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal slave_read : IN STD_LOGIC;
signal slave_reset_n : IN STD_LOGIC;
signal slave_write : IN STD_LOGIC;
signal slave_writedata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-- outputs:
signal master_address : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal master_byteenable : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal master_nativeaddress : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
signal master_read : OUT STD_LOGIC;
signal master_write : OUT STD_LOGIC;
signal master_writedata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal slave_endofpacket : OUT STD_LOGIC;
signal slave_readdata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal slave_waitrequest : OUT STD_LOGIC
);
end entity niosII_openMac_clock_2;
architecture europa of niosII_openMac_clock_2 is
component altera_std_synchronizer is
GENERIC (
depth : NATURAL
);
PORT (
signal dout : OUT STD_LOGIC;
signal clk : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal din : IN STD_LOGIC
);
end component altera_std_synchronizer;
component niosII_openMac_clock_2_edge_to_pulse is
port (
-- inputs:
signal clock : IN STD_LOGIC;
signal data_in : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal data_out : OUT STD_LOGIC
);
end component niosII_openMac_clock_2_edge_to_pulse;
component niosII_openMac_clock_2_slave_FSM is
port (
-- inputs:
signal master_read_done_token : IN STD_LOGIC;
signal master_write_done_token : IN STD_LOGIC;
signal slave_clk : IN STD_LOGIC;
signal slave_read : IN STD_LOGIC;
signal slave_reset_n : IN STD_LOGIC;
signal slave_write : IN STD_LOGIC;
-- outputs:
signal slave_read_request : OUT STD_LOGIC;
signal slave_waitrequest : OUT STD_LOGIC;
signal slave_write_request : OUT STD_LOGIC
);
end component niosII_openMac_clock_2_slave_FSM;
component niosII_openMac_clock_2_master_FSM is
port (
-- inputs:
signal master_clk : IN STD_LOGIC;
signal master_reset_n : IN STD_LOGIC;
signal master_waitrequest : IN STD_LOGIC;
signal slave_read_request_token : IN STD_LOGIC;
signal slave_write_request_token : IN STD_LOGIC;
-- outputs:
signal master_read : OUT STD_LOGIC;
signal master_read_done : OUT STD_LOGIC;
signal master_write : OUT STD_LOGIC;
signal master_write_done : OUT STD_LOGIC
);
end component niosII_openMac_clock_2_master_FSM;
component niosII_openMac_clock_2_bit_pipe is
port (
-- inputs:
signal clk1 : IN STD_LOGIC;
signal clk2 : IN STD_LOGIC;
signal data_in : IN STD_LOGIC;
signal reset_clk1_n : IN STD_LOGIC;
signal reset_clk2_n : IN STD_LOGIC;
-- outputs:
signal data_out : OUT STD_LOGIC
);
end component niosII_openMac_clock_2_bit_pipe;
signal internal_master_read : STD_LOGIC;
signal internal_master_write : STD_LOGIC;
signal internal_slave_endofpacket : STD_LOGIC;
signal internal_slave_waitrequest : STD_LOGIC;
signal master_read_done : STD_LOGIC;
signal master_read_done_sync : STD_LOGIC;
signal master_read_done_token : STD_LOGIC;
signal master_write_done : STD_LOGIC;
signal master_write_done_sync : STD_LOGIC;
signal master_write_done_token : STD_LOGIC;
signal slave_address_d1 : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal slave_byteenable_d1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal slave_nativeaddress_d1 : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal slave_read_request : STD_LOGIC;
signal slave_read_request_sync : STD_LOGIC;
signal slave_read_request_token : STD_LOGIC;
signal slave_readdata_p1 : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal slave_write_request : STD_LOGIC;
signal slave_write_request_sync : STD_LOGIC;
signal slave_write_request_token : STD_LOGIC;
signal slave_writedata_d1 : STD_LOGIC_VECTOR (15 DOWNTO 0);
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of master_address : signal is "PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of master_byteenable : signal is "PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of master_nativeaddress : signal is "PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of master_writedata : signal is "PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of slave_address_d1 : signal is "{-to ""*""} CUT=ON ; PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of slave_byteenable_d1 : signal is "{-to ""*""} CUT=ON ; PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of slave_nativeaddress_d1 : signal is "{-to ""*""} CUT=ON ; PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of slave_readdata : signal is "{-from ""*""} CUT=ON";
attribute ALTERA_ATTRIBUTE of slave_writedata_d1 : signal is "{-to ""*""} CUT=ON ; PRESERVE_REGISTER=ON";
begin
--in, which is an e_avalon_slave
--out, which is an e_avalon_master
the_altera_std_synchronizer : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => slave_clk,
din => master_read_done,
dout => master_read_done_sync,
reset_n => slave_reset_n
);
the_altera_std_synchronizer1 : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => slave_clk,
din => master_write_done,
dout => master_write_done_sync,
reset_n => slave_reset_n
);
--read_done_edge_to_pulse, which is an e_instance
read_done_edge_to_pulse : niosII_openMac_clock_2_edge_to_pulse
port map(
data_out => master_read_done_token,
clock => slave_clk,
data_in => master_read_done_sync,
reset_n => slave_reset_n
);
--write_done_edge_to_pulse, which is an e_instance
write_done_edge_to_pulse : niosII_openMac_clock_2_edge_to_pulse
port map(
data_out => master_write_done_token,
clock => slave_clk,
data_in => master_write_done_sync,
reset_n => slave_reset_n
);
--slave_FSM, which is an e_instance
slave_FSM : niosII_openMac_clock_2_slave_FSM
port map(
slave_read_request => slave_read_request,
slave_waitrequest => internal_slave_waitrequest,
slave_write_request => slave_write_request,
master_read_done_token => master_read_done_token,
master_write_done_token => master_write_done_token,
slave_clk => slave_clk,
slave_read => slave_read,
slave_reset_n => slave_reset_n,
slave_write => slave_write
);
the_altera_std_synchronizer2 : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => master_clk,
din => slave_read_request,
dout => slave_read_request_sync,
reset_n => master_reset_n
);
the_altera_std_synchronizer3 : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => master_clk,
din => slave_write_request,
dout => slave_write_request_sync,
reset_n => master_reset_n
);
--read_request_edge_to_pulse, which is an e_instance
read_request_edge_to_pulse : niosII_openMac_clock_2_edge_to_pulse
port map(
data_out => slave_read_request_token,
clock => master_clk,
data_in => slave_read_request_sync,
reset_n => master_reset_n
);
--write_request_edge_to_pulse, which is an e_instance
write_request_edge_to_pulse : niosII_openMac_clock_2_edge_to_pulse
port map(
data_out => slave_write_request_token,
clock => master_clk,
data_in => slave_write_request_sync,
reset_n => master_reset_n
);
--master_FSM, which is an e_instance
master_FSM : niosII_openMac_clock_2_master_FSM
port map(
master_read => internal_master_read,
master_read_done => master_read_done,
master_write => internal_master_write,
master_write_done => master_write_done,
master_clk => master_clk,
master_reset_n => master_reset_n,
master_waitrequest => master_waitrequest,
slave_read_request_token => slave_read_request_token,
slave_write_request_token => slave_write_request_token
);
--endofpacket_bit_pipe, which is an e_instance
endofpacket_bit_pipe : niosII_openMac_clock_2_bit_pipe
port map(
data_out => internal_slave_endofpacket,
clk1 => slave_clk,
clk2 => master_clk,
data_in => master_endofpacket,
reset_clk1_n => slave_reset_n,
reset_clk2_n => master_reset_n
);
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
slave_readdata_p1 <= std_logic_vector'("0000000000000000");
elsif master_clk'event and master_clk = '1' then
if std_logic'((internal_master_read AND NOT master_waitrequest)) = '1' then
slave_readdata_p1 <= master_readdata;
end if;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
slave_readdata <= std_logic_vector'("0000000000000000");
elsif slave_clk'event and slave_clk = '1' then
slave_readdata <= slave_readdata_p1;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
slave_writedata_d1 <= std_logic_vector'("0000000000000000");
elsif slave_clk'event and slave_clk = '1' then
slave_writedata_d1 <= slave_writedata;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
master_writedata <= std_logic_vector'("0000000000000000");
elsif master_clk'event and master_clk = '1' then
master_writedata <= slave_writedata_d1;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
slave_address_d1 <= std_logic_vector'("0000");
elsif slave_clk'event and slave_clk = '1' then
slave_address_d1 <= slave_address;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
master_address <= std_logic_vector'("0000");
elsif master_clk'event and master_clk = '1' then
master_address <= slave_address_d1;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
slave_nativeaddress_d1 <= std_logic_vector'("000");
elsif slave_clk'event and slave_clk = '1' then
slave_nativeaddress_d1 <= slave_nativeaddress;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
master_nativeaddress <= std_logic_vector'("000");
elsif master_clk'event and master_clk = '1' then
master_nativeaddress <= slave_nativeaddress_d1;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
slave_byteenable_d1 <= std_logic_vector'("00");
elsif slave_clk'event and slave_clk = '1' then
slave_byteenable_d1 <= slave_byteenable;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
master_byteenable <= std_logic_vector'("00");
elsif master_clk'event and master_clk = '1' then
master_byteenable <= slave_byteenable_d1;
end if;
end process;
--vhdl renameroo for output signals
master_read <= internal_master_read;
--vhdl renameroo for output signals
master_write <= internal_master_write;
--vhdl renameroo for output signals
slave_endofpacket <= internal_slave_endofpacket;
--vhdl renameroo for output signals
slave_waitrequest <= internal_slave_waitrequest;
end europa;
| gpl-2.0 | 0b8ad9b742208ab7d35eea7490f68092 | 0.596432 | 3.919111 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/parallelinterface/src/prlSlave-rtl-ea.vhd | 3 | 12,810 | -------------------------------------------------------------------------------
--! @file prlSlave-rtl-ea.vhd
--! @brief Multiplexed memory mapped slave
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--! Use standard ieee library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Use numeric std
use ieee.numeric_std.all;
--! Use libcommon library
library libcommon;
--! Use global package
use libcommon.global.all;
entity prlSlave is
generic (
--! Enable multiplexed address/data-bus mode (0 = FALSE)
gEnableMux : natural := 0;
--! Data bus width
gDataWidth : natural := 16;
--! Address bus width
gAddrWidth : natural := 16;
--! Ad bus width (valid when gEnableMux /= FALSE)
gAdWidth : natural := 16
);
port (
--! Clock
iClk : in std_logic;
--! Reset
iRst : in std_logic;
-- Memory mapped multiplexed slave
--! Chipselect
iPrlSlv_cs : in std_logic;
--! Read strobe
iPrlSlv_rd : in std_logic;
--! Write strobe
iPrlSlv_wr : in std_logic;
--! Address Latch enable (Multiplexed only)
iPrlSlv_ale : in std_logic;
--! High active Acknowledge
oPrlSlv_ack : out std_logic;
--! Byteenables
iPrlSlv_be : in std_logic_vector(gDataWidth/8-1 downto 0);
-- Multiplexed AD-bus
--! Address/Data bus out
oPrlSlv_ad_o : out std_logic_vector(gAdWidth-1 downto 0);
--! Address/Data bus in
iPrlSlv_ad_i : in std_logic_vector(gAdWidth-1 downto 0);
--! Address/Data bus outenable
oPrlSlv_ad_oen : out std_logic;
-- Demultiplexed AD-bus
--! Address bus
iPrlSlv_addr : in std_logic_vector(gAddrWidth-1 downto 0);
--! Data bus in
iPrlSlv_data_i : in std_logic_vector(gDataWidth-1 downto 0);
--! Data bus out
oPrlSlv_data_o : out std_logic_vector(gDataWidth-1 downto 0);
--! Data bus outenable
oPrlSlv_data_oen : out std_logic;
-- Memory Mapped master
--! MM slave host address
oMst_address : out std_logic_vector(gAddrWidth-1 downto 0);
--! MM slave host byteenable
oMst_byteenable : out std_logic_vector(gDataWidth/8-1 downto 0);
--! MM slave host read
oMst_read : out std_logic;
--! MM slave host readdata
iMst_readdata : in std_logic_vector(gDataWidth-1 downto 0);
--! MM slave host write
oMst_write : out std_logic;
--! MM slave host writedata
oMst_writedata : out std_logic_vector(gDataWidth-1 downto 0);
--! MM slave host waitrequest
iMst_waitrequest : in std_logic
);
end prlSlave;
architecture rtl of prlSlave is
-- address register to store the address populated to the interface
signal addressRegister : std_logic_vector(gAddrWidth-1 downto 0);
-- byteenable register to store byteenable qualifiers
signal byteenableRegister : std_logic_vector(gDataWidth/8-1 downto 0);
-- register clock enable
signal byteenableRegClkEnable : std_logic;
-- write data register to store the data populated to the interface
signal writeDataRegister : std_logic_vector(gDataWidth-1 downto 0);
-- register clock enable
signal writeDataRegClkEnable : std_logic;
-- read data register to store the read data populated to the host
signal readDataRegister : std_logic_vector(gDataWidth-1 downto 0);
signal readDataRegister_next : std_logic_vector(gDataWidth-1 downto 0);
-- synchronized signals
signal hostChipselect : std_logic;
signal hostWrite : std_logic;
signal hostWrite_noCs : std_logic;
signal hostRead : std_logic;
signal hostRead_noCs : std_logic;
signal hostDataEnable : std_logic;
signal hostDataEnable_reg : std_logic;
signal hostAck : std_logic;
signal hostAck_reg : std_logic;
-- fsm
type tFsm is (
sIdle,
sStart,
sWaitForBus,
sHold
);
signal fsm : tFsm;
-- Latch type
type tLatch is record
clear : std_logic;
enable : std_logic;
data : std_logic_vector(gAddrWidth-1 downto 0);
output : std_logic_vector(gAddrWidth-1 downto 0);
end record;
signal inst_latch : tLatch;
begin
--! The processes describe the register, which stores the unsynchronized
--! inputs!
reg : process(iRst, iClk)
begin
if iRst = cActivated then
addressRegister <= (others => cInactivated);
byteenableRegister <= (others => cInactivated);
writeDataRegister <= (others => cInactivated);
readDataRegister <= (others => cInactivated);
hostDataEnable_reg <= cInactivated;
hostAck_reg <= cInactivated;
elsif rising_edge(iClk) then
hostDataEnable_reg <= hostDataEnable;
hostAck_reg <= hostAck;
if byteenableRegClkEnable = cActivated then
byteenableRegister <= iPrlSlv_be;
-- Assign byte addresses to the address register
if gEnableMux /= 0 then
addressRegister <= (others => cInactivated);
addressRegister <= inst_latch.output;
else
addressRegister <= iPrlSlv_addr;
end if;
end if;
if writeDataRegClkEnable = cActivated then
if gEnableMux /= 0 then
writeDataRegister <= iPrlSlv_ad_i(writeDataRegister'range);
else
writeDataRegister <= iPrlSlv_data_i;
end if;
end if;
if iMst_waitrequest = cInactivated and hostRead = cActivated then
readDataRegister <= readDataRegister_next;
end if;
end if;
end process;
oMst_address <= addressRegister;
-- Multiplexed output
oPrlSlv_ad_oen <= hostDataEnable_reg;
oPrlSlv_ack <= hostAck_reg;
-- Demultiplexed output
oPrlSlv_data_oen <= hostDataEnable_reg;
assignReaddata : process(readDataRegister)
begin
-- default assign zeros
oPrlSlv_ad_o <= (others => cInactivated);
oPrlSlv_data_o <= (others => cInactivated);
oPrlSlv_ad_o(readDataRegister'range) <= readDataRegister;
oPrlSlv_data_o(readDataRegister'range) <= readDataRegister;
end process assignReaddata;
--! combinatoric process for ack and output enable generation
combProc : process (
hostWrite,
hostRead,
fsm
)
begin
-- default assignments to avoid unwanted latches
hostAck <= cInactivated;
hostDataEnable <= cInactivated;
if fsm = sHold then
if hostRead = cActivated then
hostDataEnable <= cActivated;
hostAck <= cActivated;
elsif hostWrite = cActivated then
hostAck <= cActivated;
end if;
end if;
end process;
--! Fsm to control access and timeout counter
fsmProc : process(iRst, iClk)
begin
if iRst = cActivated then
fsm <= sIdle;
byteenableRegClkEnable <= cInactivated;
writeDataRegClkEnable <= cInactivated;
oMst_write <= cInactivated;
oMst_read <= cInactivated;
elsif rising_edge(iClk) then
--defaults
byteenableRegClkEnable <= cInactivated;
writeDataRegClkEnable <= cInactivated;
case fsm is
when sIdle =>
oMst_write <= cInactivated;
oMst_read <= cInactivated;
if hostRead = cActivated or hostWrite = cActivated then
fsm <= sStart;
byteenableRegClkEnable <= cActivated;
writeDataRegClkEnable <= hostWrite;
end if;
when sStart =>
fsm <= sWaitForBus;
oMst_read <= hostRead;
oMst_write <= hostWrite;
when sWaitForBus =>
if iMst_waitrequest = cInactivated then
fsm <= sHold;
oMst_read <= cInactivated;
oMst_write <= cInactivated;
end if;
when sHold =>
if hostRead = cInactivated and hostWrite = cInactivated then
fsm <= sIdle;
end if;
end case;
end if;
end process;
oMst_byteenable <= byteenableRegister;
oMst_writedata <= writeDataRegister;
readDataRegister_next <= iMst_readdata;
muxLatch : if gEnableMux /= 0 generate
-- Address latch
addrLatch : entity work.dataLatch
generic map (
gDataWidth => inst_latch.data'length
)
port map (
iClear => inst_latch.clear,
iEnable => inst_latch.enable,
iData => inst_latch.data,
oData => inst_latch.output
);
inst_latch.clear <= cInactivated;
inst_latch.enable <= iPrlSlv_ale;
inst_latch.data <= iPrlSlv_ad_i(inst_latch.data'range);
end generate muxLatch;
-- synchronize all available control signals
syncChipselect : entity libcommon.synchronizer
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iArst => iRst,
iClk => iClk,
iAsync => iPrlSlv_cs,
oSync => hostChipselect
);
syncWrite : entity libcommon.synchronizer
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iArst => iRst,
iClk => iClk,
iAsync => iPrlSlv_wr,
oSync => hostWrite_noCs
);
hostWrite <= hostChipselect and hostWrite_noCs;
syncRead : entity libcommon.synchronizer
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iArst => iRst,
iClk => iClk,
iAsync => iPrlSlv_rd,
oSync => hostRead_noCs
);
hostRead <= hostChipselect and hostRead_noCs;
end rtl;
| gpl-2.0 | 967dd571f09139fb0ee5ed923426ae6a | 0.548868 | 5.119904 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/openmac/src/dma_handler.vhd | 3 | 8,221 | -------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dma_handler is
generic(
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
dma_highadr_g : integer := 31;
tx_fifo_word_size_log2_g : natural := 5;
rx_fifo_word_size_log2_g : natural := 5;
gen_dma_observer_g : boolean := true
);
port(
dma_clk : in std_logic;
rst : in std_logic;
mac_tx_off : in std_logic;
mac_rx_off : in std_logic;
dma_req_wr : in std_logic;
dma_req_rd : in std_logic;
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_ack_wr : out std_logic;
dma_ack_rd : out std_logic;
dma_rd_len : in std_logic_vector(11 downto 0);
tx_rd_clk : in std_logic;
tx_rd_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
tx_rd_empty : in std_logic;
tx_rd_full : in std_logic;
tx_rd_req : out std_logic;
rx_wr_full : in std_logic;
rx_wr_empty : in std_logic;
rx_wr_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
rx_wr_req : out std_logic;
rx_aclr : out std_logic;
rx_wr_clk : in std_logic;
dma_addr_out : out std_logic_vector(dma_highadr_g downto 1);
dma_rd_len_out : out std_logic_vector(11 downto 0);
dma_new_addr_wr : out std_logic;
dma_new_addr_rd : out std_logic;
dma_new_len : out std_logic;
dma_req_overflow : in std_logic;
dma_rd_err : out std_logic;
dma_wr_err : out std_logic
);
end dma_handler;
architecture dma_handler of dma_handler is
--clock signal
signal clk : std_logic;
--fsm
type transfer_t is (idle, first, run);
signal tx_fsm, tx_fsm_next, rx_fsm, rx_fsm_next : transfer_t := idle;
--dma signals
signal dma_ack_rd_s, dma_ack_wr_s : std_logic;
--dma observer
signal observ_rd_err, observ_wr_err : std_logic;
signal observ_rd_err_next, observ_wr_err_next : std_logic;
begin
--dma_clk, tx_rd_clk and rx_wr_clk are the same!
clk <= dma_clk; --to ease typing
rx_aclr <= rst;
process(clk, rst)
begin
if rst = '1' then
if gen_tx_fifo_g then
tx_fsm <= idle;
if gen_dma_observer_g then
observ_rd_err <= '0';
end if;
end if;
if gen_rx_fifo_g then
rx_fsm <= idle;
if gen_dma_observer_g then
observ_wr_err <= '0';
end if;
end if;
elsif clk = '1' and clk'event then
if gen_tx_fifo_g then
tx_fsm <= tx_fsm_next;
if gen_dma_observer_g then
observ_rd_err <= observ_rd_err_next;
end if;
end if;
if gen_rx_fifo_g then
rx_fsm <= rx_fsm_next;
if gen_dma_observer_g then
observ_wr_err <= observ_wr_err_next;
end if;
end if;
end if;
end process;
dma_rd_len_out <= dma_rd_len; --register in openMAC.vhd!
tx_fsm_next <= idle when gen_tx_fifo_g = false else --hang here if generic disables tx handling
first when tx_fsm = idle and dma_req_rd = '1' else
run when tx_fsm = first and dma_ack_rd_s = '1' else
idle when mac_tx_off = '1' else
tx_fsm;
rx_fsm_next <= idle when gen_rx_fifo_g = false else --hang here if generic disables rx handling
first when rx_fsm = idle and dma_req_wr = '1' else
run when rx_fsm = first else
idle when mac_rx_off = '1' else
rx_fsm;
genDmaObserver : if gen_dma_observer_g generate
begin
observ_rd_err_next <= --monoflop (deassertion with rst only)
'0' when gen_tx_fifo_g = false else
'1' when dma_req_rd = '1' and dma_ack_rd_s = '0' and dma_req_overflow = '1' else
observ_rd_err;
observ_wr_err_next <= --monoflop (deassertion with rst only)
'0' when gen_rx_fifo_g = false else
'1' when dma_req_wr = '1' and dma_ack_wr_s = '0' and dma_req_overflow = '1' else
observ_wr_err;
end generate;
dma_rd_err <= observ_rd_err;
dma_wr_err <= observ_wr_err;
--acknowledge dma request (regular or overflow)
dma_ack_rd <= dma_req_rd and (dma_ack_rd_s or dma_req_overflow);
dma_ack_wr <= dma_req_wr and (dma_ack_wr_s or dma_req_overflow);
dma_new_addr_wr <= '1' when rx_fsm = first else '0';
dma_new_addr_rd <= '1' when tx_fsm = first else '0';
dma_new_len <= '1' when tx_fsm = first else '0';
process(clk, rst)
begin
if rst = '1' then
dma_addr_out <= (others => '0');
if gen_tx_fifo_g then
tx_rd_req <= '0';
dma_ack_rd_s <= '0';
end if;
if gen_rx_fifo_g then
rx_wr_req <= '0';
dma_ack_wr_s <= '0';
end if;
elsif clk = '1' and clk'event then
--if the very first address is available, store it over the whole transfer
if tx_fsm = first or rx_fsm = first then
dma_addr_out <= dma_addr;
end if;
if gen_tx_fifo_g then
tx_rd_req <= '0';
dma_ack_rd_s <= '0';
--dma request, TX fifo is not empty and not yet ack'd
if dma_req_rd = '1' and tx_rd_empty = '0' and dma_ack_rd_s = '0' then
tx_rd_req <= '1'; --read from TX fifo
dma_ack_rd_s <= '1'; --ack the read request
end if;
end if;
if gen_rx_fifo_g then
rx_wr_req <= '0';
dma_ack_wr_s <= '0';
--dma request, RX fifo is not full and not yet ack'd
if dma_req_wr = '1' and rx_wr_full = '0' and dma_ack_wr_s = '0' then
rx_wr_req <= '1'; --write to RX fifo
dma_ack_wr_s <= '1'; --ack the read request
end if;
end if;
end if;
end process;
end dma_handler;
| gpl-2.0 | fa74d3e22600e51e41bcea0a76837084 | 0.53935 | 3.618398 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/openmac/src/master_handler.vhd | 3 | 16,722 | -------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity master_handler is
generic(
dma_highadr_g : integer := 31;
gen_tx_fifo_g : boolean := true;
tx_fifo_word_size_log2_g : natural := 5;
gen_rx_fifo_g : boolean := true;
rx_fifo_word_size_log2_g : natural := 5;
m_burstcount_width_g : integer := 4;
m_rx_burst_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
m_burst_wr_const_g : boolean := true;
fifo_data_width_g : integer := 16
);
port(
m_clk : in std_logic;
rst : in std_logic;
mac_tx_off : in std_logic;
mac_rx_off : in std_logic;
tx_wr_clk : in std_logic;
tx_wr_empty : in std_logic;
tx_wr_full : in std_logic;
rx_rd_clk : in std_logic;
rx_rd_empty : in std_logic;
rx_rd_full : in std_logic;
tx_wr_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
rx_rd_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
tx_aclr : out std_logic;
tx_wr_req : out std_logic;
rx_rd_req : out std_logic;
m_waitrequest : in std_logic;
m_readdatavalid : in std_logic;
m_write : out std_logic;
m_read : out std_logic;
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
dma_addr_in : in std_logic_vector(dma_highadr_g downto 1);
dma_len_rd : in std_logic_vector(11 downto 0);
dma_new_addr_wr : in std_logic;
dma_new_addr_rd : in std_logic;
dma_new_len_rd : in std_logic
);
end master_handler;
architecture master_handler of master_handler is
--clock signal
signal clk : std_logic;
--constants
constant tx_burst_size_c : integer := m_tx_burst_size_g; --(2**(m_burstcount_width_g-1));
constant rx_burst_size_c : integer := m_rx_burst_size_g; --(2**(m_burstcount_width_g-1));
---used to trigger rx/tx data transfers depending on fill level and burst size
constant tx_fifo_limit_c : integer := 2**tx_fifo_word_size_log2_g - tx_burst_size_c - 1; --fifo_size - burst size - 1
constant rx_fifo_limit_c : integer := rx_burst_size_c + 1; --burst size
--fsm
type transfer_t is (idle, run, finish);
signal tx_fsm, tx_fsm_next, rx_fsm, rx_fsm_next : transfer_t := idle;
--transfer signals
signal m_burstcount_s, m_burstcount_latch : std_logic_vector(m_burstcount'range);
signal m_address_latch : std_logic_vector(m_address'range);
signal m_write_s, m_read_s : std_logic;
signal rx_first_read_done, rx_rd_done : std_logic;
--fifo signals
signal arst : std_logic;
signal tx_fifo_limit, rx_fifo_limit : std_logic;
signal tx_wr_req_s, rx_rd_req_s, rx_first_rd_req : std_logic;
--generate addresses
signal tx_cnt, tx_cnt_next : std_logic_vector(m_address'range);
signal rx_cnt, rx_cnt_next : std_logic_vector(m_address'range);
--handle tx read transfer
signal tx_rd_cnt, tx_rd_cnt_next : std_logic_vector(dma_len_rd'range);
signal dma_len_rd_s : std_logic_vector(dma_len_rd'range);
begin
--m_clk, rx_rd_clk and tx_wr_clk are the same!
clk <= m_clk; --to ease typing
tx_aclr <= rst or arst;
--fifo limit is set to '1' if the fill level is equal/above the limit
tx_fifo_limit <= '1' when tx_wr_usedw >= conv_std_logic_vector(tx_fifo_limit_c, tx_wr_usedw'length) else '0';
rx_fifo_limit <= '1' when rx_rd_usedw >= conv_std_logic_vector(rx_fifo_limit_c, rx_rd_usedw'length) else '0';
process(clk, rst)
begin
if rst = '1' then
if gen_rx_fifo_g then
rx_fsm <= idle;
end if;
if gen_tx_fifo_g then
tx_fsm <= idle;
end if;
elsif clk = '1' and clk'event then
if gen_rx_fifo_g then
rx_fsm <= rx_fsm_next;
end if;
if gen_tx_fifo_g then
tx_fsm <= tx_fsm_next;
end if;
end if;
end process;
tx_fsm_next <= run when tx_fsm = idle and dma_new_addr_rd = '1' else
finish when tx_fsm = run and mac_tx_off = '1' else
idle when tx_fsm = finish and tx_wr_empty = '1' else --stay finish as long as tx fifo is filled
tx_fsm;
rx_fsm_next <= run when rx_fsm = idle and dma_new_addr_wr = '1' else
finish when rx_fsm = run and mac_rx_off = '1' else
idle when rx_fsm = finish and rx_rd_done = '1' else --stay finish as long the transfer process is not done
rx_fsm;
m_burstcount <= m_burstcount_latch when m_write_s = '1' and m_burst_wr_const_g else m_burstcount_s;
m_burstcounter <= m_burstcount_s; --output current burst counter value
m_write <= m_write_s;
m_read <= m_read_s;
--generate address
m_address <= m_address_latch when m_write_s = '1' and m_burst_wr_const_g else
rx_cnt when m_write_s = '1' and not m_burst_wr_const_g else
tx_cnt;
process(clk, rst)
begin
if rst = '1' then
if gen_tx_fifo_g then
tx_cnt <= (others => '0');
tx_rd_cnt <= (others => '0');
end if;
if gen_rx_fifo_g then
rx_cnt <= (others => '0');
end if;
elsif clk = '1' and clk'event then
if gen_tx_fifo_g then
tx_cnt <= tx_cnt_next;
tx_rd_cnt <= tx_rd_cnt_next;
end if;
if gen_rx_fifo_g then
rx_cnt <= rx_cnt_next;
end if;
end if;
end process;
dma_len_rd_s <= dma_len_rd + 1 when fifo_data_width_g = 16 else
dma_len_rd + 3 when fifo_data_width_g = 32 else
dma_len_rd;
tx_rd_cnt_next <= (others => '0') when gen_tx_fifo_g = false else
'0' & dma_len_rd_s(dma_len_rd_s'left downto 1) when dma_new_len_rd = '1' and fifo_data_width_g = 16 else
"00" & dma_len_rd_s(dma_len_rd_s'left downto 2) when dma_new_len_rd = '1' and fifo_data_width_g = 32 else
tx_rd_cnt - 1 when tx_wr_req_s = '1' and tx_rd_cnt /= 0 else
tx_rd_cnt;
tx_cnt_next <= (others => '0') when gen_tx_fifo_g = false else
tx_cnt + fifo_data_width_g/8 when tx_wr_req_s = '1' else
dma_addr_in & '0' when dma_new_addr_rd = '1' else
tx_cnt;
rx_cnt_next <= (others => '0') when gen_rx_fifo_g = false else
rx_cnt + fifo_data_width_g/8 when rx_rd_req_s = '1' else
dma_addr_in & '0' when dma_new_addr_wr = '1' else
rx_cnt;
m_byteenable <= (others => '1');
tx_wr_req_s <= m_readdatavalid;
tx_wr_req <= tx_wr_req_s;
rx_rd_req_s <= m_write_s and not m_waitrequest;
rx_rd_req <= rx_rd_req_s or rx_first_rd_req;
process(clk, rst)
--arbitration of rx and tx requests is done by process variable (tx overrules rx)
variable tx_is_the_owner_v : std_logic;
begin
if rst = '1' then
tx_is_the_owner_v := '0';
if gen_tx_fifo_g then
arst <= '0';
m_read_s <= '0';
end if;
if gen_rx_fifo_g then
rx_first_rd_req <= '0';
m_write_s <= '0';
rx_first_read_done <= '0';
rx_rd_done <= '0';
end if;
m_burstcount_s <= (others => '0');
if m_burst_wr_const_g then
m_burstcount_latch <= (others => '0');
m_address_latch <= (others => '0');
end if;
elsif clk = '1' and clk'event then
if gen_tx_fifo_g then
arst <= '0';
if m_readdatavalid = '1' then
--read was successful -> write to tx fifo
m_burstcount_s <= m_burstcount_s - 1;
end if;
case tx_fsm is
when idle =>
--no transfer in progress
when run =>
--read transfer base address is ready
if tx_fifo_limit = '0' and m_read_s = '0' and m_write_s = '0' and m_burstcount_s = 0 and tx_rd_cnt /= 0 then
--tx fifo is below defined limit -> there is place for at least one burst!
m_read_s <= '1';
if tx_rd_cnt > conv_std_logic_vector(tx_burst_size_c, tx_rd_cnt'length) then
m_burstcount_s <= conv_std_logic_vector(tx_burst_size_c, m_burstcount_s'length);
else
m_burstcount_s <= EXT(tx_rd_cnt, m_burstcount_s'length);
end if;
--a tx transfer is necessary and overrules necessary rx transfers...
tx_is_the_owner_v := '1';
elsif m_read_s = '1' and m_waitrequest = '0' then
--request is confirmed -> deassert request
m_read_s <= '0';
--so, we are done with tx requesting
tx_is_the_owner_v := '0';
end if;
when finish =>
--transfer done, MAC has its data...
---is there still a request?
if m_read_s = '1' and m_waitrequest = '0' then
--last request confirmed -> deassert request
m_read_s <= '0'; tx_is_the_owner_v := '0';
---is the burst transfer done?
elsif m_read_s = '0' and m_burstcount_s = 0 then
--burst transfer done, clear fifo
arst <= '1';
end if;
end case;
end if;
if gen_rx_fifo_g then
rx_first_rd_req <= '0';
rx_rd_done <= '0';
if m_write_s = '1' and m_waitrequest = '0' then
--write was successful
m_burstcount_s <= m_burstcount_s - 1;
end if;
case rx_fsm is
when idle =>
--no transfer in progress
rx_first_read_done <= '0';
when run =>
--a not empty fifo has to be read once, to get the very first pattern
if rx_first_read_done = '0' and rx_rd_empty = '0' then
rx_first_read_done <= '1';
rx_first_rd_req <= '1';
end if;
--write transfer base address is ready
if rx_fifo_limit = '1' and m_read_s = '0' and m_write_s = '0' and tx_is_the_owner_v = '0' and m_burstcount_s = 0 and rx_first_read_done = '1' then
--rx fifo is filled with enough data -> build burst transfer
m_write_s <= '1';
m_burstcount_s <= conv_std_logic_vector(rx_burst_size_c, m_burstcount_s'length);
if m_burst_wr_const_g then
m_burstcount_latch <= conv_std_logic_vector(rx_burst_size_c, m_burstcount_latch'length);
m_address_latch <= rx_cnt;
end if;
elsif m_write_s = '1' and m_waitrequest = '0' and m_burstcount_s = 1 then
--last transfer is done -> deassert write qualifiers
m_write_s <= '0';
end if;
when finish =>
--MAC is finished with RX, transfer rest of fifo
---note: The last word (part of crc32) is not transferred!
if rx_rd_empty = '0' and m_read_s = '0' and m_write_s = '0' and tx_is_the_owner_v = '0' and m_burstcount_s = 0 then
--rx fifo has some data left
m_write_s <= '1';
--verify how many patterns are left in the fifo
if rx_rd_usedw < conv_std_logic_vector(rx_burst_size_c, rx_rd_usedw'length) then
--start the smaller burst write transfer
m_burstcount_s <= EXT(rx_rd_usedw, m_burstcount_s'length);
if m_burst_wr_const_g then
m_burstcount_latch <= EXT(rx_rd_usedw, m_burstcount_latch'length);
m_address_latch <= rx_cnt;
end if;
--workaround: fifo is not empty but word level is zero => set to one
if rx_rd_usedw = 0 then
m_burstcount_s <= conv_std_logic_vector(1, m_burstcount_s'length);
m_burstcount_latch <= conv_std_logic_vector(1, m_burstcount_latch'length);
end if;
else
--start the maximum burst write transfer
m_burstcount_s <= conv_std_logic_vector(rx_burst_size_c, m_burstcount_s'length);
if m_burst_wr_const_g then
m_burstcount_latch <= conv_std_logic_vector(rx_burst_size_c, m_burstcount_latch'length);
m_address_latch <= rx_cnt;
end if;
end if;
elsif m_write_s = '1' and m_waitrequest = '0' and m_burstcount_s = 1 then
--transfer is done -> deassert write qualifiers
m_write_s <= '0';
--completely done?!
if rx_rd_empty = '1' then
--yes!
rx_rd_done <= '1';
end if;
elsif rx_rd_empty = '1' and m_write_s = '0' then
--nothing left in the fifo and we don't try to do anything -> done!
rx_rd_done <= '1';
end if;
end case;
end if;
end if;
end process;
end master_handler;
| gpl-2.0 | f27d8f457c6c33bf9342f70890631ade | 0.499223 | 3.808244 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | staging/fpga/boards/altera/SYSTEC_ECUcore-EP3C/design_nios2_directIO/niosII_openMac_clock_1.vhd | 4 | 30,192 | --Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity niosII_openMac_clock_1_edge_to_pulse is
port (
-- inputs:
signal clock : IN STD_LOGIC;
signal data_in : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal data_out : OUT STD_LOGIC
);
end entity niosII_openMac_clock_1_edge_to_pulse;
architecture europa of niosII_openMac_clock_1_edge_to_pulse is
signal data_in_d1 : STD_LOGIC;
begin
process (clock, reset_n)
begin
if reset_n = '0' then
data_in_d1 <= std_logic'('0');
elsif clock'event and clock = '1' then
data_in_d1 <= data_in;
end if;
end process;
data_out <= data_in XOR data_in_d1;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity niosII_openMac_clock_1_slave_FSM is
port (
-- inputs:
signal master_read_done_token : IN STD_LOGIC;
signal master_write_done_token : IN STD_LOGIC;
signal slave_clk : IN STD_LOGIC;
signal slave_read : IN STD_LOGIC;
signal slave_reset_n : IN STD_LOGIC;
signal slave_write : IN STD_LOGIC;
-- outputs:
signal slave_read_request : OUT STD_LOGIC;
signal slave_waitrequest : OUT STD_LOGIC;
signal slave_write_request : OUT STD_LOGIC
);
end entity niosII_openMac_clock_1_slave_FSM;
architecture europa of niosII_openMac_clock_1_slave_FSM is
signal internal_slave_read_request : STD_LOGIC;
signal internal_slave_write_request : STD_LOGIC;
signal next_slave_read_request : STD_LOGIC;
signal next_slave_state : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal next_slave_write_request : STD_LOGIC;
signal slave_state : STD_LOGIC_VECTOR (2 DOWNTO 0);
begin
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
internal_slave_read_request <= std_logic'('0');
elsif slave_clk'event and slave_clk = '1' then
if true then
internal_slave_read_request <= next_slave_read_request;
end if;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
internal_slave_write_request <= std_logic'('0');
elsif slave_clk'event and slave_clk = '1' then
if true then
internal_slave_write_request <= next_slave_write_request;
end if;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
slave_state <= std_logic_vector'("001");
elsif slave_clk'event and slave_clk = '1' then
if true then
slave_state <= next_slave_state;
end if;
end if;
end process;
process (internal_slave_read_request, internal_slave_write_request, master_read_done_token, master_write_done_token, slave_read, slave_state, slave_write)
begin
case slave_state is -- synthesis parallel_case
when std_logic_vector'("001") =>
--read request: go from IDLE state to READ_WAIT state
if std_logic'(slave_read) = '1' then
next_slave_state <= std_logic_vector'("010");
slave_waitrequest <= std_logic'('1');
next_slave_read_request <= NOT(internal_slave_read_request);
next_slave_write_request <= internal_slave_write_request;
elsif std_logic'(slave_write) = '1' then
next_slave_state <= std_logic_vector'("100");
slave_waitrequest <= std_logic'('1');
next_slave_read_request <= internal_slave_read_request;
next_slave_write_request <= NOT(internal_slave_write_request);
else
next_slave_state <= slave_state;
slave_waitrequest <= std_logic'('0');
next_slave_read_request <= internal_slave_read_request;
next_slave_write_request <= internal_slave_write_request;
end if;
-- when std_logic_vector'("001")
when std_logic_vector'("010") =>
--stay in READ_WAIT state until master passes read done token
if std_logic'(master_read_done_token) = '1' then
next_slave_state <= std_logic_vector'("001");
slave_waitrequest <= std_logic'('0');
else
next_slave_state <= std_logic_vector'("010");
slave_waitrequest <= std_logic'('1');
end if;
next_slave_read_request <= internal_slave_read_request;
next_slave_write_request <= internal_slave_write_request;
-- when std_logic_vector'("010")
when std_logic_vector'("100") =>
--stay in WRITE_WAIT state until master passes write done token
if std_logic'(master_write_done_token) = '1' then
next_slave_state <= std_logic_vector'("001");
slave_waitrequest <= std_logic'('0');
else
next_slave_state <= std_logic_vector'("100");
slave_waitrequest <= std_logic'('1');
end if;
next_slave_read_request <= internal_slave_read_request;
next_slave_write_request <= internal_slave_write_request;
-- when std_logic_vector'("100")
when others =>
next_slave_state <= std_logic_vector'("001");
slave_waitrequest <= std_logic'('0');
next_slave_read_request <= internal_slave_read_request;
next_slave_write_request <= internal_slave_write_request;
-- when others
end case; -- slave_state
end process;
--vhdl renameroo for output signals
slave_read_request <= internal_slave_read_request;
--vhdl renameroo for output signals
slave_write_request <= internal_slave_write_request;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity niosII_openMac_clock_1_master_FSM is
port (
-- inputs:
signal master_clk : IN STD_LOGIC;
signal master_reset_n : IN STD_LOGIC;
signal master_waitrequest : IN STD_LOGIC;
signal slave_read_request_token : IN STD_LOGIC;
signal slave_write_request_token : IN STD_LOGIC;
-- outputs:
signal master_read : OUT STD_LOGIC;
signal master_read_done : OUT STD_LOGIC;
signal master_write : OUT STD_LOGIC;
signal master_write_done : OUT STD_LOGIC
);
end entity niosII_openMac_clock_1_master_FSM;
architecture europa of niosII_openMac_clock_1_master_FSM is
signal internal_master_read1 : STD_LOGIC;
signal internal_master_read_done : STD_LOGIC;
signal internal_master_write1 : STD_LOGIC;
signal internal_master_write_done : STD_LOGIC;
signal master_state : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal next_master_read : STD_LOGIC;
signal next_master_read_done : STD_LOGIC;
signal next_master_state : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal next_master_write : STD_LOGIC;
signal next_master_write_done : STD_LOGIC;
begin
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
internal_master_read_done <= std_logic'('0');
elsif master_clk'event and master_clk = '1' then
if true then
internal_master_read_done <= next_master_read_done;
end if;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
internal_master_write_done <= std_logic'('0');
elsif master_clk'event and master_clk = '1' then
if true then
internal_master_write_done <= next_master_write_done;
end if;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
internal_master_read1 <= std_logic'('0');
elsif master_clk'event and master_clk = '1' then
if true then
internal_master_read1 <= next_master_read;
end if;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
internal_master_write1 <= std_logic'('0');
elsif master_clk'event and master_clk = '1' then
if true then
internal_master_write1 <= next_master_write;
end if;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
master_state <= std_logic_vector'("001");
elsif master_clk'event and master_clk = '1' then
if true then
master_state <= next_master_state;
end if;
end if;
end process;
process (internal_master_read1, internal_master_read_done, internal_master_write1, internal_master_write_done, master_state, master_waitrequest, slave_read_request_token, slave_write_request_token)
begin
case master_state is -- synthesis parallel_case
when std_logic_vector'("001") =>
--if read request token from slave then goto READ_WAIT state
if std_logic'(slave_read_request_token) = '1' then
next_master_state <= std_logic_vector'("010");
next_master_read <= std_logic'('1');
next_master_write <= std_logic'('0');
elsif std_logic'(slave_write_request_token) = '1' then
next_master_state <= std_logic_vector'("100");
next_master_read <= std_logic'('0');
next_master_write <= std_logic'('1');
else
next_master_state <= master_state;
next_master_read <= std_logic'('0');
next_master_write <= std_logic'('0');
end if;
next_master_read_done <= internal_master_read_done;
next_master_write_done <= internal_master_write_done;
-- when std_logic_vector'("001")
when std_logic_vector'("010") =>
--stay in READ_WAIT state until master wait is deasserted
if std_logic'(NOT(master_waitrequest)) = '1' then
next_master_state <= std_logic_vector'("001");
next_master_read_done <= NOT(internal_master_read_done);
next_master_read <= std_logic'('0');
else
next_master_state <= std_logic_vector'("010");
next_master_read_done <= internal_master_read_done;
next_master_read <= internal_master_read1;
end if;
next_master_write_done <= internal_master_write_done;
next_master_write <= std_logic'('0');
-- when std_logic_vector'("010")
when std_logic_vector'("100") =>
--stay in WRITE_WAIT state until slave wait is deasserted
if std_logic'(NOT(master_waitrequest)) = '1' then
next_master_state <= std_logic_vector'("001");
next_master_write <= std_logic'('0');
next_master_write_done <= NOT(internal_master_write_done);
else
next_master_state <= std_logic_vector'("100");
next_master_write <= internal_master_write1;
next_master_write_done <= internal_master_write_done;
end if;
next_master_read_done <= internal_master_read_done;
next_master_read <= std_logic'('0');
-- when std_logic_vector'("100")
when others =>
next_master_state <= std_logic_vector'("001");
next_master_write <= std_logic'('0');
next_master_write_done <= internal_master_write_done;
next_master_read <= std_logic'('0');
next_master_read_done <= internal_master_read_done;
-- when others
end case; -- master_state
end process;
--vhdl renameroo for output signals
master_read <= internal_master_read1;
--vhdl renameroo for output signals
master_read_done <= internal_master_read_done;
--vhdl renameroo for output signals
master_write <= internal_master_write1;
--vhdl renameroo for output signals
master_write_done <= internal_master_write_done;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity niosII_openMac_clock_1_bit_pipe is
port (
-- inputs:
signal clk1 : IN STD_LOGIC;
signal clk2 : IN STD_LOGIC;
signal data_in : IN STD_LOGIC;
signal reset_clk1_n : IN STD_LOGIC;
signal reset_clk2_n : IN STD_LOGIC;
-- outputs:
signal data_out : OUT STD_LOGIC
);
end entity niosII_openMac_clock_1_bit_pipe;
architecture europa of niosII_openMac_clock_1_bit_pipe is
signal data_in_d1 : STD_LOGIC;
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of data_in_d1 : signal is "{-to ""*""} CUT=ON ; PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of data_out : signal is "PRESERVE_REGISTER=ON";
begin
process (clk1, reset_clk1_n)
begin
if reset_clk1_n = '0' then
data_in_d1 <= std_logic'('0');
elsif clk1'event and clk1 = '1' then
data_in_d1 <= data_in;
end if;
end process;
process (clk2, reset_clk2_n)
begin
if reset_clk2_n = '0' then
data_out <= std_logic'('0');
elsif clk2'event and clk2 = '1' then
data_out <= data_in_d1;
end if;
end process;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--Clock Domain Crossing AdapterniosII_openMac_clock_1
entity niosII_openMac_clock_1 is
port (
-- inputs:
signal master_clk : IN STD_LOGIC;
signal master_endofpacket : IN STD_LOGIC;
signal master_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal master_reset_n : IN STD_LOGIC;
signal master_waitrequest : IN STD_LOGIC;
signal slave_address : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
signal slave_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal slave_clk : IN STD_LOGIC;
signal slave_nativeaddress : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal slave_read : IN STD_LOGIC;
signal slave_reset_n : IN STD_LOGIC;
signal slave_write : IN STD_LOGIC;
signal slave_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- outputs:
signal master_address : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
signal master_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal master_nativeaddress : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal master_read : OUT STD_LOGIC;
signal master_write : OUT STD_LOGIC;
signal master_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal slave_endofpacket : OUT STD_LOGIC;
signal slave_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal slave_waitrequest : OUT STD_LOGIC
);
end entity niosII_openMac_clock_1;
architecture europa of niosII_openMac_clock_1 is
component altera_std_synchronizer is
GENERIC (
depth : NATURAL
);
PORT (
signal dout : OUT STD_LOGIC;
signal clk : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal din : IN STD_LOGIC
);
end component altera_std_synchronizer;
component niosII_openMac_clock_1_edge_to_pulse is
port (
-- inputs:
signal clock : IN STD_LOGIC;
signal data_in : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal data_out : OUT STD_LOGIC
);
end component niosII_openMac_clock_1_edge_to_pulse;
component niosII_openMac_clock_1_slave_FSM is
port (
-- inputs:
signal master_read_done_token : IN STD_LOGIC;
signal master_write_done_token : IN STD_LOGIC;
signal slave_clk : IN STD_LOGIC;
signal slave_read : IN STD_LOGIC;
signal slave_reset_n : IN STD_LOGIC;
signal slave_write : IN STD_LOGIC;
-- outputs:
signal slave_read_request : OUT STD_LOGIC;
signal slave_waitrequest : OUT STD_LOGIC;
signal slave_write_request : OUT STD_LOGIC
);
end component niosII_openMac_clock_1_slave_FSM;
component niosII_openMac_clock_1_master_FSM is
port (
-- inputs:
signal master_clk : IN STD_LOGIC;
signal master_reset_n : IN STD_LOGIC;
signal master_waitrequest : IN STD_LOGIC;
signal slave_read_request_token : IN STD_LOGIC;
signal slave_write_request_token : IN STD_LOGIC;
-- outputs:
signal master_read : OUT STD_LOGIC;
signal master_read_done : OUT STD_LOGIC;
signal master_write : OUT STD_LOGIC;
signal master_write_done : OUT STD_LOGIC
);
end component niosII_openMac_clock_1_master_FSM;
component niosII_openMac_clock_1_bit_pipe is
port (
-- inputs:
signal clk1 : IN STD_LOGIC;
signal clk2 : IN STD_LOGIC;
signal data_in : IN STD_LOGIC;
signal reset_clk1_n : IN STD_LOGIC;
signal reset_clk2_n : IN STD_LOGIC;
-- outputs:
signal data_out : OUT STD_LOGIC
);
end component niosII_openMac_clock_1_bit_pipe;
signal internal_master_read : STD_LOGIC;
signal internal_master_write : STD_LOGIC;
signal internal_slave_endofpacket : STD_LOGIC;
signal internal_slave_waitrequest : STD_LOGIC;
signal master_read_done : STD_LOGIC;
signal master_read_done_sync : STD_LOGIC;
signal master_read_done_token : STD_LOGIC;
signal master_write_done : STD_LOGIC;
signal master_write_done_sync : STD_LOGIC;
signal master_write_done_token : STD_LOGIC;
signal slave_address_d1 : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal slave_byteenable_d1 : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal slave_nativeaddress_d1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal slave_read_request : STD_LOGIC;
signal slave_read_request_sync : STD_LOGIC;
signal slave_read_request_token : STD_LOGIC;
signal slave_readdata_p1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal slave_write_request : STD_LOGIC;
signal slave_write_request_sync : STD_LOGIC;
signal slave_write_request_token : STD_LOGIC;
signal slave_writedata_d1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of master_address : signal is "PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of master_byteenable : signal is "PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of master_nativeaddress : signal is "PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of master_writedata : signal is "PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of slave_address_d1 : signal is "{-to ""*""} CUT=ON ; PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of slave_byteenable_d1 : signal is "{-to ""*""} CUT=ON ; PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of slave_nativeaddress_d1 : signal is "{-to ""*""} CUT=ON ; PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of slave_readdata : signal is "{-from ""*""} CUT=ON";
attribute ALTERA_ATTRIBUTE of slave_writedata_d1 : signal is "{-to ""*""} CUT=ON ; PRESERVE_REGISTER=ON";
begin
--in, which is an e_avalon_slave
--out, which is an e_avalon_master
the_altera_std_synchronizer : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => slave_clk,
din => master_read_done,
dout => master_read_done_sync,
reset_n => slave_reset_n
);
the_altera_std_synchronizer1 : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => slave_clk,
din => master_write_done,
dout => master_write_done_sync,
reset_n => slave_reset_n
);
--read_done_edge_to_pulse, which is an e_instance
read_done_edge_to_pulse : niosII_openMac_clock_1_edge_to_pulse
port map(
data_out => master_read_done_token,
clock => slave_clk,
data_in => master_read_done_sync,
reset_n => slave_reset_n
);
--write_done_edge_to_pulse, which is an e_instance
write_done_edge_to_pulse : niosII_openMac_clock_1_edge_to_pulse
port map(
data_out => master_write_done_token,
clock => slave_clk,
data_in => master_write_done_sync,
reset_n => slave_reset_n
);
--slave_FSM, which is an e_instance
slave_FSM : niosII_openMac_clock_1_slave_FSM
port map(
slave_read_request => slave_read_request,
slave_waitrequest => internal_slave_waitrequest,
slave_write_request => slave_write_request,
master_read_done_token => master_read_done_token,
master_write_done_token => master_write_done_token,
slave_clk => slave_clk,
slave_read => slave_read,
slave_reset_n => slave_reset_n,
slave_write => slave_write
);
the_altera_std_synchronizer2 : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => master_clk,
din => slave_read_request,
dout => slave_read_request_sync,
reset_n => master_reset_n
);
the_altera_std_synchronizer3 : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => master_clk,
din => slave_write_request,
dout => slave_write_request_sync,
reset_n => master_reset_n
);
--read_request_edge_to_pulse, which is an e_instance
read_request_edge_to_pulse : niosII_openMac_clock_1_edge_to_pulse
port map(
data_out => slave_read_request_token,
clock => master_clk,
data_in => slave_read_request_sync,
reset_n => master_reset_n
);
--write_request_edge_to_pulse, which is an e_instance
write_request_edge_to_pulse : niosII_openMac_clock_1_edge_to_pulse
port map(
data_out => slave_write_request_token,
clock => master_clk,
data_in => slave_write_request_sync,
reset_n => master_reset_n
);
--master_FSM, which is an e_instance
master_FSM : niosII_openMac_clock_1_master_FSM
port map(
master_read => internal_master_read,
master_read_done => master_read_done,
master_write => internal_master_write,
master_write_done => master_write_done,
master_clk => master_clk,
master_reset_n => master_reset_n,
master_waitrequest => master_waitrequest,
slave_read_request_token => slave_read_request_token,
slave_write_request_token => slave_write_request_token
);
--endofpacket_bit_pipe, which is an e_instance
endofpacket_bit_pipe : niosII_openMac_clock_1_bit_pipe
port map(
data_out => internal_slave_endofpacket,
clk1 => slave_clk,
clk2 => master_clk,
data_in => master_endofpacket,
reset_clk1_n => slave_reset_n,
reset_clk2_n => master_reset_n
);
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
slave_readdata_p1 <= std_logic_vector'("00000000000000000000000000000000");
elsif master_clk'event and master_clk = '1' then
if std_logic'((internal_master_read AND NOT master_waitrequest)) = '1' then
slave_readdata_p1 <= master_readdata;
end if;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
slave_readdata <= std_logic_vector'("00000000000000000000000000000000");
elsif slave_clk'event and slave_clk = '1' then
slave_readdata <= slave_readdata_p1;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
slave_writedata_d1 <= std_logic_vector'("00000000000000000000000000000000");
elsif slave_clk'event and slave_clk = '1' then
slave_writedata_d1 <= slave_writedata;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
master_writedata <= std_logic_vector'("00000000000000000000000000000000");
elsif master_clk'event and master_clk = '1' then
master_writedata <= slave_writedata_d1;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
slave_address_d1 <= std_logic_vector'("0000000000");
elsif slave_clk'event and slave_clk = '1' then
slave_address_d1 <= slave_address;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
master_address <= std_logic_vector'("0000000000");
elsif master_clk'event and master_clk = '1' then
master_address <= slave_address_d1;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
slave_nativeaddress_d1 <= std_logic_vector'("00000000");
elsif slave_clk'event and slave_clk = '1' then
slave_nativeaddress_d1 <= slave_nativeaddress;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
master_nativeaddress <= std_logic_vector'("00000000");
elsif master_clk'event and master_clk = '1' then
master_nativeaddress <= slave_nativeaddress_d1;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
slave_byteenable_d1 <= std_logic_vector'("0000");
elsif slave_clk'event and slave_clk = '1' then
slave_byteenable_d1 <= slave_byteenable;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
master_byteenable <= std_logic_vector'("0000");
elsif master_clk'event and master_clk = '1' then
master_byteenable <= slave_byteenable_d1;
end if;
end process;
--vhdl renameroo for output signals
master_read <= internal_master_read;
--vhdl renameroo for output signals
master_write <= internal_master_write;
--vhdl renameroo for output signals
slave_endofpacket <= internal_slave_endofpacket;
--vhdl renameroo for output signals
slave_waitrequest <= internal_slave_waitrequest;
end europa;
| gpl-2.0 | 56bb1670276630934e3cfb249783c832 | 0.581081 | 4.013293 | false | false | false | false |
chiggs/oc_mkjpeg | design/hostif/HostIF.vhd | 2 | 9,796 | -------------------------------------------------------------------------------
-- File Name : HostIF.vhd
--
-- Project : JPEG_ENC
--
-- Module : HostIF
--
-- Content : Host Interface (Xilinx OPB v2.1)
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity HostIF is
port
(
CLK : in std_logic;
RST : in std_logic;
-- OPB
OPB_ABus : in std_logic_vector(31 downto 0);
OPB_BE : in std_logic_vector(3 downto 0);
OPB_DBus_in : in std_logic_vector(31 downto 0);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_DBus_out : out std_logic_vector(31 downto 0);
OPB_XferAck : out std_logic;
OPB_retry : out std_logic;
OPB_toutSup : out std_logic;
OPB_errAck : out std_logic;
-- Quantizer RAM
qdata : out std_logic_vector(7 downto 0);
qaddr : out std_logic_vector(6 downto 0);
qwren : out std_logic;
-- CTRL
jpeg_ready : in std_logic;
jpeg_busy : in std_logic;
-- ByteStuffer
outram_base_addr : out std_logic_vector(9 downto 0);
num_enc_bytes : in std_logic_vector(23 downto 0);
-- others
img_size_x : out std_logic_vector(15 downto 0);
img_size_y : out std_logic_vector(15 downto 0);
img_size_wr : out std_logic;
sof : out std_logic
);
end entity HostIF;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of HostIF is
constant C_ENC_START_REG : std_logic_vector(31 downto 0) := X"0000_0000";
constant C_IMAGE_SIZE_REG : std_logic_vector(31 downto 0) := X"0000_0004";
constant C_IMAGE_RAM_ACCESS_REG : std_logic_vector(31 downto 0) := X"0000_0008";
constant C_ENC_STS_REG : std_logic_vector(31 downto 0) := X"0000_000C";
constant C_COD_DATA_ADDR_REG : std_logic_vector(31 downto 0) := X"0000_0010";
constant C_ENC_LENGTH_REG : std_logic_vector(31 downto 0) := X"0000_0014";
constant C_QUANTIZER_RAM_LUM : std_logic_vector(31 downto 0) :=
X"0000_01" & "------00";
constant C_QUANTIZER_RAM_CHR : std_logic_vector(31 downto 0) :=
X"0000_02" & "------00";
constant C_IMAGE_RAM : std_logic_vector(31 downto 0) :=
X"001" & "------------------00";
constant C_IMAGE_RAM_BASE : unsigned(31 downto 0) := X"0010_0000";
signal enc_start_reg : std_logic_vector(31 downto 0);
signal image_size_reg : std_logic_vector(31 downto 0);
signal image_ram_access_reg : std_logic_vector(31 downto 0);
signal enc_sts_reg : std_logic_vector(31 downto 0);
signal cod_data_addr_reg : std_logic_vector(31 downto 0);
signal enc_length_reg : std_logic_vector(31 downto 0);
signal rd_dval : std_logic;
signal data_read : std_logic_vector(31 downto 0);
signal write_done : std_logic;
signal OPB_select_d : std_logic;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
OPB_retry <= '0';
OPB_toutSup <= '0';
OPB_errAck <= '0';
img_size_x <= image_size_reg(31 downto 16);
img_size_y <= image_size_reg(15 downto 0);
outram_base_addr <= cod_data_addr_reg(outram_base_addr'range);
-------------------------------------------------------------------
-- OPB read
-------------------------------------------------------------------
p_read : process(CLK, RST)
begin
if RST = '1' then
OPB_DBus_out <= (others => '0');
rd_dval <= '0';
data_read <= (others => '0');
elsif CLK'event and CLK = '1' then
rd_dval <= '0';
OPB_DBus_out <= data_read;
if OPB_select = '1' and OPB_select_d = '0' then
-- only double word transactions are be supported
if OPB_RNW = '1' and OPB_BE = X"F" then
case OPB_ABus is
when C_ENC_START_REG =>
data_read <= enc_start_reg;
rd_dval <= '1';
when C_IMAGE_SIZE_REG =>
data_read <= image_size_reg;
rd_dval <= '1';
when C_IMAGE_RAM_ACCESS_REG =>
data_read <= image_ram_access_reg;
rd_dval <= '1';
when C_ENC_STS_REG =>
data_read <= enc_sts_reg;
rd_dval <= '1';
when C_COD_DATA_ADDR_REG =>
data_read <= cod_data_addr_reg;
rd_dval <= '1';
when C_ENC_LENGTH_REG =>
data_read <= enc_length_reg;
rd_dval <= '1';
when others =>
data_read <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------
-- OPB write
-------------------------------------------------------------------
p_write : process(CLK, RST)
begin
if RST = '1' then
qwren <= '0';
write_done <= '0';
enc_start_reg <= (others => '0');
image_size_reg <= (others => '0');
image_ram_access_reg <= (others => '0');
enc_sts_reg <= (others => '0');
cod_data_addr_reg <= (others => '0');
enc_length_reg <= (others => '0');
qdata <= (others => '0');
qaddr <= (others => '0');
OPB_select_d <= '0';
sof <= '0';
img_size_wr <= '0';
elsif CLK'event and CLK = '1' then
qwren <= '0';
write_done <= '0';
sof <= '0';
img_size_wr <= '0';
OPB_select_d <= OPB_select;
if OPB_select = '1' and OPB_select_d = '0' then
-- only double word transactions are be supported
if OPB_RNW = '0' and OPB_BE = X"F" then
case OPB_ABus is
when C_ENC_START_REG =>
enc_start_reg <= OPB_DBus_in;
write_done <= '1';
if OPB_DBus_in(0) = '1' then
sof <= '1';
end if;
when C_IMAGE_SIZE_REG =>
image_size_reg <= OPB_DBus_in;
img_size_wr <= '1';
write_done <= '1';
when C_IMAGE_RAM_ACCESS_REG =>
image_ram_access_reg <= OPB_DBus_in;
write_done <= '1';
when C_ENC_STS_REG =>
enc_sts_reg <= (others => '0');
write_done <= '1';
when C_COD_DATA_ADDR_REG =>
cod_data_addr_reg <= OPB_DBus_in;
write_done <= '1';
when C_ENC_LENGTH_REG =>
--enc_length_reg <= OPB_DBus_in;
write_done <= '1';
when others =>
null;
end case;
if std_match(OPB_ABus, C_QUANTIZER_RAM_LUM) then
qdata <= OPB_DBus_in(qdata'range);
qaddr <= '0' & OPB_ABus(qaddr'high+2-1 downto 2);
qwren <= '1';
write_done <= '1';
end if;
if std_match(OPB_ABus, C_QUANTIZER_RAM_CHR) then
qdata <= OPB_DBus_in(qdata'range);
qaddr <= '1' & OPB_ABus(qaddr'high+2-1 downto 2);
qwren <= '1';
write_done <= '1';
end if;
end if;
end if;
-- special handling of status reg
if jpeg_ready = '1' then
-- set jpeg done flag
enc_sts_reg(1) <= '1';
end if;
enc_sts_reg(0) <= jpeg_busy;
enc_length_reg <= (others => '0');
enc_length_reg(num_enc_bytes'range) <= num_enc_bytes;
end if;
end process;
-------------------------------------------------------------------
-- transfer ACK
-------------------------------------------------------------------
p_ack : process(CLK, RST)
begin
if RST = '1' then
OPB_XferAck <= '0';
elsif CLK'event and CLK = '1' then
OPB_XferAck <= rd_dval or write_done;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- | lgpl-3.0 | c674623a3fa22a191b1449fe7a34409d | 0.384238 | 4.220595 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/boards/terasic-de2-115/mn-dual-hostif-gpio/quartus/toplevel.vhd | 1 | 12,038 | -------------------------------------------------------------------------------
--! @file toplevel.vhd
--
--! @brief Toplevel of dual Nios MN design
--
--! @details This is the toplevel of the dual Nios MN FPGA design for the
--! INK DE2-115 Evaluation Board.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library libcommon;
use libcommon.global.all;
entity toplevel is
port (
-- 50 MHZ CLK IN
EXT_CLK : in std_logic;
-- PHY Interfaces
PHY_GXCLK : out std_logic_vector(1 downto 0);
PHY_RXCLK : in std_logic_vector(1 downto 0);
PHY_RXER : in std_logic_vector(1 downto 0);
PHY_RXDV : in std_logic_vector(1 downto 0);
PHY_RXD : in std_logic_vector(7 downto 0);
PHY_TXCLK : in std_logic_vector(1 downto 0);
PHY_TXER : out std_logic_vector(1 downto 0);
PHY_TXEN : out std_logic_vector(1 downto 0);
PHY_TXD : out std_logic_vector(7 downto 0);
PHY_MDIO : inout std_logic_vector(1 downto 0);
PHY_MDC : out std_logic_vector(1 downto 0);
PHY_RESET_n : out std_logic_vector(1 downto 0);
-- EPCS
EPCS_DCLK : out std_logic;
EPCS_SCE : out std_logic;
EPCS_SDO : out std_logic;
EPCS_DATA0 : in std_logic;
-- 2 MB SRAM
SRAM_CE_n : out std_logic;
SRAM_OE_n : out std_logic;
SRAM_WE_n : out std_logic;
SRAM_ADDR : out std_logic_vector(20 downto 1);
SRAM_BE_n : out std_logic_vector(1 downto 0);
SRAM_DQ : inout std_logic_vector(15 downto 0);
-- 64 MBx2 SDRAM
SDRAM_CLK : out std_logic;
SDRAM_CAS_n : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CS_n : out std_logic;
SDRAM_RAS_n : out std_logic;
SDRAM_WE_n : out std_logic;
SDRAM_ADDR : out std_logic_vector(12 downto 0);
SDRAM_BA : out std_logic_vector(1 downto 0);
SDRAM_DQM : out std_logic_vector(3 downto 0);
SDRAM_DQ : inout std_logic_vector(31 downto 0);
-- LED green
LEDG : out std_logic_vector(1 downto 0);
-- Low active KEY
KEY_n : in std_logic_vector(3 downto 0);
-- LCD
LCD_ON : out std_logic;
LCD_BLON : out std_logic;
LCD_DQ : inout std_logic_vector(7 downto 0);
LCD_E : out std_logic;
LCD_RS : out std_logic;
LCD_RW : out std_logic;
-- BENCHMARK
BENCHMARK : out std_logic_vector(7 downto 0);
-- BENCHMARK_AP
BENCHMARK_AP : out std_logic_vector(7 downto 0)
);
end toplevel;
architecture rtl of toplevel is
component mnDualHostifGpio is
port (
clk25_clk : in std_logic;
clk50_clk : in std_logic := 'X';
clk100_clk : in std_logic;
reset_reset_n : in std_logic := 'X';
tri_state_0_tcm_address_out : out std_logic_vector(20 downto 0);
tri_state_0_tcm_byteenable_n_out : out std_logic_vector(1 downto 0);
tri_state_0_tcm_read_n_out : out std_logic;
tri_state_0_tcm_write_n_out : out std_logic;
tri_state_0_tcm_data_out : inout std_logic_vector(15 downto 0) := (others => 'X');
tri_state_0_tcm_chipselect_n_out : out std_logic;
pcp_0_benchmark_pio_export : out std_logic_vector(7 downto 0);
-- OPENMAC
openmac_0_mii_txEnable : out std_logic_vector(1 downto 0);
openmac_0_mii_txData : out std_logic_vector(7 downto 0);
openmac_0_mii_txClk : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxError : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxDataValid : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxData : in std_logic_vector(7 downto 0) := (others => 'X');
openmac_0_mii_rxClk : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_smi_nPhyRst : out std_logic_vector(1 downto 0);
openmac_0_smi_clk : out std_logic_vector(1 downto 0);
openmac_0_smi_dio : inout std_logic_vector(1 downto 0) := (others => 'X');
host_0_benchmark_pio_export : out std_logic_vector(7 downto 0);
status_led_pio_export : out std_logic_vector(1 downto 0);
key_pio_export : in std_logic_vector(3 downto 0);
epcs_flash_dclk : out std_logic;
epcs_flash_sce : out std_logic;
epcs_flash_sdo : out std_logic;
epcs_flash_data0 : in std_logic := 'X';
host_0_sdram_0_addr : out std_logic_vector(12 downto 0);
host_0_sdram_0_ba : out std_logic_vector(1 downto 0);
host_0_sdram_0_cas_n : out std_logic;
host_0_sdram_0_cke : out std_logic;
host_0_sdram_0_cs_n : out std_logic;
host_0_sdram_0_dq : inout std_logic_vector(31 downto 0) := (others => 'X');
host_0_sdram_0_dqm : out std_logic_vector(3 downto 0);
host_0_sdram_0_ras_n : out std_logic;
host_0_sdram_0_we_n : out std_logic;
lcd_data : inout std_logic_vector(7 downto 0) := (others => 'X');
lcd_E : out std_logic;
lcd_RS : out std_logic;
lcd_RW : out std_logic
);
end component mnDualHostifGpio;
-- PLL component
component pll
port (
inclk0 : in std_logic;
c0 : out std_logic;
c1 : out std_logic;
c2 : out std_logic;
c3 : out std_logic;
locked : out std_logic
);
end component;
signal clk25 : std_logic;
signal clk50 : std_logic;
signal clk100 : std_logic;
signal clk100_p : std_logic;
signal pllLocked : std_logic;
signal sramAddr : std_logic_vector(SRAM_ADDR'high downto 0);
signal key : std_logic_vector(KEY_n'range);
begin
SRAM_ADDR <= sramAddr(SRAM_ADDR'range);
PHY_GXCLK <= (others => '0');
PHY_TXER <= (others => '0');
LCD_ON <= '1';
LCD_BLON <= '1';
key <= not KEY_n;
SDRAM_CLK <= clk100_p;
inst : component mnDualHostifGpio
port map (
clk25_clk => clk25,
clk50_clk => clk50,
clk100_clk => clk100,
reset_reset_n => pllLocked,
openmac_0_mii_txEnable => PHY_TXEN,
openmac_0_mii_txData => PHY_TXD,
openmac_0_mii_txClk => PHY_TXCLK,
openmac_0_mii_rxError => PHY_RXER,
openmac_0_mii_rxDataValid => PHY_RXDV,
openmac_0_mii_rxData => PHY_RXD,
openmac_0_mii_rxClk => PHY_RXCLK,
openmac_0_smi_nPhyRst => PHY_RESET_n,
openmac_0_smi_clk => PHY_MDC,
openmac_0_smi_dio => PHY_MDIO,
tri_state_0_tcm_address_out => sramAddr,
tri_state_0_tcm_read_n_out => SRAM_OE_n,
tri_state_0_tcm_byteenable_n_out => SRAM_BE_n,
tri_state_0_tcm_write_n_out => SRAM_WE_n,
tri_state_0_tcm_data_out => SRAM_DQ,
tri_state_0_tcm_chipselect_n_out => SRAM_CE_n,
pcp_0_benchmark_pio_export => BENCHMARK,
status_led_pio_export => LEDG,
key_pio_export => key,
host_0_benchmark_pio_export => BENCHMARK_AP,
epcs_flash_dclk => EPCS_DCLK,
epcs_flash_sce => EPCS_SCE,
epcs_flash_sdo => EPCS_SDO,
epcs_flash_data0 => EPCS_DATA0,
host_0_sdram_0_addr => SDRAM_ADDR,
host_0_sdram_0_ba => SDRAM_BA,
host_0_sdram_0_cas_n => SDRAM_CAS_n,
host_0_sdram_0_cke => SDRAM_CKE,
host_0_sdram_0_cs_n => SDRAM_CS_n,
host_0_sdram_0_dq => SDRAM_DQ,
host_0_sdram_0_dqm => SDRAM_DQM,
host_0_sdram_0_ras_n => SDRAM_RAS_n,
host_0_sdram_0_we_n => SDRAM_WE_n,
lcd_data => LCD_DQ,
lcd_E => LCD_E,
lcd_RS => LCD_RS,
lcd_RW => LCD_RW
);
-- Pll Instance
pllInst : pll
port map (
inclk0 => EXT_CLK,
c0 => clk50,
c1 => clk100,
c2 => clk25,
c3 => clk100_p,
locked => pllLocked
);
end rtl;
| gpl-2.0 | 9052ac5d1d9b03362d9a195585cdac83 | 0.466273 | 3.969008 | false | false | false | false |
chiggs/oc_mkjpeg | design/top/JpegEnc.vhd | 2 | 18,585 | -------------------------------------------------------------------------------
-- File Name : JpegEnc.vhd
--
-- Project : JPEG_ENC
--
-- Module : JpegEnc
--
-- Content : JPEG Encoder Top Level
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity JpegEnc is
port
(
CLK : in std_logic;
RST : in std_logic;
-- OPB
OPB_ABus : in std_logic_vector(31 downto 0);
OPB_BE : in std_logic_vector(3 downto 0);
OPB_DBus_in : in std_logic_vector(31 downto 0);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_DBus_out : out std_logic_vector(31 downto 0);
OPB_XferAck : out std_logic;
OPB_retry : out std_logic;
OPB_toutSup : out std_logic;
OPB_errAck : out std_logic;
-- IMAGE RAM
iram_wdata : in std_logic_vector(C_PIXEL_BITS-1 downto 0);
iram_wren : in std_logic;
iram_fifo_afull : out std_logic;
-- OUT RAM
ram_byte : out std_logic_vector(7 downto 0);
ram_wren : out std_logic;
ram_wraddr : out std_logic_vector(23 downto 0);
outif_almost_full : in std_logic
);
end entity JpegEnc;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of JpegEnc is
signal qdata : std_logic_vector(7 downto 0);
signal qaddr : std_logic_vector(6 downto 0);
signal qwren : std_logic;
signal jpeg_ready : std_logic;
signal jpeg_busy : std_logic;
signal outram_base_addr : std_logic_vector(9 downto 0);
signal num_enc_bytes : std_logic_vector(23 downto 0);
signal img_size_x : std_logic_vector(15 downto 0);
signal img_size_y : std_logic_vector(15 downto 0);
signal sof : std_logic;
signal jpg_iram_rden : std_logic;
signal jpg_iram_rdaddr : std_logic_vector(31 downto 0);
signal jpg_iram_rdata : std_logic_vector(23 downto 0);
signal fdct_start : std_logic;
signal fdct_ready : std_logic;
signal zig_start : std_logic;
signal zig_ready : std_logic;
signal qua_start : std_logic;
signal qua_ready : std_logic;
signal rle_start : std_logic;
signal rle_ready : std_logic;
signal huf_start : std_logic;
signal huf_ready : std_logic;
signal bs_start : std_logic;
signal bs_ready : std_logic;
signal zz_buf_sel : std_logic;
signal zz_rd_addr : std_logic_vector(5 downto 0);
signal zz_data : std_logic_vector(11 downto 0);
signal rle_buf_sel : std_logic;
signal rle_rdaddr : std_logic_vector(5 downto 0);
signal rle_data : std_logic_vector(11 downto 0);
signal qua_buf_sel : std_logic;
signal qua_rdaddr : std_logic_vector(5 downto 0);
signal qua_data : std_logic_vector(11 downto 0);
signal huf_buf_sel : std_logic;
signal huf_rdaddr : std_logic_vector(5 downto 0);
signal huf_rden : std_logic;
signal huf_runlength : std_logic_vector(3 downto 0);
signal huf_size : std_logic_vector(3 downto 0);
signal huf_amplitude : std_logic_vector(11 downto 0);
signal huf_dval : std_logic;
signal bs_buf_sel : std_logic;
signal bs_fifo_empty : std_logic;
signal bs_rd_req : std_logic;
signal bs_packed_byte : std_logic_vector(7 downto 0);
signal huf_fifo_empty : std_logic;
signal zz_rden : std_logic;
signal fdct_sm_settings : T_SM_SETTINGS;
signal zig_sm_settings : T_SM_SETTINGS;
signal qua_sm_settings : T_SM_SETTINGS;
signal rle_sm_settings : T_SM_SETTINGS;
signal huf_sm_settings : T_SM_SETTINGS;
signal bs_sm_settings : T_SM_SETTINGS;
signal image_size_reg : std_logic_vector(31 downto 0);
signal jfif_ram_byte : std_logic_vector(7 downto 0);
signal jfif_ram_wren : std_logic;
signal jfif_ram_wraddr : std_logic_vector(23 downto 0);
signal out_mux_ctrl : std_logic;
signal img_size_wr : std_logic;
signal jfif_start : std_logic;
signal jfif_ready : std_logic;
signal bs_ram_byte : std_logic_vector(7 downto 0);
signal bs_ram_wren : std_logic;
signal bs_ram_wraddr : std_logic_vector(23 downto 0);
signal jfif_eoi : std_logic;
signal fdct_fifo_rd : std_logic;
signal fdct_fifo_q : std_logic_vector(23 downto 0);
signal fdct_fifo_hf_full : std_logic;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- Host Interface
-------------------------------------------------------------------
U_HostIF : entity work.HostIF
port map
(
CLK => CLK,
RST => RST,
-- OPB
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_DBus_in => OPB_DBus_in,
OPB_RNW => OPB_RNW,
OPB_select => OPB_select,
OPB_DBus_out => OPB_DBus_out,
OPB_XferAck => OPB_XferAck,
OPB_retry => OPB_retry,
OPB_toutSup => OPB_toutSup,
OPB_errAck => OPB_errAck,
-- Quantizer RAM
qdata => qdata,
qaddr => qaddr,
qwren => qwren,
-- CTRL
jpeg_ready => jpeg_ready,
jpeg_busy => jpeg_busy,
-- ByteStuffer
outram_base_addr => outram_base_addr,
num_enc_bytes => num_enc_bytes,
-- global
img_size_x => img_size_x,
img_size_y => img_size_y,
img_size_wr => img_size_wr,
sof => sof
);
-------------------------------------------------------------------
-- BUF_FIFO
-------------------------------------------------------------------
U_BUF_FIFO : entity work.BUF_FIFO
port map
(
CLK => CLK,
RST => RST,
-- HOST PROG
img_size_x => img_size_x,
img_size_y => img_size_y,
sof => sof,
-- HOST DATA
iram_wren => iram_wren,
iram_wdata => iram_wdata,
fifo_almost_full => iram_fifo_afull,
-- FDCT
fdct_fifo_rd => fdct_fifo_rd,
fdct_fifo_q => fdct_fifo_q,
fdct_fifo_hf_full => fdct_fifo_hf_full
);
-------------------------------------------------------------------
-- Controller
-------------------------------------------------------------------
U_CtrlSM : entity work.CtrlSM
port map
(
CLK => CLK,
RST => RST,
-- output IF
outif_almost_full => outif_almost_full,
-- HOST IF
sof => sof,
img_size_x => img_size_x,
img_size_y => img_size_y,
jpeg_ready => jpeg_ready,
jpeg_busy => jpeg_busy,
-- FDCT
fdct_start => fdct_start,
fdct_ready => fdct_ready,
fdct_sm_settings => fdct_sm_settings,
-- ZIGZAG
zig_start => zig_start,
zig_ready => zig_ready,
zig_sm_settings => zig_sm_settings,
-- Quantizer
qua_start => qua_start,
qua_ready => qua_ready,
qua_sm_settings => qua_sm_settings,
-- RLE
rle_start => rle_start,
rle_ready => rle_ready,
rle_sm_settings => rle_sm_settings,
-- Huffman
huf_start => huf_start,
huf_ready => huf_ready,
huf_sm_settings => huf_sm_settings,
-- ByteStuffdr
bs_start => bs_start,
bs_ready => bs_ready,
bs_sm_settings => bs_sm_settings,
-- JFIF GEN
jfif_start => jfif_start,
jfif_ready => jfif_ready,
jfif_eoi => jfif_eoi,
-- OUT MUX
out_mux_ctrl => out_mux_ctrl
);
-------------------------------------------------------------------
-- FDCT
-------------------------------------------------------------------
U_FDCT : entity work.FDCT
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => fdct_start,
ready_pb => fdct_ready,
fdct_sm_settings => fdct_sm_settings,
-- BUF_FIFO
bf_fifo_rd => fdct_fifo_rd,
bf_fifo_q => fdct_fifo_q,
bf_fifo_hf_full => fdct_fifo_hf_full,
-- ZIG ZAG
zz_buf_sel => zz_buf_sel,
zz_rd_addr => zz_rd_addr,
zz_data => zz_data,
zz_rden => zz_rden,
-- HOST
img_size_x => img_size_x,
img_size_y => img_size_y,
sof => sof
);
-------------------------------------------------------------------
-- ZigZag top level
-------------------------------------------------------------------
U_ZZ_TOP : entity work.ZZ_TOP
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => zig_start,
ready_pb => zig_ready,
zig_sm_settings => zig_sm_settings,
-- Quantizer
qua_buf_sel => qua_buf_sel,
qua_rdaddr => qua_rdaddr,
qua_data => qua_data,
-- FDCT
fdct_buf_sel => zz_buf_sel,
fdct_rd_addr => zz_rd_addr,
fdct_data => zz_data,
fdct_rden => zz_rden
);
-------------------------------------------------------------------
-- Quantizer top level
-------------------------------------------------------------------
U_QUANT_TOP : entity work.QUANT_TOP
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => qua_start,
ready_pb => qua_ready,
qua_sm_settings => qua_sm_settings,
-- RLE
rle_buf_sel => rle_buf_sel,
rle_rdaddr => rle_rdaddr,
rle_data => rle_data,
-- ZIGZAG
zig_buf_sel => qua_buf_sel,
zig_rd_addr => qua_rdaddr,
zig_data => qua_data,
-- HOST
qdata => qdata,
qaddr => qaddr,
qwren => qwren
);
-------------------------------------------------------------------
-- RLE TOP
-------------------------------------------------------------------
U_RLE_TOP : entity work.RLE_TOP
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => rle_start,
ready_pb => rle_ready,
rle_sm_settings => rle_sm_settings,
-- HUFFMAN
huf_buf_sel => huf_buf_sel,
huf_rden => huf_rden,
huf_runlength => huf_runlength,
huf_size => huf_size,
huf_amplitude => huf_amplitude,
huf_dval => huf_dval,
huf_fifo_empty => huf_fifo_empty,
-- Quantizer
qua_buf_sel => rle_buf_sel,
qua_rd_addr => rle_rdaddr,
qua_data => rle_data,
-- HostIF
sof => sof
);
-------------------------------------------------------------------
-- Huffman Encoder
-------------------------------------------------------------------
U_Huffman : entity work.Huffman
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => huf_start,
ready_pb => huf_ready,
huf_sm_settings => huf_sm_settings,
-- HOST IF
sof => sof,
img_size_x => img_size_x,
img_size_y => img_size_y,
-- RLE
rle_buf_sel => huf_buf_sel,
rd_en => huf_rden,
runlength => huf_runlength,
VLI_size => huf_size,
VLI => huf_amplitude,
d_val => huf_dval,
rle_fifo_empty => huf_fifo_empty,
-- Byte Stuffer
bs_buf_sel => bs_buf_sel,
bs_fifo_empty => bs_fifo_empty,
bs_rd_req => bs_rd_req,
bs_packed_byte => bs_packed_byte
);
-------------------------------------------------------------------
-- Byte Stuffer
-------------------------------------------------------------------
U_ByteStuffer : entity work.ByteStuffer
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => bs_start,
ready_pb => bs_ready,
-- HOST IF
sof => sof,
num_enc_bytes => num_enc_bytes,
outram_base_addr => outram_base_addr,
-- Huffman
huf_buf_sel => bs_buf_sel,
huf_fifo_empty => bs_fifo_empty,
huf_rd_req => bs_rd_req,
huf_packed_byte => bs_packed_byte,
-- OUT RAM
ram_byte => bs_ram_byte,
ram_wren => bs_ram_wren,
ram_wraddr => bs_ram_wraddr
);
-------------------------------------------------------------------
-- JFIF Generator
-------------------------------------------------------------------
U_JFIFGen : entity work.JFIFGen
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start => jfif_start,
ready => jfif_ready,
eoi => jfif_eoi,
-- ByteStuffer
num_enc_bytes => num_enc_bytes,
-- HOST IF
qwren => qwren,
qwaddr => qaddr,
qwdata => qdata,
image_size_reg => image_size_reg,
image_size_reg_wr => img_size_wr,
-- OUT RAM
ram_byte => jfif_ram_byte,
ram_wren => jfif_ram_wren,
ram_wraddr => jfif_ram_wraddr
);
image_size_reg <= img_size_x & img_size_y;
-------------------------------------------------------------------
-- OutMux
-------------------------------------------------------------------
U_OutMux : entity work.OutMux
port map
(
CLK => CLK,
RST => RST,
-- CTRL
out_mux_ctrl => out_mux_ctrl,
-- ByteStuffer
bs_ram_byte => bs_ram_byte,
bs_ram_wren => bs_ram_wren,
bs_ram_wraddr => bs_ram_wraddr,
-- ByteStuffer
jfif_ram_byte => jfif_ram_byte,
jfif_ram_wren => jfif_ram_wren,
jfif_ram_wraddr => jfif_ram_wraddr,
-- OUT RAM
ram_byte => ram_byte,
ram_wren => ram_wren,
ram_wraddr => ram_wraddr
);
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
-------------------------------------------------------------------------------
| lgpl-3.0 | 63f920494533c13c5f7c6639a7487b19 | 0.35039 | 4.690813 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/fifo/src/asyncFifo-e.vhd | 3 | 3,713 | -------------------------------------------------------------------------------
--! @file asyncFifo-e.vhd
--
--! @brief The asynchronous FIFO entity.
--!
--! @details This is the asynchronous FIFO interface description, for a dual
--! clocked FIFO component.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity asyncFifo is
generic (
--! Data width of write and read port
gDataWidth : natural := 8;
--! Number of words stored in fifo
gWordSize : natural := 64;
--! Number of synchronizer stages
gSyncStages : natural := 2;
--! Select memory resource ("ON" = memory / "OFF" = registers)
gMemRes : string := "ON"
);
port (
--! Asynchronous clear (FIXME: Convert this to reset, and add wr-/rd-clear inputs)
iAclr : in std_logic;
--! Write Clk
iWrClk : in std_logic;
--! Write Request
iWrReq : in std_logic;
--! Write Data
iWrData : in std_logic_vector(gDataWidth-1 downto 0);
--! Write Empty Flag
oWrEmpty : out std_logic;
--! Write Full Flag
oWrFull : out std_logic;
--! Write used words
oWrUsedw : out std_logic_vector(logDualis(gWordSize)-1 downto 0);
--! Read clk
iRdClk : in std_logic;
--! Read Request
iRdReq : in std_logic;
--! Read Data
oRdData : out std_logic_vector(gDataWidth-1 downto 0);
--! Read Empty Flag
oRdEmpty : out std_logic;
--! Read Full Flag
oRdFull : out std_logic;
--! Read used words
oRdUsedw : out std_logic_vector(logDualis(gWordSize)-1 downto 0)
);
end entity asyncFifo;
| gpl-2.0 | e92e0646a9e53c87f3629f62d77a6e2f | 0.60167 | 4.682219 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/openmac/src/openmacTimer-rtl-ea.vhd | 1 | 7,861 | -------------------------------------------------------------------------------
--! @file openmacTimer-rtl-ea.vhd
--
--! @brief OpenMAC timer module
--
--! @details This is the openMAC timer module. It supports accessing the MAC
--! time and generating interrupts.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
--! Work library
library work;
--! use openmac package
use work.openmacPkg.all;
entity openmacTimer is
generic (
--! Data width of iMacTime
gMacTimeWidth : natural := 32;
--! Generate second timer
gMacTimer_2ndTimer : boolean := false;
--! Width of pulse register
gTimerPulseRegWidth : integer := 9;
--! Enable pulse width control
gTimerEnablePulseWidth : boolean := false
);
port (
--! Reset
iRst : in std_logic;
--! Clock (same like MAC)
iClk : in std_logic;
--! Write
iWrite : in std_logic;
--! Address (dword addressing!)
iAddress : in std_logic_vector(3 downto 2);
--! Write data
iWritedata : in std_logic_vector(31 downto 0);
--! Read data
oReaddata : out std_logic_vector(31 downto 0);
--! MAC time
iMacTime : in std_logic_vector(gMacTimeWidth-1 downto 0);
--! Interrupt of first timer (level triggered)
oIrq : out std_logic;
--! Toggle output of second timer
oToggle : out std_logic
);
end openmacTimer;
architecture rtl of openmacTimer is
signal cmp_enable : std_logic;
signal tog_enable : std_logic;
signal cmp_value : std_logic_vector(iMacTime'range);
signal tog_value : std_logic_vector(iMacTime'range);
signal tog_counter_value : std_logic_vector(gTimerPulseRegWidth-1 downto 0);
signal tog_counter_preset : std_logic_vector(gTimerPulseRegWidth-1 downto 0);
signal irq_s : std_logic;
signal toggle_s : std_logic;
begin
oIrq <= irq_s;
oToggle <= toggle_s when gMacTimer_2ndTimer = TRUE else cInactivated;
--! This process generates the interrupt and toggle signals and handles the
--! register writes.
REGPROC : process(iRst, iClk)
begin
if iRst = '1' then
cmp_enable <= '0';
cmp_value <= (others => '0');
irq_s <= '0';
if gMacTimer_2ndTimer = TRUE then
tog_enable <= '0';
tog_value <= (others => '0');
toggle_s <= '0';
if gTimerEnablePulseWidth = TRUE then
tog_counter_value <= (others => '0');
tog_counter_preset <= (others => '0');
end if;
end if;
elsif rising_edge(iClk) then
--cmp
if cmp_enable = '1' and iMacTime = cmp_value then
irq_s <= '1';
end if;
--tog
if tog_enable = '1' and iMacTime = tog_value and gMacTimer_2ndTimer = TRUE then
toggle_s <= not toggle_s;
if gTimerEnablePulseWidth = TRUE then
tog_counter_value <= tog_counter_preset;
end if;
end if;
if tog_enable = '1' and toggle_s = '1'
and (not (tog_counter_value = std_logic_vector(to_unsigned(0, tog_counter_value'length))))
and gMacTimer_2ndTimer = TRUE
and gTimerEnablePulseWidth = TRUE then
tog_counter_value <= std_logic_vector(unsigned(tog_counter_value) - 1);
if tog_counter_value = std_logic_vector(to_unsigned(1, tog_counter_value'length)) then
toggle_s <= '0';
end if;
end if;
--memory mapping
if iWrite = '1' then
case iAddress is
when "00" =>
cmp_value <= iWritedata;
irq_s <= '0';
when "01" =>
cmp_enable <= iWritedata(0);
when "10" =>
if gMacTimer_2ndTimer = TRUE then
tog_value <= iWritedata;
end if;
when "11" =>
if gMacTimer_2ndTimer = TRUE then
tog_enable <= iWritedata(0);
if gTimerEnablePulseWidth = TRUE then
tog_counter_preset <= iWritedata(gTimerPulseRegWidth downto 1);
end if;
end if;
when others =>
assert (FALSE)
report "Write in forbidden area?"
severity failure;
end case;
end if;
end if;
end process REGPROC;
ASSIGN_RD : process (
iAddress,
iMacTime,
irq_s,
cmp_enable,
tog_value,
toggle_s,
tog_enable
)
begin
--default is all zero
oReaddata <= (others => cInactivated);
case iAddress is
when "00" =>
oReaddata <= iMacTime;
when "01" =>
oReaddata(1) <= irq_s;
oReaddata(0) <= cmp_enable;
when "10" =>
if gMacTimer_2ndTimer = TRUE then
oReaddata <= tog_value;
end if;
when "11" =>
if gMacTimer_2ndTimer = TRUE then
oReaddata(1) <= toggle_s;
oReaddata(0) <= tog_enable;
end if;
when others =>
NULL; --this is okay, since default assignment is above!
end case;
end process ASSIGN_RD;
end rtl;
| gpl-2.0 | 03800f266d43ca20acaeed5b9cfaf96b | 0.52347 | 4.767132 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/axiwrapper/src/axiLiteSlaveWrapper-rtl-ea.vhd | 3 | 14,600 | -------------------------------------------------------------------------------
--! @file axiLiteSlaveWrapper-rtl-ea.vhd
--
--! @brief AXI lite slave wrapper on avalon slave interface signals
--
--! @details AXI lite slave will convert AXI slave interface singal to Avalon
--! interface signals.
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2014, Bernecker+Rainer Industrie-Elektronik Ges.m.b.H. (B&R)
-- Copyright (c) 2014, Kalycito Infotech Private Limited.
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--! Use standard ieee library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Use libcommon library
library libcommon;
--! Use Global Library
use libcommon.global.all;
-------------------------------------------------------------------------------
--! @brief
--! @details AXI-lite slave wrapper will receive signals from AXI bus and
--! provide proper inputs for a Avlon interface to perform the same action
--! initiated by AXI master
-------------------------------------------------------------------------------
entity axiLiteSlaveWrapper is
generic (
--! Base Lower address for the AXI-lite slave interface
gBaseAddr : std_logic_vector(31 downto 0) := x"00000000";
--! Base Higher address for the AXI-lite slave interface
gHighAddr : std_logic_vector(31 downto 0) := x"0000ffff";
--! Address width for AXI bus interface
gAddrWidth : integer := 32;
--! Data width for AXI bus interface
gDataWidth : integer := 32
);
port (
--! Global Clock for AXI
iAclk : in std_logic;
--! Global Reset for AXI
inAReset : in std_logic;
--! Address for Write Address Channel
iAwaddr : in std_logic_vector(gAddrWidth-1 downto 0);
--! Protection for Write Address Channel
iAwprot : in std_logic_vector(2 downto 0); --unused input
--! AddressValid for Write Address Channel
iAwvalid : in std_logic;
--! AddressReady for Write Address Channel
oAwready : out std_logic;
--! WriteData for Write Data Channel
iWdata : in std_logic_vector(gDataWidth-1 downto 0);
--! WriteStrobe for Write Data Channel
iWstrb : in std_logic_vector(gDataWidth/8-1 downto 0);
--! WriteValid for Write Data Channel
iWvalid : in std_logic;
--! WriteReady for Write Data Channel
oWready : out std_logic;
--! WriteResponse for Write Response Channel
oBresp : out std_logic_vector (1 downto 0);
--! ResponseValid for Write Response Channel
oBvalid : out std_logic;
--! ResponaseReady for Write Response Channel
iBready : in std_logic;
--! ReadAddress for Read Address Channel
iAraddr : in std_logic_vector(gAddrWidth-1 downto 0);
--! ReadAddressProtection for Read Address Channel
iArprot : in std_logic_vector(2 downto 0); --unused input
--! ReadAddressValid for Read Address Channel
iArvalid : in std_logic;
--! ReadAddressReady for Read Address Channel
oArready : out std_logic;
--! ReadData for Read Data Channel
oRdata : out std_logic_vector(gDataWidth-1 downto 0);
--! ReadResponse for Read Data Channel
oRresp : out std_logic_vector(1 downto 0);
--! ReadValid for Read Data Channel
oRvalid : out std_logic;
--! ReadReady for Read Data Channel
iRready : in std_logic;
--! Address to Avalon Slave Interface
oAvsAddress : out std_logic_vector(gAddrWidth-1 downto 0);
--! Byte Enable for Avalon Slave interface
oAvsByteenable : out std_logic_vector(gDataWidth/8-1 downto 0);
--! Write Data for Avalon Slave interface
oAvsWritedata : out std_logic_vector(gDataWidth-1 downto 0);
--! Read Data for Avalon Slave interface
iAvsReaddata : in std_logic_vector(gDataWidth-1 downto 0);
--! Read signal for Avalon Slave interface
oAvsRead : out std_logic;
--! Write signal for Avalon Slave interface
oAvsWrite : out std_logic;
--! WaitRequest for Avalon slave interface
iAvsWaitrequest : in std_logic
);
end axiLiteSlaveWrapper;
architecture rtl of axiLiteSlaveWrapper is
--! Control signal FSM
type tFsm is (
sIDLE,
sREAD,
sREAD_DONE,
sWRITE,
sWRITE_DONE,
sWRRES_DONE,
sDELAY
);
--Avalon Interface designs
--! address latch for Avalon Interface
signal address : std_logic_vector(gAddrWidth-1 downto 0);
--! Muxed address from AXI interface
signal mux_address : std_logic_vector(gAddrWidth-1 downto 0);
--! Chip select for address decoder
signal chip_sel : std_logic;
--! Muxed byte enable latch from AXI Interface
signal byte_enable : std_logic_vector(gDataWidth/8-1 downto 0);
--Signals for FSM
--! synchronized fsm state
signal fsm : tFsm;
--! fsm state for combinational logic
signal fsm_next : tFsm;
--Internal Signals
--! control for Avalon read signal with fsm
signal avalonRead : std_logic;
--! Read Data latch for Avalon interface
signal avalonReadDataLatch : std_logic_vector(31 downto 0);
--! control for Avalon write signal with fsm
signal avalonWrite : std_logic;
--! write data from AXI for Avalon interface
signal axiWriteData : std_logic_vector(31 downto 0);
--! valid data from AXI to Avalon
signal axiDataValid : std_logic;
--! Write start fsm operations
signal writeStart : std_logic;
--! Write select for control write operations
signal write_sel : std_logic;
--! Read Start for fsm operations
signal readStart : std_logic;
--! Read select for control read operations
signal read_sel : std_logic;
begin
--Avalon Slave Interface Signals
oAvsAddress <= address;
oAvsByteenable <= byte_enable;
oAvsRead <= avalonRead;
oAvsWrite <= avalonWrite;
oAvsWritedata <= axiWriteData;
avalonRead <= cActivated when readStart = cActivated and fsm = sIDLE else
cActivated when fsm = sREAD else
cInactivated when fsm = sREAD_DONE else
cInactivated;
avalonWrite <= cActivated when fsm = sWRITE and iWvalid = cActivated else
cActivated when fsm = sIDLE and axiDataValid = cActivated else
cActivated when fsm = sWRITE_DONE else
cInactivated;
axiWriteData <= iWdata when axiDataValid = cActivated else
axiWriteData;
-- AXI-Lite Write Data Signals
oBvalid <= cActivated when fsm = sWRITE_DONE and iAvsWaitrequest = cInactivated else
cActivated when fsm = sWRRES_DONE else
cInactivated;
oAwready <= cActivated when fsm = sIDLE and writeStart = cActivated else
cInactivated;
oWready <= cActivated when fsm = sWRITE else
cActivated when fsm = sIDLE and axiDataValid = cActivated else
cInactivated;
-- AXI-lite Read Data Signals
oArready <= cActivated when fsm = sIDLE and readStart = cActivated else
cInactivated;
oRvalid <= cActivated when iAvsWaitrequest = cInactivated and fsm = sREAD else
cActivated when fsm = sREAD_DONE else
cInactivated;
oRdata <= avalonReadDataLatch;
avalonReadDataLatch <= iAvsReaddata when iAvsWaitrequest = cInactivated else
avalonReadDataLatch;
--TODO: Check the possibility of Error Response signals
oBresp <= "00";
oRresp <= "00";
-- Address Decoder
chip_sel <= read_sel or write_sel;
-- 64Kbyte address range only supported so MSB 16 bits enough for Decoding
write_sel <= cActivated when iAwaddr(31 downto 16) = gBaseAddr(31 downto 16) else
cInactivated;
read_sel <= cActivated when iAraddr(31 downto 16) = gBaseAddr(31 downto 16) else
cInactivated;
-- TODO: Check possibilities of reduce the no of bits in MUX/latch design
-- and avoid combinational feedback on MUX
-- Mux the address first and latch it with FSM
address <= mux_address when fsm = sIDLE else
address ;
mux_address <= iAraddr when readStart = cActivated else
iAwaddr when writeStart = cActivated else
x"00000000" ;
writeStart <= chip_sel and iAwvalid;
readStart <= chip_sel and iArvalid;
axiDataValid <= iWvalid;
byte_enable <= x"F" when readStart = cActivated and fsm = sIDLE else
iWstrb when writeStart = cActivated and fsm = sIDLE else
byte_enable;
-- Main Control FSM for converting AXI-lite signals to Avalon
--! Clock Based Process for state changes
SEQ_LOGIC_FSM : process(iAclk)
begin
if rising_edge(iAclk) then
if inAReset = cnActivated then
fsm <= sIDLE;
else
fsm <= fsm_next;
end if;
end if;
end process SEQ_LOGIC_FSM;
--! Control State machine
COM_LOGIC_FSM : process (
fsm,
chip_sel,
iAwvalid,
iArvalid,
iRready,
iWvalid,
iBready,
iAvsWaitrequest
)
begin
--Default to avoid latches
fsm_next <= fsm;
case fsm is
when sIDLE =>
if chip_sel = cActivated then
--Write Operations
if iAwvalid = cActivated then
if iWvalid = cActivated then
if iAvsWaitrequest = cInactivated then
fsm_next <= sWRRES_DONE;
else
fsm_next <= sWRITE_DONE;
end if;
else
fsm_next <= sWRITE;
end if;
--Read Operations
elsif iArvalid = cActivated then
if iAvsWaitrequest = cInactivated then
fsm_next <= sREAD_DONE;
else
fsm_next <= sREAD;
end if;
else
fsm_next <= sIDLE;
end if;
else
fsm_next <= sIDLE;
end if;
when sREAD =>
-- Read Valid gets assert Here
if iAvsWaitrequest = cInactivated then
if iRready = cActivated then
fsm_next <= sIDLE;
else
fsm_next <= sREAD_DONE;
end if;
else
fsm_next <= sREAD;
end if;
when sREAD_DONE =>
if iRready = cActivated then
fsm_next <= sIDLE;
else
fsm_next <= sREAD_DONE;
end if;
when sWRITE =>
if iWvalid = cActivated then
if iAvsWaitrequest = cInactivated then
if iBready = cActivated then
fsm_next <= sIDLE;
else
fsm_next <= sWRRES_DONE;
end if;
else
fsm_next <= sWRITE_DONE;
end if;
else
fsm_next <= sWRITE;
end if;
when sWRITE_DONE =>
if iAvsWaitrequest = cInactivated then
if iBready = cActivated then
fsm_next <= sIDLE;
else
fsm_next <= sWRRES_DONE;
end if;
else
fsm_next <= sWRITE_DONE;
end if;
when sWRRES_DONE =>
if iBready = cActivated then
fsm_next <= sIDLE;
else
fsm_next <= sWRRES_DONE;
end if;
when sDELAY =>
fsm_next <= sIDLE;
when others =>
null;
end case;
end process COM_LOGIC_FSM;
end rtl;
| gpl-2.0 | 5cf81b9d0eaca22937db2ad4637a0b45 | 0.549452 | 5.169972 | false | false | false | false |
pkerling/Chips-Demo | gigabee_tb.vhd | 1 | 5,500 | library ieee;
use ieee.std_logic_1164.all;
library ethernet_mac;
use ethernet_mac.framing_common.all;
use ethernet_mac.crc32.all;
entity gigabee_tb is
end entity;
architecture behavioral of gigabee_tb is
--Inputs
signal CLK_IN : std_logic := '0';
signal RXDV : std_logic := '0';
signal RXER : std_logic := '0';
signal RXCLK : std_logic := '0';
signal RXD : std_logic_vector(7 downto 0) := (others => '0');
signal TXCLK : std_logic := '0';
--BiDirs
signal MDIO : std_logic;
--Outputs
signal PHY_RESET : std_logic;
signal GTXCLK : std_logic;
signal TXD : std_logic_vector(7 downto 0);
signal TXEN : std_logic;
signal TXER : std_logic;
signal MDC : std_logic;
signal GPIO_LEDS : std_logic_vector(3 downto 0);
-- Clock period definitions
constant CLK_IN_period : time := 8 ns;
constant mii_tx_clk_i_period : time := 40 ns;
constant mii_rx_clk_i_period : time := 40 ns;
constant SPEED_10100 : boolean := FALSE;
-- ARP Request
type t_memory is array (natural range <>) of std_logic_vector(7 downto 0);
-- ICMP Ping Request
constant test_packet_1 : t_memory := (
x"FF", x"FF", x"FF", x"FF", x"FF", x"FF",
x"54", x"EE", x"75", x"34", x"2a", x"7e",
x"08", x"00",
x"45", x"00", x"00", x"54", x"c0", x"04", x"40", x"00", x"40",
x"01", x"f5", x"4c",
x"c0", x"a8", x"01", x"05",
x"c0", x"a8", x"01", x"01",
x"08", x"00",
x"95", x"80",
x"0c", x"4f", x"00", x"01",
x"b6", x"c4", x"7d", x"55", x"00", x"00", x"00", x"00",
x"5f", x"42", x"04", x"00", x"00", x"00", x"00", x"00",
x"10", x"11", x"12", x"13", x"14", x"15", x"16", x"17", x"18", x"19", x"1a", x"1b",
x"1c", x"1d", x"1e", x"1f", x"20", x"21", x"22", x"23", x"24", x"25", x"26", x"27", x"28",
x"29", x"2a", x"2b", x"2c", x"2d", x"2e", x"2f", x"30", x"31", x"32", x"33", x"34", x"35",
x"36", x"37"
);
-- ARP Reply
constant test_packet_2 : t_memory := (
x"FF", x"FF", x"FF", x"FF", x"FF", x"FF",
x"54", x"EE", x"75", x"34", x"2a", x"7e",
x"08", x"06",
x"00", x"01", x"08", x"00",
x"06", x"04", x"00", x"02",
x"54", x"EE", x"75", x"34", x"2a", x"7e",
x"c0", x"a8", x"02", x"05",
x"00", x"01", x"02", x"03", x"04", x"05",
x"c0", x"a8", x"02", x"02"
);
-- ARP Request
constant test_packet_3 : t_memory := (
x"FF", x"FF", x"FF", x"FF", x"FF", x"FF",
x"54", x"EE", x"75", x"34", x"2a", x"7e",
x"08", x"06",
x"00", x"01", x"08", x"00",
x"06", x"04", x"00", x"01",
x"54", x"EE", x"75", x"34", x"2a", x"7e",
x"c0", x"a8", x"01", x"05",
x"ff", x"ff", x"ff", x"ff", x"ff", x"ff",
x"c0", x"a8", x"01", x"01",
-- Padding
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"
);
constant test_packet : t_memory := test_packet_3;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut : entity work.gigabee port map(
CLK_IN => CLK_IN,
PHY_RESET => PHY_RESET,
RXDV => RXDV,
RXER => RXER,
RXCLK => RXCLK,
RXD => RXD,
TXCLK => TXCLK,
GTXCLK => GTXCLK,
TXD => TXD,
TXEN => TXEN,
TXER => TXER,
MDC => MDC,
MDIO => MDIO,
GPIO_LEDS => GPIO_LEDS,
RS232_RX => '0'
);
-- Clock process definitions
CLK_IN_process : process
begin
CLK_IN <= '0';
wait for CLK_IN_period / 2;
CLK_IN <= '1';
wait for CLK_IN_period / 2;
end process;
mii_tx_clk_i_process : process
begin
TXCLK <= '0';
wait for mii_tx_clk_i_period / 2;
TXCLK <= '1';
wait for mii_tx_clk_i_period / 2;
end process;
-- Stimulus process
stim_proc : process is
procedure mii_put1(
-- lolisim
-- crashes if (others => '0') is used instead of "00000000"
data : in std_logic_vector(7 downto 0) := "00000000";
dv : in std_logic := '1';
er : in std_logic := '0') is
begin
RXCLK <= '0';
RXDV <= dv;
RXER <= er;
RXD <= data;
wait for mii_rx_clk_i_period / 2;
RXCLK <= '1';
wait for mii_rx_clk_i_period / 2;
end procedure;
procedure mii_put(
data : in std_logic_vector(7 downto 0) := "00000000";
dv : in std_logic := '1';
er : in std_logic := '0') is
begin
if SPEED_10100 = TRUE then
mii_put1("0000" & data(3 downto 0), dv, er);
mii_put1("0000" & data(7 downto 4), dv, er);
else
mii_put1(data, dv, er);
end if;
end procedure;
procedure mii_toggle is
begin
mii_put(dv => '0', er => '0', data => open);
end procedure;
variable fcs : t_crc32;
begin
wait until PHY_RESET = '1';
wait for CLK_IN_period * 1100;
while TRUE loop
for i in 0 to 10 loop
mii_toggle;
end loop;
mii_put(std_logic_vector(START_FRAME_DELIMITER_DATA));
fcs := (others => '1');
for j in test_packet'range loop
mii_put(test_packet(j));
fcs := update_crc32(fcs, std_ulogic_vector(test_packet(j)));
end loop;
-- for j in 1 to 1000 loop
-- mii_put(x"23");
-- end loop;
for b in 0 to 3 loop
mii_put(std_logic_vector(fcs_output_byte(fcs, b)));
end loop;
while TRUE loop
mii_toggle;
end loop;
end loop;
wait;
end process;
end architecture; | mit | 74721a4a455876723976a2376491a61c | 0.512182 | 2.398604 | false | false | false | false |
cnplab/blockmon | fw-combo/src/netcope-sim/models/fl_bfm_rdy_pkg.vhd | 1 | 4,573 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- fl_bfm_rdy_pkg.vhd: RDY signal functions package for sim and monitor
-- Copyright (C) 2007 CESNET
-- Author(s): Vlastimil Kosar <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: fl_bfm_rdy_pkg.vhd 12021 2011-04-15 08:23:45Z kastovsky $
--
-- TODO:
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;
-- ----------------------------------------------------------------------------
-- RDY functions package
-- ----------------------------------------------------------------------------
PACKAGE fl_bfm_rdy_pkg IS
TYPE RDYSignalDriver IS (EVER, ONOFF, RND);
PROCEDURE DriveRdyN50_50(signal CLK : IN std_logic;
signal RDY_N : OUT std_logic);
PROCEDURE DriveRdyNAll(signal CLK : IN std_logic;
signal RDY_N : OUT std_logic);
PROCEDURE DriveRdyNRnd(signal CLK : IN std_logic;
signal RDY_N : OUT std_logic);
PROCEDURE SetSeed(Seed : in integer);
END fl_bfm_rdy_pkg;
-- ----------------------------------------------------------------------------
-- FrameLink Bus BFM Package BODY
-- ----------------------------------------------------------------------------
PACKAGE BODY fl_bfm_rdy_pkg IS
SHARED VARIABLE number: integer := 399751;
PROCEDURE SetSeed(Seed : in integer) IS
BEGIN
number := Seed;
END;
PROCEDURE Random(RND : out integer) IS
BEGIN
number := number * 69069 + 1;
RND := (number rem 7);
END;
PROCEDURE DriveRdyN50_50(signal CLK : IN std_logic;
signal RDY_N : OUT std_logic) IS
BEGIN
RDY_N <= '0';
wait until (CLK'event and CLK='1');
RDY_N <= '1';
wait until (CLK'event and CLK='1');
END;
PROCEDURE DriveRdyNAll(signal CLK : IN std_logic;
signal RDY_N : OUT std_logic) IS
BEGIN
RDY_N <= '0';
wait until (CLK'event and CLK='1');
END;
PROCEDURE DriveRdyNRnd(signal CLK : IN std_logic;
signal RDY_N : OUT std_logic) IS
VARIABLE RNDVAL: integer;
VARIABLE VALUE: std_logic;
BEGIN
Random(RNDVAL);
if (RNDVAL rem 2 = 0) then
VALUE := '0';
else
VALUE := '1';
end if;
Random(RNDVAL);
for i in 1 to RNDVAL loop
RDY_N <= VALUE;
wait until (CLK'event and CLK='1');
end loop;
END;
END fl_bfm_rdy_pkg;
| bsd-3-clause | 0545f217c7d550f264eb0146457f7767 | 0.576864 | 4.285848 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/lib/src/binaryEncoderRtl.vhd | 3 | 4,012 | -------------------------------------------------------------------------------
--! @file binaryEncoderRtl.vhd
--
--! @brief Generic Binary Encoder with reduced or-operation
--
--! @details This generic binary encoder can be configured to any width,
--! however, mind base 2 values. In order to reduce the complexity of the
--! synthesized circuit the reduced or-operation is applied.
-- (Borrowed from academic.csuohio.edu/chu_p and applied coding styles)
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity binaryEncoder is
generic (
--! One-hot data width
gDataWidth : natural := 8
);
port (
--! One hot code input
iOneHot : in std_logic_vector(gDataWidth-1 downto 0);
--! Binary encoded output
oBinary : out std_logic_vector(LogDualis(gDataWidth)-1 downto 0)
);
end binaryEncoder;
architecture rtl of binaryEncoder is
type tMaskArray is array(LogDualis(gDataWidth)-1 downto 0) of
std_logic_vector(gDataWidth-1 downto 0);
signal mask : tMaskArray;
function genOrMask return tMaskArray is
variable vOrMask: tMaskArray;
begin
for i in (LogDualis(gDataWidth)-1) downto 0 loop
for j in (gDataWidth-1) downto 0 loop
if (j/(2**i) mod 2)= 1 then
vOrMask(i)(j) := '1';
else
vOrMask(i)(j) := '0';
end if;
end loop;
end loop;
return vOrMask;
end function;
begin
mask <= genOrMask;
process (
mask,
iOneHot
)
variable rowVector : std_logic_vector(gDataWidth-1 downto 0);
variable tempBit : std_logic;
begin
for i in (LogDualis(gDataWidth)-1) downto 0 loop
rowVector := iOneHot and mask(i);
-- reduced or operation
tempBit := '0';
for j in (gDataWidth-1) downto 0 loop
tempBit := tempBit or rowVector(j);
end loop;
oBinary(i) <= tempBit;
end loop;
end process;
end rtl;
| gpl-2.0 | 2f53698fb741c8bab73fe4051ae29aaa | 0.617149 | 4.492721 | false | false | false | false |
cnplab/blockmon | fw-combo/src/common/utils.vhd | 1 | 12,400 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_unsigned.all;
package utils is
FUNCTION or_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
FUNCTION and_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
function popcount6 (arg: std_logic_vector) return std_logic_vector;
function popcount32 (arg: std_logic_vector) return std_logic_vector;
function popcount64 (arg: std_logic_vector) return std_logic_vector;
function myror (L: std_logic_vector; R: integer) return std_logic_vector;
function to_string(sv: Std_Logic_Vector) return string;
function hstr(slv: std_logic_vector) return string;
function h(slv: std_logic_vector) return string;
end utils;
package body utils is
function popcount6 (arg: std_logic_vector) return std_logic_vector is
variable temp : std_logic_vector(5 downto 0) := "000000";
variable result : std_logic_vector(2 downto 0) := "000";
begin
temp:=arg;
case temp is
when "000000" =>
result:= "000";
when "000001" =>
result:= "001";
when "000010" =>
result:= "001";
when "000011" =>
result:= "010";
when "000100" =>
result:= "001";
when "000101" =>
result:= "010";
when "000110" =>
result:= "010";
when "000111" =>
result:= "011";
when "001000" =>
result:= "001";
when "001001" =>
result:= "010";
when "001010" =>
result:= "010";
when "001011" =>
result:= "011";
when "001100" =>
result:= "010";
when "001101" =>
result:= "011";
when "001110" =>
result:= "011";
when "001111" =>
result:= "100";
when "010000" =>
result:= "001";
when "010001" =>
result:= "010";
when "010010" =>
result:= "010";
when "010011" =>
result:= "011";
when "010100" =>
result:= "010";
when "010101" =>
result:= "011";
when "010110" =>
result:= "011";
when "010111" =>
result:= "100";
when "011000" =>
result:= "010";
when "011001" =>
result:= "011";
when "011010" =>
result:= "011";
when "011011" =>
result:= "100";
when "011100" =>
result:= "011";
when "011101" =>
result:= "100";
when "011110" =>
result:= "100";
when "011111" =>
result:= "101";
when "100000" =>
result:= "001";
when "100001" =>
result:= "010";
when "100010" =>
result:= "010";
when "100011" =>
result:= "011";
when "100100" =>
result:= "010";
when "100101" =>
result:= "011";
when "100110" =>
result:= "011";
when "100111" =>
result:= "100";
when "101000" =>
result:= "010";
when "101001" =>
result:= "011";
when "101010" =>
result:= "011";
when "101011" =>
result:= "100";
when "101100" =>
result:= "011";
when "101101" =>
result:= "100";
when "101110" =>
result:= "100";
when "101111" =>
result:= "101";
when "110000" =>
result:= "010";
when "110001" =>
result:= "011";
when "110010" =>
result:= "011";
when "110011" =>
result:= "100";
when "110100" =>
result:= "011";
when "110101" =>
result:= "100";
when "110110" =>
result:= "100";
when "110111" =>
result:= "101";
when "111000" =>
result:= "011";
when "111001" =>
result:= "100";
when "111010" =>
result:= "100";
when "111011" =>
result:= "101";
when "111100" =>
result:= "100";
when "111101" =>
result:= "101";
when "111110" =>
result:= "101";
when "111111" =>
result:= "110";
when others =>
result:= "000";
end case;
return result;
end function popcount6;
function popcount32 (arg: std_logic_vector) return std_logic_vector is
variable s1,s2,s3: std_logic_vector(2 downto 0) := "000";
variable p1,p2,p3,p4,p5,p6 : std_logic_vector(2 downto 0) := "000";
variable result : std_logic_vector(5 downto 0) := "000000";
begin
--first stage compression 6:3
p1:= popcount6(arg(5 downto 0));
p2:= popcount6(arg(11 downto 6));
p3:= popcount6(arg(17 downto 12));
p4:= popcount6(arg(23 downto 18));
p5:= popcount6(arg(29 downto 24));
p6:= popcount6(arg(31 downto 30)&"0000");
--second stage compression 6:3
s1:=popcount6(p1(0) & p2(0)& p3(0) & p4(0) & p5(0) & p6(0) );
s2:=popcount6(p1(1) & p2(1)& p3(1) & p4(1) & p5(1) & p6(1) );
s3:=popcount6(p1(2) & p2(2)& p3(2) & p4(2) & p5(2) & p6(2) );
--third stage compression 6:3
result(4 downto 0):="00"&s1+'0'&s2&'0'+s3&"00";
result(5):=and_reduce(arg);
return result;
end function popcount32;
function popcount64 (arg: std_logic_vector) return std_logic_vector is
variable carry_0, carry_2: std_logic := '0';
variable u3,u4 : std_logic_vector(2 downto 0) := "000";
variable t1,t2,t3,t4 : std_logic_vector(2 downto 0) := "000";
variable s1,s2,s3,s4,s5,s6: std_logic_vector(2 downto 0) := "000";
variable p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11 : std_logic_vector(2 downto 0) := "000";
variable result : std_logic_vector(6 downto 0) := "0000000";
begin
--first stage compression 6:3
p1:= popcount6(arg(5 downto 0));
p2:= popcount6(arg(11 downto 6));
p3:= popcount6(arg(17 downto 12));
p4:= popcount6(arg(23 downto 18));
p5:= popcount6(arg(29 downto 24));
p6:= popcount6(arg(35 downto 30));
p7:= popcount6(arg(41 downto 36));
p8:= popcount6(arg(47 downto 42));
p9:= popcount6(arg(53 downto 48));
p10:= popcount6(arg(59 downto 54));
p11:= popcount6("00"& arg(63 downto 60));
--second stage compression 6:3
s1:=popcount6(p1(0) & p2(0)& p3(0) & p4(0) & p5(0) & p6(0) );
s2:=popcount6(p7(0) & p8(0)& p9(0) & p10(0) & p11(0) & '0' );
s3:=popcount6(p1(1) & p2(1)& p3(1) & p4(1) & p5(1) & p6(1) );
s4:=popcount6(p7(1) & p8(1)& p9(1) & p10(1) & p11(1) & '0' );
s5:=popcount6(p1(2) & p2(2)& p3(2) & p4(2) & p5(2) & p6(2) );
s6:=popcount6(p7(2) & p8(2)& p9(2) & p10(2) & p11(2) & '0' );
--third stage compression 6:3
result(0):=s1(0) xor s2(0);
carry_0:=s1(0) and s2(0);
t1:=popcount6(s1(1) & s2(1)& s3(0) & s4(0) & carry_0 & '0' );
t2:=popcount6(s1(2) & s2(2)& s3(1) & s4(1) & s5(0) & s6(0) );
t3:=popcount6(s3(2) & s4(2)& s5(1) & s6(1) & "00" );
t4(0):=s5(2) xor s6(2);
t4(1):=s5(2) and s6(2);
result(1):=t1(0);
result(2):=t2(0) xor t1(1);
carry_2:=t2(0) and t1(1);
u3:=popcount6(t1(2) & t2(1) & t3(0) & carry_2 & "00");
u4:=popcount6(t2(2) & t3(1) & t4(0) & "000");
--use carry save
result(3):=u3(0);
result(4):=u3(1) xor u4(0);
result(5):=u3(2) xor u4(1) xor t3(2) xor t4(1) xor (u3(1) and u4(0));
result(6):=and_reduce(arg);
return result;
end function popcount64;
function h(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'length+1)/4;
if (slv'length+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto slv'right) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end function h;
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end function hstr;
function to_string(sv: Std_Logic_Vector)
return string is
use Std.TextIO.all;
variable bv: bit_vector(sv'range) := to_bitvector(sv);
variable lp: line;
begin
write(lp, bv);
return lp.all;
end function to_string;
function myror (L: std_logic_vector; R: integer) return std_logic_vector is
begin
return to_stdlogicvector(to_bitvector(L) ror R);
end function myror;
function or_reduce (arg: std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in arg'reverse_range loop
result := arg(i) or result;
end loop;
return result;
end function or_reduce;
function and_reduce (arg: std_logic_vector) return std_logic is
variable result : std_logic := '1';
begin
for i in arg'reverse_range loop
result := arg(i) and result;
end loop;
return result;
end function and_reduce;
end utils;
| bsd-3-clause | 48b11e4f19017976368115dee134ce67 | 0.47 | 3.354978 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/axiwrapper/src/axiLiteMasterWrapper-rtl-ea.vhd | 3 | 19,332 | -------------------------------------------------------------------------------
--! @file axiLiteMasterWrapper-rtl-ea.vhd
--
--! @brief AXI lite master wrapper on avalon master interface signals
--
--! @details This will convert avalon master interface signals to AXI master
--! interface signals.
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2014, Bernecker+Rainer Industrie-Elektronik Ges.m.b.H. (B&R)
-- Copyright (c) 2014, Kalycito Infotech Private Limited.
--- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--! Use standard ieee library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Use libcommon library
library libcommon;
--! Use Global Library
use libcommon.global.all;
entity axiLiteMasterWrapper is
generic (
--! Address width for AXI bus interface
gAddrWidth : integer := 32;
--! Data width for AXI bus interface
gDataWidth : integer := 32
);
port (
--! Global Clock for AXI
iAclk : in std_logic;
--! Global Reset for AXI
inAReset : in std_logic;
--! Address for Write Address Channel
oAwaddr : out std_logic_vector(gAddrWidth-1 downto 0);
--! Protection for Write Address Channel
oAwprot : out std_logic_vector(2 downto 0);
--! AddressValid for Write Address Channel
oAwvalid : out std_logic;
--! AddressReady for Write Address Channel
iAwready : in std_logic;
--! WriteData for Write Data Channel
oWdata : out std_logic_vector(gDataWidth-1 downto 0);
--! WriteStrobe for Write Data Channel
oWstrb : out std_logic_vector(gDataWidth/8-1 downto 0);
--! WriteValid for Write Data Channel
oWvalid : out std_logic;
--! WriteReady for Write Data Channel
iWready : in std_logic;
--! WriteLast for Write Data Channel to indicate last write operations
oWlast : out std_logic;
--! WriteResponse for Write Response Channel
iBresp : in std_logic_vector(1 downto 0); --unused input
--! ResponseValid for Write Response Channel
iBvalid : in std_logic;
--! ResponaseReady for Write Response Channel
oBready : out std_logic;
--! ReadAddress for Read Address Channel
oAraddr : out std_logic_vector(gAddrWidth-1 downto 0);
--! ReadAddressProtection for Read Address Channel
oArprot : out std_logic_vector(2 downto 0);
--! ReadAddressValid for Read Address Channel
oArvalid : out std_logic;
--! ReadAddressReady for Read Address Channel
iArready : in std_logic;
--! ReadData for Read Data Channel
iRdata : in std_logic_vector(gDataWidth-1 downto 0);
--TODO: Remove unused input pin
--! ReadResponse for Read Data Channel
iRresp : in std_logic_vector(1 downto 0);
--! ReadValid for Read Data Channel
iRvalid : in std_logic;
--! ReadReady for Read Data Channel
oRready : out std_logic;
--! Host Interface IP Clock
iAvalonClk : in std_logic;
--! Host Interface Reset
iAvalonReset : in std_logic;
--! Read signal for Avalon Master Interface
iAvalonRead : in std_logic;
--! Write Signal for Avalon Master interface
iAvalonWrite : in std_logic;
--! Address for Avalon Master Interface
iAvalonAddr : in std_logic_vector(gAddrWidth-1 downto 0);
--! Byte Enable for Avalon Master interface
iAvalonBE : in std_logic_vector(3 downto 0);
--! Wait request for Avalon Master Interface
oAvalonWaitReq : out std_logic;
--! Wait Request for Avalon Master Interface
oAvalonReadValid : out std_logic;
--! Read Data for Avalon Master Interface
oAvalonReadData : out std_logic_vector(gDataWidth-1 downto 0);
--! Write Data for Avaon Master Interface
iAvalonWriteData : in std_logic_vector(gDataWidth-1 downto 0)
);
end axiLiteMasterWrapper;
architecture rtl of axiLiteMasterWrapper is
--! Axi-lite master FSM type
type tFsm is (
sINIT,
sAWVALID,
sWVALID,
sBREADY,
sARVALID,
sRREADY,
sWRITE_DONE,
sREAD_DONE
);
--! synchronized fsm state
signal fsm : tFsm;
--! combinational fsm state
signal fsm_next : tFsm;
--! Avalon Interface sync FSM
type tAvalonFsm is (
sStart,
sWait,
sDone
);
--! synchronized Avalon fsm state
signal avmFsm : tAvalonFsm ;
--! combinational fsm sate for Avalon fsm
signal avmFsm_next : tAvalonFsm ;
--Handle Avalon Master
--! Avalon Address
signal avmAddress : std_logic_vector (31 downto 0);
--! Avalon Address temporary signal
signal avmAddress_next : std_logic_vector (31 downto 0);
--! Avalon Read Signal
signal avmRead : std_logic;
--! Avalon Read Signal temporary signal
signal avmRead_next : std_logic;
--! Avalon Write Signal
signal avmWrite : std_logic;
--! Avalon Write Signal temporary signal
signal avmWrite_next : std_logic;
--! Avalon Write Data
signal avmWdata : std_logic_vector (31 downto 0);
--! Avalon Write Data Signal temporary signal
signal avmWdata_next : std_logic_vector (31 downto 0);
--! Avalon Read Data
signal avmRdata : std_logic_vector (31 downto 0);
--! Avalon Read Data temporary Signal
signal avmRdata_next : std_logic_vector (31 downto 0);
--! Avalon start operation
signal avmStart : std_logic;
--! Avalon start operation temporary signal
signal avmStart_next : std_logic;
--! Avalon Byte Enable
signal avmBE : std_logic_vector (3 downto 0);
--! Avalon Byte Enable Signal temporary signal
signal avmBE_next : std_logic_vector (3 downto 0);
--! Avalon Wait Signal
signal avmWait : std_logic;
-- Handle Avalon Master
--! Complete transfer between AXI and Avalon
signal done_transfer : std_logic;
--! Read Ready for Valid Read operations
signal RReady : std_logic;
--! Write operation complete
signal writeOp_done : std_logic;
--! Read operation complete
signal readOp_done : std_logic;
--! Read Data latch for hold data
signal readData : std_logic_vector(31 downto 0);
begin
--AXI Master Signals
-- Secure write is not enabled for read/write operations
oAwprot <= "000";
oArprot <= "000";
--Master signal for AXI interface
oAwaddr <= avmAddress;
oAraddr <= avmAddress;
oWdata <= avmWdata;
-- Only read or write at a time and Read will always 32bit
oWstrb <= avmBE;
-- Memory operations (AXI4) demands presence of WLAST (active for last data)
oWlast <= cActivated;
oAwvalid <= cActivated when fsm = sINIT and avmWrite = cActivated else
cActivated when fsm = sAWVALID else
cInactivated;
oWvalid <= cActivated when fsm = sINIT and avmWrite = cActivated else
cActivated when fsm = sAWVALID else
cActivated when fsm = sWVALID else
cInactivated;
oBready <= cActivated when fsm = sWRITE_DONE and iBvalid = cActivated else
cActivated when fsm = sBREADY else
cInactivated;
oArvalid <= cActivated when fsm = sINIT and avmRead = cActivated else
cActivated when fsm = sARVALID else
cInactivated;
RReady <= cActivated when fsm = sREAD_DONE and iRvalid = cActivated else
cInactivated;
oRready <= RReady;
-- Flop with Enable pin? Anyway passed through a register on Avalon side to
-- avoid latch issues.
--FIXME: bring into fsm
--! Hold the data while it is valid
REG_RDATA: process(iAclk)
begin
if rising_edge (iAclk) then
if inAReset = cnActivated then
readData <= x"00000000";
elsif(iRvalid = cActivated) then
readData <= iRdata;
end if;
end if;
end process REG_RDATA;
RReady <= cActivated when fsm = sREAD_DONE and iRvalid = cActivated else
cInactivated;
-- Completion of Read/Write Operations
done_transfer <= writeOp_done or readOp_done;
writeOp_done <= cActivated when fsm = sWRITE_DONE else
cInactivated;
readOp_done <= cActivated when fsm = sREAD_DONE else
cInactivated;
-- Master FSM
--TODO: Explain logic if possible with Diagram in doxygen
--! Clock Based Process for tFsm changes
SEQ_LOGIC : process(iAclk)
begin
if rising_edge (iAclk) then
if inAReset = cnActivated then
fsm <= sINIT;
else
fsm <= fsm_next;
end if;
end if;
end process SEQ_LOGIC;
-- Combinational Logics
--TODO: Explain logic if possible with Diagram in doxygen
--! Master FSM for AXI-lite interface
COMB_LOGIC : process (
fsm,
avmRead,
avmWrite,
avmStart,
iAwready,
iWready,
iBvalid,
iArready,
iRvalid
)
begin
-- Default Values for signals
fsm_next <= fsm;
case fsm is
when sINIT =>
-- Read Operations
if avmRead = cActivated then
fsm_next <= sARVALID;
if iArready = cActivated then
if iRvalid = cActivated then
fsm_next <= sREAD_DONE;
else
fsm_next <= sRREADY;
end if;
else
fsm_next <= sARVALID;
end if;
-- Write Operations
elsif avmWrite = cActivated then
fsm_next <= sAWVALID;
if iAwready = cActivated then
if iWready = cActivated then
if iBvalid = cActivated then
fsm_next <= sWRITE_DONE;
else
fsm_next <= sBREADY;
end if;
else
fsm_next <= sWVALID;
end if;
else
fsm_next <= sAWVALID;
end if;
else
fsm_next <= sINIT;
end if;
when sAWVALID =>
if iAwready = cActivated then
if iWready = cActivated then
if iBvalid = cActivated then
fsm_next <= sWRITE_DONE;
else
fsm_next <= sBREADY;
end if;
else
fsm_next <= sWVALID;
end if;
else
fsm_next <= sAWVALID;
end if;
when sWVALID =>
if iWready = cActivated then
if iBvalid = cActivated then
fsm_next <= sWRITE_DONE;
else
fsm_next <= sBREADY;
end if;
else
fsm_next <= sWVALID;
end if;
when sBREADY =>
if iBvalid = cActivated then
fsm_next <= sWRITE_DONE;
else
fsm_next <= sBREADY;
end if;
when sARVALID =>
if iArready = cActivated then
if iRvalid = cActivated then
fsm_next <= sREAD_DONE;
else
fsm_next <= sRREADY;
end if;
else
fsm_next <= sARVALID;
end if;
when sRREADY =>
if iRvalid = cActivated then
fsm_next <= sREAD_DONE;
else
fsm_next <= sRREADY;
end if;
when sWRITE_DONE =>
--Wait for Complete activity at avalon side
if(avmStart = cInactivated) then
fsm_next <= sINIT;
else
fsm_next <= sWRITE_DONE;
end if;
when sREAD_DONE =>
--Wait for Complete activity at avalon side
if(avmStart = cInactivated) then
fsm_next <= sINIT;
else
fsm_next <= sREAD_DONE;
end if;
when others =>
null;
end case;
end process COMB_LOGIC;
-- Avalon Interface signal crossing through FSM Register the inputs from
-- Avalon and Pass to AXI to avoid glitches on Master side due to different
-- clock domains
--! Sync Clock domains between Avalon & AXI through a handshaking system
AVM_SYNC: process (iAvalonClk)
begin
if rising_edge (iAvalonClk) then
if iAvalonReset = cActivated then
avmFsm <= sStart;
avmAddress <= x"00000000";
avmRead <= cInactivated;
avmWrite <= cInactivated;
avmRdata <= x"00000000";
avmWdata <= x"00000000";
avmStart <= cInactivated;
avmBE <= x"0";
else
avmFsm <= avmFsm_next ;
avmAddress <= avmAddress_next;
avmRead <= avmRead_next;
avmWrite <= avmWrite_next;
avmRdata <= avmRdata_next;
avmWdata <= avmWdata_next;
avmStart <= avmStart_next;
avmBE <= avmBE_next;
end if;
end if;
end process AVM_SYNC;
-- Split the design for better timing
--! Combinational logic part for FSM
AVM_COM: process ( iAvalonRead,
iAvalonWrite,
iAvalonWriteData,
iAvalonAddr,
iAvalonBE,
readData,
done_transfer,
avmFsm,
avmRead,
avmWrite,
avmStart,
avmAddress,
avmRdata,
avmWdata,
avmBE
)
begin
--Default/Initialization of temporary registers
avmFsm_next <= avmFsm ;
avmAddress_next <= avmAddress;
avmRead_next <= avmRead;
avmWrite_next <= avmWrite;
avmRdata_next <= avmRdata;
avmWdata_next <= avmWdata;
avmStart_next <= avmStart;
avmBE_next <= avmBE;
case avmFsm is
when sStart =>
avmAddress_next <= iAvalonAddr ;
avmBE_next <= iAvalonBE ;
if iAvalonRead = cActivated then
avmFsm_next <= sWait;
avmStart_next <= cActivated ;
avmRead_next <= cActivated ;
elsif iAvalonWrite = cActivated then
avmFsm_next <= sWait;
avmStart_next <= cActivated ;
avmWrite_next <= cActivated;
avmWdata_next <= iAvalonWriteData;
else
avmFsm_next <= sStart;
avmStart_next <= cInactivated ;
avmRead_next <= cInactivated ;
avmWrite_next <= cInactivated;
avmWdata_next <= x"00000000";
end if;
--Wait until the transfer get completed at AXI
when sWait =>
avmStart_next <= avmStart;
avmRead_next <= avmRead ;
avmWrite_next <= avmWrite;
if(done_transfer = cActivated) then
avmFsm_next <= sDone;
-- Only for Read operations
if(iAvalonRead = cActivated) then
avmRdata_next <= readData;
else
avmRdata_next <= avmRdata;
end if;
else
avmFsm_next <= sWait;
end if;
-- Handshake between two FSM domains
when sDone =>
if (done_transfer = cActivated) then
avmRead_next <= cInactivated ;
avmWrite_next <= cInactivated;
avmStart_next <= cInactivated ;
avmFsm_next <= sStart;
else
avmRead_next <= avmRead ;
avmWrite_next <= avmWrite;
avmStart_next <= avmStart;
avmFsm_next <= sDone;
end if;
end case;
end process AVM_COM;
--Avalon Interface signals
oAvalonReadData <= readData;
oAvalonReadValid <= not avmWait;
oAvalonWaitReq <= avmWait;
avmWait <= cInactivated when avmFsm = sDone else
cActivated ;
end rtl;
| gpl-2.0 | 7233a6b71dfacea28e4be85da9e251a5 | 0.527054 | 5.184232 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/lib/src/synchronizerRtl.vhd | 3 | 3,433 | -------------------------------------------------------------------------------
--! @file synchronizerRtl.vhd
--
--! @brief Synchronizer
--
--! @details This is a synchronizer with configurable stage size.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity synchronizer is
generic (
--! Stages
gStages : natural := 2;
--! Initialization level
gInit : std_logic := cInactivated
);
port (
--! Asynchronous reset
iArst : in std_logic;
--! Clock
iClk : in std_logic;
--! Asynchronous input
iAsync : in std_logic;
--! Synchronous output
oSync : out std_logic
);
end synchronizer;
architecture rtl of synchronizer is
--! Meta registers used to synchronize input signal
signal metaReg : std_logic_vector(gStages-1 downto 0);
--! Meta registers next
signal metaReg_next : std_logic_vector(metaReg'range);
begin
-- handle wrong stage generic
assert (gStages > 0)
report "gStages must be set higher 0!" severity failure;
-- output last synchronizer stage
oSync <= metaReg(metaReg'left);
-- assign asynchronous signal to metaRegisters
metaReg_next <= metaReg(metaReg'left-1 downto 0) & iAsync;
reg : process(iArst, iClk)
begin
if iArst = cActivated then
metaReg <= (others => gInit);
elsif rising_edge(iClk) then
metaReg <= metaReg_next;
end if;
end process;
end rtl;
| gpl-2.0 | ce85faed98edd7a85444c8b06adc6cb5 | 0.633557 | 4.715659 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/hostinterface/src/hostInterfaceRtl.vhd | 2 | 20,402 | -------------------------------------------------------------------------------
--! @file hostInterface.vhd
--
--! @brief toplevel of host interface
--
--! @details The toplevel instantiates the necessary components for the
--! host interface like the Dynamic Bridge and the Status-/Control Registers.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
--! Work library
library work;
--! use host interface package for specific types
use work.hostInterfacePkg.all;
entity hostInterface is
generic (
--! Version major
gVersionMajor : natural := 16#FF#;
--! Version minor
gVersionMinor : natural := 16#FF#;
--! Version revision
gVersionRevision : natural := 16#FF#;
--! Version count
gVersionCount : natural := 0;
--! Use memory blocks or registers for translation address storage (registers = 0, memory blocks /= 0)
gBridgeUseMemBlock : natural := 0;
-- Base address mapping
--! Base address Dynamic Buffer 0
gBaseDynBuf0 : natural := 16#00800#;
--! Base address Dynamic Buffer 1
gBaseDynBuf1 : natural := 16#01000#;
--! Base address Error Counter
gBaseErrCntr : natural := 16#01800#;
--! Base address TX NMT Queue
gBaseTxNmtQ : natural := 16#02800#;
--! Base address TX Generic Queue
gBaseTxGenQ : natural := 16#03800#;
--! Base address TX SyncRequest Queue
gBaseTxSynQ : natural := 16#04800#;
--! Base address TX Virtual Ethernet Queue
gBaseTxVetQ : natural := 16#05800#;
--! Base address RX Virtual Ethernet Queue
gBaseRxVetQ : natural := 16#06800#;
--! Base address Kernel-to-User Queue
gBaseK2UQ : natural := 16#07000#;
--! Base address User-to-Kernel Queue
gBaseU2KQ : natural := 16#09000#;
--! Base address Pdo
gBasePdo : natural := 16#0B000#;
--! Base address Reserved (-1 = high address of Pdo)
gBaseRes : natural := 16#0E000#;
--! Host address width
gHostAddrWidth : natural := 16
);
port (
--! Clock Source input
iClk : in std_logic;
--! Reset Source input
iRst : in std_logic;
-- Memory Mapped Slave for Host
--! MM slave host address
iHostAddress : in std_logic_vector(gHostAddrWidth-1 downto 2);
--! MM slave host byteenable
iHostByteenable : in std_logic_vector(3 downto 0);
--! MM slave host read
iHostRead : in std_logic;
--! MM slave host readdata
oHostReaddata : out std_logic_vector(31 downto 0);
--! MM slave host write
iHostWrite : in std_logic;
--! MM slave host writedata
iHostWritedata : in std_logic_vector(31 downto 0);
--! MM slave host waitrequest
oHostWaitrequest : out std_logic;
-- Memory Mapped Slave for PCP
--! MM slave pcp address
iPcpAddress : in std_logic_vector(10 downto 2);
--! MM slave pcp byteenable
iPcpByteenable : in std_logic_vector(3 downto 0);
--! MM slave pcp read
iPcpRead : in std_logic;
--! MM slave pcp readdata
oPcpReaddata : out std_logic_vector(31 downto 0);
--! MM slave pcp write
iPcpWrite : in std_logic;
--! MM slave pcp writedata
iPcpWritedata : in std_logic_vector(31 downto 0);
--! MM slave pcp waitrequest
oPcpWaitrequest : out std_logic;
-- Memory Mapped Master for Host via Dynamic Bridge
--! MM master hostBridge address
oHostBridgeAddress : out std_logic_vector(29 downto 0);
--! MM master hostBridge byteenable
oHostBridgeByteenable : out std_logic_vector(3 downto 0);
--! MM master hostBridge read
oHostBridgeRead : out std_logic;
--! MM master hostBridge readdata
iHostBridgeReaddata : in std_logic_vector(31 downto 0);
--! MM master hostBridge write
oHostBridgeWrite : out std_logic;
--! MM master hostBridge writedata
oHostBridgeWritedata : out std_logic_vector(31 downto 0);
--! MM master hostBridge waitrequest
iHostBridgeWaitrequest : in std_logic;
--! Interrupt internal sync signal (from openMAC)
iIrqIntSync : in std_logic;
--! External sync source
iIrqExtSync : in std_logic;
--! Interrupt output signal
oIrq : out std_logic
);
end hostInterface;
architecture Rtl of hostInterface is
--! Magic
constant cMagic : natural := 16#504C4B00#;
--! Base address array
constant cBaseAddressArray : tArrayStd32 := (
std_logic_vector(to_unsigned(gBaseDynBuf0, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseDynBuf1, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseErrCntr, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseTxNmtQ, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseTxGenQ, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseTxSynQ, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseTxVetQ, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseRxVetQ, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseK2UQ, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseU2KQ, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBasePdo, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseRes, cArrayStd32ElementSize))
);
--! Base address array count
constant cBaseAddressArrayCount : natural := cBaseAddressArray'length;
--! Base address set by host
constant cBaseAddressHostCount : natural := 2;
--! Base address set by pcp
constant cBaseAddressPcpCount : natural := cBaseAddressArrayCount-cBaseAddressHostCount;
--! Number of interrupt sources (sync not included)
constant cIrqSourceCount : natural := 3;
--! Bridge fsm type
type tFsm is (
sIdle,
sReqAddr,
sAccess,
sDone
);
--! select the bridge logic
signal bridgeSel : std_logic;
--! invalid address range selected
signal invalidSel : std_logic;
--! select status control registers
signal statCtrlSel : std_logic;
--! write status control register
signal statCtrlWrite : std_logic;
--! read status control register
signal statCtrlRead : std_logic;
--! waitrequest from status/control
signal statCtrlWaitrequest : std_logic;
--! readdata from status/control
signal statCtrlReaddata : std_logic_vector(oHostReaddata'range);
--! Bridge request signal
signal bridgeRequest : std_logic;
--! Bridge enable control
signal bridgeEnable : std_logic;
--! Bridge address is valid
signal bridgeAddrValid : std_logic;
--! The magic bridge outputs the dword address
signal hostBridgeAddress_dword : std_logic_vector(oHostBridgeAddress'length-1 downto 2);
--! Bridge transfer done strobe
signal bridgeTfDone : std_logic;
--! Bridge read data
signal bridgeReaddata : std_logic_vector(iHostBridgeReaddata'range);
--! Bridge state machine
signal fsm : tFsm;
--! Bridge state machine, next state
signal fsm_next : tFsm;
-- base set signals
--! BaseSet Write
signal baseSetWrite : std_logic;
--! BaseSet Read
signal baseSetRead : std_logic;
--! BaseSet byteenable
signal baseSetByteenable : std_logic_vector(3 downto 0);
--! BaseSet Writedata
signal baseSetWritedata : std_logic_vector(hostBridgeAddress_dword'range);
--! BaseSet Readdata
signal baseSetReaddata : std_logic_vector(hostBridgeAddress_dword'range);
--! BaseSet Address
signal baseSetAddress : std_logic_vector(logDualis(cBaseAddressArrayCount)-1 downto 0);
--! BaseSet acknowledge
signal baseSetAck : std_logic;
-- interrupt signals
--! Irq master enable
signal irqMasterEnable : std_logic;
--! Irq source enable
signal irqSourceEnable : std_logic_vector(cIrqSourceCount downto 0);
--! Irq acknowledge
signal irqAcknowledge : std_logic_vector(cIrqSourceCount downto 0);
--! Irq source pending
signal irqSourcePending : std_logic_vector(cIrqSourceCount downto 0);
--! Irq source set (no sync!)
signal irqSourceSet : std_logic_vector(cIrqSourceCount downto 1);
--! sync signal
signal syncSig : std_logic;
--! synchronized ext sync
signal extSync_sync : std_logic;
--! external sync signal
signal extSyncEnable : std_logic;
--! external sync config
signal extSyncConfig : std_logic_vector(cExtSyncEdgeConfigWidth-1 downto 0);
--! external sync signal detected rising edge
signal extSync_rising : std_logic;
--! external sync signal detected falling edge
signal extSync_falling : std_logic;
--! external sync signal detected any edge
signal extSync_any : std_logic;
begin
assert (2**gHostAddrWidth-1 >= gBaseRes-1)
report "The host side high address cannot be addressed! Increase gHostAddrWidth generic!"
severity failure;
-- select status/control registers if host address is below 2 kB
statCtrlSel <= cActivated when iHostAddress < cBaseAddressArray(0)(iHostAddress'range) else
cInactivated;
-- select invalid address
invalidSel <= cActivated when iHostAddress >= cBaseAddressArray(cBaseAddressArrayCount-1)(iHostAddress'range) else
cInactivated;
-- bridge is selected if status/control registers are not accessed
bridgeSel <= cInactivated when bridgeEnable = cInactivated else
cInactivated when invalidSel = cActivated else
cInactivated when statCtrlSel = cActivated else
cActivated;
-- create write and read strobe for status/control registers
statCtrlWrite <= iHostWrite and statCtrlSel;
statCtrlRead <= iHostRead and statCtrlSel;
-- host waitrequest from status/control, bridge or invalid
oHostWaitrequest <= statCtrlWaitrequest when statCtrlSel = cActivated else
not (iHostWrite or iHostRead) when invalidSel = cActivated else
cInactivated when bridgeEnable = cInactivated else
not bridgeTfDone when bridgeSel = cActivated else
cActivated;
-- host readdata from status/control or bridge
oHostReaddata <= bridgeReaddata when bridgeSel = cActivated else
statCtrlReaddata when statCtrlSel = cActivated else
(others => cInactivated);
-- select external sync if enabled, otherwise rx irq signal
syncSig <= iIrqIntSync when extSyncEnable /= cActivated else
extSync_rising when extSyncConfig = cExtSyncEdgeRis else
extSync_falling when extSyncConfig = cExtSyncEdgeFal else
extSync_any when extSyncConfig = cExtSyncEdgeAny else
cInactivated;
--! The bridge state machine handles the address translation of
--! dynamicBridge and finalizes the access to the host bridge master.
theFsmCom : process (
fsm,
bridgeSel,
bridgeAddrValid,
iHostRead,
iHostWrite,
iHostBridgeWaitrequest
)
begin
--default
fsm_next <= fsm;
case fsm is
when sIdle =>
if ( (iHostRead = cActivated or iHostWrite = cActivated) and
bridgeSel = cActivated) then
fsm_next <= sReqAddr;
end if;
when sReqAddr =>
if bridgeAddrValid = cActivated then
fsm_next <= sAccess;
end if;
when sAccess =>
if iHostBridgeWaitrequest = cInactivated then
fsm_next <= sDone;
end if;
when sDone =>
fsm_next <= sIdle;
end case;
end process;
bridgeRequest <= cActivated when fsm = sReqAddr else cInactivated;
bridgeTfDone <= cActivated when fsm = sDone else cInactivated;
--! Clock process to assign registers.
theClkPro : process(iRst, iClk)
begin
if iRst = cActivated then
fsm <= sIdle;
oHostBridgeAddress <= (others => cInactivated);
oHostBridgeByteenable <= (others => cInactivated);
oHostBridgeRead <= cInactivated;
oHostBridgeWrite <= cInactivated;
oHostBridgeWritedata <= (others => cInactivated);
elsif rising_edge(iClk) then
fsm <= fsm_next;
if iHostBridgeWaitrequest = cInactivated then
oHostBridgeRead <= cInactivated;
oHostBridgeWrite <= cInactivated;
bridgeReaddata <= iHostBridgeReaddata;
end if;
if bridgeAddrValid = cActivated then
oHostBridgeAddress <= hostBridgeAddress_dword & "00";
oHostBridgeByteenable <= iHostByteenable;
oHostBridgeRead <= iHostRead;
oHostBridgeWrite <= iHostWrite;
oHostBridgeWritedata <= iHostWritedata;
end if;
end if;
end process;
--! The synchronizer which protects us from crazy effects!
theSynchronizer : entity libcommon.synchronizer
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iArst => iRst,
iClk => iClk,
iAsync => iIrqExtSync,
oSync => extSync_sync
);
--! The Edge Detector for external sync
theExtSyncEdgeDet : entity libcommon.edgedetector
port map (
iArst => iRst,
iClk => iClk,
iEnable => cActivated,
iData => extSync_sync,
oRising => extSync_rising,
oFalling => extSync_falling,
oAny => extSync_any
);
--! The Dynamic Bridge
theDynamicBridge : entity work.dynamicBridge
generic map (
gAddressSpaceCount => cBaseAddressArrayCount-1,
gUseMemBlock => gBridgeUseMemBlock,
gBaseAddressArray => cBaseAddressArray
)
port map (
iClk => iClk,
iRst => iRst,
iBridgeAddress => iHostAddress,
iBridgeRequest => bridgeRequest,
oBridgeAddress => hostBridgeAddress_dword,
oBridgeSelectAny => open,
oBridgeSelect => open,
oBridgeValid => bridgeAddrValid,
iBaseSetWrite => baseSetWrite,
iBaseSetRead => baseSetRead,
iBaseSetByteenable => baseSetByteenable,
iBaseSetAddress => baseSetAddress,
iBaseSetData => baseSetWritedata,
oBaseSetData => baseSetReaddata,
oBaseSetAck => basesetAck
);
--! The Irq Generator
theIrqGen : entity work.irqGen
generic map (
gIrqSourceCount => cIrqSourceCount
)
port map (
iClk => iClk,
iRst => iRst,
iSync => syncSig,
iIrqSource => irqSourceSet,
oIrq => oIrq,
iIrqMasterEnable => irqMasterEnable,
iIrqSourceEnable => irqSourceEnable,
iIrqAcknowledge => irqAcknowledge,
oIrgPending => irqSourcePending
);
--! The Status-/Control Registers
theStCtrlReg : entity work.statusControlReg
generic map (
gMagic => cMagic,
gVersionMajor => gVersionMajor,
gVersionMinor => gVersionMinor,
gVersionRevision => gVersionRevision,
gVersionCount => gVersionCount,
gHostBaseSet => cBaseAddressHostCount,
gPcpBaseSet => cBaseAddressPcpCount,
gIrqSourceCount => cIrqSourceCount
)
port map (
iClk => iClk,
iRst => iRst,
iHostRead => statCtrlRead,
iHostWrite => statCtrlWrite,
iHostByteenable => iHostByteenable,
iHostAddress => iHostAddress(10 downto 2),
oHostReaddata => statCtrlReaddata,
iHostWritedata => iHostWritedata,
oHostWaitrequest => statCtrlWaitrequest,
iPcpRead => iPcpRead,
iPcpWrite => iPcpWrite,
iPcpByteenable => iPcpByteenable,
iPcpAddress => iPcpAddress,
oPcpReaddata => oPcpReaddata,
iPcpWritedata => iPcpWritedata,
oPcpWaitrequest => oPcpWaitrequest,
oBaseSetWrite => baseSetWrite,
oBaseSetRead => baseSetRead,
oBaseSetByteenable => baseSetByteenable,
oBaseSetAddress => baseSetAddress,
iBaseSetData => baseSetReaddata,
oBaseSetData => baseSetWritedata,
iBaseSetAck => basesetAck,
oIrqMasterEnable => irqMasterEnable,
oIrqSourceEnable => irqSourceEnable,
oIrqAcknowledge => irqAcknowledge,
oIrqSet => irqSourceSet,
iIrqPending => irqSourcePending,
oExtSyncEnable => extSyncEnable,
oExtSyncConfig => extSyncConfig,
oBridgeEnable => bridgeEnable
);
end Rtl;
| gpl-2.0 | 6cb351cfd12d609d67005c306f25f985 | 0.588129 | 5.263674 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/lib/src/lutFileRtl.vhd | 3 | 3,382 | -------------------------------------------------------------------------------
--! @file lutFileRtl.vhd
--
--! @brief Look-up table file implementation
--
--! @details This look-up table file stores initialization values (generics)
--! in LUT resources.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity lutFile is
generic (
gLutCount : natural := 4;
gLutWidth : natural := 32;
gLutInitValue : std_logic_vector :=
x"1111_1111" & x"2222_2222" & x"3333_3333" & x"4444_4444"
);
port (
iAddrRead : in std_logic_vector(LogDualis(gLutCount)-1 downto 0);
oData : out std_logic_vector
);
end lutFile;
architecture Rtl of lutFile is
constant cLutFile : std_logic_vector(gLutCount*gLutWidth-1 downto 0) :=
gLutInitValue;
signal lutOutput : std_logic_vector(gLutWidth-1 downto 0);
begin
--Lut File is a bitstream that is blockwise (gLutWidth) read with
--respect to iAddrRead.
bitSelect : process(iAddrRead)
begin
--default
lutOutput <= (others => '0');
for i in gLutWidth-1 downto 0 loop
--assign selected bits in Lut File to output
lutOutput(i) <= cLutFile
( (gLutCount-1-to_integer(unsigned(iAddrRead)))*gLutWidth + i );
end loop;
end process;
--! downscale lut width to output
oData <= lutOutput(oData'range);
end Rtl;
| gpl-2.0 | edcaa1829b17d89e0197fbd7e000908e | 0.63217 | 4.363871 | false | false | false | false |
cnplab/blockmon | fw-combo/src/common/simple_fifo.vhd | 1 | 3,260 | -- -----------------------------------------------------------------
-- Simple synchronous FIFO
-- -----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity SIMPLE_FIFO is
generic (
DATA_WIDTH : integer := 64;
DEPTH : integer := 512
);
port (
-- global FPGA clock
CLK : in std_logic;
-- global synchronous reset
RESET : in std_logic;
-- Write interface
DATA_IN : in std_logic_vector(DATA_WIDTH-1 downto 0);
WRITE_EN : in std_logic;
-- Read interface
DATA_OUT : out std_logic_vector(DATA_WIDTH-1 downto 0);
READ_EN : in std_logic;
-- Control
STATE_FULL : out std_logic;
STATE_EMPTY : out std_logic
);
end entity SIMPLE_FIFO;
architecture behavioral of SIMPLE_FIFO is
-- -----------------------------------------------------------------
-- Signals
-- -----------------------------------------------------------------
type ram_type is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal fifo : ram_type;
signal read_ptr : integer range 0 to DEPTH-1;
signal write_ptr : integer range 0 to DEPTH-1;
signal depth_cur : integer range 0 to DEPTH;
begin
-- -----------------------------------------------------------------
-- Logic
-- -----------------------------------------------------------------
-- FIFO read and write
process(CLK)
begin
if (CLK'event and CLK = '1') then
if (RESET = '1') then
write_ptr <= 0;
read_ptr <= 0;
DATA_OUT <= (others => '0');
else
-- Read in the FIFO
if (read_en = '1') then
data_out <= fifo(read_ptr);
-- Increment the pointer
if (read_ptr < DEPTH - 1) then
read_ptr <= read_ptr + 1;
else
read_ptr <= 0;
end if;
end if;
-- Write in the FIFO
if (write_en = '1') then
fifo(write_ptr) <= data_in;
-- Increment the pointer
if (write_ptr < DEPTH - 1) then
write_ptr <= write_ptr + 1;
else
write_ptr <= 0;
end if;
end if;
end if;
end if;
end process;
-- FIFO depth management
process(CLK)
begin
if (CLK'event and CLK = '1') then
if (RESET = '1') then
depth_cur <= 0;
else
if (write_en = '1' and read_en = '0') then
depth_cur <= depth_cur + 1;
elsif (write_en = '0' and read_en = '1') then
depth_cur <= depth_cur - 1;
end if;
end if;
end if;
end process;
-- FIFO full/empty
STATE_FULL <= '1' when (depth_cur >= DEPTH) else '0';
STATE_EMPTY <= '1' when (depth_cur <= 0) else '0';
end;
| bsd-3-clause | 5b51d5dcf2302d644c3f8ef3a174fa02 | 0.398773 | 4.559441 | false | false | false | false |
cnplab/blockmon | fw-combo/src/IPFIX/comp/fl_transformer_up.vhd | 1 | 9,370 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- transformer_up.vhd: Implementation of UP architecture of FrameLink
-- Transformer component.
-- Copyright (C) 2006 CESNET
-- Author(s): Martin Louda <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: transformer_up.vhd 6605 2008-12-26 11:55:34Z xlenga00 $
--
-- TODO:
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- library containing log2 function
use work.math_pack.all;
-- ------------------------------------------------------------------------
-- Entity declaration
-- ------------------------------------------------------------------------
entity FL_TRANSFORMER_UP is
generic(
-- FrameLink data buses width
-- only 8, 16, 32, 64 and 128 supported
-- !! RX_DATA_WIDTH < TX_DATA_WIDTH !!
RX_DATA_WIDTH : integer;
TX_DATA_WIDTH : integer
);
port(
CLK : in std_logic;
RESET : in std_logic;
-- RX interface
RX_DATA : in std_logic_vector(RX_DATA_WIDTH-1 downto 0);
RX_REM : in std_logic_vector(max(log2(RX_DATA_WIDTH/8)-1, 0) downto 0);
RX_SOF_N : in std_logic;
RX_EOF_N : in std_logic;
RX_SOP_N : in std_logic;
RX_EOP_N : in std_logic;
RX_SRC_RDY_N : in std_logic;
RX_DST_RDY_N : out std_logic;
-- TX interface
TX_DATA : out std_logic_vector(TX_DATA_WIDTH-1 downto 0);
TX_REM : out std_logic_vector(log2(TX_DATA_WIDTH/8)-1 downto 0);
TX_SOF_N : out std_logic;
TX_EOF_N : out std_logic;
TX_SOP_N : out std_logic;
TX_EOP_N : out std_logic;
TX_SRC_RDY_N : out std_logic;
TX_DST_RDY_N : in std_logic
);
end entity FL_TRANSFORMER_UP;
-- ------------------------------------------------------------------------
-- Architecture declaration
-- ------------------------------------------------------------------------
architecture full_up of FL_TRANSFORMER_UP is
constant bytes_cnt : integer := (TX_DATA_WIDTH/RX_DATA_WIDTH);
signal data_strobe : std_logic;
signal dst_rdy : std_logic;
signal lblk : std_logic;
signal flag_sop : std_logic;
signal flag_sof : std_logic;
signal flag_run : std_logic;
signal act_byte : std_logic_vector(log2(TX_DATA_WIDTH/RX_DATA_WIDTH) downto 0);
signal reg_data : std_logic_vector(TX_DATA_WIDTH-RX_DATA_WIDTH-1 downto 0) := (others => '0');
begin
assert (RX_DATA_WIDTH < TX_DATA_WIDTH)
report "FL_TRANSFORMER: Bad use of UP architecture - RX_DATA_WIDTH must be smaller than TX_DATA_WIDTH."
severity error;
-- output ports
TX_EOP_N <= RX_EOP_N or RX_SRC_RDY_N;
TX_EOF_N <= RX_EOF_N or RX_SRC_RDY_N;
TX_SOP_N <= not (lblk and ((not RX_SOP_N) or flag_sop));
TX_SOF_N <= not (lblk and ((not RX_SOF_N) or flag_sof));
RX_DST_RDY_N <= not dst_rdy;
TX_SRC_RDY_N <= not lblk;
txrem_gt8_gen: if RX_DATA_WIDTH > 8 generate
TX_REM <= conv_std_logic_vector((conv_integer(act_byte)-1)*RX_DATA_WIDTH/8
+ conv_integer(RX_REM), log2(TX_DATA_WIDTH/8))
when (lblk = '1')
else (others => '0');
end generate txrem_gt8_gen;
txrem8_gen: if RX_DATA_WIDTH = 8 generate
TX_REM <= conv_std_logic_vector(conv_integer(act_byte-1), log2(TX_DATA_WIDTH/8));
end generate txrem8_gen;
data_strobe <= dst_rdy and (not RX_SRC_RDY_N);
dst_rdy <= (not lblk) or (not TX_DST_RDY_N)
when (flag_run = '1') or (lblk = '1')
else not TX_DST_RDY_N;
-- ---------------------------------------------------------------------
-- Main logic
-- ---------------------------------------------------------------------
lblk <= '1'
when ((RX_EOP_N = '0') or (conv_integer(act_byte) = bytes_cnt)) and (RX_SRC_RDY_N = '0')
else '0';
act_bytep: process(RESET, CLK)
begin
if (CLK'event AND CLK = '1') then
if (RESET = '1') then
act_byte <= conv_std_logic_vector(1, log2(TX_DATA_WIDTH/RX_DATA_WIDTH)+1);
else
if ((TX_DST_RDY_N = '0') and (RX_SRC_RDY_N = '0')) then
if (lblk = '1') then
act_byte <= conv_std_logic_vector(1, log2(TX_DATA_WIDTH/RX_DATA_WIDTH)+1);
else
act_byte <= act_byte + 1;
end if;
end if;
end if;
end if;
end process;
-- output data shifting logic
GEN_TX_DATA: for i in (TX_DATA_WIDTH/RX_DATA_WIDTH)-1 downto 0 generate
process(reg_data, RX_DATA, lblk, act_byte)
begin
if (lblk = '1') then
if (conv_integer(act_byte) = i+1) then
TX_DATA((RX_DATA_WIDTH*(i+1))-1 downto RX_DATA_WIDTH*i) <= RX_DATA;
elsif (i = (TX_DATA_WIDTH/RX_DATA_WIDTH)-1) then
TX_DATA((RX_DATA_WIDTH*(i+1))-1 downto RX_DATA_WIDTH*i) <= (others => '0');
else
TX_DATA((RX_DATA_WIDTH*(i+1))-1 downto RX_DATA_WIDTH*i) <= reg_data((RX_DATA_WIDTH*(i+1))-1 downto RX_DATA_WIDTH*i);
end if;
else
TX_DATA((RX_DATA_WIDTH*(i+1))-1 downto RX_DATA_WIDTH*i) <= (others => '0');
end if;
end process;
end generate;
-- ---------------------------------------------------------------------
-- Registers
-- ---------------------------------------------------------------------
flag_sopp: process(RESET, CLK)
begin
if (CLK'event AND CLK = '1') then
if (RESET = '1') then
flag_sop <= '0';
else
if (lblk = '1' and TX_DST_RDY_N = '0') then
flag_sop <= '0';
elsif (RX_SOP_N = '0' and RX_SRC_RDY_N = '0') then
flag_sop <= '1';
end if;
end if;
end if;
end process;
flag_sofp: process(RESET, CLK)
begin
if (CLK'event AND CLK = '1') then
if (RESET = '1') then
flag_sof <= '0';
else
if (lblk = '1' and TX_DST_RDY_N = '0') then
flag_sof <= '0';
elsif (RX_SOF_N = '0' and RX_SRC_RDY_N = '0') then
flag_sof <= '1';
end if;
end if;
end if;
end process;
flag_runp: process(RESET, CLK)
begin
if (CLK'event AND CLK = '1') then
if (RESET = '1') then
flag_run <= '0';
else
if (RX_EOF_N = '1' and RX_SRC_RDY_N = '0') then
flag_run <= '0';
elsif (RX_SOF_N = '0' AND RX_EOF_N = '0' AND RX_SRC_RDY_N = '0') then
flag_run <= '0';
elsif (RX_SOF_N = '0' and RX_SRC_RDY_N = '0') then
flag_run <= '1';
end if;
end if;
end if;
end process;
-- output data registers
GEN_DATA:
for i in 0 to (TX_DATA_WIDTH/RX_DATA_WIDTH)-2 generate
process(CLK)
begin
if (CLK'event AND CLK = '1') then
if ((data_strobe = '1') and (conv_integer(act_byte)-1 = i)) then
reg_data(((i+1)*RX_DATA_WIDTH)-1 downto i*RX_DATA_WIDTH) <= RX_DATA;
end if;
end if;
end process;
end generate;
end architecture full_up;
| bsd-3-clause | 5e65673e7f14b46d74df922787270c27 | 0.521451 | 3.601076 | false | false | false | false |
ARC-Lab-UF/window_gen | src/wg_fifo_edge_control.vhd | 1 | 5,885 | -- Copyright (c) University of Florida
--
-- This file is part of window_gen.
--
-- window_gen is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- window_gen is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with window_gen. If not, see <http://www.gnu.org/licenses/>.
-- Greg Stitt
-- University of Florida
-- Description: This entity maintains the FIFO pointers for a
-- an array of FIFOs in the window buffer. The front pointer always
-- points to the FIFO that stores the top row of window pixels, while the back
-- pointer always points to the FIFO with the bottom row. Every time the window
-- slides down one row these pointers are updated to ensure correct windows.
--
-- This entity tracks the number of times that a current row has been read in
-- order to determine when the window has reached the end of a row, which
-- determines when the pointers should be updated. The entity also determines
-- when the current reads represent the start (left edge_ of a window (is_edge).
-- For example, the generator only produces fully immersed windows, so pixels
-- towards the end of a will never form the left edge of a window.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
use work.math_custom.all;
-------------------------------------------------------------------------------
-- Generics Description
-- PARALLEL_IO : Specifies the number of inputs and outputs provided at a time,
-- DATA_WIDTH : The width in bits of each element.
-- MAX_WINDOW_ROWS : The maximum number of rows in a generated window
-- MAX_IMAGE_COLS : The maximum number of cols in an input image/stream
-- MAX_BUFFER_SIZE : The maximum size/words of each FIFO
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Port Descriptions (all control signals are active high)
-- clk: clock
-- rst: asynchronous reset
-- en : '1' to enable
-- edge : pointer to a FIFO
-- changed : asserted when the edge changes
-- is_window_edge : '1' if the current pointer value is the edge of a window.
-- One bit for each PARALLEL_IO element, which the first at
-- the MSB and the last at the LSB.
-- buffer_size : The actual size of the FIFO buffers
-- window_per_row : The number of windows generated from each image row
-------------------------------------------------------------------------------
entity wg_fifo_edge_control is
generic (
PARALLEL_IO : positive;
MAX_BUFFER_SIZE : positive;
MAX_WINDOW_ROWS : positive;
MAX_IMAGE_COLS : positive);
port (
clk : in std_logic;
rst : in std_logic;
en : in std_logic;
edge : out unsigned(bitsNeeded(MAX_WINDOW_ROWS-1)-1 downto 0);
changed : out std_logic;
is_window_edge : out std_logic_vector(PARALLEL_IO-1 downto 0);
buffer_size : in std_logic_vector(bitsNeeded(MAX_BUFFER_SIZE)-1 downto 0);
windows_per_row : in std_logic_vector(bitsNeeded(MAX_IMAGE_COLS)-1 downto 0));
end wg_fifo_edge_control;
architecture BHV of wg_fifo_edge_control is
signal count, next_count : integer range 0 to MAX_BUFFER_SIZE;
signal addr, next_addr : unsigned(bitsNeeded(MAX_WINDOW_ROWS-1)-1 downto 0);
begin
-- registers
process(clk, rst)
begin
if (rst = '1') then
count <= 0;
addr <= (others => '0');
elsif (clk = '1' and clk'event) then
count <= next_count;
addr <= next_addr;
end if;
end process;
-- combinational logic
process(en, count, addr, buffer_size)
variable temp_count : integer range 0 to MAX_BUFFER_SIZE;
begin
-- count inputs
if (en = '1') then
temp_count := count + 1;
else
temp_count := count;
end if;
-- if at the end of a row, update the edge to point to a new fifo
if (temp_count >= unsigned(buffer_size)) then
-- addr passes last FIFO, reset to first FIFO, otherwise increment addr
if (addr = MAX_WINDOW_ROWS-1) then
next_addr <= (others => '0');
else
next_addr <= addr + 1;
end if;
-- edge changes anytime an entire row has been read
changed <= '1';
--temp_count := (others => '0');
temp_count := 0;
else
-- if still processing a row, don't change anything
changed <= '0';
next_addr <= addr;
end if;
next_count <= temp_count;
end process;
-- determine if the next PARALLEL_IO elements are the leftmost edge of a
-- generated window
process(count, windows_per_row)
begin
for i in 0 to PARALLEL_IO-1 loop
-- each count value corresponds to PARALLEL_IO elements
if (count*PARALLEL_IO+i < unsigned(windows_per_row)) then
is_window_edge(PARALLEL_IO-1-i) <= '1';
else
is_window_edge(PARALLEL_IO-1-i) <= '0';
end if;
end loop;
end process;
edge <= addr;
end BHV;
| gpl-3.0 | a0c7659df79ee751b9e029bfefff2d07 | 0.57723 | 4.144366 | false | false | false | false |
cnplab/blockmon | fw-combo/src/netcope-sim/models/ib_bfm.vhd | 1 | 33,178 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
--
-- ib_sim.vhd: Simulation component for internal bus
-- Copyright (C) 2006 CESNET
-- Author(s): Petr Kobiersky <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: ib_bfm.vhd 15096 2011-10-27 13:04:03Z kastovsky $
--
-- TODO:
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.math_pack.all;
use work.ib_pkg.all;
use work.ib_bfm_pkg.all;
use work.ib_bfm_rdy_pkg.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
ENTITY IB_BFM IS
GENERIC (
MEMORY_BASE_ADDR : std_logic_vector(63 downto 0) := X"FFFFFFFF00000000"; -- Memory Base ADDR
MEMORY_SIZE : integer := 1024; -- Defaul 1024 Bytes
MEMORY_DELAY : integer := 10 -- Delay before sending completition
);
PORT (
CLK : in std_logic;
-- Internal Bus Interface
IB_DOWN_DATA : out std_logic_vector(63 downto 0);
IB_DOWN_SOF_N : out std_logic;
IB_DOWN_EOF_N : out std_logic;
IB_DOWN_SRC_RDY_N : out std_logic;
IB_DOWN_DST_RDY_N : in std_logic;
IB_UP_DATA : in std_logic_vector(63 downto 0);
IB_UP_SOF_N : in std_logic;
IB_UP_EOF_N : in std_logic;
IB_UP_SRC_RDY_N : in std_logic;
IB_UP_DST_RDY_N : out std_logic
-- IB : inout t_internal_bus64
);
END ENTITY IB_BFM;
-- ----------------------------------------------------------------------------
-- Architecture declaration
-- ----------------------------------------------------------------------------
ARCHITECTURE IB_BFM_ARCH OF IB_BFM IS
SIGNAL aux_ib_up_dst_rdy_n : std_logic;
-- Request for completition
SIGNAL ComplReq : IbCmdType := ('0', 'Z', 'Z');
SHARED VARIABLE ComplDataCmdV : IbCmdVType;
-- Transactions
SHARED VARIABLE LclIbCmdV : IbCmdVType;
SHARED VARIABLE LclIbCmdVReceive : IbCmdVType;
-- Host Memory
TYPE MemoryType IS ARRAY (0 TO MEMORY_SIZE/8) of std_logic_vector(63 downto 0);
SHARED VARIABLE Memory : MemoryType;
-- Logging settings
SHARED VARIABLE LogTranscript : boolean := true;
SHARED VARIABLE LogFile : boolean := false;
-- Write Align Type
TYPE WriteAlignType IS
RECORD
Align : integer;
AlignReg : std_logic_vector(63 downto 0);
END RECORD;
----------------------------------------------------------------------------
-- Completition FIFO for G2LR
CONSTANT FIFO_LEN : integer := 256;
TYPE FifoType IS ARRAY (0 TO FIFO_LEN-1) of IbCmdVType;
TYPE CompletitionFifoType IS
RECORD
BeginPtr : integer;
EndPtr : integer;
Items : integer;
Empty : boolean;
Fifo : FifoType;
END RECORD;
SHARED VARIABLE ComplFifo : CompletitionFifoType;
-- -------------------------------------------------------------------------
PROCEDURE InitFifo IS
BEGIN
ComplFifo.EndPtr := 0;
ComplFifo.BeginPtr := 0;
ComplFifo.Empty := true;
ComplFifo.Items := 0;
END PROCEDURE;
-- -------------------------------------------------------------------------
PROCEDURE insertFifo(input : IN IbCmdVType) IS
BEGIN
ComplFifo.Fifo(ComplFifo.EndPtr) := input;
ComplFifo.EndPtr := ComplFifo.EndPtr+1;
ComplFifo.Items := ComplFifo.Items+1;
if (ComplFifo.EndPtr = FIFO_LEN) then
ComplFifo.EndPtr := 0;
end if;
ComplFifo.Empty := false;
ASSERT (ComplFifo.EndPtr /= ComplFifo.BeginPtr or ComplFifo.Items=0)
REPORT "IB_BFM: Completition fifo overflow";
END PROCEDURE;
-- -------------------------------------------------------------------------
PROCEDURE getFifo(output : INOUT IbCmdVType) IS
BEGIN
if (not ComplFifo.Empty) then
output:=ComplFifo.Fifo(ComplFifo.BeginPtr);
ComplFifo.BeginPtr := ComplFifo.BeginPtr + 1;
if (ComplFifo.BeginPtr = FIFO_LEN) then
ComplFifo.BeginPtr := 0;
end if;
ComplFifo.Items:=ComplFifo.Items-1;
ComplFifo.Empty:=ComplFifo.BeginPtr=ComplFifo.EndPtr;
end if;
END PROCEDURE;
-- -------------------------------------------------------------------------
PROCEDURE to_bit_vector(input : IN std_logic_vector;
output : OUT bit_vector) IS
VARIABLE i : integer;
BEGIN
for i in 0 to input'high loop
if (input(i) = '1') then
output(i) := '1';
else
output(i) := '0';
end if;
end loop;
END PROCEDURE;
-- -------------------------------------------------------------------------
-- ShowCommand Info
PROCEDURE ShowCommandInfo(cmdV : IN IbCmdVType; info : in string) IS
VARIABLE i : integer;
VARIABLE buf : LINE;
file output : TEXT open write_mode is "STD_OUTPUT";
file outfile : TEXT open append_mode is "internal_bus.log";
BEGIN
if (LogTranscript) then
CASE cmdV.CmdOp IS
WHEN LocalRead =>
write(buf, string'("IB_BFM: ")); write(buf, info); write(buf, string'(" Local2Local Read: "));
write(buf, string'(" Src Addr: 0x")); hwrite(buf, cmdV.Di.SrcAddr);
write(buf, string'(" Dst Addr: 0x")); hwrite(buf, cmdV.Di.DstAddr);
write(buf, string'(" Tag: ")); write(buf, cmdV.Di.Tag);
write(buf, string'(" Length: ")); write(buf, cmdV.Di.Length);
writeline(output, buf);
WHEN LocalWrite =>
write(buf, string'("IB_BFM: ")); write(buf, info); write(buf, string'(" Local2Local Write: "));
write(buf, string'(" Dst Addr: 0x")); hwrite(buf, cmdV.Di.DstAddr);
write(buf, string'(" Src Addr: 0x")); hwrite(buf, cmdV.Di.SrcAddr);
write(buf, string'(" Tag: ")); write(buf, cmdV.Di.Tag);
write(buf, string'(" Length: ")); write(buf, cmdV.Di.Length);
writeline(output, buf);
i:= 0;
while i < cmdV.Di.Length loop
write(buf,string'(" DATA: 0x")); hwrite(buf, cmdV.di.Data(i/8));
writeline(output, buf);
i:=i+8;
end loop;
WHEN Completition =>
write(buf, string'("IB_BFM: ")); write(buf, info); write(buf, string'(" Completition: "));
write(buf, string'(" Dst Addr: 0x")); hwrite(buf, cmdV.Di.DstAddr);
write(buf, string'(" Src Addr: 0x")); hwrite(buf, cmdV.Di.SrcAddr);
write(buf, string'(" Tag: ")); write(buf, cmdV.Di.Tag);
write(buf, string'(" Length: ")); write(buf, cmdV.Di.Length);
write(buf, string'(" LastFlag: ")); write(buf, cmdV.Di.LastFlag);
writeline(output, buf);
i:= 0;
while i < cmdV.Di.Length loop
write(buf,string'(" DATA: 0x")); hwrite(buf, cmdV.di.Data(i/8));
writeline(output, buf);
i:=i+8;
end loop;
WHEN G2LR =>
write(buf, string'("IB_BFM: ")); write(buf, info); write(buf, string'(" Global2Local Read: "));
write(buf, string'(" Dst Addr: 0x")); hwrite(buf, cmdV.Di.DstAddr);
write(buf, string'(" Src Addr: 0x")); hwrite(buf, cmdV.Di.SrcAddr);
write(buf, string'(" Tag: ")); write(buf, cmdV.Di.Tag);
write(buf, string'(" Length: ")); write(buf, cmdV.Di.Length);
writeline(output, buf);
WHEN L2GW =>
write(buf, string'("IB_BFM: ")); write(buf, info); write(buf, string'(" Local2Global Write: "));
write(buf, string'(" GlobalAddr: 0x"));hwrite(buf, cmdV.Di.DstAddr);
write(buf, string'(" LocalAddr: 0x")); hwrite(buf, cmdV.Di.SrcAddr);
write(buf, string'(" Tag: ")); write(buf, cmdV.Di.Tag);
write(buf, string'(" Length: ")); write(buf, cmdV.Di.Length);
writeline(outfile, buf);
i:= 0;
while i < cmdV.Di.Length loop
write(buf,string'(" DATA: 0x")); hwrite(buf, cmdV.di.Data(i/8));
writeline(output, buf);
i:=i+8;
end loop;
WHEN others =>
END CASE;
end if;
if (LogFile) then
CASE cmdV.CmdOp IS
WHEN LocalRead =>
write(buf, string'("IB_BFM: ")); write(buf, info); write(buf, string'(" Local2Local Read: "));
write(buf, string'(" Src Addr: 0x")); hwrite(buf, cmdV.Di.SrcAddr);
write(buf, string'(" Dst Addr: 0x")); hwrite(buf, cmdV.Di.DstAddr);
write(buf, string'(" Tag: ")); write(buf, cmdV.Di.Tag);
write(buf, string'(" Length: ")); write(buf, cmdV.Di.Length);
writeline(outfile, buf);
WHEN LocalWrite =>
write(buf, string'("IB_BFM: ")); write(buf, info); write(buf, string'(" Local2Local Write: "));
write(buf, string'(" Dst Addr: 0x")); hwrite(buf, cmdV.Di.DstAddr);
write(buf, string'(" Src Addr: 0x")); hwrite(buf, cmdV.Di.SrcAddr);
write(buf, string'(" Tag: ")); write(buf, cmdV.Di.Tag);
write(buf, string'(" Length: ")); write(buf, cmdV.Di.Length);
writeline(outfile, buf);
i:= 0;
while i < cmdV.Di.Length loop
write(buf,string'(" DATA: 0x")); hwrite(buf, cmdV.di.Data(i/8)); write(buf, string'("\n"));
writeline(outfile, buf);
i:=i+8;
end loop;
WHEN Completition =>
write(buf, string'("IB_BFM: ")); write(buf, info); write(buf, string'(" Completition: "));
write(buf, string'(" Dst Addr: 0x")); hwrite(buf, cmdV.Di.DstAddr);
write(buf, string'(" Src Addr: 0x")); hwrite(buf, cmdV.Di.SrcAddr);
write(buf, string'(" Tag: ")); write(buf, cmdV.Di.Tag);
write(buf, string'(" Length: ")); write(buf, cmdV.Di.Length);
write(buf, string'(" LastFlag: ")); write(buf, cmdV.Di.LastFlag);
writeline(outfile, buf);
i:= 0;
while i < cmdV.Di.Length loop
write(buf,string'(" DATA: 0x")); hwrite(buf, cmdV.di.Data(i/8)); write(buf, string'("\n"));
writeline(outfile, buf);
i:=i+8;
end loop;
WHEN G2LR =>
write(buf, string'("IB_BFM: ")); write(buf, info); write(buf, string'(" Global2Local Read: "));
write(buf, string'(" Dst Addr: 0x")); hwrite(buf, cmdV.Di.DstAddr);
write(buf, string'(" Src Addr: 0x")); hwrite(buf, cmdV.Di.SrcAddr);
write(buf, string'(" Tag: ")); write(buf, cmdV.Di.Tag);
write(buf, string'(" Length: ")); write(buf, cmdV.Di.Length);
writeline(outfile, buf);
WHEN L2GW =>
write(buf, string'("IB_BFM: ")); write(buf, info); write(buf, string'(" Local2Global Write: "));
write(buf, string'(" GlobalAddr: 0x"));hwrite(buf, cmdV.Di.DstAddr);
write(buf, string'(" LocalAddr: 0x")); hwrite(buf, cmdV.Di.SrcAddr);
write(buf, string'(" Tag: ")); write(buf, cmdV.Di.Tag);
write(buf, string'(" Length: ")); write(buf, cmdV.Di.Length);
writeline(outfile, buf);
i:= 0;
while i < cmdV.Di.Length loop
write(buf,string'(" DATA: 0x")); hwrite(buf, cmdV.di.Data(i/8)); write(buf, string'("\n"));
writeline(outfile, buf);
i:=i+8;
end loop;
WHEN others =>
END CASE;
writeline(outfile, buf);
end if;
END PROCEDURE;
-- -------------------------------------------------------------------------
-- Init Align
PROCEDURE AlignInit(Align : IN integer; WriteAlign : INOUT WriteAlignType) IS
BEGIN
WriteAlign.Align := Align;
WriteAlign.AlignReg := X"0000000000000000";
END PROCEDURE;
-- -------------------------------------------------------------------------
-- GetWriteCount
FUNCTION GetWriteCount(Align : IN integer;
Length : IN integer) RETURN integer IS
VARIABLE Plus : integer;
BEGIN
if (((Length+Align) mod 8) > 0) then
Plus := 1;
else
Plus := 0;
end if;
RETURN (Length+Align)/8 + Plus;
END FUNCTION;
-- -------------------------------------------------------------------------
-- GetWriteData
PROCEDURE GetWriteData(DataIn : IN std_logic_vector(63 downto 0);
SIGNAL DataOut : OUT std_logic_vector(63 downto 0);
WriteAlign : INOUT WriteAlignType) IS
VARIABLE i : integer;
VARIABLE j : integer;
BEGIN
if (WriteAlign.Align = 0) then
DataOut <= DataIn;
else
j:=0;
for i in WriteAlign.Align*8-1 downto 0 loop
DataOut(i) <= WriteAlign.AlignReg(64-(WriteAlign.Align*8)+i);
end loop;
for i in WriteAlign.Align*8 to 63 loop
DataOut(i) <= DataIn(j);
j:=j+1;
end loop;
WriteAlign.AlignReg := DataIn;
end if;
END PROCEDURE;
-- -------------------------------------------------------------------------
-- Generate LocalRead Transaction
PROCEDURE LocalRead (variable trans : IN IbCmdVType;
signal CLK : IN std_logic;
signal DATA : OUT std_logic_vector(63 downto 0);
signal SOP_N : OUT std_logic;
signal EOP_N : OUT std_logic;
signal SRC_RDY_N : OUT std_logic;
signal DST_RDY_N : IN std_logic) IS
BEGIN
DATA <= trans.Di.SrcAddr & X"00" & conv_std_logic_vector(trans.Di.Tag, 8) &
conv_std_logic_vector(trans.Di.Length,12) & C_IB_L2LR_TRANSACTION;
SRC_RDY_N <= '0';
SOP_N <= '0';
EOP_N <= '1';
wait until (CLK'event and CLK='1' and DST_RDY_N='0');
DATA <= X"00000000" & trans.Di.DstAddr;
SRC_RDY_N <= '0';
SOP_N <= '1';
EOP_N <= '0';
wait until (CLK'event and CLK='1' and DST_RDY_N='0');
SOP_N <= '1';
EOP_N <= '1';
SRC_RDY_N <= '1';
END PROCEDURE;
-- -------------------------------------------------------------------------
-- Generate LocalWrite Transaction
PROCEDURE LocalWrite(variable trans : IN IbCmdVType;
signal CLK : IN std_logic;
signal DATA : OUT std_logic_vector(63 downto 0);
signal SOP_N : OUT std_logic;
signal EOP_N : OUT std_logic;
signal SRC_RDY_N : OUT std_logic;
signal DST_RDY_N : IN std_logic) IS
VARIABLE i : integer;
VARIABLE len : integer;
VARIABLE aux_len : integer;
VARIABLE count : integer;
VARIABLE WriteAlign : WriteAlignType;
BEGIN
-- Set maximum length to 0 in header
if (trans.Di.Length = 4096) then
aux_len:= 0;
else
aux_len:=trans.Di.Length;
end if;
-- Send HDR0
DATA <= trans.Di.DstAddr & X"0000" &
conv_std_logic_vector(aux_len,12) & C_IB_L2LW_TRANSACTION;
SRC_RDY_N <= '0';
SOP_N <= '0';
EOP_N <= '1';
wait until (CLK'event and CLK='1' and DST_RDY_N='0');
-- Send HDR1
DATA <= X"00000000" & trans.Di.SrcAddr;
SRC_RDY_N <= '0';
SOP_N <= '1';
EOP_N <= '1';
wait until (CLK'event and CLK='1' and DST_RDY_N='0');
-- Send DATA
AlignInit(conv_integer(trans.Di.DstAddr(2 downto 0)), WriteAlign);
len := trans.Di.Length;
count := GetWriteCount(conv_integer(trans.Di.DstAddr(2 downto 0)),conv_integer(trans.Di.Length));
for i in 0 to count-1 loop
if (len > 0) then
GetWriteData(trans.Di.Data(i), DATA, WriteAlign);
else
GetWriteData(X"0000000000000000", DATA, WriteAlign);
end if;
SRC_RDY_N <= '0';
SOP_N <= '1';
if (i = (count-1)) then
EOP_N <= '0';
else
EOP_N <= '1';
end if;
wait until (CLK'event and CLK='1' and DST_RDY_N='0');
len := len - 8;
end loop;
SOP_N <= '1';
EOP_N <= '1';
SRC_RDY_N <= '1';
END PROCEDURE;
-- -------------------------------------------------------------------------
-- Generate Completition Transaction
PROCEDURE Completition(variable trans : IN IbCmdVType;
signal CLK : IN std_logic;
signal DATA : OUT std_logic_vector(63 downto 0);
signal SOP_N : OUT std_logic;
signal EOP_N : OUT std_logic;
signal SRC_RDY_N : OUT std_logic;
signal DST_RDY_N : IN std_logic) IS
VARIABLE i : integer;
VARIABLE len : integer;
VARIABLE count : integer;
VARIABLE WriteAlign : WriteAlignType;
BEGIN
-- Send HDR0
DATA <= trans.Di.DstAddr & X"00" & conv_std_logic_vector(trans.Di.Tag, 8) &
conv_std_logic_vector(trans.Di.Length,12) &
trans.Di.LastFlag & C_IB_RD_COMPL_TRANSACTION(2 downto 0);
SRC_RDY_N <= '0';
SOP_N <= '0';
EOP_N <= '1';
wait until (CLK'event and CLK='1' and DST_RDY_N='0');
-- Send HDR1
DATA <= X"00000000" & trans.Di.SrcAddr;
SRC_RDY_N <= '0';
SOP_N <= '1';
EOP_N <= '1';
wait until (CLK'event and CLK='1' and DST_RDY_N='0');
-- Send DATA
AlignInit(conv_integer(trans.Di.DstAddr(2 downto 0)),WriteAlign);
len := trans.Di.Length;
count := GetWriteCount(conv_integer(trans.Di.DstAddr(2 downto 0)),conv_integer(trans.Di.Length));
for i in 0 to count-1 loop
if (len > 0) then
GetWriteData(trans.Di.Data(i), DATA, WriteAlign);
else
GetWriteData(X"0000000000000000", DATA, WriteAlign);
end if;
SRC_RDY_N <= '0';
SOP_N <= '1';
if (i = (count-1)) then
EOP_N <= '0';
else
EOP_N <= '1';
end if;
wait until (CLK'event and CLK='1' and DST_RDY_N='0');
len := len - 8;
end loop;
SOP_N <= '1';
EOP_N <= '1';
SRC_RDY_N <= '1';
END PROCEDURE;
-- -------------------------------------------------------------------------
-- Receive Completition Transaction
PROCEDURE ReceiveCompletition(signal CLK : IN std_logic;
signal DATA : IN std_logic_vector(63 downto 0);
signal SOP_N : IN std_logic;
signal EOP_N : IN std_logic;
signal SRC_RDY_N : IN std_logic;
signal DST_RDY_N : IN std_logic) IS
VARIABLE i : integer;
BEGIN
-- Receive Header 1
LclIbCmdVReceive.CmdOp := Completition;
LclIbCmdVReceive.Di.DstAddr := DATA(63 downto 32);
LclIbCmdVReceive.Di.Tag := conv_integer(DATA(31 downto 16));
LclIbCmdVReceive.Di.LastFlag := DATA(3);
LclIbCmdVReceive.Di.Length := conv_integer(DATA(15 downto 4));
wait until (CLK'event and CLK='1' and SRC_RDY_N='0' and DST_RDY_N='0');
-- Receive Header2
LclIbCmdVReceive.Di.SrcAddr := DATA(63 downto 32);
-- Receive Data
i:=0;
while i < LclIbCmdVReceive.Di.Length loop
wait until (CLK'event and CLK='1' and SRC_RDY_N='0' and DST_RDY_N='0');
LclIbCmdVReceive.Di.Data(i/8) := DATA;
i:=i+8;
end loop;
END PROCEDURE;
-- -------------------------------------------------------------------------
-- Receive G2LR Transaction
PROCEDURE ReceiveG2LR(signal CLK : IN std_logic;
signal DATA : IN std_logic_vector(63 downto 0);
signal SOP_N : IN std_logic;
signal EOP_N : IN std_logic;
signal SRC_RDY_N : IN std_logic;
signal DST_RDY_N : IN std_logic) IS
BEGIN
-- Receive Header 1
LclIbCmdVReceive.CmdOp := G2LR;
LclIbCmdVReceive.Di.GlobalAddr(31 downto 0) := DATA(63 downto 32);
LclIbCmdVReceive.Di.Tag := conv_integer(DATA(31 downto 16));
if (conv_integer(DATA(15 downto 4)) = 0) then
LclIbCmdVReceive.Di.Length := 4096;
else
LclIbCmdVReceive.Di.Length := conv_integer(DATA(15 downto 4));
end if;
wait until (CLK'event and CLK='1' and SRC_RDY_N='0' and DST_RDY_N='0');
-- Receive Header2
LclIbCmdVReceive.Di.GlobalAddr(63 downto 32) := DATA(63 downto 32);
LclIbCmdVReceive.Di.LocalAddr := DATA(31 downto 0);
END PROCEDURE;
-- -------------------------------------------------------------------------
-- Receive L2GW Transaction
PROCEDURE ReceiveL2GW(signal CLK : IN std_logic;
signal DATA : IN std_logic_vector(63 downto 0);
signal SOP_N : IN std_logic;
signal EOP_N : IN std_logic;
signal SRC_RDY_N : IN std_logic;
signal DST_RDY_N : IN std_logic) IS
VARIABLE i : integer;
BEGIN
-- Receive Header 1
LclIbCmdVReceive.CmdOp := L2GW;
LclIbCmdVReceive.Di.GlobalAddr(31 downto 0) := DATA(63 downto 32);
LclIbCmdVReceive.Di.Tag := conv_integer(DATA(31 downto 16));
if (conv_integer(DATA(15 downto 4)) = 0) then
LclIbCmdVReceive.Di.Length := 4096;
else
LclIbCmdVReceive.Di.Length := conv_integer(DATA(15 downto 4));
end if;
wait until (CLK'event and CLK='1' and SRC_RDY_N='0' and DST_RDY_N='0');
-- Receive Header2
LclIbCmdVReceive.Di.GlobalAddr(63 downto 32) := DATA(63 downto 32);
LclIbCmdVReceive.Di.LocalAddr := DATA(31 downto 0);
-- Receive Data
i:=0;
while i < LclIbCmdVReceive.Di.Length loop
wait until (CLK'event and CLK='1' and SRC_RDY_N='0' and DST_RDY_N='0');
LclIbCmdVReceive.Di.Data(i/8) := DATA;
i:=i+8;
end loop;
END PROCEDURE;
-- -------------------------------------------------------------------------
-- Load Host Memory Data
PROCEDURE InitHostMemory IS
VARIABLE i : integer;
BEGIN
-- Init Memory with data
i:=0;
while i < LclIbCmdV.Di.Length loop
Memory((LclIbCmdV.Di.MemAddr+i)/8) := LclIbCmdV.Di.Data(i/8);
i:=i+8;
end loop;
while (LclIbCmdV.Di.MemAddr+i) < MEMORY_SIZE loop
Memory((LclIbCmdV.Di.MemAddr+i)/8) := X"0000000000000000";
i:=i+8;
end loop;
END PROCEDURE;
-- -------------------------------------------------------------------------
-- Show Host Memory
PROCEDURE ShowHostMemory IS
VARIABLE Data : bit_vector(63 downto 0);
VARIABLE i : integer;
VARIABLE buf : LINE;
file output : TEXT open write_mode is "STD_OUTPUT";
file outfile : TEXT open append_mode is "internal_bus.log";
BEGIN
if (LogTranscript) then
write(buf, string'("IB_BFM: Host Memory Content"));
writeline(output, buf);
end if;
if (LogFile) then
write(buf, string'("IB_BFM: Host Memory Content"));
writeline(outfile, buf);
end if;
-- Show Content
for i in 0 to MEMORY_SIZE/8 loop
if (LogTranscript) then
write(buf, string'(" DATA: 0x")); hwrite(buf, Memory(i));
writeline(output, buf);
end if;
if (LogFile) then
write(buf, string'(" DATA: 0x")); hwrite(buf, Memory(i));
writeline(outfile, buf);
end if;
end loop;
END PROCEDURE;
-- -------------------------------------------------------------------------
-- Process L2GW Transaction (Save Transaction into memory)
PROCEDURE ProcessL2GW(trans : IN IbCmdVType) IS
VARIABLE DstAddr : std_logic_vector(63 downto 0);
VARIABLE start : integer;
VARIABLE i : integer;
VARIABLE j : integer;
BEGIN
DstAddr := trans.Di.GlobalAddr - MEMORY_BASE_ADDR;
ASSERT (DstAddr >=0 and DstAddr+trans.Di.Length <= MEMORY_SIZE)
REPORT "L2GW outside of Host Memory address space";
start := conv_integer(DstAddr(31 downto 0));
j:=0;
for i in start to (start+trans.Di.Length)-1 loop
Memory(i/8)( (i mod 8)*8+7 downto (i mod 8)*8) :=
trans.Di.Data(j/8)((j mod 8)*8+7 downto (j mod 8)*8);
j:=j+1;
end loop;
END PROCEDURE;
-- -------------------------------------------------------------------------
-- Process G2LR Transaction (Save Transaction into Completition FIFO)
PROCEDURE ProcessG2LR(trans : IN IbCmdVType) IS
VARIABLE DstAddr : std_logic_vector(63 downto 0);
VARIABLE start : integer;
VARIABLE i : integer;
VARIABLE j : integer;
VARIABLE compl : IbCmdVType;
BEGIN
DstAddr := trans.Di.GlobalAddr - MEMORY_BASE_ADDR;
ASSERT (DstAddr >=0 and DstAddr+trans.Di.Length <= MEMORY_SIZE)
REPORT "L2GW outside of Host Memory address space";
compl.CmdOp := Completition;
compl.Di.DstAddr := trans.Di.LocalAddr;
compl.Di.SrcAddr := X"FFFFFFFF";
compl.Di.Tag := trans.Di.Tag;
compl.Di.Length := trans.Di.Length;
compl.Di.LastFlag := '1';
-- Get Data from memory into field
start := conv_integer(DstAddr(31 downto 0));
j:=0;
for i in start to (start+trans.Di.Length)-1 loop
compl.Di.Data(j/8)((j mod 8)*8+7 downto (j mod 8)*8) :=
Memory(i/8)( (i mod 8)*8+7 downto (i mod 8)*8);
j:=j+1;
end loop;
-- Insert Completition Into Fifo
insertFifo(compl);
END PROCEDURE;
BEGIN
-- Send Packet Process --------------------------------------------------------
SEND_PACKETS: PROCESS
file log_file : text;
BEGIN
IB_DOWN_DATA <= (others => '0');
IB_DOWN_SOF_N <= '1';
IB_DOWN_EOF_N <= '1';
IB_DOWN_SRC_RDY_N <= '1';
IbCmd.Ack <= '0';
ComplReq.Ack <= '0';
IbCmd.ReqAck <= '0';
ComplReq.ReqAck <= '0';
LOOP
-- Get Command
WHILE (IbCmd.Req = '0' and ComplReq.Req = '0') LOOP
WAIT UNTIL (IbCmd.Req = '1' or ComplReq.Req = '1');
END LOOP;
if (IbCmd.Req = '1') then
-- Send Request Acknowledge
IbCmd.ReqAck <= NOT(IbCmd.ReqAck);
-- Wait for Reqest Deasert
WAIT ON IbCmd.Req;
ReadIbCmdV(LclIbCmdV);
ShowCommandInfo(LclIbCmdV,"Downstream");
-- Process Command
CASE LclIbCmdV.CmdOp IS
WHEN LocalRead =>
LocalRead(LclIbCmdV, CLK, IB_DOWN_DATA, IB_DOWN_SOF_N, IB_DOWN_EOF_N, IB_DOWN_SRC_RDY_N, IB_DOWN_DST_RDY_N);
WHEN LocalWrite =>
LocalWrite(LclIbCmdV, CLK, IB_DOWN_DATA, IB_DOWN_SOF_N, IB_DOWN_EOF_N, IB_DOWN_SRC_RDY_N, IB_DOWN_DST_RDY_N);
WHEN Completition =>
Completition(LclIbCmdV, CLK, IB_DOWN_DATA, IB_DOWN_SOF_N, IB_DOWN_EOF_N, IB_DOWN_SRC_RDY_N, IB_DOWN_DST_RDY_N);
WHEN InitMemory =>
InitHostMemory;
WHEN InitMemoryFromAddr =>
InitHostMemory;
WHEN ShowMemory =>
ShowHostMemory;
WHEN TranscriptLogging =>
LogTranscript := LclIbCmdV.Di.Enable;
WHEN FileLogging =>
LogFile := LclIbCmdV.Di.Enable;
if (LogFile) then
file_open(log_file, "internal_bus.log", WRITE_MODE);
file_close(log_file);
end if;
WHEN others =>
END CASE;
-- Send Command done
IbCmd.Ack <= NOT(IbCmd.Ack);
end if;
if (ComplReq.Req = '1') then
-- Send Request Acknowledge
ComplReq.ReqAck <= NOT(ComplReq.ReqAck);
-- Wait for Reqest Deasert
WAIT ON ComplReq.Req;
ShowCommandInfo(ComplDataCmdV,"Downstream");
Completition(ComplDataCmdV, CLK, IB_DOWN_DATA, IB_DOWN_SOF_N, IB_DOWN_EOF_N, IB_DOWN_SRC_RDY_N, IB_DOWN_DST_RDY_N);
-- Send Command done
ComplReq.Ack <= NOT(ComplReq.Ack);
end if;
END LOOP;
END PROCESS;
-- Drive DST_RDY_N ---------------------------------------------------------------
DRIVE_DST_RDY_N: PROCESS
BEGIN
LOOP
DriveDstRdyN(CLK, aux_ib_up_dst_rdy_n);
END LOOP;
END PROCESS;
IB_UP_DST_RDY_N <= aux_ib_up_dst_rdy_n;
-- Receive Packet Process --------------------------------------------------------
RECEIVE_PACKETS: PROCESS
BEGIN
InitFifo; -- Init Completition fifo
-- IB_UP_DST_RDY_N <= '0'; Replaced by DRIVE_DST_RDY_N process
LOOP
wait until (CLK'event and CLK='1' and IB_UP_SRC_RDY_N='0' and IB_UP_SOF_N='0' and aux_ib_up_dst_rdy_n='0');
CASE IB_UP_DATA(3 downto 0) IS
WHEN C_IB_L2GW_TRANSACTION =>
-- Receive Transaction
ReceiveL2GW(CLK, IB_UP_DATA, IB_UP_SOF_N, IB_UP_EOF_N, IB_UP_SRC_RDY_N, aux_ib_up_dst_rdy_n);
-- Show Transaction info
ShowCommandInfo(LclIbCmdVReceive,"Upstream");
-- Store transaction data into memory
ProcessL2GW(LclIbCmdVReceive);
WHEN C_IB_G2LR_TRANSACTION =>
-- Receive Transaction
ReceiveG2LR(CLK, IB_UP_DATA, IB_UP_SOF_N, IB_UP_EOF_N, IB_UP_SRC_RDY_N, aux_ib_up_dst_rdy_n);
-- Show Transaction info
ShowCommandInfo(LclIbCmdVReceive,"Upstream");
-- Store Reqest into fifo
ProcessG2LR(LclIbCmdVReceive);
WHEN C_IB_RD_COMPL_TRANSACTION =>
-- Receive Transaction
ReceiveCompletition(CLK, IB_UP_DATA, IB_UP_SOF_N, IB_UP_EOF_N, IB_UP_SRC_RDY_N, aux_ib_up_dst_rdy_n);
-- Show Transaction info
ShowCommandInfo(LclIbCmdVReceive,"Upstream");
WHEN C_IB_RD_LASTCOMPL_TRANSACTION =>
-- Receive Transaction
ReceiveCompletition(CLK, IB_UP_DATA, IB_UP_SOF_N, IB_UP_EOF_N, IB_UP_SRC_RDY_N, aux_ib_up_dst_rdy_n);
-- Show Transaction info
ShowCommandInfo(LclIbCmdVReceive,"Upstream");
WHEN OTHERS =>
ASSERT false REPORT "IB_BFM: Unexcepted transaction on upstream port";
END CASE;
END LOOP;
END PROCESS;
-- Send Completitions --------------------------------------------------------
SEND_COMPLETITIONS: PROCESS
VARIABLE i : integer;
BEGIN
wait until (CLK'event and CLK='1');
LOOP
while (ComplFifo.Empty) loop
wait until (CLK'event and CLK='1');
end loop;
getFifo(ComplDataCmdV);
-- Memory delay
for i in 0 to MEMORY_DELAY loop
wait until (CLK'event and CLK='1');
end loop;
ComplReq.Req <= '1';
WAIT ON ComplReq.ReqAck;
ComplReq.Req <= '0';
WAIT ON ComplReq.Ack;
END LOOP;
END PROCESS;
END ARCHITECTURE IB_BFM_ARCH;
| bsd-3-clause | 28199bff9017719e1bf4b9c679377431 | 0.526765 | 3.903294 | false | false | false | false |
chiggs/oc_mkjpeg | design/BufFifo/multiplier.vhd | 1 | 1,940 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:18:01 03/12/2011
-- Design Name:
-- Module Name: multiplier - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity multiplier is
port (
CLK : in std_logic;
RST : in std_logic;
--
img_size_x : in std_logic_vector(15 downto 0);
img_size_y : in std_logic_vector(15 downto 0);
--
result : out std_logic_vector(31 downto 0);
threshold : out std_logic_vector(31 downto 0)
);
end multiplier;
architecture Behavioral of multiplier is
signal prev_x : std_logic_vector(15 downto 0);
signal prev_y : std_logic_vector(15 downto 0);
begin
process(CLK, RST)
begin
if (RST = '1') then
result <= x"00000000";
threshold <= x"00000000";
prev_x <= x"0000";
prev_y <= x"0000";
elsif (CLK'event and CLK = '1') then
if (prev_x /= img_size_x or prev_y /= img_size_y) then
result <= img_size_x * img_size_y;
threshold <= img_size_x * x"0007";
end if;
prev_x <= img_size_x;
prev_y <= img_size_y;
end if;
end process;
end Behavioral;
| lgpl-3.0 | 5b71675c09f26f6eff66134134dafc2d | 0.547938 | 3.415493 | false | false | false | false |
cnplab/blockmon | fw-combo/src/IPFIX/comp/fl_asfifo_cv2_128b.vhd | 1 | 9,085 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- fl_asfifo_cv2_128b.vhd : Async FL_FIFO composed of one virtex5 built-in FIFO
-- Copyright (C) 2009 CESNET
-- Author(s): Viktor Pus <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: fl_asfifo_cv2_128b.vhd 14706 2010-07-28 06:21:36Z polcak_l $
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity FL_ASFIFO_CV2_128B is
port(
RX_CLK : in std_logic;
TX_CLK : in std_logic;
RX_RESET : in std_logic;
TX_RESET : in std_logic;
RX_DATA : in std_logic_vector(127 downto 0);
RX_REM : in std_logic_vector(3 downto 0);
RX_SOP_N : in std_logic;
RX_EOP_N : in std_logic;
RX_SOF_N : in std_logic;
RX_EOF_N : in std_logic;
RX_SRC_RDY_N : in std_logic;
RX_DST_RDY_N : out std_logic;
TX_DATA : out std_logic_vector(127 downto 0);
TX_REM : out std_logic_vector(3 downto 0);
TX_SOP_N : out std_logic;
TX_EOP_N : out std_logic;
TX_SOF_N : out std_logic;
TX_EOF_N : out std_logic;
TX_SRC_RDY_N : out std_logic;
TX_DST_RDY_N : in std_logic
);
end FL_ASFIFO_CV2_128B;
-- ----------------------------------------------------------------------------
-- Architecture declaration
-- ----------------------------------------------------------------------------
architecture full of fl_asfifo_cv2_128b is
signal par0_in : std_logic_vector(7 downto 0);
signal par0_out : std_logic_vector(7 downto 0);
signal par1_in : std_logic_vector(7 downto 0);
signal par1_out : std_logic_vector(7 downto 0);
signal reset_both : std_logic;
signal sig_empty : std_logic;
signal sig_full : std_logic;
signal sig_empty0 : std_logic;
signal sig_full0 : std_logic;
signal sig_empty1 : std_logic;
signal sig_full1 : std_logic;
signal sig_rden : std_logic;
signal sig_wren : std_logic;
begin
sig_full <= sig_full0 or sig_full1;
sig_empty <= sig_empty0 or sig_empty1;
reset_both <= RX_RESET or TX_RESET;
par0_in <= RX_SOP_N & RX_EOP_N & RX_SOF_N & RX_EOF_N & RX_REM;
par1_in <= X"00";
RX_DST_RDY_N <= sig_full;
sig_wren <= (not RX_SRC_RDY_N) and (not sig_full);
FIFO36_72_inst0 : FIFO36_72
generic map (
ALMOST_FULL_OFFSET => X"0080", -- Sets almost full threshold
ALMOST_EMPTY_OFFSET => X"0080", -- Sets the almost empty threshold
DO_REG => 1, -- Enable output register (0 or 1)
-- Must be 1 if EN_SYN = FALSE
EN_ECC_READ => FALSE, -- Enable ECC decoder, TRUE or FALSE
EN_ECC_WRITE => FALSE, -- Enable ECC encoder, TRUE or FALSE
EN_SYN => FALSE, -- Specifies FIFO as Asynchronous (FALSE)
-- or Synchronous (TRUE)
FIRST_WORD_FALL_THROUGH => TRUE,-- Sets the FIFO FWFT to TRUE or FALSE
SIM_MODE => "SAFE") -- Simulation: "SAFE" vs "FAST", see "Synthesis and Simulation
-- Design Guide" for details
port map (
ALMOSTEMPTY => open, -- 1-bit almost empty output flag
ALMOSTFULL => open, -- 1-bit almost full output flag
DBITERR => open, -- 1-bit double bit error status output
DO => TX_DATA(63 downto 0), -- 64-bit data output
DOP => par0_out, -- 4-bit parity data output
ECCPARITY => open, -- 8-bit generated error correction parity
EMPTY => sig_empty0, -- 1-bit empty output flag
FULL => sig_full0, -- 1-bit full output flag
RDCOUNT => open, -- 9-bit read count output
RDERR => open, -- 1-bit read error output
WRCOUNT => open, -- 9-bit write count output
WRERR => open, -- 1-bit write error
DI => RX_DATA(63 downto 0), -- 64-bit data input
DIP => par0_in, -- 4-bit parity input
RDCLK => TX_CLK, -- 1-bit read clock input
RDEN => sig_rden, -- 1-bit read enable input
RST => reset_both, -- 1-bit reset input
WRCLK => RX_CLK, -- 1-bit write clock input
WREN => sig_wren -- 1-bit write enable input
);
FIFO36_72_inst1 : FIFO36_72
generic map (
ALMOST_FULL_OFFSET => X"0080", -- Sets almost full threshold
ALMOST_EMPTY_OFFSET => X"0080", -- Sets the almost empty threshold
DO_REG => 1, -- Enable output register (0 or 1)
-- Must be 1 if EN_SYN = FALSE
EN_ECC_READ => FALSE, -- Enable ECC decoder, TRUE or FALSE
EN_ECC_WRITE => FALSE, -- Enable ECC encoder, TRUE or FALSE
EN_SYN => FALSE, -- Specifies FIFO as Asynchronous (FALSE)
-- or Synchronous (TRUE)
FIRST_WORD_FALL_THROUGH => TRUE,-- Sets the FIFO FWFT to TRUE or FALSE
SIM_MODE => "SAFE") -- Simulation: "SAFE" vs "FAST", see "Synthesis and Simulation
-- Design Guide" for details
port map (
ALMOSTEMPTY => open, -- 1-bit almost empty output flag
ALMOSTFULL => open, -- 1-bit almost full output flag
DBITERR => open, -- 1-bit double bit error status output
DO => TX_DATA(127 downto 64), -- 64-bit data output
DOP => par1_out, -- 4-bit parity data output
ECCPARITY => open, -- 8-bit generated error correction parity
EMPTY => sig_empty1, -- 1-bit empty output flag
FULL => sig_full1, -- 1-bit full output flag
RDCOUNT => open, -- 9-bit read count output
RDERR => open, -- 1-bit read error output
WRCOUNT => open, -- 9-bit write count output
WRERR => open, -- 1-bit write error
DI => RX_DATA(127 downto 64), -- 64-bit data input
DIP => par1_in, -- 4-bit parity input
RDCLK => TX_CLK, -- 1-bit read clock input
RDEN => sig_rden, -- 1-bit read enable input
RST => reset_both, -- 1-bit reset input
WRCLK => RX_CLK, -- 1-bit write clock input
WREN => sig_wren -- 1-bit write enable input
);
TX_REM <= par0_out(3 downto 0);
TX_EOF_N <= par0_out(4);
TX_SOF_N <= par0_out(5);
TX_EOP_N <= par0_out(6);
TX_SOP_N <= par0_out(7);
TX_SRC_RDY_N <= sig_empty;
sig_rden <= (not TX_DST_RDY_N) and (not sig_empty);
end architecture full;
| bsd-3-clause | 649a1addb1f2d384ea74fa6acd22ed98 | 0.545074 | 3.977671 | false | false | false | false |
cnplab/blockmon | fw-combo/src/netcope-sim/synth_models/gics_ib_endpoint_synth.vhd | 1 | 933,780 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: O.40d
-- \ \ Application: netgen
-- / / Filename: gics_ib_endpoint_synth.vhd
-- /___/ /\ Timestamp: Wed Mar 30 10:05:03 2011
-- \ \ / \
-- \___\/\___\
--
-- Command : -ofmt vhdl -w ngc/gics_ib_endpoint_synth.ngc sim/synth_models/gics_ib_endpoint_synth.vhd
-- Device : xc5vlx110t-1-ff1136
-- Input file : ngc/gics_ib_endpoint_synth.ngc
-- Output file : sim/synth_models/gics_ib_endpoint_synth.vhd
-- # of Entities : 1
-- Design Name : gics_ib_endpoint_synth
-- Xilinx : /usr/local/fpga/xilinx131/ISE_DS/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity gics_ib_endpoint_synth is
port (
CLK : in STD_LOGIC := 'X';
WR_EOF : out STD_LOGIC;
BM_SRC_RDY_N : in STD_LOGIC := 'X';
RESET : in STD_LOGIC := 'X';
IB_UP_SRC_RDY_N : out STD_LOGIC;
IB_UP_EOF_N : out STD_LOGIC;
BM_SOF_N : in STD_LOGIC := 'X';
RD_REQ : out STD_LOGIC;
IB_DOWN_EOF_N : in STD_LOGIC := 'X';
BM_TAG_VLD : out STD_LOGIC;
RD_DST_RDY : out STD_LOGIC;
IB_DOWN_DST_RDY_N : out STD_LOGIC;
IB_UP_SOF_N : out STD_LOGIC;
WR_REQ : out STD_LOGIC;
WR_RDY : in STD_LOGIC := 'X';
RD_SRC_RDY : in STD_LOGIC := 'X';
RD_SOF : out STD_LOGIC;
IB_DOWN_SOF_N : in STD_LOGIC := 'X';
RD_ARDY_ACCEPT : in STD_LOGIC := 'X';
BM_DST_RDY_N : out STD_LOGIC;
RD_EOF : out STD_LOGIC;
IB_DOWN_SRC_RDY_N : in STD_LOGIC := 'X';
IB_UP_DST_RDY_N : in STD_LOGIC := 'X';
BM_EOF_N : in STD_LOGIC := 'X';
WR_SOF : out STD_LOGIC;
IB_UP_DATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
WR_LENGTH : out STD_LOGIC_VECTOR ( 11 downto 0 );
WR_BE : out STD_LOGIC_VECTOR ( 7 downto 0 );
RD_LENGTH : out STD_LOGIC_VECTOR ( 11 downto 0 );
RD_ADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
BM_TAG : out STD_LOGIC_VECTOR ( 7 downto 0 );
WR_DATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
WR_ADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
RD_BE : out STD_LOGIC_VECTOR ( 7 downto 0 );
RD_DATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
IB_DOWN_DATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
BM_DATA : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end gics_ib_endpoint_synth;
architecture STRUCTURE of gics_ib_endpoint_synth is
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_N111 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_N14 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_U_comparator_LT_GT_cmp_gt0000 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_U_comparator_LT_GT_cmp_gt0000241_SW0_FRB_87 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_eq : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_reg_history : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_reg_history_BRB0_90 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_reg_history_BRB1_91 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_reg_history_BRB1_rstpot_92 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_reg_history_BRB2_93 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_reg_history_BRB3_94 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_reg_history_or0000 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_U_comparator_LT_GT_cmp_gt0000 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_eq : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_eq16224_98 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_eq16271_99 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_reg_history : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_reg_history_BRB0_101 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_reg_history_BRB1_102 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_reg_history_BRB3_103 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_reg_history_BRB4_104 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_reg_history_BRB5_105 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_reg_history_BRB6_106 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_reg_history_BRB7_107 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_const_base_cnt_sel_0_0_108 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_const_base_cnt_sel_0_0_not0000 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_const_limit_cnt_sel_0_0_110 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_const_limit_cnt_sel_0_0_not0000 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_rstpot_113 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd1_114 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd1_In : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB0_117 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB1_118 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB2_119 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB3_120 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB4_121 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB5_122 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_0_0_123 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_0_1_124 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_10_0_125 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_10_1_126 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_11_0_127 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_11_1_128 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_12_0_129 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_12_1_130 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_13_0_131 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_13_1_132 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_14_0_133 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_14_1_134 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_15_0_135 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_15_1_136 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_16_0_137 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_16_1_138 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_17_0_139 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_17_1_140 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_18_0_141 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_18_1_142 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_19_0_143 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_19_1_144 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_1_0_145 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_1_1_146 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_20_0_147 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_20_1_148 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_21_0_149 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_21_1_150 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_22_0_151 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_22_1_152 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_23_0_153 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_23_1_154 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_24_0_155 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_24_1_156 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_25_0_157 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_25_1_158 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_26_0_159 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_26_1_160 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_27_0_161 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_27_1_162 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_28_0_163 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_28_1_164 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_29_0_165 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_29_1_166 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_2_0_167 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_2_1_168 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_30_0_169 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_30_1_170 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_31_0_171 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_31_1_172 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_32_0_173 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_32_1_174 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_33_0_175 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_33_1_176 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_34_0_177 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_34_1_178 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_35_0_179 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_35_1_180 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_36_0_181 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_36_1_182 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_37_0_183 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_37_1_184 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_38_0_185 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_38_1_186 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_39_0_187 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_39_1_188 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_3_0_189 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_3_1_190 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_40_0_191 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_40_1_192 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_41_0_193 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_41_1_194 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_42_0_195 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_42_1_196 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_43_0_197 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_43_1_198 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_44_0_199 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_44_1_200 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_45_0_201 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_45_1_202 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_46_0_203 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_46_1_204 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_47_0_205 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_47_1_206 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_48_0_207 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_48_1_208 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_49_0_209 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_49_1_210 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_4_0_211 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_4_1_212 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_50_0_213 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_50_1_214 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_51_0_215 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_51_1_216 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_52_0_217 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_52_1_218 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_53_0_219 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_53_1_220 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_54_0_221 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_54_1_222 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_55_0_223 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_55_1_224 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_56_0_225 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_56_1_226 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_57_0_227 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_57_1_228 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_58_0_229 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_58_1_230 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_59_0_231 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_59_1_232 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_5_0_233 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_5_1_234 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_60_0_235 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_60_1_236 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_61_0_237 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_61_1_238 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_62_0_239 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_62_1_240 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_63_0_241 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_63_1_242 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_64_0_243 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_64_1_244 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_65_0_245 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_65_1_246 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_6_0_247 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_6_1_248 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_7_0_249 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_7_1_250 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_8_0_251 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_8_1_252 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_9_0_253 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_9_1_254 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_addr_last_aux : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_addr_start_aux : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_ce_addr_last : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_ce_addr_start : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_cnt_addrpart_we_0_0_261 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_cnt_addrpart_we_0_0_not0000 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd1_263 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd1_In : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd2_265 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd2_In : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB1_268 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB10_269 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB10_rstpot_270 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB1_rstpot_271 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB2_272 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB3_273 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB3_rstpot_274 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB4_275 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB5_276 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB5_rstpot_277 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB7_278 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB8_279 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB9_280 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB0_282 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB11_283 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB2_284 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB2_rstpot_285 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB3_286 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB4_287 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB4_rstpot_288 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_not0001_289 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr_next : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr_we : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addrpart_we : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_pause_transfer : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_transfer : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_present_state_FSM_FFd1_309 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_present_state_FSM_FFd1_In : STD_LOGIC;
signal NlwRenamedSig_OI_IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_present_state_FSM_FFd2 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_present_state_FSM_FFd2_In : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd1_315 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd1_In_316 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd2_317 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd2_In_318 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB0_320 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB1_321 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB2_322 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB3_323 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB4_324 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB5_325 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_10_BRB2_328 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_10_BRB3_329 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_10_BRB4_330 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_11_BRB2_332 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_11_BRB3_333 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_11_BRB4_334 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_12_BRB2_336 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_12_BRB3_337 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_12_BRB4_338 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_13_BRB2_340 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_13_BRB3_341 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_13_BRB4_342 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_14_BRB2_344 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_14_BRB3_345 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_14_BRB4_346 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_15_BRB2_348 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_15_BRB3_349 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_15_BRB4_350 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_16_BRB2_352 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_16_BRB3_353 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_16_BRB4_354 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_17_BRB2_356 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_17_BRB3_357 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_17_BRB4_358 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_18_BRB2_360 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_18_BRB3_361 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_18_BRB4_362 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_19_BRB2_364 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_19_BRB3_365 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_19_BRB4_366 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_1_BRB2_367 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_20_BRB2_370 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_20_BRB3_371 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_20_BRB4_372 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_21_BRB2_374 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_21_BRB3_375 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_21_BRB4_376 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_22_BRB2_378 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_22_BRB3_379 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_22_BRB4_380 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_23_BRB2_382 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_23_BRB3_383 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_23_BRB4_384 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_24_BRB2_386 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_24_BRB3_387 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_24_BRB4_388 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_25_BRB2_390 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_25_BRB3_391 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_25_BRB4_392 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_26_BRB2_394 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_26_BRB3_395 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_26_BRB4_396 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_27_BRB2_398 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_27_BRB3_399 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_27_BRB4_400 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_28_BRB2_402 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_28_BRB3_403 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_28_BRB4_404 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_29_BRB2_406 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_29_BRB3_407 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_29_BRB4_408 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_2_BRB4_409 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_30_BRB2_412 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_30_BRB3_413 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_30_BRB4_414 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_31_BRB2_416 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_31_BRB3_417 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_31_BRB4_418 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_3_BRB4_427 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB1_439 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB2_440 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB3_441 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB4_442 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_5_BRB2_454 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_5_BRB3_455 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_5_BRB4_456 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_6_BRB2_462 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_6_BRB3_463 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_6_BRB4_464 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_7_BRB2_466 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_7_BRB3_467 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_7_BRB4_468 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_8_BRB2_470 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_8_BRB3_471 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_8_BRB4_472 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_9_BRB2_474 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_9_BRB3_475 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_9_BRB4_476 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_vld_478 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_vld_rstpot_479 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_eof_n_reg_480 : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_U_swapper_eof_n_reg_and0000_inv : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_addr_dec_in_eof_n : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_addr_dec_in_sof_n : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_addr_dec_out_dst_rdy_n : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_addr_dec_out_eof_n : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_addr_dec_out_sof_n : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_fsm_rd_dst_rdy_n : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_fsm_rd_src_rdy_n : STD_LOGIC;
signal IB_ENDPOINT_I_U_rd_pipe_PIPE_addr : STD_LOGIC;
signal IB_ENDPOINT_I_U_rd_pipe_PIPE_ce : STD_LOGIC;
signal IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we : STD_LOGIC;
signal IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd1 : STD_LOGIC;
signal IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd1_BRB0_623 : STD_LOGIC;
signal IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd1_BRB1_624 : STD_LOGIC;
signal IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd1_BRB2_625 : STD_LOGIC;
signal IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd1_BRB3_626 : STD_LOGIC;
signal IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd1_BRB4_627 : STD_LOGIC;
signal IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd1_BRB5_628 : STD_LOGIC;
signal IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd2_629 : STD_LOGIC;
signal IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd2_In : STD_LOGIC;
signal IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_rdy_697 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_BE_GEN_YES_U_be_gen_be_mux_6_1_700 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data1 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data2 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data3 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data4 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data5 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data6 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data7 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data8 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data9 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data_and0000 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data_not0001 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_next_state : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_next_state_0_cmp_eq0000_744 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_next_state_0_cmp_eq0000_SW0_FRB_745 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_N01 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cmp_empty : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr_ce : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd1_758 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd1_In_759 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_760 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_In : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_DATA_DST_RDY1_FRB_763 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_next_state : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0_BRB0_767 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0_BRB1_768 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0_BRB3_769 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0_BRB4_770 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd1_771 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd1_In : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd2 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB0_774 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB1_775 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB2_776 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB3_777 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB4_778 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_0_0_779 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_0_1_780 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_10_0_781 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_10_1_782 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_11_0_783 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_11_1_784 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_12_0_785 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_12_1_786 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_13_0_787 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_13_1_788 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_14_0_789 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_14_1_790 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_15_0_791 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_15_1_792 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_16_0_793 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_16_1_794 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_17_0_795 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_17_1_796 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_18_0_797 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_18_1_798 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_19_0_799 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_19_1_800 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_1_0_801 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_1_1_802 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_20_0_803 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_20_1_804 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_21_0_805 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_21_1_806 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_22_0_807 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_22_1_808 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_23_0_809 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_23_1_810 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_24_0_811 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_24_1_812 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_25_0_813 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_25_1_814 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_26_0_815 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_26_1_816 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_27_0_817 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_27_1_818 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_28_0_819 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_28_1_820 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_29_0_821 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_29_1_822 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_2_0_823 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_2_1_824 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_30_0_825 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_30_1_826 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_31_0_827 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_31_1_828 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_32_0_829 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_32_1_830 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_33_0_831 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_33_1_832 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_34_0_833 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_34_1_834 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_35_0_835 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_35_1_836 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_36_0_837 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_36_1_838 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_37_0_839 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_37_1_840 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_38_0_841 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_38_1_842 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_39_0_843 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_39_1_844 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_3_0_845 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_3_1_846 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_40_0_847 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_40_1_848 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_41_0_849 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_41_1_850 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_42_0_851 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_42_1_852 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_43_0_853 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_43_1_854 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_44_0_855 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_44_1_856 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_45_0_857 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_45_1_858 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_46_0_859 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_46_1_860 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_47_0_861 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_47_1_862 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_48_0_863 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_48_1_864 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_49_0_865 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_49_1_866 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_4_0_867 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_4_1_868 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_50_0_869 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_50_1_870 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_51_0_871 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_51_1_872 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_52_0_873 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_52_1_874 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_53_0_875 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_53_1_876 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_54_0_877 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_54_1_878 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_55_0_879 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_55_1_880 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_56_0_881 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_56_1_882 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_57_0_883 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_57_1_884 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_58_0_885 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_58_1_886 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_59_0_887 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_59_1_888 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_5_0_889 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_5_1_890 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_60_0_891 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_60_1_892 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_61_0_893 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_61_1_894 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_62_0_895 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_62_1_896 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_63_0_897 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_63_1_898 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_64_0_899 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_64_1_900 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_65_0_901 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_65_1_902 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_6_0_903 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_6_1_904 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_7_0_905 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_7_1_906 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_8_0_907 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_8_1_908 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_9_0_909 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_9_1_910 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd1_912 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd1_In : STD_LOGIC;
signal NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd2 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd2_In : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_cmp_eq0000_916 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1C : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1R : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_10_rt_922 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_11_rt_924 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_4_rt_928 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_5_rt_930 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_6_rt_932 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_7_rt_934 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_8_rt_936 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_9_rt_938 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_lut_0_Q_939 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_lut_2_Q_940 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_lut_3_Q_941 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_1_rt_944 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_10_rt_946 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_11_rt_948 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_12_rt_950 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_13_rt_952 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_14_rt_954 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_15_rt_956 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_16_rt_958 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_17_rt_960 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_18_rt_962 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_19_rt_964 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_2_rt_966 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_20_rt_968 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_21_rt_970 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_22_rt_972 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_23_rt_974 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_24_rt_976 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_25_rt_978 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_26_rt_980 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_27_rt_982 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_3_rt_984 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_4_rt_986 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_5_rt_988 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_6_rt_990 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_7_rt_992 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_8_rt_994 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_9_rt_996 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count1 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count2 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count3 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count4 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count5 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count6 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count7 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count8 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count9 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_flag4096 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_flag4096_cmp_eq000035_1038 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_flag4096_cmp_eq000071_1039 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_10_BRB2_1042 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_10_BRB3_1043 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_10_BRB4_1044 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_11_BRB2_1045 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_11_BRB3_1046 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_11_BRB4_1047 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_12_BRB2_1048 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_12_BRB3_1049 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_12_BRB4_1050 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_13_BRB2_1051 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_13_BRB3_1052 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_13_BRB4_1053 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_14_BRB2_1054 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_14_BRB3_1055 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_14_BRB4_1056 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_15_BRB2_1057 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_15_BRB3_1058 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_15_BRB4_1059 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_16_BRB2_1060 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_16_BRB3_1061 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_16_BRB4_1062 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_17_BRB2_1063 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_17_BRB3_1064 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_17_BRB4_1065 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_18_BRB2_1066 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_18_BRB3_1067 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_18_BRB4_1068 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_19_BRB2_1069 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_19_BRB3_1070 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_19_BRB4_1071 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_20_BRB2_1073 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_20_BRB3_1074 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_20_BRB4_1075 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_21_BRB2_1076 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_21_BRB3_1077 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_21_BRB4_1078 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_22_BRB2_1079 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_22_BRB3_1080 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_22_BRB4_1081 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_23_BRB2_1082 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_23_BRB3_1083 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_23_BRB4_1084 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_24_BRB2_1085 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_24_BRB3_1086 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_24_BRB4_1087 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_25_BRB2_1088 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_25_BRB3_1089 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_25_BRB4_1090 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_26_BRB2_1091 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_26_BRB3_1092 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_26_BRB4_1093 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_27_BRB2_1094 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_27_BRB3_1095 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_27_BRB4_1096 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_28_BRB2_1097 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_28_BRB3_1098 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_28_BRB4_1099 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_29_BRB2_1100 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_29_BRB3_1101 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_29_BRB4_1102 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_30_BRB2_1103 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_30_BRB3_1104 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_30_BRB4_1105 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB0_1135 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB1_1136 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB2_1137 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB3_1138 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB4_1139 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_rstpot_1140 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_3_BRB2_1141 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_3_BRB3_1142 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_3_BRB4_1143 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_3_not0001 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_4_BRB2_1145 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_4_BRB3_1146 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_4_BRB4_1147 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_5_BRB2_1148 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_5_BRB3_1149 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_5_BRB4_1150 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_6_BRB2_1151 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_6_BRB3_1152 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_6_BRB4_1153 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_7_BRB2_1154 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_7_BRB3_1155 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_7_BRB4_1156 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_8_BRB2_1157 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_8_BRB3_1158 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_8_BRB4_1159 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_9_BRB2_1160 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_9_BRB3_1161 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_9_BRB4_1162 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count_and0000 : STD_LOGIC;
signal NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_10 : STD_LOGIC;
signal NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_11 : STD_LOGIC;
signal NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_12 : STD_LOGIC;
signal NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_13 : STD_LOGIC;
signal NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_14 : STD_LOGIC;
signal NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_15 : STD_LOGIC;
signal NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_4 : STD_LOGIC;
signal NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_5 : STD_LOGIC;
signal NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_6 : STD_LOGIC;
signal NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_7 : STD_LOGIC;
signal NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_8 : STD_LOGIC;
signal NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_9 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_U_unpck_hbuf_reg_full_1196 : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_addr_ce : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_done_flag_we : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_hbuf_full : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_header_last : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_unpck_hbuf_re : STD_LOGIC;
signal IB_ENDPOINT_I_U_read_ctrl_unpck_hbuf_we : STD_LOGIC;
signal IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr : STD_LOGIC;
signal IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce : STD_LOGIC;
signal IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd1_1269 : STD_LOGIC;
signal IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd1_In : STD_LOGIC;
signal IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271 : STD_LOGIC;
signal IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_In : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB0_1278 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB1_1279 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB2_1280 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB3_1281 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB4_1282 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB5_1283 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_1_rt_1286 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_10_rt_1288 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_11_rt_1290 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_12_rt_1292 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_13_rt_1294 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_14_rt_1296 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_15_rt_1298 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_16_rt_1300 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_17_rt_1302 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_18_rt_1304 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_19_rt_1306 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_2_rt_1308 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_20_rt_1310 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_21_rt_1312 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_22_rt_1314 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_23_rt_1316 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_24_rt_1318 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_25_rt_1320 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_26_rt_1322 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_27_rt_1324 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_3_rt_1326 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_4_rt_1328 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_5_rt_1330 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_6_rt_1332 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_7_rt_1334 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_8_rt_1336 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_9_rt_1338 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_10_BRB1_1342 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_10_BRB2_1343 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_10_BRB4_1344 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_10_BRB5_1345 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_11_BRB2_1346 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_11_BRB5_1347 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_11_BRB6_1348 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_12_BRB2_1349 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_12_BRB5_1350 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_12_BRB6_1351 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_13_BRB2_1352 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_13_BRB5_1353 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_13_BRB6_1354 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_14_BRB2_1355 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_14_BRB5_1356 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_14_BRB6_1357 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_15_BRB2_1358 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_15_BRB5_1359 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_15_BRB6_1360 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_16_BRB2_1361 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_16_BRB5_1362 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_16_BRB6_1363 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_17_BRB2_1364 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_17_BRB5_1365 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_17_BRB6_1366 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_18_BRB1_1367 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_18_BRB2_1368 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_18_BRB5_1369 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_19_BRB1_1370 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_19_BRB2_1371 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_19_BRB5_1372 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_20_BRB1_1374 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_20_BRB2_1375 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_20_BRB5_1376 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_21_BRB1_1377 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_21_BRB2_1378 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_21_BRB5_1379 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_22_BRB1_1380 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_22_BRB2_1381 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_22_BRB5_1382 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_23_BRB1_1383 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_23_BRB2_1384 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_23_BRB5_1385 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_24_BRB1_1386 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_24_BRB2_1387 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_24_BRB5_1388 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_25_BRB1_1389 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_25_BRB2_1390 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_25_BRB5_1391 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_26_BRB1_1392 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_26_BRB2_1393 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_26_BRB5_1394 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_27_BRB1_1395 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_27_BRB2_1396 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_27_BRB5_1397 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_28_BRB1_1398 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_28_BRB2_1399 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_28_BRB5_1400 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB1_1401 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB2_1402 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB3_1403 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB4_1404 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB5_1405 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_30_BRB1_1406 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_30_BRB2_1407 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_30_BRB5_1408 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_BRB1_1438 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_BRB2_1439 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_BRB5_1440 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_rstpot_1441 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_3_BRB2_1442 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_3_BRB4_1443 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_3_BRB5_1444 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_4_BRB2_1445 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_4_BRB4_1446 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_4_BRB5_1447 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_5_BRB2_1448 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_5_BRB4_1449 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_5_BRB5_1450 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_6_BRB2_1451 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_6_BRB4_1452 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_6_BRB5_1453 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_7_BRB2_1454 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_7_BRB4_1455 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_7_BRB5_1456 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_8_BRB2_1457 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_8_BRB4_1458 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_8_BRB5_1459 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_9_BRB2_1460 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_9_BRB4_1461 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_9_BRB5_1462 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_10_1463 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_11_1464 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_12_1465 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_13_1466 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_14_1467 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_15_1468 : STD_LOGIC;
signal NlwRenamedSig_OI_IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_4 : STD_LOGIC;
signal NlwRenamedSig_OI_IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_5 : STD_LOGIC;
signal NlwRenamedSig_OI_IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_6 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_7_1472 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_8_1473 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_9_1474 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd1_1475 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd1_In : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd2_1477 : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd2_In : STD_LOGIC;
signal IB_ENDPOINT_I_U_write_ctrl_addr_we : STD_LOGIC;
signal IB_ENDPOINT_I_cpl_pipe_eof_n : STD_LOGIC;
signal IB_ENDPOINT_I_cpl_pipe_sof_n : STD_LOGIC;
signal IB_ENDPOINT_I_downrd_eof_n : STD_LOGIC;
signal IB_ENDPOINT_I_downrd_sof_n : STD_LOGIC;
signal IB_ENDPOINT_I_rd_pipe_dst_rdy_n : STD_LOGIC;
signal IB_ENDPOINT_I_rd_pipe_eof_n : STD_LOGIC;
signal IB_ENDPOINT_I_rd_pipe_sof_n : STD_LOGIC;
signal IB_ENDPOINT_I_wr_dst_rdy_n : STD_LOGIC;
signal IB_ENDPOINT_I_wr_eof_n : STD_LOGIC;
signal IB_ENDPOINT_I_wr_sof_n : STD_LOGIC;
signal IB_ENDPOINT_I_wr_src_rdy_n : STD_LOGIC;
signal N1 : STD_LOGIC;
signal N101 : STD_LOGIC;
signal N103 : STD_LOGIC;
signal N11 : STD_LOGIC;
signal N115 : STD_LOGIC;
signal N12 : STD_LOGIC;
signal N13 : STD_LOGIC;
signal N138 : STD_LOGIC;
signal N139 : STD_LOGIC;
signal N140 : STD_LOGIC;
signal N142 : STD_LOGIC;
signal N143 : STD_LOGIC;
signal N148 : STD_LOGIC;
signal N150 : STD_LOGIC;
signal N156 : STD_LOGIC;
signal N163 : STD_LOGIC;
signal N173 : STD_LOGIC;
signal N19 : STD_LOGIC;
signal N195 : STD_LOGIC;
signal N207 : STD_LOGIC;
signal N209 : STD_LOGIC;
signal N21 : STD_LOGIC;
signal N211 : STD_LOGIC;
signal N212 : STD_LOGIC;
signal N214 : STD_LOGIC;
signal N215 : STD_LOGIC;
signal N217 : STD_LOGIC;
signal N218 : STD_LOGIC;
signal N220 : STD_LOGIC;
signal N23 : STD_LOGIC;
signal N25 : STD_LOGIC;
signal N27 : STD_LOGIC;
signal N36 : STD_LOGIC;
signal N38 : STD_LOGIC;
signal N395 : STD_LOGIC;
signal N40 : STD_LOGIC;
signal N42 : STD_LOGIC;
signal N46 : STD_LOGIC;
signal N48 : STD_LOGIC;
signal N5 : STD_LOGIC;
signal N506 : STD_LOGIC;
signal N57 : STD_LOGIC;
signal N59 : STD_LOGIC;
signal N61 : STD_LOGIC;
signal N610 : STD_LOGIC;
signal N618 : STD_LOGIC;
signal N626 : STD_LOGIC;
signal N634 : STD_LOGIC;
signal N642 : STD_LOGIC;
signal N645 : STD_LOGIC;
signal N65 : STD_LOGIC;
signal N66 : STD_LOGIC;
signal N7 : STD_LOGIC;
signal N73 : STD_LOGIC;
signal N77 : STD_LOGIC;
signal N789 : STD_LOGIC;
signal N79 : STD_LOGIC;
signal N790 : STD_LOGIC;
signal N791 : STD_LOGIC;
signal N792 : STD_LOGIC;
signal N793 : STD_LOGIC;
signal N794 : STD_LOGIC;
signal N795 : STD_LOGIC;
signal N797 : STD_LOGIC;
signal N799 : STD_LOGIC;
signal N8 : STD_LOGIC;
signal N801 : STD_LOGIC;
signal N803 : STD_LOGIC;
signal N804 : STD_LOGIC;
signal N81 : STD_LOGIC;
signal N83 : STD_LOGIC;
signal N87 : STD_LOGIC;
signal N9 : STD_LOGIC;
signal N95 : STD_LOGIC;
signal NlwRenamedSig_OI_RD_EOF : STD_LOGIC;
signal NlwRenamedSig_OI_RD_SOF : STD_LOGIC;
signal NlwRenamedSig_OI_WR_ADDR_0_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_ADDR_10_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_ADDR_11_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_ADDR_12_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_ADDR_13_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_ADDR_14_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_ADDR_15_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_ADDR_16_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_ADDR_17_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_ADDR_18_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_ADDR_19_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_ADDR_20_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_ADDR_21_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_ADDR_22_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_ADDR_23_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_ADDR_24_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_ADDR_25_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_ADDR_26_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_ADDR_27_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_ADDR_28_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_ADDR_29_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_ADDR_3_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_ADDR_30_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_ADDR_31_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_ADDR_4_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_ADDR_5_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_ADDR_6_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_ADDR_7_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_ADDR_8_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_ADDR_9_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_0_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_10_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_11_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_12_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_13_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_14_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_15_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_32_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_33_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_34_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_35_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_36_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_37_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_38_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_39_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_4_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_40_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_41_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_42_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_43_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_44_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_45_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_46_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_47_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_48_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_49_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_5_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_50_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_51_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_52_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_53_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_54_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_55_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_56_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_57_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_58_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_59_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_6_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_60_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_61_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_62_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_63_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_7_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_8_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_DATA_9_Q : STD_LOGIC;
signal NlwRenamedSig_OI_WR_EOF : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_10_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_1_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_0_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_2_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_11_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_3_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_12_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_4_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_13_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_5_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_14_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_6_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_15_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_20_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_7_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_16_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_17_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_22_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_21_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_8_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_9_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_18_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_23_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_24_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_19_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_30_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_25_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_31_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_26_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_32_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_27_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_33_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_28_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_40_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_35_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_34_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_29_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_41_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_36_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_42_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_37_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_43_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_38_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_44_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_39_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_50_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_45_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_51_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_46_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_52_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_47_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_53_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_48_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_54_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_49_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_60_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_55_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_61_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_56_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_62_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_57_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_63_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_58_0_Q15_UNCONNECTED : STD_LOGIC;
signal NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_59_0_Q15_UNCONNECTED : STD_LOGIC;
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr : STD_LOGIC_VECTOR ( 15 downto 0 );
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_U_reg_cyc_type_lg_we_regsh_do : STD_LOGIC_VECTOR ( 0 downto 0 );
signal IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr : STD_LOGIC_VECTOR ( 15 downto 4 );
signal IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_out_data_aux : STD_LOGIC_VECTOR ( 65 downto 64 );
signal IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg : STD_LOGIC_VECTOR ( 63 downto 0 );
signal IB_ENDPOINT_I_U_down_buf_addr_dec_in_data : STD_LOGIC_VECTOR ( 63 downto 0 );
signal IB_ENDPOINT_I_U_rd_pipe_PIPE_dout : STD_LOGIC_VECTOR ( 65 downto 0 );
signal IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout : STD_LOGIC_VECTOR ( 65 downto 0 );
signal IB_ENDPOINT_I_U_read_ctrl_BE_GEN_YES_U_be_gen_Madd_last_align_lut : STD_LOGIC_VECTOR ( 1 downto 1 );
signal IB_ENDPOINT_I_U_read_ctrl_BE_GEN_YES_U_be_gen_be_mux : STD_LOGIC_VECTOR ( 6 downto 6 );
signal IB_ENDPOINT_I_U_read_ctrl_BE_GEN_YES_U_be_gen_last_align : STD_LOGIC_VECTOR ( 2 downto 2 );
signal IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_cy : STD_LOGIC_VECTOR ( 8 downto 0 );
signal IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut : STD_LOGIC_VECTOR ( 9 downto 0 );
signal IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data : STD_LOGIC_VECTOR ( 9 downto 0 );
signal IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_present_state : STD_LOGIC_VECTOR ( 0 downto 0 );
signal IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Result : STD_LOGIC_VECTOR ( 3 downto 0 );
signal IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr : STD_LOGIC_VECTOR ( 3 downto 0 );
signal IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state : STD_LOGIC_VECTOR ( 0 downto 0 );
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy : STD_LOGIC_VECTOR ( 11 downto 0 );
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy : STD_LOGIC_VECTOR ( 27 downto 0 );
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_cy : STD_LOGIC_VECTOR ( 8 downto 0 );
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut : STD_LOGIC_VECTOR ( 9 downto 0 );
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_count_aux1 : STD_LOGIC_VECTOR ( 12 downto 3 );
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000 : STD_LOGIC_VECTOR ( 28 downto 0 );
signal IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count : STD_LOGIC_VECTOR ( 9 downto 0 );
signal IB_ENDPOINT_I_U_read_ctrl_U_unpck_hbuf_data_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal IB_ENDPOINT_I_U_read_ctrl_align_in_data : STD_LOGIC_VECTOR ( 63 downto 0 );
signal IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_out_data_aux : STD_LOGIC_VECTOR ( 65 downto 64 );
signal IB_ENDPOINT_I_U_write_ctrl_BE_GEN_YES_U_be_gen_Madd_last_align_lut : STD_LOGIC_VECTOR ( 1 downto 1 );
signal IB_ENDPOINT_I_U_write_ctrl_BE_GEN_YES_U_be_gen_last_align : STD_LOGIC_VECTOR ( 2 downto 2 );
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy : STD_LOGIC_VECTOR ( 27 downto 0 );
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000 : STD_LOGIC_VECTOR ( 28 downto 0 );
signal IB_ENDPOINT_I_cpl_data : STD_LOGIC_VECTOR ( 63 downto 0 );
signal IB_ENDPOINT_I_downrd_data : STD_LOGIC_VECTOR ( 63 downto 32 );
signal NlwRenamedSig_OI_RD_ADDR : STD_LOGIC_VECTOR ( 31 downto 3 );
begin
WR_EOF <= NlwRenamedSig_OI_WR_EOF;
RD_REQ <= NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd2;
BM_TAG_VLD <= NlwRenamedSig_OI_WR_ADDR_0_Q;
IB_DOWN_DST_RDY_N <= NlwRenamedSig_OI_IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_present_state_FSM_FFd2;
RD_SOF <= NlwRenamedSig_OI_RD_SOF;
BM_DST_RDY_N <= NlwRenamedSig_OI_WR_ADDR_0_Q;
RD_EOF <= NlwRenamedSig_OI_RD_EOF;
WR_LENGTH(11) <= IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_15_1468;
WR_LENGTH(10) <= IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_14_1467;
WR_LENGTH(9) <= IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_13_1466;
WR_LENGTH(8) <= IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_12_1465;
WR_LENGTH(7) <= IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_11_1464;
WR_LENGTH(6) <= IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_10_1463;
WR_LENGTH(5) <= IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_9_1474;
WR_LENGTH(4) <= IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_8_1473;
WR_LENGTH(3) <= IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_7_1472;
WR_LENGTH(2) <= NlwRenamedSig_OI_IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_6;
WR_LENGTH(1) <= NlwRenamedSig_OI_IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_5;
WR_LENGTH(0) <= NlwRenamedSig_OI_IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_4;
RD_LENGTH(11) <= NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_15;
RD_LENGTH(10) <= NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_14;
RD_LENGTH(9) <= NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_13;
RD_LENGTH(8) <= NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_12;
RD_LENGTH(7) <= NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_11;
RD_LENGTH(6) <= NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_10;
RD_LENGTH(5) <= NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_9;
RD_LENGTH(4) <= NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_8;
RD_LENGTH(3) <= NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_7;
RD_LENGTH(2) <= NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_6;
RD_LENGTH(1) <= NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_5;
RD_LENGTH(0) <= NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_4;
RD_ADDR(31) <= NlwRenamedSig_OI_RD_ADDR(31);
RD_ADDR(30) <= NlwRenamedSig_OI_RD_ADDR(30);
RD_ADDR(29) <= NlwRenamedSig_OI_RD_ADDR(29);
RD_ADDR(28) <= NlwRenamedSig_OI_RD_ADDR(28);
RD_ADDR(27) <= NlwRenamedSig_OI_RD_ADDR(27);
RD_ADDR(26) <= NlwRenamedSig_OI_RD_ADDR(26);
RD_ADDR(25) <= NlwRenamedSig_OI_RD_ADDR(25);
RD_ADDR(24) <= NlwRenamedSig_OI_RD_ADDR(24);
RD_ADDR(23) <= NlwRenamedSig_OI_RD_ADDR(23);
RD_ADDR(22) <= NlwRenamedSig_OI_RD_ADDR(22);
RD_ADDR(21) <= NlwRenamedSig_OI_RD_ADDR(21);
RD_ADDR(20) <= NlwRenamedSig_OI_RD_ADDR(20);
RD_ADDR(19) <= NlwRenamedSig_OI_RD_ADDR(19);
RD_ADDR(18) <= NlwRenamedSig_OI_RD_ADDR(18);
RD_ADDR(17) <= NlwRenamedSig_OI_RD_ADDR(17);
RD_ADDR(16) <= NlwRenamedSig_OI_RD_ADDR(16);
RD_ADDR(15) <= NlwRenamedSig_OI_RD_ADDR(15);
RD_ADDR(14) <= NlwRenamedSig_OI_RD_ADDR(14);
RD_ADDR(13) <= NlwRenamedSig_OI_RD_ADDR(13);
RD_ADDR(12) <= NlwRenamedSig_OI_RD_ADDR(12);
RD_ADDR(11) <= NlwRenamedSig_OI_RD_ADDR(11);
RD_ADDR(10) <= NlwRenamedSig_OI_RD_ADDR(10);
RD_ADDR(9) <= NlwRenamedSig_OI_RD_ADDR(9);
RD_ADDR(8) <= NlwRenamedSig_OI_RD_ADDR(8);
RD_ADDR(7) <= NlwRenamedSig_OI_RD_ADDR(7);
RD_ADDR(6) <= NlwRenamedSig_OI_RD_ADDR(6);
RD_ADDR(5) <= NlwRenamedSig_OI_RD_ADDR(5);
RD_ADDR(4) <= NlwRenamedSig_OI_RD_ADDR(4);
RD_ADDR(3) <= NlwRenamedSig_OI_RD_ADDR(3);
RD_ADDR(2) <= NlwRenamedSig_OI_WR_ADDR_0_Q;
RD_ADDR(1) <= NlwRenamedSig_OI_WR_ADDR_0_Q;
RD_ADDR(0) <= NlwRenamedSig_OI_WR_ADDR_0_Q;
BM_TAG(7) <= NlwRenamedSig_OI_WR_ADDR_0_Q;
BM_TAG(6) <= NlwRenamedSig_OI_WR_ADDR_0_Q;
BM_TAG(5) <= NlwRenamedSig_OI_WR_ADDR_0_Q;
BM_TAG(4) <= NlwRenamedSig_OI_WR_ADDR_0_Q;
BM_TAG(3) <= NlwRenamedSig_OI_WR_ADDR_0_Q;
BM_TAG(2) <= NlwRenamedSig_OI_WR_ADDR_0_Q;
BM_TAG(1) <= NlwRenamedSig_OI_WR_ADDR_0_Q;
BM_TAG(0) <= NlwRenamedSig_OI_WR_ADDR_0_Q;
WR_DATA(63) <= NlwRenamedSig_OI_WR_DATA_63_Q;
WR_DATA(62) <= NlwRenamedSig_OI_WR_DATA_62_Q;
WR_DATA(61) <= NlwRenamedSig_OI_WR_DATA_61_Q;
WR_DATA(60) <= NlwRenamedSig_OI_WR_DATA_60_Q;
WR_DATA(59) <= NlwRenamedSig_OI_WR_DATA_59_Q;
WR_DATA(58) <= NlwRenamedSig_OI_WR_DATA_58_Q;
WR_DATA(57) <= NlwRenamedSig_OI_WR_DATA_57_Q;
WR_DATA(56) <= NlwRenamedSig_OI_WR_DATA_56_Q;
WR_DATA(55) <= NlwRenamedSig_OI_WR_DATA_55_Q;
WR_DATA(54) <= NlwRenamedSig_OI_WR_DATA_54_Q;
WR_DATA(53) <= NlwRenamedSig_OI_WR_DATA_53_Q;
WR_DATA(52) <= NlwRenamedSig_OI_WR_DATA_52_Q;
WR_DATA(51) <= NlwRenamedSig_OI_WR_DATA_51_Q;
WR_DATA(50) <= NlwRenamedSig_OI_WR_DATA_50_Q;
WR_DATA(49) <= NlwRenamedSig_OI_WR_DATA_49_Q;
WR_DATA(48) <= NlwRenamedSig_OI_WR_DATA_48_Q;
WR_DATA(47) <= NlwRenamedSig_OI_WR_DATA_47_Q;
WR_DATA(46) <= NlwRenamedSig_OI_WR_DATA_46_Q;
WR_DATA(45) <= NlwRenamedSig_OI_WR_DATA_45_Q;
WR_DATA(44) <= NlwRenamedSig_OI_WR_DATA_44_Q;
WR_DATA(43) <= NlwRenamedSig_OI_WR_DATA_43_Q;
WR_DATA(42) <= NlwRenamedSig_OI_WR_DATA_42_Q;
WR_DATA(41) <= NlwRenamedSig_OI_WR_DATA_41_Q;
WR_DATA(40) <= NlwRenamedSig_OI_WR_DATA_40_Q;
WR_DATA(39) <= NlwRenamedSig_OI_WR_DATA_39_Q;
WR_DATA(38) <= NlwRenamedSig_OI_WR_DATA_38_Q;
WR_DATA(37) <= NlwRenamedSig_OI_WR_DATA_37_Q;
WR_DATA(36) <= NlwRenamedSig_OI_WR_DATA_36_Q;
WR_DATA(35) <= NlwRenamedSig_OI_WR_DATA_35_Q;
WR_DATA(34) <= NlwRenamedSig_OI_WR_DATA_34_Q;
WR_DATA(33) <= NlwRenamedSig_OI_WR_DATA_33_Q;
WR_DATA(32) <= NlwRenamedSig_OI_WR_DATA_32_Q;
WR_DATA(15) <= NlwRenamedSig_OI_WR_DATA_15_Q;
WR_DATA(14) <= NlwRenamedSig_OI_WR_DATA_14_Q;
WR_DATA(13) <= NlwRenamedSig_OI_WR_DATA_13_Q;
WR_DATA(12) <= NlwRenamedSig_OI_WR_DATA_12_Q;
WR_DATA(11) <= NlwRenamedSig_OI_WR_DATA_11_Q;
WR_DATA(10) <= NlwRenamedSig_OI_WR_DATA_10_Q;
WR_DATA(9) <= NlwRenamedSig_OI_WR_DATA_9_Q;
WR_DATA(8) <= NlwRenamedSig_OI_WR_DATA_8_Q;
WR_DATA(7) <= NlwRenamedSig_OI_WR_DATA_7_Q;
WR_DATA(6) <= NlwRenamedSig_OI_WR_DATA_6_Q;
WR_DATA(5) <= NlwRenamedSig_OI_WR_DATA_5_Q;
WR_DATA(4) <= NlwRenamedSig_OI_WR_DATA_4_Q;
WR_DATA(0) <= NlwRenamedSig_OI_WR_DATA_0_Q;
WR_ADDR(31) <= NlwRenamedSig_OI_WR_ADDR_31_Q;
WR_ADDR(30) <= NlwRenamedSig_OI_WR_ADDR_30_Q;
WR_ADDR(29) <= NlwRenamedSig_OI_WR_ADDR_29_Q;
WR_ADDR(28) <= NlwRenamedSig_OI_WR_ADDR_28_Q;
WR_ADDR(27) <= NlwRenamedSig_OI_WR_ADDR_27_Q;
WR_ADDR(26) <= NlwRenamedSig_OI_WR_ADDR_26_Q;
WR_ADDR(25) <= NlwRenamedSig_OI_WR_ADDR_25_Q;
WR_ADDR(24) <= NlwRenamedSig_OI_WR_ADDR_24_Q;
WR_ADDR(23) <= NlwRenamedSig_OI_WR_ADDR_23_Q;
WR_ADDR(22) <= NlwRenamedSig_OI_WR_ADDR_22_Q;
WR_ADDR(21) <= NlwRenamedSig_OI_WR_ADDR_21_Q;
WR_ADDR(20) <= NlwRenamedSig_OI_WR_ADDR_20_Q;
WR_ADDR(19) <= NlwRenamedSig_OI_WR_ADDR_19_Q;
WR_ADDR(18) <= NlwRenamedSig_OI_WR_ADDR_18_Q;
WR_ADDR(17) <= NlwRenamedSig_OI_WR_ADDR_17_Q;
WR_ADDR(16) <= NlwRenamedSig_OI_WR_ADDR_16_Q;
WR_ADDR(15) <= NlwRenamedSig_OI_WR_ADDR_15_Q;
WR_ADDR(14) <= NlwRenamedSig_OI_WR_ADDR_14_Q;
WR_ADDR(13) <= NlwRenamedSig_OI_WR_ADDR_13_Q;
WR_ADDR(12) <= NlwRenamedSig_OI_WR_ADDR_12_Q;
WR_ADDR(11) <= NlwRenamedSig_OI_WR_ADDR_11_Q;
WR_ADDR(10) <= NlwRenamedSig_OI_WR_ADDR_10_Q;
WR_ADDR(9) <= NlwRenamedSig_OI_WR_ADDR_9_Q;
WR_ADDR(8) <= NlwRenamedSig_OI_WR_ADDR_8_Q;
WR_ADDR(7) <= NlwRenamedSig_OI_WR_ADDR_7_Q;
WR_ADDR(6) <= NlwRenamedSig_OI_WR_ADDR_6_Q;
WR_ADDR(5) <= NlwRenamedSig_OI_WR_ADDR_5_Q;
WR_ADDR(4) <= NlwRenamedSig_OI_WR_ADDR_4_Q;
WR_ADDR(3) <= NlwRenamedSig_OI_WR_ADDR_3_Q;
WR_ADDR(2) <= NlwRenamedSig_OI_WR_ADDR_0_Q;
WR_ADDR(1) <= NlwRenamedSig_OI_WR_ADDR_0_Q;
WR_ADDR(0) <= NlwRenamedSig_OI_WR_ADDR_0_Q;
XST_GND : GND
port map (
G => NlwRenamedSig_OI_WR_ADDR_0_Q
);
XST_VCC : VCC
port map (
P => N1
);
IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd2 : FDR
generic map(
INIT => '0'
)
port map (
C => CLK,
D => IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd2_In,
R => RESET,
Q => IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd2_1477
);
IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd1 : FDR
generic map(
INIT => '0'
)
port map (
C => CLK,
D => IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd1_In,
R => RESET,
Q => IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd1_1475
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_xor_28_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(27),
LI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_rstpot_1441,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(28)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_xor_27_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(26),
LI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_27_rt_1324,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(27)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_27_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(26),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_27_rt_1324,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(27)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_xor_26_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(25),
LI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_26_rt_1322,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(26)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_26_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(25),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_26_rt_1322,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(26)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_xor_25_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(24),
LI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_25_rt_1320,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(25)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_25_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(24),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_25_rt_1320,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(25)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_xor_24_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(23),
LI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_24_rt_1318,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(24)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_24_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(23),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_24_rt_1318,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(24)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_xor_23_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(22),
LI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_23_rt_1316,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(23)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_23_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(22),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_23_rt_1316,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(23)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_xor_22_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(21),
LI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_22_rt_1314,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(22)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_22_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(21),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_22_rt_1314,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(22)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_xor_21_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(20),
LI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_21_rt_1312,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(21)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_21_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(20),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_21_rt_1312,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(21)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_xor_20_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(19),
LI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_20_rt_1310,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(20)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_20_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(19),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_20_rt_1310,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(20)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_xor_19_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(18),
LI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_19_rt_1306,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(19)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_19_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(18),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_19_rt_1306,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(19)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_xor_18_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(17),
LI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_18_rt_1304,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(18)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_18_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(17),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_18_rt_1304,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(18)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_xor_17_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(16),
LI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_17_rt_1302,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(17)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_17_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(16),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_17_rt_1302,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(17)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_xor_16_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(15),
LI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_16_rt_1300,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(16)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_16_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(15),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_16_rt_1300,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(16)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_xor_15_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(14),
LI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_15_rt_1298,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(15)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_15_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(14),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_15_rt_1298,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(15)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_xor_14_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(13),
LI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_14_rt_1296,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(14)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_14_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(13),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_14_rt_1296,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(14)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_xor_13_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(12),
LI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_13_rt_1294,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(13)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_13_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(12),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_13_rt_1294,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(13)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_xor_12_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(11),
LI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_12_rt_1292,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(12)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_12_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(11),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_12_rt_1292,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(12)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_xor_11_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(10),
LI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_11_rt_1290,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(11)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_11_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(10),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_11_rt_1290,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(11)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_xor_10_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(9),
LI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_10_rt_1288,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(10)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_10_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(9),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_10_rt_1288,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(10)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_xor_9_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(8),
LI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_9_rt_1338,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(9)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_9_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(8),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_9_rt_1338,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(9)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_xor_8_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(7),
LI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_8_rt_1336,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(8)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_8_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(7),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_8_rt_1336,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(8)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_xor_7_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(6),
LI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_7_rt_1334,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(7)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_7_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(6),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_7_rt_1334,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(7)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_xor_6_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(5),
LI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_6_rt_1332,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(6)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_6_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(5),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_6_rt_1332,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(6)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_xor_5_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(4),
LI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_5_rt_1330,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(5)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_5_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(4),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_5_rt_1330,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(5)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_xor_4_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(3),
LI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_4_rt_1328,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(4)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_4_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(3),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_4_rt_1328,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(4)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_xor_3_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(2),
LI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_3_rt_1326,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(3)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_3_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(2),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_3_rt_1326,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(3)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_xor_2_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(1),
LI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_2_rt_1308,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(2)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_2_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(1),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_2_rt_1308,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(2)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_xor_1_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(0),
LI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_1_rt_1286,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(1)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_1_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(0),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_1_rt_1286,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(1)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_xor_0_Q : XORCY
port map (
CI => NlwRenamedSig_OI_WR_ADDR_0_Q,
LI => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_lut(0),
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(0)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_0_Q : MUXCY
port map (
CI => NlwRenamedSig_OI_WR_ADDR_0_Q,
DI => N1,
S => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_lut(0),
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy(0)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_15 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_write_ctrl_addr_we,
D => NlwRenamedSig_OI_WR_DATA_15_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_15_1468
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_14 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_write_ctrl_addr_we,
D => NlwRenamedSig_OI_WR_DATA_14_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_14_1467
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_13 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_write_ctrl_addr_we,
D => NlwRenamedSig_OI_WR_DATA_13_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_13_1466
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_12 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_write_ctrl_addr_we,
D => NlwRenamedSig_OI_WR_DATA_12_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_12_1465
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_11 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_write_ctrl_addr_we,
D => NlwRenamedSig_OI_WR_DATA_11_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_11_1464
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_10 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_write_ctrl_addr_we,
D => NlwRenamedSig_OI_WR_DATA_10_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_10_1463
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_9 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_write_ctrl_addr_we,
D => NlwRenamedSig_OI_WR_DATA_9_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_9_1474
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_8 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_write_ctrl_addr_we,
D => NlwRenamedSig_OI_WR_DATA_8_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_8_1473
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_7 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_write_ctrl_addr_we,
D => NlwRenamedSig_OI_WR_DATA_7_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_7_1472
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_6 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_write_ctrl_addr_we,
D => NlwRenamedSig_OI_WR_DATA_6_Q,
Q => NlwRenamedSig_OI_IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_6
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_5 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_write_ctrl_addr_we,
D => NlwRenamedSig_OI_WR_DATA_5_Q,
Q => NlwRenamedSig_OI_IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_5
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_write_ctrl_addr_we,
D => NlwRenamedSig_OI_WR_DATA_4_Q,
Q => NlwRenamedSig_OI_IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_4
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_write_ctrl_addr_we,
D => NlwRenamedSig_OI_WR_DATA_34_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32(2)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_0 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_write_ctrl_addr_we,
D => NlwRenamedSig_OI_WR_DATA_32_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32(0)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_1 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_write_ctrl_addr_we,
D => NlwRenamedSig_OI_WR_DATA_33_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32(1)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2 : FDS
generic map(
INIT => '0'
)
port map (
C => CLK,
D => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_In,
S => RESET,
Q => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd1 : FDR
generic map(
INIT => '0'
)
port map (
C => CLK,
D => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd1_In,
R => RESET,
Q => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd1_1269
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_0_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(0),
Q => IB_UP_DATA(0)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_1_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(1),
Q => IB_UP_DATA(1)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_2_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(2),
Q => IB_UP_DATA(2)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_3_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(3),
Q => IB_UP_DATA(3)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_4_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(4),
Q => IB_UP_DATA(4)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_5_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(5),
Q => IB_UP_DATA(5)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_6_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(6),
Q => IB_UP_DATA(6)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_7_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(7),
Q => IB_UP_DATA(7)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_8_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(8),
Q => IB_UP_DATA(8)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_9_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(9),
Q => IB_UP_DATA(9)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_10_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(10),
Q => IB_UP_DATA(10)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_11_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(11),
Q => IB_UP_DATA(11)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_12_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(12),
Q => IB_UP_DATA(12)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_13_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(13),
Q => IB_UP_DATA(13)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_14_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(14),
Q => IB_UP_DATA(14)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_15_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(15),
Q => IB_UP_DATA(15)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_16_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(16),
Q => IB_UP_DATA(16)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_17_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(17),
Q => IB_UP_DATA(17)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_18_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(18),
Q => IB_UP_DATA(18)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_19_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(19),
Q => IB_UP_DATA(19)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_20_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(20),
Q => IB_UP_DATA(20)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_21_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(21),
Q => IB_UP_DATA(21)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_22_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(22),
Q => IB_UP_DATA(22)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_23_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(23),
Q => IB_UP_DATA(23)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_24_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(24),
Q => IB_UP_DATA(24)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_25_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(25),
Q => IB_UP_DATA(25)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_26_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(26),
Q => IB_UP_DATA(26)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_27_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(27),
Q => IB_UP_DATA(27)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_28_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(28),
Q => IB_UP_DATA(28)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_29_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(29),
Q => IB_UP_DATA(29)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_30_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(30),
Q => IB_UP_DATA(30)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_31_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(31),
Q => IB_UP_DATA(31)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_32_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(32),
Q => IB_UP_DATA(32)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_33_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(33),
Q => IB_UP_DATA(33)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_34_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(34),
Q => IB_UP_DATA(34)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_35_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(35),
Q => IB_UP_DATA(35)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_36_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(36),
Q => IB_UP_DATA(36)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_37_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(37),
Q => IB_UP_DATA(37)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_38_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(38),
Q => IB_UP_DATA(38)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_39_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(39),
Q => IB_UP_DATA(39)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_40_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(40),
Q => IB_UP_DATA(40)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_41_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(41),
Q => IB_UP_DATA(41)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_42_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(42),
Q => IB_UP_DATA(42)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_43_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(43),
Q => IB_UP_DATA(43)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_44_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(44),
Q => IB_UP_DATA(44)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_45_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(45),
Q => IB_UP_DATA(45)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_46_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(46),
Q => IB_UP_DATA(46)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_47_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(47),
Q => IB_UP_DATA(47)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_48_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(48),
Q => IB_UP_DATA(48)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_49_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(49),
Q => IB_UP_DATA(49)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_50_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(50),
Q => IB_UP_DATA(50)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_51_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(51),
Q => IB_UP_DATA(51)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_52_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(52),
Q => IB_UP_DATA(52)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_53_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(53),
Q => IB_UP_DATA(53)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_54_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(54),
Q => IB_UP_DATA(54)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_55_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(55),
Q => IB_UP_DATA(55)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_56_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(56),
Q => IB_UP_DATA(56)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_57_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(57),
Q => IB_UP_DATA(57)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_58_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(58),
Q => IB_UP_DATA(58)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_59_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(59),
Q => IB_UP_DATA(59)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_60_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(60),
Q => IB_UP_DATA(60)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_61_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(61),
Q => IB_UP_DATA(61)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_62_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(62),
Q => IB_UP_DATA(62)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_63_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_data(63),
Q => IB_UP_DATA(63)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_64_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_pipe_sof_n,
Q => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_out_data_aux(64)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_65_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_cpl_pipe_eof_n,
Q => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_out_data_aux(65)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd2 : FDS
generic map(
INIT => '0'
)
port map (
C => CLK,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd2_In,
S => RESET,
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd2_629
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_0_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(0),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(0)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_1_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(1),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(1)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_2_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(2),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(2)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_3_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(3),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(3)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_4_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(4),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(4)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_5_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(5),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(5)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_6_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(6),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(6)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_7_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(7),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(7)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_8_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(8),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(8)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_9_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(9),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(9)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_10_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(10),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(10)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_11_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(11),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(11)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_12_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(12),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(12)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_13_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(13),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(13)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_14_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(14),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(14)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_15_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(15),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(15)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_16_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(16),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(16)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_17_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(17),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(17)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_18_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(18),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(18)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_19_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(19),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(19)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_20_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(20),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(20)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_21_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(21),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(21)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_22_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(22),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(22)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_23_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(23),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(23)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_24_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(24),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(24)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_25_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(25),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(25)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_26_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(26),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(26)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_27_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(27),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(27)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_28_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(28),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(28)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_29_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(29),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(29)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_30_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(30),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(30)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_31_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(31),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(31)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_32_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_downrd_data(32),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(32)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_33_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_downrd_data(33),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(33)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_34_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_downrd_data(34),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(34)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_35_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_downrd_data(35),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(35)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_36_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_downrd_data(36),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(36)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_37_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_downrd_data(37),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(37)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_38_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_downrd_data(38),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(38)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_39_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_downrd_data(39),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(39)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_40_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_downrd_data(40),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(40)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_41_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_downrd_data(41),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(41)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_42_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_downrd_data(42),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(42)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_43_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_downrd_data(43),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(43)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_44_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_downrd_data(44),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(44)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_45_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_downrd_data(45),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(45)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_46_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_downrd_data(46),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(46)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_47_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_downrd_data(47),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(47)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_48_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_downrd_data(48),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(48)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_49_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_downrd_data(49),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(49)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_50_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_downrd_data(50),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(50)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_51_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_downrd_data(51),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(51)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_52_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_downrd_data(52),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(52)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_53_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_downrd_data(53),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(53)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_54_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_downrd_data(54),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(54)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_55_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_downrd_data(55),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(55)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_56_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_downrd_data(56),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(56)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_57_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_downrd_data(57),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(57)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_58_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_downrd_data(58),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(58)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_59_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_downrd_data(59),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(59)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_60_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_downrd_data(60),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(60)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_61_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_downrd_data(61),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(61)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_62_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_downrd_data(62),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(62)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_63_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_downrd_data(63),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(63)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_64_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_downrd_sof_n,
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(64)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_65_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce,
CLK => CLK,
D => IB_ENDPOINT_I_downrd_eof_n,
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(65)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_65 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(65),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(65)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_64 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(64),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(64)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_63 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(63),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(63)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_62 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(62),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(62)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_61 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(61),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(61)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_60 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(60),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(60)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_59 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(59),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(59)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_58 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(58),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(58)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_57 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(57),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(57)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_56 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(56),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(56)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_55 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(55),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(55)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_54 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(54),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(54)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_53 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(53),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(53)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_52 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(52),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(52)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_51 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(51),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(51)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_50 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(50),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(50)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_49 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(49),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(49)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_48 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(48),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(48)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_47 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(47),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(47)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_46 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(46),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(46)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_45 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(45),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(45)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_44 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(44),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(44)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_43 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(43),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(43)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_42 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(42),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(42)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_41 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(41),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(41)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_40 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(40),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(40)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_39 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(39),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(39)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_38 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(38),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(38)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_37 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(37),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(37)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_36 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(36),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(36)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_35 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(35),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(35)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_34 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(34),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(34)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_33 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(33),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(33)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_32 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(32),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(32)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_31 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(31),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(31)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_30 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(30),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(30)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_29 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(29),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(29)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_28 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(28),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(28)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_27 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(27),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(27)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_26 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(26),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(26)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_25 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(25),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(25)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_24 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(24),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(24)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_23 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(23),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(23)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_22 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(22),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(22)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_21 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(21),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(21)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_20 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(20),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(20)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_19 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(19),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(19)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_18 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(18),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(18)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_17 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(17),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(17)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_16 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(16),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(16)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_15 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(15),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(15)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_14 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(14),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(14)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_13 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(13),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(13)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_12 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(12),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(12)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_11 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(11),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(11)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_10 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(10),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(10)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_9 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(9),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(9)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_8 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(8),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(8)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_7 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(7),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(7)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_6 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(6),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(6)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_5 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(5),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(5)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(4),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(4)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_3 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(3),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(3)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(2),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(2)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_1 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(1),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(1)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_0 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_dout(0),
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(0)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_rdy : FDRE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd1,
R => RESET,
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_rdy_697
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2 : FDP
generic map(
INIT => '0'
)
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_In,
PRE => RESET,
Q => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_760
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd1 : FDC
generic map(
INIT => '0'
)
port map (
C => CLK,
CLR => RESET,
D => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd1_In_759,
Q => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd1_758
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr_0 : FDCE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr_ce,
CLR => RESET,
D => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Result(0),
Q => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0)
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr_1 : FDCE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr_ce,
CLR => RESET,
D => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Result(1),
Q => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1)
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr_2 : FDCE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr_ce,
CLR => RESET,
D => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Result(2),
Q => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2)
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr_3 : FDCE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr_ce,
CLR => RESET,
D => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Result(3),
Q => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3)
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_10_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(10),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(10),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_10_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_1_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(1),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(1),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_1_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_0_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(0),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(0),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_0_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_2_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(2),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(2),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_2_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_11_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(11),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(11),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_11_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_3_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(3),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(3),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_3_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_12_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(12),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(12),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_12_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_4_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(4),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(4),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_4_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_13_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(13),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(13),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_13_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_5_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(5),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(5),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_5_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_14_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(14),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(14),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_14_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_6_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(6),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(6),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_6_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_15_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(15),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(15),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_15_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_20_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(20),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(20),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_20_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_7_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(7),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(7),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_7_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_16_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(16),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(16),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_16_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_17_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(17),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(17),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_17_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_22_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(22),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(22),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_22_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_21_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(21),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(21),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_21_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_8_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(8),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(8),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_8_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_9_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(9),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(9),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_9_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_18_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(18),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(18),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_18_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_23_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(23),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(23),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_23_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_24_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(24),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(24),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_24_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_19_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(19),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(19),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_19_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_30_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(30),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(30),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_30_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_25_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(25),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(25),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_25_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_31_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(31),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(31),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_31_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_26_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(26),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(26),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_26_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_32_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(32),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(32),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_32_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_27_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(27),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(27),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_27_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_33_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(33),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(33),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_33_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_28_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(28),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(28),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_28_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_40_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(40),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(40),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_40_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_35_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(35),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(35),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_35_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_34_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(34),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(34),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_34_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_29_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(29),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(29),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_29_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_41_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(41),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(41),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_41_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_36_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(36),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(36),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_36_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_42_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(42),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(42),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_42_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_37_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(37),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(37),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_37_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_43_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(43),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(43),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_43_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_38_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(38),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(38),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_38_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_44_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(44),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(44),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_44_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_39_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(39),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(39),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_39_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_50_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(50),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(50),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_50_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_45_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(45),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(45),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_45_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_51_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(51),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(51),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_51_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_46_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(46),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(46),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_46_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_52_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(52),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(52),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_52_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_47_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(47),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(47),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_47_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_53_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(53),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(53),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_53_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_48_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(48),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(48),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_48_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_54_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(54),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(54),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_54_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_49_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(49),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(49),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_49_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_60_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(60),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(60),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_60_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_55_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(55),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(55),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_55_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_61_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(61),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(61),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_61_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_56_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(56),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(56),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_56_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_62_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(62),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(62),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_62_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_57_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(57),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(57),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_57_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_63_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(63),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(63),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_63_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_58_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(58),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(58),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_58_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_59_0 : SRLC16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
A1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
A2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
A3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
CE => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce,
CLK => CLK,
D => RD_DATA(59),
Q => IB_ENDPOINT_I_U_read_ctrl_align_in_data(59),
Q15 => NLW_IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Mshreg_dout_int_59_0_Q15_UNCONNECTED
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_present_state_0 : FDR
generic map(
INIT => '0'
)
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_next_state,
R => RESET,
Q => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_present_state(0)
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_cy_0_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data_and0000,
DI => N1,
S => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut(0),
O => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_cy(0)
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_xor_0_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data_and0000,
LI => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut(0),
O => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_cy_1_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_cy(0),
DI => N1,
S => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut(1),
O => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_cy(1)
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_xor_1_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_cy(0),
LI => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut(1),
O => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data1
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_cy_2_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_cy(1),
DI => N1,
S => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut(2),
O => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_cy(2)
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_xor_2_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_cy(1),
LI => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut(2),
O => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data2
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_cy_3_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_cy(2),
DI => N1,
S => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut(3),
O => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_cy(3)
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_xor_3_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_cy(2),
LI => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut(3),
O => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data3
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_cy_4_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_cy(3),
DI => N1,
S => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut(4),
O => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_cy(4)
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_xor_4_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_cy(3),
LI => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut(4),
O => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data4
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_cy_5_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_cy(4),
DI => N1,
S => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut(5),
O => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_cy(5)
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_xor_5_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_cy(4),
LI => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut(5),
O => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data5
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_cy_6_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_cy(5),
DI => N1,
S => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut(6),
O => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_cy(6)
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_xor_6_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_cy(5),
LI => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut(6),
O => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data6
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_cy_7_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_cy(6),
DI => N1,
S => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut(7),
O => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_cy(7)
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_xor_7_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_cy(6),
LI => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut(7),
O => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data7
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_cy_8_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_cy(7),
DI => N1,
S => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut(8),
O => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_cy(8)
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_xor_8_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_cy(7),
LI => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut(8),
O => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data8
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_xor_9_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_cy(8),
LI => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut(9),
O => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data9
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data_0 : FDRE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data_not0001,
D => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data,
R => RESET,
Q => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data(0)
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data_1 : FDRE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data_not0001,
D => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data1,
R => RESET,
Q => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data(1)
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data_2 : FDRE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data_not0001,
D => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data2,
R => RESET,
Q => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data(2)
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data_3 : FDRE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data_not0001,
D => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data3,
R => RESET,
Q => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data(3)
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data_4 : FDRE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data_not0001,
D => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data4,
R => RESET,
Q => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data(4)
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data_5 : FDRE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data_not0001,
D => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data5,
R => RESET,
Q => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data(5)
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data_6 : FDRE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data_not0001,
D => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data6,
R => RESET,
Q => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data(6)
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data_7 : FDRE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data_not0001,
D => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data7,
R => RESET,
Q => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data(7)
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data_8 : FDRE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data_not0001,
D => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data8,
R => RESET,
Q => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data(8)
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data_9 : FDRE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data_not0001,
D => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data9,
R => RESET,
Q => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data(9)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpck_hbuf_data_out_0 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_unpck_hbuf_we,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(0),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpck_hbuf_data_out(0)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpck_hbuf_data_out_1 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_unpck_hbuf_we,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(1),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpck_hbuf_data_out(1)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpck_hbuf_data_out_2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_unpck_hbuf_we,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(2),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpck_hbuf_data_out(2)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpck_hbuf_data_out_3 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_unpck_hbuf_we,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(3),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpck_hbuf_data_out(3)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpck_hbuf_data_out_4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_unpck_hbuf_we,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(4),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpck_hbuf_data_out(4)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpck_hbuf_data_out_5 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_unpck_hbuf_we,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(5),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpck_hbuf_data_out(5)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpck_hbuf_data_out_6 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_unpck_hbuf_we,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(6),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpck_hbuf_data_out(6)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpck_hbuf_data_out_7 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_unpck_hbuf_we,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(7),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpck_hbuf_data_out(7)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpck_hbuf_data_out_8 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_unpck_hbuf_we,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(8),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpck_hbuf_data_out(8)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpck_hbuf_data_out_9 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_unpck_hbuf_we,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(9),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpck_hbuf_data_out(9)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpck_hbuf_reg_full : FDRSE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_unpck_hbuf_re,
D => NlwRenamedSig_OI_WR_ADDR_0_Q,
R => RESET,
S => IB_ENDPOINT_I_U_read_ctrl_unpck_hbuf_we,
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpck_hbuf_reg_full_1196
);
IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd1 : FDR
generic map(
INIT => '0'
)
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd1_In,
R => RESET,
Q => IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd1_912
);
IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd2 : FDR
generic map(
INIT => '0'
)
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd2_In,
R => RESET,
Q => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd2
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_0 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_header_last,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(0),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(0)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_1 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_header_last,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(1),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(1)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_header_last,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(2),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(2)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_done_flag_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(4),
Q => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_4
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_5 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_done_flag_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(5),
Q => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_5
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_6 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_done_flag_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(6),
Q => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_6
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_7 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_done_flag_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(7),
Q => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_7
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_8 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_done_flag_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(8),
Q => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_8
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_9 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_done_flag_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(9),
Q => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_9
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_10 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_done_flag_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(10),
Q => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_10
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_11 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_done_flag_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(11),
Q => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_11
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_12 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_done_flag_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(12),
Q => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_12
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_13 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_done_flag_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(13),
Q => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_13
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_14 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_done_flag_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(14),
Q => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_14
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_15 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_done_flag_we,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(15),
Q => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_15
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_cy_0_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count_and0000,
DI => N1,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut(0),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_cy(0)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_xor_0_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count_and0000,
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut(0),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_cy_1_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_cy(0),
DI => N1,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut(1),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_cy(1)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_xor_1_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_cy(0),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut(1),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count1
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_cy_2_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_cy(1),
DI => N1,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut(2),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_cy(2)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_xor_2_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_cy(1),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut(2),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count2
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_cy_3_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_cy(2),
DI => N1,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut(3),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_cy(3)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_xor_3_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_cy(2),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut(3),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count3
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_cy_4_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_cy(3),
DI => N1,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut(4),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_cy(4)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_xor_4_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_cy(3),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut(4),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count4
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_cy_5_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_cy(4),
DI => N1,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut(5),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_cy(5)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_xor_5_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_cy(4),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut(5),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count5
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_cy_6_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_cy(5),
DI => N1,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut(6),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_cy(6)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_xor_6_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_cy(5),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut(6),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count6
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_cy_7_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_cy(6),
DI => N1,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut(7),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_cy(7)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_xor_7_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_cy(6),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut(7),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count7
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_cy_8_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_cy(7),
DI => N1,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut(8),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_cy(8)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_xor_8_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_cy(7),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut(8),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count8
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_xor_9_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_cy(8),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut(9),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count9
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count_0 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_3_not0001,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count,
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(0)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count_1 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_3_not0001,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count1,
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(1)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count_2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_3_not0001,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count2,
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(2)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count_3 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_3_not0001,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count3,
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(3)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count_4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_3_not0001,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count4,
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(4)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count_5 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_3_not0001,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count5,
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(5)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count_6 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_3_not0001,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count6,
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(6)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count_7 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_3_not0001,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count7,
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(7)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count_8 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_3_not0001,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count8,
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(8)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count_9 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_3_not0001,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count9,
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(9)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_lut_0_Q : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(0),
I1 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_4,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_lut_0_Q_939
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_0_Q : MUXCY
port map (
CI => N1,
DI => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(0),
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_lut_0_Q_939,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy(0)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_1_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy(0),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1R,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy(1)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_2_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy(1),
DI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1C,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_lut_2_Q_940,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy(2)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_3_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy(2),
DI => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_7,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_lut_3_Q_941,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy(3)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_xor_3_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy(2),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_lut_3_Q_941,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_count_aux1(3)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_4_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy(3),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_4_rt_928,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy(4)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_xor_4_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy(3),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_4_rt_928,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_count_aux1(4)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_5_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy(4),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_5_rt_930,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy(5)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_xor_5_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy(4),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_5_rt_930,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_count_aux1(5)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_6_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy(5),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_6_rt_932,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy(6)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_xor_6_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy(5),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_6_rt_932,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_count_aux1(6)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_7_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy(6),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_7_rt_934,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy(7)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_xor_7_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy(6),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_7_rt_934,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_count_aux1(7)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_8_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy(7),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_8_rt_936,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy(8)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_xor_8_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy(7),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_8_rt_936,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_count_aux1(8)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_9_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy(8),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_9_rt_938,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy(9)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_xor_9_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy(8),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_9_rt_938,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_count_aux1(9)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_10_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy(9),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_10_rt_922,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy(10)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_xor_10_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy(9),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_10_rt_922,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_count_aux1(10)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_11_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy(10),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_11_rt_924,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy(11)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_xor_11_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy(10),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_11_rt_924,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_count_aux1(11)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_xor_12_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy(11),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_flag4096,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_count_aux1(12)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_0_Q : MUXCY
port map (
CI => NlwRenamedSig_OI_WR_ADDR_0_Q,
DI => N1,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_lut(0),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(0)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_xor_0_Q : XORCY
port map (
CI => NlwRenamedSig_OI_WR_ADDR_0_Q,
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_lut(0),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(0)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_1_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(0),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_1_rt_944,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(1)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_xor_1_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(0),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_1_rt_944,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(1)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_2_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(1),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_2_rt_966,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(2)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_xor_2_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(1),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_2_rt_966,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(2)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_3_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(2),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_3_rt_984,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(3)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_xor_3_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(2),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_3_rt_984,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(3)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_4_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(3),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_4_rt_986,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(4)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_xor_4_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(3),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_4_rt_986,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(4)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_5_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(4),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_5_rt_988,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(5)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_xor_5_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(4),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_5_rt_988,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(5)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_6_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(5),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_6_rt_990,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(6)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_xor_6_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(5),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_6_rt_990,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(6)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_7_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(6),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_7_rt_992,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(7)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_xor_7_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(6),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_7_rt_992,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(7)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_8_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(7),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_8_rt_994,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(8)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_xor_8_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(7),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_8_rt_994,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(8)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_9_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(8),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_9_rt_996,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(9)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_xor_9_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(8),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_9_rt_996,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(9)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_10_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(9),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_10_rt_946,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(10)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_xor_10_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(9),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_10_rt_946,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(10)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_11_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(10),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_11_rt_948,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(11)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_xor_11_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(10),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_11_rt_948,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(11)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_12_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(11),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_12_rt_950,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(12)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_xor_12_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(11),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_12_rt_950,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(12)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_13_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(12),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_13_rt_952,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(13)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_xor_13_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(12),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_13_rt_952,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(13)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_14_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(13),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_14_rt_954,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(14)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_xor_14_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(13),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_14_rt_954,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(14)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_15_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(14),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_15_rt_956,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(15)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_xor_15_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(14),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_15_rt_956,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(15)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_16_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(15),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_16_rt_958,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(16)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_xor_16_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(15),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_16_rt_958,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(16)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_17_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(16),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_17_rt_960,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(17)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_xor_17_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(16),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_17_rt_960,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(17)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_18_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(17),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_18_rt_962,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(18)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_xor_18_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(17),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_18_rt_962,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(18)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_19_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(18),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_19_rt_964,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(19)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_xor_19_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(18),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_19_rt_964,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(19)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_20_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(19),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_20_rt_968,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(20)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_xor_20_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(19),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_20_rt_968,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(20)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_21_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(20),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_21_rt_970,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(21)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_xor_21_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(20),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_21_rt_970,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(21)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_22_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(21),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_22_rt_972,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(22)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_xor_22_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(21),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_22_rt_972,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(22)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_23_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(22),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_23_rt_974,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(23)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_xor_23_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(22),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_23_rt_974,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(23)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_24_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(23),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_24_rt_976,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(24)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_xor_24_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(23),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_24_rt_976,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(24)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_25_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(24),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_25_rt_978,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(25)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_xor_25_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(24),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_25_rt_978,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(25)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_26_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(25),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_26_rt_980,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(26)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_xor_26_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(25),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_26_rt_980,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(26)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_27_Q : MUXCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(26),
DI => NlwRenamedSig_OI_WR_ADDR_0_Q,
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_27_rt_982,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(27)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_xor_27_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(26),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_27_rt_982,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(27)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_xor_28_Q : XORCY
port map (
CI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy(27),
LI => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_rstpot_1140,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(28)
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state_0 : FDR
generic map(
INIT => '0'
)
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_next_state,
R => RESET,
Q => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0)
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd1 : FDC
generic map(
INIT => '0'
)
port map (
C => CLK,
CLR => RESET,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd1_In,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd1_771
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_65_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_65_0_901,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_65_1_902
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_65_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_rd_pipe_sof_n,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_65_0_901
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_59_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_59_0_887,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_59_1_888
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_59_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(59),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_59_0_887
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_64_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_64_0_899,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_64_1_900
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_64_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_rd_pipe_eof_n,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_64_0_899
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_58_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_58_0_885,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_58_1_886
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_58_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(58),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_58_0_885
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_63_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_63_0_897,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_63_1_898
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_63_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(63),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_63_0_897
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_57_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_57_0_883,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_57_1_884
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_57_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(57),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_57_0_883
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_62_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_62_0_895,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_62_1_896
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_62_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(62),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_62_0_895
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_56_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_56_0_881,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_56_1_882
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_56_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(56),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_56_0_881
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_61_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_61_0_893,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_61_1_894
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_61_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(61),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_61_0_893
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_55_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_55_0_879,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_55_1_880
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_55_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(55),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_55_0_879
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_60_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_60_0_891,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_60_1_892
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_60_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(60),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_60_0_891
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_49_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_49_0_865,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_49_1_866
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_49_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(49),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_49_0_865
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_54_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_54_0_877,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_54_1_878
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_54_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(54),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_54_0_877
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_48_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_48_0_863,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_48_1_864
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_48_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(48),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_48_0_863
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_47_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_47_0_861,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_47_1_862
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_47_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(47),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_47_0_861
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_53_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_53_0_875,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_53_1_876
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_53_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(53),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_53_0_875
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_52_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_52_0_873,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_52_1_874
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_52_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(52),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_52_0_873
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_46_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_46_0_859,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_46_1_860
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_46_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(46),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_46_0_859
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_51_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_51_0_871,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_51_1_872
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_51_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(51),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_51_0_871
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_45_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_45_0_857,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_45_1_858
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_45_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(45),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_45_0_857
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_50_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_50_0_869,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_50_1_870
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_50_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(50),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_50_0_869
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_39_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_39_0_843,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_39_1_844
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_39_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(39),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_39_0_843
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_44_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_44_0_855,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_44_1_856
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_44_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(44),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_44_0_855
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_38_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_38_0_841,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_38_1_842
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_38_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(38),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_38_0_841
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_43_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_43_0_853,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_43_1_854
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_43_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(43),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_43_0_853
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_37_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_37_0_839,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_37_1_840
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_37_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(37),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_37_0_839
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_42_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_42_0_851,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_42_1_852
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_42_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(42),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_42_0_851
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_36_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_36_0_837,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_36_1_838
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_36_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(36),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_36_0_837
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_41_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_41_0_849,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_41_1_850
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_41_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(41),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_41_0_849
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_35_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_35_0_835,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_35_1_836
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_35_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(35),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_35_0_835
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_29_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_29_0_821,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_29_1_822
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_29_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(29),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_29_0_821
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_34_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_34_0_833,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_34_1_834
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_34_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(34),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_34_0_833
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_40_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_40_0_847,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_40_1_848
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_40_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(40),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_40_0_847
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_28_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_28_0_819,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_28_1_820
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_28_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(28),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_28_0_819
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_33_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_33_0_831,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_33_1_832
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_33_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(33),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_33_0_831
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_27_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_27_0_817,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_27_1_818
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_27_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(27),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_27_0_817
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_32_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_32_0_829,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_32_1_830
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_32_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(32),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_32_0_829
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_26_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_26_0_815,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_26_1_816
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_26_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(26),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_26_0_815
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_31_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_31_0_827,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_31_1_828
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_31_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(31),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_31_0_827
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_25_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_25_0_813,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_25_1_814
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_25_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(25),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_25_0_813
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_30_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_30_0_825,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_30_1_826
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_30_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(30),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_30_0_825
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_19_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_19_0_799,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_19_1_800
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_19_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(19),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_19_0_799
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_24_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_24_0_811,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_24_1_812
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_24_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(24),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_24_0_811
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_23_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_23_0_809,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_23_1_810
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_23_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(23),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_23_0_809
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_18_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_18_0_797,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_18_1_798
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_18_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(18),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_18_0_797
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_9_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_9_0_909,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_9_1_910
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_9_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(9),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_9_0_909
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_22_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_22_0_807,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_22_1_808
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_22_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(22),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_22_0_807
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_8_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_8_0_907,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_8_1_908
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_8_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(8),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_8_0_907
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_21_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_21_0_805,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_21_1_806
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_21_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(21),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_21_0_805
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_17_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_17_0_795,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_17_1_796
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_17_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(17),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_17_0_795
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_16_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_16_0_793,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_16_1_794
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_16_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(16),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_16_0_793
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_7_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_7_0_905,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_7_1_906
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_7_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(7),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_7_0_905
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_20_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_20_0_803,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_20_1_804
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_20_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(20),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_20_0_803
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_15_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_15_0_791,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_15_1_792
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_15_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(15),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_15_0_791
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_6_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_6_0_903,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_6_1_904
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_6_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(6),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_6_0_903
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_14_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_14_0_789,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_14_1_790
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_14_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(14),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_14_0_789
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_5_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_5_0_889,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_5_1_890
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_5_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(5),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_5_0_889
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_13_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_13_0_787,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_13_1_788
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_13_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(13),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_13_0_787
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_4_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_4_0_867,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_4_1_868
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_4_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(4),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_4_0_867
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_12_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_12_0_785,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_12_1_786
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_12_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(12),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_12_0_785
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_3_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_3_0_845,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_3_1_846
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_3_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(3),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_3_0_845
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_11_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_11_0_783,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_11_1_784
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_11_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(11),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_11_0_783
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_2_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_2_0_823,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_2_1_824
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_2_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(2),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_2_0_823
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_10_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_10_0_781,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_10_1_782
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_10_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(10),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_10_0_781
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_0_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_0_0_779,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_0_1_780
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_0_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(0),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_0_0_779
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_1_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_1_0_801,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_1_1_802
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_1_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(1),
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_1_0_801
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_const_base_cnt_sel_0_0 : FDRE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addrpart_we,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_const_base_cnt_sel_0_0_not0000,
R => RESET,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_const_base_cnt_sel_0_0_108
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_const_limit_cnt_sel_0_0 : FDRE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addrpart_we,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_const_limit_cnt_sel_0_0_not0000,
R => RESET,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_const_limit_cnt_sel_0_0_110
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_1_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(1),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_1_0_145
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_1_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_1_0_145,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_1_1_146
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_0_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(0),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_0_0_123
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_0_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_0_0_123,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_0_1_124
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_10_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(10),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_10_0_125
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_10_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_10_0_125,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_10_1_126
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_2_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(2),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_2_0_167
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_2_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_2_0_167,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_2_1_168
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_11_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(11),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_11_0_127
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_11_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_11_0_127,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_11_1_128
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_3_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(3),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_3_0_189
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_3_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_3_0_189,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_3_1_190
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_12_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(12),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_12_0_129
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_12_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_12_0_129,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_12_1_130
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_4_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(4),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_4_0_211
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_4_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_4_0_211,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_4_1_212
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_13_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(13),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_13_0_131
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_13_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_13_0_131,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_13_1_132
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_5_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(5),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_5_0_233
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_5_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_5_0_233,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_5_1_234
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_14_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(14),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_14_0_133
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_14_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_14_0_133,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_14_1_134
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_6_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(6),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_6_0_247
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_6_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_6_0_247,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_6_1_248
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_15_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(15),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_15_0_135
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_15_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_15_0_135,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_15_1_136
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_20_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(20),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_20_0_147
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_20_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_20_0_147,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_20_1_148
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_7_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(7),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_7_0_249
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_7_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_7_0_249,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_7_1_250
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_16_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(16),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_16_0_137
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_16_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_16_0_137,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_16_1_138
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_17_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(17),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_17_0_139
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_17_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_17_0_139,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_17_1_140
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_21_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(21),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_21_0_149
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_21_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_21_0_149,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_21_1_150
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_8_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(8),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_8_0_251
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_8_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_8_0_251,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_8_1_252
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_22_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(22),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_22_0_151
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_22_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_22_0_151,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_22_1_152
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_9_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(9),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_9_0_253
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_9_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_9_0_253,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_9_1_254
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_18_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(18),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_18_0_141
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_18_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_18_0_141,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_18_1_142
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_23_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(23),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_23_0_153
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_23_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_23_0_153,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_23_1_154
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_24_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(24),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_24_0_155
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_24_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_24_0_155,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_24_1_156
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_19_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(19),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_19_0_143
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_19_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_19_0_143,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_19_1_144
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_30_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(30),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_30_0_169
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_30_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_30_0_169,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_30_1_170
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_25_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(25),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_25_0_157
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_25_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_25_0_157,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_25_1_158
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_31_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(31),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_31_0_171
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_31_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_31_0_171,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_31_1_172
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_26_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(26),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_26_0_159
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_26_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_26_0_159,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_26_1_160
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_32_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(32),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_32_0_173
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_32_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_32_0_173,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_32_1_174
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_27_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(27),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_27_0_161
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_27_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_27_0_161,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_27_1_162
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_33_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(33),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_33_0_175
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_33_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_33_0_175,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_33_1_176
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_28_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(28),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_28_0_163
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_28_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_28_0_163,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_28_1_164
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_40_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(40),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_40_0_191
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_40_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_40_0_191,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_40_1_192
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_34_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(34),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_34_0_177
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_34_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_34_0_177,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_34_1_178
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_29_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(29),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_29_0_165
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_29_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_29_0_165,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_29_1_166
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_35_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(35),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_35_0_179
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_35_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_35_0_179,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_35_1_180
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_41_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(41),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_41_0_193
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_41_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_41_0_193,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_41_1_194
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_36_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(36),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_36_0_181
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_36_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_36_0_181,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_36_1_182
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_42_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(42),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_42_0_195
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_42_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_42_0_195,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_42_1_196
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_37_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(37),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_37_0_183
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_37_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_37_0_183,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_37_1_184
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_43_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(43),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_43_0_197
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_43_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_43_0_197,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_43_1_198
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_38_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(38),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_38_0_185
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_38_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_38_0_185,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_38_1_186
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_44_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(44),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_44_0_199
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_44_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_44_0_199,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_44_1_200
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_39_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(39),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_39_0_187
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_39_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_39_0_187,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_39_1_188
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_50_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(50),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_50_0_213
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_50_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_50_0_213,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_50_1_214
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_45_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(45),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_45_0_201
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_45_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_45_0_201,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_45_1_202
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_51_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(51),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_51_0_215
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_51_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_51_0_215,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_51_1_216
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_46_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(46),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_46_0_203
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_46_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_46_0_203,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_46_1_204
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_52_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(52),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_52_0_217
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_52_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_52_0_217,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_52_1_218
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_53_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(53),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_53_0_219
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_53_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_53_0_219,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_53_1_220
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_47_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(47),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_47_0_205
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_47_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_47_0_205,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_47_1_206
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_48_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(48),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_48_0_207
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_48_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_48_0_207,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_48_1_208
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_54_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(54),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_54_0_221
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_54_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_54_0_221,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_54_1_222
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_49_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(49),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_49_0_209
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_49_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_49_0_209,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_49_1_210
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_60_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(60),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_60_0_235
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_60_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_60_0_235,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_60_1_236
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_55_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(55),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_55_0_223
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_55_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_55_0_223,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_55_1_224
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_61_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(61),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_61_0_237
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_61_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_61_0_237,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_61_1_238
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_56_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(56),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_56_0_225
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_56_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_56_0_225,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_56_1_226
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_62_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(62),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_62_0_239
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_62_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_62_0_239,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_62_1_240
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_57_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(57),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_57_0_227
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_57_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_57_0_227,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_57_1_228
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_63_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(63),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_63_0_241
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_63_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_63_0_241,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_63_1_242
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_58_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(58),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_58_0_229
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_58_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_58_0_229,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_58_1_230
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_64_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_eof_n,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_64_0_243
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_64_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_64_0_243,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_64_1_244
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_59_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(59),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_59_0_231
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_59_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_59_0_231,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_59_1_232
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_65_0 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_sof_n,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_65_0_245
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_65_1 : FDE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_65_0_245,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_65_1_246
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd1 : FDC
generic map(
INIT => '0'
)
port map (
C => CLK,
CLR => RESET,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd1_In,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd1_114
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr_15 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr_we,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(63),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(15)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr_14 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr_we,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(62),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(14)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr_13 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr_we,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(61),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(13)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr_12 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr_we,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(60),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(12)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr_11 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr_we,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(59),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(11)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr_10 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr_we,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(58),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(10)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr_9 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr_we,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(57),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(9)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr_8 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr_we,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(56),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(8)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr_7 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr_we,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(55),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(7)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr_6 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr_we,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(54),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(6)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr_5 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr_we,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(53),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(5)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr_4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr_we,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(52),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(4)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr_3 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr_we,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(51),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(3)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr_2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr_we,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(50),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(2)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr_1 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr_we,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(49),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(1)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr_0 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr_we,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(48),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(0)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd2 : FDR
generic map(
INIT => '0'
)
port map (
C => CLK,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd2_In,
R => RESET,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd2_265
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd1 : FDR
generic map(
INIT => '0'
)
port map (
C => CLK,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd1_In,
R => RESET,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd1_263
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_U_reg_cyc_type_lg_we_SH_REG_XU_0_SH_REG_U_U_SRL16E :
SRL16E
generic map(
INIT => X"0001"
)
port map (
A0 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_ce_addr_start,
CLK => CLK,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_U_reg_cyc_type_lg_we_regsh_do(0),
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_U_reg_cyc_type_lg_we_regsh_do(0)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_U_reg_cyc_addr_start_SH_REG_XU_0_SH_REG_U_U_SRL16E :
SRL16E
generic map(
INIT => X"0001"
)
port map (
A0 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_ce_addr_start,
CLK => CLK,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_addr_start_aux,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_addr_start_aux
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_U_reg_cyc_addr_last_SH_REG_XU_0_SH_REG_U_U_SRL16E :
SRL16E
generic map(
INIT => X"0001"
)
port map (
A0 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_ce_addr_last,
CLK => CLK,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_addr_last_aux,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_addr_last_aux
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_cnt_addrpart_we_0_0 : FDRE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addrpart_we,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_cnt_addrpart_we_0_0_not0000,
R => RESET,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_cnt_addrpart_we_0_0_261
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_65_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_EOF_N,
Q => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_out_data_aux(65)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_64_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_SOF_N,
Q => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_out_data_aux(64)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_63_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(63),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(63)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_62_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(62),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(62)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_61_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(61),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(61)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_60_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(60),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(60)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_59_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(59),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(59)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_58_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(58),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(58)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_57_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(57),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(57)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_56_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(56),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(56)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_55_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(55),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(55)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_54_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(54),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(54)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_53_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(53),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(53)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_52_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(52),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(52)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_51_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(51),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(51)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_50_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(50),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(50)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_49_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(49),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(49)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_48_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(48),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(48)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_47_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(47),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(47)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_46_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(46),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(46)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_45_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(45),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(45)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_44_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(44),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(44)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_43_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(43),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(43)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_42_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(42),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(42)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_41_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(41),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(41)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_40_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(40),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(40)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_39_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(39),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(39)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_38_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(38),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(38)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_37_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(37),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(37)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_36_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(36),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(36)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_35_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(35),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(35)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_34_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(34),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(34)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_33_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(33),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(33)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_32_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(32),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(32)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_31_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(31),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(31)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_30_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(30),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(30)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_29_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(29),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(29)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_28_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(28),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(28)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_27_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(27),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(27)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_26_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(26),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(26)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_25_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(25),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(25)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_24_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(24),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(24)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_23_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(23),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(23)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_22_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(22),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(22)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_21_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(21),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(21)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_20_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(20),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(20)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_19_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(19),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(19)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_18_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(18),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(18)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_17_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(17),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(17)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_16_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(16),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(16)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_15_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(15),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(15)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_14_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(14),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(14)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_13_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(13),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(13)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_12_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(12),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(12)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_11_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(11),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(11)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_10_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(10),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(10)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_9_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(9),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(9)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_8_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(8),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(8)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_7_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(7),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(7)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_6_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(6),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(6)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_5_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(5),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(5)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_4_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(4),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(4)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_3_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(3),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(3)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_2_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(2),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(2)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_1_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(1),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(1)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_NOT_FAKE_SH_REG_DATA_WIDTH_0_SH_REG_DATA_U_SRL16E : SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr,
A1 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A2 => NlwRenamedSig_OI_WR_ADDR_0_Q,
A3 => NlwRenamedSig_OI_WR_ADDR_0_Q,
CE => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce,
CLK => CLK,
D => IB_DOWN_DATA(0),
Q => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(0)
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_present_state_FSM_FFd1 : FDR
generic map(
INIT => '0'
)
port map (
C => CLK,
D => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_present_state_FSM_FFd1_In,
R => RESET,
Q => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_present_state_FSM_FFd1_309
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_present_state_FSM_FFd2 : FDS
generic map(
INIT => '0'
)
port map (
C => CLK,
D => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_present_state_FSM_FFd2_In,
S => RESET,
Q => NlwRenamedSig_OI_IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_present_state_FSM_FFd2
);
IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd1 : FDR
generic map(
INIT => '0'
)
port map (
C => CLK,
D => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd1_In_316,
R => RESET,
Q => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd1_315
);
IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd2 : FDR
generic map(
INIT => '0'
)
port map (
C => CLK,
D => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd2_In_318,
R => RESET,
Q => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd2_317
);
IB_ENDPOINT_I_U_down_buf_U_swapper_eof_n_reg : FDSE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_eof_n_reg_and0000_inv,
D => IB_ENDPOINT_I_downrd_sof_n,
S => RESET,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_eof_n_reg_480
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_32 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => NlwRenamedSig_OI_WR_DATA_32_Q,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(32)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_33 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => NlwRenamedSig_OI_WR_DATA_33_Q,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(33)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_34 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => NlwRenamedSig_OI_WR_DATA_34_Q,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(34)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_35 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => NlwRenamedSig_OI_WR_DATA_35_Q,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(35)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_36 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => NlwRenamedSig_OI_WR_DATA_36_Q,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(36)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_37 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => NlwRenamedSig_OI_WR_DATA_37_Q,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(37)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_38 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => NlwRenamedSig_OI_WR_DATA_38_Q,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(38)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_39 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => NlwRenamedSig_OI_WR_DATA_39_Q,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(39)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_40 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => NlwRenamedSig_OI_WR_DATA_40_Q,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(40)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_41 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => NlwRenamedSig_OI_WR_DATA_41_Q,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(41)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_42 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => NlwRenamedSig_OI_WR_DATA_42_Q,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(42)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_43 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => NlwRenamedSig_OI_WR_DATA_43_Q,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(43)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_44 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => NlwRenamedSig_OI_WR_DATA_44_Q,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(44)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_45 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => NlwRenamedSig_OI_WR_DATA_45_Q,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(45)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_46 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => NlwRenamedSig_OI_WR_DATA_46_Q,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(46)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_47 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => NlwRenamedSig_OI_WR_DATA_47_Q,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(47)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_48 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => NlwRenamedSig_OI_WR_DATA_48_Q,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(48)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_49 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => NlwRenamedSig_OI_WR_DATA_49_Q,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(49)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_50 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => NlwRenamedSig_OI_WR_DATA_50_Q,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(50)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_51 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => NlwRenamedSig_OI_WR_DATA_51_Q,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(51)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_52 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => NlwRenamedSig_OI_WR_DATA_52_Q,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(52)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_53 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => NlwRenamedSig_OI_WR_DATA_53_Q,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(53)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_54 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => NlwRenamedSig_OI_WR_DATA_54_Q,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(54)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_55 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => NlwRenamedSig_OI_WR_DATA_55_Q,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(55)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_56 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => NlwRenamedSig_OI_WR_DATA_56_Q,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(56)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_57 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => NlwRenamedSig_OI_WR_DATA_57_Q,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(57)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_58 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => NlwRenamedSig_OI_WR_DATA_58_Q,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(58)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_59 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => NlwRenamedSig_OI_WR_DATA_59_Q,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(59)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_60 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => NlwRenamedSig_OI_WR_DATA_60_Q,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(60)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_61 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => NlwRenamedSig_OI_WR_DATA_61_Q,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(61)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_62 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => NlwRenamedSig_OI_WR_DATA_62_Q,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(62)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_63 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => NlwRenamedSig_OI_WR_DATA_63_Q,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(63)
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_Out21 : LUT2
generic map(
INIT => X"8"
)
port map (
I0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd1_1269,
O => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_addr
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_IN_DST_RDY1 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd1_758,
I1 => RESET,
O => RD_DST_RDY
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_Out21 : LUT2
generic map(
INIT => X"8"
)
port map (
I0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd2_629,
I1 => IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd1,
O => IB_ENDPOINT_I_U_rd_pipe_PIPE_addr
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_present_state_FSM_Out21 : LUT2
generic map(
INIT => X"8"
)
port map (
I0 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_present_state_FSM_FFd2,
I1 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_present_state_FSM_FFd1_309,
O => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_addr
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_34_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_34_1_178,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_34_0_177,
O => NlwRenamedSig_OI_WR_DATA_34_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_33_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_33_1_176,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_33_0_175,
O => NlwRenamedSig_OI_WR_DATA_33_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_32_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_32_1_174,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_32_0_173,
O => NlwRenamedSig_OI_WR_DATA_32_Q
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce1 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => IB_DOWN_SRC_RDY_N,
I1 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_present_state_FSM_FFd2,
O => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_ce
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_63_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_63_1_242,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_63_0_241,
O => NlwRenamedSig_OI_WR_DATA_63_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_62_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_62_1_240,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_62_0_239,
O => NlwRenamedSig_OI_WR_DATA_62_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_61_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_61_1_238,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_61_0_237,
O => NlwRenamedSig_OI_WR_DATA_61_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_60_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_60_1_236,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_60_0_235,
O => NlwRenamedSig_OI_WR_DATA_60_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_59_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_59_1_232,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_59_0_231,
O => NlwRenamedSig_OI_WR_DATA_59_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_58_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_58_1_230,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_58_0_229,
O => NlwRenamedSig_OI_WR_DATA_58_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_57_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_57_1_228,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_57_0_227,
O => NlwRenamedSig_OI_WR_DATA_57_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_56_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_56_1_226,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_56_0_225,
O => NlwRenamedSig_OI_WR_DATA_56_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_55_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_55_1_224,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_55_0_223,
O => NlwRenamedSig_OI_WR_DATA_55_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_54_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_54_1_222,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_54_0_221,
O => NlwRenamedSig_OI_WR_DATA_54_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_53_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_53_1_220,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_53_0_219,
O => NlwRenamedSig_OI_WR_DATA_53_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_52_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_52_1_218,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_52_0_217,
O => NlwRenamedSig_OI_WR_DATA_52_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_51_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_51_1_216,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_51_0_215,
O => NlwRenamedSig_OI_WR_DATA_51_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_50_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_50_1_214,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_50_0_213,
O => NlwRenamedSig_OI_WR_DATA_50_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_49_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_49_1_210,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_49_0_209,
O => NlwRenamedSig_OI_WR_DATA_49_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_48_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_48_1_208,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_48_0_207,
O => NlwRenamedSig_OI_WR_DATA_48_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_47_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_47_1_206,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_47_0_205,
O => NlwRenamedSig_OI_WR_DATA_47_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_46_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_46_1_204,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_46_0_203,
O => NlwRenamedSig_OI_WR_DATA_46_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_45_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_45_1_202,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_45_0_201,
O => NlwRenamedSig_OI_WR_DATA_45_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_44_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_44_1_200,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_44_0_199,
O => NlwRenamedSig_OI_WR_DATA_44_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_43_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_43_1_198,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_43_0_197,
O => NlwRenamedSig_OI_WR_DATA_43_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_42_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_42_1_196,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_42_0_195,
O => NlwRenamedSig_OI_WR_DATA_42_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_41_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_41_1_194,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_41_0_193,
O => NlwRenamedSig_OI_WR_DATA_41_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_40_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_40_1_192,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_40_0_191,
O => NlwRenamedSig_OI_WR_DATA_40_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_39_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_39_1_188,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_39_0_187,
O => NlwRenamedSig_OI_WR_DATA_39_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_38_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_38_1_186,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_38_0_185,
O => NlwRenamedSig_OI_WR_DATA_38_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_37_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_37_1_184,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_37_0_183,
O => NlwRenamedSig_OI_WR_DATA_37_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_36_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_36_1_182,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_36_0_181,
O => NlwRenamedSig_OI_WR_DATA_36_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_35_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_35_1_180,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_35_0_179,
O => NlwRenamedSig_OI_WR_DATA_35_Q
);
IB_ENDPOINT_I_U_rd_pipe_OUT_SOF_N1 : LUT2
generic map(
INIT => X"D"
)
port map (
I0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_rdy_697,
I1 => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(64),
O => IB_ENDPOINT_I_rd_pipe_sof_n
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data_not00011 : LUT3
generic map(
INIT => X"75"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_present_state(0),
I1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_760,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_DATA_DST_RDY1_FRB_763,
O => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data_not0001
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cmp_empty_cmp_eq00001 : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
I1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
I2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
I3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
O => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cmp_empty
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_CNT_ADDR_CE11 : LUT2
generic map(
INIT => X"E"
)
port map (
I0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
O => IB_ENDPOINT_I_U_read_ctrl_N01
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_9_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_9_1_254,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_9_0_253,
O => NlwRenamedSig_OI_WR_DATA_9_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_8_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_8_1_252,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_8_0_251,
O => NlwRenamedSig_OI_WR_DATA_8_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_7_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_7_1_250,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_7_0_249,
O => NlwRenamedSig_OI_WR_DATA_7_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_6_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_6_1_248,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_6_0_247,
O => NlwRenamedSig_OI_WR_DATA_6_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_5_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_5_1_234,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_5_0_233,
O => NlwRenamedSig_OI_WR_DATA_5_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_4_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_4_1_212,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_4_0_211,
O => NlwRenamedSig_OI_WR_DATA_4_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_3_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_3_1_190,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_3_0_189,
O => WR_DATA(3)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_31_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_31_1_172,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_31_0_171,
O => WR_DATA(31)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_30_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_30_1_170,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_30_0_169,
O => WR_DATA(30)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_2_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_2_1_168,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_2_0_167,
O => WR_DATA(2)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_29_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_29_1_166,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_29_0_165,
O => WR_DATA(29)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_28_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_28_1_164,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_28_0_163,
O => WR_DATA(28)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_27_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_27_1_162,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_27_0_161,
O => WR_DATA(27)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_26_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_26_1_160,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_26_0_159,
O => WR_DATA(26)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_25_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_25_1_158,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_25_0_157,
O => WR_DATA(25)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_24_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_24_1_156,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_24_0_155,
O => WR_DATA(24)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_23_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_23_1_154,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_23_0_153,
O => WR_DATA(23)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_22_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_22_1_152,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_22_0_151,
O => WR_DATA(22)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_21_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_21_1_150,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_21_0_149,
O => WR_DATA(21)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_20_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_20_1_148,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_20_0_147,
O => WR_DATA(20)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_1_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_1_1_146,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_1_0_145,
O => WR_DATA(1)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_19_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_19_1_144,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_19_0_143,
O => WR_DATA(19)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_18_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_18_1_142,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_18_0_141,
O => WR_DATA(18)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_17_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_17_1_140,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_17_0_139,
O => WR_DATA(17)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_16_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_16_1_138,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_16_0_137,
O => WR_DATA(16)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_15_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_15_1_136,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_15_0_135,
O => NlwRenamedSig_OI_WR_DATA_15_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_14_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_14_1_134,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_14_0_133,
O => NlwRenamedSig_OI_WR_DATA_14_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_13_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_13_1_132,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_13_0_131,
O => NlwRenamedSig_OI_WR_DATA_13_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_12_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_12_1_130,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_12_0_129,
O => NlwRenamedSig_OI_WR_DATA_12_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_11_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_11_1_128,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_11_0_127,
O => NlwRenamedSig_OI_WR_DATA_11_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_10_mux00001 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_10_1_126,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_10_0_125,
O => NlwRenamedSig_OI_WR_DATA_10_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_Out21 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd2_265,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd1_263,
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_pause_transfer
);
IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd1_In1 : LUT4
generic map(
INIT => X"3A2A"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd1_912,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_cmp_eq0000_916,
I2 => RD_ARDY_ACCEPT,
I3 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd2,
O => IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd1_In
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_next_state_0_mux00001 : LUT4
generic map(
INIT => X"8CDC"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_760,
I1 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_present_state(0),
I2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_DATA_DST_RDY1_FRB_763,
I3 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_next_state_0_cmp_eq0000_744,
O => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_next_state
);
IB_ENDPOINT_I_U_down_buf_U_down_fsm_RD_SOF_N1 : LUT5
generic map(
INIT => X"FFFFBABB"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB0_320,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB5_325,
I2 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB1_321,
I3 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB2_322,
I4 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB3_323,
O => N220
);
IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd2_In1 : LUT5
generic map(
INIT => X"F0F05350"
)
port map (
I0 => WR_RDY,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd1_1475,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd2_1477,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0,
I4 => IB_ENDPOINT_I_wr_src_rdy_n,
O => IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd2_In
);
IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd1_In1 : LUT5
generic map(
INIT => X"CC44EC44"
)
port map (
I0 => WR_RDY,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd1_1475,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd2_1477,
I3 => IB_ENDPOINT_I_wr_eof_n,
I4 => IB_ENDPOINT_I_wr_src_rdy_n,
O => IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd1_In
);
IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_WR_REQ1 : LUT3
generic map(
INIT => X"54"
)
port map (
I0 => IB_ENDPOINT_I_wr_src_rdy_n,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd2_1477,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd1_1475,
O => WR_REQ
);
IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_Out11 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd2,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd1_912,
O => NlwRenamedSig_OI_RD_SOF
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_flag4096_cmp_eq000035 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_14,
I1 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_15,
I2 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_13,
I3 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_12,
I4 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_11,
I5 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_10,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_flag4096_cmp_eq000035_1038
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_flag4096_cmp_eq000071 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_8,
I1 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_9,
I2 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_7,
I3 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_6,
I4 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_5,
I5 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_4,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_flag4096_cmp_eq000071_1039
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_flag4096_cmp_eq000072 : LUT2
generic map(
INIT => X"8"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_flag4096_cmp_eq000035_1038,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_flag4096_cmp_eq000071_1039,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_flag4096
);
IB_ENDPOINT_I_U_down_buf_U_swapper_eof_n_reg_and0000_inv1 : LUT3
generic map(
INIT => X"1F"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_eof_n_reg_480,
I1 => IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd2_629,
I2 => IB_ENDPOINT_I_downrd_sof_n,
O => IB_ENDPOINT_I_U_down_buf_U_swapper_eof_n_reg_and0000_inv
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv1 : LUT4
generic map(
INIT => X"0015"
)
port map (
I0 => RESET,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_vld_478,
I2 => IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd2_629,
I3 => IB_ENDPOINT_I_U_down_buf_fsm_rd_src_rdy_n,
O => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv
);
IB_ENDPOINT_I_U_down_buf_addr_dec_in_sof_n1 : LUT2
generic map(
INIT => X"D"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_present_state_FSM_FFd1_309,
I1 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_out_data_aux(64),
O => IB_ENDPOINT_I_U_down_buf_addr_dec_in_sof_n
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd2_In1 : LUT6
generic map(
INIT => X"1510101055505050"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd1_263,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_addr_last_aux,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd2_265,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_transfer,
I4 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_addr_start_aux,
I5 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_cnt_addrpart_we_0_0_261,
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd2_In
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_OUT_SOF_N1 : LUT2
generic map(
INIT => X"D"
)
port map (
I0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd1_1269,
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_out_data_aux(64),
O => IB_UP_SOF_N
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_OUT_EOF_N1 : LUT2
generic map(
INIT => X"D"
)
port map (
I0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd1_1269,
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_out_data_aux(65),
O => IB_UP_EOF_N
);
IB_ENDPOINT_I_U_down_buf_U_swapper_OUT_EOF_N1 : LUT2
generic map(
INIT => X"B"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_eof_n_reg_480,
I1 => IB_ENDPOINT_I_downrd_sof_n,
O => IB_ENDPOINT_I_downrd_eof_n
);
IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_WR_SOF1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd2_1477,
I1 => IB_ENDPOINT_I_wr_src_rdy_n,
O => WR_SOF
);
IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_WR_EOF1 : LUT3
generic map(
INIT => X"54"
)
port map (
I0 => IB_ENDPOINT_I_wr_eof_n,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd2_1477,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd1_1475,
O => NlwRenamedSig_OI_WR_EOF
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_transfer1 : LUT3
generic map(
INIT => X"10"
)
port map (
I0 => RESET,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd1_114,
I2 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_present_state_FSM_FFd1_309,
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_transfer
);
IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd2_In_SW0 : LUT5
generic map(
INIT => X"ABABABAA"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd2_317,
I1 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd1_315,
I2 => IB_ENDPOINT_I_U_down_buf_addr_dec_out_sof_n,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP,
I4 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ,
O => N7
);
IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd2_In_SW1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd2_317,
I1 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd1_315,
O => N8
);
IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd2_In : LUT6
generic map(
INIT => X"FF880588FA880088"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_fsm_rd_dst_rdy_n,
I1 => N8,
I2 => NlwRenamedSig_OI_WR_DATA_0_Q,
I3 => IB_ENDPOINT_I_U_down_buf_addr_dec_out_eof_n,
I4 => N9,
I5 => N7,
O => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd2_In_318
);
IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd1_In_SW1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd1_315,
I1 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd2_317,
O => N12
);
IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd1_In_SW2 : LUT5
generic map(
INIT => X"ABABABAA"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd1_315,
I1 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd2_317,
I2 => IB_ENDPOINT_I_U_down_buf_addr_dec_out_sof_n,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP,
I4 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ,
O => N13
);
IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd1_In : LUT6
generic map(
INIT => X"FF885088AF880088"
)
port map (
I0 => IB_ENDPOINT_I_wr_dst_rdy_n,
I1 => N12,
I2 => NlwRenamedSig_OI_WR_DATA_0_Q,
I3 => IB_ENDPOINT_I_U_down_buf_addr_dec_out_eof_n,
I4 => N11,
I5 => N13,
O => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd1_In_316
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1R2 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(1),
I1 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_5,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1R
);
IB_ENDPOINT_I_U_down_buf_addr_dec_in_eof_n1 : LUT2
generic map(
INIT => X"D"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_present_state_FSM_FFd1_309,
I1 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_out_data_aux(65),
O => IB_ENDPOINT_I_U_down_buf_addr_dec_in_eof_n
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_65_mux00001 : LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_65_1_246,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_65_0_245,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
O => IB_ENDPOINT_I_U_down_buf_addr_dec_out_sof_n
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_64_mux00001 : LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_64_1_244,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_64_0_243,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
O => IB_ENDPOINT_I_U_down_buf_addr_dec_out_eof_n
);
IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_IB_DST_RDY_N1 : LUT3
generic map(
INIT => X"54"
)
port map (
I0 => WR_RDY,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd1_1475,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd2_1477,
O => IB_ENDPOINT_I_wr_dst_rdy_n
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_In1 : LUT6
generic map(
INIT => X"AAA2AAA2AAA2AAF3"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB0_117,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB1_118,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB2_119,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB3_120,
I4 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB4_121,
I5 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB5_122,
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd1_In1 : LUT6
generic map(
INIT => X"AAAAAAAEAAAA0000"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd1_114,
I1 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_present_state_FSM_FFd1_309,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_pause_transfer,
I4 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2,
I5 => IB_ENDPOINT_I_U_down_buf_addr_dec_out_dst_rdy_n,
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd1_In
);
IB_ENDPOINT_I_U_write_ctrl_BE_GEN_YES_U_be_gen_Madd_last_align_lut_1_1 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_5,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32(1),
O => IB_ENDPOINT_I_U_write_ctrl_BE_GEN_YES_U_be_gen_Madd_last_align_lut(1)
);
IB_ENDPOINT_I_U_read_ctrl_BE_GEN_YES_U_be_gen_Madd_last_align_lut_1_1 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_5,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(1),
O => IB_ENDPOINT_I_U_read_ctrl_BE_GEN_YES_U_be_gen_Madd_last_align_lut(1)
);
IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_RD_EOF1 : LUT4
generic map(
INIT => X"8880"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_cmp_eq0000_916,
I1 => RD_ARDY_ACCEPT,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd1_912,
I3 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd2,
O => NlwRenamedSig_OI_RD_EOF
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1C1 : LUT2
generic map(
INIT => X"E"
)
port map (
I0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(1),
I1 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_5,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1C
);
IB_ENDPOINT_I_U_read_ctrl_BE_GEN_YES_U_be_gen_be_mux_1_Q : LUT6
generic map(
INIT => X"555F555F555F1113"
)
port map (
I0 => NlwRenamedSig_OI_RD_SOF,
I1 => NlwRenamedSig_OI_RD_EOF,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(1),
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(2),
I4 => IB_ENDPOINT_I_U_read_ctrl_BE_GEN_YES_U_be_gen_last_align(2),
I5 => N36,
O => RD_BE(1)
);
IB_ENDPOINT_I_U_read_ctrl_BE_GEN_YES_U_be_gen_be_mux_2_Q : LUT6
generic map(
INIT => X"11FF33FF010F030F"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(1),
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(2),
I2 => NlwRenamedSig_OI_RD_EOF,
I3 => NlwRenamedSig_OI_RD_SOF,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(0),
I5 => N42,
O => RD_BE(2)
);
IB_ENDPOINT_I_U_read_ctrl_BE_GEN_YES_U_be_gen_be_mux_4_Q : LUT6
generic map(
INIT => X"05FFFFFF01333333"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(1),
I1 => NlwRenamedSig_OI_RD_EOF,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(0),
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(2),
I4 => NlwRenamedSig_OI_RD_SOF,
I5 => N46,
O => RD_BE(4)
);
IB_ENDPOINT_I_U_rd_pipe_OUT_EOF_N1 : LUT2
generic map(
INIT => X"D"
)
port map (
I0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_rdy_697,
I1 => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(65),
O => IB_ENDPOINT_I_rd_pipe_eof_n
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_fsm_request_vector_we1 : LUT5
generic map(
INIT => X"C8408800"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd1_263,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd2_265,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_cnt_addrpart_we_0_0_261,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_transfer,
I4 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_addr_last_aux,
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr_next
);
IB_ENDPOINT_I_U_down_buf_U_swapper_IN_DST_RDY_N1 : LUT2
generic map(
INIT => X"8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_vld_478,
I1 => IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd2_629,
O => IB_ENDPOINT_I_U_down_buf_fsm_rd_dst_rdy_n
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_dout_int_0_mux00001 : LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_0_1_124,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_0_0_123,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
O => NlwRenamedSig_OI_WR_DATA_0_Q
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd2_In1 : LUT6
generic map(
INIT => X"AAAAAAAF22222223"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB0_774,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB1_775,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB2_776,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB3_777,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB4_778,
I5 => IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd1_BRB4_627,
O => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd2
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd1_In1 : LUT6
generic map(
INIT => X"A0A0A0A0A0A0A0E0"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd1_771,
I1 => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_rdy_697,
I2 => IB_ENDPOINT_I_U_read_ctrl_N01,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd2,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I5 => IB_ENDPOINT_I_rd_pipe_dst_rdy_n,
O => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd1_In
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_SHREG_CE1 : LUT4
generic map(
INIT => X"00C4"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd1_771,
I1 => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_rdy_697,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd2,
I3 => IB_ENDPOINT_I_rd_pipe_dst_rdy_n,
O => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_ce
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_U_gen_mux_DATA_OUT_10_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_cnt_addrpart_we_0_0_261,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(10),
I2 => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(42),
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(10)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_U_gen_mux_DATA_OUT_5_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_cnt_addrpart_we_0_0_261,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(5),
I2 => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(37),
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(5)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_U_gen_mux_DATA_OUT_4_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_cnt_addrpart_we_0_0_261,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(4),
I2 => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(36),
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(4)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_U_gen_mux_DATA_OUT_15_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_cnt_addrpart_we_0_0_261,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(15),
I2 => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(47),
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(15)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_U_gen_mux_DATA_OUT_13_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_cnt_addrpart_we_0_0_261,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(13),
I2 => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(45),
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(13)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_U_comparator_LT_GT_cmp_gt0000251 : LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(11),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(12),
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(13),
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(14),
I4 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(15),
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_N14
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_DATA_DST_RDY1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_next_state,
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_In,
O => N789
);
IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_cmp_eq0000_SW0 : LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(2),
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(6),
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(1),
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(9),
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(5),
O => N48
);
IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_cmp_eq0000 : LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(4),
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(0),
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(3),
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(8),
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(7),
I5 => N48,
O => IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_cmp_eq0000_916
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_U_gen_mux_DATA_OUT_9_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_cnt_addrpart_we_0_0_261,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(9),
I2 => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(41),
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(9)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_U_gen_mux_DATA_OUT_6_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_cnt_addrpart_we_0_0_261,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(6),
I2 => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(38),
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(6)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_U_gen_mux_DATA_OUT_14_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_cnt_addrpart_we_0_0_261,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(14),
I2 => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(46),
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(14)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_U_gen_mux_DATA_OUT_8_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_cnt_addrpart_we_0_0_261,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(8),
I2 => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(40),
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(8)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_U_gen_mux_DATA_OUT_12_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_cnt_addrpart_we_0_0_261,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(12),
I2 => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(44),
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(12)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_U_gen_mux_DATA_OUT_7_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_cnt_addrpart_we_0_0_261,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(7),
I2 => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(39),
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(7)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_U_gen_mux_DATA_OUT_11_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_cnt_addrpart_we_0_0_261,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(11),
I2 => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(43),
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(11)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_mux000011 : LUT6
generic map(
INIT => X"727272FFFF72FFFF"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB4_275,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB4_287,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB7_278,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB8_279,
I4 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB9_280,
I5 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB10_269,
O => N87
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_eq16224 : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(11),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(7),
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(12),
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(14),
I4 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(13),
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_eq16224_98
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_NEXT_TRANS1 : LUT3
generic map(
INIT => X"08"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_DATA_DST_RDY1_FRB_763,
I1 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_next_state_0_cmp_eq0000_744,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_760,
O => IB_ENDPOINT_I_U_read_ctrl_unpck_hbuf_re
);
IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_IB_DST_RDY_N1 : LUT5
generic map(
INIT => X"FFFF54FC"
)
port map (
I0 => RD_ARDY_ACCEPT,
I1 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd2,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd1_912,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_cmp_eq0000_916,
I4 => IB_ENDPOINT_I_U_read_ctrl_hbuf_full,
O => IB_ENDPOINT_I_rd_pipe_dst_rdy_n
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_next_state_0_cmp_eq0000_SW0 : LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data2,
I1 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data6,
I2 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data1,
I3 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data9,
I4 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data5,
O => N790
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_next_state_0_cmp_eq0000 : LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data(4),
I1 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data(0),
I2 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data(3),
I3 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data(8),
I4 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data(7),
I5 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_next_state_0_cmp_eq0000_SW0_FRB_745,
O => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_next_state_0_cmp_eq0000_744
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_27_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_WR_ADDR_30_Q,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_27_rt_1324
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_26_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_WR_ADDR_29_Q,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_26_rt_1322
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_25_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_WR_ADDR_28_Q,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_25_rt_1320
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_24_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_WR_ADDR_27_Q,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_24_rt_1318
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_23_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_WR_ADDR_26_Q,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_23_rt_1316
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_22_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_WR_ADDR_25_Q,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_22_rt_1314
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_21_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_WR_ADDR_24_Q,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_21_rt_1312
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_20_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_WR_ADDR_23_Q,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_20_rt_1310
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_19_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_WR_ADDR_22_Q,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_19_rt_1306
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_18_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_WR_ADDR_21_Q,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_18_rt_1304
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_17_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_WR_ADDR_20_Q,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_17_rt_1302
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_16_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_WR_ADDR_19_Q,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_16_rt_1300
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_15_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_WR_ADDR_18_Q,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_15_rt_1298
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_14_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_WR_ADDR_17_Q,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_14_rt_1296
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_13_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_WR_ADDR_16_Q,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_13_rt_1294
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_12_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_WR_ADDR_15_Q,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_12_rt_1292
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_11_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_WR_ADDR_14_Q,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_11_rt_1290
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_10_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_WR_ADDR_13_Q,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_10_rt_1288
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_9_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_WR_ADDR_12_Q,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_9_rt_1338
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_8_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_WR_ADDR_11_Q,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_8_rt_1336
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_WR_ADDR_10_Q,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_7_rt_1334
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_WR_ADDR_9_Q,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_6_rt_1332
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_WR_ADDR_8_Q,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_5_rt_1330
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_WR_ADDR_7_Q,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_4_rt_1328
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_WR_ADDR_6_Q,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_3_rt_1326
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_WR_ADDR_5_Q,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_2_rt_1308
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_WR_ADDR_4_Q,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_cy_1_rt_1286
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_8,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_4_rt_928
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_9,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_5_rt_930
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_10,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_6_rt_932
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_11,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_7_rt_934
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_8_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_12,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_8_rt_936
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_9_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_13,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_9_rt_938
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_10_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_14,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_10_rt_922
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_11_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_15,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_cy_11_rt_924
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_RD_ADDR(4),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_1_rt_944
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_RD_ADDR(5),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_2_rt_966
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_RD_ADDR(6),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_3_rt_984
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_RD_ADDR(7),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_4_rt_986
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_RD_ADDR(8),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_5_rt_988
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_RD_ADDR(9),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_6_rt_990
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_RD_ADDR(10),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_7_rt_992
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_8_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_RD_ADDR(11),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_8_rt_994
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_9_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_RD_ADDR(12),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_9_rt_996
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_10_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_RD_ADDR(13),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_10_rt_946
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_11_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_RD_ADDR(14),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_11_rt_948
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_12_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_RD_ADDR(15),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_12_rt_950
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_13_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_RD_ADDR(16),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_13_rt_952
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_14_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_RD_ADDR(17),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_14_rt_954
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_15_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_RD_ADDR(18),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_15_rt_956
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_16_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_RD_ADDR(19),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_16_rt_958
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_17_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_RD_ADDR(20),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_17_rt_960
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_18_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_RD_ADDR(21),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_18_rt_962
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_19_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_RD_ADDR(22),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_19_rt_964
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_20_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_RD_ADDR(23),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_20_rt_968
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_21_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_RD_ADDR(24),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_21_rt_970
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_22_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_RD_ADDR(25),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_22_rt_972
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_23_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_RD_ADDR(26),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_23_rt_974
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_24_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_RD_ADDR(27),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_24_rt_976
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_25_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_RD_ADDR(28),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_25_rt_978
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_26_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_RD_ADDR(29),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_26_rt_980
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_27_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_RD_ADDR(30),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_cy_27_rt_982
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut_9_Q : LUT4
generic map(
INIT => X"4755"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(9),
I1 => IB_ENDPOINT_I_U_read_ctrl_addr_ce,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_count_aux1(12),
I3 => IB_ENDPOINT_I_U_read_ctrl_header_last,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut(9)
);
IB_ENDPOINT_I_U_read_ctrl_U_fetch_marker_HEADER_LAST1 : LUT6
generic map(
INIT => X"0000000000AB0003"
)
port map (
I0 => RD_ARDY_ACCEPT,
I1 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd2,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd1_912,
I3 => IB_ENDPOINT_I_rd_pipe_eof_n,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_cmp_eq0000_916,
I5 => IB_ENDPOINT_I_U_read_ctrl_hbuf_full,
O => IB_ENDPOINT_I_U_read_ctrl_header_last
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_U_comparator_LT_GT_cmp_gt00002_SW0_SW0 : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(7),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(6),
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(9),
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(5),
I4 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(4),
O => N57
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_U_comparator_LT_GT_cmp_gt00002 : LUT6
generic map(
INIT => X"FFFFFFFFCF8ECFCF"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_N111,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(10),
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_const_limit_cnt_sel_0_0_110,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(8),
I4 => N57,
I5 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_N14,
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_U_comparator_LT_GT_cmp_gt0000
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_eq161 : LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(15),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(5),
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(9),
I3 => N59,
I4 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_eq16224_98,
I5 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_eq16271_99,
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_eq
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_eq161 : LUT5
generic map(
INIT => X"01000000"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(15),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(10),
I2 => N61,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_eq16224_98,
I4 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_eq16271_99,
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_eq
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_U_comparator_LT_GT_cmp_gt0000241_SW0 : LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(51),
I1 => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(50),
I2 => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(49),
I3 => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(48),
O => N81
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_U_comparator_LT_GT_cmp_gt0000241 : LUT6
generic map(
INIT => X"DDDDDDDDDDDDDDD8"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_cnt_addrpart_we_0_0_261,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_U_comparator_LT_GT_cmp_gt0000241_SW0_FRB_87,
I2 => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(35),
I3 => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(34),
I4 => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(33),
I5 => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(32),
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_N111
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_mux00001 : LUT6
generic map(
INIT => X"CCA0000000000000"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB2_272,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB5_276,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB3_273,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB1_268,
I4 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB2_284,
I5 => N87,
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_U_comparator_LT_GT_cmp_gt00002_SW2 : LUT6
generic map(
INIT => X"FFD5FF55FF55FF54"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_const_base_cnt_sel_0_0_108,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(4),
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(5),
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(10),
I4 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(9),
I5 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_N111,
O => N65
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_U_comparator_LT_GT_cmp_gt00002 : LUT6
generic map(
INIT => X"FFFFFF01FFFFFE00"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(6),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(7),
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr(8),
I3 => N66,
I4 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_N14,
I5 => N65,
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_U_comparator_LT_GT_cmp_gt0000
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_mux00002 : LUT5
generic map(
INIT => X"D1000000"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB3_286,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB0_282,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB4_287,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB2_284,
I4 => N83,
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_reg_history_rstpot_SW0 : LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_reg_history_BRB4_104,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_reg_history_BRB5_105,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_reg_history_BRB6_106,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_reg_history_BRB7_107,
O => N115
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_reg_history_rstpot : LUT4
generic map(
INIT => X"8CDC"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_reg_history_BRB0_101,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_reg_history_BRB1_102,
I2 => N115,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_reg_history_BRB3_103,
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_reg_history
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_eq16271_SW1 : LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(3),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(1),
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(0),
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(8),
O => N73
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_U_comparator_LT_GT_cmp_gt00002_SW3 : LUT6
generic map(
INIT => X"EFFFEFFFEFFFEF0F"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(9),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(10),
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_const_base_cnt_sel_0_0_108,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_cnt_addrpart_we_0_0_261,
I4 => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(42),
I5 => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(41),
O => N66
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_reg_history_rstpot : LUT4
generic map(
INIT => X"AAE2"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_reg_history_BRB0_90,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_reg_history_BRB1_91,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_reg_history_BRB2_93,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_reg_history_BRB3_94,
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_reg_history
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_eq16274_SW0 : LUT6
generic map(
INIT => X"BEFFBE33BEFFBECC"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(4),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_const_limit_cnt_sel_0_0_110,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(10),
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_cnt_addrpart_we_0_0_261,
I4 => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(36),
I5 => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(42),
O => N59
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_eq16274_SW1_SW0 : LUT4
generic map(
INIT => X"8001"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(9),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(5),
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(4),
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_const_base_cnt_sel_0_0_108,
O => N77
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_eq16274_SW1 : LUT6
generic map(
INIT => X"1D3F3F3F3F3F3F2E"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_const_base_cnt_sel_0_0_108,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_cnt_addrpart_we_0_0_261,
I2 => N77,
I3 => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(37),
I4 => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(41),
I5 => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(36),
O => N61
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_eq16271_SW2 : LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(34),
I1 => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(33),
I2 => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(32),
I3 => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(40),
I4 => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(38),
O => N79
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_eq16271 : LUT6
generic map(
INIT => X"0010001000100F1F"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(6),
I1 => N73,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_cnt_addrpart_we_0_0_261,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_ADDR_SPLITTER_YES_U_addr_splitter_reg_addr(2),
I4 => IB_ENDPOINT_I_U_down_buf_addr_dec_in_data(35),
I5 => N79,
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_eq16271_99
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_U_comparator_LT_GT_cmp_gt0000241_SW0_FRB : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr_we,
D => N81,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_U_comparator_LT_GT_cmp_gt0000241_SW0_FRB_87
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB0 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_not0001_289,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_eq,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB0_282
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB3 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_not0001_289,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_U_comparator_LT_GT_cmp_gt0000,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB3_286
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_not0001_289,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_addr_last_aux,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB2_272
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut_0_Q : LUT6
generic map(
INIT => X"5555555555554755"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(0),
I1 => IB_ENDPOINT_I_rd_pipe_eof_n,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_count_aux1(3),
I3 => N95,
I4 => IB_ENDPOINT_I_U_read_ctrl_addr_ce,
I5 => IB_ENDPOINT_I_U_read_ctrl_hbuf_full,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut(0)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut_1_Q : LUT6
generic map(
INIT => X"5555554755555555"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(1),
I1 => IB_ENDPOINT_I_rd_pipe_eof_n,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_count_aux1(4),
I3 => IB_ENDPOINT_I_U_read_ctrl_addr_ce,
I4 => IB_ENDPOINT_I_U_read_ctrl_hbuf_full,
I5 => N95,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut(1)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut_2_Q : LUT6
generic map(
INIT => X"5555554755555555"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(2),
I1 => IB_ENDPOINT_I_rd_pipe_eof_n,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_count_aux1(5),
I3 => IB_ENDPOINT_I_U_read_ctrl_addr_ce,
I4 => IB_ENDPOINT_I_U_read_ctrl_hbuf_full,
I5 => N95,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut(2)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut_3_Q : LUT6
generic map(
INIT => X"5555555555554575"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(3),
I1 => IB_ENDPOINT_I_rd_pipe_eof_n,
I2 => N95,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_count_aux1(6),
I4 => IB_ENDPOINT_I_U_read_ctrl_addr_ce,
I5 => IB_ENDPOINT_I_U_read_ctrl_hbuf_full,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut(3)
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_next_state_0_cmp_eq0000_SW1 : LUT5
generic map(
INIT => X"FFFFFEFF"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data(7),
I1 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data(4),
I2 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data(3),
I3 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data(0),
I4 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_760,
O => N101
);
IB_ENDPOINT_I_U_read_ctrl_hbuf_full1 : LUT6
generic map(
INIT => X"EEEEEEEEEEEAEEEE"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd1_771,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpck_hbuf_reg_full_1196,
I2 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data(8),
I3 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_next_state_0_cmp_eq0000_SW0_FRB_745,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_DATA_DST_RDY1_FRB_763,
I5 => N101,
O => IB_ENDPOINT_I_U_read_ctrl_hbuf_full
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut_4_Q : LUT6
generic map(
INIT => X"5555555555455575"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(4),
I1 => IB_ENDPOINT_I_rd_pipe_eof_n,
I2 => N103,
I3 => IB_ENDPOINT_I_U_read_ctrl_addr_ce,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_count_aux1(7),
I5 => IB_ENDPOINT_I_U_read_ctrl_hbuf_full,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut(4)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut_5_Q : LUT6
generic map(
INIT => X"5555554555555575"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(5),
I1 => IB_ENDPOINT_I_rd_pipe_eof_n,
I2 => N103,
I3 => IB_ENDPOINT_I_U_read_ctrl_addr_ce,
I4 => IB_ENDPOINT_I_U_read_ctrl_hbuf_full,
I5 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_count_aux1(8),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut(5)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut_6_Q : LUT6
generic map(
INIT => X"5555554555555575"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(6),
I1 => IB_ENDPOINT_I_rd_pipe_eof_n,
I2 => N103,
I3 => IB_ENDPOINT_I_U_read_ctrl_addr_ce,
I4 => IB_ENDPOINT_I_U_read_ctrl_hbuf_full,
I5 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_count_aux1(9),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut(6)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut_7_Q : LUT6
generic map(
INIT => X"5555554555555575"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(7),
I1 => IB_ENDPOINT_I_rd_pipe_eof_n,
I2 => N103,
I3 => IB_ENDPOINT_I_U_read_ctrl_addr_ce,
I4 => IB_ENDPOINT_I_U_read_ctrl_hbuf_full,
I5 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_count_aux1(10),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut(7)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut_8_Q : LUT6
generic map(
INIT => X"5555554555555575"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(8),
I1 => IB_ENDPOINT_I_rd_pipe_eof_n,
I2 => N103,
I3 => IB_ENDPOINT_I_U_read_ctrl_addr_ce,
I4 => IB_ENDPOINT_I_U_read_ctrl_hbuf_full,
I5 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_count_aux1(11),
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Mcount_reg_count_lut(8)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_reg_history_BRB0 : FDS
port map (
C => CLK,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_eq,
S => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_reg_history_or0000,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_reg_history_BRB0_101
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_reg_history_BRB1 : FDR
port map (
C => CLK,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_reg_history,
R => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_reg_history_or0000,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_reg_history_BRB1_102
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_reg_history_BRB3 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_U_comparator_LT_GT_cmp_gt0000,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_reg_history_BRB3_103
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_reg_history_BRB0 : FDS
port map (
C => CLK,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_reg_history,
S => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_reg_history_or0000,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_reg_history_BRB0_90
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_reg_history_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_U_comparator_LT_GT_cmp_gt0000,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_reg_history_BRB2_93
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_reg_history_BRB3 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_eq,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_reg_history_BRB3_94
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB4 : FDRE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_not0001_289,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_eq,
R => RESET,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB4_275
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB7 : FDRE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_not0001_289,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_U_comparator_LT_GT_cmp_gt0000,
R => RESET,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB7_278
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB8 : FDRE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_not0001_289,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_eq,
R => RESET,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB8_279
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB9 : FDSE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_not0001_289,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_U_comparator_LT_GT_cmp_gt0000,
S => RESET,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB9_280
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB11 : FDRE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_not0001_289,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_U_comparator_LT_GT_cmp_gt0000,
R => RESET,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB11_283
);
IB_ENDPOINT_I_U_down_buf_U_down_fsm_IB_DST_RDY_N : LUT6
generic map(
INIT => X"2727227727273333"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_addr_dec_out_sof_n,
I1 => N138,
I2 => N139,
I3 => N140,
I4 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP,
I5 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ,
O => IB_ENDPOINT_I_U_down_buf_addr_dec_out_dst_rdy_n
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_ce1 : LUT3
generic map(
INIT => X"15"
)
port map (
I0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd2_629,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_eof_n_reg_480,
I2 => IB_ENDPOINT_I_downrd_sof_n,
O => IB_ENDPOINT_I_U_rd_pipe_PIPE_ce
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd2_In1 : LUT6
generic map(
INIT => X"C400CC0000000000"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_eof_n_reg_480,
I1 => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_rdy_697,
I2 => IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd2_629,
I3 => IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd1,
I4 => IB_ENDPOINT_I_downrd_sof_n,
I5 => IB_ENDPOINT_I_rd_pipe_dst_rdy_n,
O => IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd2_In
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_3_not00011 : LUT5
generic map(
INIT => X"00FFE0FF"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB3_1281,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB2_1280,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB4_1282,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_10_BRB1_1342,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB3_1403,
O => N395
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd1_In1 : LUT6
generic map(
INIT => X"FF15BF15BF15BF15"
)
port map (
I0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd1_BRB0_623,
I1 => IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd1_BRB1_624,
I2 => IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd1_BRB2_625,
I3 => IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd1_BRB3_626,
I4 => IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd1_BRB4_627,
I5 => IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd1_BRB5_628,
O => IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd1
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_17_mux00001 : LUT6
generic map(
INIT => X"AAAAAAAACCCAAAAA"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_17_BRB6_1366,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_17_BRB5_1365,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB2_1280,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB3_1281,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB4_1282,
I5 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB3_1403,
O => N506
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_16_mux00001 : LUT6
generic map(
INIT => X"AAAAAAAACCCAAAAA"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_16_BRB6_1363,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_16_BRB5_1362,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB2_1280,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB3_1281,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB4_1282,
I5 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB3_1403,
O => N610
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_15_mux00001 : LUT6
generic map(
INIT => X"AAAAAAAACCCAAAAA"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_15_BRB6_1360,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_15_BRB5_1359,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB2_1280,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB3_1281,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB4_1282,
I5 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB3_1403,
O => N618
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_14_mux00001 : LUT6
generic map(
INIT => X"AAAAAAAACCCAAAAA"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_14_BRB6_1357,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_14_BRB5_1356,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB2_1280,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB3_1281,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB4_1282,
I5 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB3_1403,
O => N626
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_13_mux00001 : LUT6
generic map(
INIT => X"AAAAAAAACCCAAAAA"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_13_BRB6_1354,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_13_BRB5_1353,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB2_1280,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB3_1281,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB4_1282,
I5 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB3_1403,
O => N634
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_12_mux00001 : LUT6
generic map(
INIT => X"AAAAAAAACCCAAAAA"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_12_BRB6_1351,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_12_BRB5_1350,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB2_1280,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB3_1281,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB4_1282,
I5 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB3_1403,
O => N642
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_11_mux00001 : LUT6
generic map(
INIT => X"AAAAAAAACCCAAAAA"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_11_BRB6_1348,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_11_BRB5_1347,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB2_1280,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB3_1281,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB4_1282,
I5 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB3_1403,
O => N645
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_mux00002_SW0 : LUT2
generic map(
INIT => X"D"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd2_317,
I1 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd1_315,
O => N142
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_mux00002_SW1 : LUT6
generic map(
INIT => X"FFFFFFFF020F0E0F"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB3_286,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB0_282,
I2 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd2_317,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB2_284,
I4 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB4_287,
I5 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd1_315,
O => N143
);
IB_ENDPOINT_I_U_down_buf_U_down_fsm_RD_EOF_N1 : LUT6
generic map(
INIT => X"FFABFFA8FFAAFFAA"
)
port map (
I0 => N142,
I1 => NlwRenamedSig_OI_WR_DATA_0_Q,
I2 => IB_ENDPOINT_I_U_down_buf_addr_dec_out_sof_n,
I3 => IB_ENDPOINT_I_U_down_buf_addr_dec_out_eof_n,
I4 => N143,
I5 => N83,
O => IB_ENDPOINT_I_downrd_sof_n
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_17_rstpot : LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_17_BRB2_1364,
I1 => N506,
I2 => N395,
O => NlwRenamedSig_OI_WR_ADDR_17_Q
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_16_rstpot : LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_16_BRB2_1361,
I1 => N610,
I2 => N395,
O => NlwRenamedSig_OI_WR_ADDR_16_Q
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_15_rstpot : LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_15_BRB2_1358,
I1 => N618,
I2 => N395,
O => NlwRenamedSig_OI_WR_ADDR_15_Q
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_14_rstpot : LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_14_BRB2_1355,
I1 => N626,
I2 => N395,
O => NlwRenamedSig_OI_WR_ADDR_14_Q
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_13_rstpot : LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_13_BRB2_1352,
I1 => N634,
I2 => N395,
O => NlwRenamedSig_OI_WR_ADDR_13_Q
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_12_rstpot : LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_12_BRB2_1349,
I1 => N642,
I2 => N395,
O => NlwRenamedSig_OI_WR_ADDR_12_Q
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_11_rstpot : LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_11_BRB2_1346,
I1 => N645,
I2 => N395,
O => NlwRenamedSig_OI_WR_ADDR_11_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0 : FDC
port map (
C => CLK,
CLR => RESET,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_rstpot_113,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_lut_3_Q : LUT3
generic map(
INIT => X"36"
)
port map (
I0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(2),
I1 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_7,
I2 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_6,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_lut_3_Q_941
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_lut_2_Q : LUT4
generic map(
INIT => X"5A69"
)
port map (
I0 => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(2),
I1 => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(1),
I2 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_6,
I3 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_5,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_count_aux1_Madd_lut_2_Q_940
);
IB_ENDPOINT_I_U_down_buf_U_down_fsm_WR_SOF_N1_SW0 : LUT6
generic map(
INIT => X"A080AF8C0080008C"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB4_287,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_0_0_123,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB0_282,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I4 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB3_286,
I5 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_0_1_124,
O => N148
);
IB_ENDPOINT_I_U_down_buf_U_down_fsm_WR_SOF_N1 : LUT6
generic map(
INIT => X"FFFFFFFFABBBBBBB"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_addr_dec_out_sof_n,
I1 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd1_315,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB2_284,
I3 => N83,
I4 => N148,
I5 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd2_317,
O => IB_ENDPOINT_I_wr_sof_n
);
IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_cmp_eq0000_SW1 : LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => RD_ARDY_ACCEPT,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(3),
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(0),
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(4),
O => N150
);
IB_ENDPOINT_I_U_read_ctrl_U_fetch_marker_HEADER_LAST1_SW1 : LUT6
generic map(
INIT => X"000F000F000F111F"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(8),
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(7),
I2 => IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd1_912,
I3 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd2,
I4 => N150,
I5 => N48,
O => N95
);
IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_cmp_eq0000_SW4 : LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(3),
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(4),
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(0),
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(7),
O => N156
);
IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_COUNT_CE1 : LUT6
generic map(
INIT => X"AAA0AAA0AAA08880"
)
port map (
I0 => RD_ARDY_ACCEPT,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(8),
I2 => IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd1_912,
I3 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd2,
I4 => N156,
I5 => N48,
O => IB_ENDPOINT_I_U_read_ctrl_addr_ce
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_vld : FDR
port map (
C => CLK,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_vld_rstpot_479,
R => RESET,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_vld_478
);
IB_ENDPOINT_I_U_down_buf_U_down_fsm_IB_DST_RDY_N_SW4 : LUT6
generic map(
INIT => X"CCCC888CFFFF888C"
)
port map (
I0 => WR_RDY,
I1 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd1_315,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd1_1475,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd2_1477,
I4 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd2_317,
I5 => IB_ENDPOINT_I_U_down_buf_fsm_rd_dst_rdy_n,
O => N138
);
IB_ENDPOINT_I_U_down_buf_U_down_fsm_IB_DST_RDY_N_SW5 : LUT5
generic map(
INIT => X"AAFF7F7F"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd2_317,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_vld_478,
I2 => IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd2_629,
I3 => IB_ENDPOINT_I_wr_dst_rdy_n,
I4 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd1_315,
O => N139
);
IB_ENDPOINT_I_U_down_buf_U_down_fsm_IB_DST_RDY_N_SW6 : LUT6
generic map(
INIT => X"F700F7FFF707F7F7"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_vld_478,
I1 => IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd2_629,
I2 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd1_315,
I3 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd2_317,
I4 => IB_ENDPOINT_I_wr_dst_rdy_n,
I5 => NlwRenamedSig_OI_WR_DATA_0_Q,
O => N140
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_rstpot : LUT6
generic map(
INIT => X"F0F0F0B4F0F00A4A"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd1_114,
I1 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_present_state_FSM_FFd1_309,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_pause_transfer,
I4 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2,
I5 => IB_ENDPOINT_I_U_down_buf_addr_dec_out_dst_rdy_n,
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_rstpot_113
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count_and00001 : LUT6
generic map(
INIT => X"0000000000AB0003"
)
port map (
I0 => RD_ARDY_ACCEPT,
I1 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd2,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd1_912,
I3 => IB_ENDPOINT_I_rd_pipe_eof_n,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_cmp_eq0000_916,
I5 => IB_ENDPOINT_I_U_read_ctrl_hbuf_full,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count_and0000
);
IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_cmp_eq0000_SW6 : LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => RD_ARDY_ACCEPT,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(3),
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(0),
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(8),
O => N163
);
IB_ENDPOINT_I_U_read_ctrl_U_fetch_marker_HEADER_LAST1_SW4 : LUT6
generic map(
INIT => X"000F000F000F111F"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(7),
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count(4),
I2 => IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd1_912,
I3 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd2,
I4 => N163,
I5 => N48,
O => N103
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_mux00001_SW0 : LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => WR_RDY,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd2_1477,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd1_1475,
O => N173
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_rstpot : LUT6
generic map(
INIT => X"EEE4EEEE44E44444"
)
port map (
I0 => N395,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_BRB1_1438,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_BRB2_1439,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB3_1403,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB4_1404,
I5 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_BRB5_1440,
O => NlwRenamedSig_OI_WR_ADDR_31_Q
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_30_rstpot : LUT6
generic map(
INIT => X"AAAACCAAF0F0F0F0"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_30_BRB5_1408,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_30_BRB2_1407,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_30_BRB1_1406,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB4_1404,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB3_1403,
I5 => N395,
O => NlwRenamedSig_OI_WR_ADDR_30_Q
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_rstpot : LUT6
generic map(
INIT => X"AAAACCAAF0F0F0F0"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB5_1405,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB2_1402,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB1_1401,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB4_1404,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB3_1403,
I5 => N395,
O => NlwRenamedSig_OI_WR_ADDR_29_Q
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_28_rstpot : LUT6
generic map(
INIT => X"AAAACCAAF0F0F0F0"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_28_BRB5_1400,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_28_BRB2_1399,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_28_BRB1_1398,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB4_1404,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB3_1403,
I5 => N395,
O => NlwRenamedSig_OI_WR_ADDR_28_Q
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_27_rstpot : LUT6
generic map(
INIT => X"AAAACCAAF0F0F0F0"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_27_BRB5_1397,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_27_BRB2_1396,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_27_BRB1_1395,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB4_1404,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB3_1403,
I5 => N395,
O => NlwRenamedSig_OI_WR_ADDR_27_Q
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_26_rstpot : LUT6
generic map(
INIT => X"AAAACCAAF0F0F0F0"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_26_BRB5_1394,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_26_BRB2_1393,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_26_BRB1_1392,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB4_1404,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB3_1403,
I5 => N395,
O => NlwRenamedSig_OI_WR_ADDR_26_Q
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_25_rstpot : LUT6
generic map(
INIT => X"AAAACCAAF0F0F0F0"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_25_BRB5_1391,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_25_BRB2_1390,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_25_BRB1_1389,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB4_1404,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB3_1403,
I5 => N395,
O => NlwRenamedSig_OI_WR_ADDR_25_Q
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_24_rstpot : LUT6
generic map(
INIT => X"AAAACCAAF0F0F0F0"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_24_BRB5_1388,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_24_BRB2_1387,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_24_BRB1_1386,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB4_1404,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB3_1403,
I5 => N395,
O => NlwRenamedSig_OI_WR_ADDR_24_Q
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_23_rstpot : LUT6
generic map(
INIT => X"AAAACCAAF0F0F0F0"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_23_BRB5_1385,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_23_BRB2_1384,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_23_BRB1_1383,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB4_1404,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB3_1403,
I5 => N395,
O => NlwRenamedSig_OI_WR_ADDR_23_Q
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_vld_rstpot : LUT5
generic map(
INIT => X"A8FFA0FF"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_vld_478,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_eof_n_reg_480,
I2 => IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd2_629,
I3 => IB_ENDPOINT_I_U_down_buf_fsm_rd_src_rdy_n,
I4 => IB_ENDPOINT_I_downrd_sof_n,
O => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_vld_rstpot_479
);
IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_rstpot : LUT6
generic map(
INIT => X"DDDDCCCD9999CCC9"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB0_1278,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB1_1279,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB2_1280,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB3_1281,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB4_1282,
I5 => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB5_1283,
O => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0
);
IB_ENDPOINT_I_U_down_buf_U_swapper_in_mx_1_1 : LUT6
generic map(
INIT => X"F0F0F0F0F0F04050"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB5_325,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB1_321,
I2 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_1_BRB2_367,
I3 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB2_322,
I4 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB0_320,
I5 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB3_323,
O => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(1)
);
IB_ENDPOINT_I_U_read_ctrl_U_fetch_marker_DONE_FLAG_WE1 : LUT6
generic map(
INIT => X"0000000000AB0003"
)
port map (
I0 => RD_ARDY_ACCEPT,
I1 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd2,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd1_912,
I3 => IB_ENDPOINT_I_rd_pipe_sof_n,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_cmp_eq0000_916,
I5 => IB_ENDPOINT_I_U_read_ctrl_hbuf_full,
O => IB_ENDPOINT_I_U_read_ctrl_done_flag_we
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_reg_history_or00001 : LUT6
generic map(
INIT => X"FAEABAAAEAEAAAAA"
)
port map (
I0 => RESET,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd1_263,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd2_265,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_cnt_addrpart_we_0_0_261,
I4 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_transfer,
I5 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_addr_last_aux,
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_reg_history_or0000
);
IB_ENDPOINT_I_U_down_buf_U_swapper_in_mx_3_1 : LUT6
generic map(
INIT => X"FFFF0055FFFF0010"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB0_320,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB1_321,
I2 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB2_322,
I3 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB3_323,
I4 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_3_BRB4_427,
I5 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB5_325,
O => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(3)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_in_mx_2_1 : LUT6
generic map(
INIT => X"FFFF0055FFFF0010"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB0_320,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB1_321,
I2 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB2_322,
I3 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB3_323,
I4 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_2_BRB4_409,
I5 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB5_325,
O => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(2)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_in_mx_0_1 : LUT6
generic map(
INIT => X"FFFF0055FFFF0010"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB0_320,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB1_321,
I2 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB2_322,
I3 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB3_323,
I4 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB4_324,
I5 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB5_325,
O => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(0)
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we1 : LUT6
generic map(
INIT => X"33333333BBBF333F"
)
port map (
I0 => RD_ARDY_ACCEPT,
I1 => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_rdy_697,
I2 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd2,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd1_912,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_cmp_eq0000_916,
I5 => IB_ENDPOINT_I_U_read_ctrl_hbuf_full,
O => IB_ENDPOINT_I_U_rd_pipe_PIPE_outreg_we
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_reg_history_BRB1 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_reg_history_BRB1_rstpot_92,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_reg_history_BRB1_91
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_22_rstpot : LUT6
generic map(
INIT => X"AAAACCAAF0F0F0F0"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_22_BRB5_1382,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_22_BRB2_1381,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_22_BRB1_1380,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB4_1404,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB3_1403,
I5 => N395,
O => NlwRenamedSig_OI_WR_ADDR_22_Q
);
IB_ENDPOINT_I_U_down_buf_U_swapper_in_mx_9_1 : LUT5
generic map(
INIT => X"FBEA5140"
)
port map (
I0 => N220,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB1_439,
I2 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_9_BRB2_474,
I3 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_9_BRB3_475,
I4 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_9_BRB4_476,
O => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(9)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_in_mx_8_1 : LUT5
generic map(
INIT => X"FBEA5140"
)
port map (
I0 => N220,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB1_439,
I2 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_8_BRB2_470,
I3 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_8_BRB3_471,
I4 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_8_BRB4_472,
O => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(8)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_in_mx_7_1 : LUT5
generic map(
INIT => X"FBEA5140"
)
port map (
I0 => N220,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB1_439,
I2 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_7_BRB2_466,
I3 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_7_BRB3_467,
I4 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_7_BRB4_468,
O => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(7)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_in_mx_6_1 : LUT5
generic map(
INIT => X"FBEA5140"
)
port map (
I0 => N220,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB1_439,
I2 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_6_BRB2_462,
I3 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_6_BRB3_463,
I4 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_6_BRB4_464,
O => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(6)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_in_mx_5_1 : LUT5
generic map(
INIT => X"FBEA5140"
)
port map (
I0 => N220,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB1_439,
I2 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_5_BRB2_454,
I3 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_5_BRB3_455,
I4 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_5_BRB4_456,
O => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(5)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_in_mx_4_1 : LUT5
generic map(
INIT => X"FBEA5140"
)
port map (
I0 => N220,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB1_439,
I2 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB2_440,
I3 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB3_441,
I4 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB4_442,
O => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(4)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_in_mx_31_1 : LUT5
generic map(
INIT => X"FBEA5140"
)
port map (
I0 => N220,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB1_439,
I2 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_31_BRB2_416,
I3 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_31_BRB3_417,
I4 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_31_BRB4_418,
O => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(31)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_in_mx_30_1 : LUT5
generic map(
INIT => X"FBEA5140"
)
port map (
I0 => N220,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB1_439,
I2 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_30_BRB2_412,
I3 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_30_BRB3_413,
I4 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_30_BRB4_414,
O => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(30)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_in_mx_29_1 : LUT5
generic map(
INIT => X"FBEA5140"
)
port map (
I0 => N220,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB1_439,
I2 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_29_BRB2_406,
I3 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_29_BRB3_407,
I4 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_29_BRB4_408,
O => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(29)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_in_mx_28_1 : LUT5
generic map(
INIT => X"FBEA5140"
)
port map (
I0 => N220,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB1_439,
I2 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_28_BRB2_402,
I3 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_28_BRB3_403,
I4 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_28_BRB4_404,
O => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(28)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_in_mx_27_1 : LUT5
generic map(
INIT => X"FBEA5140"
)
port map (
I0 => N220,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB1_439,
I2 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_27_BRB2_398,
I3 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_27_BRB3_399,
I4 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_27_BRB4_400,
O => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(27)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_in_mx_26_1 : LUT5
generic map(
INIT => X"FBEA5140"
)
port map (
I0 => N220,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB1_439,
I2 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_26_BRB2_394,
I3 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_26_BRB3_395,
I4 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_26_BRB4_396,
O => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(26)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_in_mx_25_1 : LUT5
generic map(
INIT => X"FBEA5140"
)
port map (
I0 => N220,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB1_439,
I2 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_25_BRB2_390,
I3 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_25_BRB3_391,
I4 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_25_BRB4_392,
O => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(25)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_in_mx_24_1 : LUT5
generic map(
INIT => X"FBEA5140"
)
port map (
I0 => N220,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB1_439,
I2 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_24_BRB2_386,
I3 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_24_BRB3_387,
I4 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_24_BRB4_388,
O => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(24)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_in_mx_23_1 : LUT5
generic map(
INIT => X"FBEA5140"
)
port map (
I0 => N220,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB1_439,
I2 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_23_BRB2_382,
I3 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_23_BRB3_383,
I4 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_23_BRB4_384,
O => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(23)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_in_mx_22_1 : LUT5
generic map(
INIT => X"FBEA5140"
)
port map (
I0 => N220,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB1_439,
I2 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_22_BRB2_378,
I3 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_22_BRB3_379,
I4 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_22_BRB4_380,
O => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(22)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_in_mx_21_1 : LUT5
generic map(
INIT => X"FBEA5140"
)
port map (
I0 => N220,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB1_439,
I2 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_21_BRB2_374,
I3 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_21_BRB3_375,
I4 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_21_BRB4_376,
O => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(21)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_in_mx_20_1 : LUT5
generic map(
INIT => X"FBEA5140"
)
port map (
I0 => N220,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB1_439,
I2 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_20_BRB2_370,
I3 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_20_BRB3_371,
I4 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_20_BRB4_372,
O => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(20)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_in_mx_19_1 : LUT5
generic map(
INIT => X"FBEA5140"
)
port map (
I0 => N220,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB1_439,
I2 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_19_BRB2_364,
I3 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_19_BRB3_365,
I4 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_19_BRB4_366,
O => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(19)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_in_mx_18_1 : LUT5
generic map(
INIT => X"FBEA5140"
)
port map (
I0 => N220,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB1_439,
I2 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_18_BRB2_360,
I3 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_18_BRB3_361,
I4 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_18_BRB4_362,
O => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(18)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_in_mx_17_1 : LUT5
generic map(
INIT => X"FBEA5140"
)
port map (
I0 => N220,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB1_439,
I2 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_17_BRB2_356,
I3 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_17_BRB3_357,
I4 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_17_BRB4_358,
O => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(17)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_in_mx_16_1 : LUT5
generic map(
INIT => X"FBEA5140"
)
port map (
I0 => N220,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB1_439,
I2 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_16_BRB2_352,
I3 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_16_BRB3_353,
I4 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_16_BRB4_354,
O => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(16)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_in_mx_15_1 : LUT5
generic map(
INIT => X"FBEA5140"
)
port map (
I0 => N220,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB1_439,
I2 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_15_BRB2_348,
I3 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_15_BRB3_349,
I4 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_15_BRB4_350,
O => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(15)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_in_mx_14_1 : LUT5
generic map(
INIT => X"FBEA5140"
)
port map (
I0 => N220,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB1_439,
I2 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_14_BRB2_344,
I3 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_14_BRB3_345,
I4 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_14_BRB4_346,
O => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(14)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_in_mx_13_1 : LUT5
generic map(
INIT => X"FBEA5140"
)
port map (
I0 => N220,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB1_439,
I2 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_13_BRB2_340,
I3 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_13_BRB3_341,
I4 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_13_BRB4_342,
O => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(13)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_in_mx_12_1 : LUT5
generic map(
INIT => X"FBEA5140"
)
port map (
I0 => N220,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB1_439,
I2 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_12_BRB2_336,
I3 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_12_BRB3_337,
I4 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_12_BRB4_338,
O => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(12)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_in_mx_11_1 : LUT5
generic map(
INIT => X"FBEA5140"
)
port map (
I0 => N220,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB1_439,
I2 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_11_BRB2_332,
I3 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_11_BRB3_333,
I4 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_11_BRB4_334,
O => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(11)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_in_mx_10_1 : LUT5
generic map(
INIT => X"FBEA5140"
)
port map (
I0 => N220,
I1 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB1_439,
I2 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_10_BRB2_328,
I3 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_10_BRB3_329,
I4 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_10_BRB4_330,
O => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(10)
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_21_rstpot : LUT6
generic map(
INIT => X"AAAACCAAF0F0F0F0"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_21_BRB5_1379,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_21_BRB2_1378,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_21_BRB1_1377,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB4_1404,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB3_1403,
I5 => N395,
O => NlwRenamedSig_OI_WR_ADDR_21_Q
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_20_rstpot : LUT6
generic map(
INIT => X"AAAACCAAF0F0F0F0"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_20_BRB5_1376,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_20_BRB2_1375,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_20_BRB1_1374,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB4_1404,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB3_1403,
I5 => N395,
O => NlwRenamedSig_OI_WR_ADDR_20_Q
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_19_rstpot : LUT6
generic map(
INIT => X"AAAACCAAF0F0F0F0"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_19_BRB5_1372,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_19_BRB2_1371,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_19_BRB1_1370,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB4_1404,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB3_1403,
I5 => N395,
O => NlwRenamedSig_OI_WR_ADDR_19_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB2_rstpot_285,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB2_284
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB4_rstpot_288,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB4_287
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB1 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB1_rstpot_271,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB1_268
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB3 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB3_rstpot_274,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB3_273
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB5 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB5_rstpot_277,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB5_276
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB10 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB10_rstpot_270,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB10_269
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_18_rstpot : LUT6
generic map(
INIT => X"AAAACCAAF0F0F0F0"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_18_BRB5_1369,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_18_BRB2_1368,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_18_BRB1_1367,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB4_1404,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB3_1403,
I5 => N395,
O => NlwRenamedSig_OI_WR_ADDR_18_Q
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_3_rstpot : LUT5
generic map(
INIT => X"FDA87520"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB0_1135,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB1_1136,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_3_BRB2_1141,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_3_BRB3_1142,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_3_BRB4_1143,
O => NlwRenamedSig_OI_RD_ADDR(3)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_5_rstpot : LUT5
generic map(
INIT => X"AAF0CCCC"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_5_BRB4_1150,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_5_BRB3_1149,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_5_BRB2_1148,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB1_1136,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB0_1135,
O => NlwRenamedSig_OI_RD_ADDR(5)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_4_rstpot : LUT5
generic map(
INIT => X"AAF0CCCC"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_4_BRB4_1147,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_4_BRB3_1146,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_4_BRB2_1145,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB1_1136,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB0_1135,
O => NlwRenamedSig_OI_RD_ADDR(4)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_6_rstpot : LUT5
generic map(
INIT => X"AAF0CCCC"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_6_BRB4_1153,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_6_BRB3_1152,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_6_BRB2_1151,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB1_1136,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB0_1135,
O => NlwRenamedSig_OI_RD_ADDR(6)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_7_rstpot : LUT5
generic map(
INIT => X"AAF0CCCC"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_7_BRB4_1156,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_7_BRB3_1155,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_7_BRB2_1154,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB1_1136,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB0_1135,
O => NlwRenamedSig_OI_RD_ADDR(7)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_8_rstpot : LUT5
generic map(
INIT => X"AAF0CCCC"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_8_BRB4_1159,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_8_BRB3_1158,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_8_BRB2_1157,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB1_1136,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB0_1135,
O => NlwRenamedSig_OI_RD_ADDR(8)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_9_rstpot : LUT5
generic map(
INIT => X"AAF0CCCC"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_9_BRB4_1162,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_9_BRB3_1161,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_9_BRB2_1160,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB1_1136,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB0_1135,
O => NlwRenamedSig_OI_RD_ADDR(9)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_10_rstpot : LUT5
generic map(
INIT => X"AAF0CCCC"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_10_BRB4_1044,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_10_BRB3_1043,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_10_BRB2_1042,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB1_1136,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB0_1135,
O => NlwRenamedSig_OI_RD_ADDR(10)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_12_rstpot : LUT5
generic map(
INIT => X"AAF0CCCC"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_12_BRB4_1050,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_12_BRB3_1049,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_12_BRB2_1048,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB1_1136,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB0_1135,
O => NlwRenamedSig_OI_RD_ADDR(12)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_11_rstpot : LUT5
generic map(
INIT => X"AAF0CCCC"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_11_BRB4_1047,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_11_BRB3_1046,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_11_BRB2_1045,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB1_1136,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB0_1135,
O => NlwRenamedSig_OI_RD_ADDR(11)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_13_rstpot : LUT5
generic map(
INIT => X"AAF0CCCC"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_13_BRB4_1053,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_13_BRB3_1052,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_13_BRB2_1051,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB1_1136,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB0_1135,
O => NlwRenamedSig_OI_RD_ADDR(13)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_14_rstpot : LUT5
generic map(
INIT => X"FDA87520"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB0_1135,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB1_1136,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_14_BRB2_1054,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_14_BRB3_1055,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_14_BRB4_1056,
O => NlwRenamedSig_OI_RD_ADDR(14)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_20_rstpot : LUT5
generic map(
INIT => X"FDA87520"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB0_1135,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB1_1136,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_20_BRB2_1073,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_20_BRB3_1074,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_20_BRB4_1075,
O => NlwRenamedSig_OI_RD_ADDR(20)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_15_rstpot : LUT5
generic map(
INIT => X"FDA87520"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB0_1135,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB1_1136,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_15_BRB2_1057,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_15_BRB3_1058,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_15_BRB4_1059,
O => NlwRenamedSig_OI_RD_ADDR(15)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_16_rstpot : LUT5
generic map(
INIT => X"FDA87520"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB0_1135,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB1_1136,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_16_BRB2_1060,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_16_BRB3_1061,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_16_BRB4_1062,
O => NlwRenamedSig_OI_RD_ADDR(16)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_21_rstpot : LUT5
generic map(
INIT => X"FDA87520"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB0_1135,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB1_1136,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_21_BRB2_1076,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_21_BRB3_1077,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_21_BRB4_1078,
O => NlwRenamedSig_OI_RD_ADDR(21)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_17_rstpot : LUT5
generic map(
INIT => X"FDA87520"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB0_1135,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB1_1136,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_17_BRB2_1063,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_17_BRB3_1064,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_17_BRB4_1065,
O => NlwRenamedSig_OI_RD_ADDR(17)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_22_rstpot : LUT5
generic map(
INIT => X"FDA87520"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB0_1135,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB1_1136,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_22_BRB2_1079,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_22_BRB3_1080,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_22_BRB4_1081,
O => NlwRenamedSig_OI_RD_ADDR(22)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_18_rstpot : LUT5
generic map(
INIT => X"FDA87520"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB0_1135,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB1_1136,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_18_BRB2_1066,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_18_BRB3_1067,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_18_BRB4_1068,
O => NlwRenamedSig_OI_RD_ADDR(18)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_23_rstpot : LUT5
generic map(
INIT => X"FDA87520"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB0_1135,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB1_1136,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_23_BRB2_1082,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_23_BRB3_1083,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_23_BRB4_1084,
O => NlwRenamedSig_OI_RD_ADDR(23)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_19_rstpot : LUT5
generic map(
INIT => X"FDA87520"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB0_1135,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB1_1136,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_19_BRB2_1069,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_19_BRB3_1070,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_19_BRB4_1071,
O => NlwRenamedSig_OI_RD_ADDR(19)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_24_rstpot : LUT5
generic map(
INIT => X"FDA87520"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB0_1135,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB1_1136,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_24_BRB2_1085,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_24_BRB3_1086,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_24_BRB4_1087,
O => NlwRenamedSig_OI_RD_ADDR(24)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_25_rstpot : LUT5
generic map(
INIT => X"FDA87520"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB0_1135,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB1_1136,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_25_BRB2_1088,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_25_BRB3_1089,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_25_BRB4_1090,
O => NlwRenamedSig_OI_RD_ADDR(25)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_30_rstpot : LUT5
generic map(
INIT => X"FDA87520"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB0_1135,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB1_1136,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_30_BRB2_1103,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_30_BRB3_1104,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_30_BRB4_1105,
O => NlwRenamedSig_OI_RD_ADDR(30)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_26_rstpot : LUT5
generic map(
INIT => X"FDA87520"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB0_1135,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB1_1136,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_26_BRB2_1091,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_26_BRB3_1092,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_26_BRB4_1093,
O => NlwRenamedSig_OI_RD_ADDR(26)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_rstpot : LUT5
generic map(
INIT => X"FDA87520"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB0_1135,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB1_1136,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB2_1137,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB3_1138,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB4_1139,
O => NlwRenamedSig_OI_RD_ADDR(31)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_29_rstpot : LUT5
generic map(
INIT => X"FDA87520"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB0_1135,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB1_1136,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_29_BRB2_1100,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_29_BRB3_1101,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_29_BRB4_1102,
O => NlwRenamedSig_OI_RD_ADDR(29)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_27_rstpot : LUT5
generic map(
INIT => X"FDA87520"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB0_1135,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB1_1136,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_27_BRB2_1094,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_27_BRB3_1095,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_27_BRB4_1096,
O => NlwRenamedSig_OI_RD_ADDR(27)
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_28_rstpot : LUT5
generic map(
INIT => X"FDA87520"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB0_1135,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB1_1136,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_28_BRB2_1097,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_28_BRB3_1098,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_28_BRB4_1099,
O => NlwRenamedSig_OI_RD_ADDR(28)
);
IB_ENDPOINT_I_U_read_ctrl_U_fetch_marker_HEADER_LAST1_SW9 : LUT2
generic map(
INIT => X"E"
)
port map (
I0 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd2,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd1_912,
O => N207
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_count_not00011 : LUT6
generic map(
INIT => X"FFFF0000FFFF0B03"
)
port map (
I0 => RD_ARDY_ACCEPT,
I1 => N207,
I2 => IB_ENDPOINT_I_rd_pipe_eof_n,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_cmp_eq0000_916,
I4 => IB_ENDPOINT_I_U_read_ctrl_addr_ce,
I5 => IB_ENDPOINT_I_U_read_ctrl_hbuf_full,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_3_not0001
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB4_rstpot : LUT6
generic map(
INIT => X"D1D1F0F0FF00FF00"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_reg_history_BRB3_103,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_reg_history_BRB0_101,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_reg_history_BRB1_102,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB4_287,
I4 => N115,
I5 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_not0001_289,
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB4_rstpot_288
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB10_rstpot : LUT6
generic map(
INIT => X"AEA2AEA2FFFF0000"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_reg_history_BRB0_90,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_reg_history_BRB1_91,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_reg_history_BRB3_94,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_reg_history_BRB2_93,
I4 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB10_269,
I5 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_not0001_289,
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB10_rstpot_270
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0_rstpot : LUT6
generic map(
INIT => X"BBA94446BBAA4444"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0_BRB0_767,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0_BRB1_768,
I2 => IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd1_BRB4_627,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0_BRB3_769,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0_BRB4_770,
I5 => IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd1_BRB5_628,
O => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB5_rstpot : LUT6
generic map(
INIT => X"0500CCCC05000500"
)
port map (
I0 => RESET,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB5_276,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd1_114,
I3 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_present_state_FSM_FFd1_309,
I4 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr_next,
I5 => N209,
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB5_rstpot_277
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB2_rstpot : LUT6
generic map(
INIT => X"AFAFA3A0ACAFA0A0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd2_265,
I1 => N195,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr_next,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ,
I4 => N211,
I5 => N212,
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB2_rstpot_285
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB1_rstpot : LUT6
generic map(
INIT => X"AFAFA3A0ACAFA0A0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd1_263,
I1 => N195,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr_next,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ,
I4 => N214,
I5 => N215,
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB1_rstpot_271
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB3_rstpot : LUT6
generic map(
INIT => X"AFAFA3A0ACAFA0A0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_cnt_addrpart_we_0_0_261,
I1 => N195,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr_next,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ,
I4 => N217,
I5 => N218,
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB3_rstpot_274
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_not0001_SW0 : LUT6
generic map(
INIT => X"FEFEFFF0FEFEFFFF"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd1_315,
I1 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd2_317,
I2 => IB_ENDPOINT_I_U_down_buf_addr_dec_out_sof_n,
I3 => N195,
I4 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP,
I5 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ,
O => N209
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB1 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB1_439
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_4_1_212,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB2_440
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB3 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_4_0_211,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB3_441
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(36),
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_4_BRB4_442
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_5_BRB2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_5_1_234,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_5_BRB2_454
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_5_BRB3 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_5_0_233,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_5_BRB3_455
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_5_BRB4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(37),
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_5_BRB4_456
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_6_BRB2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_6_1_248,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_6_BRB2_462
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_6_BRB3 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_6_0_247,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_6_BRB3_463
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_6_BRB4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(38),
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_6_BRB4_464
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_7_BRB2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_7_1_250,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_7_BRB2_466
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_7_BRB3 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_7_0_249,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_7_BRB3_467
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_7_BRB4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(39),
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_7_BRB4_468
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_8_BRB2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_8_1_252,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_8_BRB2_470
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_8_BRB3 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_8_0_251,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_8_BRB3_471
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_8_BRB4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(40),
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_8_BRB4_472
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_9_BRB2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_9_1_254,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_9_BRB2_474
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_9_BRB3 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_9_0_253,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_9_BRB3_475
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_9_BRB4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(41),
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_9_BRB4_476
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_10_BRB2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_10_1_126,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_10_BRB2_328
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_10_BRB3 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_10_0_125,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_10_BRB3_329
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_10_BRB4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(42),
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_10_BRB4_330
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_11_BRB2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_11_1_128,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_11_BRB2_332
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_11_BRB3 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_11_0_127,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_11_BRB3_333
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_11_BRB4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(43),
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_11_BRB4_334
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_12_BRB2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_12_1_130,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_12_BRB2_336
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_12_BRB3 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_12_0_129,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_12_BRB3_337
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_12_BRB4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(44),
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_12_BRB4_338
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_13_BRB2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_13_1_132,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_13_BRB2_340
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_13_BRB3 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_13_0_131,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_13_BRB3_341
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_13_BRB4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(45),
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_13_BRB4_342
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_14_BRB2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_14_1_134,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_14_BRB2_344
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_14_BRB3 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_14_0_133,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_14_BRB3_345
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_14_BRB4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(46),
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_14_BRB4_346
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_15_BRB2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_15_1_136,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_15_BRB2_348
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_15_BRB3 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_15_0_135,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_15_BRB3_349
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_15_BRB4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(47),
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_15_BRB4_350
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_16_BRB2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_16_1_138,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_16_BRB2_352
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_16_BRB3 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_16_0_137,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_16_BRB3_353
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_16_BRB4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(48),
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_16_BRB4_354
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_17_BRB2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_17_1_140,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_17_BRB2_356
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_17_BRB3 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_17_0_139,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_17_BRB3_357
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_17_BRB4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(49),
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_17_BRB4_358
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_18_BRB2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_18_1_142,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_18_BRB2_360
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_18_BRB3 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_18_0_141,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_18_BRB3_361
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_18_BRB4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(50),
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_18_BRB4_362
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_19_BRB2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_19_1_144,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_19_BRB2_364
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_19_BRB3 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_19_0_143,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_19_BRB3_365
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_19_BRB4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(51),
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_19_BRB4_366
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_20_BRB2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_20_1_148,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_20_BRB2_370
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_20_BRB3 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_20_0_147,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_20_BRB3_371
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_20_BRB4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(52),
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_20_BRB4_372
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_21_BRB2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_21_1_150,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_21_BRB2_374
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_21_BRB3 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_21_0_149,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_21_BRB3_375
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_21_BRB4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(53),
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_21_BRB4_376
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_22_BRB2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_22_1_152,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_22_BRB2_378
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_22_BRB3 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_22_0_151,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_22_BRB3_379
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_22_BRB4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(54),
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_22_BRB4_380
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_23_BRB2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_23_1_154,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_23_BRB2_382
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_23_BRB3 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_23_0_153,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_23_BRB3_383
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_23_BRB4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(55),
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_23_BRB4_384
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_24_BRB2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_24_1_156,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_24_BRB2_386
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_24_BRB3 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_24_0_155,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_24_BRB3_387
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_24_BRB4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(56),
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_24_BRB4_388
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_25_BRB2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_25_1_158,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_25_BRB2_390
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_25_BRB3 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_25_0_157,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_25_BRB3_391
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_25_BRB4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(57),
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_25_BRB4_392
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_26_BRB2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_26_1_160,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_26_BRB2_394
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_26_BRB3 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_26_0_159,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_26_BRB3_395
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_26_BRB4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(58),
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_26_BRB4_396
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_27_BRB2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_27_1_162,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_27_BRB2_398
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_27_BRB3 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_27_0_161,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_27_BRB3_399
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_27_BRB4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(59),
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_27_BRB4_400
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_28_BRB2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_28_1_164,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_28_BRB2_402
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_28_BRB3 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_28_0_163,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_28_BRB3_403
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_28_BRB4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(60),
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_28_BRB4_404
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_29_BRB2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_29_1_166,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_29_BRB2_406
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_29_BRB3 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_29_0_165,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_29_BRB3_407
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_29_BRB4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(61),
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_29_BRB4_408
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_30_BRB2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_30_1_170,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_30_BRB2_412
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_30_BRB3 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_30_0_169,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_30_BRB3_413
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_30_BRB4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(62),
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_30_BRB4_414
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_31_BRB2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_31_1_172,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_31_BRB2_416
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_31_BRB3 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_31_0_171,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_31_BRB3_417
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_31_BRB4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(63),
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_31_BRB4_418
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB0 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_3_not0001,
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB0_1135
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB1 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_addr_ce,
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB1_1136
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(31),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB2_1137
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB3 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_RD_ADDR(31),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB3_1138
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(28),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB4_1139
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd1_BRB0 : FDS
generic map(
INIT => '1'
)
port map (
C => CLK,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd2_629,
S => RESET,
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd1_BRB0_623
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd1_BRB1 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_downrd_sof_n,
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd1_BRB1_624
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd1_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_eof_n_reg_480,
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd1_BRB2_625
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd1_BRB3 : FDR
generic map(
INIT => '0'
)
port map (
C => CLK,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd1,
R => RESET,
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd1_BRB3_626
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd1_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_rd_pipe_dst_rdy_n,
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd1_BRB4_627
);
IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd1_BRB5 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_rdy_697,
Q => IB_ENDPOINT_I_U_rd_pipe_PIPE_present_state_FSM_FFd1_BRB5_628
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB0 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd1_315,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB0_320
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB1 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => NlwRenamedSig_OI_WR_DATA_0_Q,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB1_321
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB2_322
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB3 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_out_sof_n,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB3_323
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(32),
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB4_324
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB5 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd2_317,
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_0_BRB5_325
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_1_BRB2 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(33),
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_1_BRB2_367
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_2_BRB4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(34),
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_2_BRB4_409
);
IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_3_BRB4 : FDE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_or0000_inv,
D => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(35),
Q => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg_3_BRB4_427
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB1 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_ADDR_29_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB1_1401
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(26),
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB2_1402
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB3 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_wr_src_rdy_n,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB3_1403
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB4 : FD
port map (
C => CLK,
D => N173,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB4_1404
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB5 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_DATA_61_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB5_1405
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_28_BRB1 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_ADDR_28_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_28_BRB1_1398
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_28_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(25),
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_28_BRB2_1399
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_28_BRB5 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_DATA_60_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_28_BRB5_1400
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_26_BRB1 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_ADDR_26_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_26_BRB1_1392
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_26_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(23),
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_26_BRB2_1393
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_26_BRB5 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_DATA_58_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_26_BRB5_1394
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_27_BRB1 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_ADDR_27_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_27_BRB1_1395
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_27_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(24),
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_27_BRB2_1396
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_27_BRB5 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_DATA_59_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_27_BRB5_1397
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_BRB1 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_ADDR_31_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_BRB1_1438
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(28),
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_BRB2_1439
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_BRB5 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_DATA_63_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_BRB5_1440
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_30_BRB1 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_ADDR_30_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_30_BRB1_1406
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_30_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(27),
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_30_BRB2_1407
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_30_BRB5 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_DATA_62_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_30_BRB5_1408
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0_BRB0 : FDC
port map (
C => CLK,
CLR => RESET,
D => IB_ENDPOINT_I_U_read_ctrl_N01,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0_BRB0_767
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0_BRB1 : FDC
port map (
C => CLK,
CLR => RESET,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd1_771,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0_BRB1_768
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0_BRB3 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd2,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0_BRB3_769
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0_BRB4 : FDC
port map (
C => CLK,
CLR => RESET,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0_BRB4_770
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_25_BRB1 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_ADDR_25_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_25_BRB1_1389
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_25_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(22),
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_25_BRB2_1390
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_25_BRB5 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_DATA_57_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_25_BRB5_1391
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_24_BRB1 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_ADDR_24_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_24_BRB1_1386
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_24_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(21),
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_24_BRB2_1387
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_24_BRB5 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_DATA_56_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_24_BRB5_1388
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_23_BRB1 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_ADDR_23_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_23_BRB1_1383
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_23_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(20),
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_23_BRB2_1384
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_23_BRB5 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_DATA_55_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_23_BRB5_1385
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_22_BRB1 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_ADDR_22_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_22_BRB1_1380
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_22_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(19),
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_22_BRB2_1381
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_22_BRB5 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_DATA_54_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_22_BRB5_1382
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_21_BRB1 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_ADDR_21_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_21_BRB1_1377
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_21_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(18),
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_21_BRB2_1378
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_21_BRB5 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_DATA_53_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_21_BRB5_1379
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_30_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(30),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_30_BRB2_1103
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_30_BRB3 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_RD_ADDR(30),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_30_BRB3_1104
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_30_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(27),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_30_BRB4_1105
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_20_BRB1 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_ADDR_20_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_20_BRB1_1374
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_20_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(17),
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_20_BRB2_1375
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_20_BRB5 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_DATA_52_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_20_BRB5_1376
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_29_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(29),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_29_BRB2_1100
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_29_BRB3 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_RD_ADDR(29),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_29_BRB3_1101
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_29_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(26),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_29_BRB4_1102
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_19_BRB1 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_ADDR_19_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_19_BRB1_1370
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_19_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(16),
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_19_BRB2_1371
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_19_BRB5 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_DATA_51_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_19_BRB5_1372
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_28_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(28),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_28_BRB2_1097
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_28_BRB3 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_RD_ADDR(28),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_28_BRB3_1098
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_28_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(25),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_28_BRB4_1099
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_18_BRB1 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_ADDR_18_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_18_BRB1_1367
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_18_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(15),
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_18_BRB2_1368
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_18_BRB5 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_DATA_50_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_18_BRB5_1369
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_27_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(27),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_27_BRB2_1094
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_27_BRB3 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_RD_ADDR(27),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_27_BRB3_1095
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_27_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(24),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_27_BRB4_1096
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_17_BRB2 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_ADDR_17_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_17_BRB2_1364
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_26_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(26),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_26_BRB2_1091
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_26_BRB3 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_RD_ADDR(26),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_26_BRB3_1092
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_26_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(23),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_26_BRB4_1093
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_25_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(25),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_25_BRB2_1088
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_25_BRB3 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_RD_ADDR(25),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_25_BRB3_1089
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_25_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(22),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_25_BRB4_1090
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_24_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(24),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_24_BRB2_1085
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_24_BRB3 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_RD_ADDR(24),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_24_BRB3_1086
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_24_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(21),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_24_BRB4_1087
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_23_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(23),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_23_BRB2_1082
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_23_BRB3 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_RD_ADDR(23),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_23_BRB3_1083
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_23_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(20),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_23_BRB4_1084
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_22_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(22),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_22_BRB2_1079
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_22_BRB3 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_RD_ADDR(22),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_22_BRB3_1080
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_22_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(19),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_22_BRB4_1081
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_21_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(21),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_21_BRB2_1076
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_21_BRB3 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_RD_ADDR(21),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_21_BRB3_1077
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_21_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(18),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_21_BRB4_1078
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB0 : FDP
generic map(
INIT => '0'
)
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd2,
PRE => RESET,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB0_774
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB1 : FDC
port map (
C => CLK,
CLR => RESET,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout_rdy_697,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB1_775
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB2 : FD
generic map(
INIT => '1'
)
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd1_771,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB2_776
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB3 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB3_777
);
IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_N01,
Q => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB4_778
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_20_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(20),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_20_BRB2_1073
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_20_BRB3 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_RD_ADDR(20),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_20_BRB3_1074
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_20_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(17),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_20_BRB4_1075
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_19_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(19),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_19_BRB2_1069
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_19_BRB3 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_RD_ADDR(19),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_19_BRB3_1070
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_19_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(16),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_19_BRB4_1071
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_18_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(18),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_18_BRB2_1066
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_18_BRB3 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_RD_ADDR(18),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_18_BRB3_1067
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_18_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(15),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_18_BRB4_1068
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_17_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(17),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_17_BRB2_1063
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_17_BRB3 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_RD_ADDR(17),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_17_BRB3_1064
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_17_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(14),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_17_BRB4_1065
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_16_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(16),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_16_BRB2_1060
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_16_BRB3 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_RD_ADDR(16),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_16_BRB3_1061
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_16_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(13),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_16_BRB4_1062
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_15_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(15),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_15_BRB2_1057
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_15_BRB3 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_RD_ADDR(15),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_15_BRB3_1058
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_15_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(12),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_15_BRB4_1059
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_14_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(14),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_14_BRB2_1054
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_14_BRB3 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_RD_ADDR(14),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_14_BRB3_1055
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_14_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(11),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_14_BRB4_1056
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_13_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(13),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_13_BRB2_1051
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_13_BRB3 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_RD_ADDR(13),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_13_BRB3_1052
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_13_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(10),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_13_BRB4_1053
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_12_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(12),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_12_BRB2_1048
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_12_BRB3 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_RD_ADDR(12),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_12_BRB3_1049
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_12_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(9),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_12_BRB4_1050
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_11_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(11),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_11_BRB2_1045
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_11_BRB3 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_RD_ADDR(11),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_11_BRB3_1046
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_11_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(8),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_11_BRB4_1047
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_10_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(10),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_10_BRB2_1042
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_10_BRB3 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_RD_ADDR(10),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_10_BRB3_1043
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_10_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(7),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_10_BRB4_1044
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_9_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(9),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_9_BRB2_1160
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_9_BRB3 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_RD_ADDR(9),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_9_BRB3_1161
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_9_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(6),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_9_BRB4_1162
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_8_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(8),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_8_BRB2_1157
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_8_BRB3 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_RD_ADDR(8),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_8_BRB3_1158
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_8_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(5),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_8_BRB4_1159
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_16_BRB2 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_ADDR_16_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_16_BRB2_1361
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_7_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(7),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_7_BRB2_1154
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_7_BRB3 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_RD_ADDR(7),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_7_BRB3_1155
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_7_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(4),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_7_BRB4_1156
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_15_BRB2 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_ADDR_15_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_15_BRB2_1358
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_6_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(6),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_6_BRB2_1151
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_6_BRB3 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_RD_ADDR(6),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_6_BRB3_1152
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_6_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(3),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_6_BRB4_1153
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_14_BRB2 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_ADDR_14_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_14_BRB2_1355
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_5_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(5),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_5_BRB2_1148
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_5_BRB3 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_RD_ADDR(5),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_5_BRB3_1149
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_5_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(2),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_5_BRB4_1150
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_13_BRB2 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_ADDR_13_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_13_BRB2_1352
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_4_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(4),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_4_BRB2_1145
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_4_BRB3 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_RD_ADDR(4),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_4_BRB3_1146
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_4_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(1),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_4_BRB4_1147
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_12_BRB2 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_ADDR_12_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_12_BRB2_1349
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_11_BRB2 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_ADDR_11_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_11_BRB2_1346
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_10_rstpot : LUT6
generic map(
INIT => X"AAF0AAF0CCCCAAF0"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_10_BRB5_1345,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_10_BRB4_1344,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_10_BRB2_1343,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_10_BRB1_1342,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB4_1404,
I5 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB3_1403,
O => NlwRenamedSig_OI_WR_ADDR_10_Q
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_9_rstpot : LUT6
generic map(
INIT => X"AAF0AAF0CCCCAAF0"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_9_BRB5_1462,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_9_BRB4_1461,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_9_BRB2_1460,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_10_BRB1_1342,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB4_1404,
I5 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB3_1403,
O => NlwRenamedSig_OI_WR_ADDR_9_Q
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_8_rstpot : LUT6
generic map(
INIT => X"AAF0AAF0CCCCAAF0"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_8_BRB5_1459,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_8_BRB4_1458,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_8_BRB2_1457,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_10_BRB1_1342,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB4_1404,
I5 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB3_1403,
O => NlwRenamedSig_OI_WR_ADDR_8_Q
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_7_rstpot : LUT6
generic map(
INIT => X"AAF0AAF0CCCCAAF0"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_7_BRB5_1456,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_7_BRB4_1455,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_7_BRB2_1454,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_10_BRB1_1342,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB4_1404,
I5 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB3_1403,
O => NlwRenamedSig_OI_WR_ADDR_7_Q
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_6_rstpot : LUT6
generic map(
INIT => X"AAF0AAF0CCCCAAF0"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_6_BRB5_1453,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_6_BRB4_1452,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_6_BRB2_1451,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_10_BRB1_1342,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB4_1404,
I5 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB3_1403,
O => NlwRenamedSig_OI_WR_ADDR_6_Q
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_5_rstpot : LUT6
generic map(
INIT => X"AAF0AAF0CCCCAAF0"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_5_BRB5_1450,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_5_BRB4_1449,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_5_BRB2_1448,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_10_BRB1_1342,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB4_1404,
I5 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB3_1403,
O => NlwRenamedSig_OI_WR_ADDR_5_Q
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_4_rstpot : LUT6
generic map(
INIT => X"AAF0AAF0CCCCAAF0"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_4_BRB5_1447,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_4_BRB4_1446,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_4_BRB2_1445,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_10_BRB1_1342,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB4_1404,
I5 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB3_1403,
O => NlwRenamedSig_OI_WR_ADDR_4_Q
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_3_rstpot : LUT6
generic map(
INIT => X"FDFCA8FC75302030"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB3_1403,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_10_BRB1_1342,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_3_BRB2_1442,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB4_1404,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_3_BRB4_1443,
I5 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_3_BRB5_1444,
O => NlwRenamedSig_OI_WR_ADDR_3_Q
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_reg_history_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd2_265,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_reg_history_BRB4_104
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_reg_history_BRB5 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd1_263,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_reg_history_BRB5_105
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_reg_history_BRB6 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_transfer,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_reg_history_BRB6_106
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_reg_history_BRB7 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_addr_start_aux,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_high_reg_history_BRB7_107
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_3_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_rd_pipe_PIPE_reg_dout(3),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_3_BRB2_1141
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_3_BRB3 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_RD_ADDR(3),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_3_BRB3_1142
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_3_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_3_add0000(0),
Q => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_3_BRB4_1143
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB0 : FDP
generic map(
INIT => '0'
)
port map (
C => CLK,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2,
PRE => RESET,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB0_117
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB1 : FDC
port map (
C => CLK,
CLR => RESET,
D => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_present_state_FSM_FFd1_309,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB1_118
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_pause_transfer,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB2_119
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB3 : FD
generic map(
INIT => '1'
)
port map (
C => CLK,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd1_114,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB3_120
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB4_121
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB5 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_down_buf_addr_dec_out_dst_rdy_n,
Q => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_BRB5_122
);
IB_ENDPOINT_I_U_down_buf_U_down_fsm_RD_SRC_RDY_N1 : LUT6
generic map(
INIT => X"FFABFFA8FFAAFFAA"
)
port map (
I0 => N142,
I1 => NlwRenamedSig_OI_WR_DATA_0_Q,
I2 => IB_ENDPOINT_I_U_down_buf_addr_dec_out_sof_n,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2,
I4 => N143,
I5 => N83,
O => IB_ENDPOINT_I_U_down_buf_fsm_rd_src_rdy_n
);
IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB0 : FDS
port map (
C => CLK,
D => IB_ENDPOINT_I_wr_src_rdy_n,
S => RESET,
Q => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB0_1278
);
IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB1 : FDR
port map (
C => CLK,
D => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0,
R => RESET,
Q => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB1_1279
);
IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB2 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd1_1475,
Q => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB2_1280
);
IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB3 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd2_1477,
Q => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB3_1281
);
IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB4 : FD
port map (
C => CLK,
D => WR_RDY,
Q => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB4_1282
);
IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB5 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_wr_eof_n,
Q => IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_transfer_cnt_0_0_BRB5_1283
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_10_BRB1 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_wr_sof_n,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_10_BRB1_1342
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_10_BRB2 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_DATA_42_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_10_BRB2_1343
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_10_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(7),
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_10_BRB4_1344
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_10_BRB5 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_ADDR_10_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_10_BRB5_1345
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_9_BRB2 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_DATA_41_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_9_BRB2_1460
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_9_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(6),
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_9_BRB4_1461
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_9_BRB5 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_ADDR_9_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_9_BRB5_1462
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_8_BRB2 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_DATA_40_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_8_BRB2_1457
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_8_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(5),
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_8_BRB4_1458
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_8_BRB5 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_ADDR_8_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_8_BRB5_1459
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_7_BRB2 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_DATA_39_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_7_BRB2_1454
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_7_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(4),
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_7_BRB4_1455
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_7_BRB5 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_ADDR_7_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_7_BRB5_1456
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_6_BRB2 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_DATA_38_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_6_BRB2_1451
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_6_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(3),
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_6_BRB4_1452
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_6_BRB5 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_ADDR_6_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_6_BRB5_1453
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_5_BRB2 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_DATA_37_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_5_BRB2_1448
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_5_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(2),
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_5_BRB4_1449
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_5_BRB5 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_ADDR_5_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_5_BRB5_1450
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_4_BRB2 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_DATA_36_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_4_BRB2_1445
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_4_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(1),
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_4_BRB4_1446
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_4_BRB5 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_ADDR_4_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_4_BRB5_1447
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_17_BRB5 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(14),
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_17_BRB5_1365
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_17_BRB6 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_DATA_49_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_17_BRB6_1366
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_16_BRB5 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(13),
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_16_BRB5_1362
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_16_BRB6 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_DATA_48_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_16_BRB6_1363
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_15_BRB5 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(12),
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_15_BRB5_1359
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_15_BRB6 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_DATA_47_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_15_BRB6_1360
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_14_BRB5 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(11),
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_14_BRB5_1356
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_14_BRB6 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_DATA_46_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_14_BRB6_1357
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_13_BRB5 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(10),
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_13_BRB5_1353
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_13_BRB6 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_DATA_45_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_13_BRB6_1354
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_12_BRB5 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(9),
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_12_BRB5_1350
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_12_BRB6 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_DATA_44_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_12_BRB6_1351
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_11_BRB5 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(8),
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_11_BRB5_1347
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_11_BRB6 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_DATA_43_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_11_BRB6_1348
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_3_BRB2 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_DATA_35_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_3_BRB2_1442
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_3_BRB4 : FD
port map (
C => CLK,
D => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_3_add0000(0),
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_3_BRB4_1443
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_3_BRB5 : FD
port map (
C => CLK,
D => NlwRenamedSig_OI_WR_ADDR_3_Q,
Q => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_3_BRB5_1444
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_reg_history_BRB1_rstpot : LUT5
generic map(
INIT => X"0000B2A2"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd2_265,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd1_263,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_transfer,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_addr_start_aux,
I4 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_reg_history_or0000,
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_cmp_base_reg_history_BRB1_rstpot_92
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data_and00001 : LUT4
generic map(
INIT => X"5455"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_present_state(0),
I1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_760,
I2 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
O => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data_and0000
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd1_In1 : LUT6
generic map(
INIT => X"DF8A8A8AFFAAAAAA"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd1_263,
I1 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_out_data_aux(65),
I2 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_present_state_FSM_FFd1_309,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd2_265,
I4 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_cnt_addrpart_we_0_0_261,
I5 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_transfer,
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd1_In
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_lut_0_Q : LUT5
generic map(
INIT => X"082A5D7F"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB0_1135,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB1_1136,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_3_BRB4_1143,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_3_BRB2_1141,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_3_BRB3_1142,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_Madd_reg_addr64_31_3_add0000_lut(0)
);
IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd2_In1 : LUT6
generic map(
INIT => X"545454FFF4F4F4F7"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_cmp_eq0000_916,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd1_912,
I2 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd2,
I3 => IB_ENDPOINT_I_U_read_ctrl_hbuf_full,
I4 => IB_ENDPOINT_I_rd_pipe_eof_n,
I5 => RD_ARDY_ACCEPT,
O => IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd2_In
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_lut_0_Q : LUT6
generic map(
INIT => X"0404BF0404BFBFBF"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB3_1403,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB4_1404,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_3_BRB4_1443,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_10_BRB1_1342,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_3_BRB5_1444,
I5 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_3_BRB2_1442,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_Madd_reg_addr32_31_3_add0000_lut(0)
);
IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd2_In_SW2 : LUT6
generic map(
INIT => X"F0F5F0F3F0F0F0F0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_65_1_246,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_65_0_245,
I2 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd2_317,
I3 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd1_315,
I4 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I5 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP,
O => N9
);
IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd1_In_SW0 : LUT6
generic map(
INIT => X"F0F5F0F3F0F0F0F0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_65_1_246,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_65_0_245,
I2 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd1_315,
I3 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd2_317,
I4 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I5 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP,
O => N11
);
IB_ENDPOINT_I_U_down_buf_U_swapper_out_mx_63_1 : LUT5
generic map(
INIT => X"AAAACCF0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(63),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_31_1_172,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_31_0_171,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I4 => IB_ENDPOINT_I_downrd_sof_n,
O => IB_ENDPOINT_I_downrd_data(63)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_out_mx_62_1 : LUT5
generic map(
INIT => X"AAAACCF0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(62),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_30_1_170,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_30_0_169,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I4 => IB_ENDPOINT_I_downrd_sof_n,
O => IB_ENDPOINT_I_downrd_data(62)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_out_mx_61_1 : LUT5
generic map(
INIT => X"AAAACCF0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(61),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_29_1_166,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_29_0_165,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I4 => IB_ENDPOINT_I_downrd_sof_n,
O => IB_ENDPOINT_I_downrd_data(61)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_out_mx_60_1 : LUT5
generic map(
INIT => X"AAAACCF0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(60),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_28_1_164,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_28_0_163,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I4 => IB_ENDPOINT_I_downrd_sof_n,
O => IB_ENDPOINT_I_downrd_data(60)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_out_mx_59_1 : LUT5
generic map(
INIT => X"AAAACCF0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(59),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_27_1_162,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_27_0_161,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I4 => IB_ENDPOINT_I_downrd_sof_n,
O => IB_ENDPOINT_I_downrd_data(59)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_out_mx_58_1 : LUT5
generic map(
INIT => X"AAAACCF0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(58),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_26_1_160,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_26_0_159,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I4 => IB_ENDPOINT_I_downrd_sof_n,
O => IB_ENDPOINT_I_downrd_data(58)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_out_mx_57_1 : LUT5
generic map(
INIT => X"AAAACCF0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(57),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_25_1_158,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_25_0_157,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I4 => IB_ENDPOINT_I_downrd_sof_n,
O => IB_ENDPOINT_I_downrd_data(57)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_out_mx_56_1 : LUT5
generic map(
INIT => X"AAAACCF0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(56),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_24_1_156,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_24_0_155,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I4 => IB_ENDPOINT_I_downrd_sof_n,
O => IB_ENDPOINT_I_downrd_data(56)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_out_mx_55_1 : LUT5
generic map(
INIT => X"AAAACCF0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(55),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_23_1_154,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_23_0_153,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I4 => IB_ENDPOINT_I_downrd_sof_n,
O => IB_ENDPOINT_I_downrd_data(55)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_out_mx_54_1 : LUT5
generic map(
INIT => X"AAAACCF0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(54),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_22_1_152,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_22_0_151,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I4 => IB_ENDPOINT_I_downrd_sof_n,
O => IB_ENDPOINT_I_downrd_data(54)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_out_mx_53_1 : LUT5
generic map(
INIT => X"AAAACCF0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(53),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_21_1_150,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_21_0_149,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I4 => IB_ENDPOINT_I_downrd_sof_n,
O => IB_ENDPOINT_I_downrd_data(53)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_out_mx_52_1 : LUT5
generic map(
INIT => X"AAAACCF0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(52),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_20_1_148,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_20_0_147,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I4 => IB_ENDPOINT_I_downrd_sof_n,
O => IB_ENDPOINT_I_downrd_data(52)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_out_mx_51_1 : LUT5
generic map(
INIT => X"AAAACCF0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(51),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_19_1_144,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_19_0_143,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I4 => IB_ENDPOINT_I_downrd_sof_n,
O => IB_ENDPOINT_I_downrd_data(51)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_out_mx_50_1 : LUT5
generic map(
INIT => X"AAAACCF0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(50),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_18_1_142,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_18_0_141,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I4 => IB_ENDPOINT_I_downrd_sof_n,
O => IB_ENDPOINT_I_downrd_data(50)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_out_mx_49_1 : LUT5
generic map(
INIT => X"AAAACCF0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(49),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_17_1_140,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_17_0_139,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I4 => IB_ENDPOINT_I_downrd_sof_n,
O => IB_ENDPOINT_I_downrd_data(49)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_out_mx_48_1 : LUT5
generic map(
INIT => X"AAAACCF0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(48),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_16_1_138,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_16_0_137,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I4 => IB_ENDPOINT_I_downrd_sof_n,
O => IB_ENDPOINT_I_downrd_data(48)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_out_mx_47_1 : LUT5
generic map(
INIT => X"AAAACCF0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(47),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_15_1_136,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_15_0_135,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I4 => IB_ENDPOINT_I_downrd_sof_n,
O => IB_ENDPOINT_I_downrd_data(47)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_out_mx_46_1 : LUT5
generic map(
INIT => X"AAAACCF0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(46),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_14_1_134,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_14_0_133,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I4 => IB_ENDPOINT_I_downrd_sof_n,
O => IB_ENDPOINT_I_downrd_data(46)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_out_mx_45_1 : LUT5
generic map(
INIT => X"AAAACCF0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(45),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_13_1_132,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_13_0_131,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I4 => IB_ENDPOINT_I_downrd_sof_n,
O => IB_ENDPOINT_I_downrd_data(45)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_out_mx_44_1 : LUT5
generic map(
INIT => X"AAAACCF0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(44),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_12_1_130,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_12_0_129,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I4 => IB_ENDPOINT_I_downrd_sof_n,
O => IB_ENDPOINT_I_downrd_data(44)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_out_mx_43_1 : LUT5
generic map(
INIT => X"AAAACCF0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(43),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_11_1_128,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_11_0_127,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I4 => IB_ENDPOINT_I_downrd_sof_n,
O => IB_ENDPOINT_I_downrd_data(43)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_out_mx_42_1 : LUT5
generic map(
INIT => X"AAAACCF0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(42),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_10_1_126,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_10_0_125,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I4 => IB_ENDPOINT_I_downrd_sof_n,
O => IB_ENDPOINT_I_downrd_data(42)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_out_mx_41_1 : LUT5
generic map(
INIT => X"AAAACCF0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(41),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_9_1_254,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_9_0_253,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I4 => IB_ENDPOINT_I_downrd_sof_n,
O => IB_ENDPOINT_I_downrd_data(41)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_out_mx_40_1 : LUT5
generic map(
INIT => X"AAAACCF0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(40),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_8_1_252,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_8_0_251,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I4 => IB_ENDPOINT_I_downrd_sof_n,
O => IB_ENDPOINT_I_downrd_data(40)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_out_mx_39_1 : LUT5
generic map(
INIT => X"AAAACCF0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(39),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_7_1_250,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_7_0_249,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I4 => IB_ENDPOINT_I_downrd_sof_n,
O => IB_ENDPOINT_I_downrd_data(39)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_out_mx_38_1 : LUT5
generic map(
INIT => X"AAAACCF0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(38),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_6_1_248,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_6_0_247,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I4 => IB_ENDPOINT_I_downrd_sof_n,
O => IB_ENDPOINT_I_downrd_data(38)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_out_mx_37_1 : LUT5
generic map(
INIT => X"AAAACCF0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(37),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_5_1_234,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_5_0_233,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I4 => IB_ENDPOINT_I_downrd_sof_n,
O => IB_ENDPOINT_I_downrd_data(37)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_out_mx_36_1 : LUT5
generic map(
INIT => X"AAAACCF0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(36),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_4_1_212,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_4_0_211,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I4 => IB_ENDPOINT_I_downrd_sof_n,
O => IB_ENDPOINT_I_downrd_data(36)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_out_mx_35_1 : LUT5
generic map(
INIT => X"AAAACCF0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(35),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_3_1_190,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_3_0_189,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I4 => IB_ENDPOINT_I_downrd_sof_n,
O => IB_ENDPOINT_I_downrd_data(35)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_out_mx_34_1 : LUT5
generic map(
INIT => X"AAAACCF0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(34),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_2_1_168,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_2_0_167,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I4 => IB_ENDPOINT_I_downrd_sof_n,
O => IB_ENDPOINT_I_downrd_data(34)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_out_mx_33_1 : LUT5
generic map(
INIT => X"AAAACCF0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(33),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_1_1_146,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_1_0_145,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I4 => IB_ENDPOINT_I_downrd_sof_n,
O => IB_ENDPOINT_I_downrd_data(33)
);
IB_ENDPOINT_I_U_down_buf_U_swapper_out_mx_32_1 : LUT5
generic map(
INIT => X"AAAACCF0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_swapper_data_reg(32),
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_0_1_124,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_0_0_123,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I4 => IB_ENDPOINT_I_downrd_sof_n,
O => IB_ENDPOINT_I_downrd_data(32)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_not0001_SW1 : LUT6
generic map(
INIT => X"AAAAAAACAAAAAAAA"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB2_284,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd2_265,
I2 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd1_315,
I3 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd2_317,
I4 => IB_ENDPOINT_I_U_down_buf_addr_dec_out_sof_n,
I5 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP,
O => N211
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_not0001_SW3 : LUT6
generic map(
INIT => X"AAAAAAACAAAAAAAA"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB1_268,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd1_263,
I2 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd1_315,
I3 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd2_317,
I4 => IB_ENDPOINT_I_U_down_buf_addr_dec_out_sof_n,
I5 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP,
O => N214
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_not0001_SW5 : LUT6
generic map(
INIT => X"AAAAAAACAAAAAAAA"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB3_273,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_cnt_addrpart_we_0_0_261,
I2 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd1_315,
I3 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd2_317,
I4 => IB_ENDPOINT_I_U_down_buf_addr_dec_out_sof_n,
I5 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP,
O => N217
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_not0001_SW2 : LUT6
generic map(
INIT => X"AAAAAAACAAAACCCC"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB2_284,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd2_265,
I2 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd1_315,
I3 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd2_317,
I4 => IB_ENDPOINT_I_U_down_buf_addr_dec_out_sof_n,
I5 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP,
O => N212
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_not0001_SW4 : LUT6
generic map(
INIT => X"AAAAAAACAAAACCCC"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB1_268,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd1_263,
I2 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd1_315,
I3 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd2_317,
I4 => IB_ENDPOINT_I_U_down_buf_addr_dec_out_sof_n,
I5 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP,
O => N215
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_not0001_SW6 : LUT6
generic map(
INIT => X"AAAAAAACAAAACCCC"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB3_273,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_cnt_addrpart_we_0_0_261,
I2 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd1_315,
I3 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd2_317,
I4 => IB_ENDPOINT_I_U_down_buf_addr_dec_out_sof_n,
I5 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP,
O => N218
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_DATA_DST_RDY1_FRB : FDR
generic map(
INIT => '0'
)
port map (
C => CLK,
D => N789,
R => RESET,
Q => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_DATA_DST_RDY1_FRB_763
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_next_state_0_cmp_eq0000_SW0_FRB : FDRE
port map (
C => CLK,
CE => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data_not0001,
D => N790,
R => RESET,
Q => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_next_state_0_cmp_eq0000_SW0_FRB_745
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_mux000011_SW0 : MUXF7
port map (
I0 => N791,
I1 => N792,
S => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB8_279,
O => N83
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_mux000011_SW0_F : LUT5
generic map(
INIT => X"A2808080"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB11_283,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB1_268,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB5_276,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB3_273,
I4 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB2_272,
O => N791
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_mux000011_SW0_G : LUT5
generic map(
INIT => X"A2808080"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB10_269,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB1_268,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB5_276,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB3_273,
I4 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP_BRB2_272,
O => N792
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_not0001_SW0_SW1 : MUXF7
port map (
I0 => N793,
I1 => N794,
S => IB_ENDPOINT_I_wr_dst_rdy_n,
O => N195
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_not0001_SW0_SW1_F : LUT6
generic map(
INIT => X"FFF5FFF3FFF0FFF0"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_0_1_124,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_0_0_123,
I2 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd2_317,
I3 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd1_315,
I4 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I5 => IB_ENDPOINT_I_U_down_buf_fsm_rd_dst_rdy_n,
O => N793
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_not0001_SW0_SW1_G : LUT6
generic map(
INIT => X"FFFFFFFFFFFAFFFC"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_0_1_124,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_0_0_123,
I2 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd1_315,
I3 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd2_317,
I4 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I5 => IB_ENDPOINT_I_U_down_buf_fsm_rd_dst_rdy_n,
O => N794
);
IB_ENDPOINT_I_U_down_buf_U_down_fsm_WR_SRC_RDY_N1_SW0 : LUT5
generic map(
INIT => X"D1000000"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB3_286,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB0_282,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB4_287,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB2_284,
I4 => NlwRenamedSig_OI_WR_DATA_0_Q,
O => N795
);
IB_ENDPOINT_I_U_down_buf_U_down_fsm_WR_SRC_RDY_N1 : LUT6
generic map(
INIT => X"FFDCFFDDFFDDFFDD"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd1_315,
I1 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd2_317,
I2 => IB_ENDPOINT_I_U_down_buf_addr_dec_out_sof_n,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2,
I4 => N83,
I5 => N795,
O => IB_ENDPOINT_I_wr_src_rdy_n
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_next_state_0_mux0000_SW1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_64_1_900,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_64_0_899,
O => N797
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_next_state_0_mux0000 : LUT6
generic map(
INIT => X"AAA2AAA2AAA2AAF7"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_next_state_0_cmp_eq0000_744,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_760,
I3 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd2,
I5 => N797,
O => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_next_state
);
IB_ENDPOINT_I_U_down_buf_U_down_fsm_WR_EOF_N1_SW0 : LUT5
generic map(
INIT => X"2EFFFFFF"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB3_286,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB0_282,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB4_287,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB2_284,
I4 => NlwRenamedSig_OI_WR_DATA_0_Q,
O => N799
);
IB_ENDPOINT_I_U_down_buf_U_down_fsm_WR_EOF_N1 : LUT6
generic map(
INIT => X"FBFBFBFBFBFAFBFB"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd2_317,
I1 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd1_315,
I2 => IB_ENDPOINT_I_U_down_buf_addr_dec_out_eof_n,
I3 => IB_ENDPOINT_I_U_down_buf_addr_dec_out_sof_n,
I4 => N83,
I5 => N799,
O => IB_ENDPOINT_I_wr_eof_n
);
IB_ENDPOINT_I_U_cpl_pipe_OUT_EOF_N1 : LUT3
generic map(
INIT => X"BF"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_760,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I2 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_next_state_0_cmp_eq0000_744,
O => IB_ENDPOINT_I_cpl_pipe_eof_n
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce1 : LUT4
generic map(
INIT => X"0207"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_760,
I2 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd2,
O => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_ce
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_SHREG_CE1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => RD_SRC_RDY,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd1_758,
O => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_shreg_ce
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd1_In1 : LUT6
generic map(
INIT => X"A8A8A8AFAFA8AFAF"
)
port map (
I0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd1_1269,
I1 => IB_UP_DST_RDY_N,
I2 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I4 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd2,
I5 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_760,
O => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd1_In
);
IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_HBUF_WE1 : LUT3
generic map(
INIT => X"08"
)
port map (
I0 => RD_ARDY_ACCEPT,
I1 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd2,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd1_912,
O => IB_ENDPOINT_I_U_read_ctrl_unpck_hbuf_we
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_In1 : LUT6
generic map(
INIT => X"8888888800088088"
)
port map (
I0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd1_1269,
I1 => IB_UP_DST_RDY_N,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd2,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_760,
I5 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
O => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_In
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_present_state_FSM_FFd2_In1 : LUT6
generic map(
INIT => X"A0A0A080AAAAAA88"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_present_state_FSM_FFd1_309,
I1 => RESET,
I2 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_present_state_FSM_FFd2,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_pause_transfer,
I4 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd1_114,
I5 => IB_DOWN_SRC_RDY_N,
O => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_present_state_FSM_FFd2_In
);
IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_present_state_FSM_FFd1_In1 : LUT6
generic map(
INIT => X"AAAAAAA8AAAAFFFF"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_present_state_FSM_FFd1_309,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd1_114,
I2 => RESET,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_pause_transfer,
I4 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_present_state_FSM_FFd2,
I5 => IB_DOWN_SRC_RDY_N,
O => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_present_state_FSM_FFd1_In
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd1_In_SW0 : LUT4
generic map(
INIT => X"FFBF"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
I1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
I2 => RD_SRC_RDY,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd1_758,
O => N5
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_SHREG_CE1 : LUT4
generic map(
INIT => X"4404"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd1_114,
I1 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_present_state_FSM_FFd1_309,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd2_265,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd1_263,
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_ce
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Result_1_1 : LUT4
generic map(
INIT => X"693C"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_760,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
I2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
I3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_DATA_DST_RDY1_FRB_763,
O => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Result(1)
);
IB_ENDPOINT_I_U_write_ctrl_U_fetch_marker_LENGTH_WE1 : LUT6
generic map(
INIT => X"0000555500004000"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_addr_dec_out_sof_n,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_BRB2_284,
I2 => N83,
I3 => N148,
I4 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd2_317,
I5 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd1_315,
O => IB_ENDPOINT_I_U_write_ctrl_addr_we
);
IB_ENDPOINT_I_U_cpl_pipe_OUT_SOF_N1 : LUT5
generic map(
INIT => X"FFFDFFF8"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_65_1_902,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_fsm_u_present_state_FSM_FFd2,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I4 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_65_0_901,
O => IB_ENDPOINT_I_cpl_pipe_sof_n
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Result_2_1 : LUT5
generic map(
INIT => X"6C6CC96C"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
I1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
I2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
I3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_DATA_DST_RDY1_FRB_763,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_760,
O => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Result(2)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_ce_addr_start1 : LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_present_state_FSM_FFd1_309,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd1_114,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd1_263,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd2_265,
I4 => RESET,
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_ce_addr_start
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut_0_Q : LUT6
generic map(
INIT => X"00FF001000FFEFFF"
)
port map (
I0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_760,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I3 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data(0),
I4 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_present_state(0),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_unpck_hbuf_data_out(0),
O => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut(0)
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut_1_Q : LUT6
generic map(
INIT => X"00FF001000FFEFFF"
)
port map (
I0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_760,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I3 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data(1),
I4 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_present_state(0),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_unpck_hbuf_data_out(1),
O => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut(1)
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut_2_Q : LUT6
generic map(
INIT => X"00FF001000FFEFFF"
)
port map (
I0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_760,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I3 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data(2),
I4 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_present_state(0),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_unpck_hbuf_data_out(2),
O => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut(2)
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut_3_Q : LUT6
generic map(
INIT => X"00FF001000FFEFFF"
)
port map (
I0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_760,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I3 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data(3),
I4 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_present_state(0),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_unpck_hbuf_data_out(3),
O => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut(3)
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut_4_Q : LUT6
generic map(
INIT => X"00FF001000FFEFFF"
)
port map (
I0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_760,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I3 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data(4),
I4 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_present_state(0),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_unpck_hbuf_data_out(4),
O => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut(4)
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut_5_Q : LUT6
generic map(
INIT => X"00FF001000FFEFFF"
)
port map (
I0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_760,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I3 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data(5),
I4 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_present_state(0),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_unpck_hbuf_data_out(5),
O => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut(5)
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut_6_Q : LUT6
generic map(
INIT => X"00FF001000FFEFFF"
)
port map (
I0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_760,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I3 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data(6),
I4 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_present_state(0),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_unpck_hbuf_data_out(6),
O => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut(6)
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut_7_Q : LUT6
generic map(
INIT => X"00FF001000FFEFFF"
)
port map (
I0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_760,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I3 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data(7),
I4 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_present_state(0),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_unpck_hbuf_data_out(7),
O => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut(7)
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut_8_Q : LUT6
generic map(
INIT => X"00FF001000FFEFFF"
)
port map (
I0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_760,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I3 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data(8),
I4 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_present_state(0),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_unpck_hbuf_data_out(8),
O => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut(8)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_ce_addr_last1 : LUT6
generic map(
INIT => X"202020202020A820"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd2_265,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd1_263,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_cnt_addrpart_we_0_0_261,
I3 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_present_state_FSM_FFd1_309,
I4 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd1_114,
I5 => RESET,
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_ce_addr_last
);
IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut_9_Q : LUT6
generic map(
INIT => X"00FF001000FFEFFF"
)
port map (
I0 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_760,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I3 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_cnt_data(9),
I4 => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_present_state(0),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_unpck_hbuf_data_out(9),
O => IB_ENDPOINT_I_U_read_ctrl_DATA_REORDER_NO_U_align_unit_fake_Mcount_cnt_data_lut(9)
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Result_3_1 : LUT6
generic map(
INIT => X"6C6CCC6CCCCCC9CC"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
I1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
I2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(1),
I3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_DATA_DST_RDY1_FRB_763,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_760,
I5 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
O => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Result(3)
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_CNT_ADDR_CE1 : LUT5
generic map(
INIT => X"21202122"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_DATA_DST_RDY1_FRB_763,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_760,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd1_758,
I3 => RD_SRC_RDY,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cmp_empty,
O => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr_ce
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd1_In : LUT6
generic map(
INIT => X"8C8C8C8C8D8C8C8C"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_760,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd1_758,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_DATA_DST_RDY1_FRB_763,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(3),
I4 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(2),
I5 => N5,
O => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd1_In_759
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_In1 : LUT5
generic map(
INIT => X"C5C4C4C4"
)
port map (
I0 => RD_SRC_RDY,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_760,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd1_758,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cmp_empty,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_DATA_DST_RDY1_FRB_763,
O => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd2_In
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_9_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_9_0_909,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(9),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_9_1_910,
O => IB_ENDPOINT_I_cpl_data(9)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_8_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_8_0_907,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(8),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_8_1_908,
O => IB_ENDPOINT_I_cpl_data(8)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_7_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_7_0_905,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(7),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_7_1_906,
O => IB_ENDPOINT_I_cpl_data(7)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_63_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_63_0_897,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(63),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_63_1_898,
O => IB_ENDPOINT_I_cpl_data(63)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_62_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_62_0_895,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(62),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_62_1_896,
O => IB_ENDPOINT_I_cpl_data(62)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_61_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_61_0_893,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(61),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_61_1_894,
O => IB_ENDPOINT_I_cpl_data(61)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_60_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_60_0_891,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(60),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_60_1_892,
O => IB_ENDPOINT_I_cpl_data(60)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_6_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_6_0_903,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(6),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_6_1_904,
O => IB_ENDPOINT_I_cpl_data(6)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_59_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_59_0_887,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(59),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_59_1_888,
O => IB_ENDPOINT_I_cpl_data(59)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_58_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_58_0_885,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(58),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_58_1_886,
O => IB_ENDPOINT_I_cpl_data(58)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_57_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_57_0_883,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(57),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_57_1_884,
O => IB_ENDPOINT_I_cpl_data(57)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_56_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_56_0_881,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(56),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_56_1_882,
O => IB_ENDPOINT_I_cpl_data(56)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_55_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_55_0_879,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(55),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_55_1_880,
O => IB_ENDPOINT_I_cpl_data(55)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_54_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_54_0_877,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(54),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_54_1_878,
O => IB_ENDPOINT_I_cpl_data(54)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_53_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_53_0_875,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(53),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_53_1_876,
O => IB_ENDPOINT_I_cpl_data(53)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_52_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_52_0_873,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(52),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_52_1_874,
O => IB_ENDPOINT_I_cpl_data(52)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_51_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_51_0_871,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(51),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_51_1_872,
O => IB_ENDPOINT_I_cpl_data(51)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_50_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_50_0_869,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(50),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_50_1_870,
O => IB_ENDPOINT_I_cpl_data(50)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_5_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_5_0_889,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(5),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_5_1_890,
O => IB_ENDPOINT_I_cpl_data(5)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_49_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_49_0_865,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(49),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_49_1_866,
O => IB_ENDPOINT_I_cpl_data(49)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_48_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_48_0_863,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(48),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_48_1_864,
O => IB_ENDPOINT_I_cpl_data(48)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_47_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_47_0_861,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(47),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_47_1_862,
O => IB_ENDPOINT_I_cpl_data(47)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_46_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_46_0_859,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(46),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_46_1_860,
O => IB_ENDPOINT_I_cpl_data(46)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_45_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_45_0_857,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(45),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_45_1_858,
O => IB_ENDPOINT_I_cpl_data(45)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_44_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_44_0_855,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(44),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_44_1_856,
O => IB_ENDPOINT_I_cpl_data(44)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_43_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_43_0_853,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(43),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_43_1_854,
O => IB_ENDPOINT_I_cpl_data(43)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_42_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_42_0_851,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(42),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_42_1_852,
O => IB_ENDPOINT_I_cpl_data(42)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_41_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_41_0_849,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(41),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_41_1_850,
O => IB_ENDPOINT_I_cpl_data(41)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_40_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_40_0_847,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(40),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_40_1_848,
O => IB_ENDPOINT_I_cpl_data(40)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_4_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_4_0_867,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(4),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_4_1_868,
O => IB_ENDPOINT_I_cpl_data(4)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_39_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_39_0_843,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(39),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_39_1_844,
O => IB_ENDPOINT_I_cpl_data(39)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_38_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_38_0_841,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(38),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_38_1_842,
O => IB_ENDPOINT_I_cpl_data(38)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_37_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_37_0_839,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(37),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_37_1_840,
O => IB_ENDPOINT_I_cpl_data(37)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_36_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_36_0_837,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(36),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_36_1_838,
O => IB_ENDPOINT_I_cpl_data(36)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_35_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_35_0_835,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(35),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_35_1_836,
O => IB_ENDPOINT_I_cpl_data(35)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_34_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_34_0_833,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(34),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_34_1_834,
O => IB_ENDPOINT_I_cpl_data(34)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_33_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_33_0_831,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(33),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_33_1_832,
O => IB_ENDPOINT_I_cpl_data(33)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_32_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_32_0_829,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(32),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_32_1_830,
O => IB_ENDPOINT_I_cpl_data(32)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_31_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_31_0_827,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(31),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_31_1_828,
O => IB_ENDPOINT_I_cpl_data(31)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_30_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_30_0_825,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(30),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_30_1_826,
O => IB_ENDPOINT_I_cpl_data(30)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_3_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_3_0_845,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(3),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_3_1_846,
O => IB_ENDPOINT_I_cpl_data(3)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_29_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_29_0_821,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(29),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_29_1_822,
O => IB_ENDPOINT_I_cpl_data(29)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_28_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_28_0_819,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(28),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_28_1_820,
O => IB_ENDPOINT_I_cpl_data(28)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_27_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_27_0_817,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(27),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_27_1_818,
O => IB_ENDPOINT_I_cpl_data(27)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_26_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_26_0_815,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(26),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_26_1_816,
O => IB_ENDPOINT_I_cpl_data(26)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_25_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_25_0_813,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(25),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_25_1_814,
O => IB_ENDPOINT_I_cpl_data(25)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_24_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_24_0_811,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(24),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_24_1_812,
O => IB_ENDPOINT_I_cpl_data(24)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_23_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_23_0_809,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(23),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_23_1_810,
O => IB_ENDPOINT_I_cpl_data(23)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_22_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_22_0_807,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(22),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_22_1_808,
O => IB_ENDPOINT_I_cpl_data(22)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_21_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_21_0_805,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(21),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_21_1_806,
O => IB_ENDPOINT_I_cpl_data(21)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_20_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_20_0_803,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(20),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_20_1_804,
O => IB_ENDPOINT_I_cpl_data(20)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_2_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_2_0_823,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(2),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_2_1_824,
O => IB_ENDPOINT_I_cpl_data(2)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_19_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_19_0_799,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(19),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_19_1_800,
O => IB_ENDPOINT_I_cpl_data(19)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_18_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_18_0_797,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(18),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_18_1_798,
O => IB_ENDPOINT_I_cpl_data(18)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_17_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_17_0_795,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(17),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_17_1_796,
O => IB_ENDPOINT_I_cpl_data(17)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_16_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_16_0_793,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(16),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_16_1_794,
O => IB_ENDPOINT_I_cpl_data(16)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_15_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_15_0_791,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(15),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_15_1_792,
O => IB_ENDPOINT_I_cpl_data(15)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_14_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_14_0_789,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(14),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_14_1_790,
O => IB_ENDPOINT_I_cpl_data(14)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_13_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_13_0_787,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(13),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_13_1_788,
O => IB_ENDPOINT_I_cpl_data(13)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_12_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_12_0_785,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(12),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_12_1_786,
O => IB_ENDPOINT_I_cpl_data(12)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_11_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_11_0_783,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(11),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_11_1_784,
O => IB_ENDPOINT_I_cpl_data(11)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_10_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_10_0_781,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(10),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_10_1_782,
O => IB_ENDPOINT_I_cpl_data(10)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_1_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_1_0_801,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(1),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_1_1_802,
O => IB_ENDPOINT_I_cpl_data(1)
);
IB_ENDPOINT_I_U_read_ctrl_OUT_DATA_0_1 : LUT6
generic map(
INIT => X"FFFE1110EFEE0100"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_cpl_fsm_present_state(0),
I1 => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd2_1271,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_cnt_addr_0_0,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_0_0_779,
I4 => IB_ENDPOINT_I_U_read_ctrl_align_in_data(0),
I5 => IB_ENDPOINT_I_U_read_ctrl_U_pck_hbuf_U_ib_endpoint_pck_hbuf_sh_fifo_shreg_0_1_780,
O => IB_ENDPOINT_I_cpl_data(0)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_fsm_addrpart_we1 : LUT6
generic map(
INIT => X"555D555D00040000"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd1_263,
I1 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_present_state_FSM_FFd1_309,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd1_114,
I3 => RESET,
I4 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_addr_start_aux,
I5 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd2_265,
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addrpart_we
);
IB_ENDPOINT_I_U_write_ctrl_BE_GEN_YES_U_be_gen_be_mux_3_Q : LUT6
generic map(
INIT => X"5444444555555555"
)
port map (
I0 => N19,
I1 => IB_ENDPOINT_I_U_write_ctrl_BE_GEN_YES_U_be_gen_last_align(2),
I2 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_4,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32(0),
I4 => IB_ENDPOINT_I_U_write_ctrl_BE_GEN_YES_U_be_gen_Madd_last_align_lut(1),
I5 => NlwRenamedSig_OI_WR_EOF,
O => WR_BE(3)
);
IB_ENDPOINT_I_U_write_ctrl_BE_GEN_YES_U_be_gen_be_mux_5_Q : LUT6
generic map(
INIT => X"0068008900FF00FF"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_BE_GEN_YES_U_be_gen_last_align(2),
I1 => IB_ENDPOINT_I_U_write_ctrl_BE_GEN_YES_U_be_gen_Madd_last_align_lut(1),
I2 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32(0),
I3 => N21,
I4 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_4,
I5 => NlwRenamedSig_OI_WR_EOF,
O => WR_BE(5)
);
IB_ENDPOINT_I_U_write_ctrl_BE_GEN_YES_U_be_gen_be_mux_2_Q : LUT6
generic map(
INIT => X"5555444155555555"
)
port map (
I0 => N23,
I1 => IB_ENDPOINT_I_U_write_ctrl_BE_GEN_YES_U_be_gen_Madd_last_align_lut(1),
I2 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_4,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32(0),
I4 => IB_ENDPOINT_I_U_write_ctrl_BE_GEN_YES_U_be_gen_last_align(2),
I5 => NlwRenamedSig_OI_WR_EOF,
O => WR_BE(2)
);
IB_ENDPOINT_I_U_write_ctrl_BE_GEN_YES_U_be_gen_be_mux_6_Q : LUT6
generic map(
INIT => X"000060810000FFFF"
)
port map (
I0 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_4,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32(0),
I2 => IB_ENDPOINT_I_U_write_ctrl_BE_GEN_YES_U_be_gen_Madd_last_align_lut(1),
I3 => IB_ENDPOINT_I_U_write_ctrl_BE_GEN_YES_U_be_gen_last_align(2),
I4 => N25,
I5 => NlwRenamedSig_OI_WR_EOF,
O => WR_BE(6)
);
IB_ENDPOINT_I_U_write_ctrl_BE_GEN_YES_U_be_gen_be_mux_4_Q : LUT6
generic map(
INIT => X"006A00A900FF00FF"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_BE_GEN_YES_U_be_gen_last_align(2),
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32(0),
I2 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_4,
I3 => N27,
I4 => IB_ENDPOINT_I_U_write_ctrl_BE_GEN_YES_U_be_gen_Madd_last_align_lut(1),
I5 => NlwRenamedSig_OI_WR_EOF,
O => WR_BE(4)
);
IB_ENDPOINT_I_U_read_ctrl_BE_GEN_YES_U_be_gen_be_mux_3_Q : LUT6
generic map(
INIT => X"00FFFFFF00818181"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(0),
I1 => IB_ENDPOINT_I_U_read_ctrl_BE_GEN_YES_U_be_gen_Madd_last_align_lut(1),
I2 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_4,
I3 => NlwRenamedSig_OI_RD_SOF,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(2),
I5 => N38,
O => RD_BE(3)
);
IB_ENDPOINT_I_U_read_ctrl_BE_GEN_YES_U_be_gen_be_mux_0_1 : LUT5
generic map(
INIT => X"DDDDDDDF"
)
port map (
I0 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd2,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd1_912,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(0),
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(1),
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(2),
O => RD_BE(0)
);
IB_ENDPOINT_I_U_write_ctrl_BE_GEN_YES_U_be_gen_be_mux_0_1 : LUT5
generic map(
INIT => X"DDDDDDDF"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd2_1477,
I1 => IB_ENDPOINT_I_wr_src_rdy_n,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32(0),
I3 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32(1),
I4 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32(2),
O => WR_BE(0)
);
IB_ENDPOINT_I_U_write_ctrl_BE_GEN_YES_U_be_gen_be_mux_3_SW0 : LUT3
generic map(
INIT => X"08"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32(2),
I1 => IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd2_1477,
I2 => IB_ENDPOINT_I_wr_src_rdy_n,
O => N19
);
IB_ENDPOINT_I_U_write_ctrl_BE_GEN_YES_U_be_gen_be_mux_5_SW0 : LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32(2),
I1 => IB_ENDPOINT_I_wr_src_rdy_n,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd2_1477,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32(1),
O => N21
);
IB_ENDPOINT_I_U_write_ctrl_BE_GEN_YES_U_be_gen_be_mux_2_SW0 : LUT5
generic map(
INIT => X"22202020"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd2_1477,
I1 => IB_ENDPOINT_I_wr_src_rdy_n,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32(2),
I3 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32(1),
I4 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32(0),
O => N23
);
IB_ENDPOINT_I_U_write_ctrl_BE_GEN_YES_U_be_gen_be_mux_6_SW0 : LUT5
generic map(
INIT => X"00008000"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32(1),
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32(0),
I2 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32(2),
I3 => IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd2_1477,
I4 => IB_ENDPOINT_I_wr_src_rdy_n,
O => N25
);
IB_ENDPOINT_I_U_write_ctrl_BE_GEN_YES_U_be_gen_be_mux_4_SW0 : LUT5
generic map(
INIT => X"20202000"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd2_1477,
I1 => IB_ENDPOINT_I_wr_src_rdy_n,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32(2),
I3 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32(1),
I4 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32(0),
O => N27
);
IB_ENDPOINT_I_U_read_ctrl_BE_GEN_YES_U_be_gen_be_mux_3_SW0 : LUT5
generic map(
INIT => X"FF57FFFF"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_cmp_eq0000_916,
I1 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd2,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd1_912,
I3 => IB_ENDPOINT_I_U_read_ctrl_BE_GEN_YES_U_be_gen_last_align(2),
I4 => RD_ARDY_ACCEPT,
O => N38
);
IB_ENDPOINT_I_U_read_ctrl_BE_GEN_YES_U_be_gen_be_mux_5_Q : LUT6
generic map(
INIT => X"AFAF23AFAFAFAFAF"
)
port map (
I0 => N40,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(1),
I2 => NlwRenamedSig_OI_RD_EOF,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(2),
I4 => IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd1_912,
I5 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_read_fsm_present_state_FSM_FFd2,
O => RD_BE(5)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_fsm_addr_we1 : LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => RESET,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_fsm_u_present_state_FSM_FFd1_114,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd1_263,
I3 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_present_state_FSM_FFd2_265,
I4 => IB_ENDPOINT_I_U_down_buf_INPUT_BUFFER_GEN1_U_input_pipe_PIPE_present_state_FSM_FFd1_309,
I5 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_addr_start_aux,
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr_we
);
IB_ENDPOINT_I_U_write_ctrl_BE_GEN_YES_U_be_gen_be_mux_7_1 : LUT6
generic map(
INIT => X"01080801FFFFFFFF"
)
port map (
I0 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_4,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32(0),
I2 => IB_ENDPOINT_I_U_write_ctrl_BE_GEN_YES_U_be_gen_last_align(2),
I3 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_5,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32(1),
I5 => NlwRenamedSig_OI_WR_EOF,
O => WR_BE(7)
);
IB_ENDPOINT_I_U_read_ctrl_BE_GEN_YES_U_be_gen_be_mux_7_1 : LUT6
generic map(
INIT => X"01080801FFFFFFFF"
)
port map (
I0 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_4,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(0),
I2 => IB_ENDPOINT_I_U_read_ctrl_BE_GEN_YES_U_be_gen_last_align(2),
I3 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_5,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(1),
I5 => NlwRenamedSig_OI_RD_EOF,
O => RD_BE(7)
);
IB_ENDPOINT_I_U_read_ctrl_BE_GEN_YES_U_be_gen_be_mux_1_SW0 : LUT4
generic map(
INIT => X"9FF9"
)
port map (
I0 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_4,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(0),
I2 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_5,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(1),
O => N36
);
IB_ENDPOINT_I_U_read_ctrl_BE_GEN_YES_U_be_gen_Madd_last_align_xor_2_11 : LUT6
generic map(
INIT => X"9996969696666666"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(2),
I1 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_6,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(1),
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(0),
I4 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_4,
I5 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_5,
O => IB_ENDPOINT_I_U_read_ctrl_BE_GEN_YES_U_be_gen_last_align(2)
);
IB_ENDPOINT_I_U_write_ctrl_BE_GEN_YES_U_be_gen_Madd_last_align_xor_2_11 : LUT6
generic map(
INIT => X"9996969696666666"
)
port map (
I0 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_6,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32(2),
I2 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_5,
I3 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_4,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32(0),
I5 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32(1),
O => IB_ENDPOINT_I_U_write_ctrl_BE_GEN_YES_U_be_gen_last_align(2)
);
IB_ENDPOINT_I_U_write_ctrl_BE_GEN_YES_U_be_gen_be_mux_1_Q : LUT6
generic map(
INIT => X"CCCCCCFF04CC04FF"
)
port map (
I0 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32(2),
I1 => N801,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32(1),
I3 => IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd2_1477,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_write_fsm_present_state_FSM_FFd1_1475,
I5 => IB_ENDPOINT_I_wr_src_rdy_n,
O => WR_BE(1)
);
IB_ENDPOINT_I_U_read_ctrl_BE_GEN_YES_U_be_gen_be_mux_5_SW0 : LUT6
generic map(
INIT => X"8778066006601EE1"
)
port map (
I0 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_5,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(1),
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(2),
I3 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_6,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(0),
I5 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_4,
O => N40
);
IB_ENDPOINT_I_U_read_ctrl_BE_GEN_YES_U_be_gen_be_mux_2_SW0 : LUT6
generic map(
INIT => X"FCE93F7F3F7FFCE9"
)
port map (
I0 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_4,
I1 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_5,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(1),
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(0),
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(2),
I5 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_6,
O => N42
);
IB_ENDPOINT_I_U_read_ctrl_BE_GEN_YES_U_be_gen_be_mux_4_SW0 : LUT6
generic map(
INIT => X"C33C3C3C963C3C69"
)
port map (
I0 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_4,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(2),
I2 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_6,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(1),
I4 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_5,
I5 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(0),
O => N46
);
IB_ENDPOINT_I_U_write_ctrl_BE_GEN_YES_U_be_gen_be_mux_1_SW1 : LUT6
generic map(
INIT => X"FFFFFFF6FFF6FFFF"
)
port map (
I0 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_5,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32(1),
I2 => IB_ENDPOINT_I_U_write_ctrl_BE_GEN_YES_U_be_gen_last_align(2),
I3 => IB_ENDPOINT_I_wr_eof_n,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32(0),
I5 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_length_0_4,
O => N801
);
IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_rstpot1 : LUT6
generic map(
INIT => X"EEE4EEEE44E44444"
)
port map (
I0 => N395,
I1 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_BRB1_1438,
I2 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_BRB2_1439,
I3 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB3_1403,
I4 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_29_BRB4_1404,
I5 => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_BRB5_1440,
O => IB_ENDPOINT_I_U_write_ctrl_U_unpacker_reg_addr32_31_rstpot_1441
);
IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_rstpot1 : LUT5
generic map(
INIT => X"FDA87520"
)
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB0_1135,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB1_1136,
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB2_1137,
I3 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB3_1138,
I4 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_BRB4_1139,
O => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64_31_rstpot_1140
);
IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Result_0_1_INV_0 : INV
port map (
I => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_cnt_addr(0),
O => IB_ENDPOINT_I_U_read_ctrl_U_cpl_buf_U_buf_U_ib_buffer_sh_fifo_Result(0)
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_cnt_addrpart_we_0_0_not00001_INV_0 : INV
port map (
I => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_cnt_addrpart_we_0_0_261,
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_fetch_marker_cnt_addrpart_we_0_0_not0000
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_const_limit_cnt_sel_0_0_not00001_INV_0 : INV
port map (
I => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_const_limit_cnt_sel_0_0_110,
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_const_limit_cnt_sel_0_0_not0000
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_const_base_cnt_sel_0_0_not00001_INV_0 : INV
port map (
I => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_const_base_cnt_sel_0_0_108,
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_addr_const_base_cnt_sel_0_0_not0000
);
IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_OUT_SRC_RDY_N1_INV_0 : INV
port map (
I => IB_ENDPOINT_I_U_up_buf_OUTPUT_BUFFER_GEN1_U_output_pipe_PIPE_present_state_FSM_FFd1_1269,
O => IB_UP_SRC_RDY_N
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_not0001 : MUXF7
port map (
I0 => N803,
I1 => N804,
S => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_DROP,
O => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_not0001_289
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_not0001_F : LUT6
generic map(
INIT => X"FFFF0020FFFF0070"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_65_1_246,
I2 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ,
I3 => N195,
I4 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr_next,
I5 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_65_0_245,
O => N803
);
IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_endpoint_addr_dec_req_buf_OUT_REQ_not0001_G : LUT6
generic map(
INIT => X"FFFF0002FFFF0007"
)
port map (
I0 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_cnt_addr_0_0_112,
I1 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_65_1_246,
I2 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd2_317,
I3 => IB_ENDPOINT_I_U_down_buf_U_down_fsm_present_state_FSM_FFd1_315,
I4 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_addr_next,
I5 => IB_ENDPOINT_I_U_down_buf_ADDRESS_DECODER_GEN_YES_U_addr_dec_U_ib_buffer_sh_U_ib_buffer_sh_fifo_shreg_65_0_245,
O => N804
);
IB_ENDPOINT_I_U_read_ctrl_BE_GEN_YES_U_be_gen_be_mux_6_1 : LUT6
generic map(
INIT => X"171D3515575D75D5"
)
port map (
I0 => NlwRenamedSig_OI_RD_EOF,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(1),
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(2),
I3 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_5,
I4 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_6,
I5 => NlwRenamedSig_OI_RD_SOF,
O => IB_ENDPOINT_I_U_read_ctrl_BE_GEN_YES_U_be_gen_be_mux(6)
);
IB_ENDPOINT_I_U_read_ctrl_BE_GEN_YES_U_be_gen_be_mux_6_2 : LUT6
generic map(
INIT => X"06601881FFFFFFFF"
)
port map (
I0 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_5,
I1 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(1),
I2 => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(2),
I3 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_6,
I4 => NlwRenamedSig_OI_IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_length_0_4,
I5 => NlwRenamedSig_OI_RD_EOF,
O => IB_ENDPOINT_I_U_read_ctrl_BE_GEN_YES_U_be_gen_be_mux_6_1_700
);
IB_ENDPOINT_I_U_read_ctrl_BE_GEN_YES_U_be_gen_be_mux_6_f7 : MUXF7
port map (
I0 => IB_ENDPOINT_I_U_read_ctrl_BE_GEN_YES_U_be_gen_be_mux_6_1_700,
I1 => IB_ENDPOINT_I_U_read_ctrl_BE_GEN_YES_U_be_gen_be_mux(6),
S => IB_ENDPOINT_I_U_read_ctrl_U_unpacker_reg_addr64(0),
O => RD_BE(6)
);
end STRUCTURE;
| bsd-3-clause | d0b28c29a88d5fe041ee1d6df1e1e8c5 | 0.645037 | 2.415571 | false | false | false | false |
cnplab/blockmon | fw-combo/src/generator/comp/gen_fsm.vhd | 1 | 8,380 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- gen_fsm.vhd: FSM for generating fl packets
-- Copyright (C) 2009 CESNET
-- Author(s): Petr Kastovsky <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: gen_fsm.vhd 12117 2009-11-25 13:35:03Z kastovsky $
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.math_pack.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity GEN_FSM is
port(
-- global signals
CLK : in std_logic;
RESET : in std_logic;
-- input signals
START : in std_logic; -- start is set
PACKET_END : in std_logic; -- end of packet
TRANSMIT_END : in std_logic; -- end of transmission
DST_RDY : in std_logic; -- desrtination is ready
-- output signals
SOP : out std_logic;
EOP : out std_logic;
NEXT_DATA : out std_logic; -- get next data
NEXT_LEN : out std_logic; -- get next length
SRC_RDY : out std_logic; -- source is ready
STOPPED : out std_logic -- we are stopped
);
end entity GEN_FSM;
-- ----------------------------------------------------------------------------
-- Architecture declaration
-- ----------------------------------------------------------------------------
architecture full of GEN_FSM is
-- ------------------ Types declaration ------------------------------------
type t_state is ( S_STP, S_RUN, S_PS, S_PT, S_PE );
-- S_STP - stopped
-- S_RUN - running
-- S_PS - packet start
-- S_PT - packet transmission
-- S_PE - packet end
-- ------------------ Signals declaration ----------------------------------
signal present_state, next_state : t_state;
begin
-- --------------- Sync logic -------------------------------------------
sync_logic : process( CLK )
begin
if (CLK'event AND CLK = '1') then
if (RESET = '1') then
present_state <= S_STP;
else
present_state <= next_state;
end if;
end if;
end process sync_logic;
-- ------------------ Next state logic -------------------------------------
next_state_logic : process( present_state, START, PACKET_END, TRANSMIT_END,
DST_RDY)
begin
case (present_state) is
-- ---------------------------------------------
when S_STP =>
if (START = '1') then
next_state <= S_RUN;
else
next_state <= S_STP;
end if;
-- ---------------------------------------------
when S_RUN =>
if (DST_RDY = '1') then
next_state <= S_PS;
else
next_state <= S_RUN;
end if;
-- ---------------------------------------------
when S_PS =>
if (DST_RDY = '1') then
next_state <= S_PT;
else
next_state <= S_PS;
end if;
-- ---------------------------------------------
when S_PT =>
next_state <= S_PT;
if (DST_RDY = '1') then
if (PACKET_END = '1') then
if (START = '1') then
next_state <= S_PE;
else
next_state <= S_STP;
end if;
end if;
if (TRANSMIT_END = '1') then
next_state <= S_STP;
end if;
end if;
-- ---------------------------------------------
when S_PE =>
if (TRANSMIT_END = '1') then
next_state <= S_STP;
else
if (DST_RDY = '1') then
next_state <= S_PS;
else
next_state <= S_PE;
end if;
end if;
-- ---------------------------------------------
when others =>
next_state <= S_STP;
-- ---------------------------------------------
end case;
end process next_state_logic;
-- ------------------ Output logic -----------------------------------------
output_logic: process( present_state, START, PACKET_END, TRANSMIT_END,
DST_RDY)
begin
-- ---------------------------------------------
-- Initial values
-- no active signals
-- ---------------------------------------------
NEXT_DATA <= '0';
NEXT_LEN <= '0';
SRC_RDY <= '0';
STOPPED <= '0';
SOP <= '0';
EOP <= '0';
case (present_state) is
-- ---------------------------------------------
when S_STP =>
if (START = '0') then
STOPPED <= '1';
end if;
-- ---------------------------------------------
when S_RUN =>
SRC_RDY <= '1';
if (DST_RDY = '1') then
NEXT_DATA <= '1';
SOP <= '1';
end if;
-- ---------------------------------------------
when S_PS =>
SRC_RDY <= '1';
if (DST_RDY = '1') then
NEXT_DATA <= '1';
end if;
-- ---------------------------------------------
when S_PT =>
SRC_RDY <= '1';
if (DST_RDY = '1') then
NEXT_DATA <= '1';
if (PACKET_END = '1') then
EOP <= '1';
NEXT_LEN <= '1';
if (START = '0') then
STOPPED <= '1';
end if;
end if;
if (TRANSMIT_END = '1') then
STOPPED <= '1';
end if;
end if;
-- ---------------------------------------------
when S_PE =>
if (TRANSMIT_END = '1') then
STOPPED <= '1';
else
SRC_RDY <= '1';
if (DST_RDY = '1') then
NEXT_DATA <= '1';
SOP <= '1';
end if;
end if;
-- ---------------------------------------------
when others =>
null;
-- ---------------------------------------------
end case;
end process output_logic;
end architecture full;
| bsd-3-clause | ccf46818e405ecd52f9dd5a5e35b3660 | 0.415274 | 4.753261 | false | false | false | false |
ARC-Lab-UF/window_gen | src/ram.vhd | 2 | 5,170 | -- Copyright (c) University of Florida
--
-- This file is part of window_gen.
--
-- window_gen is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- window_gen is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with window_gen. If not, see <http://www.gnu.org/licenses/>.
-- Greg Stitt
-- University of Florida
-- Description:
-- The ram entity implements a ram with a standard 1-read port, 1-write port
-- interface. The ram is configurable in terms of data width (width of each
-- word), the address width, and the number of words. The ram has a write
-- enable for writes, but does not contain a read enable. Instead, the ram
-- reads from the read address every cycle.
--
-- The entity contains several different architectures that implement different
-- ram behaviors. e.g. synchronous reads, asynchronous reads, synchronoous
-- reads during writes.
--
-- Notes:
-- Asychronous reads are not supported by all FPGAs.
--
-------------------------------------------------------------------------------
-- Generics Description
-- word_width : The width in bits of a single word (required)
-- addr_width : The width in bits of an address, which also defines the
-- number of words (required)
-- num_words : The number of words in the memory. This generic will
-- usually be 2**addr_width, but the entity supports
-- non-powers of 2 (required)
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Port Description:
-- clk : clock input
-- wen : write enable (active high)
-- waddr : write address
-- wdata : write data
-- raddr : read address
-- rdata : read data
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ram is
generic (
num_words : positive;
word_width : positive;
addr_width : positive
);
port (
clk : in std_logic;
-- write port
wen : in std_logic;
waddr : in std_logic_vector(addr_width-1 downto 0);
wdata : in std_logic_vector(word_width-1 downto 0);
-- read port
raddr : in std_logic_vector(addr_width-1 downto 0);
rdata : out std_logic_vector(word_width-1 downto 0)
);
end entity;
-- This architecture uses asynchronous reads that return the read data in the
-- same cycle.
architecture ASYNC_READ of ram is
type memory_type is array (natural range <>) of std_logic_vector(word_width-1 downto 0);
signal memory : memory_type(num_words-1 downto 0) := (others => (others => '0'));
begin
process(clk)
begin
if clk'event and clk = '1' then
if wen = '1' then
memory(to_integer(unsigned(waddr))) <= wdata;
end if;
end if;
end process;
rdata <= memory(to_integer(unsigned(raddr)));
end ASYNC_READ;
-- This architecture uses synchronous reads with a one-cycle delay. In the case
-- of reading and writing to the same address, the read returns the new data
-- that was written.
architecture SYNC_READ_DURING_WRITE of ram is
type memory_type is array (natural range <>) of std_logic_vector(word_width-1 downto 0);
signal memory : memory_type(num_words-1 downto 0) := (others => (others => '0'));
signal raddr_reg : std_logic_vector(addr_width-1 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
if wen = '1' then
memory(to_integer(unsigned(waddr))) <= wdata;
end if;
raddr_reg <= raddr;
end if;
end process;
rdata <= memory(to_integer(unsigned(raddr_reg)));
end SYNC_READ_DURING_WRITE;
-- This architecture uses synchronous reads with a one-cycle delay. In the case
-- of reading and writing to the same address, the read returns the data at
-- the address before the write.
architecture SYNC_READ of ram is
type memory_type is array (natural range <>) of std_logic_vector(word_width-1 downto 0);
signal memory : memory_type(num_words-1 downto 0) := (others => (others => '0'));
begin
process(clk)
begin
if clk'event and clk = '1' then
if wen = '1' then
memory(to_integer(unsigned(waddr))) <= wdata;
end if;
rdata <= memory(to_integer(unsigned(raddr)));
end if;
end process;
end SYNC_READ;
| gpl-3.0 | 9dd9b3cb526521e5797a9a38bbc97b84 | 0.58472 | 4.048551 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/altera/memory/src/dpRamOpenmac-rtl-a.vhd | 3 | 3,998 | --! @file dpRam-bhv-a.vhd
--
--! @brief Dual Port Ram for openMAC Register Transfer Level Architecture
--
--! @details This is the DPRAM intended for synthesis on Altera platforms only.
--! It is specific for the openMAC descriptor DPRAM which require
--! simultaneous write/read from the same address.
--!
--! Timing as follows [clk-cycles]: write=0 / read=1
--
-------------------------------------------------------------------------------
-- Architecture : rtl
-------------------------------------------------------------------------------
--
-- (c) B&R, 2015
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! use altera_mf library
library altera_mf;
use altera_mf.altera_mf_components.all;
architecture rtl of dpRamOpenmac is
begin
altsyncram_component : altsyncram
generic map (
operation_mode => "BIDIR_DUAL_PORT",
intended_device_family => "Cyclone IV",
init_file => gInitFile,
numwords_a => gNumberOfWords,
numwords_b => gNumberOfWords,
widthad_a => logDualis(gNumberOfWords),
widthad_b => logDualis(gNumberOfWords),
width_a => gWordWidth,
width_b => gWordWidth,
width_byteena_a => gWordWidth/8,
width_byteena_b => gWordWidth/8,
read_during_write_mode_mixed_ports => "OLD_DATA"
)
port map (
clock0 => iClk_A,
clocken0 => iEnable_A,
wren_a => iWriteEnable_A,
address_a => iAddress_A,
byteena_a => iByteenable_A,
data_a => iWritedata_A,
q_a => oReaddata_A,
clock1 => iClk_B,
clocken1 => iEnable_B,
wren_b => iWriteEnable_B,
address_b => iAddress_B,
byteena_b => iByteenable_B,
data_b => iWritedata_B,
q_b => oReaddata_B
);
end architecture rtl;
| gpl-2.0 | 1b6135edf4abc554258e7a569ea2aa35 | 0.555278 | 4.89951 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/openmac/src/phyMgmt-rtl-ea.vhd | 3 | 9,420 | -------------------------------------------------------------------------------
--! @file phyMgmt-rtl-ea.vhd
--
--! @brief OpenMAC phy management module
--
--! @details This is the openMAC phy management module to configure the connected
--! phys via SMI (= serial management interface).
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity phyMgmt is
port (
--! Reset
iRst : in std_logic;
--! Clock
iClk : in std_logic;
--! Address (word addresses)
iAddress : in std_logic_vector(3 downto 1);
--! Select
iSelect : in std_logic;
--! Byteenale (low-active)
inByteenable : in std_logic_vector(1 downto 0);
--! Write (low-active)
inWrite : in std_logic;
--! Writedata
iWritedata : in std_logic_vector(15 downto 0);
--! Readdata
oReaddata : out std_logic_vector(15 downto 0);
--! SMI Clock
oSmiClk : out std_logic;
--! SMI data input
iSmiDataIn : in std_logic;
--! SMI data output
oSmiDataOut : out std_logic;
--! SMI data output enable
oSmiDataOutEnable : out std_logic;
--! Phy reset (low-active)
onPhyReset : out std_logic
);
end entity phyMgmt;
architecture rtl of phyMgmt is
--! This is the shift register to serialize write and read data.
signal shift_reg : std_logic_vector(31 downto 0);
--! This is the generated SMI clock.
signal smiClk : std_logic;
--! This is the clock divider vector to generate smiClk.
signal clkDivider : std_logic_vector(4 downto 0);
--! This alias triggers shifting the shift register.
alias doShift : std_logic is clkDivider(clkDivider'high);
--! This is the bit counter for serializing.
signal bit_cnt : std_logic_vector(2 downto 0);
--! This is the byte counter for serializing.
signal byte_cnt : std_logic_vector(2 downto 0);
--! This flag signalizes activity.
signal runActive : std_logic;
--! This flag signalizes a busy shift register.
signal shiftBusy : std_logic;
--! This signal is used to control the phy reset (low active).
signal nPhyReset : std_logic;
--! This is the internal SMI data output.
signal smiDataOut : std_logic;
--! This is the internal SMI data output enable.
signal smiDataOutEnable : std_logic;
begin
---------------------------------------------------------------------------
-- Assign outputs
---------------------------------------------------------------------------
oSmiClk <= smiClk;
oSmiDataOut <= smiDataOut;
oSmiDataOutEnable <= smiDataOutEnable;
onPhyReset <= nPhyReset;
--! This process assigns the readdata vector.
ASSIGN_READDATA : process (
nPhyReset,
shiftBusy,
shift_reg,
iAddress
)
begin
-- default is zero
oReaddata <= (others => cInactivated);
if iAddress(1) = cInactivated then
oReaddata(7) <= nPhyReset;
oReaddata(0) <= shiftBusy;
else
oReaddata <= shift_reg(15 downto 0);
end if;
end process ASSIGN_READDATA;
--! This process generates the SMI signals and assigns memory mapped writes.
doSMI : process (iRst, iClk)
begin
if iRst = cActivated then
smiClk <= cInactivated;
runActive <= cInactivated;
shiftBusy <= cInactivated;
smiDataOutEnable <= cActivated;
smiDataOut <= cActivated;
nPhyReset <= cnActivated;
bit_cnt <= (others => cInactivated);
byte_cnt <= (others => cInactivated);
shift_reg <= x"0000abcd";
clkDivider <= (others => cInactivated);
elsif rising_edge(iClk) then
if doShift = cActivated then
clkDivider <= std_logic_vector(to_unsigned(8, clkDivider'length) + 1);
smiClk <= not smiClk;
else
clkDivider <= std_logic_vector(unsigned(clkDivider) - 1);
end if;
if (iSelect = cActivated and inWrite = cnActivated and shiftBusy = cInactivated and
iAddress(2) = cActivated and inByteenable(0) = cnActivated) then
nPhyReset <= iWritedata(7);
end if;
if (iSelect = cActivated and inWrite = cnActivated and shiftBusy = cInactivated and
iAddress(2) = cInactivated) then
if iAddress(1) = cInactivated then
if inByteenable(1) = cnActivated then
shift_reg(31 downto 24) <= iWritedata(15 downto 8);
end if;
if inByteenable(0) = cnActivated then
shift_reg(23 downto 16) <= iWritedata(7 downto 0);
shiftBusy <= cActivated;
end if;
else
if inByteenable(1) = cnActivated then
shift_reg(15 downto 8) <= iWritedata(15 downto 8);
end if;
if inByteenable(0) = cnActivated then
shift_reg(7 downto 0) <= iWritedata(7 downto 0);
end if;
end if;
else
if doShift = cActivated and smiClk = cActivated then
if runActive = cInactivated and shiftBusy = cActivated then
runActive <= cActivated;
byte_cnt <= "111";
bit_cnt <= "111";
else
if byte_cnt(2) = cInactivated and shiftBusy = cActivated then
smiDataOut <= shift_reg(31);
shift_reg <= shift_reg(30 downto 0) & iSmiDataIn;
end if;
bit_cnt <= std_logic_vector(unsigned(bit_cnt) - 1);
if bit_cnt = std_logic_vector(to_unsigned(0, bit_cnt'length)) then
byte_cnt <= std_logic_vector(unsigned(byte_cnt) - 1);
if byte_cnt = std_logic_vector(to_unsigned(0, byte_cnt'length)) then
shiftBusy <= cInactivated;
runActive <= cInactivated;
end if;
end if;
if (byte_cnt = std_logic_vector(to_unsigned(2, byte_cnt'length)) and
bit_cnt = std_logic_vector(to_unsigned(1, bit_cnt'length)) and
shift_reg(31) = cInactivated) then
smiDataOutEnable <= cInactivated;
end if;
end if;
if shiftBusy = cInactivated or runActive = cInactivated then
smiDataOut <= cActivated;
smiDataOutEnable <= cActivated;
end if;
end if;
end if;
end if;
end process doSMI;
end rtl; | gpl-2.0 | 47b4d7eafa36a5211b71529a1dcefdd3 | 0.524204 | 5.042827 | false | false | false | false |
chiggs/oc_mkjpeg | design/BufFifo/BUF_FIFO.vhd | 1 | 16,211 | -------------------------------------------------------------------------------
-- File Name : BUF_FIFO.vhd
--
-- Project : JPEG_ENC
--
-- Module : BUF_FIFO
--
-- Content : Input FIFO Buffer
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090311: (MK): Initial Creation.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity BUF_FIFO is
port
(
CLK : in std_logic;
RST : in std_logic;
-- HOST PROG
img_size_x : in std_logic_vector(15 downto 0);
img_size_y : in std_logic_vector(15 downto 0);
sof : in std_logic;
-- HOST DATA
iram_wren : in std_logic;
iram_wdata : in std_logic_vector(C_PIXEL_BITS-1 downto 0);
fifo_almost_full : out std_logic;
-- FDCT
fdct_fifo_rd : in std_logic;
fdct_fifo_q : out std_logic_vector(23 downto 0);
fdct_fifo_hf_full : out std_logic
);
end entity BUF_FIFO;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of BUF_FIFO is
--constant C_NUM_LINES : integer := 8 + C_EXTRA_LINES;
-- No Exstra Lines
constant C_NUM_LINES : integer := 8;
signal pixel_cnt : unsigned(15 downto 0);
signal line_cnt : unsigned(15 downto 0);
--signal ramq : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);
signal q : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);
--signal ramd : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);
signal ram_data : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);
signal wr_ptr : unsigned(log2(C_MAX_LINE_WIDTH*C_NUM_LINES)-1 downto 0);
signal ram_write : STD_LOGIC;
signal rd_ptr : unsigned(log2(C_MAX_LINE_WIDTH*C_NUM_LINES)-1 downto 0);
signal wr_addr : unsigned(log2(C_MAX_LINE_WIDTH)-1 downto 0);
signal we : STD_LOGIC;
signal rd_addr : unsigned(log2(C_MAX_LINE_WIDTH)-1 downto 0);
signal data_out : STD_LOGIC_VECTOR(15 downto 0);
--signal ramd : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);
signal data_in : unsigned(15 downto 0);
signal wr_addr2 : unsigned(log2(C_MAX_LINE_WIDTH)-1 downto 0);
signal we2 : STD_LOGIC;
signal rd_addr2 : unsigned(log2(C_MAX_LINE_WIDTH)-1 downto 0);
signal data_out2 : STD_LOGIC_VECTOR(15 downto 0);
--signal ramd : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);
signal data_in2 : unsigned(15 downto 0);
signal pix_inblk_cnt : unsigned(3 downto 0);
signal pix_inblk_cnt_d1 : unsigned(3 downto 0);
signal line_inblk_cnt : unsigned(2 downto 0);
signal read_block_cnt : unsigned(12 downto 0);
signal read_block_cnt_d1 : unsigned(12 downto 0);
signal write_block_cnt : unsigned(12 downto 0);
signal ramraddr_int : unsigned(16+log2(C_NUM_LINES)-1 downto 0);
signal raddr_base_line : unsigned(16+log2(C_NUM_LINES)-1 downto 0);
signal raddr_tmp : unsigned(15 downto 0);
--signal ramwaddr_d1 : unsigned(ramwaddr'range);
signal line_lock : unsigned(log2(C_NUM_LINES)-1 downto 0);
signal memwr_line_cnt : unsigned(log2(C_NUM_LINES)-1 downto 0);
signal memrd_offs_cnt : unsigned(log2(C_NUM_LINES)-1+1 downto 0);
signal memrd_line : unsigned(log2(C_NUM_LINES)-1 downto 0);
signal wr_line_idx : unsigned(15 downto 0);
signal rd_line_idx : unsigned(15 downto 0);
signal image_write_end : std_logic;
signal result :std_logic_vector(31 downto 0);
signal threshold :std_logic_vector(31 downto 0);
signal wr_counter : unsigned(15 downto 0);
signal rd_counter : unsigned(15 downto 0);
signal wr_mod : unsigned(15 downto 0);
signal rd_mod : unsigned(15 downto 0);
signal wr_counter_total : unsigned(31 downto 0);
signal rd_counter_total : unsigned(31 downto 0);
signal counter : unsigned(31 downto 0);
signal counter2 : unsigned(31 downto 0);
signal init_table_wr : std_logic;
signal init_table_rd : std_logic;
signal do1 : unsigned(15 downto 0);
signal do2 : unsigned(15 downto 0);
signal data_temp : unsigned(15 downto 0);
signal data_temp2 : unsigned(15 downto 0);
signal temp :std_logic_vector(23 downto 0);
signal fifo_almost_full_i : std_logic;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- RAM for SUB_FIFOs
-------------------------------------------------------------------
fifo_almost_full <= fifo_almost_full_i;
U_SUB_RAMZ : entity work.SUB_RAMZ
generic map
(
RAMADDR_W => log2( C_MAX_LINE_WIDTH*C_NUM_LINES ),
RAMDATA_W => C_PIXEL_BITS
)
port map
(
d => ram_data,
waddr => std_logic_vector(wr_ptr),
raddr => std_logic_vector(rd_ptr),
we => ram_write,
clk => clk,
q => q
);
MULTIPLIER : entity work.multiplier
PORT MAP(
CLK => CLK,
RST => RST,
img_size_x => img_size_x,
img_size_y => img_size_y,
result => result,
threshold => threshold
);
U_SUB_RAMZ_WR_ADRESS_LUT : entity work.SUB_RAMZ_LUT
generic map
(
RAMADDR_W => log2( C_MAX_LINE_WIDTH ),
RAMDATA_W => 16
)
port map
(
d => std_logic_vector(data_in),
waddr => std_logic_vector(wr_addr),
raddr => std_logic_vector(rd_addr),
we => we,
clk => CLK,
q => data_out
);
U_SUB_RAMZ_RD_ADRESS_LUT : entity work.SUB_RAMZ_LUT
generic map
(
RAMADDR_W => log2( C_MAX_LINE_WIDTH ),
RAMDATA_W => 16
)
port map
(
d => std_logic_vector(data_in2),
waddr => std_logic_vector(wr_addr2),
raddr => std_logic_vector(rd_addr2),
we => we2,
clk => CLK,
q => data_out2
);
process (CLK, RST)
begin
if (RST = '1') then
wr_counter <= (others => '0');
wr_counter_total <= (others => '0');
wr_mod <= (others => '0');
wr_ptr <= (others => '0');
ram_write <= '0';
init_table_wr <= '0';
do1 <= (others => '0');
data_temp <= (others => '0');
wr_addr <= (others => '0');
rd_addr <= (others => '0');
we <= '0';
counter <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (init_table_wr = '0') then
if (iram_wren = '1') then
if (wr_mod /= 0 and wr_counter mod 8 = "000") then
wr_ptr <= resize(do1(5 downto 3) * unsigned(img_size_x), log2(C_MAX_LINE_WIDTH*C_NUM_LINES)) + resize(do1(15 downto 6) * 8, log2(C_MAX_LINE_WIDTH*C_NUM_LINES));
data_temp <= resize(do1(5 downto 3) * unsigned(img_size_x), 16) + resize(do1(15 downto 6) * 8, 16);
--wr_ptr <= do1 / 8 mod 8 * unsigned(img_size_x) + do1 / 8 / 8 * 8;
--data_temp <= do1 / 8 mod 8 * unsigned(img_size_x) + do1 / 8 / 8 * 8;
else
if (wr_counter = 0) then
wr_ptr <= (others => '0');
else
wr_ptr <= wr_ptr + 1;
end if;
end if;
if (wr_mod /= 0 and wr_counter mod 8 = "011") then
if (wr_counter = unsigned(img_size_x) * 8 - 5) then
rd_addr <= (others => '0');
else
rd_addr <= resize((wr_counter + 5) / 8, log2(C_MAX_LINE_WIDTH));
end if;
end if;
if (wr_mod /= 0 and wr_counter mod 8 = "101") then
do1 <= unsigned(data_out);
we <= '1';
if (wr_mod = unsigned(img_size_y) / 8 - 1) then
wr_addr <= resize(counter, log2(C_MAX_LINE_WIDTH));
data_in <= resize(counter * 8, 16);
counter <= counter + 1;
else
data_in <= data_temp;
if (wr_counter = unsigned(img_size_x) * 8 - 3) then
wr_addr <= (others => '0');
else
wr_addr <= resize((wr_counter + 3) / 8 - 1, log2(C_MAX_LINE_WIDTH));
end if;
end if;
else
we <= '0';
end if;
ram_write <= '1';
ram_data <= iram_wdata;
wr_counter_total <= wr_counter_total + 1;
if (wr_counter_total = unsigned(result) - 1) then
init_table_wr <= '1';
counter <= (others => '0');
end if;
if (wr_counter = unsigned(img_size_x) * 8 - 1) then
wr_counter <= (others => '0');
wr_mod <= wr_mod + 1;
else
wr_counter <= wr_counter + 1;
end if;
else
ram_write <= '0';
end if;
if sof = '1' then
wr_counter <= (others => '0');
wr_counter_total <= (others => '0');
wr_mod <= (others => '0');
wr_ptr <= (others => '0');
ram_write <= '0';
init_table_wr <= '0';
do1 <= (others => '0');
data_temp <= (others => '0');
wr_addr <= (others => '0');
rd_addr <= (others => '0');
we <= '0';
counter <= (others => '0');
end if;
end if;
end if;
end process;
process (CLK, RST)
begin
if (RST = '1') then
fifo_almost_full_i <= '0';
fdct_fifo_hf_full <= '0';
elsif (CLK'event and CLK = '1') then
if (fifo_almost_full_i = '0' and wr_counter_total = rd_counter_total + unsigned(img_size_x)*8-2) then
fifo_almost_full_i <= '1';
end if;
if (fifo_almost_full_i = '1' and wr_counter_total < rd_counter_total + unsigned(threshold) ) then
fifo_almost_full_i <= '0';
end if;
if (wr_counter = unsigned(img_size_x) * 8 - 1) then
fdct_fifo_hf_full <= '1';
end if;
if (rd_counter = unsigned(img_size_x) * 8 - 1) then
fdct_fifo_hf_full <= '0';
fifo_almost_full_i <= '0';
end if;
if sof = '1' then
fifo_almost_full_i <= '0';
fdct_fifo_hf_full <= '0';
end if;
end if;
end process;
process (CLK, RST)
begin
if (RST = '1') then
fdct_fifo_q <= (others => '0');
temp <= (others => '0');
rd_counter <= (others => '0');
rd_counter_total <= (others => '0');
rd_mod <= x"0001";
rd_ptr <= (others => '0');
init_table_rd <= '0';
do2 <= (others => '0');
data_temp2 <= (others => '0');
wr_addr2 <= (others => '0');
rd_addr2 <= (others => '0');
we2 <= '0';
counter2 <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (init_table_rd = '0') then
if (fdct_fifo_rd = '1') then
if (rd_counter mod 8 = "000") then
--rd_ptr <= resize(do2(5 downto 3) * unsigned(img_size_x) + do2(15 downto 7) * 8, log2(C_MAX_LINE_WIDTH*C_NUM_LINES));
--data_temp2 <= resize(do2(5 downto 3) * unsigned(img_size_x) + do2(15 downto 7) * 8, 16);
rd_ptr <= resize(do2(5 downto 3) * unsigned(img_size_x), log2(C_MAX_LINE_WIDTH*C_NUM_LINES)) + resize(do2(15 downto 6) * 8, log2(C_MAX_LINE_WIDTH*C_NUM_LINES));
data_temp2 <= resize(do2(5 downto 3) * unsigned(img_size_x), 16) + resize(do2(15 downto 6) * 8, 16);
else
rd_ptr <= rd_ptr + 1;
end if;
if (rd_counter mod 8 = "011") then
if (rd_counter = unsigned(img_size_x) * 8 - 5) then
rd_addr2 <= (others => '0');
else
rd_addr2 <= resize(unsigned(rd_counter + 5) / 8, log2(C_MAX_LINE_WIDTH));
end if;
end if;
if (rd_counter mod 8 = "101") then
do2 <= unsigned(data_out2);
we2 <= '1';
if (rd_mod = unsigned(img_size_y) / 8) then
data_in2 <= resize(counter2 * 8, 16);
wr_addr2 <= resize(counter2, log2(C_MAX_LINE_WIDTH));
counter2 <= counter2 + 1;
else
data_in2 <= data_temp2;
if (rd_counter = unsigned(img_size_x) * 8 - 3) then
wr_addr2 <= (others => '0');
else
wr_addr2 <= resize(unsigned(rd_counter + 3) / 8 - 1, log2(C_MAX_LINE_WIDTH));
end if;
end if;
else
we2 <= '0';
end if;
rd_counter_total <= rd_counter_total + 1;
if (rd_counter_total = unsigned(result) - 1) then
init_table_rd <= '1';
counter2 <= (others => '0');
end if;
if (rd_counter = unsigned(img_size_x) * 8 - 1) then
rd_counter <= (others => '0');
rd_mod <= rd_mod + 1;
else
rd_counter <= rd_counter + 1;
end if;
end if;
if sof = '1' then
fdct_fifo_q <= (others => '0');
temp <= (others => '0');
rd_counter <= (others => '0');
rd_counter_total <= (others => '0');
rd_mod <= x"0001";
rd_ptr <= (others => '0');
init_table_rd <= '0';
do2 <= (others => '0');
data_temp2 <= (others => '0');
wr_addr2 <= (others => '0');
rd_addr2 <= (others => '0');
we2 <= '0';
counter2 <= (others => '0');
end if;
-- fdct_fifo_q <= (temp(15 downto 11) & "000" &
-- temp(10 downto 5) & "00" &
-- temp(4 downto 0) & "000") when C_PIXEL_BITS = 16 else
-- std_logic_vector(resize(unsigned(temp), 24));
end if;
temp <= q;
if (C_PIXEL_BITS = 16) then
fdct_fifo_q <= (temp(15 downto 11) & "000" &
temp(10 downto 5) & "00" &
temp(4 downto 0) & "000");
else
fdct_fifo_q <= temp;
end if;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- | lgpl-3.0 | cc8f0c8616316b6facbf36826c0f3a77 | 0.427858 | 3.584918 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/boards/terasic-de2-115/mn-single-hostif-drv/quartus/toplevel.vhd | 1 | 11,968 | -------------------------------------------------------------------------------
--! @file toplevel.vhd
--
--! @brief Toplevel of Nios MN design Pcp part
--
--! @details This is the toplevel of the Nios MN FPGA Pcp design for the
--! INK DE2-115 Evaluation Board.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library libcommon;
use libcommon.global.all;
entity toplevel is
port (
-- 50 MHZ CLK IN
EXT_CLK : in std_logic;
-- PHY Interfaces
PHY_GXCLK : out std_logic_vector(1 downto 0);
PHY_RXCLK : in std_logic_vector(1 downto 0);
PHY_RXER : in std_logic_vector(1 downto 0);
PHY_RXDV : in std_logic_vector(1 downto 0);
PHY_RXD : in std_logic_vector(7 downto 0);
PHY_TXCLK : in std_logic_vector(1 downto 0);
PHY_TXER : out std_logic_vector(1 downto 0);
PHY_TXEN : out std_logic_vector(1 downto 0);
PHY_TXD : out std_logic_vector(7 downto 0);
PHY_MDIO : inout std_logic_vector(1 downto 0);
PHY_MDC : out std_logic_vector(1 downto 0);
PHY_RESET_n : out std_logic_vector(1 downto 0);
-- EPCS
EPCS_DCLK : out std_logic;
EPCS_SCE : out std_logic;
EPCS_SDO : out std_logic;
EPCS_DATA0 : in std_logic;
-- 2 MB SRAM
SRAM_CE_n : out std_logic;
SRAM_OE_n : out std_logic;
SRAM_WE_n : out std_logic;
SRAM_ADDR : out std_logic_vector(20 downto 1);
SRAM_BE_n : out std_logic_vector(1 downto 0);
SRAM_DQ : inout std_logic_vector(15 downto 0);
-- HOST Interface
HOSTIF_AD : inout std_logic_vector(16 downto 0);
HOSTIF_BE : in std_logic_vector(1 downto 0);
HOSTIF_CS_n : in std_logic;
HOSTIF_WR_n : in std_logic;
HOSTIF_RD_n : in std_logic;
HOSTIF_ALE_n : in std_logic;
HOSTIF_ACK_n : out std_logic;
HOSTIF_IRQ_n : out std_logic
);
end toplevel;
architecture rtl of toplevel is
component mnSingleHostifDrv is
port (
clk25_clk : in std_logic;
clk50_clk : in std_logic := 'X';
clk100_clk : in std_logic;
reset_reset_n : in std_logic := 'X';
tri_state_0_tcm_address_out : out std_logic_vector(20 downto 0);
tri_state_0_tcm_byteenable_n_out : out std_logic_vector(1 downto 0);
tri_state_0_tcm_read_n_out : out std_logic;
tri_state_0_tcm_write_n_out : out std_logic;
tri_state_0_tcm_data_out : inout std_logic_vector(15 downto 0) := (others => 'X');
tri_state_0_tcm_chipselect_n_out : out std_logic;
pcp_0_benchmark_pio_export : out std_logic_vector(7 downto 0);
-- OPENMAC
openmac_0_mii_txEnable : out std_logic_vector(1 downto 0);
openmac_0_mii_txData : out std_logic_vector(7 downto 0);
openmac_0_mii_txClk : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxError : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxDataValid : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxData : in std_logic_vector(7 downto 0) := (others => 'X');
openmac_0_mii_rxClk : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_smi_nPhyRst : out std_logic_vector(1 downto 0);
openmac_0_smi_clk : out std_logic_vector(1 downto 0);
openmac_0_smi_dio : inout std_logic_vector(1 downto 0) := (others => 'X');
epcs_flash_dclk : out std_logic;
epcs_flash_sce : out std_logic;
epcs_flash_sdo : out std_logic;
epcs_flash_data0 : in std_logic := 'X';
hostinterface_0_irqout_irq : out std_logic;
prl0_iPrlSlv_cs : in std_logic := 'X';
prl0_iPrlSlv_rd : in std_logic := 'X';
prl0_iPrlSlv_wr : in std_logic := 'X';
prl0_iPrlSlv_ale : in std_logic := 'X';
prl0_oPrlSlv_ack : out std_logic;
prl0_iPrlSlv_be : in std_logic_vector(1 downto 0) := (others => 'X');
prl0_oPrlSlv_ad_o : out std_logic_vector(16 downto 0);
prl0_iPrlSlv_ad_i : in std_logic_vector(16 downto 0) := (others => 'X');
prl0_oPrlSlv_ad_oen : out std_logic
);
end component mnSingleHostifDrv;
-- PLL component
component pll
port (
inclk0 : in std_logic;
c0 : out std_logic;
c1 : out std_logic;
c2 : out std_logic;
c3 : out std_logic;
locked : out std_logic
);
end component;
signal clk25 : std_logic;
signal clk50 : std_logic;
signal clk100 : std_logic;
signal clk100_p : std_logic;
signal pllLocked : std_logic;
signal sramAddr : std_logic_vector(SRAM_ADDR'high downto 0);
signal parHost_chipselect : std_logic;
signal parHost_read : std_logic;
signal parHost_write : std_logic;
signal parHost_addressLatchEnable : std_logic;
signal parHost_acknowledge : std_logic;
signal parHost_ad_o : std_logic_vector(HOSTIF_AD'range);
signal parHost_ad_i : std_logic_vector(HOSTIF_AD'range);
signal parHost_ad_oen : std_logic;
signal host_irq : std_logic;
begin
SRAM_ADDR <= sramAddr(SRAM_ADDR'range);
PHY_GXCLK <= (others => '0');
PHY_TXER <= (others => '0');
HOSTIF_ACK_n <= not parHost_acknowledge;
HOSTIF_IRQ_n <= not host_irq;
parHost_chipselect <= not HOSTIF_CS_n;
parHost_write <= not HOSTIF_WR_n;
parHost_read <= not HOSTIF_RD_n;
parHost_addressLatchEnable <= not HOSTIF_ALE_n;
-- TRISTATE Buffer for AD bus
HOSTIF_AD <= parHost_ad_o when parHost_ad_oen = '1' else (others => 'Z');
parHost_ad_i <= HOSTIF_AD;
inst : component mnSingleHostifDrv
port map (
clk25_clk => clk25,
clk50_clk => clk50,
clk100_clk => clk100,
reset_reset_n => pllLocked,
openmac_0_mii_txEnable => PHY_TXEN,
openmac_0_mii_txData => PHY_TXD,
openmac_0_mii_txClk => PHY_TXCLK,
openmac_0_mii_rxError => PHY_RXER,
openmac_0_mii_rxDataValid => PHY_RXDV,
openmac_0_mii_rxData => PHY_RXD,
openmac_0_mii_rxClk => PHY_RXCLK,
openmac_0_smi_nPhyRst => PHY_RESET_n,
openmac_0_smi_clk => PHY_MDC,
openmac_0_smi_dio => PHY_MDIO,
tri_state_0_tcm_address_out => sramAddr,
tri_state_0_tcm_read_n_out => SRAM_OE_n,
tri_state_0_tcm_byteenable_n_out => SRAM_BE_n,
tri_state_0_tcm_write_n_out => SRAM_WE_n,
tri_state_0_tcm_data_out => SRAM_DQ,
tri_state_0_tcm_chipselect_n_out => SRAM_CE_n,
pcp_0_benchmark_pio_export => open,
epcs_flash_dclk => EPCS_DCLK,
epcs_flash_sce => EPCS_SCE,
epcs_flash_sdo => EPCS_SDO,
epcs_flash_data0 => EPCS_DATA0,
hostinterface_0_irqout_irq => host_irq,
prl0_iPrlSlv_cs => parHost_chipselect,
prl0_iPrlSlv_rd => parHost_read,
prl0_iPrlSlv_wr => parHost_write,
prl0_iPrlSlv_ale => parHost_addressLatchEnable,
prl0_oPrlSlv_ack => parHost_acknowledge,
prl0_iPrlSlv_be => HOSTIF_BE,
prl0_oPrlSlv_ad_o => parHost_ad_o,
prl0_iPrlSlv_ad_i => parHost_ad_i,
prl0_oPrlSlv_ad_oen => parHost_ad_oen
);
-- Pll Instance
pllInst : pll
port map (
inclk0 => EXT_CLK,
c0 => clk50,
c1 => clk100,
c2 => clk25,
c3 => open,
locked => pllLocked
);
end rtl;
| gpl-2.0 | 89a9713c29f67c67f14489dbb35856ed | 0.459726 | 4.239462 | false | false | false | false |
chiggs/oc_mkjpeg | design/BufFifo/SUB_RAMZ_LUT.vhd | 1 | 4,113 | --------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
-- --
-- Title : SUB_RAMZ --
-- Design : EV_JPEG_ENC --
-- Author : Michal Krepa -- -- --
-- --
--------------------------------------------------------------------------------
--
-- File : SUB_RAMZ.VHD
-- Created : 22/03/2009
--
--------------------------------------------------------------------------------
--
-- Description : RAM memory simulation model
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use IEEE.std_logic_textio.all;
library std;
use std.textio.all;
entity SUB_RAMZ_LUT is
generic
(
RAMADDR_W : INTEGER := 6;
RAMDATA_W : INTEGER := 12
);
port (
d : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
waddr : in STD_LOGIC_VECTOR(RAMADDR_W-1 downto 0);
raddr : in STD_LOGIC_VECTOR(RAMADDR_W-1 downto 0);
we : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0)
);
end SUB_RAMZ_LUT;
architecture RTL of SUB_RAMZ_LUT is
type mem_type is array ((2**RAMADDR_W)-1 downto 0) of
STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
--type mem_type is array (( 1296*8)-1 downto 0) of --/*1296*8*/
-- STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
impure function InitRamFromFile (RamFileName : in string) return mem_type is
FILE RamFile : text is in RamFileName;
variable RamFileLine : line;
variable RAM : mem_type;
begin
for I in 0 to (2**RAMADDR_W)-1 loop
readline (RamFile, RamFileLine);
--Write (RamFileLine, I * 8);
hread(RamFileLine, RAM(I));
--write( (I * 8),RamFileLine );
--read (RamFileLine, RAM(I), LEFT, 10);
end loop;
return RAM;
end function;
signal mem : mem_type := InitRamFromFile("../design/BufFifo/counter_8.txt") ;
signal read_addr : STD_LOGIC_VECTOR(RAMADDR_W-1 downto 0);
--attribute ram_style: string;
--attribute ram_style of mem : signal is "distributed";
begin
-------------------------------------------------------------------------------
q_sg:
-------------------------------------------------------------------------------
q <= mem(TO_INTEGER(UNSIGNED(read_addr)));
-------------------------------------------------------------------------------
read_proc: -- register read address
-------------------------------------------------------------------------------
process (clk)
begin
if clk = '1' and clk'event then
read_addr <= raddr;
end if;
end process;
-------------------------------------------------------------------------------
write_proc: --write access
-------------------------------------------------------------------------------
process (clk) begin
if clk = '1' and clk'event then
if we = '1' then
mem(TO_INTEGER(UNSIGNED(waddr))) <= d;
end if;
end if;
end process;
end RTL; | lgpl-3.0 | af0c4cd5f37cca6c879425cd71058618 | 0.332361 | 5.348505 | false | false | false | false |
cnplab/blockmon | fw-combo/src/IPFIX/comp/barrel_bit_shifter.vhd | 1 | 3,942 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- barrel_bit_shifter.vhd: Barrel shifter with generic data width
-- Copyright (C) 2010 CESNET
-- Author(s): Viktor Pus <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: barrel_bit_shifter.vhd 13189 2010-03-10 15:07:35Z pus $
--
-- TODO:
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.math_pack.all;
-- ----------------------------------------------------------------------------
-- ENTITY DECLARATION -- Barrel shifter --
-- ----------------------------------------------------------------------------
entity BARREL_BIT_SHIFTER is
generic (
DATA_WIDTH : integer := 8;
-- set true to shift left, false to shift right
SHIFT_LEFT : boolean := true
);
port (
-- Input interface ------------------------------------------------------
DATA_IN : in std_logic_vector(DATA_WIDTH-1 downto 0);
DATA_OUT : out std_logic_vector(DATA_WIDTH-1 downto 0);
SEL : in std_logic_vector(log2(DATA_WIDTH)-1 downto 0)
);
end BARREL_BIT_SHIFTER;
-- ----------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION --
-- ----------------------------------------------------------------------------
architecture barrel_bit_shifter_arch of BARREL_BIT_SHIFTER is
begin
multiplexors: for i in 0 to DATA_WIDTH-1 generate
process (DATA_IN, SEL)
variable sel_aux: integer;
begin
if (SHIFT_LEFT) then
sel_aux := conv_integer('0'&SEL);
else
sel_aux := conv_integer('0'&(0-SEL));
end if;
DATA_OUT(i) <= DATA_IN((DATA_WIDTH-sel_aux+i) mod (DATA_WIDTH));
end process;
end generate;
end barrel_bit_shifter_arch;
| bsd-3-clause | 68d18780092d827a065138ee0e3bce76 | 0.570015 | 4.594406 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/parallelinterface/src/prlMaster-rtl-ea.vhd | 3 | 13,001 | -------------------------------------------------------------------------------
--! @file prlMaster-rtl-ea.vhd
--! @brief Multiplexed memory mapped master
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--! Use standard ieee library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Use numeric std
use ieee.numeric_std.all;
--! Use libcommon library
library libcommon;
--! Use global package
use libcommon.global.all;
entity prlMaster is
generic (
--! Enable multiplexed address/data-bus mode (0 = FALSE)
gEnableMux : natural := 0;
--! Data bus width
gDataWidth : natural := 16;
--! Address bus width
gAddrWidth : natural := 16;
--! Address low
gAddrLow : natural := 0;
--! Ad bus width (valid when gEnableMux /= FALSE)
gAdWidth : natural := 16
);
port (
--! Clock
iClk : in std_logic;
--! Reset
iRst : in std_logic;
-- Memory mapped slave
--! Address
iSlv_address : in std_logic_vector(gAddrWidth-1 downto gAddrLow);
--! Read strobe
iSlv_read : in std_logic;
--! Readdata
oSlv_readdata : out std_logic_vector(gDataWidth-1 downto 0);
--! Write strobe
iSlv_write : in std_logic;
--! Writedata
iSlv_writedata : in std_logic_vector(gDataWidth-1 downto 0);
--! Waitrequest
oSlv_waitrequest : out std_logic;
--! Byteenable
iSlv_byteenable : in std_logic_vector(gDataWidth/8-1 downto 0);
-- Memory mapped multiplexed master
--! Chipselect
oPrlMst_cs : out std_logic;
-- Multiplexed AD-bus
--! Multiplexed address data bus input
iPrlMst_ad_i : in std_logic_vector(gAdWidth-1 downto 0);
--! Multiplexed address data bus output
oPrlMst_ad_o : out std_logic_vector(gAdWidth-1 downto 0);
--! Multiplexed address data bus enable
oPrlMst_ad_oen : out std_logic;
-- Demultiplexed AD-bus
--! Address bus
oPrlMst_addr : out std_logic_vector(gAddrWidth-1 downto 0);
--! Data bus in
iPrlMst_data_i : in std_logic_vector(gDataWidth-1 downto 0);
--! Data bus out
oPrlMst_data_o : out std_logic_vector(gDataWidth-1 downto 0);
--! Data bus outenable
oPrlMst_data_oen : out std_logic;
--! Byteenable
oPrlMst_be : out std_logic_vector(gDataWidth/8-1 downto 0);
--! Address latch enable
oPrlMst_ale : out std_logic;
--! Write strobe
oPrlMst_wr : out std_logic;
--! Read strobe
oPrlMst_rd : out std_logic;
--! Acknowledge
iPrlMst_ack : in std_logic
);
end entity prlMaster;
architecture rtl of prlMaster is
constant cCount_AleDisable : std_logic_vector := "011";
constant cCount_AleExit : std_logic_vector := "101";
constant cCount_max : std_logic_vector := "111";
constant cCountWidth : natural := cCount_max'length;
-- State machine for bus timing
type tFsm is (
sIdle,
sAle,
sWrd,
sHold
);
-- Synchronized ack signal
signal ack : std_logic;
-- Rising edge of ack signal
signal ack_p : std_logic;
--! This record holds all output registers to the bus.
type tReg is record
address : std_logic_vector(gAddrWidth-1 downto 0);
byteenable : std_logic_vector(gDataWidth/8-1 downto 0);
write : std_logic;
read : std_logic;
chipselect : std_logic;
data : std_logic_vector(gDataWidth-1 downto 0);
data_oen : std_logic;
data_in : std_logic_vector(gDataWidth-1 downto 0);
ad : std_logic_vector(gAdWidth-1 downto 0);
ad_oen : std_logic;
ale : std_logic;
fsm : tFsm;
count : std_logic_vector(cCountWidth-1 downto 0);
count_rst : std_logic;
end record;
-- Initialization vector of output registers
constant cRegInit : tReg := (
address => (others => cInactivated),
byteenable => (others => cInactivated),
write => cInactivated,
read => cInactivated,
chipselect => cInactivated,
data => (others => cInactivated),
data_oen => cInactivated,
data_in => (others => cInactivated),
ad => (others => cInactivated),
ad_oen => cInactivated,
ale => cInactivated,
fsm => sIdle,
count => (others => cInactivated),
count_rst => cInactivated
);
-- Register state
signal reg : tReg;
-- Next register state
signal reg_next : tReg;
begin
-- MAP IOs
oSlv_waitrequest <= not ack_p;
oSlv_readdata <= reg.data_in;
oPrlMst_be <= reg.byteenable;
oPrlMst_wr <= reg.write;
oPrlMst_rd <= reg.read;
oPrlMst_cs <= reg.chipselect;
--! Generate mux bus IOs. Demux bus is incactive.
genMux : if gEnableMux /= 0 generate
-- MUX
oPrlMst_ale <= reg.ale;
oPrlMst_ad_o <= reg.ad;
oPrlMst_ad_oen <= reg.ad_oen;
oPrlMst_addr <= (others => cInactivated);
oPrlMst_data_o <= (others => cInactivated);
oPrlMst_data_oen <= cInactivated;
-- iPrlMst_data_i is ignored
end generate genMux;
--! Generate demux bus IOs. Mux bus is incactive.
genDemux : if gEnableMux = 0 generate
-- DEMUX
oPrlMst_addr <= reg.address;
oPrlMst_data_o <= reg.data;
oPrlMst_data_oen <= reg.data_oen;
oPrlMst_ale <= cInactivated;
oPrlMst_ad_o <= (others => cInactivated);
oPrlMst_ad_oen <= cInactivated;
-- iPrlMst_ad_i is ignored
end generate genDemux;
--! This is the clock register process.
regClk : process(iRst, iClk)
begin
if iRst = cActivated then
reg <= cRegInit;
elsif rising_edge(iClk) then
reg <= reg_next;
end if;
end process regClk;
--! This is the next register state process.
combReg : process (
reg, ack,
iSlv_read,
iSlv_write,
iSlv_byteenable,
iSlv_address,
iSlv_writedata,
iPrlMst_ad_i,
iPrlMst_data_i
)
begin
-- default
reg_next <= reg;
-- counter reset active by default
reg_next.count_rst <= cActivated;
if reg.count_rst = cActivated then
reg_next.count <= (others => cInactivated);
else
reg_next.count <= std_logic_vector(unsigned(reg.count) + 1);
end if;
case reg.fsm is
when sIdle =>
reg_next.chipselect <= cInactivated;
reg_next.ale <= cInactivated;
reg_next.ad_oen <= cInactivated;
reg_next.data_oen <= cInactivated;
reg_next.read <= cInactivated;
reg_next.write <= cInactivated;
-- Start transaction if there is either a read or write.
if iSlv_write = cActivated or iSlv_read = cActivated then
reg_next.chipselect <= cActivated;
reg_next.byteenable <= iSlv_byteenable;
if gEnableMux /= 0 then
-- MUX mode
reg_next.fsm <= sAle;
reg_next.ale <= cActivated;
reg_next.ad_oen <= cActivated;
reg_next.ad <= (others => cInactivated);
reg_next.ad(iSlv_address'range) <= iSlv_address;
else
-- DEMUX mode
reg_next.fsm <= sWrd;
reg_next.write <= iSlv_write;
reg_next.read <= iSlv_read;
reg_next.data <= iSlv_writedata;
reg_next.data_oen <= iSlv_write;
reg_next.address <= iSlv_address;
end if;
end if;
when sAle =>
-- Use counter to generate ale timing.
reg_next.count_rst <= cInactivated;
if reg.count = cCount_AleDisable then
reg_next.ale <= cInactivated;
elsif reg.count = cCount_AleExit then
reg_next.count_rst <= cActivated;
reg_next.fsm <= sWrd;
reg_next.write <= iSlv_write;
reg_next.read <= iSlv_read;
reg_next.ad_oen <= iSlv_write;
reg_next.ad <= (others => cInactivated);
reg_next.ad(iSlv_writedata'range) <= iSlv_writedata;
end if;
when sWrd =>
if ack = cActivated then
reg_next.fsm <= sHold;
reg_next.count_rst <= cActivated;
reg_next.chipselect <= cInactivated;
reg_next.read <= cInactivated;
reg_next.write <= cInactivated;
reg_next.ad_oen <= cInactivated;
reg_next.data_oen <= cInactivated;
if reg.read = cActivated then
if gEnableMux /= 0 then
reg_next.data_in <= iPrlMst_ad_i(reg.data_in'range);
else
reg_next.data_in <= iPrlMst_data_i(reg.data_in'range);
end if;
end if;
end if;
when sHold =>
if ack = cInactivated then
reg_next.fsm <= sIdle;
reg_next.count_rst <= cActivated;
end if;
end case;
end process combReg;
--! Synchronizer to sync ack input.
syncAck : entity libcommon.synchronizer
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iArst => iRst,
iClk => iClk,
iAsync => iPrlMst_ack,
oSync => ack
);
--! Detect rising edge of ack signal to generate waitrequest neg. pulse.
edgeAck : entity libcommon.edgedetector
port map (
iArst => iRst,
iClk => iClk,
iEnable => cActivated,
iData => ack,
oRising => ack_p,
oFalling => open,
oAny => open
);
end architecture rtl;
| gpl-2.0 | 07491db7e5bc74de8cddd764860cad72 | 0.508192 | 4.649857 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/boards/terasic-de2-115/mn-single-hostif-gpio/quartus/toplevel.vhd | 1 | 10,419 | -------------------------------------------------------------------------------
--! @file toplevel.vhd
--
--! @brief Toplevel of Nios MN design Host part
--
--! @details This is the toplevel of the Nios MN FPGA Host design for the
--! INK DE2-115 Evaluation Board.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library libcommon;
use libcommon.global.all;
entity toplevel is
port (
-- 50 MHZ CLK IN
EXT_CLK : in std_logic;
-- EPCS
EPCS_DCLK : out std_logic;
EPCS_SCE : out std_logic;
EPCS_SDO : out std_logic;
EPCS_DATA0 : in std_logic;
-- 64 MBx2 SDRAM
SDRAM_CLK : out std_logic;
SDRAM_CAS_n : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CS_n : out std_logic;
SDRAM_RAS_n : out std_logic;
SDRAM_WE_n : out std_logic;
SDRAM_ADDR : out std_logic_vector(12 downto 0);
SDRAM_BA : out std_logic_vector(1 downto 0);
SDRAM_DQM : out std_logic_vector(3 downto 0);
SDRAM_DQ : inout std_logic_vector(31 downto 0);
-- LED green
LEDG : out std_logic_vector(1 downto 0);
-- Low active KEY
KEY_n : in std_logic_vector(3 downto 0);
-- LCD
LCD_ON : out std_logic;
LCD_BLON : out std_logic;
LCD_DQ : inout std_logic_vector(7 downto 0);
LCD_E : out std_logic;
LCD_RS : out std_logic;
LCD_RW : out std_logic;
-- HOST Interface
HOSTIF_AD : inout std_logic_vector(16 downto 0);
HOSTIF_BE : out std_logic_vector(1 downto 0);
HOSTIF_CS_n : out std_logic;
HOSTIF_WR_n : out std_logic;
HOSTIF_ALE_n : out std_logic;
HOSTIF_RD_n : out std_logic;
HOSTIF_ACK_n : in std_logic;
HOSTIF_IRQ_n : in std_logic
);
end toplevel;
architecture rtl of toplevel is
component mnSingleHostifGpio is
port (
clk25_clk : in std_logic;
clk50_clk : in std_logic := 'X';
clk100_clk : in std_logic;
reset_reset_n : in std_logic := 'X';
host_0_benchmark_pio_export : out std_logic_vector(7 downto 0);
status_led_pio_export : out std_logic_vector(1 downto 0);
key_pio_export : in std_logic_vector(3 downto 0);
epcs_flash_dclk : out std_logic;
epcs_flash_sce : out std_logic;
epcs_flash_sdo : out std_logic;
epcs_flash_data0 : in std_logic := 'X';
host_0_sdram_0_addr : out std_logic_vector(12 downto 0);
host_0_sdram_0_ba : out std_logic_vector(1 downto 0);
host_0_sdram_0_cas_n : out std_logic;
host_0_sdram_0_cke : out std_logic;
host_0_sdram_0_cs_n : out std_logic;
host_0_sdram_0_dq : inout std_logic_vector(31 downto 0) := (others => 'X');
host_0_sdram_0_dqm : out std_logic_vector(3 downto 0);
host_0_sdram_0_ras_n : out std_logic;
host_0_sdram_0_we_n : out std_logic;
host_0_irq_irq : in std_logic := 'X';
lcd_data : inout std_logic_vector(7 downto 0) := (others => 'X');
lcd_E : out std_logic;
lcd_RS : out std_logic;
lcd_RW : out std_logic;
prl0_oPrlMst_cs : out std_logic;
prl0_iPrlMst_ad_i : in std_logic_vector(16 downto 0) := (others => 'X');
prl0_oPrlMst_ad_o : out std_logic_vector(16 downto 0);
prl0_oPrlMst_ad_oen : out std_logic;
prl0_oPrlMst_be : out std_logic_vector(1 downto 0);
prl0_oPrlMst_ale : out std_logic;
prl0_oPrlMst_wr : out std_logic;
prl0_oPrlMst_rd : out std_logic;
prl0_iPrlMst_ack : in std_logic := 'X'
);
end component mnSingleHostifGpio;
-- PLL component
component pll
port (
inclk0 : in std_logic;
c0 : out std_logic;
c1 : out std_logic;
c2 : out std_logic;
c3 : out std_logic;
locked : out std_logic
);
end component;
signal clk25 : std_logic;
signal clk50 : std_logic;
signal clk100 : std_logic;
signal clk100_p : std_logic;
signal pllLocked : std_logic;
signal hostifCs : std_logic;
signal hostifWr : std_logic;
signal hostifRd : std_logic;
signal hostifAle : std_logic;
signal hostifAck : std_logic;
signal hostifAd_i : std_logic_vector(HOSTIF_AD'range);
signal hostifAd_o : std_logic_vector(HOSTIF_AD'range);
signal hostifAd_oen : std_logic;
signal hostifIrq : std_logic;
signal key : std_logic_vector(KEY_n'range);
begin
LCD_ON <= '1';
LCD_BLON <= '1';
SDRAM_CLK <= clk100_p;
HOSTIF_CS_n <= not hostifCs;
HOSTIF_WR_n <= not hostifWr;
HOSTIF_RD_n <= not hostifRd;
HOSTIF_ALE_n <= not hostifAle;
hostifAck <= not HOSTIF_ACK_n;
-- TRISTATE Buffer for AD bus
HOSTIF_AD <= hostifAd_o when hostifAd_oen = '1' else (others => 'Z');
hostifAd_i <= HOSTIF_AD;
hostifIrq <= not HOSTIF_IRQ_n;
key <= not KEY_n;
inst : component mnSingleHostifGpio
port map (
clk25_clk => clk25,
clk50_clk => clk50,
clk100_clk => clk100,
reset_reset_n => pllLocked,
status_led_pio_export => LEDG,
key_pio_export => key,
host_0_benchmark_pio_export => open,
epcs_flash_dclk => EPCS_DCLK,
epcs_flash_sce => EPCS_SCE,
epcs_flash_sdo => EPCS_SDO,
epcs_flash_data0 => EPCS_DATA0,
host_0_sdram_0_addr => SDRAM_ADDR,
host_0_sdram_0_ba => SDRAM_BA,
host_0_sdram_0_cas_n => SDRAM_CAS_n,
host_0_sdram_0_cke => SDRAM_CKE,
host_0_sdram_0_cs_n => SDRAM_CS_n,
host_0_sdram_0_dq => SDRAM_DQ,
host_0_sdram_0_dqm => SDRAM_DQM,
host_0_sdram_0_ras_n => SDRAM_RAS_n,
host_0_sdram_0_we_n => SDRAM_WE_n,
prl0_oPrlMst_cs => hostifCs,
prl0_iPrlMst_ad_i => hostifAd_i,
prl0_oPrlMst_ad_o => hostifAd_o,
prl0_oPrlMst_ad_oen => hostifAd_oen,
prl0_oPrlMst_be => HOSTIF_BE,
prl0_oPrlMst_ale => hostifAle,
prl0_oPrlMst_wr => hostifWr,
prl0_oPrlMst_rd => hostifRd,
prl0_iPrlMst_ack => hostifAck,
host_0_irq_irq => hostifIrq,
lcd_data => LCD_DQ,
lcd_E => LCD_E,
lcd_RS => LCD_RS,
lcd_RW => LCD_RW
);
-- Pll Instance
pllInst : pll
port map (
inclk0 => EXT_CLK,
c0 => clk50,
c1 => clk100,
c2 => clk25,
c3 => clk100_p,
locked => pllLocked
);
end rtl;
| gpl-2.0 | ff4480c18eaa8751e3192b8482658036 | 0.462808 | 4.08268 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/fifo/src/asyncFifo-rtl-a.vhd | 3 | 9,760 | -------------------------------------------------------------------------------
--! @file asyncFifo-rtl-a.vhd
--
--! @brief The asynchronous Fifo architecture.
--
--! @details This is a generic dual clocked FIFO using the dpRam component as
--! memory.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
architecture rtl of asyncFifo is
--! Address width
constant cAddrWidth : natural := logDualis(gWordSize);
--! Type for DPRAM port commons
type tDpramPortCommon is record
clk : std_logic;
enable : std_logic;
address : std_logic_vector(cAddrWidth-1 downto 0);
end record;
--! Type for DPRAM port assignment
type tDpramPort is record
wrPort : tDpramPortCommon;
rdPort : tDpramPortCommon;
write : std_logic;
writedata : std_logic_vector(gDataWidth-1 downto 0);
readdata : std_logic_vector(gDataWidth-1 downto 0);
end record;
--! Type for control port
type tControlPort is record
clk : std_logic;
rst : std_logic;
request : std_logic;
otherPointer : std_logic_vector(cAddrWidth downto 0);
empty : std_logic;
full : std_logic;
pointer : std_logic_vector(cAddrWidth downto 0);
address : std_logic_vector(cAddrWidth-1 downto 0);
usedWord : std_logic_vector(cAddrWidth-1 downto 0);
end record;
--! Type for pointer synchronizers
type tPointerSyncPort is record
clk : std_logic;
rst : std_logic;
din : std_logic_vector(cAddrWidth downto 0);
dout : std_logic_vector(cAddrWidth downto 0);
end record;
--! DPRAM instance
signal inst_dpram : tDpramPort;
--! Write controller instance
signal inst_writeCtrl : tControlPort;
--! Read controller instance
signal inst_readCtrl : tControlPort;
--! Write pointer synchronizer instance
signal inst_writeSync : tPointerSyncPort;
--! Read pointer synchronizer instance
signal inst_readSync : tPointerSyncPort;
begin
assert (gMemRes = "ON")
report "This FIFO implementation only supports memory resources!"
severity warning;
---------------------------------------------------------------------------
-- Assign Outputs
---------------------------------------------------------------------------
-- Write port
oWrEmpty <= inst_writeCtrl.empty;
oWrFull <= inst_writeCtrl.full;
oWrUsedw <= inst_writeCtrl.usedWord;
-- Read port
oRdEmpty <= inst_readCtrl.empty;
oRdFull <= inst_readCtrl.full;
oRdUsedw <= inst_readCtrl.usedWord;
oRdData <= inst_dpram.readdata;
---------------------------------------------------------------------------
-- Map DPRAM instance
---------------------------------------------------------------------------
-- Write port
inst_dpram.wrPort.clk <= iWrClk;
inst_dpram.wrPort.enable <= inst_writeCtrl.request;
inst_dpram.write <= inst_writeCtrl.request;
inst_dpram.wrPort.address <= inst_writeCtrl.address;
inst_dpram.writedata <= iWrData;
-- Read port
inst_dpram.rdPort.clk <= iRdClk;
inst_dpram.rdPort.enable <= iRdReq;
inst_dpram.rdPort.address <= inst_readCtrl.address;
---------------------------------------------------------------------------
-- Map Write and Read controller instance
---------------------------------------------------------------------------
inst_readCtrl.clk <= iRdClk;
inst_readCtrl.rst <= iAclr;
inst_readCtrl.request <= iRdReq;
inst_readCtrl.otherPointer <= inst_writeSync.dout;
inst_writeCtrl.clk <= iWrClk;
inst_writeCtrl.rst <= iAclr;
inst_writeCtrl.request <= iWrReq and not inst_writeCtrl.full;
inst_writeCtrl.otherPointer <= inst_readSync.dout;
---------------------------------------------------------------------------
-- Map pointer synchronizers
---------------------------------------------------------------------------
inst_readSync.rst <= iAclr;
inst_readSync.clk <= iWrClk; -- synchronize read pointer to write clock
inst_readSync.din <= inst_readCtrl.pointer;
inst_writeSync.rst <= iAclr;
inst_writeSync.clk <= iRdClk; -- synchronize write pointer to read clock
inst_writeSync.din <= inst_writeCtrl.pointer;
---------------------------------------------------------------------------
-- Instances
---------------------------------------------------------------------------
--! This is the FIFO read controller.
FIFO_READ_CONTROL : entity work.fifoRead
generic map (
gAddrWidth => cAddrWidth
)
port map (
iClk => inst_readCtrl.clk,
iRst => inst_readCtrl.rst,
iRead => inst_readCtrl.request,
iWrPointer => inst_readCtrl.otherPointer,
oEmpty => inst_readCtrl.empty,
oFull => inst_readCtrl.full,
oPointer => inst_readCtrl.pointer,
oAddress => inst_readCtrl.address,
oUsedWord => inst_readCtrl.usedWord
);
--! This is the FIFO write controller.
FIFO_WRITE_CONTROL : entity work.fifoWrite
generic map (
gAddrWidth => cAddrWidth
)
port map (
iClk => inst_writeCtrl.clk,
iRst => inst_writeCtrl.rst,
iWrite => inst_writeCtrl.request,
iRdPointer => inst_writeCtrl.otherPointer,
oEmpty => inst_writeCtrl.empty,
oFull => inst_writeCtrl.full,
oPointer => inst_writeCtrl.pointer,
oAddress => inst_writeCtrl.address,
oUsedWord => inst_writeCtrl.usedWord
);
--! This is the FIFO buffer.
FIFO_BUFFER : entity work.dpRamSplxNbe
generic map (
gWordWidth => gDataWidth,
gNumberOfWords => gWordSize,
gInitFile => "UNUSED"
)
port map (
iClk_A => inst_dpram.wrPort.clk,
iEnable_A => inst_dpram.wrPort.enable,
iWriteEnable_A => inst_dpram.write,
iAddress_A => inst_dpram.wrPort.address,
iWritedata_A => inst_dpram.writedata,
iClk_B => inst_dpram.rdPort.clk,
iEnable_B => inst_dpram.rdPort.enable,
iAddress_B => inst_dpram.rdPort.address,
oReaddata_B => inst_dpram.readdata
);
--! This generate block instantiates multiple synchrinizers to transfer
--! the write and read pointers to the opposite clock domains.
GEN_POINTERSYNC : for i in cAddrWidth downto 0 generate
WRITESYNC : entity libcommon.synchronizer
generic map (
gStages => gSyncStages,
gInit => cInactivated
)
port map (
iArst => inst_writeSync.rst,
iClk => inst_writeSync.clk,
iAsync => inst_writeSync.din(i),
oSync => inst_writeSync.dout(i)
);
READSYNC : entity libcommon.synchronizer
generic map (
gStages => gSyncStages,
gInit => cInactivated
)
port map (
iArst => inst_readSync.rst,
iClk => inst_readSync.clk,
iAsync => inst_readSync.din(i),
oSync => inst_readSync.dout(i)
);
end generate GEN_POINTERSYNC;
end rtl;
| gpl-2.0 | 4a38819ef9332e8738041201aa493974 | 0.53709 | 4.916877 | false | false | false | false |
chiggs/oc_mkjpeg | design/mdct/DCT1D.vhd | 1 | 14,104 | --------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT1D
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : DCT1D.VHD
-- Created : Sat Mar 5 7:37 2006
--
--------------------------------------------------------------------------------
--
-- Description : 1D Discrete Cosine Transform (1st stage)
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library WORK;
use WORK.MDCT_PKG.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity DCT1D is
port(
clk : in STD_LOGIC;
rst : in std_logic;
dcti : in std_logic_vector(IP_W-1 downto 0);
idv : in STD_LOGIC;
romedatao : in T_ROM1DATAO;
romodatao : in T_ROM1DATAO;
odv : out STD_LOGIC;
dcto : out std_logic_vector(OP_W-1 downto 0);
romeaddro : out T_ROM1ADDRO;
romoaddro : out T_ROM1ADDRO;
ramwaddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
ramdatai : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
ramwe : out STD_LOGIC;
wmemsel : out STD_LOGIC
);
end DCT1D;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture RTL of DCT1D is
type INPUT_DATA is array (N-1 downto 0) of SIGNED(IP_W downto 0);
signal databuf_reg : INPUT_DATA;
signal latchbuf_reg : INPUT_DATA;
signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal inpcnt_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal ramwe_s : STD_LOGIC;
signal wmemsel_reg : STD_LOGIC;
signal stage2_reg : STD_LOGIC;
signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0);
signal col_2_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal ramwaddro_s : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal even_not_odd : std_logic;
signal even_not_odd_d1 : std_logic;
signal even_not_odd_d2 : std_logic;
signal even_not_odd_d3 : std_logic;
signal ramwe_d1 : STD_LOGIC;
signal ramwe_d2 : STD_LOGIC;
signal ramwe_d3 : STD_LOGIC;
signal ramwe_d4 : STD_LOGIC;
signal ramwe_d5 : STD_LOGIC;
signal ramwe_d6 : STD_LOGIC;
signal ramwaddro_d1 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_d2 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_d3 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_d4 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_d5 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_d6 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal wmemsel_d1 : STD_LOGIC;
signal wmemsel_d2 : STD_LOGIC;
signal wmemsel_d3 : STD_LOGIC;
signal wmemsel_d4 : STD_LOGIC;
signal wmemsel_d5 : STD_LOGIC;
signal wmemsel_d6 : STD_LOGIC;
signal wmemsel_d7 : STD_LOGIC;
signal romedatao_d1 : T_ROM1DATAO;
signal romodatao_d1 : T_ROM1DATAO;
signal romedatao_d2 : T_ROM1DATAO;
signal romodatao_d2 : T_ROM1DATAO;
signal romedatao_d3 : T_ROM1DATAO;
signal romodatao_d3 : T_ROM1DATAO;
signal dcto_1 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
signal dcto_2 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
signal dcto_3 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
signal dcto_4 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
signal fpr_out : STD_LOGIC_VECTOR(DA_W-12-1 downto 0);
component FinitePrecRndNrst is
generic
(
C_IN_SZ : natural := 37;
C_OUT_SZ : natural := 16;
C_FRAC_SZ : natural := 15
);
port (
CLK : in std_logic;
RST : in std_logic;
datain : in STD_LOGIC_VECTOR(C_IN_SZ-1 downto 0);
dataval : in std_logic;
dataout : out STD_LOGIC_VECTOR(C_OUT_SZ-1 downto 0);
clip_inc : out std_logic;
dval_out : out std_logic
);
end component;
begin
ramwaddro <= ramwaddro_d6;
wmemsel <= wmemsel_d6; --wmemsel_d4;
odv <= ramwe_d6;
dcto <= STD_LOGIC_VECTOR(RESIZE(SIGNED(fpr_out),12));
ramdatai <= fpr_out;
U_FinitePrecRndNrst : FinitePrecRndNrst
generic map(
C_IN_SZ => DA_W,
C_OUT_SZ => DA_W-12,
C_FRAC_SZ => 12
)
port map(
CLK => clk,
RST => rst,
datain => dcto_4,
dataval => ramwe_d4,
dataout => fpr_out,
clip_inc => open,
dval_out => ramwe
);
process(clk,rst)
begin
if rst = '1' then
inpcnt_reg <= (others => '0');
latchbuf_reg <= (others => (others => '0'));
databuf_reg <= (others => (others => '0'));
stage2_reg <= '0';
stage2_cnt_reg <= (others => '1');
ramwe_s <= '0';
ramwaddro_s <= (others => '0');
col_reg <= (others => '0');
row_reg <= (others => '0');
wmemsel_reg <= '0';
col_2_reg <= (others => '0');
elsif clk = '1' and clk'event then
stage2_reg <= '0';
ramwe_s <= '0';
--------------------------------
-- 1st stage
--------------------------------
if idv = '1' then
inpcnt_reg <= inpcnt_reg + 1;
-- right shift input data
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
latchbuf_reg(N-1) <= SIGNED('0' & dcti) - LEVEL_SHIFT;
if inpcnt_reg = N-1 then
-- after this sum databuf_reg is in range of -256 to 254 (min to max)
databuf_reg(0) <= latchbuf_reg(1)+(SIGNED('0' & dcti) - LEVEL_SHIFT);
databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);
databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);
databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);
databuf_reg(4) <= latchbuf_reg(1)-(SIGNED('0' & dcti) - LEVEL_SHIFT);
databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);
databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);
databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);
stage2_reg <= '1';
end if;
end if;
--------------------------------
--------------------------------
-- 2nd stage
--------------------------------
if stage2_cnt_reg < N then
stage2_cnt_reg <= stage2_cnt_reg + 1;
-- write RAM
ramwe_s <= '1';
-- reverse col/row order for transposition purpose
ramwaddro_s <= STD_LOGIC_VECTOR(col_2_reg & row_reg);
-- increment column counter
col_reg <= col_reg + 1;
col_2_reg <= col_2_reg + 1;
-- finished processing one input row
if col_reg = 0 then
row_reg <= row_reg + 1;
-- switch to 2nd memory
if row_reg = N - 1 then
wmemsel_reg <= not wmemsel_reg;
col_reg <= (others => '0');
end if;
end if;
end if;
if stage2_reg = '1' then
stage2_cnt_reg <= (others => '0');
col_reg <= (0=>'1',others => '0');
col_2_reg <= (others => '0');
end if;
----------------------------------
end if;
end process;
-- output data pipeline
p_data_out_pipe : process(CLK, RST)
begin
if RST = '1' then
even_not_odd <= '0';
even_not_odd_d1 <= '0';
even_not_odd_d2 <= '0';
even_not_odd_d3 <= '0';
ramwe_d1 <= '0';
ramwe_d2 <= '0';
ramwe_d3 <= '0';
ramwe_d4 <= '0';
ramwe_d5 <= '0';
ramwe_d6 <= '0';
ramwaddro_d1 <= (others => '0');
ramwaddro_d2 <= (others => '0');
ramwaddro_d3 <= (others => '0');
ramwaddro_d4 <= (others => '0');
ramwaddro_d5 <= (others => '0');
ramwaddro_d6 <= (others => '0');
wmemsel_d1 <= '0';
wmemsel_d2 <= '0';
wmemsel_d3 <= '0';
wmemsel_d4 <= '0';
wmemsel_d5 <= '0';
wmemsel_d6 <= '0';
wmemsel_d7 <= '0';
dcto_1 <= (others => '0');
dcto_2 <= (others => '0');
dcto_3 <= (others => '0');
dcto_4 <= (others => '0');
elsif CLK'event and CLK = '1' then
even_not_odd <= stage2_cnt_reg(0);
even_not_odd_d1 <= even_not_odd;
even_not_odd_d2 <= even_not_odd_d1;
even_not_odd_d3 <= even_not_odd_d2;
ramwe_d1 <= ramwe_s;
ramwe_d2 <= ramwe_d1;
ramwe_d3 <= ramwe_d2;
ramwe_d4 <= ramwe_d3;
ramwe_d5 <= ramwe_d4;
ramwe_d6 <= ramwe_d5;
ramwaddro_d1 <= ramwaddro_s;
ramwaddro_d2 <= ramwaddro_d1;
ramwaddro_d3 <= ramwaddro_d2;
ramwaddro_d4 <= ramwaddro_d3;
ramwaddro_d5 <= ramwaddro_d4;
ramwaddro_d6 <= ramwaddro_d5;
wmemsel_d1 <= wmemsel_reg;
wmemsel_d2 <= wmemsel_d1;
wmemsel_d3 <= wmemsel_d2;
wmemsel_d4 <= wmemsel_d3;
wmemsel_d5 <= wmemsel_d4;
wmemsel_d6 <= wmemsel_d5;
wmemsel_d7 <= wmemsel_d6;
if even_not_odd = '0' then
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romedatao(0)),DA_W) +
(RESIZE(SIGNED(romedatao(1)),DA_W-1) & '0') +
(RESIZE(SIGNED(romedatao(2)),DA_W-2) & "00"),
DA_W));
else
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romodatao(0)),DA_W) +
(RESIZE(SIGNED(romodatao(1)),DA_W-1) & '0') +
(RESIZE(SIGNED(romodatao(2)),DA_W-2) & "00"),
DA_W));
end if;
if even_not_odd_d1 = '0' then
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romedatao_d1(3)),DA_W-3) & "000") +
(RESIZE(SIGNED(romedatao_d1(4)),DA_W-4) & "0000"),
DA_W));
else
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romodatao_d1(3)),DA_W-3) & "000") +
(RESIZE(SIGNED(romodatao_d1(4)),DA_W-4) & "0000"),
DA_W));
end if;
if even_not_odd_d2 = '0' then
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romedatao_d2(5)),DA_W-5) & "00000") +
(RESIZE(SIGNED(romedatao_d2(6)),DA_W-6) & "000000"),
DA_W));
else
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romodatao_d2(5)),DA_W-5) & "00000") +
(RESIZE(SIGNED(romodatao_d2(6)),DA_W-6) & "000000"),
DA_W));
end if;
if even_not_odd_d3 = '0' then
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romedatao_d3(7)),DA_W-7) & "0000000") -
(RESIZE(SIGNED(romedatao_d3(8)),DA_W-8) & "00000000"),
DA_W));
else
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romodatao_d3(7)),DA_W-7) & "0000000") -
(RESIZE(SIGNED(romodatao_d3(8)),DA_W-8) & "00000000"),
DA_W));
end if;
end if;
end process;
-- read precomputed MAC results from LUT
p_romaddr : process(CLK, RST)
begin
if RST = '1' then
romeaddro <= (others => (others => '0'));
romoaddro <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
for i in 0 to 8 loop
-- even
romeaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(i) &
databuf_reg(1)(i) &
databuf_reg(2)(i) &
databuf_reg(3)(i);
-- odd
romoaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(i) &
databuf_reg(5)(i) &
databuf_reg(6)(i) &
databuf_reg(7)(i);
end loop;
end if;
end process;
p_romdatao_d1 : process(CLK, RST)
begin
if RST = '1' then
romedatao_d1 <= (others => (others => '0'));
romodatao_d1 <= (others => (others => '0'));
romedatao_d2 <= (others => (others => '0'));
romodatao_d2 <= (others => (others => '0'));
romedatao_d3 <= (others => (others => '0'));
romodatao_d3 <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
romedatao_d1 <= romedatao;
romodatao_d1 <= romodatao;
romedatao_d2 <= romedatao_d1;
romodatao_d2 <= romodatao_d1;
romedatao_d3 <= romedatao_d2;
romodatao_d3 <= romodatao_d2;
end if;
end process;
end RTL;
--------------------------------------------------------------------------------
| lgpl-3.0 | c5928a91aacc1c15f3541fdf4c2f6cc7 | 0.44576 | 3.535723 | false | false | false | false |
cnplab/blockmon | fw-combo/src/netcope-sim/models/ib_pkg.vhd | 1 | 8,965 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- ib_pkg.vhd: Internal Bus Package
-- Copyright (C) 2006 CESNET
-- Author(s): Petr Kobiersky <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: ib_pkg.vhd 12021 2011-04-15 08:23:45Z kastovsky $
--
-- TODO:
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use IEEE.numeric_std.all;
use std.textio.all;
-- ----------------------------------------------------------------------------
-- Internal Bus Package
-- ----------------------------------------------------------------------------
package ib_pkg is
-- Address
constant C_IB_TRANS_TYPE_WIDTH : integer := 3;
constant C_IB_FLAG_WIDTH : integer := 1;
constant C_IB_LENGTH_WIDTH : integer := 12;
-- IB Transaction Type ('NORMAL/COMPL' 'LOCAL/GLOBAL' 'WRITE/READ')
constant C_IB_L2LW_TRANSACTION : std_logic_vector(3 downto 0) := "0001";
constant C_IB_L2LR_TRANSACTION : std_logic_vector(3 downto 0) := "0000";
constant C_IB_L2GW_TRANSACTION : std_logic_vector(3 downto 0) := "0011";
constant C_IB_G2LR_TRANSACTION : std_logic_vector(3 downto 0) := "0010";
constant C_IB_RD_COMPL_TRANSACTION : std_logic_vector(3 downto 0) := "0101";
constant C_IB_RD_LASTCOMPL_TRANSACTION : std_logic_vector(3 downto 0) := "1101";
-- Fourth bit of type (15 bit) is reserved for 1) Ack flag - for L2LW transaction
-- 2) Last fragment flag - for G2LR
-- Internal 64 bit Bus Link
type t_internal_bus_link64 is record
DATA : std_logic_vector(63 downto 0);
SOP_N : std_logic;
EOP_N : std_logic;
SRC_RDY_N : std_logic;
DST_RDY_N : std_logic;
end record;
-- Internal 64 bit Bus
type t_internal_bus64 is record
UP : t_internal_bus_link64;
DOWN : t_internal_bus_link64;
end record;
-- Internal Bus Write Interface
type t_ibmi_write64 is record
ADDR : std_logic_vector(31 downto 0); -- Address
DATA : std_logic_vector(63 downto 0); -- Data
BE : std_logic_vector(7 downto 0); -- Byte Enable
REQ : std_logic; -- Write Request
RDY : std_logic; -- Ready
LENGTH : std_logic_vector(11 downto 0); -- Length
SOF : std_logic; -- Start of Frame
EOF : std_logic; -- End of Frame
end record;
-- Internal Bus Read Interface (Simple)
type t_ibmi_read64s is record
-- Input interface
ADDR : std_logic_vector(31 downto 0); -- Address
BE : std_logic_vector(7 downto 0); -- Byte Enable
-- LENGTH : std_logic_vector(11 downto 0); -- Length
REQ : std_logic; -- Read Request
ARDY : std_logic; -- Address Ready
SOF_IN : std_logic; -- Start of Frame (Input)
EOF_IN : std_logic; -- End of Frame (Intput)
-- Output interface
DATA : std_logic_vector(63 downto 0); -- Read Data
SRC_RDY : std_logic; -- Data Ready
DST_RDY : std_logic; -- Endpoint Ready
end record;
-- Internal Bus Read Interface (Combined without Tags)
type t_ibmi_read64c is record
-- Input interface
ADDR : std_logic_vector(31 downto 0); -- Address
BE : std_logic_vector(7 downto 0); -- Byte Enable
LENGTH : std_logic_vector(11 downto 0); -- Length
REQ : std_logic; -- Read Request
ARDY : std_logic; -- Address Ready
ACCEPT : std_logic; -- Accept
SOF_IN : std_logic; -- Start of Frame (Input)
EOF_IN : std_logic; -- End of Frame (Intput)
-- Output interface
DATA : std_logic_vector(63 downto 0); -- Read Data
SRC_RDY : std_logic; -- Data Ready
DST_RDY : std_logic; -- Endpoint Ready
SOF_OUT : std_logic; -- Start of Frame (Output)
EOF_OUT : std_logic; -- End of Frame (Output)
end record;
-- Internal Bus Read Interface (Combined with Tags)
type t_ibmi_read64ct is record
-- Input interface
ADDR : std_logic_vector(31 downto 0); -- Address
BE : std_logic_vector(7 downto 0); -- Byte Enable
LENGTH : std_logic_vector(11 downto 0); -- Length
TAG_IN : std_logic_vector(7 downto 0); -- Read Transaction Tag (Input)
REQ : std_logic; -- Read Request
ARDY : std_logic; -- Address Ready
ACCEPT : std_logic; -- Accept
SOF_IN : std_logic; -- Start of Frame (Input)
EOF_IN : std_logic; -- End of Frame (Intput)
-- Output interface
TAG_OUT : std_logic_vector(15 downto 0); -- Read Transaction Tag (Output)
DATA : std_logic_vector(63 downto 0); -- Read Data
SRC_RDY : std_logic; -- Data Ready
DST_RDY : std_logic; -- Endpoint Ready
SOF_OUT : std_logic; -- Start of Frame (Output)
EOF_OUT : std_logic; -- End of Frame (Output)
end record;
-- Internal Bus BM Interface
type t_ibbm_64 is record
-- Master Interface Input
GLOBAL_ADDR : std_logic_vector(63 downto 0); -- Global Address
LOCAL_ADDR : std_logic_vector(31 downto 0); -- Local Address
LENGTH : std_logic_vector(11 downto 0); -- Length
TAG : std_logic_vector(15 downto 0); -- Operation TAG
TRANS_TYPE : std_logic_vector(1 downto 0); -- Type of transaction
REQ : std_logic; -- Request
-- Master Output interface
ACK : std_logic; -- Ack
OP_TAG : std_logic_vector(15 downto 0); -- Operation TAG
OP_DONE : std_logic; -- Acknowledge
end record;
end ib_pkg;
-- ----------------------------------------------------------------------------
-- Internal Bus Package
-- ----------------------------------------------------------------------------
package body ib_pkg is
end ib_pkg;
| bsd-3-clause | ce09ed996bc4b0e971df5b48b34c77de | 0.518907 | 4.326737 | false | false | false | false |
cnplab/blockmon | fw-combo/src/IPFIX/comp/mi32_async_arch_norec.vhd | 1 | 6,971 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- mi32_async_arch_norec.vhd: Architecture of mi32_async component without
-- records
-- Copyright (C) 2006 CESNET
-- Author(s): Viktor Pus <[email protected]>
-- Jiri Matousek <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: mi32_async_arch_norec.vhd 6111 2008-10-26 22:49:39Z xmatou06 $
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- ----------------------------------------------------------------------------
-- Architecture
-- ----------------------------------------------------------------------------
architecture full of MI32_ASYNC_NOREC is
-- Asynchronous signals
signal req : std_logic;
signal regasync_req_fall : std_logic;
signal regasync_req_rise : std_logic;
signal ack : std_logic;
signal regasync_ack_fall : std_logic;
signal regasync_ack_rise : std_logic;
-- Control signals
signal slave_en : std_logic;
signal done : std_logic;
signal mi_m_ardy2 : std_logic;
signal mi_s_drdy2 : std_logic;
-- Delayed signals in simulation
signal s_drdy_d : std_logic;
signal s_drd_d : std_logic_vector(31 downto 0);
-- Reigsters in direction Master -> Slave
signal reg_dwr : std_logic_vector(31 downto 0);
signal reg_addr : std_logic_vector(31 downto 0);
signal reg_rd : std_logic;
signal reg_wr : std_logic;
signal reg_be : std_logic_vector(3 downto 0);
-- Registers in direction Slave -> Master
signal reg_drd : std_logic_vector(31 downto 0);
signal reg_drdy : std_logic;
begin
-- regasync_req_fall register
process(RESET, CLK_S)
begin
if (RESET = '1') then
regasync_req_fall <= '0';
elsif (CLK_S'event AND CLK_S = '0') then
regasync_req_fall <= req;
end if;
end process;
-- regasync_req_rise register
process(RESET, CLK_S)
begin
if (RESET = '1') then
regasync_req_rise <= '0';
elsif (CLK_S'event AND CLK_S = '1') then
regasync_req_rise <= regasync_req_fall;
end if;
end process;
-- regasync_ack_fall register
process(RESET, CLK_M)
begin
if (RESET = '1') then
regasync_ack_fall <= '0';
elsif (CLK_M'event AND CLK_M = '0') then
regasync_ack_fall <= ack;
end if;
end process;
-- regasync_ack_rise register
process(RESET, CLK_M)
begin
if (RESET = '1') then
regasync_ack_rise <= '0';
elsif (CLK_M'event AND CLK_M = '1') then
regasync_ack_rise <= regasync_ack_fall;
end if;
end process;
fsm_master : entity work.MI32_ASYNC_FSMM
port map(
RESET => RESET,
CLK => CLK_M,
RD => MI_M_RD,
WR => MI_M_WR,
ACK => regasync_ack_rise,
REQ => req,
ARDY => mi_m_ardy2,
DONE => done
);
fsm_slave : entity work.MI32_ASYNC_FSMS
port map(
RESET => RESET,
CLK => CLK_S,
REQ => regasync_req_rise,
DRDY => mi_s_drdy2,
ARDY => MI_S_ARDY,
ACK => ack,
EN => slave_en
);
-- process(CLK_S)
-- begin
-- if reg_wr = '1' then
-- mi_s_drdy2 <= '1';
-- else
-- mi_s_drdy2 <= MI_S.DRDY;
-- end if;
-- end process;
mi_s_drdy2 <= '1' when reg_wr = '1' else
MI_S_DRDY;
s_drdy_d <= MI_S_DRDY
-- pragma translate off
after 1 ns
-- pragma translate on
;
s_drd_d <= MI_S_DRD
-- pragma translate off
after 1 ns
-- pragma translate on
;
reg_master_to_slave : process(CLK_M, RESET)
begin
if RESET = '1' then
reg_dwr <= (others => '0');
reg_addr <= (others => '0');
reg_rd <= '0';
reg_wr <= '0';
reg_be <= (others => '0');
elsif CLK_M'event and CLK_M = '1' then
if mi_m_ardy2 = '1' and (MI_M_RD = '1' or MI_M_WR = '1') then
reg_dwr <= MI_M_DWR;
reg_addr <= MI_M_ADDR;
reg_rd <= MI_M_RD;
reg_wr <= MI_M_WR;
reg_be <= MI_M_BE;
end if;
end if;
end process;
reg_slave_to_master : process(CLK_S, RESET)
begin
if RESET = '1' then
reg_drd <= (others => '0');
elsif CLK_S'event and CLK_S = '1' then
if mi_s_drdy2 = '1' then
reg_drd <= s_drd_d;
end if;
end if;
end process;
reg_drdy_slave_to_master : process(CLK_S, RESET)
begin
if RESET = '1' then
reg_drdy <= '0';
elsif CLK_S'event and CLK_S = '1' then
if mi_s_drdy2 = '1' then
reg_drdy <= s_drdy_d;
end if;
end if;
end process;
-- Port mapping
MI_M_ARDY <= mi_m_ardy2 and (MI_M_RD or MI_M_WR);
MI_M_DRDY <= reg_drdy when done = '1' else
'0';
MI_M_DRD <= reg_drd;
MI_S_DWR <= reg_dwr;
MI_S_ADDR <= reg_addr;
MI_S_RD <= reg_rd when slave_en = '1' else
'0';
MI_S_WR <= reg_wr when slave_en = '1' else
'0';
MI_S_BE <= reg_be;
end architecture full;
| bsd-3-clause | da84ef4517f944148fd71f3eef112bc7 | 0.57524 | 3.427237 | false | false | false | false |
cnplab/blockmon | fw-combo/src/IPFIX/comp/dec1fn.vhd | 1 | 3,339 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
--
-- dec1fn.vhd: Decoder 1 from n
-- Copyright (C) 2003 CESNET
-- Author(s): Martinek Tomas <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: dec1fn.vhd 9364 2009-07-14 07:06:35Z xplese01 $
--
-- TODO:
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use work.math_pack.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity dec1fn is
generic(
ITEMS : integer := 8
);
port(
ADDR : in std_logic_vector(log2(ITEMS)-1 downto 0);
DO : out std_logic_vector(ITEMS-1 downto 0)
);
end entity dec1fn;
-- ----------------------------------------------------------------------------
-- Architecture declaration
-- ----------------------------------------------------------------------------
architecture behavioral of dec1fn is
begin
process(ADDR)
begin
DO <= (others => '0');
for i in 0 to (ITEMS-1) loop
if (conv_std_logic_vector(i, log2(ITEMS)) = ADDR) then
DO(i) <= '1';
end if;
end loop;
end process;
end architecture behavioral;
| bsd-3-clause | a3aa22f4c5ef7e08139ed090c08ea0e7 | 0.583408 | 4.536685 | false | false | false | false |
cnplab/blockmon | fw-combo/src/IPFIX/combov2_core.vhd | 1 | 52,797 | -- combov2_core.vhd : Combov2 NetCOPE core
-- Copyright (C) 2008 CESNET
-- Author(s): Martin Kosek <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id$
--
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.combov2_core_const.all;
use work.combov2_user_const.all;
use work.math_pack.all;
use work.ibuf_general_pkg.all;
use work.fl_pkg.all;
use work.addr_space.all;
architecture full of COMBOV2_CORE is
-- ----------------------------------------------------------------------------
-- Components declaration
-- ----------------------------------------------------------------------------
component network_mod_10g2_64 is
port(
-- Clock signal for user interface
USER_CLK : in std_logic;
-- FrameLink reset
FL_RESET : in std_logic;
-- ICS reset
BUSRESET : in std_logic;
-- 2 XGMII INTERFACES
-- RX
XGMII_RESET : in std_logic_vector( 1 downto 0);
XGMII_RXCLK : in std_logic_vector( 1 downto 0);
XGMII_RXD : in std_logic_vector(127 downto 0);
XGMII_RXC : in std_logic_vector( 15 downto 0);
-- TX
XGMII_TXCLK : in std_logic_vector( 1 downto 0);
XGMII_TXD : out std_logic_vector(127 downto 0);
XGMII_TXC : out std_logic_vector( 15 downto 0);
-- USER INTERFACE
-- Network interface 0
IBUF0_TX_SOF_N : out std_logic;
IBUF0_TX_SOP_N : out std_logic;
IBUF0_TX_EOP_N : out std_logic;
IBUF0_TX_EOF_N : out std_logic;
IBUF0_TX_SRC_RDY_N : out std_logic;
IBUF0_TX_DST_RDY_N : in std_logic;
IBUF0_TX_DATA : out std_logic_vector(63 downto 0);
IBUF0_TX_REM : out std_logic_vector(2 downto 0);
-- PACODAG interface
IBUF0_CTRL_CLK : out std_logic;
IBUF0_CTRL_DATA : in std_logic_vector(63 downto 0);
IBUF0_CTRL_REM : in std_logic_vector(2 downto 0);
IBUF0_CTRL_SRC_RDY_N : in std_logic;
IBUF0_CTRL_SOP_N : in std_logic;
IBUF0_CTRL_EOP_N : in std_logic;
IBUF0_CTRL_DST_RDY_N : out std_logic;
IBUF0_CTRL_RDY : in std_logic;
-- IBUF status interface
IBUF0_SOP : out std_logic;
IBUF0_PAYLOAD_LEN : out std_logic_vector(15 downto 0);
IBUF0_FRAME_ERROR : out std_logic; -- 0: OK, 1: Error occured
IBUF0_CRC_CHECK_FAILED:out std_logic; -- 0: OK, 1: Bad CRC
IBUF0_MAC_CHECK_FAILED:out std_logic; -- 0: OK, 1: Bad MAC
IBUF0_LEN_BELOW_MIN : out std_logic; -- 0: OK, 1: Length is below min
IBUF0_LEN_OVER_MTU : out std_logic; -- 0: OK, 1: Length is over MTU
IBUF0_STAT_DV : out std_logic;
-- Signals active in '1' for one cycle for every processed packet
IBUF0_FRAME_RECEIVED : out std_logic;
IBUF0_FRAME_DISCARDED : out std_logic;
-- When active in '1' frame was discarded due to buffer overflow. Can be active only together
-- with FRAME_DISCARDED
IBUF0_BUFFER_OVF : out std_logic;
-- Sampling unit interface
IBUF0_SAU_ACCEPT : in std_logic;
IBUF0_SAU_DV : in std_logic;
-- Output buffer interface
OBUF0_RX_SOF_N : in std_logic;
OBUF0_RX_SOP_N : in std_logic;
OBUF0_RX_EOP_N : in std_logic;
OBUF0_RX_EOF_N : in std_logic;
OBUF0_RX_SRC_RDY_N : in std_logic;
OBUF0_RX_DST_RDY_N : out std_logic;
OBUF0_RX_DATA : in std_logic_vector(63 downto 0);
OBUF0_RX_REM : in std_logic_vector(2 downto 0);
-- Network interface 1 --------------------------------------------------
IBUF1_TX_SOF_N : out std_logic;
IBUF1_TX_SOP_N : out std_logic;
IBUF1_TX_EOP_N : out std_logic;
IBUF1_TX_EOF_N : out std_logic;
IBUF1_TX_SRC_RDY_N : out std_logic;
IBUF1_TX_DST_RDY_N : in std_logic;
IBUF1_TX_DATA : out std_logic_vector(63 downto 0);
IBUF1_TX_REM : out std_logic_vector(2 downto 0);
-- PACODAG interface
IBUF1_CTRL_CLK : out std_logic;
IBUF1_CTRL_DATA : in std_logic_vector(63 downto 0);
IBUF1_CTRL_REM : in std_logic_vector(2 downto 0);
IBUF1_CTRL_SRC_RDY_N : in std_logic;
IBUF1_CTRL_SOP_N : in std_logic;
IBUF1_CTRL_EOP_N : in std_logic;
IBUF1_CTRL_DST_RDY_N : out std_logic;
IBUF1_CTRL_RDY : in std_logic;
-- IBUF status interface
IBUF1_SOP : out std_logic;
IBUF1_PAYLOAD_LEN : out std_logic_vector(15 downto 0);
IBUF1_FRAME_ERROR : out std_logic; -- 0: OK, 1: Error occured
IBUF1_CRC_CHECK_FAILED:out std_logic; -- 0: OK, 1: Bad CRC
IBUF1_MAC_CHECK_FAILED:out std_logic; -- 0: OK, 1: Bad MAC
IBUF1_LEN_BELOW_MIN : out std_logic; -- 0: OK, 1: Length is below min
IBUF1_LEN_OVER_MTU : out std_logic; -- 0: OK, 1: Length is over MTU
IBUF1_STAT_DV : out std_logic;
-- Signals active in '1' for one cycle for every processed packet
IBUF1_FRAME_RECEIVED : out std_logic;
IBUF1_FRAME_DISCARDED : out std_logic;
-- When active in '1' frame was discarded due to buffer overflow. Can be active only together
-- with FRAME_DISCARDED
IBUF1_BUFFER_OVF : out std_logic;
-- Sampling unit interface
IBUF1_SAU_ACCEPT : in std_logic;
IBUF1_SAU_DV : in std_logic;
-- Output buffer interface
OBUF1_RX_SOF_N : in std_logic;
OBUF1_RX_SOP_N : in std_logic;
OBUF1_RX_EOP_N : in std_logic;
OBUF1_RX_EOF_N : in std_logic;
OBUF1_RX_SRC_RDY_N : in std_logic;
OBUF1_RX_DST_RDY_N : out std_logic;
OBUF1_RX_DATA : in std_logic_vector(63 downto 0);
OBUF1_RX_REM : in std_logic_vector(2 downto 0);
-- Led interface
IBUF_LED : out std_logic_vector(1 downto 0);
OBUF_LED : out std_logic_vector(1 downto 0);
-- Link presence interface
LINK0 : out std_logic;
LINK1 : out std_logic;
-- MI32 interface
MI32_DWR : in std_logic_vector(31 downto 0);
MI32_ADDR : in std_logic_vector(31 downto 0);
MI32_RD : in std_logic;
MI32_WR : in std_logic;
MI32_BE : in std_logic_vector(3 downto 0);
MI32_DRD : out std_logic_vector(31 downto 0);
MI32_ARDY : out std_logic;
MI32_DRDY : out std_logic
);
end component;
component NETWORK_MOD_10G2_64_16KBYTE is
port(
-- Clock signal for user interface
USER_CLK : in std_logic;
-- FrameLink reset
FL_RESET : in std_logic;
-- ICS reset
BUSRESET : in std_logic;
-- 2 XGMII INTERFACES
-- RX
XGMII_RESET : in std_logic_vector( 1 downto 0);
XGMII_RXCLK : in std_logic_vector( 1 downto 0);
XGMII_RXD : in std_logic_vector(127 downto 0);
XGMII_RXC : in std_logic_vector( 15 downto 0);
-- TX
XGMII_TXCLK : in std_logic_vector( 1 downto 0);
XGMII_TXD : out std_logic_vector(127 downto 0);
XGMII_TXC : out std_logic_vector( 15 downto 0);
-- USER INTERFACE
-- Network interface 0
IBUF0_TX_SOF_N : out std_logic;
IBUF0_TX_SOP_N : out std_logic;
IBUF0_TX_EOP_N : out std_logic;
IBUF0_TX_EOF_N : out std_logic;
IBUF0_TX_SRC_RDY_N : out std_logic;
IBUF0_TX_DST_RDY_N : in std_logic;
IBUF0_TX_DATA : out std_logic_vector(63 downto 0);
IBUF0_TX_REM : out std_logic_vector(2 downto 0);
-- PACODAG interface
IBUF0_CTRL_CLK : out std_logic;
IBUF0_CTRL_DATA : in std_logic_vector(63 downto 0);
IBUF0_CTRL_REM : in std_logic_vector(2 downto 0);
IBUF0_CTRL_SRC_RDY_N : in std_logic;
IBUF0_CTRL_SOP_N : in std_logic;
IBUF0_CTRL_EOP_N : in std_logic;
IBUF0_CTRL_DST_RDY_N : out std_logic;
IBUF0_CTRL_RDY : in std_logic;
-- IBUF status interface
IBUF0_SOP : out std_logic;
IBUF0_PAYLOAD_LEN : out std_logic_vector(15 downto 0);
IBUF0_FRAME_ERROR : out std_logic; -- 0: OK, 1: Error occured
IBUF0_CRC_CHECK_FAILED:out std_logic; -- 0: OK, 1: Bad CRC
IBUF0_MAC_CHECK_FAILED:out std_logic; -- 0: OK, 1: Bad MAC
IBUF0_LEN_BELOW_MIN : out std_logic; -- 0: OK, 1: Length is below min
IBUF0_LEN_OVER_MTU : out std_logic; -- 0: OK, 1: Length is over MTU
IBUF0_STAT_DV : out std_logic;
-- Signals active in '1' for one cycle for every processed packet
IBUF0_FRAME_RECEIVED : out std_logic;
IBUF0_FRAME_DISCARDED : out std_logic;
-- When active in '1' frame was discarded due to buffer overflow. Can be active only together
-- with FRAME_DISCARDED
IBUF0_BUFFER_OVF : out std_logic;
-- Sampling unit interface
IBUF0_SAU_ACCEPT : in std_logic;
IBUF0_SAU_DV : in std_logic;
-- Output buffer interface
OBUF0_RX_SOF_N : in std_logic;
OBUF0_RX_SOP_N : in std_logic;
OBUF0_RX_EOP_N : in std_logic;
OBUF0_RX_EOF_N : in std_logic;
OBUF0_RX_SRC_RDY_N : in std_logic;
OBUF0_RX_DST_RDY_N : out std_logic;
OBUF0_RX_DATA : in std_logic_vector(63 downto 0);
OBUF0_RX_REM : in std_logic_vector(2 downto 0);
-- Network interface 1 --------------------------------------------------
IBUF1_TX_SOF_N : out std_logic;
IBUF1_TX_SOP_N : out std_logic;
IBUF1_TX_EOP_N : out std_logic;
IBUF1_TX_EOF_N : out std_logic;
IBUF1_TX_SRC_RDY_N : out std_logic;
IBUF1_TX_DST_RDY_N : in std_logic;
IBUF1_TX_DATA : out std_logic_vector(63 downto 0);
IBUF1_TX_REM : out std_logic_vector(2 downto 0);
-- PACODAG interface
IBUF1_CTRL_CLK : out std_logic;
IBUF1_CTRL_DATA : in std_logic_vector(63 downto 0);
IBUF1_CTRL_REM : in std_logic_vector(2 downto 0);
IBUF1_CTRL_SRC_RDY_N : in std_logic;
IBUF1_CTRL_SOP_N : in std_logic;
IBUF1_CTRL_EOP_N : in std_logic;
IBUF1_CTRL_DST_RDY_N : out std_logic;
IBUF1_CTRL_RDY : in std_logic;
-- IBUF status interface
IBUF1_SOP : out std_logic;
IBUF1_PAYLOAD_LEN : out std_logic_vector(15 downto 0);
IBUF1_FRAME_ERROR : out std_logic; -- 0: OK, 1: Error occured
IBUF1_CRC_CHECK_FAILED:out std_logic; -- 0: OK, 1: Bad CRC
IBUF1_MAC_CHECK_FAILED:out std_logic; -- 0: OK, 1: Bad MAC
IBUF1_LEN_BELOW_MIN : out std_logic; -- 0: OK, 1: Length is below min
IBUF1_LEN_OVER_MTU : out std_logic; -- 0: OK, 1: Length is over MTU
IBUF1_STAT_DV : out std_logic;
-- Signals active in '1' for one cycle for every processed packet
IBUF1_FRAME_RECEIVED : out std_logic;
IBUF1_FRAME_DISCARDED : out std_logic;
-- When active in '1' frame was discarded due to buffer overflow. Can be active only together
-- with FRAME_DISCARDED
IBUF1_BUFFER_OVF : out std_logic;
-- Sampling unit interface
IBUF1_SAU_ACCEPT : in std_logic;
IBUF1_SAU_DV : in std_logic;
-- Output buffer interface
OBUF1_RX_SOF_N : in std_logic;
OBUF1_RX_SOP_N : in std_logic;
OBUF1_RX_EOP_N : in std_logic;
OBUF1_RX_EOF_N : in std_logic;
OBUF1_RX_SRC_RDY_N : in std_logic;
OBUF1_RX_DST_RDY_N : out std_logic;
OBUF1_RX_DATA : in std_logic_vector(63 downto 0);
OBUF1_RX_REM : in std_logic_vector(2 downto 0);
-- Led interface
IBUF_LED : out std_logic_vector(1 downto 0);
OBUF_LED : out std_logic_vector(1 downto 0);
-- Link presence interface
LINK0 : out std_logic;
LINK1 : out std_logic;
-- MI32 interface
MI32_DWR : in std_logic_vector(31 downto 0);
MI32_ADDR : in std_logic_vector(31 downto 0);
MI32_RD : in std_logic;
MI32_WR : in std_logic;
MI32_BE : in std_logic_vector(3 downto 0);
MI32_DRD : out std_logic_vector(31 downto 0);
MI32_ARDY : out std_logic;
MI32_DRDY : out std_logic
);
end component;
component DMA_MOD_2X64B_RXTX_16KBYTE_GEN is
port(
-- ICS Clock (IB and LB)
CLK : in std_logic;
RESET : in std_logic;
RX_INTERRUPT : out std_logic;
TX_INTERRUPT : out std_logic;
-- network interfaces interface
-- input interface
RX0_DATA : in std_logic_vector(63 downto 0);
RX0_DREM : in std_logic_vector(2 downto 0);
RX0_SOF_N : in std_logic;
RX0_EOF_N : in std_logic;
RX0_SOP_N : in std_logic;
RX0_EOP_N : in std_logic;
RX0_SRC_RDY_N : in std_logic;
RX0_DST_RDY_N : out std_logic;
RX1_DATA : in std_logic_vector(63 downto 0);
RX1_DREM : in std_logic_vector(2 downto 0);
RX1_SOF_N : in std_logic;
RX1_EOF_N : in std_logic;
RX1_SOP_N : in std_logic;
RX1_EOP_N : in std_logic;
RX1_SRC_RDY_N : in std_logic;
RX1_DST_RDY_N : out std_logic;
-- output interfaces
TX0_DATA : out std_logic_vector(63 downto 0);
TX0_DREM : out std_logic_vector(2 downto 0);
TX0_SOF_N : out std_logic;
TX0_EOF_N : out std_logic;
TX0_SOP_N : out std_logic;
TX0_EOP_N : out std_logic;
TX0_SRC_RDY_N : out std_logic;
TX0_DST_RDY_N : in std_logic;
TX1_DATA : out std_logic_vector(63 downto 0);
TX1_DREM : out std_logic_vector(2 downto 0);
TX1_SOF_N : out std_logic;
TX1_EOF_N : out std_logic;
TX1_SOP_N : out std_logic;
TX1_EOP_N : out std_logic;
TX1_SRC_RDY_N : out std_logic;
TX1_DST_RDY_N : in std_logic;
-- Internal Bus
IB_DOWN_DATA : in std_logic_vector(63 downto 0);
IB_DOWN_SOF_N : in std_logic;
IB_DOWN_EOF_N : in std_logic;
IB_DOWN_SRC_RDY_N : in std_logic;
IB_DOWN_DST_RDY_N : out std_logic;
IB_UP_DATA : out std_logic_vector(63 downto 0);
IB_UP_SOF_N : out std_logic;
IB_UP_EOF_N : out std_logic;
IB_UP_SRC_RDY_N : out std_logic;
IB_UP_DST_RDY_N : in std_logic;
-- MI32 interface
MI32_DWR : in std_logic_vector(31 downto 0);
MI32_ADDR : in std_logic_vector(31 downto 0);
MI32_RD : in std_logic;
MI32_WR : in std_logic;
MI32_BE : in std_logic_vector(3 downto 0);
MI32_DRD : out std_logic_vector(31 downto 0);
MI32_ARDY : out std_logic;
MI32_DRDY : out std_logic
);
end component;
component DMA_MOD_2x64b_RXTX_GEN is
port(
-- ICS Clock (IB and LB)
CLK : in std_logic;
RESET : in std_logic;
RX_INTERRUPT : out std_logic;
TX_INTERRUPT : out std_logic;
-- network interfaces interface
-- input interface
RX0_DATA : in std_logic_vector(63 downto 0);
RX0_DREM : in std_logic_vector(2 downto 0);
RX0_SOF_N : in std_logic;
RX0_EOF_N : in std_logic;
RX0_SOP_N : in std_logic;
RX0_EOP_N : in std_logic;
RX0_SRC_RDY_N : in std_logic;
RX0_DST_RDY_N : out std_logic;
RX1_DATA : in std_logic_vector(63 downto 0);
RX1_DREM : in std_logic_vector(2 downto 0);
RX1_SOF_N : in std_logic;
RX1_EOF_N : in std_logic;
RX1_SOP_N : in std_logic;
RX1_EOP_N : in std_logic;
RX1_SRC_RDY_N : in std_logic;
RX1_DST_RDY_N : out std_logic;
-- output interfaces
TX0_DATA : out std_logic_vector(63 downto 0);
TX0_DREM : out std_logic_vector(2 downto 0);
TX0_SOF_N : out std_logic;
TX0_EOF_N : out std_logic;
TX0_SOP_N : out std_logic;
TX0_EOP_N : out std_logic;
TX0_SRC_RDY_N : out std_logic;
TX0_DST_RDY_N : in std_logic;
TX1_DATA : out std_logic_vector(63 downto 0);
TX1_DREM : out std_logic_vector(2 downto 0);
TX1_SOF_N : out std_logic;
TX1_EOF_N : out std_logic;
TX1_SOP_N : out std_logic;
TX1_EOP_N : out std_logic;
TX1_SRC_RDY_N : out std_logic;
TX1_DST_RDY_N : in std_logic;
-- Internal Bus
IB_DOWN_DATA : in std_logic_vector(63 downto 0);
IB_DOWN_SOF_N : in std_logic;
IB_DOWN_EOF_N : in std_logic;
IB_DOWN_SRC_RDY_N : in std_logic;
IB_DOWN_DST_RDY_N : out std_logic;
IB_UP_DATA : out std_logic_vector(63 downto 0);
IB_UP_SOF_N : out std_logic;
IB_UP_EOF_N : out std_logic;
IB_UP_SRC_RDY_N : out std_logic;
IB_UP_DST_RDY_N : in std_logic;
-- MI32 interface
MI32_DWR : in std_logic_vector(31 downto 0);
MI32_ADDR : in std_logic_vector(31 downto 0);
MI32_RD : in std_logic;
MI32_WR : in std_logic;
MI32_BE : in std_logic_vector(3 downto 0);
MI32_DRD : out std_logic_vector(31 downto 0);
MI32_ARDY : out std_logic;
MI32_DRDY : out std_logic
);
end component;
component DMA_MOD_64b_8RX2TX_GEN is
port(
-- ICS Clock and RESET - drives the whole module
CLK : in std_logic;
RESET : in std_logic;
-- Synchronous at CLK
RX_INTERRUPT : out std_logic;
TX_INTERRUPT : out std_logic;
-- input interface
RX_DATA : in std_logic_vector(63 downto 0);
RX_DREM : in std_logic_vector(2 downto 0);
RX_SOF_N : in std_logic;
RX_EOF_N : in std_logic;
RX_SOP_N : in std_logic;
RX_EOP_N : in std_logic;
RX_SRC_RDY_N : in std_logic;
RX_DST_RDY_N : out std_logic_vector(7 downto 0);
-- Determine the number of channel. Must be valid for each data word.
RX_CHANNEL : in std_logic_vector(2 downto 0);
-- output interfaces
TX0_DATA : out std_logic_vector(63 downto 0);
TX0_DREM : out std_logic_vector(2 downto 0);
TX0_SOF_N : out std_logic;
TX0_EOF_N : out std_logic;
TX0_SOP_N : out std_logic;
TX0_EOP_N : out std_logic;
TX0_SRC_RDY_N : out std_logic;
TX0_DST_RDY_N : in std_logic;
TX1_DATA : out std_logic_vector(63 downto 0);
TX1_DREM : out std_logic_vector(2 downto 0);
TX1_SOF_N : out std_logic;
TX1_EOF_N : out std_logic;
TX1_SOP_N : out std_logic;
TX1_EOP_N : out std_logic;
TX1_SRC_RDY_N : out std_logic;
TX1_DST_RDY_N : in std_logic;
-- Internal Bus - CLK (ICS Clock)
IB_DOWN_DATA : in std_logic_vector(63 downto 0);
IB_DOWN_SOF_N : in std_logic;
IB_DOWN_EOF_N : in std_logic;
IB_DOWN_SRC_RDY_N:in std_logic;
IB_DOWN_DST_RDY_N:out std_logic;
IB_UP_DATA : out std_logic_vector(63 downto 0);
IB_UP_SOF_N : out std_logic;
IB_UP_EOF_N : out std_logic;
IB_UP_SRC_RDY_N: out std_logic;
IB_UP_DST_RDY_N: in std_logic;
-- MI32 Interface
MI32_DWR : in std_logic_vector(31 downto 0);
MI32_ADDR : in std_logic_vector(31 downto 0);
MI32_BE : in std_logic_vector(3 downto 0);
MI32_RD : in std_logic;
MI32_WR : in std_logic;
MI32_DRDY : out std_logic;
MI32_ARDY : out std_logic;
MI32_DRD : out std_logic_vector(31 downto 0)
);
end component;
component GICS_IB_SWITCH_SLAVE_SYNTH is
port(
CLK : in std_logic;
RESET : in std_logic;
PORT0_UP_DATA : out std_logic_vector(63 downto 0);
PORT0_UP_SOF_N : out std_logic;
PORT0_UP_EOF_N : out std_logic;
PORT0_UP_SRC_RDY_N : out std_logic;
PORT0_UP_DST_RDY_N : in std_logic;
PORT0_DOWN_DATA : in std_logic_vector(63 downto 0);
PORT0_DOWN_SOF_N : in std_logic;
PORT0_DOWN_EOF_N : in std_logic;
PORT0_DOWN_SRC_RDY_N : in std_logic;
PORT0_DOWN_DST_RDY_N : out std_logic;
PORT1_UP_DATA : in std_logic_vector(63 downto 0);
PORT1_UP_SOF_N : in std_logic;
PORT1_UP_EOF_N : in std_logic;
PORT1_UP_SRC_RDY_N : in std_logic;
PORT1_UP_DST_RDY_N : out std_logic;
PORT1_DOWN_DATA : out std_logic_vector(63 downto 0);
PORT1_DOWN_SOF_N : out std_logic;
PORT1_DOWN_EOF_N : out std_logic;
PORT1_DOWN_SRC_RDY_N : out std_logic;
PORT1_DOWN_DST_RDY_N : in std_logic;
PORT2_UP_DATA : in std_logic_vector(63 downto 0);
PORT2_UP_SOF_N : in std_logic;
PORT2_UP_EOF_N : in std_logic;
PORT2_UP_SRC_RDY_N : in std_logic;
PORT2_UP_DST_RDY_N : out std_logic;
PORT2_DOWN_DATA : out std_logic_vector(63 downto 0);
PORT2_DOWN_SOF_N : out std_logic;
PORT2_DOWN_EOF_N : out std_logic;
PORT2_DOWN_SRC_RDY_N : out std_logic;
PORT2_DOWN_DST_RDY_N : in std_logic
);
end component GICS_IB_SWITCH_SLAVE_SYNTH;
-- input buffer for differencial pair
component IBUFDS
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
-- output buffer for differencial pair
component OBUFDS
port (
OB : out std_logic;
O : out std_logic;
I : in std_logic
);
end component;
-- output buffer
component OBUF
port (
O : out std_logic;
I : in std_logic
);
end component;
-- ----------------------------------------------------------------------------
-- Signal declaration
-- ----------------------------------------------------------------------------
-- ------------------------------------------------------------------------
-- DMA module signals
-- ------------------------------------------------------------------------
-- DMA module buffers FrameLink
signal swbuf0_tx : t_fl64;
signal swbuf1_tx : t_fl64;
signal swbuf_rx : t_fl64;
signal swbuf_rx_dst_rdy_n : std_logic_vector(7 downto 0);
signal swbuf_rx_channel : std_logic_vector(2 downto 0);
-- Interrupts signals
signal rx_interrupt : std_logic;
signal tx_interrupt : std_logic;
signal reg_rx_interrupt : std_logic;
signal reg_tx_interrupt : std_logic;
signal reg_sysmon_alarm : std_logic;
signal sysmon_alarm_pulse : std_logic;
signal reg_sysmon_alarm_pulse : std_logic;
signal link0 : std_logic;
signal link1 : std_logic;
signal regasync_link0 : std_logic;
signal regasync_link1 : std_logic;
signal reg_link0 : std_logic;
signal reg_link1 : std_logic;
signal link0_change : std_logic;
signal link1_change : std_logic;
signal reg_link_change : std_logic;
signal interrupts : std_logic_vector(31 downto 0);
-- ------------------------------------------------------------------------
-- Network module signals
-- ------------------------------------------------------------------------
signal ibuf0_pacodag_clk : std_logic;
signal ibuf0_pacodag_data : std_logic_vector(63 downto 0);
signal ibuf0_pacodag_rem : std_logic_vector(2 downto 0);
signal ibuf0_pacodag_src_rdy_n : std_logic;
signal ibuf0_pacodag_sop_n : std_logic;
signal ibuf0_pacodag_eop_n : std_logic;
signal ibuf0_pacodag_dst_rdy_n : std_logic;
signal ibuf0_pacodag_rdy : std_logic; -- PCD is ready for next request
signal ibuf0_pacodag_sop : std_logic;
signal ibuf0_pacodag_stat : t_ibuf_general_stat;
signal ibuf0_pacodag_stat_dv : std_logic;
signal ibuf0_sau_accept : std_logic;
signal ibuf0_sau_dv : std_logic;
signal ibuf1_pacodag_clk : std_logic;
signal ibuf1_pacodag_data : std_logic_vector(63 downto 0);
signal ibuf1_pacodag_rem : std_logic_vector(2 downto 0);
signal ibuf1_pacodag_src_rdy_n : std_logic;
signal ibuf1_pacodag_sop_n : std_logic;
signal ibuf1_pacodag_eop_n : std_logic;
signal ibuf1_pacodag_dst_rdy_n : std_logic;
signal ibuf1_pacodag_rdy : std_logic; -- PCD is ready for next request
signal ibuf1_pacodag_sop : std_logic;
signal ibuf1_pacodag_stat : t_ibuf_general_stat;
signal ibuf1_pacodag_stat_dv : std_logic;
signal ibuf1_sau_accept : std_logic;
signal ibuf1_sau_dv : std_logic;
attribute buffer_type:string;
attribute buffer_type of ibuf1_pacodag_clk:signal is "none";
attribute buffer_type of ibuf0_pacodag_clk:signal is "none";
-- IBUFs/OBUFs to output FrameLink
signal obuf0_rx : t_fl64;
signal obuf1_rx : t_fl64;
signal ibuf0_tx : t_fl64;
signal ibuf1_tx : t_fl64;
-- ------------------------------------------------------------------------
-- Other signals
-- ------------------------------------------------------------------------
-- Internal bus signals ---------------------
signal ibus_down_data : std_logic_vector(63 downto 0);
signal ibus_down_sof_n : std_logic;
signal ibus_down_eof_n : std_logic;
signal ibus_down_src_rdy_n : std_logic;
signal ibus_down_dst_rdy_n : std_logic;
signal ibus_up_data : std_logic_vector(63 downto 0);
signal ibus_up_sof_n : std_logic;
signal ibus_up_eof_n : std_logic;
signal ibus_up_src_rdy_n : std_logic;
signal ibus_up_dst_rdy_n : std_logic;
signal app_ib_up_data : std_logic_vector(63 downto 0);
signal app_ib_up_sof_n : std_logic;
signal app_ib_up_eof_n : std_logic;
signal app_ib_up_src_rdy_n : std_logic;
signal app_ib_up_dst_rdy_n : std_logic;
signal app_ib_down_data : std_logic_vector(63 downto 0);
signal app_ib_down_sof_n : std_logic;
signal app_ib_down_eof_n : std_logic;
signal app_ib_down_src_rdy_n : std_logic;
signal app_ib_down_dst_rdy_n : std_logic;
signal mi32_dma_ardy_aux : std_logic;
signal mi32_dma_drdy_aux : std_logic;
signal mi32_dma_drd_aux : std_logic_vector(31 downto 0);
signal mi32_net_ardy_aux : std_logic;
signal mi32_net_drdy_aux : std_logic;
signal mi32_net_drd_aux : std_logic_vector(31 downto 0);
signal mi32_user_ardy_aux : std_logic;
signal mi32_user_drdy_aux : std_logic;
signal mi32_user_drd_aux : std_logic_vector(31 downto 0);
-- attributes to prevent optimization in precision
attribute dont_touch : string;
attribute dont_touch of MCLK0_IBUFDS : label is "true";
attribute dont_touch of MCLK1_IBUFDS : label is "true";
attribute dont_touch of XCLK0_IBUFDS : label is "true";
attribute dont_touch of XCLK1_IBUFDS : label is "true";
attribute dont_touch of GCLK100_IBUFDS : label is "true";
attribute dont_touch of GCLK250_IBUFDS : label is "true";
-- ----------------------------------------------------------------------------
-- Architecture body
-- ----------------------------------------------------------------------------
begin
-- -------------------------------------------------------------------------
-- USER APPLICATION MODULE
-- -------------------------------------------------------------------------
APPLICATION_I : entity work.APPLICATION
port map(
-- ----------------------------------------------------------------------
-- CLOCKs and RESETs
-- ----------------------------------------------------------------------
-- Clock signal for user interface
CLK => CLK_ICS,
RESET => RESET_ICS,
CLK_CORE => CLK_USER0,
RESET_CORE => RESET_USER0,
-- ----------------------------------------------------------------------
-- NETWORK INTERFACE 0
-- ----------------------------------------------------------------------
-- Input buffer interface
IBUF0_TX_SOF_N => ibuf0_tx.SOF_N,
IBUF0_TX_SOP_N => ibuf0_tx.SOP_N,
IBUF0_TX_EOP_N => ibuf0_tx.EOP_N,
IBUF0_TX_EOF_N => ibuf0_tx.EOF_N,
IBUF0_TX_SRC_RDY_N => ibuf0_tx.SRC_RDY_N,
IBUF0_TX_DST_RDY_N => ibuf0_tx.DST_RDY_N,
IBUF0_TX_DATA => ibuf0_tx.DATA,
IBUF0_TX_REM => ibuf0_tx.DREM,
-- PACODAG interface
IBUF0_CTRL_CLK => ibuf0_pacodag_clk,
IBUF0_CTRL_DATA => ibuf0_pacodag_data,
IBUF0_CTRL_REM => ibuf0_pacodag_rem,
IBUF0_CTRL_SRC_RDY_N => ibuf0_pacodag_src_rdy_n,
IBUF0_CTRL_SOP_N => ibuf0_pacodag_sop_n,
IBUF0_CTRL_EOP_N => ibuf0_pacodag_eop_n,
IBUF0_CTRL_DST_RDY_N => ibuf0_pacodag_dst_rdy_n,
IBUF0_CTRL_RDY => ibuf0_pacodag_rdy,
-- IBUF status interface
IBUF0_SOP => ibuf0_pacodag_sop,
IBUF0_PAYLOAD_LEN => ibuf0_pacodag_stat.payload_len,
IBUF0_FRAME_ERROR => ibuf0_pacodag_stat.frame_error,
IBUF0_CRC_CHECK_FAILED => ibuf0_pacodag_stat.crc_check_failed,
IBUF0_MAC_CHECK_FAILED => ibuf0_pacodag_stat.mac_check_failed,
IBUF0_LEN_BELOW_MIN => ibuf0_pacodag_stat.len_below_min,
IBUF0_LEN_OVER_MTU => ibuf0_pacodag_stat.len_over_mtu,
IBUF0_STAT_DV => ibuf0_pacodag_stat_dv,
-- Output buffer interface
OBUF0_RX_SOF_N => obuf0_rx.SOF_N,
OBUF0_RX_SOP_N => obuf0_rx.SOP_N,
OBUF0_RX_EOP_N => obuf0_rx.EOP_N,
OBUF0_RX_EOF_N => obuf0_rx.EOF_N,
OBUF0_RX_SRC_RDY_N => obuf0_rx.SRC_RDY_N,
OBUF0_RX_DST_RDY_N => obuf0_rx.DST_RDY_N,
OBUF0_RX_DATA => obuf0_rx.DATA,
OBUF0_RX_REM => obuf0_rx.DREM,
-- ----------------------------------------------------------------------
-- NETWORK INTERFACE 1
-- ----------------------------------------------------------------------
-- Input buffer interface
IBUF1_TX_SOF_N => ibuf1_tx.SOF_N,
IBUF1_TX_SOP_N => ibuf1_tx.SOP_N,
IBUF1_TX_EOP_N => ibuf1_tx.EOP_N,
IBUF1_TX_EOF_N => ibuf1_tx.EOF_N,
IBUF1_TX_SRC_RDY_N => ibuf1_tx.SRC_RDY_N,
IBUF1_TX_DST_RDY_N => ibuf1_tx.DST_RDY_N,
IBUF1_TX_DATA => ibuf1_tx.DATA,
IBUF1_TX_REM => ibuf1_tx.DREM,
-- PACODAG interface
IBUF1_CTRL_CLK => ibuf1_pacodag_clk,
IBUF1_CTRL_DATA => ibuf1_pacodag_data,
IBUF1_CTRL_REM => ibuf1_pacodag_rem,
IBUF1_CTRL_SRC_RDY_N => ibuf1_pacodag_src_rdy_n,
IBUF1_CTRL_SOP_N => ibuf1_pacodag_sop_n,
IBUF1_CTRL_EOP_N => ibuf1_pacodag_eop_n,
IBUF1_CTRL_DST_RDY_N => ibuf1_pacodag_dst_rdy_n,
IBUF1_CTRL_RDY => ibuf1_pacodag_rdy,
-- IBUF status interface
IBUF1_SOP => ibuf1_pacodag_sop,
IBUF1_PAYLOAD_LEN => ibuf1_pacodag_stat.payload_len,
IBUF1_FRAME_ERROR => ibuf1_pacodag_stat.frame_error,
IBUF1_CRC_CHECK_FAILED => ibuf1_pacodag_stat.crc_check_failed,
IBUF1_MAC_CHECK_FAILED => ibuf1_pacodag_stat.mac_check_failed,
IBUF1_LEN_BELOW_MIN => ibuf1_pacodag_stat.len_below_min,
IBUF1_LEN_OVER_MTU => ibuf1_pacodag_stat.len_over_mtu,
IBUF1_STAT_DV => ibuf1_pacodag_stat_dv,
-- Output buffer interface
OBUF1_RX_SOF_N => obuf1_rx.SOF_N,
OBUF1_RX_SOP_N => obuf1_rx.SOP_N,
OBUF1_RX_EOP_N => obuf1_rx.EOP_N,
OBUF1_RX_EOF_N => obuf1_rx.EOF_N,
OBUF1_RX_SRC_RDY_N => obuf1_rx.SRC_RDY_N,
OBUF1_RX_DST_RDY_N => obuf1_rx.DST_RDY_N,
OBUF1_RX_DATA => obuf1_rx.DATA,
OBUF1_RX_REM => obuf1_rx.DREM,
-- ----------------------------------------------------------------------
-- DMA INTERFACE
-- ----------------------------------------------------------------------
-- network interfaces interface
-- input interface
RX0_DATA => swbuf0_tx.DATA,
RX0_DREM => swbuf0_tx.DREM,
RX0_SOF_N => swbuf0_tx.SOF_N,
RX0_EOF_N => swbuf0_tx.EOF_N,
RX0_SOP_N => swbuf0_tx.SOP_N,
RX0_EOP_N => swbuf0_tx.EOP_N,
RX0_SRC_RDY_N => swbuf0_tx.SRC_RDY_N,
RX0_DST_RDY_N => swbuf0_tx.DST_RDY_N,
RX1_DATA => swbuf1_tx.DATA,
RX1_DREM => swbuf1_tx.DREM,
RX1_SOF_N => swbuf1_tx.SOF_N,
RX1_EOF_N => swbuf1_tx.EOF_N,
RX1_SOP_N => swbuf1_tx.SOP_N,
RX1_EOP_N => swbuf1_tx.EOP_N,
RX1_SRC_RDY_N => swbuf1_tx.SRC_RDY_N,
RX1_DST_RDY_N => swbuf1_tx.DST_RDY_N,
-- output interfaces
TX_DATA => swbuf_rx.DATA,
TX_DREM => swbuf_rx.DREM,
TX_SOF_N => swbuf_rx.SOF_N,
TX_EOF_N => swbuf_rx.EOF_N,
TX_SOP_N => swbuf_rx.SOP_N,
TX_EOP_N => swbuf_rx.EOP_N,
TX_SRC_RDY_N => swbuf_rx.SRC_RDY_N,
TX_DST_RDY_N => swbuf_rx_dst_rdy_n,
TX_CHANNEL => swbuf_rx_channel,
-- ----------------------------------------------------------------------
-- ICS INTERFACE
-- ----------------------------------------------------------------------
-- Internal Bus interface (Fast)
IB_UP_DATA => app_ib_up_data,
IB_UP_SOF_N => app_ib_up_sof_n,
IB_UP_EOF_N => app_ib_up_eof_n,
IB_UP_SRC_RDY_N => app_ib_up_src_rdy_n,
IB_UP_DST_RDY_N => app_ib_up_dst_rdy_n,
IB_DOWN_DATA => app_ib_down_data,
IB_DOWN_SOF_N => app_ib_down_sof_n,
IB_DOWN_EOF_N => app_ib_down_eof_n,
IB_DOWN_SRC_RDY_N => app_ib_down_src_rdy_n,
IB_DOWN_DST_RDY_N => app_ib_down_dst_rdy_n,
-- MI32 interface (Slow, efficient)
MI32_DWR => MI32_USER_DWR,
MI32_ADDR => MI32_USER_ADDR,
MI32_RD => MI32_USER_RD,
MI32_WR => MI32_USER_WR,
MI32_BE => MI32_USER_BE,
MI32_DRD => mi32_user_drd_aux,
MI32_ARDY => mi32_user_ardy_aux,
MI32_DRDY => mi32_user_drdy_aux,
-- ----------------------------------------------------------------------
-- TIMESTAMPS FOR PACODAG
-- ----------------------------------------------------------------------
TS => TS_NS,
TS_DV => TS_DV,
TS_CLK => TS_CLK
);
MI32_USER_DRD <= mi32_user_drd_aux;
MI32_USER_ARDY <= mi32_user_ardy_aux;
MI32_USER_DRDY <= mi32_user_drdy_aux;
-- -------------------------------------------------------------------------
-- EMPTY SAU
-- -------------------------------------------------------------------------
ibuf0_sau_accept <= '1';
ibuf0_sau_dv <= '1';
ibuf1_sau_accept <= '1';
ibuf1_sau_dv <= '1';
-- -------------------------------------------------------------------------
-- NETWORK MODULE
-- -------------------------------------------------------------------------
NETWORK_MODULE_I : NETWORK_MOD_10G2_64
port map(
USER_CLK => CLK_ICS,
FL_RESET => RESET_ICS,
BUSRESET => RESET_ICS,
-- 2 XGMII interfaces
-- RX
XGMII_RESET => XGMII_RESET,
XGMII_RXCLK => XGMII_RXCLK,
XGMII_RXD => XGMII_RXD,
XGMII_RXC => XGMII_RXC,
-- TX
XGMII_TXCLK => XGMII_TXCLK,
XGMII_TXD => XGMII_TXD,
XGMII_TXC => XGMII_TXC,
-- USER INTERFACE
-- Network interface 0
IBUF0_TX_SOF_N => ibuf0_tx.sof_n,
IBUF0_TX_SOP_N => ibuf0_tx.sop_n,
IBUF0_TX_EOP_N => ibuf0_tx.eop_n,
IBUF0_TX_EOF_N => ibuf0_tx.eof_n,
IBUF0_TX_SRC_RDY_N => ibuf0_tx.src_rdy_n,
IBUF0_TX_DST_RDY_N => ibuf0_tx.dst_rdy_n,
IBUF0_TX_DATA => ibuf0_tx.data,
IBUF0_TX_REM => ibuf0_tx.drem,
-- PACODAG interface
IBUF0_CTRL_CLK => ibuf0_pacodag_clk,
IBUF0_CTRL_DATA => ibuf0_pacodag_data,
IBUF0_CTRL_REM => ibuf0_pacodag_rem,
IBUF0_CTRL_SRC_RDY_N => ibuf0_pacodag_src_rdy_n,
IBUF0_CTRL_SOP_N => ibuf0_pacodag_sop_n,
IBUF0_CTRL_EOP_N => ibuf0_pacodag_eop_n,
IBUF0_CTRL_DST_RDY_N => ibuf0_pacodag_dst_rdy_n,
IBUF0_CTRL_RDY => ibuf0_pacodag_rdy,
-- IBUF status interface
IBUF0_SOP => ibuf0_pacodag_sop,
IBUF0_PAYLOAD_LEN => ibuf0_pacodag_stat.payload_len,
IBUF0_FRAME_ERROR => ibuf0_pacodag_stat.frame_error,
IBUF0_CRC_CHECK_FAILED=>ibuf0_pacodag_stat.crc_check_failed,
IBUF0_MAC_CHECK_FAILED=>ibuf0_pacodag_stat.mac_check_failed,
IBUF0_LEN_BELOW_MIN => ibuf0_pacodag_stat.len_below_min,
IBUF0_LEN_OVER_MTU => ibuf0_pacodag_stat.len_over_mtu,
IBUF0_STAT_DV => ibuf0_pacodag_stat_dv,
IBUF0_FRAME_RECEIVED => open,
IBUF0_FRAME_DISCARDED => open,
IBUF0_BUFFER_OVF => open,
-- Sampling unit interface
IBUF0_SAU_ACCEPT => ibuf0_sau_accept,
IBUF0_SAU_DV => ibuf0_sau_dv,
-- Output buffer interface
OBUF0_RX_SOF_N => obuf0_rx.sof_n,
OBUF0_RX_SOP_N => obuf0_rx.sop_n,
OBUF0_RX_EOP_N => obuf0_rx.eop_n,
OBUF0_RX_EOF_N => obuf0_rx.eof_n,
OBUF0_RX_SRC_RDY_N => obuf0_rx.src_rdy_n,
OBUF0_RX_DST_RDY_N => obuf0_rx.dst_rdy_n,
OBUF0_RX_DATA => obuf0_rx.data,
OBUF0_RX_REM => obuf0_rx.drem,
-- Network interface 1 --------------------------------------------------
IBUF1_TX_SOF_N => ibuf1_tx.sof_n,
IBUF1_TX_SOP_N => ibuf1_tx.sop_n,
IBUF1_TX_EOP_N => ibuf1_tx.eop_n,
IBUF1_TX_EOF_N => ibuf1_tx.eof_n,
IBUF1_TX_SRC_RDY_N => ibuf1_tx.src_rdy_n,
IBUF1_TX_DST_RDY_N => ibuf1_tx.dst_rdy_n,
IBUF1_TX_DATA => ibuf1_tx.data,
IBUF1_TX_REM => ibuf1_tx.drem,
-- PACODAG interface
IBUF1_CTRL_CLK => ibuf1_pacodag_clk,
IBUF1_CTRL_DATA => ibuf1_pacodag_data,
IBUF1_CTRL_REM => ibuf1_pacodag_rem,
IBUF1_CTRL_SRC_RDY_N => ibuf1_pacodag_src_rdy_n,
IBUF1_CTRL_SOP_N => ibuf1_pacodag_sop_n,
IBUF1_CTRL_EOP_N => ibuf1_pacodag_eop_n,
IBUF1_CTRL_DST_RDY_N => ibuf1_pacodag_dst_rdy_n,
IBUF1_CTRL_RDY => ibuf1_pacodag_rdy,
-- IBUF status interface
IBUF1_SOP => ibuf1_pacodag_sop,
IBUF1_PAYLOAD_LEN => ibuf1_pacodag_stat.payload_len,
IBUF1_FRAME_ERROR => ibuf1_pacodag_stat.frame_error,
IBUF1_CRC_CHECK_FAILED=>ibuf1_pacodag_stat.crc_check_failed,
IBUF1_MAC_CHECK_FAILED=>ibuf1_pacodag_stat.mac_check_failed,
IBUF1_LEN_BELOW_MIN => ibuf1_pacodag_stat.len_below_min,
IBUF1_LEN_OVER_MTU => ibuf1_pacodag_stat.len_over_mtu,
IBUF1_STAT_DV => ibuf1_pacodag_stat_dv,
IBUF1_FRAME_RECEIVED => open,
IBUF1_FRAME_DISCARDED => open,
IBUF1_BUFFER_OVF => open,
-- Sampling unit interface
IBUF1_SAU_ACCEPT => ibuf1_sau_accept,
IBUF1_SAU_DV => ibuf1_sau_dv,
-- Output buffer interface
OBUF1_RX_SOF_N => obuf1_rx.sof_n,
OBUF1_RX_SOP_N => obuf1_rx.sop_n,
OBUF1_RX_EOP_N => obuf1_rx.eop_n,
OBUF1_RX_EOF_N => obuf1_rx.eof_n,
OBUF1_RX_SRC_RDY_N => obuf1_rx.src_rdy_n,
OBUF1_RX_DST_RDY_N => obuf1_rx.dst_rdy_n,
OBUF1_RX_DATA => obuf1_rx.data,
OBUF1_RX_REM => obuf1_rx.drem,
-- Led interface
IBUF_LED => IBUF_LED,
OBUF_LED => OBUF_LED,
-- Link presence interface
LINK0 => link0,
LINK1 => link1,
-- MI32 interface
MI32_DWR => MI32_NET_DWR,
MI32_ADDR => MI32_NET_ADDR,
MI32_RD => MI32_NET_RD,
MI32_WR => MI32_NET_WR,
MI32_BE => MI32_NET_BE,
MI32_DRD => mi32_net_drd_aux,
MI32_ARDY => mi32_net_ardy_aux,
MI32_DRDY => mi32_net_drdy_aux
);
MI32_NET_DRD <= mi32_net_drd_aux;
MI32_NET_ARDY <= mi32_net_ardy_aux;
MI32_NET_DRDY <= mi32_net_drdy_aux;
-- -------------------------------------------------------------------------
-- DMA engine
-- -------------------------------------------------------------------------
DMA_MOD_I : DMA_MOD_64B_8RX2TX_GEN
port map(
-- Common interface
CLK => CLK_ICS,
RESET => RESET_ICS,
RX_INTERRUPT => rx_interrupt,
TX_INTERRUPT => tx_interrupt,
-- network interfaces interface
-- input interface
RX_SOF_N => swbuf_rx.sof_n,
RX_SOP_N => swbuf_rx.sop_n,
RX_EOP_N => swbuf_rx.eop_n,
RX_EOF_N => swbuf_rx.eof_n,
RX_SRC_RDY_N => swbuf_rx.src_rdy_n,
RX_DST_RDY_N => swbuf_rx_dst_rdy_n,
RX_DATA => swbuf_rx.data,
RX_DREM => swbuf_rx.drem,
RX_CHANNEL => swbuf_rx_channel,
-- output interfaces
TX0_SOF_N => swbuf0_tx.sof_n,
TX0_SOP_N => swbuf0_tx.sop_n,
TX0_EOP_N => swbuf0_tx.eop_n,
TX0_EOF_N => swbuf0_tx.eof_n,
TX0_SRC_RDY_N => swbuf0_tx.src_rdy_n,
TX0_DST_RDY_N => swbuf0_tx.dst_rdy_n,
TX0_DATA => swbuf0_tx.data,
TX0_DREM => swbuf0_tx.drem,
TX1_SOF_N => swbuf1_tx.sof_n,
TX1_SOP_N => swbuf1_tx.sop_n,
TX1_EOP_N => swbuf1_tx.eop_n,
TX1_EOF_N => swbuf1_tx.eof_n,
TX1_SRC_RDY_N => swbuf1_tx.src_rdy_n,
TX1_DST_RDY_N => swbuf1_tx.dst_rdy_n,
TX1_DATA => swbuf1_tx.data,
TX1_DREM => swbuf1_tx.drem,
-- Internal Bus
IB_DOWN_DATA => ibus_down_data,
IB_DOWN_SOF_N => ibus_down_sof_n,
IB_DOWN_EOF_N => ibus_down_eof_n,
IB_DOWN_SRC_RDY_N => ibus_down_src_rdy_n,
IB_DOWN_DST_RDY_N => ibus_down_dst_rdy_n,
IB_UP_DATA => ibus_up_data,
IB_UP_SOF_N => ibus_up_sof_n,
IB_UP_EOF_N => ibus_up_eof_n,
IB_UP_SRC_RDY_N => ibus_up_src_rdy_n,
IB_UP_DST_RDY_N => ibus_up_dst_rdy_n,
-- MI32 interface
MI32_DWR => MI32_DMA_DWR,
MI32_ADDR => MI32_DMA_ADDR,
MI32_RD => MI32_DMA_RD,
MI32_WR => MI32_DMA_WR,
MI32_BE => MI32_DMA_BE,
MI32_DRD => mi32_dma_drd_aux,
MI32_ARDY => mi32_dma_ardy_aux,
MI32_DRDY => mi32_dma_drdy_aux
);
MI32_DMA_DRD <= mi32_dma_drd_aux;
MI32_DMA_ARDY <= mi32_dma_ardy_aux;
MI32_DMA_DRDY <= mi32_dma_drdy_aux;
-- -------------------------------------------------------------------------
-- INTERNAL BUS SWITCH
-- -------------------------------------------------------------------------
ib_switch_i : GICS_IB_SWITCH_SLAVE_SYNTH
port map(
CLK => CLK_ICS,
RESET => RESET_ICS,
PORT0_UP_DATA => IB_UP_DATA,
PORT0_UP_SOF_N => IB_UP_SOF_N,
PORT0_UP_EOF_N => IB_UP_EOF_N,
PORT0_UP_SRC_RDY_N => IB_UP_SRC_RDY_N,
PORT0_UP_DST_RDY_N => IB_UP_DST_RDY_N,
PORT0_DOWN_DATA => IB_DOWN_DATA,
PORT0_DOWN_SOF_N => IB_DOWN_SOF_N,
PORT0_DOWN_EOF_N => IB_DOWN_EOF_N,
PORT0_DOWN_SRC_RDY_N => IB_DOWN_SRC_RDY_N,
PORT0_DOWN_DST_RDY_N => IB_DOWN_DST_RDY_N,
PORT1_UP_DATA => ibus_up_data,
PORT1_UP_SOF_N => ibus_up_sof_n,
PORT1_UP_EOF_N => ibus_up_eof_n,
PORT1_UP_SRC_RDY_N => ibus_up_src_rdy_n,
PORT1_UP_DST_RDY_N => ibus_up_dst_rdy_n,
PORT1_DOWN_DATA => ibus_down_data,
PORT1_DOWN_SOF_N => ibus_down_sof_n,
PORT1_DOWN_EOF_N => ibus_down_eof_n,
PORT1_DOWN_SRC_RDY_N => ibus_down_src_rdy_n,
PORT1_DOWN_DST_RDY_N => ibus_down_dst_rdy_n,
PORT2_UP_DATA => app_ib_up_data,
PORT2_UP_SOF_N => app_ib_up_sof_n,
PORT2_UP_EOF_N => app_ib_up_eof_n,
PORT2_UP_SRC_RDY_N => app_ib_up_src_rdy_n,
PORT2_UP_DST_RDY_N => app_ib_up_dst_rdy_n,
PORT2_DOWN_DATA => app_ib_down_data,
PORT2_DOWN_SOF_N => app_ib_down_sof_n,
PORT2_DOWN_EOF_N => app_ib_down_eof_n,
PORT2_DOWN_SRC_RDY_N => app_ib_down_src_rdy_n,
PORT2_DOWN_DST_RDY_N => app_ib_down_dst_rdy_n
);
-- -------------------------------------------------------------------------
-- Interrupt signal handling
-- No need to reset, because interrupts are ignored for a few cycles
-- in ID module
process(CLK_ICS)
begin
if CLK_ICS'event and CLK_ICS = '1' then
reg_rx_interrupt <= rx_interrupt;
reg_tx_interrupt <= tx_interrupt;
reg_sysmon_alarm <= SYSMON_ALARM;
reg_sysmon_alarm_pulse <= sysmon_alarm_pulse;
regasync_link0 <= link0;
regasync_link1 <= link1;
reg_link0 <= regasync_link0;
reg_link1 <= regasync_link1;
reg_link_change <= link0_change or link1_change;
end if;
end process;
-- Detect rising edge
sysmon_alarm_pulse <= '1' when (reg_sysmon_alarm='0' and SYSMON_ALARM='1')
else '0';
-- Detect change
link0_change <= reg_link0 xor regasync_link0;
link1_change <= reg_link1 xor regasync_link1;
interrupts <= X"0000000" &
reg_link_change &
reg_sysmon_alarm_pulse &
reg_tx_interrupt & reg_rx_interrupt ;
INTERRUPT <= interrupts;
-- INTR_RDY open -- TODO: deal with INTR_RDY=0, because otherwise
-- an interrupt may be lost
-- ------------------------------------------------------------------------
-- These signals are unused in NIC, but may be used in other projects
-- ------------------------------------------------------------------------
-- Clocks
MCLK0_IBUFDS : IBUFDS
port map(
I => MCLK0_P,
IB => MCLK0_N,
O => open
);
MCLK1_IBUFDS : IBUFDS
port map(
I => MCLK1_P,
IB => MCLK1_N,
O => open
);
GCLK250_IBUFDS : IBUFDS
port map(
I => GCLK250_P,
IB => GCLK250_N,
O => open
);
GCLK100_IBUFDS : IBUFDS
port map(
I => GCLK100_P,
IB => GCLK100_N,
O => open
);
XCLK1_IBUFDS : IBUFDS
port map(
I => XCLK1_P,
IB => XCLK1_N,
O => open
);
XCLK0_IBUFDS : IBUFDS
port map(
I => XCLK0_P,
IB => XCLK0_N,
O => open
);
-- SRAM (no errors reported)
-- DRAM
DSCL_OBUF : OBUF
port map(
O => DSCL,
I => reset_ics
);
DWE_N_OBUF : OBUF
port map(
O => DWE_N,
I => reset_ics
);
DCAS_N_OBUF : OBUF
port map(
O => DCAS_N,
I => reset_ics
);
DRAS_N_OBUF : OBUF
port map(
O => DRAS_N,
I => reset_ics
);
DCK0_P_OBUF : OBUF
port map(
O => DCK0_P,
I => reset_ics
);
DCK0_N_OBUF : OBUF
port map(
O => DCK0_N,
I => reset_ics
);
DCK1_P_OBUF : OBUF
port map(
O => DCK1_P,
I => reset_ics
);
DCK1_N_OBUF : OBUF
port map(
O => DCK1_N,
I => reset_ics
);
DA_OBUF_GEN: for i in 0 to 13 generate
DA_OBUF : OBUF
port map(
O => DA(i),
I => reset_ics
);
end generate;
DDM_OBUF_GEN: for i in 0 to 7 generate
DDM_OBUF : OBUF
port map(
O => DDM(i),
I => reset_ics
);
end generate;
DBA_OBUF_GEN: for i in 0 to 2 generate
DBA_OBUF : OBUF
port map(
O => DBA(i),
I => reset_ics
);
end generate;
DSA_OBUF_GEN: for i in 0 to 1 generate
DSA_OBUF : OBUF
port map(
O => DSA(i),
I => reset_ics
);
end generate;
DDODT_OBUF_GEN: for i in 0 to 1 generate
DDODT_OBUF : OBUF
port map(
O => DDODT(i),
I => reset_ics
);
end generate;
DCS_N_OBUF_GEN: for i in 0 to 1 generate
DCS_N_OBUF : OBUF
port map(
O => DCS_N(i),
I => reset_ics
);
end generate;
DCKE_OBUF_GEN: for i in 0 to 1 generate
DCKE_OBUF : OBUF
port map(
O => DCKE(i),
I => reset_ics
);
end generate;
-- Misc
FQTXD_OBUF : OBUF
port map(
O => FQTXD,
I => reset_ics
);
FQLED_OBUF_GEN: for i in 0 to 3 generate
FQLED_OBUF : OBUF
port map(
O => FQLED(i),
I => reset_ics
);
end generate;
end architecture full;
| bsd-3-clause | 6cd16609fb174607a4877b1b0bc97222 | 0.502547 | 3.280947 | false | false | false | false |
cnplab/blockmon | fw-combo/src/IPFIX/comp/mi_pipe_arch.vhd | 1 | 4,867 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- mi_pipe_arch.vhd: MI Pipe - wrapper to generic pipe
-- Copyright (C) 2010 CESNET
-- Author(s): Vaclav Bartos <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: mi_pipe_arch.vhd 14019 2010-06-11 12:51:48Z washek $
--
-- TODO:
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
-- ----------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION --
-- ----------------------------------------------------------------------------
architecture mi_pipe_arch of MI_PIPE is
signal in_data : std_logic_vector(DATA_WIDTH + ADDR_WIDTH + DATA_WIDTH/8 + 1 downto 0);
signal out_data : std_logic_vector(DATA_WIDTH + ADDR_WIDTH + DATA_WIDTH/8 + 1 downto 0);
signal in_req : std_logic;
signal in_dst_rdy : std_logic;
signal out_src_rdy : std_logic;
signal out_dst_rdy : std_logic;
signal OUT_RD_aux : std_logic;
signal OUT_WR_aux : std_logic;
begin
in_data <= IN_WR & IN_RD & IN_BE & IN_ADDR & IN_DWR;
OUT_DWR <= out_data(DATA_WIDTH-1 downto 0);
OUT_ADDR <= out_data(DATA_WIDTH+ADDR_WIDTH-1 downto DATA_WIDTH);
OUT_BE <= out_data(DATA_WIDTH+ADDR_WIDTH+DATA_WIDTH/8-1 downto DATA_WIDTH+ADDR_WIDTH);
OUT_RD_aux <= out_data(DATA_WIDTH+ADDR_WIDTH+DATA_WIDTH/8) and out_src_rdy;
OUT_WR_aux <= out_data(DATA_WIDTH+ADDR_WIDTH+DATA_WIDTH/8+1) and out_src_rdy;
OUT_RD <= OUT_RD_aux;
OUT_WR <= OUT_WR_aux;
in_req <= IN_RD or IN_WR;
out_dst_rdy <= ((not (OUT_RD_aux or OUT_WR_aux)) or OUT_ARDY);
PIPE: entity work.PIPE
generic map(
DATA_WIDTH => DATA_WIDTH + ADDR_WIDTH + DATA_WIDTH/8 + 2,
USE_OUTREG => USE_OUTREG,
FAKE_PIPE => FAKE_PIPE
)
port map(
CLK => CLK,
RESET => RESET,
IN_DATA => in_data,
IN_SRC_RDY => in_req,
IN_DST_RDY => in_dst_rdy,
OUT_DATA => out_data,
OUT_SRC_RDY => out_src_rdy,
OUT_DST_RDY => out_dst_rdy
);
IN_ARDY <= in_dst_rdy and in_req;
NOT_FAKE: if (FAKE_PIPE = false) generate
in_drdp: process(CLK)
begin
if (CLK'event and CLK = '1') then
IN_DRD <= OUT_DRD;
end if;
end process;
in_drdyp: process(RESET, CLK)
begin
if (CLK'event and CLK = '1') then
if (RESET = '1') then
IN_DRDY <= '0';
else
IN_DRDY <= OUT_DRDY;
end if;
end if;
end process;
end generate;
FAKE: if (FAKE_PIPE = true) generate
IN_DRD <= OUT_DRD;
IN_DRDY <= OUT_DRDY;
end generate;
end mi_pipe_arch;
| bsd-3-clause | a0bcd0faf8a30032131def5a85a996e3 | 0.586193 | 3.787549 | false | false | false | false |
cnplab/blockmon | fw-combo/src/IPFIX/comp/enc.vhd | 1 | 3,264 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- enc.vhd: Generic encoder
-- Copyright (C) 2006 CESNET
-- Author(s): Martin Kosek <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use work.math_pack.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity GEN_ENC is
generic(
ITEMS : integer := 16
);
port(
DI : in std_logic_vector(ITEMS-1 downto 0);
ADDR : out std_logic_vector(log2(ITEMS)-1 downto 0)
);
end entity GEN_ENC;
-- ----------------------------------------------------------------------------
-- Architecture declaration
-- ----------------------------------------------------------------------------
architecture behavioral of GEN_ENC is
begin
process(DI)
begin
ADDR <= (others => '0');
for i in 0 to (ITEMS-1) loop
if (DI(i) = '1') then
ADDR <= conv_std_logic_vector(i, log2(ITEMS));
end if;
end loop;
end process;
end architecture behavioral;
| bsd-3-clause | 46b90bef9c9a9fbd741ad9b0826fb49c | 0.582108 | 4.696403 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/openmac/src/openfilter-rtl-ea.vhd | 3 | 12,569 | -------------------------------------------------------------------------------
--! @file openfilter-rtl-ea.vhd
--
--! @brief OpenFILTER
--
--! @details This is the openFILTER used for blocking failures on the RMII lines.
--! Note: RxDv and RxDat have to be synchron to iClk
--! The following Conditions are checked:
--! * RxDV >163.64µsec HIGH -> invalid
--! * RxDV <0.64µsec LOW -> invalid
--! * RxDV 4x <5.12µsec HIGH -> invalid
--! * RxDV >5.12µsec HIGH -> valid
--! * iRxError HIGH -> invalid
--! If invalid deactivation of port, until RxDv and iRxError > 10.24µsec low
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
--! Work library
library work;
--! use openmac package
use work.openmacPkg.all;
entity openfilter is
port (
--! Reset
iRst : in std_logic;
--! RMII Clock
iClk : in std_logic;
--! RMII receive path in
iRx : in tRmiiPath;
--! RMII receive path out
oRx : out tRmiiPath;
--! RMII transmit path in
iTx : in tRmiiPath;
--! RMII transmit path out
oTx : out tRmiiPath;
--! RMII receive error
iRxError : in std_logic
);
end entity openfilter;
architecture rtl of openfilter is
--! Filter FSM type
type tFiltState is (
fs_init,
fs_GAP2short, fs_GAPext, fs_GAPok,
fs_FRMnopre, fs_FRMpre2short, fs_FRMpreOk,
fs_FRM2short, fs_FRMok, fs_FRM2long, fs_BlockAll
);
signal FiltState : tFiltState;
signal RxDel : tRmiiPathArray(3 downto 0);
signal FrameShift : std_logic;
signal LastFrameNOK : std_logic;
signal StCnt : std_logic_vector(13 downto 0);
signal BlockRxPort : std_logic;
begin
---------------------------------------------------------------------------
-- INPUT
---------------------------------------------------------------------------
RxDel(0) <= iRx;
BlockRxPort <= cActivated when (FiltState = fs_FRMnopre or
FiltState = fs_BlockAll or
LastFrameNOK = cActivated) else
cInactivated;
---------------------------------------------------------------------------
-- OUTPUT MUX
---------------------------------------------------------------------------
oRx <= cRmiiPathInit when BlockRxPort = cActivated else
RxDel(3) when FrameShift = cActivated else
RxDel(1);
oTx <= iTx;
doFsm : process(iRst, iClk)
variable RstStCnt : std_logic;
begin
if iRst = cActivated then
StCnt <= (others => cInactivated);
FiltState <= fs_init;
FrameShift <= cInactivated;
RxDel(3 downto 1) <= (others => cRmiiPathInit);
LastFrameNOK <= cInactivated;
elsif rising_edge(iClk) then
RxDel(3 downto 1) <= RxDel(2 downto 0);
-- DEFAULT --
RstStCnt := cInactivated;
case FiltState is
---------------------------------------------------------------
-- INIT
---------------------------------------------------------------
when fs_init =>
FiltState <= fs_GAP2short;
RstStCnt := cActivated;
---------------------------------------------------------------
-- GAP 2 SHORT
---------------------------------------------------------------
when fs_GAP2short =>
FrameShift <= cInactivated;
if StCnt(4) = cActivated then
-- 360ns
FiltState <= fs_GAPext;
end if;
if RxDel(0).enable = cActivated then
-- Gap < 360 ns -> too short -> Block Filter
FiltState <= fs_BlockAll;
RstStCnt := cActivated;
end if;
---------------------------------------------------------------
-- GAP EXTend
---------------------------------------------------------------
when fs_GAPext =>
if StCnt(5 downto 0) = "101110" then
FiltState <= fs_GAPok;
end if;
if RxDel(0).enable = cActivated then
-- GAP [360ns .. 960ns] -> short, but ok -> Start Frame
RstStCnt := cActivated;
FrameShift <= cActivated;
if RxDel(0).data = "01" then
-- GAP > 960ns -> OK -> Start Frame (preamble already beginning)
FiltState <= fs_FRMpre2short;
else
-- GAP > 960ns -> OK -> Start Frame and wait of preamble
FiltState <= fs_FRMnopre;
end if;
end if;
---------------------------------------------------------------
-- GAP OK
---------------------------------------------------------------
when fs_GAPok =>
if RxDel(0).enable = cActivated then
RstStCnt := cActivated;
if RxDel(0).data = "01" then
-- GAP > 960ns -> OK -> Start Frame (preamble already beginning)
FiltState <= fs_FRMpre2short;
else
-- GAP > 960ns -> OK -> Start Frame and wait of preamble
FiltState <= fs_FRMnopre;
end if;
end if;
---------------------------------------------------------------
-- FRAME, BUT STILL NO PREAMBLE
---------------------------------------------------------------
when fs_FRMnopre =>
if (StCnt(5) = cActivated or
RxDel(0).data = "11" or RxDel(0).data = "10" or
(RxDel(0).enable = cInactivated and RxDel(1).enable = cInactivated)) then
-- no preamble for >=660 ns or preamble wrong -> Block Filter
FiltState <= fs_BlockAll;
RstStCnt := cActivated;
elsif RxDel(0).data = "01" then
-- preamble starts -> Check Preamble
FiltState <= fs_FRMpre2short;
RstStCnt := cActivated;
end if;
---------------------------------------------------------------
-- FRAME CHECK PREAMBLE TOO SHORT
---------------------------------------------------------------
when fs_FRMpre2short =>
if (RxDel(0).data /= "01" or (RxDel(0).enable = cInactivated and
RxDel(1).enable = cInactivated)) then
-- preamble wrong -> Block Filter
FiltState <= fs_BlockAll;
RstStCnt := cActivated;
elsif StCnt(3) = cActivated then
-- preamble ok for 180 ns -> Preamble OK
FiltState <= fs_FRMpreOk;
end if;
---------------------------------------------------------------
-- FRAME CHECK PREAMBLE OK
---------------------------------------------------------------
when fs_FRMpreOk =>
if RxDel(0).data /= "01" then
-- preamble done -> Start Frame
FiltState <= fs_FRMok;
end if;
if ((StCnt(5) = cActivated and StCnt(2) = cActivated) or
(RxDel(0).enable = cInactivated and RxDel(1).enable = cInactivated)) then
-- preamble to long for 740 ns -> Block Filter
FiltState <= fs_BlockAll;
RstStCnt := cActivated;
end if;
-- preamble is OK
LastFrameNOK <= cInactivated;
---------------------------------------------------------------
-- FRAME OK
---------------------------------------------------------------
when fs_FRMok =>
if StCnt(13) = cActivated then
-- FRAME > 163,842 us -> too long -> Block Filter
FiltState <= fs_BlockAll;
RstStCnt := cActivated;
end if;
if RxDel(0).enable = cInactivated and RxDel(1).enable = cInactivated then
-- FRAME [163,842 us] -> OK -> Start GAP
FiltState <= fs_GAP2short;
RstStCnt := cActivated;
end if;
---------------------------------------------------------------
-- BLOCK FILTER
---------------------------------------------------------------
when fs_BlockAll =>
if StCnt(2) = cActivated then
-- Block for 100 nsec
FiltState <= fs_GAP2short;
RstStCnt := cActivated;
end if;
if RxDel(0).enable = cActivated then
-- Rxdv != cInactivated -> Reset Wait Period
RstStCnt := cActivated;
end if;
-- block next rx frame (until receive a valid preamble)
LastFrameNOK <= cActivated;
when others =>
FiltState <= fs_init;
end case;
if iRxError = cActivated then
-- iRxError -> Block Filter
FiltState <= fs_BlockAll;
RstStCnt := cActivated;
end if;
-- State Counter --
StCnt <= std_logic_vector(unsigned(StCnt) + 1);
if RstStCnt = cActivated then
StCnt <= (others => cInactivated);
end if;
end if;
end process;
end rtl;
| gpl-2.0 | 120b2d17d7c5cf40fb487b6ecefedf3a | 0.412443 | 6.071981 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/xilinx/openmac/src/ipifMasterHandler-rtl-ea.vhd | 3 | 12,592 | -------------------------------------------------------------------------------
--! @file ipifMasterHandler-rtl-ea.vhd
--
--! @brief IPIF Master handler
--
--! @details This is the IPIF master handler converting generic master interface
--! to IPIF.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity ipifMasterHandler is
generic (
--! Master address width
gMasterAddrWidth : natural := 31;
--! Master burst count width
gMasterBurstCountWidth : natural := 4;
--! IPIF address width
gIpifAddrWidth : natural := 32;
--! IPIF length width
gIpifLength : natural := 12
);
port (
--TODO: Add doxygen comments!
-- Common clock and reset
iRst : in std_logic;
iClk : in std_logic;
-- IPIF Master
iIpif_cmdAck : in std_logic;
iIpif_cmplt : in std_logic;
iIpif_error : in std_logic; --FIXME: Unused input
iIpif_rearbitrate : in std_logic; --FIXME: Unused input
iIpif_cmdTimeout : in std_logic; --FIXME: Unused input
oIpif_type : out std_logic;
oIpif_addr : out std_logic_vector(gIpifAddrWidth-1 downto 0);
oIpif_length : out std_logic_vector(gIpifLength-1 downto 0);
oIpif_be : out std_logic_vector(3 downto 0);
oIpif_lock : out std_logic;
oIpif_reset : out std_logic;
iIpif_rdData : in std_logic_vector(31 downto 0);
iIpif_rdRem : in std_logic_vector(3 downto 0); --FIXME: Unused input
oIpif_rdReq : out std_logic;
inIpif_rdSof : in std_logic;
inIpif_rdEof : in std_logic;
inIpif_rdSrcRdy : in std_logic;
inIpif_rdSrcDsc : in std_logic; --FIXME: Unused input
onIpif_rdDstRdy : out std_logic;
onIpif_rdDstDsc : out std_logic;
oIpif_wrData : out std_logic_vector(31 downto 0);
oIpif_wrRem : out std_logic_vector(3 downto 0);
oIpif_wrReq : out std_logic;
onIpif_wrSof : out std_logic;
onIpif_wrEof : out std_logic;
onIpif_wrSrcRdy : out std_logic;
onIpif_wrSrcDsc : out std_logic;
inIpif_wrDstRdy : in std_logic;
inIpif_wrDstDsc : in std_logic; --FIXME: Unused input
-- Generic master interface
iMasterRead : in std_logic;
iMasterWrite : in std_logic;
iMasterAddress : in std_logic_vector(gMasterAddrWidth-1 downto 0);
iMasterWritedata : in std_logic_vector(31 downto 0);
iMasterBurstcount : in std_logic_vector(gMasterBurstCountWidth-1 downto 0);
iMasterBurstcounter : in std_logic_vector(gMasterBurstCountWidth-1 downto 0);
oMasterReaddata : out std_logic_vector(31 downto 0);
oMasterWaitrequest : out std_logic;
oMasterReaddatavalid : out std_logic
);
end ipifMasterHandler;
architecture rtl of ipifMasterHandler is
--signals for requesting transfers
signal masterWrite : std_logic;
signal masterRead : std_logic;
signal nMasterEnable : std_logic;
signal masterWrite_l : std_logic;
signal masterRead_l : std_logic;
signal masterWrite_rise : std_logic;
signal masterRead_rise : std_logic;
signal masterWrite_fall : std_logic;
signal masterRead_fall : std_logic;
signal ipifWriteReq_reg : std_logic;
signal ipifWriteReq_next : std_logic;
signal ipifReadReq_reg : std_logic;
signal ipifReadReq_next : std_logic;
signal ipif_rdDstRdy : std_logic;
--signals for the transfer
type tTfState is (
sIdle,
sSof, sTf, sEof,
sSEof, --start/end of frame (single beat)
sWaitForCmplt
);
signal writeTf_reg : tTfState;
signal writeTf_next : tTfState;
signal readTf : tTfState;
begin
masterWrite <= iMasterWrite and not nMasterEnable;
masterRead <= iMasterRead and not nMasterEnable;
--reserved
oIpif_lock <= cInactivated;
oIpif_reset <= cInactivated;
--delay some signals..
del_proc : process(iClk, iRst)
begin
if iRst = cActivated then
masterWrite_l <= cInactivated;
masterRead_l <= cInactivated;
nMasterEnable <= cnActivated;
elsif rising_edge(iClk) then
masterWrite_l <= masterWrite;
masterRead_l <= masterRead;
if iIpif_cmplt = cActivated then
nMasterEnable <= cnActivated;
elsif masterWrite_fall = cActivated or masterRead_fall = cActivated then
nMasterEnable <= cnInactivated; --write/read done, wait for Mst_Cmplt
end if;
end if;
end process;
--generate pulse if write/read is asserted
masterWrite_rise <= cActivated when masterWrite_l = cInactivated and masterWrite = cActivated else
cInactivated;
masterRead_rise <= cActivated when masterRead_l = cInactivated and masterRead = cActivated else
cInactivated;
masterWrite_fall <= cActivated when masterWrite_l = cActivated and masterWrite = cInactivated else
cInactivated;
masterRead_fall <= cActivated when masterRead_l = cActivated and masterRead = cInactivated else
cInactivated;
--generate req qualifiers
req_proc : process(iClk, iRst)
begin
if iRst = cActivated then
ipifWriteReq_reg <= cInactivated;
ipifReadReq_reg <= cInactivated;
ipif_rdDstRdy <= cInactivated;
elsif rising_edge(iClk) then
ipifWriteReq_reg <= ipifWriteReq_next;
ipifReadReq_reg <= ipifReadReq_next;
if masterRead = cActivated then
ipif_rdDstRdy <= cActivated;
elsif readTf = sEof and inIpif_rdSrcRdy = cnActivated then
ipif_rdDstRdy <= cInactivated;
end if;
end if;
end process;
onIpif_rdDstRdy <= not ipif_rdDstRdy;
oIpif_rdReq <= ipifReadReq_reg;
oIpif_wrReq <= ipifWriteReq_reg;
oIpif_type <= cInactivated when iMasterBurstcount < 2 else --single beat
ipifReadReq_reg or ipifWriteReq_reg; --we are talking about bursts..
ipifWriteReq_next <= cInactivated when ipifWriteReq_reg = cActivated and iIpif_cmdAck = cActivated else
cActivated when ipifWriteReq_reg = cInactivated and masterWrite_rise = cActivated else
ipifWriteReq_reg;
ipifReadReq_next <= cInactivated when ipifReadReq_reg = cActivated and iIpif_cmdAck = cActivated else
cActivated when ipifReadReq_reg = cInactivated and masterRead_rise = cActivated else
ipifReadReq_reg;
--assign address, byteenable and burst size
comb_addrZeroPad : process(iMasterAddress)
begin
for i in oIpif_addr'range loop
if i <= iMasterAddress'high then
oIpif_addr(i) <= iMasterAddress(i);
else
oIpif_addr(i) <= cInactivated; --zero padding
end if;
end loop;
end process;
oIpif_be <= "1111";
oIpif_length <= conv_std_logic_vector(conv_integer(iMasterBurstcount),
oIpif_length'length - 2) & "00"; -- dword x 4 = byte
--write/read link
wrd_proc : process(iClk, iRst)
begin
if iRst = cActivated then
writeTf_reg <= sIdle;
elsif rising_edge(iClk) then
writeTf_reg <= writeTf_next;
end if;
end process;
--generate fsm for write and read transfers
writeTf_next <= sSEof when writeTf_reg = sIdle and ipifWriteReq_next = cActivated and (iMasterBurstcount <= 1 or iMasterBurstcount'length = 1) else
sSof when writeTf_reg = sIdle and ipifWriteReq_next = cActivated and iMasterBurstcount'length > 1 else
sEof when writeTf_reg = sSof and inIpif_wrDstRdy = cnActivated and iMasterBurstcount = 2 and iMasterBurstcount'length > 1 else
sTf when writeTf_reg = sSof and inIpif_wrDstRdy = cnActivated and iMasterBurstcount'length > 1 else
sEof when writeTf_reg = sTf and iMasterBurstcounter <= 2 and inIpif_wrDstRdy = cnActivated and iMasterBurstcount'length > 1 else
sWaitForCmplt when (writeTf_reg = sEof or writeTf_reg = sSEof) and inIpif_wrDstRdy = cnActivated else
sIdle when writeTf_reg = sWaitForCmplt and iIpif_cmplt = cActivated else
writeTf_reg;
readTf <= sSEof when inIpif_rdSof = cnActivated and inIpif_rdEof = cnActivated else
sSof when inIpif_rdSof = cnActivated else
sEof when inIpif_rdEof = cnActivated else
sTf when inIpif_rdSrcRdy = cnActivated else
sIdle;
--set write qualifiers
onIpif_wrSof <= cnActivated when writeTf_reg = sSof or writeTf_reg = sSEof else
cnInactivated;
onIpif_wrEof <= cnActivated when writeTf_reg = sEof or writeTf_reg = sSEof else
cnInactivated;
onIpif_wrSrcRdy <= cnActivated when writeTf_reg /= sIdle and writeTf_reg /= sWaitForCmplt else
cnInactivated;
onIpif_wrSrcDsc <= cnInactivated; --no support
oIpif_wrRem <= (others => cInactivated); --no support
--set read qualifiers
onIpif_rdDstDsc <= cnInactivated; --no support
--connect ipif with generic master
oMasterWaitrequest <= not iMasterWrite when inIpif_wrDstRdy = cnActivated else
not iMasterRead when ipifReadReq_reg = cActivated and iIpif_cmdAck = cActivated else cActivated;
oMasterReaddatavalid <= not inIpif_rdSrcRdy;
oIpif_wrData <= iMasterWritedata;
oMasterReaddata <= iIpif_rdData;
end rtl;
| gpl-2.0 | dfbe8edbb85d429ac5045ae10ddca1f6 | 0.588389 | 4.782378 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/openmac/src/convRmiiToMii-rtl-ea.vhd | 3 | 10,997 | -------------------------------------------------------------------------------
--! @file convRmiiToMii-rtl-ea.vhd
--
--! @brief RMII-to-MII converter
--
--! @details This is an RMII-to-MII converter to convert MII phy traces to RMII.
--! Example: MII PHY <--> RMII-to-MII converter <--> RMII MAC
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
--! Work library
library work;
--! use openmac package
use work.openmacPkg.all;
entity convRmiiToMii is
port (
--! Reset
iRst : in std_logic;
--! RMII Clock
iClk : in std_logic;
--! RMII transmit path
iRmiiTx : in tRmiiPath;
--! RMII receive path
oRmiiRx : out tRmiiPath;
--! MII receive clock
iMiiRxClk : in std_logic;
--! MII receive path
iMiiRx : in tMiiPath;
--! MII receive error
iMiiRxError : in std_logic;
--! MII transmit clock
iMiiTxClk : in std_logic;
--! MII transmit path
oMiiTx : out tMiiPath
);
end convRmiiToMii;
architecture rtl of convRmiiToMii is
constant DIBIT_SIZE : integer := 2;
constant NIBBLE_SIZE : integer := 4;
begin
TX_BLOCK : block
--fifo size must not be larger than 2**5
constant FIFO_NIBBLES_LOG2 : integer := 5;
signal fifo_half, fifo_full, fifo_empty, fifo_valid, txEnable_reg : std_logic;
signal fifo_wr, fifo_rd : std_logic;
signal fifo_din : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_dout, txData_reg : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_rdUsedWord : std_logic_vector (FIFO_NIBBLES_LOG2-1 downto 0);
--necessary for clr fifo
signal aclr, rTxEn_l : std_logic;
--convert dibits to nibble
signal sel_dibit : std_logic;
signal fifo_din_reg : std_logic_vector(iRmiiTx.data'range);
begin
fifo_din <= iRmiiTx.data & fifo_din_reg;
fifo_wr <= sel_dibit;
--convert dibits to nibble (to fit to fifo)
process(iClk, iRst)
begin
if iRst = cActivated then
sel_dibit <= cInactivated;
fifo_din_reg <= (others => cInactivated);
elsif iClk = cActivated and iClk'event then
if iRmiiTx.enable = cActivated then
sel_dibit <= not sel_dibit;
if sel_dibit = cInactivated then
fifo_din_reg <= iRmiiTx.data;
end if;
else
sel_dibit <= cInactivated;
end if;
end if;
end process;
fifo_half <= fifo_rdUsedWord(fifo_rdUsedWord'left);
oMiiTx.data <= txData_reg;
oMiiTx.enable <= txEnable_reg;
process(iMiiTxClk, iRst)
begin
if iRst = cActivated then
fifo_rd <= cInactivated;
fifo_valid <= cInactivated;
txData_reg <= (others => cInactivated);
txEnable_reg <= cInactivated;
elsif iMiiTxClk = cActivated and iMiiTxClk'event then
txData_reg <= fifo_dout;
txEnable_reg <= fifo_valid;
if fifo_rd = cInactivated and fifo_half = cActivated then
fifo_rd <= cActivated;
elsif fifo_rd = cActivated and fifo_empty = cActivated then
fifo_rd <= cInactivated;
end if;
if fifo_rd = cActivated and fifo_rdUsedWord > std_logic_vector(to_unsigned(1, fifo_rdUsedWord'length)) then
fifo_valid <= cActivated;
else
fifo_valid <= cInactivated;
end if;
end if;
end process;
--! This is the asynchronous FIFO used to decouple RMII from MII.
TXFIFO : entity work.asyncFifo
generic map (
gDataWidth => NIBBLE_SIZE,
gWordSize => 2**FIFO_NIBBLES_LOG2,
gSyncStages => 2,
gMemRes => "ON"
)
port map (
iAclr => aclr,
iWrClk => iClk,
iWrReq => fifo_wr,
iWrData => fifo_din,
oWrEmpty => open,
oWrFull => fifo_full,
oWrUsedw => open,
iRdClk => iMiiTxClk,
iRdReq => fifo_rd,
oRdData => fifo_dout,
oRdEmpty => fifo_empty,
oRdFull => open,
oRdUsedw => fifo_rdUsedWord
);
--sync Mii Tx En (=fifo_valid) to wr clk
process(iClk, iRst)
begin
if iRst = cActivated then
aclr <= cActivated; --reset fifo
rTxEn_l <= cInactivated;
elsif iClk = cActivated and iClk'event then
rTxEn_l <= iRmiiTx.enable;
aclr <= cInactivated; --default
--clear the full fifo after TX on RMII side is done
if fifo_full = cActivated and rTxEn_l = cActivated and iRmiiTx.enable = cInactivated then
aclr <= cActivated;
end if;
end if;
end process;
end block;
RX_BLOCK : block
--fifo size must not be larger than 2**5
constant FIFO_NIBBLES_LOG2 : integer := 5;
signal fifo_half, fifo_empty, fifo_valid : std_logic;
signal rxDataValid_reg, fifo_rd : std_logic;
signal rxError_reg : std_logic;
signal fifo_wr : std_logic;
signal rxData_reg : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_dout : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_rdUsedWord : std_logic_vector(FIFO_NIBBLES_LOG2-1 downto 0);
signal fifo_wrUsedWord : std_logic_vector(FIFO_NIBBLES_LOG2-1 downto 0);
--convert nibble to dibits
signal sel_dibit : std_logic;
signal fifo_rd_s : std_logic;
begin
process(iMiiRxClk, iRst)
begin
if iRst = cActivated then
rxData_reg <= (others => cInactivated);
rxDataValid_reg <= cInactivated;
rxError_reg <= cInactivated;
elsif iMiiRxClk = cActivated and iMiiRxClk'event then
rxData_reg <= iMiiRx.data;
rxDataValid_reg <= iMiiRx.enable;
rxError_reg <= iMiiRxError;
end if;
end process;
fifo_wr <= rxDataValid_reg and not rxError_reg;
oRmiiRx.data <= fifo_dout(fifo_dout'right+1 downto 0) when sel_dibit = cActivated else
fifo_dout(fifo_dout'left downto fifo_dout'left-1);
oRmiiRx.enable <= fifo_valid;
fifo_rd <= fifo_rd_s and not sel_dibit;
process(iClk, iRst)
begin
if iRst = cActivated then
sel_dibit <= cInactivated;
elsif iClk = cActivated and iClk'event then
if fifo_rd_s = cActivated or fifo_valid = cActivated then
sel_dibit <= not sel_dibit;
else
sel_dibit <= cInactivated;
end if;
end if;
end process;
fifo_half <= fifo_rdUsedWord(fifo_rdUsedWord'left);
process(iClk, iRst)
begin
if iRst = cActivated then
fifo_rd_s <= cInactivated;
fifo_valid <= cInactivated;
elsif iClk = cActivated and iClk'event then
if fifo_rd_s = cInactivated and fifo_half = cActivated then
fifo_rd_s <= cActivated;
elsif fifo_rd_s = cActivated and fifo_empty = cActivated then
fifo_rd_s <= cInactivated;
end if;
if fifo_rd_s = cActivated then
fifo_valid <= cActivated;
else
fifo_valid <= cInactivated;
end if;
end if;
end process;
--! This is the asynchronous FIFO used to decouple RMII from MII.
RXFIFO : entity work.asyncFifo
generic map (
gDataWidth => NIBBLE_SIZE,
gWordSize => 2**FIFO_NIBBLES_LOG2,
gSyncStages => 2,
gMemRes => "ON"
)
port map (
iAclr => iRst,
iWrClk => iMiiRxClk,
iWrReq => fifo_wr,
iWrData => rxData_reg,
oWrEmpty => open,
oWrFull => open,
oWrUsedw => open,
iRdClk => iClk,
iRdReq => fifo_rd,
oRdData => fifo_dout,
oRdEmpty => fifo_empty,
oRdFull => open,
oRdUsedw => fifo_rdUsedWord
);
end block;
end rtl;
| gpl-2.0 | bead90d82ad8b2b353e0eb4aa92c9a66 | 0.529053 | 4.738044 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/hostinterface/src/irqGenRtl.vhd | 3 | 7,254 | -------------------------------------------------------------------------------
--! @file irqGenRtl.vhd
--
--! @brief irq generator with sync latch feature
--
--! @details The irq generator is similar to a ordinary interrupt controller,
--! however, it is extended with a "sync-latch" feature. This enables to
--! throttle the interrupt requests and assert the general irq with the sync
--! input signal. Hence, any irq source is deferred to the sync assertion.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
--! Work library
library work;
--! use host interface package for specific types
use work.hostInterfacePkg.all;
entity irqGen is
generic (
--! number of interrupt sources
gIrqSourceCount : natural := 3
);
port (
-- Global
--! component wide clock signal
iClk : in std_logic;
--! component wide reset signal
iRst : in std_logic;
-- Irq
--! sync source
iSync : in std_logic;
--! interrupt source vector (pulse)
iIrqSource : in std_logic_vector(gIrqSourceCount downto 1);
--! interrupt signal
oIrq : out std_logic;
-- Control
--! master enable
iIrqMasterEnable : in std_logic;
--! interrupt source enable vector ('right is sync)
iIrqSourceEnable : in std_logic_vector(gIrqSourceCount downto 0);
--! interrupt acknowledge (pulse, 'right is sync)
iIrqAcknowledge : in std_logic_vector(gIrqSourceCount downto 0);
--! interrupt source pending
oIrgPending : out std_logic_vector(gIrqSourceCount downto 0)
);
end irqGen;
architecture Rtl of irqGen is
--! sync rising edge
signal syncRising : std_logic;
--! interrupt register latch
signal irqRegLatch, irqRegLatch_next : std_logic_vector(gIrqSourceCount downto 0);
--! interrupt source store
signal irqSourceStore, irqSourceStore_next : std_logic_vector(gIrqSourceCount downto 1);
--! unregistered irq out signal
signal unregIrq, irq_reg : std_logic;
begin
--! generate pulse for rising edge of sync
syncEdgeDet : entity libcommon.edgedetector
port map (
iArst => iRst,
iClk => iClk,
iEnable => cActivated,
iData => iSync,
oRising => syncRising,
oFalling => open,
oAny => open
);
--! irq registers
clkdReg : process(iClk)
begin
if rising_edge(iClk) then
if iRst = cActivated then
irqRegLatch <= (others => cInactivated);
irqSourceStore <= (others => cInactivated);
irq_reg <= cInactivated;
else
irqRegLatch <= irqRegLatch_next;
irqSourceStore <= irqSourceStore_next;
irq_reg <= unregIrq;
end if;
end if;
end process;
oIrq <= irq_reg;
--! irq register control
combIrqRegCont : process (
iIrqSource,
iIrqAcknowledge,
irqRegLatch,
irqSourceStore,
syncRising,
iIrqSourceEnable(iIrqSourceEnable'right)
)
begin
--default
irqRegLatch_next <= irqRegLatch;
irqSourceStore_next <= irqSourceStore;
-- do acknowledge with latched and source register
for i in gIrqSourceCount downto 1 loop
if iIrqAcknowledge(i) = cActivated then
irqRegLatch_next(i) <= cInactivated;
irqSourceStore_next(i) <= cInactivated;
end if;
end loop;
if iIrqAcknowledge(irqRegLatch'right) = cActivated then
irqRegLatch_next(irqRegLatch'right) <= cInactivated;
end if;
for i in gIrqSourceCount downto 1 loop
if iIrqSource(i) = cActivated then
irqSourceStore_next(i) <= cActivated;
end if;
end loop;
-- trigger irq with sync
if syncRising = cActivated then
-- loop through all irq sources
for i in gIrqSourceCount downto 1 loop
irqRegLatch_next(i) <= irqSourceStore(i);
end loop;
-- activate sync irq if it is enabled
-- (sync irqs in the past are not of interest!)
irqRegLatch_next(irqRegLatch'right) <= iIrqSourceEnable(iIrqSourceEnable'right);
end if;
end process;
--! output irq register
oIrgPending <= irqRegLatch;
--! irq signal generation
combIrqGen : process (
irqRegLatch,
iIrqMasterEnable,
iIrqSourceEnable
)
variable vTmp : std_logic;
begin
--default
unregIrq <= cInactivated;
-- the master enable overrules everything
if iIrqMasterEnable = cActivated then
-- check individual irqs
vTmp := cInactivated;
for i in gIrqSourceCount downto 0 loop
vTmp := vTmp or (iIrqSourceEnable(i) and irqRegLatch(i));
end loop;
-- variable holds irq state
unregIrq <= vTmp;
end if;
end process;
end Rtl;
| gpl-2.0 | 39c3cf8dc2c491068b8807292459ec2f | 0.591536 | 5.016598 | false | false | false | false |
cnplab/blockmon | fw-combo/src/netcope-sim/models/fl_bfm_pkg.vhd | 1 | 13,086 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- fl_bfm_pkg.vhd: Support package for bfm_sim
-- Copyright (C) 2007 CESNET
-- Author(s): Vlastimil Kosar <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: fl_bfm_pkg.vhd 12021 2011-04-15 08:23:45Z kastovsky $
--
-- TODO:
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.fl_bfm_rdy_pkg.all;
-- ----------------------------------------------------------------------------
-- FrameLink Bus BFM Package
-- ----------------------------------------------------------------------------
PACKAGE fl_bfm_pkg IS
TYPE StartDriveType IS (SOP, SOF, NOP);
TYPE EndDriveType IS (EOP, EOF, NOP);
CONSTANT DataTypeLength : integer := 65535;
TYPE Item IS RECORD
Data : std_logic_vector(7 downto 0);
StartControl :StartDriveType;
EndControl :EndDriveType;
END RECORD;
TYPE DataType IS ARRAY (0 TO DataTypeLength) of Item;
-- Operation parameters
TYPE CmdTypeItem IS RECORD
RDYDriver : RDYSignalDriver;
Length : integer; -- Length
Data : DataType; -- Data
--Enable : boolean;
--FileName : FileNameType;
END RECORD;
TYPE CmdType IS ARRAY (0 to 15) of CmdTypeItem;
-- Command REQ/ACK record
TYPE flCmdTypeItem IS
RECORD
Req : std_logic;
ReqAck : std_logic;
Ack : std_logic;
END RECORD;
----------------------------------------------------------------------------
-- SIGNAL FOR SETTINGS BFM REQUESTS
----------------------------------------------------------------------------
signal flCmd_0 : flCmdTypeItem := ('0','Z','Z');
signal flCmd_1 : flCmdTypeItem := ('0','Z','Z');
signal flCmd_2 : flCmdTypeItem := ('0','Z','Z');
signal flCmd_3 : flCmdTypeItem := ('0','Z','Z');
signal flCmd_4 : flCmdTypeItem := ('0','Z','Z');
signal flCmd_5 : flCmdTypeItem := ('0','Z','Z');
signal flCmd_6 : flCmdTypeItem := ('0','Z','Z');
signal flCmd_7 : flCmdTypeItem := ('0','Z','Z');
signal flCmd_8 : flCmdTypeItem := ('0','Z','Z');
signal flCmd_9 : flCmdTypeItem := ('0','Z','Z');
signal flCmd_A : flCmdTypeItem := ('0','Z','Z');
signal flCmd_B : flCmdTypeItem := ('0','Z','Z');
signal flCmd_C : flCmdTypeItem := ('0','Z','Z');
signal flCmd_D : flCmdTypeItem := ('0','Z','Z');
signal flCmd_E : flCmdTypeItem := ('0','Z','Z');
signal flCmd_F : flCmdTypeItem := ('0','Z','Z');
----------------------------------------------------------------------------
-- BFM FUNCTIONS
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Functions is called by IB BFM model to obtain command parameters
PROCEDURE ReadCommand (VARIABLE Cmd : OUT CmdTypeItem; CONSTANT FLBFMID : IN integer);
----------------------------------------------------------------------------
-- Functions is called by IB BFM model to return results
PROCEDURE WriteCommand (VARIABLE Cmd : IN CmdTypeItem; CONSTANT FLBFMID : IN integer);
-- convert character to upper case
function to_upper(c:character) return character;
-- convert hexa character to std_logic_vector
procedure convert_character(data:inout std_logic_vector; -- output 4-bit number
c:character); -- input hexa value in character
-- load 32bit number from input string
procedure load_32(data:inout std_logic_vector; -- 32bit number
s:string; -- input string
i:inout integer; -- current position in string
size:integer; -- size of string
count: inout integer); -- count of valid bytes in 32-bit number
-- read variable length string from input file
procedure read_string(file in_file: TEXT; --input file
out_string: out string; --output string
load_count: inout integer); --number of read characters
procedure SendPreparedData(
CONSTANT RDYDriver : IN RDYSignalDriver;
SIGNAL flCmd : INOUT flCmdTypeItem;
CONSTANT FLBFMID : IN integer;
CONSTANT Cmd : IN CmdType
);
PROCEDURE FLWriteFile (
CONSTANT FileName : IN string; -- Filename from where are data writen
CONSTANT RDYDriver: IN RDYSignalDriver;
SIGNAL flCmd : INOUT flCmdTypeItem;
CONSTANT FLBFMID : IN integer
);
END fl_bfm_pkg;
-- ----------------------------------------------------------------------------
-- FrameLink Bus BFM Package BODY
-- ----------------------------------------------------------------------------
PACKAGE BODY fl_bfm_pkg IS
-----------------------------------------------------------------------------
-- Command shared variable
SHARED VARIABLE Command : CmdType;
-----------------------------------------------------------------------------
-- Functions is called by IB BFM model to obtain command parameters
PROCEDURE ReadCommand (VARIABLE Cmd : OUT CmdTypeItem; CONSTANT FLBFMID : IN integer) IS
BEGIN
Cmd := Command(FLBFMID);
END;
-----------------------------------------------------------------------------
-- Functions is called by IB BFM model to return results
PROCEDURE WriteCommand (VARIABLE Cmd : IN CmdTypeItem; CONSTANT FLBFMID : IN integer) IS
BEGIN
Command(FLBFMID) := Cmd;
END;
-- read variable length string from input file
procedure read_string(file in_file: TEXT;out_string: out string;load_count: inout integer) is
variable l:line;
variable c:character;
variable not_eof: boolean;
begin
load_count:=0;
readline(in_file, l);
-- read characters from line up to length of string or end of line
for i in out_string'range loop
read(l, c, not_eof);
out_string(i) := c;
if not not_eof then -- end of line
exit;
end if;
load_count:=load_count+1;
end loop;
end read_string;
-- convert character to upper case
function to_upper(c:character) return character is
variable output:character;
begin
case c is
when 'a' => output := 'A';
when 'b' => output := 'B';
when 'c' => output := 'C';
when 'd' => output := 'D';
when 'e' => output := 'E';
when 'f' => output := 'F';
when others => output := c;
end case;
return output;
end;
-- convert hexa character to std_logic_vector
procedure convert_character(data:inout std_logic_vector;c:character) is
variable c_decoded:std_logic_vector(3 downto 0);
variable lbound:integer;
begin
case to_upper(c) is
when '0'=> c_decoded :="0000";
when '1'=> c_decoded :="0001";
when '2'=> c_decoded :="0010";
when '3'=> c_decoded :="0011";
when '4'=> c_decoded :="0100";
when '5'=> c_decoded :="0101";
when '6'=> c_decoded :="0110";
when '7'=> c_decoded :="0111";
when '8'=> c_decoded :="1000";
when '9'=> c_decoded :="1001";
when 'A'=> c_decoded :="1010";
when 'B'=> c_decoded :="1011";
when 'C'=> c_decoded :="1100";
when 'D'=> c_decoded :="1101";
when 'E'=> c_decoded :="1110";
when 'F'=> c_decoded :="1111";
when others => c_decoded :="ZZZZ";
end case;
lbound:=data'left - 4;
data:=data(lbound downto 0)&c_decoded;
end convert_character;
-- load 32bit number from input string
procedure load_32(data:inout std_logic_vector;s:string;i:inout integer;size:integer;count: inout integer) is
variable j:integer;
begin
data(31 downto 0) := (others => '0');
count := 0;
convert_character(data,s(i));
i:=i+1;
convert_character(data,s(i));
i:=i+1;
if (i<size) then
count:=count + 1;
convert_character(data,s(i));
i:=i+1;
convert_character(data,s(i));
i:=i+1;
end if;
if (i<size) then
count:=count + 1;
convert_character(data,s(i));
i:=i+1;
convert_character(data,s(i));
i:=i+1;
end if;
if (i<size) then
count:=count + 1;
convert_character(data,s(i));
i:=i+1;
convert_character(data,s(i));
i:=i+1;
end if;
end load_32;
-- Send data prepared in the Cmd parameter
procedure SendPreparedData(
CONSTANT RDYDriver : IN RDYSignalDriver;
SIGNAL flCmd : INOUT flCmdTypeItem;
CONSTANT FLBFMID : IN integer;
CONSTANT Cmd : IN CmdType
) IS
begin
Command(FLBFMID) := Cmd(FLBFMID);
flCmd.Req <= '1';
WAIT ON flCmd.ReqAck;
flCmd.Req <= '0';
WAIT ON flCmd.Ack;
end SendPreparedData;
PROCEDURE FLWriteFile (
CONSTANT FileName : IN string; -- Filename from where are data writen
CONSTANT RDYDriver: IN RDYSignalDriver;
SIGNAL flCmd : INOUT flCmdTypeItem;
CONSTANT FLBFMID : IN integer
) IS
file input_file : TEXT;
variable file_status : file_open_status;
variable s : string(1 to 2048);
variable size : integer;
variable index : integer;
variable count : integer;
variable i : integer;
variable data : std_logic_vector(31 downto 0);
BEGIN
for i in 0 to DataTypeLength loop
Command(FLBFMID).Data(i).StartControl := NOP;
Command(FLBFMID).Data(i).EndControl := NOP;
end loop;
Command(FLBFMID).Data(0).StartControl := SOF;
index := 0;
file_open(file_status, input_file, FileName, READ_MODE);
assert (file_status = OPEN_OK) report "File with data was not found!" severity ERROR;
while (not endfile(input_file)) loop
read_string(input_file, s, size);
i := 1;
if (s(i) = '#') then
assert (not(index - 1 <= 0)) report "# found on file start" severity ERROR;
Command(FLBFMID).Data(index - 1).EndControl := EOF;
Command(FLBFMID).Data(index).StartControl := SOF;
--i := i + 1;
elsif (s(i) = '$') then
assert (not(index - 1 <= 0)) report "$ found on file start" severity ERROR;
Command(FLBFMID).Data(index - 1).EndControl := EOP;
Command(FLBFMID).Data(index).StartControl := SOP;
--i := i + 1;
elsif (s(i) = '-') then
else
while (i<=size) loop
load_32(data, s, i, size, count);
for j in 0 to count loop
Command(FLBFMID).Data(index).Data := data((j + 1) * 8 - 1 downto j * 8);
index := index + 1;
end loop;
end loop;
end if;
end loop;
file_close(input_file);
Command(FLBFMID).Length := index - 1;
Command(FLBFMID).RDYDriver := RDYDriver;
-- Req toggles each time we want the BFM to do a new check.
flCmd.Req <= '1';
WAIT ON flCmd.ReqAck;
flCmd.Req <= '0';
WAIT UNTIL flCmd.Ack = '1';
END FLWriteFile;
END fl_bfm_pkg;
| bsd-3-clause | 35f9dd7de074d89ccc246a4ee4c269d6 | 0.558765 | 4.214493 | false | false | false | false |
cnplab/blockmon | fw-combo/src/generator/application_core.vhd | 1 | 15,998 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- application_core.vhd : Application core module
-- Copyright (C) 2009 CESNET
-- Author(s): Pavol Korcek <[email protected]>
-- Petr Kastovsky <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: application_core.vhd 12117 2009-11-25 13:35:03Z kastovsky $
--
-- --------------------------------------------------------------------
-- Entity declaration
-- --------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.lb_pkg.all; -- Local Bus Package
entity application_core is
port (
CLK : in std_logic;
RESET : in std_logic;
-- MI32
mi32_dwr : in std_logic_vector(31 downto 0);
mi32_addr : in std_logic_vector(31 downto 0);
mi32_rd : in std_logic;
mi32_wr : in std_logic;
mi32_be : in std_logic_vector(3 downto 0);
mi32_drd : out std_logic_vector(31 downto 0);
mi32_ardy : out std_logic;
mi32_drdy : out std_logic;
-- FL
fl_sof_n : out std_logic;
fl_sop_n : out std_logic;
fl_eop_n : out std_logic;
fl_eof_n : out std_logic;
fl_src_rdy_n : out std_logic;
fl_dst_rdy_n : in std_logic;
fl_data : out std_logic_vector(127 downto 0);
fl_rem : out std_logic_vector(3 downto 0)
);
end application_core;
architecture full of application_core is
-- ----------------------------------------------------------------------------
-- Signal declaration
-- ----------------------------------------------------------------------------
constant gndvec : std_logic_vector(31 downto 0) := X"00000000";
signal status : std_logic_vector(31 downto 0); -- status/control register
signal init0 : std_logic_vector(31 downto 0); -- init vector 0
signal init1 : std_logic_vector(31 downto 0); -- init vector 1
signal pkt_length : std_logic_vector(31 downto 0); -- actual sw packet length
signal pkt_num0 : std_logic_vector(31 downto 0); -- number of packet to send (low register)
signal pkt_num1 : std_logic_vector(31 downto 0); -- number of packet to send (high register)
signal pkt_send0 : std_logic_vector(31 downto 0); -- number of sent packets (low register)
signal pkt_send1 : std_logic_vector(31 downto 0); -- number of sent packets (high register)
signal seed : std_logic_vector(63 downto 0); -- initialization seed
signal clear : std_logic;
signal length_shift_enable : std_logic; -- shift to next random length
signal length_fill_enable : std_logic; -- filling with seed value enabled
signal rnd_length : std_logic_vector(10 downto 0); -- random length output
signal reg_length : std_logic_vector(10 downto 0); -- random length output
signal length : std_logic_vector(10 downto 0); -- finall length
signal length_sel : std_logic; -- length selector
signal data_shift_enable : std_logic; -- shift to next random data
signal data_fill_enable : std_logic; -- filling with seed value enabled
signal rnd_data : std_logic_vector(127 downto 0); -- random data output
signal last_data : std_logic; -- last data send (EOF and BE active)
signal last_be : std_logic_vector(3 downto 0); -- BE for network frame link
signal num_packets : std_logic_vector(63 downto 0); -- number of packetss to send
signal reg_send_packets : std_logic_vector(63 downto 0); -- number of actually sent packet
signal last_pkt : std_logic;
signal status_run_set : std_logic;
signal status_stp_set : std_logic;
signal status_run_clr : std_logic;
signal gen_fsm_eop : std_logic;
signal gen_fsm_sop : std_logic;
signal gen_fsm_nd : std_logic;
signal gen_fsm_nl : std_logic;
signal gen_fsm_stopped : std_logic;
signal gen_fsm_src_rdy : std_logic;
signal gen_fsm_dst_rdy : std_logic;
signal mux_rem_sel : std_logic;
signal mux_data_sel : std_logic;
-- ----------------------------------------------------------------------------
-- Architecture body
-- ----------------------------------------------------------------------------
begin
-- -------------------------------------------------------------------------
-- User registers
-- -------------------------------------------------------------------------
mi32_drdy <= mi32_rd;
mi32_ardy <= mi32_wr or mi32_rd;
REGISTERS_U : process(CLK)
begin
if (CLK = '1' and CLK'event) then
if (RESET = '1') then
status(31 downto 1) <= (others => '0');
init0 <= X"ABCDEF12"; -- init vector 0
init1 <= X"34567890"; -- init vector 1
pkt_length <= X"00000001"; -- actual packet length
pkt_num0 <= X"FFFFFFFF"; -- number of packet to send (low register)
pkt_num1 <= X"FFFFFFFF"; -- number of packet to send (high register)
-- pkt_send0 <= X"00000000"; -- number of sent packets (low register)
-- pkt_send1 <= X"00000000"; -- number of sent packets (high register)
else
status_run_set <= '0';
status_stp_set <= '0';
-- Write to my registers
if (mi32_wr = '1') then
case mi32_addr(4 downto 2) is
when "000" =>
status_run_set <= mi32_dwr(0);
status_stp_set <= not mi32_dwr(0);
status(31 downto 1) <= mi32_dwr(31 downto 1);
when "001" =>
for i in 0 to 3 loop
if mi32_be(i) = '1' then
init0(i*8+7 downto i*8) <= mi32_dwr(i*8+7 downto i*8);
end if;
end loop;
when "010" =>
for i in 0 to 3 loop
if mi32_be(i) = '1' then
init1(i*8+7 downto i*8) <= mi32_dwr(i*8+7 downto i*8);
end if;
end loop;
when "011" =>
for i in 0 to 3 loop
if mi32_be(i) = '1' then
pkt_length(i*8+7 downto i*8) <= mi32_dwr(i*8+7 downto i*8);
end if;
end loop;
when "100" =>
for i in 0 to 3 loop
if mi32_be(i) = '1' then
pkt_num0(i*8+7 downto i*8) <= mi32_dwr(i*8+7 downto i*8);
end if;
end loop;
when "101" =>
for i in 0 to 3 loop
if mi32_be(i) = '1' then
pkt_num1(i*8+7 downto i*8) <= mi32_dwr(i*8+7 downto i*8);
end if;
end loop;
when "110" =>
for i in 0 to 3 loop
if mi32_be(i) = '1' then
--pkt_send0(i*8+7 downto i*8) <= mi32_dwr(i*8+7 downto i*8); -- r
end if;
end loop;
when "111" =>
for i in 0 to 3 loop
if mi32_be(i) = '1' then
--pkt_send1(i*8+7 downto i*8) <= mi32_dwr(i*8+7 downto i*8); -- r
end if;
end loop;
when others => null;
end case;
end if;
-- Read from my registers
case mi32_addr(4 downto 2) is
when "000" => mi32_drd <= status;
when "001" => mi32_drd <= init0;
when "010" => mi32_drd <= init1;
when "011" => mi32_drd <= pkt_length;
when "100" => mi32_drd <= pkt_num0;
when "101" => mi32_drd <= pkt_num1;
when "110" => mi32_drd <= pkt_send0;
when "111" => mi32_drd <= pkt_send1;
when others => mi32_drd <= X"DEADBEEF";
end case;
end if;
end if;
end process;
status_run_clr <= gen_fsm_stopped or status_stp_set;
-- register reg_status ------------------------------------------------------
reg_statusp: process(CLK)
begin
if (CLK'event AND CLK = '1') then
if ( RESET = '1') then
status(0) <= '0';
elsif (status_run_set = '1') then
status(0) <= '1';
elsif (status_run_clr = '1') then
status(0) <= '0';
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- Generators
-- -------------------------------------------------------------------------
seed <= init1 & init0;
PKT_LENGTH_GEN_U : entity work.pseudorand_length_gen
port map (
RESET => RESET,
CLK => CLK,
S_EN => length_shift_enable,
F_EN => length_fill_enable,
DIN => seed(10 downto 0),
DOUT => rnd_length
);
PKT_DATA_GEN_U : entity work.pseudorand_data_gen
port map (
CLK => CLK,
S_EN => data_shift_enable,
F_EN => data_fill_enable,
DIN => seed,
DOUT => rnd_data
);
-- -------------------------------------------------------------------------
-- Internal registers
-- -------------------------------------------------------------------------
clear <= (last_data AND gen_fsm_dst_rdy) OR status_run_set;
-- register ---------------------------------------------------------------
reg_lengthp: process(RESET, CLK)
begin
if (RESET = '1') then
reg_length <= (others => '0');
elsif (CLK'event AND CLK = '1') then
if(clear = '1') then
reg_length <= length;
elsif(data_shift_enable = '1') then -- when request for next data
reg_length <= reg_length - 16; -- decrement
end if;
end if;
end process;
mux_data_sel <= status(2);
-- multiplexor mux_data ------------------------------------------------------
mux_datap: process(mux_data_sel, rnd_data)
begin
case mux_data_sel is
when '0' => fl_data <= (others => '0');
when '1' => fl_data <= rnd_data;
when others => fl_data <= (others => 'X');
end case;
end process;
length_sel <= status(1);
-- multiplexor length ------------------------------------------------------
length_muxp: process(length_sel, pkt_length(10 downto 0), rnd_length)
begin
case length_sel is
when '0' => length <= pkt_length(10 downto 0); -- user length
when '1' => length <= rnd_length;
when others => length <= (others => '1');
end case;
end process;
last_be <= length(3 downto 0) - 1; -- BE
mux_rem_sel <= gen_fsm_eop;
-- multiplexor mux_rem ------------------------------------------------------
mux_remp: process(mux_rem_sel, last_be)
begin
case mux_rem_sel is
when '0' => fl_rem <= (others => '1');
when '1' => fl_rem <= last_be;
when others => fl_rem <= (others => 'X');
end case;
end process;
-- register ---------------------------------------------------------------
reg_send_packetsp: process(RESET, CLK)
begin
if (RESET = '1') then
reg_send_packets <= (others => '0');
elsif (CLK'event AND CLK = '1') then
if (status_run_set = '1') then
reg_send_packets <= (others => '0');
elsif(length_shift_enable = '1') then -- when next packet send
reg_send_packets <= reg_send_packets + 1; -- increment
end if;
end if;
end process;
pkt_send0 <= reg_send_packets(31 downto 0);
pkt_send1 <= reg_send_packets(63 downto 32);
num_packets <= pkt_num1 & pkt_num0; -- from SW
-- -------------------------------------------------------------------------
-- Comparators
-- -------------------------------------------------------------------------
last_data <= '1' when (reg_length <= 16) else -- last data in packet
'0';
last_pkt <= '1' when (reg_send_packets = num_packets) else -- last packet to send
'0';
GEN_FSM_I: entity work.GEN_FSM
port map (
-- global signals
CLK => CLK,
RESET => RESET,
-- input signals
START => status(0),
PACKET_END => last_data,
TRANSMIT_END => last_pkt,
DST_RDY => gen_fsm_dst_rdy,
-- output signals
SOP => gen_fsm_sop,
EOP => gen_fsm_eop,
NEXT_DATA => gen_fsm_nd,
NEXT_LEN => gen_fsm_nl,
SRC_RDY => gen_fsm_src_rdy,
STOPPED => gen_fsm_stopped
);
gen_fsm_dst_rdy <= not fl_dst_rdy_n;
fl_src_rdy_n <= not gen_fsm_src_rdy;
length_shift_enable <= gen_fsm_nl XOR status_run_set;
data_shift_enable <= gen_fsm_nd XOR status_run_set;
length_fill_enable <= gen_fsm_stopped;
data_fill_enable <= gen_fsm_stopped;
fl_sof_n <= not gen_fsm_sop;
fl_sop_n <= not gen_fsm_sop;
fl_eof_n <= not gen_fsm_eop;
fl_eop_n <= not gen_fsm_eop;
end architecture full;
| bsd-3-clause | 59d8c51d6cf7cd752d7c01b7075e6a78 | 0.469371 | 4.107317 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/lib/src/clkXingRtl.vhd | 3 | 8,454 | -------------------------------------------------------------------------------
--! @file clkXingRtl.vhd
--
--! @brief Clock Crossing Bus converter
--
--! @details Used to transfer a faster slave interface to a slower one.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! need reduce or operation
use ieee.std_logic_misc.OR_REDUCE;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity clkXing is
generic (
gCsNum : natural := 2;
gDataWidth : natural := 32
);
port (
iArst : in std_logic;
--fast
iFastClk : in std_logic;
iFastCs : in std_logic_vector(gCsNum-1 downto 0);
iFastRNW : in std_logic;
oFastReaddata : out std_logic_vector(gDataWidth-1 downto 0);
oFastWrAck : out std_logic;
oFastRdAck : out std_logic;
--slow
iSlowClk : in std_logic;
oSlowCs : out std_logic_vector(gCsNum-1 downto 0);
oSlowRNW : out std_logic;
iSlowReaddata : in std_logic_vector(gDataWidth-1 downto 0);
iSlowWrAck : in std_logic;
iSlowRdAck : in std_logic
);
end entity;
architecture rtl of clkXing is
--! Fsm type
type tFsm is (sIdle, sTransfer);
--! Clock domain registers
type tRegClkDomain is record
chipselect : std_logic_vector(gCsNum-1 downto 0);
rnw : std_logic;
sync : std_logic;
ack : std_logic;
fsm : tFsm;
end record;
--! Register init
constant cRegClkDomainInit : tRegClkDomain := (
chipselect => (others => cInactivated),
rnw => cInactivated,
sync => cInactivated,
ack => cInactivated,
fsm => sIdle
);
--! Slow clock domain register
signal slowClkReg : tRegClkDomain;
signal slowClkReg_next : tRegClkDomain;
--! Fast clock domain register
signal fastClkReg : tRegClkDomain;
signal fastClkReg_next : tRegClkDomain;
--! Readdata register
signal readdataReg : std_logic_vector(iSlowReaddata'range);
signal readdataReg_next : std_logic_vector(readdataReg'range);
--! Transferred sync signal (fast ---> slow)
signal tranSync_sync : std_logic;
--! Transferred ack signal (slow ---> fast)
signal tranAck_sync : std_logic;
begin
-- Map registers to outputs
-- FAST
oFastWrAck <= fastClkReg.ack and not iFastRNW;
oFastRdAck <= fastClkReg.ack and iFastRNW;
oFastReaddata <= readdataReg;
-- SLOW
oSlowCs <= slowClkReg.chipselect;
oSlowRNW <= iFastRNW;
--! Fast clock domain logic
fastComb : process (
fastClkReg,
tranAck_sync,
iFastCs, iFastRNW
)
begin
-- General defaults to avoid latches
fastClkReg_next <= fastClkReg;
-- Inactivate pulsing registers
fastClkReg_next.sync <= cInactivated;
-- Assign transferred signals
fastClkReg_next.ack <= tranAck_sync;
case fastClkReg.fsm is
when sIdle =>
if OR_REDUCE(iFastCs) = cActivated then
fastClkReg_next.fsm <= sTransfer;
fastClkReg_next.sync <= cActivated;
fastClkReg_next.chipselect <= iFastCs;
fastClkReg_next.rnw <= iFastRNW;
end if;
when sTransfer =>
if fastClkReg.ack = cActivated then
fastClkReg_next.fsm <= sIdle;
end if;
end case;
end process fastComb;
--! Slow clock domain logic
slowComb : process (
slowClkReg, fastClkReg, readdataReg,
tranSync_sync,
iSlowWrAck, iSlowRdAck, iSlowReaddata
)
begin
-- Default
slowClkReg_next <= slowClkReg;
readdataReg_next <= readdataReg;
-- Inactivate pulsing registers
slowClkReg_next.ack <= cInactivated;
-- Assign transferred signals
slowClkReg_next.sync <= tranSync_sync;
case slowClkReg.fsm is
when sIdle =>
if slowClkReg.sync = cActivated then
slowClkReg_next.fsm <= sTransfer;
end if;
when sTransfer =>
slowClkReg_next.chipselect <= fastClkReg.chipselect;
slowClkReg_next.rnw <= fastClkReg.rnw;
if iSlowRdAck = cActivated or iSlowWrAck = cActivated then
slowClkReg_next.fsm <= sIdle;
slowClkReg_next.chipselect <= (others => cInactivated);
slowClkReg_next.ack <= cActivated;
if iSlowRdAck = cActivated then
readdataReg_next <= iSlowReaddata;
end if;
end if;
end case;
end process slowComb;
--! Fast clock registers
fastClockReg : process(iArst, iFastClk)
begin
if iArst = cActivated then
fastClkReg <= cRegClkDomainInit;
elsif rising_edge(iFastClk) then
fastClkReg <= fastClkReg_next;
end if;
end process fastClockReg;
--! Slow clock registers
slowClockReg : process(iArst, iSlowClk)
begin
if iArst = cActivated then
slowClkReg <= cRegClkDomainInit;
readdataReg <= (others => cInactivated);
elsif rising_edge(iSlowClk) then
slowClkReg <= slowClkReg_next;
readdataReg <= readdataReg_next;
end if;
end process slowClockReg;
--! Transfer sync pulse to slow clock domain
tranSyncToSlow : entity libcommon.syncTog
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iSrc_rst => iArst,
iSrc_clk => iFastClk,
iSrc_data => fastClkReg.sync,
iDst_rst => iArst,
iDst_clk => iSlowClk,
oDst_data => tranSync_sync
);
--! Transfer ack pulse to fast clock domain
tranAckToFast : entity libcommon.syncTog
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iSrc_rst => iArst,
iSrc_clk => iSlowClk,
iSrc_data => slowClkReg.ack,
iDst_rst => iArst,
iDst_clk => iFastClk,
oDst_data => tranAck_sync
);
end architecture;
| gpl-2.0 | b3f172f32bf31db97f8483ca59ae4aa3 | 0.571091 | 4.89803 | false | false | false | false |
cnplab/blockmon | fw-combo/src/generator/comp/pseudorand_length_gen.vhd | 1 | 7,738 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- pseudorand_length_gen.vhd : LFSR based pseudorandom generator module
-- Copyright (C) 2009 CESNET
-- Author(s): Pavol Korcek <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: pseudorand_length_gen.vhd 12090 2009-11-24 13:57:11Z korcek $
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.lfsr_pkg.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity pseudorand_length_gen is
generic (
TAPS_1024 : LFSR_TAPS :=(10, 7);
TAPS_256 : LFSR_TAPS :=(8,6,5,4);
TAPS_128 : LFSR_TAPS :=(7,6);
TAPS_64 : LFSR_TAPS :=(6,5)
);
port (
RESET : in std_logic; -- reset
CLK : in std_logic; -- clock signal
S_EN : in std_logic; -- shift enable
F_EN : in std_logic; -- fill enable
DIN : in std_logic_vector(10 downto 0); -- seed
DOUT : out std_logic_vector(10 downto 0) -- data out
);
end entity pseudorand_length_gen;
-- ----------------------------------------------------------------------------
-- Architecture declaration
-- ----------------------------------------------------------------------------
architecture beh of pseudorand_length_gen is
-- pseudorandom output registers
signal reg_1024 : std_logic_vector(9 downto 0); -- 0 - 1023
signal reg_256 : std_logic_vector(7 downto 0); -- 0 - 255
signal reg_1024_and_256 : std_logic_vector(10 downto 0); -- 0 - 1278
signal reg_128 : std_logic_vector(6 downto 0); -- 0 - 127
signal reg_64 : std_logic_vector(5 downto 0); -- 0 - 63
signal reg_128_and_64 : std_logic_vector(7 downto 0); -- 0 - 190
signal reg_last : std_logic_vector(10 downto 0); -- 0 - 1468
signal reg_add : std_logic_vector(10 downto 0); -- 64 - 1532
-- init vectors
signal init_1024 : std_logic_vector(9 downto 0);
signal init_256 : std_logic_vector(7 downto 0);
signal init_128 : std_logic_vector(6 downto 0);
signal init_64 : std_logic_vector(5 downto 0);
begin
-- -------------------------------------------------------------------------
inst1024_u: entity work.lfsr_parallel
generic map(
LFSR_LENGTH => 10,
TAPS => TAPS_1024
)
port map(
CLK => CLK,
S_EN => S_EN,
F_EN => F_EN,
DIN => init_1024,
DOUT => reg_1024
);
init_1024 <= DIN(0) & DIN(2) & DIN(9) & DIN(8) & DIN(0) & DIN(1) & DIN(7) & DIN(5) & DIN(3) & DIN(3);
-- -------------------------------------------------------------------------
inst256_u: entity work.lfsr_parallel
generic map(
LFSR_LENGTH => 8,
TAPS => TAPS_256
)
port map(
CLK => CLK,
S_EN => S_EN,
F_EN => F_EN,
DIN => init_256,
DOUT => reg_256
);
init_256 <= DIN(7) & DIN(7) & DIN(6) & DIN(5) & DIN(1) & DIN(2) & DIN(2) & DIN(4);
-- -------------------------------------------------------------------------
inst128_u: entity work.lfsr_parallel
generic map(
LFSR_LENGTH => 7,
TAPS => TAPS_128
)
port map(
CLK => CLK,
S_EN => S_EN,
F_EN => F_EN,
DIN => init_128,
DOUT => reg_128
);
init_128 <= DIN(6) & DIN(2) & DIN(3) & DIN(3) & DIN(3) & DIN(5) & DIN(9);
-- -------------------------------------------------------------------------
inst64_u: entity work.lfsr_parallel
generic map(
LFSR_LENGTH => 6,
TAPS => TAPS_64
)
port map(
CLK => CLK,
S_EN => S_EN,
F_EN => F_EN,
DIN => init_64,
DOUT => reg_64
);
init_64 <= DIN(7) & DIN(8) & DIN(9) & DIN(9) & DIN(0) & DIN(4);
-- register ------------------------------------------------------
reg_1024_and_256p: process(RESET, CLK)
begin
if(CLK'event and CLK = '1') then
if (RESET = '1') then
reg_1024_and_256 <= (others => '1');
elsif (S_EN = '1' OR F_EN = '1') then
reg_1024_and_256 <= ( '0' & reg_1024) + ( "000" & reg_256);
end if;
end if;
end process;
-- register ------------------------------------------------------
reg_128_and_64p: process(RESET, CLK)
begin
if(CLK'event and CLK = '1') then
if (RESET = '1') then
reg_128_and_64 <= (others => '1');
elsif (S_EN = '1' OR F_EN = '1') then
reg_128_and_64 <= ( '0' & reg_128) + ( "00" & reg_64);
end if;
end if;
end process;
-- register ------------------------------------------------------
reg_lastp: process(RESET, CLK)
begin
if(CLK'event and CLK = '1') then
if (RESET = '1') then
reg_last <= (others => '0');
elsif (S_EN = '1' OR F_EN = '1') then
reg_last <= (reg_1024_and_256) + ( "000" & reg_128_and_64);
end if;
end if;
end process;
-- register ------------------------------------------------------
reg_add_64p: process(RESET, CLK)
begin
if(CLK'event and CLK = '1') then
if (RESET = '1') then
reg_add <= (others => '0');
elsif (S_EN = '1' OR F_EN = '1') then
reg_add <= reg_last + conv_std_logic_vector(56, reg_last'length);
end if;
end if;
end process;
DOUT <= reg_add;
end architecture beh;
| bsd-3-clause | eba43f52d93fc466ff2373b2d5f2f2cb | 0.489661 | 3.758135 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/fifo/src/fifoWrite-rtl-ea.vhd | 3 | 5,826 | -------------------------------------------------------------------------------
--! @file fifoWrite-rtl-ea.vhd
--
--! @brief FIFO write controller
--
--! @details This is a FIFO write controller.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity fifoWrite is
generic (
gAddrWidth : natural := 4
);
port (
iClk : in std_logic;
iRst : in std_logic;
iWrite : in std_logic;
iRdPointer : in std_logic_vector(gAddrWidth downto 0);
oFull : out std_logic;
oEmpty : out std_logic;
oPointer : out std_logic_vector(gAddrWidth downto 0);
oAddress : out std_logic_vector(gAddrWidth-1 downto 0);
oUsedWord : out std_logic_vector(gAddrWidth-1 downto 0)
);
end fifoWrite;
architecture rtl of fifoWrite is
signal w_ptr_reg : std_logic_vector(gAddrWidth downto 0);
signal w_ptr_next : std_logic_vector(gAddrWidth downto 0);
signal gray1 : std_logic_vector(gAddrWidth downto 0);
signal bin : std_logic_vector(gAddrWidth downto 0);
signal bin1 : std_logic_vector(gAddrWidth downto 0);
signal waddr_all : std_logic_vector(gAddrWidth-1 downto 0);
signal waddr_msb : std_logic;
signal raddr_msb : std_logic;
signal full_flag : std_logic;
signal empty_flag : std_logic;
signal w_elements_wr : std_logic_vector(gAddrWidth downto 0);
signal w_elements_rd : std_logic_vector(gAddrWidth downto 0);
signal w_elements_diff : std_logic_vector(gAddrWidth downto 0);
signal w_elements_reg : std_logic_vector(gAddrWidth-1 downto 0);
signal w_elements_next : std_logic_vector(gAddrWidth-1 downto 0);
begin
--! Clock process for registers.
regProc : process(iClk, iRst)
begin
if iRst = cActivated then
w_ptr_reg <= (others => cInactivated);
w_elements_reg <= (others => cInactivated);
elsif rising_edge(iClk) then
w_ptr_reg <= w_ptr_next;
w_elements_reg <= w_elements_next;
end if;
end process;
-- (gAddrWidth+1)-bit Gray counter
bin <= w_ptr_reg xor (cInactivated & bin(gAddrWidth downto 1));
bin1 <= std_logic_vector(unsigned(bin) + 1);
gray1 <= bin1 xor (cInactivated & bin1(gAddrWidth downto 1));
-- update write pointer
w_ptr_next <= gray1 when iWrite = cActivated and full_flag = cInactivated else
w_ptr_reg;
-- gAddrWidth-bit Gray counter
waddr_msb <= w_ptr_reg(gAddrWidth) xor w_ptr_reg(gAddrWidth-1);
waddr_all <= waddr_msb & w_ptr_reg(gAddrWidth-2 downto 0);
raddr_msb <= iRdPointer(gAddrWidth) xor iRdPointer(gAddrWidth-1);
-- check for FIFO write empty
empty_flag <= cActivated when iRdPointer(gAddrWidth) = w_ptr_reg(gAddrWidth) and
iRdPointer(gAddrWidth-2 downto 0) = w_ptr_reg(gAddrWidth-2 downto 0) and
raddr_msb = waddr_msb else
cInactivated;
-- check for FIFO write full
full_flag <= cActivated when iRdPointer(gAddrWidth) /= w_ptr_reg(gAddrWidth) and
iRdPointer(gAddrWidth-2 downto 0) = w_ptr_reg(gAddrWidth-2 downto 0) and
raddr_msb = waddr_msb else
cInactivated;
-- convert gray value to bin and obtain difference
w_elements_wr <= bin;
w_elements_rd <= iRdPointer xor (cInactivated & w_elements_rd(gAddrWidth downto 1));
w_elements_diff <= std_logic_vector(unsigned(w_elements_wr) - unsigned(w_elements_rd));
w_elements_next <= w_elements_diff(w_elements_next'range);
-- output
oAddress <= waddr_all;
oPointer <= w_ptr_reg;
oUsedWord <= w_elements_reg;
oEmpty <= empty_flag;
oFull <= full_flag;
end rtl;
| gpl-2.0 | e058b3f70d5055e6ba9fb98ccb4c1a36 | 0.619979 | 4.158458 | false | false | false | false |
cnplab/blockmon | fw-combo/src/netcope-sim/models/fl_bfm.vhd | 1 | 10,462 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
--
-- fl_bfm.vhd: Simulation component for Frame link
-- Copyright (C) 2006 CESNET
-- Author(s): Vlastimil Kosar <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: fl_bfm.vhd 12021 2011-04-15 08:23:45Z kastovsky $
--
-- TODO:
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.fl_pkg.all;
use work.fl_bfm_rdy_pkg.all;
use work.FL_BFM_pkg.all;
-- library containing log2 function
use work.math_pack.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity FL_BFM is
generic(
-- FrameLink data bus width
-- only 8, 16, 32, 64 and 128 bit fl bus supported
DATA_WIDTH : integer;
-- uniqe identity of FL_BFM as one of 16 posible FL_BFMs in design
FL_BFM_ID : integer
);
port(
-- Common interface
RESET : in std_logic;
CLK : in std_logic;
-- Frame link output Interface
TX_DATA : out std_logic_vector(DATA_WIDTH-1 downto 0);
TX_REM : out std_logic_vector(log2(DATA_WIDTH/8)-1 downto 0);
TX_SOF_N : out std_logic;
TX_EOF_N : out std_logic;
TX_SOP_N : out std_logic;
TX_EOP_N : out std_logic;
TX_SRC_RDY_N : out std_logic;
TX_DST_RDY_N : in std_logic
);
end entity FL_BFM;
-- ----------------------------------------------------------------------------
-- Architecture declaration
-- ----------------------------------------------------------------------------
architecture FL_BFM_ARCH of FL_BFM is
SHARED VARIABLE Cmd : CmdTypeItem;
signal test: CmdTypeItem;
signal SRC_RDY_N : std_logic;
signal SRC_DRIVE : std_logic;
signal flCmd : flCmdTypeItem := ('0','Z','Z');
PROCEDURE Write(variable trans : IN CmdTypeItem;
signal CLK : IN std_logic;
signal DATA : OUT std_logic_vector(DATA_WIDTH-1 downto 0);
signal DREM : OUT std_logic_vector(log2(DATA_WIDTH/8)-1 downto 0);
signal SOF_N : OUT std_logic;
signal SOP_N : OUT std_logic;
signal EOP_N : OUT std_logic;
signal EOF_N : OUT std_logic;
signal SRC_RDY_N : IN std_logic;
signal DST_RDY_N : IN std_logic;
signal Enable : OUT std_logic) IS
variable index : integer;
variable byteCount : std_logic_vector(log2(DATA_WIDTH/8)-1 downto 0);
variable i : integer;
variable maxRem : std_logic_vector(log2(DATA_WIDTH/8)-1 downto 0);
BEGIN
Enable <= '0';
maxRem := (others => '1');
index := 0;
wait until (CLK'event and CLK='1' and SRC_RDY_N = '0'); --and DST_RDY_N='0');
Enable <= '1';
while (index <= trans.Length) loop
DATA(7 downto 0) <= trans.Data(index).Data;
byteCount := (others => '0');
i:= 1;
if (trans.Data(index).StartControl = SOF) then
SOF_N <= '0';
SOP_N <= '0';
elsif (trans.Data(index).StartControl = SOP) then
SOF_N <= '1';
SOP_N <= '0';
elsif (trans.Data(index).StartControl = NOP) then
SOF_N <= '1';
SOP_N <= '1';
end if;
if (DATA_WIDTH > 8) then
if (trans.Data(index).EndControl = NOP) then
while ((index + 1 <= trans.Length) and byteCount < maxRem) loop
index := index + 1;
byteCount := byteCount + '1';
i := i + 1;
DATA((i * 8) - 1 downto (i - 1) * 8) <= trans.Data(index).Data;
if ((trans.Data(index).EndControl = EOF) or (trans.Data(index).EndControl = EOP)) then
exit;
end if;
end loop;
end if;
end if;
if (trans.Data(index).EndControl = EOF) then
EOF_N <= '0';
EOP_N <= '0';
elsif (trans.Data(index).EndControl = EOP) then
EOF_N <= '1';
EOP_N <= '0';
elsif(trans.Data(index).EndControl = NOP) then
EOF_N <= '1';
EOP_N <= '1';
end if;
DREM <= byteCount;
wait until (CLK'event and CLK='1' and SRC_RDY_N = '0' and DST_RDY_N='0');
index := index + 1;
end loop;
Enable <= '0';
END Write;
begin
gen0: if (FL_BFM_ID = 0) generate
flCmd_0.Ack <= flCmd.Ack;
flCmd_0.ReqAck <= flCmd.ReqAck;
flCmd.Req <= flCmd_0.Req;
end generate gen0;
gen1: if (FL_BFM_ID = 1) generate
flCmd_1.Ack <= flCmd.Ack;
flCmd_1.ReqAck <= flCmd.ReqAck;
flCmd.Req <= flCmd_1.Req;
end generate gen1;
gen2: if (FL_BFM_ID = 2) generate
flCmd_2.Ack <= flCmd.Ack;
flCmd_2.ReqAck <= flCmd.ReqAck;
flCmd.Req <= flCmd_2.Req;
end generate gen2;
gen3: if (FL_BFM_ID = 3) generate
flCmd_3.Ack <= flCmd.Ack;
flCmd_3.ReqAck <= flCmd.ReqAck;
flCmd.Req <= flCmd_3.Req;
end generate gen3;
gen4: if (FL_BFM_ID = 4) generate
flCmd_4.Ack <= flCmd.Ack;
flCmd_4.ReqAck <= flCmd.ReqAck;
flCmd.Req <= flCmd_4.Req;
end generate gen4;
gen5: if (FL_BFM_ID = 5) generate
flCmd_5.Ack <= flCmd.Ack;
flCmd_5.ReqAck <= flCmd.ReqAck;
flCmd.Req <= flCmd_5.Req;
end generate gen5;
gen6: if (FL_BFM_ID = 6) generate
flCmd_6.Ack <= flCmd.Ack;
flCmd_6.ReqAck <= flCmd.ReqAck;
flCmd.Req <= flCmd_6.Req;
end generate gen6;
gen7: if (FL_BFM_ID = 7) generate
flCmd_7.Ack <= flCmd.Ack;
flCmd_7.ReqAck <= flCmd.ReqAck;
flCmd.Req <= flCmd_7.Req;
end generate gen7;
gen8: if (FL_BFM_ID = 8) generate
flCmd_8.Ack <= flCmd.Ack;
flCmd_8.ReqAck <= flCmd.ReqAck;
flCmd.Req <= flCmd_8.Req;
end generate gen8;
gen9: if (FL_BFM_ID = 9) generate
flCmd_9.Ack <= flCmd.Ack;
flCmd_9.ReqAck <= flCmd.ReqAck;
flCmd.Req <= flCmd_9.Req;
end generate gen9;
genA: if (FL_BFM_ID = 10) generate
flCmd_A.Ack <= flCmd.Ack;
flCmd_A.ReqAck <= flCmd.ReqAck;
flCmd.Req <= flCmd_A.Req;
end generate genA;
genB: if (FL_BFM_ID = 11) generate
flCmd_B.Ack <= flCmd.Ack;
flCmd_B.ReqAck <= flCmd.ReqAck;
flCmd.Req <= flCmd_B.Req;
end generate genB;
genC: if (FL_BFM_ID = 12) generate
flCmd_C.Ack <= flCmd.Ack;
flCmd_C.ReqAck <= flCmd.ReqAck;
flCmd.Req <= flCmd_C.Req;
end generate genC;
genD: if (FL_BFM_ID = 13) generate
flCmd_D.Ack <= flCmd.Ack;
flCmd_D.ReqAck <= flCmd.ReqAck;
flCmd.Req <= flCmd_D.Req;
end generate genD;
genE: if (FL_BFM_ID = 14) generate
flCmd_E.Ack <= flCmd.Ack;
flCmd_E.ReqAck <= flCmd.ReqAck;
flCmd.Req <= flCmd_E.Req;
end generate genE;
genF: if (FL_BFM_ID = 15) generate
flCmd_F.Ack <= flCmd.Ack;
flCmd_F.ReqAck <= flCmd.ReqAck;
flCmd.Req <= flCmd_F.Req;
end generate genF;
SEND:process
begin
TX_DATA <= (others => '0');
TX_REM <= (others => '0');
TX_SOF_N <= '1';
TX_EOF_N <= '1';
TX_SOP_N <= '1';
TX_EOP_N <= '1';
LOOP
flCmd.Ack <= '0';
flCmd.ReqAck <= '0';
SRC_DRIVE <= '0';
-- Get Command
WHILE (flCmd.Req = '0') LOOP
WAIT UNTIL (flCmd.Req = '1');
END LOOP;
-- Send Request Acknowledge
flCmd.ReqAck <= NOT(flCmd.ReqAck);
-- Wait for Reqest Deasert
WAIT ON flCmd.Req;
ReadCommand(Cmd, FL_BFM_ID);
test<=Cmd;
--SRC_DRIVE <= '1';
Write(Cmd, CLK, TX_DATA, TX_REM, TX_SOF_N, TX_SOP_N, TX_EOP_N, TX_EOF_N, SRC_RDY_N, TX_DST_RDY_N, SRC_DRIVE);
SRC_DRIVE <= '0';
-- Send Command done
flCmd.Ack <= '1';
wait until (CLK'event and CLK='1');
end loop;
end process;
-- Drive SRC_RDY_N ---------------------------------------------------------------
DRIVE_SRC_RDY_N: PROCESS
BEGIN
LOOP
IF (Cmd.RDYDriver = EVER) then
DriveRdyNAll(CLK, SRC_RDY_N);
elsif (Cmd.RDYDriver = ONOFF) then
DriveRdyN50_50(CLK, SRC_RDY_N);
elsif (Cmd.RDYDriver = RND) then
DriveRdyNRnd(CLK, SRC_RDY_N);
end if;
END LOOP;
END PROCESS;
TX_SRC_RDY_N <= SRC_RDY_N or not SRC_DRIVE;
end architecture FL_BFM_ARCH;
| bsd-3-clause | b565e6f35115358740b92a5bc7f599f6 | 0.555725 | 3.511917 | false | false | false | false |
cnplab/blockmon | fw-combo/src/generator/comp/lfsr_serial.vhd | 1 | 4,266 | -- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- lfsr_serial.vhd : LFSR based serial output pseudorandom generator module
-- Copyright (C) 2009 CESNET
-- Author(s): Pavol Korcek <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: lfsr_serial.vhd 12095 2009-11-24 15:12:11Z kastovsky $
--
library ieee;
use ieee.std_logic_1164.all;
use work.lfsr_pkg.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity lfsr_serial is
generic (
LFSR_LENGTH : integer := 16; -- internal LFSR width
TAPS : LFSR_TAPS :=(16,15,13,4) -- polynomial
);
port (
CLK : in std_logic; -- clock signal
S_EN : in std_logic; -- shift enable
F_EN : in std_logic; -- fill enable
DIN : in std_logic_vector(LFSR_LENGTH-1 downto 0); -- seed
DOUT : out std_logic -- data out
);
end entity lfsr_serial;
-- ----------------------------------------------------------------------------
-- Architecture declaration
-- ----------------------------------------------------------------------------
architecture beh of lfsr_serial is
signal reg : std_logic_vector((LFSR_LENGTH-1) downto 0);
begin
lfsr1 : process (CLK)
variable fb : std_logic;
begin
if (CLK'event and CLK ='1') then
-- rising edge
if S_EN='1' then
-- shift enable
-- compute new bit (xor)
fb := '0';
for j in TAPS'range loop
if fb=reg(TAPS(j)-1) then
fb := '0';
else
fb := '1';
end if;
end loop; -- j
for k in reg'left downto 1 loop
reg(k) <= reg(k-1);
end loop; -- k
reg(0) <= fb;
elsif F_EN ='1' then
-- for insert seed
reg <= DIN;
end if;
DOUT <= reg(LFSR_LENGTH-1);
end if;
end process lfsr1;
end architecture beh;
| bsd-3-clause | 5cab8f6e239e95c28502a7ca3c758338 | 0.532818 | 4.687912 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/xilinx/openmac/src/axi_openmac-rtl-ea.vhd | 1 | 72,285 | -------------------------------------------------------------------------------
--! @file axi_openmac-rtl-ea.vhd
--
--! @brief OpenMAC toplevel for Xilinx
--
--! @details This is the openMAC toplevel for Xilinx platform with AXI.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
--! Work library
library work;
--! use openmac package
use work.openmacPkg.all;
--! Common Xilinx library
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
--! AXI Lite IPIF library
library axi_lite_ipif_v1_01_a;
--! Use AXI lite ipif
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
--! AXI Master Burst library
library axi_master_burst_v1_00_a;
--! Use AXI master burst
use axi_master_burst_v1_00_a.axi_master_burst;
--! Unisim library
library unisim;
--! Use ODDR2 instance primitive
use unisim.vcomponents.oddr2;
entity axi_openmac is
generic (
-----------------------------------------------------------------------
-- General parameters
-----------------------------------------------------------------------
--! Xilinx FPGA familiy
C_FAMILY : string := "spartan6";
-----------------------------------------------------------------------
-- AXI DMA
-----------------------------------------------------------------------
--! AXI master DMA address width
C_M_AXI_MAC_DMA_ADDR_WIDTH : integer := 32;
--! AXI master DMA data width
C_M_AXI_MAC_DMA_DATA_WIDTH : integer := 32;
--! AXI master DMA native data width
C_M_AXI_MAC_DMA_NATIVE_DWIDTH : integer := 32;
--! AXI master DMA burst length width
C_M_AXI_MAC_DMA_LENGTH_WIDTH : integer := 12;
--! AXI master DMA burst length
C_M_AXI_MAC_DMA_MAX_BURST_LEN : integer := 16;
-----------------------------------------------------------------------
-- AXI REG
-----------------------------------------------------------------------
--! AXI slave REG address ranges
C_S_AXI_MAC_REG_NUM_ADDR_RANGES : integer := 2;
--! AXI slave REG range 0 base
C_S_AXI_MAC_REG_RNG0_BASEADDR : std_logic_vector := x"ffffffff";
--! AXI slave REG range 0 high
C_S_AXI_MAC_REG_RNG0_HIGHADDR : std_logic_vector := x"00000000";
--! AXI slave REG range 1 base
C_S_AXI_MAC_REG_RNG1_BASEADDR : std_logic_vector := x"ffffffff";
--! AXI slave REG range 1 high
C_S_AXI_MAC_REG_RNG1_HIGHADDR : std_logic_vector := x"00000000";
--! AXI slave REG minimum size
C_S_AXI_MAC_REG_MIN_SIZE : std_logic_vector := x"00001fff";
--! AXI slave REG data width
C_S_AXI_MAC_REG_DATA_WIDTH : integer := 32;
--! AXI slave REG address width
C_S_AXI_MAC_REG_ADDR_WIDTH : integer := 32;
--! AXI slave REG clock frequency
C_S_AXI_MAC_REG_ACLK_FREQ_HZ : integer := 50000000;
--! AXI slave REG use write strobes
C_S_AXI_MAC_REG_USE_WSTRB : integer := 1;
--! AXI slave REG enable data phase timeout timer
C_S_AXI_MAC_REG_DPHASE_TIMEOUT : integer := 0;
-----------------------------------------------------------------------
-- AXI REG
-----------------------------------------------------------------------
--! AXI slave PKT base
C_S_AXI_MAC_PKT_BASEADDR : std_logic_vector := x"ffffffff";
--! AXI slave PKT high
C_S_AXI_MAC_PKT_HIGHADDR : std_logic_vector := x"00000000";
--! AXI slave REG minimum size
C_S_AXI_MAC_PKT_MIN_SIZE : std_logic_vector := x"0000ffff";
--! AXI slave PKT data width
C_S_AXI_MAC_PKT_DATA_WIDTH : integer := 32;
--! AXI slave PKT address width
C_S_AXI_MAC_PKT_ADDR_WIDTH : integer := 32;
--! AXI slave PKT use write strobes
C_S_AXI_MAC_PKT_USE_WSTRB : integer := 1;
--! AXI slave PKT enable data phase timeout timer
C_S_AXI_MAC_PKT_DPHASE_TIMEOUT : integer := 0;
-----------------------------------------------------------------------
-- Phy configuration
-----------------------------------------------------------------------
--! Number of Phy ports
gPhyPortCount : natural := 2;
--! Phy port interface type (Rmii or Mii)
gPhyPortType : natural := cPhyPortRmii;
--! Number of SMI phy ports
gSmiPortCount : natural := 1;
-----------------------------------------------------------------------
-- General configuration
-----------------------------------------------------------------------
--! Endianness ("little" or "big")
gEndianness : string := "little";
--! Enable packet activity generator (e.g. connect to LED)
gEnableActivity : natural := cFalse;
--! Enable DMA observer circuit
gEnableDmaObserver : natural := cFalse;
-----------------------------------------------------------------------
-- DMA configuration
-----------------------------------------------------------------------
--! DMA address width (byte-addressing)
gDmaAddrWidth : natural := 32;
--! DMA data width
gDmaDataWidth : natural := 16;
--! DMA burst count width
gDmaBurstCountWidth : natural := 4;
--! DMA write burst length (Rx packets) [words]
gDmaWriteBurstLength : natural := 16;
--! DMA read burst length (Tx packets) [words]
gDmaReadBurstLength : natural := 16;
--! DMA write FIFO length (Rx packets) [words]
gDmaWriteFifoLength : natural := 16;
--! DMA read FIFO length (Tx packets) [words]
gDmaReadFifoLength : natural := 16;
-----------------------------------------------------------------------
-- Packet buffer configuration
-----------------------------------------------------------------------
--! Packet buffer location for Tx packets
gPacketBufferLocTx : natural := cPktBufLocal;
--! Packet buffer location for Rx packets
gPacketBufferLocRx : natural := cPktBufLocal;
--! Packet buffer log2(size) [log2(bytes)]
gPacketBufferLog2Size : natural := 10;
-----------------------------------------------------------------------
-- MAC timer configuration
-----------------------------------------------------------------------
--! Number of timers
gTimerCount : natural := 2;
--! Enable timer pulse width control
gTimerEnablePulseWidth : natural := cFalse;
--! Timer pulse width register width
gTimerPulseRegWidth : natural := 10
);
port (
-----------------------------------------------------------------------
-- Clock and reset signal pairs
-----------------------------------------------------------------------
--! Main clock used for openMAC, openHUB and openFILTER (freq = 50 MHz)
iClk50 : in std_logic;
--! Twice main clock used for Rmii Tx path
iClk100 : in std_logic;
-----------------------------------------------------------------------
-- MAC REG memory mapped slave
-----------------------------------------------------------------------
--! AXI slave REG clock
S_AXI_MAC_REG_ACLK : in std_logic;
--! AXI slave REG reset (low-active)
S_AXI_MAC_REG_ARESETN : in std_logic;
--! AXI slave REG address read valid
S_AXI_MAC_REG_ARVALID : in std_logic;
--! AXI slave REG address write valid
S_AXI_MAC_REG_AWVALID : in std_logic;
--! AXI slave REG response ready
S_AXI_MAC_REG_BREADY : in std_logic;
--! AXI slave REG read ready
S_AXI_MAC_REG_RREADY : in std_logic;
--! AXI slave REG write valid
S_AXI_MAC_REG_WVALID : in std_logic;
--! AXI slave REG read address
S_AXI_MAC_REG_ARADDR : in std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
--! AXI slave REG write address
S_AXI_MAC_REG_AWADDR : in std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
--! AXI slave REG write data
S_AXI_MAC_REG_WDATA : in std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
--! AXI slave REG write strobe
S_AXI_MAC_REG_WSTRB : in std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH/8-1 downto 0);
--! AXI slave REG read address ready
S_AXI_MAC_REG_ARREADY : out std_logic;
--! AXI slave REG write address ready
S_AXI_MAC_REG_AWREADY : out std_logic;
--! AXI slave REG write response valid
S_AXI_MAC_REG_BVALID : out std_logic;
--! AXI slave REG read valid
S_AXI_MAC_REG_RVALID : out std_logic;
--! AXI slave REG write ready
S_AXI_MAC_REG_WREADY : out std_logic;
--! AXI slave REG write response
S_AXI_MAC_REG_BRESP : out std_logic_vector(1 downto 0);
--! AXI slave REG read data
S_AXI_MAC_REG_RDATA : out std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
--! AXI slave REG read response
S_AXI_MAC_REG_RRESP : out std_logic_vector(1 downto 0);
-----------------------------------------------------------------------
-- MAC PACKET BUFFER memory mapped slave
-----------------------------------------------------------------------
--! AXI slave PKT clock
S_AXI_MAC_PKT_ACLK : in std_logic;
--! AXI slave PKT reset (low-active)
S_AXI_MAC_PKT_ARESETN : in std_logic;
--! AXI slave PKT address read valid
S_AXI_MAC_PKT_ARVALID : in std_logic;
--! AXI slave PKT address write valid
S_AXI_MAC_PKT_AWVALID : in std_logic;
--! AXI slave PKT response ready
S_AXI_MAC_PKT_BREADY : in std_logic;
--! AXI slave PKT read ready
S_AXI_MAC_PKT_RREADY : in std_logic;
--! AXI slave PKT write valid
S_AXI_MAC_PKT_WVALID : in std_logic;
--! AXI slave PKT read address
S_AXI_MAC_PKT_ARADDR : in std_logic_vector(C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0);
--! AXI slave PKT write address
S_AXI_MAC_PKT_AWADDR : in std_logic_vector(C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0);
--! AXI slave PKT write data
S_AXI_MAC_PKT_WDATA : in std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
--! AXI slave PKT write strobe
S_AXI_MAC_PKT_WSTRB : in std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH/8-1 downto 0);
--! AXI slave PKT read address ready
S_AXI_MAC_PKT_ARREADY : out std_logic;
--! AXI slave PKT write address ready
S_AXI_MAC_PKT_AWREADY : out std_logic;
--! AXI slave PKT write response valid
S_AXI_MAC_PKT_BVALID : out std_logic;
--! AXI slave PKT read valid
S_AXI_MAC_PKT_RVALID : out std_logic;
--! AXI slave PKT write ready
S_AXI_MAC_PKT_WREADY : out std_logic;
--! AXI slave PKT write response
S_AXI_MAC_PKT_BRESP : out std_logic_vector(1 downto 0);
--! AXI slave PKT read data
S_AXI_MAC_PKT_RDATA : out std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
--! AXI slave PKT read response
S_AXI_MAC_PKT_RRESP : out std_logic_vector(1 downto 0);
-----------------------------------------------------------------------
-- MAC DMA memory mapped master
-----------------------------------------------------------------------
--! DMA master clock
M_AXI_MAC_DMA_ACLK : in std_logic;
--! DMA master reset (low-active)
M_AXI_MAC_DMA_ARESETN : in std_logic;
--! AXI master DMA error
M_AXI_MAC_DMA_MD_ERROR : out std_logic;
--! AXI master DMA read address ready
M_AXI_MAC_DMA_ARREADY : in std_logic;
--! AXI master DMA write address ready
M_AXI_MAC_DMA_AWREADY : in std_logic;
--! AXI master DMA write response ready
M_AXI_MAC_DMA_BVALID : in std_logic;
--! AXI master DMA read last
M_AXI_MAC_DMA_RLAST : in std_logic;
--! AXI master DMA read valid
M_AXI_MAC_DMA_RVALID : in std_logic;
--! AXI master DMA write ready
M_AXI_MAC_DMA_WREADY : in std_logic;
--! AXI master DMA write response
M_AXI_MAC_DMA_BRESP : in std_logic_vector(1 downto 0);
--! AXI master DMA read data
M_AXI_MAC_DMA_RDATA : in std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0);
--! AXI master DMA read response
M_AXI_MAC_DMA_RRESP : in std_logic_vector(1 downto 0);
--! AXI master DMA read address valid
M_AXI_MAC_DMA_ARVALID : out std_logic;
--! AXI master DMA write address valid
M_AXI_MAC_DMA_AWVALID : out std_logic;
--! AXI master DMA response ready
M_AXI_MAC_DMA_BREADY : out std_logic;
--! AXI master DMA read ready
M_AXI_MAC_DMA_RREADY : out std_logic;
--! AXI master DMA write last
M_AXI_MAC_DMA_WLAST : out std_logic;
--! AXI master DMA write valid
M_AXI_MAC_DMA_WVALID : out std_logic;
--! AXI master DMA read address
M_AXI_MAC_DMA_ARADDR : out std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
--! AXI master DMA burst type
M_AXI_MAC_DMA_ARBURST : out std_logic_vector(1 downto 0);
--! AXI master DMA memory type
M_AXI_MAC_DMA_ARCACHE : out std_logic_vector(3 downto 0);
--! AXI master DMA burst length
M_AXI_MAC_DMA_ARLEN : out std_logic_vector(7 downto 0);
--! AXI master DMA protection type
M_AXI_MAC_DMA_ARPROT : out std_logic_vector(2 downto 0);
--! AXI master DMA burst size
M_AXI_MAC_DMA_ARSIZE : out std_logic_vector(2 downto 0);
--! AXI master DMA write address
M_AXI_MAC_DMA_AWADDR : out std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
--! AXI master DMA burst type
M_AXI_MAC_DMA_AWBURST : out std_logic_vector(1 downto 0);
--! AXI master DMA memory type
M_AXI_MAC_DMA_AWCACHE : out std_logic_vector(3 downto 0);
--! AXI master DMA burst length
M_AXI_MAC_DMA_AWLEN : out std_logic_vector(7 downto 0);
--! AXI master DMA protection type
M_AXI_MAC_DMA_AWPROT : out std_logic_vector(2 downto 0);
--! AXI master DMA burst size
M_AXI_MAC_DMA_AWSIZE : out std_logic_vector(2 downto 0);
--! AXI master DMA write data
M_AXI_MAC_DMA_WDATA : out std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0);
--! AXI master DMA write strobe
M_AXI_MAC_DMA_WSTRB : out std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH/8-1 downto 0);
-----------------------------------------------------------------------
-- Interrupts
-----------------------------------------------------------------------
--! MAC TIMER interrupt
TIMER_IRQ : out std_logic;
--! MAC interrupt
MAC_IRQ : out std_logic;
-----------------------------------------------------------------------
-- Rmii Phy ports
-----------------------------------------------------------------------
--! Rmii Clock ports (optional)
oRmii_clk : out std_logic_vector(gPhyPortCount-1 downto 0);
--! Rmii Rx Crs data valid ports
iRmii_rxCrsDataValid : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Rmii Rx data ports
iRmii_rxData : in std_logic_vector(gPhyPortCount*2-1 downto 0);
--! Rmii Rx error ports
iRmii_rxError : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Rmii Tx enable ports
oRmii_txEnable : out std_logic_vector(gPhyPortCount-1 downto 0);
--! Rmii Tx data ports
oRmii_txData : out std_logic_vector(gPhyPortCount*2-1 downto 0);
-----------------------------------------------------------------------
-- Mii Phy ports
-----------------------------------------------------------------------
--! Mii Rx data valid ports
iMii_rxDataValid : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Rx data ports
iMii_rxData : in std_logic_vector(gPhyPortCount*4-1 downto 0);
--! Mii Rx error ports
iMii_rxError : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Rx Clocks
iMii_rxClk : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Tx enable ports
oMii_txEnable : out std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Tx data ports
oMii_txData : out std_logic_vector(gPhyPortCount*4-1 downto 0);
--! Mii Tx Clocks
iMii_txClk : in std_logic_vector(gPhyPortCount-1 downto 0);
-----------------------------------------------------------------------
-- Phy management interface
-----------------------------------------------------------------------
--! Phy reset (low-active)
oSmi_nPhyRst : out std_logic_vector(gSmiPortCount-1 downto 0);
--! SMI clock
oSmi_clk : out std_logic_vector(gSmiPortCount-1 downto 0);
--! SMI data I/O input
iSmi_dio : in std_logic_vector(gSmiPortCount-1 downto 0);
--! SMI data I/O output
oSmi_dio : out std_logic_vector(gSmiPortCount-1 downto 0);
--! SMI data I/O tristate
oSmi_dio_tri : out std_logic;
-----------------------------------------------------------------------
-- Other ports
-----------------------------------------------------------------------
--! Packet activity (enabled with gEnableActivity)
oPktActivity : out std_logic;
--! MAC TIMER outputs
oMacTimerOut : out std_logic_vector(gTimerCount-1 downto 0)
);
end axi_openmac;
architecture rtl of axi_openmac is
--! Address zero padding vector
constant cZeroPadAddress : std_logic_vector(31 downto 0) := (others => cInactivated);
--! Address array for MAC REG IPIF
constant cMacReg_addressArray : SLV64_ARRAY_TYPE := (
(cZeroPadAddress & C_S_AXI_MAC_REG_RNG0_BASEADDR),
(cZeroPadAddress & C_S_AXI_MAC_REG_RNG0_HIGHADDR),
(cZeroPadAddress & C_S_AXI_MAC_REG_RNG1_BASEADDR),
(cZeroPadAddress & C_S_AXI_MAC_REG_RNG1_HIGHADDR)
);
--! Address array for PKT BUF IPIF
constant cPktBuf_addressArray : SLV64_ARRAY_TYPE := (
(cZeroPadAddress & C_S_AXI_MAC_PKT_BASEADDR),
(cZeroPadAddress & C_S_AXI_MAC_PKT_HIGHADDR)
);
--! Chipselect for MAC REG --> MAC REG
constant cMacReg_csMacReg : natural := 1;
--! Chipselect for MAC REG --> MAC TIMER
constant cMacReg_csMacTimer : natural := 0;
--! Chipselect for PKT BUF
constant cPktBuf_cs : natural := 0;
--! Clock Reset type
type tClkRst is record
clk : std_logic;
rst : std_logic;
regClk : std_logic;
regRst : std_logic;
dmaClk : std_logic;
dmaRst : std_logic;
pktClk : std_logic;
pktRst : std_logic;
clk2x : std_logic;
end record;
--! Mac Reg type
type tMacReg is record
chipselect : std_logic;
write : std_logic;
read : std_logic;
waitrequest : std_logic;
byteenable : std_logic_vector(cMacRegDataWidth/cByteLength-1 downto 0);
address : std_logic_vector(cMacRegAddrWidth-1 downto 0);
writedata : std_logic_vector(cMacRegDataWidth-1 downto 0);
readdata : std_logic_vector(cMacRegDataWidth-1 downto 0);
end record;
--! Mac Timer type
type tMacTimer is record
chipselect : std_logic;
write : std_logic;
read : std_logic;
waitrequest : std_logic;
address : std_logic_vector(cMacTimerAddrWidth-1 downto 0);
writedata : std_logic_vector(cMacTimerDataWidth-1 downto 0);
readdata : std_logic_vector(cMacTimerDataWidth-1 downto 0);
end record;
--! Pkt Buf type
type tPktBuf is record
chipselect : std_logic;
write : std_logic;
read : std_logic;
waitrequest : std_logic;
byteenable : std_logic_vector(cPktBufDataWidth/cByteLength-1 downto 0);
address : std_logic_vector(gPacketBufferLog2Size-1 downto 0);
writedata : std_logic_vector(cPktBufDataWidth-1 downto 0);
readdata : std_logic_vector(cPktBufDataWidth-1 downto 0);
end record;
--! Dma type
type tDma is record
write : std_logic;
read : std_logic;
waitrequest : std_logic;
readdatavalid : std_logic;
byteenable : std_logic_vector(gDmaDataWidth/cByteLength-1 downto 0);
address : std_logic_vector(gDmaAddrWidth-1 downto 0);
burstcount : std_logic_vector(gDmaBurstCountWidth-1 downto 0);
burstcounter : std_logic_vector(gDmaBurstCountWidth-1 downto 0);
writedata : std_logic_vector(gDmaDataWidth-1 downto 0);
readdata : std_logic_vector(gDmaDataWidth-1 downto 0);
end record;
--! AXI lite slave for MAC REG
type tAxiSlaveMacReg is record
axi_aclk : std_logic;
axi_aresetn : std_logic;
axi_awaddr : std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
axi_awvalid : std_logic;
axi_awready : std_logic;
axi_wdata : std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
axi_wstrb : std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH/8-1 downto 0);
axi_wvalid : std_logic;
axi_wready : std_logic;
axi_bresp : std_logic_vector(1 downto 0);
axi_bvalid : std_logic;
axi_bready : std_logic;
axi_araddr : std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
axi_arvalid : std_logic;
axi_arready : std_logic;
axi_rdata : std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
axi_rresp : std_logic_vector(1 downto 0);
axi_rvalid : std_logic;
axi_rready : std_logic;
ipif_clk : std_logic;
ipif_resetn : std_logic;
ipif_addr : std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
ipif_rnw : std_logic;
ipif_be : std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH/8-1 downto 0);
ipif_cs : std_logic_vector(((cMacReg_addressArray'length)/2-1) downto 0);
ipif_wrdata : std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
ipif_rddata : std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
ipif_wrack : std_logic;
ipif_rdack : std_logic;
ipif_error : std_logic;
end record;
--! AXI lite slave for PKT BUF
type tAxiSlavePktBuf is record
axi_aclk : std_logic;
axi_aresetn : std_logic;
axi_awaddr : std_logic_vector(C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0);
axi_awvalid : std_logic;
axi_awready : std_logic;
axi_wdata : std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
axi_wstrb : std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH/8-1 downto 0);
axi_wvalid : std_logic;
axi_wready : std_logic;
axi_bresp : std_logic_vector(1 downto 0);
axi_bvalid : std_logic;
axi_bready : std_logic;
axi_araddr : std_logic_vector(C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0);
axi_arvalid : std_logic;
axi_arready : std_logic;
axi_rdata : std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
axi_rresp : std_logic_vector(1 downto 0);
axi_rvalid : std_logic;
axi_rready : std_logic;
ipif_clk : std_logic;
ipif_resetn : std_logic;
ipif_addr : std_logic_vector(C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0);
ipif_rnw : std_logic;
ipif_be : std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH/8-1 downto 0);
ipif_cs : std_logic_vector(((cPktBuf_addressArray'length)/2-1) downto 0);
ipif_wrdata : std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
ipif_rddata : std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
ipif_wrack : std_logic;
ipif_rdack : std_logic;
ipif_error : std_logic;
end record;
--! AXI master for DMA
type tAxiMasterDma is record
axi_aclk : std_logic;
axi_aresetn : std_logic;
md_error : std_logic;
axi_arready : std_logic;
axi_arvalid : std_logic;
axi_araddr : std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
axi_arlen : std_logic_vector(7 downto 0);
axi_arsize : std_logic_vector(2 downto 0);
axi_arburst : std_logic_vector(1 downto 0);
axi_arprot : std_logic_vector(2 downto 0);
axi_arcache : std_logic_vector(3 downto 0);
axi_rready : std_logic;
axi_rvalid : std_logic;
axi_rdata : std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0);
axi_rresp : std_logic_vector(1 downto 0);
axi_rlast : std_logic;
axi_awready : std_logic;
axi_awvalid : std_logic;
axi_awaddr : std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
axi_awlen : std_logic_vector(7 downto 0);
axi_awsize : std_logic_vector(2 downto 0);
axi_awburst : std_logic_vector(1 downto 0);
axi_awprot : std_logic_vector(2 downto 0);
axi_awcache : std_logic_vector(3 downto 0);
axi_wready : std_logic;
axi_wvalid : std_logic;
axi_wdata : std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0);
axi_wstrb : std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH/8-1 downto 0);
axi_wlast : std_logic;
axi_bready : std_logic;
axi_bvalid : std_logic;
axi_bresp : std_logic_vector(1 downto 0);
ipif_mstrd_req : std_logic;
ipif_mstwr_req : std_logic;
ipif_mst_addr : std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
ipif_mst_length : std_logic_vector(C_M_AXI_MAC_DMA_LENGTH_WIDTH-1 downto 0);
ipif_mst_be : std_logic_vector(C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8-1 downto 0);
ipif_mst_type : std_logic;
ipif_mst_lock : std_logic;
ipif_mst_reset : std_logic;
ipif_mst_cmdack : std_logic;
ipif_mst_cmplt : std_logic;
ipif_mst_error : std_logic;
ipif_mst_rearbitrate : std_logic;
ipif_mst_cmd_timeout : std_logic;
ipif_mstrd_d : std_logic_vector(C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0 );
ipif_mstrd_rem : std_logic_vector(C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8-1 downto 0);
ipif_mstrd_sof_n : std_logic;
ipif_mstrd_eof_n : std_logic;
ipif_mstrd_src_rdy_n : std_logic;
ipif_mstrd_src_dsc_n : std_logic;
ipif_mstrd_dst_rdy_n : std_logic;
ipif_mstrd_dst_dsc_n : std_logic;
ipif_mstwr_d : std_logic_vector(C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0);
ipif_mstwr_rem : std_logic_vector(C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8-1 downto 0);
ipif_mstwr_sof_n : std_logic;
ipif_mstwr_eof_n : std_logic;
ipif_mstwr_src_rdy_n : std_logic;
ipif_mstwr_src_dsc_n : std_logic;
ipif_mstwr_dst_rdy_n : std_logic;
ipif_mstwr_dst_dsc_n : std_logic;
end record;
--! Clock xing for MAC REG port
type tClkXingMacRegPort is record
clk : std_logic;
cs : std_logic_vector(((cMacReg_addressArray'length)/2-1) downto 0);
rnw : std_logic;
readdata : std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
wrAck : std_logic;
rdAck : std_logic;
end record;
--! Clock xing for MAC REG
type tClkXingMacReg is record
rst : std_logic;
fast : tClkXingMacRegPort;
slow : tClkXingMacRegPort;
end record;
--! Data width converter for MAC REG
type tConvMacReg is record
rst : std_logic;
clk : std_logic;
master_select : std_logic;
master_write : std_logic;
master_read : std_logic;
master_byteenable : std_logic_vector(3 downto 0);
master_writedata : std_logic_vector(31 downto 0);
master_readdata : std_logic_vector(31 downto 0);
master_address : std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
master_WriteAck : std_logic;
master_ReadAck : std_logic;
slave_select : std_logic;
slave_write : std_logic;
slave_read : std_logic;
slave_address : std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
slave_byteenable : std_logic_vector(1 downto 0);
slave_readdata : std_logic_vector(15 downto 0);
slave_writedata : std_logic_vector(15 downto 0);
slave_ack : std_logic;
end record;
--! IPIF handler for MAC DMA
type tIpifMasterHandler is record
rst : std_logic;
clk : std_logic;
ipif_cmdAck : std_logic;
ipif_cmplt : std_logic;
ipif_error : std_logic;
ipif_rearbitrate : std_logic;
ipif_cmdTimeout : std_logic;
ipif_type : std_logic;
ipif_addr : std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
ipif_length : std_logic_vector(C_M_AXI_MAC_DMA_LENGTH_WIDTH-1 downto 0);
ipif_be : std_logic_vector(3 downto 0);
ipif_lock : std_logic;
ipif_reset : std_logic;
ipif_rdData : std_logic_vector(31 downto 0);
ipif_rdRem : std_logic_vector(3 downto 0);
ipif_rdReq : std_logic;
nIpif_rdSof : std_logic;
nIpif_rdEof : std_logic;
nIpif_rdSrcRdy : std_logic;
nIpif_rdSrcDsc : std_logic;
nIpif_rdDstRdy : std_logic;
nIpif_rdDstDsc : std_logic;
ipif_wrData : std_logic_vector(31 downto 0);
ipif_wrRem : std_logic_vector(3 downto 0);
ipif_wrReq : std_logic;
nIpif_wrSof : std_logic;
nIpif_wrEof : std_logic;
nIpif_wrSrcRdy : std_logic;
nIpif_wrSrcDsc : std_logic;
nIpif_wrDstRdy : std_logic;
nIpif_wrDstDsc : std_logic;
masterRead : std_logic;
masterWrite : std_logic;
masterAddress : std_logic_vector(gDmaAddrWidth-1 downto 0);
masterWritedata : std_logic_vector(31 downto 0);
masterBurstcount : std_logic_vector(gDmaBurstCountWidth-1 downto 0);
masterBurstcounter : std_logic_vector(gDmaBurstCountWidth-1 downto 0);
masterReaddata : std_logic_vector(31 downto 0);
masterWaitrequest : std_logic;
masterReaddatavalid : std_logic;
end record;
--! Clock and resets
signal intf_clkRst : tClkRst;
--! Mac Reg
signal intf_macReg : tMacReg;
--! Mac Timer
signal intf_macTimer : tMacTimer;
--! Packet buffer
signal intf_pktBuf : tPktBuf;
--! Dma
signal intf_dma : tDma;
--! Mac Reg IPIF
signal ipif_macReg : tAxiSlaveMacReg;
--! Packet buffer IPIF
signal ipif_pktBuf : tAxiSlavePktBuf;
--! Dma IPIF
signal ipif_dma : tAxiMasterDma;
--! Clock Xing for MAC REG IPIF
signal xing_macReg : tClkXingMacReg;
--! Dara width converter for MAC REG IPIF
signal conv_macReg : tConvMacReg;
--! Dma IPIF master handler
signal ipif_dmaMasterHdler : tIpifMasterHandler;
--! Mac Tx interrupt
signal macTx_interrupt : std_logic;
--! Mac Rx interrupt
signal macRx_interrupt : std_logic;
--! Rmii Tx path
signal rmiiTx : tRmiiPathArray(gPhyPortCount-1 downto 0);
--! Rmii Rx path
signal rmiiRx : tRmiiPathArray(gPhyPortCount-1 downto 0);
--! Mii Tx path
signal miiTx : tMiiPathArray(gPhyPortCount-1 downto 0);
--! Mii Rx path
signal miiRx : tMiiPathArray(gPhyPortCount-1 downto 0);
--! Smi tri-state-buffer input
signal smi_data_in : std_logic_vector(gSmiPortCount-1 downto 0);
--! Smi tri-state-buffer output
signal smi_data_out : std_logic_vector(gSmiPortCount-1 downto 0);
--! Smi tri-state-buffer output enable
signal smi_data_outEnable : std_logic;
begin
---------------------------------------------------------------------------
-- Map outputs
---------------------------------------------------------------------------
-- Mac interrupts are or'd to single line.
MAC_IRQ <= macTx_interrupt or macRx_interrupt;
-- Phy Tx path
rmiiPathArrayToStdLogicVector(
iVector => rmiiTx,
oEnable => oRmii_txEnable,
oData => oRmii_txData
);
miiPathArrayToStdLogicVector(
iVector => miiTx,
oEnable => oMii_txEnable,
oData => oMii_txData
);
---------------------------------------------------------------------------
-- Map inputs
---------------------------------------------------------------------------
-- Clock and resets
intf_clkRst.clk <= iClk50;
intf_clkRst.clk2x <= iClk100;
intf_clkRst.regClk <= S_AXI_MAC_REG_ACLK;
intf_clkRst.pktClk <= S_AXI_MAC_PKT_ACLK;
intf_clkRst.dmaClk <= M_AXI_MAC_DMA_ACLK;
intf_clkRst.rst <= not S_AXI_MAC_REG_ARESETN;
intf_clkRst.regRst <= not S_AXI_MAC_REG_ARESETN;
intf_clkRst.pktRst <= not S_AXI_MAC_PKT_ARESETN;
intf_clkRst.dmaRst <= not M_AXI_MAC_DMA_ARESETN;
-- Phy Rx path
stdLogicVectorToRmiiPathArray(
iEnable => iRmii_rxCrsDataValid,
iData => iRmii_rxData,
oVector => rmiiRx
);
stdLogicVectorToMiiPathArray(
iEnable => iMii_rxDataValid,
iData => iMii_rxData,
oVector => miiRx
);
---------------------------------------------------------------------------
-- Map IOs
---------------------------------------------------------------------------
-- Assign SMI IO (the tristate buffer shall be assigned by toplevel)
oSmi_dio <= smi_data_out;
oSmi_dio_tri <= not smi_data_outEnable;
smi_data_in <= iSmi_dio;
---------------------------------------------------------------------------
-- Map Instances
---------------------------------------------------------------------------
-- MAC REG --> ipif_macReg
ipif_macReg.axi_aclk <= intf_clkRst.regClk;
ipif_macReg.axi_aresetn <= not intf_clkRst.regRst;
ipif_macReg.axi_awaddr <= S_AXI_MAC_REG_AWADDR;
ipif_macReg.axi_awvalid <= S_AXI_MAC_REG_AWVALID;
S_AXI_MAC_REG_AWREADY <= ipif_macReg.axi_awready;
ipif_macReg.axi_wdata <= S_AXI_MAC_REG_WDATA;
ipif_macReg.axi_wstrb <= S_AXI_MAC_REG_WSTRB;
ipif_macReg.axi_wvalid <= S_AXI_MAC_REG_WVALID;
S_AXI_MAC_REG_WREADY <= ipif_macReg.axi_wready;
S_AXI_MAC_REG_BRESP <= ipif_macReg.axi_bresp;
S_AXI_MAC_REG_BVALID <= ipif_macReg.axi_bvalid;
ipif_macReg.axi_bready <= S_AXI_MAC_REG_BREADY;
ipif_macReg.axi_araddr <= S_AXI_MAC_REG_ARADDR;
ipif_macReg.axi_arvalid <= S_AXI_MAC_REG_ARVALID;
S_AXI_MAC_REG_ARREADY <= ipif_macReg.axi_arready;
S_AXI_MAC_REG_RDATA <= ipif_macReg.axi_rdata;
S_AXI_MAC_REG_RRESP <= ipif_macReg.axi_rresp;
S_AXI_MAC_REG_RVALID <= ipif_macReg.axi_rvalid;
ipif_macReg.axi_rready <= S_AXI_MAC_REG_RREADY;
-- xing_macReg <-- conv_macReg or intf_macTimer
--! This process assigns the read and ack path from macReg and macTimer
--! to the clock crossing slow inputs, depending on the selected target.
ASSIGN_XING_MACREG : process (conv_macReg, intf_macTimer)
begin
-- default is MAC REG source
xing_macReg.slow.readdata <= conv_macReg.master_readdata;
xing_macReg.slow.wrAck <= conv_macReg.master_WriteAck;
xing_macReg.slow.rdAck <= conv_macReg.master_ReadAck;
if intf_macTimer.chipselect = cActivated then
xing_macReg.slow.readdata <= intf_macTimer.readdata;
xing_macReg.slow.wrAck <= intf_macTimer.write and not intf_macTimer.waitrequest;
xing_macReg.slow.rdAck <= intf_macTimer.read and not intf_macTimer.waitrequest;
end if;
end process ASSIGN_XING_MACREG;
-- ipif_macReg --> xing_macReg
--unused output: ipif_macReg.ipif_resetn;
xing_macReg.rst <= intf_clkRst.regRst;
xing_macReg.fast.clk <= ipif_macReg.ipif_clk;
xing_macReg.slow.clk <= intf_clkRst.clk;
xing_macReg.fast.rnw <= ipif_macReg.ipif_rnw;
xing_macReg.fast.cs <= ipif_macReg.ipif_cs;
ipif_macReg.ipif_rddata <= xing_macReg.fast.readdata;
ipif_macReg.ipif_wrack <= xing_macReg.fast.wrAck;
ipif_macReg.ipif_rdack <= xing_macReg.fast.rdAck;
ipif_macReg.ipif_error <= cInactivated; --unused
-- ipif_macReg --> conv_macReg | xing_macReg --> conv_macReg
conv_macReg.rst <= intf_clkRst.rst;
conv_macReg.clk <= intf_clkRst.clk;
conv_macReg.master_select <= xing_macReg.slow.cs(cMacReg_csMacReg);
conv_macReg.master_write <= not xing_macReg.slow.rnw;
conv_macReg.master_read <= xing_macReg.slow.rnw;
conv_macReg.master_byteenable <= ipif_macReg.ipif_be;
conv_macReg.master_writedata <= ipif_macReg.ipif_wrdata;
conv_macReg.master_address <= ipif_macReg.ipif_addr(conv_macReg.master_address'range);
-- conv_macReg --> intf_macReg
intf_macReg.chipselect <= conv_macReg.slave_select;
intf_macReg.write <= conv_macReg.slave_write;
intf_macReg.read <= conv_macReg.slave_read;
intf_macReg.address <= conv_macReg.slave_address(intf_macReg.address'range);
intf_macReg.byteenable <= conv_macReg.slave_byteenable;
conv_macReg.slave_readdata <= intf_macReg.readdata;
intf_macReg.writedata <= conv_macReg.slave_writedata;
conv_macReg.slave_ack <= not intf_macReg.waitrequest;
-- ipif_macReg --> intf_macTimer | xing_macReg --> intf_macTimer
intf_macTimer.chipselect <= xing_macReg.slow.cs(cMacReg_csMacTimer);
intf_macTimer.write <= not xing_macReg.slow.rnw;
intf_macTimer.read <= xing_macReg.slow.rnw;
intf_macTimer.address <= ipif_macReg.ipif_addr(intf_macTimer.address'range);
intf_macTimer.writedata <= ipif_macReg.ipif_wrdata;
-- MAC PKT --> ipif_pktBuf
ipif_pktBuf.axi_aclk <= intf_clkRst.pktClk;
ipif_pktBuf.axi_aresetn <= not intf_clkRst.pktRst;
ipif_pktBuf.axi_awaddr <= S_AXI_MAC_PKT_AWADDR;
ipif_pktBuf.axi_awvalid <= S_AXI_MAC_PKT_AWVALID;
S_AXI_MAC_PKT_AWREADY <= ipif_pktBuf.axi_awready;
ipif_pktBuf.axi_wdata <= S_AXI_MAC_PKT_WDATA;
ipif_pktBuf.axi_wstrb <= S_AXI_MAC_PKT_WSTRB;
ipif_pktBuf.axi_wvalid <= S_AXI_MAC_PKT_WVALID;
S_AXI_MAC_PKT_WREADY <= ipif_pktBuf.axi_wready;
S_AXI_MAC_PKT_BRESP <= ipif_pktBuf.axi_bresp;
S_AXI_MAC_PKT_BVALID <= ipif_pktBuf.axi_bvalid;
ipif_pktBuf.axi_bready <= S_AXI_MAC_PKT_BREADY;
ipif_pktBuf.axi_araddr <= S_AXI_MAC_PKT_ARADDR;
ipif_pktBuf.axi_arvalid <= S_AXI_MAC_PKT_ARVALID;
S_AXI_MAC_PKT_ARREADY <= ipif_pktBuf.axi_arready;
S_AXI_MAC_PKT_RDATA <= ipif_pktBuf.axi_rdata;
S_AXI_MAC_PKT_RRESP <= ipif_pktBuf.axi_rresp;
S_AXI_MAC_PKT_RVALID <= ipif_pktBuf.axi_rvalid;
ipif_pktBuf.axi_rready <= S_AXI_MAC_PKT_RREADY;
-- ipif_pktBuf --> intf_pktBuf
--unused output: ipif_pktBuf.ipif_clk
--unused output: ipif_pktBuf.ipif_resetn
intf_pktBuf.address <= ipif_pktBuf.ipif_addr(intf_pktBuf.address'range);
intf_pktBuf.write <= not ipif_pktBuf.ipif_rnw;
intf_pktBuf.read <= ipif_pktBuf.ipif_rnw;
intf_pktBuf.byteenable <= ipif_pktBuf.ipif_be;
intf_pktBuf.chipselect <= ipif_pktBuf.ipif_cs(cPktBuf_cs);
intf_pktBuf.writedata <= ipif_pktBuf.ipif_wrdata;
ipif_pktBuf.ipif_rddata <= intf_pktBuf.readdata;
ipif_pktBuf.ipif_wrack <= intf_pktBuf.chipselect and intf_pktBuf.write and not intf_pktBuf.waitrequest;
ipif_pktBuf.ipif_rdack <= intf_pktBuf.chipselect and intf_pktBuf.read and not intf_pktBuf.waitrequest;
ipif_pktBuf.ipif_error <= cInactivated; --unused
-- MAC DMA --> ipif_dma
ipif_dma.axi_aclk <= intf_clkRst.dmaClk;
ipif_dma.axi_aresetn <= not intf_clkRst.dmaRst;
M_AXI_MAC_DMA_MD_ERROR <= ipif_dma.md_error;
ipif_dma.axi_arready <= M_AXI_MAC_DMA_ARREADY;
M_AXI_MAC_DMA_ARVALID <= ipif_dma.axi_arvalid;
M_AXI_MAC_DMA_ARADDR <= ipif_dma.axi_araddr;
M_AXI_MAC_DMA_ARLEN <= ipif_dma.axi_arlen;
M_AXI_MAC_DMA_ARSIZE <= ipif_dma.axi_arsize;
M_AXI_MAC_DMA_ARBURST <= ipif_dma.axi_arburst;
M_AXI_MAC_DMA_ARPROT <= ipif_dma.axi_arprot;
M_AXI_MAC_DMA_ARCACHE <= ipif_dma.axi_arcache;
M_AXI_MAC_DMA_RREADY <= ipif_dma.axi_rready;
ipif_dma.axi_rvalid <= M_AXI_MAC_DMA_RVALID;
ipif_dma.axi_rdata <= M_AXI_MAC_DMA_RDATA;
ipif_dma.axi_rresp <= M_AXI_MAC_DMA_RRESP;
ipif_dma.axi_rlast <= M_AXI_MAC_DMA_RLAST;
ipif_dma.axi_awready <= M_AXI_MAC_DMA_AWREADY;
M_AXI_MAC_DMA_AWVALID <= ipif_dma.axi_awvalid;
M_AXI_MAC_DMA_AWADDR <= ipif_dma.axi_awaddr;
M_AXI_MAC_DMA_AWLEN <= ipif_dma.axi_awlen;
M_AXI_MAC_DMA_AWSIZE <= ipif_dma.axi_awsize;
M_AXI_MAC_DMA_AWBURST <= ipif_dma.axi_awburst;
M_AXI_MAC_DMA_AWPROT <= ipif_dma.axi_awprot;
M_AXI_MAC_DMA_AWCACHE <= ipif_dma.axi_awcache;
ipif_dma.axi_wready <= M_AXI_MAC_DMA_WREADY;
M_AXI_MAC_DMA_WVALID <= ipif_dma.axi_wvalid;
M_AXI_MAC_DMA_WDATA <= ipif_dma.axi_wdata;
M_AXI_MAC_DMA_WSTRB <= ipif_dma.axi_wstrb;
M_AXI_MAC_DMA_WLAST <= ipif_dma.axi_wlast;
M_AXI_MAC_DMA_BREADY <= ipif_dma.axi_bready;
ipif_dma.axi_bvalid <= M_AXI_MAC_DMA_BVALID;
ipif_dma.axi_bresp <= M_AXI_MAC_DMA_BRESP;
-- ipif_dma --> ipif_dmaMasterHdler
ipif_dmaMasterHdler.rst <= intf_clkRst.dmaRst;
ipif_dmaMasterHdler.clk <= intf_clkRst.dmaClk;
ipif_dma.ipif_mstrd_req <= ipif_dmaMasterHdler.ipif_rdReq;
ipif_dma.ipif_mstwr_req <= ipif_dmaMasterHdler.ipif_wrReq;
ipif_dma.ipif_mst_addr <= ipif_dmaMasterHdler.ipif_addr(ipif_dma.ipif_mst_addr'range);
ipif_dma.ipif_mst_length <= ipif_dmaMasterHdler.ipif_length;
ipif_dma.ipif_mst_be <= ipif_dmaMasterHdler.ipif_be;
ipif_dma.ipif_mst_type <= ipif_dmaMasterHdler.ipif_type;
ipif_dma.ipif_mst_lock <= ipif_dmaMasterHdler.ipif_lock;
ipif_dma.ipif_mst_reset <= ipif_dmaMasterHdler.ipif_reset;
ipif_dmaMasterHdler.ipif_cmdAck <= ipif_dma.ipif_mst_cmdack;
ipif_dmaMasterHdler.ipif_cmplt <= ipif_dma.ipif_mst_cmplt;
ipif_dmaMasterHdler.ipif_error <= ipif_dma.ipif_mst_error;
ipif_dmaMasterHdler.ipif_rearbitrate <= ipif_dma.ipif_mst_rearbitrate;
ipif_dmaMasterHdler.ipif_cmdTimeout <= ipif_dma.ipif_mst_cmd_timeout;
ipif_dmaMasterHdler.ipif_rdData <= ipif_dma.ipif_mstrd_d;
ipif_dmaMasterHdler.ipif_rdRem <= ipif_dma.ipif_mstrd_rem;
ipif_dmaMasterHdler.nIpif_rdSof <= ipif_dma.ipif_mstrd_sof_n;
ipif_dmaMasterHdler.nIpif_rdEof <= ipif_dma.ipif_mstrd_eof_n;
ipif_dmaMasterHdler.nIpif_rdSrcRdy <= ipif_dma.ipif_mstrd_src_rdy_n;
ipif_dmaMasterHdler.nIpif_rdSrcDsc <= ipif_dma.ipif_mstrd_src_dsc_n;
ipif_dma.ipif_mstrd_dst_rdy_n <= ipif_dmaMasterHdler.nIpif_rdDstRdy;
ipif_dma.ipif_mstrd_dst_dsc_n <= ipif_dmaMasterHdler.nIpif_rdDstDsc;
ipif_dma.ipif_mstwr_d <= ipif_dmaMasterHdler.ipif_wrData;
ipif_dma.ipif_mstwr_rem <= ipif_dmaMasterHdler.ipif_wrRem;
ipif_dma.ipif_mstwr_sof_n <= ipif_dmaMasterHdler.nIpif_wrSof;
ipif_dma.ipif_mstwr_eof_n <= ipif_dmaMasterHdler.nIpif_wrEof;
ipif_dma.ipif_mstwr_src_rdy_n <= ipif_dmaMasterHdler.nIpif_wrSrcRdy;
ipif_dma.ipif_mstwr_src_dsc_n <= ipif_dmaMasterHdler.nIpif_wrSrcDsc;
ipif_dmaMasterHdler.nIpif_wrDstRdy <= ipif_dma.ipif_mstwr_dst_rdy_n;
ipif_dmaMasterHdler.nIpif_wrDstDsc <= ipif_dma.ipif_mstwr_dst_dsc_n;
-- ipif_dmaMasterHdler --> intf_dma
ipif_dmaMasterHdler.masterRead <= intf_dma.read;
ipif_dmaMasterHdler.masterWrite <= intf_dma.write;
ipif_dmaMasterHdler.masterAddress <= intf_dma.address;
ipif_dmaMasterHdler.masterWritedata <= intf_dma.writedata;
ipif_dmaMasterHdler.masterBurstcount <= intf_dma.burstcount;
ipif_dmaMasterHdler.masterBurstcounter <= intf_dma.burstcounter;
intf_dma.readdata <= ipif_dmaMasterHdler.masterReaddata;
intf_dma.waitrequest <= ipif_dmaMasterHdler.masterWaitrequest;
intf_dma.readdatavalid <= ipif_dmaMasterHdler.masterReaddatavalid;
---------------------------------------------------------------------------
-- Instantiations
---------------------------------------------------------------------------
--! This is the openMAC toplevel instantiation.
THEOPENMACTOP : entity work.openmacTop
generic map (
gPhyPortCount => gPhyPortCount,
gPhyPortType => gPhyPortType,
gSmiPortCount => gSmiPortCount,
gEndianness => gEndianness,
gEnableActivity => gEnableActivity,
gEnableDmaObserver => gEnableDmaObserver,
gDmaAddrWidth => gDmaAddrWidth,
gDmaDataWidth => gDmaDataWidth,
gDmaBurstCountWidth => gDmaBurstCountWidth,
gDmaWriteBurstLength => gDmaWriteBurstLength,
gDmaReadBurstLength => gDmaReadBurstLength,
gDmaWriteFifoLength => gDmaWriteFifoLength,
gDmaReadFifoLength => gDmaReadFifoLength,
gPacketBufferLocTx => gPacketBufferLocTx,
gPacketBufferLocRx => gPacketBufferLocRx,
gPacketBufferLog2Size => gPacketBufferLog2Size,
gTimerCount => gTimerCount,
gTimerEnablePulseWidth => gTimerEnablePulseWidth,
gTimerPulseRegWidth => gTimerPulseRegWidth
)
port map (
iClk => intf_clkRst.clk,
iRst => intf_clkRst.rst,
iDmaClk => intf_clkRst.dmaClk,
iDmaRst => intf_clkRst.dmaRst,
iPktBufClk => intf_clkRst.pktClk,
iPktBufRst => intf_clkRst.pktRst,
iClk2x => intf_clkRst.clk2x,
iMacReg_chipselect => intf_macReg.chipselect,
iMacReg_write => intf_macReg.write,
iMacReg_read => intf_macReg.read,
oMacReg_waitrequest => intf_macReg.waitrequest,
iMacReg_byteenable => intf_macReg.byteenable,
iMacReg_address => intf_macReg.address,
iMacReg_writedata => intf_macReg.writedata,
oMacReg_readdata => intf_macReg.readdata,
iMacTimer_chipselect => intf_macTimer.chipselect,
iMacTimer_write => intf_macTimer.write,
iMacTimer_read => intf_macTimer.read,
oMacTimer_waitrequest => intf_macTimer.waitrequest,
iMacTimer_address => intf_macTimer.address,
iMacTimer_writedata => intf_macTimer.writedata,
oMacTimer_readdata => intf_macTimer.readdata,
iPktBuf_chipselect => intf_pktBuf.chipselect,
iPktBuf_write => intf_pktBuf.write,
iPktBuf_read => intf_pktBuf.read,
oPktBuf_waitrequest => intf_pktBuf.waitrequest,
iPktBuf_byteenable => intf_pktBuf.byteenable,
iPktBuf_address => intf_pktBuf.address,
iPktBuf_writedata => intf_pktBuf.writedata,
oPktBuf_readdata => intf_pktBuf.readdata,
oDma_write => intf_dma.write,
oDma_read => intf_dma.read,
iDma_waitrequest => intf_dma.waitrequest,
iDma_readdatavalid => intf_dma.readdatavalid,
oDma_byteenable => intf_dma.byteenable,
oDma_address => intf_dma.address,
oDma_burstcount => intf_dma.burstcount,
oDma_burstcounter => intf_dma.burstcounter,
oDma_writedata => intf_dma.writedata,
iDma_readdata => intf_dma.readdata,
oMacTimer_interrupt => TIMER_IRQ,
oMacTx_interrupt => macTx_interrupt,
oMacRx_interrupt => macRx_interrupt,
iRmii_Rx => rmiiRx,
iRmii_RxError => iRmii_rxError,
oRmii_Tx => rmiiTx,
iMii_Rx => miiRx,
iMii_RxError => iMii_rxError,
iMii_RxClk => iMii_rxClk,
oMii_Tx => miiTx,
iMii_TxClk => iMii_txClk,
onPhy_reset => oSmi_nPhyRst,
oSmi_clk => oSmi_clk,
oSmi_data_outEnable => smi_data_outEnable,
oSmi_data_out => smi_data_out,
iSmi_data_in => smi_data_in,
oActivity => oPktActivity,
oMacTimer => oMacTimerOut
);
--! The MAC REG AXI lite IPIF converts the AXI interface to IPIF.
THEMACREG_AXILITE : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map (
C_S_AXI_DATA_WIDTH => C_S_AXI_MAC_REG_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_MAC_REG_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MAC_REG_MIN_SIZE,
C_USE_WSTRB => C_S_AXI_MAC_REG_USE_WSTRB,
C_DPHASE_TIMEOUT => C_S_AXI_MAC_REG_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => cMacReg_addressArray,
C_ARD_NUM_CE_ARRAY => (1, 1),
C_FAMILY => C_FAMILY
)
port map (
S_AXI_ACLK => ipif_macReg.axi_aclk,
S_AXI_ARESETN => ipif_macReg.axi_aresetn,
S_AXI_AWADDR => ipif_macReg.axi_awaddr,
S_AXI_AWVALID => ipif_macReg.axi_awvalid,
S_AXI_AWREADY => ipif_macReg.axi_awready,
S_AXI_WDATA => ipif_macReg.axi_wdata,
S_AXI_WSTRB => ipif_macReg.axi_wstrb,
S_AXI_WVALID => ipif_macReg.axi_wvalid,
S_AXI_WREADY => ipif_macReg.axi_wready,
S_AXI_BRESP => ipif_macReg.axi_bresp,
S_AXI_BVALID => ipif_macReg.axi_bvalid,
S_AXI_BREADY => ipif_macReg.axi_bready,
S_AXI_ARADDR => ipif_macReg.axi_araddr,
S_AXI_ARVALID => ipif_macReg.axi_arvalid,
S_AXI_ARREADY => ipif_macReg.axi_arready,
S_AXI_RDATA => ipif_macReg.axi_rdata,
S_AXI_RRESP => ipif_macReg.axi_rresp,
S_AXI_RVALID => ipif_macReg.axi_rvalid,
S_AXI_RREADY => ipif_macReg.axi_rready,
Bus2IP_Clk => ipif_macReg.ipif_clk,
Bus2IP_Resetn => ipif_macReg.ipif_resetn,
Bus2IP_Addr => ipif_macReg.ipif_addr,
Bus2IP_RNW => ipif_macReg.ipif_rnw,
Bus2IP_BE => ipif_macReg.ipif_be,
Bus2IP_CS => ipif_macReg.ipif_cs,
Bus2IP_RdCE => open, --don't need that feature
Bus2IP_WrCE => open, --don't need that feature
Bus2IP_Data => ipif_macReg.ipif_wrdata,
IP2Bus_Data => ipif_macReg.ipif_rddata,
IP2Bus_WrAck => ipif_macReg.ipif_wrack,
IP2Bus_RdAck => ipif_macReg.ipif_rdack,
IP2Bus_Error => ipif_macReg.ipif_error
);
--! The clock Xing ipcore transfers the signals in the AXI clock domain to
--! the iClk50 domain.
THEMACREG_CLKXING : entity libcommon.clkXing
generic map (
gCsNum => xing_macReg.fast.cs'length,
gDataWidth => xing_macReg.fast.readdata'length
)
port map (
iArst => xing_macReg.rst,
iFastClk => xing_macReg.fast.clk,
iFastCs => xing_macReg.fast.cs,
iFastRNW => xing_macReg.fast.rnw,
oFastReaddata => xing_macReg.fast.readdata,
oFastWrAck => xing_macReg.fast.wrAck,
oFastRdAck => xing_macReg.fast.rdAck,
iSlowClk => xing_macReg.slow.clk,
oSlowCs => xing_macReg.slow.cs,
oSlowRNW => xing_macReg.slow.rnw,
iSlowReaddata => xing_macReg.slow.readdata,
iSlowWrAck => xing_macReg.slow.wrAck,
iSlowRdAck => xing_macReg.slow.rdAck
);
--! The memory mapped slave converter changes from AXI's data width to 16 bit.
THEMACREG_MMCONV : entity work.mmSlaveConv
generic map (
gEndian => gEndianness,
gMasterAddrWidth => conv_macReg.master_address'length
)
port map (
iRst => conv_macReg.rst,
iClk => conv_macReg.clk,
iMaster_select => conv_macReg.master_select,
iMaster_write => conv_macReg.master_write,
iMaster_read => conv_macReg.master_read,
iMaster_byteenable => conv_macReg.master_byteenable,
iMaster_writedata => conv_macReg.master_writedata,
oMaster_readdata => conv_macReg.master_readdata,
iMaster_address => conv_macReg.master_address,
oMaster_WriteAck => conv_macReg.master_WriteAck,
oMaster_ReadAck => conv_macReg.master_ReadAck,
oSlave_select => conv_macReg.slave_select,
oSlave_write => conv_macReg.slave_write,
oSlave_read => conv_macReg.slave_read,
oSlave_address => conv_macReg.slave_address,
oSlave_byteenable => conv_macReg.slave_byteenable,
iSlave_readdata => conv_macReg.slave_readdata,
oSlave_writedata => conv_macReg.slave_writedata,
iSlave_ack => conv_macReg.slave_ack
);
--! Generate the packet buffer IPIF if any location is set to local.
GEN_THEMACPKT : if gPacketBufferLocRx = cPktBufLocal or gPacketBufferLocTx = cPktBufLocal generate
--! The MAC PKT BUF AXI lite IPIF converts the AXI interface to IPIF.
THEMACREG_AXILITE : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map (
C_S_AXI_DATA_WIDTH => C_S_AXI_MAC_PKT_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_MAC_PKT_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MAC_PKT_MIN_SIZE,
C_USE_WSTRB => C_S_AXI_MAC_PKT_USE_WSTRB,
C_DPHASE_TIMEOUT => C_S_AXI_MAC_PKT_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => cPktBuf_addressArray,
C_ARD_NUM_CE_ARRAY => (0 => 1),
C_FAMILY => C_FAMILY
)
port map (
S_AXI_ACLK => ipif_pktBuf.axi_aclk,
S_AXI_ARESETN => ipif_pktBuf.axi_aresetn,
S_AXI_AWADDR => ipif_pktBuf.axi_awaddr,
S_AXI_AWVALID => ipif_pktBuf.axi_awvalid,
S_AXI_AWREADY => ipif_pktBuf.axi_awready,
S_AXI_WDATA => ipif_pktBuf.axi_wdata,
S_AXI_WSTRB => ipif_pktBuf.axi_wstrb,
S_AXI_WVALID => ipif_pktBuf.axi_wvalid,
S_AXI_WREADY => ipif_pktBuf.axi_wready,
S_AXI_BRESP => ipif_pktBuf.axi_bresp,
S_AXI_BVALID => ipif_pktBuf.axi_bvalid,
S_AXI_BREADY => ipif_pktBuf.axi_bready,
S_AXI_ARADDR => ipif_pktBuf.axi_araddr,
S_AXI_ARVALID => ipif_pktBuf.axi_arvalid,
S_AXI_ARREADY => ipif_pktBuf.axi_arready,
S_AXI_RDATA => ipif_pktBuf.axi_rdata,
S_AXI_RRESP => ipif_pktBuf.axi_rresp,
S_AXI_RVALID => ipif_pktBuf.axi_rvalid,
S_AXI_RREADY => ipif_pktBuf.axi_rready,
Bus2IP_Clk => ipif_pktBuf.ipif_clk,
Bus2IP_Resetn => ipif_pktBuf.ipif_resetn,
Bus2IP_Addr => ipif_pktBuf.ipif_addr,
Bus2IP_RNW => ipif_pktBuf.ipif_rnw,
Bus2IP_BE => ipif_pktBuf.ipif_be,
Bus2IP_CS => ipif_pktBuf.ipif_cs,
Bus2IP_RdCE => open, --don't need that feature
Bus2IP_WrCE => open, --don't need that feature
Bus2IP_Data => ipif_pktBuf.ipif_wrdata,
IP2Bus_Data => ipif_pktBuf.ipif_rddata,
IP2Bus_WrAck => ipif_pktBuf.ipif_wrack,
IP2Bus_RdAck => ipif_pktBuf.ipif_rdack,
IP2Bus_Error => ipif_pktBuf.ipif_error
);
end generate GEN_THEMACPKT;
GEN_THEMACDMA : if gPacketBufferLocRx = cPktBufExtern or gPacketBufferLocTx = cPktBufExtern generate
--! The MAC DMA AXI master IPIF converts the AXI interface to IPIF.
THEMACDMA_AXI : entity axi_master_burst_v1_00_a.axi_master_burst
generic map (
C_M_AXI_ADDR_WIDTH => C_M_AXI_MAC_DMA_ADDR_WIDTH,
C_M_AXI_DATA_WIDTH => C_M_AXI_MAC_DMA_DATA_WIDTH,
C_MAX_BURST_LEN => C_M_AXI_MAC_DMA_MAX_BURST_LEN,
C_ADDR_PIPE_DEPTH => 1,
C_NATIVE_DATA_WIDTH => C_M_AXI_MAC_DMA_NATIVE_DWIDTH,
C_LENGTH_WIDTH => C_M_AXI_MAC_DMA_LENGTH_WIDTH,
C_FAMILY => C_FAMILY
)
port map (
m_axi_aclk => ipif_dma.axi_aclk,
m_axi_aresetn => ipif_dma.axi_aresetn,
md_error => ipif_dma.md_error,
m_axi_arready => ipif_dma.axi_arready,
m_axi_arvalid => ipif_dma.axi_arvalid,
m_axi_araddr => ipif_dma.axi_araddr,
m_axi_arlen => ipif_dma.axi_arlen,
m_axi_arsize => ipif_dma.axi_arsize,
m_axi_arburst => ipif_dma.axi_arburst,
m_axi_arprot => ipif_dma.axi_arprot,
m_axi_arcache => ipif_dma.axi_arcache,
m_axi_rready => ipif_dma.axi_rready,
m_axi_rvalid => ipif_dma.axi_rvalid,
m_axi_rdata => ipif_dma.axi_rdata,
m_axi_rresp => ipif_dma.axi_rresp,
m_axi_rlast => ipif_dma.axi_rlast,
m_axi_awready => ipif_dma.axi_awready,
m_axi_awvalid => ipif_dma.axi_awvalid,
m_axi_awaddr => ipif_dma.axi_awaddr,
m_axi_awlen => ipif_dma.axi_awlen,
m_axi_awsize => ipif_dma.axi_awsize,
m_axi_awburst => ipif_dma.axi_awburst,
m_axi_awprot => ipif_dma.axi_awprot,
m_axi_awcache => ipif_dma.axi_awcache,
m_axi_wready => ipif_dma.axi_wready,
m_axi_wvalid => ipif_dma.axi_wvalid,
m_axi_wdata => ipif_dma.axi_wdata,
m_axi_wstrb => ipif_dma.axi_wstrb,
m_axi_wlast => ipif_dma.axi_wlast,
m_axi_bready => ipif_dma.axi_bready,
m_axi_bvalid => ipif_dma.axi_bvalid,
m_axi_bresp => ipif_dma.axi_bresp,
ip2bus_mstrd_req => ipif_dma.ipif_mstrd_req,
ip2bus_mstwr_req => ipif_dma.ipif_mstwr_req,
ip2bus_mst_addr => ipif_dma.ipif_mst_addr,
ip2bus_mst_length => ipif_dma.ipif_mst_length,
ip2bus_mst_be => ipif_dma.ipif_mst_be,
ip2bus_mst_type => ipif_dma.ipif_mst_type,
ip2bus_mst_lock => ipif_dma.ipif_mst_lock,
ip2bus_mst_reset => ipif_dma.ipif_mst_reset,
bus2ip_mst_cmdack => ipif_dma.ipif_mst_cmdack,
bus2ip_mst_cmplt => ipif_dma.ipif_mst_cmplt,
bus2ip_mst_error => ipif_dma.ipif_mst_error,
bus2ip_mst_rearbitrate => ipif_dma.ipif_mst_rearbitrate,
bus2ip_mst_cmd_timeout => ipif_dma.ipif_mst_cmd_timeout,
bus2ip_mstrd_d => ipif_dma.ipif_mstrd_d,
bus2ip_mstrd_rem => ipif_dma.ipif_mstrd_rem,
bus2ip_mstrd_sof_n => ipif_dma.ipif_mstrd_sof_n,
bus2ip_mstrd_eof_n => ipif_dma.ipif_mstrd_eof_n,
bus2ip_mstrd_src_rdy_n => ipif_dma.ipif_mstrd_src_rdy_n,
bus2ip_mstrd_src_dsc_n => ipif_dma.ipif_mstrd_src_dsc_n,
ip2bus_mstrd_dst_rdy_n => ipif_dma.ipif_mstrd_dst_rdy_n,
ip2bus_mstrd_dst_dsc_n => ipif_dma.ipif_mstrd_dst_dsc_n,
ip2bus_mstwr_d => ipif_dma.ipif_mstwr_d,
ip2bus_mstwr_rem => ipif_dma.ipif_mstwr_rem,
ip2bus_mstwr_sof_n => ipif_dma.ipif_mstwr_sof_n,
ip2bus_mstwr_eof_n => ipif_dma.ipif_mstwr_eof_n,
ip2bus_mstwr_src_rdy_n => ipif_dma.ipif_mstwr_src_rdy_n,
ip2bus_mstwr_src_dsc_n => ipif_dma.ipif_mstwr_src_dsc_n,
bus2ip_mstwr_dst_rdy_n => ipif_dma.ipif_mstwr_dst_rdy_n,
bus2ip_mstwr_dst_dsc_n => ipif_dma.ipif_mstwr_dst_dsc_n
);
--! The IPIF master handler converts the IPIF master signals to the
--! openMAC's DMA interface.
THEMACDMA_IPIF_HANDLER : entity work.ipifMasterHandler
generic map (
gMasterAddrWidth => ipif_dmaMasterHdler.masterAddress'length,
gMasterBurstCountWidth => ipif_dmaMasterHdler.masterBurstcount'length,
gIpifAddrWidth => ipif_dmaMasterHdler.ipif_addr'length,
gIpifLength => ipif_dmaMasterHdler.ipif_length'length
)
port map (
iRst => ipif_dmaMasterHdler.rst,
iClk => ipif_dmaMasterHdler.clk,
iIpif_cmdAck => ipif_dmaMasterHdler.ipif_cmdAck,
iIpif_cmplt => ipif_dmaMasterHdler.ipif_cmplt,
iIpif_error => ipif_dmaMasterHdler.ipif_error,
iIpif_rearbitrate => ipif_dmaMasterHdler.ipif_rearbitrate,
iIpif_cmdTimeout => ipif_dmaMasterHdler.ipif_cmdTimeout,
oIpif_type => ipif_dmaMasterHdler.ipif_type,
oIpif_addr => ipif_dmaMasterHdler.ipif_addr,
oIpif_length => ipif_dmaMasterHdler.ipif_length,
oIpif_be => ipif_dmaMasterHdler.ipif_be,
oIpif_lock => ipif_dmaMasterHdler.ipif_lock,
oIpif_reset => ipif_dmaMasterHdler.ipif_reset,
iIpif_rdData => ipif_dmaMasterHdler.ipif_rdData,
iIpif_rdRem => ipif_dmaMasterHdler.ipif_rdRem,
oIpif_rdReq => ipif_dmaMasterHdler.ipif_rdReq,
inIpif_rdSof => ipif_dmaMasterHdler.nIpif_rdSof,
inIpif_rdEof => ipif_dmaMasterHdler.nIpif_rdEof,
inIpif_rdSrcRdy => ipif_dmaMasterHdler.nIpif_rdSrcRdy,
inIpif_rdSrcDsc => ipif_dmaMasterHdler.nIpif_rdSrcDsc,
onIpif_rdDstRdy => ipif_dmaMasterHdler.nIpif_rdDstRdy,
onIpif_rdDstDsc => ipif_dmaMasterHdler.nIpif_rdDstDsc,
oIpif_wrData => ipif_dmaMasterHdler.ipif_wrData,
oIpif_wrRem => ipif_dmaMasterHdler.ipif_wrRem,
oIpif_wrReq => ipif_dmaMasterHdler.ipif_wrReq,
onIpif_wrSof => ipif_dmaMasterHdler.nIpif_wrSof,
onIpif_wrEof => ipif_dmaMasterHdler.nIpif_wrEof,
onIpif_wrSrcRdy => ipif_dmaMasterHdler.nIpif_wrSrcRdy,
onIpif_wrSrcDsc => ipif_dmaMasterHdler.nIpif_wrSrcDsc,
inIpif_wrDstRdy => ipif_dmaMasterHdler.nIpif_wrDstRdy,
inIpif_wrDstDsc => ipif_dmaMasterHdler.nIpif_wrDstDsc,
iMasterRead => ipif_dmaMasterHdler.masterRead,
iMasterWrite => ipif_dmaMasterHdler.masterWrite,
iMasterAddress => ipif_dmaMasterHdler.masterAddress,
iMasterWritedata => ipif_dmaMasterHdler.masterWritedata,
iMasterBurstcount => ipif_dmaMasterHdler.masterBurstcount,
iMasterBurstcounter => ipif_dmaMasterHdler.masterBurstcounter,
oMasterReaddata => ipif_dmaMasterHdler.masterReaddata,
oMasterWaitrequest => ipif_dmaMasterHdler.masterWaitrequest,
oMasterReaddatavalid => ipif_dmaMasterHdler.masterReaddatavalid
);
end generate GEN_THEMACDMA;
GEN_RMII_CLK : if gPhyPortType = cPhyPortRmii generate
GEN_ODDR2 : for i in oRmii_clk'range generate
signal rmiiClk : std_logic;
signal nRmiiClk : std_logic;
begin
-- Assign rmii clock (used by openMAC) and the inverted to ODDR2.
rmiiClk <= intf_clkRst.clk;
nRmiiClk <= not rmiiClk;
--! This is a dual data rate output FF used to output the internal
--! RMII clock.
THEODDR2 : oddr2
generic map (
DDR_ALIGNMENT => "NONE", -- align D0 with C0 and D1 with C1 edge
INIT => '0', -- initialize Q with '0'
SRTYPE => "SYNC" -- take default, since RS are unused
)
port map (
D0 => cActivated,
D1 => cInactivated,
C0 => rmiiClk,
C1 => nRmiiClk,
CE => cActivated,
R => cInactivated, --unused
S => cInactivated, --unused
Q => oRmii_clk(i)
);
end generate GEN_ODDR2;
end generate GEN_RMII_CLK;
end rtl;
| gpl-2.0 | 490e0028eb4cfc7bd271bc13b00aff6c | 0.524106 | 4.046633 | false | false | false | false |
shibumi/University | VHDL/Aufgabe4.3.vhdl | 2 | 740 | --Aufgabe 4.3
library ieee;
use ieee.std_logic_1164.all;
use ieee.Numeric_STD.all;
entity Aufgabe4_3 is
port(a: in UNSIGNED(3 downto 0);
b: in UNSIGNED(3 downto 0);
s: in STD_LOGIC_VECTOR(1 DOWNTO 0);
y: out UNSIGNED(3 downto 0));
end entity;
architecture test of Aufgabe4_3 is
begin
process(a,b,s)
variable v0,v1,v2,v3,v4: UNSIGNED(3 downto 0);
begin
--Linker Bereich + Oben Rechts
v0 := a and b;
v1 := a or b;
if s(0) = '0' then
v2 := v0;
v3 := a;
else
v2 := v1;
v3 := not(a);
end if;
--Addierer / Links Unten
v4 := v3 + b;
if s(1) = '0' then
y <= v2;
else
y <= v4;
end if;
end process;
end architecture;
| gpl-3.0 | 37fb70207fdbf86745f31e5b8bbdc4dc | 0.541892 | 2.70073 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/xilinx/memory/src/dpRam-rtl-a.vhd | 1 | 5,491 | --! @file dpRam-bhv-a.vhd
--
--! @brief Dual Port Ram Register Transfer Level Architecture
--
--! @details This is the DPRAM intended for synthesis on Xilinx Spartan 6 only.
--! Timing as follows [clk-cycles]: write=0 / read=1
--
-------------------------------------------------------------------------------
-- Architecture : rtl
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
architecture rtl of dpRam is
--! Width of a byte
constant cByte : natural := 8;
--! Address width (used to generate size depending on address width)
constant cAddrWidth : natural := iAddress_A'length;
--! RAM size
constant cRamSize : natural := 2**cAddrWidth;
--! Type for data port
subtype tDataPort is std_logic_vector(gWordWidth-1 downto 0);
--! RAM type with given size
type tRam is array (cRamSize-1 downto 0) of tDataPort;
--! Shared variable to model and synthesize a DPR
shared variable vDpram : tRam := (others => (others => cInactivated));
--! Port A readport
signal readdataA : tDataPort;
--! Port B readport
signal readdataB : tDataPort;
begin
assert (gInitFile = "UNUSED")
report "Memory initialization is not supported in this architecture!"
severity warning;
-- assign readdata to ports
oReaddata_A <= readdataA;
oReaddata_B <= readdataB;
--! This process describes port A of the DPRAM. The write process considers
--! iWriteEnable_A and iByteenable_A. The read process is done with every
--! rising iClk_A edge.
PORTA : process(iClk_A)
begin
if rising_edge(iClk_A) then
if iEnable_A = cActivated then
if iWriteEnable_A = cActivated then
for i in iByteenable_A'range loop
if iByteenable_A(i) = cActivated then
-- write byte to DPRAM
vDpram(to_integer(unsigned(iAddress_A)))(
(i+1)*cByte-1 downto i*cByte
) := iWritedata_A(
(i+1)*cByte-1 downto i*cByte
);
end if; --byteenable
end loop;
end if; --writeenable
-- read word from DPRAM
readdataA <= vDpram(to_integer(unsigned(iAddress_A)));
end if; --enable
end if;
end process PORTA;
--! This process describes port B of the DPRAM. The write process considers
--! iWriteEnable_B and iByteenable_B. The read process is done with every
--! rising iClk_B edge.
PORTB : process(iClk_B)
begin
if rising_edge(iClk_B) then
if iEnable_B = cActivated then
if iWriteEnable_B = cActivated then
for i in iByteenable_B'range loop
if iByteenable_B(i) = cActivated then
-- write byte to DPRAM
vDpram(to_integer(unsigned(iAddress_B)))(
(i+1)*cByte-1 downto i*cByte
) := iWritedata_B(
(i+1)*cByte-1 downto i*cByte
);
end if; --byteenable
end loop;
end if; --writeenable
-- read word from DPRAM
readdataB <= vDpram(to_integer(unsigned(iAddress_B)));
end if; --enable
end if;
end process PORTB;
end architecture rtl;
| gpl-2.0 | 10015feb5a24086b290fb397f61399c9 | 0.580586 | 4.920251 | false | false | false | false |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/openmac/src/openhub-rtl-ea.vhd | 3 | 7,507 | -------------------------------------------------------------------------------
--! @file openhub-rtl-ea.vhd
--
--! @brief OpenHUB
--
--! @details This is the openHUB using RMII Rx and Tx lines.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
--! Work library
library work;
--! use openmac package
use work.openmacPkg.all;
entity openhub is
generic (
--! Number of ports
gPortCount : integer := 3
);
port (
--! Reset
iRst : in std_logic;
--! RMII Clock
iClk : in std_logic;
--! RMII receive paths
iRx : in tRmiiPathArray(gPortCount downto 1);
--! RMII transmit paths
oTx : out tRmiiPathArray(gPortCount downto 1);
--! Determine number of internal port (to MAC)
iIntPort : in integer range 1 to gPortCount := 1;
--! Transmit mask to enable ports
iTxMask : in std_logic_vector(gPortCount downto 1) := (others => cActivated);
--! Gives the number of the currectly receiving port
oRxPort : out integer range 0 to gPortCount
);
end entity openhub;
architecture rtl of openhub is
--! All ports inactive constant
constant cPortsAreInactive : std_logic_vector(gPortCount downto 0) := (others => cInactivated);
--! Receive path array
signal rxPath : tRmiiPathArray(gPortCount downto 0);
--! Receive path array delayed by one cycle
signal rxPath_l : tRmiiPathArray(gPortCount downto 0);
--! Transmit path array
signal txPath : tRmiiPathArray(gPortCount downto 0);
--! Stored transmit mask (is taken from iTxMask when to packet transfer is in progress)
signal txMask_reg : std_logic_vector(gPortCount downto 1);
begin
rxPath <= iRx & cRmiiPathInit;
oTx <= txPath(oTx'range);
do: process (iRst, iClk)
variable vActive : boolean;
variable vMaster : integer range 0 to gPortCount;
variable vMasterAtCollision : integer range 0 to gPortCount;
variable vCollision : boolean;
variable vRxDvm : std_logic_vector(gPortCount downto 0);
begin
if iRst = cActivated then
rxPath_l <= (others => cRmiiPathInit);
txPath <= (others => cRmiiPathInit);
vActive := false;
vMaster := 0;
vMasterAtCollision := 0;
vCollision := false;
txMask_reg <= (others => cInactivated);
elsif rising_edge(iClk) then
rxPath_l <= rxPath;
if vActive = false then
if rmiiGetEnable(rxPath_l) /= cPortsAreInactive then
for i in 1 to gPortCount loop
if (rxPath_l(i).enable = cActivated and
(rxPath_l(i).data(0) = cActivated or rxPath_l(i).data(1) = cActivated)) then
vMaster := i;
vActive := true;
exit;
end if;
end loop;
end if;
else
if rxPath_l(vMaster).enable = cInactivated and rxPath(vMaster).enable = cInactivated then
vMaster := 0;
end if;
if rmiiGetEnable(rxPath_l) = cPortsAreInactive and rmiiGetEnable(rxPath) = cPortsAreInactive then
vActive := false;
end if;
end if;
if vMaster = 0 then
txPath <= (others => cRmiiPathInit);
-- overtake new iTxMask only, when there is no active frame.
txMask_reg <= iTxMask;
else
for i in 1 to gPortCount loop -- output received frame to every port
if i /= vMaster then -- but not to the port where it is coming from - "eh kloar!"
-- only send data to active ports (=> iTxMask is set to cActivated) or the internal port (mac)
if txMask_reg(i) = cActivated or vMaster = iIntPort then
txPath(i).enable <= cActivated;
txPath(i).data <= rxPath_l(vMaster).data;
end if;
-- if there is a frame received and another is sent => collision!
if rxPath_l(i).enable = cActivated then
vCollision := true;
vMasterAtCollision := vMaster;
end if;
end if;
end loop;
end if;
if vCollision = true then
txPath(vMasterAtCollision).enable <= cActivated;
txPath(vMasterAtCollision).data <= "01";
vRxDvm := rmiiGetEnable(rxPath_l);
vRxDvm(vMasterAtCollision) := cInactivated;
if vRxDvm = cPortsAreInactive then
txPath(vMasterAtCollision) <= cRmiiPathInit;
vCollision := false;
vMasterAtCollision := 0;
end if;
end if;
-- output the master port - identifies the port (1...n) which has received the packet.
-- if master is 0, the hub is inactive.
oRxPort <= vMaster;
end if;
end process do;
end rtl;
| gpl-2.0 | fcb6bb4d3608c46c6a97d31465b86013 | 0.54629 | 4.984728 | false | false | false | false |
Subsets and Splits